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authorJoonyoung Shim <jy0922.shim@samsung.com>2014-11-06 04:29:27 (GMT)
committerChanho Park <chanho61.park@samsung.com>2014-11-18 03:01:18 (GMT)
commitb6f2238c5fe08527d524498ac6ee519f019b8bf5 (patch)
tree5dca3eded2a12c402381e5a4a4d44f1850556780
parentaa733941c8da7d8ae9d2d1cf8b7ca1cf30e2b80d (diff)
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gpu: arm: mali400: modify DVFS tables and setting
This comes from commit ("local/ARM/MALI400: R4P0_REL0: Clean up codes") of in-house kernel. Change-Id: Id835808d157438527d32b3f3cf46108ab8d45fb6 Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
-rw-r--r--drivers/gpu/arm/mali400/mali/platform/exynos4/exynos4.c39
-rw-r--r--drivers/gpu/arm/mali400/r4p0_rel0/platform/exynos/exynos.c37
2 files changed, 37 insertions, 39 deletions
diff --git a/drivers/gpu/arm/mali400/mali/platform/exynos4/exynos4.c b/drivers/gpu/arm/mali400/mali/platform/exynos4/exynos4.c
index b316d4c..f13116b 100644
--- a/drivers/gpu/arm/mali400/mali/platform/exynos4/exynos4.c
+++ b/drivers/gpu/arm/mali400/mali/platform/exynos4/exynos4.c
@@ -36,8 +36,7 @@ struct mali_exynos_variant {
struct mali_exynos_dvfs_step {
unsigned int rate;
- unsigned int min_uv;
- unsigned int max_uv;
+ unsigned int voltage;
unsigned int downthreshold;
unsigned int upthreshold;
};
@@ -74,31 +73,31 @@ static struct mali_exynos_drvdata *mali;
* DVFS tables
*/
-#define MALI_DVFS_STEP(freq, min_uv, max_uv, down, up) \
- {freq * 1000000, min_uv, max_uv, (255 * down) / 100, (255 * up) / 100}
+#define MALI_DVFS_STEP(freq, voltage, down, up) \
+ {freq, voltage, (256 * down) / 100, (256 * up) / 100}
static const struct mali_exynos_dvfs_step mali_exynos_dvfs_step_3250[] = {
- MALI_DVFS_STEP(134, 0, 0, 0, 100),
+ MALI_DVFS_STEP(134, 0, 0, 100)
};
static const struct mali_exynos_dvfs_step mali_exynos_dvfs_step_4210[] = {
- MALI_DVFS_STEP(160, 950000, 975000, 0, 85),
- MALI_DVFS_STEP(266, 1000000, 1025000, 75, 100),
+ MALI_DVFS_STEP(160, 950000, 0, 90),
+ MALI_DVFS_STEP(266, 1050000, 85, 100)
};
static const struct mali_exynos_dvfs_step mali_exynos_dvfs_step_4x12[] = {
- MALI_DVFS_STEP(160, 875000, 900000, 0, 70),
- MALI_DVFS_STEP(266, 900000, 925000, 62, 90),
- MALI_DVFS_STEP(350, 950000, 975000, 85, 90),
- MALI_DVFS_STEP(440, 1025000, 1050000, 85, 100),
+ MALI_DVFS_STEP(160, 875000, 0, 70),
+ MALI_DVFS_STEP(266, 900000, 62, 90),
+ MALI_DVFS_STEP(350, 950000, 85, 90),
+ MALI_DVFS_STEP(440, 1025000, 85, 100)
};
static const struct mali_exynos_dvfs_step mali_exynos_dvfs_step_4x12_prime[] = {
- MALI_DVFS_STEP(160, 875000, 900000, 0, 70),
- MALI_DVFS_STEP(266, 900000, 925000, 62, 90),
- MALI_DVFS_STEP(350, 950000, 975000, 85, 90),
- MALI_DVFS_STEP(440, 1025000, 1050000, 85, 90),
- MALI_DVFS_STEP(533, 1075000, 1100000, 85, 100),
+ MALI_DVFS_STEP(160, 875000, 0, 70),
+ MALI_DVFS_STEP(266, 900000, 62, 90),
+ MALI_DVFS_STEP(350, 950000, 85, 90),
+ MALI_DVFS_STEP(440, 1025000, 85, 90),
+ MALI_DVFS_STEP(533, 1075000, 95, 100)
};
/*
@@ -162,15 +161,15 @@ static void mali_exynos_set_dvfs_step(struct mali_exynos_drvdata *mali,
const struct mali_exynos_dvfs_step *next = &mali->steps[step];
if (step <= mali->dvfs_step)
- clk_set_rate(mali->sclk, next->rate);
+ clk_set_rate(mali->sclk, next->rate * 1000000);
regulator_set_voltage(mali->vdd_g3d,
- next->min_uv, next->max_uv);
+ next->voltage, next->voltage);
if (step > mali->dvfs_step)
- clk_set_rate(mali->sclk, next->rate);
+ clk_set_rate(mali->sclk, next->rate * 1000000);
- _mali_osk_profiling_add_gpufreq_event(next->rate / 1000000,
+ _mali_osk_profiling_add_gpufreq_event(next->rate * 1000000,
regulator_get_voltage(mali->vdd_g3d) / 1000);
mali->dvfs_step = step;
}
diff --git a/drivers/gpu/arm/mali400/r4p0_rel0/platform/exynos/exynos.c b/drivers/gpu/arm/mali400/r4p0_rel0/platform/exynos/exynos.c
index e8d9bf1..d2ce06e7 100644
--- a/drivers/gpu/arm/mali400/r4p0_rel0/platform/exynos/exynos.c
+++ b/drivers/gpu/arm/mali400/r4p0_rel0/platform/exynos/exynos.c
@@ -36,8 +36,7 @@ struct mali_exynos_variant {
struct mali_exynos_dvfs_step {
unsigned int rate;
- unsigned int min_uv;
- unsigned int max_uv;
+ unsigned int voltage;
unsigned int downthreshold;
unsigned int upthreshold;
};
@@ -74,27 +73,27 @@ static struct mali_exynos_drvdata *mali;
* DVFS tables
*/
-#define MALI_DVFS_STEP(freq, min_uv, max_uv, down, up) \
- {freq * 1000000, min_uv, max_uv, (255 * down) / 100, (255 * up) / 100}
+#define MALI_DVFS_STEP(freq, voltage, down, up) \
+ {freq, voltage, (256 * down) / 100, (256 * up) / 100}
static const struct mali_exynos_dvfs_step mali_exynos_dvfs_step_4210[] = {
- MALI_DVFS_STEP(160, 950000, 975000, 0, 85),
- MALI_DVFS_STEP(266, 1000000, 1025000, 75, 100),
+ MALI_DVFS_STEP(160, 950000, 0, 90),
+ MALI_DVFS_STEP(266, 1050000, 85, 100)
};
static const struct mali_exynos_dvfs_step mali_exynos_dvfs_step_4x12[] = {
- MALI_DVFS_STEP(160, 875000, 900000, 0, 70),
- MALI_DVFS_STEP(266, 900000, 925000, 62, 90),
- MALI_DVFS_STEP(350, 950000, 975000, 85, 90),
- MALI_DVFS_STEP(440, 1025000, 1050000, 85, 100),
+ MALI_DVFS_STEP(160, 875000, 0, 70),
+ MALI_DVFS_STEP(266, 900000, 62, 90),
+ MALI_DVFS_STEP(350, 950000, 85, 90),
+ MALI_DVFS_STEP(440, 1025000, 85, 100)
};
static const struct mali_exynos_dvfs_step mali_exynos_dvfs_step_4x12_prime[] = {
- MALI_DVFS_STEP(160, 875000, 900000, 0, 70),
- MALI_DVFS_STEP(266, 900000, 925000, 62, 90),
- MALI_DVFS_STEP(350, 950000, 975000, 85, 90),
- MALI_DVFS_STEP(440, 1025000, 1050000, 85, 90),
- MALI_DVFS_STEP(533, 1075000, 1100000, 85, 100),
+ MALI_DVFS_STEP(160, 875000, 0, 70),
+ MALI_DVFS_STEP(266, 900000, 62, 90),
+ MALI_DVFS_STEP(350, 950000, 85, 90),
+ MALI_DVFS_STEP(440, 1025000, 85, 90),
+ MALI_DVFS_STEP(533, 1075000, 95, 100)
};
/*
@@ -150,15 +149,15 @@ static void mali_exynos_set_dvfs_step(struct mali_exynos_drvdata *mali,
const struct mali_exynos_dvfs_step *next = &mali->steps[step];
if (step <= mali->dvfs_step)
- clk_set_rate(mali->sclk, next->rate);
+ clk_set_rate(mali->sclk, next->rate * 1000000);
regulator_set_voltage(mali->vdd_g3d,
- next->min_uv, next->max_uv);
+ next->voltage, next->voltage);
if (step > mali->dvfs_step)
- clk_set_rate(mali->sclk, next->rate);
+ clk_set_rate(mali->sclk, next->rate * 1000000);
- _mali_osk_profiling_add_gpufreq_event(next->rate / 1000000,
+ _mali_osk_profiling_add_gpufreq_event(next->rate * 1000000,
regulator_get_voltage(mali->vdd_g3d) / 1000);
mali->dvfs_step = step;
}