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| author | David Daney <ddaney@caviumnetworks.com> | 2009-05-13 15:59:55 -0700 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2009-06-17 11:06:31 +0100 |
| commit | fbeda19f82aa07082d2e1607a9f5114141dae2ac (patch) | |
| tree | c631cfe8884cd72a4fd709baf72e857edbbac477 | |
| parent | 9cffd154cf6817b130762501b91e753524ba2cd4 (diff) | |
| download | linux-3.10-fbeda19f82aa07082d2e1607a9f5114141dae2ac.tar.gz linux-3.10-fbeda19f82aa07082d2e1607a9f5114141dae2ac.tar.bz2 linux-3.10-fbeda19f82aa07082d2e1607a9f5114141dae2ac.zip | |
MIPS: Allow CPU specific overriding of CP0 hwrena impl bits.
Some CPUs have implementation dependent rdhwr registers. Allow them
to be enabled on a per CPU basis.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | arch/mips/include/asm/cpu-features.h | 4 | ||||
| -rw-r--r-- | arch/mips/kernel/traps.c | 2 |
2 files changed, 5 insertions, 1 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 1cba4b2ffd1..8ab1d12ba7f 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -234,4 +234,8 @@ #define cpu_scache_line_size() cpu_data[0].scache.linesz #endif +#ifndef cpu_hwrena_impl_bits +#define cpu_hwrena_impl_bits 0 +#endif + #endif /* __ASM_CPU_FEATURES_H */ diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index e83da174b53..f54871797ab 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1502,7 +1502,7 @@ void __cpuinit per_cpu_trap_init(void) status_set); if (cpu_has_mips_r2) { - unsigned int enable = 0x0000000f; + unsigned int enable = 0x0000000f | cpu_hwrena_impl_bits; if (!noulri && cpu_has_userlocal) enable |= (1 << 29); |