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| author | Changhwan Youn <chaos.youn@samsung.com> | 2011-07-16 10:49:47 +0900 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2011-07-20 23:28:22 +0900 |
| commit | e807acbc6fd1d5ff115f9a8eae0c1af6cf1c46c6 (patch) | |
| tree | 6a5c7698ebdf83f9813b10b9f6f84a778c40ffd6 | |
| parent | a8769a594a6d061f8018048a7cd1546924c61a5c (diff) | |
| download | linux-3.10-e807acbc6fd1d5ff115f9a8eae0c1af6cf1c46c6.tar.gz linux-3.10-e807acbc6fd1d5ff115f9a8eae0c1af6cf1c46c6.tar.bz2 linux-3.10-e807acbc6fd1d5ff115f9a8eae0c1af6cf1c46c6.zip | |
ARM: GIC: move gic_chip_data structure declaration to header
Since Samsung EXYNOS4210 cannot support register banking in GIC,
so needs to update CPU interface base address.
The 'gic_chip_data' is used for it, this patch moves gic_chip_data
structure declaraton to arch/arm/include/asm/hardware/gic.h to use
it.
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| -rw-r--r-- | arch/arm/common/gic.c | 6 | ||||
| -rw-r--r-- | arch/arm/include/asm/hardware/gic.h | 6 |
2 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index 4ddd0a6ac7f..23564edbd84 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -38,12 +38,6 @@ static DEFINE_SPINLOCK(irq_controller_lock); /* Address of GIC 0 CPU interface */ void __iomem *gic_cpu_base_addr __read_mostly; -struct gic_chip_data { - unsigned int irq_offset; - void __iomem *dist_base; - void __iomem *cpu_base; -}; - /* * Supported arch specific GIC irq extension. * Default make them NULL. diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h index 0691f9dcc50..435d3f86c70 100644 --- a/arch/arm/include/asm/hardware/gic.h +++ b/arch/arm/include/asm/hardware/gic.h @@ -41,6 +41,12 @@ void gic_secondary_init(unsigned int); void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); void gic_raise_softirq(const struct cpumask *mask, unsigned int irq); void gic_enable_ppi(unsigned int); + +struct gic_chip_data { + unsigned int irq_offset; + void __iomem *dist_base; + void __iomem *cpu_base; +}; #endif #endif |