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| author | Dan Williams <dan.j.williams@intel.com> | 2009-09-08 17:42:57 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2009-09-08 17:42:57 -0700 |
| commit | e61dacaeb3918cd00cd642e8fb0828324ac59819 (patch) | |
| tree | 70c4acf1cf33502bdca8da16bd88c0daab2bbc29 | |
| parent | 5669e31c5a4874f1634bc0ffba268a6e2fa0cdd2 (diff) | |
| download | linux-3.10-e61dacaeb3918cd00cd642e8fb0828324ac59819.tar.gz linux-3.10-e61dacaeb3918cd00cd642e8fb0828324ac59819.tar.bz2 linux-3.10-e61dacaeb3918cd00cd642e8fb0828324ac59819.zip | |
ioat3: enable dca for completion writes
Tag completion writes for direct cache access to reduce the latency of
checking for descriptor completions.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| -rw-r--r-- | drivers/dma/ioat/dma_v3.c | 3 | ||||
| -rw-r--r-- | drivers/dma/ioat/registers.h | 1 |
2 files changed, 3 insertions, 1 deletions
diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c index 22af78ec257..0913d11e09e 100644 --- a/drivers/dma/ioat/dma_v3.c +++ b/drivers/dma/ioat/dma_v3.c @@ -167,7 +167,8 @@ static void ioat3_cleanup_tasklet(unsigned long data) struct ioat2_dma_chan *ioat = (void *) data; ioat3_cleanup(ioat); - writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET); + writew(IOAT_CHANCTRL_RUN | IOAT3_CHANCTRL_COMPL_DCA_EN, + ioat->base.reg_base + IOAT_CHANCTRL_OFFSET); } static void ioat3_restart_channel(struct ioat2_dma_chan *ioat) diff --git a/drivers/dma/ioat/registers.h b/drivers/dma/ioat/registers.h index 85d04b8c563..97d26ea6d72 100644 --- a/drivers/dma/ioat/registers.h +++ b/drivers/dma/ioat/registers.h @@ -84,6 +84,7 @@ /* DMA Channel Registers */ #define IOAT_CHANCTRL_OFFSET 0x00 /* 16-bit Channel Control Register */ #define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF000 +#define IOAT3_CHANCTRL_COMPL_DCA_EN 0x0200 #define IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100 #define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020 #define IOAT_CHANCTRL_ERR_INT_EN 0x0010 |