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| author | Paul Walmsley <paul@pwsan.com> | 2012-10-29 20:55:46 -0600 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2012-11-08 12:33:07 -0700 |
| commit | d08cce6a1d6952a7774e4b61066d469c16d47a11 (patch) | |
| tree | 13b56e022d8c8eaf720256b0de9dd9e1460a5d18 | |
| parent | b6a4226c14001b0aa20b11c69190cb89d2237d3d (diff) | |
| download | linux-3.10-d08cce6a1d6952a7774e4b61066d469c16d47a11.tar.gz linux-3.10-d08cce6a1d6952a7774e4b61066d469c16d47a11.tar.bz2 linux-3.10-d08cce6a1d6952a7774e4b61066d469c16d47a11.zip | |
ARM: OMAP2/3: PRM: add SoC reset functions (using the CORE DPLL method)
Add SoC reset functions into the PRM code. These functions are based
on code from mach-omap2/prcm.c. They reset the SoC using the CORE DPLL
reset method (as opposed to one of the other two or three chip reset
methods).
Adding them here will facilitate their removal from
arch/arm/mach-omap2/prcm.c. (prcm.c is deprecated.)
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Vaibhav Hiremath <hvaibhav@ti.com>
| -rw-r--r-- | arch/arm/mach-omap2/prm2xxx.c | 14 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/prm2xxx.h | 2 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/prm3xxx.c | 15 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/prm3xxx.h | 2 |
4 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c index e2860f9c111..1f777bf2bc8 100644 --- a/arch/arm/mach-omap2/prm2xxx.c +++ b/arch/arm/mach-omap2/prm2xxx.c @@ -69,6 +69,20 @@ static u32 omap2xxx_prm_read_reset_sources(void) return r; } +/** + * omap2xxx_prm_dpll_reset - use DPLL reset to reboot the OMAP SoC + * + * Set the DPLL reset bit, which should reboot the SoC. This is the + * recommended way to restart the SoC. No return value. + */ +void omap2xxx_prm_dpll_reset(void) +{ + omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, WKUP_MOD, + OMAP2_RM_RSTCTRL); + /* OCP barrier */ + omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTCTRL); +} + int omap2xxx_clkdm_sleep(struct clockdomain *clkdm) { omap2_prm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, diff --git a/arch/arm/mach-omap2/prm2xxx.h b/arch/arm/mach-omap2/prm2xxx.h index 1d97112524f..fe8a14f190a 100644 --- a/arch/arm/mach-omap2/prm2xxx.h +++ b/arch/arm/mach-omap2/prm2xxx.h @@ -124,6 +124,8 @@ extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm); extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm); +extern void omap2xxx_prm_dpll_reset(void); + extern int __init prm2xxx_init(void); extern int __exit prm2xxx_exit(void); diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c index 1fea656b2ca..5435673ac9c 100644 --- a/arch/arm/mach-omap2/prm3xxx.c +++ b/arch/arm/mach-omap2/prm3xxx.c @@ -123,6 +123,21 @@ u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset) } /** + * omap3xxx_prm_dpll3_reset - use DPLL3 reset to reboot the OMAP SoC + * + * Set the DPLL3 reset bit, which should reboot the SoC. This is the + * recommended way to restart the SoC, considering Errata i520. No + * return value. + */ +void omap3xxx_prm_dpll3_reset(void) +{ + omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, OMAP3430_GR_MOD, + OMAP2_RM_RSTCTRL); + /* OCP barrier */ + omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP2_RM_RSTCTRL); +} + +/** * omap3xxx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events * @events: ptr to a u32, preallocated by caller * diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h index a3c28a87541..10cd41a8129 100644 --- a/arch/arm/mach-omap2/prm3xxx.h +++ b/arch/arm/mach-omap2/prm3xxx.h @@ -152,6 +152,8 @@ extern void omap3xxx_prm_ocp_barrier(void); extern void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask); extern void omap3xxx_prm_restore_irqen(u32 *saved_mask); +extern void omap3xxx_prm_dpll3_reset(void); + extern u32 omap3xxx_prm_get_reset_sources(void); #endif /* __ASSEMBLER */ |