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| author | Russ Anderson <rja@sgi.com> | 2006-10-25 14:18:27 -0500 |
|---|---|---|
| committer | Tony Luck <tony.luck@intel.com> | 2006-12-07 11:02:38 -0800 |
| commit | 323cbb09917024cab522bc7ce5c343659cbe8818 (patch) | |
| tree | f8edcf9abe1236894fa66bf809daddf001a70c4e | |
| parent | c69577711a8fd232e6b309c3e99f9a8f96f63082 (diff) | |
| download | linux-3.10-323cbb09917024cab522bc7ce5c343659cbe8818.tar.gz linux-3.10-323cbb09917024cab522bc7ce5c343659cbe8818.tar.bz2 linux-3.10-323cbb09917024cab522bc7ce5c343659cbe8818.zip | |
[IA64] Add dp bit to cache and bus check structs
Rev 2.2 of Volume 2 of "Intel Itanium Architecture Software Developer's
Manual" (January 2006) adds a dp bit to the cache_check and bus_check
fields (pages 2:401-2:404). This patch gets the structs back in sync
with the spec.
Signed-off-by: Russ Anderson (rja@sgi.com)
Signed-off-by: Tony Luck <tony.luck@intel.com>
| -rw-r--r-- | include/asm-ia64/pal.h | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h index 4283ddcc25f..b6d4f6f0c3c 100644 --- a/include/asm-ia64/pal.h +++ b/include/asm-ia64/pal.h @@ -487,10 +487,12 @@ typedef struct pal_cache_check_info_s { * error occurred */ wiv : 1, /* Way field valid */ - reserved2 : 10, + reserved2 : 1, + dp : 1, /* Data poisoned on MBE */ + reserved3 : 8, index : 20, /* Cache line index */ - reserved3 : 2, + reserved4 : 2, is : 1, /* instruction set (1 == ia32) */ iv : 1, /* instruction set field valid */ @@ -557,7 +559,7 @@ typedef struct pal_bus_check_info_s { type : 8, /* Bus xaction type*/ sev : 5, /* Bus error severity*/ hier : 2, /* Bus hierarchy level */ - reserved1 : 1, + dp : 1, /* Data poisoned on MBE */ bsi : 8, /* Bus error status * info */ |