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authorHyungwon Hwang <human.hwang@samsung.com>2014-12-15 05:36:21 (GMT)
committerHyungwon Hwang <human.hwang@samsung.com>2014-12-23 02:09:30 (GMT)
commitb8175e7f5263fe239212163d38254846e54b67d4 (patch)
tree9d4d20bda6bcf36b448cd3286a6a074018644fff
parentc5805f7ddad43efb5279cf9b6ff7cde61e15ac5f (diff)
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clk: samsung: add new variable to compensate the gap for control register
PLL35xx and PLL2550 are very similar, and so they share the code for their control. PLL2550 in Exynos5422 have different offsets to control register from the base of them. mainline linux have the variable for it. But because of too much difference between the mainline linux and Tizen 3.10. It cannot be adopted with few commits. So I made this patch to accomplish this purpose with small changes. Change-Id: Iae2192a62d9d9cc6fcd24fb009c7a41f89acb8f3 Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
-rw-r--r--drivers/clk/samsung/clk-exynos4.c5
-rw-r--r--drivers/clk/samsung/clk-pll.c21
-rw-r--r--drivers/clk/samsung/clk-pll.h2
3 files changed, 18 insertions, 10 deletions
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 96de2b4..5de5fa3 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1140,9 +1140,10 @@ void __init exynos4_clk_init(struct device_node *np, enum exynos4_soc exynos4_so
exynos4_vpll_pms);
} else {
apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
- reg_base + APLL_LOCK, pll35xx_exynos4412_pms);
+ reg_base + APLL_LOCK, pll35xx_exynos4412_pms, 0x0);
mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
- reg_base + E4X12_MPLL_LOCK, pll35xx_exynos4412_pms);
+ reg_base + E4X12_MPLL_LOCK, pll35xx_exynos4412_pms,
+ 0x0);
epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
reg_base + EPLL_LOCK, exynos4_epll_pms);
vpll = samsung_clk_register_pll36xx("fout_vpll", "fin_pll",
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 7989c27..981c119 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -34,6 +34,7 @@ struct samsung_clk_pll35xx {
struct clk_hw hw;
const void __iomem *base_reg;
struct pll_pms *pms;
+ unsigned int con_offset;
};
static int get_index(unsigned long rate, struct pll_pms *pms)
@@ -61,7 +62,8 @@ static inline unsigned long samsung_pll35xx_calc_f_out(u64 f_in,
static inline void samsung_pll35xx_get_mps(struct samsung_clk_pll35xx *pll,
u32 *m, u32 *p, u32 *s)
{
- u32 pll_con = __raw_readl(pll->base_reg + PLL35XX_PLL_CON0);
+ u32 pll_con = __raw_readl(pll->base_reg + PLL35XX_PLL_CON0
+ + pll->con_offset);
*m = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
*p = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
@@ -119,10 +121,12 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
samsung_pll35xx_get_mps(pll, &m_cur, &p_cur, &s_cur);
if (p == p_cur && m == m_cur) {
- tmp = __raw_readl(pll->base_reg + PLL35XX_PLL_CON0);
+ tmp = __raw_readl(pll->base_reg + PLL35XX_PLL_CON0
+ + pll->con_offset);
tmp &= ~(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT);
tmp |= s << PLL35XX_SDIV_SHIFT;
- __raw_writel(tmp, (u32 *)(pll->base_reg + PLL35XX_PLL_CON0));
+ __raw_writel(tmp, (u32 *)(pll->base_reg + PLL35XX_PLL_CON0
+ + pll->con_offset));
return 0;
}
@@ -132,18 +136,20 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
(u32*) (pll->base_reg + PLL35XX_PLL_LOCK));
/* Change PLL PMS */
- tmp = __raw_readl(pll->base_reg + PLL35XX_PLL_CON0);
+ tmp = __raw_readl(pll->base_reg + PLL35XX_PLL_CON0 + pll->con_offset);
tmp &= ~((PLL35XX_PDIV_MASK << PLL35XX_PDIV_SHIFT) |
(PLL35XX_MDIV_MASK << PLL35XX_MDIV_SHIFT) |
(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT));
tmp |= (p << PLL35XX_PDIV_SHIFT) | (m << PLL35XX_MDIV_SHIFT) |
(s << PLL35XX_SDIV_SHIFT);
- __raw_writel(tmp, (u32*) (pll->base_reg + PLL35XX_PLL_CON0));
+ __raw_writel(tmp, (u32 *) (pll->base_reg + PLL35XX_PLL_CON0
+ + pll->con_offset));
/* Wait for locking */
do {
cpu_relax();
- tmp = __raw_readl(pll->base_reg + PLL35XX_PLL_CON0);
+ tmp = __raw_readl(pll->base_reg + PLL35XX_PLL_CON0
+ + pll->con_offset);
} while (!(tmp & PLL35XX_LOCKED));
return 0;
@@ -158,7 +164,7 @@ static const struct clk_ops samsung_pll35xx_clk_ops = {
struct clk * __init
samsung_clk_register_pll35xx(const char *name,
const char *pname, const void __iomem *base_reg,
- struct pll_pms *pms)
+ struct pll_pms *pms, const unsigned int con_offset)
{
struct samsung_clk_pll35xx *pll;
struct clk *clk;
@@ -185,6 +191,7 @@ samsung_clk_register_pll35xx(const char *name,
pll->hw.init = &init;
pll->base_reg = base_reg;
pll->pms = pms;
+ pll->con_offset = con_offset;
clk = clk_register(NULL, &pll->hw);
if (IS_ERR(clk)) {
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index 5b1bb240..98577f3 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -40,7 +40,7 @@ struct pll_pms {
extern struct clk * __init samsung_clk_register_pll35xx(const char *name,
const char *pname, const void __iomem *base_reg,
- struct pll_pms *pms);
+ struct pll_pms *pms, const unsigned int con_offset);
extern struct clk * __init samsung_clk_register_pll36xx(const char *name,
const char *pname, void __iomem *base,
struct pll_pms *pms);