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authorVivek Gautam <gautam.vivek@samsung.com>2014-05-16 06:37:03 +0900
committerHyungwon Hwang <human.hwang@samsung.com>2014-12-17 16:18:10 +0900
commit6d2635c7e583ae1693473d14caf89716c21dba8b (patch)
tree83b769392cc080cbde83041e72b62aacf94de176
parentba49ca30c5ff23a89bceb29345e4be60bb238d54 (diff)
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ARM: dts: Enable support for USB 3.0 PHY controller for exynos5420
Add device tree nodes for USB 3.0 PHY present alongwith USB 3.0 controller Exynos 5420 SoC. This phy driver is based on generic phy framework. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi20
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index ed8ed30e555..86df4954129 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -47,6 +47,8 @@
spi0 = &spi_0;
spi1 = &spi_1;
spi2 = &spi_2;
+ usbdrdphy0 = &usbdrd_phy0;
+ usbdrdphy1 = &usbdrd_phy1;
};
cpus {
@@ -778,4 +780,22 @@
clocks = <&clock 471>;
clock-names = "secss";
};
+
+ usbdrd_phy0: phy@12100000 {
+ compatible = "samsung,exynos5420-usbdrd-phy";
+ reg = <0x12100000 0x100>;
+ clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
+ clock-names = "phy", "ref";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ #phy-cells = <1>;
+ };
+
+ usbdrd_phy1: phy@12500000 {
+ compatible = "samsung,exynos5420-usbdrd-phy";
+ reg = <0x12500000 0x100>;
+ clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
+ clock-names = "phy", "ref";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ #phy-cells = <1>;
+ };
};