diff options
| author | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2013-12-02 17:26:13 -0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2013-12-02 17:26:13 -0800 |
| commit | f5d290762e8a38e0cc3b7de94b41e8ebba6d15f4 (patch) | |
| tree | 120446d275312a364c6488dab9346b1971c18795 | |
| parent | 182af9b5c69837bd0169f8900752c2c02b09f183 (diff) | |
| download | linux-3.10-f5d290762e8a38e0cc3b7de94b41e8ebba6d15f4.tar.gz linux-3.10-f5d290762e8a38e0cc3b7de94b41e8ebba6d15f4.tar.bz2 linux-3.10-f5d290762e8a38e0cc3b7de94b41e8ebba6d15f4.zip | |
add patches.renesas/
596 files changed, 79838 insertions, 5 deletions
diff --git a/patches.renesas/0001-serial-sh-sci-HSCIF-support.patch b/patches.renesas/0001-serial-sh-sci-HSCIF-support.patch new file mode 100644 index 00000000000..a965f5c7119 --- /dev/null +++ b/patches.renesas/0001-serial-sh-sci-HSCIF-support.patch @@ -0,0 +1,350 @@ +From 81c07ee1346e7f7255af5511b715e981da36304e Mon Sep 17 00:00:00 2001 +From: Ulrich Hecht <ulrich.hecht@gmail.com> +Date: Fri, 31 May 2013 17:57:01 +0200 +Subject: serial: sh-sci: HSCIF support + +Adds support for "High Speed Serial Communications Interface with FIFO", +essentially a SCIF with 128-byte FIFOs and more accurate baud rate +generator. + +Signed-off-by: Ulrich Hecht <ulrich.hecht@gmail.com> +Acked-by: Paul Mundt <lethal@linux-sh.org> +Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit f303b364b41d3fc5bf879799128958400b7859aa) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/tty/serial/sh-sci.c | 102 ++++++++++++++++++++++++++++++++++++--- + include/linux/serial_sci.h | 12 +++-- + include/uapi/linux/serial_core.h | 3 ++ + 3 files changed, 106 insertions(+), 11 deletions(-) + +diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c +index 15641861..931d6c3a 100644 +--- a/drivers/tty/serial/sh-sci.c ++++ b/drivers/tty/serial/sh-sci.c +@@ -146,6 +146,7 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { + [SCRFDR] = sci_reg_invalid, + [SCSPTR] = sci_reg_invalid, + [SCLSR] = sci_reg_invalid, ++ [HSSRR] = sci_reg_invalid, + }, + + /* +@@ -165,6 +166,7 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { + [SCRFDR] = sci_reg_invalid, + [SCSPTR] = sci_reg_invalid, + [SCLSR] = sci_reg_invalid, ++ [HSSRR] = sci_reg_invalid, + }, + + /* +@@ -183,6 +185,7 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { + [SCRFDR] = sci_reg_invalid, + [SCSPTR] = sci_reg_invalid, + [SCLSR] = sci_reg_invalid, ++ [HSSRR] = sci_reg_invalid, + }, + + /* +@@ -201,6 +204,7 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { + [SCRFDR] = { 0x3c, 16 }, + [SCSPTR] = sci_reg_invalid, + [SCLSR] = sci_reg_invalid, ++ [HSSRR] = sci_reg_invalid, + }, + + /* +@@ -220,6 +224,7 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { + [SCRFDR] = sci_reg_invalid, + [SCSPTR] = { 0x20, 16 }, + [SCLSR] = { 0x24, 16 }, ++ [HSSRR] = sci_reg_invalid, + }, + + /* +@@ -238,6 +243,7 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { + [SCRFDR] = sci_reg_invalid, + [SCSPTR] = sci_reg_invalid, + [SCLSR] = sci_reg_invalid, ++ [HSSRR] = sci_reg_invalid, + }, + + /* +@@ -256,6 +262,26 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { + [SCRFDR] = sci_reg_invalid, + [SCSPTR] = { 0x20, 16 }, + [SCLSR] = { 0x24, 16 }, ++ [HSSRR] = sci_reg_invalid, ++ }, ++ ++ /* ++ * Common HSCIF definitions. ++ */ ++ [SCIx_HSCIF_REGTYPE] = { ++ [SCSMR] = { 0x00, 16 }, ++ [SCBRR] = { 0x04, 8 }, ++ [SCSCR] = { 0x08, 16 }, ++ [SCxTDR] = { 0x0c, 8 }, ++ [SCxSR] = { 0x10, 16 }, ++ [SCxRDR] = { 0x14, 8 }, ++ [SCFCR] = { 0x18, 16 }, ++ [SCFDR] = { 0x1c, 16 }, ++ [SCTFDR] = sci_reg_invalid, ++ [SCRFDR] = sci_reg_invalid, ++ [SCSPTR] = { 0x20, 16 }, ++ [SCLSR] = { 0x24, 16 }, ++ [HSSRR] = { 0x40, 16 }, + }, + + /* +@@ -275,6 +301,7 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { + [SCRFDR] = sci_reg_invalid, + [SCSPTR] = sci_reg_invalid, + [SCLSR] = { 0x24, 16 }, ++ [HSSRR] = sci_reg_invalid, + }, + + /* +@@ -294,6 +321,7 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { + [SCRFDR] = { 0x20, 16 }, + [SCSPTR] = { 0x24, 16 }, + [SCLSR] = { 0x28, 16 }, ++ [HSSRR] = sci_reg_invalid, + }, + + /* +@@ -313,6 +341,7 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { + [SCRFDR] = sci_reg_invalid, + [SCSPTR] = sci_reg_invalid, + [SCLSR] = sci_reg_invalid, ++ [HSSRR] = sci_reg_invalid, + }, + }; + +@@ -374,6 +403,9 @@ static int sci_probe_regmap(struct plat_sci_port *cfg) + */ + cfg->regtype = SCIx_SH4_SCIF_REGTYPE; + break; ++ case PORT_HSCIF: ++ cfg->regtype = SCIx_HSCIF_REGTYPE; ++ break; + default: + printk(KERN_ERR "Can't probe register map for given port\n"); + return -EINVAL; +@@ -1798,6 +1830,42 @@ static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps, + return ((freq + 16 * bps) / (32 * bps) - 1); + } + ++/* calculate sample rate, BRR, and clock select for HSCIF */ ++static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq, ++ int *brr, unsigned int *srr, ++ unsigned int *cks) ++{ ++ int sr, c, br, err; ++ int min_err = 1000; /* 100% */ ++ ++ /* Find the combination of sample rate and clock select with the ++ smallest deviation from the desired baud rate. */ ++ for (sr = 8; sr <= 32; sr++) { ++ for (c = 0; c <= 3; c++) { ++ /* integerized formulas from HSCIF documentation */ ++ br = freq / (sr * (1 << (2 * c + 1)) * bps) - 1; ++ if (br < 0 || br > 255) ++ continue; ++ err = freq / ((br + 1) * bps * sr * ++ (1 << (2 * c + 1)) / 1000) - 1000; ++ if (min_err > err) { ++ min_err = err; ++ *brr = br; ++ *srr = sr - 1; ++ *cks = c; ++ } ++ } ++ } ++ ++ if (min_err == 1000) { ++ WARN_ON(1); ++ /* use defaults */ ++ *brr = 255; ++ *srr = 15; ++ *cks = 0; ++ } ++} ++ + static void sci_reset(struct uart_port *port) + { + struct plat_sci_reg *reg; +@@ -1821,6 +1889,7 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios, + struct plat_sci_reg *reg; + unsigned int baud, smr_val, max_baud, cks; + int t = -1; ++ unsigned int srr; + + /* + * earlyprintk comes here early on with port->uartclk set to zero. +@@ -1833,8 +1902,17 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios, + max_baud = port->uartclk ? port->uartclk / 16 : 115200; + + baud = uart_get_baud_rate(port, termios, old, 0, max_baud); +- if (likely(baud && port->uartclk)) +- t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk); ++ if (likely(baud && port->uartclk)) { ++ if (s->cfg->scbrr_algo_id == SCBRR_ALGO_6) { ++ sci_baud_calc_hscif(baud, port->uartclk, &t, &srr, ++ &cks); ++ } else { ++ t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, ++ port->uartclk); ++ for (cks = 0; t >= 256 && cks <= 3; cks++) ++ t >>= 2; ++ } ++ } + + sci_port_enable(s); + +@@ -1853,15 +1931,15 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios, + + uart_update_timeout(port, termios->c_cflag, baud); + +- for (cks = 0; t >= 256 && cks <= 3; cks++) +- t >>= 2; +- + dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n", + __func__, smr_val, cks, t, s->cfg->scscr); + + if (t >= 0) { + serial_port_out(port, SCSMR, (smr_val & ~3) | cks); + serial_port_out(port, SCBRR, t); ++ reg = sci_getreg(port, HSSRR); ++ if (reg->size) ++ serial_port_out(port, HSSRR, srr | HSCIF_SRE); + udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */ + } else + serial_port_out(port, SCSMR, smr_val); +@@ -1947,6 +2025,8 @@ static const char *sci_type(struct uart_port *port) + return "scifa"; + case PORT_SCIFB: + return "scifb"; ++ case PORT_HSCIF: ++ return "hscif"; + } + + return NULL; +@@ -1960,7 +2040,10 @@ static inline unsigned long sci_port_size(struct uart_port *port) + * from platform resource data at such a time that ports begin to + * behave more erratically. + */ +- return 64; ++ if (port->type == PORT_HSCIF) ++ return 96; ++ else ++ return 64; + } + + static int sci_remap_port(struct uart_port *port) +@@ -2085,6 +2168,9 @@ static int sci_init_single(struct platform_device *dev, + case PORT_SCIFB: + port->fifosize = 256; + break; ++ case PORT_HSCIF: ++ port->fifosize = 128; ++ break; + case PORT_SCIFA: + port->fifosize = 64; + break; +@@ -2325,7 +2411,7 @@ static inline int sci_probe_earlyprintk(struct platform_device *pdev) + #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ + + static char banner[] __initdata = +- KERN_INFO "SuperH SCI(F) driver initialized\n"; ++ KERN_INFO "SuperH (H)SCI(F) driver initialized\n"; + + static struct uart_driver sci_uart_driver = { + .owner = THIS_MODULE, +@@ -2484,4 +2570,4 @@ module_exit(sci_exit); + MODULE_LICENSE("GPL"); + MODULE_ALIAS("platform:sh-sci"); + MODULE_AUTHOR("Paul Mundt"); +-MODULE_DESCRIPTION("SuperH SCI(F) serial driver"); ++MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); +diff --git a/include/linux/serial_sci.h b/include/linux/serial_sci.h +index eb763adf..d3404971 100644 +--- a/include/linux/serial_sci.h ++++ b/include/linux/serial_sci.h +@@ -5,7 +5,7 @@ + #include <linux/sh_dma.h> + + /* +- * Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts) ++ * Generic header for SuperH (H)SCI(F) (used by sh/sh64/h8300 and related parts) + */ + + #define SCIx_NOT_SUPPORTED (-1) +@@ -16,6 +16,7 @@ enum { + SCBRR_ALGO_3, /* (((clk * 2) + 16 * bps) / (16 * bps) - 1) */ + SCBRR_ALGO_4, /* (((clk * 2) + 16 * bps) / (32 * bps) - 1) */ + SCBRR_ALGO_5, /* (((clk * 1000 / 32) / bps) - 1) */ ++ SCBRR_ALGO_6, /* HSCIF variable sample rate algorithm */ + }; + + #define SCSCR_TIE (1 << 7) +@@ -37,7 +38,7 @@ enum { + + #define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER) + +-/* SCxSR SCIF */ ++/* SCxSR SCIF, HSCIF */ + #define SCIF_ER 0x0080 + #define SCIF_TEND 0x0040 + #define SCIF_TDFE 0x0020 +@@ -55,6 +56,9 @@ enum { + #define SCSPTR_SPB2IO (1 << 1) + #define SCSPTR_SPB2DT (1 << 0) + ++/* HSSRR HSCIF */ ++#define HSCIF_SRE 0x8000 ++ + /* Offsets into the sci_port->irqs array */ + enum { + SCIx_ERI_IRQ, +@@ -90,6 +94,7 @@ enum { + SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, + SCIx_SH4_SCIF_FIFODATA_REGTYPE, + SCIx_SH7705_SCIF_REGTYPE, ++ SCIx_HSCIF_REGTYPE, + + SCIx_NR_REGTYPES, + }; +@@ -115,6 +120,7 @@ enum { + SCSMR, SCBRR, SCSCR, SCxSR, + SCFCR, SCFDR, SCxTDR, SCxRDR, + SCLSR, SCTFDR, SCRFDR, SCSPTR, ++ HSSRR, + + SCIx_NR_REGS, + }; +@@ -137,7 +143,7 @@ struct plat_sci_port { + unsigned long mapbase; /* resource base */ + unsigned int irqs[SCIx_NR_IRQS]; /* ERI, RXI, TXI, BRI */ + unsigned int gpios[SCIx_NR_FNS]; /* SCK, RXD, TXD, CTS, RTS */ +- unsigned int type; /* SCI / SCIF / IRDA */ ++ unsigned int type; /* SCI / SCIF / IRDA / HSCIF */ + upf_t flags; /* UPF_* flags */ + unsigned long capabilities; /* Port features/capabilities */ + +diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h +index 74c2bf72..26eee07e 100644 +--- a/include/uapi/linux/serial_core.h ++++ b/include/uapi/linux/serial_core.h +@@ -226,4 +226,7 @@ + /* Rocketport EXPRESS/INFINITY */ + #define PORT_RP2 102 + ++/* SH-SCI */ ++#define PORT_HSCIF 103 ++ + #endif /* _UAPILINUX_SERIAL_CORE_H */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0002-serial-sh-sci-Initialise-variables-before-access-in-.patch b/patches.renesas/0002-serial-sh-sci-Initialise-variables-before-access-in-.patch new file mode 100644 index 00000000000..60a0ecf3fd2 --- /dev/null +++ b/patches.renesas/0002-serial-sh-sci-Initialise-variables-before-access-in-.patch @@ -0,0 +1,46 @@ +From 6fa4b6ed6e225d83465924edf96967a3be13a056 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Thu, 20 Jun 2013 21:09:45 +0900 +Subject: serial: sh-sci: Initialise variables before access in + sci_set_termios() + +This change addresses two warnings that are flagged by gcc relating to +potential access to the ssr and cks variables while they are uninitialised. + +I have addressed this by initialising the values to +the defaults present in sci_baud_calc_hscif(). + +It is my analysis that cks is always initialised if used +but that without this change ssr may be accessed while uninitialised. + +The code altered by this patch was introduced by commit +f303b364b41d3fc5bf879799128958400b7859aa ("serial: sh-sci: HSCIF support"). + +Reported-by: Arnd Bergmann <arnd@arndb.de> +Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d4759ded3bdf3eb004d583011707fdc21aeda94e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/tty/serial/sh-sci.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c +index 931d6c3a..7477e0ea 100644 +--- a/drivers/tty/serial/sh-sci.c ++++ b/drivers/tty/serial/sh-sci.c +@@ -1887,9 +1887,9 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios, + { + struct sci_port *s = to_sci_port(port); + struct plat_sci_reg *reg; +- unsigned int baud, smr_val, max_baud, cks; ++ unsigned int baud, smr_val, max_baud, cks = 0; + int t = -1; +- unsigned int srr; ++ unsigned int srr = 15; + + /* + * earlyprintk comes here early on with port->uartclk set to zero. +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0003-serial-sh-sci-use-dev_get_platdata.patch b/patches.renesas/0003-serial-sh-sci-use-dev_get_platdata.patch new file mode 100644 index 00000000000..88d6f7a5811 --- /dev/null +++ b/patches.renesas/0003-serial-sh-sci-use-dev_get_platdata.patch @@ -0,0 +1,32 @@ +From e4dc1384aea42fba61c6417f302a9d48dba956dd Mon Sep 17 00:00:00 2001 +From: Jingoo Han <jg1.han@samsung.com> +Date: Thu, 1 Aug 2013 18:17:45 +0900 +Subject: serial: sh-sci: use dev_get_platdata() + +Use the wrapper function for retrieving the platform data instead of +accessing dev->platform_data directly + +Signed-off-by: Jingoo Han <jg1.han@samsung.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 3ba35baa55fa4420f9ea7132d728ed68cfa37d28) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/tty/serial/sh-sci.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c +index 7477e0ea..9d776066 100644 +--- a/drivers/tty/serial/sh-sci.c ++++ b/drivers/tty/serial/sh-sci.c +@@ -2469,7 +2469,7 @@ static int sci_probe_single(struct platform_device *dev, + + static int sci_probe(struct platform_device *dev) + { +- struct plat_sci_port *p = dev->dev.platform_data; ++ struct plat_sci_port *p = dev_get_platdata(&dev->dev); + struct sci_port *sp = &sci_ports[dev->id]; + int ret; + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0004-ata-use-platform_-get-set-_drvdata.patch b/patches.renesas/0004-ata-use-platform_-get-set-_drvdata.patch new file mode 100644 index 00000000000..c8677a7a2e6 --- /dev/null +++ b/patches.renesas/0004-ata-use-platform_-get-set-_drvdata.patch @@ -0,0 +1,220 @@ +From c98f9448263fa3880c3fe926a2306750c407ff84 Mon Sep 17 00:00:00 2001 +From: Jingoo Han <jg1.han@samsung.com> +Date: Thu, 23 May 2013 19:41:21 +0900 +Subject: ata: use platform_{get,set}_drvdata() + +Use the wrapper functions for getting and setting the driver data using +platform_device instead of using dev_{get,set}_drvdata() with &pdev->dev, +so we can directly pass a struct platform_device. + +Also, unnecessary dev_set_drvdata() is removed, because the driver core +clears the driver data to NULL after device_release or on probe failure. + +Signed-off-by: Jingoo Han <jg1.han@samsung.com> +Signed-off-by: Tejun Heo <tj@kernel.org> +(cherry picked from commit d89995db5f238e618389604b848b431da240eb69) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/ata/pata_arasan_cf.c | 2 +- + drivers/ata/pata_at91.c | 2 +- + drivers/ata/pata_bf54x.c | 10 ++++------ + drivers/ata/pata_imx.c | 2 +- + drivers/ata/pata_mpc52xx.c | 4 ++-- + drivers/ata/pata_pxa.c | 2 +- + drivers/ata/sata_fsl.c | 14 +++++--------- + drivers/ata/sata_rcar.c | 2 +- + 8 files changed, 16 insertions(+), 22 deletions(-) + +diff --git a/drivers/ata/pata_arasan_cf.c b/drivers/ata/pata_arasan_cf.c +index 7638121c..848ed325 100644 +--- a/drivers/ata/pata_arasan_cf.c ++++ b/drivers/ata/pata_arasan_cf.c +@@ -908,7 +908,7 @@ free_clk: + + static int arasan_cf_remove(struct platform_device *pdev) + { +- struct ata_host *host = dev_get_drvdata(&pdev->dev); ++ struct ata_host *host = platform_get_drvdata(pdev); + struct arasan_cf_dev *acdev = host->ports[0]->private_data; + + ata_host_detach(host); +diff --git a/drivers/ata/pata_at91.c b/drivers/ata/pata_at91.c +index 033f3f4c..5364f97b 100644 +--- a/drivers/ata/pata_at91.c ++++ b/drivers/ata/pata_at91.c +@@ -422,7 +422,7 @@ err_put: + + static int pata_at91_remove(struct platform_device *pdev) + { +- struct ata_host *host = dev_get_drvdata(&pdev->dev); ++ struct ata_host *host = platform_get_drvdata(pdev); + struct at91_ide_info *info; + + if (!host) +diff --git a/drivers/ata/pata_bf54x.c b/drivers/ata/pata_bf54x.c +index 8d43510c..ba0d8a29 100644 +--- a/drivers/ata/pata_bf54x.c ++++ b/drivers/ata/pata_bf54x.c +@@ -1596,7 +1596,7 @@ static int bfin_atapi_probe(struct platform_device *pdev) + return -ENODEV; + } + +- dev_set_drvdata(&pdev->dev, host); ++ platform_set_drvdata(pdev, host); + + return 0; + } +@@ -1610,11 +1610,9 @@ static int bfin_atapi_probe(struct platform_device *pdev) + */ + static int bfin_atapi_remove(struct platform_device *pdev) + { +- struct device *dev = &pdev->dev; +- struct ata_host *host = dev_get_drvdata(dev); ++ struct ata_host *host = platform_get_drvdata(pdev); + + ata_host_detach(host); +- dev_set_drvdata(&pdev->dev, NULL); + + peripheral_free_list(atapi_io_port); + +@@ -1624,7 +1622,7 @@ static int bfin_atapi_remove(struct platform_device *pdev) + #ifdef CONFIG_PM + static int bfin_atapi_suspend(struct platform_device *pdev, pm_message_t state) + { +- struct ata_host *host = dev_get_drvdata(&pdev->dev); ++ struct ata_host *host = platform_get_drvdata(pdev); + if (host) + return ata_host_suspend(host, state); + else +@@ -1633,7 +1631,7 @@ static int bfin_atapi_suspend(struct platform_device *pdev, pm_message_t state) + + static int bfin_atapi_resume(struct platform_device *pdev) + { +- struct ata_host *host = dev_get_drvdata(&pdev->dev); ++ struct ata_host *host = platform_get_drvdata(pdev); + int ret; + + if (host) { +diff --git a/drivers/ata/pata_imx.c b/drivers/ata/pata_imx.c +index aa3d166e..4ec7c04b 100644 +--- a/drivers/ata/pata_imx.c ++++ b/drivers/ata/pata_imx.c +@@ -177,7 +177,7 @@ err: + + static int pata_imx_remove(struct platform_device *pdev) + { +- struct ata_host *host = dev_get_drvdata(&pdev->dev); ++ struct ata_host *host = platform_get_drvdata(pdev); + struct pata_imx_priv *priv = host->private_data; + + ata_host_detach(host); +diff --git a/drivers/ata/pata_mpc52xx.c b/drivers/ata/pata_mpc52xx.c +index 3a8fb28b..0024ced3 100644 +--- a/drivers/ata/pata_mpc52xx.c ++++ b/drivers/ata/pata_mpc52xx.c +@@ -825,7 +825,7 @@ mpc52xx_ata_remove(struct platform_device *op) + static int + mpc52xx_ata_suspend(struct platform_device *op, pm_message_t state) + { +- struct ata_host *host = dev_get_drvdata(&op->dev); ++ struct ata_host *host = platform_get_drvdata(op); + + return ata_host_suspend(host, state); + } +@@ -833,7 +833,7 @@ mpc52xx_ata_suspend(struct platform_device *op, pm_message_t state) + static int + mpc52xx_ata_resume(struct platform_device *op) + { +- struct ata_host *host = dev_get_drvdata(&op->dev); ++ struct ata_host *host = platform_get_drvdata(op); + struct mpc52xx_ata_priv *priv = host->private_data; + int rv; + +diff --git a/drivers/ata/pata_pxa.c b/drivers/ata/pata_pxa.c +index b0ac9e0c..942ef94b 100644 +--- a/drivers/ata/pata_pxa.c ++++ b/drivers/ata/pata_pxa.c +@@ -371,7 +371,7 @@ static int pxa_ata_probe(struct platform_device *pdev) + + static int pxa_ata_remove(struct platform_device *pdev) + { +- struct ata_host *host = dev_get_drvdata(&pdev->dev); ++ struct ata_host *host = platform_get_drvdata(pdev); + struct pata_pxa_data *data = host->ports[0]->private_data; + + pxa_free_dma(data->dma_channel); +diff --git a/drivers/ata/sata_fsl.c b/drivers/ata/sata_fsl.c +index 8401061b..851bd3f4 100644 +--- a/drivers/ata/sata_fsl.c ++++ b/drivers/ata/sata_fsl.c +@@ -1533,7 +1533,7 @@ static int sata_fsl_probe(struct platform_device *ofdev) + ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG, + &sata_fsl_sht); + +- dev_set_drvdata(&ofdev->dev, host); ++ platform_set_drvdata(ofdev, host); + + host_priv->intr_coalescing.show = fsl_sata_intr_coalescing_show; + host_priv->intr_coalescing.store = fsl_sata_intr_coalescing_store; +@@ -1559,10 +1559,8 @@ static int sata_fsl_probe(struct platform_device *ofdev) + + error_exit_with_cleanup: + +- if (host) { +- dev_set_drvdata(&ofdev->dev, NULL); ++ if (host) + ata_host_detach(host); +- } + + if (hcr_base) + iounmap(hcr_base); +@@ -1573,7 +1571,7 @@ error_exit_with_cleanup: + + static int sata_fsl_remove(struct platform_device *ofdev) + { +- struct ata_host *host = dev_get_drvdata(&ofdev->dev); ++ struct ata_host *host = platform_get_drvdata(ofdev); + struct sata_fsl_host_priv *host_priv = host->private_data; + + device_remove_file(&ofdev->dev, &host_priv->intr_coalescing); +@@ -1581,8 +1579,6 @@ static int sata_fsl_remove(struct platform_device *ofdev) + + ata_host_detach(host); + +- dev_set_drvdata(&ofdev->dev, NULL); +- + irq_dispose_mapping(host_priv->irq); + iounmap(host_priv->hcr_base); + kfree(host_priv); +@@ -1593,13 +1589,13 @@ static int sata_fsl_remove(struct platform_device *ofdev) + #ifdef CONFIG_PM + static int sata_fsl_suspend(struct platform_device *op, pm_message_t state) + { +- struct ata_host *host = dev_get_drvdata(&op->dev); ++ struct ata_host *host = platform_get_drvdata(op); + return ata_host_suspend(host, state); + } + + static int sata_fsl_resume(struct platform_device *op) + { +- struct ata_host *host = dev_get_drvdata(&op->dev); ++ struct ata_host *host = platform_get_drvdata(op); + struct sata_fsl_host_priv *host_priv = host->private_data; + int ret; + void __iomem *hcr_base = host_priv->hcr_base; +diff --git a/drivers/ata/sata_rcar.c b/drivers/ata/sata_rcar.c +index 249c8a28..829446af 100644 +--- a/drivers/ata/sata_rcar.c ++++ b/drivers/ata/sata_rcar.c +@@ -825,7 +825,7 @@ cleanup: + + static int sata_rcar_remove(struct platform_device *pdev) + { +- struct ata_host *host = dev_get_drvdata(&pdev->dev); ++ struct ata_host *host = platform_get_drvdata(pdev); + struct sata_rcar_priv *priv = host->private_data; + + ata_host_detach(host); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0005-sata_rcar-kill-superfluous-code-in-sata_rcar_bmdma_f.patch b/patches.renesas/0005-sata_rcar-kill-superfluous-code-in-sata_rcar_bmdma_f.patch new file mode 100644 index 00000000000..97f5616debb --- /dev/null +++ b/patches.renesas/0005-sata_rcar-kill-superfluous-code-in-sata_rcar_bmdma_f.patch @@ -0,0 +1,73 @@ +From 931a00339a6f0b0cdf5c539d5906b7e0064d7240 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Tue, 28 May 2013 02:43:23 +0400 +Subject: sata_rcar: kill superfluous code in sata_rcar_bmdma_fill_sg() + +I've modified sata_rcar_bmdma_fill_sg() to take care of splitting long +scatter/ gather segments due to the descriptor table transfer counter +being only 28 bits wide (bit 1 to bit 28) but that was in vain as even +if 'sata_rcar_sht' specified a correct 'dma_boundary' field, the DMA +and block layers would have split the S/G segments on the necassary +boundaries. Since the driver uses ATA_BMDMA_SHT() to initilaize +'sata_rcar_sht', the boundary is much smaller, only 0xFFFF, so the +code I've added is even more useless, and it's better to just remove +it. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: Tejun Heo <tj@kernel.org> +(cherry picked from commit 333279c82b984f3eac61feff2b76a8b79e3db6c8) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/ata/sata_rcar.c | 24 ++++++------------------ + 1 file changed, 6 insertions(+), 18 deletions(-) + +diff --git a/drivers/ata/sata_rcar.c b/drivers/ata/sata_rcar.c +index 829446af..d39330f6 100644 +--- a/drivers/ata/sata_rcar.c ++++ b/drivers/ata/sata_rcar.c +@@ -474,11 +474,10 @@ static void sata_rcar_bmdma_fill_sg(struct ata_queued_cmd *qc) + struct ata_port *ap = qc->ap; + struct ata_bmdma_prd *prd = ap->bmdma_prd; + struct scatterlist *sg; +- unsigned int si, pi; ++ unsigned int si; + +- pi = 0; + for_each_sg(qc->sg, sg, qc->n_elem, si) { +- u32 addr, sg_len, len; ++ u32 addr, sg_len; + + /* + * Note: h/w doesn't support 64-bit, so we unconditionally +@@ -487,24 +486,13 @@ static void sata_rcar_bmdma_fill_sg(struct ata_queued_cmd *qc) + addr = (u32)sg_dma_address(sg); + sg_len = sg_dma_len(sg); + +- /* H/w transfer count is only 29 bits long, let's be careful */ +- while (sg_len) { +- len = sg_len; +- if (len > 0x1ffffffe) +- len = 0x1ffffffe; +- +- prd[pi].addr = cpu_to_le32(addr); +- prd[pi].flags_len = cpu_to_le32(len); +- VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len); +- +- pi++; +- sg_len -= len; +- addr += len; +- } ++ prd[si].addr = cpu_to_le32(addr); ++ prd[si].flags_len = cpu_to_le32(sg_len); ++ VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", si, addr, sg_len); + } + + /* end-of-table flag */ +- prd[pi - 1].addr |= cpu_to_le32(SATA_RCAR_DTEND); ++ prd[si - 1].addr |= cpu_to_le32(SATA_RCAR_DTEND); + } + + static void sata_rcar_qc_prep(struct ata_queued_cmd *qc) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0006-sata_rcar-correct-sata_rcar_sht.patch b/patches.renesas/0006-sata_rcar-correct-sata_rcar_sht.patch new file mode 100644 index 00000000000..8214b8e615f --- /dev/null +++ b/patches.renesas/0006-sata_rcar-correct-sata_rcar_sht.patch @@ -0,0 +1,52 @@ +From 1511e50716794cefe67e43635e5c27ad6329311d Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Tue, 28 May 2013 02:45:08 +0400 +Subject: sata_rcar: correct 'sata_rcar_sht' + +Using ATA_BMDMA_SHT() to intialize 'sata_rcar_sht' was suboptimal as +the R-Car descriptor table transfer counter is 28 bits wide (bit 1 to +bit 28), so that the 'dma_boundary' field of 0xFFFF is just too small, +as well as the 'sg_tablesize' field of 128. Use ATA_BASE_SHT() to +initialize 'sata_rcar_sht' instead and give proper values to the +'dma_boundary' and 'sg_tablesize' fields explicitly. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: Tejun Heo <tj@kernel.org> +(cherry picked from commit 8bfbeed58665dbbf63813017712bd0c8e978379e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/ata/sata_rcar.c | 11 ++++++++++- + 1 file changed, 10 insertions(+), 1 deletion(-) + +diff --git a/drivers/ata/sata_rcar.c b/drivers/ata/sata_rcar.c +index d39330f6..6626a5bc 100644 +--- a/drivers/ata/sata_rcar.c ++++ b/drivers/ata/sata_rcar.c +@@ -121,6 +121,8 @@ + /* Descriptor table word 0 bit (when DTA32M = 1) */ + #define SATA_RCAR_DTEND BIT(0) + ++#define SATA_RCAR_DMA_BOUNDARY 0x1FFFFFFEUL ++ + struct sata_rcar_priv { + void __iomem *base; + struct clk *clk; +@@ -576,7 +578,14 @@ static u8 sata_rcar_bmdma_status(struct ata_port *ap) + } + + static struct scsi_host_template sata_rcar_sht = { +- ATA_BMDMA_SHT(DRV_NAME), ++ ATA_BASE_SHT(DRV_NAME), ++ /* ++ * This controller allows transfer chunks up to 512MB which cross 64KB ++ * boundaries, therefore the DMA limits are more relaxed than standard ++ * ATA SFF. ++ */ ++ .sg_tablesize = ATA_MAX_PRD, ++ .dma_boundary = SATA_RCAR_DMA_BOUNDARY, + }; + + static struct ata_port_operations sata_rcar_port_ops = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0007-sata_rcar-add-base-local-variable-to-some-functions.patch b/patches.renesas/0007-sata_rcar-add-base-local-variable-to-some-functions.patch new file mode 100644 index 00000000000..d1dc43330db --- /dev/null +++ b/patches.renesas/0007-sata_rcar-add-base-local-variable-to-some-functions.patch @@ -0,0 +1,322 @@ +From 6d9c0509b381c8bae9c90fae732850dff45d1cf1 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Tue, 28 May 2013 02:46:41 +0400 +Subject: sata_rcar: add 'base' local variable to some functions + +The 'base' field of 'struct sata_rcar_priv' is used very often +throughout the driver, so it seems worth loading it into a local +variable if it's used more than once in a function. + +While at it, put some unitialized variables after intialized ones for +aesthetic reasons. :-) + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: Tejun Heo <tj@kernel.org> +(cherry picked from commit 1b20f6a9adaa4b88d520d279c3d605f65b898625) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + drivers/ata/sata_rcar.c +--- + drivers/ata/sata_rcar.c | 101 +++++++++++++++++++++++++++--------------------- + 1 file changed, 57 insertions(+), 44 deletions(-) + +diff --git a/drivers/ata/sata_rcar.c b/drivers/ata/sata_rcar.c +index 6626a5bc..b1dd5d82 100644 +--- a/drivers/ata/sata_rcar.c ++++ b/drivers/ata/sata_rcar.c +@@ -130,41 +130,44 @@ struct sata_rcar_priv { + + static void sata_rcar_phy_initialize(struct sata_rcar_priv *priv) + { ++ void __iomem *base = priv->base; ++ + /* idle state */ +- iowrite32(0, priv->base + SATAPHYADDR_REG); ++ iowrite32(0, base + SATAPHYADDR_REG); + /* reset */ +- iowrite32(SATAPHYRESET_PHYRST, priv->base + SATAPHYRESET_REG); ++ iowrite32(SATAPHYRESET_PHYRST, base + SATAPHYRESET_REG); + udelay(10); + /* deassert reset */ +- iowrite32(0, priv->base + SATAPHYRESET_REG); ++ iowrite32(0, base + SATAPHYRESET_REG); + } + + static void sata_rcar_phy_write(struct sata_rcar_priv *priv, u16 reg, u32 val, + int group) + { ++ void __iomem *base = priv->base; + int timeout; + + /* deassert reset */ +- iowrite32(0, priv->base + SATAPHYRESET_REG); ++ iowrite32(0, base + SATAPHYRESET_REG); + /* lane 1 */ +- iowrite32(SATAPHYACCEN_PHYLANE, priv->base + SATAPHYACCEN_REG); ++ iowrite32(SATAPHYACCEN_PHYLANE, base + SATAPHYACCEN_REG); + /* write phy register value */ +- iowrite32(val, priv->base + SATAPHYWDATA_REG); ++ iowrite32(val, base + SATAPHYWDATA_REG); + /* set register group */ + if (group) + reg |= SATAPHYADDR_PHYRATEMODE; + /* write command */ +- iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, priv->base + SATAPHYADDR_REG); ++ iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, base + SATAPHYADDR_REG); + /* wait for ack */ + for (timeout = 0; timeout < 100; timeout++) { +- val = ioread32(priv->base + SATAPHYACK_REG); ++ val = ioread32(base + SATAPHYACK_REG); + if (val & SATAPHYACK_PHYACK) + break; + } + if (timeout >= 100) + pr_err("%s timeout\n", __func__); + /* idle state */ +- iowrite32(0, priv->base + SATAPHYADDR_REG); ++ iowrite32(0, base + SATAPHYADDR_REG); + } + + static void sata_rcar_freeze(struct ata_port *ap) +@@ -180,14 +183,15 @@ static void sata_rcar_freeze(struct ata_port *ap) + static void sata_rcar_thaw(struct ata_port *ap) + { + struct sata_rcar_priv *priv = ap->host->private_data; ++ void __iomem *base = priv->base; + + /* ack */ +- iowrite32(~SATA_RCAR_INT_MASK, priv->base + SATAINTSTAT_REG); ++ iowrite32(~SATA_RCAR_INT_MASK, base + SATAINTSTAT_REG); + + ata_sff_thaw(ap); + + /* unmask */ +- iowrite32(0x7ff & ~SATA_RCAR_INT_MASK, priv->base + SATAINTMASK_REG); ++ iowrite32(0x7ff & ~SATA_RCAR_INT_MASK, base + SATAINTMASK_REG); + } + + static void sata_rcar_ioread16_rep(void __iomem *reg, void *buffer, int count) +@@ -509,15 +513,16 @@ static void sata_rcar_bmdma_setup(struct ata_queued_cmd *qc) + { + struct ata_port *ap = qc->ap; + unsigned int rw = qc->tf.flags & ATA_TFLAG_WRITE; +- u32 dmactl; + struct sata_rcar_priv *priv = ap->host->private_data; ++ void __iomem *base = priv->base; ++ u32 dmactl; + + /* load PRD table addr. */ + mb(); /* make sure PRD table writes are visible to controller */ +- iowrite32(ap->bmdma_prd_dma, priv->base + ATAPI_DTB_ADR_REG); ++ iowrite32(ap->bmdma_prd_dma, base + ATAPI_DTB_ADR_REG); + + /* specify data direction, triple-check start bit is clear */ +- dmactl = ioread32(priv->base + ATAPI_CONTROL1_REG); ++ dmactl = ioread32(base + ATAPI_CONTROL1_REG); + dmactl &= ~(ATAPI_CONTROL1_RW | ATAPI_CONTROL1_STOP); + if (dmactl & ATAPI_CONTROL1_START) { + dmactl &= ~ATAPI_CONTROL1_START; +@@ -525,7 +530,7 @@ static void sata_rcar_bmdma_setup(struct ata_queued_cmd *qc) + } + if (!rw) + dmactl |= ATAPI_CONTROL1_RW; +- iowrite32(dmactl, priv->base + ATAPI_CONTROL1_REG); ++ iowrite32(dmactl, base + ATAPI_CONTROL1_REG); + + /* issue r/w command */ + ap->ops->sff_exec_command(ap, &qc->tf); +@@ -534,28 +539,30 @@ static void sata_rcar_bmdma_setup(struct ata_queued_cmd *qc) + static void sata_rcar_bmdma_start(struct ata_queued_cmd *qc) + { + struct ata_port *ap = qc->ap; +- u32 dmactl; + struct sata_rcar_priv *priv = ap->host->private_data; ++ void __iomem *base = priv->base; ++ u32 dmactl; + + /* start host DMA transaction */ +- dmactl = ioread32(priv->base + ATAPI_CONTROL1_REG); ++ dmactl = ioread32(base + ATAPI_CONTROL1_REG); + dmactl &= ~ATAPI_CONTROL1_STOP; + dmactl |= ATAPI_CONTROL1_START; +- iowrite32(dmactl, priv->base + ATAPI_CONTROL1_REG); ++ iowrite32(dmactl, base + ATAPI_CONTROL1_REG); + } + + static void sata_rcar_bmdma_stop(struct ata_queued_cmd *qc) + { + struct ata_port *ap = qc->ap; + struct sata_rcar_priv *priv = ap->host->private_data; ++ void __iomem *base = priv->base; + u32 dmactl; + + /* force termination of DMA transfer if active */ +- dmactl = ioread32(priv->base + ATAPI_CONTROL1_REG); ++ dmactl = ioread32(base + ATAPI_CONTROL1_REG); + if (dmactl & ATAPI_CONTROL1_START) { + dmactl &= ~ATAPI_CONTROL1_START; + dmactl |= ATAPI_CONTROL1_STOP; +- iowrite32(dmactl, priv->base + ATAPI_CONTROL1_REG); ++ iowrite32(dmactl, base + ATAPI_CONTROL1_REG); + } + + /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ +@@ -565,8 +572,8 @@ static void sata_rcar_bmdma_stop(struct ata_queued_cmd *qc) + static u8 sata_rcar_bmdma_status(struct ata_port *ap) + { + struct sata_rcar_priv *priv = ap->host->private_data; +- u32 status; + u8 host_stat = 0; ++ u32 status; + + status = ioread32(priv->base + ATAPI_STATUS_REG); + if (status & ATAPI_STATUS_DEVINT) +@@ -665,19 +672,20 @@ static irqreturn_t sata_rcar_interrupt(int irq, void *dev_instance) + { + struct ata_host *host = dev_instance; + struct sata_rcar_priv *priv = host->private_data; +- struct ata_port *ap; ++ void __iomem *base = priv->base; + unsigned int handled = 0; ++ struct ata_port *ap; + u32 sataintstat; + unsigned long flags; + + spin_lock_irqsave(&host->lock, flags); + +- sataintstat = ioread32(priv->base + SATAINTSTAT_REG); ++ sataintstat = ioread32(base + SATAINTSTAT_REG); + sataintstat &= SATA_RCAR_INT_MASK; + if (!sataintstat) + goto done; + /* ack */ +- iowrite32(~sataintstat & 0x7ff, priv->base + SATAINTSTAT_REG); ++ iowrite32(~sataintstat & 0x7ff, base + SATAINTSTAT_REG); + + ap = host->ports[0]; + +@@ -699,15 +707,16 @@ static void sata_rcar_setup_port(struct ata_host *host) + struct ata_port *ap = host->ports[0]; + struct ata_ioports *ioaddr = &ap->ioaddr; + struct sata_rcar_priv *priv = host->private_data; ++ void __iomem *base = priv->base; + + ap->ops = &sata_rcar_port_ops; + ap->pio_mask = ATA_PIO4; + ap->udma_mask = ATA_UDMA6; + ap->flags |= ATA_FLAG_SATA; + +- ioaddr->cmd_addr = priv->base + SDATA_REG; +- ioaddr->ctl_addr = priv->base + SSDEVCON_REG; +- ioaddr->scr_addr = priv->base + SCRSSTS_REG; ++ ioaddr->cmd_addr = base + SDATA_REG; ++ ioaddr->ctl_addr = base + SSDEVCON_REG; ++ ioaddr->scr_addr = base + SCRSSTS_REG; + ioaddr->altstatus_addr = ioaddr->ctl_addr; + + ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << 2); +@@ -725,6 +734,7 @@ static void sata_rcar_setup_port(struct ata_host *host) + static void sata_rcar_init_controller(struct ata_host *host) + { + struct sata_rcar_priv *priv = host->private_data; ++ void __iomem *base = priv->base; + u32 val; + + /* reset and setup phy */ +@@ -737,27 +747,27 @@ static void sata_rcar_init_controller(struct ata_host *host) + sata_rcar_phy_write(priv, SATAPCTLR4_REG, 0x28E80000, 0); + + /* SATA-IP reset state */ +- val = ioread32(priv->base + ATAPI_CONTROL1_REG); ++ val = ioread32(base + ATAPI_CONTROL1_REG); + val |= ATAPI_CONTROL1_RESET; +- iowrite32(val, priv->base + ATAPI_CONTROL1_REG); ++ iowrite32(val, base + ATAPI_CONTROL1_REG); + + /* ISM mode, PRD mode, DTEND flag at bit 0 */ +- val = ioread32(priv->base + ATAPI_CONTROL1_REG); ++ val = ioread32(base + ATAPI_CONTROL1_REG); + val |= ATAPI_CONTROL1_ISM; + val |= ATAPI_CONTROL1_DESE; + val |= ATAPI_CONTROL1_DTA32M; +- iowrite32(val, priv->base + ATAPI_CONTROL1_REG); ++ iowrite32(val, base + ATAPI_CONTROL1_REG); + + /* Release the SATA-IP from the reset state */ +- val = ioread32(priv->base + ATAPI_CONTROL1_REG); ++ val = ioread32(base + ATAPI_CONTROL1_REG); + val &= ~ATAPI_CONTROL1_RESET; +- iowrite32(val, priv->base + ATAPI_CONTROL1_REG); ++ iowrite32(val, base + ATAPI_CONTROL1_REG); + + /* ack and mask */ +- iowrite32(0, priv->base + SATAINTSTAT_REG); +- iowrite32(0x7ff, priv->base + SATAINTMASK_REG); ++ iowrite32(0, base + SATAINTSTAT_REG); ++ iowrite32(0x7ff, base + SATAINTMASK_REG); + /* enable interrupts */ +- iowrite32(ATAPI_INT_ENABLE_SATAINT, priv->base + ATAPI_INT_ENABLE_REG); ++ iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG); + } + + static int sata_rcar_probe(struct platform_device *pdev) +@@ -824,14 +834,15 @@ static int sata_rcar_remove(struct platform_device *pdev) + { + struct ata_host *host = platform_get_drvdata(pdev); + struct sata_rcar_priv *priv = host->private_data; ++ void __iomem *base = priv->base; + + ata_host_detach(host); + + /* disable interrupts */ +- iowrite32(0, priv->base + ATAPI_INT_ENABLE_REG); ++ iowrite32(0, base + ATAPI_INT_ENABLE_REG); + /* ack and mask */ +- iowrite32(0, priv->base + SATAINTSTAT_REG); +- iowrite32(0x7ff, priv->base + SATAINTMASK_REG); ++ iowrite32(0, base + SATAINTSTAT_REG); ++ iowrite32(0x7ff, base + SATAINTMASK_REG); + + clk_disable(priv->clk); + +@@ -843,14 +854,15 @@ static int sata_rcar_suspend(struct device *dev) + { + struct ata_host *host = dev_get_drvdata(dev); + struct sata_rcar_priv *priv = host->private_data; ++ void __iomem *base = priv->base; + int ret; + + ret = ata_host_suspend(host, PMSG_SUSPEND); + if (!ret) { + /* disable interrupts */ +- iowrite32(0, priv->base + ATAPI_INT_ENABLE_REG); ++ iowrite32(0, base + ATAPI_INT_ENABLE_REG); + /* mask */ +- iowrite32(0x7ff, priv->base + SATAINTMASK_REG); ++ iowrite32(0x7ff, base + SATAINTMASK_REG); + + clk_disable(priv->clk); + } +@@ -862,14 +874,15 @@ static int sata_rcar_resume(struct device *dev) + { + struct ata_host *host = dev_get_drvdata(dev); + struct sata_rcar_priv *priv = host->private_data; ++ void __iomem *base = priv->base; + + clk_enable(priv->clk); + + /* ack and mask */ +- iowrite32(0, priv->base + SATAINTSTAT_REG); +- iowrite32(0x7ff, priv->base + SATAINTMASK_REG); ++ iowrite32(0, base + SATAINTSTAT_REG); ++ iowrite32(0x7ff, base + SATAINTMASK_REG); + /* enable interrupts */ +- iowrite32(ATAPI_INT_ENABLE_SATAINT, priv->base + ATAPI_INT_ENABLE_REG); ++ iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG); + + ata_host_resume(host); + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0008-sata_rcar-fix-compilation-warning-in-sata_rcar_thaw.patch b/patches.renesas/0008-sata_rcar-fix-compilation-warning-in-sata_rcar_thaw.patch new file mode 100644 index 00000000000..6884d593f85 --- /dev/null +++ b/patches.renesas/0008-sata_rcar-fix-compilation-warning-in-sata_rcar_thaw.patch @@ -0,0 +1,39 @@ +From 731282ac0516fea7a9db38cda3a0a2dd7bd491a8 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Mon, 3 Jun 2013 13:16:05 -0700 +Subject: sata_rcar: fix compilation warning in sata_rcar_thaw() + +When compiling the driver with gcc 4.8, it gives the following warning: + + drivers/ata/sata_rcar.c: In function `sata_rcar_thaw': + drivers/ata/sata_rcar.c:183:2: warning: large integer implicitly truncated to unsigned type [-Woverflow] + +Fix the warning by explicit cast of the 'unsigned long' value to 'u32'. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: Tejun Heo <tj@kernel.org> +(cherry picked from commit 5ba59b59cb413b9d89f40532bad3529d5185dd3c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + drivers/ata/sata_rcar.c +--- + drivers/ata/sata_rcar.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/ata/sata_rcar.c b/drivers/ata/sata_rcar.c +index b1dd5d82..8108eb06 100644 +--- a/drivers/ata/sata_rcar.c ++++ b/drivers/ata/sata_rcar.c +@@ -186,7 +186,7 @@ static void sata_rcar_thaw(struct ata_port *ap) + void __iomem *base = priv->base; + + /* ack */ +- iowrite32(~SATA_RCAR_INT_MASK, base + SATAINTSTAT_REG); ++ iowrite32(~(u32)SATA_RCAR_INT_MASK, base + SATAINTSTAT_REG); + + ata_sff_thaw(ap); + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0009-drivers-ata-sata_rcar.c-simplify-use-of-devm_ioremap.patch b/patches.renesas/0009-drivers-ata-sata_rcar.c-simplify-use-of-devm_ioremap.patch new file mode 100644 index 00000000000..29079053bf2 --- /dev/null +++ b/patches.renesas/0009-drivers-ata-sata_rcar.c-simplify-use-of-devm_ioremap.patch @@ -0,0 +1,63 @@ +From 7ebdc8dd825f565e287fd37a115dba44ec8c34db Mon Sep 17 00:00:00 2001 +From: Julia Lawall <Julia.Lawall@lip6.fr> +Date: Wed, 14 Aug 2013 11:11:31 +0200 +Subject: drivers/ata/sata_rcar.c: simplify use of devm_ioremap_resource + +Remove unneeded error handling on the result of a call to +platform_get_resource when the value is passed to devm_ioremap_resource. + +Move the call to platform_get_resource adjacent to the call to +devm_ioremap_resource to make the connection between them more clear. + +A simplified version of the semantic patch that makes this change is as +follows: (http://coccinelle.lip6.fr/) + +// <smpl> +@@ +expression pdev,res,n,e,e1; +expression ret != 0; +identifier l; +@@ + +- res = platform_get_resource(pdev, IORESOURCE_MEM, n); + ... when != res +- if (res == NULL) { ... \(goto l;\|return ret;\) } + ... when != res ++ res = platform_get_resource(pdev, IORESOURCE_MEM, n); + e = devm_ioremap_resource(e1, res); +// </smpl> + +Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> +Signed-off-by: Tejun Heo <tj@kernel.org> +(cherry picked from commit 4a9b7f9f2704405c05b213f8f51e9f7f1fe02d1a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/ata/sata_rcar.c | 5 +---- + 1 file changed, 1 insertion(+), 4 deletions(-) + +diff --git a/drivers/ata/sata_rcar.c b/drivers/ata/sata_rcar.c +index 8108eb06..c2d95e9f 100644 +--- a/drivers/ata/sata_rcar.c ++++ b/drivers/ata/sata_rcar.c +@@ -778,10 +778,6 @@ static int sata_rcar_probe(struct platform_device *pdev) + int irq; + int ret = 0; + +- mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- if (mem == NULL) +- return -EINVAL; +- + irq = platform_get_irq(pdev, 0); + if (irq <= 0) + return -EINVAL; +@@ -807,6 +803,7 @@ static int sata_rcar_probe(struct platform_device *pdev) + + host->private_data = priv; + ++ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->base = devm_ioremap_resource(&pdev->dev, mem); + if (IS_ERR(priv->base)) { + ret = PTR_ERR(priv->base); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0010-drivers-irq-chip-irq-gic-introduce-gic_cpu_if_down.patch b/patches.renesas/0010-drivers-irq-chip-irq-gic-introduce-gic_cpu_if_down.patch new file mode 100644 index 00000000000..83128427f20 --- /dev/null +++ b/patches.renesas/0010-drivers-irq-chip-irq-gic-introduce-gic_cpu_if_down.patch @@ -0,0 +1,67 @@ +From 2fb0420dd6b871c2e1c7d7cf19098a8dc1bb8c5b Mon Sep 17 00:00:00 2001 +From: Nicolas Pitre <nicolas.pitre@linaro.org> +Date: Tue, 19 Mar 2013 23:59:04 -0400 +Subject: drivers: irq-chip: irq-gic: introduce gic_cpu_if_down() + +When processors are about to hit low power states, the assertion of +standbywfi signal, triggered by the wfi instruction, is essential to +entering low power modes. If an IRQ is pending on the processor at the +time wfi is issued, the wfi instruction completes and the processor +restarts execution without asserting the standbywfi signal. Depending +on the platform power controller HW this behaviour can be acceptable or +not; if this behaviour must be prevented software should be provided +with a way to disable the routing of interrupts to the core IRQ pins. + +On systems where raw GIC distributor interrupts are connected to the power +controller as wake-up events (hence the power controller still senses +IRQs and can wake up cores upon IRQ pending), the GIC CPU interface can +be disabled on power down, so that the GIC CPU IF output is gated and wfi +cannot complete, thereby preventing the standbywfi issue. + +This patch adds a simple function to the GIC driver that allows to +disable the GIC CPU IF from power down procedures. + +Signed-off-by: Nicolas Pitre <nico@linaro.org> +Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> +[rewrote commit log] + +Signed-off-by: Olof Johansson <olof@lixom.net> +(cherry picked from commit 10d9eb8a17cfb697967928bde06f3e7e530b03ac) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/irqchip/irq-gic.c | 6 ++++++ + include/linux/irqchip/arm-gic.h | 1 + + 2 files changed, 7 insertions(+) + +diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c +index 19ceaa60..fe44d3e2 100644 +--- a/drivers/irqchip/irq-gic.c ++++ b/drivers/irqchip/irq-gic.c +@@ -453,6 +453,12 @@ static void __cpuinit gic_cpu_init(struct gic_chip_data *gic) + writel_relaxed(1, base + GIC_CPU_CTRL); + } + ++void gic_cpu_if_down(void) ++{ ++ void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]); ++ writel_relaxed(0, cpu_base + GIC_CPU_CTRL); ++} ++ + #ifdef CONFIG_CPU_PM + /* + * Saves the GIC distributor registers during suspend or idle. Must be called +diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h +index 3e203eb2..0e5d9ecd 100644 +--- a/include/linux/irqchip/arm-gic.h ++++ b/include/linux/irqchip/arm-gic.h +@@ -66,6 +66,7 @@ extern struct irq_chip gic_arch_extn; + void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *, + u32 offset, struct device_node *); + void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); ++void gic_cpu_if_down(void); + + static inline void gic_init(unsigned int nr, int start, + void __iomem *dist , void __iomem *cpu) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0011-irqchip-renesas-intc-irqpin-DT-binding-for-sense-bit.patch b/patches.renesas/0011-irqchip-renesas-intc-irqpin-DT-binding-for-sense-bit.patch new file mode 100644 index 00000000000..d63187db5a2 --- /dev/null +++ b/patches.renesas/0011-irqchip-renesas-intc-irqpin-DT-binding-for-sense-bit.patch @@ -0,0 +1,65 @@ +From 0a1f2e30fccc5e556d0fd6e1db06fe62ca5f09b3 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Thu, 13 Jun 2013 11:23:38 +0200 +Subject: irqchip: renesas-intc-irqpin: DT binding for sense bitfield width + +Most Renesas irqpin controllers have 4-bit sense fields, however, some +have different widths. This patch adds a DT binding to optionally +specify such non-standard values. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Acked-by: Arnd Bergmann <arnd@arndb.de> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 894db164260c39870ea79e473e1307b4aa5e4257) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + .../bindings/interrupt-controller/renesas,intc-irqpin.txt | 14 ++++++++++++++ + drivers/irqchip/irq-renesas-intc-irqpin.c | 4 ++++ + 2 files changed, 18 insertions(+) + create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt + +diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt +new file mode 100644 +index 00000000..66fcaf5b +--- /dev/null ++++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt +@@ -0,0 +1,14 @@ ++DT bindings for the R-/SH-Mobile irqpin controller ++ ++Required properties: ++ ++- compatible: has to be "renesas,intc-irqpin" ++- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in ++ interrupts.txt in this directory ++ ++Optional properties: ++ ++- any properties, listed in interrupts.txt, and any standard resource allocation ++ properties ++- sense-bitfield-width: width of a single sense bitfield in the SENSE register, ++ if different from the default 4 bits +diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c +index 5a68e5ac..4aca1b2b 100644 +--- a/drivers/irqchip/irq-renesas-intc-irqpin.c ++++ b/drivers/irqchip/irq-renesas-intc-irqpin.c +@@ -18,6 +18,7 @@ + */ + + #include <linux/init.h> ++#include <linux/of.h> + #include <linux/platform_device.h> + #include <linux/spinlock.h> + #include <linux/interrupt.h> +@@ -349,6 +350,9 @@ static int intc_irqpin_probe(struct platform_device *pdev) + /* deal with driver instance configuration */ + if (pdata) + memcpy(&p->config, pdata, sizeof(*pdata)); ++ else ++ of_property_read_u32(pdev->dev.of_node, "sense-bitfield-width", ++ &p->config.sense_bitfield_width); + if (!p->config.sense_bitfield_width) + p->config.sense_bitfield_width = 4; /* default to 4 bits */ + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0012-ARM-shmobile-irqpin-add-a-DT-property-to-enable-mask.patch b/patches.renesas/0012-ARM-shmobile-irqpin-add-a-DT-property-to-enable-mask.patch new file mode 100644 index 00000000000..42ec72a14cf --- /dev/null +++ b/patches.renesas/0012-ARM-shmobile-irqpin-add-a-DT-property-to-enable-mask.patch @@ -0,0 +1,54 @@ +From 3422f9f5073e5bbd67b6e182af7a839dd9499d23 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Wed, 19 Jun 2013 07:53:09 +0200 +Subject: ARM: shmobile: irqpin: add a DT property to enable masking on parent + +To disable spurious interrupts, that get triggered on certain hardware, the +irqpin driver masks them on the parent interrupt controller. To specify +such broken devices a .control_parent parameter can be provided in the +platform data. In the DT case we need a property, to do the same. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Acked-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit c4fa4946f177ae214523586cd794ac18d34b1430) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + .../bindings/interrupt-controller/renesas,intc-irqpin.txt | 2 ++ + drivers/irqchip/irq-renesas-intc-irqpin.c | 7 +++++-- + 2 files changed, 7 insertions(+), 2 deletions(-) + +diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt +index 66fcaf5b..1f8b0c50 100644 +--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt ++++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt +@@ -12,3 +12,5 @@ Optional properties: + properties + - sense-bitfield-width: width of a single sense bitfield in the SENSE register, + if different from the default 4 bits ++- control-parent: disable and enable interrupts on the parent interrupt ++ controller, needed for some broken implementations +diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c +index 4aca1b2b..82cec63a 100644 +--- a/drivers/irqchip/irq-renesas-intc-irqpin.c ++++ b/drivers/irqchip/irq-renesas-intc-irqpin.c +@@ -348,11 +348,14 @@ static int intc_irqpin_probe(struct platform_device *pdev) + } + + /* deal with driver instance configuration */ +- if (pdata) ++ if (pdata) { + memcpy(&p->config, pdata, sizeof(*pdata)); +- else ++ } else { + of_property_read_u32(pdev->dev.of_node, "sense-bitfield-width", + &p->config.sense_bitfield_width); ++ p->config.control_parent = of_property_read_bool(pdev->dev.of_node, ++ "control-parent"); ++ } + if (!p->config.sense_bitfield_width) + p->config.sense_bitfield_width = 4; /* default to 4 bits */ + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0013-irqchip-renesas-irqc-Fix-irqc_probe-error-handling.patch b/patches.renesas/0013-irqchip-renesas-irqc-Fix-irqc_probe-error-handling.patch new file mode 100644 index 00000000000..8387580e617 --- /dev/null +++ b/patches.renesas/0013-irqchip-renesas-irqc-Fix-irqc_probe-error-handling.patch @@ -0,0 +1,34 @@ +From d6528543cfb62fbe699f0efe83907563f9bd5984 Mon Sep 17 00:00:00 2001 +From: Axel Lin <axel.lin@ingics.com> +Date: Mon, 6 May 2013 17:03:32 +0800 +Subject: irqchip: renesas-irqc: Fix irqc_probe error handling + +The code in goto err3 path is wrong because it will call fee_irq() with k == 0, +which means it does free_irq(p->irq[-1].requested_irq, &p->irq[-1]); + +Signed-off-by: Axel Lin <axel.lin@ingics.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit dfaf820a13ec160f06556e08dab423818ba87f14) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/irqchip/irq-renesas-irqc.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/irqchip/irq-renesas-irqc.c b/drivers/irqchip/irq-renesas-irqc.c +index 927bff37..2f404ba6 100644 +--- a/drivers/irqchip/irq-renesas-irqc.c ++++ b/drivers/irqchip/irq-renesas-irqc.c +@@ -248,8 +248,8 @@ static int irqc_probe(struct platform_device *pdev) + + return 0; + err3: +- for (; k >= 0; k--) +- free_irq(p->irq[k - 1].requested_irq, &p->irq[k - 1]); ++ while (--k >= 0) ++ free_irq(p->irq[k].requested_irq, &p->irq[k]); + + irq_domain_remove(p->irq_domain); + err2: +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0014-clocksource-arch_timer-use-virtual-counters.patch b/patches.renesas/0014-clocksource-arch_timer-use-virtual-counters.patch new file mode 100644 index 00000000000..733961ba8ae --- /dev/null +++ b/patches.renesas/0014-clocksource-arch_timer-use-virtual-counters.patch @@ -0,0 +1,150 @@ +From 5e0c108a4ec72c035491aad3e48971daa29886e0 Mon Sep 17 00:00:00 2001 +From: Mark Rutland <mark.rutland@arm.com> +Date: Wed, 30 Jan 2013 17:51:26 +0000 +Subject: clocksource: arch_timer: use virtual counters + +Switching between reading the virtual or physical counters is +problematic, as some core code wants a view of time before we're fully +set up. Using a function pointer and switching the source after the +first read can make time appear to go backwards, and having a check in +the read function is an unfortunate block on what we want to be a fast +path. + +Instead, this patch makes us always use the virtual counters. If we're a +guest, or don't have hyp mode, we'll use the virtual timers, and as such +don't care about CNTVOFF as long as it doesn't change in such a way as +to make time appear to travel backwards. As the guest will use the +virtual timers, a (potential) KVM host must use the physical timers +(which can wake up the host even if they fire while a guest is +executing), and hence a host must have CNTVOFF set to zero so as to have +a consistent view of time between the physical timers and virtual +counters. + +Signed-off-by: Mark Rutland <mark.rutland@arm.com> +Acked-by: Catalin Marinas <catalin.marinas@arm.com> +Acked-by: Marc Zyngier <marc.zyngier@arm.com> +Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> +Cc: Rob Herring <rob.herring@calxeda.com> +(cherry picked from commit 0d651e4e65e96989f72236bf83bd4c6e55eb6ce4) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/include/asm/arch_timer.h | 9 --------- + arch/arm64/include/asm/arch_timer.h | 10 ---------- + drivers/clocksource/arm_arch_timer.c | 23 +++++------------------ + include/clocksource/arm_arch_timer.h | 2 +- + 4 files changed, 6 insertions(+), 38 deletions(-) + +diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h +index 7c1bfc0a..accefe09 100644 +--- a/arch/arm/include/asm/arch_timer.h ++++ b/arch/arm/include/asm/arch_timer.h +@@ -80,15 +80,6 @@ static inline u32 arch_timer_get_cntfrq(void) + return val; + } + +-static inline u64 arch_counter_get_cntpct(void) +-{ +- u64 cval; +- +- isb(); +- asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval)); +- return cval; +-} +- + static inline u64 arch_counter_get_cntvct(void) + { + u64 cval; +diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h +index bf6ab242..d56ed11b 100644 +--- a/arch/arm64/include/asm/arch_timer.h ++++ b/arch/arm64/include/asm/arch_timer.h +@@ -110,16 +110,6 @@ static inline void __cpuinit arch_counter_set_user_access(void) + asm volatile("msr cntkctl_el1, %0" : : "r" (cntkctl)); + } + +-static inline u64 arch_counter_get_cntpct(void) +-{ +- u64 cval; +- +- isb(); +- asm volatile("mrs %0, cntpct_el0" : "=r" (cval)); +- +- return cval; +-} +- + static inline u64 arch_counter_get_cntvct(void) + { + u64 cval; +diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c +index a2b25418..053d846a 100644 +--- a/drivers/clocksource/arm_arch_timer.c ++++ b/drivers/clocksource/arm_arch_timer.c +@@ -186,27 +186,19 @@ u32 arch_timer_get_rate(void) + return arch_timer_rate; + } + +-/* +- * Some external users of arch_timer_read_counter (e.g. sched_clock) may try to +- * call it before it has been initialised. Rather than incur a performance +- * penalty checking for initialisation, provide a default implementation that +- * won't lead to time appearing to jump backwards. +- */ +-static u64 arch_timer_read_zero(void) ++u64 arch_timer_read_counter(void) + { +- return 0; ++ return arch_counter_get_cntvct(); + } + +-u64 (*arch_timer_read_counter)(void) = arch_timer_read_zero; +- + static cycle_t arch_counter_read(struct clocksource *cs) + { +- return arch_timer_read_counter(); ++ return arch_counter_get_cntvct(); + } + + static cycle_t arch_counter_read_cc(const struct cyclecounter *cc) + { +- return arch_timer_read_counter(); ++ return arch_counter_get_cntvct(); + } + + static struct clocksource clocksource_counter = { +@@ -287,7 +279,7 @@ static int __init arch_timer_register(void) + cyclecounter.mult = clocksource_counter.mult; + cyclecounter.shift = clocksource_counter.shift; + timecounter_init(&timecounter, &cyclecounter, +- arch_counter_get_cntpct()); ++ arch_counter_get_cntvct()); + + if (arch_timer_use_virtual) { + ppi = arch_timer_ppi[VIRT_PPI]; +@@ -376,11 +368,6 @@ static void __init arch_timer_init(struct device_node *np) + } + } + +- if (arch_timer_use_virtual) +- arch_timer_read_counter = arch_counter_get_cntvct; +- else +- arch_timer_read_counter = arch_counter_get_cntpct; +- + arch_timer_register(); + arch_timer_arch_init(); + } +diff --git a/include/clocksource/arm_arch_timer.h b/include/clocksource/arm_arch_timer.h +index e6c9c4cc..c463ce99 100644 +--- a/include/clocksource/arm_arch_timer.h ++++ b/include/clocksource/arm_arch_timer.h +@@ -32,7 +32,7 @@ + #ifdef CONFIG_ARM_ARCH_TIMER + + extern u32 arch_timer_get_rate(void); +-extern u64 (*arch_timer_read_counter)(void); ++extern u64 arch_timer_read_counter(void); + extern struct timecounter *arch_timer_get_timecounter(void); + + #else +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0015-clocksource-arch_timer-Make-register-accessors-less-.patch b/patches.renesas/0015-clocksource-arch_timer-Make-register-accessors-less-.patch new file mode 100644 index 00000000000..a0e203beb7c --- /dev/null +++ b/patches.renesas/0015-clocksource-arch_timer-Make-register-accessors-less-.patch @@ -0,0 +1,199 @@ +From fe2df0bfc0505cc146d76991f9e2370bd903238a Mon Sep 17 00:00:00 2001 +From: Stephen Boyd <sboyd@codeaurora.org> +Date: Thu, 18 Jul 2013 16:59:28 -0700 +Subject: clocksource: arch_timer: Make register accessors less error-prone + +Using an enum for the register we wish to access allows newer +compilers to determine if we've forgotten a case in our switch +statement. This allows us to remove the BUILD_BUG() instances in +the arm64 port, avoiding problems where optimizations may not +happen. + +To try and force better code generation we're currently marking +the accessor functions as inline, but newer compilers can ignore +the inline keyword unless it's marked __always_inline. Luckily on +arm and arm64 inline is __always_inline, but let's make +everything __always_inline to be explicit. + +Suggested-by: Thomas Gleixner <tglx@linutronix.de> +Cc: Thomas Gleixner <tglx@linutronix.de> +Cc: Mark Rutland <mark.rutland@arm.com> +Cc: Marc Zyngier <Marc.Zyngier@arm.com> +Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> +Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> +Acked-by: Mark Rutland <mark.rutland@arm.com> +(cherry picked from commit e09f3cc0184d6b5c3816f921b7ffb67623e5e834) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/include/asm/arch_timer.h | 14 ++++++-------- + arch/arm64/include/asm/arch_timer.h | 23 +++++++++-------------- + drivers/clocksource/arm_arch_timer.c | 6 +++--- + include/clocksource/arm_arch_timer.h | 6 ++++-- + 4 files changed, 22 insertions(+), 27 deletions(-) + +diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h +index accefe09..aeb93f38 100644 +--- a/arch/arm/include/asm/arch_timer.h ++++ b/arch/arm/include/asm/arch_timer.h +@@ -17,7 +17,8 @@ int arch_timer_arch_init(void); + * nicely work out which register we want, and chuck away the rest of + * the code. At least it does so with a recent GCC (4.6.3). + */ +-static inline void arch_timer_reg_write(const int access, const int reg, u32 val) ++static __always_inline ++void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val) + { + if (access == ARCH_TIMER_PHYS_ACCESS) { + switch (reg) { +@@ -28,9 +29,7 @@ static inline void arch_timer_reg_write(const int access, const int reg, u32 val + asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val)); + break; + } +- } +- +- if (access == ARCH_TIMER_VIRT_ACCESS) { ++ } else if (access == ARCH_TIMER_VIRT_ACCESS) { + switch (reg) { + case ARCH_TIMER_REG_CTRL: + asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val)); +@@ -44,7 +43,8 @@ static inline void arch_timer_reg_write(const int access, const int reg, u32 val + isb(); + } + +-static inline u32 arch_timer_reg_read(const int access, const int reg) ++static __always_inline ++u32 arch_timer_reg_read(int access, enum arch_timer_reg reg) + { + u32 val = 0; + +@@ -57,9 +57,7 @@ static inline u32 arch_timer_reg_read(const int access, const int reg) + asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val)); + break; + } +- } +- +- if (access == ARCH_TIMER_VIRT_ACCESS) { ++ } else if (access == ARCH_TIMER_VIRT_ACCESS) { + switch (reg) { + case ARCH_TIMER_REG_CTRL: + asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val)); +diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h +index d56ed11b..dbca7716 100644 +--- a/arch/arm64/include/asm/arch_timer.h ++++ b/arch/arm64/include/asm/arch_timer.h +@@ -26,7 +26,13 @@ + + #include <clocksource/arm_arch_timer.h> + +-static inline void arch_timer_reg_write(int access, int reg, u32 val) ++/* ++ * These register accessors are marked inline so the compiler can ++ * nicely work out which register we want, and chuck away the rest of ++ * the code. ++ */ ++static __always_inline ++void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val) + { + if (access == ARCH_TIMER_PHYS_ACCESS) { + switch (reg) { +@@ -36,8 +42,6 @@ static inline void arch_timer_reg_write(int access, int reg, u32 val) + case ARCH_TIMER_REG_TVAL: + asm volatile("msr cntp_tval_el0, %0" : : "r" (val)); + break; +- default: +- BUILD_BUG(); + } + } else if (access == ARCH_TIMER_VIRT_ACCESS) { + switch (reg) { +@@ -47,17 +51,14 @@ static inline void arch_timer_reg_write(int access, int reg, u32 val) + case ARCH_TIMER_REG_TVAL: + asm volatile("msr cntv_tval_el0, %0" : : "r" (val)); + break; +- default: +- BUILD_BUG(); + } +- } else { +- BUILD_BUG(); + } + + isb(); + } + +-static inline u32 arch_timer_reg_read(int access, int reg) ++static __always_inline ++u32 arch_timer_reg_read(int access, enum arch_timer_reg reg) + { + u32 val; + +@@ -69,8 +70,6 @@ static inline u32 arch_timer_reg_read(int access, int reg) + case ARCH_TIMER_REG_TVAL: + asm volatile("mrs %0, cntp_tval_el0" : "=r" (val)); + break; +- default: +- BUILD_BUG(); + } + } else if (access == ARCH_TIMER_VIRT_ACCESS) { + switch (reg) { +@@ -80,11 +79,7 @@ static inline u32 arch_timer_reg_read(int access, int reg) + case ARCH_TIMER_REG_TVAL: + asm volatile("mrs %0, cntv_tval_el0" : "=r" (val)); + break; +- default: +- BUILD_BUG(); + } +- } else { +- BUILD_BUG(); + } + + return val; +diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c +index 053d846a..aa070384 100644 +--- a/drivers/clocksource/arm_arch_timer.c ++++ b/drivers/clocksource/arm_arch_timer.c +@@ -43,7 +43,7 @@ static bool arch_timer_use_virtual = true; + * Architected system timer support. + */ + +-static inline irqreturn_t timer_handler(const int access, ++static __always_inline irqreturn_t timer_handler(const int access, + struct clock_event_device *evt) + { + unsigned long ctrl; +@@ -72,7 +72,7 @@ static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id) + return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt); + } + +-static inline void timer_set_mode(const int access, int mode) ++static __always_inline void timer_set_mode(const int access, int mode) + { + unsigned long ctrl; + switch (mode) { +@@ -99,7 +99,7 @@ static void arch_timer_set_mode_phys(enum clock_event_mode mode, + timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode); + } + +-static inline void set_next_event(const int access, unsigned long evt) ++static __always_inline void set_next_event(const int access, unsigned long evt) + { + unsigned long ctrl; + ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL); +diff --git a/include/clocksource/arm_arch_timer.h b/include/clocksource/arm_arch_timer.h +index c463ce99..f3da817b 100644 +--- a/include/clocksource/arm_arch_timer.h ++++ b/include/clocksource/arm_arch_timer.h +@@ -23,8 +23,10 @@ + #define ARCH_TIMER_CTRL_IT_MASK (1 << 1) + #define ARCH_TIMER_CTRL_IT_STAT (1 << 2) + +-#define ARCH_TIMER_REG_CTRL 0 +-#define ARCH_TIMER_REG_TVAL 1 ++enum arch_timer_reg { ++ ARCH_TIMER_REG_CTRL, ++ ARCH_TIMER_REG_TVAL, ++}; + + #define ARCH_TIMER_PHYS_ACCESS 0 + #define ARCH_TIMER_VIRT_ACCESS 1 +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0016-clocksource-arch_timer-Push-the-read-write-wrappers-.patch b/patches.renesas/0016-clocksource-arch_timer-Push-the-read-write-wrappers-.patch new file mode 100644 index 00000000000..478a3767bf9 --- /dev/null +++ b/patches.renesas/0016-clocksource-arch_timer-Push-the-read-write-wrappers-.patch @@ -0,0 +1,173 @@ +From fb73a1fc4cbef171ca21c6d66de5abd2a9624752 Mon Sep 17 00:00:00 2001 +From: Stephen Boyd <sboyd@codeaurora.org> +Date: Thu, 18 Jul 2013 16:59:31 -0700 +Subject: clocksource: arch_timer: Push the read/write wrappers deeper + +We're going to introduce support to read and write the memory +mapped timer registers in the next patch, so push the cp15 +read/write functions one level deeper. This simplifies the next +patch and makes it clearer what's going on. + +Cc: Mark Rutland <mark.rutland@arm.com> +Cc: Marc Zyngier <Marc.Zyngier@arm.com> +Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> +Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> +Acked-by: Mark Rutland <mark.rutland@arm.com> +(cherry picked from commit 60faddf6eb3aba16068032bdcf35e18ace4bfb21) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/include/asm/arch_timer.h | 4 ++-- + arch/arm64/include/asm/arch_timer.h | 4 ++-- + drivers/clocksource/arm_arch_timer.c | 46 ++++++++++++++++++++++++------------ + 3 files changed, 35 insertions(+), 19 deletions(-) + +diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h +index aeb93f38..55609468 100644 +--- a/arch/arm/include/asm/arch_timer.h ++++ b/arch/arm/include/asm/arch_timer.h +@@ -18,7 +18,7 @@ int arch_timer_arch_init(void); + * the code. At least it does so with a recent GCC (4.6.3). + */ + static __always_inline +-void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val) ++void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val) + { + if (access == ARCH_TIMER_PHYS_ACCESS) { + switch (reg) { +@@ -44,7 +44,7 @@ void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val) + } + + static __always_inline +-u32 arch_timer_reg_read(int access, enum arch_timer_reg reg) ++u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg) + { + u32 val = 0; + +diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h +index dbca7716..7181e777 100644 +--- a/arch/arm64/include/asm/arch_timer.h ++++ b/arch/arm64/include/asm/arch_timer.h +@@ -32,7 +32,7 @@ + * the code. + */ + static __always_inline +-void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val) ++void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val) + { + if (access == ARCH_TIMER_PHYS_ACCESS) { + switch (reg) { +@@ -58,7 +58,7 @@ void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val) + } + + static __always_inline +-u32 arch_timer_reg_read(int access, enum arch_timer_reg reg) ++u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg) + { + u32 val; + +diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c +index aa070384..6d9fad9d 100644 +--- a/drivers/clocksource/arm_arch_timer.c ++++ b/drivers/clocksource/arm_arch_timer.c +@@ -43,14 +43,28 @@ static bool arch_timer_use_virtual = true; + * Architected system timer support. + */ + ++static __always_inline ++void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val, ++ struct clock_event_device *clk) ++{ ++ arch_timer_reg_write_cp15(access, reg, val); ++} ++ ++static __always_inline ++u32 arch_timer_reg_read(int access, enum arch_timer_reg reg, ++ struct clock_event_device *clk) ++{ ++ return arch_timer_reg_read_cp15(access, reg); ++} ++ + static __always_inline irqreturn_t timer_handler(const int access, + struct clock_event_device *evt) + { + unsigned long ctrl; +- ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL); ++ ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt); + if (ctrl & ARCH_TIMER_CTRL_IT_STAT) { + ctrl |= ARCH_TIMER_CTRL_IT_MASK; +- arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl); ++ arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt); + evt->event_handler(evt); + return IRQ_HANDLED; + } +@@ -72,15 +86,16 @@ static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id) + return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt); + } + +-static __always_inline void timer_set_mode(const int access, int mode) ++static __always_inline void timer_set_mode(const int access, int mode, ++ struct clock_event_device *clk) + { + unsigned long ctrl; + switch (mode) { + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: +- ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL); ++ ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); + ctrl &= ~ARCH_TIMER_CTRL_ENABLE; +- arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl); ++ arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); + break; + default: + break; +@@ -90,36 +105,37 @@ static __always_inline void timer_set_mode(const int access, int mode) + static void arch_timer_set_mode_virt(enum clock_event_mode mode, + struct clock_event_device *clk) + { +- timer_set_mode(ARCH_TIMER_VIRT_ACCESS, mode); ++ timer_set_mode(ARCH_TIMER_VIRT_ACCESS, mode, clk); + } + + static void arch_timer_set_mode_phys(enum clock_event_mode mode, + struct clock_event_device *clk) + { +- timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode); ++ timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode, clk); + } + +-static __always_inline void set_next_event(const int access, unsigned long evt) ++static __always_inline void set_next_event(const int access, unsigned long evt, ++ struct clock_event_device *clk) + { + unsigned long ctrl; +- ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL); ++ ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); + ctrl |= ARCH_TIMER_CTRL_ENABLE; + ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; +- arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt); +- arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl); ++ arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk); ++ arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); + } + + static int arch_timer_set_next_event_virt(unsigned long evt, +- struct clock_event_device *unused) ++ struct clock_event_device *clk) + { +- set_next_event(ARCH_TIMER_VIRT_ACCESS, evt); ++ set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk); + return 0; + } + + static int arch_timer_set_next_event_phys(unsigned long evt, +- struct clock_event_device *unused) ++ struct clock_event_device *clk) + { +- set_next_event(ARCH_TIMER_PHYS_ACCESS, evt); ++ set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk); + return 0; + } + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0017-clocksource-em_sti-Convert-to-devm_-managed-helpers.patch b/patches.renesas/0017-clocksource-em_sti-Convert-to-devm_-managed-helpers.patch new file mode 100644 index 00000000000..a191a92b2c7 --- /dev/null +++ b/patches.renesas/0017-clocksource-em_sti-Convert-to-devm_-managed-helpers.patch @@ -0,0 +1,106 @@ +From 5528ed0bbde900200ce5497878af6a6d308b1098 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 30 Jul 2013 16:24:37 +0200 +Subject: clocksource: em_sti: Convert to devm_* managed helpers + +Replace kzalloc, clk_get, ioremap and request_irq by their managed +counterparts to simplify error paths. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Daniel Lezcano <daniel.lezcano@linaro.org> +(cherry picked from commit 1745e696e174b54e37c057882970e50af1e80a7f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clocksource/em_sti.c | 49 +++++++++++++------------------------------- + 1 file changed, 14 insertions(+), 35 deletions(-) + +diff --git a/drivers/clocksource/em_sti.c b/drivers/clocksource/em_sti.c +index 4329a29a..b9c81b7c 100644 +--- a/drivers/clocksource/em_sti.c ++++ b/drivers/clocksource/em_sti.c +@@ -315,68 +315,47 @@ static int em_sti_probe(struct platform_device *pdev) + { + struct em_sti_priv *p; + struct resource *res; +- int irq, ret; ++ int irq; + +- p = kzalloc(sizeof(*p), GFP_KERNEL); ++ p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL); + if (p == NULL) { + dev_err(&pdev->dev, "failed to allocate driver data\n"); +- ret = -ENOMEM; +- goto err0; ++ return -ENOMEM; + } + + p->pdev = pdev; + platform_set_drvdata(pdev, p); + +- res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- if (!res) { +- dev_err(&pdev->dev, "failed to get I/O memory\n"); +- ret = -EINVAL; +- goto err0; +- } +- + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(&pdev->dev, "failed to get irq\n"); +- ret = -EINVAL; +- goto err0; ++ return -EINVAL; + } + + /* map memory, let base point to the STI instance */ +- p->base = ioremap_nocache(res->start, resource_size(res)); +- if (p->base == NULL) { +- dev_err(&pdev->dev, "failed to remap I/O memory\n"); +- ret = -ENXIO; +- goto err0; +- } ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ p->base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(p->base)) ++ return PTR_ERR(p->base); + + /* get hold of clock */ +- p->clk = clk_get(&pdev->dev, "sclk"); ++ p->clk = devm_clk_get(&pdev->dev, "sclk"); + if (IS_ERR(p->clk)) { + dev_err(&pdev->dev, "cannot get clock\n"); +- ret = PTR_ERR(p->clk); +- goto err1; ++ return PTR_ERR(p->clk); + } + +- if (request_irq(irq, em_sti_interrupt, +- IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, +- dev_name(&pdev->dev), p)) { ++ if (devm_request_irq(&pdev->dev, irq, em_sti_interrupt, ++ IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, ++ dev_name(&pdev->dev), p)) { + dev_err(&pdev->dev, "failed to request low IRQ\n"); +- ret = -ENOENT; +- goto err2; ++ return -ENOENT; + } + + raw_spin_lock_init(&p->lock); + em_sti_register_clockevent(p); + em_sti_register_clocksource(p); + return 0; +- +-err2: +- clk_put(p->clk); +-err1: +- iounmap(p->base); +-err0: +- kfree(p); +- return ret; + } + + static int em_sti_remove(struct platform_device *pdev) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0018-clocksource-em_sti-Set-cpu_possible_mask-to-fix-SMP-.patch b/patches.renesas/0018-clocksource-em_sti-Set-cpu_possible_mask-to-fix-SMP-.patch new file mode 100644 index 00000000000..9d2ce97c560 --- /dev/null +++ b/patches.renesas/0018-clocksource-em_sti-Set-cpu_possible_mask-to-fix-SMP-.patch @@ -0,0 +1,42 @@ +From 41af3dec1a96407c5c8e0dd746d9490889dec1a2 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Wed, 18 Sep 2013 15:01:16 -0500 +Subject: clocksource: em_sti: Set cpu_possible_mask to fix SMP broadcast + +Update the STI driver by setting cpu_possible_mask to make EMEV2 +SMP work as expected together with the ARM broadcast timer. + +This breakage was introduced by: + +f7db706 ARM: 7674/1: smp: Avoid dummy clockevent being preferred over real hardware clock-event + +Without this fix SMP operation is broken on EMEV2 since no +broadcast timer interrupts trigger on the secondary CPU cores. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Tested-by: Simon Horman <horms+renesas@verge.net.au> +Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> +(cherry picked from commit 2199a5574b6d94b9ca26c6345356f45ec60fef8b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clocksource/em_sti.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clocksource/em_sti.c b/drivers/clocksource/em_sti.c +index b9c81b7c..3a5909c1 100644 +--- a/drivers/clocksource/em_sti.c ++++ b/drivers/clocksource/em_sti.c +@@ -301,7 +301,7 @@ static void em_sti_register_clockevent(struct em_sti_priv *p) + ced->name = dev_name(&p->pdev->dev); + ced->features = CLOCK_EVT_FEAT_ONESHOT; + ced->rating = 200; +- ced->cpumask = cpumask_of(0); ++ ced->cpumask = cpu_possible_mask; + ced->set_next_event = em_sti_clock_event_next; + ced->set_mode = em_sti_clock_event_mode; + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0019-gpio-rcar-R-Car-GPIO-IRQ-share-interrupt.patch b/patches.renesas/0019-gpio-rcar-R-Car-GPIO-IRQ-share-interrupt.patch new file mode 100644 index 00000000000..b9c9b1eb1a1 --- /dev/null +++ b/patches.renesas/0019-gpio-rcar-R-Car-GPIO-IRQ-share-interrupt.patch @@ -0,0 +1,34 @@ +From ef2267d538c37c8451bb7e2e8fe07ba2f442e400 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 17 Apr 2013 23:40:57 -0700 +Subject: gpio-rcar: R-Car GPIO IRQ share interrupt + +R-Car H1 or Gen2 GPIO interrupts are assigned per each GPIO domain, +but, Gen1 E1/M1 GPIO interrupts are shared for all GPIO domain. +gpio-rcar driver needs IRQF_SHARED flags for these. +This patch was tested on Bock-W board + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit c234962b808f289237a40e4ce5fc1c8066d1c9d0) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpio/gpio-rcar.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c +index b4ca4509..0f3d6473 100644 +--- a/drivers/gpio/gpio-rcar.c ++++ b/drivers/gpio/gpio-rcar.c +@@ -333,7 +333,7 @@ static int gpio_rcar_probe(struct platform_device *pdev) + } + + if (devm_request_irq(&pdev->dev, irq->start, +- gpio_rcar_irq_handler, 0, name, p)) { ++ gpio_rcar_irq_handler, IRQF_SHARED, name, p)) { + dev_err(&pdev->dev, "failed to request IRQ\n"); + ret = -ENOENT; + goto err1; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0020-gpio-rcar-Make-the-platform-data-gpio_base-field-sig.patch b/patches.renesas/0020-gpio-rcar-Make-the-platform-data-gpio_base-field-sig.patch new file mode 100644 index 00000000000..c12101bb3c5 --- /dev/null +++ b/patches.renesas/0020-gpio-rcar-Make-the-platform-data-gpio_base-field-sig.patch @@ -0,0 +1,35 @@ +From 0d67a462a81051ac61e7df42642a47f25afd8f4f Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Date: Fri, 10 May 2013 16:48:36 +0200 +Subject: gpio-rcar: Make the platform data gpio_base field signed + +The gpio_base field is used to specify the desired GPIO base for the +GPIO controller. The GPIO core can automatically allocate a GPIO number +range when the base is set to -1. To make this possible, make the field +signed. + +Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Acked-by: Linus Walleij <linus.walleij@linaro.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 36cb0066ffc55fd326c8a21ffe80aaa5bd16021b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + include/linux/platform_data/gpio-rcar.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/include/linux/platform_data/gpio-rcar.h b/include/linux/platform_data/gpio-rcar.h +index b253f77a..aba7079c 100644 +--- a/include/linux/platform_data/gpio-rcar.h ++++ b/include/linux/platform_data/gpio-rcar.h +@@ -17,7 +17,7 @@ + #define __GPIO_RCAR_H__ + + struct gpio_rcar_config { +- unsigned int gpio_base; ++ int gpio_base; + unsigned int irq_base; + unsigned int number_of_pins; + const char *pctl_name; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0021-gpio-rcar-Add-support-for-IRQ_TYPE_EDGE_BOTH.patch b/patches.renesas/0021-gpio-rcar-Add-support-for-IRQ_TYPE_EDGE_BOTH.patch new file mode 100644 index 00000000000..f4a86285f31 --- /dev/null +++ b/patches.renesas/0021-gpio-rcar-Add-support-for-IRQ_TYPE_EDGE_BOTH.patch @@ -0,0 +1,101 @@ +From d8d574975de57110e0f08077056d8741fb3c204a Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Fri, 24 May 2013 18:47:24 +0900 +Subject: gpio-rcar: Add support for IRQ_TYPE_EDGE_BOTH + +As hardware support for this feature is not universal for all SoCs a flag, +has_both_edge_trigger, has been added to the platform data of the driver to +allow this feature to be enabled. + +The motivation for this is to allow use of the gpio-keys driver on the +lager board which is based on the r8a7790 SoC. The V2 of this patch has been +fully exercised using that driver on that board. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 7e1092b5a264c484001b0cdd1f49bea7884e3366) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpio/gpio-rcar.c | 26 +++++++++++++++++++++----- + include/linux/platform_data/gpio-rcar.h | 1 + + 2 files changed, 22 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c +index 0f3d6473..d173d56d 100644 +--- a/drivers/gpio/gpio-rcar.c ++++ b/drivers/gpio/gpio-rcar.c +@@ -49,6 +49,7 @@ struct gpio_rcar_priv { + #define POSNEG 0x20 + #define EDGLEVEL 0x24 + #define FILONOFF 0x28 ++#define BOTHEDGE 0x4c + + static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs) + { +@@ -91,7 +92,8 @@ static void gpio_rcar_irq_enable(struct irq_data *d) + static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p, + unsigned int hwirq, + bool active_high_rising_edge, +- bool level_trigger) ++ bool level_trigger, ++ bool both) + { + unsigned long flags; + +@@ -108,6 +110,10 @@ static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p, + /* Configure edge or level trigger in EDGLEVEL */ + gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger); + ++ /* Select one edge or both edges in BOTHEDGE */ ++ if (p->config.has_both_edge_trigger) ++ gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both); ++ + /* Select "Interrupt Input Mode" in IOINTSEL */ + gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true); + +@@ -127,16 +133,26 @@ static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type) + + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_LEVEL_HIGH: +- gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true); ++ gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true, ++ false); + break; + case IRQ_TYPE_LEVEL_LOW: +- gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true); ++ gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true, ++ false); + break; + case IRQ_TYPE_EDGE_RISING: +- gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false); ++ gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false, ++ false); + break; + case IRQ_TYPE_EDGE_FALLING: +- gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false); ++ gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false, ++ false); ++ break; ++ case IRQ_TYPE_EDGE_BOTH: ++ if (!p->config.has_both_edge_trigger) ++ return -EINVAL; ++ gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false, ++ true); + break; + default: + return -EINVAL; +diff --git a/include/linux/platform_data/gpio-rcar.h b/include/linux/platform_data/gpio-rcar.h +index aba7079c..6c0027a3 100644 +--- a/include/linux/platform_data/gpio-rcar.h ++++ b/include/linux/platform_data/gpio-rcar.h +@@ -21,6 +21,7 @@ struct gpio_rcar_config { + unsigned int irq_base; + unsigned int number_of_pins; + const char *pctl_name; ++ unsigned has_both_edge_trigger:1; + }; + + #endif /* __GPIO_RCAR_H__ */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0022-gpio-rcar-Add-RCAR_GP_PIN-macro.patch b/patches.renesas/0022-gpio-rcar-Add-RCAR_GP_PIN-macro.patch new file mode 100644 index 00000000000..259dc5ec93d --- /dev/null +++ b/patches.renesas/0022-gpio-rcar-Add-RCAR_GP_PIN-macro.patch @@ -0,0 +1,39 @@ +From 69b2db4a30d95a8c9a2a33dc73f5cc429a706872 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 8 Apr 2013 11:36:13 +0200 +Subject: gpio-rcar: Add RCAR_GP_PIN macro + +Pins are numbered in the R-Car family documentation using a bank number +and a pin number in the bank. As the Linux pin number space is linear, +we need to flatten this by multiplying the bank number by 32 and adding +the pin number. The resulting number bear no directly visible +relationship to the documentation, making it error-prone. + +Add a RCAR_GP_PIN macro to convert from the documentation pin number +space to the linear Linux space. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +[horms+renesas@verge.net.au: non-trivial rebase on top of + "sh-pfc: r8a7779: Don't group USB OVC and PENC pins"] +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit 11df28ab76cd9e98e3e0bbbff8648d0a02509507) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + include/linux/platform_data/gpio-rcar.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/include/linux/platform_data/gpio-rcar.h b/include/linux/platform_data/gpio-rcar.h +index 6c0027a3..2d8d6943 100644 +--- a/include/linux/platform_data/gpio-rcar.h ++++ b/include/linux/platform_data/gpio-rcar.h +@@ -24,4 +24,6 @@ struct gpio_rcar_config { + unsigned has_both_edge_trigger:1; + }; + ++#define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin)) ++ + #endif /* __GPIO_RCAR_H__ */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0023-gpio-rcar-Add-DT-support.patch b/patches.renesas/0023-gpio-rcar-Add-DT-support.patch new file mode 100644 index 00000000000..34b8ed9a237 --- /dev/null +++ b/patches.renesas/0023-gpio-rcar-Add-DT-support.patch @@ -0,0 +1,202 @@ +From 9abe3b8c79c9e87f9ab8b8456d50a5c32b609a51 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 21 May 2013 13:40:06 +0200 +Subject: gpio-rcar: Add DT support + +Add DT bindings for the gpio-rcar driver and read the device +configuration from the DT node at probe time if available. + +Cc: devicetree-discuss@lists.ozlabs.org +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 159f8a0209aff155af7f6fcdedd4a4484dd19c23) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + .../devicetree/bindings/gpio/renesas,gpio-rcar.txt | 52 +++++++++++++++++ + drivers/gpio/gpio-rcar.c | 66 ++++++++++++++++++---- + 2 files changed, 108 insertions(+), 10 deletions(-) + create mode 100644 Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt + +diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt +new file mode 100644 +index 00000000..46d76a00 +--- /dev/null ++++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt +@@ -0,0 +1,52 @@ ++* Renesas R-Car GPIO Controller ++ ++Required Properties: ++ ++ - compatible: should be one of the following. ++ - "renesas,gpio-r8a7778": for R8A7778 (R-Mobile M1) compatible GPIO controller. ++ - "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO controller. ++ - "renesas,gpio-r8a7790": for R8A7790 (R-Car H2) compatible GPIO controller. ++ - "renesas,gpio-rcar": for generic R-Car GPIO controller. ++ ++ - reg: Base address and length of each memory resource used by the GPIO ++ controller hardware module. ++ ++ - interrupt-parent: phandle of the parent interrupt controller. ++ - interrupts: Interrupt specifier for the controllers interrupt. ++ ++ - gpio-controller: Marks the device node as a gpio controller. ++ - #gpio-cells: Should be 2. The first cell is the GPIO number and the second ++ cell is used to specify optional parameters as bit flags. Only the GPIO ++ active low flag (bit 0) is currently supported. ++ - gpio-ranges: Range of pins managed by the GPIO controller as a 4-cells ++ tuple using the following syntax. ++ ++ <[phandle of the pin controller node] ++ 0 ++ [index of the first pin] ++ [number of pins]> ++ ++Please refer to gpio.txt in this directory for details of the common GPIO ++bindings used by client devices. ++ ++Example: R8A7779 (R-Car H1) GPIO controller nodes ++ ++ gpio0: gpio@ffc40000 { ++ compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; ++ reg = <0xffc40000 0x2c>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 141 0x4>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ gpio-ranges = <&pfc 0 0 32>; ++ }; ++ ... ++ gpio6: gpio@ffc46000 { ++ compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; ++ reg = <0xffc46000 0x2c>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 147 0x4>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ gpio-ranges = <&pfc 0 192 9>; ++ }; +diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c +index d173d56d..5a693dd0 100644 +--- a/drivers/gpio/gpio-rcar.c ++++ b/drivers/gpio/gpio-rcar.c +@@ -51,6 +51,8 @@ struct gpio_rcar_priv { + #define FILONOFF 0x28 + #define BOTHEDGE 0x4c + ++#define RCAR_MAX_GPIO_PER_BANK 32 ++ + static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs) + { + return ioread32(p->base + offs); +@@ -274,9 +276,39 @@ static struct irq_domain_ops gpio_rcar_irq_domain_ops = { + .map = gpio_rcar_irq_domain_map, + }; + ++static void gpio_rcar_parse_pdata(struct gpio_rcar_priv *p) ++{ ++ struct gpio_rcar_config *pdata = p->pdev->dev.platform_data; ++#ifdef CONFIG_OF ++ struct device_node *np = p->pdev->dev.of_node; ++ struct of_phandle_args args; ++ int ret; ++#endif ++ ++ if (pdata) ++ p->config = *pdata; ++#ifdef CONFIG_OF ++ else if (np) { ++ ret = of_parse_phandle_with_args(np, "gpio-ranges", ++ "#gpio-range-cells", 0, &args); ++ p->config.number_of_pins = ret == 0 && args.args_count == 3 ++ ? args.args[2] ++ : RCAR_MAX_GPIO_PER_BANK; ++ p->config.gpio_base = -1; ++ } ++#endif ++ ++ if (p->config.number_of_pins == 0 || ++ p->config.number_of_pins > RCAR_MAX_GPIO_PER_BANK) { ++ dev_warn(&p->pdev->dev, ++ "Invalid number of gpio lines %u, using %u\n", ++ p->config.number_of_pins, RCAR_MAX_GPIO_PER_BANK); ++ p->config.number_of_pins = RCAR_MAX_GPIO_PER_BANK; ++ } ++} ++ + static int gpio_rcar_probe(struct platform_device *pdev) + { +- struct gpio_rcar_config *pdata = pdev->dev.platform_data; + struct gpio_rcar_priv *p; + struct resource *io, *irq; + struct gpio_chip *gpio_chip; +@@ -291,14 +323,14 @@ static int gpio_rcar_probe(struct platform_device *pdev) + goto err0; + } + +- /* deal with driver instance configuration */ +- if (pdata) +- p->config = *pdata; +- + p->pdev = pdev; +- platform_set_drvdata(pdev, p); + spin_lock_init(&p->lock); + ++ /* Get device configuration from DT node or platform data. */ ++ gpio_rcar_parse_pdata(p); ++ ++ platform_set_drvdata(pdev, p); ++ + io = platform_get_resource(pdev, IORESOURCE_MEM, 0); + irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + +@@ -325,6 +357,7 @@ static int gpio_rcar_probe(struct platform_device *pdev) + gpio_chip->set = gpio_rcar_set; + gpio_chip->to_irq = gpio_rcar_to_irq; + gpio_chip->label = name; ++ gpio_chip->dev = &pdev->dev; + gpio_chip->owner = THIS_MODULE; + gpio_chip->base = p->config.gpio_base; + gpio_chip->ngpio = p->config.number_of_pins; +@@ -371,10 +404,12 @@ static int gpio_rcar_probe(struct platform_device *pdev) + p->config.irq_base, ret); + } + +- ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0, +- gpio_chip->base, gpio_chip->ngpio); +- if (ret < 0) +- dev_warn(&pdev->dev, "failed to add pin range\n"); ++ if (p->config.pctl_name) { ++ ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0, ++ gpio_chip->base, gpio_chip->ngpio); ++ if (ret < 0) ++ dev_warn(&pdev->dev, "failed to add pin range\n"); ++ } + + return 0; + +@@ -397,11 +432,22 @@ static int gpio_rcar_remove(struct platform_device *pdev) + return 0; + } + ++#ifdef CONFIG_OF ++static const struct of_device_id gpio_rcar_of_table[] = { ++ { ++ .compatible = "renesas,gpio-rcar", ++ }, ++}; ++ ++MODULE_DEVICE_TABLE(of, gpio_rcar_of_table); ++#endif ++ + static struct platform_driver gpio_rcar_device_driver = { + .probe = gpio_rcar_probe, + .remove = gpio_rcar_remove, + .driver = { + .name = "gpio_rcar", ++ .of_match_table = of_match_ptr(gpio_rcar_of_table), + } + }; + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0024-gpio-rcar-Use-OUTDT-when-reading-GPIOs-configured-as.patch b/patches.renesas/0024-gpio-rcar-Use-OUTDT-when-reading-GPIOs-configured-as.patch new file mode 100644 index 00000000000..3d6ef368253 --- /dev/null +++ b/patches.renesas/0024-gpio-rcar-Use-OUTDT-when-reading-GPIOs-configured-as.patch @@ -0,0 +1,40 @@ +From a7b53103fa83410fea29a7cc4cb1898482d50ccb Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Mon, 17 Jun 2013 08:41:52 +0900 +Subject: gpio-rcar: Use OUTDT when reading GPIOs configured as output + +Testing on r8a7790 shows that INDT does not indicate the correct +pin state when reading a GPIO configured as output, so update +the gpio_rcar_get() function to handle this case. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit ae9550f635533b1ca5d0b50e24a720426ad237c6) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpio/gpio-rcar.c | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c +index 5a693dd0..d591ea64 100644 +--- a/drivers/gpio/gpio-rcar.c ++++ b/drivers/gpio/gpio-rcar.c +@@ -232,7 +232,14 @@ static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset) + + static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset) + { +- return (int)(gpio_rcar_read(gpio_to_priv(chip), INDT) & BIT(offset)); ++ u32 bit = BIT(offset); ++ ++ /* testing on r8a7790 shows that INDT does not show correct pin state ++ * when configured as output, so use OUTDT in case of output pins */ ++ if (gpio_rcar_read(gpio_to_priv(chip), INOUTSEL) & bit) ++ return (int)(gpio_rcar_read(gpio_to_priv(chip), OUTDT) & bit); ++ else ++ return (int)(gpio_rcar_read(gpio_to_priv(chip), INDT) & bit); + } + + static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0025-gpio-rcar-Reference-core-gpio-documentation-in-the-D.patch b/patches.renesas/0025-gpio-rcar-Reference-core-gpio-documentation-in-the-D.patch new file mode 100644 index 00000000000..a9707f79cb6 --- /dev/null +++ b/patches.renesas/0025-gpio-rcar-Reference-core-gpio-documentation-in-the-D.patch @@ -0,0 +1,48 @@ +From 907121ee5fafae98aa6b8775d98511b3e7444543 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 18 Jun 2013 12:29:48 +0200 +Subject: gpio-rcar: Reference core gpio documentation in the DT bindings + +Replaced the detailed gpio-ranges documentation with a reference to the +code gpio DT bindings, and mention the gpio flags symbolic names. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit b559c3e8e7ca469921987925baf892ab2038396e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + .../devicetree/bindings/gpio/renesas,gpio-rcar.txt | 18 ++++++------------ + 1 file changed, 6 insertions(+), 12 deletions(-) + +diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt +index 46d76a00..cb3dc7bc 100644 +--- a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt ++++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt +@@ -16,18 +16,12 @@ Required Properties: + + - gpio-controller: Marks the device node as a gpio controller. + - #gpio-cells: Should be 2. The first cell is the GPIO number and the second +- cell is used to specify optional parameters as bit flags. Only the GPIO +- active low flag (bit 0) is currently supported. +- - gpio-ranges: Range of pins managed by the GPIO controller as a 4-cells +- tuple using the following syntax. +- +- <[phandle of the pin controller node] +- 0 +- [index of the first pin] +- [number of pins]> +- +-Please refer to gpio.txt in this directory for details of the common GPIO +-bindings used by client devices. ++ cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the ++ GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported. ++ - gpio-ranges: Range of pins managed by the GPIO controller. ++ ++Please refer to gpio.txt in this directory for details of gpio-ranges property ++and the common GPIO bindings used by client devices. + + Example: R8A7779 (R-Car H1) GPIO controller nodes + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0026-gpio-rcar-Remove-ifdef-CONFIG_OF-around-OF-specific-.patch b/patches.renesas/0026-gpio-rcar-Remove-ifdef-CONFIG_OF-around-OF-specific-.patch new file mode 100644 index 00000000000..951406668f3 --- /dev/null +++ b/patches.renesas/0026-gpio-rcar-Remove-ifdef-CONFIG_OF-around-OF-specific-.patch @@ -0,0 +1,52 @@ +From 6123ad86b5be74f26d9a0afc51327721913a32f9 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 18 Jun 2013 12:29:49 +0200 +Subject: gpio-rcar: Remove #ifdef CONFIG_OF around OF-specific sections + +All functions and data types used by OF-specific code paths are declared +in <linux/of.h> regardless of CONFIG_OF. Replace the #ifdef CONFIG_OF +guard with a if(IS_ENABLED(CONFIG_OF)) and let the compiler optimize +the unused code away. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit e305062e94719ef543ae936dd56501b5a36406c6) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpio/gpio-rcar.c | 8 ++------ + 1 file changed, 2 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c +index d591ea64..34f86b26 100644 +--- a/drivers/gpio/gpio-rcar.c ++++ b/drivers/gpio/gpio-rcar.c +@@ -286,16 +286,13 @@ static struct irq_domain_ops gpio_rcar_irq_domain_ops = { + static void gpio_rcar_parse_pdata(struct gpio_rcar_priv *p) + { + struct gpio_rcar_config *pdata = p->pdev->dev.platform_data; +-#ifdef CONFIG_OF + struct device_node *np = p->pdev->dev.of_node; + struct of_phandle_args args; + int ret; +-#endif + +- if (pdata) ++ if (pdata) { + p->config = *pdata; +-#ifdef CONFIG_OF +- else if (np) { ++ } else if (IS_ENABLED(CONFIG_OF) && np) { + ret = of_parse_phandle_with_args(np, "gpio-ranges", + "#gpio-range-cells", 0, &args); + p->config.number_of_pins = ret == 0 && args.args_count == 3 +@@ -303,7 +300,6 @@ static void gpio_rcar_parse_pdata(struct gpio_rcar_priv *p) + : RCAR_MAX_GPIO_PER_BANK; + p->config.gpio_base = -1; + } +-#endif + + if (p->config.number_of_pins == 0 || + p->config.number_of_pins > RCAR_MAX_GPIO_PER_BANK) { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0027-gpio-rcar-fix-gpio_rcar_of_table.patch b/patches.renesas/0027-gpio-rcar-fix-gpio_rcar_of_table.patch new file mode 100644 index 00000000000..01f8c82cc0d --- /dev/null +++ b/patches.renesas/0027-gpio-rcar-fix-gpio_rcar_of_table.patch @@ -0,0 +1,31 @@ +From a61f80817625502c7f6e47ea6730553ed56a2077 Mon Sep 17 00:00:00 2001 +From: Arnd Bergmann <arnd@arndb.de> +Date: Mon, 17 Jun 2013 09:55:50 +0200 +Subject: gpio: rcar: fix gpio_rcar_of_table + +The device table needs to be terminated with an empty element. + +Signed-off-by: Arnd Bergmann <arnd@arndb.de> +Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Cc: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 30d2266c685ce9f560e5023e4add58f890554a46) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpio/gpio-rcar.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c +index 34f86b26..e8198dd6 100644 +--- a/drivers/gpio/gpio-rcar.c ++++ b/drivers/gpio/gpio-rcar.c +@@ -440,6 +440,7 @@ static const struct of_device_id gpio_rcar_of_table[] = { + { + .compatible = "renesas,gpio-rcar", + }, ++ { }, + }; + + MODULE_DEVICE_TABLE(of, gpio_rcar_of_table); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0028-gpio-rcar-Add-interrupt-controller-support-to-the-DT.patch b/patches.renesas/0028-gpio-rcar-Add-interrupt-controller-support-to-the-DT.patch new file mode 100644 index 00000000000..006803a8fee --- /dev/null +++ b/patches.renesas/0028-gpio-rcar-Add-interrupt-controller-support-to-the-DT.patch @@ -0,0 +1,50 @@ +From 3971223c8f243c9fd662644b64ee3116efc61b42 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 4 Jul 2013 19:44:39 +0200 +Subject: gpio-rcar: Add interrupt controller support to the DT bindings + +Update the DT bindings documentation with the interrupt-controller +and #interrupt-cells properties. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit f8b1bd71d0c5c9fdcd4458c1688208eaf06a26fb) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt +index cb3dc7bc..8655df94 100644 +--- a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt ++++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt +@@ -23,6 +23,10 @@ Required Properties: + Please refer to gpio.txt in this directory for details of gpio-ranges property + and the common GPIO bindings used by client devices. + ++The GPIO controller also acts as an interrupt controller. It uses the default ++two cells specifier as described in Documentation/devicetree/bindings/ ++interrupt-controller/interrupts.txt. ++ + Example: R8A7779 (R-Car H1) GPIO controller nodes + + gpio0: gpio@ffc40000 { +@@ -33,6 +37,8 @@ Example: R8A7779 (R-Car H1) GPIO controller nodes + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; ++ interrupt-controller; ++ #interrupt-cells = <2>; + }; + ... + gpio6: gpio@ffc46000 { +@@ -43,4 +49,6 @@ Example: R8A7779 (R-Car H1) GPIO controller nodes + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 9>; ++ interrupt-controller; ++ #interrupt-cells = <2>; + }; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0029-i2c-rcar-add-rcar-H2-support.patch b/patches.renesas/0029-i2c-rcar-add-rcar-H2-support.patch new file mode 100644 index 00000000000..e55f3804bf7 --- /dev/null +++ b/patches.renesas/0029-i2c-rcar-add-rcar-H2-support.patch @@ -0,0 +1,119 @@ +From 5f7b9de412f8b01431f539cd0c4488b315c0c8c6 Mon Sep 17 00:00:00 2001 +From: Nguyen Viet Dung <nv-dung@jinso.co.jp> +Date: Tue, 3 Sep 2013 09:09:25 +0900 +Subject: i2c: rcar: add rcar-H2 support + +This patch modify I2C driver of rcar-H1 to usable on both rcar-H1 and rcar-H2. + +Signed-off-by: Nguyen Viet Dung <nv-dung@jinso.co.jp> +Signed-off-by: Wolfram Sang <wsa@the-dreams.de> +(cherry picked from commit b720423a2627f045133bec39a31fe2bc0dab86f3) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/i2c/busses/i2c-rcar.c | 35 +++++++++++++++++++++++++++++++++-- + 1 file changed, 33 insertions(+), 2 deletions(-) + +diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c +index 4ba4a95b..18e03373 100644 +--- a/drivers/i2c/busses/i2c-rcar.c ++++ b/drivers/i2c/busses/i2c-rcar.c +@@ -101,6 +101,11 @@ enum { + #define ID_ARBLOST (1 << 3) + #define ID_NACK (1 << 4) + ++enum rcar_i2c_type { ++ I2C_RCAR_H1, ++ I2C_RCAR_H2, ++}; ++ + struct rcar_i2c_priv { + void __iomem *io; + struct i2c_adapter adap; +@@ -113,6 +118,7 @@ struct rcar_i2c_priv { + int irq; + u32 icccr; + u32 flags; ++ enum rcar_i2c_type devtype; + }; + + #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) +@@ -224,12 +230,25 @@ static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, + u32 scgd, cdf; + u32 round, ick; + u32 scl; ++ u32 cdf_width; + + if (!clkp) { + dev_err(dev, "there is no peripheral_clk\n"); + return -EIO; + } + ++ switch (priv->devtype) { ++ case I2C_RCAR_H1: ++ cdf_width = 2; ++ break; ++ case I2C_RCAR_H2: ++ cdf_width = 3; ++ break; ++ default: ++ dev_err(dev, "device type error\n"); ++ return -EIO; ++ } ++ + /* + * calculate SCL clock + * see +@@ -245,7 +264,7 @@ static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, + * clkp : peripheral_clk + * F[] : integer up-valuation + */ +- for (cdf = 0; cdf < 4; cdf++) { ++ for (cdf = 0; cdf < (1 << cdf_width); cdf++) { + ick = clk_get_rate(clkp) / (1 + cdf); + if (ick < 20000000) + goto ick_find; +@@ -287,7 +306,7 @@ scgd_find: + /* + * keep icccr value + */ +- priv->icccr = (scgd << 2 | cdf); ++ priv->icccr = (scgd << (cdf_width) | cdf); + + return 0; + } +@@ -638,6 +657,9 @@ static int rcar_i2c_probe(struct platform_device *pdev) + bus_speed = 100000; /* default 100 kHz */ + if (pdata && pdata->bus_speed) + bus_speed = pdata->bus_speed; ++ ++ priv->devtype = platform_get_device_id(pdev)->driver_data; ++ + ret = rcar_i2c_clock_calculate(priv, bus_speed, dev); + if (ret < 0) + return ret; +@@ -691,6 +713,14 @@ static int rcar_i2c_remove(struct platform_device *pdev) + return 0; + } + ++static struct platform_device_id rcar_i2c_id_table[] = { ++ { "i2c-rcar", I2C_RCAR_H1 }, ++ { "i2c-rcar_h1", I2C_RCAR_H1 }, ++ { "i2c-rcar_h2", I2C_RCAR_H2 }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(platform, rcar_i2c_id_table); ++ + static struct platform_driver rcar_i2c_driver = { + .driver = { + .name = "i2c-rcar", +@@ -698,6 +728,7 @@ static struct platform_driver rcar_i2c_driver = { + }, + .probe = rcar_i2c_probe, + .remove = rcar_i2c_remove, ++ .id_table = rcar_i2c_id_table, + }; + + module_platform_driver(rcar_i2c_driver); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0030-thermal-rcar-Fix-typo-in-probe-information-message.patch b/patches.renesas/0030-thermal-rcar-Fix-typo-in-probe-information-message.patch new file mode 100644 index 00000000000..bc735a26389 --- /dev/null +++ b/patches.renesas/0030-thermal-rcar-Fix-typo-in-probe-information-message.patch @@ -0,0 +1,30 @@ +From cb96b723c87c6b716db266658b91f66eb1baca01 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 14 May 2013 23:00:32 +0000 +Subject: thermal: rcar: Fix typo in probe information message + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Acked-by: Eduardo Valentin <eduardo.valentin@ti.com> +Signed-off-by: Zhang Rui <rui.zhang@intel.com> +(cherry picked from commit 3db46c939677e32e311d354b619fd552ceafd123) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/thermal/rcar_thermal.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/thermal/rcar_thermal.c b/drivers/thermal/rcar_thermal.c +index 8d7edd4c..3eaca06d 100644 +--- a/drivers/thermal/rcar_thermal.c ++++ b/drivers/thermal/rcar_thermal.c +@@ -458,7 +458,7 @@ static int rcar_thermal_probe(struct platform_device *pdev) + + platform_set_drvdata(pdev, common); + +- dev_info(dev, "%d sensor proved\n", i); ++ dev_info(dev, "%d sensor probed\n", i); + + return 0; + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0031-Thermal-rcar-Remove-redundant-platform_set_drvdata.patch b/patches.renesas/0031-Thermal-rcar-Remove-redundant-platform_set_drvdata.patch new file mode 100644 index 00000000000..4772f638b08 --- /dev/null +++ b/patches.renesas/0031-Thermal-rcar-Remove-redundant-platform_set_drvdata.patch @@ -0,0 +1,35 @@ +From ced6919282c99b3272c2b670f47973bbad8bf898 Mon Sep 17 00:00:00 2001 +From: Sachin Kamat <sachin.kamat@linaro.org> +Date: Fri, 3 May 2013 09:57:12 +0000 +Subject: Thermal: rcar: Remove redundant platform_set_drvdata() + +Commit 0998d06310 (device-core: Ensure drvdata = NULL when no +driver is bound) removes the need to set driver data field to +NULL. + +Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> +Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Acked-by: Eduardo Valentin <eduardo.valentin@ti.com> +Signed-off-by: Zhang Rui <rui.zhang@intel.com> +(cherry picked from commit 6135ba36f44069ad789bd9f8d6a75eebc3946eba) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/thermal/rcar_thermal.c | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/drivers/thermal/rcar_thermal.c b/drivers/thermal/rcar_thermal.c +index 3eaca06d..13b54c04 100644 +--- a/drivers/thermal/rcar_thermal.c ++++ b/drivers/thermal/rcar_thermal.c +@@ -487,8 +487,6 @@ static int rcar_thermal_remove(struct platform_device *pdev) + rcar_thermal_irq_disable(priv); + } + +- platform_set_drvdata(pdev, NULL); +- + pm_runtime_put_sync(dev); + pm_runtime_disable(dev); + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0032-ASoC-fsi-fixup-sparse-errors.patch b/patches.renesas/0032-ASoC-fsi-fixup-sparse-errors.patch new file mode 100644 index 00000000000..f7ffa0582fa --- /dev/null +++ b/patches.renesas/0032-ASoC-fsi-fixup-sparse-errors.patch @@ -0,0 +1,78 @@ +From ac88352e83f54d63d46b46dfbea44baaeabadd18 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 28 May 2013 00:55:12 -0700 +Subject: ASoC: fsi: fixup sparse errors + +This patch fixup below sparse errors + +${LINUX}/sound/soc/sh/fsi.c:1459:9: \ + error: incompatible types in conditional expression (different base types) +${LINUX}/sound/soc/sh/fsi.c:1634:25: \ + error: incompatible types in conditional expression (different base types) +${LINUX}/sound/soc/sh/fsi.c:1639:17: \ + error: incompatible types in conditional expression (different base types) +${LINUX}/sound/soc/sh/fsi.c:2093:9: \ + error: incompatible types in conditional expression (different base types) +${LINUX}/sound/soc/sh/fsi.c:2105:9: \ + error: incompatible types in conditional expression (different base types) + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> +(cherry picked from commit c375b2d7eff01d6423b95b2d44e8466beae0a15a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/fsi.c | 10 +++++++--- + 1 file changed, 7 insertions(+), 3 deletions(-) + +diff --git a/sound/soc/sh/fsi.c b/sound/soc/sh/fsi.c +index f830c41f..30390260 100644 +--- a/sound/soc/sh/fsi.c ++++ b/sound/soc/sh/fsi.c +@@ -276,7 +276,7 @@ struct fsi_stream_handler { + int (*probe)(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev); + int (*transfer)(struct fsi_priv *fsi, struct fsi_stream *io); + int (*remove)(struct fsi_priv *fsi, struct fsi_stream *io); +- void (*start_stop)(struct fsi_priv *fsi, struct fsi_stream *io, ++ int (*start_stop)(struct fsi_priv *fsi, struct fsi_stream *io, + int enable); + }; + #define fsi_stream_handler_call(io, func, args...) \ +@@ -1188,7 +1188,7 @@ static int fsi_pio_push(struct fsi_priv *fsi, struct fsi_stream *io) + samples); + } + +-static void fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io, ++static int fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io, + int enable) + { + struct fsi_master *master = fsi_get_master(fsi); +@@ -1201,6 +1201,8 @@ static void fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io, + + if (fsi_is_clk_master(fsi)) + fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0); ++ ++ return 0; + } + + static int fsi_pio_push_init(struct fsi_priv *fsi, struct fsi_stream *io) +@@ -1409,7 +1411,7 @@ static int fsi_dma_transfer(struct fsi_priv *fsi, struct fsi_stream *io) + return 0; + } + +-static void fsi_dma_push_start_stop(struct fsi_priv *fsi, struct fsi_stream *io, ++static int fsi_dma_push_start_stop(struct fsi_priv *fsi, struct fsi_stream *io, + int start) + { + struct fsi_master *master = fsi_get_master(fsi); +@@ -1422,6 +1424,8 @@ static void fsi_dma_push_start_stop(struct fsi_priv *fsi, struct fsi_stream *io, + + if (fsi_is_clk_master(fsi)) + fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0); ++ ++ return 0; + } + + static int fsi_dma_probe(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0033-ASoC-add-Renesas-R-Car-core-feature.patch b/patches.renesas/0033-ASoC-add-Renesas-R-Car-core-feature.patch new file mode 100644 index 00000000000..ebc370e1f8c --- /dev/null +++ b/patches.renesas/0033-ASoC-add-Renesas-R-Car-core-feature.patch @@ -0,0 +1,777 @@ +From 469ca87d334fb915b265861b31c52e83fb7f3846 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Sun, 21 Jul 2013 21:35:52 -0700 +Subject: ASoC: add Renesas R-Car core feature + +Renesas R-Car series sound circuit consists of SSI and its peripheral. +But this peripheral circuits are different between +R-Car Generation1 (E1/M1/H1) and Generation2 (E2/M2/H2). +(Actually, there are many difference in Generation1 chips) + +Basically, for the future, Renesas R-Car series will use +Gen2 style sound circuit, but driver should care Gen1 also. +The main differences between Gen1 and Gen2 peripheral +are 1) register offset, 2) data path. + +This patch adds basic (core) feature for R-Car +series sound driver as prototype + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Mark Brown <broonie@linaro.org> +(cherry picked from commit 1536a968892aa9095aada4b6d2ed326432cd71c8) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + include/sound/rcar_snd.h | 33 +++ + sound/soc/sh/Kconfig | 7 + + sound/soc/sh/Makefile | 3 + + sound/soc/sh/rcar/Makefile | 2 + + sound/soc/sh/rcar/core.c | 554 +++++++++++++++++++++++++++++++++++++++++++++ + sound/soc/sh/rcar/rsnd.h | 94 ++++++++ + 6 files changed, 693 insertions(+) + create mode 100644 include/sound/rcar_snd.h + create mode 100644 sound/soc/sh/rcar/Makefile + create mode 100644 sound/soc/sh/rcar/core.c + create mode 100644 sound/soc/sh/rcar/rsnd.h + +diff --git a/include/sound/rcar_snd.h b/include/sound/rcar_snd.h +new file mode 100644 +index 00000000..7272b2ea +--- /dev/null ++++ b/include/sound/rcar_snd.h +@@ -0,0 +1,33 @@ ++/* ++ * Renesas R-Car SRU/SCU/SSIU/SSI support ++ * ++ * Copyright (C) 2013 Renesas Solutions Corp. ++ * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef RCAR_SND_H ++#define RCAR_SND_H ++ ++#include <linux/sh_clk.h> ++ ++ ++#define RSND_BASE_MAX 0 ++ ++struct rsnd_dai_platform_info { ++ int ssi_id_playback; ++ int ssi_id_capture; ++}; ++ ++struct rcar_snd_info { ++ u32 flags; ++ struct rsnd_dai_platform_info *dai_info; ++ int dai_info_nr; ++ int (*start)(int id); ++ int (*stop)(int id); ++}; ++ ++#endif +diff --git a/sound/soc/sh/Kconfig b/sound/soc/sh/Kconfig +index 6bcb1164..56d8ff6a 100644 +--- a/sound/soc/sh/Kconfig ++++ b/sound/soc/sh/Kconfig +@@ -34,6 +34,13 @@ config SND_SOC_SH4_SIU + select SH_DMAE + select FW_LOADER + ++config SND_SOC_RCAR ++ tristate "R-Car series SRU/SCU/SSIU/SSI support" ++ select SND_SIMPLE_CARD ++ select RCAR_CLK_ADG ++ help ++ This option enables R-Car SUR/SCU/SSIU/SSI sound support ++ + ## + ## Boards + ## +diff --git a/sound/soc/sh/Makefile b/sound/soc/sh/Makefile +index 849b387d..aaf3dcd1 100644 +--- a/sound/soc/sh/Makefile ++++ b/sound/soc/sh/Makefile +@@ -12,6 +12,9 @@ obj-$(CONFIG_SND_SOC_SH4_SSI) += snd-soc-ssi.o + obj-$(CONFIG_SND_SOC_SH4_FSI) += snd-soc-fsi.o + obj-$(CONFIG_SND_SOC_SH4_SIU) += snd-soc-siu.o + ++## audio units for R-Car ++obj-$(CONFIG_SND_SOC_RCAR) += rcar/ ++ + ## boards + snd-soc-sh7760-ac97-objs := sh7760-ac97.o + snd-soc-migor-objs := migor.o +diff --git a/sound/soc/sh/rcar/Makefile b/sound/soc/sh/rcar/Makefile +new file mode 100644 +index 00000000..cd8089f2 +--- /dev/null ++++ b/sound/soc/sh/rcar/Makefile +@@ -0,0 +1,2 @@ ++snd-soc-rcar-objs := core.o ++obj-$(CONFIG_SND_SOC_RCAR) += snd-soc-rcar.o +diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c +new file mode 100644 +index 00000000..13b5d50e +--- /dev/null ++++ b/sound/soc/sh/rcar/core.c +@@ -0,0 +1,554 @@ ++/* ++ * Renesas R-Car SRU/SCU/SSIU/SSI support ++ * ++ * Copyright (C) 2013 Renesas Solutions Corp. ++ * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> ++ * ++ * Based on fsi.c ++ * Kuninori Morimoto <morimoto.kuninori@renesas.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++/* ++ * Renesas R-Car sound device structure ++ * ++ * Gen1 ++ * ++ * SRU : Sound Routing Unit ++ * - SRC : Sampling Rate Converter ++ * - CMD ++ * - CTU : Channel Count Conversion Unit ++ * - MIX : Mixer ++ * - DVC : Digital Volume and Mute Function ++ * - SSI : Serial Sound Interface ++ * ++ * Gen2 ++ * ++ * SCU : Sampling Rate Converter Unit ++ * - SRC : Sampling Rate Converter ++ * - CMD ++ * - CTU : Channel Count Conversion Unit ++ * - MIX : Mixer ++ * - DVC : Digital Volume and Mute Function ++ * SSIU : Serial Sound Interface Unit ++ * - SSI : Serial Sound Interface ++ */ ++ ++/* ++ * driver data Image ++ * ++ * rsnd_priv ++ * | ++ * | ** this depends on Gen1/Gen2 ++ * | ++ * +- gen ++ * | ++ * | ** these depend on data path ++ * | ** gen and platform data control it ++ * | ++ * +- rdai[0] ++ * | | sru ssiu ssi ++ * | +- playback -> [mod] -> [mod] -> [mod] -> ... ++ * | | ++ * | | sru ssiu ssi ++ * | +- capture -> [mod] -> [mod] -> [mod] -> ... ++ * | ++ * +- rdai[1] ++ * | | sru ssiu ssi ++ * | +- playback -> [mod] -> [mod] -> [mod] -> ... ++ * | | ++ * | | sru ssiu ssi ++ * | +- capture -> [mod] -> [mod] -> [mod] -> ... ++ * ... ++ * | ++ * | ** these control ssi ++ * | ++ * +- ssi ++ * | | ++ * | +- ssi[0] ++ * | +- ssi[1] ++ * | +- ssi[2] ++ * | ... ++ * | ++ * | ** these control scu ++ * | ++ * +- scu ++ * | ++ * +- scu[0] ++ * +- scu[1] ++ * +- scu[2] ++ * ... ++ * ++ * ++ * for_each_rsnd_dai(xx, priv, xx) ++ * rdai[0] => rdai[1] => rdai[2] => ... ++ * ++ * for_each_rsnd_mod(xx, rdai, xx) ++ * [mod] => [mod] => [mod] => ... ++ * ++ * rsnd_dai_call(xxx, fn ) ++ * [mod]->fn() -> [mod]->fn() -> [mod]->fn()... ++ * ++ */ ++#include <linux/pm_runtime.h> ++#include "rsnd.h" ++ ++#define RSND_RATES SNDRV_PCM_RATE_8000_96000 ++#define RSND_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) ++ ++/* ++ * rsnd_platform functions ++ */ ++#define rsnd_platform_call(priv, dai, func, param...) \ ++ (!(priv->info->func) ? -ENODEV : \ ++ priv->info->func(param)) ++ ++ ++/* ++ * rsnd_dai functions ++ */ ++struct rsnd_dai *rsnd_dai_get(struct rsnd_priv *priv, int id) ++{ ++ return priv->rdai + id; ++} ++ ++static struct rsnd_dai *rsnd_dai_to_rdai(struct snd_soc_dai *dai) ++{ ++ struct rsnd_priv *priv = snd_soc_dai_get_drvdata(dai); ++ ++ return rsnd_dai_get(priv, dai->id); ++} ++ ++int rsnd_dai_is_play(struct rsnd_dai *rdai, struct rsnd_dai_stream *io) ++{ ++ return &rdai->playback == io; ++} ++ ++/* ++ * rsnd_soc_dai functions ++ */ ++int rsnd_dai_pointer_offset(struct rsnd_dai_stream *io, int additional) ++{ ++ struct snd_pcm_substream *substream = io->substream; ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ int pos = io->byte_pos + additional; ++ ++ pos %= (runtime->periods * io->byte_per_period); ++ ++ return pos; ++} ++ ++void rsnd_dai_pointer_update(struct rsnd_dai_stream *io, int byte) ++{ ++ io->byte_pos += byte; ++ ++ if (io->byte_pos >= io->next_period_byte) { ++ struct snd_pcm_substream *substream = io->substream; ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ ++ io->period_pos++; ++ io->next_period_byte += io->byte_per_period; ++ ++ if (io->period_pos >= runtime->periods) { ++ io->byte_pos = 0; ++ io->period_pos = 0; ++ io->next_period_byte = io->byte_per_period; ++ } ++ ++ snd_pcm_period_elapsed(substream); ++ } ++} ++ ++static int rsnd_dai_stream_init(struct rsnd_dai_stream *io, ++ struct snd_pcm_substream *substream) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ ++ if (!list_empty(&io->head)) ++ return -EIO; ++ ++ INIT_LIST_HEAD(&io->head); ++ io->substream = substream; ++ io->byte_pos = 0; ++ io->period_pos = 0; ++ io->byte_per_period = runtime->period_size * ++ runtime->channels * ++ samples_to_bytes(runtime, 1); ++ io->next_period_byte = io->byte_per_period; ++ ++ return 0; ++} ++ ++static ++struct snd_soc_dai *rsnd_substream_to_dai(struct snd_pcm_substream *substream) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ ++ return rtd->cpu_dai; ++} ++ ++static ++struct rsnd_dai_stream *rsnd_rdai_to_io(struct rsnd_dai *rdai, ++ struct snd_pcm_substream *substream) ++{ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ return &rdai->playback; ++ else ++ return &rdai->capture; ++} ++ ++static int rsnd_soc_dai_trigger(struct snd_pcm_substream *substream, int cmd, ++ struct snd_soc_dai *dai) ++{ ++ struct rsnd_priv *priv = snd_soc_dai_get_drvdata(dai); ++ struct rsnd_dai *rdai = rsnd_dai_to_rdai(dai); ++ struct rsnd_dai_stream *io = rsnd_rdai_to_io(rdai, substream); ++ struct rsnd_dai_platform_info *info = rsnd_dai_get_platform_info(rdai); ++ int ssi_id = rsnd_dai_is_play(rdai, io) ? info->ssi_id_playback : ++ info->ssi_id_capture; ++ int ret; ++ unsigned long flags; ++ ++ rsnd_lock(priv, flags); ++ ++ switch (cmd) { ++ case SNDRV_PCM_TRIGGER_START: ++ ret = rsnd_dai_stream_init(io, substream); ++ if (ret < 0) ++ goto dai_trigger_end; ++ ++ ret = rsnd_platform_call(priv, dai, start, ssi_id); ++ if (ret < 0) ++ goto dai_trigger_end; ++ ++ break; ++ case SNDRV_PCM_TRIGGER_STOP: ++ ret = rsnd_platform_call(priv, dai, stop, ssi_id); ++ if (ret < 0) ++ goto dai_trigger_end; ++ ++ break; ++ default: ++ ret = -EINVAL; ++ } ++ ++dai_trigger_end: ++ rsnd_unlock(priv, flags); ++ ++ return ret; ++} ++ ++static int rsnd_soc_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) ++{ ++ struct rsnd_dai *rdai = rsnd_dai_to_rdai(dai); ++ ++ /* set master/slave audio interface */ ++ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { ++ case SND_SOC_DAIFMT_CBM_CFM: ++ rdai->clk_master = 1; ++ break; ++ case SND_SOC_DAIFMT_CBS_CFS: ++ rdai->clk_master = 0; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ /* set clock inversion */ ++ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { ++ case SND_SOC_DAIFMT_NB_IF: ++ rdai->bit_clk_inv = 0; ++ rdai->frm_clk_inv = 1; ++ break; ++ case SND_SOC_DAIFMT_IB_NF: ++ rdai->bit_clk_inv = 1; ++ rdai->frm_clk_inv = 0; ++ break; ++ case SND_SOC_DAIFMT_IB_IF: ++ rdai->bit_clk_inv = 1; ++ rdai->frm_clk_inv = 1; ++ break; ++ case SND_SOC_DAIFMT_NB_NF: ++ default: ++ rdai->bit_clk_inv = 0; ++ rdai->frm_clk_inv = 0; ++ break; ++ } ++ ++ /* set format */ ++ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { ++ case SND_SOC_DAIFMT_I2S: ++ rdai->sys_delay = 0; ++ rdai->data_alignment = 0; ++ break; ++ case SND_SOC_DAIFMT_LEFT_J: ++ rdai->sys_delay = 1; ++ rdai->data_alignment = 0; ++ break; ++ case SND_SOC_DAIFMT_RIGHT_J: ++ rdai->sys_delay = 1; ++ rdai->data_alignment = 1; ++ break; ++ } ++ ++ return 0; ++} ++ ++static const struct snd_soc_dai_ops rsnd_soc_dai_ops = { ++ .trigger = rsnd_soc_dai_trigger, ++ .set_fmt = rsnd_soc_dai_set_fmt, ++}; ++ ++static int rsnd_dai_probe(struct platform_device *pdev, ++ struct rcar_snd_info *info, ++ struct rsnd_priv *priv) ++{ ++ struct snd_soc_dai_driver *drv; ++ struct rsnd_dai *rdai; ++ struct device *dev = rsnd_priv_to_dev(priv); ++ struct rsnd_dai_platform_info *dai_info; ++ int dai_nr = info->dai_info_nr; ++ int i, pid, cid; ++ ++ drv = devm_kzalloc(dev, sizeof(*drv) * dai_nr, GFP_KERNEL); ++ rdai = devm_kzalloc(dev, sizeof(*rdai) * dai_nr, GFP_KERNEL); ++ if (!drv || !rdai) { ++ dev_err(dev, "dai allocate failed\n"); ++ return -ENOMEM; ++ } ++ ++ for (i = 0; i < dai_nr; i++) { ++ dai_info = &info->dai_info[i]; ++ ++ pid = dai_info->ssi_id_playback; ++ cid = dai_info->ssi_id_capture; ++ ++ /* ++ * init rsnd_dai ++ */ ++ INIT_LIST_HEAD(&rdai[i].playback.head); ++ INIT_LIST_HEAD(&rdai[i].capture.head); ++ ++ rdai[i].info = dai_info; ++ ++ snprintf(rdai[i].name, RSND_DAI_NAME_SIZE, "rsnd-dai.%d", i); ++ ++ /* ++ * init snd_soc_dai_driver ++ */ ++ drv[i].name = rdai[i].name; ++ drv[i].ops = &rsnd_soc_dai_ops; ++ if (pid >= 0) { ++ drv[i].playback.rates = RSND_RATES; ++ drv[i].playback.formats = RSND_FMTS; ++ drv[i].playback.channels_min = 2; ++ drv[i].playback.channels_max = 2; ++ } ++ if (cid >= 0) { ++ drv[i].capture.rates = RSND_RATES; ++ drv[i].capture.formats = RSND_FMTS; ++ drv[i].capture.channels_min = 2; ++ drv[i].capture.channels_max = 2; ++ } ++ ++ dev_dbg(dev, "%s (%d, %d) probed", rdai[i].name, pid, cid); ++ } ++ ++ priv->dai_nr = dai_nr; ++ priv->daidrv = drv; ++ priv->rdai = rdai; ++ ++ return 0; ++} ++ ++static void rsnd_dai_remove(struct platform_device *pdev, ++ struct rsnd_priv *priv) ++{ ++} ++ ++/* ++ * pcm ops ++ */ ++static struct snd_pcm_hardware rsnd_pcm_hardware = { ++ .info = SNDRV_PCM_INFO_INTERLEAVED | ++ SNDRV_PCM_INFO_MMAP | ++ SNDRV_PCM_INFO_MMAP_VALID | ++ SNDRV_PCM_INFO_PAUSE, ++ .formats = RSND_FMTS, ++ .rates = RSND_RATES, ++ .rate_min = 8000, ++ .rate_max = 192000, ++ .channels_min = 2, ++ .channels_max = 2, ++ .buffer_bytes_max = 64 * 1024, ++ .period_bytes_min = 32, ++ .period_bytes_max = 8192, ++ .periods_min = 1, ++ .periods_max = 32, ++ .fifo_size = 256, ++}; ++ ++static int rsnd_pcm_open(struct snd_pcm_substream *substream) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ int ret = 0; ++ ++ snd_soc_set_runtime_hwparams(substream, &rsnd_pcm_hardware); ++ ++ ret = snd_pcm_hw_constraint_integer(runtime, ++ SNDRV_PCM_HW_PARAM_PERIODS); ++ ++ return ret; ++} ++ ++static int rsnd_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *hw_params) ++{ ++ return snd_pcm_lib_malloc_pages(substream, ++ params_buffer_bytes(hw_params)); ++} ++ ++static snd_pcm_uframes_t rsnd_pointer(struct snd_pcm_substream *substream) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ struct snd_soc_dai *dai = rsnd_substream_to_dai(substream); ++ struct rsnd_dai *rdai = rsnd_dai_to_rdai(dai); ++ struct rsnd_dai_stream *io = rsnd_rdai_to_io(rdai, substream); ++ ++ return bytes_to_frames(runtime, io->byte_pos); ++} ++ ++static struct snd_pcm_ops rsnd_pcm_ops = { ++ .open = rsnd_pcm_open, ++ .ioctl = snd_pcm_lib_ioctl, ++ .hw_params = rsnd_hw_params, ++ .hw_free = snd_pcm_lib_free_pages, ++ .pointer = rsnd_pointer, ++}; ++ ++/* ++ * snd_soc_platform ++ */ ++ ++#define PREALLOC_BUFFER (32 * 1024) ++#define PREALLOC_BUFFER_MAX (32 * 1024) ++ ++static int rsnd_pcm_new(struct snd_soc_pcm_runtime *rtd) ++{ ++ return snd_pcm_lib_preallocate_pages_for_all( ++ rtd->pcm, ++ SNDRV_DMA_TYPE_DEV, ++ rtd->card->snd_card->dev, ++ PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); ++} ++ ++static void rsnd_pcm_free(struct snd_pcm *pcm) ++{ ++ snd_pcm_lib_preallocate_free_for_all(pcm); ++} ++ ++static struct snd_soc_platform_driver rsnd_soc_platform = { ++ .ops = &rsnd_pcm_ops, ++ .pcm_new = rsnd_pcm_new, ++ .pcm_free = rsnd_pcm_free, ++}; ++ ++static const struct snd_soc_component_driver rsnd_soc_component = { ++ .name = "rsnd", ++}; ++ ++/* ++ * rsnd probe ++ */ ++static int rsnd_probe(struct platform_device *pdev) ++{ ++ struct rcar_snd_info *info; ++ struct rsnd_priv *priv; ++ struct device *dev = &pdev->dev; ++ int ret; ++ ++ info = pdev->dev.platform_data; ++ if (!info) { ++ dev_err(dev, "driver needs R-Car sound information\n"); ++ return -ENODEV; ++ } ++ ++ /* ++ * init priv data ++ */ ++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) { ++ dev_err(dev, "priv allocate failed\n"); ++ return -ENODEV; ++ } ++ ++ priv->dev = dev; ++ priv->info = info; ++ spin_lock_init(&priv->lock); ++ ++ /* ++ * init each module ++ */ ++ ret = rsnd_dai_probe(pdev, info, priv); ++ if (ret < 0) ++ return ret; ++ ++ /* ++ * asoc register ++ */ ++ ret = snd_soc_register_platform(dev, &rsnd_soc_platform); ++ if (ret < 0) { ++ dev_err(dev, "cannot snd soc register\n"); ++ return ret; ++ } ++ ++ ret = snd_soc_register_component(dev, &rsnd_soc_component, ++ priv->daidrv, rsnd_dai_nr(priv)); ++ if (ret < 0) { ++ dev_err(dev, "cannot snd dai register\n"); ++ goto exit_snd_soc; ++ } ++ ++ dev_set_drvdata(dev, priv); ++ ++ pm_runtime_enable(dev); ++ ++ dev_info(dev, "probed\n"); ++ return ret; ++ ++exit_snd_soc: ++ snd_soc_unregister_platform(dev); ++ ++ return ret; ++} ++ ++static int rsnd_remove(struct platform_device *pdev) ++{ ++ struct rsnd_priv *priv = dev_get_drvdata(&pdev->dev); ++ ++ pm_runtime_disable(&pdev->dev); ++ ++ /* ++ * remove each module ++ */ ++ rsnd_dai_remove(pdev, priv); ++ ++ return 0; ++} ++ ++static struct platform_driver rsnd_driver = { ++ .driver = { ++ .name = "rcar_sound", ++ }, ++ .probe = rsnd_probe, ++ .remove = rsnd_remove, ++}; ++module_platform_driver(rsnd_driver); ++ ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("Renesas R-Car audio driver"); ++MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); ++MODULE_ALIAS("platform:rcar-pcm-audio"); +diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h +new file mode 100644 +index 00000000..8d04fd03 +--- /dev/null ++++ b/sound/soc/sh/rcar/rsnd.h +@@ -0,0 +1,94 @@ ++/* ++ * Renesas R-Car ++ * ++ * Copyright (C) 2013 Renesas Solutions Corp. ++ * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++#ifndef RSND_H ++#define RSND_H ++ ++#include <linux/clk.h> ++#include <linux/device.h> ++#include <linux/io.h> ++#include <linux/list.h> ++#include <linux/module.h> ++#include <sound/rcar_snd.h> ++#include <sound/soc.h> ++#include <sound/pcm_params.h> ++ ++/* ++ * pseudo register ++ * ++ * The register address offsets SRU/SCU/SSIU on Gen1/Gen2 are very different. ++ * This driver uses pseudo register in order to hide it. ++ * see gen1/gen2 for detail ++ */ ++struct rsnd_priv; ++struct rsnd_dai; ++struct rsnd_dai_stream; ++ ++/* ++ * R-Car sound DAI ++ */ ++#define RSND_DAI_NAME_SIZE 16 ++struct rsnd_dai_stream { ++ struct list_head head; /* head of rsnd_mod list */ ++ struct snd_pcm_substream *substream; ++ int byte_pos; ++ int period_pos; ++ int byte_per_period; ++ int next_period_byte; ++}; ++ ++struct rsnd_dai { ++ char name[RSND_DAI_NAME_SIZE]; ++ struct rsnd_dai_platform_info *info; /* rcar_snd.h */ ++ struct rsnd_dai_stream playback; ++ struct rsnd_dai_stream capture; ++ ++ int clk_master:1; ++ int bit_clk_inv:1; ++ int frm_clk_inv:1; ++ int sys_delay:1; ++ int data_alignment:1; ++}; ++ ++#define rsnd_dai_nr(priv) ((priv)->dai_nr) ++#define for_each_rsnd_dai(rdai, priv, i) \ ++ for (i = 0, (rdai) = rsnd_dai_get(priv, i); \ ++ i < rsnd_dai_nr(priv); \ ++ i++, (rdai) = rsnd_dai_get(priv, i)) ++ ++struct rsnd_dai *rsnd_dai_get(struct rsnd_priv *priv, int id); ++int rsnd_dai_is_play(struct rsnd_dai *rdai, struct rsnd_dai_stream *io); ++#define rsnd_dai_get_platform_info(rdai) ((rdai)->info) ++ ++void rsnd_dai_pointer_update(struct rsnd_dai_stream *io, int cnt); ++int rsnd_dai_pointer_offset(struct rsnd_dai_stream *io, int additional); ++ ++/* ++ * R-Car sound priv ++ */ ++struct rsnd_priv { ++ ++ struct device *dev; ++ struct rcar_snd_info *info; ++ spinlock_t lock; ++ ++ /* ++ * below value will be filled on rsnd_dai_probe() ++ */ ++ struct snd_soc_dai_driver *daidrv; ++ struct rsnd_dai *rdai; ++ int dai_nr; ++}; ++ ++#define rsnd_priv_to_dev(priv) ((priv)->dev) ++#define rsnd_lock(priv, flags) spin_lock_irqsave(&priv->lock, flags) ++#define rsnd_unlock(priv, flags) spin_unlock_irqrestore(&priv->lock, flags) ++ ++#endif +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0034-ASoC-fsi-reserve-prefetch-period-on-DMA-transferring.patch b/patches.renesas/0034-ASoC-fsi-reserve-prefetch-period-on-DMA-transferring.patch new file mode 100644 index 00000000000..b7b3cfec95a --- /dev/null +++ b/patches.renesas/0034-ASoC-fsi-reserve-prefetch-period-on-DMA-transferring.patch @@ -0,0 +1,129 @@ +From 6f456f8622290dde4729ff5275f1b3a0df0cc2b4 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Sun, 25 Aug 2013 23:36:23 -0700 +Subject: ASoC: fsi: reserve prefetch period on DMA transferring + +Current FSI is supporting DMAEngine transfer, +but, it needs to use work queue. +Therefore, DMA transfer settings might be late if there is heavy task. +This patch reserves next period beforehand on DMA transfer function. +Android sound will be breaking up without this patch. + +Tested-by: Tomohito Esaki <etom@igel.co.jp> +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Mark Brown <broonie@linaro.org> +(cherry picked from commit 53110a256a334c5e01db2d94c5306b4880a9180e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/fsi.c | 51 +++++++++++++++++++++++++++++++++------------------ + 1 file changed, 33 insertions(+), 18 deletions(-) + +diff --git a/sound/soc/sh/fsi.c b/sound/soc/sh/fsi.c +index 30390260..b33ca7cd 100644 +--- a/sound/soc/sh/fsi.c ++++ b/sound/soc/sh/fsi.c +@@ -235,6 +235,8 @@ struct fsi_stream { + struct sh_dmae_slave slave; /* see fsi_handler_init() */ + struct work_struct work; + dma_addr_t dma; ++ int loop_cnt; ++ int additional_pos; + }; + + struct fsi_clk { +@@ -1289,6 +1291,8 @@ static int fsi_dma_init(struct fsi_priv *fsi, struct fsi_stream *io) + io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | + BUSOP_SET(16, PACKAGE_16BITBUS_STREAM); + ++ io->loop_cnt = 2; /* push 1st, 2nd period first, then 3rd, 4th... */ ++ io->additional_pos = 0; + io->dma = dma_map_single(dai->dev, runtime->dma_area, + snd_pcm_lib_buffer_bytes(io->substream), dir); + return 0; +@@ -1305,11 +1309,15 @@ static int fsi_dma_quit(struct fsi_priv *fsi, struct fsi_stream *io) + return 0; + } + +-static dma_addr_t fsi_dma_get_area(struct fsi_stream *io) ++static dma_addr_t fsi_dma_get_area(struct fsi_stream *io, int additional) + { + struct snd_pcm_runtime *runtime = io->substream->runtime; ++ int period = io->period_pos + additional; + +- return io->dma + samples_to_bytes(runtime, io->buff_sample_pos); ++ if (period >= runtime->periods) ++ period = 0; ++ ++ return io->dma + samples_to_bytes(runtime, period * io->period_samples); + } + + static void fsi_dma_complete(void *data) +@@ -1321,7 +1329,7 @@ static void fsi_dma_complete(void *data) + enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ? + DMA_TO_DEVICE : DMA_FROM_DEVICE; + +- dma_sync_single_for_cpu(dai->dev, fsi_dma_get_area(io), ++ dma_sync_single_for_cpu(dai->dev, fsi_dma_get_area(io, 0), + samples_to_bytes(runtime, io->period_samples), dir); + + io->buff_sample_pos += io->period_samples; +@@ -1347,7 +1355,7 @@ static void fsi_dma_do_work(struct work_struct *work) + struct snd_pcm_runtime *runtime; + enum dma_data_direction dir; + int is_play = fsi_stream_is_play(fsi, io); +- int len; ++ int len, i; + dma_addr_t buf; + + if (!fsi_stream_is_working(fsi, io)) +@@ -1357,26 +1365,33 @@ static void fsi_dma_do_work(struct work_struct *work) + runtime = io->substream->runtime; + dir = is_play ? DMA_TO_DEVICE : DMA_FROM_DEVICE; + len = samples_to_bytes(runtime, io->period_samples); +- buf = fsi_dma_get_area(io); + +- dma_sync_single_for_device(dai->dev, buf, len, dir); ++ for (i = 0; i < io->loop_cnt; i++) { ++ buf = fsi_dma_get_area(io, io->additional_pos); + +- desc = dmaengine_prep_slave_single(io->chan, buf, len, dir, +- DMA_PREP_INTERRUPT | DMA_CTRL_ACK); +- if (!desc) { +- dev_err(dai->dev, "dmaengine_prep_slave_sg() fail\n"); +- return; +- } ++ dma_sync_single_for_device(dai->dev, buf, len, dir); + +- desc->callback = fsi_dma_complete; +- desc->callback_param = io; ++ desc = dmaengine_prep_slave_single(io->chan, buf, len, dir, ++ DMA_PREP_INTERRUPT | DMA_CTRL_ACK); ++ if (!desc) { ++ dev_err(dai->dev, "dmaengine_prep_slave_sg() fail\n"); ++ return; ++ } + +- if (dmaengine_submit(desc) < 0) { +- dev_err(dai->dev, "tx_submit() fail\n"); +- return; ++ desc->callback = fsi_dma_complete; ++ desc->callback_param = io; ++ ++ if (dmaengine_submit(desc) < 0) { ++ dev_err(dai->dev, "tx_submit() fail\n"); ++ return; ++ } ++ ++ dma_async_issue_pending(io->chan); ++ ++ io->additional_pos = 1; + } + +- dma_async_issue_pending(io->chan); ++ io->loop_cnt = 1; + + /* + * FIXME +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0035-backlight-Add-GPIO-based-backlight-driver.patch b/patches.renesas/0035-backlight-Add-GPIO-based-backlight-driver.patch new file mode 100644 index 00000000000..e7bdc2f79ff --- /dev/null +++ b/patches.renesas/0035-backlight-Add-GPIO-based-backlight-driver.patch @@ -0,0 +1,221 @@ +From 72dfc32a288895f831514271e6f5ac28cce979b0 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 4 Jul 2013 21:13:24 +0200 +Subject: backlight: Add GPIO-based backlight driver + +The GPIO backlight driver controls the backlight in on/off mode through +a single GPIO. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Acked-by: Jingoo Han <jg1.han@samsung.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 8b770e3c9824c98eafe67950ad6e41e09ec9c98a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/video/backlight/Kconfig | 7 ++ + drivers/video/backlight/Makefile | 1 + + drivers/video/backlight/gpio_backlight.c | 133 +++++++++++++++++++++++++++ + include/linux/platform_data/gpio_backlight.h | 21 +++++ + 4 files changed, 162 insertions(+) + create mode 100644 drivers/video/backlight/gpio_backlight.c + create mode 100644 include/linux/platform_data/gpio_backlight.h + +diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig +index d5ab6583..5ab64237 100644 +--- a/drivers/video/backlight/Kconfig ++++ b/drivers/video/backlight/Kconfig +@@ -425,6 +425,13 @@ config BACKLIGHT_AS3711 + If you have an Austrian Microsystems AS3711 say Y to enable the + backlight driver. + ++config BACKLIGHT_GPIO ++ tristate "Generic GPIO based Backlight Driver" ++ depends on GPIOLIB ++ help ++ If you have a LCD backlight adjustable by GPIO, say Y to enable ++ this driver. ++ + endif # BACKLIGHT_CLASS_DEVICE + + endif # BACKLIGHT_LCD_SUPPORT +diff --git a/drivers/video/backlight/Makefile b/drivers/video/backlight/Makefile +index 92711fe6..65698a88 100644 +--- a/drivers/video/backlight/Makefile ++++ b/drivers/video/backlight/Makefile +@@ -32,6 +32,7 @@ obj-$(CONFIG_BACKLIGHT_DA903X) += da903x_bl.o + obj-$(CONFIG_BACKLIGHT_DA9052) += da9052_bl.o + obj-$(CONFIG_BACKLIGHT_EP93XX) += ep93xx_bl.o + obj-$(CONFIG_BACKLIGHT_GENERIC) += generic_bl.o ++obj-$(CONFIG_BACKLIGHT_GPIO) += gpio_backlight.o + obj-$(CONFIG_BACKLIGHT_HP680) += hp680_bl.o + obj-$(CONFIG_BACKLIGHT_HP700) += jornada720_bl.o + obj-$(CONFIG_BACKLIGHT_LM3533) += lm3533_bl.o +diff --git a/drivers/video/backlight/gpio_backlight.c b/drivers/video/backlight/gpio_backlight.c +new file mode 100644 +index 00000000..5fa217f9 +--- /dev/null ++++ b/drivers/video/backlight/gpio_backlight.c +@@ -0,0 +1,133 @@ ++/* ++ * gpio_backlight.c - Simple GPIO-controlled backlight ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include <linux/backlight.h> ++#include <linux/err.h> ++#include <linux/fb.h> ++#include <linux/gpio.h> ++#include <linux/init.h> ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/platform_data/gpio_backlight.h> ++#include <linux/platform_device.h> ++#include <linux/slab.h> ++ ++struct gpio_backlight { ++ struct device *dev; ++ struct device *fbdev; ++ ++ int gpio; ++ int active; ++}; ++ ++static int gpio_backlight_update_status(struct backlight_device *bl) ++{ ++ struct gpio_backlight *gbl = bl_get_data(bl); ++ int brightness = bl->props.brightness; ++ ++ if (bl->props.power != FB_BLANK_UNBLANK || ++ bl->props.fb_blank != FB_BLANK_UNBLANK || ++ bl->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK)) ++ brightness = 0; ++ ++ gpio_set_value(gbl->gpio, brightness ? gbl->active : !gbl->active); ++ ++ return 0; ++} ++ ++static int gpio_backlight_get_brightness(struct backlight_device *bl) ++{ ++ return bl->props.brightness; ++} ++ ++static int gpio_backlight_check_fb(struct backlight_device *bl, ++ struct fb_info *info) ++{ ++ struct gpio_backlight *gbl = bl_get_data(bl); ++ ++ return gbl->fbdev == NULL || gbl->fbdev == info->dev; ++} ++ ++static const struct backlight_ops gpio_backlight_ops = { ++ .options = BL_CORE_SUSPENDRESUME, ++ .update_status = gpio_backlight_update_status, ++ .get_brightness = gpio_backlight_get_brightness, ++ .check_fb = gpio_backlight_check_fb, ++}; ++ ++static int gpio_backlight_probe(struct platform_device *pdev) ++{ ++ struct gpio_backlight_platform_data *pdata = pdev->dev.platform_data; ++ struct backlight_properties props; ++ struct backlight_device *bl; ++ struct gpio_backlight *gbl; ++ int ret; ++ ++ if (!pdata) { ++ dev_err(&pdev->dev, "failed to find platform data\n"); ++ return -ENODEV; ++ } ++ ++ gbl = devm_kzalloc(&pdev->dev, sizeof(*gbl), GFP_KERNEL); ++ if (gbl == NULL) ++ return -ENOMEM; ++ ++ gbl->dev = &pdev->dev; ++ gbl->fbdev = pdata->fbdev; ++ gbl->gpio = pdata->gpio; ++ gbl->active = pdata->active_low ? 0 : 1; ++ ++ ret = devm_gpio_request_one(gbl->dev, gbl->gpio, GPIOF_DIR_OUT | ++ (gbl->active ? GPIOF_INIT_LOW ++ : GPIOF_INIT_HIGH), ++ pdata->name); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "unable to request GPIO\n"); ++ return ret; ++ } ++ ++ memset(&props, 0, sizeof(props)); ++ props.type = BACKLIGHT_RAW; ++ props.max_brightness = 1; ++ bl = backlight_device_register(dev_name(&pdev->dev), &pdev->dev, gbl, ++ &gpio_backlight_ops, &props); ++ if (IS_ERR(bl)) { ++ dev_err(&pdev->dev, "failed to register backlight\n"); ++ return PTR_ERR(bl); ++ } ++ ++ bl->props.brightness = pdata->def_value; ++ backlight_update_status(bl); ++ ++ platform_set_drvdata(pdev, bl); ++ return 0; ++} ++ ++static int gpio_backlight_remove(struct platform_device *pdev) ++{ ++ struct backlight_device *bl = platform_get_drvdata(pdev); ++ ++ backlight_device_unregister(bl); ++ return 0; ++} ++ ++static struct platform_driver gpio_backlight_driver = { ++ .driver = { ++ .name = "gpio-backlight", ++ .owner = THIS_MODULE, ++ }, ++ .probe = gpio_backlight_probe, ++ .remove = gpio_backlight_remove, ++}; ++ ++module_platform_driver(gpio_backlight_driver); ++ ++MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>"); ++MODULE_DESCRIPTION("GPIO-based Backlight Driver"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:gpio-backlight"); +diff --git a/include/linux/platform_data/gpio_backlight.h b/include/linux/platform_data/gpio_backlight.h +new file mode 100644 +index 00000000..5ae0d9c8 +--- /dev/null ++++ b/include/linux/platform_data/gpio_backlight.h +@@ -0,0 +1,21 @@ ++/* ++ * gpio_backlight.h - Simple GPIO-controlled backlight ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++#ifndef __GPIO_BACKLIGHT_H__ ++#define __GPIO_BACKLIGHT_H__ ++ ++struct device; ++ ++struct gpio_backlight_platform_data { ++ struct device *fbdev; ++ int gpio; ++ int def_value; ++ bool active_low; ++ const char *name; ++}; ++ ++#endif +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0036-pwm-Add-Renesas-TPU-PWM-driver.patch b/patches.renesas/0036-pwm-Add-Renesas-TPU-PWM-driver.patch new file mode 100644 index 00000000000..f26d23c78e1 --- /dev/null +++ b/patches.renesas/0036-pwm-Add-Renesas-TPU-PWM-driver.patch @@ -0,0 +1,566 @@ +From 7dfac374156fab07fc159f395deee4dca31ed6e4 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 13 Jun 2013 18:54:44 +0200 +Subject: pwm: Add Renesas TPU PWM driver + +The Timer Pulse Unit (TPU) is a 4-channels 16-bit timer used to generate +waveforms. This driver exposes PWM functions through the PWM API for +other drivers to use. + +The code is loosely based on the leds-renesas-tpu driver by Magnus Damm +and the TPU PWM driver shipped in the Armadillo EVA 800 kernel sources. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Axel Lin <axel.lin@ingics.com> +Tested-by: Simon Horman <horms@verge.net.au> +Signed-off-by: Thierry Reding <thierry.reding@gmail.com> +(cherry picked from commit 99b82abb0a35b07310ea6334257829af168c8e08) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pwm/Kconfig | 10 + + drivers/pwm/Makefile | 1 + + drivers/pwm/pwm-renesas-tpu.c | 475 ++++++++++++++++++++++++++ + include/linux/platform_data/pwm-renesas-tpu.h | 16 + + 4 files changed, 502 insertions(+) + create mode 100644 drivers/pwm/pwm-renesas-tpu.c + create mode 100644 include/linux/platform_data/pwm-renesas-tpu.h + +diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig +index 115b6445..14a9122f 100644 +--- a/drivers/pwm/Kconfig ++++ b/drivers/pwm/Kconfig +@@ -115,6 +115,16 @@ config PWM_PXA + To compile this driver as a module, choose M here: the module + will be called pwm-pxa. + ++config PWM_RENESAS_TPU ++ tristate "Renesas TPU PWM support" ++ depends on ARCH_SHMOBILE ++ help ++ This driver exposes the Timer Pulse Unit (TPU) PWM controller found ++ in Renesas chips through the PWM API. ++ ++ To compile this driver as a module, choose M here: the module ++ will be called pwm-renesas-tpu. ++ + config PWM_SAMSUNG + tristate "Samsung PWM support" + depends on PLAT_SAMSUNG +diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile +index 94ba21e2..5aa815fd 100644 +--- a/drivers/pwm/Makefile ++++ b/drivers/pwm/Makefile +@@ -8,6 +8,7 @@ obj-$(CONFIG_PWM_LPC32XX) += pwm-lpc32xx.o + obj-$(CONFIG_PWM_MXS) += pwm-mxs.o + obj-$(CONFIG_PWM_PUV3) += pwm-puv3.o + obj-$(CONFIG_PWM_PXA) += pwm-pxa.o ++obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o + obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o + obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o + obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o +diff --git a/drivers/pwm/pwm-renesas-tpu.c b/drivers/pwm/pwm-renesas-tpu.c +new file mode 100644 +index 00000000..96e0cc48 +--- /dev/null ++++ b/drivers/pwm/pwm-renesas-tpu.c +@@ -0,0 +1,475 @@ ++/* ++ * R-Mobile TPU PWM driver ++ * ++ * Copyright (C) 2012 Renesas Solutions Corp. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <linux/clk.h> ++#include <linux/err.h> ++#include <linux/io.h> ++#include <linux/init.h> ++#include <linux/ioport.h> ++#include <linux/module.h> ++#include <linux/mutex.h> ++#include <linux/platform_data/pwm-renesas-tpu.h> ++#include <linux/platform_device.h> ++#include <linux/pm_runtime.h> ++#include <linux/pwm.h> ++#include <linux/slab.h> ++#include <linux/spinlock.h> ++ ++#define TPU_TSTR 0x00 /* Timer start register (shared) */ ++ ++#define TPU_TCRn 0x00 /* Timer control register */ ++#define TPU_TCR_CCLR_NONE (0 << 5) ++#define TPU_TCR_CCLR_TGRA (1 << 5) ++#define TPU_TCR_CCLR_TGRB (2 << 5) ++#define TPU_TCR_CCLR_TGRC (5 << 5) ++#define TPU_TCR_CCLR_TGRD (6 << 5) ++#define TPU_TCR_CKEG_RISING (0 << 3) ++#define TPU_TCR_CKEG_FALLING (1 << 3) ++#define TPU_TCR_CKEG_BOTH (2 << 3) ++#define TPU_TMDRn 0x04 /* Timer mode register */ ++#define TPU_TMDR_BFWT (1 << 6) ++#define TPU_TMDR_BFB (1 << 5) ++#define TPU_TMDR_BFA (1 << 4) ++#define TPU_TMDR_MD_NORMAL (0 << 0) ++#define TPU_TMDR_MD_PWM (2 << 0) ++#define TPU_TIORn 0x08 /* Timer I/O control register */ ++#define TPU_TIOR_IOA_0 (0 << 0) ++#define TPU_TIOR_IOA_0_CLR (1 << 0) ++#define TPU_TIOR_IOA_0_SET (2 << 0) ++#define TPU_TIOR_IOA_0_TOGGLE (3 << 0) ++#define TPU_TIOR_IOA_1 (4 << 0) ++#define TPU_TIOR_IOA_1_CLR (5 << 0) ++#define TPU_TIOR_IOA_1_SET (6 << 0) ++#define TPU_TIOR_IOA_1_TOGGLE (7 << 0) ++#define TPU_TIERn 0x0c /* Timer interrupt enable register */ ++#define TPU_TSRn 0x10 /* Timer status register */ ++#define TPU_TCNTn 0x14 /* Timer counter */ ++#define TPU_TGRAn 0x18 /* Timer general register A */ ++#define TPU_TGRBn 0x1c /* Timer general register B */ ++#define TPU_TGRCn 0x20 /* Timer general register C */ ++#define TPU_TGRDn 0x24 /* Timer general register D */ ++ ++#define TPU_CHANNEL_OFFSET 0x10 ++#define TPU_CHANNEL_SIZE 0x40 ++ ++enum tpu_pin_state { ++ TPU_PIN_INACTIVE, /* Pin is driven inactive */ ++ TPU_PIN_PWM, /* Pin is driven by PWM */ ++ TPU_PIN_ACTIVE, /* Pin is driven active */ ++}; ++ ++struct tpu_device; ++ ++struct tpu_pwm_device { ++ bool timer_on; /* Whether the timer is running */ ++ ++ struct tpu_device *tpu; ++ unsigned int channel; /* Channel number in the TPU */ ++ ++ enum pwm_polarity polarity; ++ unsigned int prescaler; ++ u16 period; ++ u16 duty; ++}; ++ ++struct tpu_device { ++ struct platform_device *pdev; ++ struct tpu_pwm_platform_data *pdata; ++ struct pwm_chip chip; ++ spinlock_t lock; ++ ++ void __iomem *base; ++ struct clk *clk; ++}; ++ ++#define to_tpu_device(c) container_of(c, struct tpu_device, chip) ++ ++static void tpu_pwm_write(struct tpu_pwm_device *pwm, int reg_nr, u16 value) ++{ ++ void __iomem *base = pwm->tpu->base + TPU_CHANNEL_OFFSET ++ + pwm->channel * TPU_CHANNEL_SIZE; ++ ++ iowrite16(value, base + reg_nr); ++} ++ ++static void tpu_pwm_set_pin(struct tpu_pwm_device *pwm, ++ enum tpu_pin_state state) ++{ ++ static const char * const states[] = { "inactive", "PWM", "active" }; ++ ++ dev_dbg(&pwm->tpu->pdev->dev, "%u: configuring pin as %s\n", ++ pwm->channel, states[state]); ++ ++ switch (state) { ++ case TPU_PIN_INACTIVE: ++ tpu_pwm_write(pwm, TPU_TIORn, ++ pwm->polarity == PWM_POLARITY_INVERSED ? ++ TPU_TIOR_IOA_1 : TPU_TIOR_IOA_0); ++ break; ++ case TPU_PIN_PWM: ++ tpu_pwm_write(pwm, TPU_TIORn, ++ pwm->polarity == PWM_POLARITY_INVERSED ? ++ TPU_TIOR_IOA_0_SET : TPU_TIOR_IOA_1_CLR); ++ break; ++ case TPU_PIN_ACTIVE: ++ tpu_pwm_write(pwm, TPU_TIORn, ++ pwm->polarity == PWM_POLARITY_INVERSED ? ++ TPU_TIOR_IOA_0 : TPU_TIOR_IOA_1); ++ break; ++ } ++} ++ ++static void tpu_pwm_start_stop(struct tpu_pwm_device *pwm, int start) ++{ ++ unsigned long flags; ++ u16 value; ++ ++ spin_lock_irqsave(&pwm->tpu->lock, flags); ++ value = ioread16(pwm->tpu->base + TPU_TSTR); ++ ++ if (start) ++ value |= 1 << pwm->channel; ++ else ++ value &= ~(1 << pwm->channel); ++ ++ iowrite16(value, pwm->tpu->base + TPU_TSTR); ++ spin_unlock_irqrestore(&pwm->tpu->lock, flags); ++} ++ ++static int tpu_pwm_timer_start(struct tpu_pwm_device *pwm) ++{ ++ int ret; ++ ++ if (!pwm->timer_on) { ++ /* Wake up device and enable clock. */ ++ pm_runtime_get_sync(&pwm->tpu->pdev->dev); ++ ret = clk_prepare_enable(pwm->tpu->clk); ++ if (ret) { ++ dev_err(&pwm->tpu->pdev->dev, "cannot enable clock\n"); ++ return ret; ++ } ++ pwm->timer_on = true; ++ } ++ ++ /* ++ * Make sure the channel is stopped, as we need to reconfigure it ++ * completely. First drive the pin to the inactive state to avoid ++ * glitches. ++ */ ++ tpu_pwm_set_pin(pwm, TPU_PIN_INACTIVE); ++ tpu_pwm_start_stop(pwm, false); ++ ++ /* ++ * - Clear TCNT on TGRB match ++ * - Count on rising edge ++ * - Set prescaler ++ * - Output 0 until TGRA, output 1 until TGRB (active low polarity) ++ * - Output 1 until TGRA, output 0 until TGRB (active high polarity ++ * - PWM mode ++ */ ++ tpu_pwm_write(pwm, TPU_TCRn, TPU_TCR_CCLR_TGRB | TPU_TCR_CKEG_RISING | ++ pwm->prescaler); ++ tpu_pwm_write(pwm, TPU_TMDRn, TPU_TMDR_MD_PWM); ++ tpu_pwm_set_pin(pwm, TPU_PIN_PWM); ++ tpu_pwm_write(pwm, TPU_TGRAn, pwm->duty); ++ tpu_pwm_write(pwm, TPU_TGRBn, pwm->period); ++ ++ dev_dbg(&pwm->tpu->pdev->dev, "%u: TGRA 0x%04x TGRB 0x%04x\n", ++ pwm->channel, pwm->duty, pwm->period); ++ ++ /* Start the channel. */ ++ tpu_pwm_start_stop(pwm, true); ++ ++ return 0; ++} ++ ++static void tpu_pwm_timer_stop(struct tpu_pwm_device *pwm) ++{ ++ if (!pwm->timer_on) ++ return; ++ ++ /* Disable channel. */ ++ tpu_pwm_start_stop(pwm, false); ++ ++ /* Stop clock and mark device as idle. */ ++ clk_disable_unprepare(pwm->tpu->clk); ++ pm_runtime_put(&pwm->tpu->pdev->dev); ++ ++ pwm->timer_on = false; ++} ++ ++/* ----------------------------------------------------------------------------- ++ * PWM API ++ */ ++ ++static int tpu_pwm_request(struct pwm_chip *chip, struct pwm_device *_pwm) ++{ ++ struct tpu_device *tpu = to_tpu_device(chip); ++ struct tpu_pwm_device *pwm; ++ ++ if (_pwm->hwpwm >= TPU_CHANNEL_MAX) ++ return -EINVAL; ++ ++ pwm = kzalloc(sizeof(*pwm), GFP_KERNEL); ++ if (pwm == NULL) ++ return -ENOMEM; ++ ++ pwm->tpu = tpu; ++ pwm->channel = _pwm->hwpwm; ++ pwm->polarity = tpu->pdata ? tpu->pdata->channels[pwm->channel].polarity ++ : PWM_POLARITY_NORMAL; ++ pwm->prescaler = 0; ++ pwm->period = 0; ++ pwm->duty = 0; ++ ++ pwm->timer_on = false; ++ ++ pwm_set_chip_data(_pwm, pwm); ++ ++ return 0; ++} ++ ++static void tpu_pwm_free(struct pwm_chip *chip, struct pwm_device *_pwm) ++{ ++ struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm); ++ ++ tpu_pwm_timer_stop(pwm); ++ kfree(pwm); ++} ++ ++static int tpu_pwm_config(struct pwm_chip *chip, struct pwm_device *_pwm, ++ int duty_ns, int period_ns) ++{ ++ static const unsigned int prescalers[] = { 1, 4, 16, 64 }; ++ struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm); ++ struct tpu_device *tpu = to_tpu_device(chip); ++ unsigned int prescaler; ++ bool duty_only = false; ++ u32 clk_rate; ++ u32 period; ++ u32 duty; ++ int ret; ++ ++ /* ++ * Pick a prescaler to avoid overflowing the counter. ++ * TODO: Pick the highest acceptable prescaler. ++ */ ++ clk_rate = clk_get_rate(tpu->clk); ++ ++ for (prescaler = 0; prescaler < ARRAY_SIZE(prescalers); ++prescaler) { ++ period = clk_rate / prescalers[prescaler] ++ / (NSEC_PER_SEC / period_ns); ++ if (period <= 0xffff) ++ break; ++ } ++ ++ if (prescaler == ARRAY_SIZE(prescalers) || period == 0) { ++ dev_err(&tpu->pdev->dev, "clock rate mismatch\n"); ++ return -ENOTSUPP; ++ } ++ ++ if (duty_ns) { ++ duty = clk_rate / prescalers[prescaler] ++ / (NSEC_PER_SEC / duty_ns); ++ if (duty > period) ++ return -EINVAL; ++ } else { ++ duty = 0; ++ } ++ ++ dev_dbg(&tpu->pdev->dev, ++ "rate %u, prescaler %u, period %u, duty %u\n", ++ clk_rate, prescalers[prescaler], period, duty); ++ ++ if (pwm->prescaler == prescaler && pwm->period == period) ++ duty_only = true; ++ ++ pwm->prescaler = prescaler; ++ pwm->period = period; ++ pwm->duty = duty; ++ ++ /* If the channel is disabled we're done. */ ++ if (!test_bit(PWMF_ENABLED, &_pwm->flags)) ++ return 0; ++ ++ if (duty_only && pwm->timer_on) { ++ /* ++ * If only the duty cycle changed and the timer is already ++ * running, there's no need to reconfigure it completely, Just ++ * modify the duty cycle. ++ */ ++ tpu_pwm_write(pwm, TPU_TGRAn, pwm->duty); ++ dev_dbg(&tpu->pdev->dev, "%u: TGRA 0x%04x\n", pwm->channel, ++ pwm->duty); ++ } else { ++ /* Otherwise perform a full reconfiguration. */ ++ ret = tpu_pwm_timer_start(pwm); ++ if (ret < 0) ++ return ret; ++ } ++ ++ if (duty == 0 || duty == period) { ++ /* ++ * To avoid running the timer when not strictly required, handle ++ * 0% and 100% duty cycles as fixed levels and stop the timer. ++ */ ++ tpu_pwm_set_pin(pwm, duty ? TPU_PIN_ACTIVE : TPU_PIN_INACTIVE); ++ tpu_pwm_timer_stop(pwm); ++ } ++ ++ return 0; ++} ++ ++static int tpu_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *_pwm, ++ enum pwm_polarity polarity) ++{ ++ struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm); ++ ++ pwm->polarity = polarity; ++ ++ return 0; ++} ++ ++static int tpu_pwm_enable(struct pwm_chip *chip, struct pwm_device *_pwm) ++{ ++ struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm); ++ int ret; ++ ++ ret = tpu_pwm_timer_start(pwm); ++ if (ret < 0) ++ return ret; ++ ++ /* ++ * To avoid running the timer when not strictly required, handle 0% and ++ * 100% duty cycles as fixed levels and stop the timer. ++ */ ++ if (pwm->duty == 0 || pwm->duty == pwm->period) { ++ tpu_pwm_set_pin(pwm, pwm->duty ? ++ TPU_PIN_ACTIVE : TPU_PIN_INACTIVE); ++ tpu_pwm_timer_stop(pwm); ++ } ++ ++ return 0; ++} ++ ++static void tpu_pwm_disable(struct pwm_chip *chip, struct pwm_device *_pwm) ++{ ++ struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm); ++ ++ /* The timer must be running to modify the pin output configuration. */ ++ tpu_pwm_timer_start(pwm); ++ tpu_pwm_set_pin(pwm, TPU_PIN_INACTIVE); ++ tpu_pwm_timer_stop(pwm); ++} ++ ++static const struct pwm_ops tpu_pwm_ops = { ++ .request = tpu_pwm_request, ++ .free = tpu_pwm_free, ++ .config = tpu_pwm_config, ++ .set_polarity = tpu_pwm_set_polarity, ++ .enable = tpu_pwm_enable, ++ .disable = tpu_pwm_disable, ++ .owner = THIS_MODULE, ++}; ++ ++/* ----------------------------------------------------------------------------- ++ * Probe and remove ++ */ ++ ++static int tpu_probe(struct platform_device *pdev) ++{ ++ struct tpu_device *tpu; ++ struct resource *res; ++ int ret; ++ ++ tpu = devm_kzalloc(&pdev->dev, sizeof(*tpu), GFP_KERNEL); ++ if (tpu == NULL) { ++ dev_err(&pdev->dev, "failed to allocate driver data\n"); ++ return -ENOMEM; ++ } ++ ++ tpu->pdata = pdev->dev.platform_data; ++ ++ /* Map memory, get clock and pin control. */ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) { ++ dev_err(&pdev->dev, "failed to get I/O memory\n"); ++ return -ENXIO; ++ } ++ ++ tpu->base = devm_ioremap_resource(&pdev->dev, res); ++ if (tpu->base == NULL) { ++ dev_err(&pdev->dev, "failed to remap I/O memory\n"); ++ return -ENXIO; ++ } ++ ++ tpu->clk = devm_clk_get(&pdev->dev, NULL); ++ if (IS_ERR(tpu->clk)) { ++ dev_err(&pdev->dev, "cannot get clock\n"); ++ return PTR_ERR(tpu->clk); ++ } ++ ++ /* Initialize and register the device. */ ++ platform_set_drvdata(pdev, tpu); ++ ++ spin_lock_init(&tpu->lock); ++ tpu->pdev = pdev; ++ ++ tpu->chip.dev = &pdev->dev; ++ tpu->chip.ops = &tpu_pwm_ops; ++ tpu->chip.base = -1; ++ tpu->chip.npwm = TPU_CHANNEL_MAX; ++ ++ ret = pwmchip_add(&tpu->chip); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "failed to register PWM chip\n"); ++ return ret; ++ } ++ ++ dev_info(&pdev->dev, "TPU PWM %d registered\n", tpu->pdev->id); ++ ++ pm_runtime_enable(&pdev->dev); ++ ++ return 0; ++} ++ ++static int tpu_remove(struct platform_device *pdev) ++{ ++ struct tpu_device *tpu = platform_get_drvdata(pdev); ++ int ret; ++ ++ ret = pwmchip_remove(&tpu->chip); ++ if (ret) ++ return ret; ++ ++ pm_runtime_disable(&pdev->dev); ++ ++ return 0; ++} ++ ++static struct platform_driver tpu_driver = { ++ .probe = tpu_probe, ++ .remove = tpu_remove, ++ .driver = { ++ .name = "renesas-tpu-pwm", ++ .owner = THIS_MODULE, ++ } ++}; ++ ++module_platform_driver(tpu_driver); ++ ++MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>"); ++MODULE_DESCRIPTION("Renesas TPU PWM Driver"); ++MODULE_LICENSE("GPL v2"); +diff --git a/include/linux/platform_data/pwm-renesas-tpu.h b/include/linux/platform_data/pwm-renesas-tpu.h +new file mode 100644 +index 00000000..a7220b10 +--- /dev/null ++++ b/include/linux/platform_data/pwm-renesas-tpu.h +@@ -0,0 +1,16 @@ ++#ifndef __PWM_RENESAS_TPU_H__ ++#define __PWM_RENESAS_TPU_H__ ++ ++#include <linux/pwm.h> ++ ++#define TPU_CHANNEL_MAX 4 ++ ++struct tpu_pwm_channel_data { ++ enum pwm_polarity polarity; ++}; ++ ++struct tpu_pwm_platform_data { ++ struct tpu_pwm_channel_data channels[TPU_CHANNEL_MAX]; ++}; ++ ++#endif /* __PWM_RENESAS_TPU_H__ */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0037-pwm-renesas-tpu-fix-return-value-check-in-tpu_probe.patch b/patches.renesas/0037-pwm-renesas-tpu-fix-return-value-check-in-tpu_probe.patch new file mode 100644 index 00000000000..db823033eaf --- /dev/null +++ b/patches.renesas/0037-pwm-renesas-tpu-fix-return-value-check-in-tpu_probe.patch @@ -0,0 +1,39 @@ +From f1fd37c8dc7513d68bccc445553098095448bcec Mon Sep 17 00:00:00 2001 +From: Wei Yongjun <yongjun_wei@trendmicro.com.cn> +Date: Tue, 25 Jun 2013 10:09:57 +0800 +Subject: pwm: renesas-tpu: fix return value check in tpu_probe() + +In case of error, the function devm_ioremap_resource() returns ERR_PTR() +and never returns NULL. The NULL test in the return value check should +be replaced with IS_ERR(). + +Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> +Reviewed-by: Axel Lin <axel.lin@ingics.com> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Thierry Reding <thierry.reding@gmail.com> +(cherry picked from commit 00cf99ee00c9f1241359c8ee5ca9230318e27a57) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pwm/pwm-renesas-tpu.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +diff --git a/drivers/pwm/pwm-renesas-tpu.c b/drivers/pwm/pwm-renesas-tpu.c +index 96e0cc48..03c1aa3c 100644 +--- a/drivers/pwm/pwm-renesas-tpu.c ++++ b/drivers/pwm/pwm-renesas-tpu.c +@@ -410,10 +410,8 @@ static int tpu_probe(struct platform_device *pdev) + } + + tpu->base = devm_ioremap_resource(&pdev->dev, res); +- if (tpu->base == NULL) { +- dev_err(&pdev->dev, "failed to remap I/O memory\n"); +- return -ENXIO; +- } ++ if (IS_ERR(tpu->base)) ++ return PTR_ERR(tpu->base); + + tpu->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(tpu->clk)) { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0038-pwm-renesas-tpu-Add-MODULE_ALIAS-to-make-module-auto.patch b/patches.renesas/0038-pwm-renesas-tpu-Add-MODULE_ALIAS-to-make-module-auto.patch new file mode 100644 index 00000000000..6de4c1a47fa --- /dev/null +++ b/patches.renesas/0038-pwm-renesas-tpu-Add-MODULE_ALIAS-to-make-module-auto.patch @@ -0,0 +1,28 @@ +From c8d32248b8fbdc350eaeee23051c30ca46662dc7 Mon Sep 17 00:00:00 2001 +From: Axel Lin <axel.lin@ingics.com> +Date: Wed, 26 Jun 2013 00:25:02 +0800 +Subject: pwm: renesas-tpu: Add MODULE_ALIAS to make module auto loading work + +This driver can be built as module, add MODULE_ALIAS to make module auto loading +work. + +Signed-off-by: Axel Lin <axel.lin@ingics.com> +Signed-off-by: Thierry Reding <thierry.reding@gmail.com> +(cherry picked from commit 71077bc8db67f560453d62c48e3bec467ec6b37f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pwm/pwm-renesas-tpu.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/pwm/pwm-renesas-tpu.c b/drivers/pwm/pwm-renesas-tpu.c +index 03c1aa3c..26008927 100644 +--- a/drivers/pwm/pwm-renesas-tpu.c ++++ b/drivers/pwm/pwm-renesas-tpu.c +@@ -471,3 +471,4 @@ module_platform_driver(tpu_driver); + MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>"); + MODULE_DESCRIPTION("Renesas TPU PWM Driver"); + MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:renesas-tpu-pwm"); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0039-pwm-renesas-tpu-Add-DT-support.patch b/patches.renesas/0039-pwm-renesas-tpu-Add-DT-support.patch new file mode 100644 index 00000000000..6e14a510db3 --- /dev/null +++ b/patches.renesas/0039-pwm-renesas-tpu-Add-DT-support.patch @@ -0,0 +1,158 @@ +From 88e52bb403941d0a0c4bdcd8788b2e0175054143 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 26 Jul 2013 00:27:41 +0200 +Subject: pwm: renesas-tpu: Add DT support + +Specify DT bindings for the TPU PWM controller and add OF support to the +driver. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Acked-by: Stephen Warren <swarren@nvidia.com> +Signed-off-by: Thierry Reding <thierry.reding@gmail.com> +(cherry picked from commit 382457e562bbb1ea7d94923e58fcbac9e981ff18) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + .../devicetree/bindings/pwm/renesas,tpu-pwm.txt | 28 +++++++++++++++ + drivers/pwm/pwm-renesas-tpu.c | 41 ++++++++++++++++++---- + 2 files changed, 62 insertions(+), 7 deletions(-) + create mode 100644 Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt + +diff --git a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt +new file mode 100644 +index 00000000..b067e84a +--- /dev/null ++++ b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt +@@ -0,0 +1,28 @@ ++* Renesas R-Car Timer Pulse Unit PWM Controller ++ ++Required Properties: ++ ++ - compatible: should be one of the following. ++ - "renesas,tpu-r8a73a4": for R8A77A4 (R-Mobile APE6) compatible PWM controller. ++ - "renesas,tpu-r8a7740": for R8A7740 (R-Mobile A1) compatible PWM controller. ++ - "renesas,tpu-r8a7790": for R8A7790 (R-Car H2) compatible PWM controller. ++ - "renesas,tpu-sh7372": for SH7372 (SH-Mobile AP4) compatible PWM controller. ++ - "renesas,tpu": for generic R-Car TPU PWM controller. ++ ++ - reg: Base address and length of each memory resource used by the PWM ++ controller hardware module. ++ ++ - #pwm-cells: should be 3. See pwm.txt in this directory for a description of ++ the cells format. The only third cell flag supported by this binding is ++ PWM_POLARITY_INVERTED. ++ ++Please refer to pwm.txt in this directory for details of the common PWM bindings ++used by client devices. ++ ++Example: R8A7740 (R-Car A1) TPU controller node ++ ++ tpu: pwm@e6600000 { ++ compatible = "renesas,tpu-r8a7740", "renesas,tpu"; ++ reg = <0xe6600000 0x100>; ++ #pwm-cells = <3>; ++ }; +diff --git a/drivers/pwm/pwm-renesas-tpu.c b/drivers/pwm/pwm-renesas-tpu.c +index 26008927..3eeffff6 100644 +--- a/drivers/pwm/pwm-renesas-tpu.c ++++ b/drivers/pwm/pwm-renesas-tpu.c +@@ -20,6 +20,7 @@ + #include <linux/ioport.h> + #include <linux/module.h> + #include <linux/mutex.h> ++#include <linux/of.h> + #include <linux/platform_data/pwm-renesas-tpu.h> + #include <linux/platform_device.h> + #include <linux/pm_runtime.h> +@@ -86,7 +87,7 @@ struct tpu_pwm_device { + + struct tpu_device { + struct platform_device *pdev; +- struct tpu_pwm_platform_data *pdata; ++ enum pwm_polarity polarities[TPU_CHANNEL_MAX]; + struct pwm_chip chip; + spinlock_t lock; + +@@ -228,8 +229,7 @@ static int tpu_pwm_request(struct pwm_chip *chip, struct pwm_device *_pwm) + + pwm->tpu = tpu; + pwm->channel = _pwm->hwpwm; +- pwm->polarity = tpu->pdata ? tpu->pdata->channels[pwm->channel].polarity +- : PWM_POLARITY_NORMAL; ++ pwm->polarity = tpu->polarities[pwm->channel]; + pwm->prescaler = 0; + pwm->period = 0; + pwm->duty = 0; +@@ -388,6 +388,16 @@ static const struct pwm_ops tpu_pwm_ops = { + * Probe and remove + */ + ++static void tpu_parse_pdata(struct tpu_device *tpu) ++{ ++ struct tpu_pwm_platform_data *pdata = tpu->pdev->dev.platform_data; ++ unsigned int i; ++ ++ for (i = 0; i < ARRAY_SIZE(tpu->polarities); ++i) ++ tpu->polarities[i] = pdata ? pdata->channels[i].polarity ++ : PWM_POLARITY_NORMAL; ++} ++ + static int tpu_probe(struct platform_device *pdev) + { + struct tpu_device *tpu; +@@ -400,7 +410,11 @@ static int tpu_probe(struct platform_device *pdev) + return -ENOMEM; + } + +- tpu->pdata = pdev->dev.platform_data; ++ spin_lock_init(&tpu->lock); ++ tpu->pdev = pdev; ++ ++ /* Initialize device configuration from platform data. */ ++ tpu_parse_pdata(tpu); + + /* Map memory, get clock and pin control. */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +@@ -422,11 +436,10 @@ static int tpu_probe(struct platform_device *pdev) + /* Initialize and register the device. */ + platform_set_drvdata(pdev, tpu); + +- spin_lock_init(&tpu->lock); +- tpu->pdev = pdev; +- + tpu->chip.dev = &pdev->dev; + tpu->chip.ops = &tpu_pwm_ops; ++ tpu->chip.of_xlate = of_pwm_xlate_with_flags; ++ tpu->chip.of_pwm_n_cells = 3; + tpu->chip.base = -1; + tpu->chip.npwm = TPU_CHANNEL_MAX; + +@@ -457,12 +470,26 @@ static int tpu_remove(struct platform_device *pdev) + return 0; + } + ++#ifdef CONFIG_OF ++static const struct of_device_id tpu_of_table[] = { ++ { .compatible = "renesas,tpu-r8a73a4", }, ++ { .compatible = "renesas,tpu-r8a7740", }, ++ { .compatible = "renesas,tpu-r8a7790", }, ++ { .compatible = "renesas,tpu-sh7372", }, ++ { .compatible = "renesas,tpu", }, ++ { }, ++}; ++ ++MODULE_DEVICE_TABLE(of, tpu_of_table); ++#endif ++ + static struct platform_driver tpu_driver = { + .probe = tpu_probe, + .remove = tpu_remove, + .driver = { + .name = "renesas-tpu-pwm", + .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(tpu_of_table), + } + }; + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0040-pwm-simplify-use-of-devm_ioremap_resource.patch b/patches.renesas/0040-pwm-simplify-use-of-devm_ioremap_resource.patch new file mode 100644 index 00000000000..e16e51e8008 --- /dev/null +++ b/patches.renesas/0040-pwm-simplify-use-of-devm_ioremap_resource.patch @@ -0,0 +1,97 @@ +From 9d218abdb7925e8d184beea77b6da269e59ce3d4 Mon Sep 17 00:00:00 2001 +From: Julia Lawall <Julia.Lawall@lip6.fr> +Date: Wed, 14 Aug 2013 11:11:25 +0200 +Subject: pwm: simplify use of devm_ioremap_resource + +Remove unneeded error handling on the result of a call to +platform_get_resource when the value is passed to devm_ioremap_resource. + +Move the call to platform_get_resource adjacent to the call to +devm_ioremap_resource to make the connection between them more clear. + +A simplified version of the semantic patch that makes this change is as +follows: (http://coccinelle.lip6.fr/) + +// <smpl> +@@ +expression pdev,res,n,e,e1; +expression ret != 0; +identifier l; +@@ + +- res = platform_get_resource(pdev, IORESOURCE_MEM, n); + ... when != res +- if (res == NULL) { ... \(goto l;\|return ret;\) } + ... when != res ++ res = platform_get_resource(pdev, IORESOURCE_MEM, n); + e = devm_ioremap_resource(e1, res); +// </smpl> + +Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> +Acked-by: Viresh Kumar <viresh.kumar@linaro.org> +Signed-off-by: Thierry Reding <thierry.reding@gmail.com> +(cherry picked from commit 88d5a2e6ffaa32e2a09a994872ca10aca07a36e9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pwm/pwm-lpc32xx.c | 3 --- + drivers/pwm/pwm-renesas-tpu.c | 5 ----- + drivers/pwm/pwm-spear.c | 7 +------ + 3 files changed, 1 insertion(+), 14 deletions(-) + +diff --git a/drivers/pwm/pwm-lpc32xx.c b/drivers/pwm/pwm-lpc32xx.c +index 8272883c..7f469d26 100644 +--- a/drivers/pwm/pwm-lpc32xx.c ++++ b/drivers/pwm/pwm-lpc32xx.c +@@ -124,9 +124,6 @@ static int lpc32xx_pwm_probe(struct platform_device *pdev) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- if (!res) +- return -EINVAL; +- + lpc32xx->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(lpc32xx->base)) + return PTR_ERR(lpc32xx->base); +diff --git a/drivers/pwm/pwm-renesas-tpu.c b/drivers/pwm/pwm-renesas-tpu.c +index 3eeffff6..aff6ba9b 100644 +--- a/drivers/pwm/pwm-renesas-tpu.c ++++ b/drivers/pwm/pwm-renesas-tpu.c +@@ -418,11 +418,6 @@ static int tpu_probe(struct platform_device *pdev) + + /* Map memory, get clock and pin control. */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- if (!res) { +- dev_err(&pdev->dev, "failed to get I/O memory\n"); +- return -ENXIO; +- } +- + tpu->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(tpu->base)) + return PTR_ERR(tpu->base); +diff --git a/drivers/pwm/pwm-spear.c b/drivers/pwm/pwm-spear.c +index 6d99e2cb..8af6ea8f 100644 +--- a/drivers/pwm/pwm-spear.c ++++ b/drivers/pwm/pwm-spear.c +@@ -178,18 +178,13 @@ static int spear_pwm_probe(struct platform_device *pdev) + int ret; + u32 val; + +- r = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- if (!r) { +- dev_err(&pdev->dev, "no memory resources defined\n"); +- return -ENODEV; +- } +- + pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); + if (!pc) { + dev_err(&pdev->dev, "failed to allocate memory\n"); + return -ENOMEM; + } + ++ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pc->mmio_base = devm_ioremap_resource(&pdev->dev, r); + if (IS_ERR(pc->mmio_base)) + return PTR_ERR(pc->mmio_base); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0041-phy-rcar-usb-remove-EHCI-internal-buffer-setup.patch b/patches.renesas/0041-phy-rcar-usb-remove-EHCI-internal-buffer-setup.patch new file mode 100644 index 00000000000..90da34a6a41 --- /dev/null +++ b/patches.renesas/0041-phy-rcar-usb-remove-EHCI-internal-buffer-setup.patch @@ -0,0 +1,110 @@ +From fa0067b3df1d6a1c7eea1bfb4f986fd81b699794 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Sun, 2 Jun 2013 01:42:26 +0400 +Subject: phy-rcar-usb: remove EHCI internal buffer setup + +Now that the EHCI internal buffer setup is done by the platform code, we can +remove such code from this driver as it never really belonged here. We also +no longer need the 2nd memory region now (2nd EHCI controller is simply missing +in e.g. R8A7778 SoC). + +The patch has been tested on the Marzen and BOCK-W boards. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Acked-by: Felipe Balbi <balbi@ti.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 463c824bb708b47a7a249bde07af4d701cacd54e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/phy/phy-rcar-usb.c | 28 ++++------------------------ + 1 file changed, 4 insertions(+), 24 deletions(-) + +diff --git a/drivers/usb/phy/phy-rcar-usb.c b/drivers/usb/phy/phy-rcar-usb.c +index a35681b0..4893dbde 100644 +--- a/drivers/usb/phy/phy-rcar-usb.c ++++ b/drivers/usb/phy/phy-rcar-usb.c +@@ -23,8 +23,6 @@ + #define USBEH0 0x080C + #define USBOH0 0x081C + #define USBCTL0 0x0858 +-#define EIIBC1 0x0094 +-#define EIIBC2 0x009C + + /* USBPCTRL1 */ + #define PHY_RST (1 << 2) +@@ -40,7 +38,6 @@ struct rcar_usb_phy_priv { + spinlock_t lock; + + void __iomem *reg0; +- void __iomem *reg1; + int counter; + }; + +@@ -59,7 +56,6 @@ static int rcar_usb_phy_init(struct usb_phy *phy) + struct rcar_usb_phy_priv *priv = usb_phy_to_priv(phy); + struct device *dev = phy->dev; + void __iomem *reg0 = priv->reg0; +- void __iomem *reg1 = priv->reg1; + int i; + u32 val; + unsigned long flags; +@@ -97,19 +93,6 @@ static int rcar_usb_phy_init(struct usb_phy *phy) + iowrite32(0x00000000, (reg0 + USBPCTRL0)); + + /* +- * EHCI IP internal buffer setting +- * EHCI IP internal buffer enable +- * +- * These are recommended value of a datasheet +- * see [USB :: EHCI internal buffer setting] +- */ +- iowrite32(0x00ff0040, (reg0 + EIIBC1)); +- iowrite32(0x00ff0040, (reg1 + EIIBC1)); +- +- iowrite32(0x00000001, (reg0 + EIIBC2)); +- iowrite32(0x00000001, (reg1 + EIIBC2)); +- +- /* + * Bus alignment settings + */ + +@@ -145,14 +128,13 @@ static void rcar_usb_phy_shutdown(struct usb_phy *phy) + static int rcar_usb_phy_probe(struct platform_device *pdev) + { + struct rcar_usb_phy_priv *priv; +- struct resource *res0, *res1; ++ struct resource *res0; + struct device *dev = &pdev->dev; +- void __iomem *reg0, *reg1; ++ void __iomem *reg0; + int ret; + + res0 = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- res1 = platform_get_resource(pdev, IORESOURCE_MEM, 1); +- if (!res0 || !res1) { ++ if (!res0) { + dev_err(dev, "Not enough platform resources\n"); + return -EINVAL; + } +@@ -164,8 +146,7 @@ static int rcar_usb_phy_probe(struct platform_device *pdev) + * this driver can't use devm_request_and_ioremap(dev, res) here + */ + reg0 = devm_ioremap_nocache(dev, res0->start, resource_size(res0)); +- reg1 = devm_ioremap_nocache(dev, res1->start, resource_size(res1)); +- if (!reg0 || !reg1) { ++ if (!reg0) { + dev_err(dev, "ioremap error\n"); + return -ENOMEM; + } +@@ -177,7 +158,6 @@ static int rcar_usb_phy_probe(struct platform_device *pdev) + } + + priv->reg0 = reg0; +- priv->reg1 = reg1; + priv->counter = 0; + priv->phy.dev = dev; + priv->phy.label = dev_name(dev); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0042-phy-rcar-usb-correct-base-address.patch b/patches.renesas/0042-phy-rcar-usb-correct-base-address.patch new file mode 100644 index 00000000000..03378d527b3 --- /dev/null +++ b/patches.renesas/0042-phy-rcar-usb-correct-base-address.patch @@ -0,0 +1,77 @@ +From 48cc6fb24264915a9ada52d5202b9a0b4741bb4d Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Sun, 2 Jun 2013 01:50:25 +0400 +Subject: phy-rcar-usb: correct base address + +The memory region that is used by the driver overlaps EHCI and OHCI register +regions for absolutely no reason now -- fix it by adding offset of 0x800 to +the base address, changing the register #define's accordingly. This has extra +positive effect that we now can use devm_ioremap_resource()... + +Note that the driver and the SoC code have to be in one patch to keep the code +bisectable... + +The patch has been tested on the Marzen board. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Acked-by: Felipe Balbi <balbi@ti.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 725bf9dcafe16aa69c8ab34c63ba36c6eb4492f2) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + arch/arm/mach-shmobile/setup-r8a7779.c +--- + drivers/usb/phy/phy-rcar-usb.c | 28 ++++++++++------------------ + 1 file changed, 10 insertions(+), 18 deletions(-) + +diff --git a/drivers/usb/phy/phy-rcar-usb.c b/drivers/usb/phy/phy-rcar-usb.c +index 4893dbde..d636cc74 100644 +--- a/drivers/usb/phy/phy-rcar-usb.c ++++ b/drivers/usb/phy/phy-rcar-usb.c +@@ -16,13 +16,13 @@ + #include <linux/spinlock.h> + #include <linux/module.h> + +-/* USBH common register */ +-#define USBPCTRL0 0x0800 +-#define USBPCTRL1 0x0804 +-#define USBST 0x0808 +-#define USBEH0 0x080C +-#define USBOH0 0x081C +-#define USBCTL0 0x0858 ++/* REGS block */ ++#define USBPCTRL0 0x00 ++#define USBPCTRL1 0x04 ++#define USBST 0x08 ++#define USBEH0 0x0C ++#define USBOH0 0x1C ++#define USBCTL0 0x58 + + /* USBPCTRL1 */ + #define PHY_RST (1 << 2) +@@ -139,17 +139,9 @@ static int rcar_usb_phy_probe(struct platform_device *pdev) + return -EINVAL; + } + +- /* +- * CAUTION +- * +- * Because this phy address is also mapped under OHCI/EHCI address area, +- * this driver can't use devm_request_and_ioremap(dev, res) here +- */ +- reg0 = devm_ioremap_nocache(dev, res0->start, resource_size(res0)); +- if (!reg0) { +- dev_err(dev, "ioremap error\n"); +- return -ENOMEM; +- } ++ reg0 = devm_ioremap_resource(dev, res0); ++ if (IS_ERR(reg0)) ++ return PTR_ERR(reg0); + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0043-phy-rcar-usb-add-platform-data.patch b/patches.renesas/0043-phy-rcar-usb-add-platform-data.patch new file mode 100644 index 00000000000..7caa9d7d116 --- /dev/null +++ b/patches.renesas/0043-phy-rcar-usb-add-platform-data.patch @@ -0,0 +1,57 @@ +From d8f13c383c13c1f5ac533cba4462c6c4d2bb543f Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Sun, 2 Jun 2013 01:52:28 +0400 +Subject: phy-rcar-usb: add platform data + +Currently the driver hard-codes USBPCTRL0 register to 0. It is wrong since this +register contains board-specific USB ports configuration and so its value should +be somehow passed via the platform data. Add the global header file containing +'struct rcar_phy_platform_data' consisting of the various bit fields describing +USB ports' pin configuration. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Acked-by: Felipe Balbi <balbi@ti.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 6a82e2a83e568dc121326b4bab24035ce7a2f50e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + include/linux/platform_data/usb-rcar-phy.h | 26 ++++++++++++++++++++++++++ + 1 file changed, 26 insertions(+) + create mode 100644 include/linux/platform_data/usb-rcar-phy.h + +diff --git a/include/linux/platform_data/usb-rcar-phy.h b/include/linux/platform_data/usb-rcar-phy.h +new file mode 100644 +index 00000000..c49f35ab +--- /dev/null ++++ b/include/linux/platform_data/usb-rcar-phy.h +@@ -0,0 +1,26 @@ ++/* ++ * Copyright (C) 2013 Renesas Solutions Corp. ++ * Copyright (C) 2013 Cogent Embedded, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef __USB_RCAR_PHY_H ++#define __USB_RCAR_PHY_H ++ ++#include <linux/types.h> ++ ++struct rcar_phy_platform_data { ++ bool port1_func:1; /* true: port 1 used by function, false: host */ ++ unsigned penc1:1; /* Output of the PENC1 pin in function mode */ ++ struct { /* Overcurrent pin control for ports 0..2 */ ++ bool select_3_3v:1; /* true: USB_OVCn pin, false: OVCn pin */ ++ /* Set to false on port 1 in function mode */ ++ bool active_high:1; /* true: active high, false: active low */ ++ /* Set to true on port 1 in function mode */ ++ } ovc_pin[3]; ++}; ++ ++#endif /* __USB_RCAR_PHY_H */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0044-phy-rcar-usb-handle-platform-data.patch b/patches.renesas/0044-phy-rcar-usb-handle-platform-data.patch new file mode 100644 index 00000000000..83eb4b38e03 --- /dev/null +++ b/patches.renesas/0044-phy-rcar-usb-handle-platform-data.patch @@ -0,0 +1,133 @@ +From 22e453504b30dc6b98e667ecf3869fbba233fa56 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Sun, 2 Jun 2013 01:57:18 +0400 +Subject: phy-rcar-usb: handle platform data + +Set the USBPCTRL0 register from the passed platform data in rcar_usb_phy_init(); +don't reset it to 0 in rcar_usb_phy_shutdown() anymore as that does not make +sense. Also, don't allow the driver's probe to succeed when the platform data +are not supplied with a device. + +The patch has been tested on the Marzen and BOCK-W boards. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Acked-by: Simon Horman <horms+renesas@verge.net.au> +Acked-by: Felipe Balbi <balbi@ti.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 7173e59e6b5f9cbde3ece66ae664454edcac6382) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/phy/phy-rcar-usb.c | 51 +++++++++++++++++++++++++++++++++++++----- + 1 file changed, 45 insertions(+), 6 deletions(-) + +diff --git a/drivers/usb/phy/phy-rcar-usb.c b/drivers/usb/phy/phy-rcar-usb.c +index d636cc74..823b2bb8 100644 +--- a/drivers/usb/phy/phy-rcar-usb.c ++++ b/drivers/usb/phy/phy-rcar-usb.c +@@ -1,8 +1,9 @@ + /* + * Renesas R-Car USB phy driver + * +- * Copyright (C) 2012 Renesas Solutions Corp. ++ * Copyright (C) 2012-2013 Renesas Solutions Corp. + * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> ++ * Copyright (C) 2013 Cogent Embedded, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as +@@ -15,6 +16,7 @@ + #include <linux/platform_device.h> + #include <linux/spinlock.h> + #include <linux/module.h> ++#include <linux/platform_data/usb-rcar-phy.h> + + /* REGS block */ + #define USBPCTRL0 0x00 +@@ -24,6 +26,25 @@ + #define USBOH0 0x1C + #define USBCTL0 0x58 + ++/* USBPCTRL0 */ ++#define OVC2 (1 << 10) /* Switches the OVC input pin for port 2: */ ++ /* 1: USB_OVC2, 0: OVC2 */ ++#define OVC1_VBUS1 (1 << 9) /* Switches the OVC input pin for port 1: */ ++ /* 1: USB_OVC1, 0: OVC1/VBUS1 */ ++ /* Function mode: set to 0 */ ++#define OVC0 (1 << 8) /* Switches the OVC input pin for port 0: */ ++ /* 1: USB_OVC0 pin, 0: OVC0 */ ++#define OVC2_ACT (1 << 6) /* Host mode: OVC2 polarity: */ ++ /* 1: active-high, 0: active-low */ ++#define PENC (1 << 4) /* Function mode: output level of PENC1 pin: */ ++ /* 1: high, 0: low */ ++#define OVC0_ACT (1 << 3) /* Host mode: OVC0 polarity: */ ++ /* 1: active-high, 0: active-low */ ++#define OVC1_ACT (1 << 1) /* Host mode: OVC1 polarity: */ ++ /* 1: active-high, 0: active-low */ ++ /* Function mode: be sure to set to 1 */ ++#define PORT1 (1 << 0) /* Selects port 1 mode: */ ++ /* 1: function, 0: host */ + /* USBPCTRL1 */ + #define PHY_RST (1 << 2) + #define PLL_ENB (1 << 1) +@@ -55,7 +76,9 @@ static int rcar_usb_phy_init(struct usb_phy *phy) + { + struct rcar_usb_phy_priv *priv = usb_phy_to_priv(phy); + struct device *dev = phy->dev; ++ struct rcar_phy_platform_data *pdata = dev->platform_data; + void __iomem *reg0 = priv->reg0; ++ static const u8 ovcn_act[] = { OVC0_ACT, OVC1_ACT, OVC2_ACT }; + int i; + u32 val; + unsigned long flags; +@@ -89,8 +112,21 @@ static int rcar_usb_phy_init(struct usb_phy *phy) + /* (4) USB-PHY reset clear */ + iowrite32(PHY_ENB | PLL_ENB | PHY_RST, (reg0 + USBPCTRL1)); + +- /* set platform specific port settings */ +- iowrite32(0x00000000, (reg0 + USBPCTRL0)); ++ /* Board specific port settings */ ++ val = 0; ++ if (pdata->port1_func) ++ val |= PORT1; ++ if (pdata->penc1) ++ val |= PENC; ++ for (i = 0; i < 3; i++) { ++ /* OVCn bits follow each other in the right order */ ++ if (pdata->ovc_pin[i].select_3_3v) ++ val |= OVC0 << i; ++ /* OVCn_ACT bits are spaced by irregular intervals */ ++ if (pdata->ovc_pin[i].active_high) ++ val |= ovcn_act[i]; ++ } ++ iowrite32(val, (reg0 + USBPCTRL0)); + + /* + * Bus alignment settings +@@ -117,10 +153,8 @@ static void rcar_usb_phy_shutdown(struct usb_phy *phy) + + spin_lock_irqsave(&priv->lock, flags); + +- if (priv->counter-- == 1) { /* last user */ +- iowrite32(0x00000000, (reg0 + USBPCTRL0)); ++ if (priv->counter-- == 1) /* last user */ + iowrite32(0x00000000, (reg0 + USBPCTRL1)); +- } + + spin_unlock_irqrestore(&priv->lock, flags); + } +@@ -133,6 +167,11 @@ static int rcar_usb_phy_probe(struct platform_device *pdev) + void __iomem *reg0; + int ret; + ++ if (!pdev->dev.platform_data) { ++ dev_err(dev, "No platform data\n"); ++ return -EINVAL; ++ } ++ + res0 = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res0) { + dev_err(dev, "Not enough platform resources\n"); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0045-phy-rcar-usb-add-R8A7778-support.patch b/patches.renesas/0045-phy-rcar-usb-add-R8A7778-support.patch new file mode 100644 index 00000000000..651045d3846 --- /dev/null +++ b/patches.renesas/0045-phy-rcar-usb-add-R8A7778-support.patch @@ -0,0 +1,185 @@ +From 08b540c8b1f152555e58d39ba03a9b820553bac1 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Sun, 9 Jun 2013 00:34:36 +0400 +Subject: phy-rcar-usb: add R8A7778 support + +The driver currently only supports R8A7779 SoC. Compared to it, R8A7778 USB-PHY +has extra register range containing two high-speed signal quality characteristic +control registers which should be set up during USB-PHY startup depending on +whether a ferrite bead is in use or not. So, we now handle an optional second +memory range in the driver's probe method, add the 'ferrite_bead' field to the +driver's platform data, and add an extra (optional) step to the USB-PHY startup +routine which sets up the extended registers. + +Also mark in the driver's Kconfig section that R8A7778 is now supported and +generally clarify that section, uppercasing the word "phy" and also changing +the module name that got lost in the big driver rename, while at it... + +The patch has been tested on the Marzen and BOCK-W boards. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Felipe Balbi <balbi@ti.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 54407f190c8d542572a9547ba5460d811810b6e4) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/phy/Kconfig | 10 ++++---- + drivers/usb/phy/phy-rcar-usb.c | 37 +++++++++++++++++++++++++----- + include/linux/platform_data/usb-rcar-phy.h | 4 +++- + 3 files changed, 39 insertions(+), 12 deletions(-) + +diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig +index 2311b1e4..c75cba7a 100644 +--- a/drivers/usb/phy/Kconfig ++++ b/drivers/usb/phy/Kconfig +@@ -186,15 +186,15 @@ config USB_MXS_PHY + MXS Phy is used by some of the i.MX SoCs, for example imx23/28/6x. + + config USB_RCAR_PHY +- tristate "Renesas R-Car USB phy support" ++ tristate "Renesas R-Car USB PHY support" + depends on USB || USB_GADGET + help +- Say Y here to add support for the Renesas R-Car USB phy driver. +- This chip is typically used as USB phy for USB host, gadget. +- This driver supports: R8A7779 ++ Say Y here to add support for the Renesas R-Car USB common PHY driver. ++ This chip is typically used as USB PHY for USB host, gadget. ++ This driver supports R8A7778 and R8A7779. + + To compile this driver as a module, choose M here: the +- module will be called rcar-phy. ++ module will be called phy-rcar-usb. + + config USB_ULPI + bool "Generic ULPI Transceiver Driver" +diff --git a/drivers/usb/phy/phy-rcar-usb.c b/drivers/usb/phy/phy-rcar-usb.c +index 823b2bb8..ae909408 100644 +--- a/drivers/usb/phy/phy-rcar-usb.c ++++ b/drivers/usb/phy/phy-rcar-usb.c +@@ -26,15 +26,21 @@ + #define USBOH0 0x1C + #define USBCTL0 0x58 + ++/* High-speed signal quality characteristic control registers (R8A7778 only) */ ++#define HSQCTL1 0x24 ++#define HSQCTL2 0x28 ++ + /* USBPCTRL0 */ +-#define OVC2 (1 << 10) /* Switches the OVC input pin for port 2: */ ++#define OVC2 (1 << 10) /* (R8A7779 only) */ ++ /* Switches the OVC input pin for port 2: */ + /* 1: USB_OVC2, 0: OVC2 */ + #define OVC1_VBUS1 (1 << 9) /* Switches the OVC input pin for port 1: */ + /* 1: USB_OVC1, 0: OVC1/VBUS1 */ + /* Function mode: set to 0 */ + #define OVC0 (1 << 8) /* Switches the OVC input pin for port 0: */ + /* 1: USB_OVC0 pin, 0: OVC0 */ +-#define OVC2_ACT (1 << 6) /* Host mode: OVC2 polarity: */ ++#define OVC2_ACT (1 << 6) /* (R8A7779 only) */ ++ /* Host mode: OVC2 polarity: */ + /* 1: active-high, 0: active-low */ + #define PENC (1 << 4) /* Function mode: output level of PENC1 pin: */ + /* 1: high, 0: low */ +@@ -59,6 +65,7 @@ struct rcar_usb_phy_priv { + spinlock_t lock; + + void __iomem *reg0; ++ void __iomem *reg1; + int counter; + }; + +@@ -78,6 +85,7 @@ static int rcar_usb_phy_init(struct usb_phy *phy) + struct device *dev = phy->dev; + struct rcar_phy_platform_data *pdata = dev->platform_data; + void __iomem *reg0 = priv->reg0; ++ void __iomem *reg1 = priv->reg1; + static const u8 ovcn_act[] = { OVC0_ACT, OVC1_ACT, OVC2_ACT }; + int i; + u32 val; +@@ -96,7 +104,16 @@ static int rcar_usb_phy_init(struct usb_phy *phy) + /* (2) start USB-PHY internal PLL */ + iowrite32(PHY_ENB | PLL_ENB, (reg0 + USBPCTRL1)); + +- /* (3) USB module status check */ ++ /* (3) set USB-PHY in accord with the conditions of usage */ ++ if (reg1) { ++ u32 hsqctl1 = pdata->ferrite_bead ? 0x41 : 0; ++ u32 hsqctl2 = pdata->ferrite_bead ? 0x0d : 7; ++ ++ iowrite32(hsqctl1, reg1 + HSQCTL1); ++ iowrite32(hsqctl2, reg1 + HSQCTL2); ++ } ++ ++ /* (4) USB module status check */ + for (i = 0; i < 1024; i++) { + udelay(10); + val = ioread32(reg0 + USBST); +@@ -109,7 +126,7 @@ static int rcar_usb_phy_init(struct usb_phy *phy) + goto phy_init_end; + } + +- /* (4) USB-PHY reset clear */ ++ /* (5) USB-PHY reset clear */ + iowrite32(PHY_ENB | PLL_ENB | PHY_RST, (reg0 + USBPCTRL1)); + + /* Board specific port settings */ +@@ -162,9 +179,9 @@ static void rcar_usb_phy_shutdown(struct usb_phy *phy) + static int rcar_usb_phy_probe(struct platform_device *pdev) + { + struct rcar_usb_phy_priv *priv; +- struct resource *res0; ++ struct resource *res0, *res1; + struct device *dev = &pdev->dev; +- void __iomem *reg0; ++ void __iomem *reg0, *reg1 = NULL; + int ret; + + if (!pdev->dev.platform_data) { +@@ -182,6 +199,13 @@ static int rcar_usb_phy_probe(struct platform_device *pdev) + if (IS_ERR(reg0)) + return PTR_ERR(reg0); + ++ res1 = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ if (res1) { ++ reg1 = devm_ioremap_resource(dev, res1); ++ if (IS_ERR(reg1)) ++ return PTR_ERR(reg1); ++ } ++ + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) { + dev_err(dev, "priv data allocation error\n"); +@@ -189,6 +213,7 @@ static int rcar_usb_phy_probe(struct platform_device *pdev) + } + + priv->reg0 = reg0; ++ priv->reg1 = reg1; + priv->counter = 0; + priv->phy.dev = dev; + priv->phy.label = dev_name(dev); +diff --git a/include/linux/platform_data/usb-rcar-phy.h b/include/linux/platform_data/usb-rcar-phy.h +index c49f35ab..8ec6964a 100644 +--- a/include/linux/platform_data/usb-rcar-phy.h ++++ b/include/linux/platform_data/usb-rcar-phy.h +@@ -13,6 +13,8 @@ + #include <linux/types.h> + + struct rcar_phy_platform_data { ++ bool ferrite_bead:1; /* (R8A7778 only) */ ++ + bool port1_func:1; /* true: port 1 used by function, false: host */ + unsigned penc1:1; /* Output of the PENC1 pin in function mode */ + struct { /* Overcurrent pin control for ports 0..2 */ +@@ -20,7 +22,7 @@ struct rcar_phy_platform_data { + /* Set to false on port 1 in function mode */ + bool active_high:1; /* true: active high, false: active low */ + /* Set to true on port 1 in function mode */ +- } ovc_pin[3]; ++ } ovc_pin[3]; /* (R8A7778 only has 2 ports) */ + }; + + #endif /* __USB_RCAR_PHY_H */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0046-usb-phy-don-t-check-resource-with-devm_ioremap_resou.patch b/patches.renesas/0046-usb-phy-don-t-check-resource-with-devm_ioremap_resou.patch new file mode 100644 index 00000000000..e14bf067851 --- /dev/null +++ b/patches.renesas/0046-usb-phy-don-t-check-resource-with-devm_ioremap_resou.patch @@ -0,0 +1,35 @@ +From 3551f00a48c6534cea6b59819879b0b0daf4b298 Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa@the-dreams.de> +Date: Tue, 23 Jul 2013 20:01:52 +0200 +Subject: usb: phy: don't check resource with devm_ioremap_resource + +devm_ioremap_resource does sanity checks on the given resource. No need to +duplicate this in the driver. + +Signed-off-by: Wolfram Sang <wsa@the-dreams.de> +Signed-off-by: Felipe Balbi <balbi@ti.com> +(cherry picked from commit fda7130354271b55eea50a4f58ea8540c9971295) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/phy/phy-rcar-usb.c | 5 ----- + 1 file changed, 5 deletions(-) + +diff --git a/drivers/usb/phy/phy-rcar-usb.c b/drivers/usb/phy/phy-rcar-usb.c +index ae909408..deb7f97f 100644 +--- a/drivers/usb/phy/phy-rcar-usb.c ++++ b/drivers/usb/phy/phy-rcar-usb.c +@@ -190,11 +190,6 @@ static int rcar_usb_phy_probe(struct platform_device *pdev) + } + + res0 = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- if (!res0) { +- dev_err(dev, "Not enough platform resources\n"); +- return -EINVAL; +- } +- + reg0 = devm_ioremap_resource(dev, res0); + if (IS_ERR(reg0)) + return PTR_ERR(reg0); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0047-of-introduce-of_parse_phandle_with_fixed_args.patch b/patches.renesas/0047-of-introduce-of_parse_phandle_with_fixed_args.patch new file mode 100644 index 00000000000..1a50a6d2621 --- /dev/null +++ b/patches.renesas/0047-of-introduce-of_parse_phandle_with_fixed_args.patch @@ -0,0 +1,152 @@ +From f144e82df6dccf7109aa821f436669ab9d439f23 Mon Sep 17 00:00:00 2001 +From: Stephen Warren <swarren@nvidia.com> +Date: Wed, 14 Aug 2013 15:27:10 -0600 +Subject: of: introduce of_parse_phandle_with_fixed_args + +This is identical to of_parse_phandle_with_args(), except that the +number of argument cells is fixed, rather than being parsed out of the +node referenced by each phandle. + +Signed-off-by: Stephen Warren <swarren@nvidia.com> +Acked-by: Mark Rutland <mark.rutland@arm.com> +Signed-off-by: Grant Likely <grant.likely@linaro.org> +(cherry picked from commit 035fd9482274bf43858b00e0ff95179af66df8e8) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/of/base.c | 66 +++++++++++++++++++++++++++++++++++++++++++++++------- + include/linux/of.h | 10 +++++++++ + 2 files changed, 68 insertions(+), 8 deletions(-) + +diff --git a/drivers/of/base.c b/drivers/of/base.c +index 1d10b4ec..32dce2e6 100644 +--- a/drivers/of/base.c ++++ b/drivers/of/base.c +@@ -1138,7 +1138,8 @@ EXPORT_SYMBOL(of_parse_phandle); + */ + static int __of_parse_phandle_with_args(const struct device_node *np, + const char *list_name, +- const char *cells_name, int index, ++ const char *cells_name, ++ int cell_count, int index, + struct of_phandle_args *out_args) + { + const __be32 *list, *list_end; +@@ -1174,11 +1175,17 @@ static int __of_parse_phandle_with_args(const struct device_node *np, + np->full_name); + goto err; + } +- if (of_property_read_u32(node, cells_name, &count)) { +- pr_err("%s: could not get %s for %s\n", +- np->full_name, cells_name, +- node->full_name); +- goto err; ++ ++ if (cells_name) { ++ if (of_property_read_u32(node, cells_name, ++ &count)) { ++ pr_err("%s: could not get %s for %s\n", ++ np->full_name, cells_name, ++ node->full_name); ++ goto err; ++ } ++ } else { ++ count = cell_count; + } + + /* +@@ -1244,11 +1251,53 @@ int of_parse_phandle_with_args(const struct device_node *np, const char *list_na + { + if (index < 0) + return -EINVAL; +- return __of_parse_phandle_with_args(np, list_name, cells_name, index, out_args); ++ return __of_parse_phandle_with_args(np, list_name, cells_name, 0, ++ index, out_args); + } + EXPORT_SYMBOL(of_parse_phandle_with_args); + + /** ++ * of_parse_phandle_with_fixed_args() - Find a node pointed by phandle in a list ++ * @np: pointer to a device tree node containing a list ++ * @list_name: property name that contains a list ++ * @cell_count: number of argument cells following the phandle ++ * @index: index of a phandle to parse out ++ * @out_args: optional pointer to output arguments structure (will be filled) ++ * ++ * This function is useful to parse lists of phandles and their arguments. ++ * Returns 0 on success and fills out_args, on error returns appropriate ++ * errno value. ++ * ++ * Caller is responsible to call of_node_put() on the returned out_args->node ++ * pointer. ++ * ++ * Example: ++ * ++ * phandle1: node1 { ++ * } ++ * ++ * phandle2: node2 { ++ * } ++ * ++ * node3 { ++ * list = <&phandle1 0 2 &phandle2 2 3>; ++ * } ++ * ++ * To get a device_node of the `node2' node you may call this: ++ * of_parse_phandle_with_fixed_args(node3, "list", 2, 1, &args); ++ */ ++int of_parse_phandle_with_fixed_args(const struct device_node *np, ++ const char *list_name, int cell_count, ++ int index, struct of_phandle_args *out_args) ++{ ++ if (index < 0) ++ return -EINVAL; ++ return __of_parse_phandle_with_args(np, list_name, NULL, cell_count, ++ index, out_args); ++} ++EXPORT_SYMBOL(of_parse_phandle_with_fixed_args); ++ ++/** + * of_count_phandle_with_args() - Find the number of phandles references in a property + * @np: pointer to a device tree node containing a list + * @list_name: property name that contains a list +@@ -1266,7 +1315,8 @@ EXPORT_SYMBOL(of_parse_phandle_with_args); + int of_count_phandle_with_args(const struct device_node *np, const char *list_name, + const char *cells_name) + { +- return __of_parse_phandle_with_args(np, list_name, cells_name, -1, NULL); ++ return __of_parse_phandle_with_args(np, list_name, cells_name, 0, -1, ++ NULL); + } + EXPORT_SYMBOL(of_count_phandle_with_args); + +diff --git a/include/linux/of.h b/include/linux/of.h +index 1fd08ca2..0c457f58 100644 +--- a/include/linux/of.h ++++ b/include/linux/of.h +@@ -280,6 +280,9 @@ extern struct device_node *of_parse_phandle(const struct device_node *np, + extern int of_parse_phandle_with_args(const struct device_node *np, + const char *list_name, const char *cells_name, int index, + struct of_phandle_args *out_args); ++extern int of_parse_phandle_with_fixed_args(const struct device_node *np, ++ const char *list_name, int cells_count, int index, ++ struct of_phandle_args *out_args); + extern int of_count_phandle_with_args(const struct device_node *np, + const char *list_name, const char *cells_name); + +@@ -488,6 +491,13 @@ static inline int of_parse_phandle_with_args(struct device_node *np, + return -ENOSYS; + } + ++static inline int of_parse_phandle_with_fixed_args(const struct device_node *np, ++ const char *list_name, int cells_count, int index, ++ struct of_phandle_args *out_args) ++{ ++ return -ENOSYS; ++} ++ + static inline int of_count_phandle_with_args(struct device_node *np, + const char *list_name, + const char *cells_name) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0048-gpio-implement-gpio-ranges-binding-document-fix.patch b/patches.renesas/0048-gpio-implement-gpio-ranges-binding-document-fix.patch new file mode 100644 index 00000000000..b5f7245c7f1 --- /dev/null +++ b/patches.renesas/0048-gpio-implement-gpio-ranges-binding-document-fix.patch @@ -0,0 +1,36 @@ +From f1df6f59c8d82463c524d410ef5b878ae3aeb278 Mon Sep 17 00:00:00 2001 +From: Stephen Warren <swarren@nvidia.com> +Date: Wed, 14 Aug 2013 15:27:12 -0600 +Subject: gpio: implement gpio-ranges binding document fix + +Use the new of_parse_phandle_with_fixed_args() to implement the +corrected gpio-ranges DT property definition. + +Signed-off-by: Stephen Warren <swarren@nvidia.com> +Acked-by: Mark Rutland <mark.rutland@arm.com> +Acked-by: Linus Walleij <linus.walleij@linaro.org> +Signed-off-by: Grant Likely <grant.likely@linaro.org> +(cherry picked from commit d9fe0039c4247383c2783923a3860227813b4d82) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpio/gpiolib-of.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c +index 665f9530..48cda3c9 100644 +--- a/drivers/gpio/gpiolib-of.c ++++ b/drivers/gpio/gpiolib-of.c +@@ -194,8 +194,8 @@ static void of_gpiochip_add_pin_range(struct gpio_chip *chip) + return; + + for (;; index++) { +- ret = of_parse_phandle_with_args(np, "gpio-ranges", +- "#gpio-range-cells", index, &pinspec); ++ ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, ++ index, &pinspec); + if (ret) + break; + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0049-gpio-rcar-Remove-gpio-range-cells-DT-property-usage.patch b/patches.renesas/0049-gpio-rcar-Remove-gpio-range-cells-DT-property-usage.patch new file mode 100644 index 00000000000..3d7776892b3 --- /dev/null +++ b/patches.renesas/0049-gpio-rcar-Remove-gpio-range-cells-DT-property-usage.patch @@ -0,0 +1,39 @@ +From ebb13861bff24408d45c68e6de85e44426a65272 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Wed, 11 Sep 2013 15:51:01 +0200 +Subject: gpio: rcar: Remove #gpio-range-cells DT property usage + +Commit a1bc260bb5f5d95da854be7898202d788e94448d ("gpio: clean up +gpio-ranges documentation") deprecated the #gpio-range-cells property. +Replace its usage with a hardcoded value in the gpio-rcar driver. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Acked-by: Linus Walleij <linus.walleij@linaro.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 01eb2d18fd5d7b1539b0023790bc3101aeee522c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpio/gpio-rcar.c | 7 +++---- + 1 file changed, 3 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c +index e8198dd6..0be07f22 100644 +--- a/drivers/gpio/gpio-rcar.c ++++ b/drivers/gpio/gpio-rcar.c +@@ -293,10 +293,9 @@ static void gpio_rcar_parse_pdata(struct gpio_rcar_priv *p) + if (pdata) { + p->config = *pdata; + } else if (IS_ENABLED(CONFIG_OF) && np) { +- ret = of_parse_phandle_with_args(np, "gpio-ranges", +- "#gpio-range-cells", 0, &args); +- p->config.number_of_pins = ret == 0 && args.args_count == 3 +- ? args.args[2] ++ ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, ++ &args); ++ p->config.number_of_pins = ret == 0 ? args.args[2] + : RCAR_MAX_GPIO_PER_BANK; + p->config.gpio_base = -1; + } +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0050-media-soc-camera-move-common-code-to-soc_camera.c.patch b/patches.renesas/0050-media-soc-camera-move-common-code-to-soc_camera.c.patch new file mode 100644 index 00000000000..17827362c80 --- /dev/null +++ b/patches.renesas/0050-media-soc-camera-move-common-code-to-soc_camera.c.patch @@ -0,0 +1,575 @@ +From 16b61d4bbfb274cd565fddaf7512c4221febfe0d Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Thu, 4 Apr 2013 08:21:12 -0300 +Subject: [media] soc-camera: move common code to soc_camera.c + +All soc-camera host drivers include a pointer to an soc-camera device in +their host private struct to check, that only one client is connected. +Move this common code to soc_camera.c. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Acked-by: Hans Verkuil <hans.verkuil@cisco.com> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> +(cherry picked from commit f7f6ce2d09c86bd80ee11bd654a1ac1e8f5dfe13) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/soc_camera/atmel-isi.c | 10 +----- + drivers/media/platform/soc_camera/mx1_camera.c | 20 +++--------- + drivers/media/platform/soc_camera/mx2_camera.c | 13 ++------ + drivers/media/platform/soc_camera/mx3_camera.c | 9 ----- + drivers/media/platform/soc_camera/omap1_camera.c | 14 ++------ + drivers/media/platform/soc_camera/pxa_camera.c | 18 +++------- + .../platform/soc_camera/sh_mobile_ceu_camera.c | 13 ++------ + drivers/media/platform/soc_camera/soc_camera.c | 38 ++++++++++++++++++---- + include/media/soc_camera.h | 1 + + 9 files changed, 49 insertions(+), 87 deletions(-) + +diff --git a/drivers/media/platform/soc_camera/atmel-isi.c b/drivers/media/platform/soc_camera/atmel-isi.c +index 1abbb36d..c9e080a5 100644 +--- a/drivers/media/platform/soc_camera/atmel-isi.c ++++ b/drivers/media/platform/soc_camera/atmel-isi.c +@@ -102,7 +102,6 @@ struct atmel_isi { + struct list_head video_buffer_list; + struct frame_buffer *active; + +- struct soc_camera_device *icd; + struct soc_camera_host soc_host; + }; + +@@ -367,7 +366,7 @@ static void start_dma(struct atmel_isi *isi, struct frame_buffer *buffer) + + /* Check if already in a frame */ + if (isi_readl(isi, ISI_STATUS) & ISI_CTRL_CDC) { +- dev_err(isi->icd->parent, "Already in frame handling.\n"); ++ dev_err(isi->soc_host.icd->parent, "Already in frame handling.\n"); + return; + } + +@@ -753,9 +752,6 @@ static int isi_camera_add_device(struct soc_camera_device *icd) + struct atmel_isi *isi = ici->priv; + int ret; + +- if (isi->icd) +- return -EBUSY; +- + ret = clk_enable(isi->pclk); + if (ret) + return ret; +@@ -766,7 +762,6 @@ static int isi_camera_add_device(struct soc_camera_device *icd) + return ret; + } + +- isi->icd = icd; + dev_dbg(icd->parent, "Atmel ISI Camera driver attached to camera %d\n", + icd->devnum); + return 0; +@@ -777,11 +772,8 @@ static void isi_camera_remove_device(struct soc_camera_device *icd) + struct soc_camera_host *ici = to_soc_camera_host(icd->parent); + struct atmel_isi *isi = ici->priv; + +- BUG_ON(icd != isi->icd); +- + clk_disable(isi->mck); + clk_disable(isi->pclk); +- isi->icd = NULL; + + dev_dbg(icd->parent, "Atmel ISI Camera driver detached from camera %d\n", + icd->devnum); +diff --git a/drivers/media/platform/soc_camera/mx1_camera.c b/drivers/media/platform/soc_camera/mx1_camera.c +index a3fd8d63..5f9ec8ef 100644 +--- a/drivers/media/platform/soc_camera/mx1_camera.c ++++ b/drivers/media/platform/soc_camera/mx1_camera.c +@@ -104,7 +104,6 @@ struct mx1_buffer { + */ + struct mx1_camera_dev { + struct soc_camera_host soc_host; +- struct soc_camera_device *icd; + struct mx1_camera_pdata *pdata; + struct mx1_buffer *active; + struct resource *res; +@@ -220,7 +219,7 @@ out: + static int mx1_camera_setup_dma(struct mx1_camera_dev *pcdev) + { + struct videobuf_buffer *vbuf = &pcdev->active->vb; +- struct device *dev = pcdev->icd->parent; ++ struct device *dev = pcdev->soc_host.icd->parent; + int ret; + + if (unlikely(!pcdev->active)) { +@@ -331,7 +330,7 @@ static void mx1_camera_wakeup(struct mx1_camera_dev *pcdev, + static void mx1_camera_dma_irq(int channel, void *data) + { + struct mx1_camera_dev *pcdev = data; +- struct device *dev = pcdev->icd->parent; ++ struct device *dev = pcdev->soc_host.icd->parent; + struct mx1_buffer *buf; + struct videobuf_buffer *vb; + unsigned long flags; +@@ -389,7 +388,7 @@ static int mclk_get_divisor(struct mx1_camera_dev *pcdev) + */ + div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1; + +- dev_dbg(pcdev->icd->parent, ++ dev_dbg(pcdev->soc_host.icd->parent, + "System clock %lukHz, target freq %dkHz, divisor %lu\n", + lcdclk / 1000, mclk / 1000, div); + +@@ -400,7 +399,7 @@ static void mx1_camera_activate(struct mx1_camera_dev *pcdev) + { + unsigned int csicr1 = CSICR1_EN; + +- dev_dbg(pcdev->icd->parent, "Activate device\n"); ++ dev_dbg(pcdev->soc_host.icd->parent, "Activate device\n"); + + clk_prepare_enable(pcdev->clk); + +@@ -416,7 +415,7 @@ static void mx1_camera_activate(struct mx1_camera_dev *pcdev) + + static void mx1_camera_deactivate(struct mx1_camera_dev *pcdev) + { +- dev_dbg(pcdev->icd->parent, "Deactivate device\n"); ++ dev_dbg(pcdev->soc_host.icd->parent, "Deactivate device\n"); + + /* Disable all CSI interface */ + __raw_writel(0x00, pcdev->base + CSICR1); +@@ -433,16 +432,11 @@ static int mx1_camera_add_device(struct soc_camera_device *icd) + struct soc_camera_host *ici = to_soc_camera_host(icd->parent); + struct mx1_camera_dev *pcdev = ici->priv; + +- if (pcdev->icd) +- return -EBUSY; +- + dev_info(icd->parent, "MX1 Camera driver attached to camera %d\n", + icd->devnum); + + mx1_camera_activate(pcdev); + +- pcdev->icd = icd; +- + return 0; + } + +@@ -452,8 +446,6 @@ static void mx1_camera_remove_device(struct soc_camera_device *icd) + struct mx1_camera_dev *pcdev = ici->priv; + unsigned int csicr1; + +- BUG_ON(icd != pcdev->icd); +- + /* disable interrupts */ + csicr1 = __raw_readl(pcdev->base + CSICR1) & ~CSI_IRQ_MASK; + __raw_writel(csicr1, pcdev->base + CSICR1); +@@ -465,8 +457,6 @@ static void mx1_camera_remove_device(struct soc_camera_device *icd) + icd->devnum); + + mx1_camera_deactivate(pcdev); +- +- pcdev->icd = NULL; + } + + static int mx1_camera_set_bus_param(struct soc_camera_device *icd) +diff --git a/drivers/media/platform/soc_camera/mx2_camera.c b/drivers/media/platform/soc_camera/mx2_camera.c +index 5bbeb43e..772e0710 100644 +--- a/drivers/media/platform/soc_camera/mx2_camera.c ++++ b/drivers/media/platform/soc_camera/mx2_camera.c +@@ -236,7 +236,6 @@ enum mx2_camera_type { + struct mx2_camera_dev { + struct device *dev; + struct soc_camera_host soc_host; +- struct soc_camera_device *icd; + struct clk *clk_emma_ahb, *clk_emma_ipg; + struct clk *clk_csi_ahb, *clk_csi_per; + +@@ -394,8 +393,8 @@ static void mx27_update_emma_buf(struct mx2_camera_dev *pcdev, + writel(phys, pcdev->base_emma + + PRP_DEST_Y_PTR - 0x14 * bufnum); + if (prp->out_fmt == V4L2_PIX_FMT_YUV420) { +- u32 imgsize = pcdev->icd->user_height * +- pcdev->icd->user_width; ++ u32 imgsize = pcdev->soc_host.icd->user_height * ++ pcdev->soc_host.icd->user_width; + + writel(phys + imgsize, pcdev->base_emma + + PRP_DEST_CB_PTR - 0x14 * bufnum); +@@ -424,9 +423,6 @@ static int mx2_camera_add_device(struct soc_camera_device *icd) + int ret; + u32 csicr1; + +- if (pcdev->icd) +- return -EBUSY; +- + ret = clk_prepare_enable(pcdev->clk_csi_ahb); + if (ret < 0) + return ret; +@@ -441,7 +437,6 @@ static int mx2_camera_add_device(struct soc_camera_device *icd) + pcdev->csicr1 = csicr1; + writel(pcdev->csicr1, pcdev->base_csi + CSICR1); + +- pcdev->icd = icd; + pcdev->frame_count = 0; + + dev_info(icd->parent, "Camera driver attached to camera %d\n", +@@ -460,14 +455,10 @@ static void mx2_camera_remove_device(struct soc_camera_device *icd) + struct soc_camera_host *ici = to_soc_camera_host(icd->parent); + struct mx2_camera_dev *pcdev = ici->priv; + +- BUG_ON(icd != pcdev->icd); +- + dev_info(icd->parent, "Camera driver detached from camera %d\n", + icd->devnum); + + mx2_camera_deactivate(pcdev); +- +- pcdev->icd = NULL; + } + + /* +diff --git a/drivers/media/platform/soc_camera/mx3_camera.c b/drivers/media/platform/soc_camera/mx3_camera.c +index 5da33773..71b9b191 100644 +--- a/drivers/media/platform/soc_camera/mx3_camera.c ++++ b/drivers/media/platform/soc_camera/mx3_camera.c +@@ -94,7 +94,6 @@ struct mx3_camera_dev { + * Interface. If anyone ever builds hardware to enable more than one + * camera _simultaneously_, they will have to modify this driver too + */ +- struct soc_camera_device *icd; + struct clk *clk; + + void __iomem *base; +@@ -517,13 +516,9 @@ static int mx3_camera_add_device(struct soc_camera_device *icd) + struct soc_camera_host *ici = to_soc_camera_host(icd->parent); + struct mx3_camera_dev *mx3_cam = ici->priv; + +- if (mx3_cam->icd) +- return -EBUSY; +- + mx3_camera_activate(mx3_cam, icd); + + mx3_cam->buf_total = 0; +- mx3_cam->icd = icd; + + dev_info(icd->parent, "MX3 Camera driver attached to camera %d\n", + icd->devnum); +@@ -538,8 +533,6 @@ static void mx3_camera_remove_device(struct soc_camera_device *icd) + struct mx3_camera_dev *mx3_cam = ici->priv; + struct idmac_channel **ichan = &mx3_cam->idmac_channel[0]; + +- BUG_ON(icd != mx3_cam->icd); +- + if (*ichan) { + dma_release_channel(&(*ichan)->dma_chan); + *ichan = NULL; +@@ -547,8 +540,6 @@ static void mx3_camera_remove_device(struct soc_camera_device *icd) + + clk_disable_unprepare(mx3_cam->clk); + +- mx3_cam->icd = NULL; +- + dev_info(icd->parent, "MX3 Camera driver detached from camera %d\n", + icd->devnum); + } +diff --git a/drivers/media/platform/soc_camera/omap1_camera.c b/drivers/media/platform/soc_camera/omap1_camera.c +index 9689a6e8..c42c23e4 100644 +--- a/drivers/media/platform/soc_camera/omap1_camera.c ++++ b/drivers/media/platform/soc_camera/omap1_camera.c +@@ -150,7 +150,6 @@ struct omap1_cam_buf { + + struct omap1_cam_dev { + struct soc_camera_host soc_host; +- struct soc_camera_device *icd; + struct clk *clk; + + unsigned int irq; +@@ -564,7 +563,7 @@ static void videobuf_done(struct omap1_cam_dev *pcdev, + { + struct omap1_cam_buf *buf = pcdev->active; + struct videobuf_buffer *vb; +- struct device *dev = pcdev->icd->parent; ++ struct device *dev = pcdev->soc_host.icd->parent; + + if (WARN_ON(!buf)) { + suspend_capture(pcdev); +@@ -790,7 +789,7 @@ out: + static irqreturn_t cam_isr(int irq, void *data) + { + struct omap1_cam_dev *pcdev = data; +- struct device *dev = pcdev->icd->parent; ++ struct device *dev = pcdev->soc_host.icd->parent; + struct omap1_cam_buf *buf = pcdev->active; + u32 it_status; + unsigned long flags; +@@ -904,9 +903,6 @@ static int omap1_cam_add_device(struct soc_camera_device *icd) + struct omap1_cam_dev *pcdev = ici->priv; + u32 ctrlclock; + +- if (pcdev->icd) +- return -EBUSY; +- + clk_enable(pcdev->clk); + + /* setup sensor clock */ +@@ -941,8 +937,6 @@ static int omap1_cam_add_device(struct soc_camera_device *icd) + + sensor_reset(pcdev, false); + +- pcdev->icd = icd; +- + dev_dbg(icd->parent, "OMAP1 Camera driver attached to camera %d\n", + icd->devnum); + return 0; +@@ -954,8 +948,6 @@ static void omap1_cam_remove_device(struct soc_camera_device *icd) + struct omap1_cam_dev *pcdev = ici->priv; + u32 ctrlclock; + +- BUG_ON(icd != pcdev->icd); +- + suspend_capture(pcdev); + disable_capture(pcdev); + +@@ -974,8 +966,6 @@ static void omap1_cam_remove_device(struct soc_camera_device *icd) + + clk_disable(pcdev->clk); + +- pcdev->icd = NULL; +- + dev_dbg(icd->parent, + "OMAP1 Camera driver detached from camera %d\n", icd->devnum); + } +diff --git a/drivers/media/platform/soc_camera/pxa_camera.c b/drivers/media/platform/soc_camera/pxa_camera.c +index d665242e..686edf7c 100644 +--- a/drivers/media/platform/soc_camera/pxa_camera.c ++++ b/drivers/media/platform/soc_camera/pxa_camera.c +@@ -200,7 +200,6 @@ struct pxa_camera_dev { + * interface. If anyone ever builds hardware to enable more than + * one camera, they will have to modify this driver too + */ +- struct soc_camera_device *icd; + struct clk *clk; + + unsigned int irq; +@@ -966,13 +965,8 @@ static int pxa_camera_add_device(struct soc_camera_device *icd) + struct soc_camera_host *ici = to_soc_camera_host(icd->parent); + struct pxa_camera_dev *pcdev = ici->priv; + +- if (pcdev->icd) +- return -EBUSY; +- + pxa_camera_activate(pcdev); + +- pcdev->icd = icd; +- + dev_info(icd->parent, "PXA Camera driver attached to camera %d\n", + icd->devnum); + +@@ -985,8 +979,6 @@ static void pxa_camera_remove_device(struct soc_camera_device *icd) + struct soc_camera_host *ici = to_soc_camera_host(icd->parent); + struct pxa_camera_dev *pcdev = ici->priv; + +- BUG_ON(icd != pcdev->icd); +- + dev_info(icd->parent, "PXA Camera driver detached from camera %d\n", + icd->devnum); + +@@ -999,8 +991,6 @@ static void pxa_camera_remove_device(struct soc_camera_device *icd) + DCSR(pcdev->dma_chans[2]) = 0; + + pxa_camera_deactivate(pcdev); +- +- pcdev->icd = NULL; + } + + static int test_platform_param(struct pxa_camera_dev *pcdev, +@@ -1596,8 +1586,8 @@ static int pxa_camera_suspend(struct device *dev) + pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3); + pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4); + +- if (pcdev->icd) { +- struct v4l2_subdev *sd = soc_camera_to_subdev(pcdev->icd); ++ if (pcdev->soc_host.icd) { ++ struct v4l2_subdev *sd = soc_camera_to_subdev(pcdev->soc_host.icd); + ret = v4l2_subdev_call(sd, core, s_power, 0); + if (ret == -ENOIOCTLCMD) + ret = 0; +@@ -1622,8 +1612,8 @@ static int pxa_camera_resume(struct device *dev) + __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3); + __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4); + +- if (pcdev->icd) { +- struct v4l2_subdev *sd = soc_camera_to_subdev(pcdev->icd); ++ if (pcdev->soc_host.icd) { ++ struct v4l2_subdev *sd = soc_camera_to_subdev(pcdev->soc_host.icd); + ret = v4l2_subdev_call(sd, core, s_power, 1); + if (ret == -ENOIOCTLCMD) + ret = 0; +diff --git a/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c b/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c +index 143d29fe..5b7d8e1d 100644 +--- a/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c ++++ b/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c +@@ -95,7 +95,6 @@ struct sh_mobile_ceu_buffer { + + struct sh_mobile_ceu_dev { + struct soc_camera_host ici; +- struct soc_camera_device *icd; + struct platform_device *csi2_pdev; + + unsigned int irq; +@@ -163,7 +162,7 @@ static u32 ceu_read(struct sh_mobile_ceu_dev *priv, unsigned long reg_offs) + static int sh_mobile_ceu_soft_reset(struct sh_mobile_ceu_dev *pcdev) + { + int i, success = 0; +- struct soc_camera_device *icd = pcdev->icd; ++ struct soc_camera_device *icd = pcdev->ici.icd; + + ceu_write(pcdev, CAPSR, 1 << 16); /* reset */ + +@@ -277,7 +276,7 @@ static int sh_mobile_ceu_videobuf_setup(struct vb2_queue *vq, + */ + static int sh_mobile_ceu_capture(struct sh_mobile_ceu_dev *pcdev) + { +- struct soc_camera_device *icd = pcdev->icd; ++ struct soc_camera_device *icd = pcdev->ici.icd; + dma_addr_t phys_addr_top, phys_addr_bottom; + unsigned long top1, top2; + unsigned long bottom1, bottom2; +@@ -552,9 +551,6 @@ static int sh_mobile_ceu_add_device(struct soc_camera_device *icd) + struct v4l2_subdev *csi2_sd; + int ret; + +- if (pcdev->icd) +- return -EBUSY; +- + dev_info(icd->parent, + "SuperH Mobile CEU driver attached to camera %d\n", + icd->devnum); +@@ -583,7 +579,6 @@ static int sh_mobile_ceu_add_device(struct soc_camera_device *icd) + */ + if (ret == -ENODEV && csi2_sd) + csi2_sd->grp_id = 0; +- pcdev->icd = icd; + + return 0; + } +@@ -595,8 +590,6 @@ static void sh_mobile_ceu_remove_device(struct soc_camera_device *icd) + struct sh_mobile_ceu_dev *pcdev = ici->priv; + struct v4l2_subdev *csi2_sd = find_csi2(pcdev); + +- BUG_ON(icd != pcdev->icd); +- + v4l2_subdev_call(csi2_sd, core, s_power, 0); + if (csi2_sd) + csi2_sd->grp_id = 0; +@@ -618,8 +611,6 @@ static void sh_mobile_ceu_remove_device(struct soc_camera_device *icd) + dev_info(icd->parent, + "SuperH Mobile CEU driver detached from camera %d\n", + icd->devnum); +- +- pcdev->icd = NULL; + } + + /* +diff --git a/drivers/media/platform/soc_camera/soc_camera.c b/drivers/media/platform/soc_camera/soc_camera.c +index 3a4efbdc..832f0593 100644 +--- a/drivers/media/platform/soc_camera/soc_camera.c ++++ b/drivers/media/platform/soc_camera/soc_camera.c +@@ -505,6 +505,32 @@ static int soc_camera_set_fmt(struct soc_camera_device *icd, + return ici->ops->set_bus_param(icd); + } + ++static int soc_camera_add_device(struct soc_camera_device *icd) ++{ ++ struct soc_camera_host *ici = to_soc_camera_host(icd->parent); ++ int ret; ++ ++ if (ici->icd) ++ return -EBUSY; ++ ++ ret = ici->ops->add(icd); ++ if (!ret) ++ ici->icd = icd; ++ ++ return ret; ++} ++ ++static void soc_camera_remove_device(struct soc_camera_device *icd) ++{ ++ struct soc_camera_host *ici = to_soc_camera_host(icd->parent); ++ ++ if (WARN_ON(icd != ici->icd)) ++ return; ++ ++ ici->ops->remove(icd); ++ ici->icd = NULL; ++} ++ + static int soc_camera_open(struct file *file) + { + struct video_device *vdev = video_devdata(file); +@@ -568,7 +594,7 @@ static int soc_camera_open(struct file *file) + if (sdesc->subdev_desc.reset) + sdesc->subdev_desc.reset(icd->pdev); + +- ret = ici->ops->add(icd); ++ ret = soc_camera_add_device(icd); + if (ret < 0) { + dev_err(icd->pdev, "Couldn't activate the camera: %d\n", ret); + goto eiciadd; +@@ -619,7 +645,7 @@ esfmt: + eresume: + __soc_camera_power_off(icd); + epower: +- ici->ops->remove(icd); ++ soc_camera_remove_device(icd); + eiciadd: + icd->use_count--; + mutex_unlock(&ici->host_lock); +@@ -645,7 +671,7 @@ static int soc_camera_close(struct file *file) + vb2_queue_release(&icd->vb2_vidq); + __soc_camera_power_off(icd); + +- ici->ops->remove(icd); ++ soc_camera_remove_device(icd); + } + + if (icd->streamer == file) +@@ -1167,7 +1193,7 @@ static int soc_camera_probe(struct soc_camera_device *icd) + ssdd->reset(icd->pdev); + + mutex_lock(&ici->host_lock); +- ret = ici->ops->add(icd); ++ ret = soc_camera_add_device(icd); + mutex_unlock(&ici->host_lock); + if (ret < 0) + goto eadd; +@@ -1240,7 +1266,7 @@ static int soc_camera_probe(struct soc_camera_device *icd) + icd->field = mf.field; + } + +- ici->ops->remove(icd); ++ soc_camera_remove_device(icd); + + mutex_unlock(&ici->host_lock); + +@@ -1263,7 +1289,7 @@ eadddev: + icd->vdev = NULL; + evdc: + mutex_lock(&ici->host_lock); +- ici->ops->remove(icd); ++ soc_camera_remove_device(icd); + mutex_unlock(&ici->host_lock); + eadd: + v4l2_ctrl_handler_free(&icd->ctrl_handler); +diff --git a/include/media/soc_camera.h b/include/media/soc_camera.h +index ff77d08c..5a46ce2d 100644 +--- a/include/media/soc_camera.h ++++ b/include/media/soc_camera.h +@@ -64,6 +64,7 @@ struct soc_camera_host { + struct mutex host_lock; /* Protect pipeline modifications */ + unsigned char nr; /* Host number */ + u32 capabilities; ++ struct soc_camera_device *icd; /* Currently attached client */ + void *priv; + const char *drv_name; + struct soc_camera_host_ops *ops; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0051-mmc-return-mmc_of_parse-errors-to-caller.patch b/patches.renesas/0051-mmc-return-mmc_of_parse-errors-to-caller.patch new file mode 100644 index 00000000000..356beeef7cb --- /dev/null +++ b/patches.renesas/0051-mmc-return-mmc_of_parse-errors-to-caller.patch @@ -0,0 +1,130 @@ +From b44ec118a86a032b43da0b0142486522f6157ea6 Mon Sep 17 00:00:00 2001 +From: Simon Baatz <gmbnomis@gmail.com> +Date: Sun, 9 Jun 2013 22:14:11 +0200 +Subject: mmc: return mmc_of_parse() errors to caller + +In addition to just logging errors encountered during DT parsing or +allocating GPIO slots for CD/WP, mmc_of_parse() now returns with an error. + +In particular, this is needed if the GPIO allocation may return +EPROBE_DEFER. + +Signed-off-by: Simon Baatz <gmbnomis@gmail.com> +Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> +Signed-off-by: Chris Ball <cjb@laptop.org> +(cherry picked from commit ec0a7517dc25b4cca8a694fd61e09771bffba022) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/core/host.c | 30 +++++++++++++++++++++++++----- + include/linux/mmc/host.h | 2 +- + 2 files changed, 26 insertions(+), 6 deletions(-) + +diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c +index 2a3593d9..89f58498 100644 +--- a/drivers/mmc/core/host.c ++++ b/drivers/mmc/core/host.c +@@ -306,7 +306,7 @@ static inline void mmc_host_clk_sysfs_init(struct mmc_host *host) + * parse the properties and set respective generic mmc-host flags and + * parameters. + */ +-void mmc_of_parse(struct mmc_host *host) ++int mmc_of_parse(struct mmc_host *host) + { + struct device_node *np; + u32 bus_width; +@@ -315,7 +315,7 @@ void mmc_of_parse(struct mmc_host *host) + int len, ret, gpio; + + if (!host->parent || !host->parent->of_node) +- return; ++ return 0; + + np = host->parent->of_node; + +@@ -338,6 +338,7 @@ void mmc_of_parse(struct mmc_host *host) + default: + dev_err(host->parent, + "Invalid \"bus-width\" value %ud!\n", bus_width); ++ return -EINVAL; + } + + /* f_max is obtained from the optional "max-frequency" property */ +@@ -367,18 +368,22 @@ void mmc_of_parse(struct mmc_host *host) + host->caps |= MMC_CAP_NEEDS_POLL; + + gpio = of_get_named_gpio_flags(np, "cd-gpios", 0, &flags); ++ if (gpio == -EPROBE_DEFER) ++ return gpio; + if (gpio_is_valid(gpio)) { + if (!(flags & OF_GPIO_ACTIVE_LOW)) + gpio_inv_cd = true; + + ret = mmc_gpio_request_cd(host, gpio); +- if (ret < 0) ++ if (ret < 0) { + dev_err(host->parent, + "Failed to request CD GPIO #%d: %d!\n", + gpio, ret); +- else ++ return ret; ++ } else { + dev_info(host->parent, "Got CD GPIO #%d.\n", + gpio); ++ } + } + + if (explicit_inv_cd ^ gpio_inv_cd) +@@ -389,14 +394,23 @@ void mmc_of_parse(struct mmc_host *host) + explicit_inv_wp = of_property_read_bool(np, "wp-inverted"); + + gpio = of_get_named_gpio_flags(np, "wp-gpios", 0, &flags); ++ if (gpio == -EPROBE_DEFER) { ++ ret = -EPROBE_DEFER; ++ goto out; ++ } + if (gpio_is_valid(gpio)) { + if (!(flags & OF_GPIO_ACTIVE_LOW)) + gpio_inv_wp = true; + + ret = mmc_gpio_request_ro(host, gpio); +- if (ret < 0) ++ if (ret < 0) { + dev_err(host->parent, + "Failed to request WP GPIO: %d!\n", ret); ++ goto out; ++ } else { ++ dev_info(host->parent, "Got WP GPIO #%d.\n", ++ gpio); ++ } + } + if (explicit_inv_wp ^ gpio_inv_wp) + host->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; +@@ -413,6 +427,12 @@ void mmc_of_parse(struct mmc_host *host) + host->pm_caps |= MMC_PM_KEEP_POWER; + if (of_find_property(np, "enable-sdio-wakeup", &len)) + host->pm_caps |= MMC_PM_WAKE_SDIO_IRQ; ++ ++ return 0; ++ ++out: ++ mmc_gpio_free_cd(host); ++ return ret; + } + + EXPORT_SYMBOL(mmc_of_parse); +diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h +index e326ae28..c8c4fbc6 100644 +--- a/include/linux/mmc/host.h ++++ b/include/linux/mmc/host.h +@@ -369,7 +369,7 @@ struct mmc_host *mmc_alloc_host(int extra, struct device *); + int mmc_add_host(struct mmc_host *); + void mmc_remove_host(struct mmc_host *); + void mmc_free_host(struct mmc_host *); +-void mmc_of_parse(struct mmc_host *host); ++int mmc_of_parse(struct mmc_host *host); + + static inline void *mmc_priv(struct mmc_host *host) + { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0052-mmc-slot-gpio-Add-debouncing-capability-to-mmc_gpio_.patch b/patches.renesas/0052-mmc-slot-gpio-Add-debouncing-capability-to-mmc_gpio_.patch new file mode 100644 index 00000000000..0a7d2c5a338 --- /dev/null +++ b/patches.renesas/0052-mmc-slot-gpio-Add-debouncing-capability-to-mmc_gpio_.patch @@ -0,0 +1,180 @@ +From 8bec0342de0d649786e321912caad6e8cc90a0c1 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 8 Aug 2013 12:38:31 +0200 +Subject: mmc: slot-gpio: Add debouncing capability to mmc_gpio_request_cd() + +Add a debounce parameter to the mmc_gpio_request_cd() function that +enables GPIO debouncing when set to a non-zero value. This can be used +by MMC host drivers to enable debouncing on the card detect signal. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: H Hartley Sweeten <hsweeten@visionengravers.com> +Signed-off-by: Chris Ball <cjb@laptop.org> +(cherry picked from commit 214fc309d1387e822d606a33a10e31cacfe83520) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + drivers/mmc/host/jz4740_mmc.c + drivers/mmc/host/mvsdio.c +--- + drivers/mmc/core/host.c | 2 +- + drivers/mmc/core/slot-gpio.c | 14 +++++++++++++- + drivers/mmc/host/mvsdio.c | 2 +- + drivers/mmc/host/sdhci-esdhc-imx.c | 2 +- + drivers/mmc/host/sdhci-pxav3.c | 3 ++- + drivers/mmc/host/sdhci-sirf.c | 2 +- + drivers/mmc/host/sh_mmcif.c | 2 +- + drivers/mmc/host/tmio_mmc_pio.c | 2 +- + include/linux/mmc/slot-gpio.h | 3 ++- + 9 files changed, 23 insertions(+), 9 deletions(-) + +diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c +index 89f58498..85bdfd00 100644 +--- a/drivers/mmc/core/host.c ++++ b/drivers/mmc/core/host.c +@@ -374,7 +374,7 @@ int mmc_of_parse(struct mmc_host *host) + if (!(flags & OF_GPIO_ACTIVE_LOW)) + gpio_inv_cd = true; + +- ret = mmc_gpio_request_cd(host, gpio); ++ ret = mmc_gpio_request_cd(host, gpio, 0); + if (ret < 0) { + dev_err(host->parent, + "Failed to request CD GPIO #%d: %d!\n", +diff --git a/drivers/mmc/core/slot-gpio.c b/drivers/mmc/core/slot-gpio.c +index 32423510..46596b71 100644 +--- a/drivers/mmc/core/slot-gpio.c ++++ b/drivers/mmc/core/slot-gpio.c +@@ -135,6 +135,7 @@ EXPORT_SYMBOL(mmc_gpio_request_ro); + * mmc_gpio_request_cd - request a gpio for card-detection + * @host: mmc host + * @gpio: gpio number requested ++ * @debounce: debounce time in microseconds + * + * As devm_* managed functions are used in mmc_gpio_request_cd(), client + * drivers do not need to explicitly call mmc_gpio_free_cd() for freeing up, +@@ -143,9 +144,14 @@ EXPORT_SYMBOL(mmc_gpio_request_ro); + * switching for card-detection, they are responsible for calling + * mmc_gpio_request_cd() and mmc_gpio_free_cd() as a pair on their own. + * ++ * If GPIO debouncing is desired, set the debounce parameter to a non-zero ++ * value. The caller is responsible for ensuring that the GPIO driver associated ++ * with the GPIO supports debouncing, otherwise an error will be returned. ++ * + * Returns zero on success, else an error. + */ +-int mmc_gpio_request_cd(struct mmc_host *host, unsigned int gpio) ++int mmc_gpio_request_cd(struct mmc_host *host, unsigned int gpio, ++ unsigned int debounce) + { + struct mmc_gpio *ctx; + int irq = gpio_to_irq(gpio); +@@ -167,6 +173,12 @@ int mmc_gpio_request_cd(struct mmc_host *host, unsigned int gpio) + */ + return ret; + ++ if (debounce) { ++ ret = gpio_set_debounce(gpio, debounce); ++ if (ret < 0) ++ return ret; ++ } ++ + /* + * Even if gpio_to_irq() returns a valid IRQ number, the platform might + * still prefer to poll, e.g., because that IRQ number is already used +diff --git a/drivers/mmc/host/mvsdio.c b/drivers/mmc/host/mvsdio.c +index 8960fc84..a1fcc1f9 100644 +--- a/drivers/mmc/host/mvsdio.c ++++ b/drivers/mmc/host/mvsdio.c +@@ -778,7 +778,7 @@ static int __init mvsd_probe(struct platform_device *pdev) + } + + if (gpio_is_valid(gpio_card_detect)) { +- ret = mmc_gpio_request_cd(mmc, gpio_card_detect); ++ ret = mmc_gpio_request_cd(mmc, gpio_card_detect, 0); + if (ret) + goto out; + } else +diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c +index d5f0d59e..a0317abb 100644 +--- a/drivers/mmc/host/sdhci-esdhc-imx.c ++++ b/drivers/mmc/host/sdhci-esdhc-imx.c +@@ -592,7 +592,7 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev) + /* card_detect */ + switch (boarddata->cd_type) { + case ESDHC_CD_GPIO: +- err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio); ++ err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0); + if (err) { + dev_err(mmc_dev(host->mmc), + "failed to request card-detect gpio!\n"); +diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c +index 1ae358e0..ce84208d 100644 +--- a/drivers/mmc/host/sdhci-pxav3.c ++++ b/drivers/mmc/host/sdhci-pxav3.c +@@ -276,7 +276,8 @@ static int sdhci_pxav3_probe(struct platform_device *pdev) + host->mmc->pm_caps |= pdata->pm_caps; + + if (gpio_is_valid(pdata->ext_cd_gpio)) { +- ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio); ++ ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio, ++ 0); + if (ret) { + dev_err(mmc_dev(host->mmc), + "failed to allocate card detect gpio\n"); +diff --git a/drivers/mmc/host/sdhci-sirf.c b/drivers/mmc/host/sdhci-sirf.c +index 09805af0..b665326d 100644 +--- a/drivers/mmc/host/sdhci-sirf.c ++++ b/drivers/mmc/host/sdhci-sirf.c +@@ -97,7 +97,7 @@ static int sdhci_sirf_probe(struct platform_device *pdev) + * gets setup in sdhci_add_host() and we oops. + */ + if (gpio_is_valid(priv->gpio_cd)) { +- ret = mmc_gpio_request_cd(host->mmc, priv->gpio_cd); ++ ret = mmc_gpio_request_cd(host->mmc, priv->gpio_cd, 0); + if (ret) { + dev_err(&pdev->dev, "card detect irq request failed: %d\n", + ret); +diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c +index ba76a532..a23f6c06 100644 +--- a/drivers/mmc/host/sh_mmcif.c ++++ b/drivers/mmc/host/sh_mmcif.c +@@ -1431,7 +1431,7 @@ static int sh_mmcif_probe(struct platform_device *pdev) + } + + if (pd && pd->use_cd_gpio) { +- ret = mmc_gpio_request_cd(mmc, pd->cd_gpio); ++ ret = mmc_gpio_request_cd(mmc, pd->cd_gpio, 0); + if (ret < 0) + goto erqcd; + } +diff --git a/drivers/mmc/host/tmio_mmc_pio.c b/drivers/mmc/host/tmio_mmc_pio.c +index f508ecb5..5a1bc3b4 100644 +--- a/drivers/mmc/host/tmio_mmc_pio.c ++++ b/drivers/mmc/host/tmio_mmc_pio.c +@@ -1091,7 +1091,7 @@ int tmio_mmc_host_probe(struct tmio_mmc_host **host, + dev_pm_qos_expose_latency_limit(&pdev->dev, 100); + + if (pdata->flags & TMIO_MMC_USE_GPIO_CD) { +- ret = mmc_gpio_request_cd(mmc, pdata->cd_gpio); ++ ret = mmc_gpio_request_cd(mmc, pdata->cd_gpio, 0); + if (ret < 0) { + tmio_mmc_host_remove(_host); + return ret; +diff --git a/include/linux/mmc/slot-gpio.h b/include/linux/mmc/slot-gpio.h +index 7d88d27b..b0c73e4c 100644 +--- a/include/linux/mmc/slot-gpio.h ++++ b/include/linux/mmc/slot-gpio.h +@@ -18,7 +18,8 @@ int mmc_gpio_request_ro(struct mmc_host *host, unsigned int gpio); + void mmc_gpio_free_ro(struct mmc_host *host); + + int mmc_gpio_get_cd(struct mmc_host *host); +-int mmc_gpio_request_cd(struct mmc_host *host, unsigned int gpio); ++int mmc_gpio_request_cd(struct mmc_host *host, unsigned int gpio, ++ unsigned int debounce); + void mmc_gpio_free_cd(struct mmc_host *host); + + #endif +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0053-mmc-sh_mmcif-don-t-clear-masked-interrupts.patch b/patches.renesas/0053-mmc-sh_mmcif-don-t-clear-masked-interrupts.patch new file mode 100644 index 00000000000..1a80f3aa777 --- /dev/null +++ b/patches.renesas/0053-mmc-sh_mmcif-don-t-clear-masked-interrupts.patch @@ -0,0 +1,43 @@ +From 73a9361644d86ae17d6ad8957433f301336d88a3 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Wed, 15 May 2013 07:50:51 +0200 +Subject: mmc: sh_mmcif: don't clear masked interrupts + +Masking events on MMCIF means that an occurrence of the masked event +won't raise an interrupt, but the event bit will still be set in the +interrupt status register. If simultaneously a different event occurs +which was enabled, both flags will be set. However, only the unmasked +event bit should be cleared in the status register in such a case. + +Clearing also the masked bit can lead to lost interrupts, which indeed +can be observed on the armadillo800eva r8a7740 board with an eMMC chip. +The problem has been introduced by the recent "mmc: sh_mmcif: simplify +IRQ processing" patch. Fix the problem by only clearing enabled interrupts. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Tested-by: Nguyen Viet Dung <nv-dung@jinso.co.jp> +Tested-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Chris Ball <cjb@laptop.org> +(cherry picked from commit 19f1ba51c79f133aec3ce558b8292e3b081363f3) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/sh_mmcif.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c +index a23f6c06..3ae1a1f8 100644 +--- a/drivers/mmc/host/sh_mmcif.c ++++ b/drivers/mmc/host/sh_mmcif.c +@@ -1244,7 +1244,8 @@ static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) + u32 state; + + state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); +- sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state); ++ sh_mmcif_writel(host->addr, MMCIF_CE_INT, ++ ~(state & sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK))); + sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN); + + if (state & ~MASK_CLEAN) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0054-mmc-sh_mmcif-handle-mmc_of_parse-errors-during-probe.patch b/patches.renesas/0054-mmc-sh_mmcif-handle-mmc_of_parse-errors-during-probe.patch new file mode 100644 index 00000000000..65ed910f5a1 --- /dev/null +++ b/patches.renesas/0054-mmc-sh_mmcif-handle-mmc_of_parse-errors-during-probe.patch @@ -0,0 +1,42 @@ +From 6a3b2f7e0e60638bf9d1f8816711fcdfed038912 Mon Sep 17 00:00:00 2001 +From: Simon Baatz <gmbnomis@gmail.com> +Date: Sun, 9 Jun 2013 22:14:12 +0200 +Subject: mmc: sh_mmcif: handle mmc_of_parse() errors during probe + +Signed-off-by: Simon Baatz <gmbnomis@gmail.com> +Acked-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Signed-off-by: Chris Ball <cjb@laptop.org> +(cherry picked from commit 2c9054dc102742e1683b5d879f7472fb712b7324) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/sh_mmcif.c | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c +index 3ae1a1f8..6f9834fd 100644 +--- a/drivers/mmc/host/sh_mmcif.c ++++ b/drivers/mmc/host/sh_mmcif.c +@@ -1370,7 +1370,11 @@ static int sh_mmcif_probe(struct platform_device *pdev) + ret = -ENOMEM; + goto ealloch; + } +- mmc_of_parse(mmc); ++ ++ ret = mmc_of_parse(mmc); ++ if (ret < 0) ++ goto eofparse; ++ + host = mmc_priv(mmc); + host->mmc = mmc; + host->addr = reg; +@@ -1465,6 +1469,7 @@ eclkupdate: + clk_put(host->hclk); + eclkget: + pm_runtime_disable(&pdev->dev); ++eofparse: + mmc_free_host(mmc); + ealloch: + iounmap(reg); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0055-mmc-sh_mmcif-Remove-.down_pwr-callback-from-platform.patch b/patches.renesas/0055-mmc-sh_mmcif-Remove-.down_pwr-callback-from-platform.patch new file mode 100644 index 00000000000..b769313cb7e --- /dev/null +++ b/patches.renesas/0055-mmc-sh_mmcif-Remove-.down_pwr-callback-from-platform.patch @@ -0,0 +1,32 @@ +From ccf38069b7e0b57169ac6c2aeece1403ed9538ec Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 8 Aug 2013 12:38:39 +0200 +Subject: mmc: sh_mmcif: Remove .down_pwr() callback from platform data + +The callback isn't used by the driver and isn't initialized by board +code. Remove it. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Acked-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Signed-off-by: Chris Ball <cjb@laptop.org> +(cherry picked from commit dcbfaf36c1933d88565501ff13feb0f4b2d38735) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + include/linux/mmc/sh_mmcif.h | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/include/linux/mmc/sh_mmcif.h b/include/linux/mmc/sh_mmcif.h +index e7d5dd67..39011eb4 100644 +--- a/include/linux/mmc/sh_mmcif.h ++++ b/include/linux/mmc/sh_mmcif.h +@@ -34,7 +34,6 @@ + + struct sh_mmcif_plat_data { + void (*set_pwr)(struct platform_device *pdev, int state); +- void (*down_pwr)(struct platform_device *pdev); + int (*get_cd)(struct platform_device *pdef); + unsigned int slave_id_tx; /* embedded slave_id_[tr]x */ + unsigned int slave_id_rx; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0056-mmc-sh_mmcif-Remove-.set_pwr-callback-from-platform-.patch b/patches.renesas/0056-mmc-sh_mmcif-Remove-.set_pwr-callback-from-platform-.patch new file mode 100644 index 00000000000..e70877357e0 --- /dev/null +++ b/patches.renesas/0056-mmc-sh_mmcif-Remove-.set_pwr-callback-from-platform-.patch @@ -0,0 +1,49 @@ +From 79102b5faa1725f10b51df9a107ec572b1d04b09 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 8 Aug 2013 12:38:40 +0200 +Subject: mmc: sh_mmcif: Remove .set_pwr() callback from platform data + +The .set_pwr() callback isn't used anymore as all platforms register +GPIO-controlled regulators. Remove it. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Acked-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Signed-off-by: Chris Ball <cjb@laptop.org> +(cherry picked from commit 83a0c7797e96e103bb3b6fcf8afb7b65dc7fc68e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/sh_mmcif.c | 3 --- + include/linux/mmc/sh_mmcif.h | 1 - + 2 files changed, 4 deletions(-) + +diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c +index 6f9834fd..a973d785 100644 +--- a/drivers/mmc/host/sh_mmcif.c ++++ b/drivers/mmc/host/sh_mmcif.c +@@ -956,11 +956,8 @@ static int sh_mmcif_clk_update(struct sh_mmcif_host *host) + + static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios) + { +- struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data; + struct mmc_host *mmc = host->mmc; + +- if (pd && pd->set_pwr) +- pd->set_pwr(host->pd, ios->power_mode != MMC_POWER_OFF); + if (!IS_ERR(mmc->supply.vmmc)) + /* Errors ignored... */ + mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, +diff --git a/include/linux/mmc/sh_mmcif.h b/include/linux/mmc/sh_mmcif.h +index 39011eb4..767fac5a 100644 +--- a/include/linux/mmc/sh_mmcif.h ++++ b/include/linux/mmc/sh_mmcif.h +@@ -33,7 +33,6 @@ + */ + + struct sh_mmcif_plat_data { +- void (*set_pwr)(struct platform_device *pdev, int state); + int (*get_cd)(struct platform_device *pdef); + unsigned int slave_id_tx; /* embedded slave_id_[tr]x */ + unsigned int slave_id_rx; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0057-mmc-sh_mmcif-move-header-include-from-header-into-.c.patch b/patches.renesas/0057-mmc-sh_mmcif-move-header-include-from-header-into-.c.patch new file mode 100644 index 00000000000..96c6e0b0a21 --- /dev/null +++ b/patches.renesas/0057-mmc-sh_mmcif-move-header-include-from-header-into-.c.patch @@ -0,0 +1,43 @@ +From c443ea12199392b1feaab40311f591ed2f14ccdd Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Fri, 2 Aug 2013 14:48:02 +0200 +Subject: mmc: sh_mmcif: move header include from header into .c + +sh_dma.h isn't needed in sh_mmcif.h, move it into sh_mmcif.c. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Signed-off-by: Chris Ball <cjb@laptop.org> +(cherry picked from commit d00cadacbe47d4883b0d5e38aa73a3f4e171d37e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/sh_mmcif.c | 1 + + include/linux/mmc/sh_mmcif.h | 1 - + 2 files changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c +index a973d785..5c419557 100644 +--- a/drivers/mmc/host/sh_mmcif.c ++++ b/drivers/mmc/host/sh_mmcif.c +@@ -61,6 +61,7 @@ + #include <linux/platform_device.h> + #include <linux/pm_qos.h> + #include <linux/pm_runtime.h> ++#include <linux/sh_dma.h> + #include <linux/spinlock.h> + #include <linux/module.h> + +diff --git a/include/linux/mmc/sh_mmcif.h b/include/linux/mmc/sh_mmcif.h +index 767fac5a..c4880ffb 100644 +--- a/include/linux/mmc/sh_mmcif.h ++++ b/include/linux/mmc/sh_mmcif.h +@@ -16,7 +16,6 @@ + + #include <linux/io.h> + #include <linux/platform_device.h> +-#include <linux/sh_dma.h> + + /* + * MMCIF : CE_CLK_CTRL [19:16] +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0058-mmc-sh_mmcif-add-support-for-Device-Tree-DMA-binding.patch b/patches.renesas/0058-mmc-sh_mmcif-add-support-for-Device-Tree-DMA-binding.patch new file mode 100644 index 00000000000..6d02e8b2a9a --- /dev/null +++ b/patches.renesas/0058-mmc-sh_mmcif-add-support-for-Device-Tree-DMA-binding.patch @@ -0,0 +1,81 @@ +From cbec534645741bf3d4fb64a47846ee61972a8ea5 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Mon, 24 Jun 2013 14:36:34 +0200 +Subject: mmc: sh_mmcif: add support for Device Tree DMA bindings + +To use DMA in the Device Tree case the driver has to be modified +to use suitable API to obtain DMA channels. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Signed-off-by: Chris Ball <cjb@laptop.org> +(cherry picked from commit acd6d772a04989eb836e98f005155793f51efc7d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/sh_mmcif.c | 26 ++++++++++++++++---------- + 1 file changed, 16 insertions(+), 10 deletions(-) + +diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c +index 5c419557..21264bd6 100644 +--- a/drivers/mmc/host/sh_mmcif.c ++++ b/drivers/mmc/host/sh_mmcif.c +@@ -387,25 +387,29 @@ static void sh_mmcif_request_dma(struct sh_mmcif_host *host, + + host->dma_active = false; + +- if (!pdata) +- return; +- +- if (pdata->slave_id_tx <= 0 || pdata->slave_id_rx <= 0) ++ if (pdata) { ++ if (pdata->slave_id_tx <= 0 || pdata->slave_id_rx <= 0) ++ return; ++ } else if (!host->pd->dev.of_node) { + return; ++ } + + /* We can only either use DMA for both Tx and Rx or not use it at all */ + dma_cap_zero(mask); + dma_cap_set(DMA_SLAVE, mask); + +- host->chan_tx = dma_request_channel(mask, shdma_chan_filter, +- (void *)pdata->slave_id_tx); ++ host->chan_tx = dma_request_slave_channel_compat(mask, shdma_chan_filter, ++ pdata ? (void *)pdata->slave_id_tx : NULL, ++ &host->pd->dev, "tx"); + dev_dbg(&host->pd->dev, "%s: TX: got channel %p\n", __func__, + host->chan_tx); + + if (!host->chan_tx) + return; + +- cfg.slave_id = pdata->slave_id_tx; ++ /* In the OF case the driver will get the slave ID from the DT */ ++ if (pdata) ++ cfg.slave_id = pdata->slave_id_tx; + cfg.direction = DMA_MEM_TO_DEV; + cfg.dst_addr = res->start + MMCIF_CE_DATA; + cfg.src_addr = 0; +@@ -413,15 +417,17 @@ static void sh_mmcif_request_dma(struct sh_mmcif_host *host, + if (ret < 0) + goto ecfgtx; + +- host->chan_rx = dma_request_channel(mask, shdma_chan_filter, +- (void *)pdata->slave_id_rx); ++ host->chan_rx = dma_request_slave_channel_compat(mask, shdma_chan_filter, ++ pdata ? (void *)pdata->slave_id_rx : NULL, ++ &host->pd->dev, "rx"); + dev_dbg(&host->pd->dev, "%s: RX: got channel %p\n", __func__, + host->chan_rx); + + if (!host->chan_rx) + goto erqrx; + +- cfg.slave_id = pdata->slave_id_rx; ++ if (pdata) ++ cfg.slave_id = pdata->slave_id_rx; + cfg.direction = DMA_DEV_TO_MEM; + cfg.dst_addr = 0; + cfg.src_addr = res->start + MMCIF_CE_DATA; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0059-mmc-sh_mmcif-revision-specific-Command-Completion-Si.patch b/patches.renesas/0059-mmc-sh_mmcif-revision-specific-Command-Completion-Si.patch new file mode 100644 index 00000000000..b6b4745b968 --- /dev/null +++ b/patches.renesas/0059-mmc-sh_mmcif-revision-specific-Command-Completion-Si.patch @@ -0,0 +1,125 @@ +From 6937bdd1e963729c156f063731bf08ae4b6916da Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Wed, 10 Jul 2013 21:21:12 +0200 +Subject: mmc: sh_mmcif: revision-specific Command Completion Signal handling + +Some earlier MMCIF IP revisions contained Command Completion Signal +support, which has been dropped again in modern versions. Sopport for +this feature is added in a way to preserve the current behaviour by +default, i.e. when it is not enabled in platform data. Patch is based +on work by Nobuyuki HIRAI. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Signed-off-by: Chris Ball <cjb@laptop.org> +(cherry picked from commit 967bcb77177cda1a426fdb2350e6ec61bcf5b5eb) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/sh_mmcif.c | 27 +++++++++++++++++++++------ + include/linux/mmc/sh_mmcif.h | 1 + + 2 files changed, 22 insertions(+), 6 deletions(-) + +diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c +index 21264bd6..c49a2d96 100644 +--- a/drivers/mmc/host/sh_mmcif.c ++++ b/drivers/mmc/host/sh_mmcif.c +@@ -134,6 +134,8 @@ + INT_BUFWEN | INT_CMD12DRE | INT_BUFRE | \ + INT_DTRANE | INT_CMD12RBE | INT_CMD12CRE) + ++#define INT_CCS (INT_CCSTO | INT_CCSRCV | INT_CCSDE) ++ + /* CE_INT_MASK */ + #define MASK_ALL 0x00000000 + #define MASK_MCCSDE (1 << 29) +@@ -162,7 +164,7 @@ + + #define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \ + MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \ +- MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | \ ++ MASK_MCRCSTO | MASK_MWDATTO | \ + MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO) + + #define MASK_CLEAN (INT_ERR_STS | MASK_MRBSYE | MASK_MCRSPE | \ +@@ -244,6 +246,7 @@ struct sh_mmcif_host { + int sg_blkidx; + bool power; + bool card_present; ++ bool ccs_enable; /* Command Completion Signal support */ + struct mutex thread_lock; + + /* DMA support */ +@@ -492,8 +495,10 @@ static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) + + sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); + sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); ++ if (host->ccs_enable) ++ tmp |= SCCSTO_29; + sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | +- SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29); ++ SRSPTO_256 | SRBSYTO_29 | SRWDTO_29); + /* byte swap on */ + sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); + } +@@ -873,6 +878,9 @@ static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, + break; + } + ++ if (host->ccs_enable) ++ mask |= MASK_MCCSTO; ++ + if (mrq->data) { + sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); + sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, +@@ -880,7 +888,10 @@ static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, + } + opc = sh_mmcif_set_cmd(host, mrq); + +- sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); ++ if (host->ccs_enable) ++ sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); ++ else ++ sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0 | INT_CCS); + sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); + /* set arg */ + sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); +@@ -1245,11 +1256,14 @@ static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id) + static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) + { + struct sh_mmcif_host *host = dev_id; +- u32 state; ++ u32 state, mask; + + state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); +- sh_mmcif_writel(host->addr, MMCIF_CE_INT, +- ~(state & sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK))); ++ mask = sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK); ++ if (host->ccs_enable) ++ sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~(state & mask)); ++ else ++ sh_mmcif_writel(host->addr, MMCIF_CE_INT, INT_CCS | ~(state & mask)); + sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN); + + if (state & ~MASK_CLEAN) +@@ -1383,6 +1397,7 @@ static int sh_mmcif_probe(struct platform_device *pdev) + host->mmc = mmc; + host->addr = reg; + host->timeout = msecs_to_jiffies(1000); ++ host->ccs_enable = !pd || !pd->ccs_unsupported; + + host->pd = pdev; + +diff --git a/include/linux/mmc/sh_mmcif.h b/include/linux/mmc/sh_mmcif.h +index c4880ffb..197ed91f 100644 +--- a/include/linux/mmc/sh_mmcif.h ++++ b/include/linux/mmc/sh_mmcif.h +@@ -36,6 +36,7 @@ struct sh_mmcif_plat_data { + unsigned int slave_id_tx; /* embedded slave_id_[tr]x */ + unsigned int slave_id_rx; + bool use_cd_gpio : 1; ++ bool ccs_unsupported : 1; + unsigned int cd_gpio; + u8 sup_pclk; /* 1 :SH7757, 0: SH7724/SH7372 */ + unsigned long caps; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0060-mmc-sh_mmcif-revision-specific-CLK_CTRL2-handling.patch b/patches.renesas/0060-mmc-sh_mmcif-revision-specific-CLK_CTRL2-handling.patch new file mode 100644 index 00000000000..ef126725be7 --- /dev/null +++ b/patches.renesas/0060-mmc-sh_mmcif-revision-specific-CLK_CTRL2-handling.patch @@ -0,0 +1,71 @@ +From 82c16d9ee4e49e577ffbf49bc20578e4e95c371d Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Wed, 10 Jul 2013 21:21:13 +0200 +Subject: mmc: sh_mmcif: revision-specific CLK_CTRL2 handling + +Some newer MMCIF IP revisions contain a CE_CLK_CTRL2 register, that has to +be set for proper operation. Support for this feature is added in a way to +preserve the current behaviour by default, i.e. when it is not enabled +in platform data. Patch is based on work by Nobuyuki HIRAI. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Signed-off-by: Chris Ball <cjb@laptop.org> +(cherry picked from commit 6d6fd3674259d16b735c961743ff28870c46cedc) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/sh_mmcif.c | 4 ++++ + include/linux/mmc/sh_mmcif.h | 2 ++ + 2 files changed, 6 insertions(+) + +diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c +index c49a2d96..e979d2db 100644 +--- a/drivers/mmc/host/sh_mmcif.c ++++ b/drivers/mmc/host/sh_mmcif.c +@@ -247,6 +247,7 @@ struct sh_mmcif_host { + bool power; + bool card_present; + bool ccs_enable; /* Command Completion Signal support */ ++ bool clk_ctrl2_enable; + struct mutex thread_lock; + + /* DMA support */ +@@ -497,6 +498,8 @@ static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) + sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); + if (host->ccs_enable) + tmp |= SCCSTO_29; ++ if (host->clk_ctrl2_enable) ++ sh_mmcif_writel(host->addr, MMCIF_CE_CLK_CTRL2, 0x0F0F0000); + sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | + SRSPTO_256 | SRBSYTO_29 | SRWDTO_29); + /* byte swap on */ +@@ -1398,6 +1401,7 @@ static int sh_mmcif_probe(struct platform_device *pdev) + host->addr = reg; + host->timeout = msecs_to_jiffies(1000); + host->ccs_enable = !pd || !pd->ccs_unsupported; ++ host->clk_ctrl2_enable = pd && pd->clk_ctrl2_present; + + host->pd = pdev; + +diff --git a/include/linux/mmc/sh_mmcif.h b/include/linux/mmc/sh_mmcif.h +index 197ed91f..ccd8fb2c 100644 +--- a/include/linux/mmc/sh_mmcif.h ++++ b/include/linux/mmc/sh_mmcif.h +@@ -37,6 +37,7 @@ struct sh_mmcif_plat_data { + unsigned int slave_id_rx; + bool use_cd_gpio : 1; + bool ccs_unsupported : 1; ++ bool clk_ctrl2_present : 1; + unsigned int cd_gpio; + u8 sup_pclk; /* 1 :SH7757, 0: SH7724/SH7372 */ + unsigned long caps; +@@ -60,6 +61,7 @@ struct sh_mmcif_plat_data { + #define MMCIF_CE_INT_MASK 0x00000044 + #define MMCIF_CE_HOST_STS1 0x00000048 + #define MMCIF_CE_HOST_STS2 0x0000004C ++#define MMCIF_CE_CLK_CTRL2 0x00000070 + #define MMCIF_CE_VERSION 0x0000007C + + /* CE_BUF_ACC */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0061-media-soc-camera-add-host-clock-callbacks-to-start-a.patch b/patches.renesas/0061-media-soc-camera-add-host-clock-callbacks-to-start-a.patch new file mode 100644 index 00000000000..88c744897bd --- /dev/null +++ b/patches.renesas/0061-media-soc-camera-add-host-clock-callbacks-to-start-a.patch @@ -0,0 +1,79 @@ +From b1c6e530403b3583e6527ad87caf4f7b43040834 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Thu, 4 Apr 2013 08:51:36 -0300 +Subject: [media] soc-camera: add host clock callbacks to start and stop the + master clock + +Currently soc-camera uses a single camera host callback to activate the +interface master clock and to configure the interface for a specific +client. However, during probing we might not have the information about +a client, we just need to activate the clock. Add new camera host driver +callbacks to only start and stop the clock without and client-specific +configuration. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Acked-by: Hans Verkuil <hans.verkuil@cisco.com> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> +(cherry picked from commit eb569cf9db804e6ba34b3a1812415e59d5e43d1a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/soc_camera/soc_camera.c | 19 +++++++++++++++++-- + include/media/soc_camera.h | 2 ++ + 2 files changed, 19 insertions(+), 2 deletions(-) + +diff --git a/drivers/media/platform/soc_camera/soc_camera.c b/drivers/media/platform/soc_camera/soc_camera.c +index 832f0593..df90565c 100644 +--- a/drivers/media/platform/soc_camera/soc_camera.c ++++ b/drivers/media/platform/soc_camera/soc_camera.c +@@ -513,10 +513,23 @@ static int soc_camera_add_device(struct soc_camera_device *icd) + if (ici->icd) + return -EBUSY; + ++ if (ici->ops->clock_start) { ++ ret = ici->ops->clock_start(ici); ++ if (ret < 0) ++ return ret; ++ } ++ + ret = ici->ops->add(icd); +- if (!ret) +- ici->icd = icd; ++ if (ret < 0) ++ goto eadd; ++ ++ ici->icd = icd; + ++ return 0; ++ ++eadd: ++ if (ici->ops->clock_stop) ++ ici->ops->clock_stop(ici); + return ret; + } + +@@ -528,6 +541,8 @@ static void soc_camera_remove_device(struct soc_camera_device *icd) + return; + + ici->ops->remove(icd); ++ if (ici->ops->clock_stop) ++ ici->ops->clock_stop(ici); + ici->icd = NULL; + } + +diff --git a/include/media/soc_camera.h b/include/media/soc_camera.h +index 5a46ce2d..64415ee8 100644 +--- a/include/media/soc_camera.h ++++ b/include/media/soc_camera.h +@@ -74,6 +74,8 @@ struct soc_camera_host_ops { + struct module *owner; + int (*add)(struct soc_camera_device *); + void (*remove)(struct soc_camera_device *); ++ int (*clock_start)(struct soc_camera_host *); ++ void (*clock_stop)(struct soc_camera_host *); + /* + * .get_formats() is called for each client device format, but + * .put_formats() is only called once. Further, if any of the calls to +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0062-media-sh-mobile-ceu-camera-move-interface-activation.patch b/patches.renesas/0062-media-sh-mobile-ceu-camera-move-interface-activation.patch new file mode 100644 index 00000000000..398da3fe18b --- /dev/null +++ b/patches.renesas/0062-media-sh-mobile-ceu-camera-move-interface-activation.patch @@ -0,0 +1,154 @@ +From 8a1a8ecd9cbb41c277077435d975204b6c07baae Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Thu, 4 Apr 2013 12:54:20 -0300 +Subject: [media] sh-mobile-ceu-camera: move interface activation and + deactivation to clock callbacks + +When adding and removing a client, the sh-mobile-ceu-camera driver activates +and, respectively, deactivates its camera interface and, if necessary, the +CSI2 controller. Only handling of the CSI2 interface is client-specific and +is only needed, when a data-exchange with the client is taking place. Move +the rest to .clock_start() and .clock_stop() callbacks. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Acked-by: Hans Verkuil <hans.verkuil@cisco.com> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> +(cherry picked from commit 0ff6a6e8fb6915e68b93ff169b1eb66c0ba15d56) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + .../platform/soc_camera/sh_mobile_ceu_camera.c | 58 +++++++++++++--------- + 1 file changed, 35 insertions(+), 23 deletions(-) + +diff --git a/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c b/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c +index 5b7d8e1d..9037472e 100644 +--- a/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c ++++ b/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c +@@ -162,7 +162,6 @@ static u32 ceu_read(struct sh_mobile_ceu_dev *priv, unsigned long reg_offs) + static int sh_mobile_ceu_soft_reset(struct sh_mobile_ceu_dev *pcdev) + { + int i, success = 0; +- struct soc_camera_device *icd = pcdev->ici.icd; + + ceu_write(pcdev, CAPSR, 1 << 16); /* reset */ + +@@ -186,7 +185,7 @@ static int sh_mobile_ceu_soft_reset(struct sh_mobile_ceu_dev *pcdev) + + + if (2 != success) { +- dev_warn(icd->pdev, "soft reset time out\n"); ++ dev_warn(pcdev->ici.v4l2_dev.dev, "soft reset time out\n"); + return -EIO; + } + +@@ -543,35 +542,21 @@ static struct v4l2_subdev *find_csi2(struct sh_mobile_ceu_dev *pcdev) + return NULL; + } + +-/* Called with .host_lock held */ + static int sh_mobile_ceu_add_device(struct soc_camera_device *icd) + { + struct soc_camera_host *ici = to_soc_camera_host(icd->parent); + struct sh_mobile_ceu_dev *pcdev = ici->priv; +- struct v4l2_subdev *csi2_sd; ++ struct v4l2_subdev *csi2_sd = find_csi2(pcdev); + int ret; + +- dev_info(icd->parent, +- "SuperH Mobile CEU driver attached to camera %d\n", +- icd->devnum); +- +- pm_runtime_get_sync(ici->v4l2_dev.dev); +- +- pcdev->buf_total = 0; +- +- ret = sh_mobile_ceu_soft_reset(pcdev); +- +- csi2_sd = find_csi2(pcdev); + if (csi2_sd) { + csi2_sd->grp_id = soc_camera_grp_id(icd); + v4l2_set_subdev_hostdata(csi2_sd, icd); + } + + ret = v4l2_subdev_call(csi2_sd, core, s_power, 1); +- if (ret < 0 && ret != -ENOIOCTLCMD && ret != -ENODEV) { +- pm_runtime_put(ici->v4l2_dev.dev); ++ if (ret < 0 && ret != -ENOIOCTLCMD && ret != -ENODEV) + return ret; +- } + + /* + * -ENODEV is special: either csi2_sd == NULL or the CSI-2 driver +@@ -580,19 +565,48 @@ static int sh_mobile_ceu_add_device(struct soc_camera_device *icd) + if (ret == -ENODEV && csi2_sd) + csi2_sd->grp_id = 0; + ++ dev_info(icd->parent, ++ "SuperH Mobile CEU driver attached to camera %d\n", ++ icd->devnum); ++ + return 0; + } + +-/* Called with .host_lock held */ + static void sh_mobile_ceu_remove_device(struct soc_camera_device *icd) + { + struct soc_camera_host *ici = to_soc_camera_host(icd->parent); + struct sh_mobile_ceu_dev *pcdev = ici->priv; + struct v4l2_subdev *csi2_sd = find_csi2(pcdev); + ++ dev_info(icd->parent, ++ "SuperH Mobile CEU driver detached from camera %d\n", ++ icd->devnum); ++ + v4l2_subdev_call(csi2_sd, core, s_power, 0); + if (csi2_sd) + csi2_sd->grp_id = 0; ++} ++ ++/* Called with .host_lock held */ ++static int sh_mobile_ceu_clock_start(struct soc_camera_host *ici) ++{ ++ struct sh_mobile_ceu_dev *pcdev = ici->priv; ++ int ret; ++ ++ pm_runtime_get_sync(ici->v4l2_dev.dev); ++ ++ pcdev->buf_total = 0; ++ ++ ret = sh_mobile_ceu_soft_reset(pcdev); ++ ++ return 0; ++} ++ ++/* Called with .host_lock held */ ++static void sh_mobile_ceu_clock_stop(struct soc_camera_host *ici) ++{ ++ struct sh_mobile_ceu_dev *pcdev = ici->priv; ++ + /* disable capture, disable interrupts */ + ceu_write(pcdev, CEIER, 0); + sh_mobile_ceu_soft_reset(pcdev); +@@ -607,10 +621,6 @@ static void sh_mobile_ceu_remove_device(struct soc_camera_device *icd) + spin_unlock_irq(&pcdev->lock); + + pm_runtime_put(ici->v4l2_dev.dev); +- +- dev_info(icd->parent, +- "SuperH Mobile CEU driver detached from camera %d\n", +- icd->devnum); + } + + /* +@@ -2027,6 +2037,8 @@ static struct soc_camera_host_ops sh_mobile_ceu_host_ops = { + .owner = THIS_MODULE, + .add = sh_mobile_ceu_add_device, + .remove = sh_mobile_ceu_remove_device, ++ .clock_start = sh_mobile_ceu_clock_start, ++ .clock_stop = sh_mobile_ceu_clock_stop, + .get_formats = sh_mobile_ceu_get_formats, + .put_formats = sh_mobile_ceu_put_formats, + .get_crop = sh_mobile_ceu_get_crop, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0063-media-sh-mobile-ceu-camera-add-primitive-OF-support.patch b/patches.renesas/0063-media-sh-mobile-ceu-camera-add-primitive-OF-support.patch new file mode 100644 index 00000000000..fbb1e127405 --- /dev/null +++ b/patches.renesas/0063-media-sh-mobile-ceu-camera-add-primitive-OF-support.patch @@ -0,0 +1,139 @@ +From ebe5f6eafcfdc6e8af99577a4ce98356e751662e Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Mon, 17 Sep 2012 07:42:55 -0300 +Subject: [media] sh-mobile-ceu-camera: add primitive OF support + +Add an OF hook to sh_mobile_ceu_camera.c, no properties so far. Booting +with DT also requires platform data to be optional. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Acked-by: Hans Verkuil <hans.verkuil@cisco.com> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> +(cherry picked from commit f146e4e79a6f5d457553dfe2ac66b93c7a39f676) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + .../platform/soc_camera/sh_mobile_ceu_camera.c | 33 +++++++++++++++------- + 1 file changed, 23 insertions(+), 10 deletions(-) + +diff --git a/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c b/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c +index 9037472e..fcc13d8e 100644 +--- a/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c ++++ b/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c +@@ -27,6 +27,7 @@ + #include <linux/kernel.h> + #include <linux/mm.h> + #include <linux/moduleparam.h> ++#include <linux/of.h> + #include <linux/time.h> + #include <linux/slab.h> + #include <linux/device.h> +@@ -118,6 +119,7 @@ struct sh_mobile_ceu_dev { + + enum v4l2_field field; + int sequence; ++ unsigned long flags; + + unsigned int image_mode:1; + unsigned int is_16bit:1; +@@ -706,7 +708,7 @@ static void sh_mobile_ceu_set_rect(struct soc_camera_device *icd) + } + + /* CSI2 special configuration */ +- if (pcdev->pdata->csi2) { ++ if (pcdev->csi2_pdev) { + in_width = ((in_width - 2) * 2); + left_offset *= 2; + } +@@ -810,7 +812,7 @@ static int sh_mobile_ceu_set_bus_param(struct soc_camera_device *icd) + /* Make choises, based on platform preferences */ + if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) && + (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) { +- if (pcdev->pdata->flags & SH_CEU_FLAG_HSYNC_LOW) ++ if (pcdev->flags & SH_CEU_FLAG_HSYNC_LOW) + common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH; + else + common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW; +@@ -818,7 +820,7 @@ static int sh_mobile_ceu_set_bus_param(struct soc_camera_device *icd) + + if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) && + (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) { +- if (pcdev->pdata->flags & SH_CEU_FLAG_VSYNC_LOW) ++ if (pcdev->flags & SH_CEU_FLAG_VSYNC_LOW) + common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH; + else + common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW; +@@ -873,11 +875,11 @@ static int sh_mobile_ceu_set_bus_param(struct soc_camera_device *icd) + value |= common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW ? 1 << 1 : 0; + value |= common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW ? 1 << 0 : 0; + +- if (pcdev->pdata->csi2) /* CSI2 mode */ ++ if (pcdev->csi2_pdev) /* CSI2 mode */ + value |= 3 << 12; + else if (pcdev->is_16bit) + value |= 1 << 12; +- else if (pcdev->pdata->flags & SH_CEU_FLAG_LOWER_8BIT) ++ else if (pcdev->flags & SH_CEU_FLAG_LOWER_8BIT) + value |= 2 << 12; + + ceu_write(pcdev, CAMCR, value); +@@ -1052,7 +1054,7 @@ static int sh_mobile_ceu_get_formats(struct soc_camera_device *icd, unsigned int + return 0; + } + +- if (!pcdev->pdata->csi2) { ++ if (!pcdev->pdata || !pcdev->pdata->csi2) { + /* Are there any restrictions in the CSI-2 case? */ + ret = sh_mobile_ceu_try_bus_param(icd, fmt->bits_per_sample); + if (ret < 0) +@@ -2107,13 +2109,17 @@ static int sh_mobile_ceu_probe(struct platform_device *pdev) + init_completion(&pcdev->complete); + + pcdev->pdata = pdev->dev.platform_data; +- if (!pcdev->pdata) { ++ if (!pcdev->pdata && !pdev->dev.of_node) { + dev_err(&pdev->dev, "CEU platform data not set.\n"); + return -EINVAL; + } + +- pcdev->max_width = pcdev->pdata->max_width ? : 2560; +- pcdev->max_height = pcdev->pdata->max_height ? : 1920; ++ /* TODO: implement per-device bus flags */ ++ if (pcdev->pdata) { ++ pcdev->max_width = pcdev->pdata->max_width ? : 2560; ++ pcdev->max_height = pcdev->pdata->max_height ? : 1920; ++ pcdev->flags = pcdev->pdata->flags; ++ } + + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) +@@ -2168,7 +2174,7 @@ static int sh_mobile_ceu_probe(struct platform_device *pdev) + goto exit_free_ctx; + + /* CSI2 interfacing */ +- csi2 = pcdev->pdata->csi2; ++ csi2 = pcdev->pdata ? pcdev->pdata->csi2 : NULL; + if (csi2) { + struct platform_device *csi2_pdev = + platform_device_alloc("sh-mobile-csi2", csi2->id); +@@ -2290,10 +2296,17 @@ static const struct dev_pm_ops sh_mobile_ceu_dev_pm_ops = { + .runtime_resume = sh_mobile_ceu_runtime_nop, + }; + ++static const struct of_device_id sh_mobile_ceu_of_match[] = { ++ { .compatible = "renesas,sh-mobile-ceu" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, sh_mobile_ceu_of_match); ++ + static struct platform_driver sh_mobile_ceu_driver = { + .driver = { + .name = "sh_mobile_ceu", + .pm = &sh_mobile_ceu_dev_pm_ops, ++ .of_match_table = sh_mobile_ceu_of_match, + }, + .probe = sh_mobile_ceu_probe, + .remove = sh_mobile_ceu_remove, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0064-media-sh-mobile-ceu-driver-support-max-width-and-hei.patch b/patches.renesas/0064-media-sh-mobile-ceu-driver-support-max-width-and-hei.patch new file mode 100644 index 00000000000..294d10e934d --- /dev/null +++ b/patches.renesas/0064-media-sh-mobile-ceu-driver-support-max-width-and-hei.patch @@ -0,0 +1,84 @@ +From 8b35032af7aa5e67ed88ceb5d66f7a95490083c5 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Mon, 17 Sep 2012 07:48:33 -0300 +Subject: [media] sh-mobile-ceu-driver: support max width and height in DT + +Some CEU implementations have non-standard (larger) maximum supported +width and height values. Add two OF properties to specify them. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Acked-by: Hans Verkuil <hans.verkuil@cisco.com> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> +(cherry picked from commit 812e8b22ea55218449de310a666dd1ce16f924ed) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + .../devicetree/bindings/media/sh_mobile_ceu.txt | 18 +++++++++++++++++ + .../platform/soc_camera/sh_mobile_ceu_camera.c | 23 ++++++++++++++++++++-- + 2 files changed, 39 insertions(+), 2 deletions(-) + create mode 100644 Documentation/devicetree/bindings/media/sh_mobile_ceu.txt + +diff --git a/Documentation/devicetree/bindings/media/sh_mobile_ceu.txt b/Documentation/devicetree/bindings/media/sh_mobile_ceu.txt +new file mode 100644 +index 00000000..1ce4e46b +--- /dev/null ++++ b/Documentation/devicetree/bindings/media/sh_mobile_ceu.txt +@@ -0,0 +1,18 @@ ++Bindings, specific for the sh_mobile_ceu_camera.c driver: ++ - compatible: Should be "renesas,sh-mobile-ceu" ++ - reg: register base and size ++ - interrupts: the interrupt number ++ - interrupt-parent: the interrupt controller ++ - renesas,max-width: maximum image width, supported on this SoC ++ - renesas,max-height: maximum image height, supported on this SoC ++ ++Example: ++ ++ceu0: ceu@0xfe910000 { ++ compatible = "renesas,sh-mobile-ceu"; ++ reg = <0xfe910000 0xa0>; ++ interrupt-parent = <&intcs>; ++ interrupts = <0x880>; ++ renesas,max-width = <8188>; ++ renesas,max-height = <8188>; ++}; +diff --git a/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c b/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c +index fcc13d8e..b0f0995f 100644 +--- a/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c ++++ b/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c +@@ -2116,11 +2116,30 @@ static int sh_mobile_ceu_probe(struct platform_device *pdev) + + /* TODO: implement per-device bus flags */ + if (pcdev->pdata) { +- pcdev->max_width = pcdev->pdata->max_width ? : 2560; +- pcdev->max_height = pcdev->pdata->max_height ? : 1920; ++ pcdev->max_width = pcdev->pdata->max_width; ++ pcdev->max_height = pcdev->pdata->max_height; + pcdev->flags = pcdev->pdata->flags; + } + ++ if (!pcdev->max_width) { ++ unsigned int v; ++ err = of_property_read_u32(pdev->dev.of_node, "renesas,max-width", &v); ++ if (!err) ++ pcdev->max_width = v; ++ ++ if (!pcdev->max_width) ++ pcdev->max_width = 2560; ++ } ++ if (!pcdev->max_height) { ++ unsigned int v; ++ err = of_property_read_u32(pdev->dev.of_node, "renesas,max-height", &v); ++ if (!err) ++ pcdev->max_height = v; ++ ++ if (!pcdev->max_height) ++ pcdev->max_height = 1920; ++ } ++ + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0065-media-V4L2-sh_mobile_ceu_camera-remove-CEU-specific-.patch b/patches.renesas/0065-media-V4L2-sh_mobile_ceu_camera-remove-CEU-specific-.patch new file mode 100644 index 00000000000..1c09affcfb7 --- /dev/null +++ b/patches.renesas/0065-media-V4L2-sh_mobile_ceu_camera-remove-CEU-specific-.patch @@ -0,0 +1,363 @@ +From 4861e6a9682168926310f0431b9ad5ee0e0dad0b Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Wed, 24 Apr 2013 11:15:30 -0300 +Subject: [media] V4L2: sh_mobile_ceu_camera: remove CEU specific data from + generic functions + +Several functions in the sh_mobile_ceu_camera driver implement generic +algorithms and can be re-used by other V4L2 camera host drivers too. These +functions attempt to optimise scaling and cropping functions of the +subdevice, e.g. a camera sensor. This patch makes those functions generic +for future re-use by other camera host drivers. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> +(cherry picked from commit eca430c83d3b63df52024d114b7641bd03482f38) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + .../platform/soc_camera/sh_mobile_ceu_camera.c | 130 +++++++++++---------- + 1 file changed, 71 insertions(+), 59 deletions(-) + +diff --git a/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c b/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c +index b0f0995f..56ba7de7 100644 +--- a/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c ++++ b/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c +@@ -996,7 +996,7 @@ static bool sh_mobile_ceu_packing_supported(const struct soc_mbus_pixelfmt *fmt) + fmt->packing == SOC_MBUS_PACKING_EXTEND16); + } + +-static int client_g_rect(struct v4l2_subdev *sd, struct v4l2_rect *rect); ++static int soc_camera_client_g_rect(struct v4l2_subdev *sd, struct v4l2_rect *rect); + + static struct soc_camera_device *ctrl_to_icd(struct v4l2_ctrl *ctrl) + { +@@ -1075,7 +1075,7 @@ static int sh_mobile_ceu_get_formats(struct soc_camera_device *icd, unsigned int + /* FIXME: subwindow is lost between close / open */ + + /* Cache current client geometry */ +- ret = client_g_rect(sd, &rect); ++ ret = soc_camera_client_g_rect(sd, &rect); + if (ret < 0) + return ret; + +@@ -1199,18 +1199,23 @@ static bool is_inside(const struct v4l2_rect *r1, const struct v4l2_rect *r2) + r1->top + r1->height < r2->top + r2->height; + } + +-static unsigned int scale_down(unsigned int size, unsigned int scale) ++static unsigned int soc_camera_shift_scale(unsigned int size, unsigned int shift, ++ unsigned int scale) + { +- return (size * 4096 + scale / 2) / scale; ++ return ((size << shift) + scale / 2) / scale; + } + +-static unsigned int calc_generic_scale(unsigned int input, unsigned int output) ++static unsigned int soc_camera_calc_scale(unsigned int input, unsigned int shift, ++ unsigned int output) + { +- return (input * 4096 + output / 2) / output; ++ return soc_camera_shift_scale(input, shift, output); + } + ++#define scale_down(size, scale) soc_camera_shift_scale(size, 12, scale) ++#define calc_generic_scale(in, out) soc_camera_shift_scale(in, 12, out) ++ + /* Get and store current client crop */ +-static int client_g_rect(struct v4l2_subdev *sd, struct v4l2_rect *rect) ++static int soc_camera_client_g_rect(struct v4l2_subdev *sd, struct v4l2_rect *rect) + { + struct v4l2_crop crop; + struct v4l2_cropcap cap; +@@ -1235,10 +1240,8 @@ static int client_g_rect(struct v4l2_subdev *sd, struct v4l2_rect *rect) + } + + /* Client crop has changed, update our sub-rectangle to remain within the area */ +-static void update_subrect(struct sh_mobile_ceu_cam *cam) ++static void update_subrect(struct v4l2_rect *rect, struct v4l2_rect *subrect) + { +- struct v4l2_rect *rect = &cam->rect, *subrect = &cam->subrect; +- + if (rect->width < subrect->width) + subrect->width = rect->width; + +@@ -1266,19 +1269,18 @@ static void update_subrect(struct sh_mobile_ceu_cam *cam) + * 2. if (1) failed, try to double the client image until we get one big enough + * 3. if (2) failed, try to request the maximum image + */ +-static int client_s_crop(struct soc_camera_device *icd, struct v4l2_crop *crop, +- struct v4l2_crop *cam_crop) ++static int soc_camera_client_s_crop(struct v4l2_subdev *sd, ++ struct v4l2_crop *crop, struct v4l2_crop *cam_crop, ++ struct v4l2_rect *target_rect, struct v4l2_rect *subrect) + { +- struct v4l2_subdev *sd = soc_camera_to_subdev(icd); + struct v4l2_rect *rect = &crop->c, *cam_rect = &cam_crop->c; + struct device *dev = sd->v4l2_dev->dev; +- struct sh_mobile_ceu_cam *cam = icd->host_priv; + struct v4l2_cropcap cap; + int ret; + unsigned int width, height; + + v4l2_subdev_call(sd, video, s_crop, crop); +- ret = client_g_rect(sd, cam_rect); ++ ret = soc_camera_client_g_rect(sd, cam_rect); + if (ret < 0) + return ret; + +@@ -1290,7 +1292,7 @@ static int client_s_crop(struct soc_camera_device *icd, struct v4l2_crop *crop, + /* Even if camera S_CROP failed, but camera rectangle matches */ + dev_dbg(dev, "Camera S_CROP successful for %dx%d@%d:%d\n", + rect->width, rect->height, rect->left, rect->top); +- cam->rect = *cam_rect; ++ *target_rect = *cam_rect; + return 0; + } + +@@ -1356,7 +1358,7 @@ static int client_s_crop(struct soc_camera_device *icd, struct v4l2_crop *crop, + cam_rect->top; + + v4l2_subdev_call(sd, video, s_crop, cam_crop); +- ret = client_g_rect(sd, cam_rect); ++ ret = soc_camera_client_g_rect(sd, cam_rect); + dev_geo(dev, "Camera S_CROP %d for %dx%d@%d:%d\n", ret, + cam_rect->width, cam_rect->height, + cam_rect->left, cam_rect->top); +@@ -1370,15 +1372,15 @@ static int client_s_crop(struct soc_camera_device *icd, struct v4l2_crop *crop, + */ + *cam_rect = cap.bounds; + v4l2_subdev_call(sd, video, s_crop, cam_crop); +- ret = client_g_rect(sd, cam_rect); ++ ret = soc_camera_client_g_rect(sd, cam_rect); + dev_geo(dev, "Camera S_CROP %d for max %dx%d@%d:%d\n", ret, + cam_rect->width, cam_rect->height, + cam_rect->left, cam_rect->top); + } + + if (!ret) { +- cam->rect = *cam_rect; +- update_subrect(cam); ++ *target_rect = *cam_rect; ++ update_subrect(target_rect, subrect); + } + + return ret; +@@ -1386,15 +1388,13 @@ static int client_s_crop(struct soc_camera_device *icd, struct v4l2_crop *crop, + + /* Iterative s_mbus_fmt, also updates cached client crop on success */ + static int client_s_fmt(struct soc_camera_device *icd, +- struct v4l2_mbus_framefmt *mf, bool ceu_can_scale) ++ struct v4l2_rect *rect, struct v4l2_rect *subrect, ++ unsigned int max_width, unsigned int max_height, ++ struct v4l2_mbus_framefmt *mf, bool host_can_scale) + { +- struct soc_camera_host *ici = to_soc_camera_host(icd->parent); +- struct sh_mobile_ceu_dev *pcdev = ici->priv; +- struct sh_mobile_ceu_cam *cam = icd->host_priv; + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); + struct device *dev = icd->parent; + unsigned int width = mf->width, height = mf->height, tmp_w, tmp_h; +- unsigned int max_width, max_height; + struct v4l2_cropcap cap; + bool ceu_1to1; + int ret; +@@ -1414,7 +1414,7 @@ static int client_s_fmt(struct soc_camera_device *icd, + } + + ceu_1to1 = false; +- if (!ceu_can_scale) ++ if (!host_can_scale) + goto update_cache; + + cap.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; +@@ -1423,8 +1423,10 @@ static int client_s_fmt(struct soc_camera_device *icd, + if (ret < 0) + return ret; + +- max_width = min(cap.bounds.width, pcdev->max_width); +- max_height = min(cap.bounds.height, pcdev->max_height); ++ if (max_width > cap.bounds.width) ++ max_width = cap.bounds.width; ++ if (max_height > cap.bounds.height) ++ max_height = cap.bounds.height; + + /* Camera set a format, but geometry is not precise, try to improve */ + tmp_w = mf->width; +@@ -1451,29 +1453,36 @@ static int client_s_fmt(struct soc_camera_device *icd, + + update_cache: + /* Update cache */ +- ret = client_g_rect(sd, &cam->rect); ++ ret = soc_camera_client_g_rect(sd, rect); + if (ret < 0) + return ret; + + if (ceu_1to1) +- cam->subrect = cam->rect; ++ *subrect = *rect; + else +- update_subrect(cam); ++ update_subrect(rect, subrect); + + return 0; + } + + /** +- * @width - on output: user width, mapped back to input +- * @height - on output: user height, mapped back to input ++ * @icd - soc-camera device ++ * @rect - camera cropping window ++ * @subrect - part of rect, sent to the user + * @mf - in- / output camera output window ++ * @width - on input: max host input width ++ * on output: user width, mapped back to input ++ * @height - on input: max host input height ++ * on output: user height, mapped back to input ++ * @host_can_scale - host can scale this pixel format ++ * @shift - shift, used for scaling + */ +-static int client_scale(struct soc_camera_device *icd, ++static int soc_camera_client_scale(struct soc_camera_device *icd, ++ struct v4l2_rect *rect, struct v4l2_rect *subrect, + struct v4l2_mbus_framefmt *mf, + unsigned int *width, unsigned int *height, +- bool ceu_can_scale) ++ bool host_can_scale, unsigned int shift) + { +- struct sh_mobile_ceu_cam *cam = icd->host_priv; + struct device *dev = icd->parent; + struct v4l2_mbus_framefmt mf_tmp = *mf; + unsigned int scale_h, scale_v; +@@ -1483,7 +1492,8 @@ static int client_scale(struct soc_camera_device *icd, + * 5. Apply iterative camera S_FMT for camera user window (also updates + * client crop cache and the imaginary sub-rectangle). + */ +- ret = client_s_fmt(icd, &mf_tmp, ceu_can_scale); ++ ret = client_s_fmt(icd, rect, subrect, *width, *height, ++ &mf_tmp, host_can_scale); + if (ret < 0) + return ret; + +@@ -1495,8 +1505,8 @@ static int client_scale(struct soc_camera_device *icd, + /* unneeded - it is already in "mf_tmp" */ + + /* 7. Calculate new client scales. */ +- scale_h = calc_generic_scale(cam->rect.width, mf_tmp.width); +- scale_v = calc_generic_scale(cam->rect.height, mf_tmp.height); ++ scale_h = soc_camera_calc_scale(rect->width, shift, mf_tmp.width); ++ scale_v = soc_camera_calc_scale(rect->height, shift, mf_tmp.height); + + mf->width = mf_tmp.width; + mf->height = mf_tmp.height; +@@ -1506,8 +1516,8 @@ static int client_scale(struct soc_camera_device *icd, + * 8. Calculate new CEU crop - apply camera scales to previously + * updated "effective" crop. + */ +- *width = scale_down(cam->subrect.width, scale_h); +- *height = scale_down(cam->subrect.height, scale_v); ++ *width = soc_camera_shift_scale(subrect->width, shift, scale_h); ++ *height = soc_camera_shift_scale(subrect->height, shift, scale_v); + + dev_geo(dev, "8: new client sub-window %ux%u\n", *width, *height); + +@@ -1550,7 +1560,8 @@ static int sh_mobile_ceu_set_crop(struct soc_camera_device *icd, + * 1. - 2. Apply iterative camera S_CROP for new input window, read back + * actual camera rectangle. + */ +- ret = client_s_crop(icd, &a_writable, &cam_crop); ++ ret = soc_camera_client_s_crop(sd, &a_writable, &cam_crop, ++ &cam->rect, &cam->subrect); + if (ret < 0) + return ret; + +@@ -1674,16 +1685,16 @@ static int sh_mobile_ceu_get_crop(struct soc_camera_device *icd, + * client crop. New scales are calculated from the requested output format and + * CEU crop, mapped backed onto the client input (subrect). + */ +-static void calculate_client_output(struct soc_camera_device *icd, +- const struct v4l2_pix_format *pix, struct v4l2_mbus_framefmt *mf) ++static void soc_camera_calc_client_output(struct soc_camera_device *icd, ++ struct v4l2_rect *rect, struct v4l2_rect *subrect, ++ const struct v4l2_pix_format *pix, struct v4l2_mbus_framefmt *mf, ++ unsigned int shift) + { +- struct sh_mobile_ceu_cam *cam = icd->host_priv; + struct device *dev = icd->parent; +- struct v4l2_rect *cam_subrect = &cam->subrect; + unsigned int scale_v, scale_h; + +- if (cam_subrect->width == cam->rect.width && +- cam_subrect->height == cam->rect.height) { ++ if (subrect->width == rect->width && ++ subrect->height == rect->height) { + /* No sub-cropping */ + mf->width = pix->width; + mf->height = pix->height; +@@ -1693,8 +1704,8 @@ static void calculate_client_output(struct soc_camera_device *icd, + /* 1.-2. Current camera scales and subwin - cached. */ + + dev_geo(dev, "2: subwin %ux%u@%u:%u\n", +- cam_subrect->width, cam_subrect->height, +- cam_subrect->left, cam_subrect->top); ++ subrect->width, subrect->height, ++ subrect->left, subrect->top); + + /* + * 3. Calculate new combined scales from input sub-window to requested +@@ -1705,8 +1716,8 @@ static void calculate_client_output(struct soc_camera_device *icd, + * TODO: CEU cannot scale images larger than VGA to smaller than SubQCIF + * (128x96) or larger than VGA + */ +- scale_h = calc_generic_scale(cam_subrect->width, pix->width); +- scale_v = calc_generic_scale(cam_subrect->height, pix->height); ++ scale_h = soc_camera_calc_scale(subrect->width, shift, pix->width); ++ scale_v = soc_camera_calc_scale(subrect->height, shift, pix->height); + + dev_geo(dev, "3: scales %u:%u\n", scale_h, scale_v); + +@@ -1714,8 +1725,8 @@ static void calculate_client_output(struct soc_camera_device *icd, + * 4. Calculate desired client output window by applying combined scales + * to client (real) input window. + */ +- mf->width = scale_down(cam->rect.width, scale_h); +- mf->height = scale_down(cam->rect.height, scale_v); ++ mf->width = soc_camera_shift_scale(rect->width, shift, scale_h); ++ mf->height = soc_camera_shift_scale(rect->height, shift, scale_v); + } + + /* Similar to set_crop multistage iterative algorithm */ +@@ -1730,8 +1741,8 @@ static int sh_mobile_ceu_set_fmt(struct soc_camera_device *icd, + struct v4l2_mbus_framefmt mf; + __u32 pixfmt = pix->pixelformat; + const struct soc_camera_format_xlate *xlate; +- /* Keep Compiler Happy */ +- unsigned int ceu_sub_width = 0, ceu_sub_height = 0; ++ unsigned int ceu_sub_width = pcdev->max_width, ++ ceu_sub_height = pcdev->max_height; + u16 scale_v, scale_h; + int ret; + bool image_mode; +@@ -1758,7 +1769,7 @@ static int sh_mobile_ceu_set_fmt(struct soc_camera_device *icd, + } + + /* 1.-4. Calculate desired client output geometry */ +- calculate_client_output(icd, pix, &mf); ++ soc_camera_calc_client_output(icd, &cam->rect, &cam->subrect, pix, &mf, 12); + mf.field = pix->field; + mf.colorspace = pix->colorspace; + mf.code = xlate->code; +@@ -1780,8 +1791,9 @@ static int sh_mobile_ceu_set_fmt(struct soc_camera_device *icd, + dev_geo(dev, "4: request camera output %ux%u\n", mf.width, mf.height); + + /* 5. - 9. */ +- ret = client_scale(icd, &mf, &ceu_sub_width, &ceu_sub_height, +- image_mode && V4L2_FIELD_NONE == field); ++ ret = soc_camera_client_scale(icd, &cam->rect, &cam->subrect, ++ &mf, &ceu_sub_width, &ceu_sub_height, ++ image_mode && V4L2_FIELD_NONE == field, 12); + + dev_geo(dev, "5-9: client scale return %d\n", ret); + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0066-media-V4L2-soc-camera-move-generic-functions-into-a-.patch b/patches.renesas/0066-media-V4L2-soc-camera-move-generic-functions-into-a-.patch new file mode 100644 index 00000000000..6bc034f7338 --- /dev/null +++ b/patches.renesas/0066-media-V4L2-soc-camera-move-generic-functions-into-a-.patch @@ -0,0 +1,945 @@ +From eba55652c12f0dd8c6eb46610dfacf616b67079e Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Thu, 25 Apr 2013 08:18:45 -0300 +Subject: [media] V4L2: soc-camera: move generic functions into a separate file + +The sh_mobile_ceu_camera driver implements a generic algorithm for setting +up an optimal client and host scaling and cropping configuration. This +patch makes those functions available for all drivers. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> +(cherry picked from commit 22e0099ac9a968a4a67fc681864a9ff453bd929f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/soc_camera/Kconfig | 4 + + drivers/media/platform/soc_camera/Makefile | 4 + + .../platform/soc_camera/sh_mobile_ceu_camera.c | 391 +------------------- + drivers/media/platform/soc_camera/soc_scale_crop.c | 401 +++++++++++++++++++++ + drivers/media/platform/soc_camera/soc_scale_crop.h | 47 +++ + 5 files changed, 459 insertions(+), 388 deletions(-) + create mode 100644 drivers/media/platform/soc_camera/soc_scale_crop.c + create mode 100644 drivers/media/platform/soc_camera/soc_scale_crop.h + +diff --git a/drivers/media/platform/soc_camera/Kconfig b/drivers/media/platform/soc_camera/Kconfig +index b139b525..99f1952d 100644 +--- a/drivers/media/platform/soc_camera/Kconfig ++++ b/drivers/media/platform/soc_camera/Kconfig +@@ -8,6 +8,9 @@ config SOC_CAMERA + over a bus like PCI or USB. For example some i2c camera connected + directly to the data bus of an SoC. + ++config SOC_CAMERA_SCALE_CROP ++ tristate ++ + config SOC_CAMERA_PLATFORM + tristate "platform camera support" + depends on SOC_CAMERA +@@ -55,6 +58,7 @@ config VIDEO_SH_MOBILE_CEU + tristate "SuperH Mobile CEU Interface driver" + depends on VIDEO_DEV && SOC_CAMERA && HAS_DMA && HAVE_CLK + select VIDEOBUF2_DMA_CONTIG ++ select SOC_CAMERA_SCALE_CROP + ---help--- + This is a v4l2 driver for the SuperH Mobile CEU Interface + +diff --git a/drivers/media/platform/soc_camera/Makefile b/drivers/media/platform/soc_camera/Makefile +index 136b7f8f..7ff714c6 100644 +--- a/drivers/media/platform/soc_camera/Makefile ++++ b/drivers/media/platform/soc_camera/Makefile +@@ -1,4 +1,8 @@ + obj-$(CONFIG_SOC_CAMERA) += soc_camera.o soc_mediabus.o ++obj-$(CONFIG_SOC_CAMERA_SCALE_CROP) += soc_scale_crop.o ++ ++# a platform subdevice driver stub, allowing to support cameras by adding a ++# couple of callback functions to the board code + obj-$(CONFIG_SOC_CAMERA_PLATFORM) += soc_camera_platform.o + + # soc-camera host drivers have to be linked after camera drivers +diff --git a/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c b/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c +index 56ba7de7..905ed7e5 100644 +--- a/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c ++++ b/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c +@@ -45,6 +45,8 @@ + #include <media/v4l2-mediabus.h> + #include <media/soc_mediabus.h> + ++#include "soc_scale_crop.h" ++ + /* register offsets for sh7722 / sh7723 */ + + #define CAPSR 0x00 /* Capture start register */ +@@ -996,8 +998,6 @@ static bool sh_mobile_ceu_packing_supported(const struct soc_mbus_pixelfmt *fmt) + fmt->packing == SOC_MBUS_PACKING_EXTEND16); + } + +-static int soc_camera_client_g_rect(struct v4l2_subdev *sd, struct v4l2_rect *rect); +- + static struct soc_camera_device *ctrl_to_icd(struct v4l2_ctrl *ctrl) + { + return container_of(ctrl->handler, struct soc_camera_device, +@@ -1185,344 +1185,8 @@ static void sh_mobile_ceu_put_formats(struct soc_camera_device *icd) + icd->host_priv = NULL; + } + +-/* Check if any dimension of r1 is smaller than respective one of r2 */ +-static bool is_smaller(const struct v4l2_rect *r1, const struct v4l2_rect *r2) +-{ +- return r1->width < r2->width || r1->height < r2->height; +-} +- +-/* Check if r1 fails to cover r2 */ +-static bool is_inside(const struct v4l2_rect *r1, const struct v4l2_rect *r2) +-{ +- return r1->left > r2->left || r1->top > r2->top || +- r1->left + r1->width < r2->left + r2->width || +- r1->top + r1->height < r2->top + r2->height; +-} +- +-static unsigned int soc_camera_shift_scale(unsigned int size, unsigned int shift, +- unsigned int scale) +-{ +- return ((size << shift) + scale / 2) / scale; +-} +- +-static unsigned int soc_camera_calc_scale(unsigned int input, unsigned int shift, +- unsigned int output) +-{ +- return soc_camera_shift_scale(input, shift, output); +-} +- + #define scale_down(size, scale) soc_camera_shift_scale(size, 12, scale) +-#define calc_generic_scale(in, out) soc_camera_shift_scale(in, 12, out) +- +-/* Get and store current client crop */ +-static int soc_camera_client_g_rect(struct v4l2_subdev *sd, struct v4l2_rect *rect) +-{ +- struct v4l2_crop crop; +- struct v4l2_cropcap cap; +- int ret; +- +- crop.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; +- +- ret = v4l2_subdev_call(sd, video, g_crop, &crop); +- if (!ret) { +- *rect = crop.c; +- return ret; +- } +- +- /* Camera driver doesn't support .g_crop(), assume default rectangle */ +- cap.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; +- +- ret = v4l2_subdev_call(sd, video, cropcap, &cap); +- if (!ret) +- *rect = cap.defrect; +- +- return ret; +-} +- +-/* Client crop has changed, update our sub-rectangle to remain within the area */ +-static void update_subrect(struct v4l2_rect *rect, struct v4l2_rect *subrect) +-{ +- if (rect->width < subrect->width) +- subrect->width = rect->width; +- +- if (rect->height < subrect->height) +- subrect->height = rect->height; +- +- if (rect->left > subrect->left) +- subrect->left = rect->left; +- else if (rect->left + rect->width > +- subrect->left + subrect->width) +- subrect->left = rect->left + rect->width - +- subrect->width; +- +- if (rect->top > subrect->top) +- subrect->top = rect->top; +- else if (rect->top + rect->height > +- subrect->top + subrect->height) +- subrect->top = rect->top + rect->height - +- subrect->height; +-} +- +-/* +- * The common for both scaling and cropping iterative approach is: +- * 1. try if the client can produce exactly what requested by the user +- * 2. if (1) failed, try to double the client image until we get one big enough +- * 3. if (2) failed, try to request the maximum image +- */ +-static int soc_camera_client_s_crop(struct v4l2_subdev *sd, +- struct v4l2_crop *crop, struct v4l2_crop *cam_crop, +- struct v4l2_rect *target_rect, struct v4l2_rect *subrect) +-{ +- struct v4l2_rect *rect = &crop->c, *cam_rect = &cam_crop->c; +- struct device *dev = sd->v4l2_dev->dev; +- struct v4l2_cropcap cap; +- int ret; +- unsigned int width, height; +- +- v4l2_subdev_call(sd, video, s_crop, crop); +- ret = soc_camera_client_g_rect(sd, cam_rect); +- if (ret < 0) +- return ret; +- +- /* +- * Now cam_crop contains the current camera input rectangle, and it must +- * be within camera cropcap bounds +- */ +- if (!memcmp(rect, cam_rect, sizeof(*rect))) { +- /* Even if camera S_CROP failed, but camera rectangle matches */ +- dev_dbg(dev, "Camera S_CROP successful for %dx%d@%d:%d\n", +- rect->width, rect->height, rect->left, rect->top); +- *target_rect = *cam_rect; +- return 0; +- } +- +- /* Try to fix cropping, that camera hasn't managed to set */ +- dev_geo(dev, "Fix camera S_CROP for %dx%d@%d:%d to %dx%d@%d:%d\n", +- cam_rect->width, cam_rect->height, +- cam_rect->left, cam_rect->top, +- rect->width, rect->height, rect->left, rect->top); +- +- /* We need sensor maximum rectangle */ +- ret = v4l2_subdev_call(sd, video, cropcap, &cap); +- if (ret < 0) +- return ret; +- +- /* Put user requested rectangle within sensor bounds */ +- soc_camera_limit_side(&rect->left, &rect->width, cap.bounds.left, 2, +- cap.bounds.width); +- soc_camera_limit_side(&rect->top, &rect->height, cap.bounds.top, 4, +- cap.bounds.height); +- +- /* +- * Popular special case - some cameras can only handle fixed sizes like +- * QVGA, VGA,... Take care to avoid infinite loop. +- */ +- width = max(cam_rect->width, 2); +- height = max(cam_rect->height, 2); +- +- /* +- * Loop as long as sensor is not covering the requested rectangle and +- * is still within its bounds +- */ +- while (!ret && (is_smaller(cam_rect, rect) || +- is_inside(cam_rect, rect)) && +- (cap.bounds.width > width || cap.bounds.height > height)) { +- +- width *= 2; +- height *= 2; +- +- cam_rect->width = width; +- cam_rect->height = height; +- +- /* +- * We do not know what capabilities the camera has to set up +- * left and top borders. We could try to be smarter in iterating +- * them, e.g., if camera current left is to the right of the +- * target left, set it to the middle point between the current +- * left and minimum left. But that would add too much +- * complexity: we would have to iterate each border separately. +- * Instead we just drop to the left and top bounds. +- */ +- if (cam_rect->left > rect->left) +- cam_rect->left = cap.bounds.left; +- +- if (cam_rect->left + cam_rect->width < rect->left + rect->width) +- cam_rect->width = rect->left + rect->width - +- cam_rect->left; +- +- if (cam_rect->top > rect->top) +- cam_rect->top = cap.bounds.top; +- +- if (cam_rect->top + cam_rect->height < rect->top + rect->height) +- cam_rect->height = rect->top + rect->height - +- cam_rect->top; +- +- v4l2_subdev_call(sd, video, s_crop, cam_crop); +- ret = soc_camera_client_g_rect(sd, cam_rect); +- dev_geo(dev, "Camera S_CROP %d for %dx%d@%d:%d\n", ret, +- cam_rect->width, cam_rect->height, +- cam_rect->left, cam_rect->top); +- } +- +- /* S_CROP must not modify the rectangle */ +- if (is_smaller(cam_rect, rect) || is_inside(cam_rect, rect)) { +- /* +- * The camera failed to configure a suitable cropping, +- * we cannot use the current rectangle, set to max +- */ +- *cam_rect = cap.bounds; +- v4l2_subdev_call(sd, video, s_crop, cam_crop); +- ret = soc_camera_client_g_rect(sd, cam_rect); +- dev_geo(dev, "Camera S_CROP %d for max %dx%d@%d:%d\n", ret, +- cam_rect->width, cam_rect->height, +- cam_rect->left, cam_rect->top); +- } +- +- if (!ret) { +- *target_rect = *cam_rect; +- update_subrect(target_rect, subrect); +- } +- +- return ret; +-} +- +-/* Iterative s_mbus_fmt, also updates cached client crop on success */ +-static int client_s_fmt(struct soc_camera_device *icd, +- struct v4l2_rect *rect, struct v4l2_rect *subrect, +- unsigned int max_width, unsigned int max_height, +- struct v4l2_mbus_framefmt *mf, bool host_can_scale) +-{ +- struct v4l2_subdev *sd = soc_camera_to_subdev(icd); +- struct device *dev = icd->parent; +- unsigned int width = mf->width, height = mf->height, tmp_w, tmp_h; +- struct v4l2_cropcap cap; +- bool ceu_1to1; +- int ret; +- +- ret = v4l2_device_call_until_err(sd->v4l2_dev, +- soc_camera_grp_id(icd), video, +- s_mbus_fmt, mf); +- if (ret < 0) +- return ret; +- +- dev_geo(dev, "camera scaled to %ux%u\n", mf->width, mf->height); +- +- if (width == mf->width && height == mf->height) { +- /* Perfect! The client has done it all. */ +- ceu_1to1 = true; +- goto update_cache; +- } +- +- ceu_1to1 = false; +- if (!host_can_scale) +- goto update_cache; +- +- cap.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; +- +- ret = v4l2_subdev_call(sd, video, cropcap, &cap); +- if (ret < 0) +- return ret; +- +- if (max_width > cap.bounds.width) +- max_width = cap.bounds.width; +- if (max_height > cap.bounds.height) +- max_height = cap.bounds.height; +- +- /* Camera set a format, but geometry is not precise, try to improve */ +- tmp_w = mf->width; +- tmp_h = mf->height; +- +- /* width <= max_width && height <= max_height - guaranteed by try_fmt */ +- while ((width > tmp_w || height > tmp_h) && +- tmp_w < max_width && tmp_h < max_height) { +- tmp_w = min(2 * tmp_w, max_width); +- tmp_h = min(2 * tmp_h, max_height); +- mf->width = tmp_w; +- mf->height = tmp_h; +- ret = v4l2_device_call_until_err(sd->v4l2_dev, +- soc_camera_grp_id(icd), video, +- s_mbus_fmt, mf); +- dev_geo(dev, "Camera scaled to %ux%u\n", +- mf->width, mf->height); +- if (ret < 0) { +- /* This shouldn't happen */ +- dev_err(dev, "Client failed to set format: %d\n", ret); +- return ret; +- } +- } +- +-update_cache: +- /* Update cache */ +- ret = soc_camera_client_g_rect(sd, rect); +- if (ret < 0) +- return ret; +- +- if (ceu_1to1) +- *subrect = *rect; +- else +- update_subrect(rect, subrect); +- +- return 0; +-} +- +-/** +- * @icd - soc-camera device +- * @rect - camera cropping window +- * @subrect - part of rect, sent to the user +- * @mf - in- / output camera output window +- * @width - on input: max host input width +- * on output: user width, mapped back to input +- * @height - on input: max host input height +- * on output: user height, mapped back to input +- * @host_can_scale - host can scale this pixel format +- * @shift - shift, used for scaling +- */ +-static int soc_camera_client_scale(struct soc_camera_device *icd, +- struct v4l2_rect *rect, struct v4l2_rect *subrect, +- struct v4l2_mbus_framefmt *mf, +- unsigned int *width, unsigned int *height, +- bool host_can_scale, unsigned int shift) +-{ +- struct device *dev = icd->parent; +- struct v4l2_mbus_framefmt mf_tmp = *mf; +- unsigned int scale_h, scale_v; +- int ret; +- +- /* +- * 5. Apply iterative camera S_FMT for camera user window (also updates +- * client crop cache and the imaginary sub-rectangle). +- */ +- ret = client_s_fmt(icd, rect, subrect, *width, *height, +- &mf_tmp, host_can_scale); +- if (ret < 0) +- return ret; +- +- dev_geo(dev, "5: camera scaled to %ux%u\n", +- mf_tmp.width, mf_tmp.height); +- +- /* 6. Retrieve camera output window (g_fmt) */ +- +- /* unneeded - it is already in "mf_tmp" */ +- +- /* 7. Calculate new client scales. */ +- scale_h = soc_camera_calc_scale(rect->width, shift, mf_tmp.width); +- scale_v = soc_camera_calc_scale(rect->height, shift, mf_tmp.height); +- +- mf->width = mf_tmp.width; +- mf->height = mf_tmp.height; +- mf->colorspace = mf_tmp.colorspace; +- +- /* +- * 8. Calculate new CEU crop - apply camera scales to previously +- * updated "effective" crop. +- */ +- *width = soc_camera_shift_scale(subrect->width, shift, scale_h); +- *height = soc_camera_shift_scale(subrect->height, shift, scale_v); +- +- dev_geo(dev, "8: new client sub-window %ux%u\n", *width, *height); +- +- return 0; +-} ++#define calc_generic_scale(in, out) soc_camera_calc_scale(in, 12, out) + + /* + * CEU can scale and crop, but we don't want to waste bandwidth and kill the +@@ -1680,55 +1344,6 @@ static int sh_mobile_ceu_get_crop(struct soc_camera_device *icd, + return 0; + } + +-/* +- * Calculate real client output window by applying new scales to the current +- * client crop. New scales are calculated from the requested output format and +- * CEU crop, mapped backed onto the client input (subrect). +- */ +-static void soc_camera_calc_client_output(struct soc_camera_device *icd, +- struct v4l2_rect *rect, struct v4l2_rect *subrect, +- const struct v4l2_pix_format *pix, struct v4l2_mbus_framefmt *mf, +- unsigned int shift) +-{ +- struct device *dev = icd->parent; +- unsigned int scale_v, scale_h; +- +- if (subrect->width == rect->width && +- subrect->height == rect->height) { +- /* No sub-cropping */ +- mf->width = pix->width; +- mf->height = pix->height; +- return; +- } +- +- /* 1.-2. Current camera scales and subwin - cached. */ +- +- dev_geo(dev, "2: subwin %ux%u@%u:%u\n", +- subrect->width, subrect->height, +- subrect->left, subrect->top); +- +- /* +- * 3. Calculate new combined scales from input sub-window to requested +- * user window. +- */ +- +- /* +- * TODO: CEU cannot scale images larger than VGA to smaller than SubQCIF +- * (128x96) or larger than VGA +- */ +- scale_h = soc_camera_calc_scale(subrect->width, shift, pix->width); +- scale_v = soc_camera_calc_scale(subrect->height, shift, pix->height); +- +- dev_geo(dev, "3: scales %u:%u\n", scale_h, scale_v); +- +- /* +- * 4. Calculate desired client output window by applying combined scales +- * to client (real) input window. +- */ +- mf->width = soc_camera_shift_scale(rect->width, shift, scale_h); +- mf->height = soc_camera_shift_scale(rect->height, shift, scale_v); +-} +- + /* Similar to set_crop multistage iterative algorithm */ + static int sh_mobile_ceu_set_fmt(struct soc_camera_device *icd, + struct v4l2_format *f) +diff --git a/drivers/media/platform/soc_camera/soc_scale_crop.c b/drivers/media/platform/soc_camera/soc_scale_crop.c +new file mode 100644 +index 00000000..be7067f5 +--- /dev/null ++++ b/drivers/media/platform/soc_camera/soc_scale_crop.c +@@ -0,0 +1,401 @@ ++/* ++ * soc-camera generic scaling-cropping manipulation functions ++ * ++ * Copyright (C) 2013 Guennadi Liakhovetski <g.liakhovetski@gmx.de> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#include <linux/device.h> ++#include <linux/module.h> ++ ++#include <media/soc_camera.h> ++#include <media/v4l2-common.h> ++ ++#include "soc_scale_crop.h" ++ ++#ifdef DEBUG_GEOMETRY ++#define dev_geo dev_info ++#else ++#define dev_geo dev_dbg ++#endif ++ ++/* Check if any dimension of r1 is smaller than respective one of r2 */ ++static bool is_smaller(const struct v4l2_rect *r1, const struct v4l2_rect *r2) ++{ ++ return r1->width < r2->width || r1->height < r2->height; ++} ++ ++/* Check if r1 fails to cover r2 */ ++static bool is_inside(const struct v4l2_rect *r1, const struct v4l2_rect *r2) ++{ ++ return r1->left > r2->left || r1->top > r2->top || ++ r1->left + r1->width < r2->left + r2->width || ++ r1->top + r1->height < r2->top + r2->height; ++} ++ ++/* Get and store current client crop */ ++int soc_camera_client_g_rect(struct v4l2_subdev *sd, struct v4l2_rect *rect) ++{ ++ struct v4l2_crop crop; ++ struct v4l2_cropcap cap; ++ int ret; ++ ++ crop.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; ++ ++ ret = v4l2_subdev_call(sd, video, g_crop, &crop); ++ if (!ret) { ++ *rect = crop.c; ++ return ret; ++ } ++ ++ /* Camera driver doesn't support .g_crop(), assume default rectangle */ ++ cap.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; ++ ++ ret = v4l2_subdev_call(sd, video, cropcap, &cap); ++ if (!ret) ++ *rect = cap.defrect; ++ ++ return ret; ++} ++EXPORT_SYMBOL(soc_camera_client_g_rect); ++ ++/* Client crop has changed, update our sub-rectangle to remain within the area */ ++static void update_subrect(struct v4l2_rect *rect, struct v4l2_rect *subrect) ++{ ++ if (rect->width < subrect->width) ++ subrect->width = rect->width; ++ ++ if (rect->height < subrect->height) ++ subrect->height = rect->height; ++ ++ if (rect->left > subrect->left) ++ subrect->left = rect->left; ++ else if (rect->left + rect->width > ++ subrect->left + subrect->width) ++ subrect->left = rect->left + rect->width - ++ subrect->width; ++ ++ if (rect->top > subrect->top) ++ subrect->top = rect->top; ++ else if (rect->top + rect->height > ++ subrect->top + subrect->height) ++ subrect->top = rect->top + rect->height - ++ subrect->height; ++} ++ ++/* ++ * The common for both scaling and cropping iterative approach is: ++ * 1. try if the client can produce exactly what requested by the user ++ * 2. if (1) failed, try to double the client image until we get one big enough ++ * 3. if (2) failed, try to request the maximum image ++ */ ++int soc_camera_client_s_crop(struct v4l2_subdev *sd, ++ struct v4l2_crop *crop, struct v4l2_crop *cam_crop, ++ struct v4l2_rect *target_rect, struct v4l2_rect *subrect) ++{ ++ struct v4l2_rect *rect = &crop->c, *cam_rect = &cam_crop->c; ++ struct device *dev = sd->v4l2_dev->dev; ++ struct v4l2_cropcap cap; ++ int ret; ++ unsigned int width, height; ++ ++ v4l2_subdev_call(sd, video, s_crop, crop); ++ ret = soc_camera_client_g_rect(sd, cam_rect); ++ if (ret < 0) ++ return ret; ++ ++ /* ++ * Now cam_crop contains the current camera input rectangle, and it must ++ * be within camera cropcap bounds ++ */ ++ if (!memcmp(rect, cam_rect, sizeof(*rect))) { ++ /* Even if camera S_CROP failed, but camera rectangle matches */ ++ dev_dbg(dev, "Camera S_CROP successful for %dx%d@%d:%d\n", ++ rect->width, rect->height, rect->left, rect->top); ++ *target_rect = *cam_rect; ++ return 0; ++ } ++ ++ /* Try to fix cropping, that camera hasn't managed to set */ ++ dev_geo(dev, "Fix camera S_CROP for %dx%d@%d:%d to %dx%d@%d:%d\n", ++ cam_rect->width, cam_rect->height, ++ cam_rect->left, cam_rect->top, ++ rect->width, rect->height, rect->left, rect->top); ++ ++ /* We need sensor maximum rectangle */ ++ ret = v4l2_subdev_call(sd, video, cropcap, &cap); ++ if (ret < 0) ++ return ret; ++ ++ /* Put user requested rectangle within sensor bounds */ ++ soc_camera_limit_side(&rect->left, &rect->width, cap.bounds.left, 2, ++ cap.bounds.width); ++ soc_camera_limit_side(&rect->top, &rect->height, cap.bounds.top, 4, ++ cap.bounds.height); ++ ++ /* ++ * Popular special case - some cameras can only handle fixed sizes like ++ * QVGA, VGA,... Take care to avoid infinite loop. ++ */ ++ width = max(cam_rect->width, 2); ++ height = max(cam_rect->height, 2); ++ ++ /* ++ * Loop as long as sensor is not covering the requested rectangle and ++ * is still within its bounds ++ */ ++ while (!ret && (is_smaller(cam_rect, rect) || ++ is_inside(cam_rect, rect)) && ++ (cap.bounds.width > width || cap.bounds.height > height)) { ++ ++ width *= 2; ++ height *= 2; ++ ++ cam_rect->width = width; ++ cam_rect->height = height; ++ ++ /* ++ * We do not know what capabilities the camera has to set up ++ * left and top borders. We could try to be smarter in iterating ++ * them, e.g., if camera current left is to the right of the ++ * target left, set it to the middle point between the current ++ * left and minimum left. But that would add too much ++ * complexity: we would have to iterate each border separately. ++ * Instead we just drop to the left and top bounds. ++ */ ++ if (cam_rect->left > rect->left) ++ cam_rect->left = cap.bounds.left; ++ ++ if (cam_rect->left + cam_rect->width < rect->left + rect->width) ++ cam_rect->width = rect->left + rect->width - ++ cam_rect->left; ++ ++ if (cam_rect->top > rect->top) ++ cam_rect->top = cap.bounds.top; ++ ++ if (cam_rect->top + cam_rect->height < rect->top + rect->height) ++ cam_rect->height = rect->top + rect->height - ++ cam_rect->top; ++ ++ v4l2_subdev_call(sd, video, s_crop, cam_crop); ++ ret = soc_camera_client_g_rect(sd, cam_rect); ++ dev_geo(dev, "Camera S_CROP %d for %dx%d@%d:%d\n", ret, ++ cam_rect->width, cam_rect->height, ++ cam_rect->left, cam_rect->top); ++ } ++ ++ /* S_CROP must not modify the rectangle */ ++ if (is_smaller(cam_rect, rect) || is_inside(cam_rect, rect)) { ++ /* ++ * The camera failed to configure a suitable cropping, ++ * we cannot use the current rectangle, set to max ++ */ ++ *cam_rect = cap.bounds; ++ v4l2_subdev_call(sd, video, s_crop, cam_crop); ++ ret = soc_camera_client_g_rect(sd, cam_rect); ++ dev_geo(dev, "Camera S_CROP %d for max %dx%d@%d:%d\n", ret, ++ cam_rect->width, cam_rect->height, ++ cam_rect->left, cam_rect->top); ++ } ++ ++ if (!ret) { ++ *target_rect = *cam_rect; ++ update_subrect(target_rect, subrect); ++ } ++ ++ return ret; ++} ++EXPORT_SYMBOL(soc_camera_client_s_crop); ++ ++/* Iterative s_mbus_fmt, also updates cached client crop on success */ ++static int client_s_fmt(struct soc_camera_device *icd, ++ struct v4l2_rect *rect, struct v4l2_rect *subrect, ++ unsigned int max_width, unsigned int max_height, ++ struct v4l2_mbus_framefmt *mf, bool host_can_scale) ++{ ++ struct v4l2_subdev *sd = soc_camera_to_subdev(icd); ++ struct device *dev = icd->parent; ++ unsigned int width = mf->width, height = mf->height, tmp_w, tmp_h; ++ struct v4l2_cropcap cap; ++ bool ceu_1to1; ++ int ret; ++ ++ ret = v4l2_device_call_until_err(sd->v4l2_dev, ++ soc_camera_grp_id(icd), video, ++ s_mbus_fmt, mf); ++ if (ret < 0) ++ return ret; ++ ++ dev_geo(dev, "camera scaled to %ux%u\n", mf->width, mf->height); ++ ++ if (width == mf->width && height == mf->height) { ++ /* Perfect! The client has done it all. */ ++ ceu_1to1 = true; ++ goto update_cache; ++ } ++ ++ ceu_1to1 = false; ++ if (!host_can_scale) ++ goto update_cache; ++ ++ cap.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; ++ ++ ret = v4l2_subdev_call(sd, video, cropcap, &cap); ++ if (ret < 0) ++ return ret; ++ ++ if (max_width > cap.bounds.width) ++ max_width = cap.bounds.width; ++ if (max_height > cap.bounds.height) ++ max_height = cap.bounds.height; ++ ++ /* Camera set a format, but geometry is not precise, try to improve */ ++ tmp_w = mf->width; ++ tmp_h = mf->height; ++ ++ /* width <= max_width && height <= max_height - guaranteed by try_fmt */ ++ while ((width > tmp_w || height > tmp_h) && ++ tmp_w < max_width && tmp_h < max_height) { ++ tmp_w = min(2 * tmp_w, max_width); ++ tmp_h = min(2 * tmp_h, max_height); ++ mf->width = tmp_w; ++ mf->height = tmp_h; ++ ret = v4l2_device_call_until_err(sd->v4l2_dev, ++ soc_camera_grp_id(icd), video, ++ s_mbus_fmt, mf); ++ dev_geo(dev, "Camera scaled to %ux%u\n", ++ mf->width, mf->height); ++ if (ret < 0) { ++ /* This shouldn't happen */ ++ dev_err(dev, "Client failed to set format: %d\n", ret); ++ return ret; ++ } ++ } ++ ++update_cache: ++ /* Update cache */ ++ ret = soc_camera_client_g_rect(sd, rect); ++ if (ret < 0) ++ return ret; ++ ++ if (ceu_1to1) ++ *subrect = *rect; ++ else ++ update_subrect(rect, subrect); ++ ++ return 0; ++} ++ ++/** ++ * @icd - soc-camera device ++ * @rect - camera cropping window ++ * @subrect - part of rect, sent to the user ++ * @mf - in- / output camera output window ++ * @width - on input: max host input width ++ * on output: user width, mapped back to input ++ * @height - on input: max host input height ++ * on output: user height, mapped back to input ++ * @host_can_scale - host can scale this pixel format ++ * @shift - shift, used for scaling ++ */ ++int soc_camera_client_scale(struct soc_camera_device *icd, ++ struct v4l2_rect *rect, struct v4l2_rect *subrect, ++ struct v4l2_mbus_framefmt *mf, ++ unsigned int *width, unsigned int *height, ++ bool host_can_scale, unsigned int shift) ++{ ++ struct device *dev = icd->parent; ++ struct v4l2_mbus_framefmt mf_tmp = *mf; ++ unsigned int scale_h, scale_v; ++ int ret; ++ ++ /* ++ * 5. Apply iterative camera S_FMT for camera user window (also updates ++ * client crop cache and the imaginary sub-rectangle). ++ */ ++ ret = client_s_fmt(icd, rect, subrect, *width, *height, ++ &mf_tmp, host_can_scale); ++ if (ret < 0) ++ return ret; ++ ++ dev_geo(dev, "5: camera scaled to %ux%u\n", ++ mf_tmp.width, mf_tmp.height); ++ ++ /* 6. Retrieve camera output window (g_fmt) */ ++ ++ /* unneeded - it is already in "mf_tmp" */ ++ ++ /* 7. Calculate new client scales. */ ++ scale_h = soc_camera_calc_scale(rect->width, shift, mf_tmp.width); ++ scale_v = soc_camera_calc_scale(rect->height, shift, mf_tmp.height); ++ ++ mf->width = mf_tmp.width; ++ mf->height = mf_tmp.height; ++ mf->colorspace = mf_tmp.colorspace; ++ ++ /* ++ * 8. Calculate new CEU crop - apply camera scales to previously ++ * updated "effective" crop. ++ */ ++ *width = soc_camera_shift_scale(subrect->width, shift, scale_h); ++ *height = soc_camera_shift_scale(subrect->height, shift, scale_v); ++ ++ dev_geo(dev, "8: new client sub-window %ux%u\n", *width, *height); ++ ++ return 0; ++} ++EXPORT_SYMBOL(soc_camera_client_scale); ++ ++/* ++ * Calculate real client output window by applying new scales to the current ++ * client crop. New scales are calculated from the requested output format and ++ * CEU crop, mapped backed onto the client input (subrect). ++ */ ++void soc_camera_calc_client_output(struct soc_camera_device *icd, ++ struct v4l2_rect *rect, struct v4l2_rect *subrect, ++ const struct v4l2_pix_format *pix, struct v4l2_mbus_framefmt *mf, ++ unsigned int shift) ++{ ++ struct device *dev = icd->parent; ++ unsigned int scale_v, scale_h; ++ ++ if (subrect->width == rect->width && ++ subrect->height == rect->height) { ++ /* No sub-cropping */ ++ mf->width = pix->width; ++ mf->height = pix->height; ++ return; ++ } ++ ++ /* 1.-2. Current camera scales and subwin - cached. */ ++ ++ dev_geo(dev, "2: subwin %ux%u@%u:%u\n", ++ subrect->width, subrect->height, ++ subrect->left, subrect->top); ++ ++ /* ++ * 3. Calculate new combined scales from input sub-window to requested ++ * user window. ++ */ ++ ++ /* ++ * TODO: CEU cannot scale images larger than VGA to smaller than SubQCIF ++ * (128x96) or larger than VGA ++ */ ++ scale_h = soc_camera_calc_scale(subrect->width, shift, pix->width); ++ scale_v = soc_camera_calc_scale(subrect->height, shift, pix->height); ++ ++ dev_geo(dev, "3: scales %u:%u\n", scale_h, scale_v); ++ ++ /* ++ * 4. Calculate desired client output window by applying combined scales ++ * to client (real) input window. ++ */ ++ mf->width = soc_camera_shift_scale(rect->width, shift, scale_h); ++ mf->height = soc_camera_shift_scale(rect->height, shift, scale_v); ++} ++EXPORT_SYMBOL(soc_camera_calc_client_output); +diff --git a/drivers/media/platform/soc_camera/soc_scale_crop.h b/drivers/media/platform/soc_camera/soc_scale_crop.h +new file mode 100644 +index 00000000..184a30df +--- /dev/null ++++ b/drivers/media/platform/soc_camera/soc_scale_crop.h +@@ -0,0 +1,47 @@ ++/* ++ * soc-camera generic scaling-cropping manipulation functions ++ * ++ * Copyright (C) 2013 Guennadi Liakhovetski <g.liakhovetski@gmx.de> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#ifndef SOC_SCALE_CROP_H ++#define SOC_SCALE_CROP_H ++ ++#include <linux/kernel.h> ++ ++struct soc_camera_device; ++ ++struct v4l2_crop; ++struct v4l2_mbus_framefmt; ++struct v4l2_pix_format; ++struct v4l2_rect; ++struct v4l2_subdev; ++ ++static inline unsigned int soc_camera_shift_scale(unsigned int size, ++ unsigned int shift, unsigned int scale) ++{ ++ return DIV_ROUND_CLOSEST(size << shift, scale); ++} ++ ++#define soc_camera_calc_scale(in, shift, out) soc_camera_shift_scale(in, shift, out) ++ ++int soc_camera_client_g_rect(struct v4l2_subdev *sd, struct v4l2_rect *rect); ++int soc_camera_client_s_crop(struct v4l2_subdev *sd, ++ struct v4l2_crop *crop, struct v4l2_crop *cam_crop, ++ struct v4l2_rect *target_rect, struct v4l2_rect *subrect); ++int soc_camera_client_scale(struct soc_camera_device *icd, ++ struct v4l2_rect *rect, struct v4l2_rect *subrect, ++ struct v4l2_mbus_framefmt *mf, ++ unsigned int *width, unsigned int *height, ++ bool host_can_scale, unsigned int shift); ++void soc_camera_calc_client_output(struct soc_camera_device *icd, ++ struct v4l2_rect *rect, struct v4l2_rect *subrect, ++ const struct v4l2_pix_format *pix, struct v4l2_mbus_framefmt *mf, ++ unsigned int shift); ++ ++#endif +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0067-sh_mobile_ceu_camera-Fix-a-compilation-warning.patch b/patches.renesas/0067-sh_mobile_ceu_camera-Fix-a-compilation-warning.patch new file mode 100644 index 00000000000..476d04d5b32 --- /dev/null +++ b/patches.renesas/0067-sh_mobile_ceu_camera-Fix-a-compilation-warning.patch @@ -0,0 +1,38 @@ +From d38be29822e5f6de98b83303c540b6a9b2ac8021 Mon Sep 17 00:00:00 2001 +From: Mauro Carvalho Chehab <m.chehab@samsung.com> +Date: Sun, 18 Aug 2013 09:36:03 -0300 +Subject: sh_mobile_ceu_camera: Fix a compilation warning + +drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c: In function 'sh_mobile_ceu_clock_start': +drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c:613:6: warning: variable 'ret' set but not used [-Wunused-but-set-variable] + +Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com> +(cherry picked from commit e5b6a69790c7112b90570db0202c6de621485fb9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c b/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c +index 905ed7e5..dc5ce6c1 100644 +--- a/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c ++++ b/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c +@@ -595,13 +595,12 @@ static void sh_mobile_ceu_remove_device(struct soc_camera_device *icd) + static int sh_mobile_ceu_clock_start(struct soc_camera_host *ici) + { + struct sh_mobile_ceu_dev *pcdev = ici->priv; +- int ret; + + pm_runtime_get_sync(ici->v4l2_dev.dev); + + pcdev->buf_total = 0; + +- ret = sh_mobile_ceu_soft_reset(pcdev); ++ sh_mobile_ceu_soft_reset(pcdev); + + return 0; + } +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0068-media-V4L2-soc_camera-Renesas-R-Car-VIN-driver.patch b/patches.renesas/0068-media-V4L2-soc_camera-Renesas-R-Car-VIN-driver.patch new file mode 100644 index 00000000000..7755ad2ef7e --- /dev/null +++ b/patches.renesas/0068-media-V4L2-soc_camera-Renesas-R-Car-VIN-driver.patch @@ -0,0 +1,1587 @@ +From 3fec97c68d4708f5f33190a78712dad95c6f487d Mon Sep 17 00:00:00 2001 +From: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Date: Thu, 25 Jul 2013 17:23:10 -0300 +Subject: [media] V4L2: soc_camera: Renesas R-Car VIN driver + +Add Renesas R-Car VIN (Video In) V4L2 driver. +Based on the patch by Phil Edworthy <phil.edworthy@renesas.com>. +[Sergei: removed deprecated IRQF_DISABLED flag, reordered/renamed 'enum chip_id' +values, reordered rcar_vin_id_table[] entries, removed senseless parens from +to_buf_list() macro, used ALIGN() macro in rcar_vin_setup(), added {} to the +*if* statement and used 'bool' values instead of 0/1 where necessary, removed +unused macros, done some reformatting and clarified some comments.] + +Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com> +(cherry picked from commit 73135e969970304a474c18c9f732fa3e36d88514) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + drivers/media/platform/soc_camera/Makefile +--- + drivers/media/platform/soc_camera/Kconfig | 8 + + drivers/media/platform/soc_camera/Makefile | 3 +- + drivers/media/platform/soc_camera/rcar_vin.c | 1486 ++++++++++++++++++++++++++ + include/linux/platform_data/camera-rcar.h | 25 + + 4 files changed, 1520 insertions(+), 2 deletions(-) + create mode 100644 drivers/media/platform/soc_camera/rcar_vin.c + create mode 100644 include/linux/platform_data/camera-rcar.h + +diff --git a/drivers/media/platform/soc_camera/Kconfig b/drivers/media/platform/soc_camera/Kconfig +index 99f1952d..519b23fd 100644 +--- a/drivers/media/platform/soc_camera/Kconfig ++++ b/drivers/media/platform/soc_camera/Kconfig +@@ -48,6 +48,14 @@ config VIDEO_PXA27x + ---help--- + This is a v4l2 driver for the PXA27x Quick Capture Interface + ++config VIDEO_RCAR_VIN ++ tristate "R-Car Video Input (VIN) support" ++ depends on VIDEO_DEV && SOC_CAMERA ++ select VIDEOBUF2_DMA_CONTIG ++ select SOC_CAMERA_SCALE_CROP ++ ---help--- ++ This is a v4l2 driver for the R-Car VIN Interface ++ + config VIDEO_SH_MOBILE_CSI2 + tristate "SuperH Mobile MIPI CSI-2 Interface driver" + depends on VIDEO_DEV && SOC_CAMERA && HAVE_CLK +diff --git a/drivers/media/platform/soc_camera/Makefile b/drivers/media/platform/soc_camera/Makefile +index 7ff714c6..8aed26d7 100644 +--- a/drivers/media/platform/soc_camera/Makefile ++++ b/drivers/media/platform/soc_camera/Makefile +@@ -14,5 +14,4 @@ obj-$(CONFIG_VIDEO_OMAP1) += omap1_camera.o + obj-$(CONFIG_VIDEO_PXA27x) += pxa_camera.o + obj-$(CONFIG_VIDEO_SH_MOBILE_CEU) += sh_mobile_ceu_camera.o + obj-$(CONFIG_VIDEO_SH_MOBILE_CSI2) += sh_mobile_csi2.o +- +-ccflags-y += -I$(srctree)/drivers/media/i2c/soc_camera ++obj-$(CONFIG_VIDEO_RCAR_VIN) += rcar_vin.o +diff --git a/drivers/media/platform/soc_camera/rcar_vin.c b/drivers/media/platform/soc_camera/rcar_vin.c +new file mode 100644 +index 00000000..d02a7e0b +--- /dev/null ++++ b/drivers/media/platform/soc_camera/rcar_vin.c +@@ -0,0 +1,1486 @@ ++/* ++ * SoC-camera host driver for Renesas R-Car VIN unit ++ * ++ * Copyright (C) 2011-2013 Renesas Solutions Corp. ++ * Copyright (C) 2013 Cogent Embedded, Inc., <source@cogentembedded.com> ++ * ++ * Based on V4L2 Driver for SuperH Mobile CEU interface "sh_mobile_ceu_camera.c" ++ * ++ * Copyright (C) 2008 Magnus Damm ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include <linux/delay.h> ++#include <linux/interrupt.h> ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/platform_data/camera-rcar.h> ++#include <linux/platform_device.h> ++#include <linux/pm_runtime.h> ++#include <linux/slab.h> ++#include <linux/videodev2.h> ++ ++#include <media/soc_camera.h> ++#include <media/soc_mediabus.h> ++#include <media/v4l2-common.h> ++#include <media/v4l2-dev.h> ++#include <media/v4l2-device.h> ++#include <media/v4l2-mediabus.h> ++#include <media/v4l2-subdev.h> ++#include <media/videobuf2-dma-contig.h> ++ ++#include "soc_scale_crop.h" ++ ++#define DRV_NAME "rcar_vin" ++ ++/* Register offsets for R-Car VIN */ ++#define VNMC_REG 0x00 /* Video n Main Control Register */ ++#define VNMS_REG 0x04 /* Video n Module Status Register */ ++#define VNFC_REG 0x08 /* Video n Frame Capture Register */ ++#define VNSLPRC_REG 0x0C /* Video n Start Line Pre-Clip Register */ ++#define VNELPRC_REG 0x10 /* Video n End Line Pre-Clip Register */ ++#define VNSPPRC_REG 0x14 /* Video n Start Pixel Pre-Clip Register */ ++#define VNEPPRC_REG 0x18 /* Video n End Pixel Pre-Clip Register */ ++#define VNSLPOC_REG 0x1C /* Video n Start Line Post-Clip Register */ ++#define VNELPOC_REG 0x20 /* Video n End Line Post-Clip Register */ ++#define VNSPPOC_REG 0x24 /* Video n Start Pixel Post-Clip Register */ ++#define VNEPPOC_REG 0x28 /* Video n End Pixel Post-Clip Register */ ++#define VNIS_REG 0x2C /* Video n Image Stride Register */ ++#define VNMB_REG(m) (0x30 + ((m) << 2)) /* Video n Memory Base m Register */ ++#define VNIE_REG 0x40 /* Video n Interrupt Enable Register */ ++#define VNINTS_REG 0x44 /* Video n Interrupt Status Register */ ++#define VNSI_REG 0x48 /* Video n Scanline Interrupt Register */ ++#define VNMTC_REG 0x4C /* Video n Memory Transfer Control Register */ ++#define VNYS_REG 0x50 /* Video n Y Scale Register */ ++#define VNXS_REG 0x54 /* Video n X Scale Register */ ++#define VNDMR_REG 0x58 /* Video n Data Mode Register */ ++#define VNDMR2_REG 0x5C /* Video n Data Mode Register 2 */ ++#define VNUVAOF_REG 0x60 /* Video n UV Address Offset Register */ ++ ++/* Register bit fields for R-Car VIN */ ++/* Video n Main Control Register bits */ ++#define VNMC_FOC (1 << 21) ++#define VNMC_YCAL (1 << 19) ++#define VNMC_INF_YUV8_BT656 (0 << 16) ++#define VNMC_INF_YUV8_BT601 (1 << 16) ++#define VNMC_INF_YUV16 (5 << 16) ++#define VNMC_VUP (1 << 10) ++#define VNMC_IM_ODD (0 << 3) ++#define VNMC_IM_ODD_EVEN (1 << 3) ++#define VNMC_IM_EVEN (2 << 3) ++#define VNMC_IM_FULL (3 << 3) ++#define VNMC_BPS (1 << 1) ++#define VNMC_ME (1 << 0) ++ ++/* Video n Module Status Register bits */ ++#define VNMS_FBS_MASK (3 << 3) ++#define VNMS_FBS_SHIFT 3 ++#define VNMS_AV (1 << 1) ++#define VNMS_CA (1 << 0) ++ ++/* Video n Frame Capture Register bits */ ++#define VNFC_C_FRAME (1 << 1) ++#define VNFC_S_FRAME (1 << 0) ++ ++/* Video n Interrupt Enable Register bits */ ++#define VNIE_FIE (1 << 4) ++#define VNIE_EFE (1 << 1) ++ ++/* Video n Data Mode Register bits */ ++#define VNDMR_EXRGB (1 << 8) ++#define VNDMR_BPSM (1 << 4) ++#define VNDMR_DTMD_YCSEP (1 << 1) ++#define VNDMR_DTMD_ARGB1555 (1 << 0) ++ ++/* Video n Data Mode Register 2 bits */ ++#define VNDMR2_VPS (1 << 30) ++#define VNDMR2_HPS (1 << 29) ++#define VNDMR2_FTEV (1 << 17) ++ ++#define VIN_MAX_WIDTH 2048 ++#define VIN_MAX_HEIGHT 2048 ++ ++enum chip_id { ++ RCAR_H1, ++ RCAR_M1, ++ RCAR_E1, ++}; ++ ++enum rcar_vin_state { ++ STOPPED = 0, ++ RUNNING, ++ STOPPING, ++}; ++ ++struct rcar_vin_priv { ++ void __iomem *base; ++ spinlock_t lock; ++ int sequence; ++ /* State of the VIN module in capturing mode */ ++ enum rcar_vin_state state; ++ struct rcar_vin_platform_data *pdata; ++ struct soc_camera_host ici; ++ struct list_head capture; ++#define MAX_BUFFER_NUM 3 ++ struct vb2_buffer *queue_buf[MAX_BUFFER_NUM]; ++ struct vb2_alloc_ctx *alloc_ctx; ++ enum v4l2_field field; ++ unsigned int vb_count; ++ unsigned int nr_hw_slots; ++ bool request_to_stop; ++ struct completion capture_stop; ++ enum chip_id chip; ++}; ++ ++#define is_continuous_transfer(priv) (priv->vb_count > MAX_BUFFER_NUM) ++ ++struct rcar_vin_buffer { ++ struct vb2_buffer vb; ++ struct list_head list; ++}; ++ ++#define to_buf_list(vb2_buffer) (&container_of(vb2_buffer, \ ++ struct rcar_vin_buffer, \ ++ vb)->list) ++ ++struct rcar_vin_cam { ++ /* VIN offsets within the camera output, before the VIN scaler */ ++ unsigned int vin_left; ++ unsigned int vin_top; ++ /* Client output, as seen by the VIN */ ++ unsigned int width; ++ unsigned int height; ++ /* ++ * User window from S_CROP / G_CROP, produced by client cropping and ++ * scaling, VIN scaling and VIN cropping, mapped back onto the client ++ * input window ++ */ ++ struct v4l2_rect subrect; ++ /* Camera cropping rectangle */ ++ struct v4l2_rect rect; ++ const struct soc_mbus_pixelfmt *extra_fmt; ++}; ++ ++/* ++ * .queue_setup() is called to check whether the driver can accept the requested ++ * number of buffers and to fill in plane sizes for the current frame format if ++ * required ++ */ ++static int rcar_vin_videobuf_setup(struct vb2_queue *vq, ++ const struct v4l2_format *fmt, ++ unsigned int *count, ++ unsigned int *num_planes, ++ unsigned int sizes[], void *alloc_ctxs[]) ++{ ++ struct soc_camera_device *icd = soc_camera_from_vb2q(vq); ++ struct soc_camera_host *ici = to_soc_camera_host(icd->parent); ++ struct rcar_vin_priv *priv = ici->priv; ++ ++ if (fmt) { ++ const struct soc_camera_format_xlate *xlate; ++ unsigned int bytes_per_line; ++ int ret; ++ ++ xlate = soc_camera_xlate_by_fourcc(icd, ++ fmt->fmt.pix.pixelformat); ++ if (!xlate) ++ return -EINVAL; ++ ret = soc_mbus_bytes_per_line(fmt->fmt.pix.width, ++ xlate->host_fmt); ++ if (ret < 0) ++ return ret; ++ ++ bytes_per_line = max_t(u32, fmt->fmt.pix.bytesperline, ret); ++ ++ ret = soc_mbus_image_size(xlate->host_fmt, bytes_per_line, ++ fmt->fmt.pix.height); ++ if (ret < 0) ++ return ret; ++ ++ sizes[0] = max_t(u32, fmt->fmt.pix.sizeimage, ret); ++ } else { ++ /* Called from VIDIOC_REQBUFS or in compatibility mode */ ++ sizes[0] = icd->sizeimage; ++ } ++ ++ alloc_ctxs[0] = priv->alloc_ctx; ++ ++ if (!vq->num_buffers) ++ priv->sequence = 0; ++ ++ if (!*count) ++ *count = 2; ++ priv->vb_count = *count; ++ ++ *num_planes = 1; ++ ++ /* Number of hardware slots */ ++ if (is_continuous_transfer(priv)) ++ priv->nr_hw_slots = MAX_BUFFER_NUM; ++ else ++ priv->nr_hw_slots = 1; ++ ++ dev_dbg(icd->parent, "count=%d, size=%u\n", *count, sizes[0]); ++ ++ return 0; ++} ++ ++static int rcar_vin_setup(struct rcar_vin_priv *priv) ++{ ++ struct soc_camera_device *icd = priv->ici.icd; ++ struct rcar_vin_cam *cam = icd->host_priv; ++ u32 vnmc, dmr, interrupts; ++ bool progressive = false, output_is_yuv = false; ++ ++ switch (priv->field) { ++ case V4L2_FIELD_TOP: ++ vnmc = VNMC_IM_ODD; ++ break; ++ case V4L2_FIELD_BOTTOM: ++ vnmc = VNMC_IM_EVEN; ++ break; ++ case V4L2_FIELD_INTERLACED: ++ case V4L2_FIELD_INTERLACED_TB: ++ vnmc = VNMC_IM_FULL; ++ break; ++ case V4L2_FIELD_INTERLACED_BT: ++ vnmc = VNMC_IM_FULL | VNMC_FOC; ++ break; ++ case V4L2_FIELD_NONE: ++ if (is_continuous_transfer(priv)) { ++ vnmc = VNMC_IM_ODD_EVEN; ++ progressive = true; ++ } else { ++ vnmc = VNMC_IM_ODD; ++ } ++ break; ++ default: ++ vnmc = VNMC_IM_ODD; ++ break; ++ } ++ ++ /* input interface */ ++ switch (icd->current_fmt->code) { ++ case V4L2_MBUS_FMT_YUYV8_1X16: ++ /* BT.601/BT.1358 16bit YCbCr422 */ ++ vnmc |= VNMC_INF_YUV16; ++ break; ++ case V4L2_MBUS_FMT_YUYV8_2X8: ++ /* BT.656 8bit YCbCr422 or BT.601 8bit YCbCr422 */ ++ vnmc |= priv->pdata->flags & RCAR_VIN_BT656 ? ++ VNMC_INF_YUV8_BT656 : VNMC_INF_YUV8_BT601; ++ default: ++ break; ++ } ++ ++ /* output format */ ++ switch (icd->current_fmt->host_fmt->fourcc) { ++ case V4L2_PIX_FMT_NV16: ++ iowrite32(ALIGN(cam->width * cam->height, 0x80), ++ priv->base + VNUVAOF_REG); ++ dmr = VNDMR_DTMD_YCSEP; ++ output_is_yuv = true; ++ break; ++ case V4L2_PIX_FMT_YUYV: ++ dmr = VNDMR_BPSM; ++ output_is_yuv = true; ++ break; ++ case V4L2_PIX_FMT_UYVY: ++ dmr = 0; ++ output_is_yuv = true; ++ break; ++ case V4L2_PIX_FMT_RGB555X: ++ dmr = VNDMR_DTMD_ARGB1555; ++ break; ++ case V4L2_PIX_FMT_RGB565: ++ dmr = 0; ++ break; ++ case V4L2_PIX_FMT_RGB32: ++ if (priv->chip == RCAR_H1 || priv->chip == RCAR_E1) { ++ dmr = VNDMR_EXRGB; ++ break; ++ } ++ default: ++ dev_warn(icd->parent, "Invalid fourcc format (0x%x)\n", ++ icd->current_fmt->host_fmt->fourcc); ++ return -EINVAL; ++ } ++ ++ /* Always update on field change */ ++ vnmc |= VNMC_VUP; ++ ++ /* If input and output use the same colorspace, use bypass mode */ ++ if (output_is_yuv) ++ vnmc |= VNMC_BPS; ++ ++ /* progressive or interlaced mode */ ++ interrupts = progressive ? VNIE_FIE | VNIE_EFE : VNIE_EFE; ++ ++ /* ack interrupts */ ++ iowrite32(interrupts, priv->base + VNINTS_REG); ++ /* enable interrupts */ ++ iowrite32(interrupts, priv->base + VNIE_REG); ++ /* start capturing */ ++ iowrite32(dmr, priv->base + VNDMR_REG); ++ iowrite32(vnmc | VNMC_ME, priv->base + VNMC_REG); ++ ++ return 0; ++} ++ ++static void rcar_vin_capture(struct rcar_vin_priv *priv) ++{ ++ if (is_continuous_transfer(priv)) ++ /* Continuous Frame Capture Mode */ ++ iowrite32(VNFC_C_FRAME, priv->base + VNFC_REG); ++ else ++ /* Single Frame Capture Mode */ ++ iowrite32(VNFC_S_FRAME, priv->base + VNFC_REG); ++} ++ ++static void rcar_vin_request_capture_stop(struct rcar_vin_priv *priv) ++{ ++ priv->state = STOPPING; ++ ++ /* set continuous & single transfer off */ ++ iowrite32(0, priv->base + VNFC_REG); ++ /* disable capture (release DMA buffer), reset */ ++ iowrite32(ioread32(priv->base + VNMC_REG) & ~VNMC_ME, ++ priv->base + VNMC_REG); ++ ++ /* update the status if stopped already */ ++ if (!(ioread32(priv->base + VNMS_REG) & VNMS_CA)) ++ priv->state = STOPPED; ++} ++ ++static int rcar_vin_get_free_hw_slot(struct rcar_vin_priv *priv) ++{ ++ int slot; ++ ++ for (slot = 0; slot < priv->nr_hw_slots; slot++) ++ if (priv->queue_buf[slot] == NULL) ++ return slot; ++ ++ return -1; ++} ++ ++static int rcar_vin_hw_ready(struct rcar_vin_priv *priv) ++{ ++ /* Ensure all HW slots are filled */ ++ return rcar_vin_get_free_hw_slot(priv) < 0 ? 1 : 0; ++} ++ ++/* Moves a buffer from the queue to the HW slots */ ++static int rcar_vin_fill_hw_slot(struct rcar_vin_priv *priv) ++{ ++ struct vb2_buffer *vb; ++ dma_addr_t phys_addr_top; ++ int slot; ++ ++ if (list_empty(&priv->capture)) ++ return 0; ++ ++ /* Find a free HW slot */ ++ slot = rcar_vin_get_free_hw_slot(priv); ++ if (slot < 0) ++ return 0; ++ ++ vb = &list_entry(priv->capture.next, struct rcar_vin_buffer, list)->vb; ++ list_del_init(to_buf_list(vb)); ++ priv->queue_buf[slot] = vb; ++ phys_addr_top = vb2_dma_contig_plane_dma_addr(vb, 0); ++ iowrite32(phys_addr_top, priv->base + VNMB_REG(slot)); ++ ++ return 1; ++} ++ ++static void rcar_vin_videobuf_queue(struct vb2_buffer *vb) ++{ ++ struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue); ++ struct soc_camera_host *ici = to_soc_camera_host(icd->parent); ++ struct rcar_vin_priv *priv = ici->priv; ++ unsigned long size; ++ ++ size = icd->sizeimage; ++ ++ if (vb2_plane_size(vb, 0) < size) { ++ dev_err(icd->parent, "Buffer #%d too small (%lu < %lu)\n", ++ vb->v4l2_buf.index, vb2_plane_size(vb, 0), size); ++ goto error; ++ } ++ ++ vb2_set_plane_payload(vb, 0, size); ++ ++ dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__, ++ vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0)); ++ ++ spin_lock_irq(&priv->lock); ++ ++ list_add_tail(to_buf_list(vb), &priv->capture); ++ rcar_vin_fill_hw_slot(priv); ++ ++ /* If we weren't running, and have enough buffers, start capturing! */ ++ if (priv->state != RUNNING && rcar_vin_hw_ready(priv)) { ++ if (rcar_vin_setup(priv)) { ++ /* Submit error */ ++ list_del_init(to_buf_list(vb)); ++ spin_unlock_irq(&priv->lock); ++ goto error; ++ } ++ priv->request_to_stop = false; ++ init_completion(&priv->capture_stop); ++ priv->state = RUNNING; ++ rcar_vin_capture(priv); ++ } ++ ++ spin_unlock_irq(&priv->lock); ++ ++ return; ++ ++error: ++ vb2_buffer_done(vb, VB2_BUF_STATE_ERROR); ++} ++ ++static void rcar_vin_videobuf_release(struct vb2_buffer *vb) ++{ ++ struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue); ++ struct soc_camera_host *ici = to_soc_camera_host(icd->parent); ++ struct rcar_vin_priv *priv = ici->priv; ++ unsigned int i; ++ int buf_in_use = 0; ++ ++ spin_lock_irq(&priv->lock); ++ ++ /* Is the buffer in use by the VIN hardware? */ ++ for (i = 0; i < MAX_BUFFER_NUM; i++) { ++ if (priv->queue_buf[i] == vb) { ++ buf_in_use = 1; ++ break; ++ } ++ } ++ ++ if (buf_in_use) { ++ while (priv->state != STOPPED) { ++ ++ /* issue stop if running */ ++ if (priv->state == RUNNING) ++ rcar_vin_request_capture_stop(priv); ++ ++ /* wait until capturing has been stopped */ ++ if (priv->state == STOPPING) { ++ priv->request_to_stop = true; ++ spin_unlock_irq(&priv->lock); ++ wait_for_completion(&priv->capture_stop); ++ spin_lock_irq(&priv->lock); ++ } ++ } ++ /* ++ * Capturing has now stopped. The buffer we have been asked ++ * to release could be any of the current buffers in use, so ++ * release all buffers that are in use by HW ++ */ ++ for (i = 0; i < MAX_BUFFER_NUM; i++) { ++ if (priv->queue_buf[i]) { ++ vb2_buffer_done(priv->queue_buf[i], ++ VB2_BUF_STATE_ERROR); ++ priv->queue_buf[i] = NULL; ++ } ++ } ++ } else { ++ list_del_init(to_buf_list(vb)); ++ } ++ ++ spin_unlock_irq(&priv->lock); ++} ++ ++static int rcar_vin_videobuf_init(struct vb2_buffer *vb) ++{ ++ INIT_LIST_HEAD(to_buf_list(vb)); ++ return 0; ++} ++ ++static int rcar_vin_stop_streaming(struct vb2_queue *vq) ++{ ++ struct soc_camera_device *icd = soc_camera_from_vb2q(vq); ++ struct soc_camera_host *ici = to_soc_camera_host(icd->parent); ++ struct rcar_vin_priv *priv = ici->priv; ++ struct list_head *buf_head, *tmp; ++ ++ spin_lock_irq(&priv->lock); ++ list_for_each_safe(buf_head, tmp, &priv->capture) ++ list_del_init(buf_head); ++ spin_unlock_irq(&priv->lock); ++ ++ return 0; ++} ++ ++static struct vb2_ops rcar_vin_vb2_ops = { ++ .queue_setup = rcar_vin_videobuf_setup, ++ .buf_init = rcar_vin_videobuf_init, ++ .buf_cleanup = rcar_vin_videobuf_release, ++ .buf_queue = rcar_vin_videobuf_queue, ++ .stop_streaming = rcar_vin_stop_streaming, ++ .wait_prepare = soc_camera_unlock, ++ .wait_finish = soc_camera_lock, ++}; ++ ++static irqreturn_t rcar_vin_irq(int irq, void *data) ++{ ++ struct rcar_vin_priv *priv = data; ++ u32 int_status; ++ bool can_run = false, hw_stopped; ++ int slot; ++ unsigned int handled = 0; ++ ++ spin_lock(&priv->lock); ++ ++ int_status = ioread32(priv->base + VNINTS_REG); ++ if (!int_status) ++ goto done; ++ /* ack interrupts */ ++ iowrite32(int_status, priv->base + VNINTS_REG); ++ handled = 1; ++ ++ /* nothing to do if capture status is 'STOPPED' */ ++ if (priv->state == STOPPED) ++ goto done; ++ ++ hw_stopped = !(ioread32(priv->base + VNMS_REG) & VNMS_CA); ++ ++ if (!priv->request_to_stop) { ++ if (is_continuous_transfer(priv)) ++ slot = (ioread32(priv->base + VNMS_REG) & ++ VNMS_FBS_MASK) >> VNMS_FBS_SHIFT; ++ else ++ slot = 0; ++ ++ priv->queue_buf[slot]->v4l2_buf.field = priv->field; ++ priv->queue_buf[slot]->v4l2_buf.sequence = priv->sequence++; ++ do_gettimeofday(&priv->queue_buf[slot]->v4l2_buf.timestamp); ++ vb2_buffer_done(priv->queue_buf[slot], VB2_BUF_STATE_DONE); ++ priv->queue_buf[slot] = NULL; ++ ++ if (priv->state != STOPPING) ++ can_run = rcar_vin_fill_hw_slot(priv); ++ ++ if (hw_stopped || !can_run) { ++ priv->state = STOPPED; ++ } else if (is_continuous_transfer(priv) && ++ list_empty(&priv->capture) && ++ priv->state == RUNNING) { ++ /* ++ * The continuous capturing requires an explicit stop ++ * operation when there is no buffer to be set into ++ * the VnMBm registers. ++ */ ++ rcar_vin_request_capture_stop(priv); ++ } else { ++ rcar_vin_capture(priv); ++ } ++ ++ } else if (hw_stopped) { ++ priv->state = STOPPED; ++ priv->request_to_stop = false; ++ complete(&priv->capture_stop); ++ } ++ ++done: ++ spin_unlock(&priv->lock); ++ ++ return IRQ_RETVAL(handled); ++} ++ ++static int rcar_vin_add_device(struct soc_camera_device *icd) ++{ ++ struct soc_camera_host *ici = to_soc_camera_host(icd->parent); ++ struct rcar_vin_priv *priv = ici->priv; ++ int i; ++ ++ for (i = 0; i < MAX_BUFFER_NUM; i++) ++ priv->queue_buf[i] = NULL; ++ ++ pm_runtime_get_sync(ici->v4l2_dev.dev); ++ ++ dev_dbg(icd->parent, "R-Car VIN driver attached to camera %d\n", ++ icd->devnum); ++ ++ return 0; ++} ++ ++static void rcar_vin_remove_device(struct soc_camera_device *icd) ++{ ++ struct soc_camera_host *ici = to_soc_camera_host(icd->parent); ++ struct rcar_vin_priv *priv = ici->priv; ++ struct vb2_buffer *vb; ++ int i; ++ ++ /* disable capture, disable interrupts */ ++ iowrite32(ioread32(priv->base + VNMC_REG) & ~VNMC_ME, ++ priv->base + VNMC_REG); ++ iowrite32(0, priv->base + VNIE_REG); ++ ++ priv->state = STOPPED; ++ priv->request_to_stop = false; ++ ++ /* make sure active buffer is cancelled */ ++ spin_lock_irq(&priv->lock); ++ for (i = 0; i < MAX_BUFFER_NUM; i++) { ++ vb = priv->queue_buf[i]; ++ if (vb) { ++ list_del_init(to_buf_list(vb)); ++ vb2_buffer_done(vb, VB2_BUF_STATE_ERROR); ++ } ++ } ++ spin_unlock_irq(&priv->lock); ++ ++ pm_runtime_put(ici->v4l2_dev.dev); ++ ++ dev_dbg(icd->parent, "R-Car VIN driver detached from camera %d\n", ++ icd->devnum); ++} ++ ++/* Called with .host_lock held */ ++static int rcar_vin_clock_start(struct soc_camera_host *ici) ++{ ++ /* VIN does not have "mclk" */ ++ return 0; ++} ++ ++/* Called with .host_lock held */ ++static void rcar_vin_clock_stop(struct soc_camera_host *ici) ++{ ++ /* VIN does not have "mclk" */ ++} ++ ++/* rect is guaranteed to not exceed the scaled camera rectangle */ ++static int rcar_vin_set_rect(struct soc_camera_device *icd) ++{ ++ struct soc_camera_host *ici = to_soc_camera_host(icd->parent); ++ struct rcar_vin_cam *cam = icd->host_priv; ++ struct rcar_vin_priv *priv = ici->priv; ++ unsigned int left_offset, top_offset; ++ unsigned char dsize = 0; ++ struct v4l2_rect *cam_subrect = &cam->subrect; ++ ++ dev_dbg(icd->parent, "Crop %ux%u@%u:%u\n", ++ icd->user_width, icd->user_height, cam->vin_left, cam->vin_top); ++ ++ left_offset = cam->vin_left; ++ top_offset = cam->vin_top; ++ ++ if (icd->current_fmt->host_fmt->fourcc == V4L2_PIX_FMT_RGB32 && ++ priv->chip == RCAR_E1) ++ dsize = 1; ++ ++ dev_dbg(icd->parent, "Cam %ux%u@%u:%u\n", ++ cam->width, cam->height, cam->vin_left, cam->vin_top); ++ dev_dbg(icd->parent, "Cam subrect %ux%u@%u:%u\n", ++ cam_subrect->width, cam_subrect->height, ++ cam_subrect->left, cam_subrect->top); ++ ++ /* Set Start/End Pixel/Line Pre-Clip */ ++ iowrite32(left_offset << dsize, priv->base + VNSPPRC_REG); ++ iowrite32((left_offset + cam->width - 1) << dsize, ++ priv->base + VNEPPRC_REG); ++ switch (priv->field) { ++ case V4L2_FIELD_INTERLACED: ++ case V4L2_FIELD_INTERLACED_TB: ++ case V4L2_FIELD_INTERLACED_BT: ++ iowrite32(top_offset / 2, priv->base + VNSLPRC_REG); ++ iowrite32((top_offset + cam->height) / 2 - 1, ++ priv->base + VNELPRC_REG); ++ break; ++ default: ++ iowrite32(top_offset, priv->base + VNSLPRC_REG); ++ iowrite32(top_offset + cam->height - 1, ++ priv->base + VNELPRC_REG); ++ break; ++ } ++ ++ /* Set Start/End Pixel/Line Post-Clip */ ++ iowrite32(0, priv->base + VNSPPOC_REG); ++ iowrite32(0, priv->base + VNSLPOC_REG); ++ iowrite32((cam_subrect->width - 1) << dsize, priv->base + VNEPPOC_REG); ++ switch (priv->field) { ++ case V4L2_FIELD_INTERLACED: ++ case V4L2_FIELD_INTERLACED_TB: ++ case V4L2_FIELD_INTERLACED_BT: ++ iowrite32(cam_subrect->height / 2 - 1, ++ priv->base + VNELPOC_REG); ++ break; ++ default: ++ iowrite32(cam_subrect->height - 1, priv->base + VNELPOC_REG); ++ break; ++ } ++ ++ iowrite32(ALIGN(cam->width, 0x10), priv->base + VNIS_REG); ++ ++ return 0; ++} ++ ++static void capture_stop_preserve(struct rcar_vin_priv *priv, u32 *vnmc) ++{ ++ *vnmc = ioread32(priv->base + VNMC_REG); ++ /* module disable */ ++ iowrite32(*vnmc & ~VNMC_ME, priv->base + VNMC_REG); ++} ++ ++static void capture_restore(struct rcar_vin_priv *priv, u32 vnmc) ++{ ++ unsigned long timeout = jiffies + 10 * HZ; ++ ++ /* ++ * Wait until the end of the current frame. It can take a long time, ++ * but if it has been aborted by a MRST1 reset, it should exit sooner. ++ */ ++ while ((ioread32(priv->base + VNMS_REG) & VNMS_AV) && ++ time_before(jiffies, timeout)) ++ msleep(1); ++ ++ if (time_after(jiffies, timeout)) { ++ dev_err(priv->ici.v4l2_dev.dev, ++ "Timeout waiting for frame end! Interface problem?\n"); ++ return; ++ } ++ ++ iowrite32(vnmc, priv->base + VNMC_REG); ++} ++ ++#define VIN_MBUS_FLAGS (V4L2_MBUS_MASTER | \ ++ V4L2_MBUS_PCLK_SAMPLE_RISING | \ ++ V4L2_MBUS_HSYNC_ACTIVE_HIGH | \ ++ V4L2_MBUS_HSYNC_ACTIVE_LOW | \ ++ V4L2_MBUS_VSYNC_ACTIVE_HIGH | \ ++ V4L2_MBUS_VSYNC_ACTIVE_LOW | \ ++ V4L2_MBUS_DATA_ACTIVE_HIGH) ++ ++static int rcar_vin_set_bus_param(struct soc_camera_device *icd) ++{ ++ struct soc_camera_host *ici = to_soc_camera_host(icd->parent); ++ struct rcar_vin_priv *priv = ici->priv; ++ struct v4l2_subdev *sd = soc_camera_to_subdev(icd); ++ struct v4l2_mbus_config cfg; ++ unsigned long common_flags; ++ u32 vnmc; ++ u32 val; ++ int ret; ++ ++ capture_stop_preserve(priv, &vnmc); ++ ++ ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg); ++ if (!ret) { ++ common_flags = soc_mbus_config_compatible(&cfg, VIN_MBUS_FLAGS); ++ if (!common_flags) { ++ dev_warn(icd->parent, ++ "MBUS flags incompatible: camera 0x%x, host 0x%x\n", ++ cfg.flags, VIN_MBUS_FLAGS); ++ return -EINVAL; ++ } ++ } else if (ret != -ENOIOCTLCMD) { ++ return ret; ++ } else { ++ common_flags = VIN_MBUS_FLAGS; ++ } ++ ++ /* Make choises, based on platform preferences */ ++ if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) && ++ (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) { ++ if (priv->pdata->flags & RCAR_VIN_HSYNC_ACTIVE_LOW) ++ common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH; ++ else ++ common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW; ++ } ++ ++ if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) && ++ (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) { ++ if (priv->pdata->flags & RCAR_VIN_VSYNC_ACTIVE_LOW) ++ common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH; ++ else ++ common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW; ++ } ++ ++ cfg.flags = common_flags; ++ ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg); ++ if (ret < 0 && ret != -ENOIOCTLCMD) ++ return ret; ++ ++ val = priv->field == V4L2_FIELD_NONE ? VNDMR2_FTEV : 0; ++ if (!(common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) ++ val |= VNDMR2_VPS; ++ if (!(common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) ++ val |= VNDMR2_HPS; ++ iowrite32(val, priv->base + VNDMR2_REG); ++ ++ ret = rcar_vin_set_rect(icd); ++ if (ret < 0) ++ return ret; ++ ++ capture_restore(priv, vnmc); ++ ++ return 0; ++} ++ ++static int rcar_vin_try_bus_param(struct soc_camera_device *icd, ++ unsigned char buswidth) ++{ ++ struct v4l2_subdev *sd = soc_camera_to_subdev(icd); ++ struct v4l2_mbus_config cfg; ++ int ret; ++ ++ ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg); ++ if (ret == -ENOIOCTLCMD) ++ return 0; ++ else if (ret) ++ return ret; ++ ++ if (buswidth > 24) ++ return -EINVAL; ++ ++ /* check is there common mbus flags */ ++ ret = soc_mbus_config_compatible(&cfg, VIN_MBUS_FLAGS); ++ if (ret) ++ return 0; ++ ++ dev_warn(icd->parent, ++ "MBUS flags incompatible: camera 0x%x, host 0x%x\n", ++ cfg.flags, VIN_MBUS_FLAGS); ++ ++ return -EINVAL; ++} ++ ++static bool rcar_vin_packing_supported(const struct soc_mbus_pixelfmt *fmt) ++{ ++ return fmt->packing == SOC_MBUS_PACKING_NONE || ++ (fmt->bits_per_sample > 8 && ++ fmt->packing == SOC_MBUS_PACKING_EXTEND16); ++} ++ ++static const struct soc_mbus_pixelfmt rcar_vin_formats[] = { ++ { ++ .fourcc = V4L2_PIX_FMT_NV16, ++ .name = "NV16", ++ .bits_per_sample = 8, ++ .packing = SOC_MBUS_PACKING_2X8_PADHI, ++ .order = SOC_MBUS_ORDER_LE, ++ .layout = SOC_MBUS_LAYOUT_PLANAR_Y_C, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_UYVY, ++ .name = "UYVY", ++ .bits_per_sample = 16, ++ .packing = SOC_MBUS_PACKING_NONE, ++ .order = SOC_MBUS_ORDER_LE, ++ .layout = SOC_MBUS_LAYOUT_PACKED, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_RGB565, ++ .name = "RGB565", ++ .bits_per_sample = 16, ++ .packing = SOC_MBUS_PACKING_NONE, ++ .order = SOC_MBUS_ORDER_LE, ++ .layout = SOC_MBUS_LAYOUT_PACKED, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_RGB555X, ++ .name = "ARGB1555", ++ .bits_per_sample = 16, ++ .packing = SOC_MBUS_PACKING_NONE, ++ .order = SOC_MBUS_ORDER_LE, ++ .layout = SOC_MBUS_LAYOUT_PACKED, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_RGB32, ++ .name = "RGB888", ++ .bits_per_sample = 32, ++ .packing = SOC_MBUS_PACKING_NONE, ++ .order = SOC_MBUS_ORDER_LE, ++ .layout = SOC_MBUS_LAYOUT_PACKED, ++ }, ++}; ++ ++static int rcar_vin_get_formats(struct soc_camera_device *icd, unsigned int idx, ++ struct soc_camera_format_xlate *xlate) ++{ ++ struct v4l2_subdev *sd = soc_camera_to_subdev(icd); ++ struct device *dev = icd->parent; ++ int ret, k, n; ++ int formats = 0; ++ struct rcar_vin_cam *cam; ++ enum v4l2_mbus_pixelcode code; ++ const struct soc_mbus_pixelfmt *fmt; ++ ++ ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code); ++ if (ret < 0) ++ return 0; ++ ++ fmt = soc_mbus_get_fmtdesc(code); ++ if (!fmt) { ++ dev_warn(dev, "unsupported format code #%u: %d\n", idx, code); ++ return 0; ++ } ++ ++ ret = rcar_vin_try_bus_param(icd, fmt->bits_per_sample); ++ if (ret < 0) ++ return 0; ++ ++ if (!icd->host_priv) { ++ struct v4l2_mbus_framefmt mf; ++ struct v4l2_rect rect; ++ struct device *dev = icd->parent; ++ int shift; ++ ++ ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf); ++ if (ret < 0) ++ return ret; ++ ++ /* Cache current client geometry */ ++ ret = soc_camera_client_g_rect(sd, &rect); ++ if (ret == -ENOIOCTLCMD) { ++ /* Sensor driver doesn't support cropping */ ++ rect.left = 0; ++ rect.top = 0; ++ rect.width = mf.width; ++ rect.height = mf.height; ++ } else if (ret < 0) { ++ return ret; ++ } ++ ++ /* ++ * If sensor proposes too large format then try smaller ones: ++ * 1280x960, 640x480, 320x240 ++ */ ++ for (shift = 0; shift < 3; shift++) { ++ if (mf.width <= VIN_MAX_WIDTH && ++ mf.height <= VIN_MAX_HEIGHT) ++ break; ++ ++ mf.width = 1280 >> shift; ++ mf.height = 960 >> shift; ++ ret = v4l2_device_call_until_err(sd->v4l2_dev, ++ soc_camera_grp_id(icd), ++ video, s_mbus_fmt, ++ &mf); ++ if (ret < 0) ++ return ret; ++ } ++ ++ if (shift == 3) { ++ dev_err(dev, ++ "Failed to configure the client below %ux%x\n", ++ mf.width, mf.height); ++ return -EIO; ++ } ++ ++ dev_dbg(dev, "camera fmt %ux%u\n", mf.width, mf.height); ++ ++ cam = kzalloc(sizeof(*cam), GFP_KERNEL); ++ if (!cam) ++ return -ENOMEM; ++ /* ++ * We are called with current camera crop, ++ * initialise subrect with it ++ */ ++ cam->rect = rect; ++ cam->subrect = rect; ++ cam->width = mf.width; ++ cam->height = mf.height; ++ ++ icd->host_priv = cam; ++ } else { ++ cam = icd->host_priv; ++ } ++ ++ /* Beginning of a pass */ ++ if (!idx) ++ cam->extra_fmt = NULL; ++ ++ switch (code) { ++ case V4L2_MBUS_FMT_YUYV8_1X16: ++ case V4L2_MBUS_FMT_YUYV8_2X8: ++ if (cam->extra_fmt) ++ break; ++ ++ /* Add all our formats that can be generated by VIN */ ++ cam->extra_fmt = rcar_vin_formats; ++ ++ n = ARRAY_SIZE(rcar_vin_formats); ++ formats += n; ++ for (k = 0; xlate && k < n; k++, xlate++) { ++ xlate->host_fmt = &rcar_vin_formats[k]; ++ xlate->code = code; ++ dev_dbg(dev, "Providing format %s using code %d\n", ++ rcar_vin_formats[k].name, code); ++ } ++ break; ++ default: ++ if (!rcar_vin_packing_supported(fmt)) ++ return 0; ++ ++ dev_dbg(dev, "Providing format %s in pass-through mode\n", ++ fmt->name); ++ break; ++ } ++ ++ /* Generic pass-through */ ++ formats++; ++ if (xlate) { ++ xlate->host_fmt = fmt; ++ xlate->code = code; ++ xlate++; ++ } ++ ++ return formats; ++} ++ ++static void rcar_vin_put_formats(struct soc_camera_device *icd) ++{ ++ kfree(icd->host_priv); ++ icd->host_priv = NULL; ++} ++ ++static int rcar_vin_set_crop(struct soc_camera_device *icd, ++ const struct v4l2_crop *a) ++{ ++ struct v4l2_crop a_writable = *a; ++ const struct v4l2_rect *rect = &a_writable.c; ++ struct soc_camera_host *ici = to_soc_camera_host(icd->parent); ++ struct rcar_vin_priv *priv = ici->priv; ++ struct v4l2_crop cam_crop; ++ struct rcar_vin_cam *cam = icd->host_priv; ++ struct v4l2_rect *cam_rect = &cam_crop.c; ++ struct v4l2_subdev *sd = soc_camera_to_subdev(icd); ++ struct device *dev = icd->parent; ++ struct v4l2_mbus_framefmt mf; ++ u32 vnmc; ++ int ret, i; ++ ++ dev_dbg(dev, "S_CROP(%ux%u@%u:%u)\n", rect->width, rect->height, ++ rect->left, rect->top); ++ ++ /* During camera cropping its output window can change too, stop VIN */ ++ capture_stop_preserve(priv, &vnmc); ++ dev_dbg(dev, "VNMC_REG 0x%x\n", vnmc); ++ ++ /* Apply iterative camera S_CROP for new input window. */ ++ ret = soc_camera_client_s_crop(sd, &a_writable, &cam_crop, ++ &cam->rect, &cam->subrect); ++ if (ret < 0) ++ return ret; ++ ++ dev_dbg(dev, "camera cropped to %ux%u@%u:%u\n", ++ cam_rect->width, cam_rect->height, ++ cam_rect->left, cam_rect->top); ++ ++ /* On success cam_crop contains current camera crop */ ++ ++ /* Retrieve camera output window */ ++ ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf); ++ if (ret < 0) ++ return ret; ++ ++ if (mf.width > VIN_MAX_WIDTH || mf.height > VIN_MAX_HEIGHT) ++ return -EINVAL; ++ ++ /* Cache camera output window */ ++ cam->width = mf.width; ++ cam->height = mf.height; ++ ++ icd->user_width = cam->width; ++ icd->user_height = cam->height; ++ ++ cam->vin_left = rect->left & ~1; ++ cam->vin_top = rect->top & ~1; ++ ++ /* Use VIN cropping to crop to the new window. */ ++ ret = rcar_vin_set_rect(icd); ++ if (ret < 0) ++ return ret; ++ ++ cam->subrect = *rect; ++ ++ dev_dbg(dev, "VIN cropped to %ux%u@%u:%u\n", ++ icd->user_width, icd->user_height, ++ cam->vin_left, cam->vin_top); ++ ++ /* Restore capture */ ++ for (i = 0; i < MAX_BUFFER_NUM; i++) { ++ if (priv->queue_buf[i] && priv->state == STOPPED) { ++ vnmc |= VNMC_ME; ++ break; ++ } ++ } ++ capture_restore(priv, vnmc); ++ ++ /* Even if only camera cropping succeeded */ ++ return ret; ++} ++ ++static int rcar_vin_get_crop(struct soc_camera_device *icd, ++ struct v4l2_crop *a) ++{ ++ struct rcar_vin_cam *cam = icd->host_priv; ++ ++ a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; ++ a->c = cam->subrect; ++ ++ return 0; ++} ++ ++/* Similar to set_crop multistage iterative algorithm */ ++static int rcar_vin_set_fmt(struct soc_camera_device *icd, ++ struct v4l2_format *f) ++{ ++ struct soc_camera_host *ici = to_soc_camera_host(icd->parent); ++ struct rcar_vin_priv *priv = ici->priv; ++ struct v4l2_subdev *sd = soc_camera_to_subdev(icd); ++ struct rcar_vin_cam *cam = icd->host_priv; ++ struct v4l2_pix_format *pix = &f->fmt.pix; ++ struct v4l2_mbus_framefmt mf; ++ struct device *dev = icd->parent; ++ __u32 pixfmt = pix->pixelformat; ++ const struct soc_camera_format_xlate *xlate; ++ unsigned int vin_sub_width = 0, vin_sub_height = 0; ++ int ret; ++ bool can_scale; ++ enum v4l2_field field; ++ v4l2_std_id std; ++ ++ dev_dbg(dev, "S_FMT(pix=0x%x, %ux%u)\n", ++ pixfmt, pix->width, pix->height); ++ ++ switch (pix->field) { ++ default: ++ pix->field = V4L2_FIELD_NONE; ++ /* fall-through */ ++ case V4L2_FIELD_NONE: ++ case V4L2_FIELD_TOP: ++ case V4L2_FIELD_BOTTOM: ++ case V4L2_FIELD_INTERLACED_TB: ++ case V4L2_FIELD_INTERLACED_BT: ++ field = pix->field; ++ break; ++ case V4L2_FIELD_INTERLACED: ++ /* Query for standard if not explicitly mentioned _TB/_BT */ ++ ret = v4l2_subdev_call(sd, video, querystd, &std); ++ if (ret < 0) ++ std = V4L2_STD_625_50; ++ ++ field = std & V4L2_STD_625_50 ? V4L2_FIELD_INTERLACED_TB : ++ V4L2_FIELD_INTERLACED_BT; ++ break; ++ } ++ ++ xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); ++ if (!xlate) { ++ dev_warn(dev, "Format %x not found\n", pixfmt); ++ return -EINVAL; ++ } ++ /* Calculate client output geometry */ ++ soc_camera_calc_client_output(icd, &cam->rect, &cam->subrect, pix, &mf, ++ 12); ++ mf.field = pix->field; ++ mf.colorspace = pix->colorspace; ++ mf.code = xlate->code; ++ ++ switch (pixfmt) { ++ case V4L2_PIX_FMT_RGB32: ++ can_scale = priv->chip != RCAR_E1; ++ break; ++ case V4L2_PIX_FMT_UYVY: ++ case V4L2_PIX_FMT_YUYV: ++ case V4L2_PIX_FMT_RGB565: ++ case V4L2_PIX_FMT_RGB555X: ++ can_scale = true; ++ break; ++ default: ++ can_scale = false; ++ break; ++ } ++ ++ dev_dbg(dev, "request camera output %ux%u\n", mf.width, mf.height); ++ ++ ret = soc_camera_client_scale(icd, &cam->rect, &cam->subrect, ++ &mf, &vin_sub_width, &vin_sub_height, ++ can_scale, 12); ++ ++ /* Done with the camera. Now see if we can improve the result */ ++ dev_dbg(dev, "Camera %d fmt %ux%u, requested %ux%u\n", ++ ret, mf.width, mf.height, pix->width, pix->height); ++ ++ if (ret == -ENOIOCTLCMD) ++ dev_dbg(dev, "Sensor doesn't support scaling\n"); ++ else if (ret < 0) ++ return ret; ++ ++ if (mf.code != xlate->code) ++ return -EINVAL; ++ ++ /* Prepare VIN crop */ ++ cam->width = mf.width; ++ cam->height = mf.height; ++ ++ /* Use VIN scaling to scale to the requested user window. */ ++ ++ /* We cannot scale up */ ++ if (pix->width > vin_sub_width) ++ vin_sub_width = pix->width; ++ ++ if (pix->height > vin_sub_height) ++ vin_sub_height = pix->height; ++ ++ pix->colorspace = mf.colorspace; ++ ++ if (!can_scale) { ++ pix->width = vin_sub_width; ++ pix->height = vin_sub_height; ++ } ++ ++ /* ++ * We have calculated CFLCR, the actual configuration will be performed ++ * in rcar_vin_set_bus_param() ++ */ ++ ++ dev_dbg(dev, "W: %u : %u, H: %u : %u\n", ++ vin_sub_width, pix->width, vin_sub_height, pix->height); ++ ++ icd->current_fmt = xlate; ++ ++ priv->field = field; ++ ++ return 0; ++} ++ ++static int rcar_vin_try_fmt(struct soc_camera_device *icd, ++ struct v4l2_format *f) ++{ ++ const struct soc_camera_format_xlate *xlate; ++ struct v4l2_pix_format *pix = &f->fmt.pix; ++ struct v4l2_subdev *sd = soc_camera_to_subdev(icd); ++ struct v4l2_mbus_framefmt mf; ++ __u32 pixfmt = pix->pixelformat; ++ int width, height; ++ int ret; ++ ++ xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); ++ if (!xlate) { ++ xlate = icd->current_fmt; ++ dev_dbg(icd->parent, "Format %x not found, keeping %x\n", ++ pixfmt, xlate->host_fmt->fourcc); ++ pixfmt = xlate->host_fmt->fourcc; ++ pix->pixelformat = pixfmt; ++ pix->colorspace = icd->colorspace; ++ } ++ ++ /* FIXME: calculate using depth and bus width */ ++ v4l_bound_align_image(&pix->width, 2, VIN_MAX_WIDTH, 1, ++ &pix->height, 4, VIN_MAX_HEIGHT, 2, 0); ++ ++ width = pix->width; ++ height = pix->height; ++ ++ /* let soc-camera calculate these values */ ++ pix->bytesperline = 0; ++ pix->sizeimage = 0; ++ ++ /* limit to sensor capabilities */ ++ mf.width = pix->width; ++ mf.height = pix->height; ++ mf.field = pix->field; ++ mf.code = xlate->code; ++ mf.colorspace = pix->colorspace; ++ ++ ret = v4l2_device_call_until_err(sd->v4l2_dev, soc_camera_grp_id(icd), ++ video, try_mbus_fmt, &mf); ++ if (ret < 0) ++ return ret; ++ ++ pix->width = mf.width; ++ pix->height = mf.height; ++ pix->field = mf.field; ++ pix->colorspace = mf.colorspace; ++ ++ if (pixfmt == V4L2_PIX_FMT_NV16) { ++ /* FIXME: check against rect_max after converting soc-camera */ ++ /* We can scale precisely, need a bigger image from camera */ ++ if (pix->width < width || pix->height < height) { ++ /* ++ * We presume, the sensor behaves sanely, i.e. if ++ * requested a bigger rectangle, it will not return a ++ * smaller one. ++ */ ++ mf.width = VIN_MAX_WIDTH; ++ mf.height = VIN_MAX_HEIGHT; ++ ret = v4l2_device_call_until_err(sd->v4l2_dev, ++ soc_camera_grp_id(icd), ++ video, try_mbus_fmt, ++ &mf); ++ if (ret < 0) { ++ dev_err(icd->parent, ++ "client try_fmt() = %d\n", ret); ++ return ret; ++ } ++ } ++ /* We will scale exactly */ ++ if (mf.width > width) ++ pix->width = width; ++ if (mf.height > height) ++ pix->height = height; ++ } ++ ++ return ret; ++} ++ ++static unsigned int rcar_vin_poll(struct file *file, poll_table *pt) ++{ ++ struct soc_camera_device *icd = file->private_data; ++ ++ return vb2_poll(&icd->vb2_vidq, file, pt); ++} ++ ++static int rcar_vin_querycap(struct soc_camera_host *ici, ++ struct v4l2_capability *cap) ++{ ++ strlcpy(cap->card, "R_Car_VIN", sizeof(cap->card)); ++ cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; ++ return 0; ++} ++ ++static int rcar_vin_init_videobuf2(struct vb2_queue *vq, ++ struct soc_camera_device *icd) ++{ ++ vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; ++ vq->io_modes = VB2_MMAP | VB2_USERPTR; ++ vq->drv_priv = icd; ++ vq->ops = &rcar_vin_vb2_ops; ++ vq->mem_ops = &vb2_dma_contig_memops; ++ vq->buf_struct_size = sizeof(struct rcar_vin_buffer); ++ vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; ++ ++ return vb2_queue_init(vq); ++} ++ ++static struct soc_camera_host_ops rcar_vin_host_ops = { ++ .owner = THIS_MODULE, ++ .add = rcar_vin_add_device, ++ .remove = rcar_vin_remove_device, ++ .clock_start = rcar_vin_clock_start, ++ .clock_stop = rcar_vin_clock_stop, ++ .get_formats = rcar_vin_get_formats, ++ .put_formats = rcar_vin_put_formats, ++ .get_crop = rcar_vin_get_crop, ++ .set_crop = rcar_vin_set_crop, ++ .try_fmt = rcar_vin_try_fmt, ++ .set_fmt = rcar_vin_set_fmt, ++ .poll = rcar_vin_poll, ++ .querycap = rcar_vin_querycap, ++ .set_bus_param = rcar_vin_set_bus_param, ++ .init_videobuf2 = rcar_vin_init_videobuf2, ++}; ++ ++static struct platform_device_id rcar_vin_id_table[] = { ++ { "r8a7779-vin", RCAR_H1 }, ++ { "r8a7778-vin", RCAR_M1 }, ++ { "uPD35004-vin", RCAR_E1 }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(platform, rcar_vin_id_table); ++ ++static int rcar_vin_probe(struct platform_device *pdev) ++{ ++ struct rcar_vin_priv *priv; ++ struct resource *mem; ++ struct rcar_vin_platform_data *pdata; ++ int irq, ret; ++ ++ pdata = pdev->dev.platform_data; ++ if (!pdata || !pdata->flags) { ++ dev_err(&pdev->dev, "platform data not set\n"); ++ return -EINVAL; ++ } ++ ++ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (mem == NULL) ++ return -EINVAL; ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq <= 0) ++ return -EINVAL; ++ ++ priv = devm_kzalloc(&pdev->dev, sizeof(struct rcar_vin_priv), ++ GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ priv->base = devm_ioremap_resource(&pdev->dev, mem); ++ if (IS_ERR(priv->base)) ++ return PTR_ERR(priv->base); ++ ++ ret = devm_request_irq(&pdev->dev, irq, rcar_vin_irq, IRQF_SHARED, ++ dev_name(&pdev->dev), priv); ++ if (ret) ++ return ret; ++ ++ priv->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev); ++ if (IS_ERR(priv->alloc_ctx)) ++ return PTR_ERR(priv->alloc_ctx); ++ ++ priv->ici.priv = priv; ++ priv->ici.v4l2_dev.dev = &pdev->dev; ++ priv->ici.nr = pdev->id; ++ priv->ici.drv_name = dev_name(&pdev->dev); ++ priv->ici.ops = &rcar_vin_host_ops; ++ ++ priv->pdata = pdata; ++ priv->chip = pdev->id_entry->driver_data; ++ spin_lock_init(&priv->lock); ++ INIT_LIST_HEAD(&priv->capture); ++ ++ priv->state = STOPPED; ++ ++ pm_suspend_ignore_children(&pdev->dev, true); ++ pm_runtime_enable(&pdev->dev); ++ ++ ret = soc_camera_host_register(&priv->ici); ++ if (ret) ++ goto cleanup; ++ ++ return 0; ++ ++cleanup: ++ pm_runtime_disable(&pdev->dev); ++ vb2_dma_contig_cleanup_ctx(priv->alloc_ctx); ++ ++ return ret; ++} ++ ++static int rcar_vin_remove(struct platform_device *pdev) ++{ ++ struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev); ++ struct rcar_vin_priv *priv = container_of(soc_host, ++ struct rcar_vin_priv, ici); ++ ++ soc_camera_host_unregister(soc_host); ++ pm_runtime_disable(&pdev->dev); ++ vb2_dma_contig_cleanup_ctx(priv->alloc_ctx); ++ ++ return 0; ++} ++ ++static struct platform_driver rcar_vin_driver = { ++ .probe = rcar_vin_probe, ++ .remove = rcar_vin_remove, ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ }, ++ .id_table = rcar_vin_id_table, ++}; ++ ++module_platform_driver(rcar_vin_driver); ++ ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:rcar_vin"); ++MODULE_DESCRIPTION("Renesas R-Car VIN camera host driver"); +diff --git a/include/linux/platform_data/camera-rcar.h b/include/linux/platform_data/camera-rcar.h +new file mode 100644 +index 00000000..dfc83c58 +--- /dev/null ++++ b/include/linux/platform_data/camera-rcar.h +@@ -0,0 +1,25 @@ ++/* ++ * Platform data for Renesas R-Car VIN soc-camera driver ++ * ++ * Copyright (C) 2011-2013 Renesas Solutions Corp. ++ * Copyright (C) 2013 Cogent Embedded, Inc., <source@cogentembedded.com> ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __CAMERA_RCAR_H_ ++#define __CAMERA_RCAR_H_ ++ ++#define RCAR_VIN_HSYNC_ACTIVE_LOW (1 << 0) ++#define RCAR_VIN_VSYNC_ACTIVE_LOW (1 << 1) ++#define RCAR_VIN_BT601 (1 << 2) ++#define RCAR_VIN_BT656 (1 << 3) ++ ++struct rcar_vin_platform_data { ++ unsigned int flags; ++}; ++ ++#endif /* __CAMERA_RCAR_H_ */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0069-ARM-dts-r8a7740-cpus-cpu-nodes-dts-updates.patch b/patches.renesas/0069-ARM-dts-r8a7740-cpus-cpu-nodes-dts-updates.patch new file mode 100644 index 00000000000..2b061920e2d --- /dev/null +++ b/patches.renesas/0069-ARM-dts-r8a7740-cpus-cpu-nodes-dts-updates.patch @@ -0,0 +1,36 @@ +From 0cca96aff0e7931ed7b8aefcdb32bfc3012bcd17 Mon Sep 17 00:00:00 2001 +From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> +Date: Thu, 18 Apr 2013 18:39:50 +0100 +Subject: ARM: dts: r8a7740: cpus/cpu nodes dts updates + +This patch updates the in-kernel dts files according to the latest cpus +and cpu bindings updates for ARM. + +Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> +Acked-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit b403201377deb51e2efbf4713f7047f292482796) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7740.dtsi | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi +index 798fa35c..8a831e91 100644 +--- a/arch/arm/boot/dts/r8a7740.dtsi ++++ b/arch/arm/boot/dts/r8a7740.dtsi +@@ -14,8 +14,12 @@ + compatible = "renesas,r8a7740"; + + cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; + cpu@0 { + compatible = "arm,cortex-a9"; ++ device_type = "cpu"; ++ reg = <0x0>; + }; + }; + }; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0070-ARM-dts-sh7372-cpus-cpu-nodes-dts-updates.patch b/patches.renesas/0070-ARM-dts-sh7372-cpus-cpu-nodes-dts-updates.patch new file mode 100644 index 00000000000..6ba49adca40 --- /dev/null +++ b/patches.renesas/0070-ARM-dts-sh7372-cpus-cpu-nodes-dts-updates.patch @@ -0,0 +1,37 @@ +From 0b28393d43129be84754c885e7803ff9fc44ba66 Mon Sep 17 00:00:00 2001 +From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> +Date: Thu, 18 Apr 2013 18:39:50 +0100 +Subject: ARM: dts: sh7372: cpus/cpu nodes dts updates + +This patch updates the in-kernel dts files according to the latest cpus +and cpu bindings updates for ARM. + +Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> +Acked-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 35fae4c313f3b211c6b98678aad31adc5f9f6ba4) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/sh7372.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi +index 677fc603..7bf020ec 100644 +--- a/arch/arm/boot/dts/sh7372.dtsi ++++ b/arch/arm/boot/dts/sh7372.dtsi +@@ -14,8 +14,13 @@ + compatible = "renesas,sh7372"; + + cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ + cpu@0 { + compatible = "arm,cortex-a8"; ++ device_type = "cpu"; ++ reg = <0x0>; + }; + }; + }; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0071-ARM-shmobile-r8a7740-Add-OF-support-to-initialze-the.patch b/patches.renesas/0071-ARM-shmobile-r8a7740-Add-OF-support-to-initialze-the.patch new file mode 100644 index 00000000000..954f0e2506a --- /dev/null +++ b/patches.renesas/0071-ARM-shmobile-r8a7740-Add-OF-support-to-initialze-the.patch @@ -0,0 +1,78 @@ +From 7452e947806b1443e50971504158cbabd647d2db Mon Sep 17 00:00:00 2001 +From: Bastian Hecht <hechtb@gmail.com> +Date: Wed, 17 Apr 2013 12:34:04 +0200 +Subject: ARM: shmobile: r8a7740: Add OF support to initialze the GIC + +We add a variant to initalize the interrupt controller in case we describe +the GIC using the Device Tree and not platform data. + +Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit f9b4df4a4d7d1124c450f0713a7a1939c7f1a205) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/include/mach/r8a7740.h | 1 + + arch/arm/mach-shmobile/intc-r8a7740.c | 24 ++++++++++++++++++------ + 2 files changed, 19 insertions(+), 6 deletions(-) + +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h +index abdc4d4e..19c04231 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h +@@ -534,6 +534,7 @@ enum { + + extern void r8a7740_meram_workaround(void); + extern void r8a7740_init_irq(void); ++extern void r8a7740_init_irq_of(void); + extern void r8a7740_map_io(void); + extern void r8a7740_add_early_devices(void); + extern void r8a7740_add_standard_devices(void); +diff --git a/arch/arm/mach-shmobile/intc-r8a7740.c b/arch/arm/mach-shmobile/intc-r8a7740.c +index b741c840..8871f771 100644 +--- a/arch/arm/mach-shmobile/intc-r8a7740.c ++++ b/arch/arm/mach-shmobile/intc-r8a7740.c +@@ -20,19 +20,15 @@ + + #include <linux/init.h> + #include <linux/io.h> ++#include <linux/irqchip.h> + #include <linux/irqchip/arm-gic.h> + +-void __init r8a7740_init_irq(void) ++static void __init r8a7740_init_irq_common(void) + { +- void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000); +- void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000); + void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10); + void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10); + void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4); + +- /* initialize the Generic Interrupt Controller PL390 r0p0 */ +- gic_init(0, 29, gic_dist_base, gic_cpu_base); +- + /* route signals to GIC */ + iowrite32(0x0, pfc_inta_ctrl); + +@@ -54,3 +50,19 @@ void __init r8a7740_init_irq(void) + iounmap(intc_msk_base); + iounmap(pfc_inta_ctrl); + } ++ ++void __init r8a7740_init_irq_of(void) ++{ ++ irqchip_init(); ++ r8a7740_init_irq_common(); ++} ++ ++void __init r8a7740_init_irq(void) ++{ ++ void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000); ++ void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000); ++ ++ /* initialize the Generic Interrupt Controller PL390 r0p0 */ ++ gic_init(0, 29, gic_dist_base, gic_cpu_base); ++ r8a7740_init_irq_common(); ++} +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0072-ARM-shmobile-r8a7740-Prepare-for-reference-DT-setup.patch b/patches.renesas/0072-ARM-shmobile-r8a7740-Prepare-for-reference-DT-setup.patch new file mode 100644 index 00000000000..2c3b6f4aa06 --- /dev/null +++ b/patches.renesas/0072-ARM-shmobile-r8a7740-Prepare-for-reference-DT-setup.patch @@ -0,0 +1,284 @@ +From 5a5688a64c8d3c5d6b7b09b091ed49d87ea7b4d8 Mon Sep 17 00:00:00 2001 +From: Bastian Hecht <hechtb@gmail.com> +Date: Wed, 17 Apr 2013 12:34:05 +0200 +Subject: ARM: shmobile: r8a7740: Prepare for reference DT setup + +We need three steps to prepare for the new Armadillo reference DT board code: + - Split the device list into r8a7740_early_devices used by the old platform + data setup (board-armadillo.c) and r8a7740_devices_dt used by both + setup variants. + - Introduce new r8a7740_init_delay() to be more flexible about calling + shmobile_setup_delay(). + - For the generic r8a7740 support, we switch to device tree setup for + the GIC, the irqpin devices and the I2C controllers. + +This is slightly similar to commit 3b00f9342623a5ebc +"ARM: shmobile: sh73a0: Do not use early devices with DT reference" + +Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 744fdc8dc0e22cc5b61ee1bcde9375f188daa330) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7740.dtsi | 117 ++++++++++++++++++++++++++ + arch/arm/mach-shmobile/include/mach/r8a7740.h | 2 + + arch/arm/mach-shmobile/setup-r8a7740.c | 54 ++++++------ + 3 files changed, 148 insertions(+), 25 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi +index 8a831e91..24e93064 100644 +--- a/arch/arm/boot/dts/r8a7740.dtsi ++++ b/arch/arm/boot/dts/r8a7740.dtsi +@@ -22,4 +22,121 @@ + reg = <0x0>; + }; + }; ++ ++ gic: interrupt-controller@c2800000 { ++ compatible = "arm,cortex-a9-gic"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ interrupt-controller; ++ reg = <0xc2800000 0x1000>, ++ <0xc2000000 0x1000>; ++ }; ++ ++ /* irqpin0: IRQ0 - IRQ7 */ ++ irqpin0: irqpin@e6900000 { ++ compatible = "renesas,intc-irqpin"; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ reg = <0xe6900000 4>, ++ <0xe6900010 4>, ++ <0xe6900020 1>, ++ <0xe6900040 1>, ++ <0xe6900060 1>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 149 0x4 ++ 0 149 0x4 ++ 0 149 0x4 ++ 0 149 0x4 ++ 0 149 0x4 ++ 0 149 0x4 ++ 0 149 0x4 ++ 0 149 0x4>; ++ }; ++ ++ /* irqpin1: IRQ8 - IRQ15 */ ++ irqpin1: irqpin@e6900004 { ++ compatible = "renesas,intc-irqpin"; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ reg = <0xe6900004 4>, ++ <0xe6900014 4>, ++ <0xe6900024 1>, ++ <0xe6900044 1>, ++ <0xe6900064 1>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 149 0x4 ++ 0 149 0x4 ++ 0 149 0x4 ++ 0 149 0x4 ++ 0 149 0x4 ++ 0 149 0x4 ++ 0 149 0x4 ++ 0 149 0x4>; ++ }; ++ ++ /* irqpin2: IRQ16 - IRQ23 */ ++ irqpin2: irqpin@e6900008 { ++ compatible = "renesas,intc-irqpin"; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ reg = <0xe6900008 4>, ++ <0xe6900018 4>, ++ <0xe6900028 1>, ++ <0xe6900048 1>, ++ <0xe6900068 1>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 149 0x4 ++ 0 149 0x4 ++ 0 149 0x4 ++ 0 149 0x4 ++ 0 149 0x4 ++ 0 149 0x4 ++ 0 149 0x4 ++ 0 149 0x4>; ++ }; ++ ++ /* irqpin3: IRQ24 - IRQ31 */ ++ irqpin3: irqpin@e690000c { ++ compatible = "renesas,intc-irqpin"; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ reg = <0xe690000c 4>, ++ <0xe690001c 4>, ++ <0xe690002c 1>, ++ <0xe690004c 1>, ++ <0xe690006c 1>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 149 0x4 ++ 0 149 0x4 ++ 0 149 0x4 ++ 0 149 0x4 ++ 0 149 0x4 ++ 0 149 0x4 ++ 0 149 0x4 ++ 0 149 0x4>; ++ }; ++ ++ i2c0: i2c@fff20000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "renesas,rmobile-iic"; ++ reg = <0xfff20000 0x425>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 201 0x4 ++ 0 202 0x4 ++ 0 203 0x4 ++ 0 204 0x4>; ++ }; ++ ++ i2c1: i2c@e6c20000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "renesas,rmobile-iic"; ++ reg = <0xe6c20000 0x425>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 70 0x4 ++ 0 71 0x4 ++ 0 72 0x4 ++ 0 73 0x4>; ++ }; + }; +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h +index 19c04231..1cf6869b 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h +@@ -533,11 +533,13 @@ enum { + }; + + extern void r8a7740_meram_workaround(void); ++extern void r8a7740_init_delay(void); + extern void r8a7740_init_irq(void); + extern void r8a7740_init_irq_of(void); + extern void r8a7740_map_io(void); + extern void r8a7740_add_early_devices(void); + extern void r8a7740_add_standard_devices(void); ++extern void r8a7740_add_standard_devices_dt(void); + extern void r8a7740_clock_init(u8 md_ck); + extern void r8a7740_pinmux_init(void); + extern void r8a7740_pm_init(void); +diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c +index 326a4ab0..9284e6fd 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7740.c ++++ b/arch/arm/mach-shmobile/setup-r8a7740.c +@@ -531,11 +531,7 @@ static struct platform_device ipmmu_device = { + .num_resources = ARRAY_SIZE(ipmmu_resources), + }; + +-static struct platform_device *r8a7740_early_devices[] __initdata = { +- &irqpin0_device, +- &irqpin1_device, +- &irqpin2_device, +- &irqpin3_device, ++static struct platform_device *r8a7740_devices_dt[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, +@@ -546,6 +542,13 @@ static struct platform_device *r8a7740_early_devices[] __initdata = { + &scif7_device, + &scifb_device, + &cmt10_device, ++}; ++ ++static struct platform_device *r8a7740_early_devices[] __initdata = { ++ &irqpin0_device, ++ &irqpin1_device, ++ &irqpin2_device, ++ &irqpin3_device, + &tmu00_device, + &tmu01_device, + &tmu02_device, +@@ -965,6 +968,8 @@ void __init r8a7740_add_standard_devices(void) + /* add devices */ + platform_add_devices(r8a7740_early_devices, + ARRAY_SIZE(r8a7740_early_devices)); ++ platform_add_devices(r8a7740_devices_dt, ++ ARRAY_SIZE(r8a7740_devices_dt)); + platform_add_devices(r8a7740_late_devices, + ARRAY_SIZE(r8a7740_late_devices)); + +@@ -986,6 +991,8 @@ void __init r8a7740_add_early_devices(void) + { + early_platform_add_devices(r8a7740_early_devices, + ARRAY_SIZE(r8a7740_early_devices)); ++ early_platform_add_devices(r8a7740_devices_dt, ++ ARRAY_SIZE(r8a7740_devices_dt)); + + /* setup early console here as well */ + shmobile_setup_console(); +@@ -993,33 +1000,29 @@ void __init r8a7740_add_early_devices(void) + + #ifdef CONFIG_USE_OF + +-void __init r8a7740_add_early_devices_dt(void) +-{ +- shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */ +- +- early_platform_add_devices(r8a7740_early_devices, +- ARRAY_SIZE(r8a7740_early_devices)); +- +- /* setup early console here as well */ +- shmobile_setup_console(); +-} +- + static const struct of_dev_auxdata r8a7740_auxdata_lookup[] __initconst = { + { } + }; + + void __init r8a7740_add_standard_devices_dt(void) + { +- /* clocks are setup late during boot in the case of DT */ +- r8a7740_clock_init(0); +- +- platform_add_devices(r8a7740_early_devices, +- ARRAY_SIZE(r8a7740_early_devices)); +- ++ platform_add_devices(r8a7740_devices_dt, ++ ARRAY_SIZE(r8a7740_devices_dt)); + of_platform_populate(NULL, of_default_bus_match_table, + r8a7740_auxdata_lookup, NULL); + } + ++void __init r8a7740_init_delay(void) ++{ ++ shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */ ++}; ++ ++static void __init r8a7740_generic_init(void) ++{ ++ r8a7740_clock_init(0); ++ r8a7740_add_standard_devices_dt(); ++} ++ + static const char *r8a7740_boards_compat_dt[] __initdata = { + "renesas,r8a7740", + NULL, +@@ -1027,9 +1030,10 @@ static const char *r8a7740_boards_compat_dt[] __initdata = { + + DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)") + .map_io = r8a7740_map_io, +- .init_early = r8a7740_add_early_devices_dt, +- .init_irq = r8a7740_init_irq, +- .init_machine = r8a7740_add_standard_devices_dt, ++ .init_early = r8a7740_init_delay, ++ .init_irq = r8a7740_init_irq_of, ++ .init_machine = r8a7740_generic_init, ++ .init_time = shmobile_timer_init, + .dt_compat = r8a7740_boards_compat_dt, + MACHINE_END + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0073-ARM-shmobile-Remove-unused-r8a73a4-GIC-CPU-interface.patch b/patches.renesas/0073-ARM-shmobile-Remove-unused-r8a73a4-GIC-CPU-interface.patch new file mode 100644 index 00000000000..b50061e6893 --- /dev/null +++ b/patches.renesas/0073-ARM-shmobile-Remove-unused-r8a73a4-GIC-CPU-interface.patch @@ -0,0 +1,35 @@ +From 35e37e69cb29876008ffc0c677ad56ea6938c006 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Thu, 16 May 2013 15:03:55 +0900 +Subject: ARM: shmobile: Remove unused r8a73a4 GIC CPU interface DT bits + +Remove unused GIC CPU interface DT bits for r8a73a4. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 572db906e0a523fe9cdb74c1e9e518ea99a2f7f2) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a73a4.dtsi | 6 ------ + 1 file changed, 6 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi +index fde2a337..4ff2019c 100644 +--- a/arch/arm/boot/dts/r8a73a4.dtsi ++++ b/arch/arm/boot/dts/r8a73a4.dtsi +@@ -37,12 +37,6 @@ + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = <1 9 0xf04>; +- +- gic-cpuif@4 { +- compatible = "arm,gic-cpuif"; +- cpuif-id = <4>; +- cpu = <&cpu0>; +- }; + }; + + timer { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0074-ARM-shmobile-Remove-unused-r8a7790-GIC-CPU-interface.patch b/patches.renesas/0074-ARM-shmobile-Remove-unused-r8a7790-GIC-CPU-interface.patch new file mode 100644 index 00000000000..36ce7c6b5b5 --- /dev/null +++ b/patches.renesas/0074-ARM-shmobile-Remove-unused-r8a7790-GIC-CPU-interface.patch @@ -0,0 +1,35 @@ +From 87a705a55800d3cbd6db764ca204cffe0f9af6a3 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Thu, 16 May 2013 15:05:16 +0900 +Subject: ARM: shmobile: Remove unused r8a7790 GIC CPU interface DT bits + +Remove unused GIC CPU interface DT bits for r8a7790. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 47016c7186faf7e0deae52d52ac6943df0e65154) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7790.dtsi | 6 ------ + 1 file changed, 6 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi +index 7a171102..339d9b11 100644 +--- a/arch/arm/boot/dts/r8a7790.dtsi ++++ b/arch/arm/boot/dts/r8a7790.dtsi +@@ -36,12 +36,6 @@ + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = <1 9 0xf04>; +- +- gic-cpuif@4 { +- compatible = "arm,gic-cpuif"; +- cpuif-id = <4>; +- cpu = <&cpu0>; +- }; + }; + + timer { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0075-ARM-shmobile-armadillo800eva-Reference-DT-implementa.patch b/patches.renesas/0075-ARM-shmobile-armadillo800eva-Reference-DT-implementa.patch new file mode 100644 index 00000000000..2f975fb4423 --- /dev/null +++ b/patches.renesas/0075-ARM-shmobile-armadillo800eva-Reference-DT-implementa.patch @@ -0,0 +1,352 @@ +From 0663fefc701a07b0b066a5b5ad492d30253a6bd3 Mon Sep 17 00:00:00 2001 +From: Bastian Hecht <hechtb@gmail.com> +Date: Wed, 17 Apr 2013 12:34:06 +0200 +Subject: ARM: shmobile: armadillo800eva: Reference DT implementation + +Provide alternate board code for the Armadillo800EVA to demonstrate how +DT may be used given the current state of driver device tree support. +This is intended to act as a reference for mach-shmobile developers. + +This a rather bare bone version with the following devices supported: + + - GIC + - irqpins + - i2c0/1 + - touchscreen + +Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 76b92b4043f2303b443645b5609a8867e8a8b5d7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/Makefile | 1 + + .../boot/dts/r8a7740-armadillo800eva-reference.dts | 45 +++++ + arch/arm/mach-shmobile/Kconfig | 14 ++ + arch/arm/mach-shmobile/Makefile | 1 + + .../board-armadillo800eva-reference.c | 213 +++++++++++++++++++++ + 5 files changed, 274 insertions(+) + create mode 100644 arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts + create mode 100644 arch/arm/mach-shmobile/board-armadillo800eva-reference.c + +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index f0895c58..389725e5 100644 +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -162,6 +162,7 @@ dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \ + dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ + r8a7740-armadillo800eva.dtb \ + r8a7778-bockw.dtb \ ++ r8a7740-armadillo800eva-reference.dtb \ + r8a7779-marzen-reference.dtb \ + r8a7790-lager.dtb \ + sh73a0-kzm9g.dtb \ +diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +new file mode 100644 +index 00000000..09ea22c2 +--- /dev/null ++++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +@@ -0,0 +1,45 @@ ++/* ++ * Reference Device Tree Source for the armadillo 800 eva board ++ * ++ * Copyright (C) 2012 Renesas Solutions Corp. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++/dts-v1/; ++/include/ "r8a7740.dtsi" ++ ++/ { ++ model = "armadillo 800 eva reference"; ++ compatible = "renesas,armadillo800eva-reference", "renesas,r8a7740"; ++ ++ chosen { ++ bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096 rw"; ++ }; ++ ++ memory { ++ device_type = "memory"; ++ reg = <0x40000000 0x20000000>; ++ }; ++ ++ reg_3p3v: regulator@0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-3.3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++}; ++ ++&i2c0 { ++ touchscreen: st1232@55 { ++ compatible = "sitronix,st1232"; ++ reg = <0x55>; ++ interrupt-parent = <&irqpin1>; ++ interrupts = <2 0>; /* IRQ10: hwirq 2 on irqpin1 */ ++ }; ++}; +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index 1a517e2f..c6fb9ec8 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -129,6 +129,20 @@ config MACH_ARMADILLO800EVA + select SND_SOC_WM8978 if SND_SIMPLE_CARD + select USE_OF + ++config MACH_ARMADILLO800EVA_REFERENCE ++ bool "Armadillo-800 EVA board - Reference Device Tree Implementation" ++ depends on ARCH_R8A7740 ++ select ARCH_REQUIRE_GPIOLIB ++ select REGULATOR_FIXED_VOLTAGE if REGULATOR ++ select SND_SOC_WM8978 if SND_SIMPLE_CARD ++ select USE_OF ++ ---help--- ++ Use reference implementation of Aramdillo800 EVA board support ++ which makes a greater use of device tree at the expense ++ of not supporting a number of devices. ++ ++ This is intended to aid developers ++ + config MACH_BOCKW + bool "BOCK-W platform" + depends on ARCH_R8A7778 +diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile +index 068f1dad..812de045 100644 +--- a/arch/arm/mach-shmobile/Makefile ++++ b/arch/arm/mach-shmobile/Makefile +@@ -46,6 +46,7 @@ obj-$(CONFIG_MACH_MARZEN) += board-marzen.o + obj-$(CONFIG_MACH_MARZEN_REFERENCE) += board-marzen-reference.o + obj-$(CONFIG_MACH_LAGER) += board-lager.o + obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o ++obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += board-armadillo800eva-reference.o + obj-$(CONFIG_MACH_KZM9D) += board-kzm9d.o + obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o + obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o +diff --git a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c +new file mode 100644 +index 00000000..03b85fec +--- /dev/null ++++ b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c +@@ -0,0 +1,213 @@ ++/* ++ * armadillo 800 eva board support ++ * ++ * Copyright (C) 2012 Renesas Solutions Corp. ++ * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ++ * ++ */ ++ ++#include <linux/clk.h> ++#include <linux/err.h> ++#include <linux/kernel.h> ++#include <linux/gpio.h> ++#include <linux/io.h> ++#include <linux/pinctrl/machine.h> ++#include <mach/common.h> ++#include <mach/r8a7740.h> ++#include <asm/mach/arch.h> ++#include <asm/hardware/cache-l2x0.h> ++ ++/* ++ * CON1 Camera Module ++ * CON2 Extension Bus ++ * CON3 HDMI Output ++ * CON4 Composite Video Output ++ * CON5 H-UDI JTAG ++ * CON6 ARM JTAG ++ * CON7 SD1 ++ * CON8 SD2 ++ * CON9 RTC BackUp ++ * CON10 Monaural Mic Input ++ * CON11 Stereo Headphone Output ++ * CON12 Audio Line Output(L) ++ * CON13 Audio Line Output(R) ++ * CON14 AWL13 Module ++ * CON15 Extension ++ * CON16 LCD1 ++ * CON17 LCD2 ++ * CON19 Power Input ++ * CON20 USB1 ++ * CON21 USB2 ++ * CON22 Serial ++ * CON23 LAN ++ * CON24 USB3 ++ * LED1 Camera LED(Yellow) ++ * LED2 Power LED (Green) ++ * ED3-LED6 User LED(Yellow) ++ * LED7 LAN link LED(Green) ++ * LED8 LAN activity LED(Yellow) ++ */ ++ ++/* ++ * DipSwitch ++ * ++ * SW1 ++ * ++ * -12345678-+---------------+---------------------------- ++ * 1 | boot | hermit ++ * 0 | boot | OS auto boot ++ * -12345678-+---------------+---------------------------- ++ * 00 | boot device | eMMC ++ * 10 | boot device | SDHI0 (CON7) ++ * 01 | boot device | - ++ * 11 | boot device | Extension Buss (CS0) ++ * -12345678-+---------------+---------------------------- ++ * 0 | Extension Bus | D8-D15 disable, eMMC enable ++ * 1 | Extension Bus | D8-D15 enable, eMMC disable ++ * -12345678-+---------------+---------------------------- ++ * 0 | SDHI1 | COM8 disable, COM14 enable ++ * 1 | SDHI1 | COM8 enable, COM14 disable ++ * -12345678-+---------------+---------------------------- ++ * 0 | USB0 | COM20 enable, COM24 disable ++ * 1 | USB0 | COM20 disable, COM24 enable ++ * -12345678-+---------------+---------------------------- ++ * 00 | JTAG | SH-X2 ++ * 10 | JTAG | ARM ++ * 01 | JTAG | - ++ * 11 | JTAG | Boundary Scan ++ *-----------+---------------+---------------------------- ++ */ ++ ++/* ++ * FSI-WM8978 ++ * ++ * this command is required when playback. ++ * ++ * # amixer set "Headphone" 50 ++ * ++ * this command is required when capture. ++ * ++ * # amixer set "Input PGA" 15 ++ * # amixer set "Left Input Mixer MicP" on ++ * # amixer set "Left Input Mixer MicN" on ++ * # amixer set "Right Input Mixer MicN" on ++ * # amixer set "Right Input Mixer MicP" on ++ */ ++ ++/* ++ * USB function ++ * ++ * When you use USB Function, ++ * set SW1.6 ON, and connect cable to CN24. ++ * ++ * USBF needs workaround on R8A7740 chip. ++ * These are a little bit complex. ++ * see ++ * usbhsf_power_ctrl() ++ */ ++ ++static const struct pinctrl_map eva_pinctrl_map[] = { ++ /* SCIFA1 */ ++ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.1", "pfc-r8a7740", ++ "scifa1_data", "scifa1"), ++}; ++ ++static void __init eva_clock_init(void) ++{ ++ struct clk *system = clk_get(NULL, "system_clk"); ++ struct clk *xtal1 = clk_get(NULL, "extal1"); ++ struct clk *usb24s = clk_get(NULL, "usb24s"); ++ struct clk *fsibck = clk_get(NULL, "fsibck"); ++ ++ if (IS_ERR(system) || ++ IS_ERR(xtal1) || ++ IS_ERR(usb24s) || ++ IS_ERR(fsibck)) { ++ pr_err("armadillo800eva board clock init failed\n"); ++ goto clock_error; ++ } ++ ++ /* armadillo 800 eva extal1 is 24MHz */ ++ clk_set_rate(xtal1, 24000000); ++ ++ /* usb24s use extal1 (= system) clock (= 24MHz) */ ++ clk_set_parent(usb24s, system); ++ ++ /* FSIBCK is 12.288MHz, and it is parent of FSI-B */ ++ clk_set_rate(fsibck, 12288000); ++ ++clock_error: ++ if (!IS_ERR(system)) ++ clk_put(system); ++ if (!IS_ERR(xtal1)) ++ clk_put(xtal1); ++ if (!IS_ERR(usb24s)) ++ clk_put(usb24s); ++ if (!IS_ERR(fsibck)) ++ clk_put(fsibck); ++} ++ ++/* ++ * board init ++ */ ++static void __init eva_init(void) ++{ ++ ++ r8a7740_clock_init(MD_CK0 | MD_CK2); ++ eva_clock_init(); ++ ++ pinctrl_register_mappings(eva_pinctrl_map, ARRAY_SIZE(eva_pinctrl_map)); ++ r8a7740_pinmux_init(); ++ ++ r8a7740_meram_workaround(); ++ ++ /* ++ * Touchscreen ++ * TODO: Move reset GPIO over to .dts when we can reference it ++ */ ++ gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */ ++ ++#ifdef CONFIG_CACHE_L2X0 ++ /* Early BRESP enable, Shared attribute override enable, 32K*8way */ ++ l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff); ++#endif ++ ++ r8a7740_add_standard_devices_dt(); ++ r8a7740_pm_init(); ++} ++ ++#define RESCNT2 IOMEM(0xe6188020) ++static void eva_restart(char mode, const char *cmd) ++{ ++ /* Do soft power on reset */ ++ writel((1 << 31), RESCNT2); ++} ++ ++static const char *eva_boards_compat_dt[] __initdata = { ++ "renesas,armadillo800eva-reference", ++ NULL, ++}; ++ ++DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva-reference") ++ .map_io = r8a7740_map_io, ++ .init_early = r8a7740_init_delay, ++ .init_irq = r8a7740_init_irq_of, ++ .init_machine = eva_init, ++ .init_time = shmobile_timer_init, ++ .init_late = shmobile_init_late, ++ .dt_compat = eva_boards_compat_dt, ++ .restart = eva_restart, ++MACHINE_END +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0076-ARM-shmobile-kzm9g-reference-add-AS3711-and-CPUFreq-.patch b/patches.renesas/0076-ARM-shmobile-kzm9g-reference-add-AS3711-and-CPUFreq-.patch new file mode 100644 index 00000000000..ba9635fca2c --- /dev/null +++ b/patches.renesas/0076-ARM-shmobile-kzm9g-reference-add-AS3711-and-CPUFreq-.patch @@ -0,0 +1,125 @@ +From ad150e26fcd8865a603be5866a58d939521a1802 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Fri, 5 Apr 2013 12:00:37 +0200 +Subject: ARM: shmobile: kzm9g-reference: add AS3711 and CPUFreq DT bindings + +This adds DT bindings for an AS3711 PMIC, used for supplying power to the +CPU, some peripherals and the backlight, as well as extends the cpu0 DT +node with OPPs and a reference to the PMIC to support the CPUFreq and +CPU DVFS functions. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 251ed17395a00a0af1e12b81ca655545eeef810d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/sh73a0-kzm9g-reference.dts | 86 ++++++++++++++++++++++++++++ + 1 file changed, 86 insertions(+) + +diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +index 5972abb5..b6f759e8 100644 +--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts ++++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +@@ -18,6 +18,19 @@ + model = "KZM-A9-GT"; + compatible = "renesas,kzm9g-reference", "renesas,sh73a0"; + ++ cpus { ++ cpu@0 { ++ cpu0-supply = <&vdd_dvfs>; ++ operating-points = < ++ /* kHz uV */ ++ 1196000 1315000 ++ 598000 1175000 ++ 398667 1065000 ++ >; ++ voltage-tolerance = <1>; /* 1% */ ++ }; ++ }; ++ + chosen { + bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200"; + }; +@@ -59,6 +72,79 @@ + }; + }; + ++&i2c0 { ++ as3711@40 { ++ compatible = "ams,as3711"; ++ reg = <0x40>; ++ ++ regulators { ++ vdd_dvfs: sd1 { ++ regulator-name = "1.315V CPU"; ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ sd2 { ++ regulator-name = "1.8V"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ sd4 { ++ regulator-name = "1.215V"; ++ regulator-min-microvolt = <1215000>; ++ regulator-max-microvolt = <1235000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ldo2 { ++ regulator-name = "2.8V CPU"; ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ldo3 { ++ regulator-name = "3.0V CPU"; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ldo4 { ++ regulator-name = "2.8V"; ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ldo5 { ++ regulator-name = "2.8V #2"; ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ldo7 { ++ regulator-name = "1.15V CPU"; ++ regulator-min-microvolt = <1150000>; ++ regulator-max-microvolt = <1150000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ldo8 { ++ regulator-name = "1.15V CPU #2"; ++ regulator-min-microvolt = <1150000>; ++ regulator-max-microvolt = <1150000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ }; ++ }; ++}; ++ + &mmcif { + bus-width = <8>; + vmmc-supply = <®_1p8v>; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0077-ARM-shmobile-marzen-reference-add-irqpin-support-in-.patch b/patches.renesas/0077-ARM-shmobile-marzen-reference-add-irqpin-support-in-.patch new file mode 100644 index 00000000000..9a31652512e --- /dev/null +++ b/patches.renesas/0077-ARM-shmobile-marzen-reference-add-irqpin-support-in-.patch @@ -0,0 +1,46 @@ +From 03c7e08219a4f3b3c078daabb3eefeaec492d944 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Wed, 3 Apr 2013 11:19:07 +0200 +Subject: ARM: shmobile: marzen-reference: add irqpin support in DT + +Add an irqpin interrupt controller DT node on marzen-reference. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 24603f3caf07f5f65aa17ed7851ad4741595cf6a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7779.dtsi | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi +index fe5c6f21..7f146c6b 100644 +--- a/arch/arm/boot/dts/r8a7779.dtsi ++++ b/arch/arm/boot/dts/r8a7779.dtsi +@@ -48,6 +48,23 @@ + <0xf0000100 0x100>; + }; + ++ irqpin0: irqpin@fe780010 { ++ compatible = "renesas,intc-irqpin"; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ reg = <0xfe78001c 4>, ++ <0xfe780010 4>, ++ <0xfe780024 4>, ++ <0xfe780044 4>, ++ <0xfe780064 4>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 27 0x4 ++ 0 28 0x4 ++ 0 29 0x4 ++ 0 30 0x4>; ++ sense-bitfield-width = <2>; ++ }; ++ + i2c0: i2c@0xffc70000 { + #address-cells = <1>; + #size-cells = <0>; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0078-ARM-shmobile-armadillo800eva-Fix-maximum-number-of-S.patch b/patches.renesas/0078-ARM-shmobile-armadillo800eva-Fix-maximum-number-of-S.patch new file mode 100644 index 00000000000..37822396177 --- /dev/null +++ b/patches.renesas/0078-ARM-shmobile-armadillo800eva-Fix-maximum-number-of-S.patch @@ -0,0 +1,31 @@ +From 3343c96b725040c0be8b1e9338da125865759547 Mon Sep 17 00:00:00 2001 +From: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> +Date: Mon, 15 Apr 2013 13:44:52 +0900 +Subject: ARM: shmobile: armadillo800eva: Fix maximum number of SCIF + +The r8a77740 has 9ch SCIF. It is not 8ch. + +Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 03e40cecc21c9b24d3911896755fde933fc52887) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/configs/armadillo800eva_defconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig +index 0f2d80da..fae939d3 100644 +--- a/arch/arm/configs/armadillo800eva_defconfig ++++ b/arch/arm/configs/armadillo800eva_defconfig +@@ -86,7 +86,7 @@ CONFIG_TOUCHSCREEN_ST1232=y + # CONFIG_SERIO is not set + # CONFIG_LEGACY_PTYS is not set + CONFIG_SERIAL_SH_SCI=y +-CONFIG_SERIAL_SH_SCI_NR_UARTS=8 ++CONFIG_SERIAL_SH_SCI_NR_UARTS=9 + CONFIG_SERIAL_SH_SCI_CONSOLE=y + # CONFIG_HW_RANDOM is not set + CONFIG_I2C=y +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0079-ARM-shmobile-bockw-enable-SDHI-on-defconfig.patch b/patches.renesas/0079-ARM-shmobile-bockw-enable-SDHI-on-defconfig.patch new file mode 100644 index 00000000000..4d9535df7fa --- /dev/null +++ b/patches.renesas/0079-ARM-shmobile-bockw-enable-SDHI-on-defconfig.patch @@ -0,0 +1,29 @@ +From ec4912f76275b927ca8be8c8ad27c6f114d8fc44 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 16 Apr 2013 22:18:11 -0700 +Subject: ARM: shmobile: bockw: enable SDHI on defconfig + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit f4b4ce8ed235d40240e1d446e612d96ab188b856) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/configs/bockw_defconfig | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm/configs/bockw_defconfig b/arch/arm/configs/bockw_defconfig +index 6524cdf3..b74a4d43 100644 +--- a/arch/arm/configs/bockw_defconfig ++++ b/arch/arm/configs/bockw_defconfig +@@ -72,6 +72,8 @@ CONFIG_SERIAL_SH_SCI_CONSOLE=y + # CONFIG_HW_RANDOM is not set + # CONFIG_HWMON is not set + # CONFIG_USB_SUPPORT is not set ++CONFIG_MMC=y ++CONFIG_MMC_SDHI=y + CONFIG_UIO=y + CONFIG_UIO_PDRV_GENIRQ=y + # CONFIG_IOMMU_SUPPORT is not set +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0080-ARM-shmobile-add-GPIO-IRQ-macro.patch b/patches.renesas/0080-ARM-shmobile-add-GPIO-IRQ-macro.patch new file mode 100644 index 00000000000..6b7d892f32b --- /dev/null +++ b/patches.renesas/0080-ARM-shmobile-add-GPIO-IRQ-macro.patch @@ -0,0 +1,35 @@ +From ba3f0a0b9d8c188cad4252229e3768a3f403636d Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 17 Apr 2013 23:41:30 -0700 +Subject: ARM: shmobile: add GPIO IRQ macro + +R-Car series gpio_rcar driver can control GPIO IRQ today. +It needs base IRQ number for gpio_rcar_config :: .irq_base +This patch adds macro for GPIO IRQ. +This patch was tested on Bock-W board + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 9904319d4f6f4fe0be84c98d73a9a2174d3893c9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/include/mach/irqs.h | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h +index b2074e2a..d241bfd6 100644 +--- a/arch/arm/mach-shmobile/include/mach/irqs.h ++++ b/arch/arm/mach-shmobile/include/mach/irqs.h +@@ -16,4 +16,9 @@ + #define IRQPIN_BASE 2000 + #define irq_pin(nr) ((nr) + IRQPIN_BASE) + ++/* GPIO IRQ */ ++#define _GPIO_IRQ_BASE 2500 ++#define GPIO_IRQ_BASE(x) (_GPIO_IRQ_BASE + (32 * x)) ++#define GPIO_IRQ(x, y) (_GPIO_IRQ_BASE + (32 * x) + y) ++ + #endif /* __ASM_MACH_IRQS_H */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0081-ARM-shmobile-r8a7778-Register-PFC-device.patch b/patches.renesas/0081-ARM-shmobile-r8a7778-Register-PFC-device.patch new file mode 100644 index 00000000000..d2419b81d43 --- /dev/null +++ b/patches.renesas/0081-ARM-shmobile-r8a7778-Register-PFC-device.patch @@ -0,0 +1,66 @@ +From 5e2f0119bcd946fe100e8216f4a961e8ede87269 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Fri, 12 Apr 2013 05:37:50 +0000 +Subject: ARM: shmobile: r8a7778: Register PFC device + +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 369b00bbe51e128a201af58a4daabb01253f126e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/Kconfig | 1 + + arch/arm/mach-shmobile/include/mach/r8a7778.h | 1 + + arch/arm/mach-shmobile/setup-r8a7778.c | 13 +++++++++++++ + 3 files changed, 15 insertions(+) + +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index c6fb9ec8..638e5c57 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -37,6 +37,7 @@ config ARCH_R8A7740 + + config ARCH_R8A7778 + bool "R-Car M1 (R8A77780)" ++ select ARCH_WANT_OPTIONAL_GPIOLIB + select CPU_V7 + select SH_CLK_CPG + select ARM_GIC +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h +index 951149e6..68053fc4 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h +@@ -28,5 +28,6 @@ extern void r8a7778_init_irq(void); + extern void r8a7778_init_irq_dt(void); + extern void r8a7778_clock_init(void); + extern void r8a7778_init_irq_extpin(int irlm); ++extern void r8a7778_pinmux_init(void); + + #endif /* __ASM_R8A7778_H__ */ +diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c +index 30b4a336..0ca57010 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7778.c ++++ b/arch/arm/mach-shmobile/setup-r8a7778.c +@@ -94,6 +94,19 @@ static struct resource ether_resources[] = { + &sh_tmu##idx##_platform_data, \ + sizeof(sh_tmu##idx##_platform_data)) + ++/* PFC */ ++static struct resource pfc_resources[] = { ++ DEFINE_RES_MEM(0xfffc0000, 0x118), ++}; ++ ++void __init r8a7778_pinmux_init(void) ++{ ++ platform_device_register_simple( ++ "pfc-r8a7778", -1, ++ pfc_resources, ++ ARRAY_SIZE(pfc_resources)); ++} ++ + void __init r8a7778_add_standard_devices(void) + { + int i; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0082-sh-pfc-Initial-r8a7790-PFC-support.patch b/patches.renesas/0082-sh-pfc-Initial-r8a7790-PFC-support.patch new file mode 100644 index 00000000000..254ea413a9d --- /dev/null +++ b/patches.renesas/0082-sh-pfc-Initial-r8a7790-PFC-support.patch @@ -0,0 +1,3725 @@ +From a88db333f27b1849158afb9f9d061bd051ba837c Mon Sep 17 00:00:00 2001 +From: Koji Matsuoka <koji.matsuoka.xm@rms.renesas.com> +Date: Mon, 8 Apr 2013 11:08:53 +0900 +Subject: sh-pfc: Initial r8a7790 PFC support + +Add initial PFC support for the r8a7790 SoC. + +At this point only GPIO interface is supported, move to +newer interfaces planned as incremental changes. + +Original authors is Koji Matsuoka-san, thanks for him +and his team for the heavy lifting. Adjusted by Magnus +to work together with updated code in drivers/pinctrl. + +Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@rms.renesas.com> +Signed-off-by: Magnus Damm <damm@opensource.se> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 58c229e18b7754dfe505f3bc1688feb28c84f42a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/include/mach/r8a7790.h | 383 +++ + drivers/pinctrl/sh-pfc/Kconfig | 5 + + drivers/pinctrl/sh-pfc/Makefile | 1 + + drivers/pinctrl/sh-pfc/core.c | 3 + + drivers/pinctrl/sh-pfc/core.h | 1 + + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 3238 +++++++++++++++++++++++++ + 6 files changed, 3631 insertions(+) + create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a7790.c + +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h +index 2e919e61..e01ac4e3 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7790.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h +@@ -1,6 +1,389 @@ + #ifndef __ASM_R8A7790_H__ + #define __ASM_R8A7790_H__ + ++/* Pin Function Controller: ++ * GPIO_FN_xx - GPIO used to select pin function ++ * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU ++ */ ++enum { ++ GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3, ++ GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7, ++ GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11, ++ GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15, ++ GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19, ++ GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23, ++ GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27, ++ GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31, ++ ++ GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3, ++ GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7, ++ GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11, ++ GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15, ++ GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19, ++ GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23, ++ GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27, ++ GPIO_GP_1_28, GPIO_GP_1_29, ++ ++ GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3, ++ GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7, ++ GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11, ++ GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15, ++ GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19, ++ GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23, ++ GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27, ++ GPIO_GP_2_28, GPIO_GP_2_29, ++ ++ GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3, ++ GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7, ++ GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11, ++ GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15, ++ GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19, ++ GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23, ++ GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27, ++ GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31, ++ ++ GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3, ++ GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7, ++ GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11, ++ GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15, ++ GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19, ++ GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23, ++ GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27, ++ GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31, ++ ++ GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3, ++ GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7, ++ GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11, ++ GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15, ++ GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19, ++ GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23, ++ GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27, ++ GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31, ++ ++ GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC_VBUS, ++ GPIO_FN_USB2_PWEN, GPIO_FN_USB2_OVC, GPIO_FN_AVS1, GPIO_FN_AVS2, ++ GPIO_FN_DU_DOTCLKIN0, GPIO_FN_DU_DOTCLKIN2, ++ ++ /* IPSR0 */ ++ GPIO_FN_D1, GPIO_FN_MSIOF3_SYNC_B, GPIO_FN_VI3_DATA1, GPIO_FN_VI0_G5, ++ GPIO_FN_VI0_G5_B, GPIO_FN_D2, GPIO_FN_MSIOF3_RXD_B, GPIO_FN_VI3_DATA2, ++ GPIO_FN_VI0_G6, GPIO_FN_VI0_G6_B, GPIO_FN_D3, GPIO_FN_MSIOF3_TXD_B, ++ GPIO_FN_VI3_DATA3, GPIO_FN_VI0_G7, GPIO_FN_VI0_G7_B, GPIO_FN_D4, ++ GPIO_FN_SCIFB1_RXD_F, GPIO_FN_SCIFB0_RXD_C, GPIO_FN_VI3_DATA4, ++ GPIO_FN_VI0_R0, GPIO_FN_VI0_R0_B, GPIO_FN_RX0_B, GPIO_FN_D5, ++ GPIO_FN_SCIFB1_TXD_F, GPIO_FN_SCIFB0_TXD_C, GPIO_FN_VI3_DATA5, ++ GPIO_FN_VI0_R1, GPIO_FN_VI0_R1_B, GPIO_FN_TX0_B, GPIO_FN_D6, ++ GPIO_FN_SCL2_C, GPIO_FN_VI3_DATA6, GPIO_FN_VI0_R2, GPIO_FN_VI0_R2_B, ++ GPIO_FN_SCL2_CIS_C, GPIO_FN_D7, GPIO_FN_AD_DI_B, GPIO_FN_SDA2_C, ++ GPIO_FN_VI3_DATA7, GPIO_FN_VI0_R3, GPIO_FN_VI0_R3_B, GPIO_FN_SDA2_CIS_C, ++ GPIO_FN_D8, GPIO_FN_SCIFA1_SCK_C, GPIO_FN_AVB_TXD0, GPIO_FN_MII_TXD0, ++ GPIO_FN_VI0_G0, GPIO_FN_VI0_G0_B, GPIO_FN_VI2_DATA0_VI2_B0, ++ ++ /* IPSR1 */ ++ GPIO_FN_D9, GPIO_FN_SCIFA1_RXD_C, GPIO_FN_AVB_TXD1, GPIO_FN_MII_TXD1, ++ GPIO_FN_VI0_G1, GPIO_FN_VI0_G1_B, GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_D10, ++ GPIO_FN_SCIFA1_TXD_C, GPIO_FN_AVB_TXD2, GPIO_FN_MII_TXD2, ++ GPIO_FN_VI0_G2, GPIO_FN_VI0_G2_B, GPIO_FN_VI2_DATA2_VI2_B2, GPIO_FN_D11, ++ GPIO_FN_SCIFA1_CTS_N_C, GPIO_FN_AVB_TXD3, GPIO_FN_MII_TXD3, ++ GPIO_FN_VI0_G3, GPIO_FN_VI0_G3_B, GPIO_FN_VI2_DATA3_VI2_B3, ++ GPIO_FN_D12, GPIO_FN_SCIFA1_RTS_N_C, GPIO_FN_AVB_TXD4, ++ GPIO_FN_VI0_HSYNC_N, GPIO_FN_VI0_HSYNC_N_B, GPIO_FN_VI2_DATA4_VI2_B4, ++ GPIO_FN_D13, GPIO_FN_AVB_TXD5, GPIO_FN_VI0_VSYNC_N, ++ GPIO_FN_VI0_VSYNC_N_B, GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_D14, ++ GPIO_FN_SCIFB1_RXD_C, GPIO_FN_AVB_TXD6, GPIO_FN_RX1_B, ++ GPIO_FN_VI0_CLKENB, GPIO_FN_VI0_CLKENB_B, GPIO_FN_VI2_DATA6_VI2_B6, ++ GPIO_FN_D15, GPIO_FN_SCIFB1_TXD_C, GPIO_FN_AVB_TXD7, GPIO_FN_TX1_B, ++ GPIO_FN_VI0_FIELD, GPIO_FN_VI0_FIELD_B, GPIO_FN_VI2_DATA7_VI2_B7, ++ GPIO_FN_A0, GPIO_FN_PWM3, GPIO_FN_A1, GPIO_FN_PWM4, ++ ++ /* IPSR2 */ ++ GPIO_FN_A2, GPIO_FN_PWM5, GPIO_FN_MSIOF1_SS1_B, GPIO_FN_A3, ++ GPIO_FN_PWM6, GPIO_FN_MSIOF1_SS2_B, GPIO_FN_A4, GPIO_FN_MSIOF1_TXD_B, ++ GPIO_FN_TPU0TO0, GPIO_FN_A5, GPIO_FN_SCIFA1_TXD_B, GPIO_FN_TPU0TO1, ++ GPIO_FN_A6, GPIO_FN_SCIFA1_RTS_N_B, GPIO_FN_TPU0TO2, GPIO_FN_A7, ++ GPIO_FN_SCIFA1_SCK_B, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_TPU0TO3, ++ GPIO_FN_A8, GPIO_FN_SCIFA1_RXD_B, GPIO_FN_SSI_SCK5_B, GPIO_FN_VI0_R4, ++ GPIO_FN_VI0_R4_B, GPIO_FN_SCIFB2_RXD_C, GPIO_FN_VI2_DATA0_VI2_B0_B, ++ GPIO_FN_A9, GPIO_FN_SCIFA1_CTS_N_B, GPIO_FN_SSI_WS5_B, GPIO_FN_VI0_R5, ++ GPIO_FN_VI0_R5_B, GPIO_FN_SCIFB2_TXD_C, GPIO_FN_VI2_DATA1_VI2_B1_B, ++ GPIO_FN_A10, GPIO_FN_SSI_SDATA5_B, GPIO_FN_MSIOF2_SYNC, GPIO_FN_VI0_R6, ++ GPIO_FN_VI0_R6_B, GPIO_FN_VI2_DATA2_VI2_B2_B, ++ ++ /* IPSR3 */ ++ GPIO_FN_A11, GPIO_FN_SCIFB2_CTS_N_B, GPIO_FN_MSIOF2_SCK, GPIO_FN_VI1_R0, ++ GPIO_FN_VI1_R0_B, GPIO_FN_VI2_G0, GPIO_FN_VI2_DATA3_VI2_B3_B, ++ GPIO_FN_A12, GPIO_FN_SCIFB2_RXD_B, GPIO_FN_MSIOF2_TXD, GPIO_FN_VI1_R1, ++ GPIO_FN_VI1_R1_B, GPIO_FN_VI2_G1, GPIO_FN_VI2_DATA4_VI2_B4_B, ++ GPIO_FN_A13, GPIO_FN_SCIFB2_RTS_N_B, GPIO_FN_EX_WAIT2, ++ GPIO_FN_MSIOF2_RXD, GPIO_FN_VI1_R2, GPIO_FN_VI1_R2_B, GPIO_FN_VI2_G2, ++ GPIO_FN_VI2_DATA5_VI2_B5_B, GPIO_FN_A14, GPIO_FN_SCIFB2_TXD_B, ++ GPIO_FN_ATACS11_N, GPIO_FN_MSIOF2_SS1, GPIO_FN_A15, ++ GPIO_FN_SCIFB2_SCK_B, GPIO_FN_ATARD1_N, GPIO_FN_MSIOF2_SS2, GPIO_FN_A16, ++ GPIO_FN_ATAWR1_N, GPIO_FN_A17, GPIO_FN_AD_DO_B, GPIO_FN_ATADIR1_N, ++ GPIO_FN_A18, GPIO_FN_AD_CLK_B, GPIO_FN_ATAG1_N, GPIO_FN_A19, ++ GPIO_FN_AD_NCS_N_B, GPIO_FN_ATACS01_N, GPIO_FN_EX_WAIT0_B, GPIO_FN_A20, ++ GPIO_FN_SPCLK, GPIO_FN_VI1_R3, GPIO_FN_VI1_R3_B, GPIO_FN_VI2_G4, ++ ++ /* IPSR4 */ ++ GPIO_FN_A21, GPIO_FN_MOSI_IO0, GPIO_FN_VI1_R4, GPIO_FN_VI1_R4_B, ++ GPIO_FN_VI2_G5, GPIO_FN_A22, GPIO_FN_MISO_IO1, GPIO_FN_VI1_R5, ++ GPIO_FN_VI1_R5_B, GPIO_FN_VI2_G6, GPIO_FN_A23, GPIO_FN_IO2, ++ GPIO_FN_VI1_G7, GPIO_FN_VI1_G7_B, GPIO_FN_VI2_G7, GPIO_FN_A24, ++ GPIO_FN_IO3, GPIO_FN_VI1_R7, GPIO_FN_VI1_R7_B, GPIO_FN_VI2_CLKENB, ++ GPIO_FN_VI2_CLKENB_B, GPIO_FN_A25, GPIO_FN_SSL, GPIO_FN_VI1_G6, ++ GPIO_FN_VI1_G6_B, GPIO_FN_VI2_FIELD, GPIO_FN_VI2_FIELD_B, GPIO_FN_CS0_N, ++ GPIO_FN_VI1_R6, GPIO_FN_VI1_R6_B, GPIO_FN_VI2_G3, GPIO_FN_MSIOF0_SS2_B, ++ GPIO_FN_CS1_N_A26, GPIO_FN_SPEEDIN, GPIO_FN_VI0_R7, GPIO_FN_VI0_R7_B, ++ GPIO_FN_VI2_CLK, GPIO_FN_VI2_CLK_B, GPIO_FN_EX_CS0_N, GPIO_FN_HRX1_B, ++ GPIO_FN_VI1_G5, GPIO_FN_VI1_G5_B, GPIO_FN_VI2_R0, GPIO_FN_HTX0_B, ++ GPIO_FN_MSIOF0_SS1_B, GPIO_FN_EX_CS1_N, GPIO_FN_GPS_CLK, ++ GPIO_FN_HCTS1_N_B, GPIO_FN_VI1_FIELD, GPIO_FN_VI1_FIELD_B, ++ GPIO_FN_VI2_R1, GPIO_FN_EX_CS2_N, GPIO_FN_GPS_SIGN, GPIO_FN_HRTS1_N_B, ++ GPIO_FN_VI3_CLKENB, GPIO_FN_VI1_G0, GPIO_FN_VI1_G0_B, GPIO_FN_VI2_R2, ++ ++ /* IPSR5 */ ++ GPIO_FN_EX_CS3_N, GPIO_FN_GPS_MAG, GPIO_FN_VI3_FIELD, GPIO_FN_VI1_G1, ++ GPIO_FN_VI1_G1_B, GPIO_FN_VI2_R3, GPIO_FN_EX_CS4_N, ++ GPIO_FN_MSIOF1_SCK_B, GPIO_FN_VI3_HSYNC_N, ++ GPIO_FN_VI2_HSYNC_N, GPIO_FN_SCL1, GPIO_FN_VI2_HSYNC_N_B, ++ GPIO_FN_INTC_EN0_N, GPIO_FN_SCL1_CIS, GPIO_FN_EX_CS5_N, GPIO_FN_CAN0_RX, ++ GPIO_FN_MSIOF1_RXD_B, GPIO_FN_VI3_VSYNC_N, GPIO_FN_VI1_G2, ++ GPIO_FN_VI1_G2_B, GPIO_FN_VI2_R4, GPIO_FN_SDA1, GPIO_FN_INTC_EN1_N, ++ GPIO_FN_SDA1_CIS, GPIO_FN_BS_N, GPIO_FN_IETX, GPIO_FN_HTX1_B, ++ GPIO_FN_CAN1_TX, GPIO_FN_DRACK0, GPIO_FN_IETX_C, GPIO_FN_RD_N, ++ GPIO_FN_CAN0_TX, GPIO_FN_SCIFA0_SCK_B, GPIO_FN_RD_WR_N, GPIO_FN_VI1_G3, ++ GPIO_FN_VI1_G3_B, GPIO_FN_VI2_R5, GPIO_FN_SCIFA0_RXD_B, ++ GPIO_FN_INTC_IRQ4_N, GPIO_FN_WE0_N, GPIO_FN_IECLK, GPIO_FN_CAN_CLK, ++ GPIO_FN_VI2_VSYNC_N, GPIO_FN_SCIFA0_TXD_B, GPIO_FN_VI2_VSYNC_N_B, ++ GPIO_FN_WE1_N, GPIO_FN_IERX, GPIO_FN_CAN1_RX, GPIO_FN_VI1_G4, ++ GPIO_FN_VI1_G4_B, GPIO_FN_VI2_R6, GPIO_FN_SCIFA0_CTS_N_B, ++ GPIO_FN_IERX_C, GPIO_FN_EX_WAIT0, GPIO_FN_IRQ3, GPIO_FN_INTC_IRQ3_N, ++ GPIO_FN_VI3_CLK, GPIO_FN_SCIFA0_RTS_N_B, GPIO_FN_HRX0_B, ++ GPIO_FN_MSIOF0_SCK_B, GPIO_FN_DREQ0_N, GPIO_FN_VI1_HSYNC_N, ++ GPIO_FN_VI1_HSYNC_N_B, GPIO_FN_VI2_R7, GPIO_FN_SSI_SCK78_C, ++ GPIO_FN_SSI_WS78_B, ++ ++ /* IPSR6 */ ++ GPIO_FN_DACK0, GPIO_FN_IRQ0, GPIO_FN_INTC_IRQ0_N, GPIO_FN_SSI_SCK6_B, ++ GPIO_FN_VI1_VSYNC_N, GPIO_FN_VI1_VSYNC_N_B, GPIO_FN_SSI_WS78_C, ++ GPIO_FN_DREQ1_N, GPIO_FN_VI1_CLKENB, GPIO_FN_VI1_CLKENB_B, ++ GPIO_FN_SSI_SDATA7_C, GPIO_FN_SSI_SCK78_B, GPIO_FN_DACK1, GPIO_FN_IRQ1, ++ GPIO_FN_INTC_IRQ1_N, GPIO_FN_SSI_WS6_B, GPIO_FN_SSI_SDATA8_C, ++ GPIO_FN_DREQ2_N, GPIO_FN_HSCK1_B, GPIO_FN_HCTS0_N_B, ++ GPIO_FN_MSIOF0_TXD_B, GPIO_FN_DACK2, GPIO_FN_IRQ2, GPIO_FN_INTC_IRQ2_N, ++ GPIO_FN_SSI_SDATA6_B, GPIO_FN_HRTS0_N_B, GPIO_FN_MSIOF0_RXD_B, ++ GPIO_FN_ETH_CRS_DV, GPIO_FN_RMII_CRS_DV, GPIO_FN_STP_ISCLK_0_B, ++ GPIO_FN_TS_SDEN0_D, GPIO_FN_GLO_Q0_C, GPIO_FN_SCL2_E, ++ GPIO_FN_SCL2_CIS_E, GPIO_FN_ETH_RX_ER, GPIO_FN_RMII_RX_ER, ++ GPIO_FN_STP_ISD_0_B, GPIO_FN_TS_SPSYNC0_D, GPIO_FN_GLO_Q1_C, ++ GPIO_FN_SDA2_E, GPIO_FN_SDA2_CIS_E, GPIO_FN_ETH_RXD0, GPIO_FN_RMII_RXD0, ++ GPIO_FN_STP_ISEN_0_B, GPIO_FN_TS_SDAT0_D, GPIO_FN_GLO_I0_C, ++ GPIO_FN_SCIFB1_SCK_G, GPIO_FN_SCK1_E, GPIO_FN_ETH_RXD1, ++ GPIO_FN_RMII_RXD1, GPIO_FN_HRX0_E, GPIO_FN_STP_ISSYNC_0_B, ++ GPIO_FN_TS_SCK0_D, GPIO_FN_GLO_I1_C, GPIO_FN_SCIFB1_RXD_G, ++ GPIO_FN_RX1_E, GPIO_FN_ETH_LINK, GPIO_FN_RMII_LINK, GPIO_FN_HTX0_E, ++ GPIO_FN_STP_IVCXO27_0_B, GPIO_FN_SCIFB1_TXD_G, GPIO_FN_TX1_E, ++ GPIO_FN_ETH_REF_CLK, GPIO_FN_RMII_REF_CLK, GPIO_FN_HCTS0_N_E, ++ GPIO_FN_STP_IVCXO27_1_B, GPIO_FN_HRX0_F, ++ ++ /* IPSR7 */ ++ GPIO_FN_ETH_MDIO, GPIO_FN_RMII_MDIO, GPIO_FN_HRTS0_N_E, ++ GPIO_FN_SIM0_D_C, GPIO_FN_HCTS0_N_F, GPIO_FN_ETH_TXD1, ++ GPIO_FN_RMII_TXD1, GPIO_FN_HTX0_F, GPIO_FN_BPFCLK_G, GPIO_FN_RDS_CLK_F, ++ GPIO_FN_ETH_TX_EN, GPIO_FN_RMII_TX_EN, GPIO_FN_SIM0_CLK_C, ++ GPIO_FN_HRTS0_N_F, GPIO_FN_ETH_MAGIC, GPIO_FN_RMII_MAGIC, ++ GPIO_FN_SIM0_RST_C, GPIO_FN_ETH_TXD0, GPIO_FN_RMII_TXD0, ++ GPIO_FN_STP_ISCLK_1_B, GPIO_FN_TS_SDEN1_C, GPIO_FN_GLO_SCLK_C, ++ GPIO_FN_ETH_MDC, GPIO_FN_RMII_MDC, GPIO_FN_STP_ISD_1_B, ++ GPIO_FN_TS_SPSYNC1_C, GPIO_FN_GLO_SDATA_C, GPIO_FN_PWM0, ++ GPIO_FN_SCIFA2_SCK_C, GPIO_FN_STP_ISEN_1_B, GPIO_FN_TS_SDAT1_C, ++ GPIO_FN_GLO_SS_C, GPIO_FN_PWM1, GPIO_FN_SCIFA2_TXD_C, ++ GPIO_FN_STP_ISSYNC_1_B, GPIO_FN_TS_SCK1_C, GPIO_FN_GLO_RFON_C, ++ GPIO_FN_PCMOE_N, GPIO_FN_PWM2, GPIO_FN_PWMFSW0, GPIO_FN_SCIFA2_RXD_C, ++ GPIO_FN_PCMWE_N, GPIO_FN_IECLK_C, GPIO_FN_DU1_DOTCLKIN, ++ GPIO_FN_AUDIO_CLKC, GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_VI0_CLK, ++ GPIO_FN_ATACS00_N, GPIO_FN_AVB_RXD1, GPIO_FN_MII_RXD1, ++ GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_ATACS10_N, GPIO_FN_AVB_RXD2, ++ GPIO_FN_MII_RXD2, ++ ++ /* IPSR8 */ ++ GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_ATARD0_N, GPIO_FN_AVB_RXD3, ++ GPIO_FN_MII_RXD3, GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_ATAWR0_N, ++ GPIO_FN_AVB_RXD4, GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_ATADIR0_N, ++ GPIO_FN_AVB_RXD5, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_ATAG0_N, ++ GPIO_FN_AVB_RXD6, GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_EX_WAIT1, ++ GPIO_FN_AVB_RXD7, GPIO_FN_VI0_DATA6_VI0_B6, GPIO_FN_AVB_RX_ER, ++ GPIO_FN_MII_RX_ER, GPIO_FN_VI0_DATA7_VI0_B7, GPIO_FN_AVB_RX_CLK, ++ GPIO_FN_MII_RX_CLK, GPIO_FN_VI1_CLK, GPIO_FN_AVB_RX_DV, ++ GPIO_FN_MII_RX_DV, GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SCIFA1_SCK_D, ++ GPIO_FN_AVB_CRS, GPIO_FN_MII_CRS, GPIO_FN_VI1_DATA1_VI1_B1, ++ GPIO_FN_SCIFA1_RXD_D, GPIO_FN_AVB_MDC, GPIO_FN_MII_MDC, ++ GPIO_FN_VI1_DATA2_VI1_B2, GPIO_FN_SCIFA1_TXD_D, GPIO_FN_AVB_MDIO, ++ GPIO_FN_MII_MDIO, GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_SCIFA1_CTS_N_D, ++ GPIO_FN_AVB_GTX_CLK, GPIO_FN_VI1_DATA4_VI1_B4, GPIO_FN_SCIFA1_RTS_N_D, ++ GPIO_FN_AVB_MAGIC, GPIO_FN_MII_MAGIC, GPIO_FN_VI1_DATA5_VI1_B5, ++ GPIO_FN_AVB_PHY_INT, GPIO_FN_VI1_DATA6_VI1_B6, GPIO_FN_AVB_GTXREFCLK, ++ GPIO_FN_SD0_CLK, GPIO_FN_VI1_DATA0_VI1_B0_B, GPIO_FN_SD0_CMD, ++ GPIO_FN_SCIFB1_SCK_B, GPIO_FN_VI1_DATA1_VI1_B1_B, ++ ++ /* IPSR9 */ ++ GPIO_FN_SD0_DAT0, GPIO_FN_SCIFB1_RXD_B, GPIO_FN_VI1_DATA2_VI1_B2_B, ++ GPIO_FN_SD0_DAT1, GPIO_FN_SCIFB1_TXD_B, GPIO_FN_VI1_DATA3_VI1_B3_B, ++ GPIO_FN_SD0_DAT2, GPIO_FN_SCIFB1_CTS_N_B, GPIO_FN_VI1_DATA4_VI1_B4_B, ++ GPIO_FN_SD0_DAT3, GPIO_FN_SCIFB1_RTS_N_B, GPIO_FN_VI1_DATA5_VI1_B5_B, ++ GPIO_FN_SD0_CD, GPIO_FN_MMC0_D6, GPIO_FN_TS_SDEN0_B, GPIO_FN_USB0_EXTP, ++ GPIO_FN_GLO_SCLK, GPIO_FN_VI1_DATA6_VI1_B6_B, GPIO_FN_SCL1_B, ++ GPIO_FN_SCL1_CIS_B, GPIO_FN_VI2_DATA6_VI2_B6_B, GPIO_FN_SD0_WP, ++ GPIO_FN_MMC0_D7, GPIO_FN_TS_SPSYNC0_B, GPIO_FN_USB0_IDIN, ++ GPIO_FN_GLO_SDATA, GPIO_FN_VI1_DATA7_VI1_B7_B, GPIO_FN_SDA1_B, ++ GPIO_FN_SDA1_CIS_B, GPIO_FN_VI2_DATA7_VI2_B7_B, GPIO_FN_SD1_CLK, ++ GPIO_FN_AVB_TX_EN, GPIO_FN_MII_TX_EN, GPIO_FN_SD1_CMD, ++ GPIO_FN_AVB_TX_ER, GPIO_FN_MII_TX_ER, GPIO_FN_SCIFB0_SCK_B, ++ GPIO_FN_SD1_DAT0, GPIO_FN_AVB_TX_CLK, GPIO_FN_MII_TX_CLK, ++ GPIO_FN_SCIFB0_RXD_B, GPIO_FN_SD1_DAT1, GPIO_FN_AVB_LINK, ++ GPIO_FN_MII_LINK, GPIO_FN_SCIFB0_TXD_B, GPIO_FN_SD1_DAT2, ++ GPIO_FN_AVB_COL, GPIO_FN_MII_COL, GPIO_FN_SCIFB0_CTS_N_B, ++ GPIO_FN_SD1_DAT3, GPIO_FN_AVB_RXD0, GPIO_FN_MII_RXD0, ++ GPIO_FN_SCIFB0_RTS_N_B, GPIO_FN_SD1_CD, GPIO_FN_MMC1_D6, ++ GPIO_FN_TS_SDEN1, GPIO_FN_USB1_EXTP, GPIO_FN_GLO_SS, GPIO_FN_VI0_CLK_B, ++ GPIO_FN_SCL2_D, GPIO_FN_SCL2_CIS_D, GPIO_FN_SIM0_CLK_B, ++ GPIO_FN_VI3_CLK_B, ++ ++ /* IPSR10 */ ++ GPIO_FN_SD1_WP, GPIO_FN_MMC1_D7, GPIO_FN_TS_SPSYNC1, GPIO_FN_USB1_IDIN, ++ GPIO_FN_GLO_RFON, GPIO_FN_VI1_CLK_B, GPIO_FN_SDA2_D, GPIO_FN_SDA2_CIS_D, ++ GPIO_FN_SIM0_D_B, GPIO_FN_SD2_CLK, GPIO_FN_MMC0_CLK, GPIO_FN_SIM0_CLK, ++ GPIO_FN_VI0_DATA0_VI0_B0_B, GPIO_FN_TS_SDEN0_C, GPIO_FN_GLO_SCLK_B, ++ GPIO_FN_VI3_DATA0_B, GPIO_FN_SD2_CMD, GPIO_FN_MMC0_CMD, GPIO_FN_SIM0_D, ++ GPIO_FN_VI0_DATA1_VI0_B1_B, GPIO_FN_SCIFB1_SCK_E, GPIO_FN_SCK1_D, ++ GPIO_FN_TS_SPSYNC0_C, GPIO_FN_GLO_SDATA_B, GPIO_FN_VI3_DATA1_B, ++ GPIO_FN_SD2_DAT0, GPIO_FN_MMC0_D0, GPIO_FN_FMCLK_B, ++ GPIO_FN_VI0_DATA2_VI0_B2_B, GPIO_FN_SCIFB1_RXD_E, GPIO_FN_RX1_D, ++ GPIO_FN_TS_SDAT0_C, GPIO_FN_GLO_SS_B, GPIO_FN_VI3_DATA2_B, ++ GPIO_FN_SD2_DAT1, GPIO_FN_MMC0_D1, GPIO_FN_FMIN_B, GPIO_FN_RDS_DATA, ++ GPIO_FN_VI0_DATA3_VI0_B3_B, GPIO_FN_SCIFB1_TXD_E, GPIO_FN_TX1_D, ++ GPIO_FN_TS_SCK0_C, GPIO_FN_GLO_RFON_B, GPIO_FN_VI3_DATA3_B, ++ GPIO_FN_SD2_DAT2, GPIO_FN_MMC0_D2, GPIO_FN_BPFCLK_B, GPIO_FN_RDS_CLK, ++ GPIO_FN_VI0_DATA4_VI0_B4_B, GPIO_FN_HRX0_D, GPIO_FN_TS_SDEN1_B, ++ GPIO_FN_GLO_Q0_B, GPIO_FN_VI3_DATA4_B, GPIO_FN_SD2_DAT3, ++ GPIO_FN_MMC0_D3, GPIO_FN_SIM0_RST, GPIO_FN_VI0_DATA5_VI0_B5_B, ++ GPIO_FN_HTX0_D, GPIO_FN_TS_SPSYNC1_B, GPIO_FN_GLO_Q1_B, ++ GPIO_FN_VI3_DATA5_B, GPIO_FN_SD2_CD, GPIO_FN_MMC0_D4, ++ GPIO_FN_TS_SDAT0_B, GPIO_FN_USB2_EXTP, GPIO_FN_GLO_I0, ++ GPIO_FN_VI0_DATA6_VI0_B6_B, GPIO_FN_HCTS0_N_D, GPIO_FN_TS_SDAT1_B, ++ GPIO_FN_GLO_I0_B, GPIO_FN_VI3_DATA6_B, ++ ++ /* IPSR11 */ ++ GPIO_FN_SD2_WP, GPIO_FN_MMC0_D5, GPIO_FN_TS_SCK0_B, GPIO_FN_USB2_IDIN, ++ GPIO_FN_GLO_I1, GPIO_FN_VI0_DATA7_VI0_B7_B, GPIO_FN_HRTS0_N_D, ++ GPIO_FN_TS_SCK1_B, GPIO_FN_GLO_I1_B, GPIO_FN_VI3_DATA7_B, ++ GPIO_FN_SD3_CLK, GPIO_FN_MMC1_CLK, GPIO_FN_SD3_CMD, GPIO_FN_MMC1_CMD, ++ GPIO_FN_MTS_N, GPIO_FN_SD3_DAT0, GPIO_FN_MMC1_D0, GPIO_FN_STM_N, ++ GPIO_FN_SD3_DAT1, GPIO_FN_MMC1_D1, GPIO_FN_MDATA, GPIO_FN_SD3_DAT2, ++ GPIO_FN_MMC1_D2, GPIO_FN_SDATA, GPIO_FN_SD3_DAT3, GPIO_FN_MMC1_D3, ++ GPIO_FN_SCKZ, GPIO_FN_SD3_CD, GPIO_FN_MMC1_D4, GPIO_FN_TS_SDAT1, ++ GPIO_FN_VSP, GPIO_FN_GLO_Q0, GPIO_FN_SIM0_RST_B, GPIO_FN_SD3_WP, ++ GPIO_FN_MMC1_D5, GPIO_FN_TS_SCK1, GPIO_FN_GLO_Q1, GPIO_FN_FMIN_C, ++ GPIO_FN_RDS_DATA_B, GPIO_FN_FMIN_E, GPIO_FN_RDS_DATA_D, GPIO_FN_FMIN_F, ++ GPIO_FN_RDS_DATA_E, GPIO_FN_MLB_CLK, GPIO_FN_SCL2_B, GPIO_FN_SCL2_CIS_B, ++ GPIO_FN_MLB_SIG, GPIO_FN_SCIFB1_RXD_D, GPIO_FN_RX1_C, GPIO_FN_SDA2_B, ++ GPIO_FN_SDA2_CIS_B, GPIO_FN_MLB_DAT, GPIO_FN_SPV_EVEN, ++ GPIO_FN_SCIFB1_TXD_D, GPIO_FN_TX1_C, GPIO_FN_BPFCLK_C, ++ GPIO_FN_RDS_CLK_B, GPIO_FN_SSI_SCK0129, GPIO_FN_CAN_CLK_B, ++ GPIO_FN_MOUT0, ++ ++ /* IPSR12 */ ++ GPIO_FN_SSI_WS0129, GPIO_FN_CAN0_TX_B, GPIO_FN_MOUT1, ++ GPIO_FN_SSI_SDATA0, GPIO_FN_CAN0_RX_B, GPIO_FN_MOUT2, ++ GPIO_FN_SSI_SDATA1, GPIO_FN_CAN1_TX_B, GPIO_FN_MOUT5, ++ GPIO_FN_SSI_SDATA2, GPIO_FN_CAN1_RX_B, GPIO_FN_SSI_SCK1, GPIO_FN_MOUT6, ++ GPIO_FN_SSI_SCK34, GPIO_FN_STP_OPWM_0, GPIO_FN_SCIFB0_SCK, ++ GPIO_FN_MSIOF1_SCK, GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_SSI_WS34, ++ GPIO_FN_STP_IVCXO27_0, GPIO_FN_SCIFB0_RXD, GPIO_FN_MSIOF1_SYNC, ++ GPIO_FN_CAN_STEP0, GPIO_FN_SSI_SDATA3, GPIO_FN_STP_ISCLK_0, ++ GPIO_FN_SCIFB0_TXD, GPIO_FN_MSIOF1_SS1, GPIO_FN_CAN_TXCLK, ++ GPIO_FN_SSI_SCK4, GPIO_FN_STP_ISD_0, GPIO_FN_SCIFB0_CTS_N, ++ GPIO_FN_MSIOF1_SS2, GPIO_FN_SSI_SCK5_C, GPIO_FN_CAN_DEBUGOUT0, ++ GPIO_FN_SSI_WS4, GPIO_FN_STP_ISEN_0, GPIO_FN_SCIFB0_RTS_N, ++ GPIO_FN_MSIOF1_TXD, GPIO_FN_SSI_WS5_C, GPIO_FN_CAN_DEBUGOUT1, ++ GPIO_FN_SSI_SDATA4, GPIO_FN_STP_ISSYNC_0, GPIO_FN_MSIOF1_RXD, ++ GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_SSI_SCK5, GPIO_FN_SCIFB1_SCK, ++ GPIO_FN_IERX_B, GPIO_FN_DU2_EXHSYNC_DU2_HSYNC, GPIO_FN_QSTH_QHS, ++ GPIO_FN_CAN_DEBUGOUT3, GPIO_FN_SSI_WS5, GPIO_FN_SCIFB1_RXD, ++ GPIO_FN_IECLK_B, GPIO_FN_DU2_EXVSYNC_DU2_VSYNC, GPIO_FN_QSTB_QHE, ++ GPIO_FN_CAN_DEBUGOUT4, ++ ++ /* IPSR13 */ ++ GPIO_FN_SSI_SDATA5, GPIO_FN_SCIFB1_TXD, GPIO_FN_IETX_B, GPIO_FN_DU2_DR2, ++ GPIO_FN_LCDOUT2, GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_SSI_SCK6, ++ GPIO_FN_SCIFB1_CTS_N, GPIO_FN_BPFCLK_D, GPIO_FN_RDS_CLK_C, ++ GPIO_FN_DU2_DR3, GPIO_FN_LCDOUT3, GPIO_FN_CAN_DEBUGOUT6, ++ GPIO_FN_BPFCLK_F, GPIO_FN_RDS_CLK_E, GPIO_FN_SSI_WS6, ++ GPIO_FN_SCIFB1_RTS_N, GPIO_FN_CAN0_TX_D, GPIO_FN_DU2_DR4, ++ GPIO_FN_LCDOUT4, GPIO_FN_CAN_DEBUGOUT7, GPIO_FN_SSI_SDATA6, ++ GPIO_FN_FMIN_D, GPIO_FN_RDS_DATA_C, GPIO_FN_DU2_DR5, GPIO_FN_LCDOUT5, ++ GPIO_FN_CAN_DEBUGOUT8, GPIO_FN_SSI_SCK78, GPIO_FN_STP_IVCXO27_1, ++ GPIO_FN_SCK1, GPIO_FN_SCIFA1_SCK, GPIO_FN_DU2_DR6, GPIO_FN_LCDOUT6, ++ GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_WS78, GPIO_FN_STP_ISCLK_1, ++ GPIO_FN_SCIFB2_SCK, GPIO_FN_SCIFA2_CTS_N, GPIO_FN_DU2_DR7, ++ GPIO_FN_LCDOUT7, GPIO_FN_CAN_DEBUGOUT10, GPIO_FN_SSI_SDATA7, ++ GPIO_FN_STP_ISD_1, GPIO_FN_SCIFB2_RXD, GPIO_FN_SCIFA2_RTS_N, ++ GPIO_FN_TCLK2, GPIO_FN_QSTVA_QVS, GPIO_FN_CAN_DEBUGOUT11, ++ GPIO_FN_BPFCLK_E, GPIO_FN_RDS_CLK_D, GPIO_FN_SSI_SDATA7_B, ++ GPIO_FN_FMIN_G, GPIO_FN_RDS_DATA_F, GPIO_FN_SSI_SDATA8, ++ GPIO_FN_STP_ISEN_1, GPIO_FN_SCIFB2_TXD, GPIO_FN_CAN0_TX_C, ++ GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_SSI_SDATA8_B, GPIO_FN_SSI_SDATA9, ++ GPIO_FN_STP_ISSYNC_1, GPIO_FN_SCIFB2_CTS_N, GPIO_FN_SSI_WS1, ++ GPIO_FN_SSI_SDATA5_C, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_AUDIO_CLKA, ++ GPIO_FN_SCIFB2_RTS_N, GPIO_FN_CAN_DEBUGOUT14, ++ ++ /* IPSR14 */ ++ GPIO_FN_AUDIO_CLKB, GPIO_FN_SCIF_CLK, GPIO_FN_CAN0_RX_D, ++ GPIO_FN_DVC_MUTE, GPIO_FN_CAN0_RX_C, GPIO_FN_CAN_DEBUGOUT15, ++ GPIO_FN_REMOCON, GPIO_FN_SCIFA0_SCK, GPIO_FN_HSCK1, GPIO_FN_SCK0, ++ GPIO_FN_MSIOF3_SS2, GPIO_FN_DU2_DG2, GPIO_FN_LCDOUT10, GPIO_FN_SDA1_C, ++ GPIO_FN_SDA1_CIS_C, GPIO_FN_SCIFA0_RXD, GPIO_FN_HRX1, GPIO_FN_RX0, ++ GPIO_FN_DU2_DR0, GPIO_FN_LCDOUT0, GPIO_FN_SCIFA0_TXD, GPIO_FN_HTX1, ++ GPIO_FN_TX0, GPIO_FN_DU2_DR1, GPIO_FN_LCDOUT1, GPIO_FN_SCIFA0_CTS_N, ++ GPIO_FN_HCTS1_N, GPIO_FN_CTS0_N, GPIO_FN_MSIOF3_SYNC, GPIO_FN_DU2_DG3, ++ GPIO_FN_LCDOUT11, GPIO_FN_PWM0_B, GPIO_FN_SCL1_C, GPIO_FN_SCL1_CIS_C, ++ GPIO_FN_SCIFA0_RTS_N, GPIO_FN_HRTS1_N, GPIO_FN_RTS0_N_TANS, ++ GPIO_FN_MSIOF3_SS1, GPIO_FN_DU2_DG0, GPIO_FN_LCDOUT8, GPIO_FN_PWM1_B, ++ GPIO_FN_SCIFA1_RXD, GPIO_FN_AD_DI, GPIO_FN_RX1, ++ GPIO_FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE, ++ GPIO_FN_SCIFA1_TXD, GPIO_FN_AD_DO, GPIO_FN_TX1, GPIO_FN_DU2_DG1, ++ GPIO_FN_LCDOUT9, GPIO_FN_SCIFA1_CTS_N, GPIO_FN_AD_CLK, ++ GPIO_FN_CTS1_N, GPIO_FN_MSIOF3_RXD, GPIO_FN_DU0_DOTCLKOUT, GPIO_FN_QCLK, ++ GPIO_FN_SCIFA1_RTS_N, GPIO_FN_AD_NCS_N, GPIO_FN_RTS1_N_TANS, ++ GPIO_FN_MSIOF3_TXD, GPIO_FN_DU1_DOTCLKOUT, GPIO_FN_QSTVB_QVE, ++ GPIO_FN_HRTS0_N_C, ++ ++ /* IPSR15 */ ++ GPIO_FN_SCIFA2_SCK, GPIO_FN_FMCLK, GPIO_FN_MSIOF3_SCK, GPIO_FN_DU2_DG7, ++ GPIO_FN_LCDOUT15, GPIO_FN_SCIF_CLK_B, GPIO_FN_SCIFA2_RXD, GPIO_FN_FMIN, ++ GPIO_FN_DU2_DB0, GPIO_FN_LCDOUT16, GPIO_FN_SCL2, GPIO_FN_SCL2_CIS, ++ GPIO_FN_SCIFA2_TXD, GPIO_FN_BPFCLK, GPIO_FN_DU2_DB1, GPIO_FN_LCDOUT17, ++ GPIO_FN_SDA2, GPIO_FN_SDA2_CIS, GPIO_FN_HSCK0, GPIO_FN_TS_SDEN0, ++ GPIO_FN_DU2_DG4, GPIO_FN_LCDOUT12, GPIO_FN_HCTS0_N_C, GPIO_FN_HRX0, ++ GPIO_FN_DU2_DB2, GPIO_FN_LCDOUT18, GPIO_FN_HTX0, GPIO_FN_DU2_DB3, ++ GPIO_FN_LCDOUT19, GPIO_FN_HCTS0_N, GPIO_FN_SSI_SCK9, GPIO_FN_DU2_DB4, ++ GPIO_FN_LCDOUT20, GPIO_FN_HRTS0_N, GPIO_FN_SSI_WS9, GPIO_FN_DU2_DB5, ++ GPIO_FN_LCDOUT21, GPIO_FN_MSIOF0_SCK, GPIO_FN_TS_SDAT0, GPIO_FN_ADICLK, ++ GPIO_FN_DU2_DB6, GPIO_FN_LCDOUT22, GPIO_FN_MSIOF0_SYNC, GPIO_FN_TS_SCK0, ++ GPIO_FN_SSI_SCK2, GPIO_FN_ADIDATA, GPIO_FN_DU2_DB7, GPIO_FN_LCDOUT23, ++ GPIO_FN_SCIFA2_RXD_B, GPIO_FN_MSIOF0_SS1, GPIO_FN_ADICHS0, ++ GPIO_FN_DU2_DG5, GPIO_FN_LCDOUT13, GPIO_FN_MSIOF0_TXD, GPIO_FN_ADICHS1, ++ GPIO_FN_DU2_DG6, GPIO_FN_LCDOUT14, ++ ++ /* IPSR16 */ ++ GPIO_FN_MSIOF0_SS2, GPIO_FN_AUDIO_CLKOUT, GPIO_FN_ADICHS2, ++ GPIO_FN_DU2_DISP, GPIO_FN_QPOLA, GPIO_FN_HTX0_C, GPIO_FN_SCIFA2_TXD_B, ++ GPIO_FN_MSIOF0_RXD, GPIO_FN_TS_SPSYNC0, GPIO_FN_SSI_WS2, ++ GPIO_FN_ADICS_SAMP, GPIO_FN_DU2_CDE, GPIO_FN_QPOLB, GPIO_FN_HRX0_C, ++ GPIO_FN_USB1_PWEN, GPIO_FN_AUDIO_CLKOUT_D, GPIO_FN_USB1_OVC, ++ GPIO_FN_TCLK1_B, ++}; ++ + void r8a7790_add_standard_devices(void); + void r8a7790_clock_init(void); + void r8a7790_pinmux_init(void); +diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig +index f8a2ae41..9f0217bc 100644 +--- a/drivers/pinctrl/sh-pfc/Kconfig ++++ b/drivers/pinctrl/sh-pfc/Kconfig +@@ -37,6 +37,11 @@ config PINCTRL_PFC_R8A7779 + depends on ARCH_R8A7779 + select PINCTRL_SH_PFC + ++config PINCTRL_PFC_R8A7790 ++ def_bool y ++ depends on ARCH_R8A7790 ++ select PINCTRL_SH_PFC ++ + config PINCTRL_PFC_SH7203 + def_bool y + depends on CPU_SUBTYPE_SH7203 +diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile +index 211cd8e9..1cbf5b18 100644 +--- a/drivers/pinctrl/sh-pfc/Makefile ++++ b/drivers/pinctrl/sh-pfc/Makefile +@@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc.o + obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o + obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o + obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o ++obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o + obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o + obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o + obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o +diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c +index b5513369..db0d6f7a 100644 +--- a/drivers/pinctrl/sh-pfc/core.c ++++ b/drivers/pinctrl/sh-pfc/core.c +@@ -427,6 +427,9 @@ static const struct platform_device_id sh_pfc_id_table[] = { + #ifdef CONFIG_PINCTRL_PFC_R8A7779 + { "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info }, + #endif ++#ifdef CONFIG_PINCTRL_PFC_R8A7790 ++ { "pfc-r8a7790", (kernel_ulong_t)&r8a7790_pinmux_info }, ++#endif + #ifdef CONFIG_PINCTRL_PFC_SH7203 + { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info }, + #endif +diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h +index 89cb4289..ee4a4d6d 100644 +--- a/drivers/pinctrl/sh-pfc/core.h ++++ b/drivers/pinctrl/sh-pfc/core.h +@@ -57,6 +57,7 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type); + extern const struct sh_pfc_soc_info r8a73a4_pinmux_info; + extern const struct sh_pfc_soc_info r8a7740_pinmux_info; + extern const struct sh_pfc_soc_info r8a7779_pinmux_info; ++extern const struct sh_pfc_soc_info r8a7790_pinmux_info; + extern const struct sh_pfc_soc_info sh7203_pinmux_info; + extern const struct sh_pfc_soc_info sh7264_pinmux_info; + extern const struct sh_pfc_soc_info sh7269_pinmux_info; +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +new file mode 100644 +index 00000000..42b0c551 +--- /dev/null ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -0,0 +1,3238 @@ ++/* ++ * R8A7790 processor support ++ * ++ * Copyright (C) 2013 Renesas Electronics Corporation ++ * Copyright (C) 2013 Magnus Damm ++ * Copyright (C) 2012 Renesas Solutions Corp. ++ * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; version 2 of the ++ * License. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ++ */ ++#include <linux/kernel.h> ++#include <mach/r8a7790.h> ++ ++#include "core.h" ++#include "sh_pfc.h" ++ ++#define CPU_32_PORT(fn, pfx, sfx) \ ++ PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ ++ PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ ++ PORT_1(fn, pfx##31, sfx) ++ ++#define CPU_32_PORT1(fn, pfx, sfx) \ ++ PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ ++ PORT_10(fn, pfx##2, sfx) ++ ++#define CPU_32_PORT2(fn, pfx, sfx) \ ++ PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ ++ PORT_10(fn, pfx##2, sfx) ++ ++/* GP_0_0_DATA -> GP_5_31_DATA (except for GP1[30],GP1[31],GP2[30],GP2[31]) */ ++#define CPU_ALL_PORT(fn, pfx, sfx) \ ++ CPU_32_PORT(fn, pfx##_0_, sfx), \ ++ CPU_32_PORT1(fn, pfx##_1_, sfx), \ ++ CPU_32_PORT2(fn, pfx##_2_, sfx), \ ++ CPU_32_PORT(fn, pfx##_3_, sfx), \ ++ CPU_32_PORT(fn, pfx##_4_, sfx), \ ++ CPU_32_PORT(fn, pfx##_5_, sfx) \ ++ ++#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) ++#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ ++ GP##pfx##_IN, GP##pfx##_OUT) ++ ++#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT ++#define _GP_INDT(pfx, sfx) GP##pfx##_DATA ++ ++#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) ++#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) ++#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) ++ ++ ++#define PORT_10_REV(fn, pfx, sfx) \ ++ PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ ++ PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ ++ PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ ++ PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ ++ PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) ++ ++#define CPU_32_PORT_REV(fn, pfx, sfx) \ ++ PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ ++ PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ ++ PORT_10_REV(fn, pfx, sfx) ++ ++#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) ++#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) ++ ++#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) ++#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ ++ FN_##ipsr, FN_##fn) ++ ++enum { ++ PINMUX_RESERVED = 0, ++ ++ PINMUX_DATA_BEGIN, ++ GP_ALL(DATA), ++ PINMUX_DATA_END, ++ ++ PINMUX_INPUT_BEGIN, ++ GP_ALL(IN), ++ PINMUX_INPUT_END, ++ ++ PINMUX_OUTPUT_BEGIN, ++ GP_ALL(OUT), ++ PINMUX_OUTPUT_END, ++ ++ PINMUX_FUNCTION_BEGIN, ++ GP_ALL(FN), ++ ++ /* GPSR0 */ ++ FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12, ++ FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27, ++ FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12, ++ FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26, ++ FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9, ++ FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22, ++ FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8, ++ FN_IP3_14_12, FN_IP3_17_15, ++ ++ /* GPSR1 */ ++ FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26, ++ FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9, ++ FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21, ++ FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6, ++ FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18, ++ FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0, ++ FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11, ++ ++ /* GPSR2 */ ++ FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4, ++ FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14, ++ FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22, ++ FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7, ++ FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23, ++ FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6, ++ FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13, ++ ++ /* GPSR3 */ ++ FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4, ++ FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18, ++ FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26, ++ FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11, ++ FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26, ++ FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9, ++ FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18, ++ ++ /* GPSR4 */ ++ FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30, ++ FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8, ++ FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20, ++ FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0, ++ FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13, ++ FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26, ++ FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9, ++ FN_IP14_15_12, FN_IP14_18_16, ++ ++ /* GPSR5 */ ++ FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28, ++ FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12, ++ FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20, ++ FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0, ++ FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7, ++ FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0, ++ FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22, ++ ++ /* IPSR0 */ ++ FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B, ++ FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, ++ FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, ++ FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B, ++ FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4, ++ FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4, ++ FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5, ++ FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5, ++ FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6, ++ FN_SCL2_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, ++ FN_SCL2_CIS_C, FN_D7, FN_AD_DI_B, FN_SDA2_C, ++ FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_SDA2_CIS_C, ++ FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, FN_MII_TXD0, ++ FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, ++ ++ /* IPSR1 */ ++ FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, FN_MII_TXD1, ++ FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10, ++ FN_SCIFA1_TXD_C, FN_AVB_TXD2, FN_MII_TXD2, ++ FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11, ++ FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, FN_MII_TXD3, ++ FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3, ++ FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4, ++ FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4, ++ FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N, ++ FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14, ++ FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B, ++ FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6, ++ FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B, ++ FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7, ++ FN_A0, FN_PWM3, FN_A1, FN_PWM4, ++ ++ /* IPSR2 */ ++ FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3, ++ FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B, ++ FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, ++ FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7, ++ FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3, ++ FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4, ++ FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_VI2_DATA0_VI2_B0_B, ++ FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5, ++ FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_VI2_DATA1_VI2_B1_B, ++ FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6, ++ FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, ++ ++ /* IPSR3 */ ++ FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0, ++ FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, ++ FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1, ++ FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B, ++ FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2, ++ FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2, ++ FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B, ++ FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B, ++ FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N, ++ FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18, ++ FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B, ++ FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK, ++ FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4, ++ ++ /* IPSR4 */ ++ FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, ++ FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, ++ FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7, ++ FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3, ++ FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB, ++ FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6, ++ FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N, ++ FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B, ++ FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B, ++ FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B, ++ FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B, ++ FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK, ++ FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B, ++ FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B, ++ FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, ++ ++ /* IPSR5 */ ++ FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, ++ FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N, ++ FN_VI2_HSYNC_N, FN_SCL1, FN_VI2_HSYNC_N_B, ++ FN_INTC_EN0_N, FN_SCL1_CIS, FN_EX_CS5_N, FN_CAN0_RX, ++ FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2, ++ FN_VI1_G2_B, FN_VI2_R4, FN_SDA1, FN_INTC_EN1_N, ++ FN_SDA1_CIS, FN_BS_N, FN_IETX, FN_HTX1_B, ++ FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N, ++ FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3, ++ FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, ++ FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK, ++ FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, ++ FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, ++ FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, ++ FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N, ++ FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B, ++ FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N, ++ FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C, ++ FN_SSI_WS78_B, ++ ++ /* IPSR6 */ ++ FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, ++ FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, ++ FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, ++ FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1, ++ FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C, ++ FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, ++ FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, ++ FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, ++ FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B, ++ FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E, ++ FN_SCL2_CIS_E, FN_ETH_RX_ER, FN_RMII_RX_ER, ++ FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C, ++ FN_SDA2_E, FN_SDA2_CIS_E, FN_ETH_RXD0, FN_RMII_RXD0, ++ FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C, ++ FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1, ++ FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B, ++ FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, ++ FN_RX1_E, FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E, ++ FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, ++ FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E, ++ FN_STP_IVCXO27_1_B, FN_HRX0_F, ++ ++ /* IPSR7 */ ++ FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E, ++ FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1, ++ FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F, ++ FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, ++ FN_HRTS0_N_F, FN_ETH_MAGIC, FN_RMII_MAGIC, ++ FN_SIM0_RST_C, FN_ETH_TXD0, FN_RMII_TXD0, ++ FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C, ++ FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B, ++ FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0, ++ FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, ++ FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C, ++ FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C, ++ FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, ++ FN_PCMWE_N, FN_IECLK_C, FN_DU1_DOTCLKIN, ++ FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK, ++ FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1, ++ FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, ++ FN_MII_RXD2, ++ ++ /* IPSR8 */ ++ FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, ++ FN_MII_RXD3, FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, ++ FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, ++ FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, ++ FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, ++ FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, ++ FN_MII_RX_ER, FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, ++ FN_MII_RX_CLK, FN_VI1_CLK, FN_AVB_RX_DV, ++ FN_MII_RX_DV, FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, ++ FN_AVB_CRS, FN_MII_CRS, FN_VI1_DATA1_VI1_B1, ++ FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC, ++ FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, ++ FN_MII_MDIO, FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, ++ FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, ++ FN_AVB_MAGIC, FN_MII_MAGIC, FN_VI1_DATA5_VI1_B5, ++ FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK, ++ FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD, ++ FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, ++ ++ /* IPSR9 */ ++ FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, ++ FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, ++ FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, ++ FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, ++ FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP, ++ FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B, ++ FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP, ++ FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, ++ FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B, ++ FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK, ++ FN_AVB_TX_EN, FN_MII_TX_EN, FN_SD1_CMD, ++ FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B, ++ FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK, ++ FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK, ++ FN_MII_LINK, FN_SCIFB0_TXD_B, FN_SD1_DAT2, ++ FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B, ++ FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0, ++ FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6, ++ FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B, ++ FN_SCL2_D, FN_SCL2_CIS_D, FN_SIM0_CLK_B, ++ FN_VI3_CLK_B, ++ ++ /* IPSR10 */ ++ FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, ++ FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D, ++ FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK, ++ FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B, ++ FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D, ++ FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D, ++ FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B, ++ FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B, ++ FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D, ++ FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B, ++ FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA, ++ FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D, ++ FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B, ++ FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK, ++ FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B, ++ FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3, ++ FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B, ++ FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, ++ FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4, ++ FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0, ++ FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B, ++ FN_GLO_I0_B, FN_VI3_DATA6_B, ++ ++ /* IPSR11 */ ++ FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN, ++ FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D, ++ FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, ++ FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD, ++ FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, ++ FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2, ++ FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3, ++ FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1, ++ FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP, ++ FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, ++ FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F, ++ FN_RDS_DATA_E, FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B, ++ FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B, ++ FN_SDA2_CIS_B, FN_MLB_DAT, FN_SPV_EVEN, ++ FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, ++ FN_RDS_CLK_B, FN_SSI_SCK0129, FN_CAN_CLK_B, ++ FN_MOUT0, ++ ++ /* IPSR12 */ ++ FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, ++ FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, ++ FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, ++ FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6, ++ FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK, ++ FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34, ++ FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC, ++ FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0, ++ FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, ++ FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N, ++ FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, ++ FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N, ++ FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, ++ FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD, ++ FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK, ++ FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS, ++ FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD, ++ FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE, ++ FN_CAN_DEBUGOUT4, ++ ++ /* IPSR13 */ ++ FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2, ++ FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6, ++ FN_SCIFB1_CTS_N, FN_BPFCLK_D, FN_RDS_CLK_C, ++ FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6, ++ FN_BPFCLK_F, FN_RDS_CLK_E, FN_SSI_WS6, ++ FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4, ++ FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6, ++ FN_FMIN_D, FN_RDS_DATA_C, FN_DU2_DR5, FN_LCDOUT5, ++ FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1, ++ FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6, ++ FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1, ++ FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7, ++ FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7, ++ FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N, ++ FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, ++ FN_BPFCLK_E, FN_RDS_CLK_D, FN_SSI_SDATA7_B, ++ FN_FMIN_G, FN_RDS_DATA_F, FN_SSI_SDATA8, ++ FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C, ++ FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9, ++ FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1, ++ FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA, ++ FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, ++ ++ /* IPSR14 */ ++ FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, ++ FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, ++ FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, ++ FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_SDA1_C, ++ FN_SDA1_CIS_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0, ++ FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1, ++ FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N, ++ FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3, ++ FN_LCDOUT11, FN_PWM0_B, FN_SCL1_C, FN_SCL1_CIS_C, ++ FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N_TANS, ++ FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, ++ FN_SCIFA1_RXD, FN_AD_DI, FN_RX1, ++ FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, ++ FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1, ++ FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK, ++ FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK, ++ FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N_TANS, ++ FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE, ++ FN_HRTS0_N_C, ++ ++ /* IPSR15 */ ++ FN_SCIFA2_SCK, FN_FMCLK, FN_MSIOF3_SCK, FN_DU2_DG7, ++ FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN, ++ FN_DU2_DB0, FN_LCDOUT16, FN_SCL2, FN_SCL2_CIS, ++ FN_SCIFA2_TXD, FN_BPFCLK, FN_DU2_DB1, FN_LCDOUT17, ++ FN_SDA2, FN_SDA2_CIS, FN_HSCK0, FN_TS_SDEN0, ++ FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0, ++ FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3, ++ FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, ++ FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, ++ FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK, ++ FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0, ++ FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23, ++ FN_SCIFA2_RXD_B, FN_MSIOF0_SS1, FN_ADICHS0, ++ FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1, ++ FN_DU2_DG6, FN_LCDOUT14, ++ ++ /* IPSR16 */ ++ FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2, ++ FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, ++ FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2, ++ FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_HRX0_C, ++ FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC, ++ FN_TCLK1_B, ++ ++ FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, ++ FN_SEL_SCIF1_4, ++ FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, ++ FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, ++ FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, ++ FN_SEL_SCIFB1_4, ++ FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6, ++ FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3, ++ FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, ++ FN_SEL_SCFA_0, FN_SEL_SCFA_1, ++ FN_SEL_SOF1_0, FN_SEL_SOF1_1, ++ FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, ++ FN_SEL_SSI6_0, FN_SEL_SSI6_1, ++ FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, ++ FN_SEL_VI3_0, FN_SEL_VI3_1, ++ FN_SEL_VI2_0, FN_SEL_VI2_1, ++ FN_SEL_VI1_0, FN_SEL_VI1_1, ++ FN_SEL_VI0_0, FN_SEL_VI0_1, ++ FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, ++ FN_SEL_LBS_0, FN_SEL_LBS_1, ++ FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, ++ FN_SEL_SOF3_0, FN_SEL_SOF3_1, ++ FN_SEL_SOF0_0, FN_SEL_SOF0_1, ++ ++ FN_SEL_TMU1_0, FN_SEL_TMU1_1, ++ FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, ++ FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, ++ FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, ++ FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, ++ FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, ++ FN_SEL_CAN1_0, FN_SEL_CAN1_1, ++ FN_SEL_ADI_0, FN_SEL_ADI_1, ++ FN_SEL_SSP_0, FN_SEL_SSP_1, ++ FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, ++ FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, ++ FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3, ++ FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, ++ FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, ++ FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, ++ FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5, ++ FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, ++ FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, ++ ++ FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, ++ FN_SEL_IIC0_0, FN_SEL_IIC0_1, ++ FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, ++ FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, ++ FN_SEL_IIC2_4, ++ FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, ++ FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, ++ FN_SEL_I2C2_4, ++ FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, ++ PINMUX_FUNCTION_END, ++ ++ PINMUX_MARK_BEGIN, ++ ++ VI1_DATA7_VI1_B7_MARK, ++ ++ USB0_PWEN_MARK, USB0_OVC_VBUS_MARK, ++ USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK, ++ DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK, ++ ++ D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK, ++ D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK, ++ VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK, ++ VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK, ++ VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK, ++ SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK, ++ VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK, ++ SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK, ++ VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK, ++ SCL2_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK, ++ SCL2_CIS_C_MARK, D7_MARK, AD_DI_B_MARK, SDA2_C_MARK, ++ VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, SDA2_CIS_C_MARK, ++ D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK, MII_TXD0_MARK, ++ VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK, ++ ++ D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK, MII_TXD1_MARK, ++ VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK, ++ SCIFA1_TXD_C_MARK, AVB_TXD2_MARK, MII_TXD2_MARK, ++ VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK, ++ SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK, MII_TXD3_MARK, ++ VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK, ++ D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK, ++ VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK, ++ D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK, ++ VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK, ++ SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK, ++ VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK, ++ D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK, ++ VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK, ++ A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK, ++ ++ A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK, ++ PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK, ++ TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK, ++ A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK, ++ SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK, ++ A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK, ++ VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, VI2_DATA0_VI2_B0_B_MARK, ++ A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK, ++ VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, VI2_DATA1_VI2_B1_B_MARK, ++ A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK, ++ VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK, ++ ++ A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK, ++ VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK, ++ A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK, ++ VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK, ++ A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK, ++ MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK, ++ VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK, ++ ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK, ++ ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK, ++ A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK, ++ AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK, ++ ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK, ++ VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK, ++ ++ A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK, ++ A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK, ++ VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK, ++ VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK, ++ VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK, ++ VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK, ++ VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK, ++ VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK, ++ CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK, ++ VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK, ++ VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK, ++ MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK, ++ HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK, ++ VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK, ++ VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK, ++ ++ EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK, ++ VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK, ++ EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK, ++ VI2_HSYNC_N_MARK, SCL1_MARK, VI2_HSYNC_N_B_MARK, ++ INTC_EN0_N_MARK, SCL1_CIS_MARK, EX_CS5_N_MARK, CAN0_RX_MARK, ++ MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK, ++ VI1_G2_B_MARK, VI2_R4_MARK, SDA1_MARK, INTC_EN1_N_MARK, ++ SDA1_CIS_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK, ++ CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK, ++ CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK, ++ VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK, ++ INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK, ++ VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK, ++ WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK, ++ VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK, ++ IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK, ++ VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK, ++ MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK, ++ VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK, ++ SSI_WS78_B_MARK, ++ ++ DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK, ++ VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK, ++ DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK, ++ SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK, ++ INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK, ++ DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK, ++ MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK, ++ SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK, ++ ETH_CRS_DV_MARK, RMII_CRS_DV_MARK, STP_ISCLK_0_B_MARK, ++ TS_SDEN0_D_MARK, GLO_Q0_C_MARK, SCL2_E_MARK, ++ SCL2_CIS_E_MARK, ETH_RX_ER_MARK, RMII_RX_ER_MARK, ++ STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK, ++ SDA2_E_MARK, SDA2_CIS_E_MARK, ETH_RXD0_MARK, RMII_RXD0_MARK, ++ STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK, ++ SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK, ++ RMII_RXD1_MARK, HRX0_E_MARK, STP_ISSYNC_0_B_MARK, ++ TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK, ++ RX1_E_MARK, ETH_LINK_MARK, RMII_LINK_MARK, HTX0_E_MARK, ++ STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK, ++ ETH_REF_CLK_MARK, RMII_REF_CLK_MARK, HCTS0_N_E_MARK, ++ STP_IVCXO27_1_B_MARK, HRX0_F_MARK, ++ ++ ETH_MDIO_MARK, RMII_MDIO_MARK, HRTS0_N_E_MARK, ++ SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK, ++ RMII_TXD1_MARK, HTX0_F_MARK, BPFCLK_G_MARK, RDS_CLK_F_MARK, ++ ETH_TX_EN_MARK, RMII_TX_EN_MARK, SIM0_CLK_C_MARK, ++ HRTS0_N_F_MARK, ETH_MAGIC_MARK, RMII_MAGIC_MARK, ++ SIM0_RST_C_MARK, ETH_TXD0_MARK, RMII_TXD0_MARK, ++ STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK, ++ ETH_MDC_MARK, RMII_MDC_MARK, STP_ISD_1_B_MARK, ++ TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK, ++ SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK, ++ GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK, ++ STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK, ++ PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK, ++ PCMWE_N_MARK, IECLK_C_MARK, DU1_DOTCLKIN_MARK, ++ AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK, ++ ATACS00_N_MARK, AVB_RXD1_MARK, MII_RXD1_MARK, ++ VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK, ++ MII_RXD2_MARK, ++ ++ VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK, ++ MII_RXD3_MARK, VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK, ++ AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK, ++ AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK, ++ AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK, ++ AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK, ++ MII_RX_ER_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK, ++ MII_RX_CLK_MARK, VI1_CLK_MARK, AVB_RX_DV_MARK, ++ MII_RX_DV_MARK, VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK, ++ AVB_CRS_MARK, MII_CRS_MARK, VI1_DATA1_VI1_B1_MARK, ++ SCIFA1_RXD_D_MARK, AVB_MDC_MARK, MII_MDC_MARK, ++ VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK, ++ MII_MDIO_MARK, VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK, ++ AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK, ++ AVB_MAGIC_MARK, MII_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK, ++ AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK, ++ SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK, ++ SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK, ++ ++ SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK, ++ SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK, ++ SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK, ++ SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK, ++ SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK, ++ GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, SCL1_B_MARK, ++ SCL1_CIS_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK, ++ MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK, ++ GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, SDA1_B_MARK, ++ SDA1_CIS_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK, ++ AVB_TX_EN_MARK, MII_TX_EN_MARK, SD1_CMD_MARK, ++ AVB_TX_ER_MARK, MII_TX_ER_MARK, SCIFB0_SCK_B_MARK, ++ SD1_DAT0_MARK, AVB_TX_CLK_MARK, MII_TX_CLK_MARK, ++ SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK, ++ MII_LINK_MARK, SCIFB0_TXD_B_MARK, SD1_DAT2_MARK, ++ AVB_COL_MARK, MII_COL_MARK, SCIFB0_CTS_N_B_MARK, ++ SD1_DAT3_MARK, AVB_RXD0_MARK, MII_RXD0_MARK, ++ SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK, ++ TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK, ++ SCL2_D_MARK, SCL2_CIS_D_MARK, SIM0_CLK_B_MARK, ++ VI3_CLK_B_MARK, ++ ++ SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK, ++ GLO_RFON_MARK, VI1_CLK_B_MARK, SDA2_D_MARK, SDA2_CIS_D_MARK, ++ SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK, ++ VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK, ++ VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK, ++ VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK, ++ TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK, ++ SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK, ++ VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK, ++ TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK, ++ SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK, RDS_DATA_MARK, ++ VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK, ++ TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK, ++ SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK, RDS_CLK_MARK, ++ VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK, ++ GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK, ++ MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK, ++ HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK, ++ VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK, ++ TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK, ++ VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK, ++ GLO_I0_B_MARK, VI3_DATA6_B_MARK, ++ ++ SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK, ++ GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK, ++ TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK, ++ SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK, ++ MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK, ++ SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK, ++ MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK, ++ SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK, ++ VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK, ++ MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK, ++ RDS_DATA_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK, FMIN_F_MARK, ++ RDS_DATA_E_MARK, MLB_CLK_MARK, SCL2_B_MARK, SCL2_CIS_B_MARK, ++ MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, SDA2_B_MARK, ++ SDA2_CIS_B_MARK, MLB_DAT_MARK, SPV_EVEN_MARK, ++ SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK, ++ RDS_CLK_B_MARK, SSI_SCK0129_MARK, CAN_CLK_B_MARK, ++ MOUT0_MARK, ++ ++ SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK, ++ SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK, ++ SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK, ++ SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK, ++ SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK, ++ MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK, ++ STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK, ++ CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK, ++ SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK, ++ SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK, ++ MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK, ++ SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK, ++ MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK, ++ SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK, ++ CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK, ++ IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK, ++ CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK, ++ IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK, ++ CAN_DEBUGOUT4_MARK, ++ ++ SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK, ++ LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK, ++ SCIFB1_CTS_N_MARK, BPFCLK_D_MARK, RDS_CLK_C_MARK, ++ DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK, ++ BPFCLK_F_MARK, RDS_CLK_E_MARK, SSI_WS6_MARK, ++ SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK, ++ LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK, ++ FMIN_D_MARK, RDS_DATA_C_MARK, DU2_DR5_MARK, LCDOUT5_MARK, ++ CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK, ++ SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK, ++ CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK, ++ SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK, ++ LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK, ++ STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK, ++ TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK, ++ BPFCLK_E_MARK, RDS_CLK_D_MARK, SSI_SDATA7_B_MARK, ++ FMIN_G_MARK, RDS_DATA_F_MARK, SSI_SDATA8_MARK, ++ STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK, ++ CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK, ++ STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK, ++ SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK, ++ SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK, ++ ++ AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK, ++ DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK, ++ REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK, ++ MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, SDA1_C_MARK, ++ SDA1_CIS_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK, ++ DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK, ++ TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK, ++ HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK, ++ LCDOUT11_MARK, PWM0_B_MARK, SCL1_C_MARK, SCL1_CIS_C_MARK, ++ SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_TANS_MARK, ++ MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK, ++ SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK, ++ DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, ++ SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK, ++ LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK, ++ CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK, ++ SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_TANS_MARK, ++ MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK, ++ HRTS0_N_C_MARK, ++ ++ SCIFA2_SCK_MARK, FMCLK_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK, ++ LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK, ++ DU2_DB0_MARK, LCDOUT16_MARK, SCL2_MARK, SCL2_CIS_MARK, ++ SCIFA2_TXD_MARK, BPFCLK_MARK, DU2_DB1_MARK, LCDOUT17_MARK, ++ SDA2_MARK, SDA2_CIS_MARK, HSCK0_MARK, TS_SDEN0_MARK, ++ DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK, ++ DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK, ++ LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK, ++ LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK, ++ LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK, ++ DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK, ++ SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK, ++ SCIFA2_RXD_B_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK, ++ DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK, ++ DU2_DG6_MARK, LCDOUT14_MARK, ++ ++ MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK, ++ DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK, ++ MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK, ++ ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, HRX0_C_MARK, ++ USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK, ++ TCLK1_B_MARK, ++ PINMUX_MARK_END, ++}; ++ ++static const pinmux_enum_t pinmux_data[] = { ++ PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ ++ ++ PINMUX_DATA(VI1_DATA7_VI1_B7_MARK, FN_VI1_DATA7_VI1_B7), ++ PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN), ++ PINMUX_DATA(USB0_OVC_VBUS_MARK, FN_USB0_OVC_VBUS), ++ PINMUX_DATA(USB2_PWEN_MARK, FN_USB2_PWEN), ++ PINMUX_DATA(USB2_OVC_MARK, FN_USB2_OVC), ++ PINMUX_DATA(AVS1_MARK, FN_AVS1), ++ PINMUX_DATA(AVS2_MARK, FN_AVS2), ++ PINMUX_DATA(DU_DOTCLKIN0_MARK, FN_DU_DOTCLKIN0), ++ PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2), ++ ++ PINMUX_IPSR_DATA(IP0_2_0, D0), ++ PINMUX_IPSR_MODSEL_DATA(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1), ++ PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI3_DATA0, SEL_VI3_0), ++ PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4, SEL_VI0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4_B, SEL_VI0_1), ++ PINMUX_IPSR_DATA(IP0_5_3, D1), ++ PINMUX_IPSR_MODSEL_DATA(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1), ++ PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI3_DATA1, SEL_VI3_0), ++ PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5, SEL_VI0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5_B, SEL_VI0_1), ++ PINMUX_IPSR_DATA(IP0_8_6, D2), ++ PINMUX_IPSR_MODSEL_DATA(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1), ++ PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI3_DATA2, SEL_VI3_0), ++ PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6, SEL_VI0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6_B, SEL_VI0_1), ++ PINMUX_IPSR_DATA(IP0_11_9, D3), ++ PINMUX_IPSR_MODSEL_DATA(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1), ++ PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI3_DATA3, SEL_VI3_0), ++ PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7, SEL_VI0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7_B, SEL_VI0_1), ++ PINMUX_IPSR_DATA(IP0_15_12, D4), ++ PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5), ++ PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2), ++ PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI3_DATA4, SEL_VI3_0), ++ PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0, SEL_VI0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0_B, SEL_VI0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP0_15_12, RX0_B, SEL_SCIF0_1), ++ PINMUX_IPSR_DATA(IP0_19_16, D5), ++ PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5), ++ PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2), ++ PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI3_DATA5, SEL_VI3_0), ++ PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1, SEL_VI0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1_B, SEL_VI0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP0_19_16, TX0_B, SEL_SCIF0_1), ++ PINMUX_IPSR_DATA(IP0_22_20, D6), ++ PINMUX_IPSR_MODSEL_DATA(IP0_22_20, SCL2_C, SEL_IIC2_2), ++ PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI3_DATA6, SEL_VI3_0), ++ PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2, SEL_VI0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2_B, SEL_VI0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP0_22_20, SCL2_CIS_C, SEL_I2C2_2), ++ PINMUX_IPSR_DATA(IP0_26_23, D7), ++ PINMUX_IPSR_MODSEL_DATA(IP0_26_23, AD_DI_B, SEL_ADI_1), ++ PINMUX_IPSR_MODSEL_DATA(IP0_26_23, SDA2_C, SEL_IIC2_2), ++ PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI3_DATA7, SEL_VI3_0), ++ PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3, SEL_VI0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3_B, SEL_VI0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP0_26_23, SDA2_CIS_C, SEL_I2C2_2), ++ PINMUX_IPSR_DATA(IP0_30_27, D8), ++ PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2), ++ PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0), ++ PINMUX_IPSR_DATA(IP0_30_27, MII_TXD0), ++ PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0, SEL_VI0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0_B, SEL_VI0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0), ++ ++ PINMUX_IPSR_DATA(IP1_3_0, D9), ++ PINMUX_IPSR_MODSEL_DATA(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2), ++ PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1), ++ PINMUX_IPSR_DATA(IP1_3_0, MII_TXD1), ++ PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1, SEL_VI0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1_B, SEL_VI0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0), ++ PINMUX_IPSR_DATA(IP1_7_4, D10), ++ PINMUX_IPSR_MODSEL_DATA(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2), ++ PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2), ++ PINMUX_IPSR_DATA(IP1_7_4, MII_TXD2), ++ PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2, SEL_VI0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2_B, SEL_VI0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0), ++ PINMUX_IPSR_DATA(IP1_11_8, D11), ++ PINMUX_IPSR_MODSEL_DATA(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2), ++ PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3), ++ PINMUX_IPSR_DATA(IP1_11_8, MII_TXD3), ++ PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3, SEL_VI0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3_B, SEL_VI0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0), ++ PINMUX_IPSR_DATA(IP1_14_12, D12), ++ PINMUX_IPSR_MODSEL_DATA(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2), ++ PINMUX_IPSR_DATA(IP1_14_12, AVB_TXD4), ++ PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0), ++ PINMUX_IPSR_DATA(IP1_17_15, D13), ++ PINMUX_IPSR_MODSEL_DATA(IP1_17_15, AVB_TXD5, SEL_SCIFA1_2), ++ PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0), ++ PINMUX_IPSR_DATA(IP1_21_18, D14), ++ PINMUX_IPSR_MODSEL_DATA(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2), ++ PINMUX_IPSR_DATA(IP1_21_18, AVB_TXD6), ++ PINMUX_IPSR_MODSEL_DATA(IP1_21_18, RX1_B, SEL_SCIF1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB, SEL_VI0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0), ++ PINMUX_IPSR_DATA(IP1_25_22, D15), ++ PINMUX_IPSR_MODSEL_DATA(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2), ++ PINMUX_IPSR_DATA(IP1_25_22, AVB_TXD7), ++ PINMUX_IPSR_MODSEL_DATA(IP1_25_22, TX1_B, SEL_SCIF1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD, SEL_VI0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD_B, SEL_VI0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0), ++ PINMUX_IPSR_DATA(IP1_27_26, A0), ++ PINMUX_IPSR_DATA(IP1_27_26, PWM3), ++ PINMUX_IPSR_DATA(IP1_29_28, A1), ++ PINMUX_IPSR_DATA(IP1_29_28, PWM4), ++ ++ PINMUX_IPSR_DATA(IP2_2_0, A2), ++ PINMUX_IPSR_DATA(IP2_2_0, PWM5), ++ PINMUX_IPSR_MODSEL_DATA(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1), ++ PINMUX_IPSR_DATA(IP2_5_3, A3), ++ PINMUX_IPSR_DATA(IP2_5_3, PWM6), ++ PINMUX_IPSR_MODSEL_DATA(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1), ++ PINMUX_IPSR_DATA(IP2_8_6, A4), ++ PINMUX_IPSR_MODSEL_DATA(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1), ++ PINMUX_IPSR_DATA(IP2_8_6, TPU0TO0), ++ PINMUX_IPSR_DATA(IP2_11_9, A5), ++ PINMUX_IPSR_MODSEL_DATA(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1), ++ PINMUX_IPSR_DATA(IP2_11_9, TPU0TO1), ++ PINMUX_IPSR_DATA(IP2_14_12, A6), ++ PINMUX_IPSR_MODSEL_DATA(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1), ++ PINMUX_IPSR_DATA(IP2_14_12, TPU0TO2), ++ PINMUX_IPSR_DATA(IP2_17_15, A7), ++ PINMUX_IPSR_MODSEL_DATA(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1), ++ PINMUX_IPSR_DATA(IP2_17_15, AUDIO_CLKOUT_B), ++ PINMUX_IPSR_DATA(IP2_17_15, TPU0TO3), ++ PINMUX_IPSR_DATA(IP2_21_18, A8), ++ PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1), ++ PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4, SEL_VI0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4_B, SEL_VI0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2), ++ PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1), ++ PINMUX_IPSR_DATA(IP2_25_22, A9), ++ PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SSI_WS5_B, SEL_SSI5_1), ++ PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5, SEL_VI0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5_B, SEL_VI0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2), ++ PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1), ++ PINMUX_IPSR_DATA(IP2_28_26, A10), ++ PINMUX_IPSR_MODSEL_DATA(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1), ++ PINMUX_IPSR_DATA(IP2_28_26, MSIOF2_SYNC), ++ PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6, SEL_VI0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6_B, SEL_VI0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1), ++ ++ PINMUX_IPSR_DATA(IP3_3_0, A11), ++ PINMUX_IPSR_MODSEL_DATA(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1), ++ PINMUX_IPSR_DATA(IP3_3_0, MSIOF2_SCK), ++ PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0, SEL_VI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0_B, SEL_VI1_1), ++ PINMUX_IPSR_DATA(IP3_3_0, VI2_G0), ++ PINMUX_IPSR_DATA(IP3_3_0, VI2_DATA3_VI2_B3_B), ++ PINMUX_IPSR_DATA(IP3_7_4, A12), ++ PINMUX_IPSR_MODSEL_DATA(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1), ++ PINMUX_IPSR_DATA(IP3_7_4, MSIOF2_TXD), ++ PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1, SEL_VI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1_B, SEL_VI1_1), ++ PINMUX_IPSR_DATA(IP3_7_4, VI2_G1), ++ PINMUX_IPSR_DATA(IP3_7_4, VI2_DATA4_VI2_B4_B), ++ PINMUX_IPSR_DATA(IP3_11_8, A13), ++ PINMUX_IPSR_MODSEL_DATA(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1), ++ PINMUX_IPSR_DATA(IP3_11_8, EX_WAIT2), ++ PINMUX_IPSR_DATA(IP3_11_8, MSIOF2_RXD), ++ PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2, SEL_VI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2_B, SEL_VI1_1), ++ PINMUX_IPSR_DATA(IP3_11_8, VI2_G2), ++ PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_0), ++ PINMUX_IPSR_DATA(IP3_14_12, A14), ++ PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1), ++ PINMUX_IPSR_DATA(IP3_14_12, ATACS11_N), ++ PINMUX_IPSR_DATA(IP3_14_12, MSIOF2_SS1), ++ PINMUX_IPSR_DATA(IP3_17_15, A15), ++ PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1), ++ PINMUX_IPSR_DATA(IP3_17_15, ATARD1_N), ++ PINMUX_IPSR_DATA(IP3_17_15, MSIOF2_SS2), ++ PINMUX_IPSR_DATA(IP3_19_18, A16), ++ PINMUX_IPSR_DATA(IP3_19_18, ATAWR1_N), ++ PINMUX_IPSR_DATA(IP3_22_20, A17), ++ PINMUX_IPSR_MODSEL_DATA(IP3_22_20, AD_DO_B, SEL_ADI_1), ++ PINMUX_IPSR_DATA(IP3_22_20, ATADIR1_N), ++ PINMUX_IPSR_DATA(IP3_25_23, A18), ++ PINMUX_IPSR_MODSEL_DATA(IP3_25_23, AD_CLK_B, SEL_ADI_1), ++ PINMUX_IPSR_DATA(IP3_25_23, ATAG1_N), ++ PINMUX_IPSR_DATA(IP3_28_26, A19), ++ PINMUX_IPSR_MODSEL_DATA(IP3_28_26, AD_NCS_N_B, SEL_ADI_1), ++ PINMUX_IPSR_DATA(IP3_28_26, ATACS01_N), ++ PINMUX_IPSR_MODSEL_DATA(IP3_28_26, EX_WAIT0_B, SEL_LBS_1), ++ PINMUX_IPSR_DATA(IP3_31_29, A20), ++ PINMUX_IPSR_DATA(IP3_31_29, SPCLK), ++ PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3, SEL_VI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3_B, SEL_VI1_1), ++ PINMUX_IPSR_DATA(IP3_31_29, VI2_G4), ++ ++ PINMUX_IPSR_DATA(IP4_2_0, A21), ++ PINMUX_IPSR_DATA(IP4_2_0, MOSI_IO0), ++ PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4, SEL_VI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4_B, SEL_VI1_1), ++ PINMUX_IPSR_DATA(IP4_2_0, VI2_G5), ++ PINMUX_IPSR_DATA(IP4_5_3, A22), ++ PINMUX_IPSR_DATA(IP4_5_3, MISO_IO1), ++ PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5, SEL_VI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5_B, SEL_VI1_1), ++ PINMUX_IPSR_DATA(IP4_5_3, VI2_G6), ++ PINMUX_IPSR_DATA(IP4_8_6, A23), ++ PINMUX_IPSR_DATA(IP4_8_6, IO2), ++ PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7, SEL_VI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7_B, SEL_VI1_1), ++ PINMUX_IPSR_DATA(IP4_8_6, VI2_G7), ++ PINMUX_IPSR_DATA(IP4_11_9, A24), ++ PINMUX_IPSR_DATA(IP4_11_9, IO3), ++ PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7, SEL_VI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7_B, SEL_VI1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB, SEL_VI2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1), ++ PINMUX_IPSR_DATA(IP4_14_12, A25), ++ PINMUX_IPSR_DATA(IP4_14_12, SSL), ++ PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6, SEL_VI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6_B, SEL_VI1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD, SEL_VI2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD_B, SEL_VI2_1), ++ PINMUX_IPSR_DATA(IP4_17_15, CS0_N), ++ PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6, SEL_VI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6_B, SEL_VI1_1), ++ PINMUX_IPSR_DATA(IP4_17_15, VI2_G3), ++ PINMUX_IPSR_MODSEL_DATA(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1), ++ PINMUX_IPSR_DATA(IP4_20_18, CS1_N_A26), ++ PINMUX_IPSR_DATA(IP4_20_18, SPEEDIN), ++ PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7, SEL_VI0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7_B, SEL_VI0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK, SEL_VI2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK_B, SEL_VI2_1), ++ PINMUX_IPSR_DATA(IP4_23_21, EX_CS0_N), ++ PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HRX1_B, SEL_HSCIF1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5, SEL_VI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5_B, SEL_VI1_1), ++ PINMUX_IPSR_DATA(IP4_23_21, VI2_R0), ++ PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HTX0_B, SEL_HSCIF0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1), ++ PINMUX_IPSR_DATA(IP4_26_24, EX_CS1_N), ++ PINMUX_IPSR_DATA(IP4_26_24, GPS_CLK), ++ PINMUX_IPSR_MODSEL_DATA(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD, SEL_VI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD_B, SEL_VI1_1), ++ PINMUX_IPSR_DATA(IP4_26_24, VI2_R1), ++ PINMUX_IPSR_DATA(IP4_29_27, EX_CS2_N), ++ PINMUX_IPSR_DATA(IP4_29_27, GPS_SIGN), ++ PINMUX_IPSR_MODSEL_DATA(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1), ++ PINMUX_IPSR_DATA(IP4_29_27, VI3_CLKENB), ++ PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0, SEL_VI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0_B, SEL_VI1_1), ++ PINMUX_IPSR_DATA(IP4_29_27, VI2_R2), ++ ++ PINMUX_IPSR_DATA(IP5_2_0, EX_CS3_N), ++ PINMUX_IPSR_DATA(IP5_2_0, GPS_MAG), ++ PINMUX_IPSR_DATA(IP5_2_0, VI3_FIELD), ++ PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1, SEL_VI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1_B, SEL_VI1_1), ++ PINMUX_IPSR_DATA(IP5_2_0, VI2_R3), ++ PINMUX_IPSR_MODSEL_DATA(IP5_5_3, EX_CS4_N, SEL_I2C1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1), ++ PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N), ++ PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SCL1, SEL_IIC1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1), ++ PINMUX_IPSR_DATA(IP5_5_3, INTC_EN0_N), ++ PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SCL1_CIS, SEL_I2C1_0), ++ PINMUX_IPSR_DATA(IP5_9_6, EX_CS5_N), ++ PINMUX_IPSR_MODSEL_DATA(IP5_9_6, CAN0_RX, SEL_CAN0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1), ++ PINMUX_IPSR_DATA(IP5_9_6, VI3_VSYNC_N), ++ PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2, SEL_VI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2_B, SEL_VI1_1), ++ PINMUX_IPSR_DATA(IP5_9_6, VI2_R4), ++ PINMUX_IPSR_MODSEL_DATA(IP5_9_6, SDA1, SEL_IIC1_0), ++ PINMUX_IPSR_DATA(IP5_9_6, INTC_EN1_N), ++ PINMUX_IPSR_MODSEL_DATA(IP5_9_6, SDA1_CIS, SEL_I2C1_0), ++ PINMUX_IPSR_DATA(IP5_12_10, BS_N), ++ PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX, SEL_IEB_0), ++ PINMUX_IPSR_MODSEL_DATA(IP5_12_10, HTX1_B, SEL_HSCIF1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP5_12_10, CAN1_TX, SEL_CAN1_0), ++ PINMUX_IPSR_DATA(IP5_12_10, DRACK0), ++ PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX_C, SEL_IEB_2), ++ PINMUX_IPSR_DATA(IP5_14_13, RD_N), ++ PINMUX_IPSR_MODSEL_DATA(IP5_14_13, CAN0_TX, SEL_CAN0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1), ++ PINMUX_IPSR_DATA(IP5_17_15, RD_WR_N), ++ PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3, SEL_VI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3_B, SEL_VI1_1), ++ PINMUX_IPSR_DATA(IP5_17_15, VI2_R5), ++ PINMUX_IPSR_MODSEL_DATA(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1), ++ PINMUX_IPSR_DATA(IP5_17_15, INTC_IRQ4_N), ++ PINMUX_IPSR_DATA(IP5_20_18, WE0_N), ++ PINMUX_IPSR_MODSEL_DATA(IP5_20_18, IECLK, SEL_IEB_0), ++ PINMUX_IPSR_MODSEL_DATA(IP5_20_18, CAN_CLK, SEL_CANCLK_0), ++ PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1), ++ PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1), ++ PINMUX_IPSR_DATA(IP5_23_21, WE1_N), ++ PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX, SEL_IEB_0), ++ PINMUX_IPSR_MODSEL_DATA(IP5_23_21, CAN1_RX, SEL_CAN1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4, SEL_VI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4_B, SEL_VI1_1), ++ PINMUX_IPSR_DATA(IP5_23_21, VI2_R6), ++ PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1), ++ PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX_C, SEL_IEB_2), ++ PINMUX_IPSR_DATA(IP5_26_24, EX_WAIT0), ++ PINMUX_IPSR_DATA(IP5_26_24, IRQ3), ++ PINMUX_IPSR_DATA(IP5_26_24, INTC_IRQ3_N), ++ PINMUX_IPSR_MODSEL_DATA(IP5_26_24, VI3_CLK, SEL_VI3_0), ++ PINMUX_IPSR_MODSEL_DATA(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1), ++ PINMUX_IPSR_MODSEL_DATA(IP5_26_24, HRX0_B, SEL_HSCIF0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1), ++ PINMUX_IPSR_DATA(IP5_29_27, DREQ0_N), ++ PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1), ++ PINMUX_IPSR_DATA(IP5_29_27, VI2_R7), ++ PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2), ++ PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_WS78_B, SEL_SSI7_1), ++ ++ PINMUX_IPSR_DATA(IP6_2_0, DACK0), ++ PINMUX_IPSR_DATA(IP6_2_0, IRQ0), ++ PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N), ++ PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1), ++ PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2), ++ PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N), ++ PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2), ++ PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1), ++ PINMUX_IPSR_DATA(IP6_8_6, DACK1), ++ PINMUX_IPSR_DATA(IP6_8_6, IRQ1), ++ PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N), ++ PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1), ++ PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2), ++ PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N), ++ PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1), ++ PINMUX_IPSR_DATA(IP6_13_11, DACK2), ++ PINMUX_IPSR_DATA(IP6_13_11, IRQ2), ++ PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N), ++ PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1), ++ PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1), ++ PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV), ++ PINMUX_IPSR_DATA(IP6_16_14, RMII_CRS_DV), ++ PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1), ++ PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3), ++ PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2), ++ PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_E, SEL_IIC2_4), ++ PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_CIS_E, SEL_I2C2_4), ++ PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER), ++ PINMUX_IPSR_DATA(IP6_19_17, RMII_RX_ER), ++ PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1), ++ PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3), ++ PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2), ++ PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_E, SEL_IIC2_4), ++ PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_CIS_E, SEL_I2C2_4), ++ PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0), ++ PINMUX_IPSR_DATA(IP6_22_20, RMII_RXD0), ++ PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1), ++ PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3), ++ PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2), ++ PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6), ++ PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4), ++ PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1), ++ PINMUX_IPSR_DATA(IP6_25_23, RMII_RXD1), ++ PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4), ++ PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1), ++ PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3), ++ PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2), ++ PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6), ++ PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4), ++ PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK), ++ PINMUX_IPSR_DATA(IP6_28_26, RMII_LINK), ++ PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4), ++ PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1), ++ PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6), ++ PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4), ++ PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK), ++ PINMUX_IPSR_DATA(IP6_31_29, RMII_REF_CLK), ++ PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4), ++ PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1), ++ PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5), ++ ++ PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO), ++ PINMUX_IPSR_DATA(IP7_2_0, RMII_MDIO), ++ PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4), ++ PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2), ++ PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5), ++ PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1), ++ PINMUX_IPSR_DATA(IP7_5_3, RMII_TXD1), ++ PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_4), ++ PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_SIM_2), ++ PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RDS_CLK_F, SEL_HSCIF0_5), ++ PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN), ++ PINMUX_IPSR_DATA(IP7_7_6, RMII_TX_EN), ++ PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2), ++ PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5), ++ PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC), ++ PINMUX_IPSR_DATA(IP7_9_8, RMII_MAGIC), ++ PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2), ++ PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0), ++ PINMUX_IPSR_DATA(IP7_12_10, RMII_TXD0), ++ PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1), ++ PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2), ++ PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2), ++ PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC), ++ PINMUX_IPSR_DATA(IP7_15_13, RMII_MDC), ++ PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1), ++ PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2), ++ PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2), ++ PINMUX_IPSR_DATA(IP7_18_16, PWM0), ++ PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2), ++ PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1), ++ PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2), ++ PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2), ++ PINMUX_IPSR_DATA(IP7_21_19, PWM1), ++ PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2), ++ PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1), ++ PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2), ++ PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2), ++ PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N), ++ PINMUX_IPSR_DATA(IP7_24_22, PWM2), ++ PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0), ++ PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2), ++ PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N), ++ PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2), ++ PINMUX_IPSR_DATA(IP7_26_25, DU1_DOTCLKIN), ++ PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC), ++ PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C), ++ PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0), ++ PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N), ++ PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1), ++ PINMUX_IPSR_DATA(IP7_28_27, MII_RXD1), ++ PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0), ++ PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N), ++ PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2), ++ PINMUX_IPSR_DATA(IP7_30_29, MII_RXD2), ++ ++ PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0), ++ PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N), ++ PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3), ++ PINMUX_IPSR_DATA(IP8_1_0, MII_RXD3), ++ PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0), ++ PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N), ++ PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4), ++ PINMUX_IPSR_MODSEL_DATA(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0), ++ PINMUX_IPSR_DATA(IP8_5_4, ATADIR0_N), ++ PINMUX_IPSR_DATA(IP8_5_4, AVB_RXD5), ++ PINMUX_IPSR_MODSEL_DATA(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0), ++ PINMUX_IPSR_DATA(IP8_7_6, ATAG0_N), ++ PINMUX_IPSR_DATA(IP8_7_6, AVB_RXD6), ++ PINMUX_IPSR_MODSEL_DATA(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0), ++ PINMUX_IPSR_DATA(IP8_9_8, EX_WAIT1), ++ PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7), ++ PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0), ++ PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER), ++ PINMUX_IPSR_DATA(IP8_11_10, MII_RX_ER), ++ PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0), ++ PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK), ++ PINMUX_IPSR_DATA(IP8_13_12, MII_RX_CLK), ++ PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0), ++ PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV), ++ PINMUX_IPSR_DATA(IP8_15_14, MII_RX_DV), ++ PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3), ++ PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS), ++ PINMUX_IPSR_DATA(IP8_17_16, MII_CRS), ++ PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3), ++ PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC), ++ PINMUX_IPSR_DATA(IP8_19_18, MII_MDC), ++ PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3), ++ PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO), ++ PINMUX_IPSR_DATA(IP8_21_20, MII_MDIO), ++ PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3), ++ PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK), ++ PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3), ++ PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC), ++ PINMUX_IPSR_DATA(IP8_25_24, MII_MAGIC), ++ PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP8_26, AVB_PHY_INT, SEL_SCIFA1_3), ++ PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0), ++ PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK), ++ PINMUX_IPSR_DATA(IP8_28, SD0_CLK), ++ PINMUX_IPSR_MODSEL_DATA(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1), ++ PINMUX_IPSR_DATA(IP8_30_29, SD0_CMD), ++ PINMUX_IPSR_MODSEL_DATA(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1), ++ ++ PINMUX_IPSR_DATA(IP9_1_0, SD0_DAT0), ++ PINMUX_IPSR_MODSEL_DATA(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1), ++ PINMUX_IPSR_DATA(IP9_3_2, SD0_DAT1), ++ PINMUX_IPSR_MODSEL_DATA(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1), ++ PINMUX_IPSR_DATA(IP9_5_4, SD0_DAT2), ++ PINMUX_IPSR_MODSEL_DATA(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1), ++ PINMUX_IPSR_DATA(IP9_7_6, SD0_DAT3), ++ PINMUX_IPSR_MODSEL_DATA(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1), ++ PINMUX_IPSR_DATA(IP9_11_8, SD0_CD), ++ PINMUX_IPSR_DATA(IP9_11_8, MMC0_D6), ++ PINMUX_IPSR_MODSEL_DATA(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1), ++ PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP), ++ PINMUX_IPSR_MODSEL_DATA(IP9_11_8, GLO_SCLK, SEL_GPS_0), ++ PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_B, SEL_IIC1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_CIS_B, SEL_I2C1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1), ++ PINMUX_IPSR_DATA(IP9_15_12, SD0_WP), ++ PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7), ++ PINMUX_IPSR_MODSEL_DATA(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1), ++ PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN), ++ PINMUX_IPSR_MODSEL_DATA(IP9_15_12, GLO_SDATA, SEL_GPS_0), ++ PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_B, SEL_IIC1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_CIS_B, SEL_I2C1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1), ++ PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK), ++ PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN), ++ PINMUX_IPSR_DATA(IP9_17_16, MII_TX_EN), ++ PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD), ++ PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER), ++ PINMUX_IPSR_DATA(IP9_19_18, MII_TX_ER), ++ PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1), ++ PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0), ++ PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK), ++ PINMUX_IPSR_DATA(IP9_21_20, MII_TX_CLK), ++ PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1), ++ PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1), ++ PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK), ++ PINMUX_IPSR_DATA(IP9_23_22, MII_LINK), ++ PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1), ++ PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2), ++ PINMUX_IPSR_DATA(IP9_25_24, AVB_COL), ++ PINMUX_IPSR_DATA(IP9_25_24, MII_COL), ++ PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1), ++ PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3), ++ PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0), ++ PINMUX_IPSR_DATA(IP9_27_26, MII_RXD0), ++ PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1), ++ PINMUX_IPSR_DATA(IP9_31_28, SD1_CD), ++ PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6), ++ PINMUX_IPSR_MODSEL_DATA(IP9_31_28, TS_SDEN1, SEL_TSIF1_0), ++ PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP), ++ PINMUX_IPSR_MODSEL_DATA(IP9_31_28, GLO_SS, SEL_GPS_0), ++ PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI0_CLK_B, SEL_VI0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_D, SEL_IIC2_3), ++ PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_CIS_D, SEL_I2C2_3), ++ PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SIM0_CLK_B, SEL_SIM_1), ++ PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI3_CLK_B, SEL_VI3_1), ++ ++ PINMUX_IPSR_DATA(IP10_3_0, SD1_WP), ++ PINMUX_IPSR_DATA(IP10_3_0, MMC1_D7), ++ PINMUX_IPSR_MODSEL_DATA(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0), ++ PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN), ++ PINMUX_IPSR_MODSEL_DATA(IP10_3_0, GLO_RFON, SEL_GPS_0), ++ PINMUX_IPSR_MODSEL_DATA(IP10_3_0, VI1_CLK_B, SEL_VI1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_D, SEL_IIC2_3), ++ PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_CIS_D, SEL_I2C2_3), ++ PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SIM0_D_B, SEL_SIM_1), ++ PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK), ++ PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK), ++ PINMUX_IPSR_MODSEL_DATA(IP10_6_4, SIM0_CLK, SEL_SIM_0), ++ PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2), ++ PINMUX_IPSR_MODSEL_DATA(IP10_6_4, GLO_SCLK_B, SEL_GPS_1), ++ PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI3_DATA0_B, SEL_VI3_1), ++ PINMUX_IPSR_DATA(IP10_10_7, SD2_CMD), ++ PINMUX_IPSR_DATA(IP10_10_7, MMC0_CMD), ++ PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SIM0_D, SEL_SIM_0), ++ PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4), ++ PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCK1_D, SEL_SCIF1_3), ++ PINMUX_IPSR_MODSEL_DATA(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2), ++ PINMUX_IPSR_MODSEL_DATA(IP10_10_7, GLO_SDATA_B, SEL_GPS_1), ++ PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI3_DATA1_B, SEL_VI3_1), ++ PINMUX_IPSR_DATA(IP10_14_11, SD2_DAT0), ++ PINMUX_IPSR_DATA(IP10_14_11, MMC0_D0), ++ PINMUX_IPSR_MODSEL_DATA(IP10_14_11, FMCLK_B, SEL_FM_1), ++ PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4), ++ PINMUX_IPSR_MODSEL_DATA(IP10_14_11, RX1_D, SEL_SCIF1_3), ++ PINMUX_IPSR_MODSEL_DATA(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2), ++ PINMUX_IPSR_MODSEL_DATA(IP10_14_11, GLO_SS_B, SEL_GPS_1), ++ PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI3_DATA2_B, SEL_VI3_1), ++ PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1), ++ PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1), ++ PINMUX_IPSR_MODSEL_DATA(IP10_18_15, FMIN_B, SEL_FM_1), ++ PINMUX_IPSR_MODSEL_DATA(IP10_18_15, RDS_DATA, SEL_RDS_0), ++ PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4), ++ PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TX1_D, SEL_SCIF1_3), ++ PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2), ++ PINMUX_IPSR_MODSEL_DATA(IP10_18_15, GLO_RFON_B, SEL_GPS_1), ++ PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI3_DATA3_B, SEL_VI3_1), ++ PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2), ++ PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2), ++ PINMUX_IPSR_MODSEL_DATA(IP10_22_19, BPFCLK_B, SEL_FM_1), ++ PINMUX_IPSR_MODSEL_DATA(IP10_22_19, RDS_CLK, SEL_RDS_0), ++ PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP10_22_19, HRX0_D, SEL_HSCIF0_3), ++ PINMUX_IPSR_MODSEL_DATA(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP10_22_19, GLO_Q0_B, SEL_GPS_1), ++ PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI3_DATA4_B, SEL_VI3_1), ++ PINMUX_IPSR_DATA(IP10_25_23, SD2_DAT3), ++ PINMUX_IPSR_DATA(IP10_25_23, MMC0_D3), ++ PINMUX_IPSR_MODSEL_DATA(IP10_25_23, SIM0_RST, SEL_SIM_0), ++ PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP10_25_23, HTX0_D, SEL_HSCIF0_3), ++ PINMUX_IPSR_MODSEL_DATA(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP10_25_23, GLO_Q1_B, SEL_GPS_1), ++ PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI3_DATA5_B, SEL_VI3_1), ++ PINMUX_IPSR_DATA(IP10_29_26, SD2_CD), ++ PINMUX_IPSR_DATA(IP10_29_26, MMC0_D4), ++ PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1), ++ PINMUX_IPSR_DATA(IP10_29_26, USB2_EXTP), ++ PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0, SEL_GPS_0), ++ PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3), ++ PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0_B, SEL_GPS_1), ++ PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI3_DATA6_B, SEL_VI3_1), ++ ++ PINMUX_IPSR_DATA(IP11_3_0, SD2_WP), ++ PINMUX_IPSR_DATA(IP11_3_0, MMC0_D5), ++ PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1), ++ PINMUX_IPSR_DATA(IP11_3_0, USB2_IDIN), ++ PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1, SEL_GPS_0), ++ PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3), ++ PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1_B, SEL_GPS_1), ++ PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI3_DATA7_B, SEL_VI3_1), ++ PINMUX_IPSR_DATA(IP11_4, SD3_CLK), ++ PINMUX_IPSR_DATA(IP11_4, MMC1_CLK), ++ PINMUX_IPSR_DATA(IP11_6_5, SD3_CMD), ++ PINMUX_IPSR_DATA(IP11_6_5, MMC1_CMD), ++ PINMUX_IPSR_DATA(IP11_6_5, MTS_N), ++ PINMUX_IPSR_DATA(IP11_8_7, SD3_DAT0), ++ PINMUX_IPSR_DATA(IP11_8_7, MMC1_D0), ++ PINMUX_IPSR_DATA(IP11_8_7, STM_N), ++ PINMUX_IPSR_DATA(IP11_10_9, SD3_DAT1), ++ PINMUX_IPSR_DATA(IP11_10_9, MMC1_D1), ++ PINMUX_IPSR_DATA(IP11_10_9, MDATA), ++ PINMUX_IPSR_DATA(IP11_12_11, SD3_DAT2), ++ PINMUX_IPSR_DATA(IP11_12_11, MMC1_D2), ++ PINMUX_IPSR_DATA(IP11_12_11, SDATA), ++ PINMUX_IPSR_DATA(IP11_14_13, SD3_DAT3), ++ PINMUX_IPSR_DATA(IP11_14_13, MMC1_D3), ++ PINMUX_IPSR_DATA(IP11_14_13, SCKZ), ++ PINMUX_IPSR_DATA(IP11_17_15, SD3_CD), ++ PINMUX_IPSR_DATA(IP11_17_15, MMC1_D4), ++ PINMUX_IPSR_MODSEL_DATA(IP11_17_15, TS_SDAT1, SEL_TSIF1_0), ++ PINMUX_IPSR_DATA(IP11_17_15, VSP), ++ PINMUX_IPSR_MODSEL_DATA(IP11_17_15, GLO_Q0, SEL_GPS_0), ++ PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SIM0_RST_B, SEL_SIM_1), ++ PINMUX_IPSR_DATA(IP11_21_18, SD3_WP), ++ PINMUX_IPSR_DATA(IP11_21_18, MMC1_D5), ++ PINMUX_IPSR_MODSEL_DATA(IP11_21_18, TS_SCK1, SEL_TSIF1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP11_21_18, GLO_Q1, SEL_GPS_0), ++ PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_C, SEL_FM_2), ++ PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_B, SEL_RDS_1), ++ PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_E, SEL_FM_4), ++ PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_D, SEL_RDS_3), ++ PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5), ++ PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_E, SEL_RDS_4), ++ PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK), ++ PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_B, SEL_IIC2_1), ++ PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_CIS_B, SEL_I2C2_1), ++ PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG), ++ PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3), ++ PINMUX_IPSR_MODSEL_DATA(IP11_26_24, RX1_C, SEL_SCIF1_2), ++ PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_B, SEL_IIC2_1), ++ PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_CIS_B, SEL_I2C2_1), ++ PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT), ++ PINMUX_IPSR_DATA(IP11_29_27, SPV_EVEN), ++ PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3), ++ PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2), ++ PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2), ++ PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RDS_CLK_B, SEL_RDS_1), ++ PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129), ++ PINMUX_IPSR_MODSEL_DATA(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1), ++ PINMUX_IPSR_DATA(IP11_31_30, MOUT0), ++ ++ PINMUX_IPSR_DATA(IP12_1_0, SSI_WS0129), ++ PINMUX_IPSR_MODSEL_DATA(IP12_1_0, CAN0_TX_B, SEL_CAN0_1), ++ PINMUX_IPSR_DATA(IP12_1_0, MOUT1), ++ PINMUX_IPSR_DATA(IP12_3_2, SSI_SDATA0), ++ PINMUX_IPSR_MODSEL_DATA(IP12_3_2, CAN0_RX_B, SEL_CAN0_1), ++ PINMUX_IPSR_DATA(IP12_3_2, MOUT2), ++ PINMUX_IPSR_DATA(IP12_5_4, SSI_SDATA1), ++ PINMUX_IPSR_MODSEL_DATA(IP12_5_4, CAN1_TX_B, SEL_CAN1_1), ++ PINMUX_IPSR_DATA(IP12_5_4, MOUT5), ++ PINMUX_IPSR_DATA(IP12_7_6, SSI_SDATA2), ++ PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_RX_B, SEL_CAN1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_TX_B, SEL_CAN1_1), ++ PINMUX_IPSR_DATA(IP12_7_6, MOUT6), ++ PINMUX_IPSR_DATA(IP12_10_8, SSI_SCK34), ++ PINMUX_IPSR_DATA(IP12_10_8, STP_OPWM_0), ++ PINMUX_IPSR_MODSEL_DATA(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0), ++ PINMUX_IPSR_MODSEL_DATA(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0), ++ PINMUX_IPSR_DATA(IP12_10_8, CAN_DEBUG_HW_TRIGGER), ++ PINMUX_IPSR_DATA(IP12_13_11, SSI_WS34), ++ PINMUX_IPSR_MODSEL_DATA(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0), ++ PINMUX_IPSR_MODSEL_DATA(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0), ++ PINMUX_IPSR_DATA(IP12_13_11, MSIOF1_SYNC), ++ PINMUX_IPSR_DATA(IP12_13_11, CAN_STEP0), ++ PINMUX_IPSR_DATA(IP12_16_14, SSI_SDATA3), ++ PINMUX_IPSR_MODSEL_DATA(IP12_16_14, STP_ISCLK_0, SEL_SSP_0), ++ PINMUX_IPSR_MODSEL_DATA(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0), ++ PINMUX_IPSR_MODSEL_DATA(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0), ++ PINMUX_IPSR_DATA(IP12_16_14, CAN_TXCLK), ++ PINMUX_IPSR_DATA(IP12_19_17, SSI_SCK4), ++ PINMUX_IPSR_MODSEL_DATA(IP12_19_17, STP_ISD_0, SEL_SSP_0), ++ PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0), ++ PINMUX_IPSR_MODSEL_DATA(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2), ++ PINMUX_IPSR_DATA(IP12_19_17, CAN_DEBUGOUT0), ++ PINMUX_IPSR_DATA(IP12_22_20, SSI_WS4), ++ PINMUX_IPSR_MODSEL_DATA(IP12_22_20, STP_ISEN_0, SEL_SSP_0), ++ PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0), ++ PINMUX_IPSR_MODSEL_DATA(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SSI_WS5_C, SEL_SSI5_2), ++ PINMUX_IPSR_DATA(IP12_22_20, CAN_DEBUGOUT1), ++ PINMUX_IPSR_DATA(IP12_24_23, SSI_SDATA4), ++ PINMUX_IPSR_MODSEL_DATA(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0), ++ PINMUX_IPSR_MODSEL_DATA(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0), ++ PINMUX_IPSR_DATA(IP12_24_23, CAN_DEBUGOUT2), ++ PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SSI_SCK5, SEL_SSI5_0), ++ PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP12_27_25, IERX_B, SEL_IEB_1), ++ PINMUX_IPSR_DATA(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC), ++ PINMUX_IPSR_DATA(IP12_27_25, QSTH_QHS), ++ PINMUX_IPSR_DATA(IP12_27_25, CAN_DEBUGOUT3), ++ PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SSI_WS5, SEL_SSI5_0), ++ PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP12_30_28, IECLK_B, SEL_IEB_1), ++ PINMUX_IPSR_DATA(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC), ++ PINMUX_IPSR_DATA(IP12_30_28, QSTB_QHE), ++ PINMUX_IPSR_DATA(IP12_30_28, CAN_DEBUGOUT4), ++ ++ PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SSI_SDATA5, SEL_SSI5_0), ++ PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP13_2_0, IETX_B, SEL_IEB_1), ++ PINMUX_IPSR_DATA(IP13_2_0, DU2_DR2), ++ PINMUX_IPSR_DATA(IP13_2_0, LCDOUT2), ++ PINMUX_IPSR_DATA(IP13_2_0, CAN_DEBUGOUT5), ++ PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SSI_SCK6, SEL_SSI6_0), ++ PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_D, SEL_FM_3), ++ PINMUX_IPSR_MODSEL_DATA(IP13_6_3, RDS_CLK_C, SEL_RDS_2), ++ PINMUX_IPSR_DATA(IP13_6_3, DU2_DR3), ++ PINMUX_IPSR_DATA(IP13_6_3, LCDOUT3), ++ PINMUX_IPSR_DATA(IP13_6_3, CAN_DEBUGOUT6), ++ PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_F, SEL_FM_5), ++ PINMUX_IPSR_MODSEL_DATA(IP13_6_3, RDS_CLK_E, SEL_RDS_4), ++ PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SSI_WS6, SEL_SSI6_0), ++ PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP13_9_7, CAN0_TX_D, SEL_CAN0_3), ++ PINMUX_IPSR_DATA(IP13_9_7, DU2_DR4), ++ PINMUX_IPSR_DATA(IP13_9_7, LCDOUT4), ++ PINMUX_IPSR_DATA(IP13_9_7, CAN_DEBUGOUT7), ++ PINMUX_IPSR_MODSEL_DATA(IP13_12_10, SSI_SDATA6, SEL_SSI6_0), ++ PINMUX_IPSR_MODSEL_DATA(IP13_12_10, FMIN_D, SEL_FM_3), ++ PINMUX_IPSR_MODSEL_DATA(IP13_12_10, RDS_DATA_C, SEL_RDS_2), ++ PINMUX_IPSR_DATA(IP13_12_10, DU2_DR5), ++ PINMUX_IPSR_DATA(IP13_12_10, LCDOUT5), ++ PINMUX_IPSR_DATA(IP13_12_10, CAN_DEBUGOUT8), ++ PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SSI_SCK78, SEL_SSI7_0), ++ PINMUX_IPSR_MODSEL_DATA(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0), ++ PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCK1, SEL_SCIF1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0), ++ PINMUX_IPSR_DATA(IP13_15_13, DU2_DR6), ++ PINMUX_IPSR_DATA(IP13_15_13, LCDOUT6), ++ PINMUX_IPSR_DATA(IP13_15_13, CAN_DEBUGOUT9), ++ PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SSI_WS78, SEL_SSI7_0), ++ PINMUX_IPSR_MODSEL_DATA(IP13_18_16, STP_ISCLK_1, SEL_SSP_0), ++ PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0), ++ PINMUX_IPSR_DATA(IP13_18_16, SCIFA2_CTS_N), ++ PINMUX_IPSR_DATA(IP13_18_16, DU2_DR7), ++ PINMUX_IPSR_DATA(IP13_18_16, LCDOUT7), ++ PINMUX_IPSR_DATA(IP13_18_16, CAN_DEBUGOUT10), ++ PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7, SEL_SSI7_0), ++ PINMUX_IPSR_MODSEL_DATA(IP13_22_19, STP_ISD_1, SEL_SSP_0), ++ PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0), ++ PINMUX_IPSR_DATA(IP13_22_19, SCIFA2_RTS_N), ++ PINMUX_IPSR_DATA(IP13_22_19, TCLK2), ++ PINMUX_IPSR_DATA(IP13_22_19, QSTVA_QVS), ++ PINMUX_IPSR_DATA(IP13_22_19, CAN_DEBUGOUT11), ++ PINMUX_IPSR_MODSEL_DATA(IP13_22_19, BPFCLK_E, SEL_FM_4), ++ PINMUX_IPSR_MODSEL_DATA(IP13_22_19, RDS_CLK_D, SEL_RDS_3), ++ PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1), ++ PINMUX_IPSR_MODSEL_DATA(IP13_22_19, FMIN_G, SEL_FM_6), ++ PINMUX_IPSR_MODSEL_DATA(IP13_22_19, RDS_DATA_F, SEL_RDS_5), ++ PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8, SEL_SSI8_0), ++ PINMUX_IPSR_MODSEL_DATA(IP13_25_23, STP_ISEN_1, SEL_SSP_0), ++ PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP13_25_23, CAN0_TX_C, SEL_CAN0_2), ++ PINMUX_IPSR_DATA(IP13_25_23, CAN_DEBUGOUT12), ++ PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1), ++ PINMUX_IPSR_DATA(IP13_28_26, SSI_SDATA9), ++ PINMUX_IPSR_MODSEL_DATA(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0), ++ PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0), ++ PINMUX_IPSR_DATA(IP13_28_26, SSI_WS1), ++ PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2), ++ PINMUX_IPSR_DATA(IP13_28_26, CAN_DEBUGOUT13), ++ PINMUX_IPSR_DATA(IP13_30_29, AUDIO_CLKA), ++ PINMUX_IPSR_MODSEL_DATA(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0), ++ PINMUX_IPSR_DATA(IP13_30_29, CAN_DEBUGOUT14), ++ ++ PINMUX_IPSR_DATA(IP14_2_0, AUDIO_CLKB), ++ PINMUX_IPSR_MODSEL_DATA(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0), ++ PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_D, SEL_CAN0_3), ++ PINMUX_IPSR_DATA(IP14_2_0, DVC_MUTE), ++ PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_C, SEL_CAN0_2), ++ PINMUX_IPSR_DATA(IP14_2_0, CAN_DEBUGOUT15), ++ PINMUX_IPSR_DATA(IP14_2_0, REMOCON), ++ PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0), ++ PINMUX_IPSR_MODSEL_DATA(IP14_5_3, HSCK1, SEL_HSCIF1_0), ++ PINMUX_IPSR_DATA(IP14_5_3, SCK0), ++ PINMUX_IPSR_DATA(IP14_5_3, MSIOF3_SS2), ++ PINMUX_IPSR_DATA(IP14_5_3, DU2_DG2), ++ PINMUX_IPSR_DATA(IP14_5_3, LCDOUT10), ++ PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SDA1_C, SEL_IIC1_2), ++ PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SDA1_CIS_C, SEL_I2C1_2), ++ PINMUX_IPSR_MODSEL_DATA(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0), ++ PINMUX_IPSR_MODSEL_DATA(IP14_8_6, HRX1, SEL_HSCIF1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP14_8_6, RX0, SEL_SCIF0_0), ++ PINMUX_IPSR_DATA(IP14_8_6, DU2_DR0), ++ PINMUX_IPSR_DATA(IP14_8_6, LCDOUT0), ++ PINMUX_IPSR_MODSEL_DATA(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0), ++ PINMUX_IPSR_MODSEL_DATA(IP14_11_9, HTX1, SEL_HSCIF1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP14_11_9, TX0, SEL_SCIF0_0), ++ PINMUX_IPSR_DATA(IP14_11_9, DU2_DR1), ++ PINMUX_IPSR_DATA(IP14_11_9, LCDOUT1), ++ PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0), ++ PINMUX_IPSR_MODSEL_DATA(IP14_15_12, HCTS1_N, SEL_HSCIF1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP14_15_12, CTS0_N, SEL_SCIF0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0), ++ PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3), ++ PINMUX_IPSR_MODSEL_DATA(IP14_15_12, LCDOUT11, SEL_HSCIF1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP14_15_12, PWM0_B, SEL_SCIF0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCL1_C, SEL_IIC1_2), ++ PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCL1_CIS_C, SEL_I2C1_2), ++ PINMUX_IPSR_MODSEL_DATA(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0), ++ PINMUX_IPSR_MODSEL_DATA(IP14_18_16, HRTS1_N, SEL_HSCIF1_0), ++ PINMUX_IPSR_DATA(IP14_18_16, RTS0_N_TANS), ++ PINMUX_IPSR_DATA(IP14_18_16, MSIOF3_SS1), ++ PINMUX_IPSR_DATA(IP14_18_16, DU2_DG0), ++ PINMUX_IPSR_DATA(IP14_18_16, LCDOUT8), ++ PINMUX_IPSR_DATA(IP14_18_16, PWM1_B), ++ PINMUX_IPSR_MODSEL_DATA(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP14_21_19, AD_DI, SEL_ADI_0), ++ PINMUX_IPSR_MODSEL_DATA(IP14_21_19, RX1, SEL_SCIF1_0), ++ PINMUX_IPSR_DATA(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE), ++ PINMUX_IPSR_DATA(IP14_21_19, QCPV_QDE), ++ PINMUX_IPSR_MODSEL_DATA(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP14_24_22, AD_DO, SEL_ADI_0), ++ PINMUX_IPSR_MODSEL_DATA(IP14_24_22, TX1, SEL_SCIF1_0), ++ PINMUX_IPSR_DATA(IP14_24_22, DU2_DG1), ++ PINMUX_IPSR_DATA(IP14_24_22, LCDOUT9), ++ PINMUX_IPSR_MODSEL_DATA(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP14_27_25, AD_CLK, SEL_ADI_0), ++ PINMUX_IPSR_DATA(IP14_27_25, CTS1_N), ++ PINMUX_IPSR_MODSEL_DATA(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0), ++ PINMUX_IPSR_DATA(IP14_27_25, DU0_DOTCLKOUT), ++ PINMUX_IPSR_DATA(IP14_27_25, QCLK), ++ PINMUX_IPSR_MODSEL_DATA(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP14_30_28, AD_NCS_N, SEL_ADI_0), ++ PINMUX_IPSR_DATA(IP14_30_28, RTS1_N_TANS), ++ PINMUX_IPSR_MODSEL_DATA(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0), ++ PINMUX_IPSR_DATA(IP14_30_28, DU1_DOTCLKOUT), ++ PINMUX_IPSR_DATA(IP14_30_28, QSTVB_QVE), ++ PINMUX_IPSR_MODSEL_DATA(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2), ++ ++ PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP15_2_0, FMCLK, SEL_FM_0), ++ PINMUX_IPSR_MODSEL_DATA(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0), ++ PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7), ++ PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15), ++ PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_0), ++ PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP15_5_3, FMIN, SEL_FM_0), ++ PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0), ++ PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16), ++ PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCL2, SEL_IIC2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCL2_CIS, SEL_I2C2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP15_8_6, BPFCLK, SEL_FM_0), ++ PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1), ++ PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17), ++ PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SDA2, SEL_IIC2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SDA2_CIS, SEL_I2C2_0), ++ PINMUX_IPSR_DATA(IP15_11_9, HSCK0), ++ PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TS_SDEN0, SEL_TSIF0_0), ++ PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4), ++ PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12), ++ PINMUX_IPSR_MODSEL_DATA(IP15_11_9, HCTS0_N_C, SEL_IIC2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SDA2_CIS, SEL_I2C2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP15_13_12, HRX0, SEL_HSCIF0_0), ++ PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2), ++ PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18), ++ PINMUX_IPSR_MODSEL_DATA(IP15_15_14, HTX0, SEL_HSCIF0_0), ++ PINMUX_IPSR_DATA(IP15_15_14, DU2_DB3), ++ PINMUX_IPSR_DATA(IP15_15_14, LCDOUT19), ++ PINMUX_IPSR_MODSEL_DATA(IP15_17_16, HCTS0_N, SEL_HSCIF0_0), ++ PINMUX_IPSR_DATA(IP15_17_16, SSI_SCK9), ++ PINMUX_IPSR_DATA(IP15_17_16, DU2_DB4), ++ PINMUX_IPSR_DATA(IP15_17_16, LCDOUT20), ++ PINMUX_IPSR_MODSEL_DATA(IP15_19_18, HRTS0_N, SEL_HSCIF0_0), ++ PINMUX_IPSR_DATA(IP15_19_18, SSI_WS9), ++ PINMUX_IPSR_DATA(IP15_19_18, DU2_DB5), ++ PINMUX_IPSR_DATA(IP15_19_18, LCDOUT21), ++ PINMUX_IPSR_MODSEL_DATA(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP15_22_20, TS_SDAT0, SEL_TSIF0_0), ++ PINMUX_IPSR_DATA(IP15_22_20, ADICLK), ++ PINMUX_IPSR_DATA(IP15_22_20, DU2_DB6), ++ PINMUX_IPSR_DATA(IP15_22_20, LCDOUT22), ++ PINMUX_IPSR_DATA(IP15_25_23, MSIOF0_SYNC), ++ PINMUX_IPSR_MODSEL_DATA(IP15_25_23, TS_SCK0, SEL_TSIF0_0), ++ PINMUX_IPSR_DATA(IP15_25_23, SSI_SCK2), ++ PINMUX_IPSR_DATA(IP15_25_23, ADIDATA), ++ PINMUX_IPSR_DATA(IP15_25_23, DU2_DB7), ++ PINMUX_IPSR_DATA(IP15_25_23, LCDOUT23), ++ PINMUX_IPSR_MODSEL_DATA(IP15_25_23, SCIFA2_RXD_B, SEL_SCIFA2_1), ++ PINMUX_IPSR_MODSEL_DATA(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0), ++ PINMUX_IPSR_DATA(IP15_27_26, ADICHS0), ++ PINMUX_IPSR_DATA(IP15_27_26, DU2_DG5), ++ PINMUX_IPSR_DATA(IP15_27_26, LCDOUT13), ++ PINMUX_IPSR_MODSEL_DATA(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0), ++ PINMUX_IPSR_DATA(IP15_29_28, ADICHS1), ++ PINMUX_IPSR_DATA(IP15_29_28, DU2_DG6), ++ PINMUX_IPSR_DATA(IP15_29_28, LCDOUT14), ++ ++ PINMUX_IPSR_MODSEL_DATA(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0), ++ PINMUX_IPSR_DATA(IP16_2_0, AUDIO_CLKOUT), ++ PINMUX_IPSR_DATA(IP16_2_0, ADICHS2), ++ PINMUX_IPSR_DATA(IP16_2_0, DU2_DISP), ++ PINMUX_IPSR_DATA(IP16_2_0, QPOLA), ++ PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HTX0_C, SEL_HSCIF0_2), ++ PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1), ++ PINMUX_IPSR_MODSEL_DATA(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0), ++ PINMUX_IPSR_DATA(IP16_5_3, SSI_WS2), ++ PINMUX_IPSR_DATA(IP16_5_3, ADICS_SAMP), ++ PINMUX_IPSR_DATA(IP16_5_3, DU2_CDE), ++ PINMUX_IPSR_DATA(IP16_5_3, QPOLB), ++ PINMUX_IPSR_MODSEL_DATA(IP16_5_3, HRX0_C, SEL_HSCIF0_2), ++ PINMUX_IPSR_DATA(IP16_6, USB1_PWEN), ++ PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D), ++ PINMUX_IPSR_DATA(IP16_7, USB1_OVC), ++ PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1), ++}; ++ ++static struct sh_pfc_pin pinmux_pins[] = { ++ PINMUX_GPIO_GP_ALL(), ++}; ++ ++#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) ++ ++static const struct pinmux_func pinmux_func_gpios[] = { ++ GPIO_FN(VI1_DATA7_VI1_B7), GPIO_FN(USB0_PWEN), GPIO_FN(USB0_OVC_VBUS), ++ GPIO_FN(USB2_PWEN), GPIO_FN(USB2_OVC), GPIO_FN(AVS1), GPIO_FN(AVS2), ++ GPIO_FN(DU_DOTCLKIN0), GPIO_FN(DU_DOTCLKIN2), ++ ++ /*IPSR0*/ ++ GPIO_FN(D1), GPIO_FN(MSIOF3_SYNC_B), GPIO_FN(VI3_DATA1), ++ GPIO_FN(VI0_G5), GPIO_FN(VI0_G5_B), GPIO_FN(D2), GPIO_FN(MSIOF3_RXD_B), ++ GPIO_FN(VI3_DATA2), GPIO_FN(VI0_G6), GPIO_FN(VI0_G6_B), GPIO_FN(D3), ++ GPIO_FN(MSIOF3_TXD_B), GPIO_FN(VI3_DATA3), GPIO_FN(VI0_G7), ++ GPIO_FN(VI0_G7_B), GPIO_FN(D4), GPIO_FN(SCIFB1_RXD_F), ++ GPIO_FN(SCIFB0_RXD_C), GPIO_FN(VI3_DATA4), GPIO_FN(VI0_R0), ++ GPIO_FN(VI0_R0_B), GPIO_FN(RX0_B), GPIO_FN(D5), GPIO_FN(SCIFB1_TXD_F), ++ GPIO_FN(SCIFB0_TXD_C), GPIO_FN(VI3_DATA5), GPIO_FN(VI0_R1), ++ GPIO_FN(VI0_R1_B), GPIO_FN(TX0_B), GPIO_FN(D6), GPIO_FN(SCL2_C), ++ GPIO_FN(VI3_DATA6), GPIO_FN(VI0_R2), GPIO_FN(VI0_R2_B), ++ GPIO_FN(SCL2_CIS_C), GPIO_FN(D7), GPIO_FN(AD_DI_B), GPIO_FN(SDA2_C), ++ GPIO_FN(VI3_DATA7), GPIO_FN(VI0_R3), GPIO_FN(VI0_R3_B), ++ GPIO_FN(SDA2_CIS_C), GPIO_FN(D8), GPIO_FN(SCIFA1_SCK_C), ++ GPIO_FN(AVB_TXD0), GPIO_FN(MII_TXD0), GPIO_FN(VI0_G0), ++ GPIO_FN(VI0_G0_B), GPIO_FN(VI2_DATA0_VI2_B0), ++ ++ /*IPSR1*/ ++ GPIO_FN(D9), GPIO_FN(SCIFA1_RXD_C), GPIO_FN(AVB_TXD1), ++ GPIO_FN(MII_TXD1), GPIO_FN(VI0_G1), GPIO_FN(VI0_G1_B), ++ GPIO_FN(VI2_DATA1_VI2_B1), GPIO_FN(D10), GPIO_FN(SCIFA1_TXD_C), ++ GPIO_FN(AVB_TXD2), GPIO_FN(MII_TXD2), GPIO_FN(VI0_G2), ++ GPIO_FN(VI0_G2_B), GPIO_FN(VI2_DATA2_VI2_B2), GPIO_FN(D11), ++ GPIO_FN(SCIFA1_CTS_N_C), GPIO_FN(AVB_TXD3), GPIO_FN(MII_TXD3), ++ GPIO_FN(VI0_G3), GPIO_FN(VI0_G3_B), GPIO_FN(VI2_DATA3_VI2_B3), ++ GPIO_FN(D12), GPIO_FN(SCIFA1_RTS_N_C), GPIO_FN(AVB_TXD4), ++ GPIO_FN(VI0_HSYNC_N), GPIO_FN(VI0_HSYNC_N_B), GPIO_FN(VI2_DATA4_VI2_B4), ++ GPIO_FN(D13), GPIO_FN(AVB_TXD5), GPIO_FN(VI0_VSYNC_N), ++ GPIO_FN(VI0_VSYNC_N_B), GPIO_FN(VI2_DATA5_VI2_B5), GPIO_FN(D14), ++ GPIO_FN(SCIFB1_RXD_C), GPIO_FN(AVB_TXD6), GPIO_FN(RX1_B), ++ GPIO_FN(VI0_CLKENB), GPIO_FN(VI0_CLKENB_B), GPIO_FN(VI2_DATA6_VI2_B6), ++ GPIO_FN(D15), GPIO_FN(SCIFB1_TXD_C), GPIO_FN(AVB_TXD7), GPIO_FN(TX1_B), ++ GPIO_FN(VI0_FIELD), GPIO_FN(VI0_FIELD_B), GPIO_FN(VI2_DATA7_VI2_B7), ++ GPIO_FN(A0), GPIO_FN(PWM3), GPIO_FN(A1), GPIO_FN(PWM4), ++ ++ /*IPSR2*/ ++ GPIO_FN(A2), GPIO_FN(PWM5), GPIO_FN(MSIOF1_SS1_B), GPIO_FN(A3), ++ GPIO_FN(PWM6), GPIO_FN(MSIOF1_SS2_B), GPIO_FN(A4), ++ GPIO_FN(MSIOF1_TXD_B), GPIO_FN(TPU0TO0), GPIO_FN(A5), ++ GPIO_FN(SCIFA1_TXD_B), GPIO_FN(TPU0TO1), GPIO_FN(A6), ++ GPIO_FN(SCIFA1_RTS_N_B), GPIO_FN(TPU0TO2), GPIO_FN(A7), ++ GPIO_FN(SCIFA1_SCK_B), GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(TPU0TO3), ++ GPIO_FN(A8), GPIO_FN(SCIFA1_RXD_B), GPIO_FN(SSI_SCK5_B), ++ GPIO_FN(VI0_R4), GPIO_FN(VI0_R4_B), GPIO_FN(SCIFB2_RXD_C), ++ GPIO_FN(VI2_DATA0_VI2_B0_B), GPIO_FN(A9), GPIO_FN(SCIFA1_CTS_N_B), ++ GPIO_FN(SSI_WS5_B), GPIO_FN(VI0_R5), GPIO_FN(VI0_R5_B), ++ GPIO_FN(SCIFB2_TXD_C), GPIO_FN(VI2_DATA1_VI2_B1_B), GPIO_FN(A10), ++ GPIO_FN(SSI_SDATA5_B), GPIO_FN(MSIOF2_SYNC), GPIO_FN(VI0_R6), ++ GPIO_FN(VI0_R6_B), GPIO_FN(VI2_DATA2_VI2_B2_B), ++ ++ /*IPSR3*/ ++ GPIO_FN(A11), GPIO_FN(SCIFB2_CTS_N_B), GPIO_FN(MSIOF2_SCK), ++ GPIO_FN(VI1_R0), GPIO_FN(VI1_R0_B), GPIO_FN(VI2_G0), ++ GPIO_FN(VI2_DATA3_VI2_B3_B), GPIO_FN(A12), GPIO_FN(SCIFB2_RXD_B), ++ GPIO_FN(MSIOF2_TXD), GPIO_FN(VI1_R1), GPIO_FN(VI1_R1_B), ++ GPIO_FN(VI2_G1), GPIO_FN(VI2_DATA4_VI2_B4_B), GPIO_FN(A13), ++ GPIO_FN(SCIFB2_RTS_N_B), GPIO_FN(EX_WAIT2), GPIO_FN(MSIOF2_RXD), ++ GPIO_FN(VI1_R2), GPIO_FN(VI1_R2_B), GPIO_FN(VI2_G2), ++ GPIO_FN(VI2_DATA5_VI2_B5_B), GPIO_FN(A14), GPIO_FN(SCIFB2_TXD_B), ++ GPIO_FN(ATACS11_N), GPIO_FN(MSIOF2_SS1), GPIO_FN(A15), ++ GPIO_FN(SCIFB2_SCK_B), GPIO_FN(ATARD1_N), GPIO_FN(MSIOF2_SS2), ++ GPIO_FN(A16), GPIO_FN(ATAWR1_N), GPIO_FN(A17), GPIO_FN(AD_DO_B), ++ GPIO_FN(ATADIR1_N), GPIO_FN(A18), GPIO_FN(AD_CLK_B), GPIO_FN(ATAG1_N), ++ GPIO_FN(A19), GPIO_FN(AD_NCS_N_B), GPIO_FN(ATACS01_N), ++ GPIO_FN(EX_WAIT0_B), GPIO_FN(A20), GPIO_FN(SPCLK), GPIO_FN(VI1_R3), ++ GPIO_FN(VI1_R3_B), GPIO_FN(VI2_G4), ++ ++ /*IPSR4*/ ++ GPIO_FN(A21), GPIO_FN(MOSI_IO0), GPIO_FN(VI1_R4), GPIO_FN(VI1_R4_B), ++ GPIO_FN(VI2_G5), GPIO_FN(A22), GPIO_FN(MISO_IO1), GPIO_FN(VI1_R5), ++ GPIO_FN(VI1_R5_B), GPIO_FN(VI2_G6), GPIO_FN(A23), GPIO_FN(IO2), ++ GPIO_FN(VI1_G7), GPIO_FN(VI1_G7_B), GPIO_FN(VI2_G7), GPIO_FN(A24), ++ GPIO_FN(IO3), GPIO_FN(VI1_R7), GPIO_FN(VI1_R7_B), GPIO_FN(VI2_CLKENB), ++ GPIO_FN(VI2_CLKENB_B), GPIO_FN(A25), GPIO_FN(SSL), GPIO_FN(VI1_G6), ++ GPIO_FN(VI1_G6_B), GPIO_FN(VI2_FIELD), GPIO_FN(VI2_FIELD_B), ++ GPIO_FN(CS0_N), GPIO_FN(VI1_R6), GPIO_FN(VI1_R6_B), GPIO_FN(VI2_G3), ++ GPIO_FN(MSIOF0_SS2_B), GPIO_FN(CS1_N_A26), GPIO_FN(SPEEDIN), ++ GPIO_FN(VI0_R7), GPIO_FN(VI0_R7_B), GPIO_FN(VI2_CLK), ++ GPIO_FN(VI2_CLK_B), GPIO_FN(EX_CS0_N), GPIO_FN(HRX1_B), ++ GPIO_FN(VI1_G5), GPIO_FN(VI1_G5_B), GPIO_FN(VI2_R0), GPIO_FN(HTX0_B), ++ GPIO_FN(MSIOF0_SS1_B), GPIO_FN(EX_CS1_N), GPIO_FN(GPS_CLK), ++ GPIO_FN(HCTS1_N_B), GPIO_FN(VI1_FIELD), GPIO_FN(VI1_FIELD_B), ++ GPIO_FN(VI2_R1), GPIO_FN(EX_CS2_N), GPIO_FN(GPS_SIGN), ++ GPIO_FN(HRTS1_N_B), GPIO_FN(VI3_CLKENB), GPIO_FN(VI1_G0), ++ GPIO_FN(VI1_G0_B), GPIO_FN(VI2_R2), ++ ++ /*IPSR5*/ ++ GPIO_FN(EX_CS3_N), GPIO_FN(GPS_MAG), GPIO_FN(VI3_FIELD), ++ GPIO_FN(VI1_G1), GPIO_FN(VI1_G1_B), GPIO_FN(VI2_R3), GPIO_FN(EX_CS4_N), ++ GPIO_FN(MSIOF1_SCK_B), GPIO_FN(VI3_HSYNC_N), GPIO_FN(VI2_HSYNC_N), ++ GPIO_FN(SCL1), GPIO_FN(VI2_HSYNC_N_B), GPIO_FN(INTC_EN0_N), ++ GPIO_FN(SCL1_CIS), GPIO_FN(EX_CS5_N), GPIO_FN(CAN0_RX), ++ GPIO_FN(MSIOF1_RXD_B), GPIO_FN(VI3_VSYNC_N), GPIO_FN(VI1_G2), ++ GPIO_FN(VI1_G2_B), GPIO_FN(VI2_R4), GPIO_FN(SDA1), GPIO_FN(INTC_EN1_N), ++ GPIO_FN(SDA1_CIS), GPIO_FN(BS_N), GPIO_FN(IETX), GPIO_FN(HTX1_B), ++ GPIO_FN(CAN1_TX), GPIO_FN(DRACK0), GPIO_FN(IETX_C), GPIO_FN(RD_N), ++ GPIO_FN(CAN0_TX), GPIO_FN(SCIFA0_SCK_B), GPIO_FN(RD_WR_N), ++ GPIO_FN(VI1_G3), GPIO_FN(VI1_G3_B), GPIO_FN(VI2_R5), ++ GPIO_FN(SCIFA0_RXD_B), GPIO_FN(INTC_IRQ4_N), GPIO_FN(WE0_N), ++ GPIO_FN(IECLK), GPIO_FN(CAN_CLK), GPIO_FN(VI2_VSYNC_N), ++ GPIO_FN(SCIFA0_TXD_B), GPIO_FN(VI2_VSYNC_N_B), GPIO_FN(WE1_N), ++ GPIO_FN(IERX), GPIO_FN(CAN1_RX), GPIO_FN(VI1_G4), GPIO_FN(VI1_G4_B), ++ GPIO_FN(VI2_R6), GPIO_FN(SCIFA0_CTS_N_B), GPIO_FN(IERX_C), ++ GPIO_FN(EX_WAIT0), GPIO_FN(IRQ3), GPIO_FN(INTC_IRQ3_N), ++ GPIO_FN(VI3_CLK), GPIO_FN(SCIFA0_RTS_N_B), GPIO_FN(HRX0_B), ++ GPIO_FN(MSIOF0_SCK_B), GPIO_FN(DREQ0_N), GPIO_FN(VI1_HSYNC_N), ++ GPIO_FN(VI1_HSYNC_N_B), GPIO_FN(VI2_R7), GPIO_FN(SSI_SCK78_C), ++ GPIO_FN(SSI_WS78_B), ++ ++ /*IPSR6*/ ++ GPIO_FN(DACK0), GPIO_FN(IRQ0), GPIO_FN(INTC_IRQ0_N), ++ GPIO_FN(SSI_SCK6_B), GPIO_FN(VI1_VSYNC_N), GPIO_FN(VI1_VSYNC_N_B), ++ GPIO_FN(SSI_WS78_C), GPIO_FN(DREQ1_N), GPIO_FN(VI1_CLKENB), ++ GPIO_FN(VI1_CLKENB_B), GPIO_FN(SSI_SDATA7_C), GPIO_FN(SSI_SCK78_B), ++ GPIO_FN(DACK1), GPIO_FN(IRQ1), GPIO_FN(INTC_IRQ1_N), GPIO_FN(SSI_WS6_B), ++ GPIO_FN(SSI_SDATA8_C), GPIO_FN(DREQ2_N), GPIO_FN(HSCK1_B), ++ GPIO_FN(HCTS0_N_B), GPIO_FN(MSIOF0_TXD_B), GPIO_FN(DACK2), ++ GPIO_FN(IRQ2), GPIO_FN(INTC_IRQ2_N), GPIO_FN(SSI_SDATA6_B), ++ GPIO_FN(HRTS0_N_B), GPIO_FN(MSIOF0_RXD_B), GPIO_FN(ETH_CRS_DV), ++ GPIO_FN(RMII_CRS_DV), GPIO_FN(STP_ISCLK_0_B), GPIO_FN(TS_SDEN0_D), ++ GPIO_FN(GLO_Q0_C), GPIO_FN(SCL2_E), GPIO_FN(SCL2_CIS_E), ++ GPIO_FN(ETH_RX_ER), GPIO_FN(RMII_RX_ER), GPIO_FN(STP_ISD_0_B), ++ GPIO_FN(TS_SPSYNC0_D), GPIO_FN(GLO_Q1_C), GPIO_FN(SDA2_E), ++ GPIO_FN(SDA2_CIS_E), GPIO_FN(ETH_RXD0), GPIO_FN(RMII_RXD0), ++ GPIO_FN(STP_ISEN_0_B), GPIO_FN(TS_SDAT0_D), GPIO_FN(GLO_I0_C), ++ GPIO_FN(SCIFB1_SCK_G), GPIO_FN(SCK1_E), GPIO_FN(ETH_RXD1), ++ GPIO_FN(RMII_RXD1), GPIO_FN(HRX0_E), GPIO_FN(STP_ISSYNC_0_B), ++ GPIO_FN(TS_SCK0_D), GPIO_FN(GLO_I1_C), GPIO_FN(SCIFB1_RXD_G), ++ GPIO_FN(RX1_E), GPIO_FN(ETH_LINK), GPIO_FN(RMII_LINK), GPIO_FN(HTX0_E), ++ GPIO_FN(STP_IVCXO27_0_B), GPIO_FN(SCIFB1_TXD_G), GPIO_FN(TX1_E), ++ GPIO_FN(ETH_REF_CLK), GPIO_FN(RMII_REF_CLK), GPIO_FN(HCTS0_N_E), ++ GPIO_FN(STP_IVCXO27_1_B), GPIO_FN(HRX0_F), ++ ++ /*IPSR7*/ ++ GPIO_FN(ETH_MDIO), GPIO_FN(RMII_MDIO), GPIO_FN(HRTS0_N_E), ++ GPIO_FN(SIM0_D_C), GPIO_FN(HCTS0_N_F), GPIO_FN(ETH_TXD1), ++ GPIO_FN(RMII_TXD1), GPIO_FN(HTX0_F), GPIO_FN(BPFCLK_G), ++ GPIO_FN(RDS_CLK_F), GPIO_FN(ETH_TX_EN), GPIO_FN(RMII_TX_EN), ++ GPIO_FN(SIM0_CLK_C), GPIO_FN(HRTS0_N_F), GPIO_FN(ETH_MAGIC), ++ GPIO_FN(RMII_MAGIC), GPIO_FN(SIM0_RST_C), GPIO_FN(ETH_TXD0), ++ GPIO_FN(RMII_TXD0), GPIO_FN(STP_ISCLK_1_B), GPIO_FN(TS_SDEN1_C), ++ GPIO_FN(GLO_SCLK_C), GPIO_FN(ETH_MDC), GPIO_FN(RMII_MDC), ++ GPIO_FN(STP_ISD_1_B), GPIO_FN(TS_SPSYNC1_C), GPIO_FN(GLO_SDATA_C), ++ GPIO_FN(PWM0), GPIO_FN(SCIFA2_SCK_C), GPIO_FN(STP_ISEN_1_B), ++ GPIO_FN(TS_SDAT1_C), GPIO_FN(GLO_SS_C), GPIO_FN(PWM1), ++ GPIO_FN(SCIFA2_TXD_C), GPIO_FN(STP_ISSYNC_1_B), GPIO_FN(TS_SCK1_C), ++ GPIO_FN(GLO_RFON_C), GPIO_FN(PCMOE_N), GPIO_FN(PWM2), GPIO_FN(PWMFSW0), ++ GPIO_FN(SCIFA2_RXD_C), GPIO_FN(PCMWE_N), GPIO_FN(IECLK_C), ++ GPIO_FN(DU1_DOTCLKIN), GPIO_FN(AUDIO_CLKC), GPIO_FN(AUDIO_CLKOUT_C), ++ GPIO_FN(VI0_CLK), GPIO_FN(ATACS00_N), GPIO_FN(AVB_RXD1), ++ GPIO_FN(MII_RXD1), GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(ATACS10_N), ++ GPIO_FN(AVB_RXD2), GPIO_FN(MII_RXD2), ++ ++ /*IPSR8*/ ++ GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(ATARD0_N), GPIO_FN(AVB_RXD3), ++ GPIO_FN(MII_RXD3), GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(ATAWR0_N), ++ GPIO_FN(AVB_RXD4), GPIO_FN(VI0_DATA3_VI0_B3), GPIO_FN(ATADIR0_N), ++ GPIO_FN(AVB_RXD5), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(ATAG0_N), ++ GPIO_FN(AVB_RXD6), GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(EX_WAIT1), ++ GPIO_FN(AVB_RXD7), GPIO_FN(VI0_DATA6_VI0_B6), GPIO_FN(AVB_RX_ER), ++ GPIO_FN(MII_RX_ER), GPIO_FN(VI0_DATA7_VI0_B7), GPIO_FN(AVB_RX_CLK), ++ GPIO_FN(MII_RX_CLK), GPIO_FN(VI1_CLK), GPIO_FN(AVB_RX_DV), ++ GPIO_FN(MII_RX_DV), GPIO_FN(VI1_DATA0_VI1_B0), GPIO_FN(SCIFA1_SCK_D), ++ GPIO_FN(AVB_CRS), GPIO_FN(MII_CRS), GPIO_FN(VI1_DATA1_VI1_B1), ++ GPIO_FN(SCIFA1_RXD_D), GPIO_FN(AVB_MDC), GPIO_FN(MII_MDC), ++ GPIO_FN(VI1_DATA2_VI1_B2), GPIO_FN(SCIFA1_TXD_D), GPIO_FN(AVB_MDIO), ++ GPIO_FN(MII_MDIO), GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(SCIFA1_CTS_N_D), ++ GPIO_FN(AVB_GTX_CLK), GPIO_FN(VI1_DATA4_VI1_B4), ++ GPIO_FN(SCIFA1_RTS_N_D), GPIO_FN(AVB_MAGIC), GPIO_FN(MII_MAGIC), ++ GPIO_FN(VI1_DATA5_VI1_B5), GPIO_FN(AVB_PHY_INT), ++ GPIO_FN(VI1_DATA6_VI1_B6), GPIO_FN(AVB_GTXREFCLK), ++ GPIO_FN(SD0_CLK), GPIO_FN(VI1_DATA0_VI1_B0_B), GPIO_FN(SD0_CMD), ++ GPIO_FN(SCIFB1_SCK_B), GPIO_FN(VI1_DATA1_VI1_B1_B), ++ ++ /*IPSR9*/ ++ GPIO_FN(SD0_DAT0), GPIO_FN(SCIFB1_RXD_B), GPIO_FN(VI1_DATA2_VI1_B2_B), ++ GPIO_FN(SD0_DAT1), GPIO_FN(SCIFB1_TXD_B), GPIO_FN(VI1_DATA3_VI1_B3_B), ++ GPIO_FN(SD0_DAT2), GPIO_FN(SCIFB1_CTS_N_B), GPIO_FN(VI1_DATA4_VI1_B4_B), ++ GPIO_FN(SD0_DAT3), GPIO_FN(SCIFB1_RTS_N_B), GPIO_FN(VI1_DATA5_VI1_B5_B), ++ GPIO_FN(SD0_CD), GPIO_FN(MMC0_D6), GPIO_FN(TS_SDEN0_B), ++ GPIO_FN(USB0_EXTP), GPIO_FN(GLO_SCLK), GPIO_FN(VI1_DATA6_VI1_B6_B), ++ GPIO_FN(SCL1_B), GPIO_FN(SCL1_CIS_B), GPIO_FN(VI2_DATA6_VI2_B6_B), ++ GPIO_FN(SD0_WP), GPIO_FN(MMC0_D7), GPIO_FN(TS_SPSYNC0_B), ++ GPIO_FN(USB0_IDIN), GPIO_FN(GLO_SDATA), GPIO_FN(VI1_DATA7_VI1_B7_B), ++ GPIO_FN(SDA1_B), GPIO_FN(SDA1_CIS_B), GPIO_FN(VI2_DATA7_VI2_B7_B), ++ GPIO_FN(SD1_CLK), GPIO_FN(AVB_TX_EN), GPIO_FN(MII_TX_EN), ++ GPIO_FN(SD1_CMD), GPIO_FN(AVB_TX_ER), GPIO_FN(MII_TX_ER), ++ GPIO_FN(SCIFB0_SCK_B), GPIO_FN(SD1_DAT0), GPIO_FN(AVB_TX_CLK), ++ GPIO_FN(MII_TX_CLK), GPIO_FN(SCIFB0_RXD_B), GPIO_FN(SD1_DAT1), ++ GPIO_FN(AVB_LINK), GPIO_FN(MII_LINK), GPIO_FN(SCIFB0_TXD_B), ++ GPIO_FN(SD1_DAT2), GPIO_FN(AVB_COL), GPIO_FN(MII_COL), ++ GPIO_FN(SCIFB0_CTS_N_B), GPIO_FN(SD1_DAT3), GPIO_FN(AVB_RXD0), ++ GPIO_FN(MII_RXD0), GPIO_FN(SCIFB0_RTS_N_B), GPIO_FN(SD1_CD), ++ GPIO_FN(MMC1_D6), GPIO_FN(TS_SDEN1), GPIO_FN(USB1_EXTP), ++ GPIO_FN(GLO_SS), GPIO_FN(VI0_CLK_B), GPIO_FN(SCL2_D), ++ GPIO_FN(SCL2_CIS_D), GPIO_FN(SIM0_CLK_B), GPIO_FN(VI3_CLK_B), ++ ++ /*IPSR10*/ ++ GPIO_FN(SD1_WP), GPIO_FN(MMC1_D7), GPIO_FN(TS_SPSYNC1), ++ GPIO_FN(USB1_IDIN), GPIO_FN(GLO_RFON), GPIO_FN(VI1_CLK_B), ++ GPIO_FN(SDA2_D), GPIO_FN(SDA2_CIS_D), GPIO_FN(SIM0_D_B), ++ GPIO_FN(SD2_CLK), GPIO_FN(MMC0_CLK), GPIO_FN(SIM0_CLK), ++ GPIO_FN(VI0_DATA0_VI0_B0_B), GPIO_FN(TS_SDEN0_C), GPIO_FN(GLO_SCLK_B), ++ GPIO_FN(VI3_DATA0_B), GPIO_FN(SD2_CMD), GPIO_FN(MMC0_CMD), ++ GPIO_FN(SIM0_D), GPIO_FN(VI0_DATA1_VI0_B1_B), GPIO_FN(SCIFB1_SCK_E), ++ GPIO_FN(SCK1_D), GPIO_FN(TS_SPSYNC0_C), GPIO_FN(GLO_SDATA_B), ++ GPIO_FN(VI3_DATA1_B), GPIO_FN(SD2_DAT0), GPIO_FN(MMC0_D0), ++ GPIO_FN(FMCLK_B), GPIO_FN(VI0_DATA2_VI0_B2_B), GPIO_FN(SCIFB1_RXD_E), ++ GPIO_FN(RX1_D), GPIO_FN(TS_SDAT0_C), GPIO_FN(GLO_SS_B), ++ GPIO_FN(VI3_DATA2_B), GPIO_FN(SD2_DAT1), GPIO_FN(MMC0_D1), ++ GPIO_FN(FMIN_B), GPIO_FN(RDS_DATA), GPIO_FN(VI0_DATA3_VI0_B3_B), ++ GPIO_FN(SCIFB1_TXD_E), GPIO_FN(TX1_D), GPIO_FN(TS_SCK0_C), ++ GPIO_FN(GLO_RFON_B), GPIO_FN(VI3_DATA3_B), GPIO_FN(SD2_DAT2), ++ GPIO_FN(MMC0_D2), GPIO_FN(BPFCLK_B), GPIO_FN(RDS_CLK), ++ GPIO_FN(VI0_DATA4_VI0_B4_B), GPIO_FN(HRX0_D), GPIO_FN(TS_SDEN1_B), ++ GPIO_FN(GLO_Q0_B), GPIO_FN(VI3_DATA4_B), GPIO_FN(SD2_DAT3), ++ GPIO_FN(MMC0_D3), GPIO_FN(SIM0_RST), GPIO_FN(VI0_DATA5_VI0_B5_B), ++ GPIO_FN(HTX0_D), GPIO_FN(TS_SPSYNC1_B), GPIO_FN(GLO_Q1_B), ++ GPIO_FN(VI3_DATA5_B), GPIO_FN(SD2_CD), GPIO_FN(MMC0_D4), ++ GPIO_FN(TS_SDAT0_B), GPIO_FN(USB2_EXTP), GPIO_FN(GLO_I0), ++ GPIO_FN(VI0_DATA6_VI0_B6_B), GPIO_FN(HCTS0_N_D), GPIO_FN(TS_SDAT1_B), ++ GPIO_FN(GLO_I0_B), GPIO_FN(VI3_DATA6_B), ++ ++ /*IPSR11*/ ++ GPIO_FN(SD2_WP), GPIO_FN(MMC0_D5), GPIO_FN(TS_SCK0_B), ++ GPIO_FN(USB2_IDIN), GPIO_FN(GLO_I1), GPIO_FN(VI0_DATA7_VI0_B7_B), ++ GPIO_FN(HRTS0_N_D), GPIO_FN(TS_SCK1_B), GPIO_FN(GLO_I1_B), ++ GPIO_FN(VI3_DATA7_B), GPIO_FN(SD3_CLK), GPIO_FN(MMC1_CLK), ++ GPIO_FN(SD3_CMD), GPIO_FN(MMC1_CMD), GPIO_FN(MTS_N), GPIO_FN(SD3_DAT0), ++ GPIO_FN(MMC1_D0), GPIO_FN(STM_N), GPIO_FN(SD3_DAT1), GPIO_FN(MMC1_D1), ++ GPIO_FN(MDATA), GPIO_FN(SD3_DAT2), GPIO_FN(MMC1_D2), GPIO_FN(SDATA), ++ GPIO_FN(SD3_DAT3), GPIO_FN(MMC1_D3), GPIO_FN(SCKZ), GPIO_FN(SD3_CD), ++ GPIO_FN(MMC1_D4), GPIO_FN(TS_SDAT1), GPIO_FN(VSP), GPIO_FN(GLO_Q0), ++ GPIO_FN(SIM0_RST_B), GPIO_FN(SD3_WP), GPIO_FN(MMC1_D5), ++ GPIO_FN(TS_SCK1), GPIO_FN(GLO_Q1), GPIO_FN(FMIN_C), GPIO_FN(RDS_DATA_B), ++ GPIO_FN(FMIN_E), GPIO_FN(RDS_DATA_D), GPIO_FN(FMIN_F), ++ GPIO_FN(RDS_DATA_E), GPIO_FN(MLB_CLK), GPIO_FN(SCL2_B), ++ GPIO_FN(SCL2_CIS_B), GPIO_FN(MLB_SIG), GPIO_FN(SCIFB1_RXD_D), ++ GPIO_FN(RX1_C), GPIO_FN(SDA2_B), GPIO_FN(SDA2_CIS_B), GPIO_FN(MLB_DAT), ++ GPIO_FN(SPV_EVEN), GPIO_FN(SCIFB1_TXD_D), GPIO_FN(TX1_C), ++ GPIO_FN(BPFCLK_C), GPIO_FN(RDS_CLK_B), GPIO_FN(SSI_SCK0129), ++ GPIO_FN(CAN_CLK_B), GPIO_FN(MOUT0), ++ ++ /*IPSR12*/ ++ GPIO_FN(SSI_WS0129), GPIO_FN(CAN0_TX_B), GPIO_FN(MOUT1), ++ GPIO_FN(SSI_SDATA0), GPIO_FN(CAN0_RX_B), GPIO_FN(MOUT2), ++ GPIO_FN(SSI_SDATA1), GPIO_FN(CAN1_TX_B), GPIO_FN(MOUT5), ++ GPIO_FN(SSI_SDATA2), GPIO_FN(CAN1_RX_B), GPIO_FN(SSI_SCK1), ++ GPIO_FN(MOUT6), GPIO_FN(SSI_SCK34), GPIO_FN(STP_OPWM_0), ++ GPIO_FN(SCIFB0_SCK), GPIO_FN(MSIOF1_SCK), GPIO_FN(CAN_DEBUG_HW_TRIGGER), ++ GPIO_FN(SSI_WS34), GPIO_FN(STP_IVCXO27_0), GPIO_FN(SCIFB0_RXD), ++ GPIO_FN(MSIOF1_SYNC), GPIO_FN(CAN_STEP0), GPIO_FN(SSI_SDATA3), ++ GPIO_FN(STP_ISCLK_0), GPIO_FN(SCIFB0_TXD), GPIO_FN(MSIOF1_SS1), ++ GPIO_FN(CAN_TXCLK), GPIO_FN(SSI_SCK4), GPIO_FN(STP_ISD_0), ++ GPIO_FN(SCIFB0_CTS_N), GPIO_FN(MSIOF1_SS2), GPIO_FN(SSI_SCK5_C), ++ GPIO_FN(CAN_DEBUGOUT0), GPIO_FN(SSI_WS4), GPIO_FN(STP_ISEN_0), ++ GPIO_FN(SCIFB0_RTS_N), GPIO_FN(MSIOF1_TXD), GPIO_FN(SSI_WS5_C), ++ GPIO_FN(CAN_DEBUGOUT1), GPIO_FN(SSI_SDATA4), GPIO_FN(STP_ISSYNC_0), ++ GPIO_FN(MSIOF1_RXD), GPIO_FN(CAN_DEBUGOUT2), GPIO_FN(SSI_SCK5), ++ GPIO_FN(SCIFB1_SCK), GPIO_FN(IERX_B), GPIO_FN(DU2_EXHSYNC_DU2_HSYNC), ++ GPIO_FN(QSTH_QHS), GPIO_FN(CAN_DEBUGOUT3), GPIO_FN(SSI_WS5), ++ GPIO_FN(SCIFB1_RXD), GPIO_FN(IECLK_B), GPIO_FN(DU2_EXVSYNC_DU2_VSYNC), ++ GPIO_FN(QSTB_QHE), GPIO_FN(CAN_DEBUGOUT4), ++ ++ /*IPSR13*/ ++ GPIO_FN(SSI_SDATA5), GPIO_FN(SCIFB1_TXD), GPIO_FN(IETX_B), ++ GPIO_FN(DU2_DR2), GPIO_FN(LCDOUT2), GPIO_FN(CAN_DEBUGOUT5), ++ GPIO_FN(SSI_SCK6), GPIO_FN(SCIFB1_CTS_N), GPIO_FN(BPFCLK_D), ++ GPIO_FN(RDS_CLK_C), GPIO_FN(DU2_DR3), GPIO_FN(LCDOUT3), ++ GPIO_FN(CAN_DEBUGOUT6), GPIO_FN(BPFCLK_F), GPIO_FN(RDS_CLK_E), ++ GPIO_FN(SSI_WS6), GPIO_FN(SCIFB1_RTS_N), GPIO_FN(CAN0_TX_D), ++ GPIO_FN(DU2_DR4), GPIO_FN(LCDOUT4), GPIO_FN(CAN_DEBUGOUT7), ++ GPIO_FN(SSI_SDATA6), GPIO_FN(FMIN_D), GPIO_FN(RDS_DATA_C), ++ GPIO_FN(DU2_DR5), GPIO_FN(LCDOUT5), GPIO_FN(CAN_DEBUGOUT8), ++ GPIO_FN(SSI_SCK78), GPIO_FN(STP_IVCXO27_1), GPIO_FN(SCK1), ++ GPIO_FN(SCIFA1_SCK), GPIO_FN(DU2_DR6), GPIO_FN(LCDOUT6), ++ GPIO_FN(CAN_DEBUGOUT9), GPIO_FN(SSI_WS78), GPIO_FN(STP_ISCLK_1), ++ GPIO_FN(SCIFB2_SCK), GPIO_FN(SCIFA2_CTS_N), GPIO_FN(DU2_DR7), ++ GPIO_FN(LCDOUT7), GPIO_FN(CAN_DEBUGOUT10), GPIO_FN(SSI_SDATA7), ++ GPIO_FN(STP_ISD_1), GPIO_FN(SCIFB2_RXD), GPIO_FN(SCIFA2_RTS_N), ++ GPIO_FN(TCLK2), GPIO_FN(QSTVA_QVS), GPIO_FN(CAN_DEBUGOUT11), ++ GPIO_FN(BPFCLK_E), GPIO_FN(RDS_CLK_D), GPIO_FN(SSI_SDATA7_B), ++ GPIO_FN(FMIN_G), GPIO_FN(RDS_DATA_F), GPIO_FN(SSI_SDATA8), ++ GPIO_FN(STP_ISEN_1), GPIO_FN(SCIFB2_TXD), GPIO_FN(CAN0_TX_C), ++ GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(SSI_SDATA8_B), GPIO_FN(SSI_SDATA9), ++ GPIO_FN(STP_ISSYNC_1), GPIO_FN(SCIFB2_CTS_N), GPIO_FN(SSI_WS1), ++ GPIO_FN(SSI_SDATA5_C), GPIO_FN(CAN_DEBUGOUT13), GPIO_FN(AUDIO_CLKA), ++ GPIO_FN(SCIFB2_RTS_N), GPIO_FN(CAN_DEBUGOUT14), ++ ++ /*IPSR14*/ ++ GPIO_FN(AUDIO_CLKB), GPIO_FN(SCIF_CLK), GPIO_FN(CAN0_RX_D), ++ GPIO_FN(DVC_MUTE), GPIO_FN(CAN0_RX_C), GPIO_FN(CAN_DEBUGOUT15), ++ GPIO_FN(REMOCON), GPIO_FN(SCIFA0_SCK), GPIO_FN(HSCK1), GPIO_FN(SCK0), ++ GPIO_FN(MSIOF3_SS2), GPIO_FN(DU2_DG2), GPIO_FN(LCDOUT10), ++ GPIO_FN(SDA1_C), GPIO_FN(SDA1_CIS_C), GPIO_FN(SCIFA0_RXD), ++ GPIO_FN(HRX1), GPIO_FN(RX0), GPIO_FN(DU2_DR0), GPIO_FN(LCDOUT0), ++ GPIO_FN(SCIFA0_TXD), GPIO_FN(HTX1), GPIO_FN(TX0), GPIO_FN(DU2_DR1), ++ GPIO_FN(LCDOUT1), GPIO_FN(SCIFA0_CTS_N), GPIO_FN(HCTS1_N), ++ GPIO_FN(CTS0_N), GPIO_FN(MSIOF3_SYNC), GPIO_FN(DU2_DG3), ++ GPIO_FN(LCDOUT11), GPIO_FN(PWM0_B), GPIO_FN(SCL1_C), ++ GPIO_FN(SCL1_CIS_C), GPIO_FN(SCIFA0_RTS_N), GPIO_FN(HRTS1_N), ++ GPIO_FN(RTS0_N_TANS), GPIO_FN(MSIOF3_SS1), GPIO_FN(DU2_DG0), ++ GPIO_FN(LCDOUT8), GPIO_FN(PWM1_B), GPIO_FN(SCIFA1_RXD), GPIO_FN(AD_DI), ++ GPIO_FN(RX1), GPIO_FN(DU2_EXODDF_DU2_ODDF_DISP_CDE), GPIO_FN(QCPV_QDE), ++ GPIO_FN(SCIFA1_TXD), GPIO_FN(AD_DO), GPIO_FN(TX1), GPIO_FN(DU2_DG1), ++ GPIO_FN(LCDOUT9), GPIO_FN(SCIFA1_CTS_N), GPIO_FN(AD_CLK), ++ GPIO_FN(CTS1_N), GPIO_FN(MSIOF3_RXD), GPIO_FN(DU0_DOTCLKOUT), ++ GPIO_FN(QCLK), GPIO_FN(SCIFA1_RTS_N), GPIO_FN(AD_NCS_N), ++ GPIO_FN(RTS1_N_TANS), GPIO_FN(MSIOF3_TXD), GPIO_FN(DU1_DOTCLKOUT), ++ GPIO_FN(QSTVB_QVE), GPIO_FN(HRTS0_N_C), ++ ++ /*IPSR15*/ ++ GPIO_FN(SCIFA2_SCK), GPIO_FN(FMCLK), GPIO_FN(MSIOF3_SCK), ++ GPIO_FN(DU2_DG7), GPIO_FN(LCDOUT15), GPIO_FN(SCIF_CLK_B), ++ GPIO_FN(SCIFA2_RXD), GPIO_FN(FMIN), GPIO_FN(DU2_DB0), ++ GPIO_FN(LCDOUT16), GPIO_FN(SCL2), GPIO_FN(SCL2_CIS), ++ GPIO_FN(SCIFA2_TXD), GPIO_FN(BPFCLK), GPIO_FN(DU2_DB1), ++ GPIO_FN(LCDOUT17), GPIO_FN(SDA2), GPIO_FN(SDA2_CIS), GPIO_FN(HSCK0), ++ GPIO_FN(TS_SDEN0), GPIO_FN(DU2_DG4), GPIO_FN(LCDOUT12), ++ GPIO_FN(HCTS0_N_C), GPIO_FN(HRX0), GPIO_FN(DU2_DB2), GPIO_FN(LCDOUT18), ++ GPIO_FN(HTX0), GPIO_FN(DU2_DB3), GPIO_FN(LCDOUT19), GPIO_FN(HCTS0_N), ++ GPIO_FN(SSI_SCK9), GPIO_FN(DU2_DB4), GPIO_FN(LCDOUT20), ++ GPIO_FN(HRTS0_N), GPIO_FN(SSI_WS9), GPIO_FN(DU2_DB5), ++ GPIO_FN(LCDOUT21), GPIO_FN(MSIOF0_SCK), GPIO_FN(TS_SDAT0), ++ GPIO_FN(ADICLK), GPIO_FN(DU2_DB6), GPIO_FN(LCDOUT22), ++ GPIO_FN(MSIOF0_SYNC), GPIO_FN(TS_SCK0), GPIO_FN(SSI_SCK2), ++ GPIO_FN(ADIDATA), GPIO_FN(DU2_DB7), GPIO_FN(LCDOUT23), ++ GPIO_FN(SCIFA2_RXD_B), GPIO_FN(MSIOF0_SS1), GPIO_FN(ADICHS0), ++ GPIO_FN(DU2_DG5), GPIO_FN(LCDOUT13), GPIO_FN(MSIOF0_TXD), ++ GPIO_FN(ADICHS1), GPIO_FN(DU2_DG6), GPIO_FN(LCDOUT14), ++ ++ /*IPSR16*/ ++ GPIO_FN(MSIOF0_SS2), GPIO_FN(AUDIO_CLKOUT), GPIO_FN(ADICHS2), ++ GPIO_FN(DU2_DISP), GPIO_FN(QPOLA), GPIO_FN(HTX0_C), ++ GPIO_FN(SCIFA2_TXD_B), GPIO_FN(MSIOF0_RXD), GPIO_FN(TS_SPSYNC0), ++ GPIO_FN(SSI_WS2), GPIO_FN(ADICS_SAMP), GPIO_FN(DU2_CDE), ++ GPIO_FN(QPOLB), GPIO_FN(HRX0_C), GPIO_FN(USB1_PWEN), ++ GPIO_FN(AUDIO_CLKOUT_D), GPIO_FN(USB1_OVC), GPIO_FN(TCLK1_B), ++}; ++ ++static struct pinmux_cfg_reg pinmux_config_regs[] = { ++ { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { ++ GP_0_31_FN, FN_IP3_17_15, ++ GP_0_30_FN, FN_IP3_14_12, ++ GP_0_29_FN, FN_IP3_11_8, ++ GP_0_28_FN, FN_IP3_7_4, ++ GP_0_27_FN, FN_IP3_3_0, ++ GP_0_26_FN, FN_IP2_28_26, ++ GP_0_25_FN, FN_IP2_25_22, ++ GP_0_24_FN, FN_IP2_21_18, ++ GP_0_23_FN, FN_IP2_17_15, ++ GP_0_22_FN, FN_IP2_14_12, ++ GP_0_21_FN, FN_IP2_11_9, ++ GP_0_20_FN, FN_IP2_8_6, ++ GP_0_19_FN, FN_IP2_5_3, ++ GP_0_18_FN, FN_IP2_2_0, ++ GP_0_17_FN, FN_IP1_29_28, ++ GP_0_16_FN, FN_IP1_27_26, ++ GP_0_15_FN, FN_IP1_25_22, ++ GP_0_14_FN, FN_IP1_21_18, ++ GP_0_13_FN, FN_IP1_17_15, ++ GP_0_12_FN, FN_IP1_14_12, ++ GP_0_11_FN, FN_IP1_11_8, ++ GP_0_10_FN, FN_IP1_7_4, ++ GP_0_9_FN, FN_IP1_3_0, ++ GP_0_8_FN, FN_IP0_30_27, ++ GP_0_7_FN, FN_IP0_26_23, ++ GP_0_6_FN, FN_IP0_22_20, ++ GP_0_5_FN, FN_IP0_19_16, ++ GP_0_4_FN, FN_IP0_15_12, ++ GP_0_3_FN, FN_IP0_11_9, ++ GP_0_2_FN, FN_IP0_8_6, ++ GP_0_1_FN, FN_IP0_5_3, ++ GP_0_0_FN, FN_IP0_2_0 } ++ }, ++ { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { ++ 0, 0, ++ 0, 0, ++ GP_1_29_FN, FN_IP6_13_11, ++ GP_1_28_FN, FN_IP6_10_9, ++ GP_1_27_FN, FN_IP6_8_6, ++ GP_1_26_FN, FN_IP6_5_3, ++ GP_1_25_FN, FN_IP6_2_0, ++ GP_1_24_FN, FN_IP5_29_27, ++ GP_1_23_FN, FN_IP5_26_24, ++ GP_1_22_FN, FN_IP5_23_21, ++ GP_1_21_FN, FN_IP5_20_18, ++ GP_1_20_FN, FN_IP5_17_15, ++ GP_1_19_FN, FN_IP5_14_13, ++ GP_1_18_FN, FN_IP5_12_10, ++ GP_1_17_FN, FN_IP5_9_6, ++ GP_1_16_FN, FN_IP5_5_3, ++ GP_1_15_FN, FN_IP5_2_0, ++ GP_1_14_FN, FN_IP4_29_27, ++ GP_1_13_FN, FN_IP4_26_24, ++ GP_1_12_FN, FN_IP4_23_21, ++ GP_1_11_FN, FN_IP4_20_18, ++ GP_1_10_FN, FN_IP4_17_15, ++ GP_1_9_FN, FN_IP4_14_12, ++ GP_1_8_FN, FN_IP4_11_9, ++ GP_1_7_FN, FN_IP4_8_6, ++ GP_1_6_FN, FN_IP4_5_3, ++ GP_1_5_FN, FN_IP4_2_0, ++ GP_1_4_FN, FN_IP3_31_29, ++ GP_1_3_FN, FN_IP3_28_26, ++ GP_1_2_FN, FN_IP3_25_23, ++ GP_1_1_FN, FN_IP3_22_20, ++ GP_1_0_FN, FN_IP3_19_18, } ++ }, ++ { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { ++ 0, 0, ++ 0, 0, ++ GP_2_29_FN, FN_IP7_15_13, ++ GP_2_28_FN, FN_IP7_12_10, ++ GP_2_27_FN, FN_IP7_9_8, ++ GP_2_26_FN, FN_IP7_7_6, ++ GP_2_25_FN, FN_IP7_5_3, ++ GP_2_24_FN, FN_IP7_2_0, ++ GP_2_23_FN, FN_IP6_31_29, ++ GP_2_22_FN, FN_IP6_28_26, ++ GP_2_21_FN, FN_IP6_25_23, ++ GP_2_20_FN, FN_IP6_22_20, ++ GP_2_19_FN, FN_IP6_19_17, ++ GP_2_18_FN, FN_IP6_16_14, ++ GP_2_17_FN, FN_VI1_DATA7_VI1_B7, ++ GP_2_16_FN, FN_IP8_27, ++ GP_2_15_FN, FN_IP8_26, ++ GP_2_14_FN, FN_IP8_25_24, ++ GP_2_13_FN, FN_IP8_23_22, ++ GP_2_12_FN, FN_IP8_21_20, ++ GP_2_11_FN, FN_IP8_19_18, ++ GP_2_10_FN, FN_IP8_17_16, ++ GP_2_9_FN, FN_IP8_15_14, ++ GP_2_8_FN, FN_IP8_13_12, ++ GP_2_7_FN, FN_IP8_11_10, ++ GP_2_6_FN, FN_IP8_9_8, ++ GP_2_5_FN, FN_IP8_7_6, ++ GP_2_4_FN, FN_IP8_5_4, ++ GP_2_3_FN, FN_IP8_3_2, ++ GP_2_2_FN, FN_IP8_1_0, ++ GP_2_1_FN, FN_IP7_30_29, ++ GP_2_0_FN, FN_IP7_28_27 } ++ }, ++ { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { ++ GP_3_31_FN, FN_IP11_21_18, ++ GP_3_30_FN, FN_IP11_17_15, ++ GP_3_29_FN, FN_IP11_14_13, ++ GP_3_28_FN, FN_IP11_12_11, ++ GP_3_27_FN, FN_IP11_10_9, ++ GP_3_26_FN, FN_IP11_8_7, ++ GP_3_25_FN, FN_IP11_6_5, ++ GP_3_24_FN, FN_IP11_4, ++ GP_3_23_FN, FN_IP11_3_0, ++ GP_3_22_FN, FN_IP10_29_26, ++ GP_3_21_FN, FN_IP10_25_23, ++ GP_3_20_FN, FN_IP10_22_19, ++ GP_3_19_FN, FN_IP10_18_15, ++ GP_3_18_FN, FN_IP10_14_11, ++ GP_3_17_FN, FN_IP10_10_7, ++ GP_3_16_FN, FN_IP10_6_4, ++ GP_3_15_FN, FN_IP10_3_0, ++ GP_3_14_FN, FN_IP9_31_28, ++ GP_3_13_FN, FN_IP9_27_26, ++ GP_3_12_FN, FN_IP9_25_24, ++ GP_3_11_FN, FN_IP9_23_22, ++ GP_3_10_FN, FN_IP9_21_20, ++ GP_3_9_FN, FN_IP9_19_18, ++ GP_3_8_FN, FN_IP9_17_16, ++ GP_3_7_FN, FN_IP9_15_12, ++ GP_3_6_FN, FN_IP9_11_8, ++ GP_3_5_FN, FN_IP9_7_6, ++ GP_3_4_FN, FN_IP9_5_4, ++ GP_3_3_FN, FN_IP9_3_2, ++ GP_3_2_FN, FN_IP9_1_0, ++ GP_3_1_FN, FN_IP8_30_29, ++ GP_3_0_FN, FN_IP8_28 } ++ }, ++ { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { ++ GP_4_31_FN, FN_IP14_18_16, ++ GP_4_30_FN, FN_IP14_15_12, ++ GP_4_29_FN, FN_IP14_11_9, ++ GP_4_28_FN, FN_IP14_8_6, ++ GP_4_27_FN, FN_IP14_5_3, ++ GP_4_26_FN, FN_IP14_2_0, ++ GP_4_25_FN, FN_IP13_30_29, ++ GP_4_24_FN, FN_IP13_28_26, ++ GP_4_23_FN, FN_IP13_25_23, ++ GP_4_22_FN, FN_IP13_22_19, ++ GP_4_21_FN, FN_IP13_18_16, ++ GP_4_20_FN, FN_IP13_15_13, ++ GP_4_19_FN, FN_IP13_12_10, ++ GP_4_18_FN, FN_IP13_9_7, ++ GP_4_17_FN, FN_IP13_6_3, ++ GP_4_16_FN, FN_IP13_2_0, ++ GP_4_15_FN, FN_IP12_30_28, ++ GP_4_14_FN, FN_IP12_27_25, ++ GP_4_13_FN, FN_IP12_24_23, ++ GP_4_12_FN, FN_IP12_22_20, ++ GP_4_11_FN, FN_IP12_19_17, ++ GP_4_10_FN, FN_IP12_16_14, ++ GP_4_9_FN, FN_IP12_13_11, ++ GP_4_8_FN, FN_IP12_10_8, ++ GP_4_7_FN, FN_IP12_7_6, ++ GP_4_6_FN, FN_IP12_5_4, ++ GP_4_5_FN, FN_IP12_3_2, ++ GP_4_4_FN, FN_IP12_1_0, ++ GP_4_3_FN, FN_IP11_31_30, ++ GP_4_2_FN, FN_IP11_29_27, ++ GP_4_1_FN, FN_IP11_26_24, ++ GP_4_0_FN, FN_IP11_23_22 } ++ }, ++ { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { ++ GP_5_31_FN, FN_IP7_24_22, ++ GP_5_30_FN, FN_IP7_21_19, ++ GP_5_29_FN, FN_IP7_18_16, ++ GP_5_28_FN, FN_DU_DOTCLKIN2, ++ GP_5_27_FN, FN_IP7_26_25, ++ GP_5_26_FN, FN_DU_DOTCLKIN0, ++ GP_5_25_FN, FN_AVS2, ++ GP_5_24_FN, FN_AVS1, ++ GP_5_23_FN, FN_USB2_OVC, ++ GP_5_22_FN, FN_USB2_PWEN, ++ GP_5_21_FN, FN_IP16_7, ++ GP_5_20_FN, FN_IP16_6, ++ GP_5_19_FN, FN_USB0_OVC_VBUS, ++ GP_5_18_FN, FN_USB0_PWEN, ++ GP_5_17_FN, FN_IP16_5_3, ++ GP_5_16_FN, FN_IP16_2_0, ++ GP_5_15_FN, FN_IP15_29_28, ++ GP_5_14_FN, FN_IP15_27_26, ++ GP_5_13_FN, FN_IP15_25_23, ++ GP_5_12_FN, FN_IP15_22_20, ++ GP_5_11_FN, FN_IP15_19_18, ++ GP_5_10_FN, FN_IP15_17_16, ++ GP_5_9_FN, FN_IP15_15_14, ++ GP_5_8_FN, FN_IP15_13_12, ++ GP_5_7_FN, FN_IP15_11_9, ++ GP_5_6_FN, FN_IP15_8_6, ++ GP_5_5_FN, FN_IP15_5_3, ++ GP_5_4_FN, FN_IP15_2_0, ++ GP_5_3_FN, FN_IP14_30_28, ++ GP_5_2_FN, FN_IP14_27_25, ++ GP_5_1_FN, FN_IP14_24_22, ++ GP_5_0_FN, FN_IP14_21_19 } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, ++ 1, 4, 4, 3, 4, 4, 3, 3, 3, 3) { ++ /* IP0_31 [1] */ ++ 0, 0, ++ /* IP0_30_27 [4] */ ++ FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, FN_MII_TXD0, ++ FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ /* IP0_26_23 [4] */ ++ FN_D7, FN_AD_DI_B, FN_SDA2_C, ++ FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_SDA2_CIS_C, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ /* IP0_22_20 [3] */ ++ FN_D6, FN_SCL2_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, ++ FN_SCL2_CIS_C, 0, 0, ++ /* IP0_19_16 [4] */ ++ FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5, ++ FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ /* IP0_15_12 [4] */ ++ FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4, ++ FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ /* IP0_11_9 [3] */ ++ FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, ++ 0, 0, 0, ++ /* IP0_8_6 [3] */ ++ FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B, ++ 0, 0, 0, ++ /* IP0_5_3 [3] */ ++ FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B, ++ 0, 0, 0, ++ /* IP0_2_0 [3] */ ++ FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B, ++ 0, 0, 0, } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, ++ 2, 2, 2, 4, 4, 3, 3, 4, 4, 4) { ++ /* IP1_31_30 [2] */ ++ 0, 0, 0, 0, ++ /* IP1_29_28 [2] */ ++ FN_A1, FN_PWM4, 0, 0, ++ /* IP1_27_26 [2] */ ++ FN_A0, FN_PWM3, 0, 0, ++ /* IP1_25_22 [4] */ ++ FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B, ++ FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ /* IP1_21_18 [4] */ ++ FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B, ++ FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ /* IP1_17_15 [3] */ ++ FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N, ++ FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, ++ 0, 0, 0, ++ /* IP1_14_12 [3] */ ++ FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4, ++ FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4, ++ 0, 0, ++ /* IP1_11_8 [4] */ ++ FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, FN_MII_TXD3, ++ FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ /* IP1_7_4 [4] */ ++ FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, FN_MII_TXD2, ++ FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ /* IP1_3_0 [4] */ ++ FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, FN_MII_TXD1, ++ FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, ++ 3, 3, 4, 4, 3, 3, 3, 3, 3, 3) { ++ /* IP2_31_29 [3] */ ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ /* IP2_28_26 [3] */ ++ FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6, ++ FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0, ++ /* IP2_25_22 [4] */ ++ FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5, ++ FN_VI0_R5_B, FN_SCIFB2_TXD_C, 0, FN_VI2_DATA1_VI2_B1_B, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ /* IP2_21_18 [4] */ ++ FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4, ++ FN_VI0_R4_B, FN_SCIFB2_RXD_C, 0, FN_VI2_DATA0_VI2_B0_B, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ /* IP2_17_15 [3] */ ++ FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3, ++ 0, 0, 0, 0, ++ /* IP2_14_12 [3] */ ++ FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0, ++ /* IP2_11_9 [3] */ ++ FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0, ++ /* IP2_8_6 [3] */ ++ FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0, ++ /* IP2_5_3 [3] */ ++ FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0, ++ /* IP2_2_0 [3] */ ++ FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, ++ 3, 3, 3, 3, 2, 3, 3, 4, 4, 4) { ++ /* IP3_31_29 [3] */ ++ FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4, ++ 0, 0, 0, ++ /* IP3_28_26 [3] */ ++ FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B, ++ 0, 0, 0, 0, ++ /* IP3_25_23 [3] */ ++ FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0, ++ /* IP3_22_20 [3] */ ++ FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0, ++ /* IP3_19_18 [2] */ ++ FN_A16, FN_ATAWR1_N, 0, 0, ++ /* IP3_17_15 [3] */ ++ FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2, ++ 0, 0, 0, 0, ++ /* IP3_14_12 [3] */ ++ FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1, ++ 0, 0, 0, 0, ++ /* IP3_11_8 [4] */ ++ FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2, ++ FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2, ++ FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0, ++ /* IP3_7_4 [4] */ ++ FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1, ++ FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ /* IP3_3_0 [4] */ ++ FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0, ++ FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, ++ 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { ++ /* IP4_31_30 [2] */ ++ 0, 0, 0, 0, ++ /* IP4_29_27 [3] */ ++ FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B, ++ FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0, ++ /* IP4_26_24 [3] */ ++ FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD, ++ FN_VI1_FIELD_B, FN_VI2_R1, 0, 0, ++ /* IP4_23_21 [3] */ ++ FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, ++ FN_HTX0_B, FN_MSIOF0_SS1_B, 0, ++ /* IP4_20_18 [3] */ ++ FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B, ++ FN_VI2_CLK, FN_VI2_CLK_B, 0, 0, ++ /* IP4_17_15 [3] */ ++ FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B, ++ 0, 0, 0, ++ /* IP4_14_12 [3] */ ++ FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD, ++ FN_VI2_FIELD_B, 0, 0, ++ /* IP4_11_9 [3] */ ++ FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB, ++ FN_VI2_CLKENB_B, 0, 0, ++ /* IP4_8_6 [3] */ ++ FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0, ++ /* IP4_5_3 [3] */ ++ FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0, ++ /* IP4_2_0 [3] */ ++ FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0, ++ } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, ++ 2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) { ++ /* IP5_31_30 [2] */ ++ 0, 0, 0, 0, ++ /* IP5_29_27 [3] */ ++ FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7, ++ FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0, ++ /* IP5_26_24 [3] */ ++ FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N, ++ FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B, ++ FN_MSIOF0_SCK_B, 0, ++ /* IP5_23_21 [3] */ ++ FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, ++ FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, ++ FN_IERX_C, 0, ++ /* IP5_20_18 [3] */ ++ FN_WE0_N, FN_IECLK, FN_CAN_CLK, ++ FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0, ++ /* IP5_17_15 [3] */ ++ FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, ++ FN_INTC_IRQ4_N, 0, 0, ++ /* IP5_14_13 [2] */ ++ FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0, ++ /* IP5_12_10 [3] */ ++ FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C, ++ 0, 0, ++ /* IP5_9_6 [4] */ ++ FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, ++ FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_SDA1, FN_INTC_EN1_N, ++ FN_SDA1_CIS, 0, 0, 0, 0, 0, 0, ++ /* IP5_5_3 [3] */ ++ FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N, ++ FN_VI2_HSYNC_N, FN_SCL1, FN_VI2_HSYNC_N_B, ++ FN_INTC_EN0_N, FN_SCL1_CIS, ++ /* IP5_2_0 [3] */ ++ FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, ++ FN_VI2_R3, 0, 0, } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, ++ 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) { ++ /* IP6_31_29 [3] */ ++ FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E, ++ FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0, ++ /* IP6_28_26 [3] */ ++ FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E, ++ FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0, ++ /* IP6_25_23 [3] */ ++ FN_ETH_RXD1, FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B, ++ FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E, ++ /* IP6_22_20 [3] */ ++ FN_ETH_RXD0, FN_RMII_RXD0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D, ++ FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0, ++ /* IP6_19_17 [3] */ ++ FN_ETH_RX_ER, FN_RMII_RX_ER, FN_STP_ISD_0_B, ++ FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_SDA2_E, FN_SDA2_CIS_E, 0, ++ /* IP6_16_14 [3] */ ++ FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B, ++ FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E, ++ FN_SCL2_CIS_E, 0, ++ /* IP6_13_11 [3] */ ++ FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, ++ FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0, ++ /* IP6_10_9 [2] */ ++ FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B, ++ /* IP6_8_6 [3] */ ++ FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B, ++ FN_SSI_SDATA8_C, 0, 0, 0, ++ /* IP6_5_3 [3] */ ++ FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, ++ FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0, ++ /* IP6_2_0 [3] */ ++ FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, ++ FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, ++ 1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) { ++ /* IP7_31 [1] */ ++ 0, 0, ++ /* IP7_30_29 [2] */ ++ FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, ++ FN_MII_RXD2, ++ /* IP7_28_27 [2] */ ++ FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1, ++ /* IP7_26_25 [2] */ ++ FN_DU1_DOTCLKIN, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0, ++ /* IP7_24_22 [3] */ ++ FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C, ++ 0, 0, 0, ++ /* IP7_21_19 [3] */ ++ FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, ++ FN_GLO_RFON_C, FN_PCMOE_N, 0, 0, ++ /* IP7_18_16 [3] */ ++ FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, ++ FN_GLO_SS_C, 0, 0, 0, ++ /* IP7_15_13 [3] */ ++ FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B, ++ FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0, ++ /* IP7_12_10 [3] */ ++ FN_ETH_TXD0, FN_RMII_TXD0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, ++ FN_GLO_SCLK_C, 0, 0, 0, ++ /* IP7_9_8 [2] */ ++ FN_ETH_MAGIC, FN_RMII_MAGIC, FN_SIM0_RST_C, 0, ++ /* IP7_7_6 [2] */ ++ FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, FN_HRTS0_N_F, ++ /* IP7_5_3 [3] */ ++ FN_ETH_TXD1, FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F, ++ 0, 0, 0, ++ /* IP7_2_0 [3] */ ++ FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E, ++ FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, ++ 1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, ++ 2, 2, 2, 2, 2, 2, 2) { ++ /* IP8_31 [1] */ ++ 0, 0, ++ /* IP8_30_29 [2] */ ++ FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0, ++ /* IP8_28 [1] */ ++ FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, ++ /* IP8_27 [1] */ ++ FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK, ++ /* IP8_26 [1] */ ++ FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT, ++ /* IP8_25_24 [2] */ ++ FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, ++ FN_AVB_MAGIC, FN_MII_MAGIC, ++ /* IP8_23_22 [2] */ ++ FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0, ++ /* IP8_21_20 [2] */ ++ FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, ++ FN_MII_MDIO, ++ /* IP8_19_18 [2] */ ++ FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC, ++ /* IP8_17_16 [2] */ ++ FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, FN_MII_CRS, ++ /* IP8_15_14 [2] */ ++ FN_VI1_CLK, FN_AVB_RX_DV, FN_MII_RX_DV, 0, ++ /* IP8_13_12 [2] */ ++ FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, FN_MII_RX_CLK, 0, ++ /* IP8_11_10 [2] */ ++ FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, FN_MII_RX_ER, 0, ++ /* IP8_9_8 [2] */ ++ FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0, ++ /* IP8_7_6 [2] */ ++ FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0, ++ /* IP8_5_4 [2] */ ++ FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0, ++ /* IP8_3_2 [2] */ ++ FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0, ++ /* IP8_1_0 [2] */ ++ FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, FN_MII_RXD3, } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, ++ 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) { ++ /* IP9_31_28 [4] */ ++ FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP, ++ FN_GLO_SS, FN_VI0_CLK_B, FN_SCL2_D, FN_SCL2_CIS_D, ++ FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0, ++ /* IP9_27_26 [2] */ ++ FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0, FN_SCIFB0_RTS_N_B, ++ /* IP9_25_24 [2] */ ++ FN_SD1_DAT2, FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B, ++ /* IP9_23_22 [2] */ ++ FN_SD1_DAT1, FN_AVB_LINK, FN_MII_LINK, FN_SCIFB0_TXD_B, ++ /* IP9_21_20 [2] */ ++ FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK, FN_SCIFB0_RXD_B, ++ /* IP9_19_18 [2] */ ++ FN_SD1_CMD, FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B, ++ /* IP9_17_16 [2] */ ++ FN_SD1_CLK, FN_AVB_TX_EN, FN_MII_TX_EN, 0, ++ /* IP9_15_12 [4] */ ++ FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, ++ FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B, ++ FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0, ++ /* IP9_11_8 [4] */ ++ FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP, ++ FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B, ++ FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0, ++ /* IP9_7_6 [2] */ ++ FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0, ++ /* IP9_5_4 [2] */ ++ FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0, ++ /* IP9_3_2 [2] */ ++ FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0, ++ /* IP9_1_0 [2] */ ++ FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, ++ 2, 4, 3, 4, 4, 4, 4, 3, 4) { ++ /* IP10_31_30 [2] */ ++ 0, 0, 0, 0, ++ /* IP10_29_26 [4] */ ++ FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0, ++ FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B, ++ FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0, ++ /* IP10_25_23 [3] */ ++ FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B, ++ FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B, ++ /* IP10_22_19 [4] */ ++ FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK, ++ FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B, ++ FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0, ++ /* IP10_18_15 [4] */ ++ FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA, ++ FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D, ++ FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B, ++ 0, 0, 0, 0, 0, 0, ++ /* IP10_14_11 [4] */ ++ FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B, ++ FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D, ++ FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B, ++ 0, 0, 0, 0, 0, 0, 0, ++ /* IP10_10_7 [4] */ ++ FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D, ++ FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D, ++ FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B, ++ 0, 0, 0, 0, 0, 0, 0, ++ /* IP10_6_4 [3] */ ++ FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK, ++ FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B, ++ FN_VI3_DATA0_B, 0, ++ /* IP10_3_0 [4] */ ++ FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, ++ FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D, ++ FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, ++ 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { ++ /* IP11_31_30 [2] */ ++ FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0, ++ /* IP11_29_27 [3] */ ++ FN_MLB_DAT, FN_SPV_EVEN, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, ++ FN_RDS_CLK_B, 0, 0, ++ /* IP11_26_24 [3] */ ++ FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B, FN_SDA2_CIS_B, ++ 0, 0, 0, ++ /* IP11_23_22 [2] */ ++ FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B, 0, ++ /* IP11_21_18 [4] */ ++ FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, ++ FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F, ++ FN_RDS_DATA_E, 0, 0, 0, 0, 0, 0, ++ /* IP11_17_15 [3] */ ++ FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1, ++ FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0, ++ /* IP11_14_13 [2] */ ++ FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0, ++ /* IP11_12_11 [2] */ ++ FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0, ++ /* IP11_10_9 [2] */ ++ FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0, ++ /* IP11_8_7 [2] */ ++ FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0, ++ /* IP11_6_5 [2] */ ++ FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0, ++ /* IP11_4 [1] */ ++ FN_SD3_CLK, FN_MMC1_CLK, ++ /* IP11_3_0 [4] */ ++ FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN, ++ FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D, ++ FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, ++ 1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) { ++ /* IP12_31 [1] */ ++ 0, 0, ++ /* IP12_30_28 [3] */ ++ FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B, ++ FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE, ++ FN_CAN_DEBUGOUT4, 0, 0, ++ /* IP12_27_25 [3] */ ++ FN_SSI_SCK5, FN_SCIFB1_SCK, ++ FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS, ++ FN_CAN_DEBUGOUT3, 0, 0, ++ /* IP12_24_23 [2] */ ++ FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD, ++ FN_CAN_DEBUGOUT2, ++ /* IP12_22_20 [3] */ ++ FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N, ++ FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0, ++ /* IP12_19_17 [3] */ ++ FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N, ++ FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0, ++ /* IP12_16_14 [3] */ ++ FN_SSI_SDATA3, FN_STP_ISCLK_0, ++ FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0, ++ /* IP12_13_11 [3] */ ++ FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC, ++ FN_CAN_STEP0, 0, 0, 0, ++ /* IP12_10_8 [3] */ ++ FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK, ++ FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0, ++ /* IP12_7_6 [2] */ ++ FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6, ++ /* IP12_5_4 [2] */ ++ FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0, ++ /* IP12_3_2 [2] */ ++ FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0, ++ /* IP12_1_0 [2] */ ++ FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, ++ 1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) { ++ /* IP13_31 [1] */ ++ 0, 0, ++ /* IP13_30_29 [2] */ ++ FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0, ++ /* IP13_28_26 [3] */ ++ FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1, ++ FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0, ++ /* IP13_25_23 [3] */ ++ FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C, ++ FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0, ++ /* IP13_22_19 [4] */ ++ FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N, ++ FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E, ++ FN_RDS_CLK_D, FN_SSI_SDATA7_B, FN_FMIN_G, FN_RDS_DATA_F, ++ 0, 0, 0, 0, ++ /* IP13_18_16 [3] */ ++ FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, ++ FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0, ++ /* IP13_15_13 [3] */ ++ FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK, ++ FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0, ++ /* IP13_12_10 [3] */ ++ FN_SSI_SDATA6, FN_FMIN_D, FN_RDS_DATA_C, FN_DU2_DR5, FN_LCDOUT5, ++ FN_CAN_DEBUGOUT8, 0, 0, ++ /* IP13_9_7 [3] */ ++ FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4, ++ FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0, ++ /* IP13_6_3 [4] */ ++ FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, FN_RDS_CLK_C, ++ FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6, ++ FN_BPFCLK_F, FN_RDS_CLK_E, 0, 0, 0, 0, 0, 0, 0, ++ /* IP13_2_0 [3] */ ++ FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2, ++ FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32, ++ 1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) { ++ /* IP14_30 [1] */ ++ 0, 0, ++ /* IP14_30_28 [3] */ ++ FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N_TANS, ++ FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE, ++ FN_HRTS0_N_C, 0, ++ /* IP14_27_25 [3] */ ++ FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD, ++ FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0, ++ /* IP14_24_22 [3] */ ++ FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1, ++ FN_LCDOUT9, 0, 0, 0, ++ /* IP14_21_19 [3] */ ++ FN_SCIFA1_RXD, FN_AD_DI, FN_RX1, ++ FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0, ++ /* IP14_18_16 [3] */ ++ FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N_TANS, ++ FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0, ++ /* IP14_15_12 [4] */ ++ FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, ++ FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_SCL1_C, FN_SCL1_CIS_C, ++ 0, 0, 0, 0, 0, 0, 0, ++ /* IP14_11_9 [3] */ ++ FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1, ++ 0, 0, 0, ++ /* IP14_8_6 [3] */ ++ FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0, ++ 0, 0, 0, ++ /* IP14_5_3 [3] */ ++ FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2, ++ FN_LCDOUT10, FN_SDA1_C, FN_SDA1_CIS_C, ++ /* IP14_2_0 [3] */ ++ FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, ++ FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, ++ FN_REMOCON, 0, } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32, ++ 2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) { ++ /* IP15_31_30 [2] */ ++ 0, 0, 0, 0, ++ /* IP15_29_28 [2] */ ++ FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14, ++ /* IP15_27_26 [2] */ ++ FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13, ++ /* IP15_25_23 [3] */ ++ FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA, ++ FN_DU2_DB7, FN_LCDOUT23, FN_SCIFA2_RXD_B, 0, ++ /* IP15_22_20 [3] */ ++ FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK, ++ FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0, ++ /* IP15_19_18 [2] */ ++ FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21, ++ /* IP15_17_16 [2] */ ++ FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20, ++ /* IP15_15_14 [2] */ ++ FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0, ++ /* IP15_13_12 [2] */ ++ FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0, ++ /* IP15_11_9 [3] */ ++ FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, ++ 0, 0, 0, ++ /* IP15_8_6 [3] */ ++ FN_SCIFA2_TXD, FN_BPFCLK, 0, FN_DU2_DB1, FN_LCDOUT17, ++ FN_SDA2, FN_SDA2_CIS, 0, ++ /* IP15_5_3 [3] */ ++ FN_SCIFA2_RXD, FN_FMIN, 0, FN_DU2_DB0, FN_LCDOUT16, ++ FN_SCL2, FN_SCL2_CIS, 0, ++ /* IP15_2_0 [3] */ ++ FN_SCIFA2_SCK, FN_FMCLK, 0, FN_MSIOF3_SCK, FN_DU2_DG7, ++ FN_LCDOUT15, FN_SCIF_CLK_B, 0, } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32, ++ 4, 4, 4, 4, 4, 4, 1, 1, 3, 3) { ++ /* IP16_31_28 [4] */ ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ /* IP16_27_24 [4] */ ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ /* IP16_23_20 [4] */ ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ /* IP16_19_16 [4] */ ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ /* IP16_15_12 [4] */ ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ /* IP16_11_8 [4] */ ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ /* IP16_7 [1] */ ++ FN_USB1_OVC, FN_TCLK1_B, ++ /* IP16_6 [1] */ ++ FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, ++ /* IP16_5_3 [3] */ ++ FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2, ++ FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_HRX0_C, 0, ++ /* IP16_2_0 [3] */ ++ FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2, ++ FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, } ++ }, ++ { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, ++ 3, 2, 2, 3, 2, 1, 1, 1, 2, 1, ++ 2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) { ++ /* SEL_SCIF1 [3] */ ++ FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, ++ FN_SEL_SCIF1_4, 0, 0, 0, ++ /* SEL_SCIFB [2] */ ++ FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0, ++ /* SEL_SCIFB2 [2] */ ++ FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0, ++ /* SEL_SCIFB1 [3] */ ++ FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, ++ FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5, ++ FN_SEL_SCIFB1_6, 0, ++ /* SEL_SCIFA1 [2] */ ++ FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, ++ FN_SEL_SCIFA1_3, ++ /* SEL_SCIF0 [1] */ ++ FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, ++ /* SEL_SCIFA [1] */ ++ FN_SEL_SCFA_0, FN_SEL_SCFA_1, ++ /* SEL_SOF1 [1] */ ++ FN_SEL_SOF1_0, FN_SEL_SOF1_1, ++ /* SEL_SSI7 [2] */ ++ FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0, ++ /* SEL_SSI6 [1] */ ++ FN_SEL_SSI6_0, FN_SEL_SSI6_1, ++ /* SEL_SSI5 [2] */ ++ FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0, ++ /* SEL_VI3 [1] */ ++ FN_SEL_VI3_0, FN_SEL_VI3_1, ++ /* SEL_VI2 [1] */ ++ FN_SEL_VI2_0, FN_SEL_VI2_1, ++ /* SEL_VI1 [1] */ ++ FN_SEL_VI1_0, FN_SEL_VI1_1, ++ /* SEL_VI0 [1] */ ++ FN_SEL_VI0_0, FN_SEL_VI0_1, ++ /* SEL_TSIF1 [2] */ ++ FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0, ++ /* RESERVED [1] */ ++ 0, 0, ++ /* SEL_LBS [1] */ ++ FN_SEL_LBS_0, FN_SEL_LBS_1, ++ /* SEL_TSIF0 [2] */ ++ FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, ++ /* SEL_SOF3 [1] */ ++ FN_SEL_SOF3_0, FN_SEL_SOF3_1, ++ /* SEL_SOF0 [1] */ ++ FN_SEL_SOF0_0, FN_SEL_SOF0_1, } ++ }, ++ { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, ++ 2, 1, 1, 1, 1, 2, 1, 2, 1, ++ 2, 1, 1, 1, 3, 3, 2, 3, 2, 2) { ++ /* RESEVED [2] */ ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ /* RESEVED [1] */ ++ 0, 0, ++ /* SEL_TMU1 [1] */ ++ FN_SEL_TMU1_0, FN_SEL_TMU1_1, ++ /* SEL_HSCIF1 [1] */ ++ FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, ++ /* SEL_SCIFCLK [1] */ ++ FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, ++ /* SEL_CAN0 [2] */ ++ FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, ++ /* SEL_CANCLK [1] */ ++ FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, ++ /* SEL_SCIFA2 [2] */ ++ FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0, ++ /* SEL_CAN1 [1] */ ++ FN_SEL_CAN1_0, FN_SEL_CAN1_1, ++ /* RESEVED [2] */ ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ /* RESEVED [1] */ ++ 0, 0, ++ /* SEL_ADI [1] */ ++ FN_SEL_ADI_0, FN_SEL_ADI_1, ++ /* SEL_SSP [1] */ ++ FN_SEL_SSP_0, FN_SEL_SSP_1, ++ /* SEL_FM [3] */ ++ FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, ++ FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0, ++ /* SEL_HSCIF0 [3] */ ++ FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, ++ FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0, ++ /* SEL_GPS [2] */ ++ FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0, ++ /* SEL_RDS [3] */ ++ FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, ++ FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5, 0, 0, ++ /* SEL_SIM [2] */ ++ FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0, ++ /* SEL_SSI8 [2] */ ++ FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, } ++ }, ++ { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, ++ 1, 1, 2, 4, 4, 2, 2, ++ 4, 2, 3, 2, 3, 2) { ++ /* SEL_IICDVFS [1] */ ++ FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, ++ /* SEL_IIC0 [1] */ ++ FN_SEL_IIC0_0, FN_SEL_IIC0_1, ++ /* RESEVED [2] */ ++ 0, 0, 0, 0, ++ /* RESEVED [4] */ ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ /* RESEVED [4] */ ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ /* RESEVED [2] */ ++ 0, 0, 0, 0, ++ /* SEL_IEB [2] */ ++ FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, ++ /* RESEVED [4] */ ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ /* RESEVED [2] */ ++ 0, 0, 0, 0, ++ /* SEL_IIC2 [3] */ ++ FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, ++ FN_SEL_IIC2_4, 0, 0, 0, ++ /* SEL_IIC1 [2] */ ++ FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0, ++ /* SEL_I2C2 [3] */ ++ FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, ++ FN_SEL_I2C2_4, 0, 0, 0, ++ /* SEL_I2C1 [2] */ ++ FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, } ++ }, ++ { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } }, ++ { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) { ++ 0, 0, ++ 0, 0, ++ GP_1_29_IN, GP_1_29_OUT, ++ GP_1_28_IN, GP_1_28_OUT, ++ GP_1_27_IN, GP_1_27_OUT, ++ GP_1_26_IN, GP_1_26_OUT, ++ GP_1_25_IN, GP_1_25_OUT, ++ GP_1_24_IN, GP_1_24_OUT, ++ GP_1_23_IN, GP_1_23_OUT, ++ GP_1_22_IN, GP_1_22_OUT, ++ GP_1_21_IN, GP_1_21_OUT, ++ GP_1_20_IN, GP_1_20_OUT, ++ GP_1_19_IN, GP_1_19_OUT, ++ GP_1_18_IN, GP_1_18_OUT, ++ GP_1_17_IN, GP_1_17_OUT, ++ GP_1_16_IN, GP_1_16_OUT, ++ GP_1_15_IN, GP_1_15_OUT, ++ GP_1_14_IN, GP_1_14_OUT, ++ GP_1_13_IN, GP_1_13_OUT, ++ GP_1_12_IN, GP_1_12_OUT, ++ GP_1_11_IN, GP_1_11_OUT, ++ GP_1_10_IN, GP_1_10_OUT, ++ GP_1_9_IN, GP_1_9_OUT, ++ GP_1_8_IN, GP_1_8_OUT, ++ GP_1_7_IN, GP_1_7_OUT, ++ GP_1_6_IN, GP_1_6_OUT, ++ GP_1_5_IN, GP_1_5_OUT, ++ GP_1_4_IN, GP_1_4_OUT, ++ GP_1_3_IN, GP_1_3_OUT, ++ GP_1_2_IN, GP_1_2_OUT, ++ GP_1_1_IN, GP_1_1_OUT, ++ GP_1_0_IN, GP_1_0_OUT, } ++ }, ++ { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { ++ 0, 0, ++ 0, 0, ++ GP_2_29_IN, GP_2_29_OUT, ++ GP_2_28_IN, GP_2_28_OUT, ++ GP_2_27_IN, GP_2_27_OUT, ++ GP_2_26_IN, GP_2_26_OUT, ++ GP_2_25_IN, GP_2_25_OUT, ++ GP_2_24_IN, GP_2_24_OUT, ++ GP_2_23_IN, GP_2_23_OUT, ++ GP_2_22_IN, GP_2_22_OUT, ++ GP_2_21_IN, GP_2_21_OUT, ++ GP_2_20_IN, GP_2_20_OUT, ++ GP_2_19_IN, GP_2_19_OUT, ++ GP_2_18_IN, GP_2_18_OUT, ++ GP_2_17_IN, GP_2_17_OUT, ++ GP_2_16_IN, GP_2_16_OUT, ++ GP_2_15_IN, GP_2_15_OUT, ++ GP_2_14_IN, GP_2_14_OUT, ++ GP_2_13_IN, GP_2_13_OUT, ++ GP_2_12_IN, GP_2_12_OUT, ++ GP_2_11_IN, GP_2_11_OUT, ++ GP_2_10_IN, GP_2_10_OUT, ++ GP_2_9_IN, GP_2_9_OUT, ++ GP_2_8_IN, GP_2_8_OUT, ++ GP_2_7_IN, GP_2_7_OUT, ++ GP_2_6_IN, GP_2_6_OUT, ++ GP_2_5_IN, GP_2_5_OUT, ++ GP_2_4_IN, GP_2_4_OUT, ++ GP_2_3_IN, GP_2_3_OUT, ++ GP_2_2_IN, GP_2_2_OUT, ++ GP_2_1_IN, GP_2_1_OUT, ++ GP_2_0_IN, GP_2_0_OUT, } ++ }, ++ { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } }, ++ { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } }, ++ { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { GP_INOUTSEL(5) } }, ++ { }, ++}; ++ ++static const struct pinmux_data_reg pinmux_data_regs[] = { ++ { PINMUX_DATA_REG("INDT0", 0xE605000C, 32) { GP_INDT(0) } }, ++ { PINMUX_DATA_REG("INDT1", 0xE605100C, 32) { ++ 0, 0, GP_1_29_DATA, GP_1_28_DATA, ++ GP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA, ++ GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA, ++ GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA, ++ GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA, ++ GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA, ++ GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA, ++ GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA } ++ }, ++ { PINMUX_DATA_REG("INDT2", 0xE605200C, 32) { ++ 0, 0, GP_2_29_DATA, GP_2_28_DATA, ++ GP_2_27_DATA, GP_2_26_DATA, GP_2_25_DATA, GP_2_24_DATA, ++ GP_2_23_DATA, GP_2_22_DATA, GP_2_21_DATA, GP_2_20_DATA, ++ GP_2_19_DATA, GP_2_18_DATA, GP_2_17_DATA, GP_2_16_DATA, ++ GP_2_15_DATA, GP_2_14_DATA, GP_2_13_DATA, GP_2_12_DATA, ++ GP_2_11_DATA, GP_2_10_DATA, GP_2_9_DATA, GP_2_8_DATA, ++ GP_2_7_DATA, GP_2_6_DATA, GP_2_5_DATA, GP_2_4_DATA, ++ GP_2_3_DATA, GP_2_2_DATA, GP_2_1_DATA, GP_2_0_DATA } ++ }, ++ { PINMUX_DATA_REG("INDT3", 0xE605300C, 32) { GP_INDT(3) } }, ++ { PINMUX_DATA_REG("INDT4", 0xE605400C, 32) { GP_INDT(4) } }, ++ { PINMUX_DATA_REG("INDT5", 0xE605500C, 32) { GP_INDT(5) } }, ++ { }, ++}; ++ ++const struct sh_pfc_soc_info r8a7790_pinmux_info = { ++ .name = "r8a77900_pfc", ++ .unlock_reg = 0xe6060000, /* PMMR */ ++ ++ .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, ++ .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, ++ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, ++ ++ .pins = pinmux_pins, ++ .nr_pins = ARRAY_SIZE(pinmux_pins), ++ ++ .func_gpios = pinmux_func_gpios, ++ .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), ++ ++ .cfg_regs = pinmux_config_regs, ++ .data_regs = pinmux_data_regs, ++ ++ .gpio_data = pinmux_data, ++ .gpio_data_size = ARRAY_SIZE(pinmux_data), ++}; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0083-sh-pfc-Add-entries-for-INTC-external-IRQs.patch b/patches.renesas/0083-sh-pfc-Add-entries-for-INTC-external-IRQs.patch new file mode 100644 index 00000000000..472d2569f92 --- /dev/null +++ b/patches.renesas/0083-sh-pfc-Add-entries-for-INTC-external-IRQs.patch @@ -0,0 +1,225 @@ +From c4b0c01eea61158526425c27055bb8b4b471b5f2 Mon Sep 17 00:00:00 2001 +From: Bastian Hecht <hechtb@gmail.com> +Date: Tue, 9 Apr 2013 10:48:50 +0000 +Subject: sh-pfc: Add entries for INTC external IRQs + +We add all necessary entries to support the external IRQs from the INTC. + +Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 09bbc1fd031da5a9c2550b334eb06df86ab537c2) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 174 +++++++++++++++++++++++++++++++++++ + 1 file changed, 174 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +index bbd87d29..d95040c3 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +@@ -30,6 +30,22 @@ + PORT_10(fn, pfx##20, sfx), \ + PORT_1(fn, pfx##210, sfx), PORT_1(fn, pfx##211, sfx) + ++#define IRQC_PIN_MUX(irq, pin) \ ++static const unsigned int intc_irq##irq##_pins[] = { \ ++ pin, \ ++}; \ ++static const unsigned int intc_irq##irq##_mux[] = { \ ++ IRQ##irq##_MARK, \ ++} ++ ++#define IRQC_PINS_MUX(irq, idx, pin) \ ++static const unsigned int intc_irq##irq##_##idx##_pins[] = { \ ++ pin, \ ++}; \ ++static const unsigned int intc_irq##irq##_##idx##_mux[] = { \ ++ IRQ##irq##_PORT##pin##_MARK, \ ++} ++ + enum { + PINMUX_RESERVED = 0, + +@@ -1658,6 +1674,59 @@ static struct sh_pfc_pin pinmux_pins[] = { + GPIO_PORT_ALL(), + }; + ++/* - INTC ------------------------------------------------------------------- */ ++IRQC_PINS_MUX(0, 0, 2); ++IRQC_PINS_MUX(0, 1, 13); ++IRQC_PIN_MUX(1, 20); ++IRQC_PINS_MUX(2, 0, 11); ++IRQC_PINS_MUX(2, 1, 12); ++IRQC_PINS_MUX(3, 0, 10); ++IRQC_PINS_MUX(3, 1, 14); ++IRQC_PINS_MUX(4, 0, 15); ++IRQC_PINS_MUX(4, 1, 172); ++IRQC_PINS_MUX(5, 0, 0); ++IRQC_PINS_MUX(5, 1, 1); ++IRQC_PINS_MUX(6, 0, 121); ++IRQC_PINS_MUX(6, 1, 173); ++IRQC_PINS_MUX(7, 0, 120); ++IRQC_PINS_MUX(7, 1, 209); ++IRQC_PIN_MUX(8, 119); ++IRQC_PINS_MUX(9, 0, 118); ++IRQC_PINS_MUX(9, 1, 210); ++IRQC_PIN_MUX(10, 19); ++IRQC_PIN_MUX(11, 104); ++IRQC_PINS_MUX(12, 0, 42); ++IRQC_PINS_MUX(12, 1, 97); ++IRQC_PINS_MUX(13, 0, 64); ++IRQC_PINS_MUX(13, 1, 98); ++IRQC_PINS_MUX(14, 0, 63); ++IRQC_PINS_MUX(14, 1, 99); ++IRQC_PINS_MUX(15, 0, 62); ++IRQC_PINS_MUX(15, 1, 100); ++IRQC_PINS_MUX(16, 0, 68); ++IRQC_PINS_MUX(16, 1, 211); ++IRQC_PIN_MUX(17, 69); ++IRQC_PIN_MUX(18, 70); ++IRQC_PIN_MUX(19, 71); ++IRQC_PIN_MUX(20, 67); ++IRQC_PIN_MUX(21, 202); ++IRQC_PIN_MUX(22, 95); ++IRQC_PIN_MUX(23, 96); ++IRQC_PIN_MUX(24, 180); ++IRQC_PIN_MUX(25, 38); ++IRQC_PINS_MUX(26, 0, 58); ++IRQC_PINS_MUX(26, 1, 81); ++IRQC_PINS_MUX(27, 0, 57); ++IRQC_PINS_MUX(27, 1, 168); ++IRQC_PINS_MUX(28, 0, 56); ++IRQC_PINS_MUX(28, 1, 169); ++IRQC_PINS_MUX(29, 0, 50); ++IRQC_PINS_MUX(29, 1, 170); ++IRQC_PINS_MUX(30, 0, 49); ++IRQC_PINS_MUX(30, 1, 171); ++IRQC_PINS_MUX(31, 0, 41); ++IRQC_PINS_MUX(31, 1, 167); ++ + /* - LCD0 ------------------------------------------------------------------- */ + static const unsigned int lcd0_data8_pins[] = { + /* D[0:7] */ +@@ -2054,6 +2123,57 @@ static const unsigned int sdhi2_wp_1_mux[] = { + }; + + static const struct sh_pfc_pin_group pinmux_groups[] = { ++ SH_PFC_PIN_GROUP(intc_irq0_0), ++ SH_PFC_PIN_GROUP(intc_irq0_1), ++ SH_PFC_PIN_GROUP(intc_irq1), ++ SH_PFC_PIN_GROUP(intc_irq2_0), ++ SH_PFC_PIN_GROUP(intc_irq2_1), ++ SH_PFC_PIN_GROUP(intc_irq3_0), ++ SH_PFC_PIN_GROUP(intc_irq3_1), ++ SH_PFC_PIN_GROUP(intc_irq4_0), ++ SH_PFC_PIN_GROUP(intc_irq4_1), ++ SH_PFC_PIN_GROUP(intc_irq5_0), ++ SH_PFC_PIN_GROUP(intc_irq5_1), ++ SH_PFC_PIN_GROUP(intc_irq6_0), ++ SH_PFC_PIN_GROUP(intc_irq6_1), ++ SH_PFC_PIN_GROUP(intc_irq7_0), ++ SH_PFC_PIN_GROUP(intc_irq7_1), ++ SH_PFC_PIN_GROUP(intc_irq8), ++ SH_PFC_PIN_GROUP(intc_irq9_0), ++ SH_PFC_PIN_GROUP(intc_irq9_1), ++ SH_PFC_PIN_GROUP(intc_irq10), ++ SH_PFC_PIN_GROUP(intc_irq11), ++ SH_PFC_PIN_GROUP(intc_irq12_0), ++ SH_PFC_PIN_GROUP(intc_irq12_1), ++ SH_PFC_PIN_GROUP(intc_irq13_0), ++ SH_PFC_PIN_GROUP(intc_irq13_1), ++ SH_PFC_PIN_GROUP(intc_irq14_0), ++ SH_PFC_PIN_GROUP(intc_irq14_1), ++ SH_PFC_PIN_GROUP(intc_irq15_0), ++ SH_PFC_PIN_GROUP(intc_irq15_1), ++ SH_PFC_PIN_GROUP(intc_irq16_0), ++ SH_PFC_PIN_GROUP(intc_irq16_1), ++ SH_PFC_PIN_GROUP(intc_irq17), ++ SH_PFC_PIN_GROUP(intc_irq18), ++ SH_PFC_PIN_GROUP(intc_irq19), ++ SH_PFC_PIN_GROUP(intc_irq20), ++ SH_PFC_PIN_GROUP(intc_irq21), ++ SH_PFC_PIN_GROUP(intc_irq22), ++ SH_PFC_PIN_GROUP(intc_irq23), ++ SH_PFC_PIN_GROUP(intc_irq24), ++ SH_PFC_PIN_GROUP(intc_irq25), ++ SH_PFC_PIN_GROUP(intc_irq26_0), ++ SH_PFC_PIN_GROUP(intc_irq26_1), ++ SH_PFC_PIN_GROUP(intc_irq27_0), ++ SH_PFC_PIN_GROUP(intc_irq27_1), ++ SH_PFC_PIN_GROUP(intc_irq28_0), ++ SH_PFC_PIN_GROUP(intc_irq28_1), ++ SH_PFC_PIN_GROUP(intc_irq29_0), ++ SH_PFC_PIN_GROUP(intc_irq29_1), ++ SH_PFC_PIN_GROUP(intc_irq30_0), ++ SH_PFC_PIN_GROUP(intc_irq30_1), ++ SH_PFC_PIN_GROUP(intc_irq31_0), ++ SH_PFC_PIN_GROUP(intc_irq31_1), + SH_PFC_PIN_GROUP(lcd0_data8), + SH_PFC_PIN_GROUP(lcd0_data9), + SH_PFC_PIN_GROUP(lcd0_data12), +@@ -2103,6 +2223,60 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(sdhi2_wp_1), + }; + ++static const char * const intc_groups[] = { ++ "intc_irq0_0", ++ "intc_irq0_1", ++ "intc_irq1", ++ "intc_irq2_0", ++ "intc_irq2_1", ++ "intc_irq3_0", ++ "intc_irq3_1", ++ "intc_irq4_0", ++ "intc_irq4_1", ++ "intc_irq5_0", ++ "intc_irq5_1", ++ "intc_irq6_0", ++ "intc_irq6_1", ++ "intc_irq7_0", ++ "intc_irq7_1", ++ "intc_irq8", ++ "intc_irq9_0", ++ "intc_irq9_1", ++ "intc_irq10", ++ "intc_irq11", ++ "intc_irq12_0", ++ "intc_irq12_1", ++ "intc_irq13_0", ++ "intc_irq13_1", ++ "intc_irq14_0", ++ "intc_irq14_1", ++ "intc_irq15_0", ++ "intc_irq15_1", ++ "intc_irq16_0", ++ "intc_irq16_1", ++ "intc_irq17", ++ "intc_irq18", ++ "intc_irq19", ++ "intc_irq20", ++ "intc_irq21", ++ "intc_irq22", ++ "intc_irq23", ++ "intc_irq24", ++ "intc_irq25", ++ "intc_irq26_0", ++ "intc_irq26_1", ++ "intc_irq27_0", ++ "intc_irq27_1", ++ "intc_irq28_0", ++ "intc_irq28_1", ++ "intc_irq29_0", ++ "intc_irq29_1", ++ "intc_irq30_0", ++ "intc_irq30_1", ++ "intc_irq31_0", ++ "intc_irq31_1", ++}; ++ + static const char * const lcd0_groups[] = { + "lcd0_data8", + "lcd0_data9", +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0084-sh-pfc-Remove-dependency-on-GPIOLIB.patch b/patches.renesas/0084-sh-pfc-Remove-dependency-on-GPIOLIB.patch new file mode 100644 index 00000000000..0e374a973fa --- /dev/null +++ b/patches.renesas/0084-sh-pfc-Remove-dependency-on-GPIOLIB.patch @@ -0,0 +1,60 @@ +From 076c833527deb3c60f9bad786f4011ec7f1ca4a0 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 9 Apr 2013 14:06:01 +0000 +Subject: sh-pfc: Remove dependency on GPIOLIB + +Make GPIO support optional for platforms that don't support GPIOLIB. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Acked-by: Linus Walleij <linus.walleij@linaro.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit bf9f0674e39ee2070d39c2bd2febef42c31b3fc0) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/Kconfig | 2 -- + drivers/pinctrl/sh-pfc/core.h | 1 + + drivers/pinctrl/sh-pfc/sh_pfc.h | 2 +- + 3 files changed, 2 insertions(+), 3 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig +index 9f0217bc..a0b6bd0b 100644 +--- a/drivers/pinctrl/sh-pfc/Kconfig ++++ b/drivers/pinctrl/sh-pfc/Kconfig +@@ -5,8 +5,6 @@ + if ARCH_SHMOBILE || SUPERH + + config PINCTRL_SH_PFC +- # XXX move off the gpio dependency +- depends on GPIOLIB + select GPIO_SH_PFC if ARCH_REQUIRE_GPIOLIB + select PINMUX + select PINCONF +diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h +index ee4a4d6d..6ec746f0 100644 +--- a/drivers/pinctrl/sh-pfc/core.h ++++ b/drivers/pinctrl/sh-pfc/core.h +@@ -11,6 +11,7 @@ + #define __SH_PFC_CORE_H__ + + #include <linux/compiler.h> ++#include <linux/spinlock.h> + #include <linux/types.h> + + #include "sh_pfc.h" +diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h +index 3b785fc4..b1707612 100644 +--- a/drivers/pinctrl/sh-pfc/sh_pfc.h ++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h +@@ -11,8 +11,8 @@ + #ifndef __SH_PFC_H + #define __SH_PFC_H + ++#include <linux/bug.h> + #include <linux/stringify.h> +-#include <asm-generic/gpio.h> + + typedef unsigned short pinmux_enum_t; + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0085-sh-pfc-r8a7790-Add-ETH-pin-groups-and-functions.patch b/patches.renesas/0085-sh-pfc-r8a7790-Add-ETH-pin-groups-and-functions.patch new file mode 100644 index 00000000000..3a57ee56470 --- /dev/null +++ b/patches.renesas/0085-sh-pfc-r8a7790-Add-ETH-pin-groups-and-functions.patch @@ -0,0 +1,100 @@ +From 37cd52b1eb0ea1a225aba81817d9986fe38a1c6b Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 8 Apr 2013 11:36:14 +0200 +Subject: sh-pfc: r8a7790: Add ETH pin groups and functions + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 1627769b5f9c7f0d966e01655764f8e487515342) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 58 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 58 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +index 42b0c551..3774242c 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -20,7 +20,10 @@ + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ ++ + #include <linux/kernel.h> ++#include <linux/platform_data/gpio-rcar.h> ++ + #include <mach/r8a7790.h> + + #include "core.h" +@@ -1820,6 +1823,57 @@ static struct sh_pfc_pin pinmux_pins[] = { + PINMUX_GPIO_GP_ALL(), + }; + ++/* - ETH -------------------------------------------------------------------- */ ++static const unsigned int eth_link_pins[] = { ++ /* LINK */ ++ RCAR_GP_PIN(2, 22), ++}; ++static const unsigned int eth_link_mux[] = { ++ ETH_LINK_MARK, ++}; ++static const unsigned int eth_magic_pins[] = { ++ /* MAGIC */ ++ RCAR_GP_PIN(2, 27), ++}; ++static const unsigned int eth_magic_mux[] = { ++ ETH_MAGIC_MARK, ++}; ++static const unsigned int eth_mdio_pins[] = { ++ /* MDC, MDIO */ ++ RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24), ++}; ++static const unsigned int eth_mdio_mux[] = { ++ ETH_MDC_MARK, ETH_MDIO_MARK, ++}; ++static const unsigned int eth_rmii_pins[] = { ++ /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */ ++ RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19), ++ RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25), ++ RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23), ++}; ++static const unsigned int eth_rmii_mux[] = { ++ ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, ++ ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK, ++}; ++ ++static const struct sh_pfc_pin_group pinmux_groups[] = { ++ SH_PFC_PIN_GROUP(eth_link), ++ SH_PFC_PIN_GROUP(eth_magic), ++ SH_PFC_PIN_GROUP(eth_mdio), ++ SH_PFC_PIN_GROUP(eth_rmii), ++}; ++ ++static const char * const eth_groups[] = { ++ "eth_link", ++ "eth_magic", ++ "eth_mdio", ++ "eth_rmii", ++}; ++ ++static const struct sh_pfc_function pinmux_functions[] = { ++ SH_PFC_FUNCTION(eth), ++}; ++ + #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) + + static const struct pinmux_func pinmux_func_gpios[] = { +@@ -3226,6 +3280,10 @@ const struct sh_pfc_soc_info r8a7790_pinmux_info = { + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), ++ .groups = pinmux_groups, ++ .nr_groups = ARRAY_SIZE(pinmux_groups), ++ .functions = pinmux_functions, ++ .nr_functions = ARRAY_SIZE(pinmux_functions), + + .func_gpios = pinmux_func_gpios, + .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0086-sh-pfc-r8a7790-Add-INTC-pin-groups-and-functions.patch b/patches.renesas/0086-sh-pfc-r8a7790-Add-INTC-pin-groups-and-functions.patch new file mode 100644 index 00000000000..ffb85d8b26b --- /dev/null +++ b/patches.renesas/0086-sh-pfc-r8a7790-Add-INTC-pin-groups-and-functions.patch @@ -0,0 +1,82 @@ +From 26a42554be9475f48f382fabbe5529f359e3c162 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 8 Apr 2013 11:36:15 +0200 +Subject: sh-pfc: r8a7790: Add INTC pin groups and functions + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 04e7ce78e096e37cf98c98b7787d5287559cf504) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 40 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 40 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +index 3774242c..a92b2046 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -1855,12 +1855,45 @@ static const unsigned int eth_rmii_mux[] = { + ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, + ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK, + }; ++/* - INTC ------------------------------------------------------------------- */ ++static const unsigned int intc_irq0_pins[] = { ++ /* IRQ */ ++ RCAR_GP_PIN(1, 25), ++}; ++static const unsigned int intc_irq0_mux[] = { ++ IRQ0_MARK, ++}; ++static const unsigned int intc_irq1_pins[] = { ++ /* IRQ */ ++ RCAR_GP_PIN(1, 27), ++}; ++static const unsigned int intc_irq1_mux[] = { ++ IRQ1_MARK, ++}; ++static const unsigned int intc_irq2_pins[] = { ++ /* IRQ */ ++ RCAR_GP_PIN(1, 29), ++}; ++static const unsigned int intc_irq2_mux[] = { ++ IRQ2_MARK, ++}; ++static const unsigned int intc_irq3_pins[] = { ++ /* IRQ */ ++ RCAR_GP_PIN(1, 23), ++}; ++static const unsigned int intc_irq3_mux[] = { ++ IRQ3_MARK, ++}; + + static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(eth_link), + SH_PFC_PIN_GROUP(eth_magic), + SH_PFC_PIN_GROUP(eth_mdio), + SH_PFC_PIN_GROUP(eth_rmii), ++ SH_PFC_PIN_GROUP(intc_irq0), ++ SH_PFC_PIN_GROUP(intc_irq1), ++ SH_PFC_PIN_GROUP(intc_irq2), ++ SH_PFC_PIN_GROUP(intc_irq3), + }; + + static const char * const eth_groups[] = { +@@ -1870,8 +1903,15 @@ static const char * const eth_groups[] = { + "eth_rmii", + }; + ++static const char * const intc_groups[] = { ++ "intc_irq0", ++ "intc_irq1", ++ "intc_irq2", ++ "intc_irq3", ++}; + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(eth), ++ SH_PFC_FUNCTION(intc), + }; + + #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0087-sh-pfc-r8a7790-Add-SCIF-SCIFA-and-SCIFB-pin-groups-a.patch b/patches.renesas/0087-sh-pfc-r8a7790-Add-SCIF-SCIFA-and-SCIFB-pin-groups-a.patch new file mode 100644 index 00000000000..56bbdc33636 --- /dev/null +++ b/patches.renesas/0087-sh-pfc-r8a7790-Add-SCIF-SCIFA-and-SCIFB-pin-groups-a.patch @@ -0,0 +1,661 @@ +From 793454928960472cf91976cbd8675ebbd26fdbd2 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 8 Apr 2013 11:36:16 +0200 +Subject: sh-pfc: r8a7790: Add SCIF, SCIFA and SCIFB pin groups and functions + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 45c6c85d13e68875ebea60c3ee694750f3f132c0) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 617 +++++++++++++++++++++++++++++++++++ + 1 file changed, 617 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +index a92b2046..54c1e10a 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -1884,6 +1884,462 @@ static const unsigned int intc_irq3_pins[] = { + static const unsigned int intc_irq3_mux[] = { + IRQ3_MARK, + }; ++/* - SCIF0 ----------------------------------------------------------------- */ ++static const unsigned int scif0_data_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), ++}; ++static const unsigned int scif0_data_mux[] = { ++ RX0_MARK, TX0_MARK, ++}; ++static const unsigned int scif0_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(4, 27), ++}; ++static const unsigned int scif0_clk_mux[] = { ++ SCK0_MARK, ++}; ++static const unsigned int scif0_ctrl_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), ++}; ++static const unsigned int scif0_ctrl_mux[] = { ++ RTS0_N_TANS_MARK, CTS0_N_MARK, ++}; ++static const unsigned int scif0_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), ++}; ++static const unsigned int scif0_data_b_mux[] = { ++ RX0_B_MARK, TX0_B_MARK, ++}; ++/* - SCIF1 ----------------------------------------------------------------- */ ++static const unsigned int scif1_data_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), ++}; ++static const unsigned int scif1_data_mux[] = { ++ RX1_MARK, TX1_MARK, ++}; ++static const unsigned int scif1_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(4, 20), ++}; ++static const unsigned int scif1_clk_mux[] = { ++ SCK1_MARK, ++}; ++static const unsigned int scif1_ctrl_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2), ++}; ++static const unsigned int scif1_ctrl_mux[] = { ++ RTS1_N_TANS_MARK, CTS1_N_MARK, ++}; ++static const unsigned int scif1_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), ++}; ++static const unsigned int scif1_data_b_mux[] = { ++ RX1_B_MARK, TX1_B_MARK, ++}; ++static const unsigned int scif1_data_c_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), ++}; ++static const unsigned int scif1_data_c_mux[] = { ++ RX1_C_MARK, TX1_C_MARK, ++}; ++static const unsigned int scif1_data_d_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), ++}; ++static const unsigned int scif1_data_d_mux[] = { ++ RX1_D_MARK, TX1_D_MARK, ++}; ++static const unsigned int scif1_clk_d_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(3, 17), ++}; ++static const unsigned int scif1_clk_d_mux[] = { ++ SCK1_D_MARK, ++}; ++static const unsigned int scif1_data_e_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), ++}; ++static const unsigned int scif1_data_e_mux[] = { ++ RX1_E_MARK, TX1_E_MARK, ++}; ++static const unsigned int scif1_clk_e_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(2, 20), ++}; ++static const unsigned int scif1_clk_e_mux[] = { ++ SCK1_E_MARK, ++}; ++/* - SCIFA0 ----------------------------------------------------------------- */ ++static const unsigned int scifa0_data_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), ++}; ++static const unsigned int scifa0_data_mux[] = { ++ SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, ++}; ++static const unsigned int scifa0_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(4, 27), ++}; ++static const unsigned int scifa0_clk_mux[] = { ++ SCIFA0_SCK_MARK, ++}; ++static const unsigned int scifa0_ctrl_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), ++}; ++static const unsigned int scifa0_ctrl_mux[] = { ++ SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK, ++}; ++static const unsigned int scifa0_data_b_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21), ++}; ++static const unsigned int scifa0_data_b_mux[] = { ++ SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK ++}; ++static const unsigned int scifa0_clk_b_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(1, 19), ++}; ++static const unsigned int scifa0_clk_b_mux[] = { ++ SCIFA0_SCK_B_MARK, ++}; ++static const unsigned int scifa0_ctrl_b_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), ++}; ++static const unsigned int scifa0_ctrl_b_mux[] = { ++ SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK, ++}; ++/* - SCIFA1 ----------------------------------------------------------------- */ ++static const unsigned int scifa1_data_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), ++}; ++static const unsigned int scifa1_data_mux[] = { ++ SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, ++}; ++static const unsigned int scifa1_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(4, 20), ++}; ++static const unsigned int scifa1_clk_mux[] = { ++ SCIFA1_SCK_MARK, ++}; ++static const unsigned int scifa1_ctrl_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2), ++}; ++static const unsigned int scifa1_ctrl_mux[] = { ++ SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK, ++}; ++static const unsigned int scifa1_data_b_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21), ++}; ++static const unsigned int scifa1_data_b_mux[] = { ++ SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK, ++}; ++static const unsigned int scifa1_clk_b_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(0, 23), ++}; ++static const unsigned int scifa1_clk_b_mux[] = { ++ SCIFA1_SCK_B_MARK, ++}; ++static const unsigned int scifa1_ctrl_b_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25), ++}; ++static const unsigned int scifa1_ctrl_b_mux[] = { ++ SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK, ++}; ++static const unsigned int scifa1_data_c_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), ++}; ++static const unsigned int scifa1_data_c_mux[] = { ++ SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK, ++}; ++static const unsigned int scifa1_clk_c_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(0, 8), ++}; ++static const unsigned int scifa1_clk_c_mux[] = { ++ SCIFA1_SCK_C_MARK, ++}; ++static const unsigned int scifa1_ctrl_c_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), ++}; ++static const unsigned int scifa1_ctrl_c_mux[] = { ++ SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK, ++}; ++static const unsigned int scifa1_data_d_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), ++}; ++static const unsigned int scifa1_data_d_mux[] = { ++ SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK, ++}; ++static const unsigned int scifa1_clk_d_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(2, 10), ++}; ++static const unsigned int scifa1_clk_d_mux[] = { ++ SCIFA1_SCK_D_MARK, ++}; ++static const unsigned int scifa1_ctrl_d_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), ++}; ++static const unsigned int scifa1_ctrl_d_mux[] = { ++ SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK, ++}; ++/* - SCIFA2 ----------------------------------------------------------------- */ ++static const unsigned int scifa2_data_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), ++}; ++static const unsigned int scifa2_data_mux[] = { ++ SCIFA2_RXD_MARK, SCIFA2_TXD_MARK, ++}; ++static const unsigned int scifa2_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(5, 4), ++}; ++static const unsigned int scifa2_clk_mux[] = { ++ SCIFA2_SCK_MARK, ++}; ++static const unsigned int scifa2_ctrl_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), ++}; ++static const unsigned int scifa2_ctrl_mux[] = { ++ SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK, ++}; ++static const unsigned int scifa2_data_b_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16), ++}; ++static const unsigned int scifa2_data_b_mux[] = { ++ SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK, ++}; ++static const unsigned int scifa2_data_c_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30), ++}; ++static const unsigned int scifa2_data_c_mux[] = { ++ SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK, ++}; ++static const unsigned int scifa2_clk_c_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(5, 29), ++}; ++static const unsigned int scifa2_clk_c_mux[] = { ++ SCIFA2_SCK_C_MARK, ++}; ++/* - SCIFB0 ----------------------------------------------------------------- */ ++static const unsigned int scifb0_data_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), ++}; ++static const unsigned int scifb0_data_mux[] = { ++ SCIFB0_RXD_MARK, SCIFB0_TXD_MARK, ++}; ++static const unsigned int scifb0_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(4, 8), ++}; ++static const unsigned int scifb0_clk_mux[] = { ++ SCIFB0_SCK_MARK, ++}; ++static const unsigned int scifb0_ctrl_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), ++}; ++static const unsigned int scifb0_ctrl_mux[] = { ++ SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK, ++}; ++static const unsigned int scifb0_data_b_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), ++}; ++static const unsigned int scifb0_data_b_mux[] = { ++ SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK, ++}; ++static const unsigned int scifb0_clk_b_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(3, 9), ++}; ++static const unsigned int scifb0_clk_b_mux[] = { ++ SCIFB0_SCK_B_MARK, ++}; ++static const unsigned int scifb0_ctrl_b_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), ++}; ++static const unsigned int scifb0_ctrl_b_mux[] = { ++ SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK, ++}; ++static const unsigned int scifb0_data_c_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), ++}; ++static const unsigned int scifb0_data_c_mux[] = { ++ SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK, ++}; ++/* - SCIFB1 ----------------------------------------------------------------- */ ++static const unsigned int scifb1_data_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), ++}; ++static const unsigned int scifb1_data_mux[] = { ++ SCIFB1_RXD_MARK, SCIFB1_TXD_MARK, ++}; ++static const unsigned int scifb1_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(4, 14), ++}; ++static const unsigned int scifb1_clk_mux[] = { ++ SCIFB1_SCK_MARK, ++}; ++static const unsigned int scifb1_ctrl_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), ++}; ++static const unsigned int scifb1_ctrl_mux[] = { ++ SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK, ++}; ++static const unsigned int scifb1_data_b_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), ++}; ++static const unsigned int scifb1_data_b_mux[] = { ++ SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK, ++}; ++static const unsigned int scifb1_clk_b_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(3, 1), ++}; ++static const unsigned int scifb1_clk_b_mux[] = { ++ SCIFB1_SCK_B_MARK, ++}; ++static const unsigned int scifb1_ctrl_b_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4), ++}; ++static const unsigned int scifb1_ctrl_b_mux[] = { ++ SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK, ++}; ++static const unsigned int scifb1_data_c_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), ++}; ++static const unsigned int scifb1_data_c_mux[] = { ++ SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK, ++}; ++static const unsigned int scifb1_data_d_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), ++}; ++static const unsigned int scifb1_data_d_mux[] = { ++ SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK, ++}; ++static const unsigned int scifb1_data_e_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), ++}; ++static const unsigned int scifb1_data_e_mux[] = { ++ SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK, ++}; ++static const unsigned int scifb1_clk_e_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(3, 17), ++}; ++static const unsigned int scifb1_clk_e_mux[] = { ++ SCIFB1_SCK_E_MARK, ++}; ++static const unsigned int scifb1_data_f_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), ++}; ++static const unsigned int scifb1_data_f_mux[] = { ++ SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK, ++}; ++static const unsigned int scifb1_data_g_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), ++}; ++static const unsigned int scifb1_data_g_mux[] = { ++ SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK, ++}; ++static const unsigned int scifb1_clk_g_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(2, 20), ++}; ++static const unsigned int scifb1_clk_g_mux[] = { ++ SCIFB1_SCK_G_MARK, ++}; ++/* - SCIFB2 ----------------------------------------------------------------- */ ++static const unsigned int scifb2_data_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), ++}; ++static const unsigned int scifb2_data_mux[] = { ++ SCIFB2_RXD_MARK, SCIFB2_TXD_MARK, ++}; ++static const unsigned int scifb2_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(4, 21), ++}; ++static const unsigned int scifb2_clk_mux[] = { ++ SCIFB2_SCK_MARK, ++}; ++static const unsigned int scifb2_ctrl_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), ++}; ++static const unsigned int scifb2_ctrl_mux[] = { ++ SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK, ++}; ++static const unsigned int scifb2_data_b_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30), ++}; ++static const unsigned int scifb2_data_b_mux[] = { ++ SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK, ++}; ++static const unsigned int scifb2_clk_b_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(0, 31), ++}; ++static const unsigned int scifb2_clk_b_mux[] = { ++ SCIFB2_SCK_B_MARK, ++}; ++static const unsigned int scifb2_ctrl_b_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27), ++}; ++static const unsigned int scifb2_ctrl_b_mux[] = { ++ SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK, ++}; ++static const unsigned int scifb2_data_c_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), ++}; ++static const unsigned int scifb2_data_c_mux[] = { ++ SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK, ++}; + + static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(eth_link), +@@ -1894,6 +2350,70 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(intc_irq1), + SH_PFC_PIN_GROUP(intc_irq2), + SH_PFC_PIN_GROUP(intc_irq3), ++ SH_PFC_PIN_GROUP(scif0_data), ++ SH_PFC_PIN_GROUP(scif0_clk), ++ SH_PFC_PIN_GROUP(scif0_ctrl), ++ SH_PFC_PIN_GROUP(scif0_data_b), ++ SH_PFC_PIN_GROUP(scif1_data), ++ SH_PFC_PIN_GROUP(scif1_clk), ++ SH_PFC_PIN_GROUP(scif1_ctrl), ++ SH_PFC_PIN_GROUP(scif1_data_b), ++ SH_PFC_PIN_GROUP(scif1_data_c), ++ SH_PFC_PIN_GROUP(scif1_data_d), ++ SH_PFC_PIN_GROUP(scif1_clk_d), ++ SH_PFC_PIN_GROUP(scif1_data_e), ++ SH_PFC_PIN_GROUP(scif1_clk_e), ++ SH_PFC_PIN_GROUP(scifa0_data), ++ SH_PFC_PIN_GROUP(scifa0_clk), ++ SH_PFC_PIN_GROUP(scifa0_ctrl), ++ SH_PFC_PIN_GROUP(scifa0_data_b), ++ SH_PFC_PIN_GROUP(scifa0_clk_b), ++ SH_PFC_PIN_GROUP(scifa0_ctrl_b), ++ SH_PFC_PIN_GROUP(scifa1_data), ++ SH_PFC_PIN_GROUP(scifa1_clk), ++ SH_PFC_PIN_GROUP(scifa1_ctrl), ++ SH_PFC_PIN_GROUP(scifa1_data_b), ++ SH_PFC_PIN_GROUP(scifa1_clk_b), ++ SH_PFC_PIN_GROUP(scifa1_ctrl_b), ++ SH_PFC_PIN_GROUP(scifa1_data_c), ++ SH_PFC_PIN_GROUP(scifa1_clk_c), ++ SH_PFC_PIN_GROUP(scifa1_ctrl_c), ++ SH_PFC_PIN_GROUP(scifa1_data_d), ++ SH_PFC_PIN_GROUP(scifa1_clk_d), ++ SH_PFC_PIN_GROUP(scifa1_ctrl_d), ++ SH_PFC_PIN_GROUP(scifa2_data), ++ SH_PFC_PIN_GROUP(scifa2_clk), ++ SH_PFC_PIN_GROUP(scifa2_ctrl), ++ SH_PFC_PIN_GROUP(scifa2_data_b), ++ SH_PFC_PIN_GROUP(scifa2_data_c), ++ SH_PFC_PIN_GROUP(scifa2_clk_c), ++ SH_PFC_PIN_GROUP(scifb0_data), ++ SH_PFC_PIN_GROUP(scifb0_clk), ++ SH_PFC_PIN_GROUP(scifb0_ctrl), ++ SH_PFC_PIN_GROUP(scifb0_data_b), ++ SH_PFC_PIN_GROUP(scifb0_clk_b), ++ SH_PFC_PIN_GROUP(scifb0_ctrl_b), ++ SH_PFC_PIN_GROUP(scifb0_data_c), ++ SH_PFC_PIN_GROUP(scifb1_data), ++ SH_PFC_PIN_GROUP(scifb1_clk), ++ SH_PFC_PIN_GROUP(scifb1_ctrl), ++ SH_PFC_PIN_GROUP(scifb1_data_b), ++ SH_PFC_PIN_GROUP(scifb1_clk_b), ++ SH_PFC_PIN_GROUP(scifb1_ctrl_b), ++ SH_PFC_PIN_GROUP(scifb1_data_c), ++ SH_PFC_PIN_GROUP(scifb1_data_d), ++ SH_PFC_PIN_GROUP(scifb1_data_e), ++ SH_PFC_PIN_GROUP(scifb1_clk_e), ++ SH_PFC_PIN_GROUP(scifb1_data_f), ++ SH_PFC_PIN_GROUP(scifb1_data_g), ++ SH_PFC_PIN_GROUP(scifb1_clk_g), ++ SH_PFC_PIN_GROUP(scifb2_data), ++ SH_PFC_PIN_GROUP(scifb2_clk), ++ SH_PFC_PIN_GROUP(scifb2_ctrl), ++ SH_PFC_PIN_GROUP(scifb2_data_b), ++ SH_PFC_PIN_GROUP(scifb2_clk_b), ++ SH_PFC_PIN_GROUP(scifb2_ctrl_b), ++ SH_PFC_PIN_GROUP(scifb2_data_c), + }; + + static const char * const eth_groups[] = { +@@ -1909,9 +2429,106 @@ static const char * const intc_groups[] = { + "intc_irq2", + "intc_irq3", + }; ++ ++static const char * const scif0_groups[] = { ++ "scif0_data", ++ "scif0_clk", ++ "scif0_ctrl", ++ "scif0_data_b", ++}; ++ ++static const char * const scif1_groups[] = { ++ "scif1_data", ++ "scif1_clk", ++ "scif1_ctrl", ++ "scif1_data_b", ++ "scif1_data_c", ++ "scif1_data_d", ++ "scif1_clk_d", ++ "scif1_data_e", ++ "scif1_clk_e", ++}; ++ ++static const char * const scifa0_groups[] = { ++ "scifa0_data", ++ "scifa0_clk", ++ "scifa0_ctrl", ++ "scifa0_data_b", ++ "scifa0_clk_b", ++ "scifa0_ctrl_b", ++}; ++ ++static const char * const scifa1_groups[] = { ++ "scifa1_data", ++ "scifa1_clk", ++ "scifa1_ctrl", ++ "scifa1_data_b", ++ "scifa1_clk_b", ++ "scifa1_ctrl_b", ++ "scifa1_data_c", ++ "scifa1_clk_c", ++ "scifa1_ctrl_c", ++ "scifa1_data_d", ++ "scifa1_clk_d", ++ "scifa1_ctrl_d", ++}; ++ ++static const char * const scifa2_groups[] = { ++ "scifa2_data", ++ "scifa2_clk", ++ "scifa2_ctrl", ++ "scifa2_data_b", ++ "scifa2_data_c", ++ "scifa2_clk_c", ++}; ++ ++static const char * const scifb0_groups[] = { ++ "scifb0_data", ++ "scifb0_clk", ++ "scifb0_ctrl", ++ "scifb0_data_b", ++ "scifb0_clk_b", ++ "scifb0_ctrl_b", ++ "scifb0_data_c", ++}; ++ ++static const char * const scifb1_groups[] = { ++ "scifb1_data", ++ "scifb1_clk", ++ "scifb1_ctrl", ++ "scifb1_data_b", ++ "scifb1_clk_b", ++ "scifb1_ctrl_b", ++ "scifb1_data_c", ++ "scifb1_data_d", ++ "scifb1_data_e", ++ "scifb1_clk_e", ++ "scifb1_data_f", ++ "scifb1_data_g", ++ "scifb1_clk_g", ++}; ++ ++static const char * const scifb2_groups[] = { ++ "scifb2_data", ++ "scifb2_clk", ++ "scifb2_ctrl", ++ "scifb2_data_b", ++ "scifb2_clk_b", ++ "scifb2_ctrl_b", ++ "scifb2_data_c", ++}; ++ + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(eth), + SH_PFC_FUNCTION(intc), ++ SH_PFC_FUNCTION(scif0), ++ SH_PFC_FUNCTION(scif1), ++ SH_PFC_FUNCTION(scifa0), ++ SH_PFC_FUNCTION(scifa1), ++ SH_PFC_FUNCTION(scifa2), ++ SH_PFC_FUNCTION(scifb0), ++ SH_PFC_FUNCTION(scifb1), ++ SH_PFC_FUNCTION(scifb2), + }; + + #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0088-sh-pfc-r8a7790-Remove-GPIO-data.patch b/patches.renesas/0088-sh-pfc-r8a7790-Remove-GPIO-data.patch new file mode 100644 index 00000000000..8b894c3e01f --- /dev/null +++ b/patches.renesas/0088-sh-pfc-r8a7790-Remove-GPIO-data.patch @@ -0,0 +1,196 @@ +From 797c262c4d8dba533352546095d3b0c112d0e9e7 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 8 Apr 2013 11:36:18 +0200 +Subject: sh-pfc: r8a7790: Remove GPIO data + +GPIOs are now handled by a separate driver, remove GPIO data from the +SoC information structure. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 30e4247e5b4d67d26668003f63f3b12d1263503f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 133 +---------------------------------- + 1 file changed, 1 insertion(+), 132 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +index 54c1e10a..7716a1e2 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -52,32 +52,12 @@ + CPU_32_PORT(fn, pfx##_5_, sfx) \ + + #define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) +-#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ +- GP##pfx##_IN, GP##pfx##_OUT) +- +-#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT +-#define _GP_INDT(pfx, sfx) GP##pfx##_DATA ++#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN) + + #define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) + #define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) + #define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) + +- +-#define PORT_10_REV(fn, pfx, sfx) \ +- PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ +- PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ +- PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ +- PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ +- PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) +- +-#define CPU_32_PORT_REV(fn, pfx, sfx) \ +- PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ +- PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ +- PORT_10_REV(fn, pfx, sfx) +- +-#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) +-#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) +- + #define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) + #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ + FN_##ipsr, FN_##fn) +@@ -89,14 +69,6 @@ enum { + GP_ALL(DATA), + PINMUX_DATA_END, + +- PINMUX_INPUT_BEGIN, +- GP_ALL(IN), +- PINMUX_INPUT_END, +- +- PINMUX_OUTPUT_BEGIN, +- GP_ALL(OUT), +- PINMUX_OUTPUT_END, +- + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + +@@ -3824,106 +3796,6 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + /* SEL_I2C1 [2] */ + FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, } + }, +- { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } }, +- { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) { +- 0, 0, +- 0, 0, +- GP_1_29_IN, GP_1_29_OUT, +- GP_1_28_IN, GP_1_28_OUT, +- GP_1_27_IN, GP_1_27_OUT, +- GP_1_26_IN, GP_1_26_OUT, +- GP_1_25_IN, GP_1_25_OUT, +- GP_1_24_IN, GP_1_24_OUT, +- GP_1_23_IN, GP_1_23_OUT, +- GP_1_22_IN, GP_1_22_OUT, +- GP_1_21_IN, GP_1_21_OUT, +- GP_1_20_IN, GP_1_20_OUT, +- GP_1_19_IN, GP_1_19_OUT, +- GP_1_18_IN, GP_1_18_OUT, +- GP_1_17_IN, GP_1_17_OUT, +- GP_1_16_IN, GP_1_16_OUT, +- GP_1_15_IN, GP_1_15_OUT, +- GP_1_14_IN, GP_1_14_OUT, +- GP_1_13_IN, GP_1_13_OUT, +- GP_1_12_IN, GP_1_12_OUT, +- GP_1_11_IN, GP_1_11_OUT, +- GP_1_10_IN, GP_1_10_OUT, +- GP_1_9_IN, GP_1_9_OUT, +- GP_1_8_IN, GP_1_8_OUT, +- GP_1_7_IN, GP_1_7_OUT, +- GP_1_6_IN, GP_1_6_OUT, +- GP_1_5_IN, GP_1_5_OUT, +- GP_1_4_IN, GP_1_4_OUT, +- GP_1_3_IN, GP_1_3_OUT, +- GP_1_2_IN, GP_1_2_OUT, +- GP_1_1_IN, GP_1_1_OUT, +- GP_1_0_IN, GP_1_0_OUT, } +- }, +- { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { +- 0, 0, +- 0, 0, +- GP_2_29_IN, GP_2_29_OUT, +- GP_2_28_IN, GP_2_28_OUT, +- GP_2_27_IN, GP_2_27_OUT, +- GP_2_26_IN, GP_2_26_OUT, +- GP_2_25_IN, GP_2_25_OUT, +- GP_2_24_IN, GP_2_24_OUT, +- GP_2_23_IN, GP_2_23_OUT, +- GP_2_22_IN, GP_2_22_OUT, +- GP_2_21_IN, GP_2_21_OUT, +- GP_2_20_IN, GP_2_20_OUT, +- GP_2_19_IN, GP_2_19_OUT, +- GP_2_18_IN, GP_2_18_OUT, +- GP_2_17_IN, GP_2_17_OUT, +- GP_2_16_IN, GP_2_16_OUT, +- GP_2_15_IN, GP_2_15_OUT, +- GP_2_14_IN, GP_2_14_OUT, +- GP_2_13_IN, GP_2_13_OUT, +- GP_2_12_IN, GP_2_12_OUT, +- GP_2_11_IN, GP_2_11_OUT, +- GP_2_10_IN, GP_2_10_OUT, +- GP_2_9_IN, GP_2_9_OUT, +- GP_2_8_IN, GP_2_8_OUT, +- GP_2_7_IN, GP_2_7_OUT, +- GP_2_6_IN, GP_2_6_OUT, +- GP_2_5_IN, GP_2_5_OUT, +- GP_2_4_IN, GP_2_4_OUT, +- GP_2_3_IN, GP_2_3_OUT, +- GP_2_2_IN, GP_2_2_OUT, +- GP_2_1_IN, GP_2_1_OUT, +- GP_2_0_IN, GP_2_0_OUT, } +- }, +- { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } }, +- { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } }, +- { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { GP_INOUTSEL(5) } }, +- { }, +-}; +- +-static const struct pinmux_data_reg pinmux_data_regs[] = { +- { PINMUX_DATA_REG("INDT0", 0xE605000C, 32) { GP_INDT(0) } }, +- { PINMUX_DATA_REG("INDT1", 0xE605100C, 32) { +- 0, 0, GP_1_29_DATA, GP_1_28_DATA, +- GP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA, +- GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA, +- GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA, +- GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA, +- GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA, +- GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA, +- GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA } +- }, +- { PINMUX_DATA_REG("INDT2", 0xE605200C, 32) { +- 0, 0, GP_2_29_DATA, GP_2_28_DATA, +- GP_2_27_DATA, GP_2_26_DATA, GP_2_25_DATA, GP_2_24_DATA, +- GP_2_23_DATA, GP_2_22_DATA, GP_2_21_DATA, GP_2_20_DATA, +- GP_2_19_DATA, GP_2_18_DATA, GP_2_17_DATA, GP_2_16_DATA, +- GP_2_15_DATA, GP_2_14_DATA, GP_2_13_DATA, GP_2_12_DATA, +- GP_2_11_DATA, GP_2_10_DATA, GP_2_9_DATA, GP_2_8_DATA, +- GP_2_7_DATA, GP_2_6_DATA, GP_2_5_DATA, GP_2_4_DATA, +- GP_2_3_DATA, GP_2_2_DATA, GP_2_1_DATA, GP_2_0_DATA } +- }, +- { PINMUX_DATA_REG("INDT3", 0xE605300C, 32) { GP_INDT(3) } }, +- { PINMUX_DATA_REG("INDT4", 0xE605400C, 32) { GP_INDT(4) } }, +- { PINMUX_DATA_REG("INDT5", 0xE605500C, 32) { GP_INDT(5) } }, + { }, + }; + +@@ -3931,8 +3803,6 @@ const struct sh_pfc_soc_info r8a7790_pinmux_info = { + .name = "r8a77900_pfc", + .unlock_reg = 0xe6060000, /* PMMR */ + +- .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, +- .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, +@@ -3946,7 +3816,6 @@ const struct sh_pfc_soc_info r8a7790_pinmux_info = { + .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), + + .cfg_regs = pinmux_config_regs, +- .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0089-sh-pfc-r8a7790-Remove-function-GPIOs.patch b/patches.renesas/0089-sh-pfc-r8a7790-Remove-function-GPIOs.patch new file mode 100644 index 00000000000..00c5d3d9d32 --- /dev/null +++ b/patches.renesas/0089-sh-pfc-r8a7790-Remove-function-GPIOs.patch @@ -0,0 +1,388 @@ +From c5d14de8824ce69c0fb63654ebeecf280c4ddbaa Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 8 Apr 2013 11:36:19 +0200 +Subject: sh-pfc: r8a7790: Remove function GPIOs + +No r8a7770 platform use the function GPIOs API. Remove it. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +[horms+renesas@verge.net.au: fixed typo in changelog: r8a7779 -> r8a7770] +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit 728d53f4a4a880d8961fb15e1b19c541c5fa1b0f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 350 ----------------------------------- + 1 file changed, 350 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +index 7716a1e2..51219e1b 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -2503,353 +2503,6 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(scifb2), + }; + +-#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) +- +-static const struct pinmux_func pinmux_func_gpios[] = { +- GPIO_FN(VI1_DATA7_VI1_B7), GPIO_FN(USB0_PWEN), GPIO_FN(USB0_OVC_VBUS), +- GPIO_FN(USB2_PWEN), GPIO_FN(USB2_OVC), GPIO_FN(AVS1), GPIO_FN(AVS2), +- GPIO_FN(DU_DOTCLKIN0), GPIO_FN(DU_DOTCLKIN2), +- +- /*IPSR0*/ +- GPIO_FN(D1), GPIO_FN(MSIOF3_SYNC_B), GPIO_FN(VI3_DATA1), +- GPIO_FN(VI0_G5), GPIO_FN(VI0_G5_B), GPIO_FN(D2), GPIO_FN(MSIOF3_RXD_B), +- GPIO_FN(VI3_DATA2), GPIO_FN(VI0_G6), GPIO_FN(VI0_G6_B), GPIO_FN(D3), +- GPIO_FN(MSIOF3_TXD_B), GPIO_FN(VI3_DATA3), GPIO_FN(VI0_G7), +- GPIO_FN(VI0_G7_B), GPIO_FN(D4), GPIO_FN(SCIFB1_RXD_F), +- GPIO_FN(SCIFB0_RXD_C), GPIO_FN(VI3_DATA4), GPIO_FN(VI0_R0), +- GPIO_FN(VI0_R0_B), GPIO_FN(RX0_B), GPIO_FN(D5), GPIO_FN(SCIFB1_TXD_F), +- GPIO_FN(SCIFB0_TXD_C), GPIO_FN(VI3_DATA5), GPIO_FN(VI0_R1), +- GPIO_FN(VI0_R1_B), GPIO_FN(TX0_B), GPIO_FN(D6), GPIO_FN(SCL2_C), +- GPIO_FN(VI3_DATA6), GPIO_FN(VI0_R2), GPIO_FN(VI0_R2_B), +- GPIO_FN(SCL2_CIS_C), GPIO_FN(D7), GPIO_FN(AD_DI_B), GPIO_FN(SDA2_C), +- GPIO_FN(VI3_DATA7), GPIO_FN(VI0_R3), GPIO_FN(VI0_R3_B), +- GPIO_FN(SDA2_CIS_C), GPIO_FN(D8), GPIO_FN(SCIFA1_SCK_C), +- GPIO_FN(AVB_TXD0), GPIO_FN(MII_TXD0), GPIO_FN(VI0_G0), +- GPIO_FN(VI0_G0_B), GPIO_FN(VI2_DATA0_VI2_B0), +- +- /*IPSR1*/ +- GPIO_FN(D9), GPIO_FN(SCIFA1_RXD_C), GPIO_FN(AVB_TXD1), +- GPIO_FN(MII_TXD1), GPIO_FN(VI0_G1), GPIO_FN(VI0_G1_B), +- GPIO_FN(VI2_DATA1_VI2_B1), GPIO_FN(D10), GPIO_FN(SCIFA1_TXD_C), +- GPIO_FN(AVB_TXD2), GPIO_FN(MII_TXD2), GPIO_FN(VI0_G2), +- GPIO_FN(VI0_G2_B), GPIO_FN(VI2_DATA2_VI2_B2), GPIO_FN(D11), +- GPIO_FN(SCIFA1_CTS_N_C), GPIO_FN(AVB_TXD3), GPIO_FN(MII_TXD3), +- GPIO_FN(VI0_G3), GPIO_FN(VI0_G3_B), GPIO_FN(VI2_DATA3_VI2_B3), +- GPIO_FN(D12), GPIO_FN(SCIFA1_RTS_N_C), GPIO_FN(AVB_TXD4), +- GPIO_FN(VI0_HSYNC_N), GPIO_FN(VI0_HSYNC_N_B), GPIO_FN(VI2_DATA4_VI2_B4), +- GPIO_FN(D13), GPIO_FN(AVB_TXD5), GPIO_FN(VI0_VSYNC_N), +- GPIO_FN(VI0_VSYNC_N_B), GPIO_FN(VI2_DATA5_VI2_B5), GPIO_FN(D14), +- GPIO_FN(SCIFB1_RXD_C), GPIO_FN(AVB_TXD6), GPIO_FN(RX1_B), +- GPIO_FN(VI0_CLKENB), GPIO_FN(VI0_CLKENB_B), GPIO_FN(VI2_DATA6_VI2_B6), +- GPIO_FN(D15), GPIO_FN(SCIFB1_TXD_C), GPIO_FN(AVB_TXD7), GPIO_FN(TX1_B), +- GPIO_FN(VI0_FIELD), GPIO_FN(VI0_FIELD_B), GPIO_FN(VI2_DATA7_VI2_B7), +- GPIO_FN(A0), GPIO_FN(PWM3), GPIO_FN(A1), GPIO_FN(PWM4), +- +- /*IPSR2*/ +- GPIO_FN(A2), GPIO_FN(PWM5), GPIO_FN(MSIOF1_SS1_B), GPIO_FN(A3), +- GPIO_FN(PWM6), GPIO_FN(MSIOF1_SS2_B), GPIO_FN(A4), +- GPIO_FN(MSIOF1_TXD_B), GPIO_FN(TPU0TO0), GPIO_FN(A5), +- GPIO_FN(SCIFA1_TXD_B), GPIO_FN(TPU0TO1), GPIO_FN(A6), +- GPIO_FN(SCIFA1_RTS_N_B), GPIO_FN(TPU0TO2), GPIO_FN(A7), +- GPIO_FN(SCIFA1_SCK_B), GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(TPU0TO3), +- GPIO_FN(A8), GPIO_FN(SCIFA1_RXD_B), GPIO_FN(SSI_SCK5_B), +- GPIO_FN(VI0_R4), GPIO_FN(VI0_R4_B), GPIO_FN(SCIFB2_RXD_C), +- GPIO_FN(VI2_DATA0_VI2_B0_B), GPIO_FN(A9), GPIO_FN(SCIFA1_CTS_N_B), +- GPIO_FN(SSI_WS5_B), GPIO_FN(VI0_R5), GPIO_FN(VI0_R5_B), +- GPIO_FN(SCIFB2_TXD_C), GPIO_FN(VI2_DATA1_VI2_B1_B), GPIO_FN(A10), +- GPIO_FN(SSI_SDATA5_B), GPIO_FN(MSIOF2_SYNC), GPIO_FN(VI0_R6), +- GPIO_FN(VI0_R6_B), GPIO_FN(VI2_DATA2_VI2_B2_B), +- +- /*IPSR3*/ +- GPIO_FN(A11), GPIO_FN(SCIFB2_CTS_N_B), GPIO_FN(MSIOF2_SCK), +- GPIO_FN(VI1_R0), GPIO_FN(VI1_R0_B), GPIO_FN(VI2_G0), +- GPIO_FN(VI2_DATA3_VI2_B3_B), GPIO_FN(A12), GPIO_FN(SCIFB2_RXD_B), +- GPIO_FN(MSIOF2_TXD), GPIO_FN(VI1_R1), GPIO_FN(VI1_R1_B), +- GPIO_FN(VI2_G1), GPIO_FN(VI2_DATA4_VI2_B4_B), GPIO_FN(A13), +- GPIO_FN(SCIFB2_RTS_N_B), GPIO_FN(EX_WAIT2), GPIO_FN(MSIOF2_RXD), +- GPIO_FN(VI1_R2), GPIO_FN(VI1_R2_B), GPIO_FN(VI2_G2), +- GPIO_FN(VI2_DATA5_VI2_B5_B), GPIO_FN(A14), GPIO_FN(SCIFB2_TXD_B), +- GPIO_FN(ATACS11_N), GPIO_FN(MSIOF2_SS1), GPIO_FN(A15), +- GPIO_FN(SCIFB2_SCK_B), GPIO_FN(ATARD1_N), GPIO_FN(MSIOF2_SS2), +- GPIO_FN(A16), GPIO_FN(ATAWR1_N), GPIO_FN(A17), GPIO_FN(AD_DO_B), +- GPIO_FN(ATADIR1_N), GPIO_FN(A18), GPIO_FN(AD_CLK_B), GPIO_FN(ATAG1_N), +- GPIO_FN(A19), GPIO_FN(AD_NCS_N_B), GPIO_FN(ATACS01_N), +- GPIO_FN(EX_WAIT0_B), GPIO_FN(A20), GPIO_FN(SPCLK), GPIO_FN(VI1_R3), +- GPIO_FN(VI1_R3_B), GPIO_FN(VI2_G4), +- +- /*IPSR4*/ +- GPIO_FN(A21), GPIO_FN(MOSI_IO0), GPIO_FN(VI1_R4), GPIO_FN(VI1_R4_B), +- GPIO_FN(VI2_G5), GPIO_FN(A22), GPIO_FN(MISO_IO1), GPIO_FN(VI1_R5), +- GPIO_FN(VI1_R5_B), GPIO_FN(VI2_G6), GPIO_FN(A23), GPIO_FN(IO2), +- GPIO_FN(VI1_G7), GPIO_FN(VI1_G7_B), GPIO_FN(VI2_G7), GPIO_FN(A24), +- GPIO_FN(IO3), GPIO_FN(VI1_R7), GPIO_FN(VI1_R7_B), GPIO_FN(VI2_CLKENB), +- GPIO_FN(VI2_CLKENB_B), GPIO_FN(A25), GPIO_FN(SSL), GPIO_FN(VI1_G6), +- GPIO_FN(VI1_G6_B), GPIO_FN(VI2_FIELD), GPIO_FN(VI2_FIELD_B), +- GPIO_FN(CS0_N), GPIO_FN(VI1_R6), GPIO_FN(VI1_R6_B), GPIO_FN(VI2_G3), +- GPIO_FN(MSIOF0_SS2_B), GPIO_FN(CS1_N_A26), GPIO_FN(SPEEDIN), +- GPIO_FN(VI0_R7), GPIO_FN(VI0_R7_B), GPIO_FN(VI2_CLK), +- GPIO_FN(VI2_CLK_B), GPIO_FN(EX_CS0_N), GPIO_FN(HRX1_B), +- GPIO_FN(VI1_G5), GPIO_FN(VI1_G5_B), GPIO_FN(VI2_R0), GPIO_FN(HTX0_B), +- GPIO_FN(MSIOF0_SS1_B), GPIO_FN(EX_CS1_N), GPIO_FN(GPS_CLK), +- GPIO_FN(HCTS1_N_B), GPIO_FN(VI1_FIELD), GPIO_FN(VI1_FIELD_B), +- GPIO_FN(VI2_R1), GPIO_FN(EX_CS2_N), GPIO_FN(GPS_SIGN), +- GPIO_FN(HRTS1_N_B), GPIO_FN(VI3_CLKENB), GPIO_FN(VI1_G0), +- GPIO_FN(VI1_G0_B), GPIO_FN(VI2_R2), +- +- /*IPSR5*/ +- GPIO_FN(EX_CS3_N), GPIO_FN(GPS_MAG), GPIO_FN(VI3_FIELD), +- GPIO_FN(VI1_G1), GPIO_FN(VI1_G1_B), GPIO_FN(VI2_R3), GPIO_FN(EX_CS4_N), +- GPIO_FN(MSIOF1_SCK_B), GPIO_FN(VI3_HSYNC_N), GPIO_FN(VI2_HSYNC_N), +- GPIO_FN(SCL1), GPIO_FN(VI2_HSYNC_N_B), GPIO_FN(INTC_EN0_N), +- GPIO_FN(SCL1_CIS), GPIO_FN(EX_CS5_N), GPIO_FN(CAN0_RX), +- GPIO_FN(MSIOF1_RXD_B), GPIO_FN(VI3_VSYNC_N), GPIO_FN(VI1_G2), +- GPIO_FN(VI1_G2_B), GPIO_FN(VI2_R4), GPIO_FN(SDA1), GPIO_FN(INTC_EN1_N), +- GPIO_FN(SDA1_CIS), GPIO_FN(BS_N), GPIO_FN(IETX), GPIO_FN(HTX1_B), +- GPIO_FN(CAN1_TX), GPIO_FN(DRACK0), GPIO_FN(IETX_C), GPIO_FN(RD_N), +- GPIO_FN(CAN0_TX), GPIO_FN(SCIFA0_SCK_B), GPIO_FN(RD_WR_N), +- GPIO_FN(VI1_G3), GPIO_FN(VI1_G3_B), GPIO_FN(VI2_R5), +- GPIO_FN(SCIFA0_RXD_B), GPIO_FN(INTC_IRQ4_N), GPIO_FN(WE0_N), +- GPIO_FN(IECLK), GPIO_FN(CAN_CLK), GPIO_FN(VI2_VSYNC_N), +- GPIO_FN(SCIFA0_TXD_B), GPIO_FN(VI2_VSYNC_N_B), GPIO_FN(WE1_N), +- GPIO_FN(IERX), GPIO_FN(CAN1_RX), GPIO_FN(VI1_G4), GPIO_FN(VI1_G4_B), +- GPIO_FN(VI2_R6), GPIO_FN(SCIFA0_CTS_N_B), GPIO_FN(IERX_C), +- GPIO_FN(EX_WAIT0), GPIO_FN(IRQ3), GPIO_FN(INTC_IRQ3_N), +- GPIO_FN(VI3_CLK), GPIO_FN(SCIFA0_RTS_N_B), GPIO_FN(HRX0_B), +- GPIO_FN(MSIOF0_SCK_B), GPIO_FN(DREQ0_N), GPIO_FN(VI1_HSYNC_N), +- GPIO_FN(VI1_HSYNC_N_B), GPIO_FN(VI2_R7), GPIO_FN(SSI_SCK78_C), +- GPIO_FN(SSI_WS78_B), +- +- /*IPSR6*/ +- GPIO_FN(DACK0), GPIO_FN(IRQ0), GPIO_FN(INTC_IRQ0_N), +- GPIO_FN(SSI_SCK6_B), GPIO_FN(VI1_VSYNC_N), GPIO_FN(VI1_VSYNC_N_B), +- GPIO_FN(SSI_WS78_C), GPIO_FN(DREQ1_N), GPIO_FN(VI1_CLKENB), +- GPIO_FN(VI1_CLKENB_B), GPIO_FN(SSI_SDATA7_C), GPIO_FN(SSI_SCK78_B), +- GPIO_FN(DACK1), GPIO_FN(IRQ1), GPIO_FN(INTC_IRQ1_N), GPIO_FN(SSI_WS6_B), +- GPIO_FN(SSI_SDATA8_C), GPIO_FN(DREQ2_N), GPIO_FN(HSCK1_B), +- GPIO_FN(HCTS0_N_B), GPIO_FN(MSIOF0_TXD_B), GPIO_FN(DACK2), +- GPIO_FN(IRQ2), GPIO_FN(INTC_IRQ2_N), GPIO_FN(SSI_SDATA6_B), +- GPIO_FN(HRTS0_N_B), GPIO_FN(MSIOF0_RXD_B), GPIO_FN(ETH_CRS_DV), +- GPIO_FN(RMII_CRS_DV), GPIO_FN(STP_ISCLK_0_B), GPIO_FN(TS_SDEN0_D), +- GPIO_FN(GLO_Q0_C), GPIO_FN(SCL2_E), GPIO_FN(SCL2_CIS_E), +- GPIO_FN(ETH_RX_ER), GPIO_FN(RMII_RX_ER), GPIO_FN(STP_ISD_0_B), +- GPIO_FN(TS_SPSYNC0_D), GPIO_FN(GLO_Q1_C), GPIO_FN(SDA2_E), +- GPIO_FN(SDA2_CIS_E), GPIO_FN(ETH_RXD0), GPIO_FN(RMII_RXD0), +- GPIO_FN(STP_ISEN_0_B), GPIO_FN(TS_SDAT0_D), GPIO_FN(GLO_I0_C), +- GPIO_FN(SCIFB1_SCK_G), GPIO_FN(SCK1_E), GPIO_FN(ETH_RXD1), +- GPIO_FN(RMII_RXD1), GPIO_FN(HRX0_E), GPIO_FN(STP_ISSYNC_0_B), +- GPIO_FN(TS_SCK0_D), GPIO_FN(GLO_I1_C), GPIO_FN(SCIFB1_RXD_G), +- GPIO_FN(RX1_E), GPIO_FN(ETH_LINK), GPIO_FN(RMII_LINK), GPIO_FN(HTX0_E), +- GPIO_FN(STP_IVCXO27_0_B), GPIO_FN(SCIFB1_TXD_G), GPIO_FN(TX1_E), +- GPIO_FN(ETH_REF_CLK), GPIO_FN(RMII_REF_CLK), GPIO_FN(HCTS0_N_E), +- GPIO_FN(STP_IVCXO27_1_B), GPIO_FN(HRX0_F), +- +- /*IPSR7*/ +- GPIO_FN(ETH_MDIO), GPIO_FN(RMII_MDIO), GPIO_FN(HRTS0_N_E), +- GPIO_FN(SIM0_D_C), GPIO_FN(HCTS0_N_F), GPIO_FN(ETH_TXD1), +- GPIO_FN(RMII_TXD1), GPIO_FN(HTX0_F), GPIO_FN(BPFCLK_G), +- GPIO_FN(RDS_CLK_F), GPIO_FN(ETH_TX_EN), GPIO_FN(RMII_TX_EN), +- GPIO_FN(SIM0_CLK_C), GPIO_FN(HRTS0_N_F), GPIO_FN(ETH_MAGIC), +- GPIO_FN(RMII_MAGIC), GPIO_FN(SIM0_RST_C), GPIO_FN(ETH_TXD0), +- GPIO_FN(RMII_TXD0), GPIO_FN(STP_ISCLK_1_B), GPIO_FN(TS_SDEN1_C), +- GPIO_FN(GLO_SCLK_C), GPIO_FN(ETH_MDC), GPIO_FN(RMII_MDC), +- GPIO_FN(STP_ISD_1_B), GPIO_FN(TS_SPSYNC1_C), GPIO_FN(GLO_SDATA_C), +- GPIO_FN(PWM0), GPIO_FN(SCIFA2_SCK_C), GPIO_FN(STP_ISEN_1_B), +- GPIO_FN(TS_SDAT1_C), GPIO_FN(GLO_SS_C), GPIO_FN(PWM1), +- GPIO_FN(SCIFA2_TXD_C), GPIO_FN(STP_ISSYNC_1_B), GPIO_FN(TS_SCK1_C), +- GPIO_FN(GLO_RFON_C), GPIO_FN(PCMOE_N), GPIO_FN(PWM2), GPIO_FN(PWMFSW0), +- GPIO_FN(SCIFA2_RXD_C), GPIO_FN(PCMWE_N), GPIO_FN(IECLK_C), +- GPIO_FN(DU1_DOTCLKIN), GPIO_FN(AUDIO_CLKC), GPIO_FN(AUDIO_CLKOUT_C), +- GPIO_FN(VI0_CLK), GPIO_FN(ATACS00_N), GPIO_FN(AVB_RXD1), +- GPIO_FN(MII_RXD1), GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(ATACS10_N), +- GPIO_FN(AVB_RXD2), GPIO_FN(MII_RXD2), +- +- /*IPSR8*/ +- GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(ATARD0_N), GPIO_FN(AVB_RXD3), +- GPIO_FN(MII_RXD3), GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(ATAWR0_N), +- GPIO_FN(AVB_RXD4), GPIO_FN(VI0_DATA3_VI0_B3), GPIO_FN(ATADIR0_N), +- GPIO_FN(AVB_RXD5), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(ATAG0_N), +- GPIO_FN(AVB_RXD6), GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(EX_WAIT1), +- GPIO_FN(AVB_RXD7), GPIO_FN(VI0_DATA6_VI0_B6), GPIO_FN(AVB_RX_ER), +- GPIO_FN(MII_RX_ER), GPIO_FN(VI0_DATA7_VI0_B7), GPIO_FN(AVB_RX_CLK), +- GPIO_FN(MII_RX_CLK), GPIO_FN(VI1_CLK), GPIO_FN(AVB_RX_DV), +- GPIO_FN(MII_RX_DV), GPIO_FN(VI1_DATA0_VI1_B0), GPIO_FN(SCIFA1_SCK_D), +- GPIO_FN(AVB_CRS), GPIO_FN(MII_CRS), GPIO_FN(VI1_DATA1_VI1_B1), +- GPIO_FN(SCIFA1_RXD_D), GPIO_FN(AVB_MDC), GPIO_FN(MII_MDC), +- GPIO_FN(VI1_DATA2_VI1_B2), GPIO_FN(SCIFA1_TXD_D), GPIO_FN(AVB_MDIO), +- GPIO_FN(MII_MDIO), GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(SCIFA1_CTS_N_D), +- GPIO_FN(AVB_GTX_CLK), GPIO_FN(VI1_DATA4_VI1_B4), +- GPIO_FN(SCIFA1_RTS_N_D), GPIO_FN(AVB_MAGIC), GPIO_FN(MII_MAGIC), +- GPIO_FN(VI1_DATA5_VI1_B5), GPIO_FN(AVB_PHY_INT), +- GPIO_FN(VI1_DATA6_VI1_B6), GPIO_FN(AVB_GTXREFCLK), +- GPIO_FN(SD0_CLK), GPIO_FN(VI1_DATA0_VI1_B0_B), GPIO_FN(SD0_CMD), +- GPIO_FN(SCIFB1_SCK_B), GPIO_FN(VI1_DATA1_VI1_B1_B), +- +- /*IPSR9*/ +- GPIO_FN(SD0_DAT0), GPIO_FN(SCIFB1_RXD_B), GPIO_FN(VI1_DATA2_VI1_B2_B), +- GPIO_FN(SD0_DAT1), GPIO_FN(SCIFB1_TXD_B), GPIO_FN(VI1_DATA3_VI1_B3_B), +- GPIO_FN(SD0_DAT2), GPIO_FN(SCIFB1_CTS_N_B), GPIO_FN(VI1_DATA4_VI1_B4_B), +- GPIO_FN(SD0_DAT3), GPIO_FN(SCIFB1_RTS_N_B), GPIO_FN(VI1_DATA5_VI1_B5_B), +- GPIO_FN(SD0_CD), GPIO_FN(MMC0_D6), GPIO_FN(TS_SDEN0_B), +- GPIO_FN(USB0_EXTP), GPIO_FN(GLO_SCLK), GPIO_FN(VI1_DATA6_VI1_B6_B), +- GPIO_FN(SCL1_B), GPIO_FN(SCL1_CIS_B), GPIO_FN(VI2_DATA6_VI2_B6_B), +- GPIO_FN(SD0_WP), GPIO_FN(MMC0_D7), GPIO_FN(TS_SPSYNC0_B), +- GPIO_FN(USB0_IDIN), GPIO_FN(GLO_SDATA), GPIO_FN(VI1_DATA7_VI1_B7_B), +- GPIO_FN(SDA1_B), GPIO_FN(SDA1_CIS_B), GPIO_FN(VI2_DATA7_VI2_B7_B), +- GPIO_FN(SD1_CLK), GPIO_FN(AVB_TX_EN), GPIO_FN(MII_TX_EN), +- GPIO_FN(SD1_CMD), GPIO_FN(AVB_TX_ER), GPIO_FN(MII_TX_ER), +- GPIO_FN(SCIFB0_SCK_B), GPIO_FN(SD1_DAT0), GPIO_FN(AVB_TX_CLK), +- GPIO_FN(MII_TX_CLK), GPIO_FN(SCIFB0_RXD_B), GPIO_FN(SD1_DAT1), +- GPIO_FN(AVB_LINK), GPIO_FN(MII_LINK), GPIO_FN(SCIFB0_TXD_B), +- GPIO_FN(SD1_DAT2), GPIO_FN(AVB_COL), GPIO_FN(MII_COL), +- GPIO_FN(SCIFB0_CTS_N_B), GPIO_FN(SD1_DAT3), GPIO_FN(AVB_RXD0), +- GPIO_FN(MII_RXD0), GPIO_FN(SCIFB0_RTS_N_B), GPIO_FN(SD1_CD), +- GPIO_FN(MMC1_D6), GPIO_FN(TS_SDEN1), GPIO_FN(USB1_EXTP), +- GPIO_FN(GLO_SS), GPIO_FN(VI0_CLK_B), GPIO_FN(SCL2_D), +- GPIO_FN(SCL2_CIS_D), GPIO_FN(SIM0_CLK_B), GPIO_FN(VI3_CLK_B), +- +- /*IPSR10*/ +- GPIO_FN(SD1_WP), GPIO_FN(MMC1_D7), GPIO_FN(TS_SPSYNC1), +- GPIO_FN(USB1_IDIN), GPIO_FN(GLO_RFON), GPIO_FN(VI1_CLK_B), +- GPIO_FN(SDA2_D), GPIO_FN(SDA2_CIS_D), GPIO_FN(SIM0_D_B), +- GPIO_FN(SD2_CLK), GPIO_FN(MMC0_CLK), GPIO_FN(SIM0_CLK), +- GPIO_FN(VI0_DATA0_VI0_B0_B), GPIO_FN(TS_SDEN0_C), GPIO_FN(GLO_SCLK_B), +- GPIO_FN(VI3_DATA0_B), GPIO_FN(SD2_CMD), GPIO_FN(MMC0_CMD), +- GPIO_FN(SIM0_D), GPIO_FN(VI0_DATA1_VI0_B1_B), GPIO_FN(SCIFB1_SCK_E), +- GPIO_FN(SCK1_D), GPIO_FN(TS_SPSYNC0_C), GPIO_FN(GLO_SDATA_B), +- GPIO_FN(VI3_DATA1_B), GPIO_FN(SD2_DAT0), GPIO_FN(MMC0_D0), +- GPIO_FN(FMCLK_B), GPIO_FN(VI0_DATA2_VI0_B2_B), GPIO_FN(SCIFB1_RXD_E), +- GPIO_FN(RX1_D), GPIO_FN(TS_SDAT0_C), GPIO_FN(GLO_SS_B), +- GPIO_FN(VI3_DATA2_B), GPIO_FN(SD2_DAT1), GPIO_FN(MMC0_D1), +- GPIO_FN(FMIN_B), GPIO_FN(RDS_DATA), GPIO_FN(VI0_DATA3_VI0_B3_B), +- GPIO_FN(SCIFB1_TXD_E), GPIO_FN(TX1_D), GPIO_FN(TS_SCK0_C), +- GPIO_FN(GLO_RFON_B), GPIO_FN(VI3_DATA3_B), GPIO_FN(SD2_DAT2), +- GPIO_FN(MMC0_D2), GPIO_FN(BPFCLK_B), GPIO_FN(RDS_CLK), +- GPIO_FN(VI0_DATA4_VI0_B4_B), GPIO_FN(HRX0_D), GPIO_FN(TS_SDEN1_B), +- GPIO_FN(GLO_Q0_B), GPIO_FN(VI3_DATA4_B), GPIO_FN(SD2_DAT3), +- GPIO_FN(MMC0_D3), GPIO_FN(SIM0_RST), GPIO_FN(VI0_DATA5_VI0_B5_B), +- GPIO_FN(HTX0_D), GPIO_FN(TS_SPSYNC1_B), GPIO_FN(GLO_Q1_B), +- GPIO_FN(VI3_DATA5_B), GPIO_FN(SD2_CD), GPIO_FN(MMC0_D4), +- GPIO_FN(TS_SDAT0_B), GPIO_FN(USB2_EXTP), GPIO_FN(GLO_I0), +- GPIO_FN(VI0_DATA6_VI0_B6_B), GPIO_FN(HCTS0_N_D), GPIO_FN(TS_SDAT1_B), +- GPIO_FN(GLO_I0_B), GPIO_FN(VI3_DATA6_B), +- +- /*IPSR11*/ +- GPIO_FN(SD2_WP), GPIO_FN(MMC0_D5), GPIO_FN(TS_SCK0_B), +- GPIO_FN(USB2_IDIN), GPIO_FN(GLO_I1), GPIO_FN(VI0_DATA7_VI0_B7_B), +- GPIO_FN(HRTS0_N_D), GPIO_FN(TS_SCK1_B), GPIO_FN(GLO_I1_B), +- GPIO_FN(VI3_DATA7_B), GPIO_FN(SD3_CLK), GPIO_FN(MMC1_CLK), +- GPIO_FN(SD3_CMD), GPIO_FN(MMC1_CMD), GPIO_FN(MTS_N), GPIO_FN(SD3_DAT0), +- GPIO_FN(MMC1_D0), GPIO_FN(STM_N), GPIO_FN(SD3_DAT1), GPIO_FN(MMC1_D1), +- GPIO_FN(MDATA), GPIO_FN(SD3_DAT2), GPIO_FN(MMC1_D2), GPIO_FN(SDATA), +- GPIO_FN(SD3_DAT3), GPIO_FN(MMC1_D3), GPIO_FN(SCKZ), GPIO_FN(SD3_CD), +- GPIO_FN(MMC1_D4), GPIO_FN(TS_SDAT1), GPIO_FN(VSP), GPIO_FN(GLO_Q0), +- GPIO_FN(SIM0_RST_B), GPIO_FN(SD3_WP), GPIO_FN(MMC1_D5), +- GPIO_FN(TS_SCK1), GPIO_FN(GLO_Q1), GPIO_FN(FMIN_C), GPIO_FN(RDS_DATA_B), +- GPIO_FN(FMIN_E), GPIO_FN(RDS_DATA_D), GPIO_FN(FMIN_F), +- GPIO_FN(RDS_DATA_E), GPIO_FN(MLB_CLK), GPIO_FN(SCL2_B), +- GPIO_FN(SCL2_CIS_B), GPIO_FN(MLB_SIG), GPIO_FN(SCIFB1_RXD_D), +- GPIO_FN(RX1_C), GPIO_FN(SDA2_B), GPIO_FN(SDA2_CIS_B), GPIO_FN(MLB_DAT), +- GPIO_FN(SPV_EVEN), GPIO_FN(SCIFB1_TXD_D), GPIO_FN(TX1_C), +- GPIO_FN(BPFCLK_C), GPIO_FN(RDS_CLK_B), GPIO_FN(SSI_SCK0129), +- GPIO_FN(CAN_CLK_B), GPIO_FN(MOUT0), +- +- /*IPSR12*/ +- GPIO_FN(SSI_WS0129), GPIO_FN(CAN0_TX_B), GPIO_FN(MOUT1), +- GPIO_FN(SSI_SDATA0), GPIO_FN(CAN0_RX_B), GPIO_FN(MOUT2), +- GPIO_FN(SSI_SDATA1), GPIO_FN(CAN1_TX_B), GPIO_FN(MOUT5), +- GPIO_FN(SSI_SDATA2), GPIO_FN(CAN1_RX_B), GPIO_FN(SSI_SCK1), +- GPIO_FN(MOUT6), GPIO_FN(SSI_SCK34), GPIO_FN(STP_OPWM_0), +- GPIO_FN(SCIFB0_SCK), GPIO_FN(MSIOF1_SCK), GPIO_FN(CAN_DEBUG_HW_TRIGGER), +- GPIO_FN(SSI_WS34), GPIO_FN(STP_IVCXO27_0), GPIO_FN(SCIFB0_RXD), +- GPIO_FN(MSIOF1_SYNC), GPIO_FN(CAN_STEP0), GPIO_FN(SSI_SDATA3), +- GPIO_FN(STP_ISCLK_0), GPIO_FN(SCIFB0_TXD), GPIO_FN(MSIOF1_SS1), +- GPIO_FN(CAN_TXCLK), GPIO_FN(SSI_SCK4), GPIO_FN(STP_ISD_0), +- GPIO_FN(SCIFB0_CTS_N), GPIO_FN(MSIOF1_SS2), GPIO_FN(SSI_SCK5_C), +- GPIO_FN(CAN_DEBUGOUT0), GPIO_FN(SSI_WS4), GPIO_FN(STP_ISEN_0), +- GPIO_FN(SCIFB0_RTS_N), GPIO_FN(MSIOF1_TXD), GPIO_FN(SSI_WS5_C), +- GPIO_FN(CAN_DEBUGOUT1), GPIO_FN(SSI_SDATA4), GPIO_FN(STP_ISSYNC_0), +- GPIO_FN(MSIOF1_RXD), GPIO_FN(CAN_DEBUGOUT2), GPIO_FN(SSI_SCK5), +- GPIO_FN(SCIFB1_SCK), GPIO_FN(IERX_B), GPIO_FN(DU2_EXHSYNC_DU2_HSYNC), +- GPIO_FN(QSTH_QHS), GPIO_FN(CAN_DEBUGOUT3), GPIO_FN(SSI_WS5), +- GPIO_FN(SCIFB1_RXD), GPIO_FN(IECLK_B), GPIO_FN(DU2_EXVSYNC_DU2_VSYNC), +- GPIO_FN(QSTB_QHE), GPIO_FN(CAN_DEBUGOUT4), +- +- /*IPSR13*/ +- GPIO_FN(SSI_SDATA5), GPIO_FN(SCIFB1_TXD), GPIO_FN(IETX_B), +- GPIO_FN(DU2_DR2), GPIO_FN(LCDOUT2), GPIO_FN(CAN_DEBUGOUT5), +- GPIO_FN(SSI_SCK6), GPIO_FN(SCIFB1_CTS_N), GPIO_FN(BPFCLK_D), +- GPIO_FN(RDS_CLK_C), GPIO_FN(DU2_DR3), GPIO_FN(LCDOUT3), +- GPIO_FN(CAN_DEBUGOUT6), GPIO_FN(BPFCLK_F), GPIO_FN(RDS_CLK_E), +- GPIO_FN(SSI_WS6), GPIO_FN(SCIFB1_RTS_N), GPIO_FN(CAN0_TX_D), +- GPIO_FN(DU2_DR4), GPIO_FN(LCDOUT4), GPIO_FN(CAN_DEBUGOUT7), +- GPIO_FN(SSI_SDATA6), GPIO_FN(FMIN_D), GPIO_FN(RDS_DATA_C), +- GPIO_FN(DU2_DR5), GPIO_FN(LCDOUT5), GPIO_FN(CAN_DEBUGOUT8), +- GPIO_FN(SSI_SCK78), GPIO_FN(STP_IVCXO27_1), GPIO_FN(SCK1), +- GPIO_FN(SCIFA1_SCK), GPIO_FN(DU2_DR6), GPIO_FN(LCDOUT6), +- GPIO_FN(CAN_DEBUGOUT9), GPIO_FN(SSI_WS78), GPIO_FN(STP_ISCLK_1), +- GPIO_FN(SCIFB2_SCK), GPIO_FN(SCIFA2_CTS_N), GPIO_FN(DU2_DR7), +- GPIO_FN(LCDOUT7), GPIO_FN(CAN_DEBUGOUT10), GPIO_FN(SSI_SDATA7), +- GPIO_FN(STP_ISD_1), GPIO_FN(SCIFB2_RXD), GPIO_FN(SCIFA2_RTS_N), +- GPIO_FN(TCLK2), GPIO_FN(QSTVA_QVS), GPIO_FN(CAN_DEBUGOUT11), +- GPIO_FN(BPFCLK_E), GPIO_FN(RDS_CLK_D), GPIO_FN(SSI_SDATA7_B), +- GPIO_FN(FMIN_G), GPIO_FN(RDS_DATA_F), GPIO_FN(SSI_SDATA8), +- GPIO_FN(STP_ISEN_1), GPIO_FN(SCIFB2_TXD), GPIO_FN(CAN0_TX_C), +- GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(SSI_SDATA8_B), GPIO_FN(SSI_SDATA9), +- GPIO_FN(STP_ISSYNC_1), GPIO_FN(SCIFB2_CTS_N), GPIO_FN(SSI_WS1), +- GPIO_FN(SSI_SDATA5_C), GPIO_FN(CAN_DEBUGOUT13), GPIO_FN(AUDIO_CLKA), +- GPIO_FN(SCIFB2_RTS_N), GPIO_FN(CAN_DEBUGOUT14), +- +- /*IPSR14*/ +- GPIO_FN(AUDIO_CLKB), GPIO_FN(SCIF_CLK), GPIO_FN(CAN0_RX_D), +- GPIO_FN(DVC_MUTE), GPIO_FN(CAN0_RX_C), GPIO_FN(CAN_DEBUGOUT15), +- GPIO_FN(REMOCON), GPIO_FN(SCIFA0_SCK), GPIO_FN(HSCK1), GPIO_FN(SCK0), +- GPIO_FN(MSIOF3_SS2), GPIO_FN(DU2_DG2), GPIO_FN(LCDOUT10), +- GPIO_FN(SDA1_C), GPIO_FN(SDA1_CIS_C), GPIO_FN(SCIFA0_RXD), +- GPIO_FN(HRX1), GPIO_FN(RX0), GPIO_FN(DU2_DR0), GPIO_FN(LCDOUT0), +- GPIO_FN(SCIFA0_TXD), GPIO_FN(HTX1), GPIO_FN(TX0), GPIO_FN(DU2_DR1), +- GPIO_FN(LCDOUT1), GPIO_FN(SCIFA0_CTS_N), GPIO_FN(HCTS1_N), +- GPIO_FN(CTS0_N), GPIO_FN(MSIOF3_SYNC), GPIO_FN(DU2_DG3), +- GPIO_FN(LCDOUT11), GPIO_FN(PWM0_B), GPIO_FN(SCL1_C), +- GPIO_FN(SCL1_CIS_C), GPIO_FN(SCIFA0_RTS_N), GPIO_FN(HRTS1_N), +- GPIO_FN(RTS0_N_TANS), GPIO_FN(MSIOF3_SS1), GPIO_FN(DU2_DG0), +- GPIO_FN(LCDOUT8), GPIO_FN(PWM1_B), GPIO_FN(SCIFA1_RXD), GPIO_FN(AD_DI), +- GPIO_FN(RX1), GPIO_FN(DU2_EXODDF_DU2_ODDF_DISP_CDE), GPIO_FN(QCPV_QDE), +- GPIO_FN(SCIFA1_TXD), GPIO_FN(AD_DO), GPIO_FN(TX1), GPIO_FN(DU2_DG1), +- GPIO_FN(LCDOUT9), GPIO_FN(SCIFA1_CTS_N), GPIO_FN(AD_CLK), +- GPIO_FN(CTS1_N), GPIO_FN(MSIOF3_RXD), GPIO_FN(DU0_DOTCLKOUT), +- GPIO_FN(QCLK), GPIO_FN(SCIFA1_RTS_N), GPIO_FN(AD_NCS_N), +- GPIO_FN(RTS1_N_TANS), GPIO_FN(MSIOF3_TXD), GPIO_FN(DU1_DOTCLKOUT), +- GPIO_FN(QSTVB_QVE), GPIO_FN(HRTS0_N_C), +- +- /*IPSR15*/ +- GPIO_FN(SCIFA2_SCK), GPIO_FN(FMCLK), GPIO_FN(MSIOF3_SCK), +- GPIO_FN(DU2_DG7), GPIO_FN(LCDOUT15), GPIO_FN(SCIF_CLK_B), +- GPIO_FN(SCIFA2_RXD), GPIO_FN(FMIN), GPIO_FN(DU2_DB0), +- GPIO_FN(LCDOUT16), GPIO_FN(SCL2), GPIO_FN(SCL2_CIS), +- GPIO_FN(SCIFA2_TXD), GPIO_FN(BPFCLK), GPIO_FN(DU2_DB1), +- GPIO_FN(LCDOUT17), GPIO_FN(SDA2), GPIO_FN(SDA2_CIS), GPIO_FN(HSCK0), +- GPIO_FN(TS_SDEN0), GPIO_FN(DU2_DG4), GPIO_FN(LCDOUT12), +- GPIO_FN(HCTS0_N_C), GPIO_FN(HRX0), GPIO_FN(DU2_DB2), GPIO_FN(LCDOUT18), +- GPIO_FN(HTX0), GPIO_FN(DU2_DB3), GPIO_FN(LCDOUT19), GPIO_FN(HCTS0_N), +- GPIO_FN(SSI_SCK9), GPIO_FN(DU2_DB4), GPIO_FN(LCDOUT20), +- GPIO_FN(HRTS0_N), GPIO_FN(SSI_WS9), GPIO_FN(DU2_DB5), +- GPIO_FN(LCDOUT21), GPIO_FN(MSIOF0_SCK), GPIO_FN(TS_SDAT0), +- GPIO_FN(ADICLK), GPIO_FN(DU2_DB6), GPIO_FN(LCDOUT22), +- GPIO_FN(MSIOF0_SYNC), GPIO_FN(TS_SCK0), GPIO_FN(SSI_SCK2), +- GPIO_FN(ADIDATA), GPIO_FN(DU2_DB7), GPIO_FN(LCDOUT23), +- GPIO_FN(SCIFA2_RXD_B), GPIO_FN(MSIOF0_SS1), GPIO_FN(ADICHS0), +- GPIO_FN(DU2_DG5), GPIO_FN(LCDOUT13), GPIO_FN(MSIOF0_TXD), +- GPIO_FN(ADICHS1), GPIO_FN(DU2_DG6), GPIO_FN(LCDOUT14), +- +- /*IPSR16*/ +- GPIO_FN(MSIOF0_SS2), GPIO_FN(AUDIO_CLKOUT), GPIO_FN(ADICHS2), +- GPIO_FN(DU2_DISP), GPIO_FN(QPOLA), GPIO_FN(HTX0_C), +- GPIO_FN(SCIFA2_TXD_B), GPIO_FN(MSIOF0_RXD), GPIO_FN(TS_SPSYNC0), +- GPIO_FN(SSI_WS2), GPIO_FN(ADICS_SAMP), GPIO_FN(DU2_CDE), +- GPIO_FN(QPOLB), GPIO_FN(HRX0_C), GPIO_FN(USB1_PWEN), +- GPIO_FN(AUDIO_CLKOUT_D), GPIO_FN(USB1_OVC), GPIO_FN(TCLK1_B), +-}; +- + static struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + GP_0_31_FN, FN_IP3_17_15, +@@ -3812,9 +3465,6 @@ const struct sh_pfc_soc_info r8a7790_pinmux_info = { + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + +- .func_gpios = pinmux_func_gpios, +- .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), +- + .cfg_regs = pinmux_config_regs, + + .gpio_data = pinmux_data, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0090-sh-pfc-r8a7790-Don-t-use-GPIO-enum-entries.patch b/patches.renesas/0090-sh-pfc-r8a7790-Don-t-use-GPIO-enum-entries.patch new file mode 100644 index 00000000000..fe4726ae139 --- /dev/null +++ b/patches.renesas/0090-sh-pfc-r8a7790-Don-t-use-GPIO-enum-entries.patch @@ -0,0 +1,124 @@ +From 71bf5d2d56d64a1ffe941b9ffb7f8416d13c6a9f Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 8 Apr 2013 11:36:20 +0200 +Subject: sh-pfc: r8a7790: Don't use GPIO enum entries + +Refactor the GPIO macro magic to use GPIO numbers directly instead of +the GPIO_GP_x_y enum entries. This will allow removing the GPIO enum +entries from the mach/r8a7790.h header. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit ed3e26049e238d066841f858509b764df37c3776) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 90 ++++++++++++++++++++++++------------ + 1 file changed, 60 insertions(+), 30 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +index 51219e1b..1656915a 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -24,39 +24,69 @@ + #include <linux/kernel.h> + #include <linux/platform_data/gpio-rcar.h> + +-#include <mach/r8a7790.h> +- + #include "core.h" + #include "sh_pfc.h" + +-#define CPU_32_PORT(fn, pfx, sfx) \ +- PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ +- PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ +- PORT_1(fn, pfx##31, sfx) +- +-#define CPU_32_PORT1(fn, pfx, sfx) \ +- PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ +- PORT_10(fn, pfx##2, sfx) +- +-#define CPU_32_PORT2(fn, pfx, sfx) \ +- PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ +- PORT_10(fn, pfx##2, sfx) +- +-/* GP_0_0_DATA -> GP_5_31_DATA (except for GP1[30],GP1[31],GP2[30],GP2[31]) */ +-#define CPU_ALL_PORT(fn, pfx, sfx) \ +- CPU_32_PORT(fn, pfx##_0_, sfx), \ +- CPU_32_PORT1(fn, pfx##_1_, sfx), \ +- CPU_32_PORT2(fn, pfx##_2_, sfx), \ +- CPU_32_PORT(fn, pfx##_3_, sfx), \ +- CPU_32_PORT(fn, pfx##_4_, sfx), \ +- CPU_32_PORT(fn, pfx##_5_, sfx) \ +- +-#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) +-#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN) +- +-#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) +-#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) +-#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) ++#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx) ++ ++#define PORT_GP_32(bank, fn, sfx) \ ++ PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ ++ PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ ++ PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ ++ PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ ++ PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ ++ PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ ++ PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ ++ PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ ++ PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ ++ PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ ++ PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ ++ PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ ++ PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \ ++ PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \ ++ PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \ ++ PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx) ++ ++#define PORT_GP_32_REV(bank, fn, sfx) \ ++ PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \ ++ PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \ ++ PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \ ++ PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \ ++ PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \ ++ PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \ ++ PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \ ++ PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \ ++ PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \ ++ PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \ ++ PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \ ++ PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \ ++ PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \ ++ PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \ ++ PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \ ++ PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx) ++ ++#define CPU_ALL_PORT(fn, sfx) \ ++ PORT_GP_32(0, fn, sfx), \ ++ PORT_GP_32(1, fn, sfx), \ ++ PORT_GP_32(2, fn, sfx), \ ++ PORT_GP_32(3, fn, sfx), \ ++ PORT_GP_32(4, fn, sfx), \ ++ PORT_GP_32(5, fn, sfx) ++ ++#define _GP_PORT_ALL(bank, pin, name, sfx) name##_##sfx ++ ++#define _GP_GPIO(bank, pin, _name, sfx) \ ++ [(bank * 32) + pin] = { \ ++ .name = __stringify(_name), \ ++ .enum_id = _name##_DATA, \ ++ } ++ ++#define _GP_DATA(bank, pin, name, sfx) \ ++ PINMUX_DATA(name##_DATA, name##_FN) ++ ++#define GP_ALL(str) CPU_ALL_PORT(_GP_PORT_ALL, str) ++#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused) ++#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused) + + #define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) + #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0091-sh-pfc-Add-r8a7778-pinmux-support.patch b/patches.renesas/0091-sh-pfc-Add-r8a7778-pinmux-support.patch new file mode 100644 index 00000000000..489fdc5d0fa --- /dev/null +++ b/patches.renesas/0091-sh-pfc-Add-r8a7778-pinmux-support.patch @@ -0,0 +1,2451 @@ +From d214c05155ccb266306bd6119367d158f906de91 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Fri, 12 Apr 2013 05:37:20 +0000 +Subject: sh-pfc: Add r8a7778 pinmux support + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Simon Horman <horms@verge.net.au> +(cherry picked from commit 87f8c988636db0d477bb63fddfaefb5be9b1c386) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/Kconfig | 5 + + drivers/pinctrl/sh-pfc/Makefile | 1 + + drivers/pinctrl/sh-pfc/core.c | 3 + + drivers/pinctrl/sh-pfc/core.h | 1 + + drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 2369 ++++++++++++++++++++++++++++++++++ + 5 files changed, 2379 insertions(+) + create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a7778.c + +diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig +index a0b6bd0b..32161c4f 100644 +--- a/drivers/pinctrl/sh-pfc/Kconfig ++++ b/drivers/pinctrl/sh-pfc/Kconfig +@@ -30,6 +30,11 @@ config PINCTRL_PFC_R8A7740 + depends on ARCH_R8A7740 + select PINCTRL_SH_PFC + ++config PINCTRL_PFC_R8A7778 ++ def_bool y ++ depends on ARCH_R8A7778 ++ select PINCTRL_SH_PFC ++ + config PINCTRL_PFC_R8A7779 + def_bool y + depends on ARCH_R8A7779 +diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile +index 1cbf5b18..5e0c222c 100644 +--- a/drivers/pinctrl/sh-pfc/Makefile ++++ b/drivers/pinctrl/sh-pfc/Makefile +@@ -5,6 +5,7 @@ endif + obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc.o + obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o + obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o ++obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o + obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o + obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o + obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o +diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c +index db0d6f7a..4540ce38 100644 +--- a/drivers/pinctrl/sh-pfc/core.c ++++ b/drivers/pinctrl/sh-pfc/core.c +@@ -424,6 +424,9 @@ static const struct platform_device_id sh_pfc_id_table[] = { + #ifdef CONFIG_PINCTRL_PFC_R8A7740 + { "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info }, + #endif ++#ifdef CONFIG_PINCTRL_PFC_R8A7778 ++ { "pfc-r8a7778", (kernel_ulong_t)&r8a7778_pinmux_info }, ++#endif + #ifdef CONFIG_PINCTRL_PFC_R8A7779 + { "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info }, + #endif +diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h +index 6ec746f0..e847afbe 100644 +--- a/drivers/pinctrl/sh-pfc/core.h ++++ b/drivers/pinctrl/sh-pfc/core.h +@@ -57,6 +57,7 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type); + + extern const struct sh_pfc_soc_info r8a73a4_pinmux_info; + extern const struct sh_pfc_soc_info r8a7740_pinmux_info; ++extern const struct sh_pfc_soc_info r8a7778_pinmux_info; + extern const struct sh_pfc_soc_info r8a7779_pinmux_info; + extern const struct sh_pfc_soc_info r8a7790_pinmux_info; + extern const struct sh_pfc_soc_info sh7203_pinmux_info; +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +new file mode 100644 +index 00000000..ddbd27b7 +--- /dev/null ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +@@ -0,0 +1,2369 @@ ++/* ++ * r8a7778 processor support - PFC hardware block ++ * ++ * Copyright (C) 2013 Renesas Solutions Corp. ++ * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> ++ * ++ * based on ++ * Copyright (C) 2011 Renesas Solutions Corp. ++ * Copyright (C) 2011 Magnus Damm ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <linux/platform_data/gpio-rcar.h> ++#include <linux/kernel.h> ++#include "sh_pfc.h" ++ ++#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx) ++ ++#define PORT_GP_32(bank, fn, sfx) \ ++ PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ ++ PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ ++ PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ ++ PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ ++ PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ ++ PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ ++ PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ ++ PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ ++ PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ ++ PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ ++ PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ ++ PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ ++ PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \ ++ PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \ ++ PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \ ++ PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx) ++ ++#define PORT_GP_27(bank, fn, sfx) \ ++ PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ ++ PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ ++ PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ ++ PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ ++ PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ ++ PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ ++ PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ ++ PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ ++ PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ ++ PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ ++ PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ ++ PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ ++ PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \ ++ PORT_GP_1(bank, 26, fn, sfx) ++ ++#define CPU_ALL_PORT(fn, sfx) \ ++ PORT_GP_32(0, fn, sfx), \ ++ PORT_GP_32(1, fn, sfx), \ ++ PORT_GP_32(2, fn, sfx), \ ++ PORT_GP_32(3, fn, sfx), \ ++ PORT_GP_27(4, fn, sfx) ++ ++#define _GP_PORT_ALL(bank, pin, name, sfx) name##_##sfx ++ ++#define _GP_GPIO(bank, pin, _name, sfx) \ ++ [RCAR_GP_PIN(bank, pin)] = { \ ++ .name = __stringify(_name), \ ++ .enum_id = _name##_DATA, \ ++ } ++ ++#define _GP_DATA(bank, pin, name, sfx) \ ++ PINMUX_DATA(name##_DATA, name##_FN) ++ ++#define GP_ALL(str) CPU_ALL_PORT(_GP_PORT_ALL, str) ++#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused) ++#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused) ++ ++#define PINMUX_IPSR_NOGP(ispr, fn) PINMUX_DATA(fn##_MARK, FN_##fn) ++#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr) ++#define PINMUX_IPSR_MSEL(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr, FN_##ms) ++#define PINMUX_IPSR_NOGM(ispr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ms) ++ ++enum { ++ PINMUX_RESERVED = 0, ++ ++ PINMUX_DATA_BEGIN, ++ GP_ALL(DATA), /* GP_0_0_DATA -> GP_4_26_DATA */ ++ PINMUX_DATA_END, ++ ++ PINMUX_FUNCTION_BEGIN, ++ GP_ALL(FN), /* GP_0_0_FN -> GP_4_26_FN */ ++ ++ /* GPSR0 */ ++ FN_IP0_1_0, FN_PENC0, FN_PENC1, FN_IP0_4_2, ++ FN_IP0_7_5, FN_IP0_11_8, FN_IP0_14_12, FN_A1, ++ FN_A2, FN_A3, FN_IP0_15, FN_IP0_16, ++ FN_IP0_17, FN_IP0_18, FN_IP0_19, FN_IP0_20, ++ FN_IP0_21, FN_IP0_22, FN_IP0_23, FN_IP0_24, ++ FN_IP0_25, FN_IP0_26, FN_IP0_27, FN_IP0_28, ++ FN_IP0_29, FN_IP0_30, FN_IP1_0, FN_IP1_1, ++ FN_IP1_4_2, FN_IP1_7_5, FN_IP1_10_8, FN_IP1_14_11, ++ ++ /* GPSR1 */ ++ FN_IP1_23_21, FN_WE0, FN_IP1_24, FN_IP1_27_25, ++ FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, ++ FN_IP2_11_9, FN_IP2_13_12, FN_IP2_16_14, FN_IP2_17, ++ FN_IP2_30, FN_IP2_31, FN_IP3_1_0, FN_IP3_4_2, ++ FN_IP3_7_5, FN_IP3_9_8, FN_IP3_12_10, FN_IP3_15_13, ++ FN_IP3_18_16, FN_IP3_20_19, FN_IP3_23_21, FN_IP3_26_24, ++ FN_IP3_27, FN_IP3_28, FN_IP3_29, FN_IP3_30, ++ FN_IP3_31, FN_IP4_0, FN_IP4_3_1, FN_IP4_6_4, ++ ++ /* GPSR2 */ ++ FN_IP4_7, FN_IP4_8, FN_IP4_10_9, FN_IP4_12_11, ++ FN_IP4_14_13, FN_IP4_16_15, FN_IP4_20_17, FN_IP4_24_21, ++ FN_IP4_26_25, FN_IP4_28_27, FN_IP4_30_29, FN_IP5_1_0, ++ FN_IP5_3_2, FN_IP5_5_4, FN_IP5_6, FN_IP5_7, ++ FN_IP5_9_8, FN_IP5_11_10, FN_IP5_12, FN_IP5_14_13, ++ FN_IP5_17_15, FN_IP5_20_18, FN_AUDIO_CLKA, FN_AUDIO_CLKB, ++ FN_IP5_22_21, FN_IP5_25_23, FN_IP5_28_26, FN_IP5_30_29, ++ FN_IP6_1_0, FN_IP6_4_2, FN_IP6_6_5, FN_IP6_7, ++ ++ /* GPSR3 */ ++ FN_IP6_8, FN_IP6_9, FN_SSI_SCK34, FN_IP6_10, ++ FN_IP6_12_11, FN_IP6_13, FN_IP6_15_14, FN_IP6_16, ++ FN_IP6_18_17, FN_IP6_20_19, FN_IP6_21, FN_IP6_23_22, ++ FN_IP6_25_24, FN_IP6_27_26, FN_IP6_29_28, FN_IP6_31_30, ++ FN_IP7_1_0, FN_IP7_3_2, FN_IP7_5_4, FN_IP7_8_6, ++ FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18, ++ FN_IP7_21, FN_IP7_24_22, FN_IP7_28_25, FN_IP7_31_29, ++ FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_10_9, ++ ++ /* GPSR4 */ ++ FN_IP8_13_11, FN_IP8_15_14, FN_IP8_18_16, FN_IP8_21_19, ++ FN_IP8_23_22, FN_IP8_26_24, FN_IP8_29_27, FN_IP9_2_0, ++ FN_IP9_5_3, FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, ++ FN_IP9_17_15, FN_IP9_20_18, FN_IP9_23_21, FN_IP9_26_24, ++ FN_IP9_29_27, FN_IP10_2_0, FN_IP10_5_3, FN_IP10_8_6, ++ FN_IP10_12_9, FN_IP10_15_13, FN_IP10_18_16, FN_IP10_21_19, ++ FN_IP10_24_22, FN_AVS1, FN_AVS2, ++ ++ /* IPSR0 */ ++ FN_PRESETOUT, FN_PWM1, FN_AUDATA0, FN_ARM_TRACEDATA_0, ++ FN_GPSCLK_C, FN_USB_OVC0, FN_TX2_E, FN_SDA2_B, ++ FN_AUDATA1, FN_ARM_TRACEDATA_1, FN_GPSIN_C, ++ FN_USB_OVC1, FN_RX2_E, FN_SCL2_B, FN_SD1_DAT2_A, ++ FN_MMC_D2, FN_BS, FN_ATADIR0_A, FN_SDSELF_A, ++ FN_PWM4_B, FN_SD1_DAT3_A, FN_MMC_D3, FN_A0, ++ FN_ATAG0_A, FN_REMOCON_B, FN_A4, FN_A5, ++ FN_A6, FN_A7, FN_A8, FN_A9, ++ FN_A10, FN_A11, FN_A12, FN_A13, ++ FN_A14, FN_A15, FN_A16, FN_A17, ++ FN_A18, FN_A19, ++ ++ /* IPSR1 */ ++ FN_A20, FN_HSPI_CS1_B, FN_A21, FN_HSPI_CLK1_B, ++ FN_A22, FN_HRTS0_B, FN_RX2_B, FN_DREQ2_A, ++ FN_A23, FN_HTX0_B, FN_TX2_B, FN_DACK2_A, ++ FN_TS_SDEN0_A, FN_SD1_CD_A, FN_MMC_D6, FN_A24, ++ FN_DREQ1_A, FN_HRX0_B, FN_TS_SPSYNC0_A, ++ FN_SD1_WP_A, FN_MMC_D7, FN_A25, FN_DACK1_A, ++ FN_HCTS0_B, FN_RX3_C, FN_TS_SDAT0_A, FN_CLKOUT, ++ FN_HSPI_TX1_B, FN_PWM0_B, FN_CS0, FN_HSPI_RX1_B, ++ FN_SSI_SCK1_B, FN_ATAG0_B, FN_CS1_A26, FN_SDA2_A, ++ FN_SCK2_B, FN_MMC_D5, FN_ATADIR0_B, FN_RD_WR, ++ FN_WE1, FN_ATAWR0_B, FN_SSI_WS1_B, FN_EX_CS0, ++ FN_SCL2_A, FN_TX3_C, FN_TS_SCK0_A, FN_EX_CS1, ++ FN_MMC_D4, ++ ++ /* IPSR2 */ ++ FN_SD1_CLK_A, FN_MMC_CLK, FN_ATACS00, FN_EX_CS2, ++ FN_SD1_CMD_A, FN_MMC_CMD, FN_ATACS10, FN_EX_CS3, ++ FN_SD1_DAT0_A, FN_MMC_D0, FN_ATARD0, FN_EX_CS4, ++ FN_EX_WAIT1_A, FN_SD1_DAT1_A, FN_MMC_D1, FN_ATAWR0_A, ++ FN_EX_CS5, FN_EX_WAIT2_A, FN_DREQ0_A, FN_RX3_A, ++ FN_DACK0, FN_TX3_A, FN_DRACK0, FN_EX_WAIT0, ++ FN_PWM0_C, FN_D0, FN_D1, FN_D2, ++ FN_D3, FN_D4, FN_D5, FN_D6, ++ FN_D7, FN_D8, FN_D9, FN_D10, ++ FN_D11, FN_RD_WR_B, FN_IRQ0, FN_MLB_CLK, ++ FN_IRQ1_A, ++ ++ /* IPSR3 */ ++ FN_MLB_SIG, FN_RX5_B, FN_SDA3_A, FN_IRQ2_A, ++ FN_MLB_DAT, FN_TX5_B, FN_SCL3_A, FN_IRQ3_A, ++ FN_SDSELF_B, FN_SD1_CMD_B, FN_SCIF_CLK, FN_AUDIO_CLKOUT_B, ++ FN_CAN_CLK_B, FN_SDA3_B, FN_SD1_CLK_B, FN_HTX0_A, ++ FN_TX0_A, FN_SD1_DAT0_B, FN_HRX0_A, FN_RX0_A, ++ FN_SD1_DAT1_B, FN_HSCK0, FN_SCK0, FN_SCL3_B, ++ FN_SD1_DAT2_B, FN_HCTS0_A, FN_CTS0, FN_SD1_DAT3_B, ++ FN_HRTS0_A, FN_RTS0, FN_SSI_SCK4, FN_DU0_DR0, ++ FN_LCDOUT0, FN_AUDATA2, FN_ARM_TRACEDATA_2, ++ FN_SDA3_C, FN_ADICHS1, FN_TS_SDEN0_B, FN_SSI_WS4, ++ FN_DU0_DR1, FN_LCDOUT1, FN_AUDATA3, FN_ARM_TRACEDATA_3, ++ FN_SCL3_C, FN_ADICHS2, FN_TS_SPSYNC0_B, ++ FN_DU0_DR2, FN_LCDOUT2, FN_DU0_DR3, FN_LCDOUT3, ++ FN_DU0_DR4, FN_LCDOUT4, FN_DU0_DR5, FN_LCDOUT5, ++ FN_DU0_DR6, FN_LCDOUT6, ++ ++ /* IPSR4 */ ++ FN_DU0_DR7, FN_LCDOUT7, FN_DU0_DG0, FN_LCDOUT8, ++ FN_AUDATA4, FN_ARM_TRACEDATA_4, FN_TX1_D, ++ FN_CAN0_TX_A, FN_ADICHS0, FN_DU0_DG1, FN_LCDOUT9, ++ FN_AUDATA5, FN_ARM_TRACEDATA_5, FN_RX1_D, ++ FN_CAN0_RX_A, FN_ADIDATA, FN_DU0_DG2, FN_LCDOUT10, ++ FN_DU0_DG3, FN_LCDOUT11, FN_DU0_DG4, FN_LCDOUT12, ++ FN_RX0_B, FN_DU0_DG5, FN_LCDOUT13, FN_TX0_B, ++ FN_DU0_DG6, FN_LCDOUT14, FN_RX4_A, FN_DU0_DG7, ++ FN_LCDOUT15, FN_TX4_A, FN_SSI_SCK2_B, FN_VI0_R0_B, ++ FN_DU0_DB0, FN_LCDOUT16, FN_AUDATA6, FN_ARM_TRACEDATA_6, ++ FN_GPSCLK_A, FN_PWM0_A, FN_ADICLK, FN_TS_SDAT0_B, ++ FN_AUDIO_CLKC, FN_VI0_R1_B, FN_DU0_DB1, FN_LCDOUT17, ++ FN_AUDATA7, FN_ARM_TRACEDATA_7, FN_GPSIN_A, ++ FN_ADICS_SAMP, FN_TS_SCK0_B, FN_VI0_R2_B, FN_DU0_DB2, ++ FN_LCDOUT18, FN_VI0_R3_B, FN_DU0_DB3, FN_LCDOUT19, ++ FN_VI0_R4_B, FN_DU0_DB4, FN_LCDOUT20, ++ ++ /* IPSR5 */ ++ FN_VI0_R5_B, FN_DU0_DB5, FN_LCDOUT21, FN_VI1_DATA10_B, ++ FN_DU0_DB6, FN_LCDOUT22, FN_VI1_DATA11_B, ++ FN_DU0_DB7, FN_LCDOUT23, FN_DU0_DOTCLKIN, ++ FN_QSTVA_QVS, FN_DU0_DOTCLKO_UT0, FN_QCLK, ++ FN_DU0_DOTCLKO_UT1, FN_QSTVB_QVE, FN_AUDIO_CLKOUT_A, ++ FN_REMOCON_C, FN_SSI_WS2_B, FN_DU0_EXHSYNC_DU0_HSYNC, ++ FN_QSTH_QHS, FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, ++ FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, ++ FN_QCPV_QDE, FN_FMCLK_D, FN_SSI_SCK1_A, FN_DU0_DISP, ++ FN_QPOLA, FN_AUDCK, FN_ARM_TRACECLK, ++ FN_BPFCLK_D, FN_SSI_WS1_A, FN_DU0_CDE, FN_QPOLB, ++ FN_AUDSYNC, FN_ARM_TRACECTL, FN_FMIN_D, ++ FN_SD1_CD_B, FN_SSI_SCK78, FN_HSPI_RX0_B, FN_TX1_B, ++ FN_SD1_WP_B, FN_SSI_WS78, FN_HSPI_CLK0_B, FN_RX1_B, ++ FN_CAN_CLK_D, FN_SSI_SDATA8, FN_SSI_SCK2_A, FN_HSPI_CS0_B, ++ FN_TX2_A, FN_CAN0_TX_B, FN_SSI_SDATA7, FN_HSPI_TX0_B, ++ FN_RX2_A, FN_CAN0_RX_B, ++ ++ /* IPSR6 */ ++ FN_SSI_SCK6, FN_HSPI_RX2_A, FN_FMCLK_B, FN_CAN1_TX_B, ++ FN_SSI_WS6, FN_HSPI_CLK2_A, FN_BPFCLK_B, FN_CAN1_RX_B, ++ FN_SSI_SDATA6, FN_HSPI_TX2_A, FN_FMIN_B, FN_SSI_SCK5, ++ FN_RX4_C, FN_SSI_WS5, FN_TX4_C, FN_SSI_SDATA5, ++ FN_RX0_D, FN_SSI_WS34, FN_ARM_TRACEDATA_8, ++ FN_SSI_SDATA4, FN_SSI_WS2_A, FN_ARM_TRACEDATA_9, ++ FN_SSI_SDATA3, FN_ARM_TRACEDATA_10, ++ FN_SSI_SCK012, FN_ARM_TRACEDATA_11, ++ FN_TX0_D, FN_SSI_WS012, FN_ARM_TRACEDATA_12, ++ FN_SSI_SDATA2, FN_HSPI_CS2_A, FN_ARM_TRACEDATA_13, ++ FN_SDA1_A, FN_SSI_SDATA1, FN_ARM_TRACEDATA_14, ++ FN_SCL1_A, FN_SCK2_A, FN_SSI_SDATA0, ++ FN_ARM_TRACEDATA_15, ++ FN_SD0_CLK, FN_SUB_TDO, FN_SD0_CMD, FN_SUB_TRST, ++ FN_SD0_DAT0, FN_SUB_TMS, FN_SD0_DAT1, FN_SUB_TCK, ++ FN_SD0_DAT2, FN_SUB_TDI, ++ ++ /* IPSR7 */ ++ FN_SD0_DAT3, FN_IRQ1_B, FN_SD0_CD, FN_TX5_A, ++ FN_SD0_WP, FN_RX5_A, FN_VI1_CLKENB, FN_HSPI_CLK0_A, ++ FN_HTX1_A, FN_RTS1_C, FN_VI1_FIELD, FN_HSPI_CS0_A, ++ FN_HRX1_A, FN_SCK1_C, FN_VI1_HSYNC, FN_HSPI_RX0_A, ++ FN_HRTS1_A, FN_FMCLK_A, FN_RX1_C, FN_VI1_VSYNC, ++ FN_HSPI_TX0, FN_HCTS1_A, FN_BPFCLK_A, FN_TX1_C, ++ FN_TCLK0, FN_HSCK1_A, FN_FMIN_A, FN_IRQ2_C, ++ FN_CTS1_C, FN_SPEEDIN, FN_VI0_CLK, FN_CAN_CLK_A, ++ FN_VI0_CLKENB, FN_SD2_DAT2_B, FN_VI1_DATA0, FN_DU1_DG6, ++ FN_HSPI_RX1_A, FN_RX4_B, FN_VI0_FIELD, FN_SD2_DAT3_B, ++ FN_VI0_R3_C, FN_VI1_DATA1, FN_DU1_DG7, FN_HSPI_CLK1_A, ++ FN_TX4_B, FN_VI0_HSYNC, FN_SD2_CD_B, FN_VI1_DATA2, ++ FN_DU1_DR2, FN_HSPI_CS1_A, FN_RX3_B, ++ ++ /* IPSR8 */ ++ FN_VI0_VSYNC, FN_SD2_WP_B, FN_VI1_DATA3, FN_DU1_DR3, ++ FN_HSPI_TX1_A, FN_TX3_B, FN_VI0_DATA0_VI0_B0, ++ FN_DU1_DG2, FN_IRQ2_B, FN_RX3_D, FN_VI0_DATA1_VI0_B1, ++ FN_DU1_DG3, FN_IRQ3_B, FN_TX3_D, FN_VI0_DATA2_VI0_B2, ++ FN_DU1_DG4, FN_RX0_C, FN_VI0_DATA3_VI0_B3, ++ FN_DU1_DG5, FN_TX1_A, FN_TX0_C, FN_VI0_DATA4_VI0_B4, ++ FN_DU1_DB2, FN_RX1_A, FN_VI0_DATA5_VI0_B5, ++ FN_DU1_DB3, FN_SCK1_A, FN_PWM4, FN_HSCK1_B, ++ FN_VI0_DATA6_VI0_G0, FN_DU1_DB4, FN_CTS1_A, ++ FN_PWM5, FN_VI0_DATA7_VI0_G1, FN_DU1_DB5, ++ FN_RTS1_A, FN_VI0_G2, FN_SD2_CLK_B, FN_VI1_DATA4, ++ FN_DU1_DR4, FN_HTX1_B, FN_VI0_G3, FN_SD2_CMD_B, ++ FN_VI1_DATA5, FN_DU1_DR5, FN_HRX1_B, ++ ++ /* IPSR9 */ ++ FN_VI0_G4, FN_SD2_DAT0_B, FN_VI1_DATA6, FN_DU1_DR6, ++ FN_HRTS1_B, FN_VI0_G5, FN_SD2_DAT1_B, FN_VI1_DATA7, ++ FN_DU1_DR7, FN_HCTS1_B, FN_VI0_R0_A, FN_VI1_CLK, ++ FN_ETH_REF_CLK, FN_DU1_DOTCLKIN, FN_VI0_R1_A, ++ FN_VI1_DATA8, FN_DU1_DB6, FN_ETH_TXD0, FN_PWM2, ++ FN_TCLK1, FN_VI0_R2_A, FN_VI1_DATA9, FN_DU1_DB7, ++ FN_ETH_TXD1, FN_PWM3, FN_VI0_R3_A, FN_ETH_CRS_DV, ++ FN_IECLK, FN_SCK2_C, FN_VI0_R4_A, FN_ETH_TX_EN, ++ FN_IETX, FN_TX2_C, FN_VI0_R5_A, FN_ETH_RX_ER, ++ FN_FMCLK_C, FN_IERX, FN_RX2_C, FN_VI1_DATA10_A, ++ FN_DU1_DOTCLKOUT, FN_ETH_RXD0, FN_BPFCLK_C, ++ FN_TX2_D, FN_SDA2_C, FN_VI1_DATA11_A, ++ FN_DU1_EXHSYNC_DU1_HSYNC, FN_ETH_RXD1, FN_FMIN_C, ++ FN_RX2_D, FN_SCL2_C, ++ ++ /* IPSR10 */ ++ FN_SD2_CLK_A, FN_DU1_EXVSYNC_DU1_VSYNC, FN_ATARD1, ++ FN_ETH_MDC, FN_SDA1_B, FN_SD2_CMD_A, ++ FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_ATAWR1, ++ FN_ETH_MDIO, FN_SCL1_B, FN_SD2_DAT0_A, FN_DU1_DISP, ++ FN_ATACS01, FN_DREQ1_B, FN_ETH_LINK, FN_CAN1_RX_A, ++ FN_SD2_DAT1_A, FN_DU1_CDE, FN_ATACS11, FN_DACK1_B, ++ FN_ETH_MAGIC, FN_CAN1_TX_A, FN_PWM6, FN_SD2_DAT2_A, ++ FN_VI1_DATA12, FN_DREQ2_B, FN_ATADIR1, FN_HSPI_CLK2_B, ++ FN_GPSCLK_B, FN_SD2_DAT3_A, FN_VI1_DATA13, FN_DACK2_B, ++ FN_ATAG1, FN_HSPI_CS2_B, FN_GPSIN_B, FN_SD2_CD_A, ++ FN_VI1_DATA14, FN_EX_WAIT1_B, FN_DREQ0_B, FN_HSPI_RX2_B, ++ FN_REMOCON_A, FN_SD2_WP_A, FN_VI1_DATA15, FN_EX_WAIT2_B, ++ FN_DACK0_B, FN_HSPI_TX2_B, FN_CAN_CLK_C, ++ ++ /* SEL */ ++ FN_SEL_SCIF5_A, FN_SEL_SCIF5_B, ++ FN_SEL_SCIF4_A, FN_SEL_SCIF4_B, FN_SEL_SCIF4_C, ++ FN_SEL_SCIF3_A, FN_SEL_SCIF3_B, FN_SEL_SCIF3_C, FN_SEL_SCIF3_D, ++ FN_SEL_SCIF2_A, FN_SEL_SCIF2_B, FN_SEL_SCIF2_C, FN_SEL_SCIF2_D, FN_SEL_SCIF2_E, ++ FN_SEL_SCIF1_A, FN_SEL_SCIF1_B, FN_SEL_SCIF1_C, FN_SEL_SCIF1_D, ++ FN_SEL_SCIF0_A, FN_SEL_SCIF0_B, FN_SEL_SCIF0_C, FN_SEL_SCIF0_D, ++ FN_SEL_SSI2_A, FN_SEL_SSI2_B, ++ FN_SEL_SSI1_A, FN_SEL_SSI1_B, ++ FN_SEL_VI1_A, FN_SEL_VI1_B, ++ FN_SEL_VI0_A, FN_SEL_VI0_B, FN_SEL_VI0_C, FN_SEL_VI0_D, ++ FN_SEL_SD2_A, FN_SEL_SD2_B, ++ FN_SEL_SD1_A, FN_SEL_SD1_B, ++ FN_SEL_IRQ3_A, FN_SEL_IRQ3_B, ++ FN_SEL_IRQ2_A, FN_SEL_IRQ2_B, FN_SEL_IRQ2_C, ++ FN_SEL_IRQ1_A, FN_SEL_IRQ1_B, ++ FN_SEL_DREQ2_A, FN_SEL_DREQ2_B, ++ FN_SEL_DREQ1_A, FN_SEL_DREQ1_B, ++ FN_SEL_DREQ0_A, FN_SEL_DREQ0_B, ++ FN_SEL_WAIT2_A, FN_SEL_WAIT2_B, ++ FN_SEL_WAIT1_A, FN_SEL_WAIT1_B, ++ FN_SEL_CAN1_A, FN_SEL_CAN1_B, ++ FN_SEL_CAN0_A, FN_SEL_CAN0_B, ++ FN_SEL_CANCLK_A, FN_SEL_CANCLK_B, ++ FN_SEL_CANCLK_C, FN_SEL_CANCLK_D, ++ FN_SEL_HSCIF1_A, FN_SEL_HSCIF1_B, ++ FN_SEL_HSCIF0_A, FN_SEL_HSCIF0_B, ++ FN_SEL_REMOCON_A, FN_SEL_REMOCON_B, FN_SEL_REMOCON_C, ++ FN_SEL_FM_A, FN_SEL_FM_B, FN_SEL_FM_C, FN_SEL_FM_D, ++ FN_SEL_GPS_A, FN_SEL_GPS_B, FN_SEL_GPS_C, ++ FN_SEL_TSIF0_A, FN_SEL_TSIF0_B, ++ FN_SEL_HSPI2_A, FN_SEL_HSPI2_B, ++ FN_SEL_HSPI1_A, FN_SEL_HSPI1_B, ++ FN_SEL_HSPI0_A, FN_SEL_HSPI0_B, ++ FN_SEL_I2C3_A, FN_SEL_I2C3_B, FN_SEL_I2C3_C, ++ FN_SEL_I2C2_A, FN_SEL_I2C2_B, FN_SEL_I2C2_C, ++ FN_SEL_I2C1_A, FN_SEL_I2C1_B, ++ PINMUX_FUNCTION_END, ++ ++ PINMUX_MARK_BEGIN, ++ ++ /* GPSR0 */ ++ PENC0_MARK, PENC1_MARK, A1_MARK, A2_MARK, A3_MARK, ++ ++ /* GPSR1 */ ++ WE0_MARK, ++ ++ /* GPSR2 */ ++ AUDIO_CLKA_MARK, ++ AUDIO_CLKB_MARK, ++ ++ /* GPSR3 */ ++ SSI_SCK34_MARK, ++ ++ /* GPSR4 */ ++ AVS1_MARK, ++ AVS2_MARK, ++ ++ VI0_R0_C_MARK, /* see GPIO_FN_VI0_R0_A */ ++ VI0_R1_C_MARK, /* see GPIO_FN_VI0_R1_A */ ++ VI0_R2_C_MARK, /* see GPIO_FN_VI0_R2_A */ ++ /* VI0_R3_C_MARK, see GPIO_FN_VI0_R3_A */ ++ VI0_R4_C_MARK, /* see GPIO_FN_VI0_R4_A */ ++ VI0_R5_C_MARK, /* see GPIO_FN_VI0_R5_A */ ++ ++ VI0_R0_D_MARK, /* see GPIO_FN_VI0_R0_B */ ++ VI0_R1_D_MARK, /* see GPIO_FN_VI0_R1_B */ ++ VI0_R2_D_MARK, /* see GPIO_FN_VI0_R2_B */ ++ VI0_R3_D_MARK, /* see GPIO_FN_VI0_R3_B */ ++ VI0_R4_D_MARK, /* see GPIO_FN_VI0_R4_B */ ++ VI0_R5_D_MARK, /* see GPIO_FN_VI0_R5_B */ ++ ++ /* IPSR0 */ ++ PRESETOUT_MARK, PWM1_MARK, AUDATA0_MARK, ++ ARM_TRACEDATA_0_MARK, GPSCLK_C_MARK, USB_OVC0_MARK, ++ TX2_E_MARK, SDA2_B_MARK, AUDATA1_MARK, ARM_TRACEDATA_1_MARK, ++ GPSIN_C_MARK, USB_OVC1_MARK, RX2_E_MARK, SCL2_B_MARK, ++ SD1_DAT2_A_MARK, MMC_D2_MARK, BS_MARK, ++ ATADIR0_A_MARK, SDSELF_A_MARK, PWM4_B_MARK, SD1_DAT3_A_MARK, ++ MMC_D3_MARK, A0_MARK, ATAG0_A_MARK, REMOCON_B_MARK, ++ A4_MARK, A5_MARK, A6_MARK, A7_MARK, ++ A8_MARK, A9_MARK, A10_MARK, A11_MARK, ++ A12_MARK, A13_MARK, A14_MARK, A15_MARK, ++ A16_MARK, A17_MARK, A18_MARK, A19_MARK, ++ ++ /* IPSR1 */ ++ A20_MARK, HSPI_CS1_B_MARK, A21_MARK, ++ HSPI_CLK1_B_MARK, A22_MARK, HRTS0_B_MARK, ++ RX2_B_MARK, DREQ2_A_MARK, A23_MARK, HTX0_B_MARK, ++ TX2_B_MARK, DACK2_A_MARK, TS_SDEN0_A_MARK, ++ SD1_CD_A_MARK, MMC_D6_MARK, A24_MARK, DREQ1_A_MARK, ++ HRX0_B_MARK, TS_SPSYNC0_A_MARK, SD1_WP_A_MARK, ++ MMC_D7_MARK, A25_MARK, DACK1_A_MARK, HCTS0_B_MARK, ++ RX3_C_MARK, TS_SDAT0_A_MARK, CLKOUT_MARK, ++ HSPI_TX1_B_MARK, PWM0_B_MARK, CS0_MARK, ++ HSPI_RX1_B_MARK, SSI_SCK1_B_MARK, ++ ATAG0_B_MARK, CS1_A26_MARK, SDA2_A_MARK, SCK2_B_MARK, ++ MMC_D5_MARK, ATADIR0_B_MARK, RD_WR_MARK, WE1_MARK, ++ ATAWR0_B_MARK, SSI_WS1_B_MARK, EX_CS0_MARK, SCL2_A_MARK, ++ TX3_C_MARK, TS_SCK0_A_MARK, EX_CS1_MARK, MMC_D4_MARK, ++ ++ /* IPSR2 */ ++ SD1_CLK_A_MARK, MMC_CLK_MARK, ATACS00_MARK, EX_CS2_MARK, ++ SD1_CMD_A_MARK, MMC_CMD_MARK, ATACS10_MARK, EX_CS3_MARK, ++ SD1_DAT0_A_MARK, MMC_D0_MARK, ATARD0_MARK, ++ EX_CS4_MARK, EX_WAIT1_A_MARK, SD1_DAT1_A_MARK, ++ MMC_D1_MARK, ATAWR0_A_MARK, EX_CS5_MARK, EX_WAIT2_A_MARK, ++ DREQ0_A_MARK, RX3_A_MARK, DACK0_MARK, TX3_A_MARK, ++ DRACK0_MARK, EX_WAIT0_MARK, PWM0_C_MARK, D0_MARK, ++ D1_MARK, D2_MARK, D3_MARK, D4_MARK, ++ D5_MARK, D6_MARK, D7_MARK, D8_MARK, ++ D9_MARK, D10_MARK, D11_MARK, RD_WR_B_MARK, ++ IRQ0_MARK, MLB_CLK_MARK, IRQ1_A_MARK, ++ ++ /* IPSR3 */ ++ MLB_SIG_MARK, RX5_B_MARK, SDA3_A_MARK, IRQ2_A_MARK, ++ MLB_DAT_MARK, TX5_B_MARK, SCL3_A_MARK, IRQ3_A_MARK, ++ SDSELF_B_MARK, SD1_CMD_B_MARK, SCIF_CLK_MARK, AUDIO_CLKOUT_B_MARK, ++ CAN_CLK_B_MARK, SDA3_B_MARK, SD1_CLK_B_MARK, HTX0_A_MARK, ++ TX0_A_MARK, SD1_DAT0_B_MARK, HRX0_A_MARK, ++ RX0_A_MARK, SD1_DAT1_B_MARK, HSCK0_MARK, ++ SCK0_MARK, SCL3_B_MARK, SD1_DAT2_B_MARK, ++ HCTS0_A_MARK, CTS0_MARK, SD1_DAT3_B_MARK, ++ HRTS0_A_MARK, RTS0_MARK, SSI_SCK4_MARK, ++ DU0_DR0_MARK, LCDOUT0_MARK, AUDATA2_MARK, ARM_TRACEDATA_2_MARK, ++ SDA3_C_MARK, ADICHS1_MARK, TS_SDEN0_B_MARK, ++ SSI_WS4_MARK, DU0_DR1_MARK, LCDOUT1_MARK, AUDATA3_MARK, ++ ARM_TRACEDATA_3_MARK, SCL3_C_MARK, ADICHS2_MARK, ++ TS_SPSYNC0_B_MARK, DU0_DR2_MARK, LCDOUT2_MARK, ++ DU0_DR3_MARK, LCDOUT3_MARK, DU0_DR4_MARK, LCDOUT4_MARK, ++ DU0_DR5_MARK, LCDOUT5_MARK, DU0_DR6_MARK, LCDOUT6_MARK, ++ ++ /* IPSR4 */ ++ DU0_DR7_MARK, LCDOUT7_MARK, DU0_DG0_MARK, LCDOUT8_MARK, ++ AUDATA4_MARK, ARM_TRACEDATA_4_MARK, ++ TX1_D_MARK, CAN0_TX_A_MARK, ADICHS0_MARK, DU0_DG1_MARK, ++ LCDOUT9_MARK, AUDATA5_MARK, ARM_TRACEDATA_5_MARK, ++ RX1_D_MARK, CAN0_RX_A_MARK, ADIDATA_MARK, DU0_DG2_MARK, ++ LCDOUT10_MARK, DU0_DG3_MARK, LCDOUT11_MARK, DU0_DG4_MARK, ++ LCDOUT12_MARK, RX0_B_MARK, DU0_DG5_MARK, LCDOUT13_MARK, ++ TX0_B_MARK, DU0_DG6_MARK, LCDOUT14_MARK, RX4_A_MARK, ++ DU0_DG7_MARK, LCDOUT15_MARK, TX4_A_MARK, SSI_SCK2_B_MARK, ++ VI0_R0_B_MARK, DU0_DB0_MARK, LCDOUT16_MARK, AUDATA6_MARK, ++ ARM_TRACEDATA_6_MARK, GPSCLK_A_MARK, PWM0_A_MARK, ++ ADICLK_MARK, TS_SDAT0_B_MARK, AUDIO_CLKC_MARK, ++ VI0_R1_B_MARK, DU0_DB1_MARK, LCDOUT17_MARK, AUDATA7_MARK, ++ ARM_TRACEDATA_7_MARK, GPSIN_A_MARK, ADICS_SAMP_MARK, ++ TS_SCK0_B_MARK, VI0_R2_B_MARK, DU0_DB2_MARK, LCDOUT18_MARK, ++ VI0_R3_B_MARK, DU0_DB3_MARK, LCDOUT19_MARK, VI0_R4_B_MARK, ++ DU0_DB4_MARK, LCDOUT20_MARK, ++ ++ /* IPSR5 */ ++ VI0_R5_B_MARK, DU0_DB5_MARK, LCDOUT21_MARK, VI1_DATA10_B_MARK, ++ DU0_DB6_MARK, LCDOUT22_MARK, VI1_DATA11_B_MARK, ++ DU0_DB7_MARK, LCDOUT23_MARK, DU0_DOTCLKIN_MARK, ++ QSTVA_QVS_MARK, DU0_DOTCLKO_UT0_MARK, ++ QCLK_MARK, DU0_DOTCLKO_UT1_MARK, QSTVB_QVE_MARK, ++ AUDIO_CLKOUT_A_MARK, REMOCON_C_MARK, SSI_WS2_B_MARK, ++ DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK, ++ DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, ++ DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, ++ QCPV_QDE_MARK, FMCLK_D_MARK, SSI_SCK1_A_MARK, ++ DU0_DISP_MARK, QPOLA_MARK, AUDCK_MARK, ARM_TRACECLK_MARK, ++ BPFCLK_D_MARK, SSI_WS1_A_MARK, DU0_CDE_MARK, QPOLB_MARK, ++ AUDSYNC_MARK, ARM_TRACECTL_MARK, FMIN_D_MARK, ++ SD1_CD_B_MARK, SSI_SCK78_MARK, HSPI_RX0_B_MARK, ++ TX1_B_MARK, SD1_WP_B_MARK, SSI_WS78_MARK, HSPI_CLK0_B_MARK, ++ RX1_B_MARK, CAN_CLK_D_MARK, SSI_SDATA8_MARK, ++ SSI_SCK2_A_MARK, HSPI_CS0_B_MARK, ++ TX2_A_MARK, CAN0_TX_B_MARK, SSI_SDATA7_MARK, ++ HSPI_TX0_B_MARK, RX2_A_MARK, CAN0_RX_B_MARK, ++ ++ /* IPSR6 */ ++ SSI_SCK6_MARK, HSPI_RX2_A_MARK, FMCLK_B_MARK, ++ CAN1_TX_B_MARK, SSI_WS6_MARK, HSPI_CLK2_A_MARK, ++ BPFCLK_B_MARK, CAN1_RX_B_MARK, SSI_SDATA6_MARK, ++ HSPI_TX2_A_MARK, FMIN_B_MARK, SSI_SCK5_MARK, ++ RX4_C_MARK, SSI_WS5_MARK, TX4_C_MARK, SSI_SDATA5_MARK, ++ RX0_D_MARK, SSI_WS34_MARK, ARM_TRACEDATA_8_MARK, ++ SSI_SDATA4_MARK, SSI_WS2_A_MARK, ARM_TRACEDATA_9_MARK, ++ SSI_SDATA3_MARK, ARM_TRACEDATA_10_MARK, ++ SSI_SCK012_MARK, ARM_TRACEDATA_11_MARK, ++ TX0_D_MARK, SSI_WS012_MARK, ARM_TRACEDATA_12_MARK, ++ SSI_SDATA2_MARK, HSPI_CS2_A_MARK, ++ ARM_TRACEDATA_13_MARK, SDA1_A_MARK, SSI_SDATA1_MARK, ++ ARM_TRACEDATA_14_MARK, SCL1_A_MARK, SCK2_A_MARK, ++ SSI_SDATA0_MARK, ARM_TRACEDATA_15_MARK, ++ SD0_CLK_MARK, SUB_TDO_MARK, SD0_CMD_MARK, SUB_TRST_MARK, ++ SD0_DAT0_MARK, SUB_TMS_MARK, SD0_DAT1_MARK, SUB_TCK_MARK, ++ SD0_DAT2_MARK, SUB_TDI_MARK, ++ ++ /* IPSR7 */ ++ SD0_DAT3_MARK, IRQ1_B_MARK, SD0_CD_MARK, TX5_A_MARK, ++ SD0_WP_MARK, RX5_A_MARK, VI1_CLKENB_MARK, ++ HSPI_CLK0_A_MARK, HTX1_A_MARK, RTS1_C_MARK, VI1_FIELD_MARK, ++ HSPI_CS0_A_MARK, HRX1_A_MARK, SCK1_C_MARK, VI1_HSYNC_MARK, ++ HSPI_RX0_A_MARK, HRTS1_A_MARK, FMCLK_A_MARK, RX1_C_MARK, ++ VI1_VSYNC_MARK, HSPI_TX0_MARK, HCTS1_A_MARK, BPFCLK_A_MARK, ++ TX1_C_MARK, TCLK0_MARK, HSCK1_A_MARK, FMIN_A_MARK, ++ IRQ2_C_MARK, CTS1_C_MARK, SPEEDIN_MARK, VI0_CLK_MARK, ++ CAN_CLK_A_MARK, VI0_CLKENB_MARK, SD2_DAT2_B_MARK, ++ VI1_DATA0_MARK, DU1_DG6_MARK, HSPI_RX1_A_MARK, ++ RX4_B_MARK, VI0_FIELD_MARK, SD2_DAT3_B_MARK, ++ VI0_R3_C_MARK, VI1_DATA1_MARK, DU1_DG7_MARK, HSPI_CLK1_A_MARK, ++ TX4_B_MARK, VI0_HSYNC_MARK, SD2_CD_B_MARK, VI1_DATA2_MARK, ++ DU1_DR2_MARK, HSPI_CS1_A_MARK, RX3_B_MARK, ++ ++ /* IPSR8 */ ++ VI0_VSYNC_MARK, SD2_WP_B_MARK, VI1_DATA3_MARK, DU1_DR3_MARK, ++ HSPI_TX1_A_MARK, TX3_B_MARK, VI0_DATA0_VI0_B0_MARK, ++ DU1_DG2_MARK, IRQ2_B_MARK, RX3_D_MARK, VI0_DATA1_VI0_B1_MARK, ++ DU1_DG3_MARK, IRQ3_B_MARK, TX3_D_MARK, VI0_DATA2_VI0_B2_MARK, ++ DU1_DG4_MARK, RX0_C_MARK, VI0_DATA3_VI0_B3_MARK, ++ DU1_DG5_MARK, TX1_A_MARK, TX0_C_MARK, VI0_DATA4_VI0_B4_MARK, ++ DU1_DB2_MARK, RX1_A_MARK, VI0_DATA5_VI0_B5_MARK, ++ DU1_DB3_MARK, SCK1_A_MARK, PWM4_MARK, HSCK1_B_MARK, ++ VI0_DATA6_VI0_G0_MARK, DU1_DB4_MARK, CTS1_A_MARK, ++ PWM5_MARK, VI0_DATA7_VI0_G1_MARK, DU1_DB5_MARK, ++ RTS1_A_MARK, VI0_G2_MARK, SD2_CLK_B_MARK, VI1_DATA4_MARK, ++ DU1_DR4_MARK, HTX1_B_MARK, VI0_G3_MARK, SD2_CMD_B_MARK, ++ VI1_DATA5_MARK, DU1_DR5_MARK, HRX1_B_MARK, ++ ++ /* IPSR9 */ ++ VI0_G4_MARK, SD2_DAT0_B_MARK, VI1_DATA6_MARK, ++ DU1_DR6_MARK, HRTS1_B_MARK, VI0_G5_MARK, SD2_DAT1_B_MARK, ++ VI1_DATA7_MARK, DU1_DR7_MARK, HCTS1_B_MARK, VI0_R0_A_MARK, ++ VI1_CLK_MARK, ETH_REF_CLK_MARK, DU1_DOTCLKIN_MARK, ++ VI0_R1_A_MARK, VI1_DATA8_MARK, DU1_DB6_MARK, ETH_TXD0_MARK, ++ PWM2_MARK, TCLK1_MARK, VI0_R2_A_MARK, VI1_DATA9_MARK, ++ DU1_DB7_MARK, ETH_TXD1_MARK, PWM3_MARK, VI0_R3_A_MARK, ++ ETH_CRS_DV_MARK, IECLK_MARK, SCK2_C_MARK, ++ VI0_R4_A_MARK, ETH_TX_EN_MARK, IETX_MARK, ++ TX2_C_MARK, VI0_R5_A_MARK, ETH_RX_ER_MARK, FMCLK_C_MARK, ++ IERX_MARK, RX2_C_MARK, VI1_DATA10_A_MARK, ++ DU1_DOTCLKOUT_MARK, ETH_RXD0_MARK, ++ BPFCLK_C_MARK, TX2_D_MARK, SDA2_C_MARK, VI1_DATA11_A_MARK, ++ DU1_EXHSYNC_DU1_HSYNC_MARK, ETH_RXD1_MARK, FMIN_C_MARK, ++ RX2_D_MARK, SCL2_C_MARK, ++ ++ /* IPSR10 */ ++ SD2_CLK_A_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, ATARD1_MARK, ++ ETH_MDC_MARK, SDA1_B_MARK, SD2_CMD_A_MARK, ++ DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, ATAWR1_MARK, ++ ETH_MDIO_MARK, SCL1_B_MARK, SD2_DAT0_A_MARK, ++ DU1_DISP_MARK, ATACS01_MARK, DREQ1_B_MARK, ETH_LINK_MARK, ++ CAN1_RX_A_MARK, SD2_DAT1_A_MARK, DU1_CDE_MARK, ++ ATACS11_MARK, DACK1_B_MARK, ETH_MAGIC_MARK, CAN1_TX_A_MARK, ++ PWM6_MARK, SD2_DAT2_A_MARK, VI1_DATA12_MARK, ++ DREQ2_B_MARK, ATADIR1_MARK, HSPI_CLK2_B_MARK, ++ GPSCLK_B_MARK, SD2_DAT3_A_MARK, VI1_DATA13_MARK, ++ DACK2_B_MARK, ATAG1_MARK, HSPI_CS2_B_MARK, ++ GPSIN_B_MARK, SD2_CD_A_MARK, VI1_DATA14_MARK, ++ EX_WAIT1_B_MARK, DREQ0_B_MARK, HSPI_RX2_B_MARK, ++ REMOCON_A_MARK, SD2_WP_A_MARK, VI1_DATA15_MARK, ++ EX_WAIT2_B_MARK, DACK0_B_MARK, ++ HSPI_TX2_B_MARK, CAN_CLK_C_MARK, ++ ++ PINMUX_MARK_END, ++}; ++ ++static const pinmux_enum_t pinmux_data[] = { ++ PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ ++ ++ PINMUX_DATA(PENC0_MARK, FN_PENC0), ++ PINMUX_DATA(PENC1_MARK, FN_PENC1), ++ PINMUX_DATA(A1_MARK, FN_A1), ++ PINMUX_DATA(A2_MARK, FN_A2), ++ PINMUX_DATA(A3_MARK, FN_A3), ++ PINMUX_DATA(WE0_MARK, FN_WE0), ++ PINMUX_DATA(AUDIO_CLKA_MARK, FN_AUDIO_CLKA), ++ PINMUX_DATA(AUDIO_CLKB_MARK, FN_AUDIO_CLKB), ++ PINMUX_DATA(SSI_SCK34_MARK, FN_SSI_SCK34), ++ PINMUX_DATA(AVS1_MARK, FN_AVS1), ++ PINMUX_DATA(AVS2_MARK, FN_AVS2), ++ ++ /* IPSR0 */ ++ PINMUX_IPSR_DATA(IP0_1_0, PRESETOUT), ++ PINMUX_IPSR_DATA(IP0_1_0, PWM1), ++ ++ PINMUX_IPSR_DATA(IP0_4_2, AUDATA0), ++ PINMUX_IPSR_DATA(IP0_4_2, ARM_TRACEDATA_0), ++ PINMUX_IPSR_MSEL(IP0_4_2, GPSCLK_C, SEL_GPS_C), ++ PINMUX_IPSR_DATA(IP0_4_2, USB_OVC0), ++ PINMUX_IPSR_DATA(IP0_4_2, TX2_E), ++ PINMUX_IPSR_MSEL(IP0_4_2, SDA2_B, SEL_I2C2_B), ++ ++ PINMUX_IPSR_DATA(IP0_7_5, AUDATA1), ++ PINMUX_IPSR_DATA(IP0_7_5, ARM_TRACEDATA_1), ++ PINMUX_IPSR_MSEL(IP0_7_5, GPSIN_C, SEL_GPS_C), ++ PINMUX_IPSR_DATA(IP0_7_5, USB_OVC1), ++ PINMUX_IPSR_MSEL(IP0_7_5, RX2_E, SEL_SCIF2_E), ++ PINMUX_IPSR_MSEL(IP0_7_5, SCL2_B, SEL_I2C2_B), ++ ++ PINMUX_IPSR_MSEL(IP0_11_8, SD1_DAT2_A, SEL_SD1_A), ++ PINMUX_IPSR_DATA(IP0_11_8, MMC_D2), ++ PINMUX_IPSR_DATA(IP0_11_8, BS), ++ PINMUX_IPSR_DATA(IP0_11_8, ATADIR0_A), ++ PINMUX_IPSR_DATA(IP0_11_8, SDSELF_A), ++ PINMUX_IPSR_DATA(IP0_11_8, PWM4_B), ++ ++ PINMUX_IPSR_MSEL(IP0_14_12, SD1_DAT3_A, SEL_SD1_A), ++ PINMUX_IPSR_DATA(IP0_14_12, MMC_D3), ++ PINMUX_IPSR_DATA(IP0_14_12, A0), ++ PINMUX_IPSR_DATA(IP0_14_12, ATAG0_A), ++ PINMUX_IPSR_MSEL(IP0_14_12, REMOCON_B, SEL_REMOCON_B), ++ ++ PINMUX_IPSR_DATA(IP0_15, A4), ++ PINMUX_IPSR_DATA(IP0_16, A5), ++ PINMUX_IPSR_DATA(IP0_17, A6), ++ PINMUX_IPSR_DATA(IP0_18, A7), ++ PINMUX_IPSR_DATA(IP0_19, A8), ++ PINMUX_IPSR_DATA(IP0_20, A9), ++ PINMUX_IPSR_DATA(IP0_21, A10), ++ PINMUX_IPSR_DATA(IP0_22, A11), ++ PINMUX_IPSR_DATA(IP0_23, A12), ++ PINMUX_IPSR_DATA(IP0_24, A13), ++ PINMUX_IPSR_DATA(IP0_25, A14), ++ PINMUX_IPSR_DATA(IP0_26, A15), ++ PINMUX_IPSR_DATA(IP0_27, A16), ++ PINMUX_IPSR_DATA(IP0_28, A17), ++ PINMUX_IPSR_DATA(IP0_29, A18), ++ PINMUX_IPSR_DATA(IP0_30, A19), ++ ++ /* IPSR1 */ ++ PINMUX_IPSR_DATA(IP1_0, A20), ++ PINMUX_IPSR_MSEL(IP1_0, HSPI_CS1_B, SEL_HSPI1_B), ++ ++ PINMUX_IPSR_DATA(IP1_1, A21), ++ PINMUX_IPSR_MSEL(IP1_1, HSPI_CLK1_B, SEL_HSPI1_B), ++ ++ PINMUX_IPSR_DATA(IP1_4_2, A22), ++ PINMUX_IPSR_MSEL(IP1_4_2, HRTS0_B, SEL_HSCIF0_B), ++ PINMUX_IPSR_MSEL(IP1_4_2, RX2_B, SEL_SCIF2_B), ++ PINMUX_IPSR_MSEL(IP1_4_2, DREQ2_A, SEL_DREQ2_A), ++ ++ PINMUX_IPSR_DATA(IP1_7_5, A23), ++ PINMUX_IPSR_DATA(IP1_7_5, HTX0_B), ++ PINMUX_IPSR_DATA(IP1_7_5, TX2_B), ++ PINMUX_IPSR_DATA(IP1_7_5, DACK2_A), ++ PINMUX_IPSR_MSEL(IP1_7_5, TS_SDEN0_A, SEL_TSIF0_A), ++ ++ PINMUX_IPSR_MSEL(IP1_10_8, SD1_CD_A, SEL_SD1_A), ++ PINMUX_IPSR_DATA(IP1_10_8, MMC_D6), ++ PINMUX_IPSR_DATA(IP1_10_8, A24), ++ PINMUX_IPSR_MSEL(IP1_10_8, DREQ1_A, SEL_DREQ1_A), ++ PINMUX_IPSR_MSEL(IP1_10_8, HRX0_B, SEL_HSCIF0_B), ++ PINMUX_IPSR_MSEL(IP1_10_8, TS_SPSYNC0_A, SEL_TSIF0_A), ++ ++ PINMUX_IPSR_MSEL(IP1_14_11, SD1_WP_A, SEL_SD1_A), ++ PINMUX_IPSR_DATA(IP1_14_11, MMC_D7), ++ PINMUX_IPSR_DATA(IP1_14_11, A25), ++ PINMUX_IPSR_DATA(IP1_14_11, DACK1_A), ++ PINMUX_IPSR_MSEL(IP1_14_11, HCTS0_B, SEL_HSCIF0_B), ++ PINMUX_IPSR_MSEL(IP1_14_11, RX3_C, SEL_SCIF3_C), ++ PINMUX_IPSR_MSEL(IP1_14_11, TS_SDAT0_A, SEL_TSIF0_A), ++ ++ PINMUX_IPSR_NOGP(IP1_16_15, CLKOUT), ++ PINMUX_IPSR_NOGP(IP1_16_15, HSPI_TX1_B), ++ PINMUX_IPSR_NOGP(IP1_16_15, PWM0_B), ++ ++ PINMUX_IPSR_NOGP(IP1_17, CS0), ++ PINMUX_IPSR_NOGM(IP1_17, HSPI_RX1_B, SEL_HSPI1_B), ++ ++ PINMUX_IPSR_NOGM(IP1_20_18, SSI_SCK1_B, SEL_SSI1_B), ++ PINMUX_IPSR_NOGP(IP1_20_18, ATAG0_B), ++ PINMUX_IPSR_NOGP(IP1_20_18, CS1_A26), ++ PINMUX_IPSR_NOGM(IP1_20_18, SDA2_A, SEL_I2C2_A), ++ PINMUX_IPSR_NOGM(IP1_20_18, SCK2_B, SEL_SCIF2_B), ++ ++ PINMUX_IPSR_DATA(IP1_23_21, MMC_D5), ++ PINMUX_IPSR_DATA(IP1_23_21, ATADIR0_B), ++ PINMUX_IPSR_DATA(IP1_23_21, RD_WR), ++ ++ PINMUX_IPSR_DATA(IP1_24, WE1), ++ PINMUX_IPSR_DATA(IP1_24, ATAWR0_B), ++ ++ PINMUX_IPSR_MSEL(IP1_27_25, SSI_WS1_B, SEL_SSI1_B), ++ PINMUX_IPSR_DATA(IP1_27_25, EX_CS0), ++ PINMUX_IPSR_MSEL(IP1_27_25, SCL2_A, SEL_I2C2_A), ++ PINMUX_IPSR_DATA(IP1_27_25, TX3_C), ++ PINMUX_IPSR_MSEL(IP1_27_25, TS_SCK0_A, SEL_TSIF0_A), ++ ++ PINMUX_IPSR_DATA(IP1_29_28, EX_CS1), ++ PINMUX_IPSR_DATA(IP1_29_28, MMC_D4), ++ ++ /* IPSR2 */ ++ PINMUX_IPSR_DATA(IP2_2_0, SD1_CLK_A), ++ PINMUX_IPSR_DATA(IP2_2_0, MMC_CLK), ++ PINMUX_IPSR_DATA(IP2_2_0, ATACS00), ++ PINMUX_IPSR_DATA(IP2_2_0, EX_CS2), ++ ++ PINMUX_IPSR_MSEL(IP2_5_3, SD1_CMD_A, SEL_SD1_A), ++ PINMUX_IPSR_DATA(IP2_5_3, MMC_CMD), ++ PINMUX_IPSR_DATA(IP2_5_3, ATACS10), ++ PINMUX_IPSR_DATA(IP2_5_3, EX_CS3), ++ ++ PINMUX_IPSR_MSEL(IP2_8_6, SD1_DAT0_A, SEL_SD1_A), ++ PINMUX_IPSR_DATA(IP2_8_6, MMC_D0), ++ PINMUX_IPSR_DATA(IP2_8_6, ATARD0), ++ PINMUX_IPSR_DATA(IP2_8_6, EX_CS4), ++ PINMUX_IPSR_MSEL(IP2_8_6, EX_WAIT1_A, SEL_WAIT1_A), ++ ++ PINMUX_IPSR_MSEL(IP2_11_9, SD1_DAT1_A, SEL_SD1_A), ++ PINMUX_IPSR_DATA(IP2_11_9, MMC_D1), ++ PINMUX_IPSR_DATA(IP2_11_9, ATAWR0_A), ++ PINMUX_IPSR_DATA(IP2_11_9, EX_CS5), ++ PINMUX_IPSR_MSEL(IP2_11_9, EX_WAIT2_A, SEL_WAIT2_A), ++ ++ PINMUX_IPSR_MSEL(IP2_13_12, DREQ0_A, SEL_DREQ0_A), ++ PINMUX_IPSR_MSEL(IP2_13_12, RX3_A, SEL_SCIF3_A), ++ ++ PINMUX_IPSR_DATA(IP2_16_14, DACK0), ++ PINMUX_IPSR_DATA(IP2_16_14, TX3_A), ++ PINMUX_IPSR_DATA(IP2_16_14, DRACK0), ++ ++ PINMUX_IPSR_DATA(IP2_17, EX_WAIT0), ++ PINMUX_IPSR_DATA(IP2_17, PWM0_C), ++ ++ PINMUX_IPSR_NOGP(IP2_18, D0), ++ PINMUX_IPSR_NOGP(IP2_19, D1), ++ PINMUX_IPSR_NOGP(IP2_20, D2), ++ PINMUX_IPSR_NOGP(IP2_21, D3), ++ PINMUX_IPSR_NOGP(IP2_22, D4), ++ PINMUX_IPSR_NOGP(IP2_23, D5), ++ PINMUX_IPSR_NOGP(IP2_24, D6), ++ PINMUX_IPSR_NOGP(IP2_25, D7), ++ PINMUX_IPSR_NOGP(IP2_26, D8), ++ PINMUX_IPSR_NOGP(IP2_27, D9), ++ PINMUX_IPSR_NOGP(IP2_28, D10), ++ PINMUX_IPSR_NOGP(IP2_29, D11), ++ ++ PINMUX_IPSR_DATA(IP2_30, RD_WR_B), ++ PINMUX_IPSR_DATA(IP2_30, IRQ0), ++ ++ PINMUX_IPSR_DATA(IP2_31, MLB_CLK), ++ PINMUX_IPSR_MSEL(IP2_31, IRQ1_A, SEL_IRQ1_A), ++ ++ /* IPSR3 */ ++ PINMUX_IPSR_DATA(IP3_1_0, MLB_SIG), ++ PINMUX_IPSR_MSEL(IP3_1_0, RX5_B, SEL_SCIF5_B), ++ PINMUX_IPSR_MSEL(IP3_1_0, SDA3_A, SEL_I2C3_A), ++ PINMUX_IPSR_MSEL(IP3_1_0, IRQ2_A, SEL_IRQ2_A), ++ ++ PINMUX_IPSR_DATA(IP3_4_2, MLB_DAT), ++ PINMUX_IPSR_DATA(IP3_4_2, TX5_B), ++ PINMUX_IPSR_MSEL(IP3_4_2, SCL3_A, SEL_I2C3_A), ++ PINMUX_IPSR_MSEL(IP3_4_2, IRQ3_A, SEL_IRQ3_A), ++ PINMUX_IPSR_DATA(IP3_4_2, SDSELF_B), ++ ++ PINMUX_IPSR_MSEL(IP3_7_5, SD1_CMD_B, SEL_SD1_B), ++ PINMUX_IPSR_DATA(IP3_7_5, SCIF_CLK), ++ PINMUX_IPSR_DATA(IP3_7_5, AUDIO_CLKOUT_B), ++ PINMUX_IPSR_MSEL(IP3_7_5, CAN_CLK_B, SEL_CANCLK_B), ++ PINMUX_IPSR_MSEL(IP3_7_5, SDA3_B, SEL_I2C3_B), ++ ++ PINMUX_IPSR_DATA(IP3_9_8, SD1_CLK_B), ++ PINMUX_IPSR_DATA(IP3_9_8, HTX0_A), ++ PINMUX_IPSR_DATA(IP3_9_8, TX0_A), ++ ++ PINMUX_IPSR_MSEL(IP3_12_10, SD1_DAT0_B, SEL_SD1_B), ++ PINMUX_IPSR_MSEL(IP3_12_10, HRX0_A, SEL_HSCIF0_A), ++ PINMUX_IPSR_MSEL(IP3_12_10, RX0_A, SEL_SCIF0_A), ++ ++ PINMUX_IPSR_MSEL(IP3_15_13, SD1_DAT1_B, SEL_SD1_B), ++ PINMUX_IPSR_MSEL(IP3_15_13, HSCK0, SEL_HSCIF0_A), ++ PINMUX_IPSR_DATA(IP3_15_13, SCK0), ++ PINMUX_IPSR_MSEL(IP3_15_13, SCL3_B, SEL_I2C3_B), ++ ++ PINMUX_IPSR_MSEL(IP3_18_16, SD1_DAT2_B, SEL_SD1_B), ++ PINMUX_IPSR_MSEL(IP3_18_16, HCTS0_A, SEL_HSCIF0_A), ++ PINMUX_IPSR_DATA(IP3_18_16, CTS0), ++ ++ PINMUX_IPSR_MSEL(IP3_20_19, SD1_DAT3_B, SEL_SD1_B), ++ PINMUX_IPSR_MSEL(IP3_20_19, HRTS0_A, SEL_HSCIF0_A), ++ PINMUX_IPSR_DATA(IP3_20_19, RTS0), ++ ++ PINMUX_IPSR_DATA(IP3_23_21, SSI_SCK4), ++ PINMUX_IPSR_DATA(IP3_23_21, DU0_DR0), ++ PINMUX_IPSR_DATA(IP3_23_21, LCDOUT0), ++ PINMUX_IPSR_DATA(IP3_23_21, AUDATA2), ++ PINMUX_IPSR_DATA(IP3_23_21, ARM_TRACEDATA_2), ++ PINMUX_IPSR_MSEL(IP3_23_21, SDA3_C, SEL_I2C3_C), ++ PINMUX_IPSR_DATA(IP3_23_21, ADICHS1), ++ PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN0_B, SEL_TSIF0_B), ++ ++ PINMUX_IPSR_DATA(IP3_26_24, SSI_WS4), ++ PINMUX_IPSR_DATA(IP3_26_24, DU0_DR1), ++ PINMUX_IPSR_DATA(IP3_26_24, LCDOUT1), ++ PINMUX_IPSR_DATA(IP3_26_24, AUDATA3), ++ PINMUX_IPSR_DATA(IP3_26_24, ARM_TRACEDATA_3), ++ PINMUX_IPSR_MSEL(IP3_26_24, SCL3_C, SEL_I2C3_C), ++ PINMUX_IPSR_DATA(IP3_26_24, ADICHS2), ++ PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC0_B, SEL_TSIF0_B), ++ ++ PINMUX_IPSR_DATA(IP3_27, DU0_DR2), ++ PINMUX_IPSR_DATA(IP3_27, LCDOUT2), ++ ++ PINMUX_IPSR_DATA(IP3_28, DU0_DR3), ++ PINMUX_IPSR_DATA(IP3_28, LCDOUT3), ++ ++ PINMUX_IPSR_DATA(IP3_29, DU0_DR4), ++ PINMUX_IPSR_DATA(IP3_29, LCDOUT4), ++ ++ PINMUX_IPSR_DATA(IP3_30, DU0_DR5), ++ PINMUX_IPSR_DATA(IP3_30, LCDOUT5), ++ ++ PINMUX_IPSR_DATA(IP3_31, DU0_DR6), ++ PINMUX_IPSR_DATA(IP3_31, LCDOUT6), ++ ++ /* IPSR4 */ ++ PINMUX_IPSR_DATA(IP4_0, DU0_DR7), ++ PINMUX_IPSR_DATA(IP4_0, LCDOUT7), ++ ++ PINMUX_IPSR_DATA(IP4_3_1, DU0_DG0), ++ PINMUX_IPSR_DATA(IP4_3_1, LCDOUT8), ++ PINMUX_IPSR_DATA(IP4_3_1, AUDATA4), ++ PINMUX_IPSR_DATA(IP4_3_1, ARM_TRACEDATA_4), ++ PINMUX_IPSR_DATA(IP4_3_1, TX1_D), ++ PINMUX_IPSR_DATA(IP4_3_1, CAN0_TX_A), ++ PINMUX_IPSR_DATA(IP4_3_1, ADICHS0), ++ ++ PINMUX_IPSR_DATA(IP4_6_4, DU0_DG1), ++ PINMUX_IPSR_DATA(IP4_6_4, LCDOUT9), ++ PINMUX_IPSR_DATA(IP4_6_4, AUDATA5), ++ PINMUX_IPSR_DATA(IP4_6_4, ARM_TRACEDATA_5), ++ PINMUX_IPSR_MSEL(IP4_6_4, RX1_D, SEL_SCIF1_D), ++ PINMUX_IPSR_MSEL(IP4_6_4, CAN0_RX_A, SEL_CAN0_A), ++ PINMUX_IPSR_DATA(IP4_6_4, ADIDATA), ++ ++ PINMUX_IPSR_DATA(IP4_7, DU0_DG2), ++ PINMUX_IPSR_DATA(IP4_7, LCDOUT10), ++ ++ PINMUX_IPSR_DATA(IP4_8, DU0_DG3), ++ PINMUX_IPSR_DATA(IP4_8, LCDOUT11), ++ ++ PINMUX_IPSR_DATA(IP4_10_9, DU0_DG4), ++ PINMUX_IPSR_DATA(IP4_10_9, LCDOUT12), ++ PINMUX_IPSR_MSEL(IP4_10_9, RX0_B, SEL_SCIF0_B), ++ ++ PINMUX_IPSR_DATA(IP4_12_11, DU0_DG5), ++ PINMUX_IPSR_DATA(IP4_12_11, LCDOUT13), ++ PINMUX_IPSR_DATA(IP4_12_11, TX0_B), ++ ++ PINMUX_IPSR_DATA(IP4_14_13, DU0_DG6), ++ PINMUX_IPSR_DATA(IP4_14_13, LCDOUT14), ++ PINMUX_IPSR_MSEL(IP4_14_13, RX4_A, SEL_SCIF4_A), ++ ++ PINMUX_IPSR_DATA(IP4_16_15, DU0_DG7), ++ PINMUX_IPSR_DATA(IP4_16_15, LCDOUT15), ++ PINMUX_IPSR_DATA(IP4_16_15, TX4_A), ++ ++ PINMUX_IPSR_MSEL(IP4_20_17, SSI_SCK2_B, SEL_SSI2_B), ++ PINMUX_DATA(VI0_R0_B_MARK, FN_IP4_20_17, FN_VI0_R0_B, FN_SEL_VI0_B), /* see sel_vi0 */ ++ PINMUX_DATA(VI0_R0_D_MARK, FN_IP4_20_17, FN_VI0_R0_B, FN_SEL_VI0_D), /* see sel_vi0 */ ++ PINMUX_IPSR_DATA(IP4_20_17, DU0_DB0), ++ PINMUX_IPSR_DATA(IP4_20_17, LCDOUT16), ++ PINMUX_IPSR_DATA(IP4_20_17, AUDATA6), ++ PINMUX_IPSR_DATA(IP4_20_17, ARM_TRACEDATA_6), ++ PINMUX_IPSR_MSEL(IP4_20_17, GPSCLK_A, SEL_GPS_A), ++ PINMUX_IPSR_DATA(IP4_20_17, PWM0_A), ++ PINMUX_IPSR_DATA(IP4_20_17, ADICLK), ++ PINMUX_IPSR_MSEL(IP4_20_17, TS_SDAT0_B, SEL_TSIF0_B), ++ ++ PINMUX_IPSR_DATA(IP4_24_21, AUDIO_CLKC), ++ PINMUX_DATA(VI0_R1_B_MARK, FN_IP4_24_21, FN_VI0_R1_B, FN_SEL_VI0_B), /* see sel_vi0 */ ++ PINMUX_DATA(VI0_R1_D_MARK, FN_IP4_24_21, FN_VI0_R1_B, FN_SEL_VI0_D), /* see sel_vi0 */ ++ PINMUX_IPSR_DATA(IP4_24_21, DU0_DB1), ++ PINMUX_IPSR_DATA(IP4_24_21, LCDOUT17), ++ PINMUX_IPSR_DATA(IP4_24_21, AUDATA7), ++ PINMUX_IPSR_DATA(IP4_24_21, ARM_TRACEDATA_7), ++ PINMUX_IPSR_MSEL(IP4_24_21, GPSIN_A, SEL_GPS_A), ++ PINMUX_IPSR_DATA(IP4_24_21, ADICS_SAMP), ++ PINMUX_IPSR_MSEL(IP4_24_21, TS_SCK0_B, SEL_TSIF0_B), ++ ++ PINMUX_DATA(VI0_R2_B_MARK, FN_IP4_26_25, FN_VI0_R2_B, FN_SEL_VI0_B), /* see sel_vi0 */ ++ PINMUX_DATA(VI0_R2_D_MARK, FN_IP4_26_25, FN_VI0_R2_B, FN_SEL_VI0_D), /* see sel_vi0 */ ++ PINMUX_IPSR_DATA(IP4_26_25, DU0_DB2), ++ PINMUX_IPSR_DATA(IP4_26_25, LCDOUT18), ++ ++ PINMUX_IPSR_MSEL(IP4_28_27, VI0_R3_B, SEL_VI0_B), ++ PINMUX_IPSR_DATA(IP4_28_27, DU0_DB3), ++ PINMUX_IPSR_DATA(IP4_28_27, LCDOUT19), ++ ++ PINMUX_DATA(VI0_R4_B_MARK, FN_IP4_30_29, FN_VI0_R4_B, FN_SEL_VI0_B), /* see sel_vi0 */ ++ PINMUX_DATA(VI0_R4_D_MARK, FN_IP4_30_29, FN_VI0_R4_B, FN_SEL_VI0_D), /* see sel_vi0 */ ++ PINMUX_IPSR_DATA(IP4_30_29, DU0_DB4), ++ PINMUX_IPSR_DATA(IP4_30_29, LCDOUT20), ++ ++ /* IPSR5 */ ++ PINMUX_DATA(VI0_R5_B_MARK, FN_IP5_1_0, FN_VI0_R5_B, FN_SEL_VI0_B), /* see sel_vi0 */ ++ PINMUX_DATA(VI0_R5_D_MARK, FN_IP5_1_0, FN_VI0_R5_B, FN_SEL_VI0_D), /* see sel_vi0 */ ++ PINMUX_IPSR_DATA(IP5_1_0, DU0_DB5), ++ PINMUX_IPSR_DATA(IP5_1_0, LCDOUT21), ++ ++ PINMUX_IPSR_MSEL(IP5_3_2, VI1_DATA10_B, SEL_VI1_B), ++ PINMUX_IPSR_DATA(IP5_3_2, DU0_DB6), ++ PINMUX_IPSR_DATA(IP5_3_2, LCDOUT22), ++ ++ PINMUX_IPSR_MSEL(IP5_5_4, VI1_DATA11_B, SEL_VI1_B), ++ PINMUX_IPSR_DATA(IP5_5_4, DU0_DB7), ++ PINMUX_IPSR_DATA(IP5_5_4, LCDOUT23), ++ ++ PINMUX_IPSR_DATA(IP5_6, DU0_DOTCLKIN), ++ PINMUX_IPSR_DATA(IP5_6, QSTVA_QVS), ++ ++ PINMUX_IPSR_DATA(IP5_7, DU0_DOTCLKO_UT0), ++ PINMUX_IPSR_DATA(IP5_7, QCLK), ++ ++ PINMUX_IPSR_DATA(IP5_9_8, DU0_DOTCLKO_UT1), ++ PINMUX_IPSR_DATA(IP5_9_8, QSTVB_QVE), ++ PINMUX_IPSR_DATA(IP5_9_8, AUDIO_CLKOUT_A), ++ PINMUX_IPSR_MSEL(IP5_9_8, REMOCON_C, SEL_REMOCON_C), ++ ++ PINMUX_IPSR_MSEL(IP5_11_10, SSI_WS2_B, SEL_SSI2_B), ++ PINMUX_IPSR_DATA(IP5_11_10, DU0_EXHSYNC_DU0_HSYNC), ++ PINMUX_IPSR_DATA(IP5_11_10, QSTH_QHS), ++ ++ PINMUX_IPSR_DATA(IP5_12, DU0_EXVSYNC_DU0_VSYNC), ++ PINMUX_IPSR_DATA(IP5_12, QSTB_QHE), ++ ++ PINMUX_IPSR_DATA(IP5_14_13, DU0_EXODDF_DU0_ODDF_DISP_CDE), ++ PINMUX_IPSR_DATA(IP5_14_13, QCPV_QDE), ++ PINMUX_IPSR_MSEL(IP5_14_13, FMCLK_D, SEL_FM_D), ++ ++ PINMUX_IPSR_MSEL(IP5_17_15, SSI_SCK1_A, SEL_SSI1_A), ++ PINMUX_IPSR_DATA(IP5_17_15, DU0_DISP), ++ PINMUX_IPSR_DATA(IP5_17_15, QPOLA), ++ PINMUX_IPSR_DATA(IP5_17_15, AUDCK), ++ PINMUX_IPSR_DATA(IP5_17_15, ARM_TRACECLK), ++ PINMUX_IPSR_DATA(IP5_17_15, BPFCLK_D), ++ ++ PINMUX_IPSR_MSEL(IP5_20_18, SSI_WS1_A, SEL_SSI1_A), ++ PINMUX_IPSR_DATA(IP5_20_18, DU0_CDE), ++ PINMUX_IPSR_DATA(IP5_20_18, QPOLB), ++ PINMUX_IPSR_DATA(IP5_20_18, AUDSYNC), ++ PINMUX_IPSR_DATA(IP5_20_18, ARM_TRACECTL), ++ PINMUX_IPSR_MSEL(IP5_20_18, FMIN_D, SEL_FM_D), ++ ++ PINMUX_IPSR_MSEL(IP5_22_21, SD1_CD_B, SEL_SD1_B), ++ PINMUX_IPSR_DATA(IP5_22_21, SSI_SCK78), ++ PINMUX_IPSR_MSEL(IP5_22_21, HSPI_RX0_B, SEL_HSPI0_B), ++ PINMUX_IPSR_DATA(IP5_22_21, TX1_B), ++ ++ PINMUX_IPSR_MSEL(IP5_25_23, SD1_WP_B, SEL_SD1_B), ++ PINMUX_IPSR_DATA(IP5_25_23, SSI_WS78), ++ PINMUX_IPSR_MSEL(IP5_25_23, HSPI_CLK0_B, SEL_HSPI0_B), ++ PINMUX_IPSR_MSEL(IP5_25_23, RX1_B, SEL_SCIF1_B), ++ PINMUX_IPSR_MSEL(IP5_25_23, CAN_CLK_D, SEL_CANCLK_D), ++ ++ PINMUX_IPSR_DATA(IP5_28_26, SSI_SDATA8), ++ PINMUX_IPSR_MSEL(IP5_28_26, SSI_SCK2_A, SEL_SSI2_A), ++ PINMUX_IPSR_MSEL(IP5_28_26, HSPI_CS0_B, SEL_HSPI0_B), ++ PINMUX_IPSR_DATA(IP5_28_26, TX2_A), ++ PINMUX_IPSR_DATA(IP5_28_26, CAN0_TX_B), ++ ++ PINMUX_IPSR_DATA(IP5_30_29, SSI_SDATA7), ++ PINMUX_IPSR_DATA(IP5_30_29, HSPI_TX0_B), ++ PINMUX_IPSR_MSEL(IP5_30_29, RX2_A, SEL_SCIF2_A), ++ PINMUX_IPSR_MSEL(IP5_30_29, CAN0_RX_B, SEL_CAN0_B), ++ ++ /* IPSR6 */ ++ PINMUX_IPSR_DATA(IP6_1_0, SSI_SCK6), ++ PINMUX_IPSR_MSEL(IP6_1_0, HSPI_RX2_A, SEL_HSPI2_A), ++ PINMUX_IPSR_MSEL(IP6_1_0, FMCLK_B, SEL_FM_B), ++ PINMUX_IPSR_DATA(IP6_1_0, CAN1_TX_B), ++ ++ PINMUX_IPSR_DATA(IP6_4_2, SSI_WS6), ++ PINMUX_IPSR_MSEL(IP6_4_2, HSPI_CLK2_A, SEL_HSPI2_A), ++ PINMUX_IPSR_DATA(IP6_4_2, BPFCLK_B), ++ PINMUX_IPSR_MSEL(IP6_4_2, CAN1_RX_B, SEL_CAN1_B), ++ ++ PINMUX_IPSR_DATA(IP6_6_5, SSI_SDATA6), ++ PINMUX_IPSR_DATA(IP6_6_5, HSPI_TX2_A), ++ PINMUX_IPSR_MSEL(IP6_6_5, FMIN_B, SEL_FM_B), ++ ++ PINMUX_IPSR_DATA(IP6_7, SSI_SCK5), ++ PINMUX_IPSR_MSEL(IP6_7, RX4_C, SEL_SCIF4_C), ++ ++ PINMUX_IPSR_DATA(IP6_8, SSI_WS5), ++ PINMUX_IPSR_DATA(IP6_8, TX4_C), ++ ++ PINMUX_IPSR_DATA(IP6_9, SSI_SDATA5), ++ PINMUX_IPSR_MSEL(IP6_9, RX0_D, SEL_SCIF0_D), ++ ++ PINMUX_IPSR_DATA(IP6_10, SSI_WS34), ++ PINMUX_IPSR_DATA(IP6_10, ARM_TRACEDATA_8), ++ ++ PINMUX_IPSR_DATA(IP6_12_11, SSI_SDATA4), ++ PINMUX_IPSR_MSEL(IP6_12_11, SSI_WS2_A, SEL_SSI2_A), ++ PINMUX_IPSR_DATA(IP6_12_11, ARM_TRACEDATA_9), ++ ++ PINMUX_IPSR_DATA(IP6_13, SSI_SDATA3), ++ PINMUX_IPSR_DATA(IP6_13, ARM_TRACEDATA_10), ++ ++ PINMUX_IPSR_DATA(IP6_15_14, SSI_SCK012), ++ PINMUX_IPSR_DATA(IP6_15_14, ARM_TRACEDATA_11), ++ PINMUX_IPSR_DATA(IP6_15_14, TX0_D), ++ ++ PINMUX_IPSR_DATA(IP6_16, SSI_WS012), ++ PINMUX_IPSR_DATA(IP6_16, ARM_TRACEDATA_12), ++ ++ PINMUX_IPSR_DATA(IP6_18_17, SSI_SDATA2), ++ PINMUX_IPSR_MSEL(IP6_18_17, HSPI_CS2_A, SEL_HSPI2_A), ++ PINMUX_IPSR_DATA(IP6_18_17, ARM_TRACEDATA_13), ++ PINMUX_IPSR_MSEL(IP6_18_17, SDA1_A, SEL_I2C1_A), ++ ++ PINMUX_IPSR_DATA(IP6_20_19, SSI_SDATA1), ++ PINMUX_IPSR_DATA(IP6_20_19, ARM_TRACEDATA_14), ++ PINMUX_IPSR_MSEL(IP6_20_19, SCL1_A, SEL_I2C1_A), ++ PINMUX_IPSR_MSEL(IP6_20_19, SCK2_A, SEL_SCIF2_A), ++ ++ PINMUX_IPSR_DATA(IP6_21, SSI_SDATA0), ++ PINMUX_IPSR_DATA(IP6_21, ARM_TRACEDATA_15), ++ ++ PINMUX_IPSR_DATA(IP6_23_22, SD0_CLK), ++ PINMUX_IPSR_DATA(IP6_23_22, SUB_TDO), ++ ++ PINMUX_IPSR_DATA(IP6_25_24, SD0_CMD), ++ PINMUX_IPSR_DATA(IP6_25_24, SUB_TRST), ++ ++ PINMUX_IPSR_DATA(IP6_27_26, SD0_DAT0), ++ PINMUX_IPSR_DATA(IP6_27_26, SUB_TMS), ++ ++ PINMUX_IPSR_DATA(IP6_29_28, SD0_DAT1), ++ PINMUX_IPSR_DATA(IP6_29_28, SUB_TCK), ++ ++ PINMUX_IPSR_DATA(IP6_31_30, SD0_DAT2), ++ PINMUX_IPSR_DATA(IP6_31_30, SUB_TDI), ++ ++ /* IPSR7 */ ++ PINMUX_IPSR_DATA(IP7_1_0, SD0_DAT3), ++ PINMUX_IPSR_MSEL(IP7_1_0, IRQ1_B, SEL_IRQ1_B), ++ ++ PINMUX_IPSR_DATA(IP7_3_2, SD0_CD), ++ PINMUX_IPSR_DATA(IP7_3_2, TX5_A), ++ ++ PINMUX_IPSR_DATA(IP7_5_4, SD0_WP), ++ PINMUX_IPSR_MSEL(IP7_5_4, RX5_A, SEL_SCIF5_A), ++ ++ PINMUX_IPSR_DATA(IP7_8_6, VI1_CLKENB), ++ PINMUX_IPSR_MSEL(IP7_8_6, HSPI_CLK0_A, SEL_HSPI0_A), ++ PINMUX_IPSR_DATA(IP7_8_6, HTX1_A), ++ PINMUX_IPSR_MSEL(IP7_8_6, RTS1_C, SEL_SCIF1_C), ++ ++ PINMUX_IPSR_DATA(IP7_11_9, VI1_FIELD), ++ PINMUX_IPSR_MSEL(IP7_11_9, HSPI_CS0_A, SEL_HSPI0_A), ++ PINMUX_IPSR_MSEL(IP7_11_9, HRX1_A, SEL_HSCIF1_A), ++ PINMUX_IPSR_MSEL(IP7_11_9, SCK1_C, SEL_SCIF1_C), ++ ++ PINMUX_IPSR_DATA(IP7_14_12, VI1_HSYNC), ++ PINMUX_IPSR_MSEL(IP7_14_12, HSPI_RX0_A, SEL_HSPI0_A), ++ PINMUX_IPSR_MSEL(IP7_14_12, HRTS1_A, SEL_HSCIF1_A), ++ PINMUX_IPSR_MSEL(IP7_14_12, FMCLK_A, SEL_FM_A), ++ PINMUX_IPSR_MSEL(IP7_14_12, RX1_C, SEL_SCIF1_C), ++ ++ PINMUX_IPSR_DATA(IP7_17_15, VI1_VSYNC), ++ PINMUX_IPSR_DATA(IP7_17_15, HSPI_TX0), ++ PINMUX_IPSR_MSEL(IP7_17_15, HCTS1_A, SEL_HSCIF1_A), ++ PINMUX_IPSR_DATA(IP7_17_15, BPFCLK_A), ++ PINMUX_IPSR_DATA(IP7_17_15, TX1_C), ++ ++ PINMUX_IPSR_DATA(IP7_20_18, TCLK0), ++ PINMUX_IPSR_MSEL(IP7_20_18, HSCK1_A, SEL_HSCIF1_A), ++ PINMUX_IPSR_MSEL(IP7_20_18, FMIN_A, SEL_FM_A), ++ PINMUX_IPSR_MSEL(IP7_20_18, IRQ2_C, SEL_IRQ2_C), ++ PINMUX_IPSR_MSEL(IP7_20_18, CTS1_C, SEL_SCIF1_C), ++ PINMUX_IPSR_DATA(IP7_20_18, SPEEDIN), ++ ++ PINMUX_IPSR_DATA(IP7_21, VI0_CLK), ++ PINMUX_IPSR_MSEL(IP7_21, CAN_CLK_A, SEL_CANCLK_A), ++ ++ PINMUX_IPSR_DATA(IP7_24_22, VI0_CLKENB), ++ PINMUX_IPSR_MSEL(IP7_24_22, SD2_DAT2_B, SEL_SD2_B), ++ PINMUX_IPSR_DATA(IP7_24_22, VI1_DATA0), ++ PINMUX_IPSR_DATA(IP7_24_22, DU1_DG6), ++ PINMUX_IPSR_MSEL(IP7_24_22, HSPI_RX1_A, SEL_HSPI1_A), ++ PINMUX_IPSR_MSEL(IP7_24_22, RX4_B, SEL_SCIF4_B), ++ ++ PINMUX_IPSR_DATA(IP7_28_25, VI0_FIELD), ++ PINMUX_IPSR_MSEL(IP7_28_25, SD2_DAT3_B, SEL_SD2_B), ++ PINMUX_DATA(VI0_R3_C_MARK, FN_IP7_28_25, FN_VI0_R3_C, FN_SEL_VI0_C), /* see sel_vi0 */ ++ PINMUX_DATA(VI0_R3_D_MARK, FN_IP7_28_25, FN_VI0_R3_C, FN_SEL_VI0_D), /* see sel_vi0 */ ++ PINMUX_IPSR_DATA(IP7_28_25, VI1_DATA1), ++ PINMUX_IPSR_DATA(IP7_28_25, DU1_DG7), ++ PINMUX_IPSR_MSEL(IP7_28_25, HSPI_CLK1_A, SEL_HSPI1_A), ++ PINMUX_IPSR_DATA(IP7_28_25, TX4_B), ++ ++ PINMUX_IPSR_DATA(IP7_31_29, VI0_HSYNC), ++ PINMUX_IPSR_MSEL(IP7_31_29, SD2_CD_B, SEL_SD2_B), ++ PINMUX_IPSR_DATA(IP7_31_29, VI1_DATA2), ++ PINMUX_IPSR_DATA(IP7_31_29, DU1_DR2), ++ PINMUX_IPSR_MSEL(IP7_31_29, HSPI_CS1_A, SEL_HSPI1_A), ++ PINMUX_IPSR_MSEL(IP7_31_29, RX3_B, SEL_SCIF3_B), ++ ++ /* IPSR8 */ ++ PINMUX_IPSR_DATA(IP8_2_0, VI0_VSYNC), ++ PINMUX_IPSR_MSEL(IP8_2_0, SD2_WP_B, SEL_SD2_B), ++ PINMUX_IPSR_DATA(IP8_2_0, VI1_DATA3), ++ PINMUX_IPSR_DATA(IP8_2_0, DU1_DR3), ++ PINMUX_IPSR_DATA(IP8_2_0, HSPI_TX1_A), ++ PINMUX_IPSR_DATA(IP8_2_0, TX3_B), ++ ++ PINMUX_IPSR_DATA(IP8_5_3, VI0_DATA0_VI0_B0), ++ PINMUX_IPSR_DATA(IP8_5_3, DU1_DG2), ++ PINMUX_IPSR_MSEL(IP8_5_3, IRQ2_B, SEL_IRQ2_B), ++ PINMUX_IPSR_MSEL(IP8_5_3, RX3_D, SEL_SCIF3_D), ++ ++ PINMUX_IPSR_DATA(IP8_8_6, VI0_DATA1_VI0_B1), ++ PINMUX_IPSR_DATA(IP8_8_6, DU1_DG3), ++ PINMUX_IPSR_MSEL(IP8_8_6, IRQ3_B, SEL_IRQ3_B), ++ PINMUX_IPSR_DATA(IP8_8_6, TX3_D), ++ ++ PINMUX_IPSR_DATA(IP8_10_9, VI0_DATA2_VI0_B2), ++ PINMUX_IPSR_DATA(IP8_10_9, DU1_DG4), ++ PINMUX_IPSR_MSEL(IP8_10_9, RX0_C, SEL_SCIF0_C), ++ ++ PINMUX_IPSR_DATA(IP8_13_11, VI0_DATA3_VI0_B3), ++ PINMUX_IPSR_DATA(IP8_13_11, DU1_DG5), ++ PINMUX_IPSR_DATA(IP8_13_11, TX1_A), ++ PINMUX_IPSR_DATA(IP8_13_11, TX0_C), ++ ++ PINMUX_IPSR_DATA(IP8_15_14, VI0_DATA4_VI0_B4), ++ PINMUX_IPSR_DATA(IP8_15_14, DU1_DB2), ++ PINMUX_IPSR_MSEL(IP8_15_14, RX1_A, SEL_SCIF1_A), ++ ++ PINMUX_IPSR_DATA(IP8_18_16, VI0_DATA5_VI0_B5), ++ PINMUX_IPSR_DATA(IP8_18_16, DU1_DB3), ++ PINMUX_IPSR_MSEL(IP8_18_16, SCK1_A, SEL_SCIF1_A), ++ PINMUX_IPSR_DATA(IP8_18_16, PWM4), ++ PINMUX_IPSR_MSEL(IP8_18_16, HSCK1_B, SEL_HSCIF1_B), ++ ++ PINMUX_IPSR_DATA(IP8_21_19, VI0_DATA6_VI0_G0), ++ PINMUX_IPSR_DATA(IP8_21_19, DU1_DB4), ++ PINMUX_IPSR_MSEL(IP8_21_19, CTS1_A, SEL_SCIF1_A), ++ PINMUX_IPSR_DATA(IP8_21_19, PWM5), ++ ++ PINMUX_IPSR_DATA(IP8_23_22, VI0_DATA7_VI0_G1), ++ PINMUX_IPSR_DATA(IP8_23_22, DU1_DB5), ++ PINMUX_IPSR_MSEL(IP8_23_22, RTS1_A, SEL_SCIF1_A), ++ ++ PINMUX_IPSR_DATA(IP8_26_24, VI0_G2), ++ PINMUX_IPSR_DATA(IP8_26_24, SD2_CLK_B), ++ PINMUX_IPSR_DATA(IP8_26_24, VI1_DATA4), ++ PINMUX_IPSR_DATA(IP8_26_24, DU1_DR4), ++ PINMUX_IPSR_DATA(IP8_26_24, HTX1_B), ++ ++ PINMUX_IPSR_DATA(IP8_29_27, VI0_G3), ++ PINMUX_IPSR_MSEL(IP8_29_27, SD2_CMD_B, SEL_SD2_B), ++ PINMUX_IPSR_DATA(IP8_29_27, VI1_DATA5), ++ PINMUX_IPSR_DATA(IP8_29_27, DU1_DR5), ++ PINMUX_IPSR_MSEL(IP8_29_27, HRX1_B, SEL_HSCIF1_B), ++ ++ /* IPSR9 */ ++ PINMUX_IPSR_DATA(IP9_2_0, VI0_G4), ++ PINMUX_IPSR_MSEL(IP9_2_0, SD2_DAT0_B, SEL_SD2_B), ++ PINMUX_IPSR_DATA(IP9_2_0, VI1_DATA6), ++ PINMUX_IPSR_DATA(IP9_2_0, DU1_DR6), ++ PINMUX_IPSR_MSEL(IP9_2_0, HRTS1_B, SEL_HSCIF1_B), ++ ++ PINMUX_IPSR_DATA(IP9_5_3, VI0_G5), ++ PINMUX_IPSR_MSEL(IP9_5_3, SD2_DAT1_B, SEL_SD2_B), ++ PINMUX_IPSR_DATA(IP9_5_3, VI1_DATA7), ++ PINMUX_IPSR_DATA(IP9_5_3, DU1_DR7), ++ PINMUX_IPSR_MSEL(IP9_5_3, HCTS1_B, SEL_HSCIF1_B), ++ ++ PINMUX_DATA(VI0_R0_A_MARK, FN_IP9_8_6, FN_VI0_R0_A, FN_SEL_VI0_A), /* see sel_vi0 */ ++ PINMUX_DATA(VI0_R0_C_MARK, FN_IP9_8_6, FN_VI0_R0_A, FN_SEL_VI0_C), /* see sel_vi0 */ ++ PINMUX_IPSR_DATA(IP9_8_6, VI1_CLK), ++ PINMUX_IPSR_DATA(IP9_8_6, ETH_REF_CLK), ++ PINMUX_IPSR_DATA(IP9_8_6, DU1_DOTCLKIN), ++ ++ PINMUX_DATA(VI0_R1_A_MARK, FN_IP9_11_9, FN_VI0_R1_A, FN_SEL_VI0_A), /* see sel_vi0 */ ++ PINMUX_DATA(VI0_R1_C_MARK, FN_IP9_11_9, FN_VI0_R1_A, FN_SEL_VI0_C), /* see sel_vi0 */ ++ PINMUX_IPSR_DATA(IP9_11_9, VI1_DATA8), ++ PINMUX_IPSR_DATA(IP9_11_9, DU1_DB6), ++ PINMUX_IPSR_DATA(IP9_11_9, ETH_TXD0), ++ PINMUX_IPSR_DATA(IP9_11_9, PWM2), ++ PINMUX_IPSR_DATA(IP9_11_9, TCLK1), ++ ++ PINMUX_DATA(VI0_R2_A_MARK, FN_IP9_14_12, FN_VI0_R2_A, FN_SEL_VI0_A), /* see sel_vi0 */ ++ PINMUX_DATA(VI0_R2_C_MARK, FN_IP9_14_12, FN_VI0_R2_A, FN_SEL_VI0_C), /* see sel_vi0 */ ++ PINMUX_IPSR_DATA(IP9_14_12, VI1_DATA9), ++ PINMUX_IPSR_DATA(IP9_14_12, DU1_DB7), ++ PINMUX_IPSR_DATA(IP9_14_12, ETH_TXD1), ++ PINMUX_IPSR_DATA(IP9_14_12, PWM3), ++ ++ PINMUX_IPSR_MSEL(IP9_17_15, VI0_R3_A, SEL_VI0_A), ++ PINMUX_IPSR_DATA(IP9_17_15, ETH_CRS_DV), ++ PINMUX_IPSR_DATA(IP9_17_15, IECLK), ++ PINMUX_IPSR_MSEL(IP9_17_15, SCK2_C, SEL_SCIF2_C), ++ ++ PINMUX_DATA(VI0_R4_A_MARK, FN_IP9_20_18, FN_VI0_R4_A, FN_SEL_VI0_A), /* see sel_vi0 */ ++ PINMUX_DATA(VI0_R3_C_MARK, FN_IP9_20_18, FN_VI0_R4_A, FN_SEL_VI0_C), /* see sel_vi0 */ ++ PINMUX_IPSR_DATA(IP9_20_18, ETH_TX_EN), ++ PINMUX_IPSR_DATA(IP9_20_18, IETX), ++ PINMUX_IPSR_DATA(IP9_20_18, TX2_C), ++ ++ PINMUX_DATA(VI0_R5_A_MARK, FN_IP9_23_21, FN_VI0_R5_A, FN_SEL_VI0_A), /* see sel_vi0 */ ++ PINMUX_DATA(VI0_R5_C_MARK, FN_IP9_23_21, FN_VI0_R5_A, FN_SEL_VI0_C), /* see sel_vi0 */ ++ PINMUX_IPSR_DATA(IP9_23_21, ETH_RX_ER), ++ PINMUX_IPSR_MSEL(IP9_23_21, FMCLK_C, SEL_FM_C), ++ PINMUX_IPSR_DATA(IP9_23_21, IERX), ++ PINMUX_IPSR_MSEL(IP9_23_21, RX2_C, SEL_SCIF2_C), ++ ++ PINMUX_IPSR_MSEL(IP9_26_24, VI1_DATA10_A, SEL_VI1_A), ++ PINMUX_IPSR_DATA(IP9_26_24, DU1_DOTCLKOUT), ++ PINMUX_IPSR_DATA(IP9_26_24, ETH_RXD0), ++ PINMUX_IPSR_DATA(IP9_26_24, BPFCLK_C), ++ PINMUX_IPSR_DATA(IP9_26_24, TX2_D), ++ PINMUX_IPSR_MSEL(IP9_26_24, SDA2_C, SEL_I2C2_C), ++ ++ PINMUX_IPSR_MSEL(IP9_29_27, VI1_DATA11_A, SEL_VI1_A), ++ PINMUX_IPSR_DATA(IP9_29_27, DU1_EXHSYNC_DU1_HSYNC), ++ PINMUX_IPSR_DATA(IP9_29_27, ETH_RXD1), ++ PINMUX_IPSR_MSEL(IP9_29_27, FMIN_C, SEL_FM_C), ++ PINMUX_IPSR_MSEL(IP9_29_27, RX2_D, SEL_SCIF2_D), ++ PINMUX_IPSR_MSEL(IP9_29_27, SCL2_C, SEL_I2C2_C), ++ ++ /* IPSR10 */ ++ PINMUX_IPSR_DATA(IP10_2_0, SD2_CLK_A), ++ PINMUX_IPSR_DATA(IP10_2_0, DU1_EXVSYNC_DU1_VSYNC), ++ PINMUX_IPSR_DATA(IP10_2_0, ATARD1), ++ PINMUX_IPSR_DATA(IP10_2_0, ETH_MDC), ++ PINMUX_IPSR_MSEL(IP10_2_0, SDA1_B, SEL_I2C1_B), ++ ++ PINMUX_IPSR_MSEL(IP10_5_3, SD2_CMD_A, SEL_SD2_A), ++ PINMUX_IPSR_DATA(IP10_5_3, DU1_EXODDF_DU1_ODDF_DISP_CDE), ++ PINMUX_IPSR_DATA(IP10_5_3, ATAWR1), ++ PINMUX_IPSR_DATA(IP10_5_3, ETH_MDIO), ++ PINMUX_IPSR_MSEL(IP10_5_3, SCL1_B, SEL_I2C1_B), ++ ++ PINMUX_IPSR_MSEL(IP10_8_6, SD2_DAT0_A, SEL_SD2_A), ++ PINMUX_IPSR_DATA(IP10_8_6, DU1_DISP), ++ PINMUX_IPSR_DATA(IP10_8_6, ATACS01), ++ PINMUX_IPSR_MSEL(IP10_8_6, DREQ1_B, SEL_DREQ1_B), ++ PINMUX_IPSR_DATA(IP10_8_6, ETH_LINK), ++ PINMUX_IPSR_MSEL(IP10_8_6, CAN1_RX_A, SEL_CAN1_A), ++ ++ PINMUX_IPSR_MSEL(IP10_12_9, SD2_DAT1_A, SEL_SD2_A), ++ PINMUX_IPSR_DATA(IP10_12_9, DU1_CDE), ++ PINMUX_IPSR_DATA(IP10_12_9, ATACS11), ++ PINMUX_IPSR_DATA(IP10_12_9, DACK1_B), ++ PINMUX_IPSR_DATA(IP10_12_9, ETH_MAGIC), ++ PINMUX_IPSR_DATA(IP10_12_9, CAN1_TX_A), ++ PINMUX_IPSR_DATA(IP10_12_9, PWM6), ++ ++ PINMUX_IPSR_MSEL(IP10_15_13, SD2_DAT2_A, SEL_SD2_A), ++ PINMUX_IPSR_DATA(IP10_15_13, VI1_DATA12), ++ PINMUX_IPSR_MSEL(IP10_15_13, DREQ2_B, SEL_DREQ2_B), ++ PINMUX_IPSR_DATA(IP10_15_13, ATADIR1), ++ PINMUX_IPSR_MSEL(IP10_15_13, HSPI_CLK2_B, SEL_HSPI2_B), ++ PINMUX_IPSR_MSEL(IP10_15_13, GPSCLK_B, SEL_GPS_B), ++ ++ PINMUX_IPSR_MSEL(IP10_18_16, SD2_DAT3_A, SEL_SD2_A), ++ PINMUX_IPSR_DATA(IP10_18_16, VI1_DATA13), ++ PINMUX_IPSR_DATA(IP10_18_16, DACK2_B), ++ PINMUX_IPSR_DATA(IP10_18_16, ATAG1), ++ PINMUX_IPSR_MSEL(IP10_18_16, HSPI_CS2_B, SEL_HSPI2_B), ++ PINMUX_IPSR_MSEL(IP10_18_16, GPSIN_B, SEL_GPS_B), ++ ++ PINMUX_IPSR_MSEL(IP10_21_19, SD2_CD_A, SEL_SD2_A), ++ PINMUX_IPSR_DATA(IP10_21_19, VI1_DATA14), ++ PINMUX_IPSR_MSEL(IP10_21_19, EX_WAIT1_B, SEL_WAIT1_B), ++ PINMUX_IPSR_MSEL(IP10_21_19, DREQ0_B, SEL_DREQ0_B), ++ PINMUX_IPSR_MSEL(IP10_21_19, HSPI_RX2_B, SEL_HSPI2_B), ++ PINMUX_IPSR_MSEL(IP10_21_19, REMOCON_A, SEL_REMOCON_A), ++ ++ PINMUX_IPSR_MSEL(IP10_24_22, SD2_WP_A, SEL_SD2_A), ++ PINMUX_IPSR_DATA(IP10_24_22, VI1_DATA15), ++ PINMUX_IPSR_MSEL(IP10_24_22, EX_WAIT2_B, SEL_WAIT2_B), ++ PINMUX_IPSR_DATA(IP10_24_22, DACK0_B), ++ PINMUX_IPSR_DATA(IP10_24_22, HSPI_TX2_B), ++ PINMUX_IPSR_MSEL(IP10_24_22, CAN_CLK_C, SEL_CANCLK_C), ++}; ++ ++static struct sh_pfc_pin pinmux_pins[] = { ++ PINMUX_GPIO_GP_ALL(), ++}; ++ ++/* Pin numbers for pins without a corresponding GPIO port number are computed ++ * from the row and column numbers with a 1000 offset to avoid collisions with ++ * GPIO port numbers. ++ */ ++#define PIN_NUMBER(row, col) (1000+((row)-1)*25+(col)-1) ++ ++/* - SCIF macro ------------------------------------------------------------- */ ++#define SCIF_PFC_PIN(name, args...) \ ++ static const unsigned int name ##_pins[] = { args } ++#define SCIF_PFC_DAT(name, tx, rx) \ ++ static const unsigned int name ##_mux[] = { tx##_MARK, rx##_MARK, } ++#define SCIF_PFC_CTR(name, cts, rts) \ ++ static const unsigned int name ##_mux[] = { cts##_MARK, rts##_MARK, } ++#define SCIF_PFC_CLK(name, sck) \ ++ static const unsigned int name ##_mux[] = { sck##_MARK, } ++ ++/* - HSCIF0 ----------------------------------------------------------------- */ ++SCIF_PFC_PIN(hscif0_data_a, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18)); ++SCIF_PFC_DAT(hscif0_data_a, HTX0_A, HRX0_A); ++SCIF_PFC_PIN(hscif0_data_b, RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 30)); ++SCIF_PFC_DAT(hscif0_data_b, HTX0_B, HRX0_B); ++SCIF_PFC_PIN(hscif0_ctrl_a, RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21)); ++SCIF_PFC_CTR(hscif0_ctrl_a, HCTS0_A, HRTS0_A); ++SCIF_PFC_PIN(hscif0_ctrl_b, RCAR_GP_PIN(0, 31), RCAR_GP_PIN(0, 28)); ++SCIF_PFC_CTR(hscif0_ctrl_b, HCTS0_B, HRTS0_B); ++SCIF_PFC_PIN(hscif0_clk, RCAR_GP_PIN(1, 19)); ++SCIF_PFC_CLK(hscif0_clk, HSCK0); ++ ++/* - HSCIF1 ----------------------------------------------------------------- */ ++SCIF_PFC_PIN(hscif1_data_a, RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20)); ++SCIF_PFC_DAT(hscif1_data_a, HTX1_A, HRX1_A); ++SCIF_PFC_PIN(hscif1_data_b, RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6)); ++SCIF_PFC_DAT(hscif1_data_b, HTX1_B, HRX1_B); ++SCIF_PFC_PIN(hscif1_ctrl_a, RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21)); ++SCIF_PFC_CTR(hscif1_ctrl_a, HCTS1_A, HRTS1_A); ++SCIF_PFC_PIN(hscif1_ctrl_b, RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7)); ++SCIF_PFC_CTR(hscif1_ctrl_b, HCTS1_B, HRTS1_B); ++SCIF_PFC_PIN(hscif1_clk_a, RCAR_GP_PIN(3, 23)); ++SCIF_PFC_CLK(hscif1_clk_a, HSCK1_A); ++SCIF_PFC_PIN(hscif1_clk_b, RCAR_GP_PIN(4, 2)); ++SCIF_PFC_CLK(hscif1_clk_b, HSCK1_B); ++ ++/* - SCIF CLOCK ------------------------------------------------------------- */ ++SCIF_PFC_PIN(scif_clk, RCAR_GP_PIN(1, 16)); ++SCIF_PFC_CLK(scif_clk, SCIF_CLK); ++ ++/* - SCIF0 ------------------------------------------------------------------ */ ++SCIF_PFC_PIN(scif0_data_a, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18)); ++SCIF_PFC_DAT(scif0_data_a, TX0_A, RX0_A); ++SCIF_PFC_PIN(scif0_data_b, RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2)); ++SCIF_PFC_DAT(scif0_data_b, TX0_B, RX0_B); ++SCIF_PFC_PIN(scif0_data_c, RCAR_GP_PIN(4, 0), RCAR_GP_PIN(3, 31)); ++SCIF_PFC_DAT(scif0_data_c, TX0_C, RX0_C); ++SCIF_PFC_PIN(scif0_data_d, RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 1)); ++SCIF_PFC_DAT(scif0_data_d, TX0_D, RX0_D); ++SCIF_PFC_PIN(scif0_ctrl, RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21)); ++SCIF_PFC_CTR(scif0_ctrl, CTS0, RTS0); ++SCIF_PFC_PIN(scif0_clk, RCAR_GP_PIN(1, 19)); ++SCIF_PFC_CLK(scif0_clk, SCK0); ++ ++/* - SCIF1 ------------------------------------------------------------------ */ ++SCIF_PFC_PIN(scif1_data_a, RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1)); ++SCIF_PFC_DAT(scif1_data_a, TX1_A, RX1_A); ++SCIF_PFC_PIN(scif1_data_b, RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25)); ++SCIF_PFC_DAT(scif1_data_b, TX1_B, RX1_B); ++SCIF_PFC_PIN(scif1_data_c, RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21)); ++SCIF_PFC_DAT(scif1_data_c, TX1_C, RX1_C); ++SCIF_PFC_PIN(scif1_data_d, RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31)); ++SCIF_PFC_DAT(scif1_data_d, TX1_D, RX1_D); ++SCIF_PFC_PIN(scif1_ctrl_a, RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4)); ++SCIF_PFC_CTR(scif1_ctrl_a, CTS1_A, RTS1_A); ++SCIF_PFC_PIN(scif1_ctrl_c, RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 19)); ++SCIF_PFC_CTR(scif1_ctrl_c, CTS1_C, RTS1_C); ++SCIF_PFC_PIN(scif1_clk_a, RCAR_GP_PIN(4, 2)); ++SCIF_PFC_CLK(scif1_clk_a, SCK1_A); ++SCIF_PFC_PIN(scif1_clk_c, RCAR_GP_PIN(3, 20)); ++SCIF_PFC_CLK(scif1_clk_c, SCK1_C); ++ ++/* - SCIF2 ------------------------------------------------------------------ */ ++SCIF_PFC_PIN(scif2_data_a, RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27)); ++SCIF_PFC_DAT(scif2_data_a, TX2_A, RX2_A); ++SCIF_PFC_PIN(scif2_data_b, RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 28)); ++SCIF_PFC_DAT(scif2_data_b, TX2_B, RX2_B); ++SCIF_PFC_PIN(scif2_data_c, RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14)); ++SCIF_PFC_DAT(scif2_data_c, TX2_C, RX2_C); ++SCIF_PFC_PIN(scif2_data_d, RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16)); ++SCIF_PFC_DAT(scif2_data_d, TX2_D, RX2_D); ++SCIF_PFC_PIN(scif2_data_e, RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4)); ++SCIF_PFC_DAT(scif2_data_e, TX2_E, RX2_E); ++SCIF_PFC_PIN(scif2_clk_a, RCAR_GP_PIN(3, 9)); ++SCIF_PFC_CLK(scif2_clk_a, SCK2_A); ++SCIF_PFC_PIN(scif2_clk_b, PIN_NUMBER(3, 20)); ++SCIF_PFC_CLK(scif2_clk_b, SCK2_B); ++SCIF_PFC_PIN(scif2_clk_c, RCAR_GP_PIN(4, 12)); ++SCIF_PFC_CLK(scif2_clk_c, SCK2_C); ++ ++/* - SCIF3 ------------------------------------------------------------------ */ ++SCIF_PFC_PIN(scif3_data_a, RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9)); ++SCIF_PFC_DAT(scif3_data_a, TX3_A, RX3_A); ++SCIF_PFC_PIN(scif3_data_b, RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27)); ++SCIF_PFC_DAT(scif3_data_b, TX3_B, RX3_B); ++SCIF_PFC_PIN(scif3_data_c, RCAR_GP_PIN(1, 3), RCAR_GP_PIN(0, 31)); ++SCIF_PFC_DAT(scif3_data_c, TX3_C, RX3_C); ++SCIF_PFC_PIN(scif3_data_d, RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 29)); ++SCIF_PFC_DAT(scif3_data_d, TX3_D, RX3_D); ++ ++/* - SCIF4 ------------------------------------------------------------------ */ ++SCIF_PFC_PIN(scif4_data_a, RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4)); ++SCIF_PFC_DAT(scif4_data_a, TX4_A, RX4_A); ++SCIF_PFC_PIN(scif4_data_b, RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 25)); ++SCIF_PFC_DAT(scif4_data_b, TX4_B, RX4_B); ++SCIF_PFC_PIN(scif4_data_c, RCAR_GP_PIN(3, 0), RCAR_GP_PIN(2, 31)); ++SCIF_PFC_DAT(scif4_data_c, TX4_C, RX4_C); ++ ++/* - SCIF5 ------------------------------------------------------------------ */ ++SCIF_PFC_PIN(scif5_data_a, RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18)); ++SCIF_PFC_DAT(scif5_data_a, TX5_A, RX5_A); ++SCIF_PFC_PIN(scif5_data_b, RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14)); ++SCIF_PFC_DAT(scif5_data_b, TX5_B, RX5_B); ++ ++static const struct sh_pfc_pin_group pinmux_groups[] = { ++ SH_PFC_PIN_GROUP(hscif0_data_a), ++ SH_PFC_PIN_GROUP(hscif0_data_b), ++ SH_PFC_PIN_GROUP(hscif0_ctrl_a), ++ SH_PFC_PIN_GROUP(hscif0_ctrl_b), ++ SH_PFC_PIN_GROUP(hscif0_clk), ++ SH_PFC_PIN_GROUP(hscif1_data_a), ++ SH_PFC_PIN_GROUP(hscif1_data_b), ++ SH_PFC_PIN_GROUP(hscif1_ctrl_a), ++ SH_PFC_PIN_GROUP(hscif1_ctrl_b), ++ SH_PFC_PIN_GROUP(hscif1_clk_a), ++ SH_PFC_PIN_GROUP(hscif1_clk_b), ++ SH_PFC_PIN_GROUP(scif_clk), ++ SH_PFC_PIN_GROUP(scif0_data_a), ++ SH_PFC_PIN_GROUP(scif0_data_b), ++ SH_PFC_PIN_GROUP(scif0_data_c), ++ SH_PFC_PIN_GROUP(scif0_data_d), ++ SH_PFC_PIN_GROUP(scif0_ctrl), ++ SH_PFC_PIN_GROUP(scif0_clk), ++ SH_PFC_PIN_GROUP(scif1_data_a), ++ SH_PFC_PIN_GROUP(scif1_data_b), ++ SH_PFC_PIN_GROUP(scif1_data_c), ++ SH_PFC_PIN_GROUP(scif1_data_d), ++ SH_PFC_PIN_GROUP(scif1_ctrl_a), ++ SH_PFC_PIN_GROUP(scif1_ctrl_c), ++ SH_PFC_PIN_GROUP(scif1_clk_a), ++ SH_PFC_PIN_GROUP(scif1_clk_c), ++ SH_PFC_PIN_GROUP(scif2_data_a), ++ SH_PFC_PIN_GROUP(scif2_data_b), ++ SH_PFC_PIN_GROUP(scif2_data_c), ++ SH_PFC_PIN_GROUP(scif2_data_d), ++ SH_PFC_PIN_GROUP(scif2_data_e), ++ SH_PFC_PIN_GROUP(scif2_clk_a), ++ SH_PFC_PIN_GROUP(scif2_clk_b), ++ SH_PFC_PIN_GROUP(scif2_clk_c), ++ SH_PFC_PIN_GROUP(scif3_data_a), ++ SH_PFC_PIN_GROUP(scif3_data_b), ++ SH_PFC_PIN_GROUP(scif3_data_c), ++ SH_PFC_PIN_GROUP(scif3_data_d), ++ SH_PFC_PIN_GROUP(scif4_data_a), ++ SH_PFC_PIN_GROUP(scif4_data_b), ++ SH_PFC_PIN_GROUP(scif4_data_c), ++ SH_PFC_PIN_GROUP(scif5_data_a), ++ SH_PFC_PIN_GROUP(scif5_data_b), ++}; ++ ++static const char * const hscif0_groups[] = { ++ "hscif0_data_a", ++ "hscif0_data_b", ++ "hscif0_ctrl_a", ++ "hscif0_ctrl_b", ++ "hscif0_clk", ++}; ++ ++static const char * const hscif1_groups[] = { ++ "hscif1_data_a", ++ "hscif1_data_b", ++ "hscif1_ctrl_a", ++ "hscif1_ctrl_b", ++ "hscif1_clk_a", ++ "hscif1_clk_b", ++}; ++ ++static const char * const scif_clk_groups[] = { ++ "scif_clk", ++}; ++ ++static const char * const scif0_groups[] = { ++ "scif0_data_a", ++ "scif0_data_b", ++ "scif0_data_c", ++ "scif0_data_d", ++ "scif0_ctrl", ++ "scif0_clk", ++}; ++ ++static const char * const scif1_groups[] = { ++ "scif1_data_a", ++ "scif1_data_b", ++ "scif1_data_c", ++ "scif1_data_d", ++ "scif1_ctrl_a", ++ "scif1_ctrl_c", ++ "scif1_clk_a", ++ "scif1_clk_c", ++}; ++ ++static const char * const scif2_groups[] = { ++ "scif2_data_a", ++ "scif2_data_b", ++ "scif2_data_c", ++ "scif2_data_d", ++ "scif2_data_e", ++ "scif2_clk_a", ++ "scif2_clk_b", ++ "scif2_clk_c", ++}; ++ ++static const char * const scif3_groups[] = { ++ "scif3_data_a", ++ "scif3_data_b", ++ "scif3_data_c", ++ "scif3_data_d", ++}; ++ ++static const char * const scif4_groups[] = { ++ "scif4_data_a", ++ "scif4_data_b", ++ "scif4_data_c", ++}; ++ ++static const char * const scif5_groups[] = { ++ "scif5_data_a", ++ "scif5_data_b", ++}; ++ ++static const struct sh_pfc_function pinmux_functions[] = { ++ SH_PFC_FUNCTION(hscif0), ++ SH_PFC_FUNCTION(hscif1), ++ SH_PFC_FUNCTION(scif_clk), ++ SH_PFC_FUNCTION(scif0), ++ SH_PFC_FUNCTION(scif1), ++ SH_PFC_FUNCTION(scif2), ++ SH_PFC_FUNCTION(scif3), ++ SH_PFC_FUNCTION(scif4), ++ SH_PFC_FUNCTION(scif5), ++}; ++ ++static struct pinmux_cfg_reg pinmux_config_regs[] = { ++ { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) { ++ GP_0_31_FN, FN_IP1_14_11, ++ GP_0_30_FN, FN_IP1_10_8, ++ GP_0_29_FN, FN_IP1_7_5, ++ GP_0_28_FN, FN_IP1_4_2, ++ GP_0_27_FN, FN_IP1_1, ++ GP_0_26_FN, FN_IP1_0, ++ GP_0_25_FN, FN_IP0_30, ++ GP_0_24_FN, FN_IP0_29, ++ GP_0_23_FN, FN_IP0_28, ++ GP_0_22_FN, FN_IP0_27, ++ GP_0_21_FN, FN_IP0_26, ++ GP_0_20_FN, FN_IP0_25, ++ GP_0_19_FN, FN_IP0_24, ++ GP_0_18_FN, FN_IP0_23, ++ GP_0_17_FN, FN_IP0_22, ++ GP_0_16_FN, FN_IP0_21, ++ GP_0_15_FN, FN_IP0_20, ++ GP_0_14_FN, FN_IP0_19, ++ GP_0_13_FN, FN_IP0_18, ++ GP_0_12_FN, FN_IP0_17, ++ GP_0_11_FN, FN_IP0_16, ++ GP_0_10_FN, FN_IP0_15, ++ GP_0_9_FN, FN_A3, ++ GP_0_8_FN, FN_A2, ++ GP_0_7_FN, FN_A1, ++ GP_0_6_FN, FN_IP0_14_12, ++ GP_0_5_FN, FN_IP0_11_8, ++ GP_0_4_FN, FN_IP0_7_5, ++ GP_0_3_FN, FN_IP0_4_2, ++ GP_0_2_FN, FN_PENC1, ++ GP_0_1_FN, FN_PENC0, ++ GP_0_0_FN, FN_IP0_1_0 } ++ }, ++ { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) { ++ GP_1_31_FN, FN_IP4_6_4, ++ GP_1_30_FN, FN_IP4_3_1, ++ GP_1_29_FN, FN_IP4_0, ++ GP_1_28_FN, FN_IP3_31, ++ GP_1_27_FN, FN_IP3_30, ++ GP_1_26_FN, FN_IP3_29, ++ GP_1_25_FN, FN_IP3_28, ++ GP_1_24_FN, FN_IP3_27, ++ GP_1_23_FN, FN_IP3_26_24, ++ GP_1_22_FN, FN_IP3_23_21, ++ GP_1_21_FN, FN_IP3_20_19, ++ GP_1_20_FN, FN_IP3_18_16, ++ GP_1_19_FN, FN_IP3_15_13, ++ GP_1_18_FN, FN_IP3_12_10, ++ GP_1_17_FN, FN_IP3_9_8, ++ GP_1_16_FN, FN_IP3_7_5, ++ GP_1_15_FN, FN_IP3_4_2, ++ GP_1_14_FN, FN_IP3_1_0, ++ GP_1_13_FN, FN_IP2_31, ++ GP_1_12_FN, FN_IP2_30, ++ GP_1_11_FN, FN_IP2_17, ++ GP_1_10_FN, FN_IP2_16_14, ++ GP_1_9_FN, FN_IP2_13_12, ++ GP_1_8_FN, FN_IP2_11_9, ++ GP_1_7_FN, FN_IP2_8_6, ++ GP_1_6_FN, FN_IP2_5_3, ++ GP_1_5_FN, FN_IP2_2_0, ++ GP_1_4_FN, FN_IP1_29_28, ++ GP_1_3_FN, FN_IP1_27_25, ++ GP_1_2_FN, FN_IP1_24, ++ GP_1_1_FN, FN_WE0, ++ GP_1_0_FN, FN_IP1_23_21 } ++ }, ++ { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) { ++ GP_2_31_FN, FN_IP6_7, ++ GP_2_30_FN, FN_IP6_6_5, ++ GP_2_29_FN, FN_IP6_4_2, ++ GP_2_28_FN, FN_IP6_1_0, ++ GP_2_27_FN, FN_IP5_30_29, ++ GP_2_26_FN, FN_IP5_28_26, ++ GP_2_25_FN, FN_IP5_25_23, ++ GP_2_24_FN, FN_IP5_22_21, ++ GP_2_23_FN, FN_AUDIO_CLKB, ++ GP_2_22_FN, FN_AUDIO_CLKA, ++ GP_2_21_FN, FN_IP5_20_18, ++ GP_2_20_FN, FN_IP5_17_15, ++ GP_2_19_FN, FN_IP5_14_13, ++ GP_2_18_FN, FN_IP5_12, ++ GP_2_17_FN, FN_IP5_11_10, ++ GP_2_16_FN, FN_IP5_9_8, ++ GP_2_15_FN, FN_IP5_7, ++ GP_2_14_FN, FN_IP5_6, ++ GP_2_13_FN, FN_IP5_5_4, ++ GP_2_12_FN, FN_IP5_3_2, ++ GP_2_11_FN, FN_IP5_1_0, ++ GP_2_10_FN, FN_IP4_30_29, ++ GP_2_9_FN, FN_IP4_28_27, ++ GP_2_8_FN, FN_IP4_26_25, ++ GP_2_7_FN, FN_IP4_24_21, ++ GP_2_6_FN, FN_IP4_20_17, ++ GP_2_5_FN, FN_IP4_16_15, ++ GP_2_4_FN, FN_IP4_14_13, ++ GP_2_3_FN, FN_IP4_12_11, ++ GP_2_2_FN, FN_IP4_10_9, ++ GP_2_1_FN, FN_IP4_8, ++ GP_2_0_FN, FN_IP4_7 } ++ }, ++ { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) { ++ GP_3_31_FN, FN_IP8_10_9, ++ GP_3_30_FN, FN_IP8_8_6, ++ GP_3_29_FN, FN_IP8_5_3, ++ GP_3_28_FN, FN_IP8_2_0, ++ GP_3_27_FN, FN_IP7_31_29, ++ GP_3_26_FN, FN_IP7_28_25, ++ GP_3_25_FN, FN_IP7_24_22, ++ GP_3_24_FN, FN_IP7_21, ++ GP_3_23_FN, FN_IP7_20_18, ++ GP_3_22_FN, FN_IP7_17_15, ++ GP_3_21_FN, FN_IP7_14_12, ++ GP_3_20_FN, FN_IP7_11_9, ++ GP_3_19_FN, FN_IP7_8_6, ++ GP_3_18_FN, FN_IP7_5_4, ++ GP_3_17_FN, FN_IP7_3_2, ++ GP_3_16_FN, FN_IP7_1_0, ++ GP_3_15_FN, FN_IP6_31_30, ++ GP_3_14_FN, FN_IP6_29_28, ++ GP_3_13_FN, FN_IP6_27_26, ++ GP_3_12_FN, FN_IP6_25_24, ++ GP_3_11_FN, FN_IP6_23_22, ++ GP_3_10_FN, FN_IP6_21, ++ GP_3_9_FN, FN_IP6_20_19, ++ GP_3_8_FN, FN_IP6_18_17, ++ GP_3_7_FN, FN_IP6_16, ++ GP_3_6_FN, FN_IP6_15_14, ++ GP_3_5_FN, FN_IP6_13, ++ GP_3_4_FN, FN_IP6_12_11, ++ GP_3_3_FN, FN_IP6_10, ++ GP_3_2_FN, FN_SSI_SCK34, ++ GP_3_1_FN, FN_IP6_9, ++ GP_3_0_FN, FN_IP6_8 } ++ }, ++ { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) { ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ GP_4_26_FN, FN_AVS2, ++ GP_4_25_FN, FN_AVS1, ++ GP_4_24_FN, FN_IP10_24_22, ++ GP_4_23_FN, FN_IP10_21_19, ++ GP_4_22_FN, FN_IP10_18_16, ++ GP_4_21_FN, FN_IP10_15_13, ++ GP_4_20_FN, FN_IP10_12_9, ++ GP_4_19_FN, FN_IP10_8_6, ++ GP_4_18_FN, FN_IP10_5_3, ++ GP_4_17_FN, FN_IP10_2_0, ++ GP_4_16_FN, FN_IP9_29_27, ++ GP_4_15_FN, FN_IP9_26_24, ++ GP_4_14_FN, FN_IP9_23_21, ++ GP_4_13_FN, FN_IP9_20_18, ++ GP_4_12_FN, FN_IP9_17_15, ++ GP_4_11_FN, FN_IP9_14_12, ++ GP_4_10_FN, FN_IP9_11_9, ++ GP_4_9_FN, FN_IP9_8_6, ++ GP_4_8_FN, FN_IP9_5_3, ++ GP_4_7_FN, FN_IP9_2_0, ++ GP_4_6_FN, FN_IP8_29_27, ++ GP_4_5_FN, FN_IP8_26_24, ++ GP_4_4_FN, FN_IP8_23_22, ++ GP_4_3_FN, FN_IP8_21_19, ++ GP_4_2_FN, FN_IP8_18_16, ++ GP_4_1_FN, FN_IP8_15_14, ++ GP_4_0_FN, FN_IP8_13_11 } ++ }, ++ ++ { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32, ++ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, ++ 1, 1, 1, 1, 1, 1, 3, 4, 3, 3, 2) { ++ /* IP0_31 [1] */ ++ 0, 0, ++ /* IP0_30 [1] */ ++ FN_A19, 0, ++ /* IP0_29 [1] */ ++ FN_A18, 0, ++ /* IP0_28 [1] */ ++ FN_A17, 0, ++ /* IP0_27 [1] */ ++ FN_A16, 0, ++ /* IP0_26 [1] */ ++ FN_A15, 0, ++ /* IP0_25 [1] */ ++ FN_A14, 0, ++ /* IP0_24 [1] */ ++ FN_A13, 0, ++ /* IP0_23 [1] */ ++ FN_A12, 0, ++ /* IP0_22 [1] */ ++ FN_A11, 0, ++ /* IP0_21 [1] */ ++ FN_A10, 0, ++ /* IP0_20 [1] */ ++ FN_A9, 0, ++ /* IP0_19 [1] */ ++ FN_A8, 0, ++ /* IP0_18 [1] */ ++ FN_A7, 0, ++ /* IP0_17 [1] */ ++ FN_A6, 0, ++ /* IP0_16 [1] */ ++ FN_A5, 0, ++ /* IP0_15 [1] */ ++ FN_A4, 0, ++ /* IP0_14_12 [3] */ ++ FN_SD1_DAT3_A, FN_MMC_D3, 0, FN_A0, ++ FN_ATAG0_A, 0, FN_REMOCON_B, 0, ++ /* IP0_11_8 [4] */ ++ FN_SD1_DAT2_A, FN_MMC_D2, 0, FN_BS, ++ FN_ATADIR0_A, 0, FN_SDSELF_B, 0, ++ FN_PWM4_B, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IP0_7_5 [3] */ ++ FN_AUDATA1, FN_ARM_TRACEDATA_1, FN_GPSIN_C, FN_USB_OVC1, ++ FN_RX2_E, FN_SCL2_B, 0, 0, ++ /* IP0_4_2 [3] */ ++ FN_AUDATA0, FN_ARM_TRACEDATA_0, FN_GPSCLK_C, FN_USB_OVC0, ++ FN_TX2_E, FN_SDA2_B, 0, 0, ++ /* IP0_1_0 [2] */ ++ FN_PRESETOUT, 0, FN_PWM1, 0, ++ } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32, ++ 1, 1, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3, 3, 1, 1) { ++ /* IP1_31 [1] */ ++ 0, 0, ++ /* IP1_30 [1] */ ++ 0, 0, ++ /* IP1_29_28 [2] */ ++ FN_EX_CS1, FN_MMC_D4, 0, 0, ++ /* IP1_27_25 [3] */ ++ FN_SSI_WS1_B, FN_EX_CS0, FN_SCL2_A, FN_TX3_C, ++ FN_TS_SCK0_A, 0, 0, 0, ++ /* IP1_24 [1] */ ++ FN_WE1, FN_ATAWR0_B, ++ /* IP1_23_21 [3] */ ++ FN_MMC_D5, FN_ATADIR0_B, 0, FN_RD_WR, ++ 0, 0, 0, 0, ++ /* IP1_20_18 [3] */ ++ FN_SSI_SCK1_B, FN_ATAG0_B, FN_CS1_A26, FN_SDA2_A, ++ FN_SCK2_B, 0, 0, 0, ++ /* IP1_17 [1] */ ++ FN_CS0, FN_HSPI_RX1_B, ++ /* IP1_16_15 [2] */ ++ FN_CLKOUT, FN_HSPI_TX1_B, FN_PWM0_B, 0, ++ /* IP1_14_11 [4] */ ++ FN_SD1_WP_A, FN_MMC_D7, 0, FN_A25, ++ FN_DACK1_A, 0, FN_HCTS0_B, FN_RX3_C, ++ FN_TS_SDAT0_A, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IP1_10_8 [3] */ ++ FN_SD1_CLK_B, FN_MMC_D6, 0, FN_A24, ++ FN_DREQ1_A, 0, FN_HRX0_B, FN_TS_SPSYNC0_A, ++ /* IP1_7_5 [3] */ ++ FN_A23, FN_HTX0_B, FN_TX2_B, FN_DACK2_A, ++ FN_TS_SDEN0_A, 0, 0, 0, ++ /* IP1_4_2 [3] */ ++ FN_A22, FN_HRTS0_B, FN_RX2_B, FN_DREQ2_A, ++ 0, 0, 0, 0, ++ /* IP1_1 [1] */ ++ FN_A21, FN_HSPI_CLK1_B, ++ /* IP1_0 [1] */ ++ FN_A20, FN_HSPI_CS1_B, ++ } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32, ++ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, ++ 1, 1, 1, 1, 3, 2, 3, 3, 3, 3) { ++ /* IP2_31 [1] */ ++ FN_MLB_CLK, FN_IRQ3_A, ++ /* IP2_30 [1] */ ++ FN_RD_WR_B, FN_IRQ0, ++ /* IP2_29 [1] */ ++ FN_D11, 0, ++ /* IP2_28 [1] */ ++ FN_D10, 0, ++ /* IP2_27 [1] */ ++ FN_D9, 0, ++ /* IP2_26 [1] */ ++ FN_D8, 0, ++ /* IP2_25 [1] */ ++ FN_D7, 0, ++ /* IP2_24 [1] */ ++ FN_D6, 0, ++ /* IP2_23 [1] */ ++ FN_D5, 0, ++ /* IP2_22 [1] */ ++ FN_D4, 0, ++ /* IP2_21 [1] */ ++ FN_D3, 0, ++ /* IP2_20 [1] */ ++ FN_D2, 0, ++ /* IP2_19 [1] */ ++ FN_D1, 0, ++ /* IP2_18 [1] */ ++ FN_D0, 0, ++ /* IP2_17 [1] */ ++ FN_EX_WAIT0, FN_PWM0_C, ++ /* IP2_16_14 [3] */ ++ FN_DACK0, 0, 0, FN_TX3_A, ++ FN_DRACK0, 0, 0, 0, ++ /* IP2_13_12 [2] */ ++ FN_DREQ0_A, 0, 0, FN_RX3_A, ++ /* IP2_11_9 [3] */ ++ FN_SD1_DAT1_A, FN_MMC_D1, 0, FN_ATAWR0_A, ++ FN_EX_CS5, FN_EX_WAIT2_A, 0, 0, ++ /* IP2_8_6 [3] */ ++ FN_SD1_DAT0_A, FN_MMC_D0, 0, FN_ATARD0, ++ FN_EX_CS4, FN_EX_WAIT1_A, 0, 0, ++ /* IP2_5_3 [3] */ ++ FN_SD1_CMD_A, FN_MMC_CMD, 0, FN_ATACS10, ++ FN_EX_CS3, 0, 0, 0, ++ /* IP2_2_0 [3] */ ++ FN_SD1_CLK_A, FN_MMC_CLK, 0, FN_ATACS00, ++ FN_EX_CS2, 0, 0, 0, ++ } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32, ++ 1, 1, 1, 1, 1, 3, 3, 2, ++ 3, 3, 3, 2, 3, 3, 2) { ++ /* IP3_31 [1] */ ++ FN_DU0_DR6, FN_LCDOUT6, ++ /* IP3_30 [1] */ ++ FN_DU0_DR5, FN_LCDOUT5, ++ /* IP3_29 [1] */ ++ FN_DU0_DR4, FN_LCDOUT4, ++ /* IP3_28 [1] */ ++ FN_DU0_DR3, FN_LCDOUT3, ++ /* IP3_27 [1] */ ++ FN_DU0_DR2, FN_LCDOUT2, ++ /* IP3_26_24 [3] */ ++ FN_SSI_WS4, FN_DU0_DR1, FN_LCDOUT1, FN_AUDATA3, ++ FN_ARM_TRACEDATA_3, FN_SCL3_C, FN_ADICHS2, FN_TS_SPSYNC0_B, ++ /* IP3_23_21 [3] */ ++ FN_SSI_SCK4, FN_DU0_DR0, FN_LCDOUT0, FN_AUDATA2, ++ FN_ARM_TRACEDATA_2, FN_SDA3_C, FN_ADICHS1, FN_TS_SDEN0_B, ++ /* IP3_20_19 [2] */ ++ FN_SD1_DAT3_B, FN_HRTS0_A, FN_RTS0, 0, ++ /* IP3_18_16 [3] */ ++ FN_SD1_DAT2_B, FN_HCTS0_A, FN_CTS0, 0, ++ 0, 0, 0, 0, ++ /* IP3_15_13 [3] */ ++ FN_SD1_DAT1_B, FN_HSCK0, FN_SCK0, FN_SCL3_B, ++ 0, 0, 0, 0, ++ /* IP3_12_10 [3] */ ++ FN_SD1_DAT0_B, FN_HRX0_A, FN_RX0_A, 0, ++ 0, 0, 0, 0, ++ /* IP3_9_8 [2] */ ++ FN_SD1_CLK_B, FN_HTX0_A, FN_TX0_A, 0, ++ /* IP3_7_5 [3] */ ++ FN_SD1_CMD_B, FN_SCIF_CLK, FN_AUDIO_CLKOUT_B, FN_CAN_CLK_B, ++ FN_SDA3_B, 0, 0, 0, ++ /* IP3_4_2 [3] */ ++ FN_MLB_DAT, FN_TX5_B, FN_SCL3_A, FN_IRQ3_A, ++ FN_SDSELF_B, 0, 0, 0, ++ /* IP3_1_0 [2] */ ++ FN_MLB_SIG, FN_RX5_B, FN_SDA3_A, FN_IRQ2_A, ++ } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32, ++ 1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1, 3, 3, 1) { ++ /* IP4_31 [1] */ ++ 0, 0, ++ /* IP4_30_29 [2] */ ++ FN_VI0_R4_B, FN_DU0_DB4, FN_LCDOUT20, 0, ++ /* IP4_28_27 [2] */ ++ FN_VI0_R3_B, FN_DU0_DB3, FN_LCDOUT19, 0, ++ /* IP4_26_25 [2] */ ++ FN_VI0_R2_B, FN_DU0_DB2, FN_LCDOUT18, 0, ++ /* IP4_24_21 [4] */ ++ FN_AUDIO_CLKC, FN_VI0_R1_B, FN_DU0_DB1, FN_LCDOUT17, ++ FN_AUDATA7, FN_ARM_TRACEDATA_7, FN_GPSIN_A, 0, ++ FN_ADICS_SAMP, FN_TS_SCK0_B, 0, 0, ++ 0, 0, 0, 0, ++ /* IP4_20_17 [4] */ ++ FN_SSI_SCK2_B, FN_VI0_R0_B, FN_DU0_DB0, FN_LCDOUT16, ++ FN_AUDATA6, FN_ARM_TRACEDATA_6, FN_GPSCLK_A, FN_PWM0_A, ++ FN_ADICLK, FN_TS_SDAT0_B, 0, 0, ++ 0, 0, 0, 0, ++ /* IP4_16_15 [2] */ ++ FN_DU0_DG7, FN_LCDOUT15, FN_TX4_A, 0, ++ /* IP4_14_13 [2] */ ++ FN_DU0_DG6, FN_LCDOUT14, FN_RX4_A, 0, ++ /* IP4_12_11 [2] */ ++ FN_DU0_DG5, FN_LCDOUT13, FN_TX0_B, 0, ++ /* IP4_10_9 [2] */ ++ FN_DU0_DG4, FN_LCDOUT12, FN_RX0_B, 0, ++ /* IP4_8 [1] */ ++ FN_DU0_DG3, FN_LCDOUT11, ++ /* IP4_7 [1] */ ++ FN_DU0_DG2, FN_LCDOUT10, ++ /* IP4_6_4 [3] */ ++ FN_DU0_DG1, FN_LCDOUT9, FN_AUDATA5, FN_ARM_TRACEDATA_5, ++ FN_RX1_D, FN_CAN0_RX_A, FN_ADIDATA, 0, ++ /* IP4_3_1 [3] */ ++ FN_DU0_DG0, FN_LCDOUT8, FN_AUDATA4, FN_ARM_TRACEDATA_4, ++ FN_TX1_D, FN_CAN0_TX_A, FN_ADICHS0, 0, ++ /* IP4_0 [1] */ ++ FN_DU0_DR7, FN_LCDOUT7, ++ } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32, ++ 1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1, 1, 2, 2, 2) { ++ ++ /* IP5_31 [1] */ ++ 0, 0, ++ /* IP5_30_29 [2] */ ++ FN_SSI_SDATA7, FN_HSPI_TX0_B, FN_RX2_A, FN_CAN0_RX_B, ++ /* IP5_28_26 [3] */ ++ FN_SSI_SDATA8, FN_SSI_SCK2_A, FN_HSPI_CS0_B, FN_TX2_A, ++ FN_CAN0_TX_B, 0, 0, 0, ++ /* IP5_25_23 [3] */ ++ FN_SD1_WP_B, FN_SSI_WS78, FN_HSPI_CLK0_B, FN_RX1_B, ++ FN_CAN_CLK_D, 0, 0, 0, ++ /* IP5_22_21 [2] */ ++ FN_SD1_CD_B, FN_SSI_SCK78, FN_HSPI_RX0_B, FN_TX1_B, ++ /* IP5_20_18 [3] */ ++ FN_SSI_WS1_A, FN_DU0_CDE, FN_QPOLB, FN_AUDSYNC, ++ FN_ARM_TRACECTL, FN_FMIN_D, 0, 0, ++ /* IP5_17_15 [3] */ ++ FN_SSI_SCK1_A, FN_DU0_DISP, FN_QPOLA, FN_AUDCK, ++ FN_ARM_TRACECLK, FN_BPFCLK_D, 0, 0, ++ /* IP5_14_13 [2] */ ++ FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, ++ FN_FMCLK_D, 0, ++ /* IP5_12 [1] */ ++ FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, ++ /* IP5_11_10 [2] */ ++ FN_SSI_WS2_B, FN_DU0_EXHSYNC_DU0_HSYNC, ++ FN_QSTH_QHS, 0, ++ /* IP5_9_8 [2] */ ++ FN_DU0_DOTCLKO_UT1, FN_QSTVB_QVE, ++ FN_AUDIO_CLKOUT_A, FN_REMOCON_C, ++ /* IP5_7 [1] */ ++ FN_DU0_DOTCLKO_UT0, FN_QCLK, ++ /* IP5_6 [1] */ ++ FN_DU0_DOTCLKIN, FN_QSTVA_QVS, ++ /* IP5_5_4 [2] */ ++ FN_VI1_DATA11_B, FN_DU0_DB7, FN_LCDOUT23, 0, ++ /* IP5_3_2 [2] */ ++ FN_VI1_DATA10_B, FN_DU0_DB6, FN_LCDOUT22, 0, ++ /* IP5_1_0 [2] */ ++ FN_VI0_R5_B, FN_DU0_DB5, FN_LCDOUT21, 0, ++ } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32, ++ 2, 2, 2, 2, 2, 1, 2, 2, 1, 2, ++ 1, 2, 1, 1, 1, 1, 2, 3, 2) { ++ /* IP6_31_30 [2] */ ++ FN_SD0_DAT2, 0, FN_SUB_TDI, 0, ++ /* IP6_29_28 [2] */ ++ FN_SD0_DAT1, 0, FN_SUB_TCK, 0, ++ /* IP6_27_26 [2] */ ++ FN_SD0_DAT0, 0, FN_SUB_TMS, 0, ++ /* IP6_25_24 [2] */ ++ FN_SD0_CMD, 0, FN_SUB_TRST, 0, ++ /* IP6_23_22 [2] */ ++ FN_SD0_CLK, 0, FN_SUB_TDO, 0, ++ /* IP6_21 [1] */ ++ FN_SSI_SDATA0, FN_ARM_TRACEDATA_15, ++ /* IP6_20_19 [2] */ ++ FN_SSI_SDATA1, FN_ARM_TRACEDATA_14, ++ FN_SCL1_A, FN_SCK2_A, ++ /* IP6_18_17 [2] */ ++ FN_SSI_SDATA2, FN_HSPI_CS2_A, ++ FN_ARM_TRACEDATA_13, FN_SDA1_A, ++ /* IP6_16 [1] */ ++ FN_SSI_WS012, FN_ARM_TRACEDATA_12, ++ /* IP6_15_14 [2] */ ++ FN_SSI_SCK012, FN_ARM_TRACEDATA_11, ++ FN_TX0_D, 0, ++ /* IP6_13 [1] */ ++ FN_SSI_SDATA3, FN_ARM_TRACEDATA_10, ++ /* IP6_12_11 [2] */ ++ FN_SSI_SDATA4, FN_SSI_WS2_A, ++ FN_ARM_TRACEDATA_9, 0, ++ /* IP6_10 [1] */ ++ FN_SSI_WS34, FN_ARM_TRACEDATA_8, ++ /* IP6_9 [1] */ ++ FN_SSI_SDATA5, FN_RX0_D, ++ /* IP6_8 [1] */ ++ FN_SSI_WS5, FN_TX4_C, ++ /* IP6_7 [1] */ ++ FN_SSI_SCK5, FN_RX4_C, ++ /* IP6_6_5 [2] */ ++ FN_SSI_SDATA6, FN_HSPI_TX2_A, ++ FN_FMIN_B, 0, ++ /* IP6_4_2 [3] */ ++ FN_SSI_WS6, FN_HSPI_CLK2_A, ++ FN_BPFCLK_B, FN_CAN1_RX_B, ++ 0, 0, 0, 0, ++ /* IP6_1_0 [2] */ ++ FN_SSI_SCK6, FN_HSPI_RX2_A, ++ FN_FMCLK_B, FN_CAN1_TX_B, ++ } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32, ++ 3, 4, 3, 1, 3, 3, 3, 3, 3, 2, 2, 2) { ++ ++ /* IP7_31_29 [3] */ ++ FN_VI0_HSYNC, FN_SD2_CD_B, FN_VI1_DATA2, FN_DU1_DR2, ++ 0, FN_HSPI_CS1_A, FN_RX3_B, 0, ++ /* IP7_28_25 [4] */ ++ FN_VI0_FIELD, FN_SD2_DAT3_B, FN_VI0_R3_C, FN_VI1_DATA1, ++ FN_DU1_DG7, 0, FN_HSPI_CLK1_A, FN_TX4_B, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IP7_24_22 [3] */ ++ FN_VI0_CLKENB, FN_SD2_DAT2_B, FN_VI1_DATA0, FN_DU1_DG6, ++ 0, FN_HSPI_RX1_A, FN_RX4_B, 0, ++ /* IP7_21 [1] */ ++ FN_VI0_CLK, FN_CAN_CLK_A, ++ /* IP7_20_18 [3] */ ++ FN_TCLK0, FN_HSCK1_A, FN_FMIN_A, 0, ++ FN_IRQ2_C, FN_CTS1_C, FN_SPEEDIN, 0, ++ /* IP7_17_15 [3] */ ++ FN_VI1_VSYNC, FN_HSPI_TX0, FN_HCTS1_A, FN_BPFCLK_A, ++ 0, FN_TX1_C, 0, 0, ++ /* IP7_14_12 [3] */ ++ FN_VI1_HSYNC, FN_HSPI_RX0_A, FN_HRTS1_A, FN_FMCLK_A, ++ 0, FN_RX1_C, 0, 0, ++ /* IP7_11_9 [3] */ ++ FN_VI1_FIELD, FN_HSPI_CS0_A, FN_HRX1_A, 0, ++ FN_SCK1_C, 0, 0, 0, ++ /* IP7_8_6 [3] */ ++ FN_VI1_CLKENB, FN_HSPI_CLK0_A, FN_HTX1_A, 0, ++ FN_RTS1_C, 0, 0, 0, ++ /* IP7_5_4 [2] */ ++ FN_SD0_WP, 0, FN_RX5_A, 0, ++ /* IP7_3_2 [2] */ ++ FN_SD0_CD, 0, FN_TX5_A, 0, ++ /* IP7_1_0 [2] */ ++ FN_SD0_DAT3, 0, FN_IRQ1_B, 0, ++ } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32, ++ 1, 1, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3) { ++ /* IP8_31 [1] */ ++ 0, 0, ++ /* IP8_30 [1] */ ++ 0, 0, ++ /* IP8_29_27 [3] */ ++ FN_VI0_G3, FN_SD2_CMD_B, FN_VI1_DATA5, FN_DU1_DR5, ++ 0, FN_HRX1_B, 0, 0, ++ /* IP8_26_24 [3] */ ++ FN_VI0_G2, FN_SD2_CLK_B, FN_VI1_DATA4, FN_DU1_DR4, ++ 0, FN_HTX1_B, 0, 0, ++ /* IP8_23_22 [2] */ ++ FN_VI0_DATA7_VI0_G1, FN_DU1_DB5, ++ FN_RTS1_A, 0, ++ /* IP8_21_19 [3] */ ++ FN_VI0_DATA6_VI0_G0, FN_DU1_DB4, ++ FN_CTS1_A, FN_PWM5, ++ 0, 0, 0, 0, ++ /* IP8_18_16 [3] */ ++ FN_VI0_DATA5_VI0_B5, FN_DU1_DB3, FN_SCK1_A, FN_PWM4, ++ 0, FN_HSCK1_B, 0, 0, ++ /* IP8_15_14 [2] */ ++ FN_VI0_DATA4_VI0_B4, FN_DU1_DB2, FN_RX1_A, 0, ++ /* IP8_13_11 [3] */ ++ FN_VI0_DATA3_VI0_B3, FN_DU1_DG5, FN_TX1_A, FN_TX0_C, ++ 0, 0, 0, 0, ++ /* IP8_10_9 [2] */ ++ FN_VI0_DATA2_VI0_B2, FN_DU1_DG4, FN_RX0_C, 0, ++ /* IP8_8_6 [3] */ ++ FN_VI0_DATA1_VI0_B1, FN_DU1_DG3, FN_IRQ3_B, FN_TX3_D, ++ 0, 0, 0, 0, ++ /* IP8_5_3 [3] */ ++ FN_VI0_DATA0_VI0_B0, FN_DU1_DG2, FN_IRQ2_B, FN_RX3_D, ++ 0, 0, 0, 0, ++ /* IP8_2_0 [3] */ ++ FN_VI0_VSYNC, FN_SD2_WP_B, FN_VI1_DATA3, FN_DU1_DR3, ++ 0, FN_HSPI_TX1_A, FN_TX3_B, 0, ++ } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32, ++ 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { ++ /* IP9_31 [1] */ ++ 0, 0, ++ /* IP9_30 [1] */ ++ 0, 0, ++ /* IP9_29_27 [3] */ ++ FN_VI1_DATA11_A, FN_DU1_EXHSYNC_DU1_HSYNC, ++ FN_ETH_RXD1, FN_FMIN_C, ++ 0, FN_RX2_D, ++ FN_SCL2_C, 0, ++ /* IP9_26_24 [3] */ ++ FN_VI1_DATA10_A, FN_DU1_DOTCLKOUT, ++ FN_ETH_RXD0, FN_BPFCLK_C, ++ 0, FN_TX2_D, ++ FN_SDA2_C, 0, ++ /* IP9_23_21 [3] */ ++ FN_VI0_R5_A, 0, FN_ETH_RX_ER, FN_FMCLK_C, ++ FN_IERX, FN_RX2_C, 0, 0, ++ /* IP9_20_18 [3] */ ++ FN_VI0_R4_A, FN_ETH_TX_EN, 0, 0, ++ FN_IETX, FN_TX2_C, 0, 0, ++ /* IP9_17_15 [3] */ ++ FN_VI0_R3_A, FN_ETH_CRS_DV, 0, FN_IECLK, ++ FN_SCK2_C, 0, 0, 0, ++ /* IP9_14_12 [3] */ ++ FN_VI0_R2_A, FN_VI1_DATA9, FN_DU1_DB7, FN_ETH_TXD1, ++ 0, FN_PWM3, 0, 0, ++ /* IP9_11_9 [3] */ ++ FN_VI0_R1_A, FN_VI1_DATA8, FN_DU1_DB6, FN_ETH_TXD0, ++ 0, FN_PWM2, FN_TCLK1, 0, ++ /* IP9_8_6 [3] */ ++ FN_VI0_R0_A, FN_VI1_CLK, FN_ETH_REF_CLK, FN_DU1_DOTCLKIN, ++ 0, 0, 0, 0, ++ /* IP9_5_3 [3] */ ++ FN_VI0_G5, FN_SD2_DAT1_B, FN_VI1_DATA7, FN_DU1_DR7, ++ 0, FN_HCTS1_B, 0, 0, ++ /* IP9_2_0 [3] */ ++ FN_VI0_G4, FN_SD2_DAT0_B, FN_VI1_DATA6, FN_DU1_DR6, ++ 0, FN_HRTS1_B, 0, 0, ++ } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32, ++ 1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 4, 3, 3, 3) { ++ ++ /* IP10_31 [1] */ ++ 0, 0, ++ /* IP10_30 [1] */ ++ 0, 0, ++ /* IP10_29 [1] */ ++ 0, 0, ++ /* IP10_28 [1] */ ++ 0, 0, ++ /* IP10_27 [1] */ ++ 0, 0, ++ /* IP10_26 [1] */ ++ 0, 0, ++ /* IP10_25 [1] */ ++ 0, 0, ++ /* IP10_24_22 [3] */ ++ FN_SD2_WP_A, FN_VI1_DATA15, FN_EX_WAIT2_B, FN_DACK0_B, ++ FN_HSPI_TX2_B, FN_CAN_CLK_C, 0, 0, ++ /* IP10_21_19 [3] */ ++ FN_SD2_CD_A, FN_VI1_DATA14, FN_EX_WAIT1_B, FN_DREQ0_B, ++ FN_HSPI_RX2_B, FN_REMOCON_A, 0, 0, ++ /* IP10_18_16 [3] */ ++ FN_SD2_DAT3_A, FN_VI1_DATA13, FN_DACK2_B, FN_ATAG1, ++ FN_HSPI_CS2_B, FN_GPSIN_B, 0, 0, ++ /* IP10_15_13 [3] */ ++ FN_SD2_DAT2_A, FN_VI1_DATA12, FN_DREQ2_B, FN_ATADIR1, ++ FN_HSPI_CLK2_B, FN_GPSCLK_B, 0, 0, ++ /* IP10_12_9 [4] */ ++ FN_SD2_DAT1_A, FN_DU1_CDE, FN_ATACS11, FN_DACK1_B, ++ FN_ETH_MAGIC, FN_CAN1_TX_A, 0, FN_PWM6, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IP10_8_6 [3] */ ++ FN_SD2_DAT0_A, FN_DU1_DISP, FN_ATACS01, FN_DREQ1_B, ++ FN_ETH_LINK, FN_CAN1_RX_A, 0, 0, ++ /* IP10_5_3 [3] */ ++ FN_SD2_CMD_A, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, ++ FN_ATAWR1, FN_ETH_MDIO, ++ FN_SCL1_B, 0, ++ 0, 0, ++ /* IP10_2_0 [3] */ ++ FN_SD2_CLK_A, FN_DU1_EXVSYNC_DU1_VSYNC, ++ FN_ATARD1, FN_ETH_MDC, ++ FN_SDA1_B, 0, ++ 0, 0, ++ } ++ }, ++ { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xfffc0050, 32, ++ 1, 1, 2, 2, 3, 2, 2, 1, 1, 1, 1, 2, ++ 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) { ++ ++ /* SEL 31 [1] */ ++ 0, 0, ++ /* SEL_30 (SCIF5) [1] */ ++ FN_SEL_SCIF5_A, FN_SEL_SCIF5_B, ++ /* SEL_29_28 (SCIF4) [2] */ ++ FN_SEL_SCIF4_A, FN_SEL_SCIF4_B, ++ FN_SEL_SCIF4_C, 0, ++ /* SEL_27_26 (SCIF3) [2] */ ++ FN_SEL_SCIF3_A, FN_SEL_SCIF3_B, ++ FN_SEL_SCIF3_C, FN_SEL_SCIF3_D, ++ /* SEL_25_23 (SCIF2) [3] */ ++ FN_SEL_SCIF2_A, FN_SEL_SCIF2_B, ++ FN_SEL_SCIF2_C, FN_SEL_SCIF2_D, ++ FN_SEL_SCIF2_E, 0, ++ 0, 0, ++ /* SEL_22_21 (SCIF1) [2] */ ++ FN_SEL_SCIF1_A, FN_SEL_SCIF1_B, ++ FN_SEL_SCIF1_C, FN_SEL_SCIF1_D, ++ /* SEL_20_19 (SCIF0) [2] */ ++ FN_SEL_SCIF0_A, FN_SEL_SCIF0_B, ++ FN_SEL_SCIF0_C, FN_SEL_SCIF0_D, ++ /* SEL_18 [1] */ ++ 0, 0, ++ /* SEL_17 (SSI2) [1] */ ++ FN_SEL_SSI2_A, FN_SEL_SSI2_B, ++ /* SEL_16 (SSI1) [1] */ ++ FN_SEL_SSI1_A, FN_SEL_SSI1_B, ++ /* SEL_15 (VI1) [1] */ ++ FN_SEL_VI1_A, FN_SEL_VI1_B, ++ /* SEL_14_13 (VI0) [2] */ ++ FN_SEL_VI0_A, FN_SEL_VI0_B, ++ FN_SEL_VI0_C, FN_SEL_VI0_D, ++ /* SEL_12 [1] */ ++ 0, 0, ++ /* SEL_11 (SD2) [1] */ ++ FN_SEL_SD2_A, FN_SEL_SD2_B, ++ /* SEL_10 (SD1) [1] */ ++ FN_SEL_SD1_A, FN_SEL_SD1_B, ++ /* SEL_9 (IRQ3) [1] */ ++ FN_SEL_IRQ3_A, FN_SEL_IRQ3_B, ++ /* SEL_8_7 (IRQ2) [2] */ ++ FN_SEL_IRQ2_A, FN_SEL_IRQ2_B, ++ FN_SEL_IRQ2_C, 0, ++ /* SEL_6 (IRQ1) [1] */ ++ FN_SEL_IRQ1_A, FN_SEL_IRQ1_B, ++ /* SEL_5 [1] */ ++ 0, 0, ++ /* SEL_4 (DREQ2) [1] */ ++ FN_SEL_DREQ2_A, FN_SEL_DREQ2_B, ++ /* SEL_3 (DREQ1) [1] */ ++ FN_SEL_DREQ1_A, FN_SEL_DREQ1_B, ++ /* SEL_2 (DREQ0) [1] */ ++ FN_SEL_DREQ0_A, FN_SEL_DREQ0_B, ++ /* SEL_1 (WAIT2) [1] */ ++ FN_SEL_WAIT2_A, FN_SEL_WAIT2_B, ++ /* SEL_0 (WAIT1) [1] */ ++ FN_SEL_WAIT1_A, FN_SEL_WAIT1_B, ++ } ++ }, ++ { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xfffc0054, 32, ++ 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, ++ 1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 2, 2, 1) { ++ ++ /* SEL_31 [1] */ ++ 0, 0, ++ /* SEL_30 [1] */ ++ 0, 0, ++ /* SEL_29 [1] */ ++ 0, 0, ++ /* SEL_28 [1] */ ++ 0, 0, ++ /* SEL_27 (CAN1) [1] */ ++ FN_SEL_CAN1_A, FN_SEL_CAN1_B, ++ /* SEL_26 (CAN0) [1] */ ++ FN_SEL_CAN0_A, FN_SEL_CAN0_B, ++ /* SEL_25_24 (CANCLK) [2] */ ++ FN_SEL_CANCLK_A, FN_SEL_CANCLK_B, ++ FN_SEL_CANCLK_C, FN_SEL_CANCLK_D, ++ /* SEL_23 (HSCIF1) [1] */ ++ FN_SEL_HSCIF1_A, FN_SEL_HSCIF1_B, ++ /* SEL_22 (HSCIF0) [1] */ ++ FN_SEL_HSCIF0_A, FN_SEL_HSCIF0_B, ++ /* SEL_21 [1] */ ++ 0, 0, ++ /* SEL_20 [1] */ ++ 0, 0, ++ /* SEL_19 [1] */ ++ 0, 0, ++ /* SEL_18 [1] */ ++ 0, 0, ++ /* SEL_17 [1] */ ++ 0, 0, ++ /* SEL_16 [1] */ ++ 0, 0, ++ /* SEL_15 [1] */ ++ 0, 0, ++ /* SEL_14_13 (REMOCON) [2] */ ++ FN_SEL_REMOCON_A, FN_SEL_REMOCON_B, ++ FN_SEL_REMOCON_C, 0, ++ /* SEL_12_11 (FM) [2] */ ++ FN_SEL_FM_A, FN_SEL_FM_B, ++ FN_SEL_FM_C, FN_SEL_FM_D, ++ /* SEL_10_9 (GPS) [2] */ ++ FN_SEL_GPS_A, FN_SEL_GPS_B, ++ FN_SEL_GPS_C, 0, ++ /* SEL_8 (TSIF0) [1] */ ++ FN_SEL_TSIF0_A, FN_SEL_TSIF0_B, ++ /* SEL_7 (HSPI2) [1] */ ++ FN_SEL_HSPI2_A, FN_SEL_HSPI2_B, ++ /* SEL_6 (HSPI1) [1] */ ++ FN_SEL_HSPI1_A, FN_SEL_HSPI1_B, ++ /* SEL_5 (HSPI0) [1] */ ++ FN_SEL_HSPI0_A, FN_SEL_HSPI0_B, ++ /* SEL_4_3 (I2C3) [2] */ ++ FN_SEL_I2C3_A, FN_SEL_I2C3_B, ++ FN_SEL_I2C3_C, 0, ++ /* SEL_2_1 (I2C2) [2] */ ++ FN_SEL_I2C2_A, FN_SEL_I2C2_B, ++ FN_SEL_I2C2_C, 0, ++ /* SEL_0 (I2C1) [1] */ ++ FN_SEL_I2C1_A, FN_SEL_I2C1_B, ++ } ++ }, ++ { }, ++}; ++ ++const struct sh_pfc_soc_info r8a7778_pinmux_info = { ++ .name = "r8a7778_pfc", ++ ++ .unlock_reg = 0xfffc0000, /* PMMR */ ++ ++ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, ++ ++ .pins = pinmux_pins, ++ .nr_pins = ARRAY_SIZE(pinmux_pins), ++ ++ .groups = pinmux_groups, ++ .nr_groups = ARRAY_SIZE(pinmux_groups), ++ ++ .functions = pinmux_functions, ++ .nr_functions = ARRAY_SIZE(pinmux_functions), ++ ++ .cfg_regs = pinmux_config_regs, ++ ++ .gpio_data = pinmux_data, ++ .gpio_data_size = ARRAY_SIZE(pinmux_data), ++}; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0092-sh-pfc-r8a7740-Add-SCIFA1-data-group.patch b/patches.renesas/0092-sh-pfc-r8a7740-Add-SCIFA1-data-group.patch new file mode 100644 index 00000000000..25cb501b09c --- /dev/null +++ b/patches.renesas/0092-sh-pfc-r8a7740-Add-SCIFA1-data-group.patch @@ -0,0 +1,65 @@ +From b2a31fcd17540e368881401a8bb1970d6e6cf6cc Mon Sep 17 00:00:00 2001 +From: Bastian Hecht <hechtb@gmail.com> +Date: Wed, 17 Apr 2013 10:34:01 +0000 +Subject: sh-pfc: r8a7740: Add SCIFA1 data group + +Add SCIFA1 as preparation to switch to pinctrl in board files. + +Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 8fbfdbbb04f88604f58c032440a2bc03649697ba) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +index d95040c3..4753f544 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +@@ -1999,6 +1999,14 @@ static const unsigned int mmc0_ctrl_1_pins[] = { + static const unsigned int mmc0_ctrl_1_mux[] = { + MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK, + }; ++/* - SCIFA1 ----------------------------------------------------------------- */ ++static const unsigned int scifa1_data_pins[] = { ++ /* RXD, TXD */ ++ 195, 196, ++}; ++static const unsigned int scifa1_data_mux[] = { ++ SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, ++}; + /* - SDHI0 ------------------------------------------------------------------ */ + static const unsigned int sdhi0_data1_pins[] = { + /* D0 */ +@@ -2204,6 +2212,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(mmc0_data4_1), + SH_PFC_PIN_GROUP(mmc0_data8_1), + SH_PFC_PIN_GROUP(mmc0_ctrl_1), ++ SH_PFC_PIN_GROUP(scifa1_data), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), +@@ -2316,6 +2325,10 @@ static const char * const mmc0_groups[] = { + "mmc0_ctrl_1", + }; + ++static const char * const scifa1_groups[] = { ++ "scifa1_data", ++}; ++ + static const char * const sdhi0_groups[] = { + "sdhi0_data1", + "sdhi0_data4", +@@ -2346,6 +2359,7 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(lcd0), + SH_PFC_FUNCTION(lcd1), + SH_PFC_FUNCTION(mmc0), ++ SH_PFC_FUNCTION(scifa1), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0093-sh-pfc-r8a7779-Replace-hardcoded-pin-numbers-with-RC.patch b/patches.renesas/0093-sh-pfc-r8a7779-Replace-hardcoded-pin-numbers-with-RC.patch new file mode 100644 index 00000000000..d1072ee6b1c --- /dev/null +++ b/patches.renesas/0093-sh-pfc-r8a7779-Replace-hardcoded-pin-numbers-with-RC.patch @@ -0,0 +1,1112 @@ +From 0cf58a15a72fcdaf766772e38d9c2035f2180ff7 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 8 Apr 2013 12:05:31 +0200 +Subject: sh-pfc: r8a7779: Replace hardcoded pin numbers with RCAR_GP_PIN macro + +Use the RCAR_GP_PIN macro to convert from the documentation pin number +space to the linear pinctrl space. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit e21ea1977ca37596bd1cfc0dcb230a7b21811b71) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 300 +++++++++++++++++++---------------- + 1 file changed, 167 insertions(+), 133 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +index 8cd90e7e..e1491a50 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +@@ -19,6 +19,7 @@ + */ + + #include <linux/kernel.h> ++#include <linux/platform_data/gpio-rcar.h> + + #include "sh_pfc.h" + +@@ -1472,9 +1473,12 @@ static struct sh_pfc_pin pinmux_pins[] = { + /* - DU0 -------------------------------------------------------------------- */ + static const unsigned int du0_rgb666_pins[] = { + /* R[7:2], G[7:2], B[7:2] */ +- 188, 187, 186, 185, 184, 183, +- 194, 193, 192, 191, 190, 189, +- 200, 199, 198, 197, 196, 195, ++ RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26), ++ RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), ++ RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 0), ++ RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29), ++ RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), ++ RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 3), + }; + static const unsigned int du0_rgb666_mux[] = { + DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK, +@@ -1486,9 +1490,14 @@ static const unsigned int du0_rgb666_mux[] = { + }; + static const unsigned int du0_rgb888_pins[] = { + /* R[7:0], G[7:0], B[7:0] */ +- 188, 187, 186, 185, 184, 183, 24, 23, +- 194, 193, 192, 191, 190, 189, 26, 25, +- 200, 199, 198, 197, 196, 195, 28, 27, ++ RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26), ++ RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), ++ RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23), RCAR_GP_PIN(6, 2), ++ RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(5, 31), ++ RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29), RCAR_GP_PIN(0, 26), ++ RCAR_GP_PIN(0, 25), RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 7), ++ RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 4), ++ RCAR_GP_PIN(6, 3), RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 27), + }; + static const unsigned int du0_rgb888_mux[] = { + DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK, +@@ -1500,28 +1509,28 @@ static const unsigned int du0_rgb888_mux[] = { + }; + static const unsigned int du0_clk_in_pins[] = { + /* CLKIN */ +- 29, ++ RCAR_GP_PIN(0, 29), + }; + static const unsigned int du0_clk_in_mux[] = { + DU0_DOTCLKIN_MARK, + }; + static const unsigned int du0_clk_out_0_pins[] = { + /* CLKOUT */ +- 180, ++ RCAR_GP_PIN(5, 20), + }; + static const unsigned int du0_clk_out_0_mux[] = { + DU0_DOTCLKOUT0_MARK, + }; + static const unsigned int du0_clk_out_1_pins[] = { + /* CLKOUT */ +- 30, ++ RCAR_GP_PIN(0, 30), + }; + static const unsigned int du0_clk_out_1_mux[] = { + DU0_DOTCLKOUT1_MARK, + }; + static const unsigned int du0_sync_0_pins[] = { + /* VSYNC, HSYNC, DISP */ +- 182, 181, 31, ++ RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(0, 31), + }; + static const unsigned int du0_sync_0_mux[] = { + DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, +@@ -1529,7 +1538,7 @@ static const unsigned int du0_sync_0_mux[] = { + }; + static const unsigned int du0_sync_1_pins[] = { + /* VSYNC, HSYNC, DISP */ +- 182, 181, 32, ++ RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(1, 0), + }; + static const unsigned int du0_sync_1_mux[] = { + DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, +@@ -1537,14 +1546,14 @@ static const unsigned int du0_sync_1_mux[] = { + }; + static const unsigned int du0_oddf_pins[] = { + /* ODDF */ +- 31, ++ RCAR_GP_PIN(0, 31), + }; + static const unsigned int du0_oddf_mux[] = { + DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK + }; + static const unsigned int du0_cde_pins[] = { + /* CDE */ +- 33, ++ RCAR_GP_PIN(1, 1), + }; + static const unsigned int du0_cde_mux[] = { + DU0_CDE_MARK +@@ -1552,9 +1561,12 @@ static const unsigned int du0_cde_mux[] = { + /* - DU1 -------------------------------------------------------------------- */ + static const unsigned int du1_rgb666_pins[] = { + /* R[7:2], G[7:2], B[7:2] */ +- 41, 40, 39, 38, 37, 36, +- 49, 48, 47, 46, 45, 44, +- 57, 56, 55, 54, 53, 52, ++ RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), ++ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4), ++ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15), ++ RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12), ++ RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23), ++ RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 20), + }; + static const unsigned int du1_rgb666_mux[] = { + DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, +@@ -1566,9 +1578,14 @@ static const unsigned int du1_rgb666_mux[] = { + }; + static const unsigned int du1_rgb888_pins[] = { + /* R[7:0], G[7:0], B[7:0] */ +- 41, 40, 39, 38, 37, 36, 35, 34, +- 49, 48, 47, 46, 45, 44, 43, 32, +- 57, 56, 55, 54, 53, 52, 51, 50, ++ RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), ++ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4), ++ RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 17), ++ RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), ++ RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), ++ RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24), ++ RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), ++ RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), + }; + static const unsigned int du1_rgb888_mux[] = { + DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, +@@ -1580,21 +1597,21 @@ static const unsigned int du1_rgb888_mux[] = { + }; + static const unsigned int du1_clk_in_pins[] = { + /* CLKIN */ +- 58, ++ RCAR_GP_PIN(1, 26), + }; + static const unsigned int du1_clk_in_mux[] = { + DU1_DOTCLKIN_MARK, + }; + static const unsigned int du1_clk_out_pins[] = { + /* CLKOUT */ +- 59, ++ RCAR_GP_PIN(1, 27), + }; + static const unsigned int du1_clk_out_mux[] = { + DU1_DOTCLKOUT_MARK, + }; + static const unsigned int du1_sync_0_pins[] = { + /* VSYNC, HSYNC, DISP */ +- 61, 60, 62, ++ RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 30), + }; + static const unsigned int du1_sync_0_mux[] = { + DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, +@@ -1602,7 +1619,7 @@ static const unsigned int du1_sync_0_mux[] = { + }; + static const unsigned int du1_sync_1_pins[] = { + /* VSYNC, HSYNC, DISP */ +- 61, 60, 63, ++ RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 31), + }; + static const unsigned int du1_sync_1_mux[] = { + DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, +@@ -1610,14 +1627,14 @@ static const unsigned int du1_sync_1_mux[] = { + }; + static const unsigned int du1_oddf_pins[] = { + /* ODDF */ +- 62, ++ RCAR_GP_PIN(1, 30), + }; + static const unsigned int du1_oddf_mux[] = { + DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK + }; + static const unsigned int du1_cde_pins[] = { + /* CDE */ +- 64, ++ RCAR_GP_PIN(2, 0), + }; + static const unsigned int du1_cde_mux[] = { + DU1_CDE_MARK +@@ -1625,7 +1642,8 @@ static const unsigned int du1_cde_mux[] = { + /* - HSPI0 ------------------------------------------------------------------ */ + static const unsigned int hspi0_pins[] = { + /* CLK, CS, RX, TX */ +- 150, 151, 153, 152, ++ RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 25), ++ RCAR_GP_PIN(4, 24), + }; + static const unsigned int hspi0_mux[] = { + HSPI_CLK0_MARK, HSPI_CS0_MARK, HSPI_RX0_MARK, HSPI_TX0_MARK, +@@ -1633,28 +1651,32 @@ static const unsigned int hspi0_mux[] = { + /* - HSPI1 ------------------------------------------------------------------ */ + static const unsigned int hspi1_pins[] = { + /* CLK, CS, RX, TX */ +- 63, 58, 64, 62, ++ RCAR_GP_PIN(1, 31), RCAR_GP_PIN(1, 26), RCAR_GP_PIN(2, 0), ++ RCAR_GP_PIN(1, 30), + }; + static const unsigned int hspi1_mux[] = { + HSPI_CLK1_MARK, HSPI_CS1_MARK, HSPI_RX1_MARK, HSPI_TX1_MARK, + }; + static const unsigned int hspi1_b_pins[] = { + /* CLK, CS, RX, TX */ +- 90, 91, 93, 92, ++ RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 29), ++ RCAR_GP_PIN(2, 28), + }; + static const unsigned int hspi1_b_mux[] = { + HSPI_CLK1_B_MARK, HSPI_CS1_B_MARK, HSPI_RX1_B_MARK, HSPI_TX1_B_MARK, + }; + static const unsigned int hspi1_c_pins[] = { + /* CLK, CS, RX, TX */ +- 141, 142, 144, 143, ++ RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 16), ++ RCAR_GP_PIN(4, 15), + }; + static const unsigned int hspi1_c_mux[] = { + HSPI_CLK1_C_MARK, HSPI_CS1_C_MARK, HSPI_RX1_C_MARK, HSPI_TX1_C_MARK, + }; + static const unsigned int hspi1_d_pins[] = { + /* CLK, CS, RX, TX */ +- 101, 102, 104, 103, ++ RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 8), ++ RCAR_GP_PIN(3, 7), + }; + static const unsigned int hspi1_d_mux[] = { + HSPI_CLK1_D_MARK, HSPI_CS1_D_MARK, HSPI_RX1_D_MARK, HSPI_TX1_D_MARK, +@@ -1662,14 +1684,16 @@ static const unsigned int hspi1_d_mux[] = { + /* - HSPI2 ------------------------------------------------------------------ */ + static const unsigned int hspi2_pins[] = { + /* CLK, CS, RX, TX */ +- 9, 10, 11, 14, ++ RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), ++ RCAR_GP_PIN(0, 14), + }; + static const unsigned int hspi2_mux[] = { + HSPI_CLK2_MARK, HSPI_CS2_MARK, HSPI_RX2_MARK, HSPI_TX2_MARK, + }; + static const unsigned int hspi2_b_pins[] = { + /* CLK, CS, RX, TX */ +- 7, 13, 8, 6, ++ RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 8), ++ RCAR_GP_PIN(0, 6), + }; + static const unsigned int hspi2_b_mux[] = { + HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK, +@@ -1677,56 +1701,56 @@ static const unsigned int hspi2_b_mux[] = { + /* - INTC ------------------------------------------------------------------- */ + static const unsigned int intc_irq0_pins[] = { + /* IRQ */ +- 78, ++ RCAR_GP_PIN(2, 14), + }; + static const unsigned int intc_irq0_mux[] = { + IRQ0_MARK, + }; + static const unsigned int intc_irq0_b_pins[] = { + /* IRQ */ +- 141, ++ RCAR_GP_PIN(4, 13), + }; + static const unsigned int intc_irq0_b_mux[] = { + IRQ0_B_MARK, + }; + static const unsigned int intc_irq1_pins[] = { + /* IRQ */ +- 79, ++ RCAR_GP_PIN(2, 15), + }; + static const unsigned int intc_irq1_mux[] = { + IRQ1_MARK, + }; + static const unsigned int intc_irq1_b_pins[] = { + /* IRQ */ +- 142, ++ RCAR_GP_PIN(4, 14), + }; + static const unsigned int intc_irq1_b_mux[] = { + IRQ1_B_MARK, + }; + static const unsigned int intc_irq2_pins[] = { + /* IRQ */ +- 88, ++ RCAR_GP_PIN(2, 24), + }; + static const unsigned int intc_irq2_mux[] = { + IRQ2_MARK, + }; + static const unsigned int intc_irq2_b_pins[] = { + /* IRQ */ +- 143, ++ RCAR_GP_PIN(4, 15), + }; + static const unsigned int intc_irq2_b_mux[] = { + IRQ2_B_MARK, + }; + static const unsigned int intc_irq3_pins[] = { + /* IRQ */ +- 89, ++ RCAR_GP_PIN(2, 25), + }; + static const unsigned int intc_irq3_mux[] = { + IRQ3_MARK, + }; + static const unsigned int intc_irq3_b_pins[] = { + /* IRQ */ +- 144, ++ RCAR_GP_PIN(4, 16), + }; + static const unsigned int intc_irq3_b_mux[] = { + IRQ3_B_MARK, +@@ -1734,56 +1758,56 @@ static const unsigned int intc_irq3_b_mux[] = { + /* - LSBC ------------------------------------------------------------------- */ + static const unsigned int lbsc_cs0_pins[] = { + /* CS */ +- 13, ++ RCAR_GP_PIN(0, 13), + }; + static const unsigned int lbsc_cs0_mux[] = { + CS0_MARK, + }; + static const unsigned int lbsc_cs1_pins[] = { + /* CS */ +- 14, ++ RCAR_GP_PIN(0, 14), + }; + static const unsigned int lbsc_cs1_mux[] = { + CS1_A26_MARK, + }; + static const unsigned int lbsc_ex_cs0_pins[] = { + /* CS */ +- 15, ++ RCAR_GP_PIN(0, 15), + }; + static const unsigned int lbsc_ex_cs0_mux[] = { + EX_CS0_MARK, + }; + static const unsigned int lbsc_ex_cs1_pins[] = { + /* CS */ +- 16, ++ RCAR_GP_PIN(0, 16), + }; + static const unsigned int lbsc_ex_cs1_mux[] = { + EX_CS1_MARK, + }; + static const unsigned int lbsc_ex_cs2_pins[] = { + /* CS */ +- 17, ++ RCAR_GP_PIN(0, 17), + }; + static const unsigned int lbsc_ex_cs2_mux[] = { + EX_CS2_MARK, + }; + static const unsigned int lbsc_ex_cs3_pins[] = { + /* CS */ +- 18, ++ RCAR_GP_PIN(0, 18), + }; + static const unsigned int lbsc_ex_cs3_mux[] = { + EX_CS3_MARK, + }; + static const unsigned int lbsc_ex_cs4_pins[] = { + /* CS */ +- 19, ++ RCAR_GP_PIN(0, 19), + }; + static const unsigned int lbsc_ex_cs4_mux[] = { + EX_CS4_MARK, + }; + static const unsigned int lbsc_ex_cs5_pins[] = { + /* CS */ +- 20, ++ RCAR_GP_PIN(0, 20), + }; + static const unsigned int lbsc_ex_cs5_mux[] = { + EX_CS5_MARK, +@@ -1791,21 +1815,24 @@ static const unsigned int lbsc_ex_cs5_mux[] = { + /* - MMCIF ------------------------------------------------------------------ */ + static const unsigned int mmc0_data1_pins[] = { + /* D[0] */ +- 19, ++ RCAR_GP_PIN(0, 19), + }; + static const unsigned int mmc0_data1_mux[] = { + MMC0_D0_MARK, + }; + static const unsigned int mmc0_data4_pins[] = { + /* D[0:3] */ +- 19, 20, 21, 2, ++ RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21), ++ RCAR_GP_PIN(0, 2), + }; + static const unsigned int mmc0_data4_mux[] = { + MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, + }; + static const unsigned int mmc0_data8_pins[] = { + /* D[0:7] */ +- 19, 20, 21, 2, 10, 11, 15, 16, ++ RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21), ++ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), ++ RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16), + }; + static const unsigned int mmc0_data8_mux[] = { + MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, +@@ -1813,28 +1840,31 @@ static const unsigned int mmc0_data8_mux[] = { + }; + static const unsigned int mmc0_ctrl_pins[] = { + /* CMD, CLK */ +- 18, 17, ++ RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17), + }; + static const unsigned int mmc0_ctrl_mux[] = { + MMC0_CMD_MARK, MMC0_CLK_MARK, + }; + static const unsigned int mmc1_data1_pins[] = { + /* D[0] */ +- 72, ++ RCAR_GP_PIN(2, 8), + }; + static const unsigned int mmc1_data1_mux[] = { + MMC1_D0_MARK, + }; + static const unsigned int mmc1_data4_pins[] = { + /* D[0:3] */ +- 72, 73, 74, 75, ++ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), ++ RCAR_GP_PIN(2, 11), + }; + static const unsigned int mmc1_data4_mux[] = { + MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, + }; + static const unsigned int mmc1_data8_pins[] = { + /* D[0:7] */ +- 72, 73, 74, 75, 76, 77, 80, 81, ++ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), ++ RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), ++ RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), + }; + static const unsigned int mmc1_data8_mux[] = { + MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, +@@ -1842,7 +1872,7 @@ static const unsigned int mmc1_data8_mux[] = { + }; + static const unsigned int mmc1_ctrl_pins[] = { + /* CMD, CLK */ +- 68, 65, ++ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 1), + }; + static const unsigned int mmc1_ctrl_mux[] = { + MMC1_CMD_MARK, MMC1_CLK_MARK, +@@ -1850,84 +1880,84 @@ static const unsigned int mmc1_ctrl_mux[] = { + /* - SCIF0 ------------------------------------------------------------------ */ + static const unsigned int scif0_data_pins[] = { + /* RXD, TXD */ +- 153, 152, ++ RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), + }; + static const unsigned int scif0_data_mux[] = { + RX0_MARK, TX0_MARK, + }; + static const unsigned int scif0_clk_pins[] = { + /* SCK */ +- 156, ++ RCAR_GP_PIN(4, 28), + }; + static const unsigned int scif0_clk_mux[] = { + SCK0_MARK, + }; + static const unsigned int scif0_ctrl_pins[] = { + /* RTS, CTS */ +- 151, 150, ++ RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), + }; + static const unsigned int scif0_ctrl_mux[] = { + RTS0_TANS_MARK, CTS0_MARK, + }; + static const unsigned int scif0_data_b_pins[] = { + /* RXD, TXD */ +- 20, 19, ++ RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), + }; + static const unsigned int scif0_data_b_mux[] = { + RX0_B_MARK, TX0_B_MARK, + }; + static const unsigned int scif0_clk_b_pins[] = { + /* SCK */ +- 33, ++ RCAR_GP_PIN(1, 1), + }; + static const unsigned int scif0_clk_b_mux[] = { + SCK0_B_MARK, + }; + static const unsigned int scif0_ctrl_b_pins[] = { + /* RTS, CTS */ +- 18, 11, ++ RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11), + }; + static const unsigned int scif0_ctrl_b_mux[] = { + RTS0_B_TANS_B_MARK, CTS0_B_MARK, + }; + static const unsigned int scif0_data_c_pins[] = { + /* RXD, TXD */ +- 146, 147, ++ RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19), + }; + static const unsigned int scif0_data_c_mux[] = { + RX0_C_MARK, TX0_C_MARK, + }; + static const unsigned int scif0_clk_c_pins[] = { + /* SCK */ +- 145, ++ RCAR_GP_PIN(4, 17), + }; + static const unsigned int scif0_clk_c_mux[] = { + SCK0_C_MARK, + }; + static const unsigned int scif0_ctrl_c_pins[] = { + /* RTS, CTS */ +- 149, 148, ++ RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), + }; + static const unsigned int scif0_ctrl_c_mux[] = { + RTS0_C_TANS_C_MARK, CTS0_C_MARK, + }; + static const unsigned int scif0_data_d_pins[] = { + /* RXD, TXD */ +- 43, 42, ++ RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), + }; + static const unsigned int scif0_data_d_mux[] = { + RX0_D_MARK, TX0_D_MARK, + }; + static const unsigned int scif0_clk_d_pins[] = { + /* SCK */ +- 50, ++ RCAR_GP_PIN(1, 18), + }; + static const unsigned int scif0_clk_d_mux[] = { + SCK0_D_MARK, + }; + static const unsigned int scif0_ctrl_d_pins[] = { + /* RTS, CTS */ +- 51, 35, ++ RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 3), + }; + static const unsigned int scif0_ctrl_d_mux[] = { + RTS0_D_TANS_D_MARK, CTS0_D_MARK, +@@ -1935,63 +1965,63 @@ static const unsigned int scif0_ctrl_d_mux[] = { + /* - SCIF1 ------------------------------------------------------------------ */ + static const unsigned int scif1_data_pins[] = { + /* RXD, TXD */ +- 149, 148, ++ RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), + }; + static const unsigned int scif1_data_mux[] = { + RX1_MARK, TX1_MARK, + }; + static const unsigned int scif1_clk_pins[] = { + /* SCK */ +- 145, ++ RCAR_GP_PIN(4, 17), + }; + static const unsigned int scif1_clk_mux[] = { + SCK1_MARK, + }; + static const unsigned int scif1_ctrl_pins[] = { + /* RTS, CTS */ +- 147, 146, ++ RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18), + }; + static const unsigned int scif1_ctrl_mux[] = { + RTS1_TANS_MARK, CTS1_MARK, + }; + static const unsigned int scif1_data_b_pins[] = { + /* RXD, TXD */ +- 117, 114, ++ RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 18), + }; + static const unsigned int scif1_data_b_mux[] = { + RX1_B_MARK, TX1_B_MARK, + }; + static const unsigned int scif1_clk_b_pins[] = { + /* SCK */ +- 113, ++ RCAR_GP_PIN(3, 17), + }; + static const unsigned int scif1_clk_b_mux[] = { + SCK1_B_MARK, + }; + static const unsigned int scif1_ctrl_b_pins[] = { + /* RTS, CTS */ +- 115, 116, ++ RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), + }; + static const unsigned int scif1_ctrl_b_mux[] = { + RTS1_B_TANS_B_MARK, CTS1_B_MARK, + }; + static const unsigned int scif1_data_c_pins[] = { + /* RXD, TXD */ +- 67, 66, ++ RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2), + }; + static const unsigned int scif1_data_c_mux[] = { + RX1_C_MARK, TX1_C_MARK, + }; + static const unsigned int scif1_clk_c_pins[] = { + /* SCK */ +- 86, ++ RCAR_GP_PIN(2, 22), + }; + static const unsigned int scif1_clk_c_mux[] = { + SCK1_C_MARK, + }; + static const unsigned int scif1_ctrl_c_pins[] = { + /* RTS, CTS */ +- 69, 68, ++ RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), + }; + static const unsigned int scif1_ctrl_c_mux[] = { + RTS1_C_TANS_C_MARK, CTS1_C_MARK, +@@ -1999,63 +2029,63 @@ static const unsigned int scif1_ctrl_c_mux[] = { + /* - SCIF2 ------------------------------------------------------------------ */ + static const unsigned int scif2_data_pins[] = { + /* RXD, TXD */ +- 106, 105, ++ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 9), + }; + static const unsigned int scif2_data_mux[] = { + RX2_MARK, TX2_MARK, + }; + static const unsigned int scif2_clk_pins[] = { + /* SCK */ +- 107, ++ RCAR_GP_PIN(3, 11), + }; + static const unsigned int scif2_clk_mux[] = { + SCK2_MARK, + }; + static const unsigned int scif2_data_b_pins[] = { + /* RXD, TXD */ +- 120, 119, ++ RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 23), + }; + static const unsigned int scif2_data_b_mux[] = { + RX2_B_MARK, TX2_B_MARK, + }; + static const unsigned int scif2_clk_b_pins[] = { + /* SCK */ +- 118, ++ RCAR_GP_PIN(3, 22), + }; + static const unsigned int scif2_clk_b_mux[] = { + SCK2_B_MARK, + }; + static const unsigned int scif2_data_c_pins[] = { + /* RXD, TXD */ +- 33, 31, ++ RCAR_GP_PIN(1, 1), RCAR_GP_PIN(0, 31), + }; + static const unsigned int scif2_data_c_mux[] = { + RX2_C_MARK, TX2_C_MARK, + }; + static const unsigned int scif2_clk_c_pins[] = { + /* SCK */ +- 32, ++ RCAR_GP_PIN(1, 0), + }; + static const unsigned int scif2_clk_c_mux[] = { + SCK2_C_MARK, + }; + static const unsigned int scif2_data_d_pins[] = { + /* RXD, TXD */ +- 64, 62, ++ RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30), + }; + static const unsigned int scif2_data_d_mux[] = { + RX2_D_MARK, TX2_D_MARK, + }; + static const unsigned int scif2_clk_d_pins[] = { + /* SCK */ +- 63, ++ RCAR_GP_PIN(1, 31), + }; + static const unsigned int scif2_clk_d_mux[] = { + SCK2_D_MARK, + }; + static const unsigned int scif2_data_e_pins[] = { + /* RXD, TXD */ +- 20, 19, ++ RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), + }; + static const unsigned int scif2_data_e_mux[] = { + RX2_E_MARK, TX2_E_MARK, +@@ -2063,14 +2093,14 @@ static const unsigned int scif2_data_e_mux[] = { + /* - SCIF3 ------------------------------------------------------------------ */ + static const unsigned int scif3_data_pins[] = { + /* RXD, TXD */ +- 137, 136, ++ RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8), + }; + static const unsigned int scif3_data_mux[] = { + RX3_IRDA_RX_MARK, TX3_IRDA_TX_MARK, + }; + static const unsigned int scif3_clk_pins[] = { + /* SCK */ +- 135, ++ RCAR_GP_PIN(4, 7), + }; + static const unsigned int scif3_clk_mux[] = { + SCK3_MARK, +@@ -2078,35 +2108,35 @@ static const unsigned int scif3_clk_mux[] = { + + static const unsigned int scif3_data_b_pins[] = { + /* RXD, TXD */ +- 64, 62, ++ RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30), + }; + static const unsigned int scif3_data_b_mux[] = { + RX3_B_IRDA_RX_B_MARK, TX3_B_IRDA_TX_B_MARK, + }; + static const unsigned int scif3_data_c_pins[] = { + /* RXD, TXD */ +- 15, 12, ++ RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 12), + }; + static const unsigned int scif3_data_c_mux[] = { + RX3_C_IRDA_RX_C_MARK, TX3C_IRDA_TX_C_MARK, + }; + static const unsigned int scif3_data_d_pins[] = { + /* RXD, TXD */ +- 30, 29, ++ RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 29), + }; + static const unsigned int scif3_data_d_mux[] = { + RX3_D_IRDA_RX_D_MARK, TX3_D_IRDA_TX_D_MARK, + }; + static const unsigned int scif3_data_e_pins[] = { + /* RXD, TXD */ +- 35, 34, ++ RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), + }; + static const unsigned int scif3_data_e_mux[] = { + RX3_E_IRDA_RX_E_MARK, TX3_E_IRDA_TX_E_MARK, + }; + static const unsigned int scif3_clk_e_pins[] = { + /* SCK */ +- 42, ++ RCAR_GP_PIN(1, 10), + }; + static const unsigned int scif3_clk_e_mux[] = { + SCK3_E_MARK, +@@ -2114,42 +2144,42 @@ static const unsigned int scif3_clk_e_mux[] = { + /* - SCIF4 ------------------------------------------------------------------ */ + static const unsigned int scif4_data_pins[] = { + /* RXD, TXD */ +- 123, 122, ++ RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 26), + }; + static const unsigned int scif4_data_mux[] = { + RX4_MARK, TX4_MARK, + }; + static const unsigned int scif4_clk_pins[] = { + /* SCK */ +- 121, ++ RCAR_GP_PIN(3, 25), + }; + static const unsigned int scif4_clk_mux[] = { + SCK4_MARK, + }; + static const unsigned int scif4_data_b_pins[] = { + /* RXD, TXD */ +- 111, 110, ++ RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), + }; + static const unsigned int scif4_data_b_mux[] = { + RX4_B_MARK, TX4_B_MARK, + }; + static const unsigned int scif4_clk_b_pins[] = { + /* SCK */ +- 112, ++ RCAR_GP_PIN(3, 16), + }; + static const unsigned int scif4_clk_b_mux[] = { + SCK4_B_MARK, + }; + static const unsigned int scif4_data_c_pins[] = { + /* RXD, TXD */ +- 22, 21, ++ RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21), + }; + static const unsigned int scif4_data_c_mux[] = { + RX4_C_MARK, TX4_C_MARK, + }; + static const unsigned int scif4_data_d_pins[] = { + /* RXD, TXD */ +- 69, 68, ++ RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), + }; + static const unsigned int scif4_data_d_mux[] = { + RX4_D_MARK, TX4_D_MARK, +@@ -2157,56 +2187,56 @@ static const unsigned int scif4_data_d_mux[] = { + /* - SCIF5 ------------------------------------------------------------------ */ + static const unsigned int scif5_data_pins[] = { + /* RXD, TXD */ +- 51, 50, ++ RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), + }; + static const unsigned int scif5_data_mux[] = { + RX5_MARK, TX5_MARK, + }; + static const unsigned int scif5_clk_pins[] = { + /* SCK */ +- 43, ++ RCAR_GP_PIN(1, 11), + }; + static const unsigned int scif5_clk_mux[] = { + SCK5_MARK, + }; + static const unsigned int scif5_data_b_pins[] = { + /* RXD, TXD */ +- 18, 11, ++ RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11), + }; + static const unsigned int scif5_data_b_mux[] = { + RX5_B_MARK, TX5_B_MARK, + }; + static const unsigned int scif5_clk_b_pins[] = { + /* SCK */ +- 19, ++ RCAR_GP_PIN(0, 19), + }; + static const unsigned int scif5_clk_b_mux[] = { + SCK5_B_MARK, + }; + static const unsigned int scif5_data_c_pins[] = { + /* RXD, TXD */ +- 24, 23, ++ RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23), + }; + static const unsigned int scif5_data_c_mux[] = { + RX5_C_MARK, TX5_C_MARK, + }; + static const unsigned int scif5_clk_c_pins[] = { + /* SCK */ +- 28, ++ RCAR_GP_PIN(0, 28), + }; + static const unsigned int scif5_clk_c_mux[] = { + SCK5_C_MARK, + }; + static const unsigned int scif5_data_d_pins[] = { + /* RXD, TXD */ +- 8, 6, ++ RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), + }; + static const unsigned int scif5_data_d_mux[] = { + RX5_D_MARK, TX5_D_MARK, + }; + static const unsigned int scif5_clk_d_pins[] = { + /* SCK */ +- 7, ++ RCAR_GP_PIN(0, 7), + }; + static const unsigned int scif5_clk_d_mux[] = { + SCK5_D_MARK, +@@ -2214,35 +2244,36 @@ static const unsigned int scif5_clk_d_mux[] = { + /* - SDHI0 ------------------------------------------------------------------ */ + static const unsigned int sdhi0_data1_pins[] = { + /* D0 */ +- 117, ++ RCAR_GP_PIN(3, 21), + }; + static const unsigned int sdhi0_data1_mux[] = { + SD0_DAT0_MARK, + }; + static const unsigned int sdhi0_data4_pins[] = { + /* D[0:3] */ +- 117, 118, 119, 120, ++ RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), ++ RCAR_GP_PIN(3, 24), + }; + static const unsigned int sdhi0_data4_mux[] = { + SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, + }; + static const unsigned int sdhi0_ctrl_pins[] = { + /* CMD, CLK */ +- 114, 113, ++ RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 17), + }; + static const unsigned int sdhi0_ctrl_mux[] = { + SD0_CMD_MARK, SD0_CLK_MARK, + }; + static const unsigned int sdhi0_cd_pins[] = { + /* CD */ +- 115, ++ RCAR_GP_PIN(3, 19), + }; + static const unsigned int sdhi0_cd_mux[] = { + SD0_CD_MARK, + }; + static const unsigned int sdhi0_wp_pins[] = { + /* WP */ +- 116, ++ RCAR_GP_PIN(3, 20), + }; + static const unsigned int sdhi0_wp_mux[] = { + SD0_WP_MARK, +@@ -2250,35 +2281,36 @@ static const unsigned int sdhi0_wp_mux[] = { + /* - SDHI1 ------------------------------------------------------------------ */ + static const unsigned int sdhi1_data1_pins[] = { + /* D0 */ +- 19, ++ RCAR_GP_PIN(0, 19), + }; + static const unsigned int sdhi1_data1_mux[] = { + SD1_DAT0_MARK, + }; + static const unsigned int sdhi1_data4_pins[] = { + /* D[0:3] */ +- 19, 20, 21, 2, ++ RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21), ++ RCAR_GP_PIN(0, 2), + }; + static const unsigned int sdhi1_data4_mux[] = { + SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, + }; + static const unsigned int sdhi1_ctrl_pins[] = { + /* CMD, CLK */ +- 18, 17, ++ RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17), + }; + static const unsigned int sdhi1_ctrl_mux[] = { + SD1_CMD_MARK, SD1_CLK_MARK, + }; + static const unsigned int sdhi1_cd_pins[] = { + /* CD */ +- 10, ++ RCAR_GP_PIN(0, 10), + }; + static const unsigned int sdhi1_cd_mux[] = { + SD1_CD_MARK, + }; + static const unsigned int sdhi1_wp_pins[] = { + /* WP */ +- 11, ++ RCAR_GP_PIN(0, 11), + }; + static const unsigned int sdhi1_wp_mux[] = { + SD1_WP_MARK, +@@ -2286,35 +2318,36 @@ static const unsigned int sdhi1_wp_mux[] = { + /* - SDHI2 ------------------------------------------------------------------ */ + static const unsigned int sdhi2_data1_pins[] = { + /* D0 */ +- 97, ++ RCAR_GP_PIN(3, 1), + }; + static const unsigned int sdhi2_data1_mux[] = { + SD2_DAT0_MARK, + }; + static const unsigned int sdhi2_data4_pins[] = { + /* D[0:3] */ +- 97, 98, 99, 100, ++ RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), ++ RCAR_GP_PIN(3, 4), + }; + static const unsigned int sdhi2_data4_mux[] = { + SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, + }; + static const unsigned int sdhi2_ctrl_pins[] = { + /* CMD, CLK */ +- 102, 101, ++ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5), + }; + static const unsigned int sdhi2_ctrl_mux[] = { + SD2_CMD_MARK, SD2_CLK_MARK, + }; + static const unsigned int sdhi2_cd_pins[] = { + /* CD */ +- 103, ++ RCAR_GP_PIN(3, 7), + }; + static const unsigned int sdhi2_cd_mux[] = { + SD2_CD_MARK, + }; + static const unsigned int sdhi2_wp_pins[] = { + /* WP */ +- 104, ++ RCAR_GP_PIN(3, 8), + }; + static const unsigned int sdhi2_wp_mux[] = { + SD2_WP_MARK, +@@ -2322,35 +2355,36 @@ static const unsigned int sdhi2_wp_mux[] = { + /* - SDHI3 ------------------------------------------------------------------ */ + static const unsigned int sdhi3_data1_pins[] = { + /* D0 */ +- 50, ++ RCAR_GP_PIN(1, 18), + }; + static const unsigned int sdhi3_data1_mux[] = { + SD3_DAT0_MARK, + }; + static const unsigned int sdhi3_data4_pins[] = { + /* D[0:3] */ +- 50, 51, 52, 53, ++ RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 20), ++ RCAR_GP_PIN(1, 21), + }; + static const unsigned int sdhi3_data4_mux[] = { + SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, + }; + static const unsigned int sdhi3_ctrl_pins[] = { + /* CMD, CLK */ +- 35, 34, ++ RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), + }; + static const unsigned int sdhi3_ctrl_mux[] = { + SD3_CMD_MARK, SD3_CLK_MARK, + }; + static const unsigned int sdhi3_cd_pins[] = { + /* CD */ +- 62, ++ RCAR_GP_PIN(1, 30), + }; + static const unsigned int sdhi3_cd_mux[] = { + SD3_CD_MARK, + }; + static const unsigned int sdhi3_wp_pins[] = { + /* WP */ +- 64, ++ RCAR_GP_PIN(2, 0), + }; + static const unsigned int sdhi3_wp_mux[] = { + SD3_WP_MARK, +@@ -2358,14 +2392,14 @@ static const unsigned int sdhi3_wp_mux[] = { + /* - USB0 ------------------------------------------------------------------- */ + static const unsigned int usb0_pins[] = { + /* PENC */ +- 154, ++ RCAR_GP_PIN(4, 26), + }; + static const unsigned int usb0_mux[] = { + USB_PENC0_MARK, + }; + static const unsigned int usb0_ovc_pins[] = { + /* USB_OVC */ +- 150 ++ RCAR_GP_PIN(4, 22), + }; + static const unsigned int usb0_ovc_mux[] = { + USB_OVC0_MARK, +@@ -2373,14 +2407,14 @@ static const unsigned int usb0_ovc_mux[] = { + /* - USB1 ------------------------------------------------------------------- */ + static const unsigned int usb1_pins[] = { + /* PENC */ +- 155, ++ RCAR_GP_PIN(4, 27), + }; + static const unsigned int usb1_mux[] = { + USB_PENC1_MARK, + }; + static const unsigned int usb1_ovc_pins[] = { + /* USB_OVC */ +- 152, ++ RCAR_GP_PIN(4, 24), + }; + static const unsigned int usb1_ovc_mux[] = { + USB_OVC1_MARK, +@@ -2388,14 +2422,14 @@ static const unsigned int usb1_ovc_mux[] = { + /* - USB2 ------------------------------------------------------------------- */ + static const unsigned int usb2_pins[] = { + /* PENC */ +- 156, ++ RCAR_GP_PIN(4, 28), + }; + static const unsigned int usb2_mux[] = { + USB_PENC2_MARK, + }; + static const unsigned int usb2_ovc_pins[] = { + /* USB_OVC */ +- 125, ++ RCAR_GP_PIN(3, 29), + }; + static const unsigned int usb2_ovc_mux[] = { + USB_OVC2_MARK, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0094-sh-pfc-r8a7779-use-RCAR_GP_PIN-on-_GP_GPIO-macro.patch b/patches.renesas/0094-sh-pfc-r8a7779-use-RCAR_GP_PIN-on-_GP_GPIO-macro.patch new file mode 100644 index 00000000000..d1e80db34d0 --- /dev/null +++ b/patches.renesas/0094-sh-pfc-r8a7779-use-RCAR_GP_PIN-on-_GP_GPIO-macro.patch @@ -0,0 +1,30 @@ +From d61e104429792992114e0c76f45e8d1fc54e2ef0 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 9 Apr 2013 04:54:18 +0000 +Subject: sh-pfc: r8a7779: use RCAR_GP_PIN() on _GP_GPIO() macro + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit de9edf7d2c816c80337a79fc9d0cff8f4ceb42c0) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +index e1491a50..1590d6ce 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +@@ -80,7 +80,7 @@ + #define _GP_PORT_ALL(bank, pin, name, sfx) name##_##sfx + + #define _GP_GPIO(bank, pin, _name, sfx) \ +- [(bank * 32) + pin] = { \ ++ [RCAR_GP_PIN(bank, pin)] = { \ + .name = __stringify(_name), \ + .enum_id = _name##_DATA, \ + } +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0095-sh-pfc-r8a7779-add-VIN-pin-groups.patch b/patches.renesas/0095-sh-pfc-r8a7779-add-VIN-pin-groups.patch new file mode 100644 index 00000000000..35d39e0a28a --- /dev/null +++ b/patches.renesas/0095-sh-pfc-r8a7779-add-VIN-pin-groups.patch @@ -0,0 +1,211 @@ +From 2476790ccfb5824df1b9f63bce8a5ca41d9d37fb Mon Sep 17 00:00:00 2001 +From: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Date: Tue, 16 Apr 2013 22:17:28 +0000 +Subject: sh-pfc: r8a7779: add VIN pin groups + +Add VIN DATA[0:7]/CLK/HSYNC/VSYNC pin groups to R8A7779 PFC driver. + +Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Acked-by: Linus Walleij <linus.walleij@linaro.org> +[horms+renesas@verge.net.au: trivial rebase on top of + "sh-pfc: r8a7779: Don't group USB OVC and PENC pins"] +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit 54ee73c6f52c506fce83328ab902f375b9af472f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 147 ++++++++++++++++++++++++++++++++++- + 1 file changed, 146 insertions(+), 1 deletion(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +index 1590d6ce..37ba5719 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +@@ -1,8 +1,9 @@ + /* + * r8a7779 processor support - PFC hardware block + * +- * Copyright (C) 2011 Renesas Solutions Corp. ++ * Copyright (C) 2011, 2013 Renesas Solutions Corp. + * Copyright (C) 2011 Magnus Damm ++ * Copyright (C) 2013 Cogent Embedded, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by +@@ -2434,6 +2435,110 @@ static const unsigned int usb2_ovc_pins[] = { + static const unsigned int usb2_ovc_mux[] = { + USB_OVC2_MARK, + }; ++/* - VIN0 ------------------------------------------------------------------- */ ++static const unsigned int vin0_data8_pins[] = { ++ /* D[0:7] */ ++ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), ++ RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), ++ RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), ++}; ++static const unsigned int vin0_data8_mux[] = { ++ VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, VI0_DATA2_VI0_B2_MARK, ++ VI0_DATA3_VI0_B3_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, ++ VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, ++}; ++static const unsigned int vin0_clk_pins[] = { ++ /* CLK */ ++ RCAR_GP_PIN(2, 1), ++}; ++static const unsigned int vin0_clk_mux[] = { ++ VI0_CLK_MARK, ++}; ++static const unsigned int vin0_sync_pins[] = { ++ /* HSYNC, VSYNC */ ++ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), ++}; ++static const unsigned int vin0_sync_mux[] = { ++ VI0_HSYNC_MARK, VI0_VSYNC_MARK, ++}; ++/* - VIN1 ------------------------------------------------------------------- */ ++static const unsigned int vin1_data8_pins[] = { ++ /* D[0:7] */ ++ RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), ++ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), ++ RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), ++}; ++static const unsigned int vin1_data8_mux[] = { ++ VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, VI1_DATA2_VI1_B2_MARK, ++ VI1_DATA3_VI1_B3_MARK, VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, ++ VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK, ++}; ++static const unsigned int vin1_clk_pins[] = { ++ /* CLK */ ++ RCAR_GP_PIN(2, 30), ++}; ++static const unsigned int vin1_clk_mux[] = { ++ VI1_CLK_MARK, ++}; ++static const unsigned int vin1_sync_pins[] = { ++ /* HSYNC, VSYNC */ ++ RCAR_GP_PIN(2, 31), RCAR_GP_PIN(3, 0), ++}; ++static const unsigned int vin1_sync_mux[] = { ++ VI1_HSYNC_MARK, VI1_VSYNC_MARK, ++}; ++/* - VIN2 ------------------------------------------------------------------- */ ++static const unsigned int vin2_data8_pins[] = { ++ /* D[0:7] */ ++ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), ++ RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), ++ RCAR_GP_PIN(1, 31), RCAR_GP_PIN(2, 0), ++}; ++static const unsigned int vin2_data8_mux[] = { ++ VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK, VI2_DATA2_VI2_B2_MARK, ++ VI2_DATA3_VI2_B3_MARK, VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK, ++ VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK, ++}; ++static const unsigned int vin2_clk_pins[] = { ++ /* CLK */ ++ RCAR_GP_PIN(1, 30), ++}; ++static const unsigned int vin2_clk_mux[] = { ++ VI2_CLK_MARK, ++}; ++static const unsigned int vin2_sync_pins[] = { ++ /* HSYNC, VSYNC */ ++ RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29), ++}; ++static const unsigned int vin2_sync_mux[] = { ++ VI2_HSYNC_MARK, VI2_VSYNC_MARK, ++}; ++/* - VIN3 ------------------------------------------------------------------- */ ++static const unsigned int vin3_data8_pins[] = { ++ /* D[0:7] */ ++ RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), ++ RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), ++ RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), ++}; ++static const unsigned int vin3_data8_mux[] = { ++ VI3_DATA0_MARK, VI3_DATA1_MARK, VI3_DATA2_MARK, ++ VI3_DATA3_MARK, VI3_DATA4_MARK, VI3_DATA5_MARK, ++ VI3_DATA6_MARK, VI3_DATA7_MARK, ++}; ++static const unsigned int vin3_clk_pins[] = { ++ /* CLK */ ++ RCAR_GP_PIN(2, 31), ++}; ++static const unsigned int vin3_clk_mux[] = { ++ VI3_CLK_MARK, ++}; ++static const unsigned int vin3_sync_pins[] = { ++ /* HSYNC, VSYNC */ ++ RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29), ++}; ++static const unsigned int vin3_sync_mux[] = { ++ VI3_HSYNC_MARK, VI3_VSYNC_MARK, ++}; + + static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(du0_rgb666), +@@ -2561,6 +2666,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(usb1_ovc), + SH_PFC_PIN_GROUP(usb2), + SH_PFC_PIN_GROUP(usb2_ovc), ++ SH_PFC_PIN_GROUP(vin0_data8), ++ SH_PFC_PIN_GROUP(vin0_clk), ++ SH_PFC_PIN_GROUP(vin0_sync), ++ SH_PFC_PIN_GROUP(vin1_data8), ++ SH_PFC_PIN_GROUP(vin1_clk), ++ SH_PFC_PIN_GROUP(vin1_sync), ++ SH_PFC_PIN_GROUP(vin2_data8), ++ SH_PFC_PIN_GROUP(vin2_clk), ++ SH_PFC_PIN_GROUP(vin2_sync), ++ SH_PFC_PIN_GROUP(vin3_data8), ++ SH_PFC_PIN_GROUP(vin3_clk), ++ SH_PFC_PIN_GROUP(vin3_sync), + }; + + static const char * const du0_groups[] = { +@@ -2754,6 +2871,30 @@ static const char * const usb2_groups[] = { + "usb2_ovc", + }; + ++static const char * const vin0_groups[] = { ++ "vin0_data8", ++ "vin0_clk", ++ "vin0_sync", ++}; ++ ++static const char * const vin1_groups[] = { ++ "vin1_data8", ++ "vin1_clk", ++ "vin1_sync", ++}; ++ ++static const char * const vin2_groups[] = { ++ "vin2_data8", ++ "vin2_clk", ++ "vin2_sync", ++}; ++ ++static const char * const vin3_groups[] = { ++ "vin3_data8", ++ "vin3_clk", ++ "vin3_sync", ++}; ++ + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(du0), + SH_PFC_FUNCTION(du1), +@@ -2777,6 +2918,10 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(usb0), + SH_PFC_FUNCTION(usb1), + SH_PFC_FUNCTION(usb2), ++ SH_PFC_FUNCTION(vin0), ++ SH_PFC_FUNCTION(vin1), ++ SH_PFC_FUNCTION(vin2), ++ SH_PFC_FUNCTION(vin3), + }; + + static const struct pinmux_cfg_reg pinmux_config_regs[] = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0096-sh-pfc-r8a7778-add-common-PFC-macro-helper.patch b/patches.renesas/0096-sh-pfc-r8a7778-add-common-PFC-macro-helper.patch new file mode 100644 index 00000000000..5d84a28e483 --- /dev/null +++ b/patches.renesas/0096-sh-pfc-r8a7778-add-common-PFC-macro-helper.patch @@ -0,0 +1,60 @@ +From 3d6fb0fe8439bfed9d5e1c9692e17b84ee225b0e Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Thu, 18 Apr 2013 20:07:34 -0700 +Subject: sh-pfc: r8a7778: add common PFC macro helper + +pfc-r8a7778 will have many devices pfc support in the future, +and current pfc-r8a7778 is using pin/mux definition macro for SCIF. +The device definition style using macro is readable code IMO, +but creating new macro for each devices is not good sense. +This patch adds common SH_PFC_xx() macro for each new feature devices + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit a10cd30ed6c786fc4756cb1393fea63331e3e315) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 26 ++++++++++++++++++-------- + 1 file changed, 18 insertions(+), 8 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +index ddbd27b7..139f9dde 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +@@ -1303,15 +1303,25 @@ static struct sh_pfc_pin pinmux_pins[] = { + */ + #define PIN_NUMBER(row, col) (1000+((row)-1)*25+(col)-1) + +-/* - SCIF macro ------------------------------------------------------------- */ +-#define SCIF_PFC_PIN(name, args...) \ ++/* - macro */ ++#define SH_PFC_PINS(name, args...) \ + static const unsigned int name ##_pins[] = { args } +-#define SCIF_PFC_DAT(name, tx, rx) \ +- static const unsigned int name ##_mux[] = { tx##_MARK, rx##_MARK, } +-#define SCIF_PFC_CTR(name, cts, rts) \ +- static const unsigned int name ##_mux[] = { cts##_MARK, rts##_MARK, } +-#define SCIF_PFC_CLK(name, sck) \ +- static const unsigned int name ##_mux[] = { sck##_MARK, } ++#define SH_PFC_MUX1(name, arg1) \ ++ static const unsigned int name ##_mux[] = { arg1##_MARK } ++#define SH_PFC_MUX2(name, arg1, arg2) \ ++ static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, } ++#define SH_PFC_MUX3(name, arg1, arg2, arg3) \ ++ static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, \ ++ arg3##_MARK } ++#define SH_PFC_MUX4(name, arg1, arg2, arg3, arg4) \ ++ static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, \ ++ arg3##_MARK, arg4##_MARK } ++ ++/* - SCIF macro ------------------------------------------------------------- */ ++#define SCIF_PFC_PIN(name, args...) SH_PFC_PINS(name, args) ++#define SCIF_PFC_DAT(name, tx, rx) SH_PFC_MUX2(name, tx, rx) ++#define SCIF_PFC_CTR(name, cts, rts) SH_PFC_MUX2(name, cts, rts) ++#define SCIF_PFC_CLK(name, sck) SH_PFC_MUX1(name, sck) + + /* - HSCIF0 ----------------------------------------------------------------- */ + SCIF_PFC_PIN(hscif0_data_a, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18)); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0097-sh-pfc-r8a7778-add-SDHI-support.patch b/patches.renesas/0097-sh-pfc-r8a7778-add-SDHI-support.patch new file mode 100644 index 00000000000..6b90caaf60b --- /dev/null +++ b/patches.renesas/0097-sh-pfc-r8a7778-add-SDHI-support.patch @@ -0,0 +1,189 @@ +From 524fba2c4ee5dde087e35759ea8ebc8dcdd954c8 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Thu, 18 Apr 2013 20:08:23 -0700 +Subject: sh-pfc: r8a7778: add SDHI support + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 564617d2f92473031d035deb273da5374e62d0f0) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 141 +++++++++++++++++++++++++++++++++++ + 1 file changed, 141 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +index 139f9dde..b1925cc1 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +@@ -1427,6 +1427,84 @@ SCIF_PFC_DAT(scif5_data_a, TX5_A, RX5_A); + SCIF_PFC_PIN(scif5_data_b, RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14)); + SCIF_PFC_DAT(scif5_data_b, TX5_B, RX5_B); + ++/* - SDHI macro ------------------------------------------------------------- */ ++#define SDHI_PFC_PINS(name, args...) SH_PFC_PINS(name, args) ++#define SDHI_PFC_DAT1(name, d0) SH_PFC_MUX1(name, d0) ++#define SDHI_PFC_DAT4(name, d0, d1, d2, d3) SH_PFC_MUX4(name, d0, d1, d2, d3) ++#define SDHI_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd) ++#define SDHI_PFC_CDPN(name, cd) SH_PFC_MUX1(name, cd) ++#define SDHI_PFC_WPPN(name, wp) SH_PFC_MUX1(name, wp) ++ ++/* - SDHI0 ------------------------------------------------------------------ */ ++SDHI_PFC_PINS(sdhi0_cd, RCAR_GP_PIN(3, 17)); ++SDHI_PFC_CDPN(sdhi0_cd, SD0_CD); ++SDHI_PFC_PINS(sdhi0_ctrl, RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12)); ++SDHI_PFC_CTRL(sdhi0_ctrl, SD0_CLK, SD0_CMD); ++SDHI_PFC_PINS(sdhi0_data1, RCAR_GP_PIN(3, 13)); ++SDHI_PFC_DAT1(sdhi0_data1, SD0_DAT0); ++SDHI_PFC_PINS(sdhi0_data4, RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), ++ RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16)); ++SDHI_PFC_DAT4(sdhi0_data4, SD0_DAT0, SD0_DAT1, ++ SD0_DAT2, SD0_DAT3); ++SDHI_PFC_PINS(sdhi0_wp, RCAR_GP_PIN(3, 18)); ++SDHI_PFC_WPPN(sdhi0_wp, SD0_WP); ++ ++/* - SDHI1 ------------------------------------------------------------------ */ ++SDHI_PFC_PINS(sdhi1_a_cd, RCAR_GP_PIN(0, 30)); ++SDHI_PFC_CDPN(sdhi1_a_cd, SD1_CD_A); ++SDHI_PFC_PINS(sdhi1_a_ctrl, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6)); ++SDHI_PFC_CTRL(sdhi1_a_ctrl, SD1_CLK_A, SD1_CMD_A); ++SDHI_PFC_PINS(sdhi1_a_data1, RCAR_GP_PIN(1, 7)); ++SDHI_PFC_DAT1(sdhi1_a_data1, SD1_DAT0_A); ++SDHI_PFC_PINS(sdhi1_a_data4, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), ++ RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6)); ++SDHI_PFC_DAT4(sdhi1_a_data4, SD1_DAT0_A, SD1_DAT1_A, ++ SD1_DAT2_A, SD1_DAT3_A); ++SDHI_PFC_PINS(sdhi1_a_wp, RCAR_GP_PIN(0, 31)); ++SDHI_PFC_WPPN(sdhi1_a_wp, SD1_WP_A); ++ ++SDHI_PFC_PINS(sdhi1_b_cd, RCAR_GP_PIN(2, 24)); ++SDHI_PFC_CDPN(sdhi1_b_cd, SD1_CD_B); ++SDHI_PFC_PINS(sdhi1_b_ctrl, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16)); ++SDHI_PFC_CTRL(sdhi1_b_ctrl, SD1_CLK_B, SD1_CMD_B); ++SDHI_PFC_PINS(sdhi1_b_data1, RCAR_GP_PIN(1, 18)); ++SDHI_PFC_DAT1(sdhi1_b_data1, SD1_DAT0_B); ++SDHI_PFC_PINS(sdhi1_b_data4, RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), ++ RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21)); ++SDHI_PFC_DAT4(sdhi1_b_data4, SD1_DAT0_B, SD1_DAT1_B, ++ SD1_DAT2_B, SD1_DAT3_B); ++SDHI_PFC_PINS(sdhi1_b_wp, RCAR_GP_PIN(2, 25)); ++SDHI_PFC_WPPN(sdhi1_b_wp, SD1_WP_B); ++ ++ ++/* - SDH2 ------------------------------------------------------------------- */ ++SDHI_PFC_PINS(sdhi2_a_cd, RCAR_GP_PIN(4, 23)); ++SDHI_PFC_CDPN(sdhi2_a_cd, SD2_CD_A); ++SDHI_PFC_PINS(sdhi2_a_ctrl, RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18)); ++SDHI_PFC_CTRL(sdhi2_a_ctrl, SD2_CLK_A, SD2_CMD_A); ++SDHI_PFC_PINS(sdhi2_a_data1, RCAR_GP_PIN(4, 19)); ++SDHI_PFC_DAT1(sdhi2_a_data1, SD2_DAT0_A); ++SDHI_PFC_PINS(sdhi2_a_data4, RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20), ++ RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22)); ++SDHI_PFC_DAT4(sdhi2_a_data4, SD2_DAT0_A, SD2_DAT1_A, ++ SD2_DAT2_A, SD2_DAT3_A); ++SDHI_PFC_PINS(sdhi2_a_wp, RCAR_GP_PIN(4, 24)); ++SDHI_PFC_WPPN(sdhi2_a_wp, SD2_WP_A); ++ ++SDHI_PFC_PINS(sdhi2_b_cd, RCAR_GP_PIN(3, 27)); ++SDHI_PFC_CDPN(sdhi2_b_cd, SD2_CD_B); ++SDHI_PFC_PINS(sdhi2_b_ctrl, RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6)); ++SDHI_PFC_CTRL(sdhi2_b_ctrl, SD2_CLK_B, SD2_CMD_B); ++SDHI_PFC_PINS(sdhi2_b_data1, RCAR_GP_PIN(4, 7)); ++SDHI_PFC_DAT1(sdhi2_b_data1, SD2_DAT0_B); ++SDHI_PFC_PINS(sdhi2_b_data4, RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), ++ RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26)); ++SDHI_PFC_DAT4(sdhi2_b_data4, SD2_DAT0_B, SD2_DAT1_B, ++ SD2_DAT2_B, SD2_DAT3_B); ++SDHI_PFC_PINS(sdhi2_b_wp, RCAR_GP_PIN(3, 28)); ++SDHI_PFC_WPPN(sdhi2_b_wp, SD2_WP_B); ++ ++ + static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(hscif0_data_a), + SH_PFC_PIN_GROUP(hscif0_data_b), +@@ -1471,6 +1549,31 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(scif4_data_c), + SH_PFC_PIN_GROUP(scif5_data_a), + SH_PFC_PIN_GROUP(scif5_data_b), ++ SH_PFC_PIN_GROUP(sdhi0_cd), ++ SH_PFC_PIN_GROUP(sdhi0_ctrl), ++ SH_PFC_PIN_GROUP(sdhi0_data1), ++ SH_PFC_PIN_GROUP(sdhi0_data4), ++ SH_PFC_PIN_GROUP(sdhi0_wp), ++ SH_PFC_PIN_GROUP(sdhi1_a_cd), ++ SH_PFC_PIN_GROUP(sdhi1_a_ctrl), ++ SH_PFC_PIN_GROUP(sdhi1_a_data1), ++ SH_PFC_PIN_GROUP(sdhi1_a_data4), ++ SH_PFC_PIN_GROUP(sdhi1_a_wp), ++ SH_PFC_PIN_GROUP(sdhi1_b_cd), ++ SH_PFC_PIN_GROUP(sdhi1_b_ctrl), ++ SH_PFC_PIN_GROUP(sdhi1_b_data1), ++ SH_PFC_PIN_GROUP(sdhi1_b_data4), ++ SH_PFC_PIN_GROUP(sdhi1_b_wp), ++ SH_PFC_PIN_GROUP(sdhi2_a_cd), ++ SH_PFC_PIN_GROUP(sdhi2_a_ctrl), ++ SH_PFC_PIN_GROUP(sdhi2_a_data1), ++ SH_PFC_PIN_GROUP(sdhi2_a_data4), ++ SH_PFC_PIN_GROUP(sdhi2_a_wp), ++ SH_PFC_PIN_GROUP(sdhi2_b_cd), ++ SH_PFC_PIN_GROUP(sdhi2_b_ctrl), ++ SH_PFC_PIN_GROUP(sdhi2_b_data1), ++ SH_PFC_PIN_GROUP(sdhi2_b_data4), ++ SH_PFC_PIN_GROUP(sdhi2_b_wp), + }; + + static const char * const hscif0_groups[] = { +@@ -1543,6 +1646,41 @@ static const char * const scif5_groups[] = { + "scif5_data_b", + }; + ++ ++static const char * const sdhi0_groups[] = { ++ "sdhi0_cd", ++ "sdhi0_ctrl", ++ "sdhi0_data1", ++ "sdhi0_data4", ++ "sdhi0_wp", ++}; ++ ++static const char * const sdhi1_groups[] = { ++ "sdhi1_a_cd", ++ "sdhi1_a_ctrl", ++ "sdhi1_a_data1", ++ "sdhi1_a_data4", ++ "sdhi1_a_wp", ++ "sdhi1_b_cd", ++ "sdhi1_b_ctrl", ++ "sdhi1_b_data1", ++ "sdhi1_b_data4", ++ "sdhi1_b_wp", ++}; ++ ++static const char * const sdhi2_groups[] = { ++ "sdhi2_a_cd", ++ "sdhi2_a_ctrl", ++ "sdhi2_a_data1", ++ "sdhi2_a_data4", ++ "sdhi2_a_wp", ++ "sdhi2_b_cd", ++ "sdhi2_b_ctrl", ++ "sdhi2_b_data1", ++ "sdhi2_b_data4", ++ "sdhi2_b_wp", ++}; ++ + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), +@@ -1553,6 +1691,9 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(scif3), + SH_PFC_FUNCTION(scif4), + SH_PFC_FUNCTION(scif5), ++ SH_PFC_FUNCTION(sdhi0), ++ SH_PFC_FUNCTION(sdhi1), ++ SH_PFC_FUNCTION(sdhi2), + }; + + static struct pinmux_cfg_reg pinmux_config_regs[] = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0098-sh-pfc-sh7372-Add-BSC-pin-groups-and-functions.patch b/patches.renesas/0098-sh-pfc-sh7372-Add-BSC-pin-groups-and-functions.patch new file mode 100644 index 00000000000..7fc881e09c3 --- /dev/null +++ b/patches.renesas/0098-sh-pfc-sh7372-Add-BSC-pin-groups-and-functions.patch @@ -0,0 +1,172 @@ +From 41ffb95ac141b942b7a2416ac977d699dc424a22 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Apr 2013 12:31:08 +0200 +Subject: sh-pfc: sh7372: Add BSC pin groups and functions + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit e68e6415432da0855a80590c0efa88aada79ca1e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-sh7372.c | 124 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 124 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +index df0ae21a..9545b3c6 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +@@ -933,6 +933,102 @@ static struct sh_pfc_pin pinmux_pins[] = { + GPIO_PORT_ALL(), + }; + ++/* - BSC -------------------------------------------------------------------- */ ++static const unsigned int bsc_data8_pins[] = { ++ /* D[0:7] */ ++ 46, 47, 48, 49, 50, 51, 52, 53, ++}; ++static const unsigned int bsc_data8_mux[] = { ++ D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, ++ D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, ++}; ++static const unsigned int bsc_data16_pins[] = { ++ /* D[0:15] */ ++ 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, ++}; ++static const unsigned int bsc_data16_mux[] = { ++ D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, ++ D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, ++ D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, ++ D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK, ++}; ++static const unsigned int bsc_cs0_pins[] = { ++ /* CS */ ++ 62, ++}; ++static const unsigned int bsc_cs0_mux[] = { ++ CS0_MARK, ++}; ++static const unsigned int bsc_cs2_pins[] = { ++ /* CS */ ++ 63, ++}; ++static const unsigned int bsc_cs2_mux[] = { ++ CS2_MARK, ++}; ++static const unsigned int bsc_cs4_pins[] = { ++ /* CS */ ++ 64, ++}; ++static const unsigned int bsc_cs4_mux[] = { ++ CS4_MARK, ++}; ++static const unsigned int bsc_cs5a_pins[] = { ++ /* CS */ ++ 65, ++}; ++static const unsigned int bsc_cs5a_mux[] = { ++ CS5A_MARK, ++}; ++static const unsigned int bsc_cs5b_pins[] = { ++ /* CS */ ++ 66, ++}; ++static const unsigned int bsc_cs5b_mux[] = { ++ CS5B_MARK, ++}; ++static const unsigned int bsc_cs6a_pins[] = { ++ /* CS */ ++ 67, ++}; ++static const unsigned int bsc_cs6a_mux[] = { ++ CS6A_MARK, ++}; ++static const unsigned int bsc_rd_we8_pins[] = { ++ /* RD, WE[0] */ ++ 69, 70, ++}; ++static const unsigned int bsc_rd_we8_mux[] = { ++ RD_FSC_MARK, WE0_FWE_MARK, ++}; ++static const unsigned int bsc_rd_we16_pins[] = { ++ /* RD, WE[0:1] */ ++ 69, 70, 71, ++}; ++static const unsigned int bsc_rd_we16_mux[] = { ++ RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, ++}; ++static const unsigned int bsc_bs_pins[] = { ++ /* BS */ ++ 19, ++}; ++static const unsigned int bsc_bs_mux[] = { ++ BS_MARK, ++}; ++static const unsigned int bsc_rdwr_pins[] = { ++ /* RDWR */ ++ 75, ++}; ++static const unsigned int bsc_rdwr_mux[] = { ++ RDWR_MARK, ++}; ++static const unsigned int bsc_wait_pins[] = { ++ /* WAIT */ ++ 74, ++}; ++static const unsigned int bsc_wait_mux[] = { ++ WAIT_MARK, ++}; + /* - MMCIF ------------------------------------------------------------------ */ + static const unsigned int mmc0_data1_0_pins[] = { + /* D[0] */ +@@ -1075,6 +1171,18 @@ static const unsigned int sdhi2_ctrl_mux[] = { + }; + + static const struct sh_pfc_pin_group pinmux_groups[] = { ++ SH_PFC_PIN_GROUP(bsc_data8), ++ SH_PFC_PIN_GROUP(bsc_data16), ++ SH_PFC_PIN_GROUP(bsc_cs0), ++ SH_PFC_PIN_GROUP(bsc_cs2), ++ SH_PFC_PIN_GROUP(bsc_cs4), ++ SH_PFC_PIN_GROUP(bsc_cs5a), ++ SH_PFC_PIN_GROUP(bsc_cs5b), ++ SH_PFC_PIN_GROUP(bsc_cs6a), ++ SH_PFC_PIN_GROUP(bsc_rd_we8), ++ SH_PFC_PIN_GROUP(bsc_rd_we16), ++ SH_PFC_PIN_GROUP(bsc_bs), ++ SH_PFC_PIN_GROUP(bsc_rdwr), + SH_PFC_PIN_GROUP(mmc0_data1_0), + SH_PFC_PIN_GROUP(mmc0_data4_0), + SH_PFC_PIN_GROUP(mmc0_data8_0), +@@ -1096,6 +1204,21 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(sdhi2_ctrl), + }; + ++static const char * const bsc_groups[] = { ++ "bsc_data8", ++ "bsc_data16", ++ "bsc_cs0", ++ "bsc_cs2", ++ "bsc_cs4", ++ "bsc_cs5a", ++ "bsc_cs5b", ++ "bsc_cs6a", ++ "bsc_rd_we8", ++ "bsc_rd_we16", ++ "bsc_bs", ++ "bsc_rdwr", ++}; ++ + static const char * const mmc0_groups[] = { + "mmc0_data1_0", + "mmc0_data4_0", +@@ -1128,6 +1251,7 @@ static const char * const sdhi2_groups[] = { + }; + + static const struct sh_pfc_function pinmux_functions[] = { ++ SH_PFC_FUNCTION(bsc), + SH_PFC_FUNCTION(mmc0), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0099-sh-pfc-sh7372-Add-CEU-pin-groups-and-functions.patch b/patches.renesas/0099-sh-pfc-sh7372-Add-CEU-pin-groups-and-functions.patch new file mode 100644 index 00000000000..501ea82f0ea --- /dev/null +++ b/patches.renesas/0099-sh-pfc-sh7372-Add-CEU-pin-groups-and-functions.patch @@ -0,0 +1,118 @@ +From c5b747b048c5e4fb440d2877c884754e110c8ac1 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Apr 2013 12:31:08 +0200 +Subject: sh-pfc: sh7372: Add CEU pin groups and functions + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d4d1c6538ea4784bc1386014dee65a796d207815) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-sh7372.c | 70 +++++++++++++++++++++++++++++++++++++ + 1 file changed, 70 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +index 9545b3c6..3da83198 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +@@ -1029,6 +1029,58 @@ static const unsigned int bsc_wait_pins[] = { + static const unsigned int bsc_wait_mux[] = { + WAIT_MARK, + }; ++/* - CEU -------------------------------------------------------------------- */ ++static const unsigned int ceu_data_0_7_pins[] = { ++ /* D[0:7] */ ++ 102, 103, 104, 105, 106, 107, 108, 109, ++}; ++static const unsigned int ceu_data_0_7_mux[] = { ++ VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK, VIO_D3_MARK, ++ VIO_D4_MARK, VIO_D5_MARK, VIO_D6_MARK, VIO_D7_MARK, ++}; ++static const unsigned int ceu_data_8_15_pins[] = { ++ /* D[8:15] */ ++ 110, 111, 112, 113, 114, 115, 116, 117, ++}; ++static const unsigned int ceu_data_8_15_mux[] = { ++ VIO_D8_MARK, VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK, ++ VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK, VIO_D15_MARK, ++}; ++static const unsigned int ceu_clk_0_pins[] = { ++ /* CKO */ ++ 120, ++}; ++static const unsigned int ceu_clk_0_mux[] = { ++ VIO_CKO_MARK, ++}; ++static const unsigned int ceu_clk_1_pins[] = { ++ /* CKO */ ++ 16, ++}; ++static const unsigned int ceu_clk_1_mux[] = { ++ VIO_CKO1_MARK, ++}; ++static const unsigned int ceu_clk_2_pins[] = { ++ /* CKO */ ++ 17, ++}; ++static const unsigned int ceu_clk_2_mux[] = { ++ VIO_CKO2_MARK, ++}; ++static const unsigned int ceu_sync_pins[] = { ++ /* CLK, VD, HD */ ++ 118, 100, 101, ++}; ++static const unsigned int ceu_sync_mux[] = { ++ VIO_CLK_MARK, VIO_VD_MARK, VIO_HD_MARK, ++}; ++static const unsigned int ceu_field_pins[] = { ++ /* FIELD */ ++ 119, ++}; ++static const unsigned int ceu_field_mux[] = { ++ VIO_FIELD_MARK, ++}; + /* - MMCIF ------------------------------------------------------------------ */ + static const unsigned int mmc0_data1_0_pins[] = { + /* D[0] */ +@@ -1183,6 +1235,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(bsc_rd_we16), + SH_PFC_PIN_GROUP(bsc_bs), + SH_PFC_PIN_GROUP(bsc_rdwr), ++ SH_PFC_PIN_GROUP(ceu_data_0_7), ++ SH_PFC_PIN_GROUP(ceu_data_8_15), ++ SH_PFC_PIN_GROUP(ceu_clk_0), ++ SH_PFC_PIN_GROUP(ceu_clk_1), ++ SH_PFC_PIN_GROUP(ceu_clk_2), ++ SH_PFC_PIN_GROUP(ceu_sync), ++ SH_PFC_PIN_GROUP(ceu_field), + SH_PFC_PIN_GROUP(mmc0_data1_0), + SH_PFC_PIN_GROUP(mmc0_data4_0), + SH_PFC_PIN_GROUP(mmc0_data8_0), +@@ -1219,6 +1278,16 @@ static const char * const bsc_groups[] = { + "bsc_rdwr", + }; + ++static const char * const ceu_groups[] = { ++ "ceu_data_0_7", ++ "ceu_data_8_15", ++ "ceu_clk_0", ++ "ceu_clk_1", ++ "ceu_clk_2", ++ "ceu_sync", ++ "ceu_field", ++}; ++ + static const char * const mmc0_groups[] = { + "mmc0_data1_0", + "mmc0_data4_0", +@@ -1252,6 +1321,7 @@ static const char * const sdhi2_groups[] = { + + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(bsc), ++ SH_PFC_FUNCTION(ceu), + SH_PFC_FUNCTION(mmc0), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0100-sh-pfc-sh7372-Add-FLCTL-pin-groups-and-functions.patch b/patches.renesas/0100-sh-pfc-sh7372-Add-FLCTL-pin-groups-and-functions.patch new file mode 100644 index 00000000000..6c7cdd4f0ac --- /dev/null +++ b/patches.renesas/0100-sh-pfc-sh7372-Add-FLCTL-pin-groups-and-functions.patch @@ -0,0 +1,92 @@ +From 662376db0568c9bd4fe5c106945474a00ce0c8d2 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Apr 2013 12:31:08 +0200 +Subject: sh-pfc: sh7372: Add FLCTL pin groups and functions + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 8b1b71d3a857cb0486e27516d9d296ae7b45c5ca) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-sh7372.c | 44 +++++++++++++++++++++++++++++++++++++ + 1 file changed, 44 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +index 3da83198..99486996 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +@@ -1081,6 +1081,38 @@ static const unsigned int ceu_field_pins[] = { + static const unsigned int ceu_field_mux[] = { + VIO_FIELD_MARK, + }; ++/* - FLCTL ------------------------------------------------------------------ */ ++static const unsigned int flctl_data_pins[] = { ++ /* NAF[0:15] */ ++ 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, ++}; ++static const unsigned int flctl_data_mux[] = { ++ D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, ++ D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, ++ D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, ++ D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK, ++}; ++static const unsigned int flctl_ce0_pins[] = { ++ /* CE */ ++ 68, ++}; ++static const unsigned int flctl_ce0_mux[] = { ++ FCE0_MARK, ++}; ++static const unsigned int flctl_ce1_pins[] = { ++ /* CE */ ++ 66, ++}; ++static const unsigned int flctl_ce1_mux[] = { ++ FCE1_MARK, ++}; ++static const unsigned int flctl_ctrl_pins[] = { ++ /* FCDE, FOE, FSC, FWE, FRB */ ++ 24, 23, 69, 70, 73, ++}; ++static const unsigned int flctl_ctrl_mux[] = { ++ A5_FCDE_MARK, A4_FOE_MARK, RD_FSC_MARK, WE0_FWE_MARK, FRB_MARK, ++}; + /* - MMCIF ------------------------------------------------------------------ */ + static const unsigned int mmc0_data1_0_pins[] = { + /* D[0] */ +@@ -1242,6 +1274,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(ceu_clk_2), + SH_PFC_PIN_GROUP(ceu_sync), + SH_PFC_PIN_GROUP(ceu_field), ++ SH_PFC_PIN_GROUP(flctl_data), ++ SH_PFC_PIN_GROUP(flctl_ce0), ++ SH_PFC_PIN_GROUP(flctl_ce1), ++ SH_PFC_PIN_GROUP(flctl_ctrl), + SH_PFC_PIN_GROUP(mmc0_data1_0), + SH_PFC_PIN_GROUP(mmc0_data4_0), + SH_PFC_PIN_GROUP(mmc0_data8_0), +@@ -1288,6 +1324,13 @@ static const char * const ceu_groups[] = { + "ceu_field", + }; + ++static const char * const flctl_groups[] = { ++ "flctl_data", ++ "flctl_ce0", ++ "flctl_ce1", ++ "flctl_ctrl", ++}; ++ + static const char * const mmc0_groups[] = { + "mmc0_data1_0", + "mmc0_data4_0", +@@ -1322,6 +1365,7 @@ static const char * const sdhi2_groups[] = { + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(bsc), + SH_PFC_FUNCTION(ceu), ++ SH_PFC_FUNCTION(flctl), + SH_PFC_FUNCTION(mmc0), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0101-sh-pfc-sh7372-Add-FSI-pin-groups-and-functions.patch b/patches.renesas/0101-sh-pfc-sh7372-Add-FSI-pin-groups-and-functions.patch new file mode 100644 index 00000000000..1aaaeb048cb --- /dev/null +++ b/patches.renesas/0101-sh-pfc-sh7372-Add-FSI-pin-groups-and-functions.patch @@ -0,0 +1,139 @@ +From 1fee0894534d105bfcf98146745cb5c958d9f3ed Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Apr 2013 12:31:08 +0200 +Subject: sh-pfc: sh7372: Add FSI pin groups and functions + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 971a0cd6dcb6330c88fdc935944f1bbfe118ba00) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-sh7372.c | 91 +++++++++++++++++++++++++++++++++++++ + 1 file changed, 91 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +index 99486996..641f6ee5 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +@@ -1113,6 +1113,71 @@ static const unsigned int flctl_ctrl_pins[] = { + static const unsigned int flctl_ctrl_mux[] = { + A5_FCDE_MARK, A4_FOE_MARK, RD_FSC_MARK, WE0_FWE_MARK, FRB_MARK, + }; ++/* - FSIA ------------------------------------------------------------------- */ ++static const unsigned int fsia_mclk_in_pins[] = { ++ /* CK */ ++ 4, ++}; ++static const unsigned int fsia_mclk_in_mux[] = { ++ FSIACK_MARK, ++}; ++static const unsigned int fsia_mclk_out_pins[] = { ++ /* OMC */ ++ 8, ++}; ++static const unsigned int fsia_mclk_out_mux[] = { ++ FSIAOMC_MARK, ++}; ++static const unsigned int fsia_sclk_in_pins[] = { ++ /* ILR, IBT */ ++ 5, 6, ++}; ++static const unsigned int fsia_sclk_in_mux[] = { ++ FSIAILR_MARK, FSIAIBT_MARK, ++}; ++static const unsigned int fsia_sclk_out_pins[] = { ++ /* OLR, OBT */ ++ 9, 10, ++}; ++static const unsigned int fsia_sclk_out_mux[] = { ++ FSIAOLR_MARK, FSIAOBT_MARK, ++}; ++static const unsigned int fsia_data_in_pins[] = { ++ /* ISLD */ ++ 7, ++}; ++static const unsigned int fsia_data_in_mux[] = { ++ FSIAISLD_MARK, ++}; ++static const unsigned int fsia_data_out_pins[] = { ++ /* OSLD */ ++ 11, ++}; ++static const unsigned int fsia_data_out_mux[] = { ++ FSIAOSLD_MARK, ++}; ++static const unsigned int fsia_spdif_0_pins[] = { ++ /* SPDIF */ ++ 11, ++}; ++static const unsigned int fsia_spdif_0_mux[] = { ++ FSIASPDIF_11_MARK, ++}; ++static const unsigned int fsia_spdif_1_pins[] = { ++ /* SPDIF */ ++ 15, ++}; ++static const unsigned int fsia_spdif_1_mux[] = { ++ FSIASPDIF_15_MARK, ++}; ++/* - FSIB ------------------------------------------------------------------- */ ++static const unsigned int fsib_mclk_in_pins[] = { ++ /* CK */ ++ 4, ++}; ++static const unsigned int fsib_mclk_in_mux[] = { ++ FSIBCK_MARK, ++}; + /* - MMCIF ------------------------------------------------------------------ */ + static const unsigned int mmc0_data1_0_pins[] = { + /* D[0] */ +@@ -1278,6 +1343,15 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(flctl_ce0), + SH_PFC_PIN_GROUP(flctl_ce1), + SH_PFC_PIN_GROUP(flctl_ctrl), ++ SH_PFC_PIN_GROUP(fsia_mclk_in), ++ SH_PFC_PIN_GROUP(fsia_mclk_out), ++ SH_PFC_PIN_GROUP(fsia_sclk_in), ++ SH_PFC_PIN_GROUP(fsia_sclk_out), ++ SH_PFC_PIN_GROUP(fsia_data_in), ++ SH_PFC_PIN_GROUP(fsia_data_out), ++ SH_PFC_PIN_GROUP(fsia_spdif_0), ++ SH_PFC_PIN_GROUP(fsia_spdif_1), ++ SH_PFC_PIN_GROUP(fsib_mclk_in), + SH_PFC_PIN_GROUP(mmc0_data1_0), + SH_PFC_PIN_GROUP(mmc0_data4_0), + SH_PFC_PIN_GROUP(mmc0_data8_0), +@@ -1331,6 +1405,21 @@ static const char * const flctl_groups[] = { + "flctl_ctrl", + }; + ++static const char * const fsia_groups[] = { ++ "fsia_mclk_in", ++ "fsia_mclk_out", ++ "fsia_sclk_in", ++ "fsia_sclk_out", ++ "fsia_data_in", ++ "fsia_data_out", ++ "fsia_spdif_0", ++ "fsia_spdif_1", ++}; ++ ++static const char * const fsib_groups[] = { ++ "fsib_mclk_in", ++}; ++ + static const char * const mmc0_groups[] = { + "mmc0_data1_0", + "mmc0_data4_0", +@@ -1366,6 +1455,8 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(bsc), + SH_PFC_FUNCTION(ceu), + SH_PFC_FUNCTION(flctl), ++ SH_PFC_FUNCTION(fsia), ++ SH_PFC_FUNCTION(fsib), + SH_PFC_FUNCTION(mmc0), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0102-sh-pfc-sh7372-Add-HDMI-pin-groups-and-functions.patch b/patches.renesas/0102-sh-pfc-sh7372-Add-HDMI-pin-groups-and-functions.patch new file mode 100644 index 00000000000..7a72e64962c --- /dev/null +++ b/patches.renesas/0102-sh-pfc-sh7372-Add-HDMI-pin-groups-and-functions.patch @@ -0,0 +1,62 @@ +From 76682ea1f1e8452ac444e071fda9488ab3ae37d6 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Apr 2013 12:31:08 +0200 +Subject: sh-pfc: sh7372: Add HDMI pin groups and functions + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 7231fa45e9e01fa9288098579b2d2a93202f4d3f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-sh7372.c | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +index 641f6ee5..73b9e255 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +@@ -1178,6 +1178,14 @@ static const unsigned int fsib_mclk_in_pins[] = { + static const unsigned int fsib_mclk_in_mux[] = { + FSIBCK_MARK, + }; ++/* - HDMI ------------------------------------------------------------------- */ ++static const unsigned int hdmi_pins[] = { ++ /* HPD, CEC */ ++ 169, 170, ++}; ++static const unsigned int hdmi_mux[] = { ++ HDMI_HPD_MARK, HDMI_CEC_MARK, ++}; + /* - MMCIF ------------------------------------------------------------------ */ + static const unsigned int mmc0_data1_0_pins[] = { + /* D[0] */ +@@ -1352,6 +1360,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(fsia_spdif_0), + SH_PFC_PIN_GROUP(fsia_spdif_1), + SH_PFC_PIN_GROUP(fsib_mclk_in), ++ SH_PFC_PIN_GROUP(hdmi), + SH_PFC_PIN_GROUP(mmc0_data1_0), + SH_PFC_PIN_GROUP(mmc0_data4_0), + SH_PFC_PIN_GROUP(mmc0_data8_0), +@@ -1420,6 +1429,10 @@ static const char * const fsib_groups[] = { + "fsib_mclk_in", + }; + ++static const char * const hdmi_groups[] = { ++ "hdmi", ++}; ++ + static const char * const mmc0_groups[] = { + "mmc0_data1_0", + "mmc0_data4_0", +@@ -1457,6 +1470,7 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(flctl), + SH_PFC_FUNCTION(fsia), + SH_PFC_FUNCTION(fsib), ++ SH_PFC_FUNCTION(hdmi), + SH_PFC_FUNCTION(mmc0), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0103-sh-pfc-sh7372-Add-INTC-pin-groups-and-functions.patch b/patches.renesas/0103-sh-pfc-sh7372-Add-INTC-pin-groups-and-functions.patch new file mode 100644 index 00000000000..b4c6bb45b7e --- /dev/null +++ b/patches.renesas/0103-sh-pfc-sh7372-Add-INTC-pin-groups-and-functions.patch @@ -0,0 +1,216 @@ +From f6fe72e693076c8e3fd0aec3f48500733bce351f Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Apr 2013 12:31:08 +0200 +Subject: sh-pfc: sh7372: Add INTC pin groups and functions + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 4d0882963ece22f8b7c8b0e0832f083a04b891da) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-sh7372.c | 161 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 161 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +index 73b9e255..def6e2cf 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +@@ -34,6 +34,28 @@ + PORT_10(fn, pfx##16, sfx), PORT_10(fn, pfx##17, sfx), \ + PORT_10(fn, pfx##18, sfx), PORT_1(fn, pfx##190, sfx) + ++#define IRQC_PIN_MUX(irq, pin) \ ++static const unsigned int intc_irq##irq##_pins[] = { \ ++ pin, \ ++}; \ ++static const unsigned int intc_irq##irq##_mux[] = { \ ++ IRQ##irq##_MARK, \ ++} ++ ++#define IRQC_PINS_MUX(irq, pin0, pin1) \ ++static const unsigned int intc_irq##irq##_0_pins[] = { \ ++ pin0, \ ++}; \ ++static const unsigned int intc_irq##irq##_0_mux[] = { \ ++ IRQ##irq##_##pin0##_MARK, \ ++}; \ ++static const unsigned int intc_irq##irq##_1_pins[] = { \ ++ pin1, \ ++}; \ ++static const unsigned int intc_irq##irq##_1_mux[] = { \ ++ IRQ##irq##_##pin1##_MARK, \ ++} ++ + enum { + PINMUX_RESERVED = 0, + +@@ -1186,6 +1208,39 @@ static const unsigned int hdmi_pins[] = { + static const unsigned int hdmi_mux[] = { + HDMI_HPD_MARK, HDMI_CEC_MARK, + }; ++/* - INTC ------------------------------------------------------------------- */ ++IRQC_PINS_MUX(0, 6, 162); ++IRQC_PIN_MUX(1, 12); ++IRQC_PINS_MUX(2, 4, 5); ++IRQC_PINS_MUX(3, 8, 16); ++IRQC_PINS_MUX(4, 17, 163); ++IRQC_PIN_MUX(5, 18); ++IRQC_PINS_MUX(6, 39, 164); ++IRQC_PINS_MUX(7, 40, 167); ++IRQC_PINS_MUX(8, 41, 168); ++IRQC_PINS_MUX(9, 42, 169); ++IRQC_PIN_MUX(10, 65); ++IRQC_PIN_MUX(11, 67); ++IRQC_PINS_MUX(12, 80, 137); ++IRQC_PINS_MUX(13, 81, 145); ++IRQC_PINS_MUX(14, 82, 146); ++IRQC_PINS_MUX(15, 83, 147); ++IRQC_PINS_MUX(16, 84, 170); ++IRQC_PIN_MUX(17, 85); ++IRQC_PIN_MUX(18, 86); ++IRQC_PIN_MUX(19, 87); ++IRQC_PIN_MUX(20, 92); ++IRQC_PIN_MUX(21, 93); ++IRQC_PIN_MUX(22, 94); ++IRQC_PIN_MUX(23, 95); ++IRQC_PIN_MUX(24, 112); ++IRQC_PIN_MUX(25, 119); ++IRQC_PINS_MUX(26, 121, 172); ++IRQC_PINS_MUX(27, 122, 180); ++IRQC_PINS_MUX(28, 123, 181); ++IRQC_PINS_MUX(29, 129, 182); ++IRQC_PINS_MUX(30, 130, 183); ++IRQC_PINS_MUX(31, 138, 184); + /* - MMCIF ------------------------------------------------------------------ */ + static const unsigned int mmc0_data1_0_pins[] = { + /* D[0] */ +@@ -1361,6 +1416,57 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(fsia_spdif_1), + SH_PFC_PIN_GROUP(fsib_mclk_in), + SH_PFC_PIN_GROUP(hdmi), ++ SH_PFC_PIN_GROUP(intc_irq0_0), ++ SH_PFC_PIN_GROUP(intc_irq0_1), ++ SH_PFC_PIN_GROUP(intc_irq1), ++ SH_PFC_PIN_GROUP(intc_irq2_0), ++ SH_PFC_PIN_GROUP(intc_irq2_1), ++ SH_PFC_PIN_GROUP(intc_irq3_0), ++ SH_PFC_PIN_GROUP(intc_irq3_1), ++ SH_PFC_PIN_GROUP(intc_irq4_0), ++ SH_PFC_PIN_GROUP(intc_irq4_1), ++ SH_PFC_PIN_GROUP(intc_irq5), ++ SH_PFC_PIN_GROUP(intc_irq6_0), ++ SH_PFC_PIN_GROUP(intc_irq6_1), ++ SH_PFC_PIN_GROUP(intc_irq7_0), ++ SH_PFC_PIN_GROUP(intc_irq7_1), ++ SH_PFC_PIN_GROUP(intc_irq8_0), ++ SH_PFC_PIN_GROUP(intc_irq8_1), ++ SH_PFC_PIN_GROUP(intc_irq9_0), ++ SH_PFC_PIN_GROUP(intc_irq9_1), ++ SH_PFC_PIN_GROUP(intc_irq10), ++ SH_PFC_PIN_GROUP(intc_irq11), ++ SH_PFC_PIN_GROUP(intc_irq12_0), ++ SH_PFC_PIN_GROUP(intc_irq12_1), ++ SH_PFC_PIN_GROUP(intc_irq13_0), ++ SH_PFC_PIN_GROUP(intc_irq13_1), ++ SH_PFC_PIN_GROUP(intc_irq14_0), ++ SH_PFC_PIN_GROUP(intc_irq14_1), ++ SH_PFC_PIN_GROUP(intc_irq15_0), ++ SH_PFC_PIN_GROUP(intc_irq15_1), ++ SH_PFC_PIN_GROUP(intc_irq16_0), ++ SH_PFC_PIN_GROUP(intc_irq16_1), ++ SH_PFC_PIN_GROUP(intc_irq17), ++ SH_PFC_PIN_GROUP(intc_irq18), ++ SH_PFC_PIN_GROUP(intc_irq19), ++ SH_PFC_PIN_GROUP(intc_irq20), ++ SH_PFC_PIN_GROUP(intc_irq21), ++ SH_PFC_PIN_GROUP(intc_irq22), ++ SH_PFC_PIN_GROUP(intc_irq23), ++ SH_PFC_PIN_GROUP(intc_irq24), ++ SH_PFC_PIN_GROUP(intc_irq25), ++ SH_PFC_PIN_GROUP(intc_irq26_0), ++ SH_PFC_PIN_GROUP(intc_irq26_1), ++ SH_PFC_PIN_GROUP(intc_irq27_0), ++ SH_PFC_PIN_GROUP(intc_irq27_1), ++ SH_PFC_PIN_GROUP(intc_irq28_0), ++ SH_PFC_PIN_GROUP(intc_irq28_1), ++ SH_PFC_PIN_GROUP(intc_irq29_0), ++ SH_PFC_PIN_GROUP(intc_irq29_1), ++ SH_PFC_PIN_GROUP(intc_irq30_0), ++ SH_PFC_PIN_GROUP(intc_irq30_1), ++ SH_PFC_PIN_GROUP(intc_irq31_0), ++ SH_PFC_PIN_GROUP(intc_irq31_1), + SH_PFC_PIN_GROUP(mmc0_data1_0), + SH_PFC_PIN_GROUP(mmc0_data4_0), + SH_PFC_PIN_GROUP(mmc0_data8_0), +@@ -1433,6 +1539,60 @@ static const char * const hdmi_groups[] = { + "hdmi", + }; + ++static const char * const intc_groups[] = { ++ "intc_irq0_0", ++ "intc_irq0_1", ++ "intc_irq1", ++ "intc_irq2_0", ++ "intc_irq2_1", ++ "intc_irq3_0", ++ "intc_irq3_1", ++ "intc_irq4_0", ++ "intc_irq4_1", ++ "intc_irq5", ++ "intc_irq6_0", ++ "intc_irq6_1", ++ "intc_irq7_0", ++ "intc_irq7_1", ++ "intc_irq8_0", ++ "intc_irq8_1", ++ "intc_irq9_0", ++ "intc_irq9_1", ++ "intc_irq10", ++ "intc_irq11", ++ "intc_irq12_0", ++ "intc_irq12_1", ++ "intc_irq13_0", ++ "intc_irq13_1", ++ "intc_irq14_0", ++ "intc_irq14_1", ++ "intc_irq15_0", ++ "intc_irq15_1", ++ "intc_irq16_0", ++ "intc_irq16_1", ++ "intc_irq17", ++ "intc_irq18", ++ "intc_irq19", ++ "intc_irq20", ++ "intc_irq21", ++ "intc_irq22", ++ "intc_irq23", ++ "intc_irq24", ++ "intc_irq25", ++ "intc_irq26_0", ++ "intc_irq26_1", ++ "intc_irq27_0", ++ "intc_irq27_1", ++ "intc_irq28_0", ++ "intc_irq28_1", ++ "intc_irq29_0", ++ "intc_irq29_1", ++ "intc_irq30_0", ++ "intc_irq30_1", ++ "intc_irq31_0", ++ "intc_irq31_1", ++}; ++ + static const char * const mmc0_groups[] = { + "mmc0_data1_0", + "mmc0_data4_0", +@@ -1471,6 +1631,7 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(fsia), + SH_PFC_FUNCTION(fsib), + SH_PFC_FUNCTION(hdmi), ++ SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(mmc0), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0104-sh-pfc-sh7372-Add-KEYSC-pin-groups-and-functions.patch b/patches.renesas/0104-sh-pfc-sh7372-Add-KEYSC-pin-groups-and-functions.patch new file mode 100644 index 00000000000..e702a0bc3a6 --- /dev/null +++ b/patches.renesas/0104-sh-pfc-sh7372-Add-KEYSC-pin-groups-and-functions.patch @@ -0,0 +1,139 @@ +From f10351c8052552e56b64d5b4614c164ef7297316 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Apr 2013 12:31:08 +0200 +Subject: sh-pfc: sh7372: Add KEYSC pin groups and functions + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 41eb7d605eb53959dd1d38bd5d1d490faee7c499) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-sh7372.c | 91 +++++++++++++++++++++++++++++++++++++ + 1 file changed, 91 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +index def6e2cf..50cbff6e 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +@@ -1241,6 +1241,75 @@ IRQC_PINS_MUX(28, 123, 181); + IRQC_PINS_MUX(29, 129, 182); + IRQC_PINS_MUX(30, 130, 183); + IRQC_PINS_MUX(31, 138, 184); ++/* - KEYSC ------------------------------------------------------------------ */ ++static const unsigned int keysc_in04_0_pins[] = { ++ /* KEYIN[0:4] */ ++ 136, 135, 134, 133, 132, ++}; ++static const unsigned int keysc_in04_0_mux[] = { ++ KEYIN0_136_MARK, KEYIN1_135_MARK, KEYIN2_134_MARK, KEYIN3_133_MARK, ++ KEYIN4_MARK, ++}; ++static const unsigned int keysc_in04_1_pins[] = { ++ /* KEYIN[0:4] */ ++ 121, 122, 123, 124, 132, ++}; ++static const unsigned int keysc_in04_1_mux[] = { ++ KEYIN0_121_MARK, KEYIN1_122_MARK, KEYIN2_123_MARK, KEYIN3_124_MARK, ++ KEYIN4_MARK, ++}; ++static const unsigned int keysc_in5_pins[] = { ++ /* KEYIN5 */ ++ 131, ++}; ++static const unsigned int keysc_in5_mux[] = { ++ KEYIN5_MARK, ++}; ++static const unsigned int keysc_in6_pins[] = { ++ /* KEYIN6 */ ++ 130, ++}; ++static const unsigned int keysc_in6_mux[] = { ++ KEYIN6_MARK, ++}; ++static const unsigned int keysc_in7_pins[] = { ++ /* KEYIN7 */ ++ 129, ++}; ++static const unsigned int keysc_in7_mux[] = { ++ KEYIN7_MARK, ++}; ++static const unsigned int keysc_out4_pins[] = { ++ /* KEYOUT[0:3] */ ++ 128, 127, 126, 125, ++}; ++static const unsigned int keysc_out4_mux[] = { ++ KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, ++}; ++static const unsigned int keysc_out5_pins[] = { ++ /* KEYOUT[0:4] */ ++ 128, 127, 126, 125, 124, ++}; ++static const unsigned int keysc_out5_mux[] = { ++ KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, ++ KEYOUT4_MARK, ++}; ++static const unsigned int keysc_out6_pins[] = { ++ /* KEYOUT[0:5] */ ++ 128, 127, 126, 125, 124, 123, ++}; ++static const unsigned int keysc_out6_mux[] = { ++ KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, ++ KEYOUT4_MARK, KEYOUT5_MARK, ++}; ++static const unsigned int keysc_out8_pins[] = { ++ /* KEYOUT[0:7] */ ++ 128, 127, 126, 125, 124, 123, 122, 121, ++}; ++static const unsigned int keysc_out8_mux[] = { ++ KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, ++ KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK, ++}; + /* - MMCIF ------------------------------------------------------------------ */ + static const unsigned int mmc0_data1_0_pins[] = { + /* D[0] */ +@@ -1467,6 +1536,15 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(intc_irq30_1), + SH_PFC_PIN_GROUP(intc_irq31_0), + SH_PFC_PIN_GROUP(intc_irq31_1), ++ SH_PFC_PIN_GROUP(keysc_in04_0), ++ SH_PFC_PIN_GROUP(keysc_in04_1), ++ SH_PFC_PIN_GROUP(keysc_in5), ++ SH_PFC_PIN_GROUP(keysc_in6), ++ SH_PFC_PIN_GROUP(keysc_in7), ++ SH_PFC_PIN_GROUP(keysc_out4), ++ SH_PFC_PIN_GROUP(keysc_out5), ++ SH_PFC_PIN_GROUP(keysc_out6), ++ SH_PFC_PIN_GROUP(keysc_out8), + SH_PFC_PIN_GROUP(mmc0_data1_0), + SH_PFC_PIN_GROUP(mmc0_data4_0), + SH_PFC_PIN_GROUP(mmc0_data8_0), +@@ -1593,6 +1671,18 @@ static const char * const intc_groups[] = { + "intc_irq31_1", + }; + ++static const char * const keysc_groups[] = { ++ "keysc_in04_0", ++ "keysc_in04_1", ++ "keysc_in5", ++ "keysc_in6", ++ "keysc_in7", ++ "keysc_out4", ++ "keysc_out5", ++ "keysc_out6", ++ "keysc_out8", ++}; ++ + static const char * const mmc0_groups[] = { + "mmc0_data1_0", + "mmc0_data4_0", +@@ -1632,6 +1722,7 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(fsib), + SH_PFC_FUNCTION(hdmi), + SH_PFC_FUNCTION(intc), ++ SH_PFC_FUNCTION(keysc), + SH_PFC_FUNCTION(mmc0), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0105-sh-pfc-sh7372-Add-LCDC-pin-groups-and-functions.patch b/patches.renesas/0105-sh-pfc-sh7372-Add-LCDC-pin-groups-and-functions.patch new file mode 100644 index 00000000000..3fbbb1ad87c --- /dev/null +++ b/patches.renesas/0105-sh-pfc-sh7372-Add-LCDC-pin-groups-and-functions.patch @@ -0,0 +1,169 @@ +From a58def8e86229e2604dacd80af8a3241c07bbb36 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Apr 2013 12:31:08 +0200 +Subject: sh-pfc: sh7372: Add LCDC pin groups and functions + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit f3e03eb82543162f3f39c030defb9b2b5392f274) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-sh7372.c | 121 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 121 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +index 50cbff6e..8503747a 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +@@ -1310,6 +1310,103 @@ static const unsigned int keysc_out8_mux[] = { + KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, + KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK, + }; ++/* - LCD -------------------------------------------------------------------- */ ++static const unsigned int lcd_data8_pins[] = { ++ /* D[0:7] */ ++ 121, 122, 123, 124, 125, 126, 127, 128, ++}; ++static const unsigned int lcd_data8_mux[] = { ++ /* LCDC */ ++ LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, ++ LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, ++}; ++static const unsigned int lcd_data9_pins[] = { ++ /* D[0:8] */ ++ 121, 122, 123, 124, 125, 126, 127, 128, ++ 129, ++ 137, 138, 139, 140, 141, 142, 143, 144, ++}; ++static const unsigned int lcd_data9_mux[] = { ++ LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, ++ LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, ++ LCDD8_MARK, ++}; ++static const unsigned int lcd_data12_pins[] = { ++ /* D[0:11] */ ++ 121, 122, 123, 124, 125, 126, 127, 128, ++ 129, 130, 131, 132, ++}; ++static const unsigned int lcd_data12_mux[] = { ++ LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, ++ LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, ++ LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, ++}; ++static const unsigned int lcd_data16_pins[] = { ++ /* D[0:15] */ ++ 121, 122, 123, 124, 125, 126, 127, 128, ++ 129, 130, 131, 132, 133, 134, 135, 136, ++}; ++static const unsigned int lcd_data16_mux[] = { ++ LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, ++ LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, ++ LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, ++ LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, ++}; ++static const unsigned int lcd_data18_pins[] = { ++ /* D[0:17] */ ++ 121, 122, 123, 124, 125, 126, 127, 128, ++ 129, 130, 131, 132, 133, 134, 135, 136, ++ 137, 138, ++}; ++static const unsigned int lcd_data18_mux[] = { ++ LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, ++ LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, ++ LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, ++ LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, ++ LCDD16_MARK, LCDD17_MARK, ++}; ++static const unsigned int lcd_data24_pins[] = { ++ /* D[0:23] */ ++ 121, 122, 123, 124, 125, 126, 127, 128, ++ 129, 130, 131, 132, 133, 134, 135, 136, ++ 137, 138, 139, 140, 141, 142, 143, 144, ++}; ++static const unsigned int lcd_data24_mux[] = { ++ LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, ++ LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, ++ LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, ++ LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, ++ LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK, ++ LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK, ++}; ++static const unsigned int lcd_display_pins[] = { ++ /* DON */ ++ 151, ++}; ++static const unsigned int lcd_display_mux[] = { ++ LCDDON_MARK, ++}; ++static const unsigned int lcd_lclk_pins[] = { ++ /* LCLK */ ++ 150, ++}; ++static const unsigned int lcd_lclk_mux[] = { ++ LCDLCLK_MARK, ++}; ++static const unsigned int lcd_sync_pins[] = { ++ /* VSYN, HSYN, DCK, DISP */ ++ 146, 145, 147, 149, ++}; ++static const unsigned int lcd_sync_mux[] = { ++ LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK, ++}; ++static const unsigned int lcd_sys_pins[] = { ++ /* CS, WR, RD, RS */ ++ 145, 147, 148, 149, ++}; ++static const unsigned int lcd_sys_mux[] = { ++ LCDCS_MARK, LCDWR_MARK, LCDRD_MARK, LCDRS_MARK, ++}; + /* - MMCIF ------------------------------------------------------------------ */ + static const unsigned int mmc0_data1_0_pins[] = { + /* D[0] */ +@@ -1545,6 +1642,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(keysc_out5), + SH_PFC_PIN_GROUP(keysc_out6), + SH_PFC_PIN_GROUP(keysc_out8), ++ SH_PFC_PIN_GROUP(lcd_data8), ++ SH_PFC_PIN_GROUP(lcd_data9), ++ SH_PFC_PIN_GROUP(lcd_data12), ++ SH_PFC_PIN_GROUP(lcd_data16), ++ SH_PFC_PIN_GROUP(lcd_data18), ++ SH_PFC_PIN_GROUP(lcd_data24), ++ SH_PFC_PIN_GROUP(lcd_display), ++ SH_PFC_PIN_GROUP(lcd_lclk), ++ SH_PFC_PIN_GROUP(lcd_sync), ++ SH_PFC_PIN_GROUP(lcd_sys), + SH_PFC_PIN_GROUP(mmc0_data1_0), + SH_PFC_PIN_GROUP(mmc0_data4_0), + SH_PFC_PIN_GROUP(mmc0_data8_0), +@@ -1683,6 +1790,19 @@ static const char * const keysc_groups[] = { + "keysc_out8", + }; + ++static const char * const lcd_groups[] = { ++ "lcd_data8", ++ "lcd_data9", ++ "lcd_data12", ++ "lcd_data16", ++ "lcd_data18", ++ "lcd_data24", ++ "lcd_display", ++ "lcd_lclk", ++ "lcd_sync", ++ "lcd_sys", ++}; ++ + static const char * const mmc0_groups[] = { + "mmc0_data1_0", + "mmc0_data4_0", +@@ -1723,6 +1843,7 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(hdmi), + SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(keysc), ++ SH_PFC_FUNCTION(lcd), + SH_PFC_FUNCTION(mmc0), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0106-sh-pfc-sh7372-Add-SCIF-pin-groups-and-functions.patch b/patches.renesas/0106-sh-pfc-sh7372-Add-SCIF-pin-groups-and-functions.patch new file mode 100644 index 00000000000..5d65bbff257 --- /dev/null +++ b/patches.renesas/0106-sh-pfc-sh7372-Add-SCIF-pin-groups-and-functions.patch @@ -0,0 +1,245 @@ +From 555884b3ba88f93a26b2df56c403062e50a62310 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Apr 2013 12:31:08 +0200 +Subject: sh-pfc: sh7372: Add SCIF pin groups and functions + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit ddc3296179bc6abbeebc90e101001726a528bc3d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-sh7372.c | 197 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 197 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +index 8503747a..46466bb1 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +@@ -1467,6 +1467,139 @@ static const unsigned int mmc0_ctrl_1_pins[] = { + static const unsigned int mmc0_ctrl_1_mux[] = { + MMCCMD1_MARK, MMCCLK1_MARK, + }; ++/* - SCIFA0 ----------------------------------------------------------------- */ ++static const unsigned int scifa0_data_pins[] = { ++ /* RXD, TXD */ ++ 153, 152, ++}; ++static const unsigned int scifa0_data_mux[] = { ++ SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, ++}; ++static const unsigned int scifa0_clk_pins[] = { ++ /* SCK */ ++ 156, ++}; ++static const unsigned int scifa0_clk_mux[] = { ++ SCIFA0_SCK_MARK, ++}; ++static const unsigned int scifa0_ctrl_pins[] = { ++ /* RTS, CTS */ ++ 157, 158, ++}; ++static const unsigned int scifa0_ctrl_mux[] = { ++ SCIFA0_RTS_MARK, SCIFA0_CTS_MARK, ++}; ++/* - SCIFA1 ----------------------------------------------------------------- */ ++static const unsigned int scifa1_data_pins[] = { ++ /* RXD, TXD */ ++ 155, 154, ++}; ++static const unsigned int scifa1_data_mux[] = { ++ SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, ++}; ++static const unsigned int scifa1_clk_pins[] = { ++ /* SCK */ ++ 159, ++}; ++static const unsigned int scifa1_clk_mux[] = { ++ SCIFA1_SCK_MARK, ++}; ++static const unsigned int scifa1_ctrl_pins[] = { ++ /* RTS, CTS */ ++ 160, 161, ++}; ++static const unsigned int scifa1_ctrl_mux[] = { ++ SCIFA1_RTS_MARK, SCIFA1_CTS_MARK, ++}; ++/* - SCIFA2 ----------------------------------------------------------------- */ ++static const unsigned int scifa2_data_pins[] = { ++ /* RXD, TXD */ ++ 97, 96, ++}; ++static const unsigned int scifa2_data_mux[] = { ++ SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK, ++}; ++static const unsigned int scifa2_clk_pins[] = { ++ /* SCK */ ++ 98, ++}; ++static const unsigned int scifa2_clk_mux[] = { ++ SCIFA2_SCK1_MARK, ++}; ++static const unsigned int scifa2_ctrl_pins[] = { ++ /* RTS, CTS */ ++ 95, 94, ++}; ++static const unsigned int scifa2_ctrl_mux[] = { ++ SCIFA2_RTS1_MARK, SCIFA2_CTS1_MARK, ++}; ++/* - SCIFA3 ----------------------------------------------------------------- */ ++static const unsigned int scifa3_data_pins[] = { ++ /* RXD, TXD */ ++ 144, 143, ++}; ++static const unsigned int scifa3_data_mux[] = { ++ SCIFA3_RXD_MARK, SCIFA3_TXD_MARK, ++}; ++static const unsigned int scifa3_clk_pins[] = { ++ /* SCK */ ++ 142, ++}; ++static const unsigned int scifa3_clk_mux[] = { ++ SCIFA3_SCK_MARK, ++}; ++static const unsigned int scifa3_ctrl_0_pins[] = { ++ /* RTS, CTS */ ++ 44, 43, ++}; ++static const unsigned int scifa3_ctrl_0_mux[] = { ++ SCIFA3_RTS_44_MARK, SCIFA3_CTS_43_MARK, ++}; ++static const unsigned int scifa3_ctrl_1_pins[] = { ++ /* RTS, CTS */ ++ 141, 140, ++}; ++static const unsigned int scifa3_ctrl_1_mux[] = { ++ SCIFA3_RTS_141_MARK, SCIFA3_CTS_140_MARK, ++}; ++/* - SCIFA4 ----------------------------------------------------------------- */ ++static const unsigned int scifa4_data_pins[] = { ++ /* RXD, TXD */ ++ 5, 6, ++}; ++static const unsigned int scifa4_data_mux[] = { ++ SCIFA4_RXD_MARK, SCIFA4_TXD_MARK, ++}; ++/* - SCIFA5 ----------------------------------------------------------------- */ ++static const unsigned int scifa5_data_pins[] = { ++ /* RXD, TXD */ ++ 8, 12, ++}; ++static const unsigned int scifa5_data_mux[] = { ++ SCIFA5_RXD_MARK, SCIFA5_TXD_MARK, ++}; ++/* - SCIFB ------------------------------------------------------------------ */ ++static const unsigned int scifb_data_pins[] = { ++ /* RXD, TXD */ ++ 166, 165, ++}; ++static const unsigned int scifb_data_mux[] = { ++ SCIFB_RXD_MARK, SCIFB_TXD_MARK, ++}; ++static const unsigned int scifb_clk_pins[] = { ++ /* SCK */ ++ 162, ++}; ++static const unsigned int scifb_clk_mux[] = { ++ SCIFB_SCK_MARK, ++}; ++static const unsigned int scifb_ctrl_pins[] = { ++ /* RTS, CTS */ ++ 163, 164, ++}; ++static const unsigned int scifb_ctrl_mux[] = { ++ SCIFB_RTS_MARK, SCIFB_CTS_MARK, ++}; + /* - SDHI0 ------------------------------------------------------------------ */ + static const unsigned int sdhi0_data1_pins[] = { + /* D0 */ +@@ -1660,6 +1793,24 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(mmc0_data4_1), + SH_PFC_PIN_GROUP(mmc0_data8_1), + SH_PFC_PIN_GROUP(mmc0_ctrl_1), ++ SH_PFC_PIN_GROUP(scifa0_data), ++ SH_PFC_PIN_GROUP(scifa0_clk), ++ SH_PFC_PIN_GROUP(scifa0_ctrl), ++ SH_PFC_PIN_GROUP(scifa1_data), ++ SH_PFC_PIN_GROUP(scifa1_clk), ++ SH_PFC_PIN_GROUP(scifa1_ctrl), ++ SH_PFC_PIN_GROUP(scifa2_data), ++ SH_PFC_PIN_GROUP(scifa2_clk), ++ SH_PFC_PIN_GROUP(scifa2_ctrl), ++ SH_PFC_PIN_GROUP(scifa3_data), ++ SH_PFC_PIN_GROUP(scifa3_clk), ++ SH_PFC_PIN_GROUP(scifa3_ctrl_0), ++ SH_PFC_PIN_GROUP(scifa3_ctrl_1), ++ SH_PFC_PIN_GROUP(scifa4_data), ++ SH_PFC_PIN_GROUP(scifa5_data), ++ SH_PFC_PIN_GROUP(scifb_data), ++ SH_PFC_PIN_GROUP(scifb_clk), ++ SH_PFC_PIN_GROUP(scifb_ctrl), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), +@@ -1814,6 +1965,45 @@ static const char * const mmc0_groups[] = { + "mmc0_ctrl_1", + }; + ++static const char * const scifa0_groups[] = { ++ "scifa0_data", ++ "scifa0_clk", ++ "scifa0_ctrl", ++}; ++ ++static const char * const scifa1_groups[] = { ++ "scifa1_data", ++ "scifa1_clk", ++ "scifa1_ctrl", ++}; ++ ++static const char * const scifa2_groups[] = { ++ "scifa2_data", ++ "scifa2_clk", ++ "scifa2_ctrl", ++}; ++ ++static const char * const scifa3_groups[] = { ++ "scifa3_data", ++ "scifa3_clk", ++ "scifa3_ctrl_0", ++ "scifa3_ctrl_1", ++}; ++ ++static const char * const scifa4_groups[] = { ++ "scifa4_data", ++}; ++ ++static const char * const scifa5_groups[] = { ++ "scifa5_data", ++}; ++ ++static const char * const scifb_groups[] = { ++ "scifb_data", ++ "scifb_clk", ++ "scifb_ctrl", ++}; ++ + static const char * const sdhi0_groups[] = { + "sdhi0_data1", + "sdhi0_data4", +@@ -1845,6 +2035,13 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(keysc), + SH_PFC_FUNCTION(lcd), + SH_PFC_FUNCTION(mmc0), ++ SH_PFC_FUNCTION(scifa0), ++ SH_PFC_FUNCTION(scifa1), ++ SH_PFC_FUNCTION(scifa2), ++ SH_PFC_FUNCTION(scifa3), ++ SH_PFC_FUNCTION(scifa4), ++ SH_PFC_FUNCTION(scifa5), ++ SH_PFC_FUNCTION(scifb), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0107-sh-pfc-sh7372-Add-USB-pin-groups-and-functions.patch b/patches.renesas/0107-sh-pfc-sh7372-Add-USB-pin-groups-and-functions.patch new file mode 100644 index 00000000000..f4491444ce7 --- /dev/null +++ b/patches.renesas/0107-sh-pfc-sh7372-Add-USB-pin-groups-and-functions.patch @@ -0,0 +1,130 @@ +From 0878177b59c3f3427fde6c7c548dfb8611a947fa Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Apr 2013 12:31:08 +0200 +Subject: sh-pfc: sh7372: Add USB pin groups and functions + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit e04662d69b12cc70c4703361bad11a93e7a08046) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-sh7372.c | 82 +++++++++++++++++++++++++++++++++++++ + 1 file changed, 82 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +index 46466bb1..4dc2ccb7 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +@@ -1680,6 +1680,64 @@ static const unsigned int sdhi2_ctrl_pins[] = { + static const unsigned int sdhi2_ctrl_mux[] = { + SDHICMD2_MARK, SDHICLK2_MARK, + }; ++/* - USB0 ------------------------------------------------------------------- */ ++static const unsigned int usb0_vbus_pins[] = { ++ /* VBUS */ ++ 167, ++}; ++static const unsigned int usb0_vbus_mux[] = { ++ VBUS0_0_MARK, ++}; ++static const unsigned int usb0_otg_id_pins[] = { ++ /* IDIN */ ++ 113, ++}; ++static const unsigned int usb0_otg_id_mux[] = { ++ IDIN_0_MARK, ++}; ++static const unsigned int usb0_otg_ctrl_pins[] = { ++ /* PWEN, EXTLP, OVCN, OVCN2 */ ++ 116, 114, 117, 115, ++}; ++static const unsigned int usb0_otg_ctrl_mux[] = { ++ PWEN_0_MARK, EXTLP_0_MARK, OVCN_0_MARK, OVCN2_0_MARK, ++}; ++/* - USB1 ------------------------------------------------------------------- */ ++static const unsigned int usb1_vbus_pins[] = { ++ /* VBUS */ ++ 168, ++}; ++static const unsigned int usb1_vbus_mux[] = { ++ VBUS0_1_MARK, ++}; ++static const unsigned int usb1_otg_id_0_pins[] = { ++ /* IDIN */ ++ 113, ++}; ++static const unsigned int usb1_otg_id_0_mux[] = { ++ IDIN_1_113_MARK, ++}; ++static const unsigned int usb1_otg_id_1_pins[] = { ++ /* IDIN */ ++ 18, ++}; ++static const unsigned int usb1_otg_id_1_mux[] = { ++ IDIN_1_18_MARK, ++}; ++static const unsigned int usb1_otg_ctrl_0_pins[] = { ++ /* PWEN, EXTLP, OVCN, OVCN2 */ ++ 115, 116, 114, 117, 113, ++}; ++static const unsigned int usb1_otg_ctrl_0_mux[] = { ++ PWEN_1_115_MARK, EXTLP_1_MARK, OVCN_1_114_MARK, OVCN2_1_MARK, ++}; ++static const unsigned int usb1_otg_ctrl_1_pins[] = { ++ /* PWEN, EXTLP, OVCN, OVCN2 */ ++ 138, 116, 162, 117, 18, ++}; ++static const unsigned int usb1_otg_ctrl_1_mux[] = { ++ PWEN_1_138_MARK, EXTLP_1_MARK, OVCN_1_162_MARK, OVCN2_1_MARK, ++}; + + static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(bsc_data8), +@@ -1822,6 +1880,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_ctrl), ++ SH_PFC_PIN_GROUP(usb0_vbus), ++ SH_PFC_PIN_GROUP(usb0_otg_id), ++ SH_PFC_PIN_GROUP(usb0_otg_ctrl), ++ SH_PFC_PIN_GROUP(usb1_vbus), ++ SH_PFC_PIN_GROUP(usb1_otg_id_0), ++ SH_PFC_PIN_GROUP(usb1_otg_id_1), ++ SH_PFC_PIN_GROUP(usb1_otg_ctrl_0), ++ SH_PFC_PIN_GROUP(usb1_otg_ctrl_1), + }; + + static const char * const bsc_groups[] = { +@@ -2024,6 +2090,20 @@ static const char * const sdhi2_groups[] = { + "sdhi2_ctrl", + }; + ++static const char * const usb0_groups[] = { ++ "usb0_vbus", ++ "usb0_otg_id", ++ "usb0_otg_ctrl", ++}; ++ ++static const char * const usb1_groups[] = { ++ "usb1_vbus", ++ "usb1_otg_id_0", ++ "usb1_otg_id_1", ++ "usb1_otg_ctrl_0", ++ "usb1_otg_ctrl_1", ++}; ++ + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(bsc), + SH_PFC_FUNCTION(ceu), +@@ -2045,6 +2125,8 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), ++ SH_PFC_FUNCTION(usb0), ++ SH_PFC_FUNCTION(usb1), + }; + + #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0108-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-t.patch b/patches.renesas/0108-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-t.patch new file mode 100644 index 00000000000..7a05c164721 --- /dev/null +++ b/patches.renesas/0108-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-t.patch @@ -0,0 +1,43 @@ +From a813cd8b5610b2835106efa2eadcf23c48e5956b Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Apr 2013 13:29:48 +0200 +Subject: ARM: shmobile: mackerel: Register pinctrl mapping for the ADXL34X + +Replace the GPIO-based ADXL34X pinmux configuration by a pinctrl +mapping. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit cd87d903f12c1baea6caf68e02e21ce7004c79a4) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-mackerel.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c +index fa3407da..d40d9dae 100644 +--- a/arch/arm/mach-shmobile/board-mackerel.c ++++ b/arch/arm/mach-shmobile/board-mackerel.c +@@ -1309,6 +1309,9 @@ static struct i2c_board_info i2c1_devices[] = { + }; + + static const struct pinctrl_map mackerel_pinctrl_map[] = { ++ /* ADXL34X */ ++ PIN_MAP_MUX_GROUP_DEFAULT("1-0053", "pfc-sh7372", ++ "intc_irq21", "intc"), + /* SDHI0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", + "sdhi0_data4", "sdhi0"), +@@ -1460,8 +1463,7 @@ static void __init mackerel_init(void) + gpio_request(GPIO_FN_IRQ7_40, NULL); + irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); + +- /* enable Accelerometer */ +- gpio_request(GPIO_FN_IRQ21, NULL); ++ /* Accelerometer */ + irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH); + + /* SDHI0 PORT172 card-detect IRQ26 */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0109-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-C.patch b/patches.renesas/0109-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-C.patch new file mode 100644 index 00000000000..e8727c5cdbf --- /dev/null +++ b/patches.renesas/0109-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-C.patch @@ -0,0 +1,60 @@ +From e3833ebf917031534bf9de871ca5564cc632b0b3 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Apr 2013 13:29:48 +0200 +Subject: ARM: shmobile: mackerel: Register pinctrl mapping for CEU + +Replace the GPIO-based CEU pinmux configuration by a pinctrl mapping. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 0acbc34c816c95687dda0db61bc4215d8ca67725) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-mackerel.c | 24 +++++++++--------------- + 1 file changed, 9 insertions(+), 15 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c +index d40d9dae..fdd7e3fd 100644 +--- a/arch/arm/mach-shmobile/board-mackerel.c ++++ b/arch/arm/mach-shmobile/board-mackerel.c +@@ -1312,6 +1312,15 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = { + /* ADXL34X */ + PIN_MAP_MUX_GROUP_DEFAULT("1-0053", "pfc-sh7372", + "intc_irq21", "intc"), ++ /* CEU */ ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372", ++ "ceu_data_0_7", "ceu"), ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372", ++ "ceu_clk_0", "ceu"), ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372", ++ "ceu_sync", "ceu"), ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372", ++ "ceu_field", "ceu"), + /* SDHI0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", + "sdhi0_data4", "sdhi0"), +@@ -1497,21 +1506,6 @@ static void __init mackerel_init(void) + gpio_request(GPIO_FN_SCIFA2_TXD1, NULL); + gpio_request(GPIO_FN_SCIFA2_RXD1, NULL); + +- /* CEU */ +- gpio_request(GPIO_FN_VIO_CLK, NULL); +- gpio_request(GPIO_FN_VIO_VD, NULL); +- gpio_request(GPIO_FN_VIO_HD, NULL); +- gpio_request(GPIO_FN_VIO_FIELD, NULL); +- gpio_request(GPIO_FN_VIO_CKO, NULL); +- gpio_request(GPIO_FN_VIO_D7, NULL); +- gpio_request(GPIO_FN_VIO_D6, NULL); +- gpio_request(GPIO_FN_VIO_D5, NULL); +- gpio_request(GPIO_FN_VIO_D4, NULL); +- gpio_request(GPIO_FN_VIO_D3, NULL); +- gpio_request(GPIO_FN_VIO_D2, NULL); +- gpio_request(GPIO_FN_VIO_D1, NULL); +- gpio_request(GPIO_FN_VIO_D0, NULL); +- + /* HDMI */ + gpio_request(GPIO_FN_HDMI_HPD, NULL); + gpio_request(GPIO_FN_HDMI_CEC, NULL); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0110-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-F.patch b/patches.renesas/0110-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-F.patch new file mode 100644 index 00000000000..dca6e463577 --- /dev/null +++ b/patches.renesas/0110-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-F.patch @@ -0,0 +1,67 @@ +From 30e16c9f56ef326f4bb3a8a49a261cbeeb8d991d Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Apr 2013 13:29:48 +0200 +Subject: ARM: shmobile: mackerel: Register pinctrl mapping for FLCTL + +Replace the GPIO-based FLCTL pinmux configuration by a pinctrl mapping. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 7e4f07d73affe680b31ae7178133f98da9eff4fb) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-mackerel.c | 31 +++++++------------------------ + 1 file changed, 7 insertions(+), 24 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c +index fdd7e3fd..955fefd3 100644 +--- a/arch/arm/mach-shmobile/board-mackerel.c ++++ b/arch/arm/mach-shmobile/board-mackerel.c +@@ -1321,6 +1321,13 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = { + "ceu_sync", "ceu"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372", + "ceu_field", "ceu"), ++ /* FLCTL */ ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372", ++ "flctl_data", "flctl"), ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372", ++ "flctl_ce0", "flctl"), ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372", ++ "flctl_ctrl", "flctl"), + /* SDHI0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", + "sdhi0_data4", "sdhi0"), +@@ -1478,30 +1485,6 @@ static void __init mackerel_init(void) + /* SDHI0 PORT172 card-detect IRQ26 */ + gpio_request(GPIO_FN_IRQ26_172, NULL); + +- /* FLCTL */ +- gpio_request(GPIO_FN_D0_NAF0, NULL); +- gpio_request(GPIO_FN_D1_NAF1, NULL); +- gpio_request(GPIO_FN_D2_NAF2, NULL); +- gpio_request(GPIO_FN_D3_NAF3, NULL); +- gpio_request(GPIO_FN_D4_NAF4, NULL); +- gpio_request(GPIO_FN_D5_NAF5, NULL); +- gpio_request(GPIO_FN_D6_NAF6, NULL); +- gpio_request(GPIO_FN_D7_NAF7, NULL); +- gpio_request(GPIO_FN_D8_NAF8, NULL); +- gpio_request(GPIO_FN_D9_NAF9, NULL); +- gpio_request(GPIO_FN_D10_NAF10, NULL); +- gpio_request(GPIO_FN_D11_NAF11, NULL); +- gpio_request(GPIO_FN_D12_NAF12, NULL); +- gpio_request(GPIO_FN_D13_NAF13, NULL); +- gpio_request(GPIO_FN_D14_NAF14, NULL); +- gpio_request(GPIO_FN_D15_NAF15, NULL); +- gpio_request(GPIO_FN_FCE0, NULL); +- gpio_request(GPIO_FN_WE0_FWE, NULL); +- gpio_request(GPIO_FN_FRB, NULL); +- gpio_request(GPIO_FN_A4_FOE, NULL); +- gpio_request(GPIO_FN_A5_FCDE, NULL); +- gpio_request(GPIO_FN_RD_FSC, NULL); +- + /* enable GPS module (GT-720F) */ + gpio_request(GPIO_FN_SCIFA2_TXD1, NULL); + gpio_request(GPIO_FN_SCIFA2_RXD1, NULL); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0111-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-F.patch b/patches.renesas/0111-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-F.patch new file mode 100644 index 00000000000..a4c4295128f --- /dev/null +++ b/patches.renesas/0111-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-F.patch @@ -0,0 +1,62 @@ +From c46f3ef555a88ee588bd75bd40255df32bdbd947 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Apr 2013 13:29:48 +0200 +Subject: ARM: shmobile: mackerel: Register pinctrl mapping for FSI + +Replace the GPIO-based FSI pinmux configuration by a pinctrl mapping. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d39a15793ceded60e4d4f49aab5d6883781a312b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-mackerel.c | 19 ++++++++++++------- + 1 file changed, 12 insertions(+), 7 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c +index 955fefd3..f2e8740f 100644 +--- a/arch/arm/mach-shmobile/board-mackerel.c ++++ b/arch/arm/mach-shmobile/board-mackerel.c +@@ -1328,6 +1328,16 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = { + "flctl_ce0", "flctl"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372", + "flctl_ctrl", "flctl"), ++ /* FSIA (AK4643) */ ++ PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372", ++ "fsia_sclk_in", "fsia"), ++ PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372", ++ "fsia_data_in", "fsia"), ++ PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372", ++ "fsia_data_out", "fsia"), ++ /* FSIB (HDMI) */ ++ PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-sh7372", ++ "fsib_mclk_in", "fsib"), + /* SDHI0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", + "sdhi0_data4", "sdhi0"), +@@ -1446,11 +1456,7 @@ static void __init mackerel_init(void) + gpio_request_pulldown(GPIO_PORT167CR); /* VBUS0_1 pull down */ + gpio_request(GPIO_FN_IDIN_1_113, NULL); + +- /* enable FSI2 port A (ak4643) */ +- gpio_request(GPIO_FN_FSIAIBT, NULL); +- gpio_request(GPIO_FN_FSIAILR, NULL); +- gpio_request(GPIO_FN_FSIAISLD, NULL); +- gpio_request(GPIO_FN_FSIAOSLD, NULL); ++ /* FSI2 port A (ak4643) */ + gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */ + + gpio_request(9, NULL); +@@ -1460,8 +1466,7 @@ static void __init mackerel_init(void) + + intc_set_priority(IRQ_FSI, 3); /* irq priority FSI(3) > SMSC911X(2) */ + +- /* setup FSI2 port B (HDMI) */ +- gpio_request(GPIO_FN_FSIBCK, NULL); ++ /* FSI2 port B (HDMI) */ + __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */ + + /* set SPU2 clock to 119.6 MHz */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0112-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-H.patch b/patches.renesas/0112-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-H.patch new file mode 100644 index 00000000000..cea6312b138 --- /dev/null +++ b/patches.renesas/0112-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-H.patch @@ -0,0 +1,43 @@ +From aeed83cb250c8837ffbba7945a7bb2ea6b4b9f61 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Apr 2013 13:29:48 +0200 +Subject: ARM: shmobile: mackerel: Register pinctrl mapping for HDMI + +Replace the GPIO-based HDMI pinmux configuration by a pinctrl mapping. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit cfced2c8f9472dba8004ee37b4b111b3f876c843) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-mackerel.c | 7 +++---- + 1 file changed, 3 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c +index f2e8740f..e5bcd187 100644 +--- a/arch/arm/mach-shmobile/board-mackerel.c ++++ b/arch/arm/mach-shmobile/board-mackerel.c +@@ -1338,6 +1338,9 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = { + /* FSIB (HDMI) */ + PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-sh7372", + "fsib_mclk_in", "fsib"), ++ /* HDMI */ ++ PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-sh7372", ++ "hdmi", "hdmi"), + /* SDHI0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", + "sdhi0_data4", "sdhi0"), +@@ -1494,10 +1497,6 @@ static void __init mackerel_init(void) + gpio_request(GPIO_FN_SCIFA2_TXD1, NULL); + gpio_request(GPIO_FN_SCIFA2_RXD1, NULL); + +- /* HDMI */ +- gpio_request(GPIO_FN_HDMI_HPD, NULL); +- gpio_request(GPIO_FN_HDMI_CEC, NULL); +- + /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */ + srcr4 = __raw_readl(SRCR4); + __raw_writel(srcr4 | (1 << 13), SRCR4); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0113-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-L.patch b/patches.renesas/0113-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-L.patch new file mode 100644 index 00000000000..00bbcad8232 --- /dev/null +++ b/patches.renesas/0113-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-L.patch @@ -0,0 +1,69 @@ +From 03abe7aeb9935f9684481102eb9b24cd352a5f46 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Apr 2013 13:29:48 +0200 +Subject: ARM: shmobile: mackerel: Register pinctrl mapping for LCD + +Replace the GPIO-based LCD pinmux configuration by a pinctrl mapping. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 845a802cd14b6ef4c791284980a09d887407aeaa) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-mackerel.c | 33 +++++---------------------------- + 1 file changed, 5 insertions(+), 28 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c +index e5bcd187..07eeb55b 100644 +--- a/arch/arm/mach-shmobile/board-mackerel.c ++++ b/arch/arm/mach-shmobile/board-mackerel.c +@@ -1341,6 +1341,11 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = { + /* HDMI */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-sh7372", + "hdmi", "hdmi"), ++ /* LCDC */ ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372", ++ "lcd_data24", "lcd"), ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372", ++ "lcd_sync", "lcd"), + /* SDHI0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", + "sdhi0_data4", "sdhi0"), +@@ -1417,34 +1422,6 @@ static void __init mackerel_init(void) + gpio_request(GPIO_FN_CS5A, NULL); + gpio_request(GPIO_FN_IRQ6_39, NULL); + +- /* LCDC */ +- gpio_request(GPIO_FN_LCDD23, NULL); +- gpio_request(GPIO_FN_LCDD22, NULL); +- gpio_request(GPIO_FN_LCDD21, NULL); +- gpio_request(GPIO_FN_LCDD20, NULL); +- gpio_request(GPIO_FN_LCDD19, NULL); +- gpio_request(GPIO_FN_LCDD18, NULL); +- gpio_request(GPIO_FN_LCDD17, NULL); +- gpio_request(GPIO_FN_LCDD16, NULL); +- gpio_request(GPIO_FN_LCDD15, NULL); +- gpio_request(GPIO_FN_LCDD14, NULL); +- gpio_request(GPIO_FN_LCDD13, NULL); +- gpio_request(GPIO_FN_LCDD12, NULL); +- gpio_request(GPIO_FN_LCDD11, NULL); +- gpio_request(GPIO_FN_LCDD10, NULL); +- gpio_request(GPIO_FN_LCDD9, NULL); +- gpio_request(GPIO_FN_LCDD8, NULL); +- gpio_request(GPIO_FN_LCDD7, NULL); +- gpio_request(GPIO_FN_LCDD6, NULL); +- gpio_request(GPIO_FN_LCDD5, NULL); +- gpio_request(GPIO_FN_LCDD4, NULL); +- gpio_request(GPIO_FN_LCDD3, NULL); +- gpio_request(GPIO_FN_LCDD2, NULL); +- gpio_request(GPIO_FN_LCDD1, NULL); +- gpio_request(GPIO_FN_LCDD0, NULL); +- gpio_request(GPIO_FN_LCDDISP, NULL); +- gpio_request(GPIO_FN_LCDDCK, NULL); +- + /* backlight, off by default */ + gpio_request_one(31, GPIOF_OUT_INIT_LOW, NULL); + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0114-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-S.patch b/patches.renesas/0114-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-S.patch new file mode 100644 index 00000000000..c4c0574895d --- /dev/null +++ b/patches.renesas/0114-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-S.patch @@ -0,0 +1,57 @@ +From 90d4f79fe5509bba6fd781613389f0c66e7e40b4 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Apr 2013 13:29:48 +0200 +Subject: ARM: shmobile: mackerel: Register pinctrl mapping for SCIF + +Replace the GPIO-based SCIF pinmux configuration by a pinctrl mapping. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 0dcea78510eef0bc60406db73746787f1491e190) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-mackerel.c | 14 ++++++-------- + 1 file changed, 6 insertions(+), 8 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c +index 07eeb55b..bd3666bc 100644 +--- a/arch/arm/mach-shmobile/board-mackerel.c ++++ b/arch/arm/mach-shmobile/board-mackerel.c +@@ -1346,6 +1346,12 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = { + "lcd_data24", "lcd"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372", + "lcd_sync", "lcd"), ++ /* SCIFA0 */ ++ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-sh7372", ++ "scifa0_data", "scifa0"), ++ /* SCIFA2 (GT-720F GPS module) */ ++ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh7372", ++ "scifa2_data", "scifa2"), + /* SDHI0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", + "sdhi0_data4", "sdhi0"), +@@ -1414,10 +1420,6 @@ static void __init mackerel_init(void) + ARRAY_SIZE(mackerel_pinctrl_map)); + sh7372_pinmux_init(); + +- /* enable SCIFA0 */ +- gpio_request(GPIO_FN_SCIFA0_TXD, NULL); +- gpio_request(GPIO_FN_SCIFA0_RXD, NULL); +- + /* enable SMSC911X */ + gpio_request(GPIO_FN_CS5A, NULL); + gpio_request(GPIO_FN_IRQ6_39, NULL); +@@ -1470,10 +1472,6 @@ static void __init mackerel_init(void) + /* SDHI0 PORT172 card-detect IRQ26 */ + gpio_request(GPIO_FN_IRQ26_172, NULL); + +- /* enable GPS module (GT-720F) */ +- gpio_request(GPIO_FN_SCIFA2_TXD1, NULL); +- gpio_request(GPIO_FN_SCIFA2_RXD1, NULL); +- + /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */ + srcr4 = __raw_readl(SRCR4); + __raw_writel(srcr4 | (1 << 13), SRCR4); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0115-ARM-shmobile-mackerel-Register-IRQ-pinctrl-mapping-f.patch b/patches.renesas/0115-ARM-shmobile-mackerel-Register-IRQ-pinctrl-mapping-f.patch new file mode 100644 index 00000000000..b800b06fc50 --- /dev/null +++ b/patches.renesas/0115-ARM-shmobile-mackerel-Register-IRQ-pinctrl-mapping-f.patch @@ -0,0 +1,42 @@ +From cc14b25a00e89e6641e3c115f178ae2b1d979409 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Apr 2013 13:29:48 +0200 +Subject: ARM: shmobile: mackerel: Register IRQ pinctrl mapping for SDHI0 + +Replace the GPIO-based SDHI0 IRQ pinmux configuration by a pinctrl +mapping. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 886c5353a821b28939f095ea2394e6d471f11be0) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-mackerel.c | 5 ++--- + 1 file changed, 2 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c +index bd3666bc..4be236d1 100644 +--- a/arch/arm/mach-shmobile/board-mackerel.c ++++ b/arch/arm/mach-shmobile/board-mackerel.c +@@ -1359,6 +1359,8 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = { + "sdhi0_ctrl", "sdhi0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", + "sdhi0_wp", "sdhi0"), ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", ++ "intc_irq26_1", "intc"), + /* SDHI1 */ + #if !IS_ENABLED(CONFIG_MMC_SH_MMCIF) + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372", +@@ -1469,9 +1471,6 @@ static void __init mackerel_init(void) + /* Accelerometer */ + irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH); + +- /* SDHI0 PORT172 card-detect IRQ26 */ +- gpio_request(GPIO_FN_IRQ26_172, NULL); +- + /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */ + srcr4 = __raw_readl(SRCR4); + __raw_writel(srcr4 | (1 << 13), SRCR4); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0116-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-S.patch b/patches.renesas/0116-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-S.patch new file mode 100644 index 00000000000..b5bb47473da --- /dev/null +++ b/patches.renesas/0116-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-S.patch @@ -0,0 +1,46 @@ +From 6f7c2bb37dbf8cb75238a972ced6fd3ff748ef4e Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Apr 2013 13:29:48 +0200 +Subject: ARM: shmobile: mackerel: Register pinctrl mapping for SMSC911x + +Replace the GPIO-based SMSC911x pinmux configuration by a pinctrl +mapping. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 98f2d3645f8c32a35ed7f51639172a1bad1c0dbb) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-mackerel.c | 9 +++++---- + 1 file changed, 5 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c +index 4be236d1..49b66a85 100644 +--- a/arch/arm/mach-shmobile/board-mackerel.c ++++ b/arch/arm/mach-shmobile/board-mackerel.c +@@ -1379,6 +1379,11 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = { + "sdhi2_data4", "sdhi2"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372", + "sdhi2_ctrl", "sdhi2"), ++ /* SMSC911X */ ++ PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372", ++ "bsc_cs5a", "bsc"), ++ PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372", ++ "intc_irq6_0", "intc"), + }; + + #define GPIO_PORT9CR IOMEM(0xE6051009) +@@ -1422,10 +1427,6 @@ static void __init mackerel_init(void) + ARRAY_SIZE(mackerel_pinctrl_map)); + sh7372_pinmux_init(); + +- /* enable SMSC911X */ +- gpio_request(GPIO_FN_CS5A, NULL); +- gpio_request(GPIO_FN_IRQ6_39, NULL); +- + /* backlight, off by default */ + gpio_request_one(31, GPIOF_OUT_INIT_LOW, NULL); + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0117-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-S.patch b/patches.renesas/0117-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-S.patch new file mode 100644 index 00000000000..21e5e2f8754 --- /dev/null +++ b/patches.renesas/0117-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-S.patch @@ -0,0 +1,42 @@ +From 83fb7b63e6d53cb816688e44354e8d4c04a87d89 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Apr 2013 13:29:48 +0200 +Subject: ARM: shmobile: mackerel: Register pinctrl mapping for ST1232 + +Replace the GPIO-based ST1232 pinmux configuration by a pinctrl mapping. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit a4bb48874ed7bc2d27b5ec12082894226db9aa11) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-mackerel.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c +index 49b66a85..83506357 100644 +--- a/arch/arm/mach-shmobile/board-mackerel.c ++++ b/arch/arm/mach-shmobile/board-mackerel.c +@@ -1384,6 +1384,9 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = { + "bsc_cs5a", "bsc"), + PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372", + "intc_irq6_0", "intc"), ++ /* ST1232 */ ++ PIN_MAP_MUX_GROUP_DEFAULT("0-0055", "pfc-sh7372", ++ "intc_irq7_0", "intc"), + }; + + #define GPIO_PORT9CR IOMEM(0xE6051009) +@@ -1465,8 +1468,7 @@ static void __init mackerel_init(void) + gpio_request(GPIO_FN_IRQ9_42, NULL); + irq_set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH); + +- /* enable Touchscreen */ +- gpio_request(GPIO_FN_IRQ7_40, NULL); ++ /* Touchscreen */ + irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); + + /* Accelerometer */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0118-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-T.patch b/patches.renesas/0118-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-T.patch new file mode 100644 index 00000000000..fc132c9c909 --- /dev/null +++ b/patches.renesas/0118-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-T.patch @@ -0,0 +1,43 @@ +From 6e848fd16f34df458bb6bded632de900d310ddfa Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Apr 2013 13:29:48 +0200 +Subject: ARM: shmobile: mackerel: Register pinctrl mapping for TCA6416 + +Replace the GPIO-based TCA6416 pinmux configuration by a pinctrl +mapping. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 47f902899fc81886da88b078d74aec17b0040487) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-mackerel.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c +index 83506357..397e73c4 100644 +--- a/arch/arm/mach-shmobile/board-mackerel.c ++++ b/arch/arm/mach-shmobile/board-mackerel.c +@@ -1387,6 +1387,9 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = { + /* ST1232 */ + PIN_MAP_MUX_GROUP_DEFAULT("0-0055", "pfc-sh7372", + "intc_irq7_0", "intc"), ++ /* TCA6416 */ ++ PIN_MAP_MUX_GROUP_DEFAULT("0-0020", "pfc-sh7372", ++ "intc_irq9_0", "intc"), + }; + + #define GPIO_PORT9CR IOMEM(0xE6051009) +@@ -1464,8 +1467,7 @@ static void __init mackerel_init(void) + clk_put(clk); + } + +- /* enable Keypad */ +- gpio_request(GPIO_FN_IRQ9_42, NULL); ++ /* Keypad */ + irq_set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH); + + /* Touchscreen */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0119-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-U.patch b/patches.renesas/0119-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-U.patch new file mode 100644 index 00000000000..260c86fc60f --- /dev/null +++ b/patches.renesas/0119-ARM-shmobile-mackerel-Register-pinctrl-mapping-for-U.patch @@ -0,0 +1,51 @@ +From 84c124d60f68bd52d579531497ffa4e96734f2c9 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Apr 2013 13:29:48 +0200 +Subject: ARM: shmobile: mackerel: Register pinctrl mapping for USBHS + +Replace the GPIO-based USBHS pinmux configuration by a pinctrl mapping. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit c135190ded645910813d3188469c185c82b13900) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-mackerel.c | 11 ++++++++--- + 1 file changed, 8 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c +index 397e73c4..85f51a84 100644 +--- a/arch/arm/mach-shmobile/board-mackerel.c ++++ b/arch/arm/mach-shmobile/board-mackerel.c +@@ -1390,6 +1390,14 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = { + /* TCA6416 */ + PIN_MAP_MUX_GROUP_DEFAULT("0-0020", "pfc-sh7372", + "intc_irq9_0", "intc"), ++ /* USBHS0 */ ++ PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.0", "pfc-sh7372", ++ "usb0_vbus", "usb0"), ++ /* USBHS1 */ ++ PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372", ++ "usb1_vbus", "usb1"), ++ PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372", ++ "usb1_otg_id_0", "usb1"), + }; + + #define GPIO_PORT9CR IOMEM(0xE6051009) +@@ -1439,13 +1447,10 @@ static void __init mackerel_init(void) + gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ + + /* USBHS0 */ +- gpio_request(GPIO_FN_VBUS0_0, NULL); + gpio_request_pulldown(GPIO_PORT168CR); /* VBUS0_0 pull down */ + + /* USBHS1 */ +- gpio_request(GPIO_FN_VBUS0_1, NULL); + gpio_request_pulldown(GPIO_PORT167CR); /* VBUS0_1 pull down */ +- gpio_request(GPIO_FN_IDIN_1_113, NULL); + + /* FSI2 port A (ak4643) */ + gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0120-ARM-shmobile-ap4evb-Register-pinctrl-mapping-for-CEU.patch b/patches.renesas/0120-ARM-shmobile-ap4evb-Register-pinctrl-mapping-for-CEU.patch new file mode 100644 index 00000000000..6175b14c861 --- /dev/null +++ b/patches.renesas/0120-ARM-shmobile-ap4evb-Register-pinctrl-mapping-for-CEU.patch @@ -0,0 +1,41 @@ +From cffbaf7aaccf22267914d4130c3b50b84da766fc Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Apr 2013 13:29:48 +0200 +Subject: ARM: shmobile: ap4evb: Register pinctrl mapping for CEU + +Replace the GPIO-based CEU pinmux configuration by a pinctrl mapping. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit bdf439f1878925c536533dd908467a3462171c33) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-ap4evb.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c +index 45f78cad..f42e731e 100644 +--- a/arch/arm/mach-shmobile/board-ap4evb.c ++++ b/arch/arm/mach-shmobile/board-ap4evb.c +@@ -1086,6 +1086,9 @@ static struct i2c_board_info i2c1_devices[] = { + + + static const struct pinctrl_map ap4evb_pinctrl_map[] = { ++ /* CEU */ ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372", ++ "ceu_clk_0", "ceu"), + /* MMCIF */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372", + "mmc0_data8_0", "mmc0"), +@@ -1288,8 +1291,6 @@ static void __init ap4evb_init(void) + */ + + /* MIPI-CSI stuff */ +- gpio_request(GPIO_FN_VIO_CKO, NULL); +- + clk = clk_get(NULL, "vck1_clk"); + if (!IS_ERR(clk)) { + clk_set_rate(clk, clk_round_rate(clk, 13000000)); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0121-ARM-shmobile-ap4evb-Register-pinctrl-mapping-for-FSI.patch b/patches.renesas/0121-ARM-shmobile-ap4evb-Register-pinctrl-mapping-for-FSI.patch new file mode 100644 index 00000000000..fd616b2e477 --- /dev/null +++ b/patches.renesas/0121-ARM-shmobile-ap4evb-Register-pinctrl-mapping-for-FSI.patch @@ -0,0 +1,62 @@ +From b76ba88f0eb5f1466e5cc528bffbd57afadacdd0 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Apr 2013 13:29:48 +0200 +Subject: ARM: shmobile: ap4evb: Register pinctrl mapping for FSI + +Replace the GPIO-based FSI pinmux configuration by a pinctrl mapping. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d2e0ca63a892b761d9d87bd709d696c29afb557c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-ap4evb.c | 19 ++++++++++++------- + 1 file changed, 12 insertions(+), 7 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c +index f42e731e..2f036856 100644 +--- a/arch/arm/mach-shmobile/board-ap4evb.c ++++ b/arch/arm/mach-shmobile/board-ap4evb.c +@@ -1089,6 +1089,16 @@ static const struct pinctrl_map ap4evb_pinctrl_map[] = { + /* CEU */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372", + "ceu_clk_0", "ceu"), ++ /* FSIA (AK4643) */ ++ PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372", ++ "fsia_sclk_in", "fsia"), ++ PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372", ++ "fsia_data_in", "fsia"), ++ PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372", ++ "fsia_data_out", "fsia"), ++ /* FSIB (HDMI) */ ++ PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-sh7372", ++ "fsib_mclk_in", "fsib"), + /* MMCIF */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372", + "mmc0_data8_0", "mmc0"), +@@ -1165,11 +1175,7 @@ static void __init ap4evb_init(void) + /* setup USB phy */ + __raw_writew(0x8a0a, IOMEM(0xE6058130)); /* USBCR4 */ + +- /* enable FSI2 port A (ak4643) */ +- gpio_request(GPIO_FN_FSIAIBT, NULL); +- gpio_request(GPIO_FN_FSIAILR, NULL); +- gpio_request(GPIO_FN_FSIAISLD, NULL); +- gpio_request(GPIO_FN_FSIAOSLD, NULL); ++ /* FSI2 port A (ak4643) */ + gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */ + + gpio_request(9, NULL); +@@ -1180,8 +1186,7 @@ static void __init ap4evb_init(void) + /* card detect pin for MMC slot (CN7) */ + gpio_request_one(41, GPIOF_IN, NULL); + +- /* setup FSI2 port B (HDMI) */ +- gpio_request(GPIO_FN_FSIBCK, NULL); ++ /* FSI2 port B (HDMI) */ + __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */ + + /* set SPU2 clock to 119.6 MHz */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0122-ARM-shmobile-ap4evb-Register-pinctrl-mapping-for-HDM.patch b/patches.renesas/0122-ARM-shmobile-ap4evb-Register-pinctrl-mapping-for-HDM.patch new file mode 100644 index 00000000000..ccc237156c1 --- /dev/null +++ b/patches.renesas/0122-ARM-shmobile-ap4evb-Register-pinctrl-mapping-for-HDM.patch @@ -0,0 +1,43 @@ +From 2af865d7f4ab164adf65b7f94f86d1118e99ccac Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Apr 2013 13:29:48 +0200 +Subject: ARM: shmobile: ap4evb: Register pinctrl mapping for HDMI + +Replace the GPIO-based HDMI pinmux configuration by a pinctrl mapping. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d9aa3005e5eed457097a392dcab72ba3fbc55911) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-ap4evb.c | 7 +++---- + 1 file changed, 3 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c +index 2f036856..2dfa235b 100644 +--- a/arch/arm/mach-shmobile/board-ap4evb.c ++++ b/arch/arm/mach-shmobile/board-ap4evb.c +@@ -1099,6 +1099,9 @@ static const struct pinctrl_map ap4evb_pinctrl_map[] = { + /* FSIB (HDMI) */ + PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-sh7372", + "fsib_mclk_in", "fsib"), ++ /* HDMI */ ++ PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-sh7372", ++ "hdmi", "hdmi"), + /* MMCIF */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372", + "mmc0_data8_0", "mmc0"), +@@ -1305,10 +1308,6 @@ static void __init ap4evb_init(void) + + sh7372_add_standard_devices(); + +- /* HDMI */ +- gpio_request(GPIO_FN_HDMI_HPD, NULL); +- gpio_request(GPIO_FN_HDMI_CEC, NULL); +- + /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */ + #define SRCR4 IOMEM(0xe61580bc) + srcr4 = __raw_readl(SRCR4); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0123-ARM-shmobile-ap4evb-Register-pinctrl-mapping-for-KEY.patch b/patches.renesas/0123-ARM-shmobile-ap4evb-Register-pinctrl-mapping-for-KEY.patch new file mode 100644 index 00000000000..26b7758abb4 --- /dev/null +++ b/patches.renesas/0123-ARM-shmobile-ap4evb-Register-pinctrl-mapping-for-KEY.patch @@ -0,0 +1,53 @@ +From 014244fab67e612c267ec6dcaa8fc0c9d20593ab Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Apr 2013 13:29:48 +0200 +Subject: ARM: shmobile: ap4evb: Register pinctrl mapping for KEYSC + +Replace the GPIO-based KEYSC pinmux configuration by a pinctrl mapping. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 6cd49f71a420cfab69e0b208052b7a39f5642262) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-ap4evb.c | 17 +++++------------ + 1 file changed, 5 insertions(+), 12 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c +index 2dfa235b..c7a9efc5 100644 +--- a/arch/arm/mach-shmobile/board-ap4evb.c ++++ b/arch/arm/mach-shmobile/board-ap4evb.c +@@ -1102,6 +1102,11 @@ static const struct pinctrl_map ap4evb_pinctrl_map[] = { + /* HDMI */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-sh7372", + "hdmi", "hdmi"), ++ /* KEYSC */ ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc", "pfc-sh7372", ++ "keysc_in04_0", "keysc"), ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc", "pfc-sh7372", ++ "keysc_out5", "keysc"), + /* MMCIF */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372", + "mmc0_data8_0", "mmc0"), +@@ -1219,18 +1224,6 @@ static void __init ap4evb_init(void) + * IRQ28 for Touch Panel, set dip switches S3, S43 as OFF, ON. + */ + +- /* enable KEYSC */ +- gpio_request(GPIO_FN_KEYOUT0, NULL); +- gpio_request(GPIO_FN_KEYOUT1, NULL); +- gpio_request(GPIO_FN_KEYOUT2, NULL); +- gpio_request(GPIO_FN_KEYOUT3, NULL); +- gpio_request(GPIO_FN_KEYOUT4, NULL); +- gpio_request(GPIO_FN_KEYIN0_136, NULL); +- gpio_request(GPIO_FN_KEYIN1_135, NULL); +- gpio_request(GPIO_FN_KEYIN2_134, NULL); +- gpio_request(GPIO_FN_KEYIN3_133, NULL); +- gpio_request(GPIO_FN_KEYIN4, NULL); +- + /* enable TouchScreen */ + irq_set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW); + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0124-ARM-shmobile-ap4evb-Register-pinctrl-mapping-for-LCD.patch b/patches.renesas/0124-ARM-shmobile-ap4evb-Register-pinctrl-mapping-for-LCD.patch new file mode 100644 index 00000000000..63503dc9d9e --- /dev/null +++ b/patches.renesas/0124-ARM-shmobile-ap4evb-Register-pinctrl-mapping-for-LCD.patch @@ -0,0 +1,65 @@ +From a3f1d7e921e56f833ad954d1917a6dbb633f68f0 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Apr 2013 13:29:48 +0200 +Subject: ARM: shmobile: ap4evb: Register pinctrl mapping for LCD + +Replace the GPIO-based LCD pinmux configuration by a pinctrl mapping. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 8b53e595524ba7298d8b9a91f408884de8a31fe0) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-ap4evb.c | 29 +++++++---------------------- + 1 file changed, 7 insertions(+), 22 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c +index c7a9efc5..c6e1e448 100644 +--- a/arch/arm/mach-shmobile/board-ap4evb.c ++++ b/arch/arm/mach-shmobile/board-ap4evb.c +@@ -1107,6 +1107,13 @@ static const struct pinctrl_map ap4evb_pinctrl_map[] = { + "keysc_in04_0", "keysc"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc", "pfc-sh7372", + "keysc_out5", "keysc"), ++#ifndef CONFIG_AP4EVB_QHD ++ /* LCDC */ ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372", ++ "lcd_data18", "lcd"), ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372", ++ "lcd_sync", "lcd"), ++#endif + /* MMCIF */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372", + "mmc0_data8_0", "mmc0"), +@@ -1245,28 +1252,6 @@ static void __init ap4evb_init(void) + * For WVGA Panel (18-bit RGB, CONFIG_AP4EVB_WVGA=y) and + * IRQ7 for Touch Panel, set dip switches S3, S43 to ON, OFF. + */ +- +- gpio_request(GPIO_FN_LCDD17, NULL); +- gpio_request(GPIO_FN_LCDD16, NULL); +- gpio_request(GPIO_FN_LCDD15, NULL); +- gpio_request(GPIO_FN_LCDD14, NULL); +- gpio_request(GPIO_FN_LCDD13, NULL); +- gpio_request(GPIO_FN_LCDD12, NULL); +- gpio_request(GPIO_FN_LCDD11, NULL); +- gpio_request(GPIO_FN_LCDD10, NULL); +- gpio_request(GPIO_FN_LCDD9, NULL); +- gpio_request(GPIO_FN_LCDD8, NULL); +- gpio_request(GPIO_FN_LCDD7, NULL); +- gpio_request(GPIO_FN_LCDD6, NULL); +- gpio_request(GPIO_FN_LCDD5, NULL); +- gpio_request(GPIO_FN_LCDD4, NULL); +- gpio_request(GPIO_FN_LCDD3, NULL); +- gpio_request(GPIO_FN_LCDD2, NULL); +- gpio_request(GPIO_FN_LCDD1, NULL); +- gpio_request(GPIO_FN_LCDD0, NULL); +- gpio_request(GPIO_FN_LCDDISP, NULL); +- gpio_request(GPIO_FN_LCDDCK, NULL); +- + gpio_request_one(189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */ + gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0125-ARM-shmobile-ap4evb-Register-pinctrl-mapping-for-SCI.patch b/patches.renesas/0125-ARM-shmobile-ap4evb-Register-pinctrl-mapping-for-SCI.patch new file mode 100644 index 00000000000..a989c336394 --- /dev/null +++ b/patches.renesas/0125-ARM-shmobile-ap4evb-Register-pinctrl-mapping-for-SCI.patch @@ -0,0 +1,43 @@ +From 1d40a68cded35f3569b25b95a607a4d8471e5db1 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Apr 2013 13:29:48 +0200 +Subject: ARM: shmobile: ap4evb: Register pinctrl mapping for SCIF + +Replace the GPIO-based SCIF pinmux configuration by a pinctrl mapping. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 09f2780de9fe5838b1b21d79897676e2b0d54e00) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-ap4evb.c | 7 +++---- + 1 file changed, 3 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c +index c6e1e448..31639832 100644 +--- a/arch/arm/mach-shmobile/board-ap4evb.c ++++ b/arch/arm/mach-shmobile/board-ap4evb.c +@@ -1119,6 +1119,9 @@ static const struct pinctrl_map ap4evb_pinctrl_map[] = { + "mmc0_data8_0", "mmc0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372", + "mmc0_ctrl_0", "mmc0"), ++ /* SCIFA0 */ ++ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-sh7372", ++ "scifa0_data", "scifa0"), + /* SDHI0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", + "sdhi0_data4", "sdhi0"), +@@ -1165,10 +1168,6 @@ static void __init ap4evb_init(void) + ARRAY_SIZE(ap4evb_pinctrl_map)); + sh7372_pinmux_init(); + +- /* enable SCIFA0 */ +- gpio_request(GPIO_FN_SCIFA0_TXD, NULL); +- gpio_request(GPIO_FN_SCIFA0_RXD, NULL); +- + /* enable SMSC911X */ + gpio_request(GPIO_FN_CS5A, NULL); + gpio_request(GPIO_FN_IRQ6_39, NULL); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0126-ARM-shmobile-ap4evb-Register-pinctrl-mapping-for-SMS.patch b/patches.renesas/0126-ARM-shmobile-ap4evb-Register-pinctrl-mapping-for-SMS.patch new file mode 100644 index 00000000000..a6e51ed9953 --- /dev/null +++ b/patches.renesas/0126-ARM-shmobile-ap4evb-Register-pinctrl-mapping-for-SMS.patch @@ -0,0 +1,46 @@ +From 87698f9c46d9095ce727a5f9a3782a52513680ea Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Apr 2013 13:29:48 +0200 +Subject: ARM: shmobile: ap4evb: Register pinctrl mapping for SMSC911x + +Replace the GPIO-based SMSC911x pinmux configuration by a pinctrl +mapping. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 5436c2b9b48992349a1fb26dfd72a08c984ccba8) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-ap4evb.c | 9 +++++---- + 1 file changed, 5 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c +index 31639832..9ee8bcd0 100644 +--- a/arch/arm/mach-shmobile/board-ap4evb.c ++++ b/arch/arm/mach-shmobile/board-ap4evb.c +@@ -1136,6 +1136,11 @@ static const struct pinctrl_map ap4evb_pinctrl_map[] = { + "sdhi1_data4", "sdhi1"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372", + "sdhi1_ctrl", "sdhi1"), ++ /* SMSC911X */ ++ PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372", ++ "bsc_cs5a", "bsc"), ++ PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372", ++ "intc_irq6_0", "intc"), + }; + + #define GPIO_PORT9CR IOMEM(0xE6051009) +@@ -1168,10 +1173,6 @@ static void __init ap4evb_init(void) + ARRAY_SIZE(ap4evb_pinctrl_map)); + sh7372_pinmux_init(); + +- /* enable SMSC911X */ +- gpio_request(GPIO_FN_CS5A, NULL); +- gpio_request(GPIO_FN_IRQ6_39, NULL); +- + /* enable Debug switch (S6) */ + gpio_request_one(32, GPIOF_IN | GPIOF_EXPORT, NULL); + gpio_request_one(33, GPIOF_IN | GPIOF_EXPORT, NULL); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0127-ARM-shmobile-ap4evb-Simplify-tsc2007-pen-state-read-.patch b/patches.renesas/0127-ARM-shmobile-ap4evb-Simplify-tsc2007-pen-state-read-.patch new file mode 100644 index 00000000000..eab8d837cf3 --- /dev/null +++ b/patches.renesas/0127-ARM-shmobile-ap4evb-Simplify-tsc2007-pen-state-read-.patch @@ -0,0 +1,49 @@ +From f29ee235b83d0bf497ef1ff459f2cd23c23a9167 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Sun, 21 Apr 2013 18:56:15 +0200 +Subject: ARM: shmobile: ap4evb: Simplify tsc2007 pen state read function + +The pen state is retrieved by reading the state of a pin used as an IRQ. +There's no need to reconfigure the pin as a pure GPIO, as the IRQ pin +state can be read. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 4a666a783b0bb989afe87686f80c94d6ac1897a8) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-ap4evb.c | 13 ++----------- + 1 file changed, 2 insertions(+), 11 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c +index 9ee8bcd0..0109bb3c 100644 +--- a/arch/arm/mach-shmobile/board-ap4evb.c ++++ b/arch/arm/mach-shmobile/board-ap4evb.c +@@ -1037,22 +1037,13 @@ out: + #define IRQ7 evt2irq(0x02e0) /* IRQ7A */ + static int ts_get_pendown_state(void) + { +- int val; +- +- gpio_free(GPIO_TSC_IRQ); +- +- gpio_request_one(GPIO_TSC_PORT, GPIOF_IN, NULL); +- +- val = gpio_get_value(GPIO_TSC_PORT); +- +- gpio_request(GPIO_TSC_IRQ, NULL); +- +- return !val; ++ return !gpio_get_value(GPIO_TSC_PORT); + } + + static int ts_init(void) + { + gpio_request(GPIO_TSC_IRQ, NULL); ++ gpio_request_one(GPIO_TSC_PORT, GPIOF_IN, NULL); + + return 0; + } +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0128-ARM-shmobile-ap4evb-Register-pinctrl-mapping-for-TSC.patch b/patches.renesas/0128-ARM-shmobile-ap4evb-Register-pinctrl-mapping-for-TSC.patch new file mode 100644 index 00000000000..9443c23eec6 --- /dev/null +++ b/patches.renesas/0128-ARM-shmobile-ap4evb-Register-pinctrl-mapping-for-TSC.patch @@ -0,0 +1,57 @@ +From 37fa124dd782f44beb3806f6955b021138b00416 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Apr 2013 13:29:48 +0200 +Subject: ARM: shmobile: ap4evb: Register pinctrl mapping for TSC2007 + +Replace the GPIO-based TSC2007 pinmux configuration by a pinctrl +mapping. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 119612d2f930e09a571a73fb6944f90571f494d5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-ap4evb.c | 11 ++++++++--- + 1 file changed, 8 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c +index 0109bb3c..152a5f72 100644 +--- a/arch/arm/mach-shmobile/board-ap4evb.c ++++ b/arch/arm/mach-shmobile/board-ap4evb.c +@@ -1026,10 +1026,8 @@ out: + + /* TouchScreen */ + #ifdef CONFIG_AP4EVB_QHD +-# define GPIO_TSC_IRQ GPIO_FN_IRQ28_123 + # define GPIO_TSC_PORT 123 + #else /* WVGA */ +-# define GPIO_TSC_IRQ GPIO_FN_IRQ7_40 + # define GPIO_TSC_PORT 40 + #endif + +@@ -1042,7 +1040,6 @@ static int ts_get_pendown_state(void) + + static int ts_init(void) + { +- gpio_request(GPIO_TSC_IRQ, NULL); + gpio_request_one(GPIO_TSC_PORT, GPIOF_IN, NULL); + + return 0; +@@ -1132,6 +1129,14 @@ static const struct pinctrl_map ap4evb_pinctrl_map[] = { + "bsc_cs5a", "bsc"), + PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372", + "intc_irq6_0", "intc"), ++ /* TSC2007 */ ++#ifdef CONFIG_AP4EVB_QHD ++ PIN_MAP_MUX_GROUP_DEFAULT("1-0048", "pfc-sh7372", ++ "intc_irq28_0", "intc"), ++#else /* WVGA */ ++ PIN_MAP_MUX_GROUP_DEFAULT("1-0048", "pfc-sh7372", ++ "intc_irq7_0", "intc"), ++#endif + }; + + #define GPIO_PORT9CR IOMEM(0xE6051009) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0129-ARM-shmobile-ap4evb-Register-pinctrl-mapping-for-USB.patch b/patches.renesas/0129-ARM-shmobile-ap4evb-Register-pinctrl-mapping-for-USB.patch new file mode 100644 index 00000000000..ea6d309c8c2 --- /dev/null +++ b/patches.renesas/0129-ARM-shmobile-ap4evb-Register-pinctrl-mapping-for-USB.patch @@ -0,0 +1,51 @@ +From 9caefd8d6cfd68d633bf2a4055ef6084c0111987 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Apr 2013 13:29:48 +0200 +Subject: ARM: shmobile: ap4evb: Register pinctrl mapping for USBHS + +Replace the GPIO-based USBHS pinmux configuration by a pinctrl mapping. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 025cc6ec8b655a700718e836e8b7a1d5ae298efc) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-ap4evb.c | 15 +++++++-------- + 1 file changed, 7 insertions(+), 8 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c +index 152a5f72..297bf5ee 100644 +--- a/arch/arm/mach-shmobile/board-ap4evb.c ++++ b/arch/arm/mach-shmobile/board-ap4evb.c +@@ -1137,6 +1137,13 @@ static const struct pinctrl_map ap4evb_pinctrl_map[] = { + PIN_MAP_MUX_GROUP_DEFAULT("1-0048", "pfc-sh7372", + "intc_irq7_0", "intc"), + #endif ++ /* USBHS1 */ ++ PIN_MAP_MUX_GROUP_DEFAULT("r8a66597_hcd.1", "pfc-sh7372", ++ "usb1_vbus", "usb1"), ++ PIN_MAP_MUX_GROUP_DEFAULT("r8a66597_hcd.1", "pfc-sh7372", ++ "usb1_otg_id_0", "usb1"), ++ PIN_MAP_MUX_GROUP_DEFAULT("r8a66597_hcd.1", "pfc-sh7372", ++ "usb1_otg_ctrl_0", "usb1"), + }; + + #define GPIO_PORT9CR IOMEM(0xE6051009) +@@ -1175,14 +1182,6 @@ static void __init ap4evb_init(void) + gpio_request_one(34, GPIOF_IN | GPIOF_EXPORT, NULL); + gpio_request_one(35, GPIOF_IN | GPIOF_EXPORT, NULL); + +- /* USB enable */ +- gpio_request(GPIO_FN_VBUS0_1, NULL); +- gpio_request(GPIO_FN_IDIN_1_18, NULL); +- gpio_request(GPIO_FN_PWEN_1_115, NULL); +- gpio_request(GPIO_FN_OVCN_1_114, NULL); +- gpio_request(GPIO_FN_EXTLP_1, NULL); +- gpio_request(GPIO_FN_OVCN2_1, NULL); +- + /* setup USB phy */ + __raw_writew(0x8a0a, IOMEM(0xE6058130)); /* USBCR4 */ + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0130-sh-pfc-sh7372-Replace-GPIO_PORTx-enum-with-GPIO-port.patch b/patches.renesas/0130-sh-pfc-sh7372-Replace-GPIO_PORTx-enum-with-GPIO-port.patch new file mode 100644 index 00000000000..2feedf50cda --- /dev/null +++ b/patches.renesas/0130-sh-pfc-sh7372-Replace-GPIO_PORTx-enum-with-GPIO-port.patch @@ -0,0 +1,109 @@ +From 2098bea3dd118fbb44d8b6b9a28d0012f7c85695 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 22 Apr 2013 00:02:06 +0200 +Subject: sh-pfc: sh7372: Replace GPIO_PORTx enum with GPIO port numbers + +The PFC GPIO API implementation moved to using port numbers. Replace all +GPIO_PORTx enum usage with the corresponding port number. The GPIO_PORTx +enum values are identical to the port number on this platform. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 4e65c958d353d3cf1759d301b806f89cb41c142e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-sh7372.c | 71 ++++++++++++++++++++----------------- + 1 file changed, 39 insertions(+), 32 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +index 4dc2ccb7..70477ce2 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +@@ -34,6 +34,13 @@ + PORT_10(fn, pfx##16, sfx), PORT_10(fn, pfx##17, sfx), \ + PORT_10(fn, pfx##18, sfx), PORT_1(fn, pfx##190, sfx) + ++#undef _GPIO_PORT ++#define _GPIO_PORT(gpio, sfx) \ ++ [gpio] = { \ ++ .name = __stringify(PORT##gpio), \ ++ .enum_id = PORT##gpio##_DATA, \ ++ } ++ + #define IRQC_PIN_MUX(irq, pin) \ + static const unsigned int intc_irq##irq##_pins[] = { \ + pin, \ +@@ -2771,38 +2778,38 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { + #define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5)) + #define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5)) + static const struct pinmux_irq pinmux_irqs[] = { +- PINMUX_IRQ(EXT_IRQ16L(0), GPIO_PORT6, GPIO_PORT162), +- PINMUX_IRQ(EXT_IRQ16L(1), GPIO_PORT12), +- PINMUX_IRQ(EXT_IRQ16L(2), GPIO_PORT4, GPIO_PORT5), +- PINMUX_IRQ(EXT_IRQ16L(3), GPIO_PORT8, GPIO_PORT16), +- PINMUX_IRQ(EXT_IRQ16L(4), GPIO_PORT17, GPIO_PORT163), +- PINMUX_IRQ(EXT_IRQ16L(5), GPIO_PORT18), +- PINMUX_IRQ(EXT_IRQ16L(6), GPIO_PORT39, GPIO_PORT164), +- PINMUX_IRQ(EXT_IRQ16L(7), GPIO_PORT40, GPIO_PORT167), +- PINMUX_IRQ(EXT_IRQ16L(8), GPIO_PORT41, GPIO_PORT168), +- PINMUX_IRQ(EXT_IRQ16L(9), GPIO_PORT42, GPIO_PORT169), +- PINMUX_IRQ(EXT_IRQ16L(10), GPIO_PORT65), +- PINMUX_IRQ(EXT_IRQ16L(11), GPIO_PORT67), +- PINMUX_IRQ(EXT_IRQ16L(12), GPIO_PORT80, GPIO_PORT137), +- PINMUX_IRQ(EXT_IRQ16L(13), GPIO_PORT81, GPIO_PORT145), +- PINMUX_IRQ(EXT_IRQ16L(14), GPIO_PORT82, GPIO_PORT146), +- PINMUX_IRQ(EXT_IRQ16L(15), GPIO_PORT83, GPIO_PORT147), +- PINMUX_IRQ(EXT_IRQ16H(16), GPIO_PORT84, GPIO_PORT170), +- PINMUX_IRQ(EXT_IRQ16H(17), GPIO_PORT85), +- PINMUX_IRQ(EXT_IRQ16H(18), GPIO_PORT86), +- PINMUX_IRQ(EXT_IRQ16H(19), GPIO_PORT87), +- PINMUX_IRQ(EXT_IRQ16H(20), GPIO_PORT92), +- PINMUX_IRQ(EXT_IRQ16H(21), GPIO_PORT93), +- PINMUX_IRQ(EXT_IRQ16H(22), GPIO_PORT94), +- PINMUX_IRQ(EXT_IRQ16H(23), GPIO_PORT95), +- PINMUX_IRQ(EXT_IRQ16H(24), GPIO_PORT112), +- PINMUX_IRQ(EXT_IRQ16H(25), GPIO_PORT119), +- PINMUX_IRQ(EXT_IRQ16H(26), GPIO_PORT121, GPIO_PORT172), +- PINMUX_IRQ(EXT_IRQ16H(27), GPIO_PORT122, GPIO_PORT180), +- PINMUX_IRQ(EXT_IRQ16H(28), GPIO_PORT123, GPIO_PORT181), +- PINMUX_IRQ(EXT_IRQ16H(29), GPIO_PORT129, GPIO_PORT182), +- PINMUX_IRQ(EXT_IRQ16H(30), GPIO_PORT130, GPIO_PORT183), +- PINMUX_IRQ(EXT_IRQ16H(31), GPIO_PORT138, GPIO_PORT184), ++ PINMUX_IRQ(EXT_IRQ16L(0), 6, 162), ++ PINMUX_IRQ(EXT_IRQ16L(1), 12), ++ PINMUX_IRQ(EXT_IRQ16L(2), 4, 5), ++ PINMUX_IRQ(EXT_IRQ16L(3), 8, 16), ++ PINMUX_IRQ(EXT_IRQ16L(4), 17, 163), ++ PINMUX_IRQ(EXT_IRQ16L(5), 18), ++ PINMUX_IRQ(EXT_IRQ16L(6), 39, 164), ++ PINMUX_IRQ(EXT_IRQ16L(7), 40, 167), ++ PINMUX_IRQ(EXT_IRQ16L(8), 41, 168), ++ PINMUX_IRQ(EXT_IRQ16L(9), 42, 169), ++ PINMUX_IRQ(EXT_IRQ16L(10), 65), ++ PINMUX_IRQ(EXT_IRQ16L(11), 67), ++ PINMUX_IRQ(EXT_IRQ16L(12), 80, 137), ++ PINMUX_IRQ(EXT_IRQ16L(13), 81, 145), ++ PINMUX_IRQ(EXT_IRQ16L(14), 82, 146), ++ PINMUX_IRQ(EXT_IRQ16L(15), 83, 147), ++ PINMUX_IRQ(EXT_IRQ16H(16), 84, 170), ++ PINMUX_IRQ(EXT_IRQ16H(17), 85), ++ PINMUX_IRQ(EXT_IRQ16H(18), 86), ++ PINMUX_IRQ(EXT_IRQ16H(19), 87), ++ PINMUX_IRQ(EXT_IRQ16H(20), 92), ++ PINMUX_IRQ(EXT_IRQ16H(21), 93), ++ PINMUX_IRQ(EXT_IRQ16H(22), 94), ++ PINMUX_IRQ(EXT_IRQ16H(23), 95), ++ PINMUX_IRQ(EXT_IRQ16H(24), 112), ++ PINMUX_IRQ(EXT_IRQ16H(25), 119), ++ PINMUX_IRQ(EXT_IRQ16H(26), 121, 172), ++ PINMUX_IRQ(EXT_IRQ16H(27), 122, 180), ++ PINMUX_IRQ(EXT_IRQ16H(28), 123, 181), ++ PINMUX_IRQ(EXT_IRQ16H(29), 129, 182), ++ PINMUX_IRQ(EXT_IRQ16H(30), 130, 183), ++ PINMUX_IRQ(EXT_IRQ16H(31), 138, 184), + }; + + const struct sh_pfc_soc_info sh7372_pinmux_info = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0131-sh-pfc-sh7372-Remove-function-GPIOs.patch b/patches.renesas/0131-sh-pfc-sh7372-Remove-function-GPIOs.patch new file mode 100644 index 00000000000..cfea5b1a0ea --- /dev/null +++ b/patches.renesas/0131-sh-pfc-sh7372-Remove-function-GPIOs.patch @@ -0,0 +1,283 @@ +From 5bddbe400c1e586658038b0f338ebd1ccb437dcc Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 22 Apr 2013 00:05:16 +0200 +Subject: sh-pfc: sh7372: Remove function GPIOs + +No sh7372 platform use the function GPIOs API. Remove it. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 15dba8a4541be779d8cf1993d2d7eca3dc5aae7b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-sh7372.c | 247 ------------------------------------ + 1 file changed, 247 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +index 70477ce2..94960670 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +@@ -2136,250 +2136,6 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(usb1), + }; + +-#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) +- +-static const struct pinmux_func pinmux_func_gpios[] = { +- /* IRQ */ +- GPIO_FN(IRQ0_6), GPIO_FN(IRQ0_162), GPIO_FN(IRQ1), +- GPIO_FN(IRQ2_4), GPIO_FN(IRQ2_5), GPIO_FN(IRQ3_8), +- GPIO_FN(IRQ3_16), GPIO_FN(IRQ4_17), GPIO_FN(IRQ4_163), +- GPIO_FN(IRQ5), GPIO_FN(IRQ6_39), GPIO_FN(IRQ6_164), +- GPIO_FN(IRQ7_40), GPIO_FN(IRQ7_167), GPIO_FN(IRQ8_41), +- GPIO_FN(IRQ8_168), GPIO_FN(IRQ9_42), GPIO_FN(IRQ9_169), +- GPIO_FN(IRQ10), GPIO_FN(IRQ11), GPIO_FN(IRQ12_80), +- GPIO_FN(IRQ12_137), GPIO_FN(IRQ13_81), GPIO_FN(IRQ13_145), +- GPIO_FN(IRQ14_82), GPIO_FN(IRQ14_146), GPIO_FN(IRQ15_83), +- GPIO_FN(IRQ15_147), GPIO_FN(IRQ16_84), GPIO_FN(IRQ16_170), +- GPIO_FN(IRQ17), GPIO_FN(IRQ18), GPIO_FN(IRQ19), +- GPIO_FN(IRQ20), GPIO_FN(IRQ21), GPIO_FN(IRQ22), +- GPIO_FN(IRQ23), GPIO_FN(IRQ24), GPIO_FN(IRQ25), +- GPIO_FN(IRQ26_121), GPIO_FN(IRQ26_172), GPIO_FN(IRQ27_122), +- GPIO_FN(IRQ27_180), GPIO_FN(IRQ28_123), GPIO_FN(IRQ28_181), +- GPIO_FN(IRQ29_129), GPIO_FN(IRQ29_182), GPIO_FN(IRQ30_130), +- GPIO_FN(IRQ30_183), GPIO_FN(IRQ31_138), GPIO_FN(IRQ31_184), +- +- /* MSIOF0 */ +- GPIO_FN(MSIOF0_TSYNC), GPIO_FN(MSIOF0_TSCK), GPIO_FN(MSIOF0_RXD), +- GPIO_FN(MSIOF0_RSCK), GPIO_FN(MSIOF0_RSYNC), GPIO_FN(MSIOF0_MCK0), +- GPIO_FN(MSIOF0_MCK1), GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), +- GPIO_FN(MSIOF0_TXD), +- +- /* MSIOF1 */ +- GPIO_FN(MSIOF1_TSCK_39), GPIO_FN(MSIOF1_TSCK_88), +- GPIO_FN(MSIOF1_TSYNC_40), GPIO_FN(MSIOF1_TSYNC_89), +- GPIO_FN(MSIOF1_TXD_41), GPIO_FN(MSIOF1_TXD_90), +- GPIO_FN(MSIOF1_RXD_42), GPIO_FN(MSIOF1_RXD_91), +- GPIO_FN(MSIOF1_SS1_43), GPIO_FN(MSIOF1_SS1_92), +- GPIO_FN(MSIOF1_SS2_44), GPIO_FN(MSIOF1_SS2_93), +- GPIO_FN(MSIOF1_RSCK), GPIO_FN(MSIOF1_RSYNC), +- GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1), +- +- /* MSIOF2 */ +- GPIO_FN(MSIOF2_RSCK), GPIO_FN(MSIOF2_RSYNC), GPIO_FN(MSIOF2_MCK0), +- GPIO_FN(MSIOF2_MCK1), GPIO_FN(MSIOF2_SS1), GPIO_FN(MSIOF2_SS2), +- GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_TSCK), GPIO_FN(MSIOF2_RXD), +- GPIO_FN(MSIOF2_TXD), +- +- /* BBIF1 */ +- GPIO_FN(BBIF1_RXD), GPIO_FN(BBIF1_TSYNC), GPIO_FN(BBIF1_TSCK), +- GPIO_FN(BBIF1_TXD), GPIO_FN(BBIF1_RSCK), GPIO_FN(BBIF1_RSYNC), +- GPIO_FN(BBIF1_FLOW), GPIO_FN(BB_RX_FLOW_N), +- +- /* BBIF2 */ +- GPIO_FN(BBIF2_TSCK1), GPIO_FN(BBIF2_TSYNC1), +- GPIO_FN(BBIF2_TXD1), GPIO_FN(BBIF2_RXD), +- +- /* FSI */ +- GPIO_FN(FSIACK), GPIO_FN(FSIBCK), GPIO_FN(FSIAILR), +- GPIO_FN(FSIAIBT), GPIO_FN(FSIAISLD), GPIO_FN(FSIAOMC), +- GPIO_FN(FSIAOLR), GPIO_FN(FSIAOBT), GPIO_FN(FSIAOSLD), +- GPIO_FN(FSIASPDIF_11), GPIO_FN(FSIASPDIF_15), +- +- /* FMSI */ +- GPIO_FN(FMSOCK), GPIO_FN(FMSOOLR), GPIO_FN(FMSIOLR), +- GPIO_FN(FMSOOBT), GPIO_FN(FMSIOBT), GPIO_FN(FMSOSLD), +- GPIO_FN(FMSOILR), GPIO_FN(FMSIILR), GPIO_FN(FMSOIBT), +- GPIO_FN(FMSIIBT), GPIO_FN(FMSISLD), GPIO_FN(FMSICK), +- +- /* SCIFA0 */ +- GPIO_FN(SCIFA0_TXD), GPIO_FN(SCIFA0_RXD), GPIO_FN(SCIFA0_SCK), +- GPIO_FN(SCIFA0_RTS), GPIO_FN(SCIFA0_CTS), +- +- /* SCIFA1 */ +- GPIO_FN(SCIFA1_TXD), GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_SCK), +- GPIO_FN(SCIFA1_RTS), GPIO_FN(SCIFA1_CTS), +- +- /* SCIFA2 */ +- GPIO_FN(SCIFA2_CTS1), GPIO_FN(SCIFA2_RTS1), GPIO_FN(SCIFA2_TXD1), +- GPIO_FN(SCIFA2_RXD1), GPIO_FN(SCIFA2_SCK1), +- +- /* SCIFA3 */ +- GPIO_FN(SCIFA3_CTS_43), GPIO_FN(SCIFA3_CTS_140), +- GPIO_FN(SCIFA3_RTS_44), GPIO_FN(SCIFA3_RTS_141), +- GPIO_FN(SCIFA3_SCK), GPIO_FN(SCIFA3_TXD), +- GPIO_FN(SCIFA3_RXD), +- +- /* SCIFA4 */ +- GPIO_FN(SCIFA4_RXD), GPIO_FN(SCIFA4_TXD), +- +- /* SCIFA5 */ +- GPIO_FN(SCIFA5_RXD), GPIO_FN(SCIFA5_TXD), +- +- /* SCIFB */ +- GPIO_FN(SCIFB_SCK), GPIO_FN(SCIFB_RTS), GPIO_FN(SCIFB_CTS), +- GPIO_FN(SCIFB_TXD), GPIO_FN(SCIFB_RXD), +- +- /* CEU */ +- GPIO_FN(VIO_HD), GPIO_FN(VIO_CKO1), GPIO_FN(VIO_CKO2), +- GPIO_FN(VIO_VD), GPIO_FN(VIO_CLK), GPIO_FN(VIO_FIELD), +- GPIO_FN(VIO_CKO), GPIO_FN(VIO_D0), GPIO_FN(VIO_D1), +- GPIO_FN(VIO_D2), GPIO_FN(VIO_D3), GPIO_FN(VIO_D4), +- GPIO_FN(VIO_D5), GPIO_FN(VIO_D6), GPIO_FN(VIO_D7), +- GPIO_FN(VIO_D8), GPIO_FN(VIO_D9), GPIO_FN(VIO_D10), +- GPIO_FN(VIO_D11), GPIO_FN(VIO_D12), GPIO_FN(VIO_D13), +- GPIO_FN(VIO_D14), GPIO_FN(VIO_D15), +- +- /* USB0 */ +- GPIO_FN(IDIN_0), GPIO_FN(EXTLP_0), GPIO_FN(OVCN2_0), +- GPIO_FN(PWEN_0), GPIO_FN(OVCN_0), GPIO_FN(VBUS0_0), +- +- /* USB1 */ +- GPIO_FN(IDIN_1_18), GPIO_FN(IDIN_1_113), +- GPIO_FN(OVCN_1_114), GPIO_FN(OVCN_1_162), +- GPIO_FN(PWEN_1_115), GPIO_FN(PWEN_1_138), +- GPIO_FN(EXTLP_1), GPIO_FN(OVCN2_1), +- GPIO_FN(VBUS0_1), +- +- /* GPIO */ +- GPIO_FN(GPI0), GPIO_FN(GPI1), GPIO_FN(GPO0), GPIO_FN(GPO1), +- +- /* BSC */ +- GPIO_FN(BS), GPIO_FN(WE1), GPIO_FN(CKO), +- GPIO_FN(WAIT), GPIO_FN(RDWR), +- +- GPIO_FN(A0), GPIO_FN(A1), GPIO_FN(A2), +- GPIO_FN(A3), GPIO_FN(A6), GPIO_FN(A7), +- GPIO_FN(A8), GPIO_FN(A9), GPIO_FN(A10), +- GPIO_FN(A11), GPIO_FN(A12), GPIO_FN(A13), +- GPIO_FN(A14), GPIO_FN(A15), GPIO_FN(A16), +- GPIO_FN(A17), GPIO_FN(A18), GPIO_FN(A19), +- GPIO_FN(A20), GPIO_FN(A21), GPIO_FN(A22), +- GPIO_FN(A23), GPIO_FN(A24), GPIO_FN(A25), +- GPIO_FN(A26), +- +- GPIO_FN(CS0), GPIO_FN(CS2), GPIO_FN(CS4), +- GPIO_FN(CS5A), GPIO_FN(CS5B), GPIO_FN(CS6A), +- +- /* BSC/FLCTL */ +- GPIO_FN(RD_FSC), GPIO_FN(WE0_FWE), GPIO_FN(A4_FOE), +- GPIO_FN(A5_FCDE), GPIO_FN(D0_NAF0), GPIO_FN(D1_NAF1), +- GPIO_FN(D2_NAF2), GPIO_FN(D3_NAF3), GPIO_FN(D4_NAF4), +- GPIO_FN(D5_NAF5), GPIO_FN(D6_NAF6), GPIO_FN(D7_NAF7), +- GPIO_FN(D8_NAF8), GPIO_FN(D9_NAF9), GPIO_FN(D10_NAF10), +- GPIO_FN(D11_NAF11), GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13), +- GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15), +- +- /* SPU2 */ +- GPIO_FN(VINT_I), +- +- /* FLCTL */ +- GPIO_FN(FCE1), GPIO_FN(FCE0), GPIO_FN(FRB), +- +- /* HSI */ +- GPIO_FN(GP_RX_FLAG), GPIO_FN(GP_RX_DATA), GPIO_FN(GP_TX_READY), +- GPIO_FN(GP_RX_WAKE), GPIO_FN(MP_TX_FLAG), GPIO_FN(MP_TX_DATA), +- GPIO_FN(MP_RX_READY), GPIO_FN(MP_TX_WAKE), +- +- /* MFI */ +- GPIO_FN(MFIv6), +- GPIO_FN(MFIv4), +- +- GPIO_FN(MEMC_BUSCLK_MEMC_A0), GPIO_FN(MEMC_ADV_MEMC_DREQ0), +- GPIO_FN(MEMC_WAIT_MEMC_DREQ1), GPIO_FN(MEMC_CS1_MEMC_A1), +- GPIO_FN(MEMC_CS0), GPIO_FN(MEMC_NOE), +- GPIO_FN(MEMC_NWE), GPIO_FN(MEMC_INT), +- +- GPIO_FN(MEMC_AD0), GPIO_FN(MEMC_AD1), GPIO_FN(MEMC_AD2), +- GPIO_FN(MEMC_AD3), GPIO_FN(MEMC_AD4), GPIO_FN(MEMC_AD5), +- GPIO_FN(MEMC_AD6), GPIO_FN(MEMC_AD7), GPIO_FN(MEMC_AD8), +- GPIO_FN(MEMC_AD9), GPIO_FN(MEMC_AD10), GPIO_FN(MEMC_AD11), +- GPIO_FN(MEMC_AD12), GPIO_FN(MEMC_AD13), GPIO_FN(MEMC_AD14), +- GPIO_FN(MEMC_AD15), +- +- /* SIM */ +- GPIO_FN(SIM_RST), GPIO_FN(SIM_CLK), GPIO_FN(SIM_D), +- +- /* TPU */ +- GPIO_FN(TPU0TO0), GPIO_FN(TPU0TO1), GPIO_FN(TPU0TO2_93), +- GPIO_FN(TPU0TO2_99), GPIO_FN(TPU0TO3), +- +- /* I2C2 */ +- GPIO_FN(I2C_SCL2), GPIO_FN(I2C_SDA2), +- +- /* I2C3(1) */ +- GPIO_FN(I2C_SCL3), GPIO_FN(I2C_SDA3), +- +- /* I2C3(2) */ +- GPIO_FN(I2C_SCL3S), GPIO_FN(I2C_SDA3S), +- +- /* I2C4(2) */ +- GPIO_FN(I2C_SCL4), GPIO_FN(I2C_SDA4), +- +- /* I2C4(2) */ +- GPIO_FN(I2C_SCL4S), GPIO_FN(I2C_SDA4S), +- +- /* KEYSC */ +- GPIO_FN(KEYOUT0), GPIO_FN(KEYIN0_121), GPIO_FN(KEYIN0_136), +- GPIO_FN(KEYOUT1), GPIO_FN(KEYIN1_122), GPIO_FN(KEYIN1_135), +- GPIO_FN(KEYOUT2), GPIO_FN(KEYIN2_123), GPIO_FN(KEYIN2_134), +- GPIO_FN(KEYOUT3), GPIO_FN(KEYIN3_124), GPIO_FN(KEYIN3_133), +- GPIO_FN(KEYOUT4), GPIO_FN(KEYIN4), GPIO_FN(KEYOUT5), +- GPIO_FN(KEYIN5), GPIO_FN(KEYOUT6), GPIO_FN(KEYIN6), +- GPIO_FN(KEYOUT7), GPIO_FN(KEYIN7), +- +- /* LCDC */ +- GPIO_FN(LCDHSYN), GPIO_FN(LCDCS), GPIO_FN(LCDVSYN), +- GPIO_FN(LCDDCK), GPIO_FN(LCDWR), GPIO_FN(LCDRD), +- GPIO_FN(LCDDISP), GPIO_FN(LCDRS), GPIO_FN(LCDLCLK), +- GPIO_FN(LCDDON), +- +- GPIO_FN(LCDD0), GPIO_FN(LCDD1), GPIO_FN(LCDD2), +- GPIO_FN(LCDD3), GPIO_FN(LCDD4), GPIO_FN(LCDD5), +- GPIO_FN(LCDD6), GPIO_FN(LCDD7), GPIO_FN(LCDD8), +- GPIO_FN(LCDD9), GPIO_FN(LCDD10), GPIO_FN(LCDD11), +- GPIO_FN(LCDD12), GPIO_FN(LCDD13), GPIO_FN(LCDD14), +- GPIO_FN(LCDD15), GPIO_FN(LCDD16), GPIO_FN(LCDD17), +- GPIO_FN(LCDD18), GPIO_FN(LCDD19), GPIO_FN(LCDD20), +- GPIO_FN(LCDD21), GPIO_FN(LCDD22), GPIO_FN(LCDD23), +- +- GPIO_FN(LCDC0_SELECT), +- GPIO_FN(LCDC1_SELECT), +- +- /* IRDA */ +- GPIO_FN(IRDA_OUT), GPIO_FN(IRDA_IN), GPIO_FN(IRDA_FIRSEL), +- GPIO_FN(IROUT_139), GPIO_FN(IROUT_140), +- +- /* TSIF1 */ +- GPIO_FN(TS0_1SELECT), +- GPIO_FN(TS0_2SELECT), +- GPIO_FN(TS1_1SELECT), +- GPIO_FN(TS1_2SELECT), +- +- GPIO_FN(TS_SPSYNC1), GPIO_FN(TS_SDAT1), +- GPIO_FN(TS_SDEN1), GPIO_FN(TS_SCK1), +- +- /* TSIF2 */ +- GPIO_FN(TS_SPSYNC2), GPIO_FN(TS_SDAT2), +- GPIO_FN(TS_SDEN2), GPIO_FN(TS_SCK2), +- +- /* HDMI */ +- GPIO_FN(HDMI_HPD), GPIO_FN(HDMI_CEC), +- +- /* SDENC */ +- GPIO_FN(SDENC_CPG), +- GPIO_FN(SDENC_DV_CLKI), +-}; +- + static const struct pinmux_cfg_reg pinmux_config_regs[] = { + PORTCR(0, 0xE6051000), /* PORT0CR */ + PORTCR(1, 0xE6051001), /* PORT1CR */ +@@ -2827,9 +2583,6 @@ const struct sh_pfc_soc_info sh7372_pinmux_info = { + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + +- .func_gpios = pinmux_func_gpios, +- .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), +- + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0132-ARM-shmobile-sh7372-Remove-all-GPIOs.patch b/patches.renesas/0132-ARM-shmobile-sh7372-Remove-all-GPIOs.patch new file mode 100644 index 00000000000..a7401e58084 --- /dev/null +++ b/patches.renesas/0132-ARM-shmobile-sh7372-Remove-all-GPIOs.patch @@ -0,0 +1,421 @@ +From f2b38c019a234a66e90692e3bb35b5f893194d3e Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 22 Apr 2013 00:05:41 +0200 +Subject: ARM: shmobile: sh7372: Remove all GPIOs + +Function GPIOs are not used anymore, and all code use the GPIO numbers +directly. Remove the GPIOs enumeration. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 0d0c8e3669682095c86805ee5e0b1e8a3dd68800) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/include/mach/sh7372.h | 391 --------------------------- + 1 file changed, 391 deletions(-) + +diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h +index fd7cba02..e882717c 100644 +--- a/arch/arm/mach-shmobile/include/mach/sh7372.h ++++ b/arch/arm/mach-shmobile/include/mach/sh7372.h +@@ -15,397 +15,6 @@ + #include <linux/pm_domain.h> + #include <mach/pm-rmobile.h> + +-/* +- * Pin Function Controller: +- * GPIO_FN_xx - GPIO used to select pin function +- * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU +- */ +-enum { +- /* PORT */ +- GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4, +- GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9, +- +- GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14, +- GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19, +- +- GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24, +- GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29, +- +- GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34, +- GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39, +- +- GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44, +- GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49, +- +- GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54, +- GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59, +- +- GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64, +- GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69, +- +- GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74, +- GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79, +- +- GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84, +- GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89, +- +- GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94, +- GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99, +- +- GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104, +- GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109, +- +- GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114, +- GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119, +- +- GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124, +- GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129, +- +- GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134, +- GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139, +- +- GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144, +- GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149, +- +- GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154, +- GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159, +- +- GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164, +- GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169, +- +- GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174, +- GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179, +- +- GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184, +- GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189, +- +- GPIO_PORT190, +- +- /* IRQ */ +- GPIO_FN_IRQ0_6, /* PORT 6 */ +- GPIO_FN_IRQ0_162, /* PORT 162 */ +- GPIO_FN_IRQ1, /* PORT 12 */ +- GPIO_FN_IRQ2_4, /* PORT 4 */ +- GPIO_FN_IRQ2_5, /* PORT 5 */ +- GPIO_FN_IRQ3_8, /* PORT 8 */ +- GPIO_FN_IRQ3_16, /* PORT 16 */ +- GPIO_FN_IRQ4_17, /* PORT 17 */ +- GPIO_FN_IRQ4_163, /* PORT 163 */ +- GPIO_FN_IRQ5, /* PORT 18 */ +- GPIO_FN_IRQ6_39, /* PORT 39 */ +- GPIO_FN_IRQ6_164, /* PORT 164 */ +- GPIO_FN_IRQ7_40, /* PORT 40 */ +- GPIO_FN_IRQ7_167, /* PORT 167 */ +- GPIO_FN_IRQ8_41, /* PORT 41 */ +- GPIO_FN_IRQ8_168, /* PORT 168 */ +- GPIO_FN_IRQ9_42, /* PORT 42 */ +- GPIO_FN_IRQ9_169, /* PORT 169 */ +- GPIO_FN_IRQ10, /* PORT 65 */ +- GPIO_FN_IRQ11, /* PORT 67 */ +- GPIO_FN_IRQ12_80, /* PORT 80 */ +- GPIO_FN_IRQ12_137, /* PORT 137 */ +- GPIO_FN_IRQ13_81, /* PORT 81 */ +- GPIO_FN_IRQ13_145, /* PORT 145 */ +- GPIO_FN_IRQ14_82, /* PORT 82 */ +- GPIO_FN_IRQ14_146, /* PORT 146 */ +- GPIO_FN_IRQ15_83, /* PORT 83 */ +- GPIO_FN_IRQ15_147, /* PORT 147 */ +- GPIO_FN_IRQ16_84, /* PORT 84 */ +- GPIO_FN_IRQ16_170, /* PORT 170 */ +- GPIO_FN_IRQ17, /* PORT 85 */ +- GPIO_FN_IRQ18, /* PORT 86 */ +- GPIO_FN_IRQ19, /* PORT 87 */ +- GPIO_FN_IRQ20, /* PORT 92 */ +- GPIO_FN_IRQ21, /* PORT 93 */ +- GPIO_FN_IRQ22, /* PORT 94 */ +- GPIO_FN_IRQ23, /* PORT 95 */ +- GPIO_FN_IRQ24, /* PORT 112 */ +- GPIO_FN_IRQ25, /* PORT 119 */ +- GPIO_FN_IRQ26_121, /* PORT 121 */ +- GPIO_FN_IRQ26_172, /* PORT 172 */ +- GPIO_FN_IRQ27_122, /* PORT 122 */ +- GPIO_FN_IRQ27_180, /* PORT 180 */ +- GPIO_FN_IRQ28_123, /* PORT 123 */ +- GPIO_FN_IRQ28_181, /* PORT 181 */ +- GPIO_FN_IRQ29_129, /* PORT 129 */ +- GPIO_FN_IRQ29_182, /* PORT 182 */ +- GPIO_FN_IRQ30_130, /* PORT 130 */ +- GPIO_FN_IRQ30_183, /* PORT 183 */ +- GPIO_FN_IRQ31_138, /* PORT 138 */ +- GPIO_FN_IRQ31_184, /* PORT 184 */ +- +- /* +- * MSIOF0 (PORT 36, 37, 38, 39 +- * 40, 41, 42, 43, 44, 45) +- */ +- GPIO_FN_MSIOF0_TSYNC, GPIO_FN_MSIOF0_TSCK, +- GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_RSCK, +- GPIO_FN_MSIOF0_RSYNC, GPIO_FN_MSIOF0_MCK0, +- GPIO_FN_MSIOF0_MCK1, GPIO_FN_MSIOF0_SS1, +- GPIO_FN_MSIOF0_SS2, GPIO_FN_MSIOF0_TXD, +- +- /* +- * MSIOF1 (PORT 39, 40, 41, 42, 43, 44 +- * 84, 85, 86, 87, 88, 89, 90, 91, 92, 93) +- */ +- GPIO_FN_MSIOF1_TSCK_39, GPIO_FN_MSIOF1_TSYNC_40, +- GPIO_FN_MSIOF1_TSCK_88, GPIO_FN_MSIOF1_TSYNC_89, +- GPIO_FN_MSIOF1_TXD_41, GPIO_FN_MSIOF1_RXD_42, +- GPIO_FN_MSIOF1_TXD_90, GPIO_FN_MSIOF1_RXD_91, +- GPIO_FN_MSIOF1_SS1_43, GPIO_FN_MSIOF1_SS2_44, +- GPIO_FN_MSIOF1_SS1_92, GPIO_FN_MSIOF1_SS2_93, +- GPIO_FN_MSIOF1_RSCK, GPIO_FN_MSIOF1_RSYNC, +- GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1, +- +- /* +- * MSIOF2 (PORT 134, 135, 136, 137, 138, 139 +- * 148, 149, 150, 151) +- */ +- GPIO_FN_MSIOF2_RSCK, GPIO_FN_MSIOF2_RSYNC, +- GPIO_FN_MSIOF2_MCK0, GPIO_FN_MSIOF2_MCK1, +- GPIO_FN_MSIOF2_SS1, GPIO_FN_MSIOF2_SS2, +- GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_TSCK, +- GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TXD, +- +- /* MSIOF3 (PORT 76, 77, 78, 79, 80, 81, 82, 83) */ +- GPIO_FN_BBIF1_RXD, GPIO_FN_BBIF1_TSYNC, +- GPIO_FN_BBIF1_TSCK, GPIO_FN_BBIF1_TXD, +- GPIO_FN_BBIF1_RSCK, GPIO_FN_BBIF1_RSYNC, +- GPIO_FN_BBIF1_FLOW, GPIO_FN_BB_RX_FLOW_N, +- +- /* MSIOF4 (PORT 0, 1, 2, 3) */ +- GPIO_FN_BBIF2_TSCK1, GPIO_FN_BBIF2_TSYNC1, +- GPIO_FN_BBIF2_TXD1, GPIO_FN_BBIF2_RXD, +- +- /* FSI (PORT 4, 5, 6, 7, 8, 9, 10, 11, 15) */ +- GPIO_FN_FSIACK, GPIO_FN_FSIBCK, +- GPIO_FN_FSIAILR, GPIO_FN_FSIAIBT, +- GPIO_FN_FSIAISLD, GPIO_FN_FSIAOMC, +- GPIO_FN_FSIAOLR, GPIO_FN_FSIAOBT, +- GPIO_FN_FSIAOSLD, GPIO_FN_FSIASPDIF_11, +- GPIO_FN_FSIASPDIF_15, +- +- /* FMSI (PORT 12, 13, 14, 15, 16, 17, 18, 65) */ +- GPIO_FN_FMSOCK, GPIO_FN_FMSOOLR, +- GPIO_FN_FMSIOLR, GPIO_FN_FMSOOBT, +- GPIO_FN_FMSIOBT, GPIO_FN_FMSOSLD, +- GPIO_FN_FMSOILR, GPIO_FN_FMSIILR, +- GPIO_FN_FMSOIBT, GPIO_FN_FMSIIBT, +- GPIO_FN_FMSISLD, GPIO_FN_FMSICK, +- +- /* SCIFA0 (PORT 152, 153, 156, 157, 158) */ +- GPIO_FN_SCIFA0_TXD, GPIO_FN_SCIFA0_RXD, +- GPIO_FN_SCIFA0_SCK, GPIO_FN_SCIFA0_RTS, +- GPIO_FN_SCIFA0_CTS, +- +- /* SCIFA1 (PORT 154, 155, 159, 160, 161) */ +- GPIO_FN_SCIFA1_TXD, GPIO_FN_SCIFA1_RXD, +- GPIO_FN_SCIFA1_SCK, GPIO_FN_SCIFA1_RTS, +- GPIO_FN_SCIFA1_CTS, +- +- /* SCIFA2 (PORT 94, 95, 96, 97, 98) */ +- GPIO_FN_SCIFA2_CTS1, GPIO_FN_SCIFA2_RTS1, +- GPIO_FN_SCIFA2_TXD1, GPIO_FN_SCIFA2_RXD1, +- GPIO_FN_SCIFA2_SCK1, +- +- /* SCIFA3 (PORT 43, 44, +- 140, 141, 142, 143, 144) */ +- GPIO_FN_SCIFA3_CTS_43, GPIO_FN_SCIFA3_CTS_140, +- GPIO_FN_SCIFA3_RTS_44, GPIO_FN_SCIFA3_RTS_141, +- GPIO_FN_SCIFA3_SCK, GPIO_FN_SCIFA3_TXD, +- GPIO_FN_SCIFA3_RXD, +- +- /* SCIFA4 (PORT 5, 6) */ +- GPIO_FN_SCIFA4_RXD, GPIO_FN_SCIFA4_TXD, +- +- /* SCIFA5 (PORT 8, 12) */ +- GPIO_FN_SCIFA5_RXD, GPIO_FN_SCIFA5_TXD, +- +- /* SCIFB (PORT 162, 163, 164, 165, 166) */ +- GPIO_FN_SCIFB_SCK, GPIO_FN_SCIFB_RTS, +- GPIO_FN_SCIFB_CTS, GPIO_FN_SCIFB_TXD, +- GPIO_FN_SCIFB_RXD, +- +- /* +- * CEU (PORT 16, 17, +- * 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, +- * 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, +- * 120) +- */ +- GPIO_FN_VIO_HD, GPIO_FN_VIO_CKO1, GPIO_FN_VIO_CKO2, +- GPIO_FN_VIO_VD, GPIO_FN_VIO_CLK, GPIO_FN_VIO_FIELD, +- GPIO_FN_VIO_CKO, +- GPIO_FN_VIO_D0, GPIO_FN_VIO_D1, GPIO_FN_VIO_D2, +- GPIO_FN_VIO_D3, GPIO_FN_VIO_D4, GPIO_FN_VIO_D5, +- GPIO_FN_VIO_D6, GPIO_FN_VIO_D7, GPIO_FN_VIO_D8, +- GPIO_FN_VIO_D9, GPIO_FN_VIO_D10, GPIO_FN_VIO_D11, +- GPIO_FN_VIO_D12, GPIO_FN_VIO_D13, GPIO_FN_VIO_D14, +- GPIO_FN_VIO_D15, +- +- /* USB0 (PORT 113, 114, 115, 116, 117, 167) */ +- GPIO_FN_IDIN_0, GPIO_FN_EXTLP_0, +- GPIO_FN_OVCN2_0, GPIO_FN_PWEN_0, +- GPIO_FN_OVCN_0, GPIO_FN_VBUS0_0, +- +- /* USB1 (PORT 18, 113, 114, 115, 116, 117, 138, 162, 168) */ +- GPIO_FN_IDIN_1_18, GPIO_FN_IDIN_1_113, +- GPIO_FN_PWEN_1_115, GPIO_FN_PWEN_1_138, +- GPIO_FN_OVCN_1_114, GPIO_FN_OVCN_1_162, +- GPIO_FN_EXTLP_1, GPIO_FN_OVCN2_1, +- GPIO_FN_VBUS0_1, +- +- /* GPIO (PORT 41, 42, 43, 44) */ +- GPIO_FN_GPI0, GPIO_FN_GPI1, GPIO_FN_GPO0, GPIO_FN_GPO1, +- +- /* +- * BSC (PORT 19, +- * 20, 21, 22, 25, 26, 27, 28, 29, +- * 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, +- * 40, 41, 42, 43, 44, 45, +- * 62, 63, 64, 65, 66, 67, +- * 71, 72, 74, 75) +- */ +- GPIO_FN_BS, GPIO_FN_WE1, +- GPIO_FN_CKO, GPIO_FN_WAIT, GPIO_FN_RDWR, +- +- GPIO_FN_A0, GPIO_FN_A1, GPIO_FN_A2, GPIO_FN_A3, +- GPIO_FN_A6, GPIO_FN_A7, GPIO_FN_A8, GPIO_FN_A9, +- GPIO_FN_A10, GPIO_FN_A11, GPIO_FN_A12, GPIO_FN_A13, +- GPIO_FN_A14, GPIO_FN_A15, GPIO_FN_A16, GPIO_FN_A17, +- GPIO_FN_A18, GPIO_FN_A19, GPIO_FN_A20, GPIO_FN_A21, +- GPIO_FN_A22, GPIO_FN_A23, GPIO_FN_A24, GPIO_FN_A25, +- GPIO_FN_A26, +- +- GPIO_FN_CS0, GPIO_FN_CS2, GPIO_FN_CS4, +- GPIO_FN_CS5A, GPIO_FN_CS5B, GPIO_FN_CS6A, +- +- /* +- * BSC/FLCTL (PORT 23, 24, +- * 46, 47, 48, 49, +- * 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, +- * 60, 61, 69, 70) +- */ +- GPIO_FN_RD_FSC, GPIO_FN_WE0_FWE, +- GPIO_FN_A4_FOE, GPIO_FN_A5_FCDE, +- GPIO_FN_D0_NAF0, GPIO_FN_D1_NAF1, GPIO_FN_D2_NAF2, +- GPIO_FN_D3_NAF3, GPIO_FN_D4_NAF4, GPIO_FN_D5_NAF5, +- GPIO_FN_D6_NAF6, GPIO_FN_D7_NAF7, GPIO_FN_D8_NAF8, +- GPIO_FN_D9_NAF9, GPIO_FN_D10_NAF10, GPIO_FN_D11_NAF11, +- GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, GPIO_FN_D14_NAF14, +- GPIO_FN_D15_NAF15, +- +- /* SPU2 (PORT 65) */ +- GPIO_FN_VINT_I, +- +- /* FLCTL (PORT 66, 68, 73) */ +- GPIO_FN_FCE1, GPIO_FN_FCE0, GPIO_FN_FRB, +- +- /* HSI (PORT 76, 77, 78, 79, 80, 81, 82, 83) */ +- GPIO_FN_GP_RX_FLAG, GPIO_FN_GP_RX_DATA, GPIO_FN_GP_TX_READY, +- GPIO_FN_GP_RX_WAKE, GPIO_FN_MP_TX_FLAG, GPIO_FN_MP_TX_DATA, +- GPIO_FN_MP_RX_READY, GPIO_FN_MP_TX_WAKE, +- +- /* +- * MFI (PORT 76, 77, 78, 79, +- * 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, +- * 90, 91, 92, 93, 94, 95, 96, 97, 98, 99) +- */ +- GPIO_FN_MFIv6, /* see MSEL4CR 6 */ +- GPIO_FN_MFIv4, /* see MSEL4CR 6 */ +- +- GPIO_FN_MEMC_CS0, GPIO_FN_MEMC_BUSCLK_MEMC_A0, +- GPIO_FN_MEMC_CS1_MEMC_A1, GPIO_FN_MEMC_ADV_MEMC_DREQ0, +- GPIO_FN_MEMC_WAIT_MEMC_DREQ1, GPIO_FN_MEMC_NOE, +- GPIO_FN_MEMC_NWE, GPIO_FN_MEMC_INT, +- +- GPIO_FN_MEMC_AD0, GPIO_FN_MEMC_AD1, GPIO_FN_MEMC_AD2, +- GPIO_FN_MEMC_AD3, GPIO_FN_MEMC_AD4, GPIO_FN_MEMC_AD5, +- GPIO_FN_MEMC_AD6, GPIO_FN_MEMC_AD7, GPIO_FN_MEMC_AD8, +- GPIO_FN_MEMC_AD9, GPIO_FN_MEMC_AD10, GPIO_FN_MEMC_AD11, +- GPIO_FN_MEMC_AD12, GPIO_FN_MEMC_AD13, GPIO_FN_MEMC_AD14, +- GPIO_FN_MEMC_AD15, +- +- /* SIM (PORT 94, 95, 98) */ +- GPIO_FN_SIM_RST, GPIO_FN_SIM_CLK, GPIO_FN_SIM_D, +- +- /* TPU (PORT 93, 99, 112, 160, 161) */ +- GPIO_FN_TPU0TO0, GPIO_FN_TPU0TO1, +- GPIO_FN_TPU0TO2_93, GPIO_FN_TPU0TO2_99, +- GPIO_FN_TPU0TO3, +- +- /* I2C2 (PORT 110, 111) */ +- GPIO_FN_I2C_SCL2, GPIO_FN_I2C_SDA2, +- +- /* I2C3(1) (PORT 114, 115) */ +- GPIO_FN_I2C_SCL3, GPIO_FN_I2C_SDA3, +- +- /* I2C3(2) (PORT 137, 145) */ +- GPIO_FN_I2C_SCL3S, GPIO_FN_I2C_SDA3S, +- +- /* I2C4(2) (PORT 116, 117) */ +- GPIO_FN_I2C_SCL4, GPIO_FN_I2C_SDA4, +- +- /* I2C4(2) (PORT 146, 147) */ +- GPIO_FN_I2C_SCL4S, GPIO_FN_I2C_SDA4S, +- +- /* +- * KEYSC (PORT 121, 122, 123, 124, 125, 126, 127, 128, 129, +- * 130, 131, 132, 133, 134, 135, 136) +- */ +- GPIO_FN_KEYOUT0, GPIO_FN_KEYIN0_121, GPIO_FN_KEYIN0_136, +- GPIO_FN_KEYOUT1, GPIO_FN_KEYIN1_122, GPIO_FN_KEYIN1_135, +- GPIO_FN_KEYOUT2, GPIO_FN_KEYIN2_123, GPIO_FN_KEYIN2_134, +- GPIO_FN_KEYOUT3, GPIO_FN_KEYIN3_124, GPIO_FN_KEYIN3_133, +- GPIO_FN_KEYOUT4, GPIO_FN_KEYIN4, +- GPIO_FN_KEYOUT5, GPIO_FN_KEYIN5, +- GPIO_FN_KEYOUT6, GPIO_FN_KEYIN6, +- GPIO_FN_KEYOUT7, GPIO_FN_KEYIN7, +- +- /* +- * LCDC (PORT 121, 122, 123, 124, 125, 126, 127, 128, 129, +- * 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, +- * 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, +- * 150, 151) +- */ +- GPIO_FN_LCDC0_SELECT, /* LCDC 0 */ +- GPIO_FN_LCDC1_SELECT, /* LCDC 1 */ +- GPIO_FN_LCDHSYN, GPIO_FN_LCDCS, GPIO_FN_LCDVSYN, +- GPIO_FN_LCDDCK, GPIO_FN_LCDWR, GPIO_FN_LCDRD, +- GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_LCDLCLK, +- GPIO_FN_LCDDON, +- +- GPIO_FN_LCDD0, GPIO_FN_LCDD1, GPIO_FN_LCDD2, GPIO_FN_LCDD3, +- GPIO_FN_LCDD4, GPIO_FN_LCDD5, GPIO_FN_LCDD6, GPIO_FN_LCDD7, +- GPIO_FN_LCDD8, GPIO_FN_LCDD9, GPIO_FN_LCDD10, GPIO_FN_LCDD11, +- GPIO_FN_LCDD12, GPIO_FN_LCDD13, GPIO_FN_LCDD14, GPIO_FN_LCDD15, +- GPIO_FN_LCDD16, GPIO_FN_LCDD17, GPIO_FN_LCDD18, GPIO_FN_LCDD19, +- GPIO_FN_LCDD20, GPIO_FN_LCDD21, GPIO_FN_LCDD22, GPIO_FN_LCDD23, +- +- /* IRDA (PORT 139, 140, 141, 142) */ +- GPIO_FN_IRDA_OUT, GPIO_FN_IRDA_IN, GPIO_FN_IRDA_FIRSEL, +- GPIO_FN_IROUT_139, GPIO_FN_IROUT_140, +- +- /* TSIF1 (PORT 156, 157, 158, 159) */ +- GPIO_FN_TS0_1SELECT, /* TSIF0 - 1 select */ +- GPIO_FN_TS0_2SELECT, /* TSIF0 - 2 select */ +- GPIO_FN_TS1_1SELECT, /* TSIF1 - 1 select */ +- GPIO_FN_TS1_2SELECT, /* TSIF1 - 2 select */ +- +- GPIO_FN_TS_SPSYNC1, GPIO_FN_TS_SDAT1, +- GPIO_FN_TS_SDEN1, GPIO_FN_TS_SCK1, +- +- /* TSIF2 (PORT 137, 145, 146, 147) */ +- GPIO_FN_TS_SPSYNC2, GPIO_FN_TS_SDAT2, +- GPIO_FN_TS_SDEN2, GPIO_FN_TS_SCK2, +- +- /* HDMI (PORT 169, 170) */ +- GPIO_FN_HDMI_HPD, GPIO_FN_HDMI_CEC, +- +- /* SDENC see MSEL4CR 19 */ +- GPIO_FN_SDENC_CPG, +- GPIO_FN_SDENC_DV_CLKI, +-}; +- + /* DMA slave IDs */ + enum { + SHDMA_SLAVE_INVALID, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0133-sh-pfc-sh7372-Add-bias-pull-up-down-pinconf-support.patch b/patches.renesas/0133-sh-pfc-sh7372-Add-bias-pull-up-down-pinconf-support.patch new file mode 100644 index 00000000000..9ef2ed78df0 --- /dev/null +++ b/patches.renesas/0133-sh-pfc-sh7372-Add-bias-pull-up-down-pinconf-support.patch @@ -0,0 +1,412 @@ +From fe658d9b572e0387bd29618710eb2fbc2abe05f4 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 23 Apr 2013 14:24:19 +0200 +Subject: sh-pfc: sh7372: Add bias (pull-up/down) pinconf support + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 7cacd755594ea9347fb83dcb23d2f44c371747dd) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-sh7372.c | 341 ++++++++++++++++++++++-------------- + 1 file changed, 211 insertions(+), 130 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +index 94960670..6dfb1877 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +@@ -20,10 +20,14 @@ + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ ++#include <linux/io.h> + #include <linux/kernel.h> ++#include <linux/pinctrl/pinconf-generic.h> ++ + #include <mach/irqs.h> + #include <mach/sh7372.h> + ++#include "core.h" + #include "sh_pfc.h" + + #define CPU_ALL_PORT(fn, pfx, sfx) \ +@@ -76,16 +80,6 @@ enum { + PORT_ALL(IN), + PINMUX_INPUT_END, + +- /* PORT0_IN_PU -> PORT190_IN_PU */ +- PINMUX_INPUT_PULLUP_BEGIN, +- PORT_ALL(IN_PU), +- PINMUX_INPUT_PULLUP_END, +- +- /* PORT0_IN_PD -> PORT190_IN_PD */ +- PINMUX_INPUT_PULLDOWN_BEGIN, +- PORT_ALL(IN_PD), +- PINMUX_INPUT_PULLDOWN_END, +- + /* PORT0_OUT -> PORT190_OUT */ + PINMUX_OUTPUT_BEGIN, + PORT_ALL(OUT), +@@ -397,124 +391,11 @@ enum { + PINMUX_MARK_END, + }; + +-static const pinmux_enum_t pinmux_data[] = { ++#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx) ++#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) + +- /* specify valid pin states for each pin in GPIO mode */ +- PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1), +- PORT_DATA_O(2), PORT_DATA_I_PD(3), +- PORT_DATA_I_PD(4), PORT_DATA_I_PD(5), +- PORT_DATA_IO_PU_PD(6), PORT_DATA_I_PD(7), +- PORT_DATA_IO_PD(8), PORT_DATA_O(9), +- +- PORT_DATA_O(10), PORT_DATA_O(11), +- PORT_DATA_IO_PU_PD(12), PORT_DATA_IO_PD(13), +- PORT_DATA_IO_PD(14), PORT_DATA_O(15), +- PORT_DATA_IO_PD(16), PORT_DATA_IO_PD(17), +- PORT_DATA_I_PD(18), PORT_DATA_IO(19), +- +- PORT_DATA_IO(20), PORT_DATA_IO(21), +- PORT_DATA_IO(22), PORT_DATA_IO(23), +- PORT_DATA_IO(24), PORT_DATA_IO(25), +- PORT_DATA_IO(26), PORT_DATA_IO(27), +- PORT_DATA_IO(28), PORT_DATA_IO(29), +- +- PORT_DATA_IO(30), PORT_DATA_IO(31), +- PORT_DATA_IO(32), PORT_DATA_IO(33), +- PORT_DATA_IO(34), PORT_DATA_IO(35), +- PORT_DATA_IO(36), PORT_DATA_IO(37), +- PORT_DATA_IO(38), PORT_DATA_IO(39), +- +- PORT_DATA_IO(40), PORT_DATA_IO(41), +- PORT_DATA_IO(42), PORT_DATA_IO(43), +- PORT_DATA_IO(44), PORT_DATA_IO(45), +- PORT_DATA_IO_PU(46), PORT_DATA_IO_PU(47), +- PORT_DATA_IO_PU(48), PORT_DATA_IO_PU(49), +- +- PORT_DATA_IO_PU(50), PORT_DATA_IO_PU(51), +- PORT_DATA_IO_PU(52), PORT_DATA_IO_PU(53), +- PORT_DATA_IO_PU(54), PORT_DATA_IO_PU(55), +- PORT_DATA_IO_PU(56), PORT_DATA_IO_PU(57), +- PORT_DATA_IO_PU(58), PORT_DATA_IO_PU(59), +- +- PORT_DATA_IO_PU(60), PORT_DATA_IO_PU(61), +- PORT_DATA_IO(62), PORT_DATA_O(63), +- PORT_DATA_O(64), PORT_DATA_IO_PU(65), +- PORT_DATA_O(66), PORT_DATA_IO_PU(67), /*66?*/ +- PORT_DATA_O(68), PORT_DATA_IO(69), +- +- PORT_DATA_IO(70), PORT_DATA_IO(71), +- PORT_DATA_O(72), PORT_DATA_I_PU(73), +- PORT_DATA_I_PU_PD(74), PORT_DATA_IO_PU_PD(75), +- PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77), +- PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79), +- +- PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81), +- PORT_DATA_IO_PU_PD(82), PORT_DATA_IO_PU_PD(83), +- PORT_DATA_IO_PU_PD(84), PORT_DATA_IO_PU_PD(85), +- PORT_DATA_IO_PU_PD(86), PORT_DATA_IO_PU_PD(87), +- PORT_DATA_IO_PU_PD(88), PORT_DATA_IO_PU_PD(89), +- +- PORT_DATA_IO_PU_PD(90), PORT_DATA_IO_PU_PD(91), +- PORT_DATA_IO_PU_PD(92), PORT_DATA_IO_PU_PD(93), +- PORT_DATA_IO_PU_PD(94), PORT_DATA_IO_PU_PD(95), +- PORT_DATA_IO_PU(96), PORT_DATA_IO_PU_PD(97), +- PORT_DATA_IO_PU_PD(98), PORT_DATA_O(99), /*99?*/ +- +- PORT_DATA_IO_PD(100), PORT_DATA_IO_PD(101), +- PORT_DATA_IO_PD(102), PORT_DATA_IO_PD(103), +- PORT_DATA_IO_PD(104), PORT_DATA_IO_PD(105), +- PORT_DATA_IO_PU(106), PORT_DATA_IO_PU(107), +- PORT_DATA_IO_PU(108), PORT_DATA_IO_PU(109), +- +- PORT_DATA_IO_PU(110), PORT_DATA_IO_PU(111), +- PORT_DATA_IO_PD(112), PORT_DATA_IO_PD(113), +- PORT_DATA_IO_PU(114), PORT_DATA_IO_PU(115), +- PORT_DATA_IO_PU(116), PORT_DATA_IO_PU(117), +- PORT_DATA_IO_PU(118), PORT_DATA_IO_PU(119), +- +- PORT_DATA_IO_PU(120), PORT_DATA_IO_PD(121), +- PORT_DATA_IO_PD(122), PORT_DATA_IO_PD(123), +- PORT_DATA_IO_PD(124), PORT_DATA_IO_PD(125), +- PORT_DATA_IO_PD(126), PORT_DATA_IO_PD(127), +- PORT_DATA_IO_PD(128), PORT_DATA_IO_PU_PD(129), +- +- PORT_DATA_IO_PU_PD(130), PORT_DATA_IO_PU_PD(131), +- PORT_DATA_IO_PU_PD(132), PORT_DATA_IO_PU_PD(133), +- PORT_DATA_IO_PU_PD(134), PORT_DATA_IO_PU_PD(135), +- PORT_DATA_IO_PD(136), PORT_DATA_IO_PD(137), +- PORT_DATA_IO_PD(138), PORT_DATA_IO_PD(139), +- +- PORT_DATA_IO_PD(140), PORT_DATA_IO_PD(141), +- PORT_DATA_IO_PD(142), PORT_DATA_IO_PU_PD(143), +- PORT_DATA_IO_PD(144), PORT_DATA_IO_PD(145), +- PORT_DATA_IO_PD(146), PORT_DATA_IO_PD(147), +- PORT_DATA_IO_PD(148), PORT_DATA_IO_PD(149), +- +- PORT_DATA_IO_PD(150), PORT_DATA_IO_PD(151), +- PORT_DATA_IO_PU_PD(152), PORT_DATA_I_PD(153), +- PORT_DATA_IO_PU_PD(154), PORT_DATA_I_PD(155), +- PORT_DATA_IO_PD(156), PORT_DATA_IO_PD(157), +- PORT_DATA_I_PD(158), PORT_DATA_IO_PD(159), +- +- PORT_DATA_O(160), PORT_DATA_IO_PD(161), +- PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163), +- PORT_DATA_I_PD(164), PORT_DATA_IO_PD(165), +- PORT_DATA_I_PD(166), PORT_DATA_I_PD(167), +- PORT_DATA_I_PD(168), PORT_DATA_I_PD(169), +- +- PORT_DATA_I_PD(170), PORT_DATA_O(171), +- PORT_DATA_IO_PU_PD(172), PORT_DATA_IO_PU_PD(173), +- PORT_DATA_IO_PU_PD(174), PORT_DATA_IO_PU_PD(175), +- PORT_DATA_IO_PU_PD(176), PORT_DATA_IO_PU_PD(177), +- PORT_DATA_IO_PU_PD(178), PORT_DATA_O(179), +- +- PORT_DATA_IO_PU_PD(180), PORT_DATA_IO_PU_PD(181), +- PORT_DATA_IO_PU_PD(182), PORT_DATA_IO_PU_PD(183), +- PORT_DATA_IO_PU_PD(184), PORT_DATA_O(185), +- PORT_DATA_IO_PU_PD(186), PORT_DATA_IO_PU_PD(187), +- PORT_DATA_IO_PU_PD(188), PORT_DATA_IO_PU_PD(189), +- +- PORT_DATA_IO_PU_PD(190), ++static const pinmux_enum_t pinmux_data[] = { ++ PINMUX_DATA_GP_ALL(), + + /* IRQ */ + PINMUX_DATA(IRQ0_6_MARK, PORT6_FN0, MSEL1CR_0_0), +@@ -958,8 +839,128 @@ static const pinmux_enum_t pinmux_data[] = { + PINMUX_DATA(MFIv4_MARK, MSEL4CR_6_1), + }; + ++#define SH7372_PIN(pin, cfgs) \ ++ { \ ++ .name = __stringify(PORT##pin), \ ++ .enum_id = PORT##pin##_DATA, \ ++ .configs = cfgs, \ ++ } ++ ++#define __I (SH_PFC_PIN_CFG_INPUT) ++#define __O (SH_PFC_PIN_CFG_OUTPUT) ++#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT) ++#define __PD (SH_PFC_PIN_CFG_PULL_DOWN) ++#define __PU (SH_PFC_PIN_CFG_PULL_UP) ++#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP) ++ ++#define SH7372_PIN_I_PD(pin) SH7372_PIN(pin, __I | __PD) ++#define SH7372_PIN_I_PU(pin) SH7372_PIN(pin, __I | __PU) ++#define SH7372_PIN_I_PU_PD(pin) SH7372_PIN(pin, __I | __PUD) ++#define SH7372_PIN_IO(pin) SH7372_PIN(pin, __IO) ++#define SH7372_PIN_IO_PD(pin) SH7372_PIN(pin, __IO | __PD) ++#define SH7372_PIN_IO_PU(pin) SH7372_PIN(pin, __IO | __PU) ++#define SH7372_PIN_IO_PU_PD(pin) SH7372_PIN(pin, __IO | __PUD) ++#define SH7372_PIN_O(pin) SH7372_PIN(pin, __O) ++#define SH7372_PIN_O_PU_PD(pin) SH7372_PIN(pin, __O | __PUD) ++ + static struct sh_pfc_pin pinmux_pins[] = { +- GPIO_PORT_ALL(), ++ /* Table 57-1 (I/O and Pull U/D) */ ++ SH7372_PIN_IO_PD(0), SH7372_PIN_IO_PD(1), ++ SH7372_PIN_O(2), SH7372_PIN_I_PD(3), ++ SH7372_PIN_I_PD(4), SH7372_PIN_I_PD(5), ++ SH7372_PIN_IO_PU_PD(6), SH7372_PIN_I_PD(7), ++ SH7372_PIN_IO_PD(8), SH7372_PIN_O(9), ++ SH7372_PIN_O(10), SH7372_PIN_O(11), ++ SH7372_PIN_IO_PU_PD(12), SH7372_PIN_IO_PD(13), ++ SH7372_PIN_IO_PD(14), SH7372_PIN_O(15), ++ SH7372_PIN_IO_PD(16), SH7372_PIN_IO_PD(17), ++ SH7372_PIN_I_PD(18), SH7372_PIN_IO(19), ++ SH7372_PIN_IO(20), SH7372_PIN_IO(21), ++ SH7372_PIN_IO(22), SH7372_PIN_IO(23), ++ SH7372_PIN_IO(24), SH7372_PIN_IO(25), ++ SH7372_PIN_IO(26), SH7372_PIN_IO(27), ++ SH7372_PIN_IO(28), SH7372_PIN_IO(29), ++ SH7372_PIN_IO(30), SH7372_PIN_IO(31), ++ SH7372_PIN_IO(32), SH7372_PIN_IO(33), ++ SH7372_PIN_IO(34), SH7372_PIN_IO(35), ++ SH7372_PIN_IO(36), SH7372_PIN_IO(37), ++ SH7372_PIN_IO(38), SH7372_PIN_IO(39), ++ SH7372_PIN_IO(40), SH7372_PIN_IO(41), ++ SH7372_PIN_IO(42), SH7372_PIN_IO(43), ++ SH7372_PIN_IO(44), SH7372_PIN_IO(45), ++ SH7372_PIN_IO_PU(46), SH7372_PIN_IO_PU(47), ++ SH7372_PIN_IO_PU(48), SH7372_PIN_IO_PU(49), ++ SH7372_PIN_IO_PU(50), SH7372_PIN_IO_PU(51), ++ SH7372_PIN_IO_PU(52), SH7372_PIN_IO_PU(53), ++ SH7372_PIN_IO_PU(54), SH7372_PIN_IO_PU(55), ++ SH7372_PIN_IO_PU(56), SH7372_PIN_IO_PU(57), ++ SH7372_PIN_IO_PU(58), SH7372_PIN_IO_PU(59), ++ SH7372_PIN_IO_PU(60), SH7372_PIN_IO_PU(61), ++ SH7372_PIN_IO(62), SH7372_PIN_O(63), ++ SH7372_PIN_O(64), SH7372_PIN_IO_PU(65), ++ SH7372_PIN_O_PU_PD(66), SH7372_PIN_IO_PU(67), ++ SH7372_PIN_O(68), SH7372_PIN_IO(69), ++ SH7372_PIN_IO(70), SH7372_PIN_IO(71), ++ SH7372_PIN_O(72), SH7372_PIN_I_PU(73), ++ SH7372_PIN_I_PU_PD(74), SH7372_PIN_IO_PU_PD(75), ++ SH7372_PIN_IO_PU_PD(76), SH7372_PIN_IO_PU_PD(77), ++ SH7372_PIN_IO_PU_PD(78), SH7372_PIN_IO_PU_PD(79), ++ SH7372_PIN_IO_PU_PD(80), SH7372_PIN_IO_PU_PD(81), ++ SH7372_PIN_IO_PU_PD(82), SH7372_PIN_IO_PU_PD(83), ++ SH7372_PIN_IO_PU_PD(84), SH7372_PIN_IO_PU_PD(85), ++ SH7372_PIN_IO_PU_PD(86), SH7372_PIN_IO_PU_PD(87), ++ SH7372_PIN_IO_PU_PD(88), SH7372_PIN_IO_PU_PD(89), ++ SH7372_PIN_IO_PU_PD(90), SH7372_PIN_IO_PU_PD(91), ++ SH7372_PIN_IO_PU_PD(92), SH7372_PIN_IO_PU_PD(93), ++ SH7372_PIN_IO_PU_PD(94), SH7372_PIN_IO_PU_PD(95), ++ SH7372_PIN_IO_PU(96), SH7372_PIN_IO_PU_PD(97), ++ SH7372_PIN_IO_PU_PD(98), SH7372_PIN_O_PU_PD(99), ++ SH7372_PIN_IO_PD(100), SH7372_PIN_IO_PD(101), ++ SH7372_PIN_IO_PD(102), SH7372_PIN_IO_PD(103), ++ SH7372_PIN_IO_PD(104), SH7372_PIN_IO_PD(105), ++ SH7372_PIN_IO_PU(106), SH7372_PIN_IO_PU(107), ++ SH7372_PIN_IO_PU(108), SH7372_PIN_IO_PU(109), ++ SH7372_PIN_IO_PU(110), SH7372_PIN_IO_PU(111), ++ SH7372_PIN_IO_PD(112), SH7372_PIN_IO_PD(113), ++ SH7372_PIN_IO_PU(114), SH7372_PIN_IO_PU(115), ++ SH7372_PIN_IO_PU(116), SH7372_PIN_IO_PU(117), ++ SH7372_PIN_IO_PU(118), SH7372_PIN_IO_PU(119), ++ SH7372_PIN_IO_PU(120), SH7372_PIN_IO_PD(121), ++ SH7372_PIN_IO_PD(122), SH7372_PIN_IO_PD(123), ++ SH7372_PIN_IO_PD(124), SH7372_PIN_IO_PD(125), ++ SH7372_PIN_IO_PD(126), SH7372_PIN_IO_PD(127), ++ SH7372_PIN_IO_PD(128), SH7372_PIN_IO_PU_PD(129), ++ SH7372_PIN_IO_PU_PD(130), SH7372_PIN_IO_PU_PD(131), ++ SH7372_PIN_IO_PU_PD(132), SH7372_PIN_IO_PU_PD(133), ++ SH7372_PIN_IO_PU_PD(134), SH7372_PIN_IO_PU_PD(135), ++ SH7372_PIN_IO_PD(136), SH7372_PIN_IO_PD(137), ++ SH7372_PIN_IO_PD(138), SH7372_PIN_IO_PD(139), ++ SH7372_PIN_IO_PD(140), SH7372_PIN_IO_PD(141), ++ SH7372_PIN_IO_PD(142), SH7372_PIN_IO_PU_PD(143), ++ SH7372_PIN_IO_PD(144), SH7372_PIN_IO_PD(145), ++ SH7372_PIN_IO_PD(146), SH7372_PIN_IO_PD(147), ++ SH7372_PIN_IO_PD(148), SH7372_PIN_IO_PD(149), ++ SH7372_PIN_IO_PD(150), SH7372_PIN_IO_PD(151), ++ SH7372_PIN_IO_PU_PD(152), SH7372_PIN_I_PD(153), ++ SH7372_PIN_IO_PU_PD(154), SH7372_PIN_I_PD(155), ++ SH7372_PIN_IO_PD(156), SH7372_PIN_IO_PD(157), ++ SH7372_PIN_I_PD(158), SH7372_PIN_IO_PD(159), ++ SH7372_PIN_O(160), SH7372_PIN_IO_PD(161), ++ SH7372_PIN_IO_PD(162), SH7372_PIN_IO_PD(163), ++ SH7372_PIN_I_PD(164), SH7372_PIN_IO_PD(165), ++ SH7372_PIN_I_PD(166), SH7372_PIN_I_PD(167), ++ SH7372_PIN_I_PD(168), SH7372_PIN_I_PD(169), ++ SH7372_PIN_I_PD(170), SH7372_PIN_O(171), ++ SH7372_PIN_IO_PU_PD(172), SH7372_PIN_IO_PU_PD(173), ++ SH7372_PIN_IO_PU_PD(174), SH7372_PIN_IO_PU_PD(175), ++ SH7372_PIN_IO_PU_PD(176), SH7372_PIN_IO_PU_PD(177), ++ SH7372_PIN_IO_PU_PD(178), SH7372_PIN_O(179), ++ SH7372_PIN_IO_PU_PD(180), SH7372_PIN_IO_PU_PD(181), ++ SH7372_PIN_IO_PU_PD(182), SH7372_PIN_IO_PU_PD(183), ++ SH7372_PIN_IO_PU_PD(184), SH7372_PIN_O(185), ++ SH7372_PIN_IO_PU_PD(186), SH7372_PIN_IO_PU_PD(187), ++ SH7372_PIN_IO_PU_PD(188), SH7372_PIN_IO_PU_PD(189), ++ SH7372_PIN_IO_PU_PD(190), + }; + + /* - BSC -------------------------------------------------------------------- */ +@@ -2136,6 +2137,17 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(usb1), + }; + ++#undef PORTCR ++#define PORTCR(nr, reg) \ ++ { \ ++ PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ ++ _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \ ++ PORT##nr##_FN0, PORT##nr##_FN1, \ ++ PORT##nr##_FN2, PORT##nr##_FN3, \ ++ PORT##nr##_FN4, PORT##nr##_FN5, \ ++ PORT##nr##_FN6, PORT##nr##_FN7 } \ ++ } ++ + static const struct pinmux_cfg_reg pinmux_config_regs[] = { + PORTCR(0, 0xE6051000), /* PORT0CR */ + PORTCR(1, 0xE6051001), /* PORT1CR */ +@@ -2568,11 +2580,80 @@ static const struct pinmux_irq pinmux_irqs[] = { + PINMUX_IRQ(EXT_IRQ16H(31), 138, 184), + }; + ++#define PORTnCR_PULMD_OFF (0 << 6) ++#define PORTnCR_PULMD_DOWN (2 << 6) ++#define PORTnCR_PULMD_UP (3 << 6) ++#define PORTnCR_PULMD_MASK (3 << 6) ++ ++struct sh7372_portcr_group { ++ unsigned int end_pin; ++ unsigned int offset; ++}; ++ ++static const struct sh7372_portcr_group sh7372_portcr_offsets[] = { ++ { 45, 0x1000 }, { 75, 0x2000 }, { 99, 0x0000 }, { 120, 0x3000 }, ++ { 151, 0x0000 }, { 155, 0x3000 }, { 166, 0x0000 }, { 190, 0x2000 }, ++}; ++ ++static void __iomem *sh7372_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < ARRAY_SIZE(sh7372_portcr_offsets); ++i) { ++ const struct sh7372_portcr_group *group = ++ &sh7372_portcr_offsets[i]; ++ ++ if (i <= group->end_pin) ++ return pfc->window->virt + group->offset + pin; ++ } ++ ++ return NULL; ++} ++ ++static unsigned int sh7372_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) ++{ ++ void __iomem *addr = sh7372_pinmux_portcr(pfc, pin); ++ u32 value = ioread8(addr) & PORTnCR_PULMD_MASK; ++ ++ switch (value) { ++ case PORTnCR_PULMD_UP: ++ return PIN_CONFIG_BIAS_PULL_UP; ++ case PORTnCR_PULMD_DOWN: ++ return PIN_CONFIG_BIAS_PULL_DOWN; ++ case PORTnCR_PULMD_OFF: ++ default: ++ return PIN_CONFIG_BIAS_DISABLE; ++ } ++} ++ ++static void sh7372_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, ++ unsigned int bias) ++{ ++ void __iomem *addr = sh7372_pinmux_portcr(pfc, pin); ++ u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK; ++ ++ switch (bias) { ++ case PIN_CONFIG_BIAS_PULL_UP: ++ value |= PORTnCR_PULMD_UP; ++ break; ++ case PIN_CONFIG_BIAS_PULL_DOWN: ++ value |= PORTnCR_PULMD_DOWN; ++ break; ++ } ++ ++ iowrite8(value, addr); ++} ++ ++static const struct sh_pfc_soc_operations sh7372_pinmux_ops = { ++ .get_bias = sh7372_pinmux_get_bias, ++ .set_bias = sh7372_pinmux_set_bias, ++}; ++ + const struct sh_pfc_soc_info sh7372_pinmux_info = { + .name = "sh7372_pfc", ++ .ops = &sh7372_pinmux_ops, ++ + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, +- .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, +- .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0134-sh-pfc-r8a7740-Add-SCIF-pin-groups-and-functions.patch b/patches.renesas/0134-sh-pfc-r8a7740-Add-SCIF-pin-groups-and-functions.patch new file mode 100644 index 00000000000..069daac6deb --- /dev/null +++ b/patches.renesas/0134-sh-pfc-r8a7740-Add-SCIF-pin-groups-and-functions.patch @@ -0,0 +1,405 @@ +From 9e24b780112bfd5ec0437d3d355db14777093195 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 18 Apr 2013 01:04:30 +0200 +Subject: sh-pfc: r8a7740: Add SCIF pin groups and functions + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit cdd2c769356bb31b9a8f399dffb524f25336fe82) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 346 +++++++++++++++++++++++++++++++++++ + 1 file changed, 346 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +index 4753f544..58b02848 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +@@ -1999,6 +1999,28 @@ static const unsigned int mmc0_ctrl_1_pins[] = { + static const unsigned int mmc0_ctrl_1_mux[] = { + MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK, + }; ++/* - SCIFA0 ----------------------------------------------------------------- */ ++static const unsigned int scifa0_data_pins[] = { ++ /* RXD, TXD */ ++ 197, 198, ++}; ++static const unsigned int scifa0_data_mux[] = { ++ SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, ++}; ++static const unsigned int scifa0_clk_pins[] = { ++ /* SCK */ ++ 188, ++}; ++static const unsigned int scifa0_clk_mux[] = { ++ SCIFA0_SCK_MARK, ++}; ++static const unsigned int scifa0_ctrl_pins[] = { ++ /* RTS, CTS */ ++ 194, 193, ++}; ++static const unsigned int scifa0_ctrl_mux[] = { ++ SCIFA0_RTS_MARK, SCIFA0_CTS_MARK, ++}; + /* - SCIFA1 ----------------------------------------------------------------- */ + static const unsigned int scifa1_data_pins[] = { + /* RXD, TXD */ +@@ -2007,6 +2029,230 @@ static const unsigned int scifa1_data_pins[] = { + static const unsigned int scifa1_data_mux[] = { + SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, + }; ++static const unsigned int scifa1_clk_pins[] = { ++ /* SCK */ ++ 185, ++}; ++static const unsigned int scifa1_clk_mux[] = { ++ SCIFA1_SCK_MARK, ++}; ++static const unsigned int scifa1_ctrl_pins[] = { ++ /* RTS, CTS */ ++ 23, 21, ++}; ++static const unsigned int scifa1_ctrl_mux[] = { ++ SCIFA1_RTS_MARK, SCIFA1_CTS_MARK, ++}; ++/* - SCIFA2 ----------------------------------------------------------------- */ ++static const unsigned int scifa2_data_pins[] = { ++ /* RXD, TXD */ ++ 200, 201, ++}; ++static const unsigned int scifa2_data_mux[] = { ++ SCIFA2_RXD_MARK, SCIFA2_TXD_MARK, ++}; ++static const unsigned int scifa2_clk_0_pins[] = { ++ /* SCK */ ++ 22, ++}; ++static const unsigned int scifa2_clk_0_mux[] = { ++ SCIFA2_SCK_PORT22_MARK, ++}; ++static const unsigned int scifa2_clk_1_pins[] = { ++ /* SCK */ ++ 199, ++}; ++static const unsigned int scifa2_clk_1_mux[] = { ++ SCIFA2_SCK_PORT199_MARK, ++}; ++static const unsigned int scifa2_ctrl_pins[] = { ++ /* RTS, CTS */ ++ 96, 95, ++}; ++static const unsigned int scifa2_ctrl_mux[] = { ++ SCIFA2_RTS_MARK, SCIFA2_CTS_MARK, ++}; ++/* - SCIFA3 ----------------------------------------------------------------- */ ++static const unsigned int scifa3_data_0_pins[] = { ++ /* RXD, TXD */ ++ 174, 175, ++}; ++static const unsigned int scifa3_data_0_mux[] = { ++ SCIFA3_RXD_PORT174_MARK, SCIFA3_TXD_PORT175_MARK, ++}; ++static const unsigned int scifa3_clk_0_pins[] = { ++ /* SCK */ ++ 116, ++}; ++static const unsigned int scifa3_clk_0_mux[] = { ++ SCIFA3_SCK_PORT116_MARK, ++}; ++static const unsigned int scifa3_ctrl_0_pins[] = { ++ /* RTS, CTS */ ++ 105, 117, ++}; ++static const unsigned int scifa3_ctrl_0_mux[] = { ++ SCIFA3_RTS_PORT105_MARK, SCIFA3_CTS_PORT117_MARK, ++}; ++static const unsigned int scifa3_data_1_pins[] = { ++ /* RXD, TXD */ ++ 159, 160, ++}; ++static const unsigned int scifa3_data_1_mux[] = { ++ SCIFA3_RXD_PORT159_MARK, SCIFA3_TXD_PORT160_MARK, ++}; ++static const unsigned int scifa3_clk_1_pins[] = { ++ /* SCK */ ++ 158, ++}; ++static const unsigned int scifa3_clk_1_mux[] = { ++ SCIFA3_SCK_PORT158_MARK, ++}; ++static const unsigned int scifa3_ctrl_1_pins[] = { ++ /* RTS, CTS */ ++ 161, 162, ++}; ++static const unsigned int scifa3_ctrl_1_mux[] = { ++ SCIFA3_RTS_PORT161_MARK, SCIFA3_CTS_PORT162_MARK, ++}; ++/* - SCIFA4 ----------------------------------------------------------------- */ ++static const unsigned int scifa4_data_0_pins[] = { ++ /* RXD, TXD */ ++ 12, 13, ++}; ++static const unsigned int scifa4_data_0_mux[] = { ++ SCIFA4_RXD_PORT12_MARK, SCIFA4_TXD_PORT13_MARK, ++}; ++static const unsigned int scifa4_data_1_pins[] = { ++ /* RXD, TXD */ ++ 204, 203, ++}; ++static const unsigned int scifa4_data_1_mux[] = { ++ SCIFA4_RXD_PORT204_MARK, SCIFA4_TXD_PORT203_MARK, ++}; ++static const unsigned int scifa4_data_2_pins[] = { ++ /* RXD, TXD */ ++ 94, 93, ++}; ++static const unsigned int scifa4_data_2_mux[] = { ++ SCIFA4_RXD_PORT94_MARK, SCIFA4_TXD_PORT93_MARK, ++}; ++static const unsigned int scifa4_clk_0_pins[] = { ++ /* SCK */ ++ 21, ++}; ++static const unsigned int scifa4_clk_0_mux[] = { ++ SCIFA4_SCK_PORT21_MARK, ++}; ++static const unsigned int scifa4_clk_1_pins[] = { ++ /* SCK */ ++ 205, ++}; ++static const unsigned int scifa4_clk_1_mux[] = { ++ SCIFA4_SCK_PORT205_MARK, ++}; ++/* - SCIFA5 ----------------------------------------------------------------- */ ++static const unsigned int scifa5_data_0_pins[] = { ++ /* RXD, TXD */ ++ 10, 20, ++}; ++static const unsigned int scifa5_data_0_mux[] = { ++ SCIFA5_RXD_PORT10_MARK, SCIFA5_TXD_PORT20_MARK, ++}; ++static const unsigned int scifa5_data_1_pins[] = { ++ /* RXD, TXD */ ++ 207, 208, ++}; ++static const unsigned int scifa5_data_1_mux[] = { ++ SCIFA5_RXD_PORT207_MARK, SCIFA5_TXD_PORT208_MARK, ++}; ++static const unsigned int scifa5_data_2_pins[] = { ++ /* RXD, TXD */ ++ 92, 91, ++}; ++static const unsigned int scifa5_data_2_mux[] = { ++ SCIFA5_RXD_PORT92_MARK, SCIFA5_TXD_PORT91_MARK, ++}; ++static const unsigned int scifa5_clk_0_pins[] = { ++ /* SCK */ ++ 23, ++}; ++static const unsigned int scifa5_clk_0_mux[] = { ++ SCIFA5_SCK_PORT23_MARK, ++}; ++static const unsigned int scifa5_clk_1_pins[] = { ++ /* SCK */ ++ 206, ++}; ++static const unsigned int scifa5_clk_1_mux[] = { ++ SCIFA5_SCK_PORT206_MARK, ++}; ++/* - SCIFA6 ----------------------------------------------------------------- */ ++static const unsigned int scifa6_data_pins[] = { ++ /* RXD, TXD */ ++ 25, 26, ++}; ++static const unsigned int scifa6_data_mux[] = { ++ SCIFA6_RXD_MARK, SCIFA6_TXD_MARK, ++}; ++static const unsigned int scifa6_clk_pins[] = { ++ /* SCK */ ++ 24, ++}; ++static const unsigned int scifa6_clk_mux[] = { ++ SCIFA6_SCK_MARK, ++}; ++/* - SCIFA7 ----------------------------------------------------------------- */ ++static const unsigned int scifa7_data_pins[] = { ++ /* RXD, TXD */ ++ 0, 1, ++}; ++static const unsigned int scifa7_data_mux[] = { ++ SCIFA7_RXD_MARK, SCIFA7_TXD_MARK, ++}; ++/* - SCIFB ------------------------------------------------------------------ */ ++static const unsigned int scifb_data_0_pins[] = { ++ /* RXD, TXD */ ++ 191, 192, ++}; ++static const unsigned int scifb_data_0_mux[] = { ++ SCIFB_RXD_PORT191_MARK, SCIFB_TXD_PORT192_MARK, ++}; ++static const unsigned int scifb_clk_0_pins[] = { ++ /* SCK */ ++ 190, ++}; ++static const unsigned int scifb_clk_0_mux[] = { ++ SCIFB_SCK_PORT190_MARK, ++}; ++static const unsigned int scifb_ctrl_0_pins[] = { ++ /* RTS, CTS */ ++ 186, 187, ++}; ++static const unsigned int scifb_ctrl_0_mux[] = { ++ SCIFB_RTS_PORT186_MARK, SCIFB_CTS_PORT187_MARK, ++}; ++static const unsigned int scifb_data_1_pins[] = { ++ /* RXD, TXD */ ++ 3, 4, ++}; ++static const unsigned int scifb_data_1_mux[] = { ++ SCIFB_RXD_PORT3_MARK, SCIFB_TXD_PORT4_MARK, ++}; ++static const unsigned int scifb_clk_1_pins[] = { ++ /* SCK */ ++ 2, ++}; ++static const unsigned int scifb_clk_1_mux[] = { ++ SCIFB_SCK_PORT2_MARK, ++}; ++static const unsigned int scifb_ctrl_1_pins[] = { ++ /* RTS, CTS */ ++ 172, 173, ++}; ++static const unsigned int scifb_ctrl_1_mux[] = { ++ SCIFB_RTS_PORT172_MARK, SCIFB_CTS_PORT173_MARK, ++}; + /* - SDHI0 ------------------------------------------------------------------ */ + static const unsigned int sdhi0_data1_pins[] = { + /* D0 */ +@@ -2212,7 +2458,41 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(mmc0_data4_1), + SH_PFC_PIN_GROUP(mmc0_data8_1), + SH_PFC_PIN_GROUP(mmc0_ctrl_1), ++ SH_PFC_PIN_GROUP(scifa0_data), ++ SH_PFC_PIN_GROUP(scifa0_clk), ++ SH_PFC_PIN_GROUP(scifa0_ctrl), + SH_PFC_PIN_GROUP(scifa1_data), ++ SH_PFC_PIN_GROUP(scifa1_clk), ++ SH_PFC_PIN_GROUP(scifa1_ctrl), ++ SH_PFC_PIN_GROUP(scifa2_data), ++ SH_PFC_PIN_GROUP(scifa2_clk_0), ++ SH_PFC_PIN_GROUP(scifa2_clk_1), ++ SH_PFC_PIN_GROUP(scifa2_ctrl), ++ SH_PFC_PIN_GROUP(scifa3_data_0), ++ SH_PFC_PIN_GROUP(scifa3_clk_0), ++ SH_PFC_PIN_GROUP(scifa3_ctrl_0), ++ SH_PFC_PIN_GROUP(scifa3_data_1), ++ SH_PFC_PIN_GROUP(scifa3_clk_1), ++ SH_PFC_PIN_GROUP(scifa3_ctrl_1), ++ SH_PFC_PIN_GROUP(scifa4_data_0), ++ SH_PFC_PIN_GROUP(scifa4_data_1), ++ SH_PFC_PIN_GROUP(scifa4_data_2), ++ SH_PFC_PIN_GROUP(scifa4_clk_0), ++ SH_PFC_PIN_GROUP(scifa4_clk_1), ++ SH_PFC_PIN_GROUP(scifa5_data_0), ++ SH_PFC_PIN_GROUP(scifa5_data_1), ++ SH_PFC_PIN_GROUP(scifa5_data_2), ++ SH_PFC_PIN_GROUP(scifa5_clk_0), ++ SH_PFC_PIN_GROUP(scifa5_clk_1), ++ SH_PFC_PIN_GROUP(scifa6_data), ++ SH_PFC_PIN_GROUP(scifa6_clk), ++ SH_PFC_PIN_GROUP(scifa7_data), ++ SH_PFC_PIN_GROUP(scifb_data_0), ++ SH_PFC_PIN_GROUP(scifb_clk_0), ++ SH_PFC_PIN_GROUP(scifb_ctrl_0), ++ SH_PFC_PIN_GROUP(scifb_data_1), ++ SH_PFC_PIN_GROUP(scifb_clk_1), ++ SH_PFC_PIN_GROUP(scifb_ctrl_1), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), +@@ -2325,8 +2605,66 @@ static const char * const mmc0_groups[] = { + "mmc0_ctrl_1", + }; + ++static const char * const scifa0_groups[] = { ++ "scifa0_data", ++ "scifa0_clk", ++ "scifa0_ctrl", ++}; ++ + static const char * const scifa1_groups[] = { + "scifa1_data", ++ "scifa1_clk", ++ "scifa1_ctrl", ++}; ++ ++static const char * const scifa2_groups[] = { ++ "scifa2_data", ++ "scifa2_clk_0", ++ "scifa2_clk_1", ++ "scifa2_ctrl", ++}; ++ ++static const char * const scifa3_groups[] = { ++ "scifa3_data_0", ++ "scifa3_clk_0", ++ "scifa3_ctrl_0", ++ "scifa3_data_1", ++ "scifa3_clk_1", ++ "scifa3_ctrl_1", ++}; ++ ++static const char * const scifa4_groups[] = { ++ "scifa4_data_0", ++ "scifa4_data_1", ++ "scifa4_data_2", ++ "scifa4_clk_0", ++ "scifa4_clk_1", ++}; ++ ++static const char * const scifa5_groups[] = { ++ "scifa5_data_0", ++ "scifa5_data_1", ++ "scifa5_data_2", ++ "scifa5_clk_0", ++ "scifa5_clk_1", ++}; ++ ++static const char * const scifa6_groups[] = { ++ "scifa6_data", ++ "scifa6_clk", ++}; ++ ++static const char * const scifa7_groups[] = { ++ "scifa7_data", ++}; ++ ++static const char * const scifb_groups[] = { ++ "scifb_data_0", ++ "scifb_clk_0", ++ "scifb_ctrl_0", ++ "scifb_data_1", ++ "scifb_clk_1", ++ "scifb_ctrl_1", + }; + + static const char * const sdhi0_groups[] = { +@@ -2359,7 +2697,15 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(lcd0), + SH_PFC_FUNCTION(lcd1), + SH_PFC_FUNCTION(mmc0), ++ SH_PFC_FUNCTION(scifa0), + SH_PFC_FUNCTION(scifa1), ++ SH_PFC_FUNCTION(scifa2), ++ SH_PFC_FUNCTION(scifa3), ++ SH_PFC_FUNCTION(scifa4), ++ SH_PFC_FUNCTION(scifa5), ++ SH_PFC_FUNCTION(scifa6), ++ SH_PFC_FUNCTION(scifa7), ++ SH_PFC_FUNCTION(scifb), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0135-sh-pfc-r8a7740-Declare-missing-INTC-function.patch b/patches.renesas/0135-sh-pfc-r8a7740-Declare-missing-INTC-function.patch new file mode 100644 index 00000000000..96ec91116e1 --- /dev/null +++ b/patches.renesas/0135-sh-pfc-r8a7740-Declare-missing-INTC-function.patch @@ -0,0 +1,31 @@ +From e65fc8eac484d27daca6e7bdc6a5e55d4a58e91b Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 18 Apr 2013 10:54:18 +0200 +Subject: sh-pfc: r8a7740: Declare missing INTC function + +When adding the INTC pin groups the INTC function hasn't been added to +the functions list. Fix it. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d031696e02c87418221eeb50ecdc4bb812a5897f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +index 58b02848..da00bc40 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +@@ -2694,6 +2694,7 @@ static const char * const sdhi2_groups[] = { + }; + + static const struct sh_pfc_function pinmux_functions[] = { ++ SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(lcd0), + SH_PFC_FUNCTION(lcd1), + SH_PFC_FUNCTION(mmc0), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0136-sh-pfc-r8a7740-Add-BSC-pin-groups-and-functions.patch b/patches.renesas/0136-sh-pfc-r8a7740-Add-BSC-pin-groups-and-functions.patch new file mode 100644 index 00000000000..48a4d4b4d86 --- /dev/null +++ b/patches.renesas/0136-sh-pfc-r8a7740-Add-BSC-pin-groups-and-functions.patch @@ -0,0 +1,203 @@ +From e4a7e624c4afe916eabb98faf26616c1a54ea3ff Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 18 Apr 2013 01:04:30 +0200 +Subject: sh-pfc: r8a7740: Add BSC pin groups and functions + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit b7099c498b6cf9f53bb392f7b0087ad212299707) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 155 +++++++++++++++++++++++++++++++++++ + 1 file changed, 155 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +index da00bc40..f17a39ad 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +@@ -1674,6 +1674,127 @@ static struct sh_pfc_pin pinmux_pins[] = { + GPIO_PORT_ALL(), + }; + ++/* - BSC -------------------------------------------------------------------- */ ++static const unsigned int bsc_data8_pins[] = { ++ /* D[0:7] */ ++ 157, 156, 155, 154, 153, 152, 151, 150, ++}; ++static const unsigned int bsc_data8_mux[] = { ++ D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, ++ D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, ++}; ++static const unsigned int bsc_data16_pins[] = { ++ /* D[0:15] */ ++ 157, 156, 155, 154, 153, 152, 151, 150, ++ 149, 148, 147, 146, 145, 144, 143, 142, ++}; ++static const unsigned int bsc_data16_mux[] = { ++ D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, ++ D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, ++ D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, ++ D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK, ++}; ++static const unsigned int bsc_data32_pins[] = { ++ /* D[0:31] */ ++ 157, 156, 155, 154, 153, 152, 151, 150, ++ 149, 148, 147, 146, 145, 144, 143, 142, ++ 171, 170, 169, 168, 167, 166, 173, 172, ++ 165, 164, 163, 162, 161, 160, 159, 158, ++}; ++static const unsigned int bsc_data32_mux[] = { ++ D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, ++ D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, ++ D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, ++ D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK, ++ D16_MARK, D17_MARK, D18_MARK, D19_MARK, ++ D20_MARK, D21_MARK, D22_MARK, D23_MARK, ++ D24_MARK, D25_MARK, D26_MARK, D27_MARK, ++ D28_MARK, D29_MARK, D30_MARK, D31_MARK, ++}; ++static const unsigned int bsc_cs0_pins[] = { ++ /* CS */ ++ 109, ++}; ++static const unsigned int bsc_cs0_mux[] = { ++ CS0_MARK, ++}; ++static const unsigned int bsc_cs2_pins[] = { ++ /* CS */ ++ 110, ++}; ++static const unsigned int bsc_cs2_mux[] = { ++ CS2_MARK, ++}; ++static const unsigned int bsc_cs4_pins[] = { ++ /* CS */ ++ 111, ++}; ++static const unsigned int bsc_cs4_mux[] = { ++ CS4_MARK, ++}; ++static const unsigned int bsc_cs5a_0_pins[] = { ++ /* CS */ ++ 105, ++}; ++static const unsigned int bsc_cs5a_0_mux[] = { ++ CS5A_PORT105_MARK, ++}; ++static const unsigned int bsc_cs5a_1_pins[] = { ++ /* CS */ ++ 19, ++}; ++static const unsigned int bsc_cs5a_1_mux[] = { ++ CS5A_PORT19_MARK, ++}; ++static const unsigned int bsc_cs5b_pins[] = { ++ /* CS */ ++ 103, ++}; ++static const unsigned int bsc_cs5b_mux[] = { ++ CS5B_MARK, ++}; ++static const unsigned int bsc_cs6a_pins[] = { ++ /* CS */ ++ 104, ++}; ++static const unsigned int bsc_cs6a_mux[] = { ++ CS6A_MARK, ++}; ++static const unsigned int bsc_rd_we8_pins[] = { ++ /* RD, WE[0] */ ++ 115, 113, ++}; ++static const unsigned int bsc_rd_we8_mux[] = { ++ RD_FSC_MARK, WE0_FWE_MARK, ++}; ++static const unsigned int bsc_rd_we16_pins[] = { ++ /* RD, WE[0:1] */ ++ 115, 113, 112, ++}; ++static const unsigned int bsc_rd_we16_mux[] = { ++ RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, ++}; ++static const unsigned int bsc_rd_we32_pins[] = { ++ /* RD, WE[0:3] */ ++ 115, 113, 112, 108, 107, ++}; ++static const unsigned int bsc_rd_we32_mux[] = { ++ RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, WE2_ICIORD_MARK, WE3_ICIOWR_MARK, ++}; ++static const unsigned int bsc_bs_pins[] = { ++ /* BS */ ++ 175, ++}; ++static const unsigned int bsc_bs_mux[] = { ++ BS_MARK, ++}; ++static const unsigned int bsc_rdwr_pins[] = { ++ /* RDWR */ ++ 114, ++}; ++static const unsigned int bsc_rdwr_mux[] = { ++ RDWR_MARK, ++}; + /* - INTC ------------------------------------------------------------------- */ + IRQC_PINS_MUX(0, 0, 2); + IRQC_PINS_MUX(0, 1, 13); +@@ -2377,6 +2498,21 @@ static const unsigned int sdhi2_wp_1_mux[] = { + }; + + static const struct sh_pfc_pin_group pinmux_groups[] = { ++ SH_PFC_PIN_GROUP(bsc_data8), ++ SH_PFC_PIN_GROUP(bsc_data16), ++ SH_PFC_PIN_GROUP(bsc_data32), ++ SH_PFC_PIN_GROUP(bsc_cs0), ++ SH_PFC_PIN_GROUP(bsc_cs2), ++ SH_PFC_PIN_GROUP(bsc_cs4), ++ SH_PFC_PIN_GROUP(bsc_cs5a_0), ++ SH_PFC_PIN_GROUP(bsc_cs5a_1), ++ SH_PFC_PIN_GROUP(bsc_cs5b), ++ SH_PFC_PIN_GROUP(bsc_cs6a), ++ SH_PFC_PIN_GROUP(bsc_rd_we8), ++ SH_PFC_PIN_GROUP(bsc_rd_we16), ++ SH_PFC_PIN_GROUP(bsc_rd_we32), ++ SH_PFC_PIN_GROUP(bsc_bs), ++ SH_PFC_PIN_GROUP(bsc_rdwr), + SH_PFC_PIN_GROUP(intc_irq0_0), + SH_PFC_PIN_GROUP(intc_irq0_1), + SH_PFC_PIN_GROUP(intc_irq1), +@@ -2512,6 +2648,24 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(sdhi2_wp_1), + }; + ++static const char * const bsc_groups[] = { ++ "bsc_data8", ++ "bsc_data16", ++ "bsc_data32", ++ "bsc_cs0", ++ "bsc_cs2", ++ "bsc_cs4", ++ "bsc_cs5a_0", ++ "bsc_cs5a_1", ++ "bsc_cs5b", ++ "bsc_cs6a", ++ "bsc_rd_we8", ++ "bsc_rd_we16", ++ "bsc_rd_we32", ++ "bsc_bs", ++ "bsc_rdwr", ++}; ++ + static const char * const intc_groups[] = { + "intc_irq0_0", + "intc_irq0_1", +@@ -2694,6 +2848,7 @@ static const char * const sdhi2_groups[] = { + }; + + static const struct sh_pfc_function pinmux_functions[] = { ++ SH_PFC_FUNCTION(bsc), + SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(lcd0), + SH_PFC_FUNCTION(lcd1), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0137-sh-pfc-r8a7740-Add-GETHER-pin-groups-and-functions.patch b/patches.renesas/0137-sh-pfc-r8a7740-Add-GETHER-pin-groups-and-functions.patch new file mode 100644 index 00000000000..22da678385f --- /dev/null +++ b/patches.renesas/0137-sh-pfc-r8a7740-Add-GETHER-pin-groups-and-functions.patch @@ -0,0 +1,130 @@ +From 94c161993ac51e1ecca9e5226ab74c5af02801b1 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 18 Apr 2013 01:04:30 +0200 +Subject: sh-pfc: r8a7740: Add GETHER pin groups and functions + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit bae11d30d0cafdc5824dd6ea0bbb1ef229416b72) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 82 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 82 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +index f17a39ad..1b98990c 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +@@ -1795,6 +1795,72 @@ static const unsigned int bsc_rdwr_pins[] = { + static const unsigned int bsc_rdwr_mux[] = { + RDWR_MARK, + }; ++/* - GETHER ----------------------------------------------------------------- */ ++static const unsigned int gether_rmii_pins[] = { ++ /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK, MDC, MDIO */ ++ 195, 196, 194, 193, 200, 201, 199, 159, 202, 208, ++}; ++static const unsigned int gether_rmii_mux[] = { ++ RMII_RXD0_MARK, RMII_RXD1_MARK, RMII_RX_ER_MARK, RMII_CRS_DV_MARK, ++ RMII_TXD0_MARK, RMII_TXD1_MARK, RMII_TX_EN_MARK, RMII_REF50CK_MARK, ++ RMII_MDC_MARK, RMII_MDIO_MARK, ++}; ++static const unsigned int gether_mii_pins[] = { ++ /* RXD[0:3], RX_CLK, RX_DV, RX_ER ++ * TXD[0:3], TX_CLK, TX_EN, TX_ER ++ * CRS, COL, MDC, MDIO, ++ */ ++ 185, 186, 187, 188, 174, 161, 204, ++ 171, 170, 169, 168, 184, 183, 203, ++ 205, 163, 206, 207, ++}; ++static const unsigned int gether_mii_mux[] = { ++ ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK, ++ ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK, ++ ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK, ++ ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK, ++ ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK, ++}; ++static const unsigned int gether_gmii_pins[] = { ++ /* RXD[0:7], RX_CLK, RX_DV, RX_ER ++ * TXD[0:7], GTX_CLK, TX_CLK, TX_EN, TX_ER ++ * CRS, COL, MDC, MDIO, REF125CK_MARK, ++ */ ++ 185, 186, 187, 188, 189, 190, 191, 192, 174, 161, 204, ++ 171, 170, 169, 168, 167, 166, 173, 172, 176, 184, 183, 203, ++ 205, 163, 206, 207, ++}; ++static const unsigned int gether_gmii_mux[] = { ++ ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK, ++ ET_ERXD4_MARK, ET_ERXD5_MARK, ET_ERXD6_MARK, ET_ERXD7_MARK, ++ ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK, ++ ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK, ++ ET_ETXD4_MARK, ET_ETXD5_MARK, ET_ETXD6_MARK, ET_ETXD7_MARK, ++ ET_GTX_CLK_MARK, ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK, ++ ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK, ++ RMII_REF125CK_MARK, ++}; ++static const unsigned int gether_int_pins[] = { ++ /* PHY_INT */ ++ 164, ++}; ++static const unsigned int gether_int_mux[] = { ++ ET_PHY_INT_MARK, ++}; ++static const unsigned int gether_link_pins[] = { ++ /* LINK */ ++ 177, ++}; ++static const unsigned int gether_link_mux[] = { ++ ET_LINK_MARK, ++}; ++static const unsigned int gether_wol_pins[] = { ++ /* WOL */ ++ 175, ++}; ++static const unsigned int gether_wol_mux[] = { ++ ET_WOL_MARK, ++}; + /* - INTC ------------------------------------------------------------------- */ + IRQC_PINS_MUX(0, 0, 2); + IRQC_PINS_MUX(0, 1, 13); +@@ -2513,6 +2579,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(bsc_rd_we32), + SH_PFC_PIN_GROUP(bsc_bs), + SH_PFC_PIN_GROUP(bsc_rdwr), ++ SH_PFC_PIN_GROUP(gether_rmii), ++ SH_PFC_PIN_GROUP(gether_mii), ++ SH_PFC_PIN_GROUP(gether_gmii), ++ SH_PFC_PIN_GROUP(gether_int), ++ SH_PFC_PIN_GROUP(gether_link), ++ SH_PFC_PIN_GROUP(gether_wol), + SH_PFC_PIN_GROUP(intc_irq0_0), + SH_PFC_PIN_GROUP(intc_irq0_1), + SH_PFC_PIN_GROUP(intc_irq1), +@@ -2666,6 +2738,15 @@ static const char * const bsc_groups[] = { + "bsc_rdwr", + }; + ++static const char * const gether_groups[] = { ++ "gether_rmii", ++ "gether_mii", ++ "gether_gmii", ++ "gether_int", ++ "gether_link", ++ "gether_wol", ++}; ++ + static const char * const intc_groups[] = { + "intc_irq0_0", + "intc_irq0_1", +@@ -2849,6 +2930,7 @@ static const char * const sdhi2_groups[] = { + + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(bsc), ++ SH_PFC_FUNCTION(gether), + SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(lcd0), + SH_PFC_FUNCTION(lcd1), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0138-sh-pfc-r8a7740-Add-CEU-pin-groups-and-functions.patch b/patches.renesas/0138-sh-pfc-r8a7740-Add-CEU-pin-groups-and-functions.patch new file mode 100644 index 00000000000..e29c0a4d58f --- /dev/null +++ b/patches.renesas/0138-sh-pfc-r8a7740-Add-CEU-pin-groups-and-functions.patch @@ -0,0 +1,172 @@ +From e29c4f54f32569d1435a9e1801b8c318bcc37f6f Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 18 Apr 2013 01:04:30 +0200 +Subject: sh-pfc: r8a7740: Add CEU pin groups and functions + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 0ec939bd75d4a7905f4dbb79d2eb239ce6e2cbaf) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 124 +++++++++++++++++++++++++++++++++++ + 1 file changed, 124 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +index 1b98990c..71d7c1ff 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +@@ -1795,6 +1795,98 @@ static const unsigned int bsc_rdwr_pins[] = { + static const unsigned int bsc_rdwr_mux[] = { + RDWR_MARK, + }; ++/* - CEU0 ------------------------------------------------------------------- */ ++static const unsigned int ceu0_data_0_7_pins[] = { ++ /* D[0:7] */ ++ 34, 33, 32, 31, 30, 29, 28, 27, ++}; ++static const unsigned int ceu0_data_0_7_mux[] = { ++ VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK, ++ VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK, ++}; ++static const unsigned int ceu0_data_8_15_0_pins[] = { ++ /* D[8:15] */ ++ 182, 181, 180, 179, 178, 26, 25, 24, ++}; ++static const unsigned int ceu0_data_8_15_0_mux[] = { ++ VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK, ++ VIO0_D12_MARK, VIO0_D13_PORT26_MARK, VIO0_D14_PORT25_MARK, ++ VIO0_D15_PORT24_MARK, ++}; ++static const unsigned int ceu0_data_8_15_1_pins[] = { ++ /* D[8:15] */ ++ 182, 181, 180, 179, 178, 22, 95, 96, ++}; ++static const unsigned int ceu0_data_8_15_1_mux[] = { ++ VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK, ++ VIO0_D12_MARK, VIO0_D13_PORT22_MARK, VIO0_D14_PORT95_MARK, ++ VIO0_D15_PORT96_MARK, ++}; ++static const unsigned int ceu0_clk_0_pins[] = { ++ /* CKO */ ++ 36, ++}; ++static const unsigned int ceu0_clk_0_mux[] = { ++ VIO_CKO_MARK, ++}; ++static const unsigned int ceu0_clk_1_pins[] = { ++ /* CKO */ ++ 14, ++}; ++static const unsigned int ceu0_clk_1_mux[] = { ++ VIO_CKO1_MARK, ++}; ++static const unsigned int ceu0_clk_2_pins[] = { ++ /* CKO */ ++ 15, ++}; ++static const unsigned int ceu0_clk_2_mux[] = { ++ VIO_CKO2_MARK, ++}; ++static const unsigned int ceu0_sync_pins[] = { ++ /* CLK, VD, HD */ ++ 35, 39, 37, ++}; ++static const unsigned int ceu0_sync_mux[] = { ++ VIO0_CLK_MARK, VIO0_VD_MARK, VIO0_HD_MARK, ++}; ++static const unsigned int ceu0_field_pins[] = { ++ /* FIELD */ ++ 38, ++}; ++static const unsigned int ceu0_field_mux[] = { ++ VIO0_FIELD_MARK, ++}; ++/* - CEU1 ------------------------------------------------------------------- */ ++static const unsigned int ceu1_data_pins[] = { ++ /* D[0:7] */ ++ 182, 181, 180, 179, 178, 26, 25, 24, ++}; ++static const unsigned int ceu1_data_mux[] = { ++ VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK, ++ VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK, ++}; ++static const unsigned int ceu1_clk_pins[] = { ++ /* CKO */ ++ 23, ++}; ++static const unsigned int ceu1_clk_mux[] = { ++ VIO_CKO_1_MARK, ++}; ++static const unsigned int ceu1_sync_pins[] = { ++ /* CLK, VD, HD */ ++ 197, 198, 160, ++}; ++static const unsigned int ceu1_sync_mux[] = { ++ VIO1_CLK_MARK, VIO1_VD_MARK, VIO1_HD_MARK, ++}; ++static const unsigned int ceu1_field_pins[] = { ++ /* FIELD */ ++ 21, ++}; ++static const unsigned int ceu1_field_mux[] = { ++ VIO1_FIELD_MARK, ++}; + /* - GETHER ----------------------------------------------------------------- */ + static const unsigned int gether_rmii_pins[] = { + /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK, MDC, MDIO */ +@@ -2579,6 +2671,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(bsc_rd_we32), + SH_PFC_PIN_GROUP(bsc_bs), + SH_PFC_PIN_GROUP(bsc_rdwr), ++ SH_PFC_PIN_GROUP(ceu0_data_0_7), ++ SH_PFC_PIN_GROUP(ceu0_data_8_15_0), ++ SH_PFC_PIN_GROUP(ceu0_data_8_15_1), ++ SH_PFC_PIN_GROUP(ceu0_clk_0), ++ SH_PFC_PIN_GROUP(ceu0_clk_1), ++ SH_PFC_PIN_GROUP(ceu0_clk_2), ++ SH_PFC_PIN_GROUP(ceu0_sync), ++ SH_PFC_PIN_GROUP(ceu0_field), ++ SH_PFC_PIN_GROUP(ceu1_data), ++ SH_PFC_PIN_GROUP(ceu1_clk), ++ SH_PFC_PIN_GROUP(ceu1_sync), ++ SH_PFC_PIN_GROUP(ceu1_field), + SH_PFC_PIN_GROUP(gether_rmii), + SH_PFC_PIN_GROUP(gether_mii), + SH_PFC_PIN_GROUP(gether_gmii), +@@ -2738,6 +2842,24 @@ static const char * const bsc_groups[] = { + "bsc_rdwr", + }; + ++static const char * const ceu0_groups[] = { ++ "ceu0_data_0_7", ++ "ceu0_data_8_15_0", ++ "ceu0_data_8_15_1", ++ "ceu0_clk_0", ++ "ceu0_clk_1", ++ "ceu0_clk_2", ++ "ceu0_sync", ++ "ceu0_field", ++}; ++ ++static const char * const ceu1_groups[] = { ++ "ceu1_data", ++ "ceu1_clk", ++ "ceu1_sync", ++ "ceu1_field", ++}; ++ + static const char * const gether_groups[] = { + "gether_rmii", + "gether_mii", +@@ -2930,6 +3052,8 @@ static const char * const sdhi2_groups[] = { + + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(bsc), ++ SH_PFC_FUNCTION(ceu0), ++ SH_PFC_FUNCTION(ceu1), + SH_PFC_FUNCTION(gether), + SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(lcd0), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0139-sh-pfc-r8a7740-Add-FSI-pin-groups-and-functions.patch b/patches.renesas/0139-sh-pfc-r8a7740-Add-FSI-pin-groups-and-functions.patch new file mode 100644 index 00000000000..d23d665bcd1 --- /dev/null +++ b/patches.renesas/0139-sh-pfc-r8a7740-Add-FSI-pin-groups-and-functions.patch @@ -0,0 +1,166 @@ +From b574bc252f68382d14d5c45c62c34187bc4fc1da Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 18 Apr 2013 01:04:30 +0200 +Subject: sh-pfc: r8a7740: Add FSI pin groups and functions + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 909dd95f13d7c8e80565fd17ad6b0065c5c90242) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 118 +++++++++++++++++++++++++++++++++++ + 1 file changed, 118 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +index 71d7c1ff..49da76ae 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +@@ -1887,6 +1887,92 @@ static const unsigned int ceu1_field_pins[] = { + static const unsigned int ceu1_field_mux[] = { + VIO1_FIELD_MARK, + }; ++/* - FSIA ------------------------------------------------------------------- */ ++static const unsigned int fsia_mclk_in_pins[] = { ++ /* CK */ ++ 11, ++}; ++static const unsigned int fsia_mclk_in_mux[] = { ++ FSIACK_MARK, ++}; ++static const unsigned int fsia_mclk_out_pins[] = { ++ /* OMC */ ++ 10, ++}; ++static const unsigned int fsia_mclk_out_mux[] = { ++ FSIAOMC_MARK, ++}; ++static const unsigned int fsia_sclk_in_pins[] = { ++ /* ILR, IBT */ ++ 12, 13, ++}; ++static const unsigned int fsia_sclk_in_mux[] = { ++ FSIAILR_MARK, FSIAIBT_MARK, ++}; ++static const unsigned int fsia_sclk_out_pins[] = { ++ /* OLR, OBT */ ++ 7, 8, ++}; ++static const unsigned int fsia_sclk_out_mux[] = { ++ FSIAOLR_MARK, FSIAOBT_MARK, ++}; ++static const unsigned int fsia_data_in_0_pins[] = { ++ /* ISLD */ ++ 0, ++}; ++static const unsigned int fsia_data_in_0_mux[] = { ++ FSIAISLD_PORT0_MARK, ++}; ++static const unsigned int fsia_data_in_1_pins[] = { ++ /* ISLD */ ++ 5, ++}; ++static const unsigned int fsia_data_in_1_mux[] = { ++ FSIAISLD_PORT5_MARK, ++}; ++static const unsigned int fsia_data_out_0_pins[] = { ++ /* OSLD */ ++ 9, ++}; ++static const unsigned int fsia_data_out_0_mux[] = { ++ FSIAOSLD_MARK, ++}; ++static const unsigned int fsia_data_out_1_pins[] = { ++ /* OSLD */ ++ 0, ++}; ++static const unsigned int fsia_data_out_1_mux[] = { ++ FSIAOSLD1_MARK, ++}; ++static const unsigned int fsia_data_out_2_pins[] = { ++ /* OSLD */ ++ 1, ++}; ++static const unsigned int fsia_data_out_2_mux[] = { ++ FSIAOSLD2_MARK, ++}; ++static const unsigned int fsia_spdif_0_pins[] = { ++ /* SPDIF */ ++ 9, ++}; ++static const unsigned int fsia_spdif_0_mux[] = { ++ FSIASPDIF_PORT9_MARK, ++}; ++static const unsigned int fsia_spdif_1_pins[] = { ++ /* SPDIF */ ++ 18, ++}; ++static const unsigned int fsia_spdif_1_mux[] = { ++ FSIASPDIF_PORT18_MARK, ++}; ++/* - FSIB ------------------------------------------------------------------- */ ++static const unsigned int fsib_mclk_in_pins[] = { ++ /* CK */ ++ 11, ++}; ++static const unsigned int fsib_mclk_in_mux[] = { ++ FSIBCK_MARK, ++}; + /* - GETHER ----------------------------------------------------------------- */ + static const unsigned int gether_rmii_pins[] = { + /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK, MDC, MDIO */ +@@ -2683,6 +2769,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(ceu1_clk), + SH_PFC_PIN_GROUP(ceu1_sync), + SH_PFC_PIN_GROUP(ceu1_field), ++ SH_PFC_PIN_GROUP(fsia_mclk_in), ++ SH_PFC_PIN_GROUP(fsia_mclk_out), ++ SH_PFC_PIN_GROUP(fsia_sclk_in), ++ SH_PFC_PIN_GROUP(fsia_sclk_out), ++ SH_PFC_PIN_GROUP(fsia_data_in_0), ++ SH_PFC_PIN_GROUP(fsia_data_in_1), ++ SH_PFC_PIN_GROUP(fsia_data_out_0), ++ SH_PFC_PIN_GROUP(fsia_data_out_1), ++ SH_PFC_PIN_GROUP(fsia_data_out_2), ++ SH_PFC_PIN_GROUP(fsia_spdif_0), ++ SH_PFC_PIN_GROUP(fsia_spdif_1), ++ SH_PFC_PIN_GROUP(fsib_mclk_in), + SH_PFC_PIN_GROUP(gether_rmii), + SH_PFC_PIN_GROUP(gether_mii), + SH_PFC_PIN_GROUP(gether_gmii), +@@ -2860,6 +2958,24 @@ static const char * const ceu1_groups[] = { + "ceu1_field", + }; + ++static const char * const fsia_groups[] = { ++ "fsia_mclk_in", ++ "fsia_mclk_out", ++ "fsia_sclk_in", ++ "fsia_sclk_out", ++ "fsia_data_in_0", ++ "fsia_data_in_1", ++ "fsia_data_out_0", ++ "fsia_data_out_1", ++ "fsia_data_out_2", ++ "fsia_spdif_0", ++ "fsia_spdif_1", ++}; ++ ++static const char * const fsib_groups[] = { ++ "fsib_mclk_in", ++}; ++ + static const char * const gether_groups[] = { + "gether_rmii", + "gether_mii", +@@ -3054,6 +3170,8 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(bsc), + SH_PFC_FUNCTION(ceu0), + SH_PFC_FUNCTION(ceu1), ++ SH_PFC_FUNCTION(fsia), ++ SH_PFC_FUNCTION(fsib), + SH_PFC_FUNCTION(gether), + SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(lcd0), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0140-sh-pfc-r8a7740-Add-HDMI-pin-groups-and-functions.patch b/patches.renesas/0140-sh-pfc-r8a7740-Add-HDMI-pin-groups-and-functions.patch new file mode 100644 index 00000000000..da98b313a5b --- /dev/null +++ b/patches.renesas/0140-sh-pfc-r8a7740-Add-HDMI-pin-groups-and-functions.patch @@ -0,0 +1,62 @@ +From 3c2c20d274468b74879902a6337fd84c243ecc89 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 18 Apr 2013 01:04:30 +0200 +Subject: sh-pfc: r8a7740: Add HDMI pin groups and functions + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit a37d60659fbef3560c7b4fa5f9d7cf34863f3ae2) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +index 49da76ae..5a77d393 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +@@ -2039,6 +2039,14 @@ static const unsigned int gether_wol_pins[] = { + static const unsigned int gether_wol_mux[] = { + ET_WOL_MARK, + }; ++/* - HDMI ------------------------------------------------------------------- */ ++static const unsigned int hdmi_pins[] = { ++ /* HPD, CEC */ ++ 210, 211, ++}; ++static const unsigned int hdmi_mux[] = { ++ HDMI_HPD_MARK, HDMI_CEC_MARK, ++}; + /* - INTC ------------------------------------------------------------------- */ + IRQC_PINS_MUX(0, 0, 2); + IRQC_PINS_MUX(0, 1, 13); +@@ -2787,6 +2795,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(gether_int), + SH_PFC_PIN_GROUP(gether_link), + SH_PFC_PIN_GROUP(gether_wol), ++ SH_PFC_PIN_GROUP(hdmi), + SH_PFC_PIN_GROUP(intc_irq0_0), + SH_PFC_PIN_GROUP(intc_irq0_1), + SH_PFC_PIN_GROUP(intc_irq1), +@@ -2985,6 +2994,10 @@ static const char * const gether_groups[] = { + "gether_wol", + }; + ++static const char * const hdmi_groups[] = { ++ "hdmi", ++}; ++ + static const char * const intc_groups[] = { + "intc_irq0_0", + "intc_irq0_1", +@@ -3173,6 +3186,7 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(fsia), + SH_PFC_FUNCTION(fsib), + SH_PFC_FUNCTION(gether), ++ SH_PFC_FUNCTION(hdmi), + SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(lcd0), + SH_PFC_FUNCTION(lcd1), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0141-sh-pfc-r8a7740-Hardcode-the-LCDC0-output.patch b/patches.renesas/0141-sh-pfc-r8a7740-Hardcode-the-LCDC0-output.patch new file mode 100644 index 00000000000..7a400078b29 --- /dev/null +++ b/patches.renesas/0141-sh-pfc-r8a7740-Hardcode-the-LCDC0-output.patch @@ -0,0 +1,79 @@ +From 9aeb0e74e055e295f22d855807433dc522ff90af Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Apr 2013 11:52:59 +0200 +Subject: sh-pfc: r8a7740: Hardcode the LCDC0 output + +The r8a7740 has two LCDC units and two sets of LCDC output signals. By +default LCDC0 is routed to the LCD0 signals, and LCDC1 to the LCD1 +signals. However, LCDC1 can be routed to the LCD0 signals by setting bit +MSEL6 in MSEL3CR (the LCD0 signals are further pinmuxed the usual way). + +This could be configured by duplicating the LCD0 pin groups for LCDC1. +However, this would unnecessarily complicate the LCD pin groups, as no +r8a7740 board supported in mainline use such a configuration. Hardcode +the MSEL3CR MSEL6 bit to 0 for now. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit b79839024f41bca04098eff0f85e66cf20c15a2a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 14 +------------- + 1 file changed, 1 insertion(+), 13 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +index 5a77d393..9afc7b0e 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +@@ -277,8 +277,6 @@ enum { + SCIFB_CTS_PORT173_MARK, + + /* LCD0 */ +- LCDC0_SELECT_MARK, +- + LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, + LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, + LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, +@@ -301,8 +299,6 @@ enum { + LCD0_LCLK_PORT102_MARK, + + /* LCD1 */ +- LCDC1_SELECT_MARK, +- + LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, + LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, + LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, +@@ -1002,7 +998,7 @@ static const pinmux_enum_t pinmux_data[] = { + PINMUX_DATA(IRQ27_PORT57_MARK, PORT57_FN0, MSEL1CR_27_1), + + /* Port58 */ +- PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1), ++ PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1, MSEL3CR_6_0), + PINMUX_DATA(KEYOUT7_MARK, PORT58_FN3), + PINMUX_DATA(KEYIN0_PORT58_MARK, PORT58_FN4, MSEL4CR_18_1), + PINMUX_DATA(DV_D0_MARK, PORT58_FN6), +@@ -1649,10 +1645,6 @@ static const pinmux_enum_t pinmux_data[] = { + PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1), + PINMUX_DATA(HDMI_CEC_MARK, PORT211_FN1), + +- /* LCDC select */ +- PINMUX_DATA(LCDC0_SELECT_MARK, MSEL3CR_6_0), +- PINMUX_DATA(LCDC1_SELECT_MARK, MSEL3CR_6_1), +- + /* SDENC */ + PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0), + PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1), +@@ -3578,10 +3570,6 @@ static const struct pinmux_func pinmux_func_gpios[] = { + /* IRREM */ + GPIO_FN(IROUT), + +- /* LCDC */ +- GPIO_FN(LCDC0_SELECT), +- GPIO_FN(LCDC1_SELECT), +- + /* SDENC */ + GPIO_FN(SDENC_CPG), + GPIO_FN(SDENC_DV_CLKI), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0142-ARM-shmobile-armadillo800eva-Register-pinctrl-mappin.patch b/patches.renesas/0142-ARM-shmobile-armadillo800eva-Register-pinctrl-mappin.patch new file mode 100644 index 00000000000..585a241f44f --- /dev/null +++ b/patches.renesas/0142-ARM-shmobile-armadillo800eva-Register-pinctrl-mappin.patch @@ -0,0 +1,62 @@ +From 568d95dda5bb39d4d6aea40f4e1d9b963c6c673a Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 18 Apr 2013 01:18:41 +0200 +Subject: ARM: shmobile: armadillo800eva: Register pinctrl mapping for INTC + +Replace the GPIO-based INTC pinmux configuration by a pinctrl mapping. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 89ae7b5bbd3e65bc6ab7a577ca5ec18569589c8c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-armadillo800eva.c | 18 +++++++++++------- + 1 file changed, 11 insertions(+), 7 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c +index b85b2882..8d8b3624 100644 +--- a/arch/arm/mach-shmobile/board-armadillo800eva.c ++++ b/arch/arm/mach-shmobile/board-armadillo800eva.c +@@ -1065,6 +1065,12 @@ static const struct pinctrl_map eva_pinctrl_map[] = { + "sdhi0_ctrl", "sdhi0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740", + "sdhi0_wp", "sdhi0"), ++ /* ST1232 */ ++ PIN_MAP_MUX_GROUP_DEFAULT("0-0055", "pfc-r8a7740", ++ "intc_irq10", "intc"), ++ /* USBHS */ ++ PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-r8a7740", ++ "intc_irq7_1", "intc"), + }; + + static void __init eva_clock_init(void) +@@ -1130,7 +1136,7 @@ static void __init eva_init(void) + gpio_request_one(202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */ + + /* Touchscreen */ +- gpio_request(GPIO_FN_IRQ10, NULL); /* TP_INT */ ++ gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */ + + /* GETHER */ + gpio_request(GPIO_FN_ET_CRS, NULL); +@@ -1163,13 +1169,11 @@ static void __init eva_init(void) + } else { + /* USB Func */ + /* +- * A1 chip has 2 IRQ7 pin and it was controled by MSEL register. +- * OTOH, usbhs interrupt needs its value (HI/LOW) to decide +- * USB connection/disconnection (usbhsf_get_vbus()). +- * This means we needs to select GPIO_FN_IRQ7_PORT209 first, +- * and select GPIO 209 here ++ * The USBHS interrupt handlers needs to read the IRQ pin value ++ * (HI/LOW) to diffentiate USB connection and disconnection ++ * events (usbhsf_get_vbus()). We thus need to select both the ++ * intc_irq7_1 pin group and GPIO 209 here. + */ +- gpio_request(GPIO_FN_IRQ7_PORT209, NULL); + gpio_request_one(209, GPIOF_IN, NULL); + + platform_device_register(&usbhsf_device); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0143-ARM-shmobile-armadillo800eva-Register-pinctrl-mappin.patch b/patches.renesas/0143-ARM-shmobile-armadillo800eva-Register-pinctrl-mappin.patch new file mode 100644 index 00000000000..ad6179156ba --- /dev/null +++ b/patches.renesas/0143-ARM-shmobile-armadillo800eva-Register-pinctrl-mappin.patch @@ -0,0 +1,61 @@ +From 21e7273cc83bb9d8f5e1eac41681b0f226af0834 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 18 Apr 2013 01:18:41 +0200 +Subject: ARM: shmobile: armadillo800eva: Register pinctrl mapping for GETHER + +Replace the GPIO-based GETHER pinmux configuration by a pinctrl mapping. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 613285ce72c2194d43dee43a2b3c9bac6acff792) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-armadillo800eva.c | 25 +++++-------------------- + 1 file changed, 5 insertions(+), 20 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c +index 8d8b3624..328f6502 100644 +--- a/arch/arm/mach-shmobile/board-armadillo800eva.c ++++ b/arch/arm/mach-shmobile/board-armadillo800eva.c +@@ -1046,6 +1046,11 @@ static struct platform_device *eva_devices[] __initdata = { + }; + + static const struct pinctrl_map eva_pinctrl_map[] = { ++ /* GETHER */ ++ PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740", ++ "gether_mii", "gether"), ++ PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740", ++ "gether_int", "gether"), + /* LCD0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740", + "lcd0_data24_0", "lcd0"), +@@ -1139,26 +1144,6 @@ static void __init eva_init(void) + gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */ + + /* GETHER */ +- gpio_request(GPIO_FN_ET_CRS, NULL); +- gpio_request(GPIO_FN_ET_MDC, NULL); +- gpio_request(GPIO_FN_ET_MDIO, NULL); +- gpio_request(GPIO_FN_ET_TX_ER, NULL); +- gpio_request(GPIO_FN_ET_RX_ER, NULL); +- gpio_request(GPIO_FN_ET_ERXD0, NULL); +- gpio_request(GPIO_FN_ET_ERXD1, NULL); +- gpio_request(GPIO_FN_ET_ERXD2, NULL); +- gpio_request(GPIO_FN_ET_ERXD3, NULL); +- gpio_request(GPIO_FN_ET_TX_CLK, NULL); +- gpio_request(GPIO_FN_ET_TX_EN, NULL); +- gpio_request(GPIO_FN_ET_ETXD0, NULL); +- gpio_request(GPIO_FN_ET_ETXD1, NULL); +- gpio_request(GPIO_FN_ET_ETXD2, NULL); +- gpio_request(GPIO_FN_ET_ETXD3, NULL); +- gpio_request(GPIO_FN_ET_PHY_INT, NULL); +- gpio_request(GPIO_FN_ET_COL, NULL); +- gpio_request(GPIO_FN_ET_RX_DV, NULL); +- gpio_request(GPIO_FN_ET_RX_CLK, NULL); +- + gpio_request_one(18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */ + + /* USB */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0144-ARM-shmobile-armadillo800eva-Register-pinctrl-mappin.patch b/patches.renesas/0144-ARM-shmobile-armadillo800eva-Register-pinctrl-mappin.patch new file mode 100644 index 00000000000..6b6f5b0b3aa --- /dev/null +++ b/patches.renesas/0144-ARM-shmobile-armadillo800eva-Register-pinctrl-mappin.patch @@ -0,0 +1,60 @@ +From 6abf484720cf8bde6890eddb2149aeb51c4e7d80 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 18 Apr 2013 01:18:41 +0200 +Subject: ARM: shmobile: armadillo800eva: Register pinctrl mapping for CEU0 + +Replace the GPIO-based CEU0 pinmux configuration by a pinctrl mapping. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit babde827f26223149dc33ffc5237458ac9e30c96) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-armadillo800eva.c | 24 +++++++++--------------- + 1 file changed, 9 insertions(+), 15 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c +index 328f6502..4327f7e6 100644 +--- a/arch/arm/mach-shmobile/board-armadillo800eva.c ++++ b/arch/arm/mach-shmobile/board-armadillo800eva.c +@@ -1046,6 +1046,15 @@ static struct platform_device *eva_devices[] __initdata = { + }; + + static const struct pinctrl_map eva_pinctrl_map[] = { ++ /* CEU0 */ ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740", ++ "ceu0_data_0_7", "ceu0"), ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740", ++ "ceu0_clk_0", "ceu0"), ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740", ++ "ceu0_sync", "ceu0"), ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740", ++ "ceu0_field", "ceu0"), + /* GETHER */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740", + "gether_mii", "gether"), +@@ -1165,21 +1174,6 @@ static void __init eva_init(void) + usb = &usbhsf_device; + } + +- /* CEU0 */ +- gpio_request(GPIO_FN_VIO0_D7, NULL); +- gpio_request(GPIO_FN_VIO0_D6, NULL); +- gpio_request(GPIO_FN_VIO0_D5, NULL); +- gpio_request(GPIO_FN_VIO0_D4, NULL); +- gpio_request(GPIO_FN_VIO0_D3, NULL); +- gpio_request(GPIO_FN_VIO0_D2, NULL); +- gpio_request(GPIO_FN_VIO0_D1, NULL); +- gpio_request(GPIO_FN_VIO0_D0, NULL); +- gpio_request(GPIO_FN_VIO0_CLK, NULL); +- gpio_request(GPIO_FN_VIO0_HD, NULL); +- gpio_request(GPIO_FN_VIO0_VD, NULL); +- gpio_request(GPIO_FN_VIO0_FIELD, NULL); +- gpio_request(GPIO_FN_VIO_CKO, NULL); +- + /* CON1/CON15 Camera */ + gpio_request_one(173, GPIOF_OUT_INIT_LOW, NULL); /* STANDBY */ + gpio_request_one(172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0145-ARM-shmobile-armadillo800eva-Register-pinctrl-mappin.patch b/patches.renesas/0145-ARM-shmobile-armadillo800eva-Register-pinctrl-mappin.patch new file mode 100644 index 00000000000..e33d6c06baf --- /dev/null +++ b/patches.renesas/0145-ARM-shmobile-armadillo800eva-Register-pinctrl-mappin.patch @@ -0,0 +1,62 @@ +From 1fe3b7d1c2a6541417fbe5ad1a3ffb6e6d75da93 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 18 Apr 2013 01:18:41 +0200 +Subject: ARM: shmobile: armadillo800eva: Register pinctrl mapping for FSI + +Replace the GPIO-based FSI pinmux configuration by a pinctrl mapping. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit fed8976e39198a86751c5283ff43643c3d9294a4) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-armadillo800eva.c | 21 ++++++++++++--------- + 1 file changed, 12 insertions(+), 9 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c +index 4327f7e6..4e1f8f3f 100644 +--- a/arch/arm/mach-shmobile/board-armadillo800eva.c ++++ b/arch/arm/mach-shmobile/board-armadillo800eva.c +@@ -1055,6 +1055,18 @@ static const struct pinctrl_map eva_pinctrl_map[] = { + "ceu0_sync", "ceu0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740", + "ceu0_field", "ceu0"), ++ /* FSIA */ ++ PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740", ++ "fsia_sclk_in", "fsia"), ++ PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740", ++ "fsia_mclk_out", "fsia"), ++ PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740", ++ "fsia_data_in_1", "fsia"), ++ PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740", ++ "fsia_data_out_0", "fsia"), ++ /* FSIB */ ++ PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-r8a7740", ++ "fsib_mclk_in", "fsib"), + /* GETHER */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740", + "gether_mii", "gether"), +@@ -1181,20 +1193,11 @@ static void __init eva_init(void) + gpio_request_one(158, GPIOF_OUT_INIT_LOW, NULL); /* CAM_PON */ + + /* FSI-WM8978 */ +- gpio_request(GPIO_FN_FSIAIBT, NULL); +- gpio_request(GPIO_FN_FSIAILR, NULL); +- gpio_request(GPIO_FN_FSIAOMC, NULL); +- gpio_request(GPIO_FN_FSIAOSLD, NULL); +- gpio_request(GPIO_FN_FSIAISLD_PORT5, NULL); +- + gpio_request(7, NULL); + gpio_request(8, NULL); + gpio_direction_none(GPIO_PORT7CR); /* FSIAOBT needs no direction */ + gpio_direction_none(GPIO_PORT8CR); /* FSIAOLR needs no direction */ + +- /* FSI-HDMI */ +- gpio_request(GPIO_FN_FSIBCK, NULL); +- + /* HDMI */ + gpio_request(GPIO_FN_HDMI_HPD, NULL); + gpio_request(GPIO_FN_HDMI_CEC, NULL); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0146-ARM-shmobile-armadillo800eva-Register-pinctrl-mappin.patch b/patches.renesas/0146-ARM-shmobile-armadillo800eva-Register-pinctrl-mappin.patch new file mode 100644 index 00000000000..007be39a180 --- /dev/null +++ b/patches.renesas/0146-ARM-shmobile-armadillo800eva-Register-pinctrl-mappin.patch @@ -0,0 +1,43 @@ +From 97fdbc53628831349cef2025135750c0dcb2e58b Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 18 Apr 2013 01:18:41 +0200 +Subject: ARM: shmobile: armadillo800eva: Register pinctrl mapping for HDMI + +Replace the GPIO-based HDMI pinmux configuration by a pinctrl mapping. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit f1bb4ab084626b093ed050dc979144b73f2efc03) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-armadillo800eva.c | 7 +++---- + 1 file changed, 3 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c +index 4e1f8f3f..dad4966d 100644 +--- a/arch/arm/mach-shmobile/board-armadillo800eva.c ++++ b/arch/arm/mach-shmobile/board-armadillo800eva.c +@@ -1072,6 +1072,9 @@ static const struct pinctrl_map eva_pinctrl_map[] = { + "gether_mii", "gether"), + PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740", + "gether_int", "gether"), ++ /* HDMI */ ++ PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-r8a7740", ++ "hdmi", "hdmi"), + /* LCD0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740", + "lcd0_data24_0", "lcd0"), +@@ -1198,10 +1201,6 @@ static void __init eva_init(void) + gpio_direction_none(GPIO_PORT7CR); /* FSIAOBT needs no direction */ + gpio_direction_none(GPIO_PORT8CR); /* FSIAOLR needs no direction */ + +- /* HDMI */ +- gpio_request(GPIO_FN_HDMI_HPD, NULL); +- gpio_request(GPIO_FN_HDMI_CEC, NULL); +- + /* + * CAUTION + * +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0147-ARM-shmobile-armadillo800eva-Don-t-configure-LCDC-ro.patch b/patches.renesas/0147-ARM-shmobile-armadillo800eva-Don-t-configure-LCDC-ro.patch new file mode 100644 index 00000000000..ca8c8446bb8 --- /dev/null +++ b/patches.renesas/0147-ARM-shmobile-armadillo800eva-Don-t-configure-LCDC-ro.patch @@ -0,0 +1,32 @@ +From 90670c7d11c9867a38ed0d7d78160abc604e44c3 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 23 Apr 2013 00:17:58 +0200 +Subject: ARM: shmobile: armadillo800eva: Don't configure LCDC routing manually + +LCDC routing is configured automatically in the PFC driver, don't +configure it manually in board code. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 1b5961c31d67d0c2fcce202af3c4ccdb9385eaa7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-armadillo800eva.c | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c +index dad4966d..8ec69612 100644 +--- a/arch/arm/mach-shmobile/board-armadillo800eva.c ++++ b/arch/arm/mach-shmobile/board-armadillo800eva.c +@@ -1159,8 +1159,6 @@ static void __init eva_init(void) + gpio_request(GPIO_FN_SCIFA1_TXD, NULL); + + /* LCDC0 */ +- gpio_request(GPIO_FN_LCDC0_SELECT, NULL); +- + gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ + gpio_request_one(202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */ + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0148-ARM-shmobile-armadillo800eva-Replace-GPIO_PORTx-with.patch b/patches.renesas/0148-ARM-shmobile-armadillo800eva-Replace-GPIO_PORTx-with.patch new file mode 100644 index 00000000000..e34a36ecd41 --- /dev/null +++ b/patches.renesas/0148-ARM-shmobile-armadillo800eva-Replace-GPIO_PORTx-with.patch @@ -0,0 +1,79 @@ +From bb8cb923760b515f0420c8d10104f0506ee7e30f Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 23 Apr 2013 00:32:52 +0200 +Subject: ARM: shmobile: armadillo800eva: Replace GPIO_PORTx with GPIO port + numbers + +The PFC GPIO API implementation moved to using port numbers. Replace all +GPIO_PORTx enum usage with the corresponding port number. The GPIO_PORTx +enum values are identical to the port number on this platform. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit f5c02edc51515ea0bcb461030d0a13f7af41e979) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-armadillo800eva.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c +index 8ec69612..aafa99b1 100644 +--- a/arch/arm/mach-shmobile/board-armadillo800eva.c ++++ b/arch/arm/mach-shmobile/board-armadillo800eva.c +@@ -584,7 +584,7 @@ static struct regulator_init_data vcc_sdhi0_init_data = { + static struct fixed_voltage_config vcc_sdhi0_info = { + .supply_name = "SDHI0 Vcc", + .microvolts = 3300000, +- .gpio = GPIO_PORT75, ++ .gpio = 75, + .enable_high = 1, + .init_data = &vcc_sdhi0_init_data, + }; +@@ -615,7 +615,7 @@ static struct regulator_init_data vccq_sdhi0_init_data = { + }; + + static struct gpio vccq_sdhi0_gpios[] = { +- {GPIO_PORT17, GPIOF_OUT_INIT_LOW, "vccq-sdhi0" }, ++ {17, GPIOF_OUT_INIT_LOW, "vccq-sdhi0" }, + }; + + static struct gpio_regulator_state vccq_sdhi0_states[] = { +@@ -626,7 +626,7 @@ static struct gpio_regulator_state vccq_sdhi0_states[] = { + static struct gpio_regulator_config vccq_sdhi0_info = { + .supply_name = "vqmmc", + +- .enable_gpio = GPIO_PORT74, ++ .enable_gpio = 74, + .enable_high = 1, + .enabled_at_boot = 0, + +@@ -664,7 +664,7 @@ static struct regulator_init_data vcc_sdhi1_init_data = { + static struct fixed_voltage_config vcc_sdhi1_info = { + .supply_name = "SDHI1 Vcc", + .microvolts = 3300000, +- .gpio = GPIO_PORT16, ++ .gpio = 16, + .enable_high = 1, + .init_data = &vcc_sdhi1_init_data, + }; +@@ -693,7 +693,7 @@ static struct sh_mobile_sdhi_info sdhi0_info = { + .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | + MMC_CAP_POWER_OFF_CARD, + .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD, +- .cd_gpio = GPIO_PORT167, ++ .cd_gpio = 167, + }; + + static struct resource sdhi0_resources[] = { +@@ -736,7 +736,7 @@ static struct sh_mobile_sdhi_info sdhi1_info = { + MMC_CAP_POWER_OFF_CARD, + .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD, + /* Port72 cannot generate IRQs, will be used in polling mode. */ +- .cd_gpio = GPIO_PORT72, ++ .cd_gpio = 72, + }; + + static struct resource sdhi1_resources[] = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0149-ARM-shmobile-bonito-Remove-empty-core-devices-array.patch b/patches.renesas/0149-ARM-shmobile-bonito-Remove-empty-core-devices-array.patch new file mode 100644 index 00000000000..404be6dc119 --- /dev/null +++ b/patches.renesas/0149-ARM-shmobile-bonito-Remove-empty-core-devices-array.patch @@ -0,0 +1,46 @@ +From e2e7f309ba49b69a1cbfec76b2f5a11cd47c73ea Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 18 Apr 2013 01:27:32 +0200 +Subject: ARM: shmobile: bonito: Remove empty core devices array + +The core devices array is empty, passing it to platform_add_devices() is +a no-op. Remove it. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 6c887d2c0918f37fd5fb2493c605bd73cb25e326) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-bonito.c | 9 --------- + 1 file changed, 9 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c +index 70d992c5..b111c135 100644 +--- a/arch/arm/mach-shmobile/board-bonito.c ++++ b/arch/arm/mach-shmobile/board-bonito.c +@@ -331,12 +331,6 @@ static struct platform_device smsc_device = { + }; + + /* +- * core board devices +- */ +-static struct platform_device *bonito_core_devices[] __initdata = { +-}; +- +-/* + * base board devices + */ + static struct platform_device *bonito_base_devices[] __initdata = { +@@ -397,9 +391,6 @@ static void __init bonito_init(void) + + r8a7740_add_standard_devices(); + +- platform_add_devices(bonito_core_devices, +- ARRAY_SIZE(bonito_core_devices)); +- + /* + * base board settings + */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0150-ARM-shmobile-bonito-Register-pinctrl-mapping-for-SCI.patch b/patches.renesas/0150-ARM-shmobile-bonito-Register-pinctrl-mapping-for-SCI.patch new file mode 100644 index 00000000000..6f55813d0cc --- /dev/null +++ b/patches.renesas/0150-ARM-shmobile-bonito-Register-pinctrl-mapping-for-SCI.patch @@ -0,0 +1,46 @@ +From 7533a4ba08bfeacc798173253bd3bf8172b1951d Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 18 Apr 2013 01:18:41 +0200 +Subject: ARM: shmobile: bonito: Register pinctrl mapping for SCIF + +Replace the GPIO-based SCIF pinmux configuration by a pinctrl mapping. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 7cded0c90badbf396345e46459a6cbca14fc7ae3) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-bonito.c | 10 ++++++++-- + 1 file changed, 8 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c +index b111c135..b6620662 100644 +--- a/arch/arm/mach-shmobile/board-bonito.c ++++ b/arch/arm/mach-shmobile/board-bonito.c +@@ -369,6 +369,12 @@ static void __init bonito_map_io(void) + #define VCCQ1CR IOMEM(0xE6058140) + #define VCCQ1LCDCR IOMEM(0xE6058186) + ++static const struct pinctrl_map scifa5_pinctrl_map[] = { ++ /* SCIFA5 */ ++ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.5", "pfc-r8a7740", ++ "scifa5_data_2", "scifa5"), ++}; ++ + static void __init bonito_init(void) + { + u16 val; +@@ -423,8 +429,8 @@ static void __init bonito_init(void) + if (BIT_OFF(bsw2, 1) && /* S38.3 = ON */ + BIT_OFF(bsw3, 9) && /* S39.6 = ON */ + BIT_OFF(bsw4, 4)) { /* S43.1 = ON */ +- gpio_request(GPIO_FN_SCIFA5_TXD_PORT91, NULL); +- gpio_request(GPIO_FN_SCIFA5_RXD_PORT92, NULL); ++ pinctrl_register_mappings(scifa5_pinctrl_map, ++ ARRAY_SIZE(scifa5_pinctrl_map)); + } + + /* +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0151-ARM-shmobile-bonito-Register-pinctrl-mapping-for-INT.patch b/patches.renesas/0151-ARM-shmobile-bonito-Register-pinctrl-mapping-for-INT.patch new file mode 100644 index 00000000000..222aa19e9e6 --- /dev/null +++ b/patches.renesas/0151-ARM-shmobile-bonito-Register-pinctrl-mapping-for-INT.patch @@ -0,0 +1,57 @@ +From 9ea265aed1dfc8cacdd4d21c0d29a13c65d8acd1 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 18 Apr 2013 01:18:41 +0200 +Subject: ARM: shmobile: bonito: Register pinctrl mapping for INTC + +Replace the GPIO-based INTC pinmux configuration by a pinctrl mapping. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit f569b10f66f1038550b960848c187584a11c9e3a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-bonito.c | 14 +++++++++++++- + 1 file changed, 13 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c +index b6620662..5076f4d5 100644 +--- a/arch/arm/mach-shmobile/board-bonito.c ++++ b/arch/arm/mach-shmobile/board-bonito.c +@@ -369,6 +369,17 @@ static void __init bonito_map_io(void) + #define VCCQ1CR IOMEM(0xE6058140) + #define VCCQ1LCDCR IOMEM(0xE6058186) + ++/* ++ * HACK: The FPGA mappings should be associated with the FPGA device, but we ++ * don't have one at the moment. Associate them with the PFC device to make ++ * sure they will be applied. ++ */ ++static const struct pinctrl_map fpga_pinctrl_map[] = { ++ /* FPGA */ ++ PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740", ++ "intc_irq10", "intc"), ++}; ++ + static const struct pinctrl_map scifa5_pinctrl_map[] = { + /* SCIFA5 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.5", "pfc-r8a7740", +@@ -381,6 +392,8 @@ static void __init bonito_init(void) + + regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); + ++ pinctrl_register_mappings(fpga_pinctrl_map, ++ ARRAY_SIZE(fpga_pinctrl_map)); + r8a7740_pinmux_init(); + bonito_fpga_init(); + +@@ -412,7 +425,6 @@ static void __init bonito_init(void) + gpio_request(GPIO_FN_CS5B, NULL); + gpio_request(GPIO_FN_CS6A, NULL); + gpio_request(GPIO_FN_CS5A_PORT105, NULL); +- gpio_request(GPIO_FN_IRQ10, NULL); + + val = bonito_fpga_read(BVERR); + pr_info("bonito version: cpu %02x, base %02x\n", +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0152-ARM-shmobile-bonito-Register-pinctrl-mapping-for-BSC.patch b/patches.renesas/0152-ARM-shmobile-bonito-Register-pinctrl-mapping-for-BSC.patch new file mode 100644 index 00000000000..f90b43f7ad9 --- /dev/null +++ b/patches.renesas/0152-ARM-shmobile-bonito-Register-pinctrl-mapping-for-BSC.patch @@ -0,0 +1,49 @@ +From 831f716282318852998dc6349fcee3aff7cb4303 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 18 Apr 2013 01:18:41 +0200 +Subject: ARM: shmobile: bonito: Register pinctrl mapping for BSC + +Replace the GPIO-based BSC pinmux configuration by a pinctrl mapping. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 055b246946976616de6c7ba3acc1fd5a614b96b0) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-bonito.c | 13 ++++++------- + 1 file changed, 6 insertions(+), 7 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c +index 5076f4d5..2781c7fd 100644 +--- a/arch/arm/mach-shmobile/board-bonito.c ++++ b/arch/arm/mach-shmobile/board-bonito.c +@@ -377,6 +377,12 @@ static void __init bonito_map_io(void) + static const struct pinctrl_map fpga_pinctrl_map[] = { + /* FPGA */ + PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740", ++ "bsc_cs5a_0", "bsc"), ++ PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740", ++ "bsc_cs5b", "bsc"), ++ PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740", ++ "bsc_cs6a", "bsc"), ++ PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740", + "intc_irq10", "intc"), + }; + +@@ -419,13 +425,6 @@ static void __init bonito_init(void) + u16 bsw3; + u16 bsw4; + +- /* +- * FPGA +- */ +- gpio_request(GPIO_FN_CS5B, NULL); +- gpio_request(GPIO_FN_CS6A, NULL); +- gpio_request(GPIO_FN_CS5A_PORT105, NULL); +- + val = bonito_fpga_read(BVERR); + pr_info("bonito version: cpu %02x, base %02x\n", + ((val >> 8) & 0xFF), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0153-ARM-shmobile-bonito-Don-t-configure-LCDC-routing-man.patch b/patches.renesas/0153-ARM-shmobile-bonito-Don-t-configure-LCDC-routing-man.patch new file mode 100644 index 00000000000..860645f25cf --- /dev/null +++ b/patches.renesas/0153-ARM-shmobile-bonito-Don-t-configure-LCDC-routing-man.patch @@ -0,0 +1,31 @@ +From b83d43ef343898faba7ba5504723a3c37766a7df Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 23 Apr 2013 00:17:58 +0200 +Subject: ARM: shmobile: bonito: Don't configure LCDC routing manually + +LCDC routing is configured automatically in the PFC driver, don't +configure it manually in board code. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 8be14c78e751205b1c0f4b38fa417d5fe5cc15d1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-bonito.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c +index 2781c7fd..b373e9ce 100644 +--- a/arch/arm/mach-shmobile/board-bonito.c ++++ b/arch/arm/mach-shmobile/board-bonito.c +@@ -451,7 +451,6 @@ static void __init bonito_init(void) + BIT_ON(bsw2, 2)) { /* S38.2 = OFF */ + pinctrl_register_mappings(lcdc0_pinctrl_map, + ARRAY_SIZE(lcdc0_pinctrl_map)); +- gpio_request(GPIO_FN_LCDC0_SELECT, NULL); + + gpio_request_one(61, GPIOF_OUT_INIT_HIGH, + NULL); /* LCDDON */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0154-sh-pfc-r8a7740-Remove-SCIF-function-GPIOS.patch b/patches.renesas/0154-sh-pfc-r8a7740-Remove-SCIF-function-GPIOS.patch new file mode 100644 index 00000000000..51fe43ef2fb --- /dev/null +++ b/patches.renesas/0154-sh-pfc-r8a7740-Remove-SCIF-function-GPIOS.patch @@ -0,0 +1,102 @@ +From 35880e048ebc2b700afaf87044536d9d234da417 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 18 Apr 2013 01:05:50 +0200 +Subject: sh-pfc: r8a7740: Remove SCIF function GPIOS + +All r8a7740 platforms now use the pinctrl API to control the SCIF pins, +the corresponding function GPIOS are unused. Remove them. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit aae36d71a38874beb97be7a742b4e8d65cc50983) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 72 ------------------------------------ + 1 file changed, 72 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +index 9afc7b0e..3b53193a 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +@@ -3261,78 +3261,6 @@ static const struct pinmux_func pinmux_func_gpios[] = { + GPIO_FN(FMSOIBT), GPIO_FN(FMSOOLR), GPIO_FN(FMSOOBT), + GPIO_FN(FMSOSLD), GPIO_FN(FMSOCK), + +- /* SCIFA0 */ +- GPIO_FN(SCIFA0_SCK), GPIO_FN(SCIFA0_CTS), GPIO_FN(SCIFA0_RTS), +- GPIO_FN(SCIFA0_RXD), GPIO_FN(SCIFA0_TXD), +- +- /* SCIFA1 */ +- GPIO_FN(SCIFA1_CTS), GPIO_FN(SCIFA1_SCK), +- GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_TXD), GPIO_FN(SCIFA1_RTS), +- +- /* SCIFA2 */ +- GPIO_FN(SCIFA2_SCK_PORT22), /* SCIFA2_SCK Port 22/199 */ +- GPIO_FN(SCIFA2_SCK_PORT199), +- GPIO_FN(SCIFA2_RXD), GPIO_FN(SCIFA2_TXD), +- GPIO_FN(SCIFA2_CTS), GPIO_FN(SCIFA2_RTS), +- +- /* SCIFA3 */ +- GPIO_FN(SCIFA3_RTS_PORT105), /* MSEL5CR_8_0 */ +- GPIO_FN(SCIFA3_SCK_PORT116), +- GPIO_FN(SCIFA3_CTS_PORT117), +- GPIO_FN(SCIFA3_RXD_PORT174), +- GPIO_FN(SCIFA3_TXD_PORT175), +- +- GPIO_FN(SCIFA3_RTS_PORT161), /* MSEL5CR_8_1 */ +- GPIO_FN(SCIFA3_SCK_PORT158), +- GPIO_FN(SCIFA3_CTS_PORT162), +- GPIO_FN(SCIFA3_RXD_PORT159), +- GPIO_FN(SCIFA3_TXD_PORT160), +- +- /* SCIFA4 */ +- GPIO_FN(SCIFA4_RXD_PORT12), /* MSEL5CR[12:11] = 00 */ +- GPIO_FN(SCIFA4_TXD_PORT13), +- +- GPIO_FN(SCIFA4_RXD_PORT204), /* MSEL5CR[12:11] = 01 */ +- GPIO_FN(SCIFA4_TXD_PORT203), +- +- GPIO_FN(SCIFA4_RXD_PORT94), /* MSEL5CR[12:11] = 10 */ +- GPIO_FN(SCIFA4_TXD_PORT93), +- +- GPIO_FN(SCIFA4_SCK_PORT21), /* SCIFA4_SCK Port 21/205 */ +- GPIO_FN(SCIFA4_SCK_PORT205), +- +- /* SCIFA5 */ +- GPIO_FN(SCIFA5_TXD_PORT20), /* MSEL5CR[15:14] = 00 */ +- GPIO_FN(SCIFA5_RXD_PORT10), +- +- GPIO_FN(SCIFA5_RXD_PORT207), /* MSEL5CR[15:14] = 01 */ +- GPIO_FN(SCIFA5_TXD_PORT208), +- +- GPIO_FN(SCIFA5_TXD_PORT91), /* MSEL5CR[15:14] = 10 */ +- GPIO_FN(SCIFA5_RXD_PORT92), +- +- GPIO_FN(SCIFA5_SCK_PORT23), /* SCIFA5_SCK Port 23/206 */ +- GPIO_FN(SCIFA5_SCK_PORT206), +- +- /* SCIFA6 */ +- GPIO_FN(SCIFA6_SCK), GPIO_FN(SCIFA6_RXD), GPIO_FN(SCIFA6_TXD), +- +- /* SCIFA7 */ +- GPIO_FN(SCIFA7_TXD), GPIO_FN(SCIFA7_RXD), +- +- /* SCIFAB */ +- GPIO_FN(SCIFB_SCK_PORT190), /* MSEL5CR_17_0 */ +- GPIO_FN(SCIFB_RXD_PORT191), +- GPIO_FN(SCIFB_TXD_PORT192), +- GPIO_FN(SCIFB_RTS_PORT186), +- GPIO_FN(SCIFB_CTS_PORT187), +- +- GPIO_FN(SCIFB_SCK_PORT2), /* MSEL5CR_17_1 */ +- GPIO_FN(SCIFB_RXD_PORT3), +- GPIO_FN(SCIFB_TXD_PORT4), +- GPIO_FN(SCIFB_RTS_PORT172), +- GPIO_FN(SCIFB_CTS_PORT173), +- + /* RSPI */ + GPIO_FN(RSPI_SSL0_A), GPIO_FN(RSPI_SSL1_A), GPIO_FN(RSPI_SSL2_A), + GPIO_FN(RSPI_SSL3_A), GPIO_FN(RSPI_CK_A), GPIO_FN(RSPI_MOSI_A), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0155-sh-pfc-r8a7740-Remove-INTC-function-GPIOS.patch b/patches.renesas/0155-sh-pfc-r8a7740-Remove-INTC-function-GPIOS.patch new file mode 100644 index 00000000000..1b73b53fc7e --- /dev/null +++ b/patches.renesas/0155-sh-pfc-r8a7740-Remove-INTC-function-GPIOS.patch @@ -0,0 +1,64 @@ +From f08cadd8df21c3f1e92c1e0fa88bc0a4ed283c70 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 18 Apr 2013 01:05:50 +0200 +Subject: sh-pfc: r8a7740: Remove INTC function GPIOS + +All r8a7740 platforms now use the pinctrl API to control the INTC pins, +the corresponding function GPIOS are unused. Remove them. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 78c3e9b2a14af83aac563a50eaa1eaaeeb970815) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 34 ---------------------------------- + 1 file changed, 34 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +index 3b53193a..0429c7d4 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +@@ -3200,40 +3200,6 @@ static const struct sh_pfc_function pinmux_functions[] = { + #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) + + static const struct pinmux_func pinmux_func_gpios[] = { +- /* IRQ */ +- GPIO_FN(IRQ0_PORT2), GPIO_FN(IRQ0_PORT13), +- GPIO_FN(IRQ1), +- GPIO_FN(IRQ2_PORT11), GPIO_FN(IRQ2_PORT12), +- GPIO_FN(IRQ3_PORT10), GPIO_FN(IRQ3_PORT14), +- GPIO_FN(IRQ4_PORT15), GPIO_FN(IRQ4_PORT172), +- GPIO_FN(IRQ5_PORT0), GPIO_FN(IRQ5_PORT1), +- GPIO_FN(IRQ6_PORT121), GPIO_FN(IRQ6_PORT173), +- GPIO_FN(IRQ7_PORT120), GPIO_FN(IRQ7_PORT209), +- GPIO_FN(IRQ8), +- GPIO_FN(IRQ9_PORT118), GPIO_FN(IRQ9_PORT210), +- GPIO_FN(IRQ10), +- GPIO_FN(IRQ11), +- GPIO_FN(IRQ12_PORT42), GPIO_FN(IRQ12_PORT97), +- GPIO_FN(IRQ13_PORT64), GPIO_FN(IRQ13_PORT98), +- GPIO_FN(IRQ14_PORT63), GPIO_FN(IRQ14_PORT99), +- GPIO_FN(IRQ15_PORT62), GPIO_FN(IRQ15_PORT100), +- GPIO_FN(IRQ16_PORT68), GPIO_FN(IRQ16_PORT211), +- GPIO_FN(IRQ17), +- GPIO_FN(IRQ18), +- GPIO_FN(IRQ19), +- GPIO_FN(IRQ20), +- GPIO_FN(IRQ21), +- GPIO_FN(IRQ22), +- GPIO_FN(IRQ23), +- GPIO_FN(IRQ24), +- GPIO_FN(IRQ25), +- GPIO_FN(IRQ26_PORT58), GPIO_FN(IRQ26_PORT81), +- GPIO_FN(IRQ27_PORT57), GPIO_FN(IRQ27_PORT168), +- GPIO_FN(IRQ28_PORT56), GPIO_FN(IRQ28_PORT169), +- GPIO_FN(IRQ29_PORT50), GPIO_FN(IRQ29_PORT170), +- GPIO_FN(IRQ30_PORT49), GPIO_FN(IRQ30_PORT171), +- GPIO_FN(IRQ31_PORT41), GPIO_FN(IRQ31_PORT167), +- + /* Function */ + + /* DBGT */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0156-sh-pfc-r8a7740-Remove-BSC-function-GPIOS.patch b/patches.renesas/0156-sh-pfc-r8a7740-Remove-BSC-function-GPIOS.patch new file mode 100644 index 00000000000..b2968bea79c --- /dev/null +++ b/patches.renesas/0156-sh-pfc-r8a7740-Remove-BSC-function-GPIOS.patch @@ -0,0 +1,63 @@ +From f0a805012bf1f18a8622eae992f6225bbd44f92e Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 18 Apr 2013 01:05:50 +0200 +Subject: sh-pfc: r8a7740: Remove BSC function GPIOS + +All r8a7740 platforms now use the pinctrl API to control the BSC pins, +the corresponding function GPIOS are unused. Remove them. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 0be4e53913ab52140d1e9e4498dc8c4a93b2a1c7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 26 ++------------------------ + 1 file changed, 2 insertions(+), 24 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +index 0429c7d4..c78eda8c 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +@@ -3377,11 +3377,7 @@ static const struct pinmux_func pinmux_func_gpios[] = { + GPIO_FN(BBIF2_TSCK2_PORT89), + GPIO_FN(BBIF2_TSYNC2_PORT184), + +- /* BSC / FLCTL / PCMCIA */ +- GPIO_FN(CS0), GPIO_FN(CS2), GPIO_FN(CS4), +- GPIO_FN(CS5B), GPIO_FN(CS6A), +- GPIO_FN(CS5A_PORT105), /* CS5A PORT 19/105 */ +- GPIO_FN(CS5A_PORT19), ++ /* FLCTL / PCMCIA */ + GPIO_FN(IOIS16), /* ? */ + + GPIO_FN(A0), GPIO_FN(A1), GPIO_FN(A2), GPIO_FN(A3), +@@ -3393,25 +3389,7 @@ static const struct pinmux_func pinmux_func_gpios[] = { + GPIO_FN(A22), GPIO_FN(A23), GPIO_FN(A24), GPIO_FN(A25), + GPIO_FN(A26), + +- GPIO_FN(D0_NAF0), GPIO_FN(D1_NAF1), /* share with FLCTL */ +- GPIO_FN(D2_NAF2), GPIO_FN(D3_NAF3), /* share with FLCTL */ +- GPIO_FN(D4_NAF4), GPIO_FN(D5_NAF5), /* share with FLCTL */ +- GPIO_FN(D6_NAF6), GPIO_FN(D7_NAF7), /* share with FLCTL */ +- GPIO_FN(D8_NAF8), GPIO_FN(D9_NAF9), /* share with FLCTL */ +- GPIO_FN(D10_NAF10), GPIO_FN(D11_NAF11), /* share with FLCTL */ +- GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13), /* share with FLCTL */ +- GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15), /* share with FLCTL */ +- GPIO_FN(D16), GPIO_FN(D17), GPIO_FN(D18), GPIO_FN(D19), +- GPIO_FN(D20), GPIO_FN(D21), GPIO_FN(D22), GPIO_FN(D23), +- GPIO_FN(D24), GPIO_FN(D25), GPIO_FN(D26), GPIO_FN(D27), +- GPIO_FN(D28), GPIO_FN(D29), GPIO_FN(D30), GPIO_FN(D31), +- +- GPIO_FN(WE0_FWE), /* share with FLCTL */ +- GPIO_FN(WE1), +- GPIO_FN(WE2_ICIORD), /* share with PCMCIA */ +- GPIO_FN(WE3_ICIOWR), /* share with PCMCIA */ +- GPIO_FN(CKO), GPIO_FN(BS), GPIO_FN(RDWR), +- GPIO_FN(RD_FSC), /* share with FLCTL */ ++ GPIO_FN(CKO), + GPIO_FN(WAIT_PORT177), /* WAIT Port 90/177 */ + GPIO_FN(WAIT_PORT90), + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0157-sh-pfc-r8a7740-Remove-GETHER-function-GPIOS.patch b/patches.renesas/0157-sh-pfc-r8a7740-Remove-GETHER-function-GPIOS.patch new file mode 100644 index 00000000000..7505efb8ed3 --- /dev/null +++ b/patches.renesas/0157-sh-pfc-r8a7740-Remove-GETHER-function-GPIOS.patch @@ -0,0 +1,50 @@ +From a963fa5a5abf98a0a0bf1da54a3030386444e77a Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 18 Apr 2013 01:05:50 +0200 +Subject: sh-pfc: r8a7740: Remove GETHER function GPIOS + +All r8a7740 platforms now use the pinctrl API to control the GETHER +pins, the corresponding function GPIOS are unused. Remove them. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 3456e2543e9af564d205e03feb010246dc214857) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 20 -------------------- + 1 file changed, 20 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +index c78eda8c..58fbe6b1 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +@@ -3410,26 +3410,6 @@ static const struct pinmux_func pinmux_func_gpios[] = { + GPIO_FN(IDE_INT), GPIO_FN(IDE_RST), GPIO_FN(IDE_DIRECTION), + GPIO_FN(IDE_EXBUF_ENB), GPIO_FN(IDE_IODACK), GPIO_FN(IDE_IODREQ), + +- /* RMII */ +- GPIO_FN(RMII_CRS_DV), GPIO_FN(RMII_RX_ER), GPIO_FN(RMII_RXD0), +- GPIO_FN(RMII_RXD1), GPIO_FN(RMII_TX_EN), GPIO_FN(RMII_TXD0), +- GPIO_FN(RMII_MDC), GPIO_FN(RMII_TXD1), GPIO_FN(RMII_MDIO), +- GPIO_FN(RMII_REF50CK), GPIO_FN(RMII_REF125CK), /* for GMII */ +- +- /* GEther */ +- GPIO_FN(ET_TX_CLK), GPIO_FN(ET_TX_EN), GPIO_FN(ET_ETXD0), +- GPIO_FN(ET_ETXD1), GPIO_FN(ET_ETXD2), GPIO_FN(ET_ETXD3), +- GPIO_FN(ET_ETXD4), GPIO_FN(ET_ETXD5), /* for GEther */ +- GPIO_FN(ET_ETXD6), GPIO_FN(ET_ETXD7), /* for GEther */ +- GPIO_FN(ET_COL), GPIO_FN(ET_TX_ER), GPIO_FN(ET_RX_CLK), +- GPIO_FN(ET_RX_DV), GPIO_FN(ET_ERXD0), GPIO_FN(ET_ERXD1), +- GPIO_FN(ET_ERXD2), GPIO_FN(ET_ERXD3), +- GPIO_FN(ET_ERXD4), GPIO_FN(ET_ERXD5), /* for GEther */ +- GPIO_FN(ET_ERXD6), GPIO_FN(ET_ERXD7), /* for GEther */ +- GPIO_FN(ET_RX_ER), GPIO_FN(ET_CRS), GPIO_FN(ET_MDC), +- GPIO_FN(ET_MDIO), GPIO_FN(ET_LINK), GPIO_FN(ET_PHY_INT), +- GPIO_FN(ET_WOL), GPIO_FN(ET_GTX_CLK), +- + /* DMA0 */ + GPIO_FN(DREQ0), GPIO_FN(DACK0), + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0158-sh-pfc-r8a7740-Remove-CEU-function-GPIOS.patch b/patches.renesas/0158-sh-pfc-r8a7740-Remove-CEU-function-GPIOS.patch new file mode 100644 index 00000000000..55aabd20cf3 --- /dev/null +++ b/patches.renesas/0158-sh-pfc-r8a7740-Remove-CEU-function-GPIOS.patch @@ -0,0 +1,58 @@ +From 97437529269656a83b9a9dc421d23752ba492f5e Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 18 Apr 2013 01:05:50 +0200 +Subject: sh-pfc: r8a7740: Remove CEU function GPIOS + +All r8a7740 platforms now use the pinctrl API to control the CEU pins, +the corresponding function GPIOS are unused. Remove them. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 75c57d2c908c4b1c57139db2f817483dc7052a5e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 28 ---------------------------- + 1 file changed, 28 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +index 58fbe6b1..7ab4ff2b 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +@@ -3232,34 +3232,6 @@ static const struct pinmux_func pinmux_func_gpios[] = { + GPIO_FN(RSPI_SSL3_A), GPIO_FN(RSPI_CK_A), GPIO_FN(RSPI_MOSI_A), + GPIO_FN(RSPI_MISO_A), + +- /* VIO CKO */ +- GPIO_FN(VIO_CKO1), +- GPIO_FN(VIO_CKO2), +- GPIO_FN(VIO_CKO_1), +- GPIO_FN(VIO_CKO), +- +- /* VIO0 */ +- GPIO_FN(VIO0_D0), GPIO_FN(VIO0_D1), GPIO_FN(VIO0_D2), +- GPIO_FN(VIO0_D3), GPIO_FN(VIO0_D4), GPIO_FN(VIO0_D5), +- GPIO_FN(VIO0_D6), GPIO_FN(VIO0_D7), GPIO_FN(VIO0_D8), +- GPIO_FN(VIO0_D9), GPIO_FN(VIO0_D10), GPIO_FN(VIO0_D11), +- GPIO_FN(VIO0_D12), GPIO_FN(VIO0_VD), GPIO_FN(VIO0_HD), +- GPIO_FN(VIO0_CLK), GPIO_FN(VIO0_FIELD), +- +- GPIO_FN(VIO0_D13_PORT26), /* MSEL5CR_27_0 */ +- GPIO_FN(VIO0_D14_PORT25), +- GPIO_FN(VIO0_D15_PORT24), +- +- GPIO_FN(VIO0_D13_PORT22), /* MSEL5CR_27_1 */ +- GPIO_FN(VIO0_D14_PORT95), +- GPIO_FN(VIO0_D15_PORT96), +- +- /* VIO1 */ +- GPIO_FN(VIO1_D0), GPIO_FN(VIO1_D1), GPIO_FN(VIO1_D2), +- GPIO_FN(VIO1_D3), GPIO_FN(VIO1_D4), GPIO_FN(VIO1_D5), +- GPIO_FN(VIO1_D6), GPIO_FN(VIO1_D7), GPIO_FN(VIO1_VD), +- GPIO_FN(VIO1_HD), GPIO_FN(VIO1_CLK), GPIO_FN(VIO1_FIELD), +- + /* TPU0 */ + GPIO_FN(TPU0TO0), GPIO_FN(TPU0TO1), GPIO_FN(TPU0TO3), + GPIO_FN(TPU0TO2_PORT66), /* TPU0TO2 Port 66/202 */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0159-sh-pfc-r8a7740-Remove-FSI-function-GPIOS.patch b/patches.renesas/0159-sh-pfc-r8a7740-Remove-FSI-function-GPIOS.patch new file mode 100644 index 00000000000..81e9cfacd6d --- /dev/null +++ b/patches.renesas/0159-sh-pfc-r8a7740-Remove-FSI-function-GPIOS.patch @@ -0,0 +1,42 @@ +From 76af5d40895e75873e1ff5e8047c431c5484af0a Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 18 Apr 2013 01:05:50 +0200 +Subject: sh-pfc: r8a7740: Remove FSI function GPIOS + +All r8a7740 platforms now use the pinctrl API to control the FSI pins, +the corresponding function GPIOS are unused. Remove them. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 592e0c30291f86b5f0455c9e524ba01c140ed5f2) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 12 ------------ + 1 file changed, 12 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +index 7ab4ff2b..a93fd84c 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +@@ -3207,18 +3207,6 @@ static const struct pinmux_func pinmux_func_gpios[] = { + GPIO_FN(DBGMD10), GPIO_FN(DBGMD11), GPIO_FN(DBGMD20), + GPIO_FN(DBGMD21), + +- /* FSI-A */ +- GPIO_FN(FSIAISLD_PORT0), /* FSIAISLD Port 0/5 */ +- GPIO_FN(FSIAISLD_PORT5), +- GPIO_FN(FSIASPDIF_PORT9), /* FSIASPDIF Port 9/18 */ +- GPIO_FN(FSIASPDIF_PORT18), +- GPIO_FN(FSIAOSLD1), GPIO_FN(FSIAOSLD2), GPIO_FN(FSIAOLR), +- GPIO_FN(FSIAOBT), GPIO_FN(FSIAOSLD), GPIO_FN(FSIAOMC), +- GPIO_FN(FSIACK), GPIO_FN(FSIAILR), GPIO_FN(FSIAIBT), +- +- /* FSI-B */ +- GPIO_FN(FSIBCK), +- + /* FMSI */ + GPIO_FN(FMSISLD_PORT1), /* FMSISLD Port 1/6 */ + GPIO_FN(FMSISLD_PORT6), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0160-sh-pfc-r8a7740-Remove-HDMI-function-GPIOS.patch b/patches.renesas/0160-sh-pfc-r8a7740-Remove-HDMI-function-GPIOS.patch new file mode 100644 index 00000000000..f10e1f84bce --- /dev/null +++ b/patches.renesas/0160-sh-pfc-r8a7740-Remove-HDMI-function-GPIOS.patch @@ -0,0 +1,34 @@ +From cfbe496e5973b300df5b6f7f155555d006ab2ff9 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 18 Apr 2013 01:05:50 +0200 +Subject: sh-pfc: r8a7740: Remove HDMI function GPIOS + +All r8a7740 platforms now use the pinctrl API to control the HDMI pins, +the corresponding function GPIOS are unused. Remove them. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 0f7f51d82c31fdd4eba4b2fef0502248ea812ba7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 4 ---- + 1 file changed, 4 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +index a93fd84c..fb7a3e8e 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +@@ -3386,10 +3386,6 @@ static const struct pinmux_func pinmux_func_gpios[] = { + GPIO_FN(SDENC_CPG), + GPIO_FN(SDENC_DV_CLKI), + +- /* HDMI */ +- GPIO_FN(HDMI_HPD), +- GPIO_FN(HDMI_CEC), +- + /* SYSC */ + GPIO_FN(RESETP_PULLUP), + GPIO_FN(RESETP_PLAIN), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0161-cpufreq-rename-index-as-driver_data-in-cpufreq_frequ.patch b/patches.renesas/0161-cpufreq-rename-index-as-driver_data-in-cpufreq_frequ.patch new file mode 100644 index 00000000000..21da402628e --- /dev/null +++ b/patches.renesas/0161-cpufreq-rename-index-as-driver_data-in-cpufreq_frequ.patch @@ -0,0 +1,1259 @@ +From 917e749c4ccc58160a88667a4b32c6040ccc4f00 Mon Sep 17 00:00:00 2001 +From: Viresh Kumar <viresh.kumar@linaro.org> +Date: Sat, 30 Mar 2013 16:25:15 +0530 +Subject: cpufreq: rename index as driver_data in cpufreq_frequency_table + +The "index" field of struct cpufreq_frequency_table was never an +index and isn't used at all by the cpufreq core. It only is useful +for cpufreq drivers for their internal purposes. + +Many people nowadays blindly set it in ascending order with the +assumption that the core will use it, which is a mistake. + +Rename it to "driver_data" as that's what its purpose is. All of its +users are updated accordingly. + +[rjw: Changelog] +Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> +Acked-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> + +(cherry picked from commit 5070158804b5339c71809f5e673cea1cfacd804d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + Documentation/cpu-freq/cpu-drivers.txt | 10 +- + arch/arm/mach-davinci/da850.c | 8 +- + arch/arm/mach-s3c24xx/cpufreq-utils.c | 2 +- + arch/arm/mach-s3c24xx/cpufreq.c | 4 +- + arch/arm/mach-s3c24xx/pll-s3c2410.c | 54 +++++----- + arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c | 54 +++++----- + arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c | 110 ++++++++++----------- + arch/arm/mach-shmobile/clock-sh7372.c | 6 +- + arch/arm/plat-samsung/include/plat/cpu-freq-core.h | 2 +- + arch/mips/loongson/lemote-2f/clock.c | 3 +- + arch/powerpc/platforms/pasemi/cpufreq.c | 5 +- + drivers/base/power/opp.c | 4 +- + drivers/cpufreq/acpi-cpufreq.c | 6 +- + drivers/cpufreq/blackfin-cpufreq.c | 10 +- + drivers/cpufreq/e_powersaver.c | 8 +- + drivers/cpufreq/freq_table.c | 26 ++--- + drivers/cpufreq/ia64-acpi-cpufreq.c | 2 +- + drivers/cpufreq/kirkwood-cpufreq.c | 2 +- + drivers/cpufreq/longhaul.c | 16 +-- + drivers/cpufreq/loongson2_cpufreq.c | 2 +- + drivers/cpufreq/p4-clockmod.c | 4 +- + drivers/cpufreq/powernow-k6.c | 8 +- + drivers/cpufreq/powernow-k7.c | 16 +-- + drivers/cpufreq/powernow-k8.c | 18 ++-- + drivers/cpufreq/ppc_cbe_cpufreq.c | 4 +- + drivers/cpufreq/pxa2xx-cpufreq.c | 8 +- + drivers/cpufreq/pxa3xx-cpufreq.c | 4 +- + drivers/cpufreq/s3c2416-cpufreq.c | 2 +- + drivers/cpufreq/s3c64xx-cpufreq.c | 2 +- + drivers/cpufreq/sc520_freq.c | 2 +- + drivers/cpufreq/sparc-us2e-cpufreq.c | 12 +-- + drivers/cpufreq/sparc-us3-cpufreq.c | 8 +- + drivers/cpufreq/spear-cpufreq.c | 4 +- + drivers/cpufreq/speedstep-centrino.c | 8 +- + drivers/mfd/db8500-prcmu.c | 10 +- + drivers/sh/clk/core.c | 4 +- + include/linux/cpufreq.h | 2 +- + 37 files changed, 223 insertions(+), 227 deletions(-) + +diff --git a/Documentation/cpu-freq/cpu-drivers.txt b/Documentation/cpu-freq/cpu-drivers.txt +index a3585eac..19fa98e0 100644 +--- a/Documentation/cpu-freq/cpu-drivers.txt ++++ b/Documentation/cpu-freq/cpu-drivers.txt +@@ -186,7 +186,7 @@ As most cpufreq processors only allow for being set to a few specific + frequencies, a "frequency table" with some functions might assist in + some work of the processor driver. Such a "frequency table" consists + of an array of struct cpufreq_frequency_table entries, with any value in +-"index" you want to use, and the corresponding frequency in ++"driver_data" you want to use, and the corresponding frequency in + "frequency". At the end of the table, you need to add a + cpufreq_frequency_table entry with frequency set to CPUFREQ_TABLE_END. And + if you want to skip one entry in the table, set the frequency to +@@ -214,10 +214,4 @@ int cpufreq_frequency_table_target(struct cpufreq_policy *policy, + is the corresponding frequency table helper for the ->target + stage. Just pass the values to this function, and the unsigned int + index returns the number of the frequency table entry which contains +-the frequency the CPU shall be set to. PLEASE NOTE: This is not the +-"index" which is in this cpufreq_table_entry.index, but instead +-cpufreq_table[index]. So, the new frequency is +-cpufreq_table[index].frequency, and the value you stored into the +-frequency table "index" field is +-cpufreq_table[index].index. +- ++the frequency the CPU shall be set to. +diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c +index 4d693384..a0d4f603 100644 +--- a/arch/arm/mach-davinci/da850.c ++++ b/arch/arm/mach-davinci/da850.c +@@ -1004,7 +1004,7 @@ static const struct da850_opp da850_opp_96 = { + + #define OPP(freq) \ + { \ +- .index = (unsigned int) &da850_opp_##freq, \ ++ .driver_data = (unsigned int) &da850_opp_##freq, \ + .frequency = freq * 1000, \ + } + +@@ -1016,7 +1016,7 @@ static struct cpufreq_frequency_table da850_freq_table[] = { + OPP(200), + OPP(96), + { +- .index = 0, ++ .driver_data = 0, + .frequency = CPUFREQ_TABLE_END, + }, + }; +@@ -1044,7 +1044,7 @@ static int da850_set_voltage(unsigned int index) + if (!cvdd) + return -ENODEV; + +- opp = (struct da850_opp *) cpufreq_info.freq_table[index].index; ++ opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data; + + return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max); + } +@@ -1125,7 +1125,7 @@ static int da850_set_pll0rate(struct clk *clk, unsigned long index) + struct pll_data *pll = clk->pll_data; + int ret; + +- opp = (struct da850_opp *) cpufreq_info.freq_table[index].index; ++ opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data; + prediv = opp->prediv; + mult = opp->mult; + postdiv = opp->postdiv; +diff --git a/arch/arm/mach-s3c24xx/cpufreq-utils.c b/arch/arm/mach-s3c24xx/cpufreq-utils.c +index ddd8280e..2a0aa568 100644 +--- a/arch/arm/mach-s3c24xx/cpufreq-utils.c ++++ b/arch/arm/mach-s3c24xx/cpufreq-utils.c +@@ -60,5 +60,5 @@ void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg) + */ + void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg) + { +- __raw_writel(cfg->pll.index, S3C2410_MPLLCON); ++ __raw_writel(cfg->pll.driver_data, S3C2410_MPLLCON); + } +diff --git a/arch/arm/mach-s3c24xx/cpufreq.c b/arch/arm/mach-s3c24xx/cpufreq.c +index 3c0e78ed..3513e747 100644 +--- a/arch/arm/mach-s3c24xx/cpufreq.c ++++ b/arch/arm/mach-s3c24xx/cpufreq.c +@@ -70,7 +70,7 @@ static void s3c_cpufreq_getcur(struct s3c_cpufreq_config *cfg) + cfg->freq.pclk = pclk = clk_get_rate(clk_pclk); + cfg->freq.armclk = armclk = clk_get_rate(clk_arm); + +- cfg->pll.index = __raw_readl(S3C2410_MPLLCON); ++ cfg->pll.driver_data = __raw_readl(S3C2410_MPLLCON); + cfg->pll.frequency = fclk; + + cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10); +@@ -431,7 +431,7 @@ static unsigned int suspend_freq; + static int s3c_cpufreq_suspend(struct cpufreq_policy *policy) + { + suspend_pll.frequency = clk_get_rate(_clk_mpll); +- suspend_pll.index = __raw_readl(S3C2410_MPLLCON); ++ suspend_pll.driver_data = __raw_readl(S3C2410_MPLLCON); + suspend_freq = s3c_cpufreq_get(0) * 1000; + + return 0; +diff --git a/arch/arm/mach-s3c24xx/pll-s3c2410.c b/arch/arm/mach-s3c24xx/pll-s3c2410.c +index dcf3420a..5e37d368 100644 +--- a/arch/arm/mach-s3c24xx/pll-s3c2410.c ++++ b/arch/arm/mach-s3c24xx/pll-s3c2410.c +@@ -33,36 +33,36 @@ + #include <plat/cpu-freq-core.h> + + static struct cpufreq_frequency_table pll_vals_12MHz[] = { +- { .frequency = 34000000, .index = PLLVAL(82, 2, 3), }, +- { .frequency = 45000000, .index = PLLVAL(82, 1, 3), }, +- { .frequency = 51000000, .index = PLLVAL(161, 3, 3), }, +- { .frequency = 48000000, .index = PLLVAL(120, 2, 3), }, +- { .frequency = 56000000, .index = PLLVAL(142, 2, 3), }, +- { .frequency = 68000000, .index = PLLVAL(82, 2, 2), }, +- { .frequency = 79000000, .index = PLLVAL(71, 1, 2), }, +- { .frequency = 85000000, .index = PLLVAL(105, 2, 2), }, +- { .frequency = 90000000, .index = PLLVAL(112, 2, 2), }, +- { .frequency = 101000000, .index = PLLVAL(127, 2, 2), }, +- { .frequency = 113000000, .index = PLLVAL(105, 1, 2), }, +- { .frequency = 118000000, .index = PLLVAL(150, 2, 2), }, +- { .frequency = 124000000, .index = PLLVAL(116, 1, 2), }, +- { .frequency = 135000000, .index = PLLVAL(82, 2, 1), }, +- { .frequency = 147000000, .index = PLLVAL(90, 2, 1), }, +- { .frequency = 152000000, .index = PLLVAL(68, 1, 1), }, +- { .frequency = 158000000, .index = PLLVAL(71, 1, 1), }, +- { .frequency = 170000000, .index = PLLVAL(77, 1, 1), }, +- { .frequency = 180000000, .index = PLLVAL(82, 1, 1), }, +- { .frequency = 186000000, .index = PLLVAL(85, 1, 1), }, +- { .frequency = 192000000, .index = PLLVAL(88, 1, 1), }, +- { .frequency = 203000000, .index = PLLVAL(161, 3, 1), }, ++ { .frequency = 34000000, .driver_data = PLLVAL(82, 2, 3), }, ++ { .frequency = 45000000, .driver_data = PLLVAL(82, 1, 3), }, ++ { .frequency = 51000000, .driver_data = PLLVAL(161, 3, 3), }, ++ { .frequency = 48000000, .driver_data = PLLVAL(120, 2, 3), }, ++ { .frequency = 56000000, .driver_data = PLLVAL(142, 2, 3), }, ++ { .frequency = 68000000, .driver_data = PLLVAL(82, 2, 2), }, ++ { .frequency = 79000000, .driver_data = PLLVAL(71, 1, 2), }, ++ { .frequency = 85000000, .driver_data = PLLVAL(105, 2, 2), }, ++ { .frequency = 90000000, .driver_data = PLLVAL(112, 2, 2), }, ++ { .frequency = 101000000, .driver_data = PLLVAL(127, 2, 2), }, ++ { .frequency = 113000000, .driver_data = PLLVAL(105, 1, 2), }, ++ { .frequency = 118000000, .driver_data = PLLVAL(150, 2, 2), }, ++ { .frequency = 124000000, .driver_data = PLLVAL(116, 1, 2), }, ++ { .frequency = 135000000, .driver_data = PLLVAL(82, 2, 1), }, ++ { .frequency = 147000000, .driver_data = PLLVAL(90, 2, 1), }, ++ { .frequency = 152000000, .driver_data = PLLVAL(68, 1, 1), }, ++ { .frequency = 158000000, .driver_data = PLLVAL(71, 1, 1), }, ++ { .frequency = 170000000, .driver_data = PLLVAL(77, 1, 1), }, ++ { .frequency = 180000000, .driver_data = PLLVAL(82, 1, 1), }, ++ { .frequency = 186000000, .driver_data = PLLVAL(85, 1, 1), }, ++ { .frequency = 192000000, .driver_data = PLLVAL(88, 1, 1), }, ++ { .frequency = 203000000, .driver_data = PLLVAL(161, 3, 1), }, + + /* 2410A extras */ + +- { .frequency = 210000000, .index = PLLVAL(132, 2, 1), }, +- { .frequency = 226000000, .index = PLLVAL(105, 1, 1), }, +- { .frequency = 266000000, .index = PLLVAL(125, 1, 1), }, +- { .frequency = 268000000, .index = PLLVAL(126, 1, 1), }, +- { .frequency = 270000000, .index = PLLVAL(127, 1, 1), }, ++ { .frequency = 210000000, .driver_data = PLLVAL(132, 2, 1), }, ++ { .frequency = 226000000, .driver_data = PLLVAL(105, 1, 1), }, ++ { .frequency = 266000000, .driver_data = PLLVAL(125, 1, 1), }, ++ { .frequency = 268000000, .driver_data = PLLVAL(126, 1, 1), }, ++ { .frequency = 270000000, .driver_data = PLLVAL(127, 1, 1), }, + }; + + static int s3c2410_plls_add(struct device *dev, struct subsys_interface *sif) +diff --git a/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c b/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c +index 67378175..a19460e6 100644 +--- a/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c ++++ b/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c +@@ -21,33 +21,33 @@ + #include <plat/cpu-freq-core.h> + + static struct cpufreq_frequency_table s3c2440_plls_12[] __initdata = { +- { .frequency = 75000000, .index = PLLVAL(0x75, 3, 3), }, /* FVco 600.000000 */ +- { .frequency = 80000000, .index = PLLVAL(0x98, 4, 3), }, /* FVco 640.000000 */ +- { .frequency = 90000000, .index = PLLVAL(0x70, 2, 3), }, /* FVco 720.000000 */ +- { .frequency = 100000000, .index = PLLVAL(0x5c, 1, 3), }, /* FVco 800.000000 */ +- { .frequency = 110000000, .index = PLLVAL(0x66, 1, 3), }, /* FVco 880.000000 */ +- { .frequency = 120000000, .index = PLLVAL(0x70, 1, 3), }, /* FVco 960.000000 */ +- { .frequency = 150000000, .index = PLLVAL(0x75, 3, 2), }, /* FVco 600.000000 */ +- { .frequency = 160000000, .index = PLLVAL(0x98, 4, 2), }, /* FVco 640.000000 */ +- { .frequency = 170000000, .index = PLLVAL(0x4d, 1, 2), }, /* FVco 680.000000 */ +- { .frequency = 180000000, .index = PLLVAL(0x70, 2, 2), }, /* FVco 720.000000 */ +- { .frequency = 190000000, .index = PLLVAL(0x57, 1, 2), }, /* FVco 760.000000 */ +- { .frequency = 200000000, .index = PLLVAL(0x5c, 1, 2), }, /* FVco 800.000000 */ +- { .frequency = 210000000, .index = PLLVAL(0x84, 2, 2), }, /* FVco 840.000000 */ +- { .frequency = 220000000, .index = PLLVAL(0x66, 1, 2), }, /* FVco 880.000000 */ +- { .frequency = 230000000, .index = PLLVAL(0x6b, 1, 2), }, /* FVco 920.000000 */ +- { .frequency = 240000000, .index = PLLVAL(0x70, 1, 2), }, /* FVco 960.000000 */ +- { .frequency = 300000000, .index = PLLVAL(0x75, 3, 1), }, /* FVco 600.000000 */ +- { .frequency = 310000000, .index = PLLVAL(0x93, 4, 1), }, /* FVco 620.000000 */ +- { .frequency = 320000000, .index = PLLVAL(0x98, 4, 1), }, /* FVco 640.000000 */ +- { .frequency = 330000000, .index = PLLVAL(0x66, 2, 1), }, /* FVco 660.000000 */ +- { .frequency = 340000000, .index = PLLVAL(0x4d, 1, 1), }, /* FVco 680.000000 */ +- { .frequency = 350000000, .index = PLLVAL(0xa7, 4, 1), }, /* FVco 700.000000 */ +- { .frequency = 360000000, .index = PLLVAL(0x70, 2, 1), }, /* FVco 720.000000 */ +- { .frequency = 370000000, .index = PLLVAL(0xb1, 4, 1), }, /* FVco 740.000000 */ +- { .frequency = 380000000, .index = PLLVAL(0x57, 1, 1), }, /* FVco 760.000000 */ +- { .frequency = 390000000, .index = PLLVAL(0x7a, 2, 1), }, /* FVco 780.000000 */ +- { .frequency = 400000000, .index = PLLVAL(0x5c, 1, 1), }, /* FVco 800.000000 */ ++ { .frequency = 75000000, .driver_data = PLLVAL(0x75, 3, 3), }, /* FVco 600.000000 */ ++ { .frequency = 80000000, .driver_data = PLLVAL(0x98, 4, 3), }, /* FVco 640.000000 */ ++ { .frequency = 90000000, .driver_data = PLLVAL(0x70, 2, 3), }, /* FVco 720.000000 */ ++ { .frequency = 100000000, .driver_data = PLLVAL(0x5c, 1, 3), }, /* FVco 800.000000 */ ++ { .frequency = 110000000, .driver_data = PLLVAL(0x66, 1, 3), }, /* FVco 880.000000 */ ++ { .frequency = 120000000, .driver_data = PLLVAL(0x70, 1, 3), }, /* FVco 960.000000 */ ++ { .frequency = 150000000, .driver_data = PLLVAL(0x75, 3, 2), }, /* FVco 600.000000 */ ++ { .frequency = 160000000, .driver_data = PLLVAL(0x98, 4, 2), }, /* FVco 640.000000 */ ++ { .frequency = 170000000, .driver_data = PLLVAL(0x4d, 1, 2), }, /* FVco 680.000000 */ ++ { .frequency = 180000000, .driver_data = PLLVAL(0x70, 2, 2), }, /* FVco 720.000000 */ ++ { .frequency = 190000000, .driver_data = PLLVAL(0x57, 1, 2), }, /* FVco 760.000000 */ ++ { .frequency = 200000000, .driver_data = PLLVAL(0x5c, 1, 2), }, /* FVco 800.000000 */ ++ { .frequency = 210000000, .driver_data = PLLVAL(0x84, 2, 2), }, /* FVco 840.000000 */ ++ { .frequency = 220000000, .driver_data = PLLVAL(0x66, 1, 2), }, /* FVco 880.000000 */ ++ { .frequency = 230000000, .driver_data = PLLVAL(0x6b, 1, 2), }, /* FVco 920.000000 */ ++ { .frequency = 240000000, .driver_data = PLLVAL(0x70, 1, 2), }, /* FVco 960.000000 */ ++ { .frequency = 300000000, .driver_data = PLLVAL(0x75, 3, 1), }, /* FVco 600.000000 */ ++ { .frequency = 310000000, .driver_data = PLLVAL(0x93, 4, 1), }, /* FVco 620.000000 */ ++ { .frequency = 320000000, .driver_data = PLLVAL(0x98, 4, 1), }, /* FVco 640.000000 */ ++ { .frequency = 330000000, .driver_data = PLLVAL(0x66, 2, 1), }, /* FVco 660.000000 */ ++ { .frequency = 340000000, .driver_data = PLLVAL(0x4d, 1, 1), }, /* FVco 680.000000 */ ++ { .frequency = 350000000, .driver_data = PLLVAL(0xa7, 4, 1), }, /* FVco 700.000000 */ ++ { .frequency = 360000000, .driver_data = PLLVAL(0x70, 2, 1), }, /* FVco 720.000000 */ ++ { .frequency = 370000000, .driver_data = PLLVAL(0xb1, 4, 1), }, /* FVco 740.000000 */ ++ { .frequency = 380000000, .driver_data = PLLVAL(0x57, 1, 1), }, /* FVco 760.000000 */ ++ { .frequency = 390000000, .driver_data = PLLVAL(0x7a, 2, 1), }, /* FVco 780.000000 */ ++ { .frequency = 400000000, .driver_data = PLLVAL(0x5c, 1, 1), }, /* FVco 800.000000 */ + }; + + static int s3c2440_plls12_add(struct device *dev, struct subsys_interface *sif) +diff --git a/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c b/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c +index debfa106..1191b290 100644 +--- a/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c ++++ b/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c +@@ -21,61 +21,61 @@ + #include <plat/cpu-freq-core.h> + + static struct cpufreq_frequency_table s3c2440_plls_169344[] __initdata = { +- { .frequency = 78019200, .index = PLLVAL(121, 5, 3), }, /* FVco 624.153600 */ +- { .frequency = 84067200, .index = PLLVAL(131, 5, 3), }, /* FVco 672.537600 */ +- { .frequency = 90115200, .index = PLLVAL(141, 5, 3), }, /* FVco 720.921600 */ +- { .frequency = 96163200, .index = PLLVAL(151, 5, 3), }, /* FVco 769.305600 */ +- { .frequency = 102135600, .index = PLLVAL(185, 6, 3), }, /* FVco 817.084800 */ +- { .frequency = 108259200, .index = PLLVAL(171, 5, 3), }, /* FVco 866.073600 */ +- { .frequency = 114307200, .index = PLLVAL(127, 3, 3), }, /* FVco 914.457600 */ +- { .frequency = 120234240, .index = PLLVAL(134, 3, 3), }, /* FVco 961.873920 */ +- { .frequency = 126161280, .index = PLLVAL(141, 3, 3), }, /* FVco 1009.290240 */ +- { .frequency = 132088320, .index = PLLVAL(148, 3, 3), }, /* FVco 1056.706560 */ +- { .frequency = 138015360, .index = PLLVAL(155, 3, 3), }, /* FVco 1104.122880 */ +- { .frequency = 144789120, .index = PLLVAL(163, 3, 3), }, /* FVco 1158.312960 */ +- { .frequency = 150100363, .index = PLLVAL(187, 9, 2), }, /* FVco 600.401454 */ +- { .frequency = 156038400, .index = PLLVAL(121, 5, 2), }, /* FVco 624.153600 */ +- { .frequency = 162086400, .index = PLLVAL(126, 5, 2), }, /* FVco 648.345600 */ +- { .frequency = 168134400, .index = PLLVAL(131, 5, 2), }, /* FVco 672.537600 */ +- { .frequency = 174048000, .index = PLLVAL(177, 7, 2), }, /* FVco 696.192000 */ +- { .frequency = 180230400, .index = PLLVAL(141, 5, 2), }, /* FVco 720.921600 */ +- { .frequency = 186278400, .index = PLLVAL(124, 4, 2), }, /* FVco 745.113600 */ +- { .frequency = 192326400, .index = PLLVAL(151, 5, 2), }, /* FVco 769.305600 */ +- { .frequency = 198132480, .index = PLLVAL(109, 3, 2), }, /* FVco 792.529920 */ +- { .frequency = 204271200, .index = PLLVAL(185, 6, 2), }, /* FVco 817.084800 */ +- { .frequency = 210268800, .index = PLLVAL(141, 4, 2), }, /* FVco 841.075200 */ +- { .frequency = 216518400, .index = PLLVAL(171, 5, 2), }, /* FVco 866.073600 */ +- { .frequency = 222264000, .index = PLLVAL(97, 2, 2), }, /* FVco 889.056000 */ +- { .frequency = 228614400, .index = PLLVAL(127, 3, 2), }, /* FVco 914.457600 */ +- { .frequency = 234259200, .index = PLLVAL(158, 4, 2), }, /* FVco 937.036800 */ +- { .frequency = 240468480, .index = PLLVAL(134, 3, 2), }, /* FVco 961.873920 */ +- { .frequency = 246960000, .index = PLLVAL(167, 4, 2), }, /* FVco 987.840000 */ +- { .frequency = 252322560, .index = PLLVAL(141, 3, 2), }, /* FVco 1009.290240 */ +- { .frequency = 258249600, .index = PLLVAL(114, 2, 2), }, /* FVco 1032.998400 */ +- { .frequency = 264176640, .index = PLLVAL(148, 3, 2), }, /* FVco 1056.706560 */ +- { .frequency = 270950400, .index = PLLVAL(120, 2, 2), }, /* FVco 1083.801600 */ +- { .frequency = 276030720, .index = PLLVAL(155, 3, 2), }, /* FVco 1104.122880 */ +- { .frequency = 282240000, .index = PLLVAL(92, 1, 2), }, /* FVco 1128.960000 */ +- { .frequency = 289578240, .index = PLLVAL(163, 3, 2), }, /* FVco 1158.312960 */ +- { .frequency = 294235200, .index = PLLVAL(131, 2, 2), }, /* FVco 1176.940800 */ +- { .frequency = 300200727, .index = PLLVAL(187, 9, 1), }, /* FVco 600.401454 */ +- { .frequency = 306358690, .index = PLLVAL(191, 9, 1), }, /* FVco 612.717380 */ +- { .frequency = 312076800, .index = PLLVAL(121, 5, 1), }, /* FVco 624.153600 */ +- { .frequency = 318366720, .index = PLLVAL(86, 3, 1), }, /* FVco 636.733440 */ +- { .frequency = 324172800, .index = PLLVAL(126, 5, 1), }, /* FVco 648.345600 */ +- { .frequency = 330220800, .index = PLLVAL(109, 4, 1), }, /* FVco 660.441600 */ +- { .frequency = 336268800, .index = PLLVAL(131, 5, 1), }, /* FVco 672.537600 */ +- { .frequency = 342074880, .index = PLLVAL(93, 3, 1), }, /* FVco 684.149760 */ +- { .frequency = 348096000, .index = PLLVAL(177, 7, 1), }, /* FVco 696.192000 */ +- { .frequency = 355622400, .index = PLLVAL(118, 4, 1), }, /* FVco 711.244800 */ +- { .frequency = 360460800, .index = PLLVAL(141, 5, 1), }, /* FVco 720.921600 */ +- { .frequency = 366206400, .index = PLLVAL(165, 6, 1), }, /* FVco 732.412800 */ +- { .frequency = 372556800, .index = PLLVAL(124, 4, 1), }, /* FVco 745.113600 */ +- { .frequency = 378201600, .index = PLLVAL(126, 4, 1), }, /* FVco 756.403200 */ +- { .frequency = 384652800, .index = PLLVAL(151, 5, 1), }, /* FVco 769.305600 */ +- { .frequency = 391608000, .index = PLLVAL(177, 6, 1), }, /* FVco 783.216000 */ +- { .frequency = 396264960, .index = PLLVAL(109, 3, 1), }, /* FVco 792.529920 */ +- { .frequency = 402192000, .index = PLLVAL(87, 2, 1), }, /* FVco 804.384000 */ ++ { .frequency = 78019200, .driver_data = PLLVAL(121, 5, 3), }, /* FVco 624.153600 */ ++ { .frequency = 84067200, .driver_data = PLLVAL(131, 5, 3), }, /* FVco 672.537600 */ ++ { .frequency = 90115200, .driver_data = PLLVAL(141, 5, 3), }, /* FVco 720.921600 */ ++ { .frequency = 96163200, .driver_data = PLLVAL(151, 5, 3), }, /* FVco 769.305600 */ ++ { .frequency = 102135600, .driver_data = PLLVAL(185, 6, 3), }, /* FVco 817.084800 */ ++ { .frequency = 108259200, .driver_data = PLLVAL(171, 5, 3), }, /* FVco 866.073600 */ ++ { .frequency = 114307200, .driver_data = PLLVAL(127, 3, 3), }, /* FVco 914.457600 */ ++ { .frequency = 120234240, .driver_data = PLLVAL(134, 3, 3), }, /* FVco 961.873920 */ ++ { .frequency = 126161280, .driver_data = PLLVAL(141, 3, 3), }, /* FVco 1009.290240 */ ++ { .frequency = 132088320, .driver_data = PLLVAL(148, 3, 3), }, /* FVco 1056.706560 */ ++ { .frequency = 138015360, .driver_data = PLLVAL(155, 3, 3), }, /* FVco 1104.122880 */ ++ { .frequency = 144789120, .driver_data = PLLVAL(163, 3, 3), }, /* FVco 1158.312960 */ ++ { .frequency = 150100363, .driver_data = PLLVAL(187, 9, 2), }, /* FVco 600.401454 */ ++ { .frequency = 156038400, .driver_data = PLLVAL(121, 5, 2), }, /* FVco 624.153600 */ ++ { .frequency = 162086400, .driver_data = PLLVAL(126, 5, 2), }, /* FVco 648.345600 */ ++ { .frequency = 168134400, .driver_data = PLLVAL(131, 5, 2), }, /* FVco 672.537600 */ ++ { .frequency = 174048000, .driver_data = PLLVAL(177, 7, 2), }, /* FVco 696.192000 */ ++ { .frequency = 180230400, .driver_data = PLLVAL(141, 5, 2), }, /* FVco 720.921600 */ ++ { .frequency = 186278400, .driver_data = PLLVAL(124, 4, 2), }, /* FVco 745.113600 */ ++ { .frequency = 192326400, .driver_data = PLLVAL(151, 5, 2), }, /* FVco 769.305600 */ ++ { .frequency = 198132480, .driver_data = PLLVAL(109, 3, 2), }, /* FVco 792.529920 */ ++ { .frequency = 204271200, .driver_data = PLLVAL(185, 6, 2), }, /* FVco 817.084800 */ ++ { .frequency = 210268800, .driver_data = PLLVAL(141, 4, 2), }, /* FVco 841.075200 */ ++ { .frequency = 216518400, .driver_data = PLLVAL(171, 5, 2), }, /* FVco 866.073600 */ ++ { .frequency = 222264000, .driver_data = PLLVAL(97, 2, 2), }, /* FVco 889.056000 */ ++ { .frequency = 228614400, .driver_data = PLLVAL(127, 3, 2), }, /* FVco 914.457600 */ ++ { .frequency = 234259200, .driver_data = PLLVAL(158, 4, 2), }, /* FVco 937.036800 */ ++ { .frequency = 240468480, .driver_data = PLLVAL(134, 3, 2), }, /* FVco 961.873920 */ ++ { .frequency = 246960000, .driver_data = PLLVAL(167, 4, 2), }, /* FVco 987.840000 */ ++ { .frequency = 252322560, .driver_data = PLLVAL(141, 3, 2), }, /* FVco 1009.290240 */ ++ { .frequency = 258249600, .driver_data = PLLVAL(114, 2, 2), }, /* FVco 1032.998400 */ ++ { .frequency = 264176640, .driver_data = PLLVAL(148, 3, 2), }, /* FVco 1056.706560 */ ++ { .frequency = 270950400, .driver_data = PLLVAL(120, 2, 2), }, /* FVco 1083.801600 */ ++ { .frequency = 276030720, .driver_data = PLLVAL(155, 3, 2), }, /* FVco 1104.122880 */ ++ { .frequency = 282240000, .driver_data = PLLVAL(92, 1, 2), }, /* FVco 1128.960000 */ ++ { .frequency = 289578240, .driver_data = PLLVAL(163, 3, 2), }, /* FVco 1158.312960 */ ++ { .frequency = 294235200, .driver_data = PLLVAL(131, 2, 2), }, /* FVco 1176.940800 */ ++ { .frequency = 300200727, .driver_data = PLLVAL(187, 9, 1), }, /* FVco 600.401454 */ ++ { .frequency = 306358690, .driver_data = PLLVAL(191, 9, 1), }, /* FVco 612.717380 */ ++ { .frequency = 312076800, .driver_data = PLLVAL(121, 5, 1), }, /* FVco 624.153600 */ ++ { .frequency = 318366720, .driver_data = PLLVAL(86, 3, 1), }, /* FVco 636.733440 */ ++ { .frequency = 324172800, .driver_data = PLLVAL(126, 5, 1), }, /* FVco 648.345600 */ ++ { .frequency = 330220800, .driver_data = PLLVAL(109, 4, 1), }, /* FVco 660.441600 */ ++ { .frequency = 336268800, .driver_data = PLLVAL(131, 5, 1), }, /* FVco 672.537600 */ ++ { .frequency = 342074880, .driver_data = PLLVAL(93, 3, 1), }, /* FVco 684.149760 */ ++ { .frequency = 348096000, .driver_data = PLLVAL(177, 7, 1), }, /* FVco 696.192000 */ ++ { .frequency = 355622400, .driver_data = PLLVAL(118, 4, 1), }, /* FVco 711.244800 */ ++ { .frequency = 360460800, .driver_data = PLLVAL(141, 5, 1), }, /* FVco 720.921600 */ ++ { .frequency = 366206400, .driver_data = PLLVAL(165, 6, 1), }, /* FVco 732.412800 */ ++ { .frequency = 372556800, .driver_data = PLLVAL(124, 4, 1), }, /* FVco 745.113600 */ ++ { .frequency = 378201600, .driver_data = PLLVAL(126, 4, 1), }, /* FVco 756.403200 */ ++ { .frequency = 384652800, .driver_data = PLLVAL(151, 5, 1), }, /* FVco 769.305600 */ ++ { .frequency = 391608000, .driver_data = PLLVAL(177, 6, 1), }, /* FVco 783.216000 */ ++ { .frequency = 396264960, .driver_data = PLLVAL(109, 3, 1), }, /* FVco 792.529920 */ ++ { .frequency = 402192000, .driver_data = PLLVAL(87, 2, 1), }, /* FVco 804.384000 */ + }; + + static int s3c2440_plls169344_add(struct device *dev, +diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c +index 7e105932..5390c6bb 100644 +--- a/arch/arm/mach-shmobile/clock-sh7372.c ++++ b/arch/arm/mach-shmobile/clock-sh7372.c +@@ -142,15 +142,15 @@ static void pllc2_table_rebuild(struct clk *clk) + /* Initialise PLLC2 frequency table */ + for (i = 0; i < ARRAY_SIZE(pllc2_freq_table) - 2; i++) { + pllc2_freq_table[i].frequency = clk->parent->rate * (i + 20) * 2; +- pllc2_freq_table[i].index = i; ++ pllc2_freq_table[i].driver_data = i; + } + + /* This is a special entry - switching PLL off makes it a repeater */ + pllc2_freq_table[i].frequency = clk->parent->rate; +- pllc2_freq_table[i].index = i; ++ pllc2_freq_table[i].driver_data = i; + + pllc2_freq_table[++i].frequency = CPUFREQ_TABLE_END; +- pllc2_freq_table[i].index = i; ++ pllc2_freq_table[i].driver_data = i; + } + + static unsigned long pllc2_recalc(struct clk *clk) +diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h +index 95509d8e..a8a760dd 100644 +--- a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h ++++ b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h +@@ -285,7 +285,7 @@ static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table, + s3c_freq_dbg("%s: { %d = %u kHz }\n", + __func__, index, freq); + +- table[index].index = index; ++ table[index].driver_data = index; + table[index].frequency = freq; + } + +diff --git a/arch/mips/loongson/lemote-2f/clock.c b/arch/mips/loongson/lemote-2f/clock.c +index bc739d4b..4dc2f5fa 100644 +--- a/arch/mips/loongson/lemote-2f/clock.c ++++ b/arch/mips/loongson/lemote-2f/clock.c +@@ -121,7 +121,8 @@ int clk_set_rate(struct clk *clk, unsigned long rate) + clk->rate = rate; + + regval = LOONGSON_CHIPCFG0; +- regval = (regval & ~0x7) | (loongson2_clockmod_table[i].index - 1); ++ regval = (regval & ~0x7) | ++ (loongson2_clockmod_table[i].driver_data - 1); + LOONGSON_CHIPCFG0 = regval; + + return ret; +diff --git a/arch/powerpc/platforms/pasemi/cpufreq.c b/arch/powerpc/platforms/pasemi/cpufreq.c +index be1e7958..b704da40 100644 +--- a/arch/powerpc/platforms/pasemi/cpufreq.c ++++ b/arch/powerpc/platforms/pasemi/cpufreq.c +@@ -204,7 +204,8 @@ static int pas_cpufreq_cpu_init(struct cpufreq_policy *policy) + + /* initialize frequency table */ + for (i=0; pas_freqs[i].frequency!=CPUFREQ_TABLE_END; i++) { +- pas_freqs[i].frequency = get_astate_freq(pas_freqs[i].index) * 100000; ++ pas_freqs[i].frequency = ++ get_astate_freq(pas_freqs[i].driver_data) * 100000; + pr_debug("%d: %d\n", i, pas_freqs[i].frequency); + } + +@@ -280,7 +281,7 @@ static int pas_cpufreq_target(struct cpufreq_policy *policy, + pr_debug("setting frequency for cpu %d to %d kHz, 1/%d of max frequency\n", + policy->cpu, + pas_freqs[pas_astate_new].frequency, +- pas_freqs[pas_astate_new].index); ++ pas_freqs[pas_astate_new].driver_data); + + current_astate = pas_astate_new; + +diff --git a/drivers/base/power/opp.c b/drivers/base/power/opp.c +index f0077cb8..c8ec1863 100644 +--- a/drivers/base/power/opp.c ++++ b/drivers/base/power/opp.c +@@ -648,14 +648,14 @@ int opp_init_cpufreq_table(struct device *dev, + + list_for_each_entry(opp, &dev_opp->opp_list, node) { + if (opp->available) { +- freq_table[i].index = i; ++ freq_table[i].driver_data = i; + freq_table[i].frequency = opp->rate / 1000; + i++; + } + } + mutex_unlock(&dev_opp_list_lock); + +- freq_table[i].index = i; ++ freq_table[i].driver_data = i; + freq_table[i].frequency = CPUFREQ_TABLE_END; + + *table = &freq_table[0]; +diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c +index edc089e9..c24cba1c 100644 +--- a/drivers/cpufreq/acpi-cpufreq.c ++++ b/drivers/cpufreq/acpi-cpufreq.c +@@ -232,7 +232,7 @@ static unsigned extract_msr(u32 msr, struct acpi_cpufreq_data *data) + perf = data->acpi_data; + + for (i = 0; data->freq_table[i].frequency != CPUFREQ_TABLE_END; i++) { +- if (msr == perf->states[data->freq_table[i].index].status) ++ if (msr == perf->states[data->freq_table[i].driver_data].status) + return data->freq_table[i].frequency; + } + return data->freq_table[0].frequency; +@@ -442,7 +442,7 @@ static int acpi_cpufreq_target(struct cpufreq_policy *policy, + goto out; + } + +- next_perf_state = data->freq_table[next_state].index; ++ next_perf_state = data->freq_table[next_state].driver_data; + if (perf->state == next_perf_state) { + if (unlikely(data->resume)) { + pr_debug("Called after resume, resetting to P%d\n", +@@ -811,7 +811,7 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) + data->freq_table[valid_states-1].frequency / 1000) + continue; + +- data->freq_table[valid_states].index = i; ++ data->freq_table[valid_states].driver_data = i; + data->freq_table[valid_states].frequency = + perf->states[i].core_frequency * 1000; + valid_states++; +diff --git a/drivers/cpufreq/blackfin-cpufreq.c b/drivers/cpufreq/blackfin-cpufreq.c +index 995511e80..9cdbbd27 100644 +--- a/drivers/cpufreq/blackfin-cpufreq.c ++++ b/drivers/cpufreq/blackfin-cpufreq.c +@@ -20,23 +20,23 @@ + + + /* this is the table of CCLK frequencies, in Hz */ +-/* .index is the entry in the auxiliary dpm_state_table[] */ ++/* .driver_data is the entry in the auxiliary dpm_state_table[] */ + static struct cpufreq_frequency_table bfin_freq_table[] = { + { + .frequency = CPUFREQ_TABLE_END, +- .index = 0, ++ .driver_data = 0, + }, + { + .frequency = CPUFREQ_TABLE_END, +- .index = 1, ++ .driver_data = 1, + }, + { + .frequency = CPUFREQ_TABLE_END, +- .index = 2, ++ .driver_data = 2, + }, + { + .frequency = CPUFREQ_TABLE_END, +- .index = 0, ++ .driver_data = 0, + }, + }; + +diff --git a/drivers/cpufreq/e_powersaver.c b/drivers/cpufreq/e_powersaver.c +index 37380fb9..324aff20 100644 +--- a/drivers/cpufreq/e_powersaver.c ++++ b/drivers/cpufreq/e_powersaver.c +@@ -188,7 +188,7 @@ static int eps_target(struct cpufreq_policy *policy, + } + + /* Make frequency transition */ +- dest_state = centaur->freq_table[newstate].index & 0xffff; ++ dest_state = centaur->freq_table[newstate].driver_data & 0xffff; + ret = eps_set_state(centaur, policy, dest_state); + if (ret) + printk(KERN_ERR "eps: Timeout!\n"); +@@ -380,9 +380,9 @@ static int eps_cpu_init(struct cpufreq_policy *policy) + f_table = ¢aur->freq_table[0]; + if (brand != EPS_BRAND_C7M) { + f_table[0].frequency = fsb * min_multiplier; +- f_table[0].index = (min_multiplier << 8) | min_voltage; ++ f_table[0].driver_data = (min_multiplier << 8) | min_voltage; + f_table[1].frequency = fsb * max_multiplier; +- f_table[1].index = (max_multiplier << 8) | max_voltage; ++ f_table[1].driver_data = (max_multiplier << 8) | max_voltage; + f_table[2].frequency = CPUFREQ_TABLE_END; + } else { + k = 0; +@@ -391,7 +391,7 @@ static int eps_cpu_init(struct cpufreq_policy *policy) + for (i = min_multiplier; i <= max_multiplier; i++) { + voltage = (k * step) / 256 + min_voltage; + f_table[k].frequency = fsb * i; +- f_table[k].index = (i << 8) | voltage; ++ f_table[k].driver_data = (i << 8) | voltage; + k++; + } + f_table[k].frequency = CPUFREQ_TABLE_END; +diff --git a/drivers/cpufreq/freq_table.c b/drivers/cpufreq/freq_table.c +index d7a79662..f0d87412 100644 +--- a/drivers/cpufreq/freq_table.c ++++ b/drivers/cpufreq/freq_table.c +@@ -34,8 +34,8 @@ int cpufreq_frequency_table_cpuinfo(struct cpufreq_policy *policy, + + continue; + } +- pr_debug("table entry %u: %u kHz, %u index\n", +- i, freq, table[i].index); ++ pr_debug("table entry %u: %u kHz, %u driver_data\n", ++ i, freq, table[i].driver_data); + if (freq < min_freq) + min_freq = freq; + if (freq > max_freq) +@@ -97,11 +97,11 @@ int cpufreq_frequency_table_target(struct cpufreq_policy *policy, + unsigned int *index) + { + struct cpufreq_frequency_table optimal = { +- .index = ~0, ++ .driver_data = ~0, + .frequency = 0, + }; + struct cpufreq_frequency_table suboptimal = { +- .index = ~0, ++ .driver_data = ~0, + .frequency = 0, + }; + unsigned int i; +@@ -129,12 +129,12 @@ int cpufreq_frequency_table_target(struct cpufreq_policy *policy, + if (freq <= target_freq) { + if (freq >= optimal.frequency) { + optimal.frequency = freq; +- optimal.index = i; ++ optimal.driver_data = i; + } + } else { + if (freq <= suboptimal.frequency) { + suboptimal.frequency = freq; +- suboptimal.index = i; ++ suboptimal.driver_data = i; + } + } + break; +@@ -142,26 +142,26 @@ int cpufreq_frequency_table_target(struct cpufreq_policy *policy, + if (freq >= target_freq) { + if (freq <= optimal.frequency) { + optimal.frequency = freq; +- optimal.index = i; ++ optimal.driver_data = i; + } + } else { + if (freq >= suboptimal.frequency) { + suboptimal.frequency = freq; +- suboptimal.index = i; ++ suboptimal.driver_data = i; + } + } + break; + } + } +- if (optimal.index > i) { +- if (suboptimal.index > i) ++ if (optimal.driver_data > i) { ++ if (suboptimal.driver_data > i) + return -EINVAL; +- *index = suboptimal.index; ++ *index = suboptimal.driver_data; + } else +- *index = optimal.index; ++ *index = optimal.driver_data; + + pr_debug("target is %u (%u kHz, %u)\n", *index, table[*index].frequency, +- table[*index].index); ++ table[*index].driver_data); + + return 0; + } +diff --git a/drivers/cpufreq/ia64-acpi-cpufreq.c b/drivers/cpufreq/ia64-acpi-cpufreq.c +index c0075dba..573c14ea 100644 +--- a/drivers/cpufreq/ia64-acpi-cpufreq.c ++++ b/drivers/cpufreq/ia64-acpi-cpufreq.c +@@ -326,7 +326,7 @@ acpi_cpufreq_cpu_init ( + /* table init */ + for (i = 0; i <= data->acpi_data.state_count; i++) + { +- data->freq_table[i].index = i; ++ data->freq_table[i].driver_data = i; + if (i < data->acpi_data.state_count) { + data->freq_table[i].frequency = + data->acpi_data.states[i].core_frequency * 1000; +diff --git a/drivers/cpufreq/kirkwood-cpufreq.c b/drivers/cpufreq/kirkwood-cpufreq.c +index b2644af9..c233ea61 100644 +--- a/drivers/cpufreq/kirkwood-cpufreq.c ++++ b/drivers/cpufreq/kirkwood-cpufreq.c +@@ -59,7 +59,7 @@ static void kirkwood_cpufreq_set_cpu_state(struct cpufreq_policy *policy, + unsigned int index) + { + struct cpufreq_freqs freqs; +- unsigned int state = kirkwood_freq_table[index].index; ++ unsigned int state = kirkwood_freq_table[index].driver_data; + unsigned long reg; + + freqs.old = kirkwood_cpufreq_get_cpu_frequency(0); +diff --git a/drivers/cpufreq/longhaul.c b/drivers/cpufreq/longhaul.c +index b448638e..b6a0a7a4 100644 +--- a/drivers/cpufreq/longhaul.c ++++ b/drivers/cpufreq/longhaul.c +@@ -254,7 +254,7 @@ static void longhaul_setstate(struct cpufreq_policy *policy, + u32 bm_timeout = 1000; + unsigned int dir = 0; + +- mults_index = longhaul_table[table_index].index; ++ mults_index = longhaul_table[table_index].driver_data; + /* Safety precautions */ + mult = mults[mults_index & 0x1f]; + if (mult == -1) +@@ -487,7 +487,7 @@ static int __cpuinit longhaul_get_ranges(void) + if (ratio > maxmult || ratio < minmult) + continue; + longhaul_table[k].frequency = calc_speed(ratio); +- longhaul_table[k].index = j; ++ longhaul_table[k].driver_data = j; + k++; + } + if (k <= 1) { +@@ -508,8 +508,8 @@ static int __cpuinit longhaul_get_ranges(void) + if (min_i != j) { + swap(longhaul_table[j].frequency, + longhaul_table[min_i].frequency); +- swap(longhaul_table[j].index, +- longhaul_table[min_i].index); ++ swap(longhaul_table[j].driver_data, ++ longhaul_table[min_i].driver_data); + } + } + +@@ -517,7 +517,7 @@ static int __cpuinit longhaul_get_ranges(void) + + /* Find index we are running on */ + for (j = 0; j < k; j++) { +- if (mults[longhaul_table[j].index & 0x1f] == mult) { ++ if (mults[longhaul_table[j].driver_data & 0x1f] == mult) { + longhaul_index = j; + break; + } +@@ -613,7 +613,7 @@ static void __cpuinit longhaul_setup_voltagescaling(void) + pos = (speed - min_vid_speed) / kHz_step + minvid.pos; + else + pos = minvid.pos; +- longhaul_table[j].index |= mV_vrm_table[pos] << 8; ++ longhaul_table[j].driver_data |= mV_vrm_table[pos] << 8; + vid = vrm_mV_table[mV_vrm_table[pos]]; + printk(KERN_INFO PFX "f: %d kHz, index: %d, vid: %d mV\n", + speed, j, vid.mV); +@@ -656,12 +656,12 @@ static int longhaul_target(struct cpufreq_policy *policy, + * this in hardware, C3 is old and we need to do this + * in software. */ + i = longhaul_index; +- current_vid = (longhaul_table[longhaul_index].index >> 8); ++ current_vid = (longhaul_table[longhaul_index].driver_data >> 8); + current_vid &= 0x1f; + if (table_index > longhaul_index) + dir = 1; + while (i != table_index) { +- vid = (longhaul_table[i].index >> 8) & 0x1f; ++ vid = (longhaul_table[i].driver_data >> 8) & 0x1f; + if (vid != current_vid) { + longhaul_setstate(policy, i); + current_vid = vid; +diff --git a/drivers/cpufreq/loongson2_cpufreq.c b/drivers/cpufreq/loongson2_cpufreq.c +index f92b02ae..9536852c 100644 +--- a/drivers/cpufreq/loongson2_cpufreq.c ++++ b/drivers/cpufreq/loongson2_cpufreq.c +@@ -72,7 +72,7 @@ static int loongson2_cpufreq_target(struct cpufreq_policy *policy, + + freq = + ((cpu_clock_freq / 1000) * +- loongson2_clockmod_table[newstate].index) / 8; ++ loongson2_clockmod_table[newstate].driver_data) / 8; + if (freq < policy->min || freq > policy->max) + return -EINVAL; + +diff --git a/drivers/cpufreq/p4-clockmod.c b/drivers/cpufreq/p4-clockmod.c +index 421ef37d..9ee78170 100644 +--- a/drivers/cpufreq/p4-clockmod.c ++++ b/drivers/cpufreq/p4-clockmod.c +@@ -118,7 +118,7 @@ static int cpufreq_p4_target(struct cpufreq_policy *policy, + return -EINVAL; + + freqs.old = cpufreq_p4_get(policy->cpu); +- freqs.new = stock_freq * p4clockmod_table[newstate].index / 8; ++ freqs.new = stock_freq * p4clockmod_table[newstate].driver_data / 8; + + if (freqs.new == freqs.old) + return 0; +@@ -131,7 +131,7 @@ static int cpufreq_p4_target(struct cpufreq_policy *policy, + * Developer's Manual, Volume 3 + */ + for_each_cpu(i, policy->cpus) +- cpufreq_p4_setdc(i, p4clockmod_table[newstate].index); ++ cpufreq_p4_setdc(i, p4clockmod_table[newstate].driver_data); + + /* notifiers */ + cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE); +diff --git a/drivers/cpufreq/powernow-k6.c b/drivers/cpufreq/powernow-k6.c +index ea0222a4..ea8e1038 100644 +--- a/drivers/cpufreq/powernow-k6.c ++++ b/drivers/cpufreq/powernow-k6.c +@@ -58,7 +58,7 @@ static int powernow_k6_get_cpu_multiplier(void) + msrval = POWERNOW_IOPORT + 0x0; + wrmsr(MSR_K6_EPMR, msrval, 0); /* disable it again */ + +- return clock_ratio[(invalue >> 5)&7].index; ++ return clock_ratio[(invalue >> 5)&7].driver_data; + } + + +@@ -75,13 +75,13 @@ static void powernow_k6_set_state(struct cpufreq_policy *policy, + unsigned long msrval; + struct cpufreq_freqs freqs; + +- if (clock_ratio[best_i].index > max_multiplier) { ++ if (clock_ratio[best_i].driver_data > max_multiplier) { + printk(KERN_ERR PFX "invalid target frequency\n"); + return; + } + + freqs.old = busfreq * powernow_k6_get_cpu_multiplier(); +- freqs.new = busfreq * clock_ratio[best_i].index; ++ freqs.new = busfreq * clock_ratio[best_i].driver_data; + + cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE); + +@@ -156,7 +156,7 @@ static int powernow_k6_cpu_init(struct cpufreq_policy *policy) + + /* table init */ + for (i = 0; (clock_ratio[i].frequency != CPUFREQ_TABLE_END); i++) { +- f = clock_ratio[i].index; ++ f = clock_ratio[i].driver_data; + if (f > max_multiplier) + clock_ratio[i].frequency = CPUFREQ_ENTRY_INVALID; + else +diff --git a/drivers/cpufreq/powernow-k7.c b/drivers/cpufreq/powernow-k7.c +index 53888dac..b9f80b71 100644 +--- a/drivers/cpufreq/powernow-k7.c ++++ b/drivers/cpufreq/powernow-k7.c +@@ -186,7 +186,7 @@ static int get_ranges(unsigned char *pst) + fid = *pst++; + + powernow_table[j].frequency = (fsb * fid_codes[fid]) / 10; +- powernow_table[j].index = fid; /* lower 8 bits */ ++ powernow_table[j].driver_data = fid; /* lower 8 bits */ + + speed = powernow_table[j].frequency; + +@@ -203,7 +203,7 @@ static int get_ranges(unsigned char *pst) + maximum_speed = speed; + + vid = *pst++; +- powernow_table[j].index |= (vid << 8); /* upper 8 bits */ ++ powernow_table[j].driver_data |= (vid << 8); /* upper 8 bits */ + + pr_debug(" FID: 0x%x (%d.%dx [%dMHz]) " + "VID: 0x%x (%d.%03dV)\n", fid, fid_codes[fid] / 10, +@@ -212,7 +212,7 @@ static int get_ranges(unsigned char *pst) + mobile_vid_table[vid]%1000); + } + powernow_table[number_scales].frequency = CPUFREQ_TABLE_END; +- powernow_table[number_scales].index = 0; ++ powernow_table[number_scales].driver_data = 0; + + return 0; + } +@@ -260,8 +260,8 @@ static void change_speed(struct cpufreq_policy *policy, unsigned int index) + * vid are the upper 8 bits. + */ + +- fid = powernow_table[index].index & 0xFF; +- vid = (powernow_table[index].index & 0xFF00) >> 8; ++ fid = powernow_table[index].driver_data & 0xFF; ++ vid = (powernow_table[index].driver_data & 0xFF00) >> 8; + + rdmsrl(MSR_K7_FID_VID_STATUS, fidvidstatus.val); + cfid = fidvidstatus.bits.CFID; +@@ -373,8 +373,8 @@ static int powernow_acpi_init(void) + fid = pc.bits.fid; + + powernow_table[i].frequency = fsb * fid_codes[fid] / 10; +- powernow_table[i].index = fid; /* lower 8 bits */ +- powernow_table[i].index |= (vid << 8); /* upper 8 bits */ ++ powernow_table[i].driver_data = fid; /* lower 8 bits */ ++ powernow_table[i].driver_data |= (vid << 8); /* upper 8 bits */ + + speed = powernow_table[i].frequency; + speed_mhz = speed / 1000; +@@ -417,7 +417,7 @@ static int powernow_acpi_init(void) + } + + powernow_table[i].frequency = CPUFREQ_TABLE_END; +- powernow_table[i].index = 0; ++ powernow_table[i].driver_data = 0; + + /* notify BIOS that we exist */ + acpi_processor_notify_smm(THIS_MODULE); +diff --git a/drivers/cpufreq/powernow-k8.c b/drivers/cpufreq/powernow-k8.c +index b828efe4..51343a12 100644 +--- a/drivers/cpufreq/powernow-k8.c ++++ b/drivers/cpufreq/powernow-k8.c +@@ -584,9 +584,9 @@ static void print_basics(struct powernow_k8_data *data) + CPUFREQ_ENTRY_INVALID) { + printk(KERN_INFO PFX + "fid 0x%x (%d MHz), vid 0x%x\n", +- data->powernow_table[j].index & 0xff, ++ data->powernow_table[j].driver_data & 0xff, + data->powernow_table[j].frequency/1000, +- data->powernow_table[j].index >> 8); ++ data->powernow_table[j].driver_data >> 8); + } + } + if (data->batps) +@@ -632,13 +632,13 @@ static int fill_powernow_table(struct powernow_k8_data *data, + + for (j = 0; j < data->numps; j++) { + int freq; +- powernow_table[j].index = pst[j].fid; /* lower 8 bits */ +- powernow_table[j].index |= (pst[j].vid << 8); /* upper 8 bits */ ++ powernow_table[j].driver_data = pst[j].fid; /* lower 8 bits */ ++ powernow_table[j].driver_data |= (pst[j].vid << 8); /* upper 8 bits */ + freq = find_khz_freq_from_fid(pst[j].fid); + powernow_table[j].frequency = freq; + } + powernow_table[data->numps].frequency = CPUFREQ_TABLE_END; +- powernow_table[data->numps].index = 0; ++ powernow_table[data->numps].driver_data = 0; + + if (query_current_values_with_pending_wait(data)) { + kfree(powernow_table); +@@ -810,7 +810,7 @@ static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data) + + powernow_table[data->acpi_data.state_count].frequency = + CPUFREQ_TABLE_END; +- powernow_table[data->acpi_data.state_count].index = 0; ++ powernow_table[data->acpi_data.state_count].driver_data = 0; + data->powernow_table = powernow_table; + + if (cpumask_first(cpu_core_mask(data->cpu)) == data->cpu) +@@ -865,7 +865,7 @@ static int fill_powernow_table_fidvid(struct powernow_k8_data *data, + pr_debug(" %d : fid 0x%x, vid 0x%x\n", i, fid, vid); + + index = fid | (vid<<8); +- powernow_table[i].index = index; ++ powernow_table[i].driver_data = index; + + freq = find_khz_freq_from_fid(fid); + powernow_table[i].frequency = freq; +@@ -941,8 +941,8 @@ static int transition_frequency_fidvid(struct powernow_k8_data *data, + * the cpufreq frequency table in find_psb_table, vid + * are the upper 8 bits. + */ +- fid = data->powernow_table[index].index & 0xFF; +- vid = (data->powernow_table[index].index & 0xFF00) >> 8; ++ fid = data->powernow_table[index].driver_data & 0xFF; ++ vid = (data->powernow_table[index].driver_data & 0xFF00) >> 8; + + pr_debug("table matched fid 0x%x, giving vid 0x%x\n", fid, vid); + +diff --git a/drivers/cpufreq/ppc_cbe_cpufreq.c b/drivers/cpufreq/ppc_cbe_cpufreq.c +index e577a1db..5936f8d6 100644 +--- a/drivers/cpufreq/ppc_cbe_cpufreq.c ++++ b/drivers/cpufreq/ppc_cbe_cpufreq.c +@@ -106,7 +106,7 @@ static int cbe_cpufreq_cpu_init(struct cpufreq_policy *policy) + + /* initialize frequency table */ + for (i=0; cbe_freqs[i].frequency!=CPUFREQ_TABLE_END; i++) { +- cbe_freqs[i].frequency = max_freq / cbe_freqs[i].index; ++ cbe_freqs[i].frequency = max_freq / cbe_freqs[i].driver_data; + pr_debug("%d: %d\n", i, cbe_freqs[i].frequency); + } + +@@ -165,7 +165,7 @@ static int cbe_cpufreq_target(struct cpufreq_policy *policy, + "1/%d of max frequency\n", + policy->cpu, + cbe_freqs[cbe_pmode_new].frequency, +- cbe_freqs[cbe_pmode_new].index); ++ cbe_freqs[cbe_pmode_new].driver_data); + + rc = set_pmode(policy->cpu, cbe_pmode_new); + +diff --git a/drivers/cpufreq/pxa2xx-cpufreq.c b/drivers/cpufreq/pxa2xx-cpufreq.c +index 9e5bc8e3..fb3981ac 100644 +--- a/drivers/cpufreq/pxa2xx-cpufreq.c ++++ b/drivers/cpufreq/pxa2xx-cpufreq.c +@@ -420,7 +420,7 @@ static int pxa_cpufreq_init(struct cpufreq_policy *policy) + /* Generate pxa25x the run cpufreq_frequency_table struct */ + for (i = 0; i < NUM_PXA25x_RUN_FREQS; i++) { + pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz; +- pxa255_run_freq_table[i].index = i; ++ pxa255_run_freq_table[i].driver_data = i; + } + pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END; + +@@ -428,7 +428,7 @@ static int pxa_cpufreq_init(struct cpufreq_policy *policy) + for (i = 0; i < NUM_PXA25x_TURBO_FREQS; i++) { + pxa255_turbo_freq_table[i].frequency = + pxa255_turbo_freqs[i].khz; +- pxa255_turbo_freq_table[i].index = i; ++ pxa255_turbo_freq_table[i].driver_data = i; + } + pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END; + +@@ -440,9 +440,9 @@ static int pxa_cpufreq_init(struct cpufreq_policy *policy) + if (freq > pxa27x_maxfreq) + break; + pxa27x_freq_table[i].frequency = freq; +- pxa27x_freq_table[i].index = i; ++ pxa27x_freq_table[i].driver_data = i; + } +- pxa27x_freq_table[i].index = i; ++ pxa27x_freq_table[i].driver_data = i; + pxa27x_freq_table[i].frequency = CPUFREQ_TABLE_END; + + /* +diff --git a/drivers/cpufreq/pxa3xx-cpufreq.c b/drivers/cpufreq/pxa3xx-cpufreq.c +index 15d60f85..9c92ef03 100644 +--- a/drivers/cpufreq/pxa3xx-cpufreq.c ++++ b/drivers/cpufreq/pxa3xx-cpufreq.c +@@ -98,10 +98,10 @@ static int setup_freqs_table(struct cpufreq_policy *policy, + return -ENOMEM; + + for (i = 0; i < num; i++) { +- table[i].index = i; ++ table[i].driver_data = i; + table[i].frequency = freqs[i].cpufreq_mhz * 1000; + } +- table[num].index = i; ++ table[num].driver_data = i; + table[num].frequency = CPUFREQ_TABLE_END; + + pxa3xx_freqs = freqs; +diff --git a/drivers/cpufreq/s3c2416-cpufreq.c b/drivers/cpufreq/s3c2416-cpufreq.c +index 4f1881ee..69f2e558 100644 +--- a/drivers/cpufreq/s3c2416-cpufreq.c ++++ b/drivers/cpufreq/s3c2416-cpufreq.c +@@ -244,7 +244,7 @@ static int s3c2416_cpufreq_set_target(struct cpufreq_policy *policy, + if (ret != 0) + goto out; + +- idx = s3c_freq->freq_table[i].index; ++ idx = s3c_freq->freq_table[i].driver_data; + + if (idx == SOURCE_HCLK) + to_dvs = 1; +diff --git a/drivers/cpufreq/s3c64xx-cpufreq.c b/drivers/cpufreq/s3c64xx-cpufreq.c +index 27cacb52..306d395d 100644 +--- a/drivers/cpufreq/s3c64xx-cpufreq.c ++++ b/drivers/cpufreq/s3c64xx-cpufreq.c +@@ -87,7 +87,7 @@ static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy, + freqs.old = clk_get_rate(armclk) / 1000; + freqs.new = s3c64xx_freq_table[i].frequency; + freqs.flags = 0; +- dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[i].index]; ++ dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[i].driver_data]; + + if (freqs.old == freqs.new) + return 0; +diff --git a/drivers/cpufreq/sc520_freq.c b/drivers/cpufreq/sc520_freq.c +index f740b134..77a21097 100644 +--- a/drivers/cpufreq/sc520_freq.c ++++ b/drivers/cpufreq/sc520_freq.c +@@ -71,7 +71,7 @@ static void sc520_freq_set_cpu_state(struct cpufreq_policy *policy, + local_irq_disable(); + + clockspeed_reg = *cpuctl & ~0x03; +- *cpuctl = clockspeed_reg | sc520_freq_table[state].index; ++ *cpuctl = clockspeed_reg | sc520_freq_table[state].driver_data; + + local_irq_enable(); + +diff --git a/drivers/cpufreq/sparc-us2e-cpufreq.c b/drivers/cpufreq/sparc-us2e-cpufreq.c +index 306ae462..93061a40 100644 +--- a/drivers/cpufreq/sparc-us2e-cpufreq.c ++++ b/drivers/cpufreq/sparc-us2e-cpufreq.c +@@ -308,17 +308,17 @@ static int __init us2e_freq_cpu_init(struct cpufreq_policy *policy) + struct cpufreq_frequency_table *table = + &us2e_freq_table[cpu].table[0]; + +- table[0].index = 0; ++ table[0].driver_data = 0; + table[0].frequency = clock_tick / 1; +- table[1].index = 1; ++ table[1].driver_data = 1; + table[1].frequency = clock_tick / 2; +- table[2].index = 2; ++ table[2].driver_data = 2; + table[2].frequency = clock_tick / 4; +- table[2].index = 3; ++ table[2].driver_data = 3; + table[2].frequency = clock_tick / 6; +- table[2].index = 4; ++ table[2].driver_data = 4; + table[2].frequency = clock_tick / 8; +- table[2].index = 5; ++ table[2].driver_data = 5; + table[3].frequency = CPUFREQ_TABLE_END; + + policy->cpuinfo.transition_latency = 0; +diff --git a/drivers/cpufreq/sparc-us3-cpufreq.c b/drivers/cpufreq/sparc-us3-cpufreq.c +index c71ee142..880ee293 100644 +--- a/drivers/cpufreq/sparc-us3-cpufreq.c ++++ b/drivers/cpufreq/sparc-us3-cpufreq.c +@@ -169,13 +169,13 @@ static int __init us3_freq_cpu_init(struct cpufreq_policy *policy) + struct cpufreq_frequency_table *table = + &us3_freq_table[cpu].table[0]; + +- table[0].index = 0; ++ table[0].driver_data = 0; + table[0].frequency = clock_tick / 1; +- table[1].index = 1; ++ table[1].driver_data = 1; + table[1].frequency = clock_tick / 2; +- table[2].index = 2; ++ table[2].driver_data = 2; + table[2].frequency = clock_tick / 32; +- table[3].index = 0; ++ table[3].driver_data = 0; + table[3].frequency = CPUFREQ_TABLE_END; + + policy->cpuinfo.transition_latency = 0; +diff --git a/drivers/cpufreq/spear-cpufreq.c b/drivers/cpufreq/spear-cpufreq.c +index 156829f4..c3efa7f2 100644 +--- a/drivers/cpufreq/spear-cpufreq.c ++++ b/drivers/cpufreq/spear-cpufreq.c +@@ -250,11 +250,11 @@ static int spear_cpufreq_driver_init(void) + } + + for (i = 0; i < cnt; i++) { +- freq_tbl[i].index = i; ++ freq_tbl[i].driver_data = i; + freq_tbl[i].frequency = be32_to_cpup(val++); + } + +- freq_tbl[i].index = i; ++ freq_tbl[i].driver_data = i; + freq_tbl[i].frequency = CPUFREQ_TABLE_END; + + spear_cpufreq.freq_tbl = freq_tbl; +diff --git a/drivers/cpufreq/speedstep-centrino.c b/drivers/cpufreq/speedstep-centrino.c +index 618e6f41..0915e712 100644 +--- a/drivers/cpufreq/speedstep-centrino.c ++++ b/drivers/cpufreq/speedstep-centrino.c +@@ -79,11 +79,11 @@ static struct cpufreq_driver centrino_driver; + + /* Computes the correct form for IA32_PERF_CTL MSR for a particular + frequency/voltage operating point; frequency in MHz, volts in mV. +- This is stored as "index" in the structure. */ ++ This is stored as "driver_data" in the structure. */ + #define OP(mhz, mv) \ + { \ + .frequency = (mhz) * 1000, \ +- .index = (((mhz)/100) << 8) | ((mv - 700) / 16) \ ++ .driver_data = (((mhz)/100) << 8) | ((mv - 700) / 16) \ + } + + /* +@@ -307,7 +307,7 @@ static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe) + per_cpu(centrino_model, cpu)->op_points[i].frequency + != CPUFREQ_TABLE_END; + i++) { +- if (msr == per_cpu(centrino_model, cpu)->op_points[i].index) ++ if (msr == per_cpu(centrino_model, cpu)->op_points[i].driver_data) + return per_cpu(centrino_model, cpu)-> + op_points[i].frequency; + } +@@ -501,7 +501,7 @@ static int centrino_target (struct cpufreq_policy *policy, + break; + } + +- msr = per_cpu(centrino_model, cpu)->op_points[newstate].index; ++ msr = per_cpu(centrino_model, cpu)->op_points[newstate].driver_data; + + if (first_cpu) { + rdmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, &oldmsr, &h); +diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c +index 66f80973..ed79d7b7 100644 +--- a/drivers/mfd/db8500-prcmu.c ++++ b/drivers/mfd/db8500-prcmu.c +@@ -1724,9 +1724,9 @@ static long round_clock_rate(u8 clock, unsigned long rate) + + /* CPU FREQ table, may be changed due to if MAX_OPP is supported. */ + static struct cpufreq_frequency_table db8500_cpufreq_table[] = { +- { .frequency = 200000, .index = ARM_EXTCLK,}, +- { .frequency = 400000, .index = ARM_50_OPP,}, +- { .frequency = 800000, .index = ARM_100_OPP,}, ++ { .frequency = 200000, .driver_data = ARM_EXTCLK,}, ++ { .frequency = 400000, .driver_data = ARM_50_OPP,}, ++ { .frequency = 800000, .driver_data = ARM_100_OPP,}, + { .frequency = CPUFREQ_TABLE_END,}, /* To be used for MAX_OPP. */ + { .frequency = CPUFREQ_TABLE_END,}, + }; +@@ -1901,7 +1901,7 @@ static int set_armss_rate(unsigned long rate) + return -EINVAL; + + /* Set the new arm opp. */ +- return db8500_prcmu_set_arm_opp(db8500_cpufreq_table[i].index); ++ return db8500_prcmu_set_arm_opp(db8500_cpufreq_table[i].driver_data); + } + + static int set_plldsi_rate(unsigned long rate) +@@ -3105,7 +3105,7 @@ static void db8500_prcmu_update_cpufreq(void) + { + if (prcmu_has_arm_maxopp()) { + db8500_cpufreq_table[3].frequency = 1000000; +- db8500_cpufreq_table[3].index = ARM_MAX_OPP; ++ db8500_cpufreq_table[3].driver_data = ARM_MAX_OPP; + } + } + +diff --git a/drivers/sh/clk/core.c b/drivers/sh/clk/core.c +index 7715de26..74727851 100644 +--- a/drivers/sh/clk/core.c ++++ b/drivers/sh/clk/core.c +@@ -63,12 +63,12 @@ void clk_rate_table_build(struct clk *clk, + else + freq = clk->parent->rate * mult / div; + +- freq_table[i].index = i; ++ freq_table[i].driver_data = i; + freq_table[i].frequency = freq; + } + + /* Termination entry */ +- freq_table[i].index = i; ++ freq_table[i].driver_data = i; + freq_table[i].frequency = CPUFREQ_TABLE_END; + } + +diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h +index 037d36ae..09ba2460 100644 +--- a/include/linux/cpufreq.h ++++ b/include/linux/cpufreq.h +@@ -404,7 +404,7 @@ extern struct cpufreq_governor cpufreq_gov_conservative; + #define CPUFREQ_TABLE_END ~1 + + struct cpufreq_frequency_table { +- unsigned int index; /* any */ ++ unsigned int driver_data; /* driver specific data, not used by core */ + unsigned int frequency; /* kHz - doesn't need to be in ascending + * order */ + }; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0162-ARM-shmobile-bockw-enable-I2C-in-defconfig.patch b/patches.renesas/0162-ARM-shmobile-bockw-enable-I2C-in-defconfig.patch new file mode 100644 index 00000000000..3c67b8ff3ea --- /dev/null +++ b/patches.renesas/0162-ARM-shmobile-bockw-enable-I2C-in-defconfig.patch @@ -0,0 +1,35 @@ +From 7034d79fe6267454d9c43dde22af23e3ce152e29 Mon Sep 17 00:00:00 2001 +From: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Date: Wed, 17 Apr 2013 22:47:27 +0400 +Subject: ARM: shmobile: bockw: enable I2C in defconfig + +Enable I2C driver in 'bockw_defconfig'. + +Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +[ horms+renesas@verge.net.au: resolved trivial conflicts ] +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit 5de156bbc79d3048561f6c117ea14e96e3b75cd0) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/configs/bockw_defconfig | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm/configs/bockw_defconfig b/arch/arm/configs/bockw_defconfig +index b74a4d43..2c3f34e3 100644 +--- a/arch/arm/configs/bockw_defconfig ++++ b/arch/arm/configs/bockw_defconfig +@@ -71,6 +71,8 @@ CONFIG_SERIAL_SH_SCI_NR_UARTS=6 + CONFIG_SERIAL_SH_SCI_CONSOLE=y + # CONFIG_HW_RANDOM is not set + # CONFIG_HWMON is not set ++CONFIG_I2C=y ++CONFIG_I2C_RCAR=y + # CONFIG_USB_SUPPORT is not set + CONFIG_MMC=y + CONFIG_MMC_SDHI=y +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0163-ARM-shmobile-bockw-enable-CONFIG_PM_RUNTIME-in-defco.patch b/patches.renesas/0163-ARM-shmobile-bockw-enable-CONFIG_PM_RUNTIME-in-defco.patch new file mode 100644 index 00000000000..9b53f96a0fd --- /dev/null +++ b/patches.renesas/0163-ARM-shmobile-bockw-enable-CONFIG_PM_RUNTIME-in-defco.patch @@ -0,0 +1,32 @@ +From 7fdfbf217bdde0b676710cb4c1b20615e841201d Mon Sep 17 00:00:00 2001 +From: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Date: Wed, 17 Apr 2013 03:03:45 +0400 +Subject: ARM: shmobile: bockw: enable CONFIG_PM_RUNTIME in defconfig + +Enable CONFIG_PM_RUNTIME in 'bockw_defconfig' -- it's already used by TMU, SCI, +I2C, and Ether drivers to control the clocks... + +Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 3308f0e7c9723f01a21cd727bd2e46d5f2af6358) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/configs/bockw_defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/configs/bockw_defconfig b/arch/arm/configs/bockw_defconfig +index 2c3f34e3..a4bc76d2 100644 +--- a/arch/arm/configs/bockw_defconfig ++++ b/arch/arm/configs/bockw_defconfig +@@ -31,6 +31,7 @@ CONFIG_CMDLINE="console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp" + CONFIG_CMDLINE_FORCE=y + # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set + # CONFIG_SUSPEND is not set ++CONFIG_PM_RUNTIME=y + CONFIG_NET=y + CONFIG_UNIX=y + CONFIG_INET=y +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0164-ARM-shmobile-bockw-enable-USB-in-defconfig.patch b/patches.renesas/0164-ARM-shmobile-bockw-enable-USB-in-defconfig.patch new file mode 100644 index 00000000000..fc9f4a2000c --- /dev/null +++ b/patches.renesas/0164-ARM-shmobile-bockw-enable-USB-in-defconfig.patch @@ -0,0 +1,48 @@ +From 4fd737d4ef8dacac425593317333d2a7633162f3 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Wed, 17 Apr 2013 01:35:09 +0400 +Subject: ARM: shmobile: bockw: enable USB in defconfig + +Enable USB platform EHCI/OHCI and common PHY drivers in 'bockw_defconfig'. +Enable USB storage driver and SCSI disk driver that it needs as well... + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit fadc6e3ba1d2e79e25918da73093038c19297f30) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/configs/bockw_defconfig | 11 ++++++++++- + 1 file changed, 10 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/configs/bockw_defconfig b/arch/arm/configs/bockw_defconfig +index a4bc76d2..d6626086 100644 +--- a/arch/arm/configs/bockw_defconfig ++++ b/arch/arm/configs/bockw_defconfig +@@ -49,6 +49,8 @@ CONFIG_DEVTMPFS_MOUNT=y + # CONFIG_STANDALONE is not set + # CONFIG_PREVENT_FIRMWARE_BUILD is not set + # CONFIG_FW_LOADER is not set ++CONFIG_SCSI=y ++CONFIG_BLK_DEV_SD=y + CONFIG_NETDEVICES=y + # CONFIG_NET_CADENCE is not set + # CONFIG_NET_VENDOR_BROADCOM is not set +@@ -74,7 +76,14 @@ CONFIG_SERIAL_SH_SCI_CONSOLE=y + # CONFIG_HWMON is not set + CONFIG_I2C=y + CONFIG_I2C_RCAR=y +-# CONFIG_USB_SUPPORT is not set ++CONFIG_USB=y ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_HCD_PLATFORM=y ++CONFIG_USB_EHCI_HCD_PLATFORM=y ++CONFIG_USB_STORAGE=y ++CONFIG_USB_RCAR_PHY=y + CONFIG_MMC=y + CONFIG_MMC_SDHI=y + CONFIG_UIO=y +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0165-ARM-shmobile-kzm9g-enable-AS3711-PMIC-in-defconfig.patch b/patches.renesas/0165-ARM-shmobile-kzm9g-enable-AS3711-PMIC-in-defconfig.patch new file mode 100644 index 00000000000..19003fe173d --- /dev/null +++ b/patches.renesas/0165-ARM-shmobile-kzm9g-enable-AS3711-PMIC-in-defconfig.patch @@ -0,0 +1,36 @@ +From 214e21b018364687b5d6574ff2f96b35e1ae3ab4 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Wed, 3 Apr 2013 17:53:54 +0200 +Subject: ARM: shmobile: kzm9g: enable AS3711 PMIC in defconfig + +An AS3711 PMIC is used on kzm9g to supply CPU power and LCD backlight. +This patch enables it in board defconfig. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 76d415dfa7d53a2f92550484d766ae475a427daf) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/configs/kzm9g_defconfig | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig +index f6e585b3..1ad02802 100644 +--- a/arch/arm/configs/kzm9g_defconfig ++++ b/arch/arm/configs/kzm9g_defconfig +@@ -84,9 +84,12 @@ CONFIG_I2C_CHARDEV=y + CONFIG_I2C_SH_MOBILE=y + CONFIG_GPIO_PCF857X=y + # CONFIG_HWMON is not set ++CONFIG_MFD_AS3711=y + CONFIG_REGULATOR=y ++CONFIG_REGULATOR_AS3711=y + CONFIG_FB=y + CONFIG_FB_SH_MOBILE_LCDC=y ++CONFIG_BACKLIGHT_AS3711=y + CONFIG_FRAMEBUFFER_CONSOLE=y + CONFIG_LOGO=y + CONFIG_FB_SH_MOBILE_MERAM=y +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0166-ARM-shmobile-armadillo800eva-Convert-SCIFA1-to-pinct.patch b/patches.renesas/0166-ARM-shmobile-armadillo800eva-Convert-SCIFA1-to-pinct.patch new file mode 100644 index 00000000000..7931b693ef9 --- /dev/null +++ b/patches.renesas/0166-ARM-shmobile-armadillo800eva-Convert-SCIFA1-to-pinct.patch @@ -0,0 +1,44 @@ +From 60f96820cf1c2fc3b98b4d4bc4e7813d3ec6083c Mon Sep 17 00:00:00 2001 +From: Bastian Hecht <hechtb@gmail.com> +Date: Wed, 17 Apr 2013 10:34:02 +0000 +Subject: ARM: shmobile: armadillo800eva: Convert SCIFA1 to pinctrl + +We use the new pinctrl framework now. + +Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 7cdfb46ea95292ad477af498470bd3a85d9b3dcb) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-armadillo800eva.c | 7 +++---- + 1 file changed, 3 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c +index aafa99b1..44a62150 100644 +--- a/arch/arm/mach-shmobile/board-armadillo800eva.c ++++ b/arch/arm/mach-shmobile/board-armadillo800eva.c +@@ -1087,6 +1087,9 @@ static const struct pinctrl_map eva_pinctrl_map[] = { + "mmc0_data8_1", "mmc0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740", + "mmc0_ctrl_1", "mmc0"), ++ /* SCIFA1 */ ++ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.1", "pfc-r8a7740", ++ "scifa1_data", "scifa1"), + /* SDHI0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740", + "sdhi0_data4", "sdhi0"), +@@ -1154,10 +1157,6 @@ static void __init eva_init(void) + r8a7740_pinmux_init(); + r8a7740_meram_workaround(); + +- /* SCIFA1 */ +- gpio_request(GPIO_FN_SCIFA1_RXD, NULL); +- gpio_request(GPIO_FN_SCIFA1_TXD, NULL); +- + /* LCDC0 */ + gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ + gpio_request_one(202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0167-ARM-shmobile-r8a7740-Remove-SCIF-function-GPIOs.patch b/patches.renesas/0167-ARM-shmobile-r8a7740-Remove-SCIF-function-GPIOs.patch new file mode 100644 index 00000000000..3ab13f00e21 --- /dev/null +++ b/patches.renesas/0167-ARM-shmobile-r8a7740-Remove-SCIF-function-GPIOs.patch @@ -0,0 +1,104 @@ +From 1f4ffa359021ea6aebd05dd44c14f2615d73447e Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 18 Apr 2013 01:06:57 +0200 +Subject: ARM: shmobile: r8a7740: Remove SCIF function GPIOs + +Those GPIOs have been deprecated by the pinctrl API. They are unused and +unneeded, remove them. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit ac32d7cbf0c300b72cc985868bf0cc6993cadd41) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/include/mach/r8a7740.h | 74 --------------------------- + 1 file changed, 74 deletions(-) + +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h +index 1cf6869b..2656a6df 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h +@@ -165,80 +165,6 @@ enum { + GPIO_FN_FMSOOBT, GPIO_FN_FMSOSLD, + GPIO_FN_FMSOCK, + +- /* SCIFA0 */ +- GPIO_FN_SCIFA0_SCK, GPIO_FN_SCIFA0_CTS, +- GPIO_FN_SCIFA0_RTS, GPIO_FN_SCIFA0_RXD, +- GPIO_FN_SCIFA0_TXD, +- +- /* SCIFA1 */ +- GPIO_FN_SCIFA1_CTS, GPIO_FN_SCIFA1_SCK, +- GPIO_FN_SCIFA1_RXD, GPIO_FN_SCIFA1_TXD, +- GPIO_FN_SCIFA1_RTS, +- +- /* SCIFA2 */ +- GPIO_FN_SCIFA2_SCK_PORT22, /* SCIFA2_SCK Port 22/199 */ +- GPIO_FN_SCIFA2_SCK_PORT199, +- GPIO_FN_SCIFA2_RXD, GPIO_FN_SCIFA2_TXD, +- GPIO_FN_SCIFA2_CTS, GPIO_FN_SCIFA2_RTS, +- +- /* SCIFA3 */ +- GPIO_FN_SCIFA3_RTS_PORT105, /* MSEL5CR_8_0 */ +- GPIO_FN_SCIFA3_SCK_PORT116, +- GPIO_FN_SCIFA3_CTS_PORT117, +- GPIO_FN_SCIFA3_RXD_PORT174, +- GPIO_FN_SCIFA3_TXD_PORT175, +- +- GPIO_FN_SCIFA3_RTS_PORT161, /* MSEL5CR_8_1 */ +- GPIO_FN_SCIFA3_SCK_PORT158, +- GPIO_FN_SCIFA3_CTS_PORT162, +- GPIO_FN_SCIFA3_RXD_PORT159, +- GPIO_FN_SCIFA3_TXD_PORT160, +- +- /* SCIFA4 */ +- GPIO_FN_SCIFA4_RXD_PORT12, /* MSEL5CR[12:11] = 00 */ +- GPIO_FN_SCIFA4_TXD_PORT13, +- +- GPIO_FN_SCIFA4_RXD_PORT204, /* MSEL5CR[12:11] = 01 */ +- GPIO_FN_SCIFA4_TXD_PORT203, +- +- GPIO_FN_SCIFA4_RXD_PORT94, /* MSEL5CR[12:11] = 10 */ +- GPIO_FN_SCIFA4_TXD_PORT93, +- +- GPIO_FN_SCIFA4_SCK_PORT21, /* SCIFA4_SCK Port 21/205 */ +- GPIO_FN_SCIFA4_SCK_PORT205, +- +- /* SCIFA5 */ +- GPIO_FN_SCIFA5_TXD_PORT20, /* MSEL5CR[15:14] = 00 */ +- GPIO_FN_SCIFA5_RXD_PORT10, +- +- GPIO_FN_SCIFA5_RXD_PORT207, /* MSEL5CR[15:14] = 01 */ +- GPIO_FN_SCIFA5_TXD_PORT208, +- +- GPIO_FN_SCIFA5_TXD_PORT91, /* MSEL5CR[15:14] = 10 */ +- GPIO_FN_SCIFA5_RXD_PORT92, +- +- GPIO_FN_SCIFA5_SCK_PORT23, /* SCIFA5_SCK Port 23/206 */ +- GPIO_FN_SCIFA5_SCK_PORT206, +- +- /* SCIFA6 */ +- GPIO_FN_SCIFA6_SCK, GPIO_FN_SCIFA6_RXD, GPIO_FN_SCIFA6_TXD, +- +- /* SCIFA7 */ +- GPIO_FN_SCIFA7_TXD, GPIO_FN_SCIFA7_RXD, +- +- /* SCIFAB */ +- GPIO_FN_SCIFB_SCK_PORT190, /* MSEL5CR_17_0 */ +- GPIO_FN_SCIFB_RXD_PORT191, +- GPIO_FN_SCIFB_TXD_PORT192, +- GPIO_FN_SCIFB_RTS_PORT186, +- GPIO_FN_SCIFB_CTS_PORT187, +- +- GPIO_FN_SCIFB_SCK_PORT2, /* MSEL5CR_17_1 */ +- GPIO_FN_SCIFB_RXD_PORT3, +- GPIO_FN_SCIFB_TXD_PORT4, +- GPIO_FN_SCIFB_RTS_PORT172, +- GPIO_FN_SCIFB_CTS_PORT173, +- + /* LCD0 */ + GPIO_FN_LCDC0_SELECT, + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0168-ARM-shmobile-r8a7740-Remove-INTC-function-GPIOs.patch b/patches.renesas/0168-ARM-shmobile-r8a7740-Remove-INTC-function-GPIOs.patch new file mode 100644 index 00000000000..a2385e771d0 --- /dev/null +++ b/patches.renesas/0168-ARM-shmobile-r8a7740-Remove-INTC-function-GPIOs.patch @@ -0,0 +1,64 @@ +From 37826ef2222350b92c1675f12e82ef242d18595c Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 18 Apr 2013 01:06:57 +0200 +Subject: ARM: shmobile: r8a7740: Remove INTC function GPIOs + +Those GPIOs have been deprecated by the pinctrl API. They are unused and +unneeded, remove them. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 1343000c34e84cd31e720dbefd491e6b06347f33) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/include/mach/r8a7740.h | 34 --------------------------- + 1 file changed, 34 deletions(-) + +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h +index 2656a6df..ef6ddb6b 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h +@@ -100,40 +100,6 @@ enum { + + GPIO_PORT210, GPIO_PORT211, + +- /* IRQ */ +- GPIO_FN_IRQ0_PORT2, GPIO_FN_IRQ0_PORT13, +- GPIO_FN_IRQ1, +- GPIO_FN_IRQ2_PORT11, GPIO_FN_IRQ2_PORT12, +- GPIO_FN_IRQ3_PORT10, GPIO_FN_IRQ3_PORT14, +- GPIO_FN_IRQ4_PORT15, GPIO_FN_IRQ4_PORT172, +- GPIO_FN_IRQ5_PORT0, GPIO_FN_IRQ5_PORT1, +- GPIO_FN_IRQ6_PORT121, GPIO_FN_IRQ6_PORT173, +- GPIO_FN_IRQ7_PORT120, GPIO_FN_IRQ7_PORT209, +- GPIO_FN_IRQ8, +- GPIO_FN_IRQ9_PORT118, GPIO_FN_IRQ9_PORT210, +- GPIO_FN_IRQ10, +- GPIO_FN_IRQ11, +- GPIO_FN_IRQ12_PORT42, GPIO_FN_IRQ12_PORT97, +- GPIO_FN_IRQ13_PORT64, GPIO_FN_IRQ13_PORT98, +- GPIO_FN_IRQ14_PORT63, GPIO_FN_IRQ14_PORT99, +- GPIO_FN_IRQ15_PORT62, GPIO_FN_IRQ15_PORT100, +- GPIO_FN_IRQ16_PORT68, GPIO_FN_IRQ16_PORT211, +- GPIO_FN_IRQ17, +- GPIO_FN_IRQ18, +- GPIO_FN_IRQ19, +- GPIO_FN_IRQ20, +- GPIO_FN_IRQ21, +- GPIO_FN_IRQ22, +- GPIO_FN_IRQ23, +- GPIO_FN_IRQ24, +- GPIO_FN_IRQ25, +- GPIO_FN_IRQ26_PORT58, GPIO_FN_IRQ26_PORT81, +- GPIO_FN_IRQ27_PORT57, GPIO_FN_IRQ27_PORT168, +- GPIO_FN_IRQ28_PORT56, GPIO_FN_IRQ28_PORT169, +- GPIO_FN_IRQ29_PORT50, GPIO_FN_IRQ29_PORT170, +- GPIO_FN_IRQ30_PORT49, GPIO_FN_IRQ30_PORT171, +- GPIO_FN_IRQ31_PORT41, GPIO_FN_IRQ31_PORT167, +- + /* Function */ + + /* DBGT */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0169-ARM-shmobile-r8a7740-Remove-BSC-function-GPIOs.patch b/patches.renesas/0169-ARM-shmobile-r8a7740-Remove-BSC-function-GPIOs.patch new file mode 100644 index 00000000000..c63e99e02bd --- /dev/null +++ b/patches.renesas/0169-ARM-shmobile-r8a7740-Remove-BSC-function-GPIOs.patch @@ -0,0 +1,64 @@ +From 1793bdcf3c603dfafb8a64bbfa50e8cfb38e0632 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 18 Apr 2013 01:06:57 +0200 +Subject: ARM: shmobile: r8a7740: Remove BSC function GPIOs + +Those GPIOs have been deprecated by the pinctrl API. They are unused and +unneeded, remove them. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 45bfd2adab925bee7fc39100dcd3fc8f19088a7a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/include/mach/r8a7740.h | 27 ++------------------------- + 1 file changed, 2 insertions(+), 25 deletions(-) + +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h +index ef6ddb6b..28c0542e 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h +@@ -297,11 +297,7 @@ enum { + GPIO_FN_BBIF2_TSCK2_PORT89, + GPIO_FN_BBIF2_TSYNC2_PORT184, + +- /* BSC / FLCTL / PCMCIA */ +- GPIO_FN_CS0, GPIO_FN_CS2, GPIO_FN_CS4, +- GPIO_FN_CS5B, GPIO_FN_CS6A, +- GPIO_FN_CS5A_PORT105, /* CS5A PORT 19/105 */ +- GPIO_FN_CS5A_PORT19, ++ /* FLCTL / PCMCIA */ + GPIO_FN_IOIS16, /* ? */ + + GPIO_FN_A0, GPIO_FN_A1, GPIO_FN_A2, GPIO_FN_A3, +@@ -314,26 +310,7 @@ enum { + GPIO_FN_A22, GPIO_FN_A23, GPIO_FN_A24, GPIO_FN_A25, + GPIO_FN_A26, + +- GPIO_FN_D0_NAF0, GPIO_FN_D1_NAF1, /* share with FLCTL */ +- GPIO_FN_D2_NAF2, GPIO_FN_D3_NAF3, /* share with FLCTL */ +- GPIO_FN_D4_NAF4, GPIO_FN_D5_NAF5, /* share with FLCTL */ +- GPIO_FN_D6_NAF6, GPIO_FN_D7_NAF7, /* share with FLCTL */ +- GPIO_FN_D8_NAF8, GPIO_FN_D9_NAF9, /* share with FLCTL */ +- GPIO_FN_D10_NAF10, GPIO_FN_D11_NAF11, /* share with FLCTL */ +- GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, /* share with FLCTL */ +- GPIO_FN_D14_NAF14, GPIO_FN_D15_NAF15, /* share with FLCTL */ +- +- GPIO_FN_D16, GPIO_FN_D17, GPIO_FN_D18, GPIO_FN_D19, +- GPIO_FN_D20, GPIO_FN_D21, GPIO_FN_D22, GPIO_FN_D23, +- GPIO_FN_D24, GPIO_FN_D25, GPIO_FN_D26, GPIO_FN_D27, +- GPIO_FN_D28, GPIO_FN_D29, GPIO_FN_D30, GPIO_FN_D31, +- +- GPIO_FN_WE0_FWE, /* share with FLCTL */ +- GPIO_FN_WE1, +- GPIO_FN_WE2_ICIORD, /* share with PCMCIA */ +- GPIO_FN_WE3_ICIOWR, /* share with PCMCIA */ +- GPIO_FN_CKO, GPIO_FN_BS, GPIO_FN_RDWR, +- GPIO_FN_RD_FSC, /* share with FLCTL */ ++ GPIO_FN_CKO, + GPIO_FN_WAIT_PORT177, /* WAIT Port 90/177 */ + GPIO_FN_WAIT_PORT90, + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0170-ARM-shmobile-r8a7740-Remove-GETHER-function-GPIOs.patch b/patches.renesas/0170-ARM-shmobile-r8a7740-Remove-GETHER-function-GPIOs.patch new file mode 100644 index 00000000000..2d8347f4edd --- /dev/null +++ b/patches.renesas/0170-ARM-shmobile-r8a7740-Remove-GETHER-function-GPIOs.patch @@ -0,0 +1,53 @@ +From c7164e513bd2b0596b74a79dcd4ae0a14332360b Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 18 Apr 2013 01:06:57 +0200 +Subject: ARM: shmobile: r8a7740: Remove GETHER function GPIOs + +Those GPIOs have been deprecated by the pinctrl API. They are unused and +unneeded, remove them. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 3dad31ad2eb56f07df795c53cec47e99d46d0ee1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/include/mach/r8a7740.h | 23 ----------------------- + 1 file changed, 23 deletions(-) + +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h +index 28c0542e..3a8de9c1 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h +@@ -331,29 +331,6 @@ enum { + GPIO_FN_IDE_INT, GPIO_FN_IDE_RST, GPIO_FN_IDE_DIRECTION, + GPIO_FN_IDE_EXBUF_ENB, GPIO_FN_IDE_IODACK, GPIO_FN_IDE_IODREQ, + +- /* RMII */ +- GPIO_FN_RMII_CRS_DV, GPIO_FN_RMII_RX_ER, GPIO_FN_RMII_RXD0, +- GPIO_FN_RMII_RXD1, GPIO_FN_RMII_TX_EN, GPIO_FN_RMII_TXD0, +- GPIO_FN_RMII_MDC, GPIO_FN_RMII_TXD1, GPIO_FN_RMII_MDIO, +- GPIO_FN_RMII_REF50CK, /* for RMII */ +- GPIO_FN_RMII_REF125CK, /* for GMII */ +- +- /* GEther */ +- GPIO_FN_ET_TX_CLK, GPIO_FN_ET_TX_EN, GPIO_FN_ET_ETXD0, +- GPIO_FN_ET_ETXD1, GPIO_FN_ET_ETXD2, GPIO_FN_ET_ETXD3, +- GPIO_FN_ET_ETXD4, GPIO_FN_ET_ETXD5, /* for GEther */ +- GPIO_FN_ET_ETXD6, GPIO_FN_ET_ETXD7, /* for GEther */ +- GPIO_FN_ET_COL, GPIO_FN_ET_TX_ER, +- GPIO_FN_ET_RX_CLK, GPIO_FN_ET_RX_DV, +- GPIO_FN_ET_ERXD0, GPIO_FN_ET_ERXD1, +- GPIO_FN_ET_ERXD2, GPIO_FN_ET_ERXD3, +- GPIO_FN_ET_ERXD4, GPIO_FN_ET_ERXD5, /* for GEther */ +- GPIO_FN_ET_ERXD6, GPIO_FN_ET_ERXD7, /* for GEther */ +- GPIO_FN_ET_RX_ER, GPIO_FN_ET_CRS, +- GPIO_FN_ET_MDC, GPIO_FN_ET_MDIO, +- GPIO_FN_ET_LINK, GPIO_FN_ET_PHY_INT, +- GPIO_FN_ET_WOL, GPIO_FN_ET_GTX_CLK, +- + /* DMA0 */ + GPIO_FN_DREQ0, GPIO_FN_DACK0, + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0171-ARM-shmobile-r8a7740-Remove-CEU-function-GPIOs.patch b/patches.renesas/0171-ARM-shmobile-r8a7740-Remove-CEU-function-GPIOs.patch new file mode 100644 index 00000000000..9e3ee4a1d33 --- /dev/null +++ b/patches.renesas/0171-ARM-shmobile-r8a7740-Remove-CEU-function-GPIOs.patch @@ -0,0 +1,58 @@ +From 6e1d3d5e50571d4ce551c3708534fe7642920b73 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 18 Apr 2013 01:06:57 +0200 +Subject: ARM: shmobile: r8a7740: Remove CEU function GPIOs + +Those GPIOs have been deprecated by the pinctrl API. They are unused and +unneeded, remove them. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 102b61e80ba2741e018229453284e1f1371c3922) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/include/mach/r8a7740.h | 28 --------------------------- + 1 file changed, 28 deletions(-) + +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h +index 3a8de9c1..4bec7cd6 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h +@@ -143,34 +143,6 @@ enum { + GPIO_FN_RSPI_MOSI_A, GPIO_FN_RSPI_MISO_A, + GPIO_FN_RSPI_CK_A, + +- /* VIO CKO */ +- GPIO_FN_VIO_CKO1, +- GPIO_FN_VIO_CKO2, +- GPIO_FN_VIO_CKO_1, +- GPIO_FN_VIO_CKO, +- +- /* VIO0 */ +- GPIO_FN_VIO0_D0, GPIO_FN_VIO0_D1, GPIO_FN_VIO0_D2, +- GPIO_FN_VIO0_D3, GPIO_FN_VIO0_D4, GPIO_FN_VIO0_D5, +- GPIO_FN_VIO0_D6, GPIO_FN_VIO0_D7, GPIO_FN_VIO0_D8, +- GPIO_FN_VIO0_D9, GPIO_FN_VIO0_D10, GPIO_FN_VIO0_D11, +- GPIO_FN_VIO0_D12, GPIO_FN_VIO0_VD, GPIO_FN_VIO0_HD, +- GPIO_FN_VIO0_CLK, GPIO_FN_VIO0_FIELD, +- +- GPIO_FN_VIO0_D13_PORT26, /* MSEL5CR_27_0 */ +- GPIO_FN_VIO0_D14_PORT25, +- GPIO_FN_VIO0_D15_PORT24, +- +- GPIO_FN_VIO0_D13_PORT22, /* MSEL5CR_27_1 */ +- GPIO_FN_VIO0_D14_PORT95, +- GPIO_FN_VIO0_D15_PORT96, +- +- /* VIO1 */ +- GPIO_FN_VIO1_D0, GPIO_FN_VIO1_D1, GPIO_FN_VIO1_D2, +- GPIO_FN_VIO1_D3, GPIO_FN_VIO1_D4, GPIO_FN_VIO1_D5, +- GPIO_FN_VIO1_D6, GPIO_FN_VIO1_D7, GPIO_FN_VIO1_VD, +- GPIO_FN_VIO1_HD, GPIO_FN_VIO1_CLK, GPIO_FN_VIO1_FIELD, +- + /* TPU0 */ + GPIO_FN_TPU0TO0, GPIO_FN_TPU0TO1, + GPIO_FN_TPU0TO3, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0172-ARM-shmobile-r8a7740-Remove-FSI-function-GPIOs.patch b/patches.renesas/0172-ARM-shmobile-r8a7740-Remove-FSI-function-GPIOs.patch new file mode 100644 index 00000000000..d297e826e66 --- /dev/null +++ b/patches.renesas/0172-ARM-shmobile-r8a7740-Remove-FSI-function-GPIOs.patch @@ -0,0 +1,44 @@ +From 48d3abadd3f62d6cb05fdb9f1889a437b1dde664 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 18 Apr 2013 01:06:57 +0200 +Subject: ARM: shmobile: r8a7740: Remove FSI function GPIOs + +Those GPIOs have been deprecated by the pinctrl API. They are unused and +unneeded, remove them. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit eb86857362e5c8874c9d7e5c13c95e3dd5908411) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/include/mach/r8a7740.h | 14 -------------- + 1 file changed, 14 deletions(-) + +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h +index 4bec7cd6..cb8e3fb5 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h +@@ -107,20 +107,6 @@ enum { + GPIO_FN_DBGMD10, GPIO_FN_DBGMD11, GPIO_FN_DBGMD20, + GPIO_FN_DBGMD21, + +- /* FSI-A */ +- GPIO_FN_FSIAISLD_PORT0, /* FSIAISLD Port 0/5 */ +- GPIO_FN_FSIAISLD_PORT5, +- GPIO_FN_FSIASPDIF_PORT9, /* FSIASPDIF Port 9/18 */ +- GPIO_FN_FSIASPDIF_PORT18, +- GPIO_FN_FSIAOSLD1, GPIO_FN_FSIAOSLD2, +- GPIO_FN_FSIAOLR, GPIO_FN_FSIAOBT, +- GPIO_FN_FSIAOSLD, GPIO_FN_FSIAOMC, +- GPIO_FN_FSIACK, GPIO_FN_FSIAILR, +- GPIO_FN_FSIAIBT, +- +- /* FSI-B */ +- GPIO_FN_FSIBCK, +- + /* FMSI */ + GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */ + GPIO_FN_FMSISLD_PORT6, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0173-ARM-shmobile-r8a7740-Remove-HDMI-function-GPIOs.patch b/patches.renesas/0173-ARM-shmobile-r8a7740-Remove-HDMI-function-GPIOs.patch new file mode 100644 index 00000000000..3e72f1217d7 --- /dev/null +++ b/patches.renesas/0173-ARM-shmobile-r8a7740-Remove-HDMI-function-GPIOs.patch @@ -0,0 +1,34 @@ +From 02097e4d4ad3e21394ceab53a72546bddfb6fa87 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 18 Apr 2013 01:06:57 +0200 +Subject: ARM: shmobile: r8a7740: Remove HDMI function GPIOs + +Those GPIOs have been deprecated by the pinctrl API. They are unused and +unneeded, remove them. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 7e454d1f26c704413f52050ba67d3144b853faed) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/include/mach/r8a7740.h | 4 ---- + 1 file changed, 4 deletions(-) + +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h +index cb8e3fb5..ed30a1df 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h +@@ -300,10 +300,6 @@ enum { + GPIO_FN_RESETP_PULLUP, + GPIO_FN_RESETP_PLAIN, + +- /* HDMI */ +- GPIO_FN_HDMI_HPD, +- GPIO_FN_HDMI_CEC, +- + /* SDENC */ + GPIO_FN_SDENC_CPG, + GPIO_FN_SDENC_DV_CLKI, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0174-sh-pfc-r8a7740-Remove-function-GPIOs.patch b/patches.renesas/0174-sh-pfc-r8a7740-Remove-function-GPIOs.patch new file mode 100644 index 00000000000..5ff95c42d15 --- /dev/null +++ b/patches.renesas/0174-sh-pfc-r8a7740-Remove-function-GPIOs.patch @@ -0,0 +1,241 @@ +From 69eb33885426025b70c8405873d617888f79f715 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 23 Apr 2013 00:29:23 +0200 +Subject: sh-pfc: r8a7740: Remove function GPIOs + +No r8a7740 platform use the function GPIOs API. Remove it. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d65c5ee14e998dd60aeeedbb037a2d0839e832e5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 205 ----------------------------------- + 1 file changed, 205 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +index fb7a3e8e..9f44fd65 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +@@ -3197,208 +3197,6 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(sdhi2), + }; + +-#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) +- +-static const struct pinmux_func pinmux_func_gpios[] = { +- /* Function */ +- +- /* DBGT */ +- GPIO_FN(DBGMDT2), GPIO_FN(DBGMDT1), GPIO_FN(DBGMDT0), +- GPIO_FN(DBGMD10), GPIO_FN(DBGMD11), GPIO_FN(DBGMD20), +- GPIO_FN(DBGMD21), +- +- /* FMSI */ +- GPIO_FN(FMSISLD_PORT1), /* FMSISLD Port 1/6 */ +- GPIO_FN(FMSISLD_PORT6), +- GPIO_FN(FMSIILR), GPIO_FN(FMSIIBT), GPIO_FN(FMSIOLR), +- GPIO_FN(FMSIOBT), GPIO_FN(FMSICK), GPIO_FN(FMSOILR), +- GPIO_FN(FMSOIBT), GPIO_FN(FMSOOLR), GPIO_FN(FMSOOBT), +- GPIO_FN(FMSOSLD), GPIO_FN(FMSOCK), +- +- /* RSPI */ +- GPIO_FN(RSPI_SSL0_A), GPIO_FN(RSPI_SSL1_A), GPIO_FN(RSPI_SSL2_A), +- GPIO_FN(RSPI_SSL3_A), GPIO_FN(RSPI_CK_A), GPIO_FN(RSPI_MOSI_A), +- GPIO_FN(RSPI_MISO_A), +- +- /* TPU0 */ +- GPIO_FN(TPU0TO0), GPIO_FN(TPU0TO1), GPIO_FN(TPU0TO3), +- GPIO_FN(TPU0TO2_PORT66), /* TPU0TO2 Port 66/202 */ +- GPIO_FN(TPU0TO2_PORT202), +- +- /* SSP1 0 */ +- GPIO_FN(STP0_IPD0), GPIO_FN(STP0_IPD1), GPIO_FN(STP0_IPD2), +- GPIO_FN(STP0_IPD3), GPIO_FN(STP0_IPD4), GPIO_FN(STP0_IPD5), +- GPIO_FN(STP0_IPD6), GPIO_FN(STP0_IPD7), GPIO_FN(STP0_IPEN), +- GPIO_FN(STP0_IPCLK), GPIO_FN(STP0_IPSYNC), +- +- /* SSP1 1 */ +- GPIO_FN(STP1_IPD1), GPIO_FN(STP1_IPD2), GPIO_FN(STP1_IPD3), +- GPIO_FN(STP1_IPD4), GPIO_FN(STP1_IPD5), GPIO_FN(STP1_IPD6), +- GPIO_FN(STP1_IPD7), GPIO_FN(STP1_IPCLK), GPIO_FN(STP1_IPSYNC), +- +- GPIO_FN(STP1_IPD0_PORT186), /* MSEL5CR_23_0 */ +- GPIO_FN(STP1_IPEN_PORT187), +- +- GPIO_FN(STP1_IPD0_PORT194), /* MSEL5CR_23_1 */ +- GPIO_FN(STP1_IPEN_PORT193), +- +- /* SIM */ +- GPIO_FN(SIM_RST), GPIO_FN(SIM_CLK), +- GPIO_FN(SIM_D_PORT22), /* SIM_D Port 22/199 */ +- GPIO_FN(SIM_D_PORT199), +- +- /* MSIOF2 */ +- GPIO_FN(MSIOF2_TXD), GPIO_FN(MSIOF2_RXD), GPIO_FN(MSIOF2_TSCK), +- GPIO_FN(MSIOF2_SS2), GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_SS1), +- GPIO_FN(MSIOF2_MCK1), GPIO_FN(MSIOF2_MCK0), GPIO_FN(MSIOF2_RSYNC), +- GPIO_FN(MSIOF2_RSCK), +- +- /* KEYSC */ +- GPIO_FN(KEYIN4), GPIO_FN(KEYIN5), +- GPIO_FN(KEYIN6), GPIO_FN(KEYIN7), +- GPIO_FN(KEYOUT0), GPIO_FN(KEYOUT1), GPIO_FN(KEYOUT2), +- GPIO_FN(KEYOUT3), GPIO_FN(KEYOUT4), GPIO_FN(KEYOUT5), +- GPIO_FN(KEYOUT6), GPIO_FN(KEYOUT7), +- +- GPIO_FN(KEYIN0_PORT43), /* MSEL4CR_18_0 */ +- GPIO_FN(KEYIN1_PORT44), +- GPIO_FN(KEYIN2_PORT45), +- GPIO_FN(KEYIN3_PORT46), +- +- GPIO_FN(KEYIN0_PORT58), /* MSEL4CR_18_1 */ +- GPIO_FN(KEYIN1_PORT57), +- GPIO_FN(KEYIN2_PORT56), +- GPIO_FN(KEYIN3_PORT55), +- +- /* VOU */ +- GPIO_FN(DV_D0), GPIO_FN(DV_D1), GPIO_FN(DV_D2), +- GPIO_FN(DV_D3), GPIO_FN(DV_D4), GPIO_FN(DV_D5), +- GPIO_FN(DV_D6), GPIO_FN(DV_D7), GPIO_FN(DV_D8), +- GPIO_FN(DV_D9), GPIO_FN(DV_D10), GPIO_FN(DV_D11), +- GPIO_FN(DV_D12), GPIO_FN(DV_D13), GPIO_FN(DV_D14), +- GPIO_FN(DV_D15), GPIO_FN(DV_CLK), +- GPIO_FN(DV_VSYNC), GPIO_FN(DV_HSYNC), +- +- /* MEMC */ +- GPIO_FN(MEMC_AD0), GPIO_FN(MEMC_AD1), GPIO_FN(MEMC_AD2), +- GPIO_FN(MEMC_AD3), GPIO_FN(MEMC_AD4), GPIO_FN(MEMC_AD5), +- GPIO_FN(MEMC_AD6), GPIO_FN(MEMC_AD7), GPIO_FN(MEMC_AD8), +- GPIO_FN(MEMC_AD9), GPIO_FN(MEMC_AD10), GPIO_FN(MEMC_AD11), +- GPIO_FN(MEMC_AD12), GPIO_FN(MEMC_AD13), GPIO_FN(MEMC_AD14), +- GPIO_FN(MEMC_AD15), GPIO_FN(MEMC_CS0), GPIO_FN(MEMC_INT), +- GPIO_FN(MEMC_NWE), GPIO_FN(MEMC_NOE), GPIO_FN(MEMC_CS1), +- GPIO_FN(MEMC_A1), GPIO_FN(MEMC_ADV), GPIO_FN(MEMC_DREQ0), +- GPIO_FN(MEMC_WAIT), GPIO_FN(MEMC_DREQ1), GPIO_FN(MEMC_BUSCLK), +- GPIO_FN(MEMC_A0), +- +- /* MSIOF0 */ +- GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), GPIO_FN(MSIOF0_RXD), +- GPIO_FN(MSIOF0_TXD), GPIO_FN(MSIOF0_MCK0), GPIO_FN(MSIOF0_MCK1), +- GPIO_FN(MSIOF0_RSYNC), GPIO_FN(MSIOF0_RSCK), GPIO_FN(MSIOF0_TSCK), +- GPIO_FN(MSIOF0_TSYNC), +- +- /* MSIOF1 */ +- GPIO_FN(MSIOF1_RSCK), GPIO_FN(MSIOF1_RSYNC), +- GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1), +- +- GPIO_FN(MSIOF1_SS2_PORT116), GPIO_FN(MSIOF1_SS1_PORT117), +- GPIO_FN(MSIOF1_RXD_PORT118), GPIO_FN(MSIOF1_TXD_PORT119), +- GPIO_FN(MSIOF1_TSYNC_PORT120), +- GPIO_FN(MSIOF1_TSCK_PORT121), /* MSEL4CR_10_0 */ +- +- GPIO_FN(MSIOF1_SS1_PORT67), GPIO_FN(MSIOF1_TSCK_PORT72), +- GPIO_FN(MSIOF1_TSYNC_PORT73), GPIO_FN(MSIOF1_TXD_PORT74), +- GPIO_FN(MSIOF1_RXD_PORT75), +- GPIO_FN(MSIOF1_SS2_PORT202), /* MSEL4CR_10_1 */ +- +- /* GPIO */ +- GPIO_FN(GPO0), GPIO_FN(GPI0), +- GPIO_FN(GPO1), GPIO_FN(GPI1), +- +- /* USB0 */ +- GPIO_FN(USB0_OCI), GPIO_FN(USB0_PPON), GPIO_FN(VBUS), +- +- /* USB1 */ +- GPIO_FN(USB1_OCI), GPIO_FN(USB1_PPON), +- +- /* BBIF1 */ +- GPIO_FN(BBIF1_RXD), GPIO_FN(BBIF1_TXD), GPIO_FN(BBIF1_TSYNC), +- GPIO_FN(BBIF1_TSCK), GPIO_FN(BBIF1_RSCK), GPIO_FN(BBIF1_RSYNC), +- GPIO_FN(BBIF1_FLOW), GPIO_FN(BBIF1_RX_FLOW_N), +- +- /* BBIF2 */ +- GPIO_FN(BBIF2_TXD2_PORT5), /* MSEL5CR_0_0 */ +- GPIO_FN(BBIF2_RXD2_PORT60), +- GPIO_FN(BBIF2_TSYNC2_PORT6), +- GPIO_FN(BBIF2_TSCK2_PORT59), +- +- GPIO_FN(BBIF2_RXD2_PORT90), /* MSEL5CR_0_1 */ +- GPIO_FN(BBIF2_TXD2_PORT183), +- GPIO_FN(BBIF2_TSCK2_PORT89), +- GPIO_FN(BBIF2_TSYNC2_PORT184), +- +- /* FLCTL / PCMCIA */ +- GPIO_FN(IOIS16), /* ? */ +- +- GPIO_FN(A0), GPIO_FN(A1), GPIO_FN(A2), GPIO_FN(A3), +- GPIO_FN(A4_FOE), GPIO_FN(A5_FCDE), /* share with FLCTL */ +- GPIO_FN(A6), GPIO_FN(A7), GPIO_FN(A8), GPIO_FN(A9), +- GPIO_FN(A10), GPIO_FN(A11), GPIO_FN(A12), GPIO_FN(A13), +- GPIO_FN(A14), GPIO_FN(A15), GPIO_FN(A16), GPIO_FN(A17), +- GPIO_FN(A18), GPIO_FN(A19), GPIO_FN(A20), GPIO_FN(A21), +- GPIO_FN(A22), GPIO_FN(A23), GPIO_FN(A24), GPIO_FN(A25), +- GPIO_FN(A26), +- +- GPIO_FN(CKO), +- GPIO_FN(WAIT_PORT177), /* WAIT Port 90/177 */ +- GPIO_FN(WAIT_PORT90), +- +- GPIO_FN(FCE0), GPIO_FN(FCE1), GPIO_FN(FRB), /* FLCTL */ +- +- /* IRDA */ +- GPIO_FN(IRDA_FIRSEL), GPIO_FN(IRDA_IN), GPIO_FN(IRDA_OUT), +- +- /* ATAPI */ +- GPIO_FN(IDE_D0), GPIO_FN(IDE_D1), GPIO_FN(IDE_D2), +- GPIO_FN(IDE_D3), GPIO_FN(IDE_D4), GPIO_FN(IDE_D5), +- GPIO_FN(IDE_D6), GPIO_FN(IDE_D7), GPIO_FN(IDE_D8), +- GPIO_FN(IDE_D9), GPIO_FN(IDE_D10), GPIO_FN(IDE_D11), +- GPIO_FN(IDE_D12), GPIO_FN(IDE_D13), GPIO_FN(IDE_D14), +- GPIO_FN(IDE_D15), GPIO_FN(IDE_A0), GPIO_FN(IDE_A1), +- GPIO_FN(IDE_A2), GPIO_FN(IDE_CS0), GPIO_FN(IDE_CS1), +- GPIO_FN(IDE_IOWR), GPIO_FN(IDE_IORD), GPIO_FN(IDE_IORDY), +- GPIO_FN(IDE_INT), GPIO_FN(IDE_RST), GPIO_FN(IDE_DIRECTION), +- GPIO_FN(IDE_EXBUF_ENB), GPIO_FN(IDE_IODACK), GPIO_FN(IDE_IODREQ), +- +- /* DMA0 */ +- GPIO_FN(DREQ0), GPIO_FN(DACK0), +- +- /* DMA1 */ +- GPIO_FN(DREQ1), GPIO_FN(DACK1), +- +- /* SYSC */ +- GPIO_FN(RESETOUTS), +- +- /* IRREM */ +- GPIO_FN(IROUT), +- +- /* SDENC */ +- GPIO_FN(SDENC_CPG), +- GPIO_FN(SDENC_DV_CLKI), +- +- /* SYSC */ +- GPIO_FN(RESETP_PULLUP), +- GPIO_FN(RESETP_PLAIN), +- +- /* DEBUG */ +- GPIO_FN(EDEBGREQ_PULLDOWN), +- GPIO_FN(EDEBGREQ_PULLUP), +- +- GPIO_FN(TRACEAUD_FROM_VIO), +- GPIO_FN(TRACEAUD_FROM_LCDC0), +- GPIO_FN(TRACEAUD_FROM_MEMC), +-}; +- + static const struct pinmux_cfg_reg pinmux_config_regs[] = { + PORTCR(0, 0xe6050000), /* PORT0CR */ + PORTCR(1, 0xe6050001), /* PORT1CR */ +@@ -3872,9 +3670,6 @@ const struct sh_pfc_soc_info r8a7740_pinmux_info = { + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + +- .func_gpios = pinmux_func_gpios, +- .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), +- + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0175-sh-pfc-r8a7740-Replace-GPIO_PORTx-enum-with-GPIO-por.patch b/patches.renesas/0175-sh-pfc-r8a7740-Replace-GPIO_PORTx-enum-with-GPIO-por.patch new file mode 100644 index 00000000000..62a9743f8ea --- /dev/null +++ b/patches.renesas/0175-sh-pfc-r8a7740-Replace-GPIO_PORTx-enum-with-GPIO-por.patch @@ -0,0 +1,109 @@ +From 71b027d9ed545b5acad88a03381f13e32a7fc442 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 23 Apr 2013 00:36:40 +0200 +Subject: sh-pfc: r8a7740: Replace GPIO_PORTx enum with GPIO port numbers + +The PFC GPIO API implementation moved to using port numbers. Replace all +GPIO_PORTx enum usage with the corresponding port number. The GPIO_PORTx +enum values are identical to the port number on this platform. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 7d5684575c1729952effc6b285eb74d2009839c5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 71 ++++++++++++++++++++---------------- + 1 file changed, 39 insertions(+), 32 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +index 9f44fd65..6af8fae4 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +@@ -30,6 +30,13 @@ + PORT_10(fn, pfx##20, sfx), \ + PORT_1(fn, pfx##210, sfx), PORT_1(fn, pfx##211, sfx) + ++#undef _GPIO_PORT ++#define _GPIO_PORT(gpio, sfx) \ ++ [gpio] = { \ ++ .name = __stringify(PORT##gpio), \ ++ .enum_id = PORT##gpio##_DATA, \ ++ } ++ + #define IRQC_PIN_MUX(irq, pin) \ + static const unsigned int intc_irq##irq##_pins[] = { \ + pin, \ +@@ -3616,38 +3623,38 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { + }; + + static const struct pinmux_irq pinmux_irqs[] = { +- PINMUX_IRQ(irq_pin(0), GPIO_PORT2, GPIO_PORT13), /* IRQ0A */ +- PINMUX_IRQ(irq_pin(1), GPIO_PORT20), /* IRQ1A */ +- PINMUX_IRQ(irq_pin(2), GPIO_PORT11, GPIO_PORT12), /* IRQ2A */ +- PINMUX_IRQ(irq_pin(3), GPIO_PORT10, GPIO_PORT14), /* IRQ3A */ +- PINMUX_IRQ(irq_pin(4), GPIO_PORT15, GPIO_PORT172),/* IRQ4A */ +- PINMUX_IRQ(irq_pin(5), GPIO_PORT0, GPIO_PORT1), /* IRQ5A */ +- PINMUX_IRQ(irq_pin(6), GPIO_PORT121, GPIO_PORT173),/* IRQ6A */ +- PINMUX_IRQ(irq_pin(7), GPIO_PORT120, GPIO_PORT209),/* IRQ7A */ +- PINMUX_IRQ(irq_pin(8), GPIO_PORT119), /* IRQ8A */ +- PINMUX_IRQ(irq_pin(9), GPIO_PORT118, GPIO_PORT210),/* IRQ9A */ +- PINMUX_IRQ(irq_pin(10), GPIO_PORT19), /* IRQ10A */ +- PINMUX_IRQ(irq_pin(11), GPIO_PORT104), /* IRQ11A */ +- PINMUX_IRQ(irq_pin(12), GPIO_PORT42, GPIO_PORT97), /* IRQ12A */ +- PINMUX_IRQ(irq_pin(13), GPIO_PORT64, GPIO_PORT98), /* IRQ13A */ +- PINMUX_IRQ(irq_pin(14), GPIO_PORT63, GPIO_PORT99), /* IRQ14A */ +- PINMUX_IRQ(irq_pin(15), GPIO_PORT62, GPIO_PORT100),/* IRQ15A */ +- PINMUX_IRQ(irq_pin(16), GPIO_PORT68, GPIO_PORT211),/* IRQ16A */ +- PINMUX_IRQ(irq_pin(17), GPIO_PORT69), /* IRQ17A */ +- PINMUX_IRQ(irq_pin(18), GPIO_PORT70), /* IRQ18A */ +- PINMUX_IRQ(irq_pin(19), GPIO_PORT71), /* IRQ19A */ +- PINMUX_IRQ(irq_pin(20), GPIO_PORT67), /* IRQ20A */ +- PINMUX_IRQ(irq_pin(21), GPIO_PORT202), /* IRQ21A */ +- PINMUX_IRQ(irq_pin(22), GPIO_PORT95), /* IRQ22A */ +- PINMUX_IRQ(irq_pin(23), GPIO_PORT96), /* IRQ23A */ +- PINMUX_IRQ(irq_pin(24), GPIO_PORT180), /* IRQ24A */ +- PINMUX_IRQ(irq_pin(25), GPIO_PORT38), /* IRQ25A */ +- PINMUX_IRQ(irq_pin(26), GPIO_PORT58, GPIO_PORT81), /* IRQ26A */ +- PINMUX_IRQ(irq_pin(27), GPIO_PORT57, GPIO_PORT168),/* IRQ27A */ +- PINMUX_IRQ(irq_pin(28), GPIO_PORT56, GPIO_PORT169),/* IRQ28A */ +- PINMUX_IRQ(irq_pin(29), GPIO_PORT50, GPIO_PORT170),/* IRQ29A */ +- PINMUX_IRQ(irq_pin(30), GPIO_PORT49, GPIO_PORT171),/* IRQ30A */ +- PINMUX_IRQ(irq_pin(31), GPIO_PORT41, GPIO_PORT167),/* IRQ31A */ ++ PINMUX_IRQ(irq_pin(0), 2, 13), /* IRQ0A */ ++ PINMUX_IRQ(irq_pin(1), 20), /* IRQ1A */ ++ PINMUX_IRQ(irq_pin(2), 11, 12), /* IRQ2A */ ++ PINMUX_IRQ(irq_pin(3), 10, 14), /* IRQ3A */ ++ PINMUX_IRQ(irq_pin(4), 15, 172), /* IRQ4A */ ++ PINMUX_IRQ(irq_pin(5), 0, 1), /* IRQ5A */ ++ PINMUX_IRQ(irq_pin(6), 121, 173), /* IRQ6A */ ++ PINMUX_IRQ(irq_pin(7), 120, 209), /* IRQ7A */ ++ PINMUX_IRQ(irq_pin(8), 119), /* IRQ8A */ ++ PINMUX_IRQ(irq_pin(9), 118, 210), /* IRQ9A */ ++ PINMUX_IRQ(irq_pin(10), 19), /* IRQ10A */ ++ PINMUX_IRQ(irq_pin(11), 104), /* IRQ11A */ ++ PINMUX_IRQ(irq_pin(12), 42, 97), /* IRQ12A */ ++ PINMUX_IRQ(irq_pin(13), 64, 98), /* IRQ13A */ ++ PINMUX_IRQ(irq_pin(14), 63, 99), /* IRQ14A */ ++ PINMUX_IRQ(irq_pin(15), 62, 100), /* IRQ15A */ ++ PINMUX_IRQ(irq_pin(16), 68, 211), /* IRQ16A */ ++ PINMUX_IRQ(irq_pin(17), 69), /* IRQ17A */ ++ PINMUX_IRQ(irq_pin(18), 70), /* IRQ18A */ ++ PINMUX_IRQ(irq_pin(19), 71), /* IRQ19A */ ++ PINMUX_IRQ(irq_pin(20), 67), /* IRQ20A */ ++ PINMUX_IRQ(irq_pin(21), 202), /* IRQ21A */ ++ PINMUX_IRQ(irq_pin(22), 95), /* IRQ22A */ ++ PINMUX_IRQ(irq_pin(23), 96), /* IRQ23A */ ++ PINMUX_IRQ(irq_pin(24), 180), /* IRQ24A */ ++ PINMUX_IRQ(irq_pin(25), 38), /* IRQ25A */ ++ PINMUX_IRQ(irq_pin(26), 58, 81), /* IRQ26A */ ++ PINMUX_IRQ(irq_pin(27), 57, 168), /* IRQ27A */ ++ PINMUX_IRQ(irq_pin(28), 56, 169), /* IRQ28A */ ++ PINMUX_IRQ(irq_pin(29), 50, 170), /* IRQ29A */ ++ PINMUX_IRQ(irq_pin(30), 49, 171), /* IRQ30A */ ++ PINMUX_IRQ(irq_pin(31), 41, 167), /* IRQ31A */ + }; + + const struct sh_pfc_soc_info r8a7740_pinmux_info = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0176-ARM-shmobile-r8a7740-Remove-all-GPIOs.patch b/patches.renesas/0176-ARM-shmobile-r8a7740-Remove-all-GPIOs.patch new file mode 100644 index 00000000000..f3ac11c6a5d --- /dev/null +++ b/patches.renesas/0176-ARM-shmobile-r8a7740-Remove-all-GPIOs.patch @@ -0,0 +1,318 @@ +From e2afc729649a033ef61bb668eb6210a725600555 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 23 Apr 2013 00:30:05 +0200 +Subject: ARM: shmobile: r8a7740: Remove all GPIOs + +Function GPIOs are not used anymore, and all code use the GPIO numbers +directly. Remove the GPIOs enumeration. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit f92e1360b425ff585619aadabfd7da40f2305ad4) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/include/mach/r8a7740.h | 288 -------------------------- + 1 file changed, 288 deletions(-) + +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h +index ed30a1df..b34d19b5 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h +@@ -28,294 +28,6 @@ + #define MD_CK1 (1 << 1) + #define MD_CK0 (1 << 0) + +-/* +- * Pin Function Controller: +- * GPIO_FN_xx - GPIO used to select pin function +- * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU +- */ +-enum { +- /* PORT */ +- GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4, +- GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9, +- +- GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14, +- GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19, +- +- GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24, +- GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29, +- +- GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34, +- GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39, +- +- GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44, +- GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49, +- +- GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54, +- GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59, +- +- GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64, +- GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69, +- +- GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74, +- GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79, +- +- GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84, +- GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89, +- +- GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94, +- GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99, +- +- GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104, +- GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109, +- +- GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114, +- GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119, +- +- GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124, +- GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129, +- +- GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134, +- GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139, +- +- GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144, +- GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149, +- +- GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154, +- GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159, +- +- GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164, +- GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169, +- +- GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174, +- GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179, +- +- GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184, +- GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189, +- +- GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194, +- GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199, +- +- GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204, +- GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209, +- +- GPIO_PORT210, GPIO_PORT211, +- +- /* Function */ +- +- /* DBGT */ +- GPIO_FN_DBGMDT2, GPIO_FN_DBGMDT1, GPIO_FN_DBGMDT0, +- GPIO_FN_DBGMD10, GPIO_FN_DBGMD11, GPIO_FN_DBGMD20, +- GPIO_FN_DBGMD21, +- +- /* FMSI */ +- GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */ +- GPIO_FN_FMSISLD_PORT6, +- GPIO_FN_FMSIILR, GPIO_FN_FMSIIBT, +- GPIO_FN_FMSIOLR, GPIO_FN_FMSIOBT, +- GPIO_FN_FMSICK, GPIO_FN_FMSOILR, +- GPIO_FN_FMSOIBT, GPIO_FN_FMSOOLR, +- GPIO_FN_FMSOOBT, GPIO_FN_FMSOSLD, +- GPIO_FN_FMSOCK, +- +- /* LCD0 */ +- GPIO_FN_LCDC0_SELECT, +- +- /* LCD1 */ +- GPIO_FN_LCDC1_SELECT, +- +- /* RSPI */ +- GPIO_FN_RSPI_SSL0_A, GPIO_FN_RSPI_SSL1_A, +- GPIO_FN_RSPI_SSL2_A, GPIO_FN_RSPI_SSL3_A, +- GPIO_FN_RSPI_MOSI_A, GPIO_FN_RSPI_MISO_A, +- GPIO_FN_RSPI_CK_A, +- +- /* TPU0 */ +- GPIO_FN_TPU0TO0, GPIO_FN_TPU0TO1, +- GPIO_FN_TPU0TO3, +- GPIO_FN_TPU0TO2_PORT66, /* TPU0TO2 Port 66/202 */ +- GPIO_FN_TPU0TO2_PORT202, +- +- /* SSP1 0 */ +- GPIO_FN_STP0_IPD0, GPIO_FN_STP0_IPD1, GPIO_FN_STP0_IPD2, +- GPIO_FN_STP0_IPD3, GPIO_FN_STP0_IPD4, GPIO_FN_STP0_IPD5, +- GPIO_FN_STP0_IPD6, GPIO_FN_STP0_IPD7, GPIO_FN_STP0_IPEN, +- GPIO_FN_STP0_IPCLK, GPIO_FN_STP0_IPSYNC, +- +- /* SSP1 1 */ +- GPIO_FN_STP1_IPD1, GPIO_FN_STP1_IPD2, GPIO_FN_STP1_IPD3, +- GPIO_FN_STP1_IPD4, GPIO_FN_STP1_IPD5, GPIO_FN_STP1_IPD6, +- GPIO_FN_STP1_IPD7, GPIO_FN_STP1_IPCLK, GPIO_FN_STP1_IPSYNC, +- +- GPIO_FN_STP1_IPD0_PORT186, /* MSEL5CR_23_0 */ +- GPIO_FN_STP1_IPEN_PORT187, +- +- GPIO_FN_STP1_IPD0_PORT194, /* MSEL5CR_23_1 */ +- GPIO_FN_STP1_IPEN_PORT193, +- +- /* SIM */ +- GPIO_FN_SIM_RST, GPIO_FN_SIM_CLK, +- GPIO_FN_SIM_D_PORT22, /* SIM_D Port 22/199 */ +- GPIO_FN_SIM_D_PORT199, +- +- /* MSIOF2 */ +- GPIO_FN_MSIOF2_TXD, GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TSCK, +- GPIO_FN_MSIOF2_SS2, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_SS1, +- GPIO_FN_MSIOF2_MCK1, GPIO_FN_MSIOF2_MCK0, GPIO_FN_MSIOF2_RSYNC, +- GPIO_FN_MSIOF2_RSCK, +- +- /* KEYSC */ +- GPIO_FN_KEYIN4, GPIO_FN_KEYIN5, +- GPIO_FN_KEYIN6, GPIO_FN_KEYIN7, +- GPIO_FN_KEYOUT0, GPIO_FN_KEYOUT1, GPIO_FN_KEYOUT2, +- GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT4, GPIO_FN_KEYOUT5, +- GPIO_FN_KEYOUT6, GPIO_FN_KEYOUT7, +- +- GPIO_FN_KEYIN0_PORT43, /* MSEL4CR_18_0 */ +- GPIO_FN_KEYIN1_PORT44, +- GPIO_FN_KEYIN2_PORT45, +- GPIO_FN_KEYIN3_PORT46, +- +- GPIO_FN_KEYIN0_PORT58, /* MSEL4CR_18_1 */ +- GPIO_FN_KEYIN1_PORT57, +- GPIO_FN_KEYIN2_PORT56, +- GPIO_FN_KEYIN3_PORT55, +- +- /* VOU */ +- GPIO_FN_DV_D0, GPIO_FN_DV_D1, GPIO_FN_DV_D2, GPIO_FN_DV_D3, +- GPIO_FN_DV_D4, GPIO_FN_DV_D5, GPIO_FN_DV_D6, GPIO_FN_DV_D7, +- GPIO_FN_DV_D8, GPIO_FN_DV_D9, GPIO_FN_DV_D10, GPIO_FN_DV_D11, +- GPIO_FN_DV_D12, GPIO_FN_DV_D13, GPIO_FN_DV_D14, GPIO_FN_DV_D15, +- GPIO_FN_DV_CLK, +- GPIO_FN_DV_VSYNC, +- GPIO_FN_DV_HSYNC, +- +- /* MEMC */ +- GPIO_FN_MEMC_AD0, GPIO_FN_MEMC_AD1, GPIO_FN_MEMC_AD2, +- GPIO_FN_MEMC_AD3, GPIO_FN_MEMC_AD4, GPIO_FN_MEMC_AD5, +- GPIO_FN_MEMC_AD6, GPIO_FN_MEMC_AD7, GPIO_FN_MEMC_AD8, +- GPIO_FN_MEMC_AD9, GPIO_FN_MEMC_AD10, GPIO_FN_MEMC_AD11, +- GPIO_FN_MEMC_AD12, GPIO_FN_MEMC_AD13, GPIO_FN_MEMC_AD14, +- GPIO_FN_MEMC_AD15, GPIO_FN_MEMC_CS0, GPIO_FN_MEMC_INT, +- GPIO_FN_MEMC_NWE, GPIO_FN_MEMC_NOE, +- +- GPIO_FN_MEMC_CS1, /* MSEL4CR_6_0 */ +- GPIO_FN_MEMC_ADV, +- GPIO_FN_MEMC_WAIT, +- GPIO_FN_MEMC_BUSCLK, +- +- GPIO_FN_MEMC_A1, /* MSEL4CR_6_1 */ +- GPIO_FN_MEMC_DREQ0, +- GPIO_FN_MEMC_DREQ1, +- GPIO_FN_MEMC_A0, +- +- /* MSIOF0 */ +- GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2, +- GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD, +- GPIO_FN_MSIOF0_MCK0, GPIO_FN_MSIOF0_MCK1, +- GPIO_FN_MSIOF0_RSYNC, GPIO_FN_MSIOF0_RSCK, +- GPIO_FN_MSIOF0_TSCK, GPIO_FN_MSIOF0_TSYNC, +- +- /* MSIOF1 */ +- GPIO_FN_MSIOF1_RSCK, GPIO_FN_MSIOF1_RSYNC, +- GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1, +- +- GPIO_FN_MSIOF1_SS2_PORT116, GPIO_FN_MSIOF1_SS1_PORT117, +- GPIO_FN_MSIOF1_RXD_PORT118, GPIO_FN_MSIOF1_TXD_PORT119, +- GPIO_FN_MSIOF1_TSYNC_PORT120, +- GPIO_FN_MSIOF1_TSCK_PORT121, /* MSEL4CR_10_0 */ +- +- GPIO_FN_MSIOF1_SS1_PORT67, GPIO_FN_MSIOF1_TSCK_PORT72, +- GPIO_FN_MSIOF1_TSYNC_PORT73, GPIO_FN_MSIOF1_TXD_PORT74, +- GPIO_FN_MSIOF1_RXD_PORT75, +- GPIO_FN_MSIOF1_SS2_PORT202, /* MSEL4CR_10_1 */ +- +- /* GPIO */ +- GPIO_FN_GPO0, GPIO_FN_GPI0, +- GPIO_FN_GPO1, GPIO_FN_GPI1, +- +- /* USB0 */ +- GPIO_FN_USB0_OCI, GPIO_FN_USB0_PPON, GPIO_FN_VBUS, +- +- /* USB1 */ +- GPIO_FN_USB1_OCI, GPIO_FN_USB1_PPON, +- +- /* BBIF1 */ +- GPIO_FN_BBIF1_RXD, GPIO_FN_BBIF1_TXD, GPIO_FN_BBIF1_TSYNC, +- GPIO_FN_BBIF1_TSCK, GPIO_FN_BBIF1_RSCK, GPIO_FN_BBIF1_RSYNC, +- GPIO_FN_BBIF1_FLOW, GPIO_FN_BBIF1_RX_FLOW_N, +- +- /* BBIF2 */ +- GPIO_FN_BBIF2_TXD2_PORT5, /* MSEL5CR_0_0 */ +- GPIO_FN_BBIF2_RXD2_PORT60, +- GPIO_FN_BBIF2_TSYNC2_PORT6, +- GPIO_FN_BBIF2_TSCK2_PORT59, +- +- GPIO_FN_BBIF2_RXD2_PORT90, /* MSEL5CR_0_1 */ +- GPIO_FN_BBIF2_TXD2_PORT183, +- GPIO_FN_BBIF2_TSCK2_PORT89, +- GPIO_FN_BBIF2_TSYNC2_PORT184, +- +- /* FLCTL / PCMCIA */ +- GPIO_FN_IOIS16, /* ? */ +- +- GPIO_FN_A0, GPIO_FN_A1, GPIO_FN_A2, GPIO_FN_A3, +- GPIO_FN_A4_FOE, /* share with FLCTL */ +- GPIO_FN_A5_FCDE, /* share with FLCTL */ +- GPIO_FN_A6, GPIO_FN_A7, GPIO_FN_A8, GPIO_FN_A9, +- GPIO_FN_A10, GPIO_FN_A11, GPIO_FN_A12, GPIO_FN_A13, +- GPIO_FN_A14, GPIO_FN_A15, GPIO_FN_A16, GPIO_FN_A17, +- GPIO_FN_A18, GPIO_FN_A19, GPIO_FN_A20, GPIO_FN_A21, +- GPIO_FN_A22, GPIO_FN_A23, GPIO_FN_A24, GPIO_FN_A25, +- GPIO_FN_A26, +- +- GPIO_FN_CKO, +- GPIO_FN_WAIT_PORT177, /* WAIT Port 90/177 */ +- GPIO_FN_WAIT_PORT90, +- +- GPIO_FN_FCE0, GPIO_FN_FCE1, GPIO_FN_FRB, /* FLCTL */ +- +- /* IRDA */ +- GPIO_FN_IRDA_FIRSEL, GPIO_FN_IRDA_IN, GPIO_FN_IRDA_OUT, +- +- /* ATAPI */ +- GPIO_FN_IDE_D0, GPIO_FN_IDE_D1, GPIO_FN_IDE_D2, +- GPIO_FN_IDE_D3, GPIO_FN_IDE_D4, GPIO_FN_IDE_D5, +- GPIO_FN_IDE_D6, GPIO_FN_IDE_D7, GPIO_FN_IDE_D8, +- GPIO_FN_IDE_D9, GPIO_FN_IDE_D10, GPIO_FN_IDE_D11, +- GPIO_FN_IDE_D12, GPIO_FN_IDE_D13, GPIO_FN_IDE_D14, +- GPIO_FN_IDE_D15, GPIO_FN_IDE_A0, GPIO_FN_IDE_A1, +- GPIO_FN_IDE_A2, GPIO_FN_IDE_CS0, GPIO_FN_IDE_CS1, +- GPIO_FN_IDE_IOWR, GPIO_FN_IDE_IORD, GPIO_FN_IDE_IORDY, +- GPIO_FN_IDE_INT, GPIO_FN_IDE_RST, GPIO_FN_IDE_DIRECTION, +- GPIO_FN_IDE_EXBUF_ENB, GPIO_FN_IDE_IODACK, GPIO_FN_IDE_IODREQ, +- +- /* DMA0 */ +- GPIO_FN_DREQ0, GPIO_FN_DACK0, +- +- /* DMA1 */ +- GPIO_FN_DREQ1, GPIO_FN_DACK1, +- +- /* SYSC */ +- GPIO_FN_RESETOUTS, +- GPIO_FN_RESETP_PULLUP, +- GPIO_FN_RESETP_PLAIN, +- +- /* SDENC */ +- GPIO_FN_SDENC_CPG, +- GPIO_FN_SDENC_DV_CLKI, +- +- /* IRREM */ +- GPIO_FN_IROUT, +- +- /* DEBUG */ +- GPIO_FN_EDEBGREQ_PULLDOWN, +- GPIO_FN_EDEBGREQ_PULLUP, +- +- GPIO_FN_TRACEAUD_FROM_VIO, +- GPIO_FN_TRACEAUD_FROM_LCDC0, +- GPIO_FN_TRACEAUD_FROM_MEMC, +-}; +- + /* DMA slave IDs */ + enum { + SHDMA_SLAVE_INVALID, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0177-sh-pfc-r8a7740-Add-bias-pull-up-down-pinconf-support.patch b/patches.renesas/0177-sh-pfc-r8a7740-Add-bias-pull-up-down-pinconf-support.patch new file mode 100644 index 00000000000..1b6327225f5 --- /dev/null +++ b/patches.renesas/0177-sh-pfc-r8a7740-Add-bias-pull-up-down-pinconf-support.patch @@ -0,0 +1,437 @@ +From 3484bc204064e0e85e16f643dabcb39624484cef Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 23 Apr 2013 14:24:19 +0200 +Subject: sh-pfc: r8a7740: Add bias (pull-up/down) pinconf support + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 80da8e02d22caaef78a91f3834ed92455f19088b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 365 +++++++++++++++++++++-------------- + 1 file changed, 220 insertions(+), 145 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +index 6af8fae4..e5ef587a 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +@@ -18,10 +18,14 @@ + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ ++#include <linux/io.h> + #include <linux/kernel.h> ++#include <linux/pinctrl/pinconf-generic.h> ++ + #include <mach/r8a7740.h> + #include <mach/irqs.h> + ++#include "core.h" + #include "sh_pfc.h" + + #define CPU_ALL_PORT(fn, pfx, sfx) \ +@@ -66,16 +70,6 @@ enum { + PORT_ALL(IN), + PINMUX_INPUT_END, + +- /* PORT0_IN_PU -> PORT211_IN_PU */ +- PINMUX_INPUT_PULLUP_BEGIN, +- PORT_ALL(IN_PU), +- PINMUX_INPUT_PULLUP_END, +- +- /* PORT0_IN_PD -> PORT211_IN_PD */ +- PINMUX_INPUT_PULLDOWN_BEGIN, +- PORT_ALL(IN_PD), +- PINMUX_INPUT_PULLDOWN_END, +- + /* PORT0_OUT -> PORT211_OUT */ + PINMUX_OUTPUT_BEGIN, + PORT_ALL(OUT), +@@ -596,137 +590,11 @@ enum { + PINMUX_MARK_END, + }; + ++#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx) ++#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) ++ + static const pinmux_enum_t pinmux_data[] = { +- /* specify valid pin states for each pin in GPIO mode */ +- +- /* I/O and Pull U/D */ +- PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1), +- PORT_DATA_IO_PD(2), PORT_DATA_IO_PD(3), +- PORT_DATA_IO_PD(4), PORT_DATA_IO_PD(5), +- PORT_DATA_IO_PD(6), PORT_DATA_IO(7), +- PORT_DATA_IO(8), PORT_DATA_IO(9), +- +- PORT_DATA_IO_PD(10), PORT_DATA_IO_PD(11), +- PORT_DATA_IO_PD(12), PORT_DATA_IO_PU_PD(13), +- PORT_DATA_IO_PD(14), PORT_DATA_IO_PD(15), +- PORT_DATA_IO_PD(16), PORT_DATA_IO_PD(17), +- PORT_DATA_IO(18), PORT_DATA_IO_PU(19), +- +- PORT_DATA_IO_PU_PD(20), PORT_DATA_IO_PD(21), +- PORT_DATA_IO_PU_PD(22), PORT_DATA_IO(23), +- PORT_DATA_IO_PU(24), PORT_DATA_IO_PU(25), +- PORT_DATA_IO_PU(26), PORT_DATA_IO_PU(27), +- PORT_DATA_IO_PU(28), PORT_DATA_IO_PU(29), +- +- PORT_DATA_IO_PU(30), PORT_DATA_IO_PD(31), +- PORT_DATA_IO_PD(32), PORT_DATA_IO_PD(33), +- PORT_DATA_IO_PD(34), PORT_DATA_IO_PU(35), +- PORT_DATA_IO_PU(36), PORT_DATA_IO_PD(37), +- PORT_DATA_IO_PU(38), PORT_DATA_IO_PD(39), +- +- PORT_DATA_IO_PU_PD(40), PORT_DATA_IO_PD(41), +- PORT_DATA_IO_PD(42), PORT_DATA_IO_PU_PD(43), +- PORT_DATA_IO_PU_PD(44), PORT_DATA_IO_PU_PD(45), +- PORT_DATA_IO_PU_PD(46), PORT_DATA_IO_PU_PD(47), +- PORT_DATA_IO_PU_PD(48), PORT_DATA_IO_PU_PD(49), +- +- PORT_DATA_IO_PU_PD(50), PORT_DATA_IO_PD(51), +- PORT_DATA_IO_PD(52), PORT_DATA_IO_PD(53), +- PORT_DATA_IO_PD(54), PORT_DATA_IO_PU_PD(55), +- PORT_DATA_IO_PU_PD(56), PORT_DATA_IO_PU_PD(57), +- PORT_DATA_IO_PU_PD(58), PORT_DATA_IO_PU_PD(59), +- +- PORT_DATA_IO_PU_PD(60), PORT_DATA_IO_PD(61), +- PORT_DATA_IO_PD(62), PORT_DATA_IO_PD(63), +- PORT_DATA_IO_PD(64), PORT_DATA_IO_PD(65), +- PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67), +- PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69), +- +- PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71), +- PORT_DATA_IO_PU_PD(72), PORT_DATA_IO_PU_PD(73), +- PORT_DATA_IO_PU_PD(74), PORT_DATA_IO_PU_PD(75), +- PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77), +- PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79), +- +- PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81), +- PORT_DATA_IO(82), PORT_DATA_IO_PU_PD(83), +- PORT_DATA_IO(84), PORT_DATA_IO_PD(85), +- PORT_DATA_IO_PD(86), PORT_DATA_IO_PD(87), +- PORT_DATA_IO_PD(88), PORT_DATA_IO_PD(89), +- +- PORT_DATA_IO_PD(90), PORT_DATA_IO_PU_PD(91), +- PORT_DATA_IO_PU_PD(92), PORT_DATA_IO_PU_PD(93), +- PORT_DATA_IO_PU_PD(94), PORT_DATA_IO_PU_PD(95), +- PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97), +- PORT_DATA_IO_PU_PD(98), PORT_DATA_IO_PU_PD(99), +- +- PORT_DATA_IO_PU_PD(100), PORT_DATA_IO(101), +- PORT_DATA_IO_PU(102), PORT_DATA_IO_PU_PD(103), +- PORT_DATA_IO_PU(104), PORT_DATA_IO_PU(105), +- PORT_DATA_IO_PU_PD(106), PORT_DATA_IO(107), +- PORT_DATA_IO(108), PORT_DATA_IO(109), +- +- PORT_DATA_IO(110), PORT_DATA_IO(111), +- PORT_DATA_IO(112), PORT_DATA_IO(113), +- PORT_DATA_IO_PU_PD(114), PORT_DATA_IO(115), +- PORT_DATA_IO_PD(116), PORT_DATA_IO_PD(117), +- PORT_DATA_IO_PD(118), PORT_DATA_IO_PD(119), +- +- PORT_DATA_IO_PD(120), PORT_DATA_IO_PD(121), +- PORT_DATA_IO_PD(122), PORT_DATA_IO_PD(123), +- PORT_DATA_IO_PD(124), PORT_DATA_IO(125), +- PORT_DATA_IO(126), PORT_DATA_IO(127), +- PORT_DATA_IO(128), PORT_DATA_IO(129), +- +- PORT_DATA_IO(130), PORT_DATA_IO(131), +- PORT_DATA_IO(132), PORT_DATA_IO(133), +- PORT_DATA_IO(134), PORT_DATA_IO(135), +- PORT_DATA_IO(136), PORT_DATA_IO(137), +- PORT_DATA_IO(138), PORT_DATA_IO(139), +- +- PORT_DATA_IO(140), PORT_DATA_IO(141), +- PORT_DATA_IO_PU(142), PORT_DATA_IO_PU(143), +- PORT_DATA_IO_PU(144), PORT_DATA_IO_PU(145), +- PORT_DATA_IO_PU(146), PORT_DATA_IO_PU(147), +- PORT_DATA_IO_PU(148), PORT_DATA_IO_PU(149), +- +- PORT_DATA_IO_PU(150), PORT_DATA_IO_PU(151), +- PORT_DATA_IO_PU(152), PORT_DATA_IO_PU(153), +- PORT_DATA_IO_PU(154), PORT_DATA_IO_PU(155), +- PORT_DATA_IO_PU(156), PORT_DATA_IO_PU(157), +- PORT_DATA_IO_PD(158), PORT_DATA_IO_PD(159), +- +- PORT_DATA_IO_PU_PD(160), PORT_DATA_IO_PD(161), +- PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163), +- PORT_DATA_IO_PD(164), PORT_DATA_IO_PD(165), +- PORT_DATA_IO_PU(166), PORT_DATA_IO_PU(167), +- PORT_DATA_IO_PU(168), PORT_DATA_IO_PU(169), +- +- PORT_DATA_IO_PU(170), PORT_DATA_IO_PU(171), +- PORT_DATA_IO_PD(172), PORT_DATA_IO_PD(173), +- PORT_DATA_IO_PD(174), PORT_DATA_IO_PD(175), +- PORT_DATA_IO_PU(176), PORT_DATA_IO_PU_PD(177), +- PORT_DATA_IO_PU(178), PORT_DATA_IO_PD(179), +- +- PORT_DATA_IO_PD(180), PORT_DATA_IO_PU(181), +- PORT_DATA_IO_PU(182), PORT_DATA_IO(183), +- PORT_DATA_IO_PD(184), PORT_DATA_IO_PD(185), +- PORT_DATA_IO_PD(186), PORT_DATA_IO_PD(187), +- PORT_DATA_IO_PD(188), PORT_DATA_IO_PD(189), +- +- PORT_DATA_IO_PD(190), PORT_DATA_IO_PD(191), +- PORT_DATA_IO_PD(192), PORT_DATA_IO_PU_PD(193), +- PORT_DATA_IO_PU_PD(194), PORT_DATA_IO_PD(195), +- PORT_DATA_IO_PU_PD(196), PORT_DATA_IO_PD(197), +- PORT_DATA_IO_PU_PD(198), PORT_DATA_IO_PU_PD(199), +- +- PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU(201), +- PORT_DATA_IO_PU_PD(202), PORT_DATA_IO(203), +- PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205), +- PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PU_PD(207), +- PORT_DATA_IO_PU_PD(208), PORT_DATA_IO_PD(209), +- +- PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211), ++ PINMUX_DATA_GP_ALL(), + + /* Port0 */ + PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1), +@@ -1669,8 +1537,138 @@ static const pinmux_enum_t pinmux_data[] = { + PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0), + }; + ++#define R8A7740_PIN(pin, cfgs) \ ++ { \ ++ .name = __stringify(PORT##pin), \ ++ .enum_id = PORT##pin##_DATA, \ ++ .configs = cfgs, \ ++ } ++ ++#define __I (SH_PFC_PIN_CFG_INPUT) ++#define __O (SH_PFC_PIN_CFG_OUTPUT) ++#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT) ++#define __PD (SH_PFC_PIN_CFG_PULL_DOWN) ++#define __PU (SH_PFC_PIN_CFG_PULL_UP) ++#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP) ++ ++#define R8A7740_PIN_I_PD(pin) R8A7740_PIN(pin, __I | __PD) ++#define R8A7740_PIN_I_PU(pin) R8A7740_PIN(pin, __I | __PU) ++#define R8A7740_PIN_I_PU_PD(pin) R8A7740_PIN(pin, __I | __PUD) ++#define R8A7740_PIN_IO(pin) R8A7740_PIN(pin, __IO) ++#define R8A7740_PIN_IO_PD(pin) R8A7740_PIN(pin, __IO | __PD) ++#define R8A7740_PIN_IO_PU(pin) R8A7740_PIN(pin, __IO | __PU) ++#define R8A7740_PIN_IO_PU_PD(pin) R8A7740_PIN(pin, __IO | __PUD) ++#define R8A7740_PIN_O(pin) R8A7740_PIN(pin, __O) ++#define R8A7740_PIN_O_PU_PD(pin) R8A7740_PIN(pin, __O | __PUD) ++ + static struct sh_pfc_pin pinmux_pins[] = { +- GPIO_PORT_ALL(), ++ /* Table 56-1 (I/O and Pull U/D) */ ++ R8A7740_PIN_IO_PD(0), R8A7740_PIN_IO_PD(1), ++ R8A7740_PIN_IO_PD(2), R8A7740_PIN_IO_PD(3), ++ R8A7740_PIN_IO_PD(4), R8A7740_PIN_IO_PD(5), ++ R8A7740_PIN_IO_PD(6), R8A7740_PIN_IO(7), ++ R8A7740_PIN_IO(8), R8A7740_PIN_IO(9), ++ R8A7740_PIN_IO_PD(10), R8A7740_PIN_IO_PD(11), ++ R8A7740_PIN_IO_PD(12), R8A7740_PIN_IO_PU_PD(13), ++ R8A7740_PIN_IO_PD(14), R8A7740_PIN_IO_PD(15), ++ R8A7740_PIN_IO_PD(16), R8A7740_PIN_IO_PD(17), ++ R8A7740_PIN_IO(18), R8A7740_PIN_IO_PU(19), ++ R8A7740_PIN_IO_PU_PD(20), R8A7740_PIN_IO_PD(21), ++ R8A7740_PIN_IO_PU_PD(22), R8A7740_PIN_IO(23), ++ R8A7740_PIN_IO_PU(24), R8A7740_PIN_IO_PU(25), ++ R8A7740_PIN_IO_PU(26), R8A7740_PIN_IO_PU(27), ++ R8A7740_PIN_IO_PU(28), R8A7740_PIN_IO_PU(29), ++ R8A7740_PIN_IO_PU(30), R8A7740_PIN_IO_PD(31), ++ R8A7740_PIN_IO_PD(32), R8A7740_PIN_IO_PD(33), ++ R8A7740_PIN_IO_PD(34), R8A7740_PIN_IO_PU(35), ++ R8A7740_PIN_IO_PU(36), R8A7740_PIN_IO_PD(37), ++ R8A7740_PIN_IO_PU(38), R8A7740_PIN_IO_PD(39), ++ R8A7740_PIN_IO_PU_PD(40), R8A7740_PIN_IO_PD(41), ++ R8A7740_PIN_IO_PD(42), R8A7740_PIN_IO_PU_PD(43), ++ R8A7740_PIN_IO_PU_PD(44), R8A7740_PIN_IO_PU_PD(45), ++ R8A7740_PIN_IO_PU_PD(46), R8A7740_PIN_IO_PU_PD(47), ++ R8A7740_PIN_IO_PU_PD(48), R8A7740_PIN_IO_PU_PD(49), ++ R8A7740_PIN_IO_PU_PD(50), R8A7740_PIN_IO_PD(51), ++ R8A7740_PIN_IO_PD(52), R8A7740_PIN_IO_PD(53), ++ R8A7740_PIN_IO_PD(54), R8A7740_PIN_IO_PU_PD(55), ++ R8A7740_PIN_IO_PU_PD(56), R8A7740_PIN_IO_PU_PD(57), ++ R8A7740_PIN_IO_PU_PD(58), R8A7740_PIN_IO_PU_PD(59), ++ R8A7740_PIN_IO_PU_PD(60), R8A7740_PIN_IO_PD(61), ++ R8A7740_PIN_IO_PD(62), R8A7740_PIN_IO_PD(63), ++ R8A7740_PIN_IO_PD(64), R8A7740_PIN_IO_PD(65), ++ R8A7740_PIN_IO_PU_PD(66), R8A7740_PIN_IO_PU_PD(67), ++ R8A7740_PIN_IO_PU_PD(68), R8A7740_PIN_IO_PU_PD(69), ++ R8A7740_PIN_IO_PU_PD(70), R8A7740_PIN_IO_PU_PD(71), ++ R8A7740_PIN_IO_PU_PD(72), R8A7740_PIN_IO_PU_PD(73), ++ R8A7740_PIN_IO_PU_PD(74), R8A7740_PIN_IO_PU_PD(75), ++ R8A7740_PIN_IO_PU_PD(76), R8A7740_PIN_IO_PU_PD(77), ++ R8A7740_PIN_IO_PU_PD(78), R8A7740_PIN_IO_PU_PD(79), ++ R8A7740_PIN_IO_PU_PD(80), R8A7740_PIN_IO_PU_PD(81), ++ R8A7740_PIN_IO(82), R8A7740_PIN_IO_PU_PD(83), ++ R8A7740_PIN_IO(84), R8A7740_PIN_IO_PD(85), ++ R8A7740_PIN_IO_PD(86), R8A7740_PIN_IO_PD(87), ++ R8A7740_PIN_IO_PD(88), R8A7740_PIN_IO_PD(89), ++ R8A7740_PIN_IO_PD(90), R8A7740_PIN_IO_PU_PD(91), ++ R8A7740_PIN_IO_PU_PD(92), R8A7740_PIN_IO_PU_PD(93), ++ R8A7740_PIN_IO_PU_PD(94), R8A7740_PIN_IO_PU_PD(95), ++ R8A7740_PIN_IO_PU_PD(96), R8A7740_PIN_IO_PU_PD(97), ++ R8A7740_PIN_IO_PU_PD(98), R8A7740_PIN_IO_PU_PD(99), ++ R8A7740_PIN_IO_PU_PD(100), R8A7740_PIN_IO(101), ++ R8A7740_PIN_IO_PU(102), R8A7740_PIN_IO_PU_PD(103), ++ R8A7740_PIN_IO_PU(104), R8A7740_PIN_IO_PU(105), ++ R8A7740_PIN_IO_PU_PD(106), R8A7740_PIN_IO(107), ++ R8A7740_PIN_IO(108), R8A7740_PIN_IO(109), ++ R8A7740_PIN_IO(110), R8A7740_PIN_IO(111), ++ R8A7740_PIN_IO(112), R8A7740_PIN_IO(113), ++ R8A7740_PIN_IO_PU_PD(114), R8A7740_PIN_IO(115), ++ R8A7740_PIN_IO_PD(116), R8A7740_PIN_IO_PD(117), ++ R8A7740_PIN_IO_PD(118), R8A7740_PIN_IO_PD(119), ++ R8A7740_PIN_IO_PD(120), R8A7740_PIN_IO_PD(121), ++ R8A7740_PIN_IO_PD(122), R8A7740_PIN_IO_PD(123), ++ R8A7740_PIN_IO_PD(124), R8A7740_PIN_IO(125), ++ R8A7740_PIN_IO(126), R8A7740_PIN_IO(127), ++ R8A7740_PIN_IO(128), R8A7740_PIN_IO(129), ++ R8A7740_PIN_IO(130), R8A7740_PIN_IO(131), ++ R8A7740_PIN_IO(132), R8A7740_PIN_IO(133), ++ R8A7740_PIN_IO(134), R8A7740_PIN_IO(135), ++ R8A7740_PIN_IO(136), R8A7740_PIN_IO(137), ++ R8A7740_PIN_IO(138), R8A7740_PIN_IO(139), ++ R8A7740_PIN_IO(140), R8A7740_PIN_IO(141), ++ R8A7740_PIN_IO_PU(142), R8A7740_PIN_IO_PU(143), ++ R8A7740_PIN_IO_PU(144), R8A7740_PIN_IO_PU(145), ++ R8A7740_PIN_IO_PU(146), R8A7740_PIN_IO_PU(147), ++ R8A7740_PIN_IO_PU(148), R8A7740_PIN_IO_PU(149), ++ R8A7740_PIN_IO_PU(150), R8A7740_PIN_IO_PU(151), ++ R8A7740_PIN_IO_PU(152), R8A7740_PIN_IO_PU(153), ++ R8A7740_PIN_IO_PU(154), R8A7740_PIN_IO_PU(155), ++ R8A7740_PIN_IO_PU(156), R8A7740_PIN_IO_PU(157), ++ R8A7740_PIN_IO_PD(158), R8A7740_PIN_IO_PD(159), ++ R8A7740_PIN_IO_PU_PD(160), R8A7740_PIN_IO_PD(161), ++ R8A7740_PIN_IO_PD(162), R8A7740_PIN_IO_PD(163), ++ R8A7740_PIN_IO_PD(164), R8A7740_PIN_IO_PD(165), ++ R8A7740_PIN_IO_PU(166), R8A7740_PIN_IO_PU(167), ++ R8A7740_PIN_IO_PU(168), R8A7740_PIN_IO_PU(169), ++ R8A7740_PIN_IO_PU(170), R8A7740_PIN_IO_PU(171), ++ R8A7740_PIN_IO_PD(172), R8A7740_PIN_IO_PD(173), ++ R8A7740_PIN_IO_PD(174), R8A7740_PIN_IO_PD(175), ++ R8A7740_PIN_IO_PU(176), R8A7740_PIN_IO_PU_PD(177), ++ R8A7740_PIN_IO_PU(178), R8A7740_PIN_IO_PD(179), ++ R8A7740_PIN_IO_PD(180), R8A7740_PIN_IO_PU(181), ++ R8A7740_PIN_IO_PU(182), R8A7740_PIN_IO(183), ++ R8A7740_PIN_IO_PD(184), R8A7740_PIN_IO_PD(185), ++ R8A7740_PIN_IO_PD(186), R8A7740_PIN_IO_PD(187), ++ R8A7740_PIN_IO_PD(188), R8A7740_PIN_IO_PD(189), ++ R8A7740_PIN_IO_PD(190), R8A7740_PIN_IO_PD(191), ++ R8A7740_PIN_IO_PD(192), R8A7740_PIN_IO_PU_PD(193), ++ R8A7740_PIN_IO_PU_PD(194), R8A7740_PIN_IO_PD(195), ++ R8A7740_PIN_IO_PU_PD(196), R8A7740_PIN_IO_PD(197), ++ R8A7740_PIN_IO_PU_PD(198), R8A7740_PIN_IO_PU_PD(199), ++ R8A7740_PIN_IO_PU_PD(200), R8A7740_PIN_IO_PU(201), ++ R8A7740_PIN_IO_PU_PD(202), R8A7740_PIN_IO(203), ++ R8A7740_PIN_IO_PU_PD(204), R8A7740_PIN_IO_PU_PD(205), ++ R8A7740_PIN_IO_PU_PD(206), R8A7740_PIN_IO_PU_PD(207), ++ R8A7740_PIN_IO_PU_PD(208), R8A7740_PIN_IO_PD(209), ++ R8A7740_PIN_IO_PD(210), R8A7740_PIN_IO_PD(211), + }; + + /* - BSC -------------------------------------------------------------------- */ +@@ -3204,6 +3202,17 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(sdhi2), + }; + ++#undef PORTCR ++#define PORTCR(nr, reg) \ ++ { \ ++ PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ ++ _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \ ++ PORT##nr##_FN0, PORT##nr##_FN1, \ ++ PORT##nr##_FN2, PORT##nr##_FN3, \ ++ PORT##nr##_FN4, PORT##nr##_FN5, \ ++ PORT##nr##_FN6, PORT##nr##_FN7 } \ ++ } ++ + static const struct pinmux_cfg_reg pinmux_config_regs[] = { + PORTCR(0, 0xe6050000), /* PORT0CR */ + PORTCR(1, 0xe6050001), /* PORT1CR */ +@@ -3657,14 +3666,80 @@ static const struct pinmux_irq pinmux_irqs[] = { + PINMUX_IRQ(irq_pin(31), 41, 167), /* IRQ31A */ + }; + ++#define PORTnCR_PULMD_OFF (0 << 6) ++#define PORTnCR_PULMD_DOWN (2 << 6) ++#define PORTnCR_PULMD_UP (3 << 6) ++#define PORTnCR_PULMD_MASK (3 << 6) ++ ++struct r8a7740_portcr_group { ++ unsigned int end_pin; ++ unsigned int offset; ++}; ++ ++static const struct r8a7740_portcr_group r8a7740_portcr_offsets[] = { ++ { 83, 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 }, ++}; ++ ++static void __iomem *r8a7740_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < ARRAY_SIZE(r8a7740_portcr_offsets); ++i) { ++ const struct r8a7740_portcr_group *group = ++ &r8a7740_portcr_offsets[i]; ++ ++ if (i <= group->end_pin) ++ return pfc->window->virt + group->offset + pin; ++ } ++ ++ return NULL; ++} ++ ++static unsigned int r8a7740_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) ++{ ++ void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin); ++ u32 value = ioread8(addr) & PORTnCR_PULMD_MASK; ++ ++ switch (value) { ++ case PORTnCR_PULMD_UP: ++ return PIN_CONFIG_BIAS_PULL_UP; ++ case PORTnCR_PULMD_DOWN: ++ return PIN_CONFIG_BIAS_PULL_DOWN; ++ case PORTnCR_PULMD_OFF: ++ default: ++ return PIN_CONFIG_BIAS_DISABLE; ++ } ++} ++ ++static void r8a7740_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, ++ unsigned int bias) ++{ ++ void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin); ++ u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK; ++ ++ switch (bias) { ++ case PIN_CONFIG_BIAS_PULL_UP: ++ value |= PORTnCR_PULMD_UP; ++ break; ++ case PIN_CONFIG_BIAS_PULL_DOWN: ++ value |= PORTnCR_PULMD_DOWN; ++ break; ++ } ++ ++ iowrite8(value, addr); ++} ++ ++static const struct sh_pfc_soc_operations r8a7740_pinmux_ops = { ++ .get_bias = r8a7740_pinmux_get_bias, ++ .set_bias = r8a7740_pinmux_set_bias, ++}; ++ + const struct sh_pfc_soc_info r8a7740_pinmux_info = { + .name = "r8a7740_pfc", ++ .ops = &r8a7740_pinmux_ops, ++ + .input = { PINMUX_INPUT_BEGIN, + PINMUX_INPUT_END }, +- .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, +- PINMUX_INPUT_PULLUP_END }, +- .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, +- PINMUX_INPUT_PULLDOWN_END }, + .output = { PINMUX_OUTPUT_BEGIN, + PINMUX_OUTPUT_END }, + .function = { PINMUX_FUNCTION_BEGIN, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0178-sh-pfc-r8a7778-Fix-outdated-GPIO_FN-comments.patch b/patches.renesas/0178-sh-pfc-r8a7778-Fix-outdated-GPIO_FN-comments.patch new file mode 100644 index 00000000000..ed9b64a06aa --- /dev/null +++ b/patches.renesas/0178-sh-pfc-r8a7778-Fix-outdated-GPIO_FN-comments.patch @@ -0,0 +1,56 @@ +From c08292f86be53e3870e9108bc0debefeab3c281e Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 23 Apr 2013 11:08:05 +0000 +Subject: sh-pfc: r8a7778: Fix outdated GPIO_FN comments + +Function GPIOs have been removed, remove comments that refer to them. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 0eef12d732b92453340f17632eb7d51a9808aa07) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 26 +++++++++++++------------- + 1 file changed, 13 insertions(+), 13 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +index b1925cc1..72f7a3c1 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +@@ -376,19 +376,19 @@ enum { + AVS1_MARK, + AVS2_MARK, + +- VI0_R0_C_MARK, /* see GPIO_FN_VI0_R0_A */ +- VI0_R1_C_MARK, /* see GPIO_FN_VI0_R1_A */ +- VI0_R2_C_MARK, /* see GPIO_FN_VI0_R2_A */ +- /* VI0_R3_C_MARK, see GPIO_FN_VI0_R3_A */ +- VI0_R4_C_MARK, /* see GPIO_FN_VI0_R4_A */ +- VI0_R5_C_MARK, /* see GPIO_FN_VI0_R5_A */ +- +- VI0_R0_D_MARK, /* see GPIO_FN_VI0_R0_B */ +- VI0_R1_D_MARK, /* see GPIO_FN_VI0_R1_B */ +- VI0_R2_D_MARK, /* see GPIO_FN_VI0_R2_B */ +- VI0_R3_D_MARK, /* see GPIO_FN_VI0_R3_B */ +- VI0_R4_D_MARK, /* see GPIO_FN_VI0_R4_B */ +- VI0_R5_D_MARK, /* see GPIO_FN_VI0_R5_B */ ++ VI0_R0_C_MARK, /* see sel_vi0 */ ++ VI0_R1_C_MARK, /* see sel_vi0 */ ++ VI0_R2_C_MARK, /* see sel_vi0 */ ++ /* VI0_R3_C_MARK, */ ++ VI0_R4_C_MARK, /* see sel_vi0 */ ++ VI0_R5_C_MARK, /* see sel_vi0 */ ++ ++ VI0_R0_D_MARK, /* see sel_vi0 */ ++ VI0_R1_D_MARK, /* see sel_vi0 */ ++ VI0_R2_D_MARK, /* see sel_vi0 */ ++ VI0_R3_D_MARK, /* see sel_vi0 */ ++ VI0_R4_D_MARK, /* see sel_vi0 */ ++ VI0_R5_D_MARK, /* see sel_vi0 */ + + /* IPSR0 */ + PRESETOUT_MARK, PWM1_MARK, AUDATA0_MARK, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0179-sh-pfc-r8a7778-tidyup-SDHI-naming-suffixes-and-sort-.patch b/patches.renesas/0179-sh-pfc-r8a7778-tidyup-SDHI-naming-suffixes-and-sort-.patch new file mode 100644 index 00000000000..101bc22273b --- /dev/null +++ b/patches.renesas/0179-sh-pfc-r8a7778-tidyup-SDHI-naming-suffixes-and-sort-.patch @@ -0,0 +1,222 @@ +From 20ca60dcd77bbada47cf0c97f121c15f71c15198 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 23 Apr 2013 04:32:32 +0000 +Subject: sh-pfc: r8a7778: tidyup SDHI naming suffixes and sort it + alphabetically + +SDHI 1/2 are the target + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 0290df2d249e62b0e44b7c41d5fdd2c59c412587) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 164 +++++++++++++++++------------------ + 1 file changed, 80 insertions(+), 84 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +index 72f7a3c1..15295a5b 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +@@ -1450,60 +1450,56 @@ SDHI_PFC_PINS(sdhi0_wp, RCAR_GP_PIN(3, 18)); + SDHI_PFC_WPPN(sdhi0_wp, SD0_WP); + + /* - SDHI1 ------------------------------------------------------------------ */ +-SDHI_PFC_PINS(sdhi1_a_cd, RCAR_GP_PIN(0, 30)); +-SDHI_PFC_CDPN(sdhi1_a_cd, SD1_CD_A); +-SDHI_PFC_PINS(sdhi1_a_ctrl, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6)); +-SDHI_PFC_CTRL(sdhi1_a_ctrl, SD1_CLK_A, SD1_CMD_A); +-SDHI_PFC_PINS(sdhi1_a_data1, RCAR_GP_PIN(1, 7)); +-SDHI_PFC_DAT1(sdhi1_a_data1, SD1_DAT0_A); +-SDHI_PFC_PINS(sdhi1_a_data4, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), ++SDHI_PFC_PINS(sdhi1_cd_a, RCAR_GP_PIN(0, 30)); ++SDHI_PFC_CDPN(sdhi1_cd_a, SD1_CD_A); ++SDHI_PFC_PINS(sdhi1_cd_b, RCAR_GP_PIN(2, 24)); ++SDHI_PFC_CDPN(sdhi1_cd_b, SD1_CD_B); ++SDHI_PFC_PINS(sdhi1_ctrl_a, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6)); ++SDHI_PFC_CTRL(sdhi1_ctrl_a, SD1_CLK_A, SD1_CMD_A); ++SDHI_PFC_PINS(sdhi1_ctrl_b, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16)); ++SDHI_PFC_CTRL(sdhi1_ctrl_b, SD1_CLK_B, SD1_CMD_B); ++SDHI_PFC_PINS(sdhi1_data1_a, RCAR_GP_PIN(1, 7)); ++SDHI_PFC_DAT1(sdhi1_data1_a, SD1_DAT0_A); ++SDHI_PFC_PINS(sdhi1_data1_b, RCAR_GP_PIN(1, 18)); ++SDHI_PFC_DAT1(sdhi1_data1_b, SD1_DAT0_B); ++SDHI_PFC_PINS(sdhi1_data4_a, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6)); +-SDHI_PFC_DAT4(sdhi1_a_data4, SD1_DAT0_A, SD1_DAT1_A, ++SDHI_PFC_DAT4(sdhi1_data4_a, SD1_DAT0_A, SD1_DAT1_A, + SD1_DAT2_A, SD1_DAT3_A); +-SDHI_PFC_PINS(sdhi1_a_wp, RCAR_GP_PIN(0, 31)); +-SDHI_PFC_WPPN(sdhi1_a_wp, SD1_WP_A); +- +-SDHI_PFC_PINS(sdhi1_b_cd, RCAR_GP_PIN(2, 24)); +-SDHI_PFC_CDPN(sdhi1_b_cd, SD1_CD_B); +-SDHI_PFC_PINS(sdhi1_b_ctrl, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16)); +-SDHI_PFC_CTRL(sdhi1_b_ctrl, SD1_CLK_B, SD1_CMD_B); +-SDHI_PFC_PINS(sdhi1_b_data1, RCAR_GP_PIN(1, 18)); +-SDHI_PFC_DAT1(sdhi1_b_data1, SD1_DAT0_B); +-SDHI_PFC_PINS(sdhi1_b_data4, RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), ++SDHI_PFC_PINS(sdhi1_data4_b, RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), + RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21)); +-SDHI_PFC_DAT4(sdhi1_b_data4, SD1_DAT0_B, SD1_DAT1_B, ++SDHI_PFC_DAT4(sdhi1_data4_b, SD1_DAT0_B, SD1_DAT1_B, + SD1_DAT2_B, SD1_DAT3_B); +-SDHI_PFC_PINS(sdhi1_b_wp, RCAR_GP_PIN(2, 25)); +-SDHI_PFC_WPPN(sdhi1_b_wp, SD1_WP_B); +- ++SDHI_PFC_PINS(sdhi1_wp_a, RCAR_GP_PIN(0, 31)); ++SDHI_PFC_WPPN(sdhi1_wp_a, SD1_WP_A); ++SDHI_PFC_PINS(sdhi1_wp_b, RCAR_GP_PIN(2, 25)); ++SDHI_PFC_WPPN(sdhi1_wp_b, SD1_WP_B); + + /* - SDH2 ------------------------------------------------------------------- */ +-SDHI_PFC_PINS(sdhi2_a_cd, RCAR_GP_PIN(4, 23)); +-SDHI_PFC_CDPN(sdhi2_a_cd, SD2_CD_A); +-SDHI_PFC_PINS(sdhi2_a_ctrl, RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18)); +-SDHI_PFC_CTRL(sdhi2_a_ctrl, SD2_CLK_A, SD2_CMD_A); +-SDHI_PFC_PINS(sdhi2_a_data1, RCAR_GP_PIN(4, 19)); +-SDHI_PFC_DAT1(sdhi2_a_data1, SD2_DAT0_A); +-SDHI_PFC_PINS(sdhi2_a_data4, RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20), ++SDHI_PFC_PINS(sdhi2_cd_a, RCAR_GP_PIN(4, 23)); ++SDHI_PFC_CDPN(sdhi2_cd_a, SD2_CD_A); ++SDHI_PFC_PINS(sdhi2_cd_b, RCAR_GP_PIN(3, 27)); ++SDHI_PFC_CDPN(sdhi2_cd_b, SD2_CD_B); ++SDHI_PFC_PINS(sdhi2_ctrl_a, RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18)); ++SDHI_PFC_CTRL(sdhi2_ctrl_a, SD2_CLK_A, SD2_CMD_A); ++SDHI_PFC_PINS(sdhi2_ctrl_b, RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6)); ++SDHI_PFC_CTRL(sdhi2_ctrl_b, SD2_CLK_B, SD2_CMD_B); ++SDHI_PFC_PINS(sdhi2_data1_a, RCAR_GP_PIN(4, 19)); ++SDHI_PFC_DAT1(sdhi2_data1_a, SD2_DAT0_A); ++SDHI_PFC_PINS(sdhi2_data1_b, RCAR_GP_PIN(4, 7)); ++SDHI_PFC_DAT1(sdhi2_data1_b, SD2_DAT0_B); ++SDHI_PFC_PINS(sdhi2_data4_a, RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20), + RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22)); +-SDHI_PFC_DAT4(sdhi2_a_data4, SD2_DAT0_A, SD2_DAT1_A, ++SDHI_PFC_DAT4(sdhi2_data4_a, SD2_DAT0_A, SD2_DAT1_A, + SD2_DAT2_A, SD2_DAT3_A); +-SDHI_PFC_PINS(sdhi2_a_wp, RCAR_GP_PIN(4, 24)); +-SDHI_PFC_WPPN(sdhi2_a_wp, SD2_WP_A); +- +-SDHI_PFC_PINS(sdhi2_b_cd, RCAR_GP_PIN(3, 27)); +-SDHI_PFC_CDPN(sdhi2_b_cd, SD2_CD_B); +-SDHI_PFC_PINS(sdhi2_b_ctrl, RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6)); +-SDHI_PFC_CTRL(sdhi2_b_ctrl, SD2_CLK_B, SD2_CMD_B); +-SDHI_PFC_PINS(sdhi2_b_data1, RCAR_GP_PIN(4, 7)); +-SDHI_PFC_DAT1(sdhi2_b_data1, SD2_DAT0_B); +-SDHI_PFC_PINS(sdhi2_b_data4, RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), ++SDHI_PFC_PINS(sdhi2_data4_b, RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), + RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26)); +-SDHI_PFC_DAT4(sdhi2_b_data4, SD2_DAT0_B, SD2_DAT1_B, ++SDHI_PFC_DAT4(sdhi2_data4_b, SD2_DAT0_B, SD2_DAT1_B, + SD2_DAT2_B, SD2_DAT3_B); +-SDHI_PFC_PINS(sdhi2_b_wp, RCAR_GP_PIN(3, 28)); +-SDHI_PFC_WPPN(sdhi2_b_wp, SD2_WP_B); +- ++SDHI_PFC_PINS(sdhi2_wp_a, RCAR_GP_PIN(4, 24)); ++SDHI_PFC_WPPN(sdhi2_wp_a, SD2_WP_A); ++SDHI_PFC_PINS(sdhi2_wp_b, RCAR_GP_PIN(3, 28)); ++SDHI_PFC_WPPN(sdhi2_wp_b, SD2_WP_B); + + static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(hscif0_data_a), +@@ -1554,26 +1550,26 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_wp), +- SH_PFC_PIN_GROUP(sdhi1_a_cd), +- SH_PFC_PIN_GROUP(sdhi1_a_ctrl), +- SH_PFC_PIN_GROUP(sdhi1_a_data1), +- SH_PFC_PIN_GROUP(sdhi1_a_data4), +- SH_PFC_PIN_GROUP(sdhi1_a_wp), +- SH_PFC_PIN_GROUP(sdhi1_b_cd), +- SH_PFC_PIN_GROUP(sdhi1_b_ctrl), +- SH_PFC_PIN_GROUP(sdhi1_b_data1), +- SH_PFC_PIN_GROUP(sdhi1_b_data4), +- SH_PFC_PIN_GROUP(sdhi1_b_wp), +- SH_PFC_PIN_GROUP(sdhi2_a_cd), +- SH_PFC_PIN_GROUP(sdhi2_a_ctrl), +- SH_PFC_PIN_GROUP(sdhi2_a_data1), +- SH_PFC_PIN_GROUP(sdhi2_a_data4), +- SH_PFC_PIN_GROUP(sdhi2_a_wp), +- SH_PFC_PIN_GROUP(sdhi2_b_cd), +- SH_PFC_PIN_GROUP(sdhi2_b_ctrl), +- SH_PFC_PIN_GROUP(sdhi2_b_data1), +- SH_PFC_PIN_GROUP(sdhi2_b_data4), +- SH_PFC_PIN_GROUP(sdhi2_b_wp), ++ SH_PFC_PIN_GROUP(sdhi1_cd_a), ++ SH_PFC_PIN_GROUP(sdhi1_cd_b), ++ SH_PFC_PIN_GROUP(sdhi1_ctrl_a), ++ SH_PFC_PIN_GROUP(sdhi1_ctrl_b), ++ SH_PFC_PIN_GROUP(sdhi1_data1_a), ++ SH_PFC_PIN_GROUP(sdhi1_data1_b), ++ SH_PFC_PIN_GROUP(sdhi1_data4_a), ++ SH_PFC_PIN_GROUP(sdhi1_data4_b), ++ SH_PFC_PIN_GROUP(sdhi1_wp_a), ++ SH_PFC_PIN_GROUP(sdhi1_wp_b), ++ SH_PFC_PIN_GROUP(sdhi2_cd_a), ++ SH_PFC_PIN_GROUP(sdhi2_cd_b), ++ SH_PFC_PIN_GROUP(sdhi2_ctrl_a), ++ SH_PFC_PIN_GROUP(sdhi2_ctrl_b), ++ SH_PFC_PIN_GROUP(sdhi2_data1_a), ++ SH_PFC_PIN_GROUP(sdhi2_data1_b), ++ SH_PFC_PIN_GROUP(sdhi2_data4_a), ++ SH_PFC_PIN_GROUP(sdhi2_data4_b), ++ SH_PFC_PIN_GROUP(sdhi2_wp_a), ++ SH_PFC_PIN_GROUP(sdhi2_wp_b), + }; + + static const char * const hscif0_groups[] = { +@@ -1656,29 +1652,29 @@ static const char * const sdhi0_groups[] = { + }; + + static const char * const sdhi1_groups[] = { +- "sdhi1_a_cd", +- "sdhi1_a_ctrl", +- "sdhi1_a_data1", +- "sdhi1_a_data4", +- "sdhi1_a_wp", +- "sdhi1_b_cd", +- "sdhi1_b_ctrl", +- "sdhi1_b_data1", +- "sdhi1_b_data4", +- "sdhi1_b_wp", ++ "sdhi1_cd_a", ++ "sdhi1_cd_b", ++ "sdhi1_ctrl_a", ++ "sdhi1_ctrl_b", ++ "sdhi1_data1_a", ++ "sdhi1_data1_b", ++ "sdhi1_data4_a", ++ "sdhi1_data4_b", ++ "sdhi1_wp_a", ++ "sdhi1_wp_b", + }; + + static const char * const sdhi2_groups[] = { +- "sdhi2_a_cd", +- "sdhi2_a_ctrl", +- "sdhi2_a_data1", +- "sdhi2_a_data4", +- "sdhi2_a_wp", +- "sdhi2_b_cd", +- "sdhi2_b_ctrl", +- "sdhi2_b_data1", +- "sdhi2_b_data4", +- "sdhi2_b_wp", ++ "sdhi2_cd_a", ++ "sdhi2_cd_b", ++ "sdhi2_ctrl_a", ++ "sdhi2_ctrl_b", ++ "sdhi2_data1_a", ++ "sdhi2_data1_b", ++ "sdhi2_data4_a", ++ "sdhi2_data4_b", ++ "sdhi2_wp_a", ++ "sdhi2_wp_b", + }; + + static const struct sh_pfc_function pinmux_functions[] = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0180-ARM-shmobile-r8a7778-add-GPIO-support.patch b/patches.renesas/0180-ARM-shmobile-r8a7778-add-GPIO-support.patch new file mode 100644 index 00000000000..bdd1a27dfeb --- /dev/null +++ b/patches.renesas/0180-ARM-shmobile-r8a7778-add-GPIO-support.patch @@ -0,0 +1,82 @@ +From 78b6a770f918caa370f2f8b43bfa405abbb139bb Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 17 Apr 2013 23:41:50 -0700 +Subject: ARM: shmobile: r8a7778: add GPIO support + +This patch was tested on Bock-W board + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 39ca2283358852fa944f4abb8eb7ed8403b50420) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a7778.c | 36 +++++++++++++++++++++++++++++++++- + 1 file changed, 35 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c +index 0ca57010..1f36ecc3 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7778.c ++++ b/arch/arm/mach-shmobile/setup-r8a7778.c +@@ -24,6 +24,7 @@ + #include <linux/irqchip/arm-gic.h> + #include <linux/of.h> + #include <linux/of_platform.h> ++#include <linux/platform_data/gpio-rcar.h> + #include <linux/platform_data/irq-renesas-intc-irqpin.h> + #include <linux/platform_device.h> + #include <linux/irqchip.h> +@@ -94,17 +95,50 @@ static struct resource ether_resources[] = { + &sh_tmu##idx##_platform_data, \ + sizeof(sh_tmu##idx##_platform_data)) + +-/* PFC */ ++/* PFC/GPIO */ + static struct resource pfc_resources[] = { + DEFINE_RES_MEM(0xfffc0000, 0x118), + }; + ++#define R8A7778_GPIO(idx) \ ++static struct resource r8a7778_gpio##idx##_resources[] = { \ ++ DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30), \ ++ DEFINE_RES_IRQ(gic_iid(0x87)), \ ++}; \ ++ \ ++static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data = { \ ++ .gpio_base = 32 * (idx), \ ++ .irq_base = GPIO_IRQ_BASE(idx), \ ++ .number_of_pins = 32, \ ++ .pctl_name = "pfc-r8a7778", \ ++} ++ ++R8A7778_GPIO(0); ++R8A7778_GPIO(1); ++R8A7778_GPIO(2); ++R8A7778_GPIO(3); ++R8A7778_GPIO(4); ++ ++#define r8a7778_register_gpio(idx) \ ++ platform_device_register_resndata( \ ++ &platform_bus, "gpio_rcar", idx, \ ++ r8a7778_gpio##idx##_resources, \ ++ ARRAY_SIZE(r8a7778_gpio##idx##_resources), \ ++ &r8a7778_gpio##idx##_platform_data, \ ++ sizeof(r8a7778_gpio##idx##_platform_data)) ++ + void __init r8a7778_pinmux_init(void) + { + platform_device_register_simple( + "pfc-r8a7778", -1, + pfc_resources, + ARRAY_SIZE(pfc_resources)); ++ ++ r8a7778_register_gpio(0); ++ r8a7778_register_gpio(1); ++ r8a7778_register_gpio(2); ++ r8a7778_register_gpio(3); ++ r8a7778_register_gpio(4); + } + + void __init r8a7778_add_standard_devices(void) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0181-ARM-shmobile-r8a7790-Register-GPIO-devices.patch b/patches.renesas/0181-ARM-shmobile-r8a7790-Register-GPIO-devices.patch new file mode 100644 index 00000000000..c5f10d5d87d --- /dev/null +++ b/patches.renesas/0181-ARM-shmobile-r8a7790-Register-GPIO-devices.patch @@ -0,0 +1,77 @@ +From 832ff8c4332d932cf0d9799e74cf084ca3884c65 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 8 Apr 2013 11:36:17 +0200 +Subject: ARM: shmobile: r8a7790: Register GPIO devices + +Move GPIOs handling from the PFC device to separate GPIO devices. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 43ca9cbb29e11181888159b9a6375b1720672b82) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a7790.c | 35 +++++++++++++++++++++++++++++++++- + 1 file changed, 34 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c +index 49de2d56..eeef5f61 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7790.c ++++ b/arch/arm/mach-shmobile/setup-r8a7790.c +@@ -23,6 +23,7 @@ + #include <linux/kernel.h> + #include <linux/of_platform.h> + #include <linux/serial_sci.h> ++#include <linux/platform_data/gpio-rcar.h> + #include <linux/platform_data/irq-renesas-irqc.h> + #include <mach/common.h> + #include <mach/irqs.h> +@@ -31,13 +32,45 @@ + + static const struct resource pfc_resources[] = { + DEFINE_RES_MEM(0xe6060000, 0x250), +- DEFINE_RES_MEM(0xe6050000, 0x5050), + }; + ++#define R8A7790_GPIO(idx) \ ++static struct resource r8a7790_gpio##idx##_resources[] = { \ ++ DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50), \ ++ DEFINE_RES_IRQ(gic_spi(4 + (idx))), \ ++}; \ ++ \ ++static struct gpio_rcar_config r8a7790_gpio##idx##_platform_data = { \ ++ .gpio_base = 32 * (idx), \ ++ .irq_base = 0, \ ++ .number_of_pins = 32, \ ++ .pctl_name = "pfc-r8a7790", \ ++}; \ ++ ++R8A7790_GPIO(0); ++R8A7790_GPIO(1); ++R8A7790_GPIO(2); ++R8A7790_GPIO(3); ++R8A7790_GPIO(4); ++R8A7790_GPIO(5); ++ ++#define r8a7790_register_gpio(idx) \ ++ platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \ ++ r8a7790_gpio##idx##_resources, \ ++ ARRAY_SIZE(r8a7790_gpio##idx##_resources), \ ++ &r8a7790_gpio##idx##_platform_data, \ ++ sizeof(r8a7790_gpio##idx##_platform_data)) ++ + void __init r8a7790_pinmux_init(void) + { + platform_device_register_simple("pfc-r8a7790", -1, pfc_resources, + ARRAY_SIZE(pfc_resources)); ++ r8a7790_register_gpio(0); ++ r8a7790_register_gpio(1); ++ r8a7790_register_gpio(2); ++ r8a7790_register_gpio(3); ++ r8a7790_register_gpio(4); ++ r8a7790_register_gpio(5); + } + + #define SCIF_COMMON(scif_type, baseaddr, irq) \ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0182-ARM-shmobile-r8a7790-Remove-all-GPIOs.patch b/patches.renesas/0182-ARM-shmobile-r8a7790-Remove-all-GPIOs.patch new file mode 100644 index 00000000000..a40b6e84cc5 --- /dev/null +++ b/patches.renesas/0182-ARM-shmobile-r8a7790-Remove-all-GPIOs.patch @@ -0,0 +1,413 @@ +From ac7cd8d37c0b41df6d302815c65909b72ee95452 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 8 Apr 2013 11:36:21 +0200 +Subject: ARM: shmobile: r8a7790: Remove all GPIOs + +Function GPIOs are not used anymore, and all code use the GPIO numbers +directly. Remove the GPIOs enumeration. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 3654520cfe98815296f9871da35297445bb8c515) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/include/mach/r8a7790.h | 383 -------------------------- + 1 file changed, 383 deletions(-) + +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h +index e01ac4e3..2e919e61 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7790.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h +@@ -1,389 +1,6 @@ + #ifndef __ASM_R8A7790_H__ + #define __ASM_R8A7790_H__ + +-/* Pin Function Controller: +- * GPIO_FN_xx - GPIO used to select pin function +- * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU +- */ +-enum { +- GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3, +- GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7, +- GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11, +- GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15, +- GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19, +- GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23, +- GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27, +- GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31, +- +- GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3, +- GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7, +- GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11, +- GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15, +- GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19, +- GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23, +- GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27, +- GPIO_GP_1_28, GPIO_GP_1_29, +- +- GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3, +- GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7, +- GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11, +- GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15, +- GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19, +- GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23, +- GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27, +- GPIO_GP_2_28, GPIO_GP_2_29, +- +- GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3, +- GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7, +- GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11, +- GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15, +- GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19, +- GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23, +- GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27, +- GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31, +- +- GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3, +- GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7, +- GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11, +- GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15, +- GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19, +- GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23, +- GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27, +- GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31, +- +- GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3, +- GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7, +- GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11, +- GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15, +- GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19, +- GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23, +- GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27, +- GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31, +- +- GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC_VBUS, +- GPIO_FN_USB2_PWEN, GPIO_FN_USB2_OVC, GPIO_FN_AVS1, GPIO_FN_AVS2, +- GPIO_FN_DU_DOTCLKIN0, GPIO_FN_DU_DOTCLKIN2, +- +- /* IPSR0 */ +- GPIO_FN_D1, GPIO_FN_MSIOF3_SYNC_B, GPIO_FN_VI3_DATA1, GPIO_FN_VI0_G5, +- GPIO_FN_VI0_G5_B, GPIO_FN_D2, GPIO_FN_MSIOF3_RXD_B, GPIO_FN_VI3_DATA2, +- GPIO_FN_VI0_G6, GPIO_FN_VI0_G6_B, GPIO_FN_D3, GPIO_FN_MSIOF3_TXD_B, +- GPIO_FN_VI3_DATA3, GPIO_FN_VI0_G7, GPIO_FN_VI0_G7_B, GPIO_FN_D4, +- GPIO_FN_SCIFB1_RXD_F, GPIO_FN_SCIFB0_RXD_C, GPIO_FN_VI3_DATA4, +- GPIO_FN_VI0_R0, GPIO_FN_VI0_R0_B, GPIO_FN_RX0_B, GPIO_FN_D5, +- GPIO_FN_SCIFB1_TXD_F, GPIO_FN_SCIFB0_TXD_C, GPIO_FN_VI3_DATA5, +- GPIO_FN_VI0_R1, GPIO_FN_VI0_R1_B, GPIO_FN_TX0_B, GPIO_FN_D6, +- GPIO_FN_SCL2_C, GPIO_FN_VI3_DATA6, GPIO_FN_VI0_R2, GPIO_FN_VI0_R2_B, +- GPIO_FN_SCL2_CIS_C, GPIO_FN_D7, GPIO_FN_AD_DI_B, GPIO_FN_SDA2_C, +- GPIO_FN_VI3_DATA7, GPIO_FN_VI0_R3, GPIO_FN_VI0_R3_B, GPIO_FN_SDA2_CIS_C, +- GPIO_FN_D8, GPIO_FN_SCIFA1_SCK_C, GPIO_FN_AVB_TXD0, GPIO_FN_MII_TXD0, +- GPIO_FN_VI0_G0, GPIO_FN_VI0_G0_B, GPIO_FN_VI2_DATA0_VI2_B0, +- +- /* IPSR1 */ +- GPIO_FN_D9, GPIO_FN_SCIFA1_RXD_C, GPIO_FN_AVB_TXD1, GPIO_FN_MII_TXD1, +- GPIO_FN_VI0_G1, GPIO_FN_VI0_G1_B, GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_D10, +- GPIO_FN_SCIFA1_TXD_C, GPIO_FN_AVB_TXD2, GPIO_FN_MII_TXD2, +- GPIO_FN_VI0_G2, GPIO_FN_VI0_G2_B, GPIO_FN_VI2_DATA2_VI2_B2, GPIO_FN_D11, +- GPIO_FN_SCIFA1_CTS_N_C, GPIO_FN_AVB_TXD3, GPIO_FN_MII_TXD3, +- GPIO_FN_VI0_G3, GPIO_FN_VI0_G3_B, GPIO_FN_VI2_DATA3_VI2_B3, +- GPIO_FN_D12, GPIO_FN_SCIFA1_RTS_N_C, GPIO_FN_AVB_TXD4, +- GPIO_FN_VI0_HSYNC_N, GPIO_FN_VI0_HSYNC_N_B, GPIO_FN_VI2_DATA4_VI2_B4, +- GPIO_FN_D13, GPIO_FN_AVB_TXD5, GPIO_FN_VI0_VSYNC_N, +- GPIO_FN_VI0_VSYNC_N_B, GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_D14, +- GPIO_FN_SCIFB1_RXD_C, GPIO_FN_AVB_TXD6, GPIO_FN_RX1_B, +- GPIO_FN_VI0_CLKENB, GPIO_FN_VI0_CLKENB_B, GPIO_FN_VI2_DATA6_VI2_B6, +- GPIO_FN_D15, GPIO_FN_SCIFB1_TXD_C, GPIO_FN_AVB_TXD7, GPIO_FN_TX1_B, +- GPIO_FN_VI0_FIELD, GPIO_FN_VI0_FIELD_B, GPIO_FN_VI2_DATA7_VI2_B7, +- GPIO_FN_A0, GPIO_FN_PWM3, GPIO_FN_A1, GPIO_FN_PWM4, +- +- /* IPSR2 */ +- GPIO_FN_A2, GPIO_FN_PWM5, GPIO_FN_MSIOF1_SS1_B, GPIO_FN_A3, +- GPIO_FN_PWM6, GPIO_FN_MSIOF1_SS2_B, GPIO_FN_A4, GPIO_FN_MSIOF1_TXD_B, +- GPIO_FN_TPU0TO0, GPIO_FN_A5, GPIO_FN_SCIFA1_TXD_B, GPIO_FN_TPU0TO1, +- GPIO_FN_A6, GPIO_FN_SCIFA1_RTS_N_B, GPIO_FN_TPU0TO2, GPIO_FN_A7, +- GPIO_FN_SCIFA1_SCK_B, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_TPU0TO3, +- GPIO_FN_A8, GPIO_FN_SCIFA1_RXD_B, GPIO_FN_SSI_SCK5_B, GPIO_FN_VI0_R4, +- GPIO_FN_VI0_R4_B, GPIO_FN_SCIFB2_RXD_C, GPIO_FN_VI2_DATA0_VI2_B0_B, +- GPIO_FN_A9, GPIO_FN_SCIFA1_CTS_N_B, GPIO_FN_SSI_WS5_B, GPIO_FN_VI0_R5, +- GPIO_FN_VI0_R5_B, GPIO_FN_SCIFB2_TXD_C, GPIO_FN_VI2_DATA1_VI2_B1_B, +- GPIO_FN_A10, GPIO_FN_SSI_SDATA5_B, GPIO_FN_MSIOF2_SYNC, GPIO_FN_VI0_R6, +- GPIO_FN_VI0_R6_B, GPIO_FN_VI2_DATA2_VI2_B2_B, +- +- /* IPSR3 */ +- GPIO_FN_A11, GPIO_FN_SCIFB2_CTS_N_B, GPIO_FN_MSIOF2_SCK, GPIO_FN_VI1_R0, +- GPIO_FN_VI1_R0_B, GPIO_FN_VI2_G0, GPIO_FN_VI2_DATA3_VI2_B3_B, +- GPIO_FN_A12, GPIO_FN_SCIFB2_RXD_B, GPIO_FN_MSIOF2_TXD, GPIO_FN_VI1_R1, +- GPIO_FN_VI1_R1_B, GPIO_FN_VI2_G1, GPIO_FN_VI2_DATA4_VI2_B4_B, +- GPIO_FN_A13, GPIO_FN_SCIFB2_RTS_N_B, GPIO_FN_EX_WAIT2, +- GPIO_FN_MSIOF2_RXD, GPIO_FN_VI1_R2, GPIO_FN_VI1_R2_B, GPIO_FN_VI2_G2, +- GPIO_FN_VI2_DATA5_VI2_B5_B, GPIO_FN_A14, GPIO_FN_SCIFB2_TXD_B, +- GPIO_FN_ATACS11_N, GPIO_FN_MSIOF2_SS1, GPIO_FN_A15, +- GPIO_FN_SCIFB2_SCK_B, GPIO_FN_ATARD1_N, GPIO_FN_MSIOF2_SS2, GPIO_FN_A16, +- GPIO_FN_ATAWR1_N, GPIO_FN_A17, GPIO_FN_AD_DO_B, GPIO_FN_ATADIR1_N, +- GPIO_FN_A18, GPIO_FN_AD_CLK_B, GPIO_FN_ATAG1_N, GPIO_FN_A19, +- GPIO_FN_AD_NCS_N_B, GPIO_FN_ATACS01_N, GPIO_FN_EX_WAIT0_B, GPIO_FN_A20, +- GPIO_FN_SPCLK, GPIO_FN_VI1_R3, GPIO_FN_VI1_R3_B, GPIO_FN_VI2_G4, +- +- /* IPSR4 */ +- GPIO_FN_A21, GPIO_FN_MOSI_IO0, GPIO_FN_VI1_R4, GPIO_FN_VI1_R4_B, +- GPIO_FN_VI2_G5, GPIO_FN_A22, GPIO_FN_MISO_IO1, GPIO_FN_VI1_R5, +- GPIO_FN_VI1_R5_B, GPIO_FN_VI2_G6, GPIO_FN_A23, GPIO_FN_IO2, +- GPIO_FN_VI1_G7, GPIO_FN_VI1_G7_B, GPIO_FN_VI2_G7, GPIO_FN_A24, +- GPIO_FN_IO3, GPIO_FN_VI1_R7, GPIO_FN_VI1_R7_B, GPIO_FN_VI2_CLKENB, +- GPIO_FN_VI2_CLKENB_B, GPIO_FN_A25, GPIO_FN_SSL, GPIO_FN_VI1_G6, +- GPIO_FN_VI1_G6_B, GPIO_FN_VI2_FIELD, GPIO_FN_VI2_FIELD_B, GPIO_FN_CS0_N, +- GPIO_FN_VI1_R6, GPIO_FN_VI1_R6_B, GPIO_FN_VI2_G3, GPIO_FN_MSIOF0_SS2_B, +- GPIO_FN_CS1_N_A26, GPIO_FN_SPEEDIN, GPIO_FN_VI0_R7, GPIO_FN_VI0_R7_B, +- GPIO_FN_VI2_CLK, GPIO_FN_VI2_CLK_B, GPIO_FN_EX_CS0_N, GPIO_FN_HRX1_B, +- GPIO_FN_VI1_G5, GPIO_FN_VI1_G5_B, GPIO_FN_VI2_R0, GPIO_FN_HTX0_B, +- GPIO_FN_MSIOF0_SS1_B, GPIO_FN_EX_CS1_N, GPIO_FN_GPS_CLK, +- GPIO_FN_HCTS1_N_B, GPIO_FN_VI1_FIELD, GPIO_FN_VI1_FIELD_B, +- GPIO_FN_VI2_R1, GPIO_FN_EX_CS2_N, GPIO_FN_GPS_SIGN, GPIO_FN_HRTS1_N_B, +- GPIO_FN_VI3_CLKENB, GPIO_FN_VI1_G0, GPIO_FN_VI1_G0_B, GPIO_FN_VI2_R2, +- +- /* IPSR5 */ +- GPIO_FN_EX_CS3_N, GPIO_FN_GPS_MAG, GPIO_FN_VI3_FIELD, GPIO_FN_VI1_G1, +- GPIO_FN_VI1_G1_B, GPIO_FN_VI2_R3, GPIO_FN_EX_CS4_N, +- GPIO_FN_MSIOF1_SCK_B, GPIO_FN_VI3_HSYNC_N, +- GPIO_FN_VI2_HSYNC_N, GPIO_FN_SCL1, GPIO_FN_VI2_HSYNC_N_B, +- GPIO_FN_INTC_EN0_N, GPIO_FN_SCL1_CIS, GPIO_FN_EX_CS5_N, GPIO_FN_CAN0_RX, +- GPIO_FN_MSIOF1_RXD_B, GPIO_FN_VI3_VSYNC_N, GPIO_FN_VI1_G2, +- GPIO_FN_VI1_G2_B, GPIO_FN_VI2_R4, GPIO_FN_SDA1, GPIO_FN_INTC_EN1_N, +- GPIO_FN_SDA1_CIS, GPIO_FN_BS_N, GPIO_FN_IETX, GPIO_FN_HTX1_B, +- GPIO_FN_CAN1_TX, GPIO_FN_DRACK0, GPIO_FN_IETX_C, GPIO_FN_RD_N, +- GPIO_FN_CAN0_TX, GPIO_FN_SCIFA0_SCK_B, GPIO_FN_RD_WR_N, GPIO_FN_VI1_G3, +- GPIO_FN_VI1_G3_B, GPIO_FN_VI2_R5, GPIO_FN_SCIFA0_RXD_B, +- GPIO_FN_INTC_IRQ4_N, GPIO_FN_WE0_N, GPIO_FN_IECLK, GPIO_FN_CAN_CLK, +- GPIO_FN_VI2_VSYNC_N, GPIO_FN_SCIFA0_TXD_B, GPIO_FN_VI2_VSYNC_N_B, +- GPIO_FN_WE1_N, GPIO_FN_IERX, GPIO_FN_CAN1_RX, GPIO_FN_VI1_G4, +- GPIO_FN_VI1_G4_B, GPIO_FN_VI2_R6, GPIO_FN_SCIFA0_CTS_N_B, +- GPIO_FN_IERX_C, GPIO_FN_EX_WAIT0, GPIO_FN_IRQ3, GPIO_FN_INTC_IRQ3_N, +- GPIO_FN_VI3_CLK, GPIO_FN_SCIFA0_RTS_N_B, GPIO_FN_HRX0_B, +- GPIO_FN_MSIOF0_SCK_B, GPIO_FN_DREQ0_N, GPIO_FN_VI1_HSYNC_N, +- GPIO_FN_VI1_HSYNC_N_B, GPIO_FN_VI2_R7, GPIO_FN_SSI_SCK78_C, +- GPIO_FN_SSI_WS78_B, +- +- /* IPSR6 */ +- GPIO_FN_DACK0, GPIO_FN_IRQ0, GPIO_FN_INTC_IRQ0_N, GPIO_FN_SSI_SCK6_B, +- GPIO_FN_VI1_VSYNC_N, GPIO_FN_VI1_VSYNC_N_B, GPIO_FN_SSI_WS78_C, +- GPIO_FN_DREQ1_N, GPIO_FN_VI1_CLKENB, GPIO_FN_VI1_CLKENB_B, +- GPIO_FN_SSI_SDATA7_C, GPIO_FN_SSI_SCK78_B, GPIO_FN_DACK1, GPIO_FN_IRQ1, +- GPIO_FN_INTC_IRQ1_N, GPIO_FN_SSI_WS6_B, GPIO_FN_SSI_SDATA8_C, +- GPIO_FN_DREQ2_N, GPIO_FN_HSCK1_B, GPIO_FN_HCTS0_N_B, +- GPIO_FN_MSIOF0_TXD_B, GPIO_FN_DACK2, GPIO_FN_IRQ2, GPIO_FN_INTC_IRQ2_N, +- GPIO_FN_SSI_SDATA6_B, GPIO_FN_HRTS0_N_B, GPIO_FN_MSIOF0_RXD_B, +- GPIO_FN_ETH_CRS_DV, GPIO_FN_RMII_CRS_DV, GPIO_FN_STP_ISCLK_0_B, +- GPIO_FN_TS_SDEN0_D, GPIO_FN_GLO_Q0_C, GPIO_FN_SCL2_E, +- GPIO_FN_SCL2_CIS_E, GPIO_FN_ETH_RX_ER, GPIO_FN_RMII_RX_ER, +- GPIO_FN_STP_ISD_0_B, GPIO_FN_TS_SPSYNC0_D, GPIO_FN_GLO_Q1_C, +- GPIO_FN_SDA2_E, GPIO_FN_SDA2_CIS_E, GPIO_FN_ETH_RXD0, GPIO_FN_RMII_RXD0, +- GPIO_FN_STP_ISEN_0_B, GPIO_FN_TS_SDAT0_D, GPIO_FN_GLO_I0_C, +- GPIO_FN_SCIFB1_SCK_G, GPIO_FN_SCK1_E, GPIO_FN_ETH_RXD1, +- GPIO_FN_RMII_RXD1, GPIO_FN_HRX0_E, GPIO_FN_STP_ISSYNC_0_B, +- GPIO_FN_TS_SCK0_D, GPIO_FN_GLO_I1_C, GPIO_FN_SCIFB1_RXD_G, +- GPIO_FN_RX1_E, GPIO_FN_ETH_LINK, GPIO_FN_RMII_LINK, GPIO_FN_HTX0_E, +- GPIO_FN_STP_IVCXO27_0_B, GPIO_FN_SCIFB1_TXD_G, GPIO_FN_TX1_E, +- GPIO_FN_ETH_REF_CLK, GPIO_FN_RMII_REF_CLK, GPIO_FN_HCTS0_N_E, +- GPIO_FN_STP_IVCXO27_1_B, GPIO_FN_HRX0_F, +- +- /* IPSR7 */ +- GPIO_FN_ETH_MDIO, GPIO_FN_RMII_MDIO, GPIO_FN_HRTS0_N_E, +- GPIO_FN_SIM0_D_C, GPIO_FN_HCTS0_N_F, GPIO_FN_ETH_TXD1, +- GPIO_FN_RMII_TXD1, GPIO_FN_HTX0_F, GPIO_FN_BPFCLK_G, GPIO_FN_RDS_CLK_F, +- GPIO_FN_ETH_TX_EN, GPIO_FN_RMII_TX_EN, GPIO_FN_SIM0_CLK_C, +- GPIO_FN_HRTS0_N_F, GPIO_FN_ETH_MAGIC, GPIO_FN_RMII_MAGIC, +- GPIO_FN_SIM0_RST_C, GPIO_FN_ETH_TXD0, GPIO_FN_RMII_TXD0, +- GPIO_FN_STP_ISCLK_1_B, GPIO_FN_TS_SDEN1_C, GPIO_FN_GLO_SCLK_C, +- GPIO_FN_ETH_MDC, GPIO_FN_RMII_MDC, GPIO_FN_STP_ISD_1_B, +- GPIO_FN_TS_SPSYNC1_C, GPIO_FN_GLO_SDATA_C, GPIO_FN_PWM0, +- GPIO_FN_SCIFA2_SCK_C, GPIO_FN_STP_ISEN_1_B, GPIO_FN_TS_SDAT1_C, +- GPIO_FN_GLO_SS_C, GPIO_FN_PWM1, GPIO_FN_SCIFA2_TXD_C, +- GPIO_FN_STP_ISSYNC_1_B, GPIO_FN_TS_SCK1_C, GPIO_FN_GLO_RFON_C, +- GPIO_FN_PCMOE_N, GPIO_FN_PWM2, GPIO_FN_PWMFSW0, GPIO_FN_SCIFA2_RXD_C, +- GPIO_FN_PCMWE_N, GPIO_FN_IECLK_C, GPIO_FN_DU1_DOTCLKIN, +- GPIO_FN_AUDIO_CLKC, GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_VI0_CLK, +- GPIO_FN_ATACS00_N, GPIO_FN_AVB_RXD1, GPIO_FN_MII_RXD1, +- GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_ATACS10_N, GPIO_FN_AVB_RXD2, +- GPIO_FN_MII_RXD2, +- +- /* IPSR8 */ +- GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_ATARD0_N, GPIO_FN_AVB_RXD3, +- GPIO_FN_MII_RXD3, GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_ATAWR0_N, +- GPIO_FN_AVB_RXD4, GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_ATADIR0_N, +- GPIO_FN_AVB_RXD5, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_ATAG0_N, +- GPIO_FN_AVB_RXD6, GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_EX_WAIT1, +- GPIO_FN_AVB_RXD7, GPIO_FN_VI0_DATA6_VI0_B6, GPIO_FN_AVB_RX_ER, +- GPIO_FN_MII_RX_ER, GPIO_FN_VI0_DATA7_VI0_B7, GPIO_FN_AVB_RX_CLK, +- GPIO_FN_MII_RX_CLK, GPIO_FN_VI1_CLK, GPIO_FN_AVB_RX_DV, +- GPIO_FN_MII_RX_DV, GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SCIFA1_SCK_D, +- GPIO_FN_AVB_CRS, GPIO_FN_MII_CRS, GPIO_FN_VI1_DATA1_VI1_B1, +- GPIO_FN_SCIFA1_RXD_D, GPIO_FN_AVB_MDC, GPIO_FN_MII_MDC, +- GPIO_FN_VI1_DATA2_VI1_B2, GPIO_FN_SCIFA1_TXD_D, GPIO_FN_AVB_MDIO, +- GPIO_FN_MII_MDIO, GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_SCIFA1_CTS_N_D, +- GPIO_FN_AVB_GTX_CLK, GPIO_FN_VI1_DATA4_VI1_B4, GPIO_FN_SCIFA1_RTS_N_D, +- GPIO_FN_AVB_MAGIC, GPIO_FN_MII_MAGIC, GPIO_FN_VI1_DATA5_VI1_B5, +- GPIO_FN_AVB_PHY_INT, GPIO_FN_VI1_DATA6_VI1_B6, GPIO_FN_AVB_GTXREFCLK, +- GPIO_FN_SD0_CLK, GPIO_FN_VI1_DATA0_VI1_B0_B, GPIO_FN_SD0_CMD, +- GPIO_FN_SCIFB1_SCK_B, GPIO_FN_VI1_DATA1_VI1_B1_B, +- +- /* IPSR9 */ +- GPIO_FN_SD0_DAT0, GPIO_FN_SCIFB1_RXD_B, GPIO_FN_VI1_DATA2_VI1_B2_B, +- GPIO_FN_SD0_DAT1, GPIO_FN_SCIFB1_TXD_B, GPIO_FN_VI1_DATA3_VI1_B3_B, +- GPIO_FN_SD0_DAT2, GPIO_FN_SCIFB1_CTS_N_B, GPIO_FN_VI1_DATA4_VI1_B4_B, +- GPIO_FN_SD0_DAT3, GPIO_FN_SCIFB1_RTS_N_B, GPIO_FN_VI1_DATA5_VI1_B5_B, +- GPIO_FN_SD0_CD, GPIO_FN_MMC0_D6, GPIO_FN_TS_SDEN0_B, GPIO_FN_USB0_EXTP, +- GPIO_FN_GLO_SCLK, GPIO_FN_VI1_DATA6_VI1_B6_B, GPIO_FN_SCL1_B, +- GPIO_FN_SCL1_CIS_B, GPIO_FN_VI2_DATA6_VI2_B6_B, GPIO_FN_SD0_WP, +- GPIO_FN_MMC0_D7, GPIO_FN_TS_SPSYNC0_B, GPIO_FN_USB0_IDIN, +- GPIO_FN_GLO_SDATA, GPIO_FN_VI1_DATA7_VI1_B7_B, GPIO_FN_SDA1_B, +- GPIO_FN_SDA1_CIS_B, GPIO_FN_VI2_DATA7_VI2_B7_B, GPIO_FN_SD1_CLK, +- GPIO_FN_AVB_TX_EN, GPIO_FN_MII_TX_EN, GPIO_FN_SD1_CMD, +- GPIO_FN_AVB_TX_ER, GPIO_FN_MII_TX_ER, GPIO_FN_SCIFB0_SCK_B, +- GPIO_FN_SD1_DAT0, GPIO_FN_AVB_TX_CLK, GPIO_FN_MII_TX_CLK, +- GPIO_FN_SCIFB0_RXD_B, GPIO_FN_SD1_DAT1, GPIO_FN_AVB_LINK, +- GPIO_FN_MII_LINK, GPIO_FN_SCIFB0_TXD_B, GPIO_FN_SD1_DAT2, +- GPIO_FN_AVB_COL, GPIO_FN_MII_COL, GPIO_FN_SCIFB0_CTS_N_B, +- GPIO_FN_SD1_DAT3, GPIO_FN_AVB_RXD0, GPIO_FN_MII_RXD0, +- GPIO_FN_SCIFB0_RTS_N_B, GPIO_FN_SD1_CD, GPIO_FN_MMC1_D6, +- GPIO_FN_TS_SDEN1, GPIO_FN_USB1_EXTP, GPIO_FN_GLO_SS, GPIO_FN_VI0_CLK_B, +- GPIO_FN_SCL2_D, GPIO_FN_SCL2_CIS_D, GPIO_FN_SIM0_CLK_B, +- GPIO_FN_VI3_CLK_B, +- +- /* IPSR10 */ +- GPIO_FN_SD1_WP, GPIO_FN_MMC1_D7, GPIO_FN_TS_SPSYNC1, GPIO_FN_USB1_IDIN, +- GPIO_FN_GLO_RFON, GPIO_FN_VI1_CLK_B, GPIO_FN_SDA2_D, GPIO_FN_SDA2_CIS_D, +- GPIO_FN_SIM0_D_B, GPIO_FN_SD2_CLK, GPIO_FN_MMC0_CLK, GPIO_FN_SIM0_CLK, +- GPIO_FN_VI0_DATA0_VI0_B0_B, GPIO_FN_TS_SDEN0_C, GPIO_FN_GLO_SCLK_B, +- GPIO_FN_VI3_DATA0_B, GPIO_FN_SD2_CMD, GPIO_FN_MMC0_CMD, GPIO_FN_SIM0_D, +- GPIO_FN_VI0_DATA1_VI0_B1_B, GPIO_FN_SCIFB1_SCK_E, GPIO_FN_SCK1_D, +- GPIO_FN_TS_SPSYNC0_C, GPIO_FN_GLO_SDATA_B, GPIO_FN_VI3_DATA1_B, +- GPIO_FN_SD2_DAT0, GPIO_FN_MMC0_D0, GPIO_FN_FMCLK_B, +- GPIO_FN_VI0_DATA2_VI0_B2_B, GPIO_FN_SCIFB1_RXD_E, GPIO_FN_RX1_D, +- GPIO_FN_TS_SDAT0_C, GPIO_FN_GLO_SS_B, GPIO_FN_VI3_DATA2_B, +- GPIO_FN_SD2_DAT1, GPIO_FN_MMC0_D1, GPIO_FN_FMIN_B, GPIO_FN_RDS_DATA, +- GPIO_FN_VI0_DATA3_VI0_B3_B, GPIO_FN_SCIFB1_TXD_E, GPIO_FN_TX1_D, +- GPIO_FN_TS_SCK0_C, GPIO_FN_GLO_RFON_B, GPIO_FN_VI3_DATA3_B, +- GPIO_FN_SD2_DAT2, GPIO_FN_MMC0_D2, GPIO_FN_BPFCLK_B, GPIO_FN_RDS_CLK, +- GPIO_FN_VI0_DATA4_VI0_B4_B, GPIO_FN_HRX0_D, GPIO_FN_TS_SDEN1_B, +- GPIO_FN_GLO_Q0_B, GPIO_FN_VI3_DATA4_B, GPIO_FN_SD2_DAT3, +- GPIO_FN_MMC0_D3, GPIO_FN_SIM0_RST, GPIO_FN_VI0_DATA5_VI0_B5_B, +- GPIO_FN_HTX0_D, GPIO_FN_TS_SPSYNC1_B, GPIO_FN_GLO_Q1_B, +- GPIO_FN_VI3_DATA5_B, GPIO_FN_SD2_CD, GPIO_FN_MMC0_D4, +- GPIO_FN_TS_SDAT0_B, GPIO_FN_USB2_EXTP, GPIO_FN_GLO_I0, +- GPIO_FN_VI0_DATA6_VI0_B6_B, GPIO_FN_HCTS0_N_D, GPIO_FN_TS_SDAT1_B, +- GPIO_FN_GLO_I0_B, GPIO_FN_VI3_DATA6_B, +- +- /* IPSR11 */ +- GPIO_FN_SD2_WP, GPIO_FN_MMC0_D5, GPIO_FN_TS_SCK0_B, GPIO_FN_USB2_IDIN, +- GPIO_FN_GLO_I1, GPIO_FN_VI0_DATA7_VI0_B7_B, GPIO_FN_HRTS0_N_D, +- GPIO_FN_TS_SCK1_B, GPIO_FN_GLO_I1_B, GPIO_FN_VI3_DATA7_B, +- GPIO_FN_SD3_CLK, GPIO_FN_MMC1_CLK, GPIO_FN_SD3_CMD, GPIO_FN_MMC1_CMD, +- GPIO_FN_MTS_N, GPIO_FN_SD3_DAT0, GPIO_FN_MMC1_D0, GPIO_FN_STM_N, +- GPIO_FN_SD3_DAT1, GPIO_FN_MMC1_D1, GPIO_FN_MDATA, GPIO_FN_SD3_DAT2, +- GPIO_FN_MMC1_D2, GPIO_FN_SDATA, GPIO_FN_SD3_DAT3, GPIO_FN_MMC1_D3, +- GPIO_FN_SCKZ, GPIO_FN_SD3_CD, GPIO_FN_MMC1_D4, GPIO_FN_TS_SDAT1, +- GPIO_FN_VSP, GPIO_FN_GLO_Q0, GPIO_FN_SIM0_RST_B, GPIO_FN_SD3_WP, +- GPIO_FN_MMC1_D5, GPIO_FN_TS_SCK1, GPIO_FN_GLO_Q1, GPIO_FN_FMIN_C, +- GPIO_FN_RDS_DATA_B, GPIO_FN_FMIN_E, GPIO_FN_RDS_DATA_D, GPIO_FN_FMIN_F, +- GPIO_FN_RDS_DATA_E, GPIO_FN_MLB_CLK, GPIO_FN_SCL2_B, GPIO_FN_SCL2_CIS_B, +- GPIO_FN_MLB_SIG, GPIO_FN_SCIFB1_RXD_D, GPIO_FN_RX1_C, GPIO_FN_SDA2_B, +- GPIO_FN_SDA2_CIS_B, GPIO_FN_MLB_DAT, GPIO_FN_SPV_EVEN, +- GPIO_FN_SCIFB1_TXD_D, GPIO_FN_TX1_C, GPIO_FN_BPFCLK_C, +- GPIO_FN_RDS_CLK_B, GPIO_FN_SSI_SCK0129, GPIO_FN_CAN_CLK_B, +- GPIO_FN_MOUT0, +- +- /* IPSR12 */ +- GPIO_FN_SSI_WS0129, GPIO_FN_CAN0_TX_B, GPIO_FN_MOUT1, +- GPIO_FN_SSI_SDATA0, GPIO_FN_CAN0_RX_B, GPIO_FN_MOUT2, +- GPIO_FN_SSI_SDATA1, GPIO_FN_CAN1_TX_B, GPIO_FN_MOUT5, +- GPIO_FN_SSI_SDATA2, GPIO_FN_CAN1_RX_B, GPIO_FN_SSI_SCK1, GPIO_FN_MOUT6, +- GPIO_FN_SSI_SCK34, GPIO_FN_STP_OPWM_0, GPIO_FN_SCIFB0_SCK, +- GPIO_FN_MSIOF1_SCK, GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_SSI_WS34, +- GPIO_FN_STP_IVCXO27_0, GPIO_FN_SCIFB0_RXD, GPIO_FN_MSIOF1_SYNC, +- GPIO_FN_CAN_STEP0, GPIO_FN_SSI_SDATA3, GPIO_FN_STP_ISCLK_0, +- GPIO_FN_SCIFB0_TXD, GPIO_FN_MSIOF1_SS1, GPIO_FN_CAN_TXCLK, +- GPIO_FN_SSI_SCK4, GPIO_FN_STP_ISD_0, GPIO_FN_SCIFB0_CTS_N, +- GPIO_FN_MSIOF1_SS2, GPIO_FN_SSI_SCK5_C, GPIO_FN_CAN_DEBUGOUT0, +- GPIO_FN_SSI_WS4, GPIO_FN_STP_ISEN_0, GPIO_FN_SCIFB0_RTS_N, +- GPIO_FN_MSIOF1_TXD, GPIO_FN_SSI_WS5_C, GPIO_FN_CAN_DEBUGOUT1, +- GPIO_FN_SSI_SDATA4, GPIO_FN_STP_ISSYNC_0, GPIO_FN_MSIOF1_RXD, +- GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_SSI_SCK5, GPIO_FN_SCIFB1_SCK, +- GPIO_FN_IERX_B, GPIO_FN_DU2_EXHSYNC_DU2_HSYNC, GPIO_FN_QSTH_QHS, +- GPIO_FN_CAN_DEBUGOUT3, GPIO_FN_SSI_WS5, GPIO_FN_SCIFB1_RXD, +- GPIO_FN_IECLK_B, GPIO_FN_DU2_EXVSYNC_DU2_VSYNC, GPIO_FN_QSTB_QHE, +- GPIO_FN_CAN_DEBUGOUT4, +- +- /* IPSR13 */ +- GPIO_FN_SSI_SDATA5, GPIO_FN_SCIFB1_TXD, GPIO_FN_IETX_B, GPIO_FN_DU2_DR2, +- GPIO_FN_LCDOUT2, GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_SSI_SCK6, +- GPIO_FN_SCIFB1_CTS_N, GPIO_FN_BPFCLK_D, GPIO_FN_RDS_CLK_C, +- GPIO_FN_DU2_DR3, GPIO_FN_LCDOUT3, GPIO_FN_CAN_DEBUGOUT6, +- GPIO_FN_BPFCLK_F, GPIO_FN_RDS_CLK_E, GPIO_FN_SSI_WS6, +- GPIO_FN_SCIFB1_RTS_N, GPIO_FN_CAN0_TX_D, GPIO_FN_DU2_DR4, +- GPIO_FN_LCDOUT4, GPIO_FN_CAN_DEBUGOUT7, GPIO_FN_SSI_SDATA6, +- GPIO_FN_FMIN_D, GPIO_FN_RDS_DATA_C, GPIO_FN_DU2_DR5, GPIO_FN_LCDOUT5, +- GPIO_FN_CAN_DEBUGOUT8, GPIO_FN_SSI_SCK78, GPIO_FN_STP_IVCXO27_1, +- GPIO_FN_SCK1, GPIO_FN_SCIFA1_SCK, GPIO_FN_DU2_DR6, GPIO_FN_LCDOUT6, +- GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_WS78, GPIO_FN_STP_ISCLK_1, +- GPIO_FN_SCIFB2_SCK, GPIO_FN_SCIFA2_CTS_N, GPIO_FN_DU2_DR7, +- GPIO_FN_LCDOUT7, GPIO_FN_CAN_DEBUGOUT10, GPIO_FN_SSI_SDATA7, +- GPIO_FN_STP_ISD_1, GPIO_FN_SCIFB2_RXD, GPIO_FN_SCIFA2_RTS_N, +- GPIO_FN_TCLK2, GPIO_FN_QSTVA_QVS, GPIO_FN_CAN_DEBUGOUT11, +- GPIO_FN_BPFCLK_E, GPIO_FN_RDS_CLK_D, GPIO_FN_SSI_SDATA7_B, +- GPIO_FN_FMIN_G, GPIO_FN_RDS_DATA_F, GPIO_FN_SSI_SDATA8, +- GPIO_FN_STP_ISEN_1, GPIO_FN_SCIFB2_TXD, GPIO_FN_CAN0_TX_C, +- GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_SSI_SDATA8_B, GPIO_FN_SSI_SDATA9, +- GPIO_FN_STP_ISSYNC_1, GPIO_FN_SCIFB2_CTS_N, GPIO_FN_SSI_WS1, +- GPIO_FN_SSI_SDATA5_C, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_AUDIO_CLKA, +- GPIO_FN_SCIFB2_RTS_N, GPIO_FN_CAN_DEBUGOUT14, +- +- /* IPSR14 */ +- GPIO_FN_AUDIO_CLKB, GPIO_FN_SCIF_CLK, GPIO_FN_CAN0_RX_D, +- GPIO_FN_DVC_MUTE, GPIO_FN_CAN0_RX_C, GPIO_FN_CAN_DEBUGOUT15, +- GPIO_FN_REMOCON, GPIO_FN_SCIFA0_SCK, GPIO_FN_HSCK1, GPIO_FN_SCK0, +- GPIO_FN_MSIOF3_SS2, GPIO_FN_DU2_DG2, GPIO_FN_LCDOUT10, GPIO_FN_SDA1_C, +- GPIO_FN_SDA1_CIS_C, GPIO_FN_SCIFA0_RXD, GPIO_FN_HRX1, GPIO_FN_RX0, +- GPIO_FN_DU2_DR0, GPIO_FN_LCDOUT0, GPIO_FN_SCIFA0_TXD, GPIO_FN_HTX1, +- GPIO_FN_TX0, GPIO_FN_DU2_DR1, GPIO_FN_LCDOUT1, GPIO_FN_SCIFA0_CTS_N, +- GPIO_FN_HCTS1_N, GPIO_FN_CTS0_N, GPIO_FN_MSIOF3_SYNC, GPIO_FN_DU2_DG3, +- GPIO_FN_LCDOUT11, GPIO_FN_PWM0_B, GPIO_FN_SCL1_C, GPIO_FN_SCL1_CIS_C, +- GPIO_FN_SCIFA0_RTS_N, GPIO_FN_HRTS1_N, GPIO_FN_RTS0_N_TANS, +- GPIO_FN_MSIOF3_SS1, GPIO_FN_DU2_DG0, GPIO_FN_LCDOUT8, GPIO_FN_PWM1_B, +- GPIO_FN_SCIFA1_RXD, GPIO_FN_AD_DI, GPIO_FN_RX1, +- GPIO_FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE, +- GPIO_FN_SCIFA1_TXD, GPIO_FN_AD_DO, GPIO_FN_TX1, GPIO_FN_DU2_DG1, +- GPIO_FN_LCDOUT9, GPIO_FN_SCIFA1_CTS_N, GPIO_FN_AD_CLK, +- GPIO_FN_CTS1_N, GPIO_FN_MSIOF3_RXD, GPIO_FN_DU0_DOTCLKOUT, GPIO_FN_QCLK, +- GPIO_FN_SCIFA1_RTS_N, GPIO_FN_AD_NCS_N, GPIO_FN_RTS1_N_TANS, +- GPIO_FN_MSIOF3_TXD, GPIO_FN_DU1_DOTCLKOUT, GPIO_FN_QSTVB_QVE, +- GPIO_FN_HRTS0_N_C, +- +- /* IPSR15 */ +- GPIO_FN_SCIFA2_SCK, GPIO_FN_FMCLK, GPIO_FN_MSIOF3_SCK, GPIO_FN_DU2_DG7, +- GPIO_FN_LCDOUT15, GPIO_FN_SCIF_CLK_B, GPIO_FN_SCIFA2_RXD, GPIO_FN_FMIN, +- GPIO_FN_DU2_DB0, GPIO_FN_LCDOUT16, GPIO_FN_SCL2, GPIO_FN_SCL2_CIS, +- GPIO_FN_SCIFA2_TXD, GPIO_FN_BPFCLK, GPIO_FN_DU2_DB1, GPIO_FN_LCDOUT17, +- GPIO_FN_SDA2, GPIO_FN_SDA2_CIS, GPIO_FN_HSCK0, GPIO_FN_TS_SDEN0, +- GPIO_FN_DU2_DG4, GPIO_FN_LCDOUT12, GPIO_FN_HCTS0_N_C, GPIO_FN_HRX0, +- GPIO_FN_DU2_DB2, GPIO_FN_LCDOUT18, GPIO_FN_HTX0, GPIO_FN_DU2_DB3, +- GPIO_FN_LCDOUT19, GPIO_FN_HCTS0_N, GPIO_FN_SSI_SCK9, GPIO_FN_DU2_DB4, +- GPIO_FN_LCDOUT20, GPIO_FN_HRTS0_N, GPIO_FN_SSI_WS9, GPIO_FN_DU2_DB5, +- GPIO_FN_LCDOUT21, GPIO_FN_MSIOF0_SCK, GPIO_FN_TS_SDAT0, GPIO_FN_ADICLK, +- GPIO_FN_DU2_DB6, GPIO_FN_LCDOUT22, GPIO_FN_MSIOF0_SYNC, GPIO_FN_TS_SCK0, +- GPIO_FN_SSI_SCK2, GPIO_FN_ADIDATA, GPIO_FN_DU2_DB7, GPIO_FN_LCDOUT23, +- GPIO_FN_SCIFA2_RXD_B, GPIO_FN_MSIOF0_SS1, GPIO_FN_ADICHS0, +- GPIO_FN_DU2_DG5, GPIO_FN_LCDOUT13, GPIO_FN_MSIOF0_TXD, GPIO_FN_ADICHS1, +- GPIO_FN_DU2_DG6, GPIO_FN_LCDOUT14, +- +- /* IPSR16 */ +- GPIO_FN_MSIOF0_SS2, GPIO_FN_AUDIO_CLKOUT, GPIO_FN_ADICHS2, +- GPIO_FN_DU2_DISP, GPIO_FN_QPOLA, GPIO_FN_HTX0_C, GPIO_FN_SCIFA2_TXD_B, +- GPIO_FN_MSIOF0_RXD, GPIO_FN_TS_SPSYNC0, GPIO_FN_SSI_WS2, +- GPIO_FN_ADICS_SAMP, GPIO_FN_DU2_CDE, GPIO_FN_QPOLB, GPIO_FN_HRX0_C, +- GPIO_FN_USB1_PWEN, GPIO_FN_AUDIO_CLKOUT_D, GPIO_FN_USB1_OVC, +- GPIO_FN_TCLK1_B, +-}; +- + void r8a7790_add_standard_devices(void); + void r8a7790_clock_init(void); + void r8a7790_pinmux_init(void); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0183-ARM-shmobile-r8a7779-pinmux-platform-device-cleanup.patch b/patches.renesas/0183-ARM-shmobile-r8a7779-pinmux-platform-device-cleanup.patch new file mode 100644 index 00000000000..4c25c6f4cc9 --- /dev/null +++ b/patches.renesas/0183-ARM-shmobile-r8a7779-pinmux-platform-device-cleanup.patch @@ -0,0 +1,56 @@ +From 1e2fa62b82329ebacabae7472707bdee654b5da1 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Fri, 12 Apr 2013 14:21:29 +0200 +Subject: ARM: shmobile: r8a7779 pinmux platform device cleanup + +Use DEFINE_RES_MEM() to save a couple of lines of code. + +Signed-off-by: Magnus Damm <damm@opensource.se> +[lp: Don't declare r8a7779_pfc_resources as const] +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit 0ccaf5bb3fb6ad8d1fe3464cf269a3225c853c46) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a7779.c | 17 +++-------------- + 1 file changed, 3 insertions(+), 14 deletions(-) + +diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c +index b0b39484..dbb13f28 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7779.c ++++ b/arch/arm/mach-shmobile/setup-r8a7779.c +@@ -65,11 +65,7 @@ void __init r8a7779_map_io(void) + } + + static struct resource r8a7779_pfc_resources[] = { +- [0] = { +- .start = 0xfffc0000, +- .end = 0xfffc023b, +- .flags = IORESOURCE_MEM, +- }, ++ DEFINE_RES_MEM(0xfffc0000, 0x023c), + }; + + static struct platform_device r8a7779_pfc_device = { +@@ -81,15 +77,8 @@ static struct platform_device r8a7779_pfc_device = { + + #define R8A7779_GPIO(idx, npins) \ + static struct resource r8a7779_gpio##idx##_resources[] = { \ +- [0] = { \ +- .start = 0xffc40000 + 0x1000 * (idx), \ +- .end = 0xffc4002b + 0x1000 * (idx), \ +- .flags = IORESOURCE_MEM, \ +- }, \ +- [1] = { \ +- .start = gic_iid(0xad + (idx)), \ +- .flags = IORESOURCE_IRQ, \ +- } \ ++ DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c), \ ++ DEFINE_RES_IRQ(gic_iid(0xad + (idx))), \ + }; \ + \ + static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = { \ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0184-sh-pfc-Add-support-for-SoC-specific-initialization.patch b/patches.renesas/0184-sh-pfc-Add-support-for-SoC-specific-initialization.patch new file mode 100644 index 00000000000..7e830e05005 --- /dev/null +++ b/patches.renesas/0184-sh-pfc-Add-support-for-SoC-specific-initialization.patch @@ -0,0 +1,95 @@ +From 69b260be465249c3eec50b7e7aef099ed87ef420 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Sun, 21 Apr 2013 20:21:57 +0200 +Subject: sh-pfc: Add support for SoC-specific initialization + +Add two optional init and exit SoC operations and call them from the +core at probe and remove time. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Acked-by: Linus Walleij <linus.walleij@linaro.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 0c151062f32c9db819c2ca3081d6f98194d61e78) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/core.c | 16 +++++++++++++++- + drivers/pinctrl/sh-pfc/core.h | 1 + + drivers/pinctrl/sh-pfc/sh_pfc.h | 2 ++ + 3 files changed, 18 insertions(+), 1 deletion(-) + +diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c +index 4540ce38..3b2fd43f 100644 +--- a/drivers/pinctrl/sh-pfc/core.c ++++ b/drivers/pinctrl/sh-pfc/core.c +@@ -372,6 +372,12 @@ static int sh_pfc_probe(struct platform_device *pdev) + + spin_lock_init(&pfc->lock); + ++ if (info->ops && info->ops->init) { ++ ret = info->ops->init(pfc); ++ if (ret < 0) ++ return ret; ++ } ++ + pinctrl_provide_dummies(); + + /* +@@ -379,7 +385,7 @@ static int sh_pfc_probe(struct platform_device *pdev) + */ + ret = sh_pfc_register_pinctrl(pfc); + if (unlikely(ret != 0)) +- return ret; ++ goto error; + + #ifdef CONFIG_GPIO_SH_PFC + /* +@@ -401,6 +407,11 @@ static int sh_pfc_probe(struct platform_device *pdev) + dev_info(pfc->dev, "%s support registered\n", info->name); + + return 0; ++ ++error: ++ if (info->ops && info->ops->exit) ++ info->ops->exit(pfc); ++ return ret; + } + + static int sh_pfc_remove(struct platform_device *pdev) +@@ -412,6 +423,9 @@ static int sh_pfc_remove(struct platform_device *pdev) + #endif + sh_pfc_unregister_pinctrl(pfc); + ++ if (pfc->info->ops && pfc->info->ops->exit) ++ pfc->info->ops->exit(pfc); ++ + platform_set_drvdata(pdev, NULL); + + return 0; +diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h +index e847afbe..f02ba1dd 100644 +--- a/drivers/pinctrl/sh-pfc/core.h ++++ b/drivers/pinctrl/sh-pfc/core.h +@@ -28,6 +28,7 @@ struct sh_pfc_pinctrl; + struct sh_pfc { + struct device *dev; + const struct sh_pfc_soc_info *info; ++ void *soc_data; + spinlock_t lock; + + unsigned int num_windows; +diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h +index b1707612..830ae1ff 100644 +--- a/drivers/pinctrl/sh-pfc/sh_pfc.h ++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h +@@ -129,6 +129,8 @@ struct pinmux_range { + struct sh_pfc; + + struct sh_pfc_soc_operations { ++ int (*init)(struct sh_pfc *pfc); ++ void (*exit)(struct sh_pfc *pfc); + unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin); + void (*set_bias)(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0185-sh-pfc-sh73a0-Add-VCCQ-MC0-regulator.patch b/patches.renesas/0185-sh-pfc-sh73a0-Add-VCCQ-MC0-regulator.patch new file mode 100644 index 00000000000..66480708385 --- /dev/null +++ b/patches.renesas/0185-sh-pfc-sh73a0-Add-VCCQ-MC0-regulator.patch @@ -0,0 +1,200 @@ +From 79998aa5ef8dbec4b49324259fe9381bd81fc9e8 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Sun, 21 Apr 2013 23:26:26 +0200 +Subject: sh-pfc: sh73a0: Add VCCQ MC0 regulator + +The sh73a0 has an internal power gate on the VCCQ power supply for the +SDHI0 device that is controlled (for some strange reason) by a bit in a +PFC register. This feature should be exposed as a regulator. + +As the same register is also used for pin control purposes there is no +way to achieve atomic read/write sequences with a separate regulator +driver. We thus need to implement the regulator here. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> +Acked-by: Linus Walleij <linus.walleij@linaro.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit ea770ad2ec054e26076d677f2e87add53712941c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/Kconfig | 1 + + drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 134 ++++++++++++++++++++++++++++++++++++ + 2 files changed, 135 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig +index 32161c4f..636a882b 100644 +--- a/drivers/pinctrl/sh-pfc/Kconfig ++++ b/drivers/pinctrl/sh-pfc/Kconfig +@@ -72,6 +72,7 @@ config PINCTRL_PFC_SH73A0 + def_bool y + depends on ARCH_SH73A0 + select PINCTRL_SH_PFC ++ select REGULATOR + + config PINCTRL_PFC_SH7720 + def_bool y +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +index 587f7772..b7837248 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +@@ -20,7 +20,11 @@ + */ + #include <linux/io.h> + #include <linux/kernel.h> ++#include <linux/module.h> + #include <linux/pinctrl/pinconf-generic.h> ++#include <linux/regulator/driver.h> ++#include <linux/regulator/machine.h> ++#include <linux/slab.h> + + #include <mach/sh73a0.h> + #include <mach/irqs.h> +@@ -3888,6 +3892,92 @@ static const struct pinmux_irq pinmux_irqs[] = { + PINMUX_IRQ(EXT_IRQ16L(9), 308), + }; + ++/* ----------------------------------------------------------------------------- ++ * VCCQ MC0 regulator ++ */ ++ ++static void sh73a0_vccq_mc0_endisable(struct regulator_dev *reg, bool enable) ++{ ++ struct sh_pfc *pfc = reg->reg_data; ++ void __iomem *addr = pfc->window[1].virt + 4; ++ unsigned long flags; ++ u32 value; ++ ++ spin_lock_irqsave(&pfc->lock, flags); ++ ++ value = ioread32(addr); ++ ++ if (enable) ++ value |= BIT(28); ++ else ++ value &= ~BIT(28); ++ ++ iowrite32(value, addr); ++ ++ spin_unlock_irqrestore(&pfc->lock, flags); ++} ++ ++static int sh73a0_vccq_mc0_enable(struct regulator_dev *reg) ++{ ++ sh73a0_vccq_mc0_endisable(reg, true); ++ return 0; ++} ++ ++static int sh73a0_vccq_mc0_disable(struct regulator_dev *reg) ++{ ++ sh73a0_vccq_mc0_endisable(reg, false); ++ return 0; ++} ++ ++static int sh73a0_vccq_mc0_is_enabled(struct regulator_dev *reg) ++{ ++ struct sh_pfc *pfc = reg->reg_data; ++ void __iomem *addr = pfc->window[1].virt + 4; ++ unsigned long flags; ++ u32 value; ++ ++ spin_lock_irqsave(&pfc->lock, flags); ++ value = ioread32(addr); ++ spin_unlock_irqrestore(&pfc->lock, flags); ++ ++ return !!(value & BIT(28)); ++} ++ ++static int sh73a0_vccq_mc0_get_voltage(struct regulator_dev *reg) ++{ ++ return 3300000; ++} ++ ++static struct regulator_ops sh73a0_vccq_mc0_ops = { ++ .enable = sh73a0_vccq_mc0_enable, ++ .disable = sh73a0_vccq_mc0_disable, ++ .is_enabled = sh73a0_vccq_mc0_is_enabled, ++ .get_voltage = sh73a0_vccq_mc0_get_voltage, ++}; ++ ++static const struct regulator_desc sh73a0_vccq_mc0_desc = { ++ .owner = THIS_MODULE, ++ .name = "vccq_mc0", ++ .type = REGULATOR_VOLTAGE, ++ .ops = &sh73a0_vccq_mc0_ops, ++}; ++ ++static struct regulator_consumer_supply sh73a0_vccq_mc0_consumers[] = { ++ REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"), ++}; ++ ++static const struct regulator_init_data sh73a0_vccq_mc0_init_data = { ++ .constraints = { ++ .valid_ops_mask = REGULATOR_CHANGE_STATUS, ++ }, ++ .num_consumer_supplies = ARRAY_SIZE(sh73a0_vccq_mc0_consumers), ++ .consumer_supplies = sh73a0_vccq_mc0_consumers, ++}; ++ ++/* ----------------------------------------------------------------------------- ++ * Pin bias ++ */ ++ + #define PORTnCR_PULMD_OFF (0 << 6) + #define PORTnCR_PULMD_DOWN (2 << 6) + #define PORTnCR_PULMD_UP (3 << 6) +@@ -3934,7 +4024,51 @@ static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + iowrite8(value, addr); + } + ++/* ----------------------------------------------------------------------------- ++ * SoC information ++ */ ++ ++struct sh73a0_pinmux_data { ++ struct regulator_dev *vccq_mc0; ++}; ++ ++static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc) ++{ ++ struct sh73a0_pinmux_data *data; ++ struct regulator_config cfg = { }; ++ int ret; ++ ++ data = devm_kzalloc(pfc->dev, sizeof(*data), GFP_KERNEL); ++ if (data == NULL) ++ return -ENOMEM; ++ ++ cfg.dev = pfc->dev; ++ cfg.init_data = &sh73a0_vccq_mc0_init_data; ++ cfg.driver_data = pfc; ++ ++ data->vccq_mc0 = regulator_register(&sh73a0_vccq_mc0_desc, &cfg); ++ if (IS_ERR(data->vccq_mc0)) { ++ ret = PTR_ERR(data->vccq_mc0); ++ dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n", ++ ret); ++ return ret; ++ } ++ ++ pfc->soc_data = data; ++ ++ return 0; ++} ++ ++static void sh73a0_pinmux_soc_exit(struct sh_pfc *pfc) ++{ ++ struct sh73a0_pinmux_data *data = pfc->soc_data; ++ ++ regulator_unregister(data->vccq_mc0); ++} ++ + static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = { ++ .init = sh73a0_pinmux_soc_init, ++ .exit = sh73a0_pinmux_soc_exit, + .get_bias = sh73a0_pinmux_get_bias, + .set_bias = sh73a0_pinmux_set_bias, + }; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0186-ARM-shmobile-kzm9g-Remove-the-VCCQ-MC0-function-GPIO.patch b/patches.renesas/0186-ARM-shmobile-kzm9g-Remove-the-VCCQ-MC0-function-GPIO.patch new file mode 100644 index 00000000000..33e34ba4dbd --- /dev/null +++ b/patches.renesas/0186-ARM-shmobile-kzm9g-Remove-the-VCCQ-MC0-function-GPIO.patch @@ -0,0 +1,34 @@ +From 1889908a588518325efeb74cd3bd20decdf2100a Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Sun, 21 Apr 2013 23:29:14 +0200 +Subject: ARM: shmobile: kzm9g: Remove the VCCQ MC0 function GPIO + +The VCCQ MC0 power gate is now controlled by a regulator registered by +the PFC driver. Remove the corresponding function GPIO. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Acked-by: Linus Walleij <linus.walleij@linaro.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 261e4e1d8e517c32a408350455fdf200c7dd8407) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-kzm9g.c | 3 --- + 1 file changed, 3 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c +index e6b775a1..fc4ca9be 100644 +--- a/arch/arm/mach-shmobile/board-kzm9g.c ++++ b/arch/arm/mach-shmobile/board-kzm9g.c +@@ -788,9 +788,6 @@ static void __init kzm_init(void) + /* Touchscreen */ + gpio_request_one(223, GPIOF_IN, NULL); /* IRQ8 */ + +- /* enable SD */ +- gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL); +- + #ifdef CONFIG_CACHE_L2X0 + /* Early BRESP enable, Shared attribute override enable, 64K*8way */ + l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0187-ARM-shmobile-kzm9g-reference-Remove-the-VCCQ-MC0-fun.patch b/patches.renesas/0187-ARM-shmobile-kzm9g-reference-Remove-the-VCCQ-MC0-fun.patch new file mode 100644 index 00000000000..5479e67de39 --- /dev/null +++ b/patches.renesas/0187-ARM-shmobile-kzm9g-reference-Remove-the-VCCQ-MC0-fun.patch @@ -0,0 +1,32 @@ +From f790835fb9bd35966664d3e88dfc9aa4d9a7cb07 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Sun, 21 Apr 2013 23:29:14 +0200 +Subject: ARM: shmobile: kzm9g-reference: Remove the VCCQ MC0 function GPIO + +The VCCQ MC0 power gate is now controlled by a regulator registered by +the PFC driver. Remove the corresponding function GPIO. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Acked-by: Linus Walleij <linus.walleij@linaro.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 7af2aec18af6bebd78302b797ef081ddb36a4982) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-kzm9g-reference.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c +index aefa50d3..44055fe8 100644 +--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c ++++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c +@@ -79,7 +79,6 @@ static void __init kzm_init(void) + sh73a0_pinmux_init(); + + /* enable SD */ +- gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL); + gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */ + + gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0188-sh-pfc-r8a7778-add-USB-pin-groups.patch b/patches.renesas/0188-sh-pfc-r8a7778-add-USB-pin-groups.patch new file mode 100644 index 00000000000..4f0099972e0 --- /dev/null +++ b/patches.renesas/0188-sh-pfc-r8a7778-add-USB-pin-groups.patch @@ -0,0 +1,80 @@ +From 324a377b25c8f48279298c74f52dcd864e742786 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Wed, 8 May 2013 23:12:47 +0000 +Subject: sh-pfc: r8a7778: add USB pin groups + +Add USB0/1 PENC/USB_OVC pin groups to R8A7778 PFC driver. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Acked-by: Linus Walleij <linus.walleij@linaro.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 5cee53b6fc59c60c7fb7328c0a339dd37e6a5105) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 28 ++++++++++++++++++++++++++++ + 1 file changed, 28 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +index 15295a5b..1f692e5b 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +@@ -1501,6 +1501,18 @@ SDHI_PFC_WPPN(sdhi2_wp_a, SD2_WP_A); + SDHI_PFC_PINS(sdhi2_wp_b, RCAR_GP_PIN(3, 28)); + SDHI_PFC_WPPN(sdhi2_wp_b, SD2_WP_B); + ++/* - USB0 ------------------------------------------------------------------- */ ++SH_PFC_PINS(usb0, RCAR_GP_PIN(0, 1)); ++SH_PFC_MUX1(usb0, PENC0); ++SH_PFC_PINS(usb0_ovc, RCAR_GP_PIN(0, 3)); ++SH_PFC_MUX1(usb0_ovc, USB_OVC0); ++ ++/* - USB1 ------------------------------------------------------------------- */ ++SH_PFC_PINS(usb1, RCAR_GP_PIN(0, 2)); ++SH_PFC_MUX1(usb1, PENC1); ++SH_PFC_PINS(usb1_ovc, RCAR_GP_PIN(0, 4)); ++SH_PFC_MUX1(usb1_ovc, USB_OVC1); ++ + static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(hscif0_data_a), + SH_PFC_PIN_GROUP(hscif0_data_b), +@@ -1570,6 +1582,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(sdhi2_data4_b), + SH_PFC_PIN_GROUP(sdhi2_wp_a), + SH_PFC_PIN_GROUP(sdhi2_wp_b), ++ SH_PFC_PIN_GROUP(usb0), ++ SH_PFC_PIN_GROUP(usb0_ovc), ++ SH_PFC_PIN_GROUP(usb1), ++ SH_PFC_PIN_GROUP(usb1_ovc), + }; + + static const char * const hscif0_groups[] = { +@@ -1677,6 +1693,16 @@ static const char * const sdhi2_groups[] = { + "sdhi2_wp_b", + }; + ++static const char * const usb0_groups[] = { ++ "usb0", ++ "usb0_ovc", ++}; ++ ++static const char * const usb1_groups[] = { ++ "usb1", ++ "usb1_ovc", ++}; ++ + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), +@@ -1690,6 +1716,8 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), ++ SH_PFC_FUNCTION(usb0), ++ SH_PFC_FUNCTION(usb1), + }; + + static struct pinmux_cfg_reg pinmux_config_regs[] = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0189-sh-pfc-sh73a0-Add-TPU-pin-groups-and-functions.patch b/patches.renesas/0189-sh-pfc-sh73a0-Add-TPU-pin-groups-and-functions.patch new file mode 100644 index 00000000000..47e85ffc615 --- /dev/null +++ b/patches.renesas/0189-sh-pfc-sh73a0-Add-TPU-pin-groups-and-functions.patch @@ -0,0 +1,261 @@ +From 715482e00910ab9a8cfac75de1a324cbab60bab8 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Wed, 24 Apr 2013 01:07:16 +0200 +Subject: sh-pfc: sh73a0: Add TPU pin groups and functions + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 5da4eb049de803c7e9b81afbadf9f2e70e34dcae) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 213 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 213 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +index b7837248..78f7ae80 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +@@ -2542,6 +2542,157 @@ static const unsigned int sdhi2_ctrl_pins[] = { + static const unsigned int sdhi2_ctrl_mux[] = { + SDHICMD2_MARK, SDHICLK2_MARK, + }; ++/* - TPU0 ------------------------------------------------------------------- */ ++static const unsigned int tpu0_to0_pins[] = { ++ /* TO */ ++ 55, ++}; ++static const unsigned int tpu0_to0_mux[] = { ++ TPU0TO0_MARK, ++}; ++static const unsigned int tpu0_to1_pins[] = { ++ /* TO */ ++ 59, ++}; ++static const unsigned int tpu0_to1_mux[] = { ++ TPU0TO1_MARK, ++}; ++static const unsigned int tpu0_to2_pins[] = { ++ /* TO */ ++ 140, ++}; ++static const unsigned int tpu0_to2_mux[] = { ++ TPU0TO2_MARK, ++}; ++static const unsigned int tpu0_to3_pins[] = { ++ /* TO */ ++ 141, ++}; ++static const unsigned int tpu0_to3_mux[] = { ++ TPU0TO3_MARK, ++}; ++/* - TPU1 ------------------------------------------------------------------- */ ++static const unsigned int tpu1_to0_pins[] = { ++ /* TO */ ++ 246, ++}; ++static const unsigned int tpu1_to0_mux[] = { ++ TPU1TO0_MARK, ++}; ++static const unsigned int tpu1_to1_0_pins[] = { ++ /* TO */ ++ 28, ++}; ++static const unsigned int tpu1_to1_0_mux[] = { ++ PORT28_TPU1TO1_MARK, ++}; ++static const unsigned int tpu1_to1_1_pins[] = { ++ /* TO */ ++ 29, ++}; ++static const unsigned int tpu1_to1_1_mux[] = { ++ PORT29_TPU1TO1_MARK, ++}; ++static const unsigned int tpu1_to2_pins[] = { ++ /* TO */ ++ 153, ++}; ++static const unsigned int tpu1_to2_mux[] = { ++ TPU1TO2_MARK, ++}; ++static const unsigned int tpu1_to3_pins[] = { ++ /* TO */ ++ 145, ++}; ++static const unsigned int tpu1_to3_mux[] = { ++ TPU1TO3_MARK, ++}; ++/* - TPU2 ------------------------------------------------------------------- */ ++static const unsigned int tpu2_to0_pins[] = { ++ /* TO */ ++ 248, ++}; ++static const unsigned int tpu2_to0_mux[] = { ++ TPU2TO0_MARK, ++}; ++static const unsigned int tpu2_to1_pins[] = { ++ /* TO */ ++ 197, ++}; ++static const unsigned int tpu2_to1_mux[] = { ++ TPU2TO1_MARK, ++}; ++static const unsigned int tpu2_to2_pins[] = { ++ /* TO */ ++ 50, ++}; ++static const unsigned int tpu2_to2_mux[] = { ++ TPU2TO2_MARK, ++}; ++static const unsigned int tpu2_to3_pins[] = { ++ /* TO */ ++ 51, ++}; ++static const unsigned int tpu2_to3_mux[] = { ++ TPU2TO3_MARK, ++}; ++/* - TPU3 ------------------------------------------------------------------- */ ++static const unsigned int tpu3_to0_pins[] = { ++ /* TO */ ++ 163, ++}; ++static const unsigned int tpu3_to0_mux[] = { ++ TPU3TO0_MARK, ++}; ++static const unsigned int tpu3_to1_pins[] = { ++ /* TO */ ++ 247, ++}; ++static const unsigned int tpu3_to1_mux[] = { ++ TPU3TO1_MARK, ++}; ++static const unsigned int tpu3_to2_pins[] = { ++ /* TO */ ++ 54, ++}; ++static const unsigned int tpu3_to2_mux[] = { ++ TPU3TO2_MARK, ++}; ++static const unsigned int tpu3_to3_pins[] = { ++ /* TO */ ++ 53, ++}; ++static const unsigned int tpu3_to3_mux[] = { ++ TPU3TO3_MARK, ++}; ++/* - TPU4 ------------------------------------------------------------------- */ ++static const unsigned int tpu4_to0_pins[] = { ++ /* TO */ ++ 241, ++}; ++static const unsigned int tpu4_to0_mux[] = { ++ TPU4TO0_MARK, ++}; ++static const unsigned int tpu4_to1_pins[] = { ++ /* TO */ ++ 199, ++}; ++static const unsigned int tpu4_to1_mux[] = { ++ TPU4TO1_MARK, ++}; ++static const unsigned int tpu4_to2_pins[] = { ++ /* TO */ ++ 58, ++}; ++static const unsigned int tpu4_to2_mux[] = { ++ TPU4TO2_MARK, ++}; ++static const unsigned int tpu4_to3_pins[] = { ++ /* TO */ ++}; ++static const unsigned int tpu4_to3_mux[] = { ++ TPU4TO3_MARK, ++}; + /* - USB -------------------------------------------------------------------- */ + static const unsigned int usb_vbus_pins[] = { + /* VBUS */ +@@ -2693,6 +2844,27 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_ctrl), ++ SH_PFC_PIN_GROUP(tpu0_to0), ++ SH_PFC_PIN_GROUP(tpu0_to1), ++ SH_PFC_PIN_GROUP(tpu0_to2), ++ SH_PFC_PIN_GROUP(tpu0_to3), ++ SH_PFC_PIN_GROUP(tpu1_to0), ++ SH_PFC_PIN_GROUP(tpu1_to1_0), ++ SH_PFC_PIN_GROUP(tpu1_to1_1), ++ SH_PFC_PIN_GROUP(tpu1_to2), ++ SH_PFC_PIN_GROUP(tpu1_to3), ++ SH_PFC_PIN_GROUP(tpu2_to0), ++ SH_PFC_PIN_GROUP(tpu2_to1), ++ SH_PFC_PIN_GROUP(tpu2_to2), ++ SH_PFC_PIN_GROUP(tpu2_to3), ++ SH_PFC_PIN_GROUP(tpu3_to0), ++ SH_PFC_PIN_GROUP(tpu3_to1), ++ SH_PFC_PIN_GROUP(tpu3_to2), ++ SH_PFC_PIN_GROUP(tpu3_to3), ++ SH_PFC_PIN_GROUP(tpu4_to0), ++ SH_PFC_PIN_GROUP(tpu4_to1), ++ SH_PFC_PIN_GROUP(tpu4_to2), ++ SH_PFC_PIN_GROUP(tpu4_to3), + SH_PFC_PIN_GROUP(usb_vbus), + }; + +@@ -2912,6 +3084,42 @@ static const char * const usb_groups[] = { + "usb_vbus", + }; + ++static const char * const tpu0_groups[] = { ++ "tpu0_to0", ++ "tpu0_to1", ++ "tpu0_to2", ++ "tpu0_to3", ++}; ++ ++static const char * const tpu1_groups[] = { ++ "tpu1_to0", ++ "tpu1_to1_0", ++ "tpu1_to1_1", ++ "tpu1_to2", ++ "tpu1_to3", ++}; ++ ++static const char * const tpu2_groups[] = { ++ "tpu2_to0", ++ "tpu2_to1", ++ "tpu2_to2", ++ "tpu2_to3", ++}; ++ ++static const char * const tpu3_groups[] = { ++ "tpu3_to0", ++ "tpu3_to1", ++ "tpu3_to2", ++ "tpu3_to3", ++}; ++ ++static const char * const tpu4_groups[] = { ++ "tpu4_to0", ++ "tpu4_to1", ++ "tpu4_to2", ++ "tpu4_to3", ++}; ++ + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(bsc), + SH_PFC_FUNCTION(fsia), +@@ -2937,6 +3145,11 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), ++ SH_PFC_FUNCTION(tpu0), ++ SH_PFC_FUNCTION(tpu1), ++ SH_PFC_FUNCTION(tpu2), ++ SH_PFC_FUNCTION(tpu3), ++ SH_PFC_FUNCTION(tpu4), + SH_PFC_FUNCTION(usb), + }; + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0190-sh-pfc-r8a7740-Add-TPU-pin-groups-and-functions.patch b/patches.renesas/0190-sh-pfc-r8a7740-Add-TPU-pin-groups-and-functions.patch new file mode 100644 index 00000000000..369bef902fa --- /dev/null +++ b/patches.renesas/0190-sh-pfc-r8a7740-Add-TPU-pin-groups-and-functions.patch @@ -0,0 +1,98 @@ +From 1c15fbe8147fac5113bba0252297dedb6221c983 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 23 Apr 2013 16:04:07 +0200 +Subject: sh-pfc: r8a7740: Add TPU pin groups and functions + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit c2ad27e63dac83af4d6acd7af2f424497f1d4c74) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 50 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 50 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +index e5ef587a..f6ea47c4 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +@@ -2745,6 +2745,42 @@ static const unsigned int sdhi2_wp_1_pins[] = { + static const unsigned int sdhi2_wp_1_mux[] = { + SDHI2_WP_PORT25_MARK, + }; ++/* - TPU0 ------------------------------------------------------------------- */ ++static const unsigned int tpu0_to0_pins[] = { ++ /* TO */ ++ 23, ++}; ++static const unsigned int tpu0_to0_mux[] = { ++ TPU0TO0_MARK, ++}; ++static const unsigned int tpu0_to1_pins[] = { ++ /* TO */ ++ 21, ++}; ++static const unsigned int tpu0_to1_mux[] = { ++ TPU0TO1_MARK, ++}; ++static const unsigned int tpu0_to2_0_pins[] = { ++ /* TO */ ++ 66, ++}; ++static const unsigned int tpu0_to2_0_mux[] = { ++ TPU0TO2_PORT66_MARK, ++}; ++static const unsigned int tpu0_to2_1_pins[] = { ++ /* TO */ ++ 202, ++}; ++static const unsigned int tpu0_to2_1_mux[] = { ++ TPU0TO2_PORT202_MARK, ++}; ++static const unsigned int tpu0_to3_pins[] = { ++ /* TO */ ++ 180, ++}; ++static const unsigned int tpu0_to3_mux[] = { ++ TPU0TO3_MARK, ++}; + + static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(bsc_data8), +@@ -2926,6 +2962,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(sdhi2_wp_0), + SH_PFC_PIN_GROUP(sdhi2_cd_1), + SH_PFC_PIN_GROUP(sdhi2_wp_1), ++ SH_PFC_PIN_GROUP(tpu0_to0), ++ SH_PFC_PIN_GROUP(tpu0_to1), ++ SH_PFC_PIN_GROUP(tpu0_to2_0), ++ SH_PFC_PIN_GROUP(tpu0_to2_1), ++ SH_PFC_PIN_GROUP(tpu0_to3), + }; + + static const char * const bsc_groups[] = { +@@ -3176,6 +3217,14 @@ static const char * const sdhi2_groups[] = { + "sdhi2_wp_1", + }; + ++static const char * const tpu0_groups[] = { ++ "tpu0_to0", ++ "tpu0_to1", ++ "tpu0_to2_0", ++ "tpu0_to2_1", ++ "tpu0_to3", ++}; ++ + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(bsc), + SH_PFC_FUNCTION(ceu0), +@@ -3200,6 +3249,7 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), ++ SH_PFC_FUNCTION(tpu0), + }; + + #undef PORTCR +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0191-sh-pfc-r8a7790-Add-TPU-pin-groups-and-functions.patch b/patches.renesas/0191-sh-pfc-r8a7790-Add-TPU-pin-groups-and-functions.patch new file mode 100644 index 00000000000..a7aa625e9e0 --- /dev/null +++ b/patches.renesas/0191-sh-pfc-r8a7790-Add-TPU-pin-groups-and-functions.patch @@ -0,0 +1,89 @@ +From 2f7aa516ddacb03c9926e3a57b2e28aef5b98aa8 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Wed, 24 Apr 2013 13:20:17 +0200 +Subject: sh-pfc: r8a7790: Add TPU pin groups and functions + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 682e05a14fb424160bd978bca4e6ba1dcc919f21) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 41 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 41 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +index 1656915a..5be29995 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -2342,6 +2342,35 @@ static const unsigned int scifb2_data_c_pins[] = { + static const unsigned int scifb2_data_c_mux[] = { + SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK, + }; ++/* - TPU0 ------------------------------------------------------------------- */ ++static const unsigned int tpu0_to0_pins[] = { ++ /* TO */ ++ RCAR_GP_PIN(0, 20), ++}; ++static const unsigned int tpu0_to0_mux[] = { ++ TPU0TO0_MARK, ++}; ++static const unsigned int tpu0_to1_pins[] = { ++ /* TO */ ++ RCAR_GP_PIN(0, 21), ++}; ++static const unsigned int tpu0_to1_mux[] = { ++ TPU0TO1_MARK, ++}; ++static const unsigned int tpu0_to2_pins[] = { ++ /* TO */ ++ RCAR_GP_PIN(0, 22), ++}; ++static const unsigned int tpu0_to2_mux[] = { ++ TPU0TO2_MARK, ++}; ++static const unsigned int tpu0_to3_pins[] = { ++ /* TO */ ++ RCAR_GP_PIN(0, 23), ++}; ++static const unsigned int tpu0_to3_mux[] = { ++ TPU0TO3_MARK, ++}; + + static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(eth_link), +@@ -2416,6 +2445,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(scifb2_clk_b), + SH_PFC_PIN_GROUP(scifb2_ctrl_b), + SH_PFC_PIN_GROUP(scifb2_data_c), ++ SH_PFC_PIN_GROUP(tpu0_to0), ++ SH_PFC_PIN_GROUP(tpu0_to1), ++ SH_PFC_PIN_GROUP(tpu0_to2), ++ SH_PFC_PIN_GROUP(tpu0_to3), + }; + + static const char * const eth_groups[] = { +@@ -2520,6 +2553,13 @@ static const char * const scifb2_groups[] = { + "scifb2_data_c", + }; + ++static const char * const tpu0_groups[] = { ++ "tpu0_to0", ++ "tpu0_to1", ++ "tpu0_to2", ++ "tpu0_to3", ++}; ++ + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(eth), + SH_PFC_FUNCTION(intc), +@@ -2531,6 +2571,7 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(scifb0), + SH_PFC_FUNCTION(scifb1), + SH_PFC_FUNCTION(scifb2), ++ SH_PFC_FUNCTION(tpu0), + }; + + static struct pinmux_cfg_reg pinmux_config_regs[] = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0192-sh-pfc-sh73a0-Remove-function-GPIOs.patch b/patches.renesas/0192-sh-pfc-sh73a0-Remove-function-GPIOs.patch new file mode 100644 index 00000000000..5a3a58bd5c8 --- /dev/null +++ b/patches.renesas/0192-sh-pfc-sh73a0-Remove-function-GPIOs.patch @@ -0,0 +1,438 @@ +From 4c5c29c9dd4f82f79574938bb174f057c9011ef6 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Wed, 24 Apr 2013 01:31:10 +0200 +Subject: sh-pfc: sh73a0: Remove function GPIOs + +No sh73a0 platform use the function GPIOs API. Remove it. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit a27c5cd1a08cc95c914900cc20277d2f39e02496) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 395 ------------------------------------ + 1 file changed, 395 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +index 78f7ae80..7956df58 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +@@ -26,7 +26,6 @@ + #include <linux/regulator/machine.h> + #include <linux/slab.h> + +-#include <mach/sh73a0.h> + #include <mach/irqs.h> + + #include "core.h" +@@ -3153,397 +3152,6 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(usb), + }; + +-#define PINMUX_FN_BASE GPIO_FN_GPI0 +- +-static const struct pinmux_func pinmux_func_gpios[] = { +- /* Table 25-1 (Functions 0-7) */ +- GPIO_FN(GPI0), +- GPIO_FN(GPI1), +- GPIO_FN(GPI2), +- GPIO_FN(GPI3), +- GPIO_FN(GPI4), +- GPIO_FN(GPI5), +- GPIO_FN(GPI6), +- GPIO_FN(GPI7), +- GPIO_FN(GPO7), \ +- GPIO_FN(MFG0_OUT2), +- GPIO_FN(GPO6), \ +- GPIO_FN(MFG1_OUT2), +- GPIO_FN(GPO5), \ +- GPIO_FN(PORT16_VIO_CKOR), +- GPIO_FN(PORT19_VIO_CKO2), +- GPIO_FN(GPO0), +- GPIO_FN(GPO1), +- GPIO_FN(GPO2), \ +- GPIO_FN(STATUS0), +- GPIO_FN(GPO3), \ +- GPIO_FN(STATUS1), +- GPIO_FN(GPO4), \ +- GPIO_FN(STATUS2), +- GPIO_FN(VINT), +- GPIO_FN(TCKON), +- GPIO_FN(XDVFS1), \ +- GPIO_FN(MFG0_OUT1), \ +- GPIO_FN(PORT27_IROUT), +- GPIO_FN(XDVFS2), \ +- GPIO_FN(PORT28_TPU1TO1), +- GPIO_FN(SIM_RST), \ +- GPIO_FN(PORT29_TPU1TO1), +- GPIO_FN(SIM_CLK), \ +- GPIO_FN(PORT30_VIO_CKOR), +- GPIO_FN(SIM_D), \ +- GPIO_FN(PORT31_IROUT), +- GPIO_FN(XWUP), +- GPIO_FN(VACK), +- GPIO_FN(XTAL1L), +- GPIO_FN(PORT49_IROUT), \ +- GPIO_FN(BBIF2_TSYNC2), \ +- GPIO_FN(TPU2TO2), \ +- +- GPIO_FN(BBIF2_TSCK2), \ +- GPIO_FN(TPU2TO3), \ +- GPIO_FN(BBIF2_TXD2), +- GPIO_FN(TPU3TO3), \ +- GPIO_FN(TPU3TO2), \ +- GPIO_FN(TPU0TO0), +- GPIO_FN(A0), \ +- GPIO_FN(BS_), +- GPIO_FN(A12), \ +- GPIO_FN(TPU4TO2), +- GPIO_FN(A13), \ +- GPIO_FN(TPU0TO1), +- GPIO_FN(A14), \ +- GPIO_FN(A15), \ +- GPIO_FN(A16), \ +- GPIO_FN(MSIOF0_SS1), +- GPIO_FN(A17), \ +- GPIO_FN(MSIOF0_TSYNC), +- GPIO_FN(A18), \ +- GPIO_FN(MSIOF0_TSCK), +- GPIO_FN(A19), \ +- GPIO_FN(MSIOF0_TXD), +- GPIO_FN(A20), \ +- GPIO_FN(MSIOF0_RSCK), +- GPIO_FN(A21), \ +- GPIO_FN(MSIOF0_RSYNC), +- GPIO_FN(A22), \ +- GPIO_FN(MSIOF0_MCK0), +- GPIO_FN(A23), \ +- GPIO_FN(MSIOF0_MCK1), +- GPIO_FN(A24), \ +- GPIO_FN(MSIOF0_RXD), +- GPIO_FN(A25), \ +- GPIO_FN(MSIOF0_SS2), +- GPIO_FN(A26), \ +- GPIO_FN(FCE1_), +- GPIO_FN(DACK0), +- GPIO_FN(FCE0_), \ +- GPIO_FN(WAIT_), \ +- GPIO_FN(DREQ0), +- GPIO_FN(FRB), +- GPIO_FN(CKO), +- GPIO_FN(NBRSTOUT_), +- GPIO_FN(NBRST_), +- GPIO_FN(BBIF2_TXD), +- GPIO_FN(BBIF2_RXD), +- GPIO_FN(BBIF2_SYNC), +- GPIO_FN(BBIF2_SCK), +- GPIO_FN(MFG3_IN2), +- GPIO_FN(MFG3_IN1), +- GPIO_FN(BBIF1_SS2), \ +- GPIO_FN(MFG3_OUT1), +- GPIO_FN(HSI_RX_DATA), \ +- GPIO_FN(BBIF1_RXD), +- GPIO_FN(HSI_TX_WAKE), \ +- GPIO_FN(BBIF1_TSCK), +- GPIO_FN(HSI_TX_DATA), \ +- GPIO_FN(BBIF1_TSYNC), +- GPIO_FN(HSI_TX_READY), \ +- GPIO_FN(BBIF1_TXD), +- GPIO_FN(HSI_RX_READY), \ +- GPIO_FN(BBIF1_RSCK), \ +- GPIO_FN(HSI_RX_WAKE), \ +- GPIO_FN(BBIF1_RSYNC), \ +- GPIO_FN(HSI_RX_FLAG), \ +- GPIO_FN(BBIF1_SS1), \ +- GPIO_FN(BBIF1_FLOW), +- GPIO_FN(HSI_TX_FLAG), +- GPIO_FN(VIO_VD), \ +- GPIO_FN(VIO2_VD), \ +- +- GPIO_FN(VIO_HD), \ +- GPIO_FN(VIO2_HD), \ +- GPIO_FN(VIO_D0), \ +- GPIO_FN(PORT130_MSIOF2_RXD), \ +- GPIO_FN(VIO_D1), \ +- GPIO_FN(PORT131_MSIOF2_SS1), \ +- GPIO_FN(VIO_D2), \ +- GPIO_FN(PORT132_MSIOF2_SS2), \ +- GPIO_FN(VIO_D3), \ +- GPIO_FN(MSIOF2_TSYNC), \ +- GPIO_FN(VIO_D4), \ +- GPIO_FN(MSIOF2_TXD), \ +- GPIO_FN(VIO_D5), \ +- GPIO_FN(MSIOF2_TSCK), \ +- GPIO_FN(VIO_D6), \ +- GPIO_FN(VIO_D7), \ +- GPIO_FN(VIO_D8), \ +- GPIO_FN(VIO2_D0), \ +- GPIO_FN(VIO_D9), \ +- GPIO_FN(VIO2_D1), \ +- GPIO_FN(VIO_D10), \ +- GPIO_FN(TPU0TO2), \ +- GPIO_FN(VIO2_D2), \ +- GPIO_FN(VIO_D11), \ +- GPIO_FN(TPU0TO3), \ +- GPIO_FN(VIO2_D3), \ +- GPIO_FN(VIO_D12), \ +- GPIO_FN(VIO2_D4), \ +- GPIO_FN(VIO_D13), \ +- GPIO_FN(VIO2_D5), \ +- GPIO_FN(VIO_D14), \ +- GPIO_FN(VIO2_D6), \ +- GPIO_FN(VIO_D15), \ +- GPIO_FN(TPU1TO3), \ +- GPIO_FN(VIO2_D7), \ +- GPIO_FN(VIO_CLK), \ +- GPIO_FN(VIO2_CLK), \ +- GPIO_FN(VIO_FIELD), \ +- GPIO_FN(VIO2_FIELD), \ +- GPIO_FN(VIO_CKO), +- GPIO_FN(A27), \ +- GPIO_FN(MFG0_IN1), \ +- GPIO_FN(MFG0_IN2), +- GPIO_FN(TS_SPSYNC3), \ +- GPIO_FN(MSIOF2_RSCK), +- GPIO_FN(TS_SDAT3), \ +- GPIO_FN(MSIOF2_RSYNC), +- GPIO_FN(TPU1TO2), \ +- GPIO_FN(TS_SDEN3), \ +- GPIO_FN(PORT153_MSIOF2_SS1), +- GPIO_FN(MSIOF2_MCK0), +- GPIO_FN(MSIOF2_MCK1), +- GPIO_FN(PORT156_MSIOF2_SS2), +- GPIO_FN(PORT157_MSIOF2_RXD), +- GPIO_FN(DINT_), \ +- GPIO_FN(TS_SCK3), +- GPIO_FN(NMI), +- GPIO_FN(TPU3TO0), +- GPIO_FN(BBIF2_TSYNC1), +- GPIO_FN(BBIF2_TSCK1), +- GPIO_FN(BBIF2_TXD1), +- GPIO_FN(MFG2_OUT2), \ +- GPIO_FN(TPU2TO1), +- GPIO_FN(TPU4TO1), \ +- GPIO_FN(MFG4_OUT2), +- GPIO_FN(D16), +- GPIO_FN(D17), +- GPIO_FN(D18), +- GPIO_FN(D19), +- GPIO_FN(D20), +- GPIO_FN(D21), +- GPIO_FN(D22), +- GPIO_FN(PORT207_MSIOF0L_SS1), \ +- GPIO_FN(D23), +- GPIO_FN(PORT208_MSIOF0L_SS2), \ +- GPIO_FN(D24), +- GPIO_FN(D25), +- GPIO_FN(DREQ2), \ +- GPIO_FN(PORT210_MSIOF0L_SS1), \ +- GPIO_FN(D26), +- GPIO_FN(PORT211_MSIOF0L_SS2), \ +- GPIO_FN(D27), +- GPIO_FN(TS_SPSYNC1), \ +- GPIO_FN(MSIOF0L_MCK0), \ +- GPIO_FN(D28), +- GPIO_FN(TS_SDAT1), \ +- GPIO_FN(MSIOF0L_MCK1), \ +- GPIO_FN(D29), +- GPIO_FN(TS_SDEN1), \ +- GPIO_FN(MSIOF0L_RSCK), \ +- GPIO_FN(D30), +- GPIO_FN(TS_SCK1), \ +- GPIO_FN(MSIOF0L_RSYNC), \ +- GPIO_FN(D31), +- GPIO_FN(DACK2), \ +- GPIO_FN(MSIOF0L_TSYNC), \ +- GPIO_FN(VIO2_FIELD3), \ +- GPIO_FN(DACK3), \ +- GPIO_FN(PORT218_VIO_CKOR), +- GPIO_FN(DREQ3), \ +- GPIO_FN(MSIOF0L_TSCK), \ +- GPIO_FN(VIO2_CLK3), \ +- GPIO_FN(DREQ1), \ +- GPIO_FN(PWEN), \ +- GPIO_FN(MSIOF0L_RXD), \ +- GPIO_FN(VIO2_HD3), \ +- GPIO_FN(DACK1), \ +- GPIO_FN(OVCN), \ +- GPIO_FN(MSIOF0L_TXD), \ +- GPIO_FN(VIO2_VD3), \ +- +- GPIO_FN(OVCN2), +- GPIO_FN(EXTLP), \ +- GPIO_FN(PORT226_VIO_CKO2), +- GPIO_FN(IDIN), +- GPIO_FN(MFG1_IN1), +- GPIO_FN(MSIOF1_TXD), \ +- GPIO_FN(MSIOF1_TSYNC), \ +- GPIO_FN(MSIOF1_TSCK), \ +- GPIO_FN(MSIOF1_RXD), \ +- GPIO_FN(MSIOF1_RSCK), \ +- GPIO_FN(VIO2_CLK2), \ +- GPIO_FN(MSIOF1_RSYNC), \ +- GPIO_FN(MFG1_IN2), \ +- GPIO_FN(VIO2_VD2), \ +- GPIO_FN(MSIOF1_MCK0), \ +- GPIO_FN(MSIOF1_MCK1), \ +- GPIO_FN(MSIOF1_SS1), \ +- GPIO_FN(VIO2_FIELD2), \ +- GPIO_FN(MSIOF1_SS2), \ +- GPIO_FN(VIO2_HD2), \ +- GPIO_FN(PORT241_IROUT), \ +- GPIO_FN(MFG4_OUT1), \ +- GPIO_FN(TPU4TO0), +- GPIO_FN(MFG4_IN2), +- GPIO_FN(PORT243_VIO_CKO2), +- GPIO_FN(MFG2_IN1), \ +- GPIO_FN(MSIOF2R_RXD), +- GPIO_FN(MFG2_IN2), \ +- GPIO_FN(MSIOF2R_TXD), +- GPIO_FN(MFG1_OUT1), \ +- GPIO_FN(TPU1TO0), +- GPIO_FN(MFG3_OUT2), \ +- GPIO_FN(TPU3TO1), +- GPIO_FN(MFG2_OUT1), \ +- GPIO_FN(TPU2TO0), \ +- GPIO_FN(MSIOF2R_TSCK), +- GPIO_FN(PORT249_IROUT), \ +- GPIO_FN(MFG4_IN1), \ +- GPIO_FN(MSIOF2R_TSYNC), +- GPIO_FN(SDHICLK0), +- GPIO_FN(SDHICD0), +- GPIO_FN(SDHID0_0), +- GPIO_FN(SDHID0_1), +- GPIO_FN(SDHID0_2), +- GPIO_FN(SDHID0_3), +- GPIO_FN(SDHICMD0), +- GPIO_FN(SDHIWP0), +- GPIO_FN(SDHICLK1), +- GPIO_FN(SDHID1_0), \ +- GPIO_FN(TS_SPSYNC2), +- GPIO_FN(SDHID1_1), \ +- GPIO_FN(TS_SDAT2), +- GPIO_FN(SDHID1_2), \ +- GPIO_FN(TS_SDEN2), +- GPIO_FN(SDHID1_3), \ +- GPIO_FN(TS_SCK2), +- GPIO_FN(SDHICMD1), +- GPIO_FN(SDHICLK2), +- GPIO_FN(SDHID2_0), \ +- GPIO_FN(TS_SPSYNC4), +- GPIO_FN(SDHID2_1), \ +- GPIO_FN(TS_SDAT4), +- GPIO_FN(SDHID2_2), \ +- GPIO_FN(TS_SDEN4), +- GPIO_FN(SDHID2_3), \ +- GPIO_FN(TS_SCK4), +- GPIO_FN(SDHICMD2), +- GPIO_FN(MMCCLK0), +- GPIO_FN(MMCD0_0), +- GPIO_FN(MMCD0_1), +- GPIO_FN(MMCD0_2), +- GPIO_FN(MMCD0_3), +- GPIO_FN(MMCD0_4), \ +- GPIO_FN(TS_SPSYNC5), +- GPIO_FN(MMCD0_5), \ +- GPIO_FN(TS_SDAT5), +- GPIO_FN(MMCD0_6), \ +- GPIO_FN(TS_SDEN5), +- GPIO_FN(MMCD0_7), \ +- GPIO_FN(TS_SCK5), +- GPIO_FN(MMCCMD0), +- GPIO_FN(RESETOUTS_), \ +- GPIO_FN(EXTAL2OUT), +- GPIO_FN(MCP_WAIT__MCP_FRB), +- GPIO_FN(MCP_CKO), \ +- GPIO_FN(MMCCLK1), +- GPIO_FN(MCP_D15_MCP_NAF15), +- GPIO_FN(MCP_D14_MCP_NAF14), +- GPIO_FN(MCP_D13_MCP_NAF13), +- GPIO_FN(MCP_D12_MCP_NAF12), +- GPIO_FN(MCP_D11_MCP_NAF11), +- GPIO_FN(MCP_D10_MCP_NAF10), +- GPIO_FN(MCP_D9_MCP_NAF9), +- GPIO_FN(MCP_D8_MCP_NAF8), \ +- GPIO_FN(MMCCMD1), +- GPIO_FN(MCP_D7_MCP_NAF7), \ +- GPIO_FN(MMCD1_7), +- +- GPIO_FN(MCP_D6_MCP_NAF6), \ +- GPIO_FN(MMCD1_6), +- GPIO_FN(MCP_D5_MCP_NAF5), \ +- GPIO_FN(MMCD1_5), +- GPIO_FN(MCP_D4_MCP_NAF4), \ +- GPIO_FN(MMCD1_4), +- GPIO_FN(MCP_D3_MCP_NAF3), \ +- GPIO_FN(MMCD1_3), +- GPIO_FN(MCP_D2_MCP_NAF2), \ +- GPIO_FN(MMCD1_2), +- GPIO_FN(MCP_D1_MCP_NAF1), \ +- GPIO_FN(MMCD1_1), +- GPIO_FN(MCP_D0_MCP_NAF0), \ +- GPIO_FN(MMCD1_0), +- GPIO_FN(MCP_NBRSTOUT_), +- GPIO_FN(MCP_WE0__MCP_FWE), \ +- GPIO_FN(MCP_RDWR_MCP_FWE), +- +- /* MSEL2 special cases */ +- GPIO_FN(TSIF2_TS_XX1), +- GPIO_FN(TSIF2_TS_XX2), +- GPIO_FN(TSIF2_TS_XX3), +- GPIO_FN(TSIF2_TS_XX4), +- GPIO_FN(TSIF2_TS_XX5), +- GPIO_FN(TSIF1_TS_XX1), +- GPIO_FN(TSIF1_TS_XX2), +- GPIO_FN(TSIF1_TS_XX3), +- GPIO_FN(TSIF1_TS_XX4), +- GPIO_FN(TSIF1_TS_XX5), +- GPIO_FN(TSIF0_TS_XX1), +- GPIO_FN(TSIF0_TS_XX2), +- GPIO_FN(TSIF0_TS_XX3), +- GPIO_FN(TSIF0_TS_XX4), +- GPIO_FN(TSIF0_TS_XX5), +- GPIO_FN(MST1_TS_XX1), +- GPIO_FN(MST1_TS_XX2), +- GPIO_FN(MST1_TS_XX3), +- GPIO_FN(MST1_TS_XX4), +- GPIO_FN(MST1_TS_XX5), +- GPIO_FN(MST0_TS_XX1), +- GPIO_FN(MST0_TS_XX2), +- GPIO_FN(MST0_TS_XX3), +- GPIO_FN(MST0_TS_XX4), +- GPIO_FN(MST0_TS_XX5), +- +- /* MSEL3 special cases */ +- GPIO_FN(SDHI0_VCCQ_MC0_ON), +- GPIO_FN(SDHI0_VCCQ_MC0_OFF), +- GPIO_FN(DEBUG_MON_VIO), +- GPIO_FN(DEBUG_MON_LCDD), +- GPIO_FN(LCDC_LCDC0), +- GPIO_FN(LCDC_LCDC1), +- +- /* MSEL4 special cases */ +- GPIO_FN(IRQ9_MEM_INT), +- GPIO_FN(IRQ9_MCP_INT), +- GPIO_FN(A11), +- GPIO_FN(TPU4TO3), +- GPIO_FN(RESETA_N_PU_ON), +- GPIO_FN(RESETA_N_PU_OFF), +- GPIO_FN(EDBGREQ_PD), +- GPIO_FN(EDBGREQ_PU), +-}; +- + #undef PORTCR + #define PORTCR(nr, reg) \ + { \ +@@ -4303,9 +3911,6 @@ const struct sh_pfc_soc_info sh73a0_pinmux_info = { + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + +- .func_gpios = pinmux_func_gpios, +- .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), +- + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0193-sh-pfc-r8a7778-add-VIN-pin-groups.patch b/patches.renesas/0193-sh-pfc-r8a7778-add-VIN-pin-groups.patch new file mode 100644 index 00000000000..a111d56e2ee --- /dev/null +++ b/patches.renesas/0193-sh-pfc-r8a7778-add-VIN-pin-groups.patch @@ -0,0 +1,131 @@ +From 9318cdd9451c644f90ffd629a62ad21088d6cbf8 Mon Sep 17 00:00:00 2001 +From: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Date: Thu, 9 May 2013 03:14:35 +0400 +Subject: sh-pfc: r8a7778: add VIN pin groups + +Add VIN DATA[0:8]/CLK/HSYNC/VSYNC pin groups to R8A7778 PFC driver. +While at it, add SH_PFC_MUX8() macro for 8-bit data busses. + +Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +[Sergei: updated the copyrights, added SH_PFC_MUX8() macro for 8-bit data bus, +made use of SH_PFC_*() macros to define the pin groups.] +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Acked-by: Linus Walleij <linus.walleij@linaro.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit 2d7cd3987056e958af32962d74441dddd70cb8f6) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 60 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 60 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +index 1f692e5b..e518c33d 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +@@ -3,6 +3,7 @@ + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> ++ * Copyright (C) 2013 Cogent Embedded, Inc. + * + * based on + * Copyright (C) 2011 Renesas Solutions Corp. +@@ -1316,6 +1317,11 @@ static struct sh_pfc_pin pinmux_pins[] = { + #define SH_PFC_MUX4(name, arg1, arg2, arg3, arg4) \ + static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, \ + arg3##_MARK, arg4##_MARK } ++#define SH_PFC_MUX8(name, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8) \ ++ static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, \ ++ arg3##_MARK, arg4##_MARK, \ ++ arg5##_MARK, arg6##_MARK, \ ++ arg7##_MARK, arg8##_MARK, } + + /* - SCIF macro ------------------------------------------------------------- */ + #define SCIF_PFC_PIN(name, args...) SH_PFC_PINS(name, args) +@@ -1513,6 +1519,40 @@ SH_PFC_MUX1(usb1, PENC1); + SH_PFC_PINS(usb1_ovc, RCAR_GP_PIN(0, 4)); + SH_PFC_MUX1(usb1_ovc, USB_OVC1); + ++/* - VIN macros ------------------------------------------------------------- */ ++#define VIN_PFC_PINS(name, args...) SH_PFC_PINS(name, args) ++#define VIN_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7) \ ++ SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7) ++#define VIN_PFC_CLK(name, clk) SH_PFC_MUX1(name, clk) ++#define VIN_PFC_SYNC(name, hsync, vsync) SH_PFC_MUX2(name, hsync, vsync) ++ ++/* - VIN0 ------------------------------------------------------------------- */ ++VIN_PFC_PINS(vin0_data8, RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 30), ++ RCAR_GP_PIN(3, 31), RCAR_GP_PIN(4, 0), ++ RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), ++ RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4)); ++VIN_PFC_DAT8(vin0_data8, VI0_DATA0_VI0_B0, VI0_DATA1_VI0_B1, ++ VI0_DATA2_VI0_B2, VI0_DATA3_VI0_B3, ++ VI0_DATA4_VI0_B4, VI0_DATA5_VI0_B5, ++ VI0_DATA6_VI0_G0, VI0_DATA7_VI0_G1); ++VIN_PFC_PINS(vin0_clk, RCAR_GP_PIN(3, 24)); ++VIN_PFC_CLK(vin0_clk, VI0_CLK); ++VIN_PFC_PINS(vin0_sync, RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28)); ++VIN_PFC_SYNC(vin0_sync, VI0_HSYNC, VI0_VSYNC); ++/* - VIN1 ------------------------------------------------------------------- */ ++VIN_PFC_PINS(vin1_data8, RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), ++ RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), ++ RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6), ++ RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8)); ++VIN_PFC_DAT8(vin1_data8, VI1_DATA0, VI1_DATA1, ++ VI1_DATA2, VI1_DATA3, ++ VI1_DATA4, VI1_DATA5, ++ VI1_DATA6, VI1_DATA7); ++VIN_PFC_PINS(vin1_clk, RCAR_GP_PIN(4, 9)); ++VIN_PFC_CLK(vin1_clk, VI1_CLK); ++VIN_PFC_PINS(vin1_sync, RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22)); ++VIN_PFC_SYNC(vin1_sync, VI1_HSYNC, VI1_VSYNC); ++ + static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(hscif0_data_a), + SH_PFC_PIN_GROUP(hscif0_data_b), +@@ -1586,6 +1626,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(usb0_ovc), + SH_PFC_PIN_GROUP(usb1), + SH_PFC_PIN_GROUP(usb1_ovc), ++ SH_PFC_PIN_GROUP(vin0_data8), ++ SH_PFC_PIN_GROUP(vin0_clk), ++ SH_PFC_PIN_GROUP(vin0_sync), ++ SH_PFC_PIN_GROUP(vin1_data8), ++ SH_PFC_PIN_GROUP(vin1_clk), ++ SH_PFC_PIN_GROUP(vin1_sync), + }; + + static const char * const hscif0_groups[] = { +@@ -1703,6 +1749,18 @@ static const char * const usb1_groups[] = { + "usb1_ovc", + }; + ++static const char * const vin0_groups[] = { ++ "vin0_data8", ++ "vin0_clk", ++ "vin0_sync", ++}; ++ ++static const char * const vin1_groups[] = { ++ "vin1_data8", ++ "vin1_clk", ++ "vin1_sync", ++}; ++ + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), +@@ -1718,6 +1776,8 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(usb0), + SH_PFC_FUNCTION(usb1), ++ SH_PFC_FUNCTION(vin0), ++ SH_PFC_FUNCTION(vin1), + }; + + static struct pinmux_cfg_reg pinmux_config_regs[] = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0194-sh-pfc-r8a7778-add-Ether-pin-groups.patch b/patches.renesas/0194-sh-pfc-r8a7778-add-Ether-pin-groups.patch new file mode 100644 index 00000000000..dbf68310791 --- /dev/null +++ b/patches.renesas/0194-sh-pfc-r8a7778-add-Ether-pin-groups.patch @@ -0,0 +1,78 @@ +From 54a931e8b1f31cd84fd859d40a38f3125e04cb73 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Wed, 8 May 2013 23:15:50 +0000 +Subject: sh-pfc: r8a7778: add Ether pin groups + +Add Ether RMII/LINK/MAGIC pin groups to R8A7778 PFC driver. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Laurent Pinchart<laurent.pinchart@ideasonboard.com> +Acked-by: Linus Walleij <linus.walleij@linaro.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 3c5886d145a1bd46601313c735de214bc874aebc) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 26 ++++++++++++++++++++++++++ + 1 file changed, 26 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +index e518c33d..bc20083b 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +@@ -1323,6 +1323,22 @@ static struct sh_pfc_pin pinmux_pins[] = { + arg5##_MARK, arg6##_MARK, \ + arg7##_MARK, arg8##_MARK, } + ++/* - Ether ------------------------------------------------------------------ */ ++SH_PFC_PINS(ether_rmii, RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), ++ RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 9), ++ RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), ++ RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 14), ++ RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17)); ++static const unsigned int ether_rmii_mux[] = { ++ ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK, ++ ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK, ++ ETH_MDIO_MARK, ETH_MDC_MARK, ++}; ++SH_PFC_PINS(ether_link, RCAR_GP_PIN(4, 19)); ++SH_PFC_MUX1(ether_link, ETH_LINK); ++SH_PFC_PINS(ether_magic, RCAR_GP_PIN(4, 20)); ++SH_PFC_MUX1(ether_magic, ETH_MAGIC); ++ + /* - SCIF macro ------------------------------------------------------------- */ + #define SCIF_PFC_PIN(name, args...) SH_PFC_PINS(name, args) + #define SCIF_PFC_DAT(name, tx, rx) SH_PFC_MUX2(name, tx, rx) +@@ -1554,6 +1570,9 @@ VIN_PFC_PINS(vin1_sync, RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22)); + VIN_PFC_SYNC(vin1_sync, VI1_HSYNC, VI1_VSYNC); + + static const struct sh_pfc_pin_group pinmux_groups[] = { ++ SH_PFC_PIN_GROUP(ether_rmii), ++ SH_PFC_PIN_GROUP(ether_link), ++ SH_PFC_PIN_GROUP(ether_magic), + SH_PFC_PIN_GROUP(hscif0_data_a), + SH_PFC_PIN_GROUP(hscif0_data_b), + SH_PFC_PIN_GROUP(hscif0_ctrl_a), +@@ -1634,6 +1653,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(vin1_sync), + }; + ++static const char * const ether_groups[] = { ++ "ether_rmii", ++ "ether_link", ++ "ether_magic", ++}; ++ + static const char * const hscif0_groups[] = { + "hscif0_data_a", + "hscif0_data_b", +@@ -1762,6 +1787,7 @@ static const char * const vin1_groups[] = { + }; + + static const struct sh_pfc_function pinmux_functions[] = { ++ SH_PFC_FUNCTION(ether), + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), + SH_PFC_FUNCTION(scif_clk), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0195-sh-pfc-r8a7779-add-Ether-pin-groups.patch b/patches.renesas/0195-sh-pfc-r8a7779-add-Ether-pin-groups.patch new file mode 100644 index 00000000000..8fb0111782d --- /dev/null +++ b/patches.renesas/0195-sh-pfc-r8a7779-add-Ether-pin-groups.patch @@ -0,0 +1,94 @@ +From e6464679c6a2388373a31a366b0f07db793fc0ea Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Wed, 8 May 2013 23:17:33 +0000 +Subject: sh-pfc: r8a7779: add Ether pin groups + +Add Ether RMII/LINK/MAGIC pin groups to R8A7779 PFC driver. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Laurent Pinchart<laurent.pinchart@ideasonboard.com> +Acked-by: Linus Walleij <linus.walleij@linaro.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit eca4e3b3ccea8ca2a71bd33ab517d8387536b44d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 42 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 42 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +index 37ba5719..96bdf480 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +@@ -1640,6 +1640,38 @@ static const unsigned int du1_cde_pins[] = { + static const unsigned int du1_cde_mux[] = { + DU1_CDE_MARK + }; ++/* - Ether ------------------------------------------------------------------ */ ++static const unsigned int ether_rmii_pins[] = { ++ /* ++ * ETH_TXD0, ETH_TXD1, ETH_TX_EN, ETH_REFCLK, ++ * ETH_RXD0, ETH_RXD1, ETH_CRS_DV, ETH_RX_ER, ++ * ETH_MDIO, ETH_MDC ++ */ ++ RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 18), ++ RCAR_GP_PIN(2, 26), ++ RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 17), ++ RCAR_GP_PIN(2, 19), ++ RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 28), ++}; ++static const unsigned int ether_rmii_mux[] = { ++ ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK, ++ ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK, ++ ETH_MDIO_MARK, ETH_MDC_MARK, ++}; ++static const unsigned int ether_link_pins[] = { ++ /* ETH_LINK */ ++ RCAR_GP_PIN(2, 24), ++}; ++static const unsigned int ether_link_mux[] = { ++ ETH_LINK_MARK, ++}; ++static const unsigned int ether_magic_pins[] = { ++ /* ETH_MAGIC */ ++ RCAR_GP_PIN(2, 25), ++}; ++static const unsigned int ether_magic_mux[] = { ++ ETH_MAGIC_MARK, ++}; + /* - HSPI0 ------------------------------------------------------------------ */ + static const unsigned int hspi0_pins[] = { + /* CLK, CS, RX, TX */ +@@ -2558,6 +2590,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(du1_sync_1), + SH_PFC_PIN_GROUP(du1_oddf), + SH_PFC_PIN_GROUP(du1_cde), ++ SH_PFC_PIN_GROUP(ether_rmii), ++ SH_PFC_PIN_GROUP(ether_link), ++ SH_PFC_PIN_GROUP(ether_magic), + SH_PFC_PIN_GROUP(hspi0), + SH_PFC_PIN_GROUP(hspi1), + SH_PFC_PIN_GROUP(hspi1_b), +@@ -2703,6 +2738,12 @@ static const char * const du1_groups[] = { + "du1_cde", + }; + ++static const char * const ether_groups[] = { ++ "ether_rmii", ++ "ether_link", ++ "ether_magic", ++}; ++ + static const char * const hspi0_groups[] = { + "hspi0", + }; +@@ -2898,6 +2939,7 @@ static const char * const vin3_groups[] = { + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(du0), + SH_PFC_FUNCTION(du1), ++ SH_PFC_FUNCTION(ether), + SH_PFC_FUNCTION(hspi0), + SH_PFC_FUNCTION(hspi1), + SH_PFC_FUNCTION(hspi2), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0196-sh-pfc-r8a7778-fixup-IRQ1A-settings.patch b/patches.renesas/0196-sh-pfc-r8a7778-fixup-IRQ1A-settings.patch new file mode 100644 index 00000000000..4c3b02360d0 --- /dev/null +++ b/patches.renesas/0196-sh-pfc-r8a7778-fixup-IRQ1A-settings.patch @@ -0,0 +1,32 @@ +From 89f82bba2f051b11d52461d85f996c9b47f224a2 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Mon, 13 May 2013 21:10:17 -0700 +Subject: sh-pfc: r8a7778: fixup IRQ1A settings + +IP2[31] func2 is IRQ1A, not IRQ3A + +Reported-by: Yusuke Goda <yusuke.goda.sx@renesas.com> +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d64d00504acede6a90f9f49867f7705ba638f121) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +index bc20083b..6b2c6b58 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +@@ -2080,7 +2080,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 3, 2, 3, 3, 3, 3) { + /* IP2_31 [1] */ +- FN_MLB_CLK, FN_IRQ3_A, ++ FN_MLB_CLK, FN_IRQ1_A, + /* IP2_30 [1] */ + FN_RD_WR_B, FN_IRQ0, + /* IP2_29 [1] */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0197-pinctrl-sh-pfc-fix-r8a7790-Function-Select-register-.patch b/patches.renesas/0197-pinctrl-sh-pfc-fix-r8a7790-Function-Select-register-.patch new file mode 100644 index 00000000000..f11d20f9285 --- /dev/null +++ b/patches.renesas/0197-pinctrl-sh-pfc-fix-r8a7790-Function-Select-register-.patch @@ -0,0 +1,62 @@ +From 4a1e239591ea463754c5e87f5a081a5a340bab2a Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Wed, 15 May 2013 10:46:49 +0000 +Subject: pinctrl: sh-pfc: fix r8a7790 Function Select register tables + +Fix several errors in Peripheral Function Select register tables for +r8a7790, which prevent various function pins from being correctly +configured. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Acked-by: Linus Walleij <linus.walleij@linaro.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 17babad61d7be374cbcaaeff22408912833cc316) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 14 ++++++-------- + 1 file changed, 6 insertions(+), 8 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +index 5be29995..a2f83ae9 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -3175,7 +3175,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, +- 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { ++ 2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) { + /* IP11_31_30 [2] */ + FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0, + /* IP11_29_27 [3] */ +@@ -3441,12 +3441,10 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + FN_SEL_SOF0_0, FN_SEL_SOF0_1, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, +- 2, 1, 1, 1, 1, 2, 1, 2, 1, +- 2, 1, 1, 1, 3, 3, 2, 3, 2, 2) { +- /* RESEVED [2] */ ++ 3, 1, 1, 1, 2, 1, 2, 1, 2, ++ 1, 1, 1, 3, 3, 2, 3, 2, 2) { ++ /* RESEVED [3] */ + 0, 0, 0, 0, 0, 0, 0, 0, +- /* RESEVED [1] */ +- 0, 0, + /* SEL_TMU1 [1] */ + FN_SEL_TMU1_0, FN_SEL_TMU1_1, + /* SEL_HSCIF1 [1] */ +@@ -3462,8 +3460,8 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + /* SEL_CAN1 [1] */ + FN_SEL_CAN1_0, FN_SEL_CAN1_1, + /* RESEVED [2] */ +- 0, 0, 0, 0, 0, 0, 0, 0, +- /* RESEVED [1] */ ++ 0, 0, 0, 0, ++ /* RESEVED [1] (actually TX2, RX2 vs. TX2_B, RX2_B of SCIF2) */ + 0, 0, + /* SEL_ADI [1] */ + FN_SEL_ADI_0, FN_SEL_ADI_1, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0198-pinctrl-sh-pfc-fix-a-typo-in-pfc-r8a7790.patch b/patches.renesas/0198-pinctrl-sh-pfc-fix-a-typo-in-pfc-r8a7790.patch new file mode 100644 index 00000000000..787bfc965a1 --- /dev/null +++ b/patches.renesas/0198-pinctrl-sh-pfc-fix-a-typo-in-pfc-r8a7790.patch @@ -0,0 +1,74 @@ +From 8b4b029389156416cd18f32fc4e97f0df280c434 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Wed, 15 May 2013 10:46:54 +0000 +Subject: pinctrl: sh-pfc: fix a typo in pfc-r8a7790 + +Fix multiple occurrences of the "RESEVED" typo. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Acked-by: Linus Walleij <linus.walleij@linaro.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 7f35184b3d49a5420a9f6a6e0a1238bf602c6cb1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 18 +++++++++--------- + 1 file changed, 9 insertions(+), 9 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +index a2f83ae9..93384227 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -3443,7 +3443,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, + 3, 1, 1, 1, 2, 1, 2, 1, 2, + 1, 1, 1, 3, 3, 2, 3, 2, 2) { +- /* RESEVED [3] */ ++ /* RESERVED [3] */ + 0, 0, 0, 0, 0, 0, 0, 0, + /* SEL_TMU1 [1] */ + FN_SEL_TMU1_0, FN_SEL_TMU1_1, +@@ -3459,9 +3459,9 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0, + /* SEL_CAN1 [1] */ + FN_SEL_CAN1_0, FN_SEL_CAN1_1, +- /* RESEVED [2] */ ++ /* RESERVED [2] */ + 0, 0, 0, 0, +- /* RESEVED [1] (actually TX2, RX2 vs. TX2_B, RX2_B of SCIF2) */ ++ /* RESERVED [1] (actually TX2, RX2 vs. TX2_B, RX2_B of SCIF2) */ + 0, 0, + /* SEL_ADI [1] */ + FN_SEL_ADI_0, FN_SEL_ADI_1, +@@ -3490,22 +3490,22 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, + /* SEL_IIC0 [1] */ + FN_SEL_IIC0_0, FN_SEL_IIC0_1, +- /* RESEVED [2] */ ++ /* RESERVED [2] */ + 0, 0, 0, 0, +- /* RESEVED [4] */ ++ /* RESERVED [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, +- /* RESEVED [4] */ ++ /* RESERVED [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, +- /* RESEVED [2] */ ++ /* RESERVED [2] */ + 0, 0, 0, 0, + /* SEL_IEB [2] */ + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, +- /* RESEVED [4] */ ++ /* RESERVED [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, +- /* RESEVED [2] */ ++ /* RESERVED [2] */ + 0, 0, 0, 0, + /* SEL_IIC2 [3] */ + FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0199-sh-pfc-r8a7778-add-I2C-pin-groups.patch b/patches.renesas/0199-sh-pfc-r8a7778-add-I2C-pin-groups.patch new file mode 100644 index 00000000000..6e559fab3c1 --- /dev/null +++ b/patches.renesas/0199-sh-pfc-r8a7778-add-I2C-pin-groups.patch @@ -0,0 +1,104 @@ +From 1b300068a031d0b9cdec4534b37824df9150f36b Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 22 May 2013 20:15:53 -0700 +Subject: sh-pfc: r8a7778: add I2C pin groups + +Add I2C SDA/SCL pin groups to R8A7778 PFC driver. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 0dcbc69e2bcf99539739f16cff56e48fb3e8229c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 54 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 54 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +index 6b2c6b58..605f8ae6 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +@@ -1371,6 +1371,32 @@ SCIF_PFC_CLK(hscif1_clk_a, HSCK1_A); + SCIF_PFC_PIN(hscif1_clk_b, RCAR_GP_PIN(4, 2)); + SCIF_PFC_CLK(hscif1_clk_b, HSCK1_B); + ++/* - I2C macro ------------------------------------------------------------- */ ++#define I2C_PFC_PIN(name, args...) SH_PFC_PINS(name, args) ++#define I2C_PFC_MUX(name, sda, scl) SH_PFC_MUX2(name, sda, scl) ++ ++/* - I2C1 ------------------------------------------------------------------ */ ++I2C_PFC_PIN(i2c1_a, RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9)); ++I2C_PFC_MUX(i2c1_a, SDA1_A, SCL1_A); ++I2C_PFC_PIN(i2c1_b, RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18)); ++I2C_PFC_MUX(i2c1_b, SDA1_B, SCL1_B); ++ ++/* - I2C2 ------------------------------------------------------------------ */ ++I2C_PFC_PIN(i2c2_a, PIN_NUMBER(3, 20), RCAR_GP_PIN(1, 3)); ++I2C_PFC_MUX(i2c2_a, SDA2_A, SCL2_A); ++I2C_PFC_PIN(i2c2_b, RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4)); ++I2C_PFC_MUX(i2c2_b, SDA2_B, SCL2_B); ++I2C_PFC_PIN(i2c2_c, RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16)); ++I2C_PFC_MUX(i2c2_c, SDA2_C, SCL2_C); ++ ++/* - I2C3 ------------------------------------------------------------------ */ ++I2C_PFC_PIN(i2c3_a, RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15)); ++I2C_PFC_MUX(i2c3_a, SDA3_A, SCL3_A); ++I2C_PFC_PIN(i2c3_b, RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 19)); ++I2C_PFC_MUX(i2c3_b, SDA3_B, SCL3_B); ++I2C_PFC_PIN(i2c3_c, RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23)); ++I2C_PFC_MUX(i2c3_c, SDA3_C, SCL3_C); ++ + /* - SCIF CLOCK ------------------------------------------------------------- */ + SCIF_PFC_PIN(scif_clk, RCAR_GP_PIN(1, 16)); + SCIF_PFC_CLK(scif_clk, SCIF_CLK); +@@ -1584,6 +1610,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(hscif1_ctrl_b), + SH_PFC_PIN_GROUP(hscif1_clk_a), + SH_PFC_PIN_GROUP(hscif1_clk_b), ++ SH_PFC_PIN_GROUP(i2c1_a), ++ SH_PFC_PIN_GROUP(i2c1_b), ++ SH_PFC_PIN_GROUP(i2c2_a), ++ SH_PFC_PIN_GROUP(i2c2_b), ++ SH_PFC_PIN_GROUP(i2c2_c), ++ SH_PFC_PIN_GROUP(i2c3_a), ++ SH_PFC_PIN_GROUP(i2c3_b), ++ SH_PFC_PIN_GROUP(i2c3_c), + SH_PFC_PIN_GROUP(scif_clk), + SH_PFC_PIN_GROUP(scif0_data_a), + SH_PFC_PIN_GROUP(scif0_data_b), +@@ -1676,6 +1710,23 @@ static const char * const hscif1_groups[] = { + "hscif1_clk_b", + }; + ++static const char * const i2c1_groups[] = { ++ "i2c1_a", ++ "i2c1_b", ++}; ++ ++static const char * const i2c2_groups[] = { ++ "i2c2_a", ++ "i2c2_b", ++ "i2c2_c", ++}; ++ ++static const char * const i2c3_groups[] = { ++ "i2c3_a", ++ "i2c3_b", ++ "i2c3_c", ++}; ++ + static const char * const scif_clk_groups[] = { + "scif_clk", + }; +@@ -1790,6 +1841,9 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(ether), + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), ++ SH_PFC_FUNCTION(i2c1), ++ SH_PFC_FUNCTION(i2c2), ++ SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0200-sh-pfc-r8a7778-add-HSPI-pin-groups.patch b/patches.renesas/0200-sh-pfc-r8a7778-add-HSPI-pin-groups.patch new file mode 100644 index 00000000000..a36589e80d3 --- /dev/null +++ b/patches.renesas/0200-sh-pfc-r8a7778-add-HSPI-pin-groups.patch @@ -0,0 +1,111 @@ +From 2b93c3b3be4b8de2dfdea9bbbbf4fd335c8e9282 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 22 May 2013 20:16:30 -0700 +Subject: sh-pfc: r8a7778: add HSPI pin groups + +Add HSPI CLK/CS/RX/TX pin groups to R8A7778 PFC driver. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 09cc76a95802e87dfda0fe6ecad2090de65e0ab1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 61 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 61 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +index 605f8ae6..bf5e3d89 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +@@ -1371,6 +1371,43 @@ SCIF_PFC_CLK(hscif1_clk_a, HSCK1_A); + SCIF_PFC_PIN(hscif1_clk_b, RCAR_GP_PIN(4, 2)); + SCIF_PFC_CLK(hscif1_clk_b, HSCK1_B); + ++/* - HSPI macro --------------------------------------------------------------*/ ++#define HSPI_PFC_PIN(name, args...) SH_PFC_PINS(name, args) ++#define HSPI_PFC_DAT(name, clk, cs, rx, tx) SH_PFC_MUX4(name, clk, cs, rx, tx) ++ ++/* - HSPI0 -------------------------------------------------------------------*/ ++HSPI_PFC_PIN(hspi0_a, RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), ++ RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22)); ++HSPI_PFC_DAT(hspi0_a, HSPI_CLK0_A, HSPI_CS0_A, ++ HSPI_RX0_A, HSPI_TX0); ++ ++HSPI_PFC_PIN(hspi0_b, RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26), ++ RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 27)); ++HSPI_PFC_DAT(hspi0_b, HSPI_CLK0_B, HSPI_CS0_B, ++ HSPI_RX0_B, HSPI_TX0_B); ++ ++/* - HSPI1 -------------------------------------------------------------------*/ ++HSPI_PFC_PIN(hspi1_a, RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), ++ RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 28)); ++HSPI_PFC_DAT(hspi1_a, HSPI_CLK1_A, HSPI_CS1_A, ++ HSPI_RX1_A, HSPI_TX1_A); ++ ++HSPI_PFC_PIN(hspi1_b, RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 26), ++ PIN_NUMBER(20, 1), PIN_NUMBER(25, 2)); ++HSPI_PFC_DAT(hspi1_b, HSPI_CLK1_B, HSPI_CS1_B, ++ HSPI_RX1_B, HSPI_TX1_B); ++ ++/* - HSPI2 -------------------------------------------------------------------*/ ++HSPI_PFC_PIN(hspi2_a, RCAR_GP_PIN(2, 29), RCAR_GP_PIN(3, 8), ++ RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 30)); ++HSPI_PFC_DAT(hspi2_a, HSPI_CLK2_A, HSPI_CS2_A, ++ HSPI_RX2_A, HSPI_TX2_A); ++ ++HSPI_PFC_PIN(hspi2_b, RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22), ++ RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24)); ++HSPI_PFC_DAT(hspi2_b, HSPI_CLK2_B, HSPI_CS2_B, ++ HSPI_RX2_B, HSPI_TX2_B); ++ + /* - I2C macro ------------------------------------------------------------- */ + #define I2C_PFC_PIN(name, args...) SH_PFC_PINS(name, args) + #define I2C_PFC_MUX(name, sda, scl) SH_PFC_MUX2(name, sda, scl) +@@ -1610,6 +1647,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(hscif1_ctrl_b), + SH_PFC_PIN_GROUP(hscif1_clk_a), + SH_PFC_PIN_GROUP(hscif1_clk_b), ++ SH_PFC_PIN_GROUP(hspi0_a), ++ SH_PFC_PIN_GROUP(hspi0_b), ++ SH_PFC_PIN_GROUP(hspi1_a), ++ SH_PFC_PIN_GROUP(hspi1_b), ++ SH_PFC_PIN_GROUP(hspi2_a), ++ SH_PFC_PIN_GROUP(hspi2_b), + SH_PFC_PIN_GROUP(i2c1_a), + SH_PFC_PIN_GROUP(i2c1_b), + SH_PFC_PIN_GROUP(i2c2_a), +@@ -1710,6 +1753,21 @@ static const char * const hscif1_groups[] = { + "hscif1_clk_b", + }; + ++static const char * const hspi0_groups[] = { ++ "hspi0_a", ++ "hspi0_b", ++}; ++ ++static const char * const hspi1_groups[] = { ++ "hspi1_a", ++ "hspi1_b", ++}; ++ ++static const char * const hspi2_groups[] = { ++ "hspi2_a", ++ "hspi2_b", ++}; ++ + static const char * const i2c1_groups[] = { + "i2c1_a", + "i2c1_b", +@@ -1841,6 +1899,9 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(ether), + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), ++ SH_PFC_FUNCTION(hspi0), ++ SH_PFC_FUNCTION(hspi1), ++ SH_PFC_FUNCTION(hspi2), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0201-sh-pfc-r8a7778-add-MMCIF-pin-groups.patch b/patches.renesas/0201-sh-pfc-r8a7778-add-MMCIF-pin-groups.patch new file mode 100644 index 00000000000..2603dc08805 --- /dev/null +++ b/patches.renesas/0201-sh-pfc-r8a7778-add-MMCIF-pin-groups.patch @@ -0,0 +1,88 @@ +From 0ee289e3166cf0a438c2f6cebe12af367e81a173 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 22 May 2013 20:17:04 -0700 +Subject: sh-pfc: r8a7778: add MMCIF pin groups + +Add MMCIF CLK/CMD/DATA groups to R8A7778 PFC driver. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 3ef2a776d13826a6f574d0637e4be7ce7e3be676) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 38 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 38 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +index bf5e3d89..1dcbabcd 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +@@ -1434,6 +1434,32 @@ I2C_PFC_MUX(i2c3_b, SDA3_B, SCL3_B); + I2C_PFC_PIN(i2c3_c, RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23)); + I2C_PFC_MUX(i2c3_c, SDA3_C, SCL3_C); + ++/* - MMC macro -------------------------------------------------------------- */ ++#define MMC_PFC_PINS(name, args...) SH_PFC_PINS(name, args) ++#define MMC_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd) ++#define MMC_PFC_DAT1(name, d0) SH_PFC_MUX1(name, d0) ++#define MMC_PFC_DAT4(name, d0, d1, d2, d3) SH_PFC_MUX4(name, d0, d1, d2, d3) ++#define MMC_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7) \ ++ SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7) ++ ++/* - MMC -------------------------------------------------------------------- */ ++MMC_PFC_PINS(mmc_ctrl, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6)); ++MMC_PFC_CTRL(mmc_ctrl, MMC_CLK, MMC_CMD); ++MMC_PFC_PINS(mmc_data1, RCAR_GP_PIN(1, 7)); ++MMC_PFC_DAT1(mmc_data1, MMC_D0); ++MMC_PFC_PINS(mmc_data4, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(2, 8), ++ RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6)); ++MMC_PFC_DAT4(mmc_data4, MMC_D0, MMC_D1, ++ MMC_D2, MMC_D3); ++MMC_PFC_PINS(mmc_data8, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(2, 8), ++ RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), ++ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0), ++ RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31)); ++MMC_PFC_DAT8(mmc_data8, MMC_D0, MMC_D1, ++ MMC_D2, MMC_D3, ++ MMC_D4, MMC_D5, ++ MMC_D6, MMC_D7); ++ + /* - SCIF CLOCK ------------------------------------------------------------- */ + SCIF_PFC_PIN(scif_clk, RCAR_GP_PIN(1, 16)); + SCIF_PFC_CLK(scif_clk, SCIF_CLK); +@@ -1661,6 +1687,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(i2c3_a), + SH_PFC_PIN_GROUP(i2c3_b), + SH_PFC_PIN_GROUP(i2c3_c), ++ SH_PFC_PIN_GROUP(mmc_ctrl), ++ SH_PFC_PIN_GROUP(mmc_data1), ++ SH_PFC_PIN_GROUP(mmc_data4), ++ SH_PFC_PIN_GROUP(mmc_data8), + SH_PFC_PIN_GROUP(scif_clk), + SH_PFC_PIN_GROUP(scif0_data_a), + SH_PFC_PIN_GROUP(scif0_data_b), +@@ -1785,6 +1815,13 @@ static const char * const i2c3_groups[] = { + "i2c3_c", + }; + ++static const char * const mmc_groups[] = { ++ "mmc_ctrl", ++ "mmc_data1", ++ "mmc_data4", ++ "mmc_data8", ++}; ++ + static const char * const scif_clk_groups[] = { + "scif_clk", + }; +@@ -1905,6 +1942,7 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), ++ SH_PFC_FUNCTION(mmc), + SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0202-pinctrl-r8a7790-add-pinmux-data-for-MMCIF-and-SDHI-i.patch b/patches.renesas/0202-pinctrl-r8a7790-add-pinmux-data-for-MMCIF-and-SDHI-i.patch new file mode 100644 index 00000000000..97288f17e24 --- /dev/null +++ b/patches.renesas/0202-pinctrl-r8a7790-add-pinmux-data-for-MMCIF-and-SDHI-i.patch @@ -0,0 +1,345 @@ +From 33d321fd4f60a4446e92601374c7845fbe112c4e Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Fri, 17 May 2013 16:55:12 +0200 +Subject: pinctrl: r8a7790: add pinmux data for MMCIF and SDHI interfaces + +This patch adds pinmux groups and functions for the two MMCIF and four +SDHI interfaces on r8a73a4 (APE6). + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 066f0d6eb7c057e8e797a3d74b30764ed21952a2) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 294 +++++++++++++++++++++++++++++++++++ + 1 file changed, 294 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +index 93384227..85d77a41 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -2372,6 +2372,220 @@ static const unsigned int tpu0_to3_mux[] = { + TPU0TO3_MARK, + }; + ++/* - MMCIF ------------------------------------------------------------------ */ ++static const unsigned int mmc0_data1_pins[] = { ++ /* D[0] */ ++ RCAR_GP_PIN(3, 18), ++}; ++static const unsigned int mmc0_data1_mux[] = { ++ MMC0_D0_MARK, ++}; ++static const unsigned int mmc0_data4_pins[] = { ++ /* D[0:3] */ ++ RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), ++ RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), ++}; ++static const unsigned int mmc0_data4_mux[] = { ++ MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, ++}; ++static const unsigned int mmc0_data8_pins[] = { ++ /* D[0:7] */ ++ RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), ++ RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), ++ RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), ++ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), ++}; ++static const unsigned int mmc0_data8_mux[] = { ++ MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, ++ MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK, ++}; ++static const unsigned int mmc0_ctrl_pins[] = { ++ /* CLK, CMD */ ++ RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), ++}; ++static const unsigned int mmc0_ctrl_mux[] = { ++ MMC0_CLK_MARK, MMC0_CMD_MARK, ++}; ++ ++static const unsigned int mmc1_data1_pins[] = { ++ /* D[0] */ ++ RCAR_GP_PIN(3, 26), ++}; ++static const unsigned int mmc1_data1_mux[] = { ++ MMC1_D0_MARK, ++}; ++static const unsigned int mmc1_data4_pins[] = { ++ /* D[0:3] */ ++ RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), ++ RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), ++}; ++static const unsigned int mmc1_data4_mux[] = { ++ MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, ++}; ++static const unsigned int mmc1_data8_pins[] = { ++ /* D[0:7] */ ++ RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), ++ RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), ++ RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), ++ RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), ++}; ++static const unsigned int mmc1_data8_mux[] = { ++ MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, ++ MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK, ++}; ++static const unsigned int mmc1_ctrl_pins[] = { ++ /* CLK, CMD */ ++ RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25), ++}; ++static const unsigned int mmc1_ctrl_mux[] = { ++ MMC1_CLK_MARK, MMC1_CMD_MARK, ++}; ++ ++/* - SDHI ------------------------------------------------------------------- */ ++static const unsigned int sdhi0_data1_pins[] = { ++ /* D0 */ ++ RCAR_GP_PIN(3, 2), ++}; ++static const unsigned int sdhi0_data1_mux[] = { ++ SD0_DAT0_MARK, ++}; ++static const unsigned int sdhi0_data4_pins[] = { ++ /* D[0:3] */ ++ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), ++}; ++static const unsigned int sdhi0_data4_mux[] = { ++ SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, ++}; ++static const unsigned int sdhi0_ctrl_pins[] = { ++ /* CLK, CMD */ ++ RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), ++}; ++static const unsigned int sdhi0_ctrl_mux[] = { ++ SD0_CLK_MARK, SD0_CMD_MARK, ++}; ++static const unsigned int sdhi0_cd_pins[] = { ++ /* CD */ ++ RCAR_GP_PIN(3, 6), ++}; ++static const unsigned int sdhi0_cd_mux[] = { ++ SD0_CD_MARK, ++}; ++static const unsigned int sdhi0_wp_pins[] = { ++ /* WP */ ++ RCAR_GP_PIN(3, 7), ++}; ++static const unsigned int sdhi0_wp_mux[] = { ++ SD0_WP_MARK, ++}; ++ ++static const unsigned int sdhi1_data1_pins[] = { ++ /* D0 */ ++ RCAR_GP_PIN(3, 10), ++}; ++static const unsigned int sdhi1_data1_mux[] = { ++ SD1_DAT0_MARK, ++}; ++static const unsigned int sdhi1_data4_pins[] = { ++ /* D[0:3] */ ++ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), ++}; ++static const unsigned int sdhi1_data4_mux[] = { ++ SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, ++}; ++static const unsigned int sdhi1_ctrl_pins[] = { ++ /* CLK, CMD */ ++ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), ++}; ++static const unsigned int sdhi1_ctrl_mux[] = { ++ SD1_CLK_MARK, SD1_CMD_MARK, ++}; ++static const unsigned int sdhi1_cd_pins[] = { ++ /* CD */ ++ RCAR_GP_PIN(3, 14), ++}; ++static const unsigned int sdhi1_cd_mux[] = { ++ SD1_CD_MARK, ++}; ++static const unsigned int sdhi1_wp_pins[] = { ++ /* WP */ ++ RCAR_GP_PIN(3, 15), ++}; ++static const unsigned int sdhi1_wp_mux[] = { ++ SD1_WP_MARK, ++}; ++ ++static const unsigned int sdhi2_data1_pins[] = { ++ /* D0 */ ++ RCAR_GP_PIN(3, 18), ++}; ++static const unsigned int sdhi2_data1_mux[] = { ++ SD2_DAT0_MARK, ++}; ++static const unsigned int sdhi2_data4_pins[] = { ++ /* D[0:3] */ ++ RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), ++}; ++static const unsigned int sdhi2_data4_mux[] = { ++ SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, ++}; ++static const unsigned int sdhi2_ctrl_pins[] = { ++ /* CLK, CMD */ ++ RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), ++}; ++static const unsigned int sdhi2_ctrl_mux[] = { ++ SD2_CLK_MARK, SD2_CMD_MARK, ++}; ++static const unsigned int sdhi2_cd_pins[] = { ++ /* CD */ ++ RCAR_GP_PIN(3, 22), ++}; ++static const unsigned int sdhi2_cd_mux[] = { ++ SD2_CD_MARK, ++}; ++static const unsigned int sdhi2_wp_pins[] = { ++ /* WP */ ++ RCAR_GP_PIN(3, 23), ++}; ++static const unsigned int sdhi2_wp_mux[] = { ++ SD2_WP_MARK, ++}; ++ ++static const unsigned int sdhi3_data1_pins[] = { ++ /* D0 */ ++ RCAR_GP_PIN(3, 26), ++}; ++static const unsigned int sdhi3_data1_mux[] = { ++ SD3_DAT0_MARK, ++}; ++static const unsigned int sdhi3_data4_pins[] = { ++ /* D[0:3] */ ++ RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), ++}; ++static const unsigned int sdhi3_data4_mux[] = { ++ SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, ++}; ++static const unsigned int sdhi3_ctrl_pins[] = { ++ /* CLK, CMD */ ++ RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25), ++}; ++static const unsigned int sdhi3_ctrl_mux[] = { ++ SD3_CLK_MARK, SD3_CMD_MARK, ++}; ++static const unsigned int sdhi3_cd_pins[] = { ++ /* CD */ ++ RCAR_GP_PIN(3, 30), ++}; ++static const unsigned int sdhi3_cd_mux[] = { ++ SD3_CD_MARK, ++}; ++static const unsigned int sdhi3_wp_pins[] = { ++ /* WP */ ++ RCAR_GP_PIN(3, 31), ++}; ++static const unsigned int sdhi3_wp_mux[] = { ++ SD3_WP_MARK, ++}; ++ + static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(eth_link), + SH_PFC_PIN_GROUP(eth_magic), +@@ -2449,6 +2663,34 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(tpu0_to1), + SH_PFC_PIN_GROUP(tpu0_to2), + SH_PFC_PIN_GROUP(tpu0_to3), ++ SH_PFC_PIN_GROUP(mmc0_data1), ++ SH_PFC_PIN_GROUP(mmc0_data4), ++ SH_PFC_PIN_GROUP(mmc0_data8), ++ SH_PFC_PIN_GROUP(mmc0_ctrl), ++ SH_PFC_PIN_GROUP(mmc1_data1), ++ SH_PFC_PIN_GROUP(mmc1_data4), ++ SH_PFC_PIN_GROUP(mmc1_data8), ++ SH_PFC_PIN_GROUP(mmc1_ctrl), ++ SH_PFC_PIN_GROUP(sdhi0_data1), ++ SH_PFC_PIN_GROUP(sdhi0_data4), ++ SH_PFC_PIN_GROUP(sdhi0_ctrl), ++ SH_PFC_PIN_GROUP(sdhi0_cd), ++ SH_PFC_PIN_GROUP(sdhi0_wp), ++ SH_PFC_PIN_GROUP(sdhi1_data1), ++ SH_PFC_PIN_GROUP(sdhi1_data4), ++ SH_PFC_PIN_GROUP(sdhi1_ctrl), ++ SH_PFC_PIN_GROUP(sdhi1_cd), ++ SH_PFC_PIN_GROUP(sdhi1_wp), ++ SH_PFC_PIN_GROUP(sdhi2_data1), ++ SH_PFC_PIN_GROUP(sdhi2_data4), ++ SH_PFC_PIN_GROUP(sdhi2_ctrl), ++ SH_PFC_PIN_GROUP(sdhi2_cd), ++ SH_PFC_PIN_GROUP(sdhi2_wp), ++ SH_PFC_PIN_GROUP(sdhi3_data1), ++ SH_PFC_PIN_GROUP(sdhi3_data4), ++ SH_PFC_PIN_GROUP(sdhi3_ctrl), ++ SH_PFC_PIN_GROUP(sdhi3_cd), ++ SH_PFC_PIN_GROUP(sdhi3_wp), + }; + + static const char * const eth_groups[] = { +@@ -2560,6 +2802,52 @@ static const char * const tpu0_groups[] = { + "tpu0_to3", + }; + ++static const char * const mmc0_groups[] = { ++ "mmc0_data1", ++ "mmc0_data4", ++ "mmc0_data8", ++ "mmc0_ctrl", ++}; ++ ++static const char * const mmc1_groups[] = { ++ "mmc1_data1", ++ "mmc1_data4", ++ "mmc1_data8", ++ "mmc1_ctrl", ++}; ++ ++static const char * const sdhi0_groups[] = { ++ "sdhi0_data1", ++ "sdhi0_data4", ++ "sdhi0_ctrl", ++ "sdhi0_cd", ++ "sdhi0_wp", ++}; ++ ++static const char * const sdhi1_groups[] = { ++ "sdhi1_data1", ++ "sdhi1_data4", ++ "sdhi1_ctrl", ++ "sdhi1_cd", ++ "sdhi1_wp", ++}; ++ ++static const char * const sdhi2_groups[] = { ++ "sdhi2_data1", ++ "sdhi2_data4", ++ "sdhi2_ctrl", ++ "sdhi2_cd", ++ "sdhi2_wp", ++}; ++ ++static const char * const sdhi3_groups[] = { ++ "sdhi3_data1", ++ "sdhi3_data4", ++ "sdhi3_ctrl", ++ "sdhi3_cd", ++ "sdhi3_wp", ++}; ++ + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(eth), + SH_PFC_FUNCTION(intc), +@@ -2572,6 +2860,12 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(scifb1), + SH_PFC_FUNCTION(scifb2), + SH_PFC_FUNCTION(tpu0), ++ SH_PFC_FUNCTION(mmc0), ++ SH_PFC_FUNCTION(mmc1), ++ SH_PFC_FUNCTION(sdhi0), ++ SH_PFC_FUNCTION(sdhi1), ++ SH_PFC_FUNCTION(sdhi2), ++ SH_PFC_FUNCTION(sdhi3), + }; + + static struct pinmux_cfg_reg pinmux_config_regs[] = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0203-pinctrl-sh-pfc-r8a7779-Fix-missing-MOD_SEL2-entry.patch b/patches.renesas/0203-pinctrl-sh-pfc-r8a7779-Fix-missing-MOD_SEL2-entry.patch new file mode 100644 index 00000000000..1dd89c64c23 --- /dev/null +++ b/patches.renesas/0203-pinctrl-sh-pfc-r8a7779-Fix-missing-MOD_SEL2-entry.patch @@ -0,0 +1,39 @@ +From faa6abde94a12913a84854002327e0407633fa44 Mon Sep 17 00:00:00 2001 +From: Phil Edworthy <phil.edworthy@renesas.com> +Date: Mon, 3 Jun 2013 08:52:28 +0100 +Subject: pinctrl: sh-pfc: r8a7779: Fix missing MOD_SEL2 entry + +The list of functions selected by the MOD_SEL2 register was missing +an entry. This caused all entries after this to modify the MOD_SEL2 +register incorrectly. + +This bug showed up when selecting i2c2_c pins on the Renesas Hurricane board. + +This bug has been present since pinmux support was added for the +r8a7779 SoC by 881023d28b465eb457067dc8bbca0f24d8b34279 ("sh-pfc: Add +r8a7779 pinmux support") in v3.8-rc4. + +Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit b9ffcc2b12301eaf726ac24c93de01017ffea178) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +index 96bdf480..8e22ca6c 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +@@ -3768,7 +3768,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + /* SEL_SCIF [2] */ + FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3, + /* SEL_CANCLK [2] */ +- FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, ++ FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, 0, + /* SEL_CAN0 [1] */ + FN_SEL_CAN0_0, FN_SEL_CAN0_1, + /* SEL_HSCIF1 [1] */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0204-ARM-shmobile-r8a7790-Configure-R-Car-GPIO-for-IRQ_TY.patch b/patches.renesas/0204-ARM-shmobile-r8a7790-Configure-R-Car-GPIO-for-IRQ_TY.patch new file mode 100644 index 00000000000..b6d82a31521 --- /dev/null +++ b/patches.renesas/0204-ARM-shmobile-r8a7790-Configure-R-Car-GPIO-for-IRQ_TY.patch @@ -0,0 +1,35 @@ +From ac1e195dfd3a292ebd10355e67bc0272bb27a954 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Mon, 13 May 2013 17:53:52 +0900 +Subject: ARM: shmobile: r8a7790: Configure R-Car GPIO for IRQ_TYPE_EDGE_BOTH + +"gpio-rcar: Support IRQ_TYPE_EDGE_BOTH" adds support to the R-Car GPIO +driver for IRQ_TYPE_EDGE_BOTH. As hardware support for this feature is +not universal for all SoCs a flag, has_both_edge_trigger, has been +added to the platform data of the driver to allow this feature to be +enabled. + +As the r8a7790 SoC hardware supports this feature enable it. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d93906b869dd9444823f04ea64a585143f18a26e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a7790.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c +index eeef5f61..b461d934 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7790.c ++++ b/arch/arm/mach-shmobile/setup-r8a7790.c +@@ -45,6 +45,7 @@ static struct gpio_rcar_config r8a7790_gpio##idx##_platform_data = { \ + .irq_base = 0, \ + .number_of_pins = 32, \ + .pctl_name = "pfc-r8a7790", \ ++ .has_both_edge_trigger = 1, \ + }; \ + + R8A7790_GPIO(0); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0205-ARM-shmobile-r8a7740-pinmux-platform-device-cleanup.patch b/patches.renesas/0205-ARM-shmobile-r8a7740-pinmux-platform-device-cleanup.patch new file mode 100644 index 00000000000..6ce067f8195 --- /dev/null +++ b/patches.renesas/0205-ARM-shmobile-r8a7740-pinmux-platform-device-cleanup.patch @@ -0,0 +1,59 @@ +From 279d4974c9edc675b70d53bf7c7469e91318009e Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Wed, 3 Apr 2013 15:32:58 +0900 +Subject: ARM: shmobile: r8a7740 pinmux platform device cleanup + +Use DEFINE_RES_MEM() and platform_device_register_simple() +to save a couple of lines of code. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 3404622a77f90168fd1190c64e92edf548c0f8f0) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a7740.c | 24 +++++------------------- + 1 file changed, 5 insertions(+), 19 deletions(-) + +diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c +index 9284e6fd..00c5a707 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7740.c ++++ b/arch/arm/mach-shmobile/setup-r8a7740.c +@@ -70,29 +70,15 @@ void __init r8a7740_map_io(void) + } + + /* PFC */ +-static struct resource r8a7740_pfc_resources[] = { +- [0] = { +- .start = 0xe6050000, +- .end = 0xe6057fff, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = 0xe605800c, +- .end = 0xe605802b, +- .flags = IORESOURCE_MEM, +- } +-}; +- +-static struct platform_device r8a7740_pfc_device = { +- .name = "pfc-r8a7740", +- .id = -1, +- .resource = r8a7740_pfc_resources, +- .num_resources = ARRAY_SIZE(r8a7740_pfc_resources), ++static const struct resource pfc_resources[] = { ++ DEFINE_RES_MEM(0xe6050000, 0x8000), ++ DEFINE_RES_MEM(0xe605800c, 0x0020), + }; + + void __init r8a7740_pinmux_init(void) + { +- platform_device_register(&r8a7740_pfc_device); ++ platform_device_register_simple("pfc-r8a7740", -1, pfc_resources, ++ ARRAY_SIZE(pfc_resources)); + } + + static struct renesas_intc_irqpin_config irqpin0_platform_data = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0206-ARM-shmobile-kzm9g-tidyup-FSI-pinctrl.patch b/patches.renesas/0206-ARM-shmobile-kzm9g-tidyup-FSI-pinctrl.patch new file mode 100644 index 00000000000..4385825afab --- /dev/null +++ b/patches.renesas/0206-ARM-shmobile-kzm9g-tidyup-FSI-pinctrl.patch @@ -0,0 +1,42 @@ +From 080249b18a4a53adcedf53b3b0fed269c1c8471a Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 22 May 2013 18:34:10 -0700 +Subject: ARM: shmobile: kzm9g: tidyup FSI pinctrl + +sh73a0 needs "sh_fsi2", not "sh_fsi2.0" + +Tested-by: Hiep Cao Minh <cm-hiep@jinso.co.jp> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 41534a37c427c9b715ee75cd7ef34785bb81785f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-kzm9g.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c +index fc4ca9be..1fdf05cb 100644 +--- a/arch/arm/mach-shmobile/board-kzm9g.c ++++ b/arch/arm/mach-shmobile/board-kzm9g.c +@@ -663,13 +663,13 @@ static unsigned long pin_pullup_conf[] = { + + static const struct pinctrl_map kzm_pinctrl_map[] = { + /* FSIA (AK4648) */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0", + "fsia_mclk_in", "fsia"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0", + "fsia_sclk_in", "fsia"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0", + "fsia_data_in", "fsia"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0", + "fsia_data_out", "fsia"), + /* I2C3 */ + PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0", +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0207-ARM-shmobile-bockw-add-pinctrl-support.patch b/patches.renesas/0207-ARM-shmobile-bockw-add-pinctrl-support.patch new file mode 100644 index 00000000000..8a0d6b3c746 --- /dev/null +++ b/patches.renesas/0207-ARM-shmobile-bockw-add-pinctrl-support.patch @@ -0,0 +1,57 @@ +From d36e835844358b45c040c1521f147acf13eb4fe6 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Fri, 12 Apr 2013 05:38:03 +0000 +Subject: ARM: shmobile: bockw: add pinctrl support + +SCIF0 support as 1st step + +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 111ea17927b4be0be2423c4b7a94d6b0ab1d92a6) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-bockw.c | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c +index 38e5e50f..dac4365c 100644 +--- a/arch/arm/mach-shmobile/board-bockw.c ++++ b/arch/arm/mach-shmobile/board-bockw.c +@@ -18,6 +18,7 @@ + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + ++#include <linux/pinctrl/machine.h> + #include <linux/platform_device.h> + #include <linux/smsc911x.h> + #include <mach/common.h> +@@ -37,6 +38,14 @@ static struct resource smsc911x_resources[] = { + DEFINE_RES_IRQ(irq_pin(0)), /* IRQ 0 */ + }; + ++static const struct pinctrl_map bockw_pinctrl_map[] = { ++ /* SCIF0 */ ++ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778", ++ "scif0_data_a", "scif0"), ++ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778", ++ "scif0_ctrl", "scif0"), ++}; ++ + #define IRQ0MR 0x30 + static void __init bockw_init(void) + { +@@ -46,6 +55,10 @@ static void __init bockw_init(void) + r8a7778_init_irq_extpin(1); + r8a7778_add_standard_devices(); + ++ pinctrl_register_mappings(bockw_pinctrl_map, ++ ARRAY_SIZE(bockw_pinctrl_map)); ++ r8a7778_pinmux_init(); ++ + fpga = ioremap_nocache(0x18200000, SZ_1M); + if (fpga) { + /* +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0208-ARM-shmobile-lager-Initialize-pinmux.patch b/patches.renesas/0208-ARM-shmobile-lager-Initialize-pinmux.patch new file mode 100644 index 00000000000..0e1b1cb1892 --- /dev/null +++ b/patches.renesas/0208-ARM-shmobile-lager-Initialize-pinmux.patch @@ -0,0 +1,54 @@ +From 3a3cfd8dea95e08a3c76d98d6f03d56acc91a591 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 8 Apr 2013 11:36:22 +0200 +Subject: ARM: shmobile: lager: Initialize pinmux + +Initialize r8a7790 pinmuxing and register mappings for the two debug +serial ports. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit e3a28ac29c1ff54a45167adb34ebedd51205c2ff) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-lager.c | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c +index f587187a..6114edd0 100644 +--- a/arch/arm/mach-shmobile/board-lager.c ++++ b/arch/arm/mach-shmobile/board-lager.c +@@ -21,15 +21,30 @@ + #include <linux/interrupt.h> + #include <linux/irqchip.h> + #include <linux/kernel.h> ++#include <linux/pinctrl/machine.h> + #include <linux/platform_device.h> + #include <mach/common.h> + #include <mach/r8a7790.h> + #include <asm/mach-types.h> + #include <asm/mach/arch.h> + ++static const struct pinctrl_map lager_pinctrl_map[] = { ++ /* SCIF0 (CN19: DEBUG SERIAL0) */ ++ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790", ++ "scif0_data", "scif0"), ++ /* SCIF1 (CN20: DEBUG SERIAL1) */ ++ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7790", ++ "scif1_data", "scif1"), ++}; ++ + static void __init lager_add_standard_devices(void) + { + r8a7790_clock_init(); ++ ++ pinctrl_register_mappings(lager_pinctrl_map, ++ ARRAY_SIZE(lager_pinctrl_map)); ++ r8a7790_pinmux_init(); ++ + r8a7790_add_standard_devices(); + } + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0209-ARM-shmobile-marzen-Use-RCAR_GP_PIN-macro.patch b/patches.renesas/0209-ARM-shmobile-marzen-Use-RCAR_GP_PIN-macro.patch new file mode 100644 index 00000000000..a31d15d7b53 --- /dev/null +++ b/patches.renesas/0209-ARM-shmobile-marzen-Use-RCAR_GP_PIN-macro.patch @@ -0,0 +1,50 @@ +From 1d94b403c7d3401f6714fea25cb5363e1d555a41 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 8 Apr 2013 12:05:32 +0200 +Subject: ARM: shmobile: marzen: Use RCAR_GP_PIN macro + +Replace hardcoded pin numbers with the RCAR_GP_PIN macro to make the +code match the documentation. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 5fcf4a3c3a5bc08bf72a50ef1332501a3c1b96bb) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-marzen.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c +index b9594e91..9112faef 100644 +--- a/arch/arm/mach-shmobile/board-marzen.c ++++ b/arch/arm/mach-shmobile/board-marzen.c +@@ -28,6 +28,7 @@ + #include <linux/leds.h> + #include <linux/dma-mapping.h> + #include <linux/pinctrl/machine.h> ++#include <linux/platform_data/gpio-rcar.h> + #include <linux/regulator/fixed.h> + #include <linux/regulator/machine.h> + #include <linux/smsc911x.h> +@@ -173,15 +174,15 @@ static struct platform_device usb_phy_device = { + static struct gpio_led marzen_leds[] = { + { + .name = "led2", +- .gpio = 157, ++ .gpio = RCAR_GP_PIN(4, 29), + .default_state = LEDS_GPIO_DEFSTATE_ON, + }, { + .name = "led3", +- .gpio = 158, ++ .gpio = RCAR_GP_PIN(4, 30), + .default_state = LEDS_GPIO_DEFSTATE_ON, + }, { + .name = "led4", +- .gpio = 159, ++ .gpio = RCAR_GP_PIN(4, 31), + .default_state = LEDS_GPIO_DEFSTATE_ON, + }, + }; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0210-ARM-shmobile-r8a7740-Make-private-clock-arrays-stati.patch b/patches.renesas/0210-ARM-shmobile-r8a7740-Make-private-clock-arrays-stati.patch new file mode 100644 index 00000000000..21dee184d4b --- /dev/null +++ b/patches.renesas/0210-ARM-shmobile-r8a7740-Make-private-clock-arrays-stati.patch @@ -0,0 +1,44 @@ +From 532897ac14177982d32fe8334b004df755e0c829 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 16 Apr 2013 17:16:19 +0200 +Subject: ARM: shmobile: r8a7740: Make private clock arrays static + +Both clock-r8a7740.c and clock-r8a7790.c define a div4_clks array as +non-static. Compiling support for both SoCs thus result in a symbol +redefinition. Fix it by defining the arrays as static. + +To avoid further similar issues, also define the main_clks as static. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 2482c589c3299c3c4aaf2f9c27e1759e972492a4) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a7740.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c +index c0d39aa6..54afa042 100644 +--- a/arch/arm/mach-shmobile/clock-r8a7740.c ++++ b/arch/arm/mach-shmobile/clock-r8a7740.c +@@ -266,7 +266,7 @@ static struct clk fsiack_clk = { + static struct clk fsibck_clk = { + }; + +-struct clk *main_clks[] = { ++static struct clk *main_clks[] = { + &extalr_clk, + &extal1_clk, + &extal2_clk, +@@ -317,7 +317,7 @@ enum { + DIV4_NR + }; + +-struct clk div4_clks[DIV4_NR] = { ++static struct clk div4_clks[DIV4_NR] = { + [DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT), + [DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT), + [DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0211-ARM-shmobile-r8a7778-correct-model-name-in-Kconfig.patch b/patches.renesas/0211-ARM-shmobile-r8a7778-correct-model-name-in-Kconfig.patch new file mode 100644 index 00000000000..96022333b49 --- /dev/null +++ b/patches.renesas/0211-ARM-shmobile-r8a7778-correct-model-name-in-Kconfig.patch @@ -0,0 +1,38 @@ +From 3c0ccb17644a4e67bc2c59eeba7b06cccc597850 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Thu, 9 May 2013 00:05:40 +0000 +Subject: ARM: shmobile: r8a7778: correct model name in Kconfig + +The correct model name is R-Car M1A or R8A77781; R8A77780 corresponds to R-Car +M1S which is a SH based SoC. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +[horms+renesas@verge.net.au: manually applied] +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit 45fa9295a0215c99019653b06f11dcda0340a7f7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + arch/arm/mach-shmobile/Kconfig +--- + arch/arm/mach-shmobile/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index 638e5c57..7a927839 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -36,7 +36,7 @@ config ARCH_R8A7740 + select RENESAS_INTC_IRQPIN + + config ARCH_R8A7778 +- bool "R-Car M1 (R8A77780)" ++ bool "R-Car M1 (R8A777801)" + select ARCH_WANT_OPTIONAL_GPIOLIB + select CPU_V7 + select SH_CLK_CPG +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0212-ARM-shmobile-sh73a0-Use-DEFINE_RES_MEM-everywhere.patch b/patches.renesas/0212-ARM-shmobile-sh73a0-Use-DEFINE_RES_MEM-everywhere.patch new file mode 100644 index 00000000000..00378e297f4 --- /dev/null +++ b/patches.renesas/0212-ARM-shmobile-sh73a0-Use-DEFINE_RES_MEM-everywhere.patch @@ -0,0 +1,172 @@ +From 65e793e2ea3069204cc8241aa1863170a6257913 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Tue, 23 Apr 2013 02:27:15 +0000 +Subject: ARM: shmobile: sh73a0: Use DEFINE_RES_MEM*() everywhere + +Convert code to use DEFINE_RES_MEM*() macros. +These macros were already used in this file, +this change makes their usage consistent throughout the file. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit abbec5f4157325cbb5ef249b0712dba57606810e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-sh73a0.c | 79 ++++++----------------------------- + 1 file changed, 13 insertions(+), 66 deletions(-) + +diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c +index 9696f364..35d512a4 100644 +--- a/arch/arm/mach-shmobile/setup-sh73a0.c ++++ b/arch/arm/mach-shmobile/setup-sh73a0.c +@@ -288,12 +288,7 @@ static struct sh_timer_config tmu00_platform_data = { + }; + + static struct resource tmu00_resources[] = { +- [0] = { +- .name = "TMU00", +- .start = 0xfff60008, +- .end = 0xfff60013, +- .flags = IORESOURCE_MEM, +- }, ++ [0] = DEFINE_RES_MEM_NAMED(0xfff60008, 0xc, "TMU00"), + [1] = { + .start = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */ + .flags = IORESOURCE_IRQ, +@@ -318,12 +313,7 @@ static struct sh_timer_config tmu01_platform_data = { + }; + + static struct resource tmu01_resources[] = { +- [0] = { +- .name = "TMU01", +- .start = 0xfff60014, +- .end = 0xfff6001f, +- .flags = IORESOURCE_MEM, +- }, ++ [0] = DEFINE_RES_MEM_NAMED(0xfff60014, 0xc, "TMU00"), + [1] = { + .start = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */ + .flags = IORESOURCE_IRQ, +@@ -341,12 +331,7 @@ static struct platform_device tmu01_device = { + }; + + static struct resource i2c0_resources[] = { +- [0] = { +- .name = "IIC0", +- .start = 0xe6820000, +- .end = 0xe6820425 - 1, +- .flags = IORESOURCE_MEM, +- }, ++ [0] = DEFINE_RES_MEM_NAMED(0xe6820000, 0x426, "IIC0"), + [1] = { + .start = gic_spi(167), + .end = gic_spi(170), +@@ -355,12 +340,7 @@ static struct resource i2c0_resources[] = { + }; + + static struct resource i2c1_resources[] = { +- [0] = { +- .name = "IIC1", +- .start = 0xe6822000, +- .end = 0xe6822425 - 1, +- .flags = IORESOURCE_MEM, +- }, ++ [0] = DEFINE_RES_MEM_NAMED(0xe6822000, 0x426, "IIC1"), + [1] = { + .start = gic_spi(51), + .end = gic_spi(54), +@@ -369,12 +349,7 @@ static struct resource i2c1_resources[] = { + }; + + static struct resource i2c2_resources[] = { +- [0] = { +- .name = "IIC2", +- .start = 0xe6824000, +- .end = 0xe6824425 - 1, +- .flags = IORESOURCE_MEM, +- }, ++ [0] = DEFINE_RES_MEM_NAMED(0xe6824000, 0x426, "IIC2"), + [1] = { + .start = gic_spi(171), + .end = gic_spi(174), +@@ -383,12 +358,7 @@ static struct resource i2c2_resources[] = { + }; + + static struct resource i2c3_resources[] = { +- [0] = { +- .name = "IIC3", +- .start = 0xe6826000, +- .end = 0xe6826425 - 1, +- .flags = IORESOURCE_MEM, +- }, ++ [0] = DEFINE_RES_MEM_NAMED(0xe6826000, 0x426, "IIC3"), + [1] = { + .start = gic_spi(183), + .end = gic_spi(186), +@@ -397,12 +367,7 @@ static struct resource i2c3_resources[] = { + }; + + static struct resource i2c4_resources[] = { +- [0] = { +- .name = "IIC4", +- .start = 0xe6828000, +- .end = 0xe6828425 - 1, +- .flags = IORESOURCE_MEM, +- }, ++ [0] = DEFINE_RES_MEM_NAMED(0xe6828000, 0x426, "IIC4"), + [1] = { + .start = gic_spi(187), + .end = gic_spi(190), +@@ -623,12 +588,7 @@ static struct sh_dmae_pdata sh73a0_dmae_platform_data = { + }; + + static struct resource sh73a0_dmae_resources[] = { +- { +- /* Registers including DMAOR and channels including DMARSx */ +- .start = 0xfe000020, +- .end = 0xfe008a00 - 1, +- .flags = IORESOURCE_MEM, +- }, ++ DEFINE_RES_MEM(0xfe000020, 0x89e0), + { + .name = "error_irq", + .start = gic_spi(129), +@@ -727,18 +687,10 @@ static struct sh_dmae_pdata sh73a0_mpdma_platform_data = { + + /* Resource order important! */ + static struct resource sh73a0_mpdma_resources[] = { +- { +- /* Channel registers and DMAOR */ +- .start = 0xec618020, +- .end = 0xec61828f, +- .flags = IORESOURCE_MEM, +- }, +- { +- /* DMARSx */ +- .start = 0xec619000, +- .end = 0xec61900b, +- .flags = IORESOURCE_MEM, +- }, ++ /* Channel registers and DMAOR */ ++ DEFINE_RES_MEM(0xec618020, 0x270), ++ /* DMARSx */ ++ DEFINE_RES_MEM(0xec619000, 0xc), + { + .name = "error_irq", + .start = gic_spi(181), +@@ -785,12 +737,7 @@ static struct platform_device pmu_device = { + + /* an IPMMU module for ICB */ + static struct resource ipmmu_resources[] = { +- [0] = { +- .name = "IPMMU", +- .start = 0xfe951000, +- .end = 0xfe9510ff, +- .flags = IORESOURCE_MEM, +- }, ++ DEFINE_RES_MEM_NAMED(0xfe951000, 0x100, "IPMMU"), + }; + + static const char * const ipmmu_dev_names[] = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0213-ARM-shmobile-remove-from-SH_FIXED_RATIO_CLK-macro.patch b/patches.renesas/0213-ARM-shmobile-remove-from-SH_FIXED_RATIO_CLK-macro.patch new file mode 100644 index 00000000000..e1129cfe1cb --- /dev/null +++ b/patches.renesas/0213-ARM-shmobile-remove-from-SH_FIXED_RATIO_CLK-macro.patch @@ -0,0 +1,35 @@ +From 8752fdc6f65954973f4008e3573fc84ec0dcfbf7 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Thu, 4 Apr 2013 00:05:42 -0700 +Subject: ARM: shmobile: remove ";" from SH_FIXED_RATIO_CLK*() macro + +Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit bdd5d28461f8f94b4eb719d229b9ed66ca28636f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/include/mach/clock.h | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/include/mach/clock.h b/arch/arm/mach-shmobile/include/mach/clock.h +index 76ac6129..89020443 100644 +--- a/arch/arm/mach-shmobile/include/mach/clock.h ++++ b/arch/arm/mach-shmobile/include/mach/clock.h +@@ -24,11 +24,11 @@ struct clk name = { \ + } + + #define SH_FIXED_RATIO_CLK(name, p, r) \ +-static SH_FIXED_RATIO_CLKg(name, p, r); ++static SH_FIXED_RATIO_CLKg(name, p, r) + + #define SH_FIXED_RATIO_CLK_SET(name, p, m, d) \ + SH_CLK_RATIO(name, m, d); \ +- SH_FIXED_RATIO_CLK(name, p, name); ++ SH_FIXED_RATIO_CLK(name, p, name) + + #define SH_CLK_SET_RATIO(p, m, d) \ + { \ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0214-ARM-shmobile-use-do-while-on-SH_CLK_SET_RATIO.patch b/patches.renesas/0214-ARM-shmobile-use-do-while-on-SH_CLK_SET_RATIO.patch new file mode 100644 index 00000000000..bf7d0ac474a --- /dev/null +++ b/patches.renesas/0214-ARM-shmobile-use-do-while-on-SH_CLK_SET_RATIO.patch @@ -0,0 +1,34 @@ +From 968deade76d07ef32c7d961a1d2784c8576a6a50 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Fri, 12 Apr 2013 00:41:07 -0700 +Subject: ARM: shmobile: use do{ }while() on SH_CLK_SET_RATIO() + +SH_CLK_SET_RATIO() will be trouble without this patch + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit b6825a02fd3c43f2bd2e126fdbe9d83d6ca44f4e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/include/mach/clock.h | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/include/mach/clock.h b/arch/arm/mach-shmobile/include/mach/clock.h +index 89020443..03e56074 100644 +--- a/arch/arm/mach-shmobile/include/mach/clock.h ++++ b/arch/arm/mach-shmobile/include/mach/clock.h +@@ -31,9 +31,9 @@ static SH_FIXED_RATIO_CLKg(name, p, r) + SH_FIXED_RATIO_CLK(name, p, name) + + #define SH_CLK_SET_RATIO(p, m, d) \ +-{ \ ++do { \ + (p)->mul = m; \ + (p)->div = d; \ +-} ++} while (0) + + #endif +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0215-ARM-shmobile-r8a7778-fixup-Ether-setup-code-position.patch b/patches.renesas/0215-ARM-shmobile-r8a7778-fixup-Ether-setup-code-position.patch new file mode 100644 index 00000000000..7729cc56f2b --- /dev/null +++ b/patches.renesas/0215-ARM-shmobile-r8a7778-fixup-Ether-setup-code-position.patch @@ -0,0 +1,75 @@ +From 29cfcc3507c5a5cf98537ae39b069e9cee6df975 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Mon, 8 Apr 2013 22:33:44 -0700 +Subject: ARM: shmobile: r8a7778: fixup Ether setup code position + +Ether setup code position was scattering. +This patch fixes it up + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 734e02f888c97e285ce3481dc6418b8dc27b22f4) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + arch/arm/mach-shmobile/setup-r8a7778.c +--- + arch/arm/mach-shmobile/setup-r8a7778.c | 28 ++++++++++++++-------------- + 1 file changed, 14 insertions(+), 14 deletions(-) + +diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c +index 1f36ecc3..06ead4a0 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7778.c ++++ b/arch/arm/mach-shmobile/setup-r8a7778.c +@@ -81,12 +81,6 @@ static struct sh_timer_config sh_tmu1_platform_data = { + .clocksource_rating = 200, + }; + +-/* Ether */ +-static struct resource ether_resources[] = { +- DEFINE_RES_MEM(0xfde00000, 0x400), +- DEFINE_RES_IRQ(gic_iid(0x89)), +-}; +- + #define r8a7778_register_tmu(idx) \ + platform_device_register_resndata( \ + &platform_bus, "sh_tmu", idx, \ +@@ -95,6 +89,20 @@ static struct resource ether_resources[] = { + &sh_tmu##idx##_platform_data, \ + sizeof(sh_tmu##idx##_platform_data)) + ++/* Ether */ ++static struct resource ether_resources[] = { ++ DEFINE_RES_MEM(0xfde00000, 0x400), ++ DEFINE_RES_IRQ(gic_iid(0x89)), ++}; ++ ++void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata) ++{ ++ platform_device_register_resndata(&platform_bus, "sh_eth", -1, ++ ether_resources, ++ ARRAY_SIZE(ether_resources), ++ pdata, sizeof(*pdata)); ++} ++ + /* PFC/GPIO */ + static struct resource pfc_resources[] = { + DEFINE_RES_MEM(0xfffc0000, 0x118), +@@ -165,14 +173,6 @@ void __init r8a7778_add_standard_devices(void) + r8a7778_register_tmu(1); + } + +-void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata) +-{ +- platform_device_register_resndata(&platform_bus, "sh_eth", -1, +- ether_resources, +- ARRAY_SIZE(ether_resources), +- pdata, sizeof(*pdata)); +-} +- + static struct renesas_intc_irqpin_config irqpin_platform_data = { + .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ + .sense_bitfield_width = 2, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0216-ARM-shmobile-r8a7740-Add-interim-sh-eth-device-name-.patch b/patches.renesas/0216-ARM-shmobile-r8a7740-Add-interim-sh-eth-device-name-.patch new file mode 100644 index 00000000000..997cde30e20 --- /dev/null +++ b/patches.renesas/0216-ARM-shmobile-r8a7740-Add-interim-sh-eth-device-name-.patch @@ -0,0 +1,32 @@ +From deae674c502ca18df8864c82d145a0d0c2b7daf6 Mon Sep 17 00:00:00 2001 +From: Bastian Hecht <hechtb@gmail.com> +Date: Tue, 18 Dec 2012 17:22:38 +0000 +Subject: ARM: shmobile: r8a7740: Add interim sh-eth device name to clocks list + +When we use the ethernet device via DT setup, we need to add it +to a lookup list until this is properly handled later in a DT-only +fashion. + +Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 9e0b428f079d7b4c9d59c868b6f5b4ad2193e86b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a7740.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c +index 54afa042..008b11cf 100644 +--- a/arch/arm/mach-shmobile/clock-r8a7740.c ++++ b/arch/arm/mach-shmobile/clock-r8a7740.c +@@ -592,6 +592,7 @@ static struct clk_lookup lookups[] = { + CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP312]), + CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), + CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP309]), ++ CLKDEV_DEV_ID("e9a00000.sh-eth", &mstp_clks[MSTP309]), + + CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), + CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0217-ARM-shmobile-r8a7740-Add-I2C-DT-clock-names.patch b/patches.renesas/0217-ARM-shmobile-r8a7740-Add-I2C-DT-clock-names.patch new file mode 100644 index 00000000000..22f964aeddc --- /dev/null +++ b/patches.renesas/0217-ARM-shmobile-r8a7740-Add-I2C-DT-clock-names.patch @@ -0,0 +1,38 @@ +From b68afd32522fa03e86b084f2c42366b97d83260d Mon Sep 17 00:00:00 2001 +From: Bastian Hecht <hechtb@gmail.com> +Date: Wed, 17 Apr 2013 12:34:03 +0200 +Subject: ARM: shmobile: r8a7740: Add I2C DT clock names + +Add clock association for i2c0 and i2c1 for the new DT names. + +Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 8d79071eec6a343a30057def27b79ac41eb4f192) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a7740.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c +index 008b11cf..ecdc0a4c 100644 +--- a/arch/arm/mach-shmobile/clock-r8a7740.c ++++ b/arch/arm/mach-shmobile/clock-r8a7740.c +@@ -551,6 +551,7 @@ static struct clk_lookup lookups[] = { + CLKDEV_DEV_ID("sh_tmu.4", &mstp_clks[MSTP111]), + CLKDEV_DEV_ID("sh_tmu.5", &mstp_clks[MSTP111]), + CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), ++ CLKDEV_DEV_ID("fff20000.i2c", &mstp_clks[MSTP116]), + CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), + CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), + CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), +@@ -584,6 +585,7 @@ static struct clk_lookup lookups[] = { + CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), + CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), + CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), ++ CLKDEV_DEV_ID("e6c20000.i2c", &mstp_clks[MSTP323]), + CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]), + CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), + CLKDEV_DEV_ID("e6850000.sdhi", &mstp_clks[MSTP314]), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0218-ARM-shmobile-r8a7740-add-TPU-PWM-support.patch b/patches.renesas/0218-ARM-shmobile-r8a7740-add-TPU-PWM-support.patch new file mode 100644 index 00000000000..492e54a67f4 --- /dev/null +++ b/patches.renesas/0218-ARM-shmobile-r8a7740-add-TPU-PWM-support.patch @@ -0,0 +1,46 @@ +From b7775ae3b628d980ced02b06a294fc66fe6e5687 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 26 Oct 2012 15:38:47 +0200 +Subject: ARM: shmobile: r8a7740: add TPU PWM support + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Tested-by: Simon Horman <horms@verge.net.au> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 58645fe9a81d517eb99a137868f11ac39aa71eb9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a7740.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c +index ecdc0a4c..7fd32d60 100644 +--- a/arch/arm/mach-shmobile/clock-r8a7740.c ++++ b/arch/arm/mach-shmobile/clock-r8a7740.c +@@ -461,7 +461,7 @@ enum { + + MSTP329, MSTP328, MSTP323, MSTP320, + MSTP314, MSTP313, MSTP312, +- MSTP309, ++ MSTP309, MSTP304, + + MSTP416, MSTP415, MSTP407, MSTP406, + +@@ -499,6 +499,7 @@ static struct clk mstp_clks[MSTP_NR] = { + [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */ + [MSTP312] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */ + [MSTP309] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 9, 0), /* GEther */ ++ [MSTP304] = SH_CLK_MSTP32(&div4_clks[DIV4_CP], SMSTPCR3, 4, 0), /* TPU0 */ + + [MSTP416] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 16, 0), /* USBHOST */ + [MSTP415] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */ +@@ -595,6 +596,7 @@ static struct clk_lookup lookups[] = { + CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), + CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP309]), + CLKDEV_DEV_ID("e9a00000.sh-eth", &mstp_clks[MSTP309]), ++ CLKDEV_DEV_ID("renesas_tpu_pwm", &mstp_clks[MSTP304]), + + CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), + CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0219-ARM-shmobile-r8a73a4-add-main-clock.patch b/patches.renesas/0219-ARM-shmobile-r8a73a4-add-main-clock.patch new file mode 100644 index 00000000000..6aee2c8bdf1 --- /dev/null +++ b/patches.renesas/0219-ARM-shmobile-r8a73a4-add-main-clock.patch @@ -0,0 +1,122 @@ +From e43eeb4c203a65a4f9df3160631584271f8f1641 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Thu, 4 Apr 2013 21:20:40 -0700 +Subject: ARM: shmobile: r8a73a4: add main clock + +Almost all clock needs main clock which is basis clock on r8a73a4. +This patch adds it, and, set parent clock via CKSCR register. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 5e634d98635a135016d77e03de2cecbaba8d9d56) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a73a4.c | 53 ++++++++++++++++++++++++++++++++++ + 1 file changed, 53 insertions(+) + +diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c +index e710c00c..42942b43 100644 +--- a/arch/arm/mach-shmobile/clock-r8a73a4.c ++++ b/arch/arm/mach-shmobile/clock-r8a73a4.c +@@ -22,6 +22,7 @@ + #include <linux/kernel.h> + #include <linux/sh_clk.h> + #include <linux/clkdev.h> ++#include <mach/clock.h> + #include <mach/common.h> + + #define CPG_BASE 0xe6150000 +@@ -31,6 +32,8 @@ + #define SMSTPCR2 0xe6150138 + #define SMSTPCR5 0xe6150144 + ++#define CKSCR 0xE61500C0 ++ + static struct clk_mapping cpg_mapping = { + .phys = CPG_BASE, + .len = CPG_LEN, +@@ -51,10 +54,32 @@ static struct clk extal2_clk = { + .mapping = &cpg_mapping, + }; + ++static struct sh_clk_ops followparent_clk_ops = { ++ .recalc = followparent_recalc, ++}; ++ ++static struct clk main_clk = { ++ /* .parent will be set r8a73a4_clock_init */ ++ .ops = &followparent_clk_ops, ++}; ++ ++SH_CLK_RATIO(div2, 1, 2); ++SH_CLK_RATIO(div4, 1, 4); ++ ++SH_FIXED_RATIO_CLK(main_div2_clk, main_clk, div2); ++SH_FIXED_RATIO_CLK(extal1_div2_clk, extal1_clk, div2); ++SH_FIXED_RATIO_CLK(extal2_div2_clk, extal2_clk, div2); ++SH_FIXED_RATIO_CLK(extal2_div4_clk, extal2_clk, div4); ++ + static struct clk *main_clks[] = { + &extalr_clk, + &extal1_clk, ++ &extal1_div2_clk, + &extal2_clk, ++ &extal2_div2_clk, ++ &extal2_div4_clk, ++ &main_clk, ++ &main_div2_clk, + }; + + enum { +@@ -74,6 +99,13 @@ static struct clk mstp_clks[MSTP_NR] = { + }; + + static struct clk_lookup lookups[] = { ++ /* main clock */ ++ CLKDEV_CON_ID("extal1", &extal1_clk), ++ CLKDEV_CON_ID("extal1_div2", &extal1_div2_clk), ++ CLKDEV_CON_ID("extal2", &extal2_clk), ++ CLKDEV_CON_ID("extal2_div2", &extal2_div2_clk), ++ CLKDEV_CON_ID("extal2_div4", &extal2_div4_clk), ++ + CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), + CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), + CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), +@@ -90,6 +122,7 @@ void __init r8a73a4_clock_init(void) + { + void __iomem *cpg_base, *reg; + int k, ret = 0; ++ u32 ckscr; + + /* fix MPCLK to EXTAL2 for now. + * this is needed until more detailed clock topology is supported +@@ -100,6 +133,26 @@ void __init r8a73a4_clock_init(void) + iowrite32(ioread32(reg) | 1 << 7 | 0x0c, reg); /* set CKSEL */ + iounmap(cpg_base); + ++ reg = ioremap_nocache(CKSCR, PAGE_SIZE); ++ BUG_ON(!reg); ++ ckscr = ioread32(reg); ++ iounmap(reg); ++ ++ switch ((ckscr >> 28) & 0x3) { ++ case 0: ++ main_clk.parent = &extal1_clk; ++ break; ++ case 1: ++ main_clk.parent = &extal1_div2_clk; ++ break; ++ case 2: ++ main_clk.parent = &extal2_clk; ++ break; ++ case 3: ++ main_clk.parent = &extal2_div2_clk; ++ break; ++ } ++ + for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) + ret = clk_register(main_clks[k]); + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0220-ARM-shmobile-r8a73a4-add-pll-clocks.patch b/patches.renesas/0220-ARM-shmobile-r8a73a4-add-pll-clocks.patch new file mode 100644 index 00000000000..37e4d63e937 --- /dev/null +++ b/patches.renesas/0220-ARM-shmobile-r8a73a4-add-pll-clocks.patch @@ -0,0 +1,151 @@ +From 83f0d79728f06e5635568560d84017113acd2b25 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Thu, 4 Apr 2013 21:21:39 -0700 +Subject: ARM: shmobile: r8a73a4: add pll clocks + +PLL clocks are basis clock for other clock. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 0c3091ad45ac975244a7c0570e10b645743bb01c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a73a4.c | 101 +++++++++++++++++++++++++++++++++ + 1 file changed, 101 insertions(+) + +diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c +index 42942b43..2be592f6 100644 +--- a/arch/arm/mach-shmobile/clock-r8a73a4.c ++++ b/arch/arm/mach-shmobile/clock-r8a73a4.c +@@ -33,6 +33,14 @@ + #define SMSTPCR5 0xe6150144 + + #define CKSCR 0xE61500C0 ++#define PLLECR 0xE61500D0 ++#define PLL1CR 0xE6150028 ++#define PLL2CR 0xE615002C ++#define PLL2SCR 0xE61501F4 ++#define PLL2HCR 0xE61501E4 ++ ++ ++#define CPG_MAP(o) ((o - CPG_BASE) + cpg_mapping.base) + + static struct clk_mapping cpg_mapping = { + .phys = CPG_BASE, +@@ -71,6 +79,86 @@ SH_FIXED_RATIO_CLK(extal1_div2_clk, extal1_clk, div2); + SH_FIXED_RATIO_CLK(extal2_div2_clk, extal2_clk, div2); + SH_FIXED_RATIO_CLK(extal2_div4_clk, extal2_clk, div4); + ++/* ++ * PLL clocks ++ */ ++static struct clk *pll_parent_main[] = { ++ [0] = &main_clk, ++ [1] = &main_div2_clk ++}; ++ ++static struct clk *pll_parent_main_extal[8] = { ++ [0] = &main_div2_clk, ++ [1] = &extal2_div2_clk, ++ [3] = &extal2_div4_clk, ++ [4] = &main_clk, ++ [5] = &extal2_clk, ++}; ++ ++static unsigned long pll_recalc(struct clk *clk) ++{ ++ unsigned long mult = 1; ++ ++ if (ioread32(CPG_MAP(PLLECR)) & (1 << clk->enable_bit)) ++ mult = (((ioread32(clk->mapped_reg) >> 24) & 0x7f) + 1); ++ ++ return clk->parent->rate * mult; ++} ++ ++static int pll_set_parent(struct clk *clk, struct clk *parent) ++{ ++ u32 val; ++ int i, ret; ++ ++ if (!clk->parent_table || !clk->parent_num) ++ return -EINVAL; ++ ++ /* Search the parent */ ++ for (i = 0; i < clk->parent_num; i++) ++ if (clk->parent_table[i] == parent) ++ break; ++ ++ if (i == clk->parent_num) ++ return -ENODEV; ++ ++ ret = clk_reparent(clk, parent); ++ if (ret < 0) ++ return ret; ++ ++ val = ioread32(clk->mapped_reg) & ++ ~(((1 << clk->src_width) - 1) << clk->src_shift); ++ ++ iowrite32(val | i << clk->src_shift, clk->mapped_reg); ++ ++ return 0; ++} ++ ++static struct sh_clk_ops pll_clk_ops = { ++ .recalc = pll_recalc, ++ .set_parent = pll_set_parent, ++}; ++ ++#define PLL_CLOCK(name, p, pt, w, s, reg, e) \ ++ static struct clk name = { \ ++ .ops = &pll_clk_ops, \ ++ .flags = CLK_ENABLE_ON_INIT, \ ++ .parent = p, \ ++ .parent_table = pt, \ ++ .parent_num = ARRAY_SIZE(pt), \ ++ .src_width = w, \ ++ .src_shift = s, \ ++ .enable_reg = (void __iomem *)reg, \ ++ .enable_bit = e, \ ++ .mapping = &cpg_mapping, \ ++ } ++ ++PLL_CLOCK(pll1_clk, &main_clk, pll_parent_main, 1, 7, PLL1CR, 1); ++PLL_CLOCK(pll2_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2CR, 2); ++PLL_CLOCK(pll2s_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2SCR, 4); ++PLL_CLOCK(pll2h_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2HCR, 5); ++ ++SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2); ++ + static struct clk *main_clks[] = { + &extalr_clk, + &extal1_clk, +@@ -80,6 +168,11 @@ static struct clk *main_clks[] = { + &extal2_div4_clk, + &main_clk, + &main_div2_clk, ++ &pll1_clk, ++ &pll1_div2_clk, ++ &pll2_clk, ++ &pll2s_clk, ++ &pll2h_clk, + }; + + enum { +@@ -106,6 +199,14 @@ static struct clk_lookup lookups[] = { + CLKDEV_CON_ID("extal2_div2", &extal2_div2_clk), + CLKDEV_CON_ID("extal2_div4", &extal2_div4_clk), + ++ /* pll clock */ ++ CLKDEV_CON_ID("pll1", &pll1_clk), ++ CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk), ++ CLKDEV_CON_ID("pll2", &pll2_clk), ++ CLKDEV_CON_ID("pll2s", &pll2s_clk), ++ CLKDEV_CON_ID("pll2h", &pll2h_clk), ++ ++ /* MSTP */ + CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), + CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), + CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0221-ARM-shmobile-r8a73a4-add-div4-clocks.patch b/patches.renesas/0221-ARM-shmobile-r8a73a4-add-div4-clocks.patch new file mode 100644 index 00000000000..00c9bca5616 --- /dev/null +++ b/patches.renesas/0221-ARM-shmobile-r8a73a4-add-div4-clocks.patch @@ -0,0 +1,88 @@ +From df781d4ddcb4681f3258b27dcb1a597f63a4c1d2 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Thu, 4 Apr 2013 21:22:16 -0700 +Subject: ARM: shmobile: r8a73a4: add div4 clocks + +DIV4 clocks control each core clocks. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit b89edf344696e7783312a370b6477beea90116f9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a73a4.c | 45 ++++++++++++++++++++++++++++++++++ + 1 file changed, 45 insertions(+) + +diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c +index 2be592f6..147314ac 100644 +--- a/arch/arm/mach-shmobile/clock-r8a73a4.c ++++ b/arch/arm/mach-shmobile/clock-r8a73a4.c +@@ -32,6 +32,8 @@ + #define SMSTPCR2 0xe6150138 + #define SMSTPCR5 0xe6150144 + ++#define FRQCRA 0xE6150000 ++#define FRQCRB 0xE6150004 + #define CKSCR 0xE61500C0 + #define PLLECR 0xE61500D0 + #define PLL1CR 0xE6150028 +@@ -175,6 +177,46 @@ static struct clk *main_clks[] = { + &pll2h_clk, + }; + ++/* DIV4 */ ++static void div4_kick(struct clk *clk) ++{ ++ unsigned long value; ++ ++ /* set KICK bit in FRQCRB to update hardware setting */ ++ value = ioread32(CPG_MAP(FRQCRB)); ++ value |= (1 << 31); ++ iowrite32(value, CPG_MAP(FRQCRB)); ++} ++ ++static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10}; ++ ++static struct clk_div_mult_table div4_div_mult_table = { ++ .divisors = divisors, ++ .nr_divisors = ARRAY_SIZE(divisors), ++}; ++ ++static struct clk_div4_table div4_table = { ++ .div_mult_table = &div4_div_mult_table, ++ .kick = div4_kick, ++}; ++ ++enum { ++ DIV4_I, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2, ++ DIV4_ZX, DIV4_ZS, DIV4_HP, ++ DIV4_NR }; ++ ++static struct clk div4_clks[DIV4_NR] = { ++ [DIV4_I] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 20, 0x0dff, CLK_ENABLE_ON_INIT), ++ [DIV4_M3] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT), ++ [DIV4_B] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 8, 0x0dff, CLK_ENABLE_ON_INIT), ++ [DIV4_M1] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 4, 0x1dff, 0), ++ [DIV4_M2] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 0, 0x1dff, 0), ++ [DIV4_ZX] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 12, 0x0dff, 0), ++ [DIV4_ZS] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 8, 0x0dff, 0), ++ [DIV4_HP] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 4, 0x0dff, 0), ++}; ++ ++/* MSTP */ + enum { + MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, + MSTP522, +@@ -258,6 +300,9 @@ void __init r8a73a4_clock_init(void) + ret = clk_register(main_clks[k]); + + if (!ret) ++ ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); ++ ++ if (!ret) + ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); + + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0222-ARM-shmobile-r8a73a4-add-div6-clocks.patch b/patches.renesas/0222-ARM-shmobile-r8a73a4-add-div6-clocks.patch new file mode 100644 index 00000000000..aea442aed31 --- /dev/null +++ b/patches.renesas/0222-ARM-shmobile-r8a73a4-add-div6-clocks.patch @@ -0,0 +1,280 @@ +From 7f596d8c4af42b10957fab62fb952406cab4fcf6 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Thu, 4 Apr 2013 21:22:41 -0700 +Subject: ARM: shmobile: r8a73a4: add div6 clocks + +DIV6 clocks control each core clocks. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 9051e9125bf1088780c84deef6e16cf1c01f035c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a73a4.c | 182 +++++++++++++++++++++++++++++---- + 1 file changed, 163 insertions(+), 19 deletions(-) + +diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c +index 147314ac..f6227bb1 100644 +--- a/arch/arm/mach-shmobile/clock-r8a73a4.c ++++ b/arch/arm/mach-shmobile/clock-r8a73a4.c +@@ -28,19 +28,34 @@ + #define CPG_BASE 0xe6150000 + #define CPG_LEN 0x270 + +-#define MPCKCR 0xe6150080 + #define SMSTPCR2 0xe6150138 + #define SMSTPCR5 0xe6150144 + + #define FRQCRA 0xE6150000 + #define FRQCRB 0xE6150004 +-#define CKSCR 0xE61500C0 ++#define VCLKCR1 0xE6150008 ++#define VCLKCR2 0xE615000C ++#define VCLKCR3 0xE615001C ++#define VCLKCR4 0xE6150014 ++#define VCLKCR5 0xE6150034 ++#define ZBCKCR 0xE6150010 ++#define SD0CKCR 0xE6150074 ++#define SD1CKCR 0xE6150078 ++#define SD2CKCR 0xE615007C ++#define MMC0CKCR 0xE6150240 ++#define MMC1CKCR 0xE6150244 ++#define FSIACKCR 0xE6150018 ++#define FSIBCKCR 0xE6150090 ++#define MPCKCR 0xe6150080 ++#define SPUVCKCR 0xE6150094 ++#define HSICKCR 0xE615026C ++#define M4CKCR 0xE6150098 + #define PLLECR 0xE61500D0 + #define PLL1CR 0xE6150028 + #define PLL2CR 0xE615002C + #define PLL2SCR 0xE61501F4 + #define PLL2HCR 0xE61501E4 +- ++#define CKSCR 0xE61500C0 + + #define CPG_MAP(o) ((o - CPG_BASE) + cpg_mapping.base) + +@@ -81,6 +96,13 @@ SH_FIXED_RATIO_CLK(extal1_div2_clk, extal1_clk, div2); + SH_FIXED_RATIO_CLK(extal2_div2_clk, extal2_clk, div2); + SH_FIXED_RATIO_CLK(extal2_div4_clk, extal2_clk, div4); + ++/* External FSIACK/FSIBCK clock */ ++static struct clk fsiack_clk = { ++}; ++ ++static struct clk fsibck_clk = { ++}; ++ + /* + * PLL clocks + */ +@@ -170,6 +192,8 @@ static struct clk *main_clks[] = { + &extal2_div4_clk, + &main_clk, + &main_div2_clk, ++ &fsiack_clk, ++ &fsibck_clk, + &pll1_clk, + &pll1_div2_clk, + &pll2_clk, +@@ -216,6 +240,111 @@ static struct clk div4_clks[DIV4_NR] = { + [DIV4_HP] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 4, 0x0dff, 0), + }; + ++enum { ++ DIV6_ZB, ++ DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2, ++ DIV6_MMC0, DIV6_MMC1, ++ DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_VCK4, DIV6_VCK5, ++ DIV6_FSIA, DIV6_FSIB, ++ DIV6_MP, DIV6_M4, DIV6_HSI, DIV6_SPUV, ++ DIV6_NR }; ++ ++static struct clk *div6_parents[8] = { ++ [0] = &pll1_div2_clk, ++ [1] = &pll2s_clk, ++ [3] = &extal2_clk, ++ [4] = &main_div2_clk, ++ [6] = &extalr_clk, ++}; ++ ++static struct clk *fsia_parents[4] = { ++ [0] = &pll1_div2_clk, ++ [1] = &pll2s_clk, ++ [2] = &fsiack_clk, ++}; ++ ++static struct clk *fsib_parents[4] = { ++ [0] = &pll1_div2_clk, ++ [1] = &pll2s_clk, ++ [2] = &fsibck_clk, ++}; ++ ++static struct clk *mp_parents[4] = { ++ [0] = &pll1_div2_clk, ++ [1] = &pll2s_clk, ++ [2] = &extal2_clk, ++ [3] = &extal2_clk, ++}; ++ ++static struct clk *m4_parents[2] = { ++ [0] = &pll2s_clk, ++}; ++ ++static struct clk *hsi_parents[4] = { ++ [0] = &pll2h_clk, ++ [1] = &pll1_div2_clk, ++ [3] = &pll2s_clk, ++}; ++ ++/*** FIXME *** ++ * SH_CLK_DIV6_EXT() macro doesn't care .mapping ++ * but, it is necessary on R-Car (= ioremap() base CPG) ++ * The difference between ++ * SH_CLK_DIV6_EXT() <--> SH_CLK_MAP_DIV6_EXT() ++ * is only .mapping ++ */ ++#define SH_CLK_MAP_DIV6_EXT(_reg, _flags, _parents, \ ++ _num_parents, _src_shift, _src_width) \ ++{ \ ++ .enable_reg = (void __iomem *)_reg, \ ++ .enable_bit = 0, /* unused */ \ ++ .flags = _flags | CLK_MASK_DIV_ON_DISABLE, \ ++ .div_mask = SH_CLK_DIV6_MSK, \ ++ .parent_table = _parents, \ ++ .parent_num = _num_parents, \ ++ .src_shift = _src_shift, \ ++ .src_width = _src_width, \ ++ .mapping = &cpg_mapping, \ ++} ++ ++static struct clk div6_clks[DIV6_NR] = { ++ [DIV6_ZB] = SH_CLK_MAP_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT, ++ div6_parents, 2, 7, 1), ++ [DIV6_SDHI0] = SH_CLK_MAP_DIV6_EXT(SD0CKCR, 0, ++ div6_parents, 2, 6, 2), ++ [DIV6_SDHI1] = SH_CLK_MAP_DIV6_EXT(SD1CKCR, 0, ++ div6_parents, 2, 6, 2), ++ [DIV6_SDHI2] = SH_CLK_MAP_DIV6_EXT(SD2CKCR, 0, ++ div6_parents, 2, 6, 2), ++ [DIV6_MMC0] = SH_CLK_MAP_DIV6_EXT(MMC0CKCR, 0, ++ div6_parents, 2, 6, 2), ++ [DIV6_MMC1] = SH_CLK_MAP_DIV6_EXT(MMC1CKCR, 0, ++ div6_parents, 2, 6, 2), ++ [DIV6_VCK1] = SH_CLK_MAP_DIV6_EXT(VCLKCR1, 0, /* didn't care bit[6-7] */ ++ div6_parents, ARRAY_SIZE(div6_parents), 12, 3), ++ [DIV6_VCK2] = SH_CLK_MAP_DIV6_EXT(VCLKCR2, 0, /* didn't care bit[6-7] */ ++ div6_parents, ARRAY_SIZE(div6_parents), 12, 3), ++ [DIV6_VCK3] = SH_CLK_MAP_DIV6_EXT(VCLKCR3, 0, /* didn't care bit[6-7] */ ++ div6_parents, ARRAY_SIZE(div6_parents), 12, 3), ++ [DIV6_VCK4] = SH_CLK_MAP_DIV6_EXT(VCLKCR4, 0, /* didn't care bit[6-7] */ ++ div6_parents, ARRAY_SIZE(div6_parents), 12, 3), ++ [DIV6_VCK5] = SH_CLK_MAP_DIV6_EXT(VCLKCR5, 0, /* didn't care bit[6-7] */ ++ div6_parents, ARRAY_SIZE(div6_parents), 12, 3), ++ [DIV6_FSIA] = SH_CLK_MAP_DIV6_EXT(FSIACKCR, 0, ++ fsia_parents, ARRAY_SIZE(fsia_parents), 6, 2), ++ [DIV6_FSIB] = SH_CLK_MAP_DIV6_EXT(FSIBCKCR, 0, ++ fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2), ++ [DIV6_MP] = SH_CLK_MAP_DIV6_EXT(MPCKCR, 0, /* it needs bit[9-11] control */ ++ mp_parents, ARRAY_SIZE(mp_parents), 6, 2), ++ /* pll2s will be selected always for M4 */ ++ [DIV6_M4] = SH_CLK_MAP_DIV6_EXT(M4CKCR, 0, /* it needs bit[9] control */ ++ m4_parents, ARRAY_SIZE(m4_parents), 6, 1), ++ [DIV6_HSI] = SH_CLK_MAP_DIV6_EXT(HSICKCR, 0, /* it needs bit[9] control */ ++ hsi_parents, ARRAY_SIZE(hsi_parents), 6, 2), ++ [DIV6_SPUV] = SH_CLK_MAP_DIV6_EXT(SPUVCKCR, 0, ++ mp_parents, ARRAY_SIZE(mp_parents), 6, 2), ++}; ++ + /* MSTP */ + enum { + MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, +@@ -224,12 +353,12 @@ enum { + }; + + static struct clk mstp_clks[MSTP_NR] = { +- [MSTP204] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 4, 0), /* SCIFA0 */ +- [MSTP203] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 3, 0), /* SCIFA1 */ +- [MSTP206] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 6, 0), /* SCIFB0 */ +- [MSTP207] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ +- [MSTP216] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ +- [MSTP217] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 17, 0), /* SCIFB3 */ ++ [MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 4, 0), /* SCIFA0 */ ++ [MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 3, 0), /* SCIFA1 */ ++ [MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 6, 0), /* SCIFB0 */ ++ [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 7, 0), /* SCIFB1 */ ++ [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 16, 0), /* SCIFB2 */ ++ [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 17, 0), /* SCIFB3 */ + [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */ + }; + +@@ -240,6 +369,8 @@ static struct clk_lookup lookups[] = { + CLKDEV_CON_ID("extal2", &extal2_clk), + CLKDEV_CON_ID("extal2_div2", &extal2_div2_clk), + CLKDEV_CON_ID("extal2_div4", &extal2_div4_clk), ++ CLKDEV_CON_ID("fsiack", &fsiack_clk), ++ CLKDEV_CON_ID("fsibck", &fsibck_clk), + + /* pll clock */ + CLKDEV_CON_ID("pll1", &pll1_clk), +@@ -248,6 +379,25 @@ static struct clk_lookup lookups[] = { + CLKDEV_CON_ID("pll2s", &pll2s_clk), + CLKDEV_CON_ID("pll2h", &pll2h_clk), + ++ /* DIV6 */ ++ CLKDEV_CON_ID("zb", &div6_clks[DIV6_ZB]), ++ CLKDEV_CON_ID("sdhi0", &div6_clks[DIV6_SDHI0]), ++ CLKDEV_CON_ID("sdhi1", &div6_clks[DIV6_SDHI1]), ++ CLKDEV_CON_ID("sdhi2", &div6_clks[DIV6_SDHI2]), ++ CLKDEV_CON_ID("mmc0", &div6_clks[DIV6_MMC0]), ++ CLKDEV_CON_ID("mmc1", &div6_clks[DIV6_MMC1]), ++ CLKDEV_CON_ID("vck1", &div6_clks[DIV6_VCK1]), ++ CLKDEV_CON_ID("vck2", &div6_clks[DIV6_VCK2]), ++ CLKDEV_CON_ID("vck3", &div6_clks[DIV6_VCK3]), ++ CLKDEV_CON_ID("vck4", &div6_clks[DIV6_VCK4]), ++ CLKDEV_CON_ID("vck5", &div6_clks[DIV6_VCK5]), ++ CLKDEV_CON_ID("fsia", &div6_clks[DIV6_FSIA]), ++ CLKDEV_CON_ID("fsib", &div6_clks[DIV6_FSIB]), ++ CLKDEV_CON_ID("mp", &div6_clks[DIV6_MP]), ++ CLKDEV_CON_ID("m4", &div6_clks[DIV6_M4]), ++ CLKDEV_CON_ID("hsi", &div6_clks[DIV6_HSI]), ++ CLKDEV_CON_ID("spuv", &div6_clks[DIV6_SPUV]), ++ + /* MSTP */ + CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), + CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), +@@ -263,19 +413,10 @@ static struct clk_lookup lookups[] = { + + void __init r8a73a4_clock_init(void) + { +- void __iomem *cpg_base, *reg; ++ void __iomem *reg; + int k, ret = 0; + u32 ckscr; + +- /* fix MPCLK to EXTAL2 for now. +- * this is needed until more detailed clock topology is supported +- */ +- cpg_base = ioremap_nocache(CPG_BASE, CPG_LEN); +- BUG_ON(!cpg_base); +- reg = cpg_base + (MPCKCR - CPG_BASE); +- iowrite32(ioread32(reg) | 1 << 7 | 0x0c, reg); /* set CKSEL */ +- iounmap(cpg_base); +- + reg = ioremap_nocache(CKSCR, PAGE_SIZE); + BUG_ON(!reg); + ckscr = ioread32(reg); +@@ -303,6 +444,9 @@ void __init r8a73a4_clock_init(void) + ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); + + if (!ret) ++ ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR); ++ ++ if (!ret) + ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); + + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0223-ARM-shmobile-r8a7779-Add-PCIe-clocks.patch b/patches.renesas/0223-ARM-shmobile-r8a7779-Add-PCIe-clocks.patch new file mode 100644 index 00000000000..c53bd2e07f0 --- /dev/null +++ b/patches.renesas/0223-ARM-shmobile-r8a7779-Add-PCIe-clocks.patch @@ -0,0 +1,45 @@ +From 0ea5997ae51bd78f955019c64b3481f366609a85 Mon Sep 17 00:00:00 2001 +From: Phil Edworthy <Phil.Edworthy@renesas.com> +Date: Tue, 9 Apr 2013 14:35:15 +0000 +Subject: ARM: shmobile: r8a7779: Add PCIe clocks + +Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 0f704e1285100452ad8b02a1658fe723bc93aeee) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a7779.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c +index 31d5cd4d..9daeb8c3 100644 +--- a/arch/arm/mach-shmobile/clock-r8a7779.c ++++ b/arch/arm/mach-shmobile/clock-r8a7779.c +@@ -112,7 +112,7 @@ static struct clk *main_clks[] = { + }; + + enum { MSTP323, MSTP322, MSTP321, MSTP320, +- MSTP115, MSTP114, ++ MSTP116, MSTP115, MSTP114, + MSTP103, MSTP101, MSTP100, + MSTP030, + MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, +@@ -125,6 +125,7 @@ static struct clk mstp_clks[MSTP_NR] = { + [MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */ + [MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */ + [MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */ ++ [MSTP116] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 16, 0), /* PCIe */ + [MSTP115] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 15, 0), /* SATA */ + [MSTP114] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 14, 0), /* Ether */ + [MSTP103] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 3, 0), /* DU */ +@@ -161,6 +162,7 @@ static struct clk_lookup lookups[] = { + CLKDEV_CON_ID("peripheral_clk", &clkp_clk), + + /* MSTP32 clocks */ ++ CLKDEV_DEV_ID("rcar-pcie", &mstp_clks[MSTP116]), /* PCIe */ + CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */ + CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */ + CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0224-ARM-shmobile-r8a7778-use-fixed-ratio-clock.patch b/patches.renesas/0224-ARM-shmobile-r8a7778-use-fixed-ratio-clock.patch new file mode 100644 index 00000000000..233c9667b94 --- /dev/null +++ b/patches.renesas/0224-ARM-shmobile-r8a7778-use-fixed-ratio-clock.patch @@ -0,0 +1,222 @@ +From fa94cef471c81d347a0ab60f7faac26ad37c99f9 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Fri, 12 Apr 2013 01:13:14 -0700 +Subject: ARM: shmobile: r8a7778: use fixed ratio clock + +R-Car M1 has many clocks, and it is possible to +read/use clock ratio of these clocks from FRQMRx. +But, these ratio are fixed value and +these are decided by MD pin status. + +This patch reads MD pin status, +and used fixed ratio clock for other clocks. +It was tesed on bock-w board. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 08b93ec126ffc0b810ac615729e14c4a3571b9c8) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a7778.c | 149 ++++++++++++++++++++++++++++++--- + 1 file changed, 136 insertions(+), 13 deletions(-) + +diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c +index cd685529..5cc271ec 100644 +--- a/arch/arm/mach-shmobile/clock-r8a7778.c ++++ b/arch/arm/mach-shmobile/clock-r8a7778.c +@@ -23,9 +23,23 @@ + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + ++/* ++ * MD MD MD MD PLLA PLLB EXTAL clki clkz ++ * 19 18 12 11 (HMz) (MHz) (MHz) ++ *---------------------------------------------------------------------------- ++ * 1 0 0 0 x21 x21 38.00 800 800 ++ * 1 0 0 1 x24 x24 33.33 800 800 ++ * 1 0 1 0 x28 x28 28.50 800 800 ++ * 1 0 1 1 x32 x32 25.00 800 800 ++ * 1 1 0 1 x24 x21 33.33 800 700 ++ * 1 1 1 0 x28 x21 28.50 800 600 ++ * 1 1 1 1 x32 x24 25.00 800 600 ++ */ ++ + #include <linux/io.h> + #include <linux/sh_clk.h> + #include <linux/clkdev.h> ++#include <mach/clock.h> + #include <mach/common.h> + + #define MSTPCR0 IOMEM(0xffc80030) +@@ -37,6 +51,9 @@ + #define MSTPCR4 IOMEM(0xffc80050) + #define MSTPCR5 IOMEM(0xffc80054) + #define MSTPCR6 IOMEM(0xffc80058) ++#define MODEMR 0xFFCC0020 ++ ++#define MD(nr) BIT(nr) + + /* ioremap() through clock mapping mandatory to avoid + * collision with ARM coherent DMA virtual memory range. +@@ -47,14 +64,42 @@ static struct clk_mapping cpg_mapping = { + .len = 0x80, + }; + +-static struct clk clkp = { +- .rate = 62500000, /* FIXME: shortcut */ +- .flags = CLK_ENABLE_ON_INIT, ++static struct clk extal_clk = { ++ /* .rate will be updated on r8a7778_clock_init() */ + .mapping = &cpg_mapping, + }; + ++/* ++ * clock ratio of these clock will be updated ++ * on r8a7778_clock_init() ++ */ ++SH_FIXED_RATIO_CLK_SET(plla_clk, extal_clk, 1, 1); ++SH_FIXED_RATIO_CLK_SET(pllb_clk, extal_clk, 1, 1); ++SH_FIXED_RATIO_CLK_SET(i_clk, plla_clk, 1, 1); ++SH_FIXED_RATIO_CLK_SET(s_clk, plla_clk, 1, 1); ++SH_FIXED_RATIO_CLK_SET(s1_clk, plla_clk, 1, 1); ++SH_FIXED_RATIO_CLK_SET(s3_clk, plla_clk, 1, 1); ++SH_FIXED_RATIO_CLK_SET(s4_clk, plla_clk, 1, 1); ++SH_FIXED_RATIO_CLK_SET(b_clk, plla_clk, 1, 1); ++SH_FIXED_RATIO_CLK_SET(out_clk, plla_clk, 1, 1); ++SH_FIXED_RATIO_CLK_SET(p_clk, plla_clk, 1, 1); ++SH_FIXED_RATIO_CLK_SET(g_clk, plla_clk, 1, 1); ++SH_FIXED_RATIO_CLK_SET(z_clk, pllb_clk, 1, 1); ++ + static struct clk *main_clks[] = { +- &clkp, ++ &extal_clk, ++ &plla_clk, ++ &pllb_clk, ++ &i_clk, ++ &s_clk, ++ &s1_clk, ++ &s3_clk, ++ &s4_clk, ++ &b_clk, ++ &out_clk, ++ &p_clk, ++ &g_clk, ++ &z_clk, + }; + + enum { +@@ -64,15 +109,15 @@ enum { + MSTP_NR }; + + static struct clk mstp_clks[MSTP_NR] = { +- [MSTP114] = SH_CLK_MSTP32(&clkp, MSTPCR1, 14, 0), /* Ether */ +- [MSTP026] = SH_CLK_MSTP32(&clkp, MSTPCR0, 26, 0), /* SCIF0 */ +- [MSTP025] = SH_CLK_MSTP32(&clkp, MSTPCR0, 25, 0), /* SCIF1 */ +- [MSTP024] = SH_CLK_MSTP32(&clkp, MSTPCR0, 24, 0), /* SCIF2 */ +- [MSTP023] = SH_CLK_MSTP32(&clkp, MSTPCR0, 23, 0), /* SCIF3 */ +- [MSTP022] = SH_CLK_MSTP32(&clkp, MSTPCR0, 22, 0), /* SCIF4 */ +- [MSTP021] = SH_CLK_MSTP32(&clkp, MSTPCR0, 21, 0), /* SCIF5 */ +- [MSTP016] = SH_CLK_MSTP32(&clkp, MSTPCR0, 16, 0), /* TMU0 */ +- [MSTP015] = SH_CLK_MSTP32(&clkp, MSTPCR0, 15, 0), /* TMU1 */ ++ [MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */ ++ [MSTP026] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 26, 0), /* SCIF0 */ ++ [MSTP025] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 25, 0), /* SCIF1 */ ++ [MSTP024] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 24, 0), /* SCIF2 */ ++ [MSTP023] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 23, 0), /* SCIF3 */ ++ [MSTP022] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 22, 0), /* SCIF4 */ ++ [MSTP021] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 21, 0), /* SCIF5 */ ++ [MSTP016] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 16, 0), /* TMU0 */ ++ [MSTP015] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 15, 0), /* TMU1 */ + }; + + static struct clk_lookup lookups[] = { +@@ -90,8 +135,86 @@ static struct clk_lookup lookups[] = { + + void __init r8a7778_clock_init(void) + { ++ void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE); ++ u32 mode; + int k, ret = 0; + ++ BUG_ON(!modemr); ++ mode = ioread32(modemr); ++ iounmap(modemr); ++ ++ switch (mode & (MD(19) | MD(18) | MD(12) | MD(11))) { ++ case MD(19): ++ extal_clk.rate = 38000000; ++ SH_CLK_SET_RATIO(&plla_clk_ratio, 21, 1); ++ SH_CLK_SET_RATIO(&pllb_clk_ratio, 21, 1); ++ break; ++ case MD(19) | MD(11): ++ extal_clk.rate = 33333333; ++ SH_CLK_SET_RATIO(&plla_clk_ratio, 24, 1); ++ SH_CLK_SET_RATIO(&pllb_clk_ratio, 24, 1); ++ break; ++ case MD(19) | MD(12): ++ extal_clk.rate = 28500000; ++ SH_CLK_SET_RATIO(&plla_clk_ratio, 28, 1); ++ SH_CLK_SET_RATIO(&pllb_clk_ratio, 28, 1); ++ break; ++ case MD(19) | MD(12) | MD(11): ++ extal_clk.rate = 25000000; ++ SH_CLK_SET_RATIO(&plla_clk_ratio, 32, 1); ++ SH_CLK_SET_RATIO(&pllb_clk_ratio, 32, 1); ++ break; ++ case MD(19) | MD(18) | MD(11): ++ extal_clk.rate = 33333333; ++ SH_CLK_SET_RATIO(&plla_clk_ratio, 24, 1); ++ SH_CLK_SET_RATIO(&pllb_clk_ratio, 21, 1); ++ break; ++ case MD(19) | MD(18) | MD(12): ++ extal_clk.rate = 28500000; ++ SH_CLK_SET_RATIO(&plla_clk_ratio, 28, 1); ++ SH_CLK_SET_RATIO(&pllb_clk_ratio, 21, 1); ++ break; ++ case MD(19) | MD(18) | MD(12) | MD(11): ++ extal_clk.rate = 25000000; ++ SH_CLK_SET_RATIO(&plla_clk_ratio, 32, 1); ++ SH_CLK_SET_RATIO(&pllb_clk_ratio, 24, 1); ++ break; ++ default: ++ BUG(); ++ } ++ ++ if (mode & MD(1)) { ++ SH_CLK_SET_RATIO(&i_clk_ratio, 1, 1); ++ SH_CLK_SET_RATIO(&s_clk_ratio, 1, 3); ++ SH_CLK_SET_RATIO(&s1_clk_ratio, 1, 6); ++ SH_CLK_SET_RATIO(&s3_clk_ratio, 1, 4); ++ SH_CLK_SET_RATIO(&s4_clk_ratio, 1, 8); ++ SH_CLK_SET_RATIO(&p_clk_ratio, 1, 12); ++ SH_CLK_SET_RATIO(&g_clk_ratio, 1, 12); ++ if (mode & MD(2)) { ++ SH_CLK_SET_RATIO(&b_clk_ratio, 1, 18); ++ SH_CLK_SET_RATIO(&out_clk_ratio, 1, 18); ++ } else { ++ SH_CLK_SET_RATIO(&b_clk_ratio, 1, 12); ++ SH_CLK_SET_RATIO(&out_clk_ratio, 1, 12); ++ } ++ } else { ++ SH_CLK_SET_RATIO(&i_clk_ratio, 1, 1); ++ SH_CLK_SET_RATIO(&s_clk_ratio, 1, 4); ++ SH_CLK_SET_RATIO(&s1_clk_ratio, 1, 8); ++ SH_CLK_SET_RATIO(&s3_clk_ratio, 1, 4); ++ SH_CLK_SET_RATIO(&s4_clk_ratio, 1, 8); ++ SH_CLK_SET_RATIO(&p_clk_ratio, 1, 16); ++ SH_CLK_SET_RATIO(&g_clk_ratio, 1, 12); ++ if (mode & MD(2)) { ++ SH_CLK_SET_RATIO(&b_clk_ratio, 1, 16); ++ SH_CLK_SET_RATIO(&out_clk_ratio, 1, 16); ++ } else { ++ SH_CLK_SET_RATIO(&b_clk_ratio, 1, 12); ++ SH_CLK_SET_RATIO(&out_clk_ratio, 1, 12); ++ } ++ } ++ + for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) + ret = clk_register(main_clks[k]); + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0225-ARM-shmobile-r8a7778-add-SDHI-clock-support.patch b/patches.renesas/0225-ARM-shmobile-r8a7778-add-SDHI-clock-support.patch new file mode 100644 index 00000000000..7db55d6dbd1 --- /dev/null +++ b/patches.renesas/0225-ARM-shmobile-r8a7778-add-SDHI-clock-support.patch @@ -0,0 +1,47 @@ +From 8b3f6d83c54dcce79b0c27685a36c27c423233a0 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 16 Apr 2013 22:17:04 -0700 +Subject: ARM: shmobile: r8a7778: add SDHI clock support + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 1189b1cb50a0f9e039594ccd504f7de641e30bdf) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a7778.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c +index 5cc271ec..b251e4d0 100644 +--- a/arch/arm/mach-shmobile/clock-r8a7778.c ++++ b/arch/arm/mach-shmobile/clock-r8a7778.c +@@ -103,12 +103,16 @@ static struct clk *main_clks[] = { + }; + + enum { ++ MSTP323, MSTP322, MSTP321, + MSTP114, + MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, + MSTP016, MSTP015, + MSTP_NR }; + + static struct clk mstp_clks[MSTP_NR] = { ++ [MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */ ++ [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */ ++ [MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */ + [MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */ + [MSTP026] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 26, 0), /* SCIF0 */ + [MSTP025] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 25, 0), /* SCIF1 */ +@@ -122,6 +126,9 @@ static struct clk mstp_clks[MSTP_NR] = { + + static struct clk_lookup lookups[] = { + /* MSTP32 clocks */ ++ CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */ ++ CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ ++ CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ + CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */ + CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */ + CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0226-ARM-shmobile-r8a7778-Register-SDHI-device.patch b/patches.renesas/0226-ARM-shmobile-r8a7778-Register-SDHI-device.patch new file mode 100644 index 00000000000..e1f3b4b0706 --- /dev/null +++ b/patches.renesas/0226-ARM-shmobile-r8a7778-Register-SDHI-device.patch @@ -0,0 +1,77 @@ +From b0f9d5f02c39d3c02dab4f01b11ac2f2d770cb96 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 16 Apr 2013 22:17:25 -0700 +Subject: ARM: shmobile: r8a7778: Register SDHI device + +This patch adds SDHI register function which needs id number (= 0/1/2) + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit dab581139c475719caa29356727b930c0245e2af) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + arch/arm/mach-shmobile/include/mach/r8a7778.h + arch/arm/mach-shmobile/setup-r8a7778.c +--- + arch/arm/mach-shmobile/include/mach/r8a7778.h | 2 ++ + arch/arm/mach-shmobile/setup-r8a7778.c | 24 ++++++++++++++++++++++++ + 2 files changed, 26 insertions(+) + +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h +index 68053fc4..ae65b459 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h +@@ -18,6 +18,7 @@ + #ifndef __ASM_R8A7778_H__ + #define __ASM_R8A7778_H__ + ++#include <linux/mmc/sh_mobile_sdhi.h> + #include <linux/sh_eth.h> + + extern void r8a7778_add_standard_devices(void); +@@ -29,5 +30,6 @@ extern void r8a7778_init_irq_dt(void); + extern void r8a7778_clock_init(void); + extern void r8a7778_init_irq_extpin(int irlm); + extern void r8a7778_pinmux_init(void); ++extern void r8a7778_sdhi_init(int id, struct sh_mobile_sdhi_info *info); + + #endif /* __ASM_R8A7778_H__ */ +diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c +index 06ead4a0..1b9b7f2a 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7778.c ++++ b/arch/arm/mach-shmobile/setup-r8a7778.c +@@ -147,6 +147,30 @@ void __init r8a7778_pinmux_init(void) + r8a7778_register_gpio(2); + r8a7778_register_gpio(3); + r8a7778_register_gpio(4); ++}; ++ ++/* SDHI */ ++static struct resource sdhi_resources[] = { ++ /* SDHI0 */ ++ DEFINE_RES_MEM(0xFFE4C000, 0x100), ++ DEFINE_RES_IRQ(gic_iid(0x77)), ++ /* SDHI1 */ ++ DEFINE_RES_MEM(0xFFE4D000, 0x100), ++ DEFINE_RES_IRQ(gic_iid(0x78)), ++ /* SDHI2 */ ++ DEFINE_RES_MEM(0xFFE4F000, 0x100), ++ DEFINE_RES_IRQ(gic_iid(0x76)), ++}; ++ ++void __init r8a7778_sdhi_init(int id, ++ struct sh_mobile_sdhi_info *info) ++{ ++ BUG_ON(id < 0 || id > 2); ++ ++ platform_device_register_resndata( ++ &platform_bus, "sh_mobile_sdhi", id, ++ sdhi_resources + (2 * id), 2, ++ info, sizeof(*info)); + } + + void __init r8a7778_add_standard_devices(void) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0227-ARM-shmobile-r8a7790-add-main-clock.patch b/patches.renesas/0227-ARM-shmobile-r8a7790-add-main-clock.patch new file mode 100644 index 00000000000..335985ff504 --- /dev/null +++ b/patches.renesas/0227-ARM-shmobile-r8a7790-add-main-clock.patch @@ -0,0 +1,231 @@ +From 8ae6b6c0be4268cddc8326ac0e279dab57c1e576 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Fri, 12 Apr 2013 00:42:22 -0700 +Subject: ARM: shmobile: r8a7790: add main clock + +Almost all clock needs main clock which is basis clock on r8a7790. +This patch adds it, and, set its parent/ratio via MD pin. +It is based on v0.05 datasheet + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 8d100c0454a9960c9bf0b67e07225db5d32cca83) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a7790.c | 161 ++++++++++++++++++++++++++++++++- + 1 file changed, 156 insertions(+), 5 deletions(-) + +diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c +index bad9bf2e..850e47f7 100644 +--- a/arch/arm/mach-shmobile/clock-r8a7790.c ++++ b/arch/arm/mach-shmobile/clock-r8a7790.c +@@ -22,32 +22,113 @@ + #include <linux/kernel.h> + #include <linux/sh_clk.h> + #include <linux/clkdev.h> ++#include <mach/clock.h> + #include <mach/common.h> + ++/* ++ * MD EXTAL PLL0 PLL1 PLL3 ++ * 14 13 19 (MHz) *1 *1 ++ *--------------------------------------------------- ++ * 0 0 0 15 x 1 x172/2 x208/2 x106 ++ * 0 0 1 15 x 1 x172/2 x208/2 x88 ++ * 0 1 0 20 x 1 x130/2 x156/2 x80 ++ * 0 1 1 20 x 1 x130/2 x156/2 x66 ++ * 1 0 0 26 / 2 x200/2 x240/2 x122 ++ * 1 0 1 26 / 2 x200/2 x240/2 x102 ++ * 1 1 0 30 / 2 x172/2 x208/2 x106 ++ * 1 1 1 30 / 2 x172/2 x208/2 x88 ++ * ++ * *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2) ++ * see "p1 / 2" on R8A7790_CLOCK_ROOT() below ++ */ ++ ++#define MD(nr) (1 << nr) ++ + #define CPG_BASE 0xe6150000 + #define CPG_LEN 0x1000 + + #define SMSTPCR2 0xe6150138 + #define SMSTPCR7 0xe615014c + ++#define MODEMR 0xE6160060 ++ + static struct clk_mapping cpg_mapping = { + .phys = CPG_BASE, + .len = CPG_LEN, + }; + +-static struct clk p_clk = { +- .rate = 65000000, /* shortcut for now */ ++static struct clk extal_clk = { ++ /* .rate will be updated on r8a7790_clock_init() */ + .mapping = &cpg_mapping, + }; + +-static struct clk mp_clk = { +- .rate = 52000000, /* shortcut for now */ +- .mapping = &cpg_mapping, ++static struct sh_clk_ops followparent_clk_ops = { ++ .recalc = followparent_recalc, + }; + ++static struct clk main_clk = { ++ /* .parent will be set r8a73a4_clock_init */ ++ .ops = &followparent_clk_ops, ++}; ++ ++/* ++ * clock ratio of these clock will be updated ++ * on r8a7790_clock_init() ++ */ ++SH_FIXED_RATIO_CLK_SET(pll1_clk, main_clk, 1, 1); ++SH_FIXED_RATIO_CLK_SET(pll3_clk, main_clk, 1, 1); ++SH_FIXED_RATIO_CLK_SET(lb_clk, pll1_clk, 1, 1); ++SH_FIXED_RATIO_CLK_SET(qspi_clk, pll1_clk, 1, 1); ++ ++/* fixed ratio clock */ ++SH_FIXED_RATIO_CLK_SET(extal_div2_clk, extal_clk, 1, 2); ++SH_FIXED_RATIO_CLK_SET(cp_clk, extal_clk, 1, 2); ++ ++SH_FIXED_RATIO_CLK_SET(pll1_div2_clk, pll1_clk, 1, 2); ++SH_FIXED_RATIO_CLK_SET(zg_clk, pll1_clk, 1, 3); ++SH_FIXED_RATIO_CLK_SET(zx_clk, pll1_clk, 1, 3); ++SH_FIXED_RATIO_CLK_SET(zs_clk, pll1_clk, 1, 6); ++SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12); ++SH_FIXED_RATIO_CLK_SET(i_clk, pll1_clk, 1, 2); ++SH_FIXED_RATIO_CLK_SET(b_clk, pll1_clk, 1, 12); ++SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24); ++SH_FIXED_RATIO_CLK_SET(cl_clk, pll1_clk, 1, 48); ++SH_FIXED_RATIO_CLK_SET(m2_clk, pll1_clk, 1, 8); ++SH_FIXED_RATIO_CLK_SET(imp_clk, pll1_clk, 1, 4); ++SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024)); ++SH_FIXED_RATIO_CLK_SET(oscclk_clk, pll1_clk, 1, (12 * 1024)); ++ ++SH_FIXED_RATIO_CLK_SET(zb3_clk, pll3_clk, 1, 4); ++SH_FIXED_RATIO_CLK_SET(zb3d2_clk, pll3_clk, 1, 8); ++SH_FIXED_RATIO_CLK_SET(ddr_clk, pll3_clk, 1, 8); ++SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15); ++ + static struct clk *main_clks[] = { ++ &extal_clk, ++ &extal_div2_clk, ++ &main_clk, ++ &pll1_clk, ++ &pll1_div2_clk, ++ &pll3_clk, ++ &lb_clk, ++ &qspi_clk, ++ &zg_clk, ++ &zx_clk, ++ &zs_clk, ++ &hp_clk, ++ &i_clk, ++ &b_clk, + &p_clk, ++ &cl_clk, ++ &m2_clk, ++ &imp_clk, ++ &rclk_clk, ++ &oscclk_clk, ++ &zb3_clk, ++ &zb3d2_clk, ++ &ddr_clk, + &mp_clk, ++ &cp_clk, + }; + + enum { MSTP721, MSTP720, +@@ -64,6 +145,35 @@ static struct clk mstp_clks[MSTP_NR] = { + }; + + static struct clk_lookup lookups[] = { ++ ++ /* main clocks */ ++ CLKDEV_CON_ID("extal", &extal_clk), ++ CLKDEV_CON_ID("extal_div2", &extal_div2_clk), ++ CLKDEV_CON_ID("main", &main_clk), ++ CLKDEV_CON_ID("pll1", &pll1_clk), ++ CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk), ++ CLKDEV_CON_ID("pll3", &pll3_clk), ++ CLKDEV_CON_ID("zg", &zg_clk), ++ CLKDEV_CON_ID("zx", &zx_clk), ++ CLKDEV_CON_ID("zs", &zs_clk), ++ CLKDEV_CON_ID("hp", &hp_clk), ++ CLKDEV_CON_ID("i", &i_clk), ++ CLKDEV_CON_ID("b", &b_clk), ++ CLKDEV_CON_ID("lb", &lb_clk), ++ CLKDEV_CON_ID("p", &p_clk), ++ CLKDEV_CON_ID("cl", &cl_clk), ++ CLKDEV_CON_ID("m2", &m2_clk), ++ CLKDEV_CON_ID("imp", &imp_clk), ++ CLKDEV_CON_ID("rclk", &rclk_clk), ++ CLKDEV_CON_ID("oscclk", &oscclk_clk), ++ CLKDEV_CON_ID("zb3", &zb3_clk), ++ CLKDEV_CON_ID("zb3d2", &zb3d2_clk), ++ CLKDEV_CON_ID("ddr", &ddr_clk), ++ CLKDEV_CON_ID("mp", &mp_clk), ++ CLKDEV_CON_ID("qspi", &qspi_clk), ++ CLKDEV_CON_ID("cp", &cp_clk), ++ ++ /* MSTP */ + CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), + CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), + CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), +@@ -74,10 +184,51 @@ static struct clk_lookup lookups[] = { + CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), + }; + ++#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ ++ extal_clk.rate = e * 1000 * 1000; \ ++ main_clk.parent = m; \ ++ SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1); \ ++ if (mode & MD(19)) \ ++ SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1); \ ++ else \ ++ SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1) ++ ++ + void __init r8a7790_clock_init(void) + { ++ void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE); ++ u32 mode; + int k, ret = 0; + ++ BUG_ON(!modemr); ++ mode = ioread32(modemr); ++ iounmap(modemr); ++ ++ switch (mode & (MD(14) | MD(13))) { ++ case 0: ++ R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88); ++ break; ++ case MD(13): ++ R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66); ++ break; ++ case MD(14): ++ R8A7790_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102); ++ break; ++ case MD(13) | MD(14): ++ R8A7790_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88); ++ break; ++ } ++ ++ if (mode & (MD(18))) ++ SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 36); ++ else ++ SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 24); ++ ++ if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2)) ++ SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16); ++ else ++ SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20); ++ + for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) + ret = clk_register(main_clks[k]); + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0228-ARM-shmobile-r8a7790-add-div4-clocks.patch b/patches.renesas/0228-ARM-shmobile-r8a7790-add-div4-clocks.patch new file mode 100644 index 00000000000..b2f9902390b --- /dev/null +++ b/patches.renesas/0228-ARM-shmobile-r8a7790-add-div4-clocks.patch @@ -0,0 +1,82 @@ +From dd1a63fa61c30a9f9d4cd65ed40f0fbee25c1401 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Fri, 12 Apr 2013 00:42:52 -0700 +Subject: ARM: shmobile: r8a7790: add div4 clocks + +DIV4 clocks control SD* core clocks. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 9f13ee6f83c52065112d3e396e42e3780911ef53) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a7790.c | 32 ++++++++++++++++++++++++++++++++ + 1 file changed, 32 insertions(+) + +diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c +index 850e47f7..c85e6432 100644 +--- a/arch/arm/mach-shmobile/clock-r8a7790.c ++++ b/arch/arm/mach-shmobile/clock-r8a7790.c +@@ -51,6 +51,7 @@ + #define SMSTPCR7 0xe615014c + + #define MODEMR 0xE6160060 ++#define SDCKCR 0xE6150074 + + static struct clk_mapping cpg_mapping = { + .phys = CPG_BASE, +@@ -131,6 +132,29 @@ static struct clk *main_clks[] = { + &cp_clk, + }; + ++/* SDHI (DIV4) clock */ ++static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 }; ++ ++static struct clk_div_mult_table div4_div_mult_table = { ++ .divisors = divisors, ++ .nr_divisors = ARRAY_SIZE(divisors), ++}; ++ ++static struct clk_div4_table div4_table = { ++ .div_mult_table = &div4_div_mult_table, ++}; ++ ++enum { ++ DIV4_SDH, DIV4_SD0, DIV4_SD1, DIV4_NR ++}; ++ ++struct clk div4_clks[DIV4_NR] = { ++ [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT), ++ [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT), ++ [DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1de0, CLK_ENABLE_ON_INIT), ++}; ++ ++/* MSTP */ + enum { MSTP721, MSTP720, + MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP_NR }; + static struct clk mstp_clks[MSTP_NR] = { +@@ -173,6 +197,11 @@ static struct clk_lookup lookups[] = { + CLKDEV_CON_ID("qspi", &qspi_clk), + CLKDEV_CON_ID("cp", &cp_clk), + ++ /* DIV4 */ ++ CLKDEV_CON_ID("sdh", &div4_clks[DIV4_SDH]), ++ CLKDEV_CON_ID("sd0", &div4_clks[DIV4_SD0]), ++ CLKDEV_CON_ID("sd1", &div4_clks[DIV4_SD1]), ++ + /* MSTP */ + CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), + CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), +@@ -233,6 +262,9 @@ void __init r8a7790_clock_init(void) + ret = clk_register(main_clks[k]); + + if (!ret) ++ ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); ++ ++ if (!ret) + ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); + + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0229-ARM-shmobile-r8a7790-add-div6-clocks.patch b/patches.renesas/0229-ARM-shmobile-r8a7790-add-div6-clocks.patch new file mode 100644 index 00000000000..c45411af722 --- /dev/null +++ b/patches.renesas/0229-ARM-shmobile-r8a7790-add-div6-clocks.patch @@ -0,0 +1,84 @@ +From bf71445a139ce01a15c453be422489e9e6485b44 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Fri, 12 Apr 2013 00:43:09 -0700 +Subject: ARM: shmobile: r8a7790: add div6 clocks + +DIV6 clocks control SD*/MMC* core clocks. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 46632512c4b6ed9d52abe5ef3ba288d8441af73c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a7790.c | 34 ++++++++++++++++++++++++++++++++++ + 1 file changed, 34 insertions(+) + +diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c +index c85e6432..a4810034 100644 +--- a/arch/arm/mach-shmobile/clock-r8a7790.c ++++ b/arch/arm/mach-shmobile/clock-r8a7790.c +@@ -52,6 +52,12 @@ + + #define MODEMR 0xE6160060 + #define SDCKCR 0xE6150074 ++#define SD2CKCR 0xE6150078 ++#define SD3CKCR 0xE615007C ++#define MMC0CKCR 0xE6150240 ++#define MMC1CKCR 0xE6150244 ++#define SSPCKCR 0xE6150248 ++#define SSPRSCKCR 0xE615024C + + static struct clk_mapping cpg_mapping = { + .phys = CPG_BASE, +@@ -154,6 +160,23 @@ struct clk div4_clks[DIV4_NR] = { + [DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1de0, CLK_ENABLE_ON_INIT), + }; + ++/* DIV6 clocks */ ++enum { ++ DIV6_SD2, DIV6_SD3, ++ DIV6_MMC0, DIV6_MMC1, ++ DIV6_SSP, DIV6_SSPRS, ++ DIV6_NR ++}; ++ ++static struct clk div6_clks[DIV6_NR] = { ++ [DIV6_SD2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0), ++ [DIV6_SD3] = SH_CLK_DIV6(&pll1_div2_clk, SD3CKCR, 0), ++ [DIV6_MMC0] = SH_CLK_DIV6(&pll1_div2_clk, MMC0CKCR, 0), ++ [DIV6_MMC1] = SH_CLK_DIV6(&pll1_div2_clk, MMC1CKCR, 0), ++ [DIV6_SSP] = SH_CLK_DIV6(&pll1_div2_clk, SSPCKCR, 0), ++ [DIV6_SSPRS] = SH_CLK_DIV6(&pll1_div2_clk, SSPRSCKCR, 0), ++}; ++ + /* MSTP */ + enum { MSTP721, MSTP720, + MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP_NR }; +@@ -202,6 +225,14 @@ static struct clk_lookup lookups[] = { + CLKDEV_CON_ID("sd0", &div4_clks[DIV4_SD0]), + CLKDEV_CON_ID("sd1", &div4_clks[DIV4_SD1]), + ++ /* DIV6 */ ++ CLKDEV_CON_ID("sd2", &div6_clks[DIV6_SD2]), ++ CLKDEV_CON_ID("sd3", &div6_clks[DIV6_SD3]), ++ CLKDEV_CON_ID("mmc0", &div6_clks[DIV6_MMC0]), ++ CLKDEV_CON_ID("mmc1", &div6_clks[DIV6_MMC1]), ++ CLKDEV_CON_ID("ssp", &div6_clks[DIV6_SSP]), ++ CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]), ++ + /* MSTP */ + CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), + CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), +@@ -265,6 +296,9 @@ void __init r8a7790_clock_init(void) + ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); + + if (!ret) ++ ret = sh_clk_div6_register(div6_clks, DIV6_NR); ++ ++ if (!ret) + ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); + + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0230-ARM-shmobile-r8a7790-Make-private-clock-arrays-stati.patch b/patches.renesas/0230-ARM-shmobile-r8a7790-Make-private-clock-arrays-stati.patch new file mode 100644 index 00000000000..8926929b0c6 --- /dev/null +++ b/patches.renesas/0230-ARM-shmobile-r8a7790-Make-private-clock-arrays-stati.patch @@ -0,0 +1,33 @@ +From 59e9bea3189d254819f4d4d91df56f202ee5c9a1 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 16 Apr 2013 17:16:20 +0200 +Subject: ARM: shmobile: r8a7790: Make private clock arrays static + +Both clock-r8a7740.c and clock-r8a7790.c define a div4_clks array as +non-static. Compiling support for both SoCs thus result in a symbol +redefinition. Fix it by defining the arrays as static. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 72378a4ab7fc30e1ad6a5266218ccc7933d60370) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a7790.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c +index a4810034..bedd20ca 100644 +--- a/arch/arm/mach-shmobile/clock-r8a7790.c ++++ b/arch/arm/mach-shmobile/clock-r8a7790.c +@@ -154,7 +154,7 @@ enum { + DIV4_SDH, DIV4_SD0, DIV4_SD1, DIV4_NR + }; + +-struct clk div4_clks[DIV4_NR] = { ++static struct clk div4_clks[DIV4_NR] = { + [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT), + [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT), + [DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1de0, CLK_ENABLE_ON_INIT), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0231-ARM-shmobile-r8a7790-add-TPU-PWM-support.patch b/patches.renesas/0231-ARM-shmobile-r8a7790-add-TPU-PWM-support.patch new file mode 100644 index 00000000000..d089e50b016 --- /dev/null +++ b/patches.renesas/0231-ARM-shmobile-r8a7790-add-TPU-PWM-support.patch @@ -0,0 +1,48 @@ +From 99b1297e1b4eb5c54093eb855996af321b18d51d Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Wed, 24 Apr 2013 22:36:01 +0200 +Subject: ARM: shmobile: r8a7790: add TPU PWM support + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit aa9c185bbcd9cffdb0cda1ad24edd801f70178c5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a7790.c | 11 +++++++++-- + 1 file changed, 9 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c +index bedd20ca..b393592e 100644 +--- a/arch/arm/mach-shmobile/clock-r8a7790.c ++++ b/arch/arm/mach-shmobile/clock-r8a7790.c +@@ -48,6 +48,7 @@ + #define CPG_LEN 0x1000 + + #define SMSTPCR2 0xe6150138 ++#define SMSTPCR3 0xe615013c + #define SMSTPCR7 0xe615014c + + #define MODEMR 0xE6160060 +@@ -178,11 +179,17 @@ static struct clk div6_clks[DIV6_NR] = { + }; + + /* MSTP */ +-enum { MSTP721, MSTP720, +- MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP_NR }; ++enum { ++ MSTP721, MSTP720, ++ MSTP304, ++ MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, ++ MSTP_NR ++}; ++ + static struct clk mstp_clks[MSTP_NR] = { + [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ + [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ ++ [MSTP304] = SH_CLK_MSTP32(&cp_clk, SMSTPCR3, 4, 0), /* TPU0 */ + [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ + [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ + [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0232-ARM-shmobile-sh73a0-add-support-for-adjusting-CPU-fr.patch b/patches.renesas/0232-ARM-shmobile-sh73a0-add-support-for-adjusting-CPU-fr.patch new file mode 100644 index 00000000000..a93406faa6d --- /dev/null +++ b/patches.renesas/0232-ARM-shmobile-sh73a0-add-support-for-adjusting-CPU-fr.patch @@ -0,0 +1,162 @@ +From dd9b0fc43de4278f117fc6bc092924a89e8981bb Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Fri, 5 Apr 2013 12:00:36 +0200 +Subject: ARM: shmobile: sh73a0: add support for adjusting CPU frequency + +On SH73A0 the output of PLL0 is supplied to two dividers, feeding clock to +the CPU core and SGX. Lower CPU frequencies allow the use of lower supply +voltages and thus reduce power consumption. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 73107925f4b45b81ea4732475280502fefd35efa) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-sh73a0.c | 95 ++++++++++++++++++++++++++++++++++- + 1 file changed, 93 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c +index 784fbaa4..acb9e097 100644 +--- a/arch/arm/mach-shmobile/clock-sh73a0.c ++++ b/arch/arm/mach-shmobile/clock-sh73a0.c +@@ -228,6 +228,11 @@ enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2, + + static struct clk div4_clks[DIV4_NR] = { + [DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT), ++ /* ++ * ZG clock is dividing PLL0 frequency to supply SGX. Make sure not to ++ * exceed maximum frequencies of 201.5MHz for VDD_DVFS=1.175 and ++ * 239.2MHz for VDD_DVFS=1.315V. ++ */ + [DIV4_ZG] = SH_CLK_DIV4(&pll0_clk, FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT), + [DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT), + [DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT), +@@ -252,6 +257,85 @@ static struct clk twd_clk = { + .ops = &twd_clk_ops, + }; + ++static int (*div4_set_rate)(struct clk *clk, unsigned long rate); ++static unsigned long (*div4_recalc)(struct clk *clk); ++static long (*div4_round_rate)(struct clk *clk, unsigned long rate); ++ ++static int zclk_set_rate(struct clk *clk, unsigned long rate) ++{ ++ int ret; ++ ++ if (!clk->parent || !__clk_get(clk->parent)) ++ return -ENODEV; ++ ++ if (readl(FRQCRB) & (1 << 31)) ++ return -EBUSY; ++ ++ if (rate == clk_get_rate(clk->parent)) { ++ /* 1:1 - switch off divider */ ++ __raw_writel(__raw_readl(FRQCRB) & ~(1 << 28), FRQCRB); ++ /* nullify the divider to prepare for the next time */ ++ ret = div4_set_rate(clk, rate / 2); ++ if (!ret) ++ ret = frqcr_kick(); ++ if (ret > 0) ++ ret = 0; ++ } else { ++ /* Enable the divider */ ++ __raw_writel(__raw_readl(FRQCRB) | (1 << 28), FRQCRB); ++ ++ ret = frqcr_kick(); ++ if (ret >= 0) ++ /* ++ * set the divider - call the DIV4 method, it will kick ++ * FRQCRB too ++ */ ++ ret = div4_set_rate(clk, rate); ++ if (ret < 0) ++ goto esetrate; ++ } ++ ++esetrate: ++ __clk_put(clk->parent); ++ return ret; ++} ++ ++static long zclk_round_rate(struct clk *clk, unsigned long rate) ++{ ++ unsigned long div_freq = div4_round_rate(clk, rate), ++ parent_freq = clk_get_rate(clk->parent); ++ ++ if (rate > div_freq && abs(parent_freq - rate) < rate - div_freq) ++ return parent_freq; ++ ++ return div_freq; ++} ++ ++static unsigned long zclk_recalc(struct clk *clk) ++{ ++ /* ++ * Must recalculate frequencies in case PLL0 has been changed, even if ++ * the divisor is unused ATM! ++ */ ++ unsigned long div_freq = div4_recalc(clk); ++ ++ if (__raw_readl(FRQCRB) & (1 << 28)) ++ return div_freq; ++ ++ return clk_get_rate(clk->parent); ++} ++ ++static void zclk_extend(void) ++{ ++ /* We extend the DIV4 clock with a 1:1 pass-through case */ ++ div4_set_rate = div4_clks[DIV4_Z].ops->set_rate; ++ div4_round_rate = div4_clks[DIV4_Z].ops->round_rate; ++ div4_recalc = div4_clks[DIV4_Z].ops->recalc; ++ div4_clks[DIV4_Z].ops->set_rate = zclk_set_rate; ++ div4_clks[DIV4_Z].ops->round_rate = zclk_round_rate; ++ div4_clks[DIV4_Z].ops->recalc = zclk_recalc; ++} ++ + enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1, + DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2, + DIV6_FSIA, DIV6_FSIB, DIV6_SUB, +@@ -450,7 +534,7 @@ static struct clk *late_main_clks[] = { + }; + + enum { MSTP001, +- MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100, ++ MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP112, MSTP100, + MSTP219, MSTP218, MSTP217, + MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, + MSTP331, MSTP329, MSTP328, MSTP325, MSTP323, MSTP322, +@@ -471,6 +555,7 @@ static struct clk mstp_clks[MSTP_NR] = { + [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */ + [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX0 */ + [MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */ ++ [MSTP112] = MSTP(&div4_clks[DIV4_ZG], SMSTPCR1, 12, 0), /* SGX */ + [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */ + [MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */ + [MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* SY-DMAC */ +@@ -513,6 +598,9 @@ static struct clk_lookup lookups[] = { + CLKDEV_CON_ID("r_clk", &r_clk), + CLKDEV_DEV_ID("smp_twd", &twd_clk), /* smp_twd */ + ++ /* DIV4 clocks */ ++ CLKDEV_DEV_ID("cpufreq-cpu0", &div4_clks[DIV4_Z]), ++ + /* DIV6 clocks */ + CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]), + CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]), +@@ -604,8 +692,11 @@ void __init sh73a0_clock_init(void) + for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) + ret = clk_register(main_clks[k]); + +- if (!ret) ++ if (!ret) { + ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); ++ if (!ret) ++ zclk_extend(); ++ } + + if (!ret) + ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0233-ARM-shmobile-sh73a0-add-CPUFreq-support.patch b/patches.renesas/0233-ARM-shmobile-sh73a0-add-CPUFreq-support.patch new file mode 100644 index 00000000000..37be8d860f9 --- /dev/null +++ b/patches.renesas/0233-ARM-shmobile-sh73a0-add-CPUFreq-support.patch @@ -0,0 +1,59 @@ +From 70692e7ed7edd4cc844340df49509af13be76119 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Fri, 5 Apr 2013 12:00:38 +0200 +Subject: ARM: shmobile: sh73a0: add CPUFreq support + +This patch enables the use of the generic cpufreq-cpu0 driver on sh73a0. +Providing a regulator, a list of OPPs in DT, combined with a virtual +cpufreq-cpu0 platform device and a clock, attached to it is everything, +the cpufreq-cpu0 driver needs. The first sh73a0 platform, implementing +such CPUFreq support is kzm9g-reference. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d23473828c1188805c9e0b2a2e5be158d07ce7de) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/Kconfig | 2 ++ + arch/arm/mach-shmobile/setup-sh73a0.c | 5 +++++ + 2 files changed, 7 insertions(+) + +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index 7a927839..b542d00d 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -184,6 +184,8 @@ config MACH_KZM9D + config MACH_KZM9G + bool "KZM-A9-GT board" + depends on ARCH_SH73A0 ++ select ARCH_HAS_CPUFREQ ++ select ARCH_HAS_OPP + select ARCH_REQUIRE_GPIOLIB + select REGULATOR_FIXED_VOLTAGE if REGULATOR + select SND_SOC_AK4642 if SND_SIMPLE_CARD +diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c +index 35d512a4..127891ab 100644 +--- a/arch/arm/mach-shmobile/setup-sh73a0.c ++++ b/arch/arm/mach-shmobile/setup-sh73a0.c +@@ -963,6 +963,8 @@ static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = { + + void __init sh73a0_add_standard_devices_dt(void) + { ++ struct platform_device_info devinfo = { .name = "cpufreq-cpu0", .id = -1, }; ++ + /* clocks are setup late during boot in the case of DT */ + sh73a0_clock_init(); + +@@ -970,6 +972,9 @@ void __init sh73a0_add_standard_devices_dt(void) + ARRAY_SIZE(sh73a0_devices_dt)); + of_platform_populate(NULL, of_default_bus_match_table, + sh73a0_auxdata_lookup, NULL); ++ ++ /* Instantiate cpufreq-cpu0 */ ++ platform_device_register_full(&devinfo); + } + + static const char *sh73a0_boards_compat_dt[] __initdata = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0234-ARM-shmobile-sh73a0-Always-use-shmobile_setup_delay.patch b/patches.renesas/0234-ARM-shmobile-sh73a0-Always-use-shmobile_setup_delay.patch new file mode 100644 index 00000000000..3ab0adbf23e --- /dev/null +++ b/patches.renesas/0234-ARM-shmobile-sh73a0-Always-use-shmobile_setup_delay.patch @@ -0,0 +1,59 @@ +From 7d0c1866145a9e3aee40297483294b564513f70c Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Wed, 22 May 2013 15:04:14 +0900 +Subject: ARM: shmobile: sh73a0: Always use shmobile_setup_delay() + +Break out the function sh73a0_init_delay() that now +gets called both for the C version of the code and +the DT -reference boards. This way we handle both +cases in the same way. + +Allows us to boot with TWD only in the kernel configuration +for C board code. TWD is not yet enabled in the case of +DT -reference - this due to a dependency on CCF. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 43cb8cb739b9d5f9f723b1953c58b95d3102d821) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-sh73a0.c | 11 ++++++----- + 1 file changed, 6 insertions(+), 5 deletions(-) + +diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c +index 127891ab..96e7ca1e 100644 +--- a/arch/arm/mach-shmobile/setup-sh73a0.c ++++ b/arch/arm/mach-shmobile/setup-sh73a0.c +@@ -929,11 +929,17 @@ void __init sh73a0_add_standard_devices(void) + ARRAY_SIZE(sh73a0_late_devices)); + } + ++void __init sh73a0_init_delay(void) ++{ ++ shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */ ++} ++ + /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ + void __init __weak sh73a0_register_twd(void) { } + + void __init sh73a0_earlytimer_init(void) + { ++ sh73a0_init_delay(); + sh73a0_clock_init(); + shmobile_earlytimer_init(); + sh73a0_register_twd(); +@@ -952,11 +958,6 @@ void __init sh73a0_add_early_devices(void) + + #ifdef CONFIG_USE_OF + +-void __init sh73a0_init_delay(void) +-{ +- shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */ +-} +- + static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = { + {}, + }; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0235-ARM-shmobile-sh73a0-do-not-overwrite-all-div4-clock-.patch b/patches.renesas/0235-ARM-shmobile-sh73a0-do-not-overwrite-all-div4-clock-.patch new file mode 100644 index 00000000000..4a55069fdab --- /dev/null +++ b/patches.renesas/0235-ARM-shmobile-sh73a0-do-not-overwrite-all-div4-clock-.patch @@ -0,0 +1,97 @@ +From 5142f0248dbf960a651236eb5b702eda069d9c51 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Thu, 23 May 2013 00:09:36 +0200 +Subject: ARM: shmobile: sh73a0: do not overwrite all div4 clock operations + +An earlier commit "ARM: shmobile: sh73a0: add support for adjusting CPU +frequency" intended to replace some clock operations only for the Z-clock, +instead it replaced them for all div4 clocks, since all div4 clocks share +the same copy of clock operations. Fix this by using a separate clock +operations structure for Z-clock. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 3b207a45f909a73b6d7fbdcef49e9287ad7385af) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-sh73a0.c | 28 +++++++++++++++------------- + 1 file changed, 15 insertions(+), 13 deletions(-) + +diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c +index acb9e097..d05cf903 100644 +--- a/arch/arm/mach-shmobile/clock-sh73a0.c ++++ b/arch/arm/mach-shmobile/clock-sh73a0.c +@@ -257,9 +257,8 @@ static struct clk twd_clk = { + .ops = &twd_clk_ops, + }; + +-static int (*div4_set_rate)(struct clk *clk, unsigned long rate); +-static unsigned long (*div4_recalc)(struct clk *clk); +-static long (*div4_round_rate)(struct clk *clk, unsigned long rate); ++static struct sh_clk_ops zclk_ops; ++static const struct sh_clk_ops *div4_clk_ops; + + static int zclk_set_rate(struct clk *clk, unsigned long rate) + { +@@ -275,7 +274,7 @@ static int zclk_set_rate(struct clk *clk, unsigned long rate) + /* 1:1 - switch off divider */ + __raw_writel(__raw_readl(FRQCRB) & ~(1 << 28), FRQCRB); + /* nullify the divider to prepare for the next time */ +- ret = div4_set_rate(clk, rate / 2); ++ ret = div4_clk_ops->set_rate(clk, rate / 2); + if (!ret) + ret = frqcr_kick(); + if (ret > 0) +@@ -290,7 +289,7 @@ static int zclk_set_rate(struct clk *clk, unsigned long rate) + * set the divider - call the DIV4 method, it will kick + * FRQCRB too + */ +- ret = div4_set_rate(clk, rate); ++ ret = div4_clk_ops->set_rate(clk, rate); + if (ret < 0) + goto esetrate; + } +@@ -302,7 +301,7 @@ esetrate: + + static long zclk_round_rate(struct clk *clk, unsigned long rate) + { +- unsigned long div_freq = div4_round_rate(clk, rate), ++ unsigned long div_freq = div4_clk_ops->round_rate(clk, rate), + parent_freq = clk_get_rate(clk->parent); + + if (rate > div_freq && abs(parent_freq - rate) < rate - div_freq) +@@ -317,7 +316,7 @@ static unsigned long zclk_recalc(struct clk *clk) + * Must recalculate frequencies in case PLL0 has been changed, even if + * the divisor is unused ATM! + */ +- unsigned long div_freq = div4_recalc(clk); ++ unsigned long div_freq = div4_clk_ops->recalc(clk); + + if (__raw_readl(FRQCRB) & (1 << 28)) + return div_freq; +@@ -327,13 +326,16 @@ static unsigned long zclk_recalc(struct clk *clk) + + static void zclk_extend(void) + { ++ div4_clk_ops = div4_clks[DIV4_Z].ops; ++ + /* We extend the DIV4 clock with a 1:1 pass-through case */ +- div4_set_rate = div4_clks[DIV4_Z].ops->set_rate; +- div4_round_rate = div4_clks[DIV4_Z].ops->round_rate; +- div4_recalc = div4_clks[DIV4_Z].ops->recalc; +- div4_clks[DIV4_Z].ops->set_rate = zclk_set_rate; +- div4_clks[DIV4_Z].ops->round_rate = zclk_round_rate; +- div4_clks[DIV4_Z].ops->recalc = zclk_recalc; ++ zclk_ops = *div4_clk_ops; ++ ++ zclk_ops.set_rate = zclk_set_rate; ++ zclk_ops.round_rate = zclk_round_rate; ++ zclk_ops.recalc = zclk_recalc; ++ ++ div4_clks[DIV4_Z].ops = &zclk_ops; + } + + enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0236-ARM-shmobile-sh73a0-div4-clocks-must-check-the-kick-.patch b/patches.renesas/0236-ARM-shmobile-sh73a0-div4-clocks-must-check-the-kick-.patch new file mode 100644 index 00000000000..cbf999e0bc2 --- /dev/null +++ b/patches.renesas/0236-ARM-shmobile-sh73a0-div4-clocks-must-check-the-kick-.patch @@ -0,0 +1,79 @@ +From dd927617ab0fb585bb466cf7660db0bf3f89c522 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Thu, 23 May 2013 00:10:00 +0200 +Subject: ARM: shmobile: sh73a0: div4 clocks must check the kick bit before + changing rate + +According to the datasheet, it is not allowed to change div4 clock rates +if an earlier rate change operation is still in progress, as indicated by +a set kick bit. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 413bfd0e67894c930242482cd15ac09a800e2ab8) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-sh73a0.c | 24 +++++++++++++++++++----- + 1 file changed, 19 insertions(+), 5 deletions(-) + +diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c +index d05cf903..d9fd0336 100644 +--- a/arch/arm/mach-shmobile/clock-sh73a0.c ++++ b/arch/arm/mach-shmobile/clock-sh73a0.c +@@ -257,7 +257,7 @@ static struct clk twd_clk = { + .ops = &twd_clk_ops, + }; + +-static struct sh_clk_ops zclk_ops; ++static struct sh_clk_ops zclk_ops, kicker_ops; + static const struct sh_clk_ops *div4_clk_ops; + + static int zclk_set_rate(struct clk *clk, unsigned long rate) +@@ -324,18 +324,32 @@ static unsigned long zclk_recalc(struct clk *clk) + return clk_get_rate(clk->parent); + } + +-static void zclk_extend(void) ++static int kicker_set_rate(struct clk *clk, unsigned long rate) + { +- div4_clk_ops = div4_clks[DIV4_Z].ops; ++ if (__raw_readl(FRQCRB) & (1 << 31)) ++ return -EBUSY; ++ ++ return div4_clk_ops->set_rate(clk, rate); ++} ++ ++static void div4_clk_extend(void) ++{ ++ int i; ++ ++ div4_clk_ops = div4_clks[0].ops; + ++ /* Add a kicker-busy check before changing the rate */ ++ kicker_ops = *div4_clk_ops; + /* We extend the DIV4 clock with a 1:1 pass-through case */ + zclk_ops = *div4_clk_ops; + ++ kicker_ops.set_rate = kicker_set_rate; + zclk_ops.set_rate = zclk_set_rate; + zclk_ops.round_rate = zclk_round_rate; + zclk_ops.recalc = zclk_recalc; + +- div4_clks[DIV4_Z].ops = &zclk_ops; ++ for (i = 0; i < DIV4_NR; i++) ++ div4_clks[i].ops = i == DIV4_Z ? &zclk_ops : &kicker_ops; + } + + enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1, +@@ -697,7 +711,7 @@ void __init sh73a0_clock_init(void) + if (!ret) { + ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); + if (!ret) +- zclk_extend(); ++ div4_clk_extend(); + } + + if (!ret) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0237-ARM-shmobile-ape6evm-MP-clock-parent-become-EXTAL2.patch b/patches.renesas/0237-ARM-shmobile-ape6evm-MP-clock-parent-become-EXTAL2.patch new file mode 100644 index 00000000000..cc5a1c6c22d --- /dev/null +++ b/patches.renesas/0237-ARM-shmobile-ape6evm-MP-clock-parent-become-EXTAL2.patch @@ -0,0 +1,56 @@ +From 5993447e837757df142b3efedec71b9d269414fe Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Thu, 4 Apr 2013 21:24:27 -0700 +Subject: ARM: shmobile: ape6evm: MP clock parent become EXTAL2 + +The orignal commit 3263e09d287fbaa8a9424b5e69396599a3bbd518 +(ARM: shmobile: Initial r8a73a4 SoC support V3) +put MP clock parent as EXTAL2, but its code was removed +on DIV6 clock support commit. +This patch makes it consistent. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit b8568a0483a3363eda73d629536c8a019256a0bf) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-ape6evm.c | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c +index 55b8c9fe..5eb0caa6 100644 +--- a/arch/arm/mach-shmobile/board-ape6evm.c ++++ b/arch/arm/mach-shmobile/board-ape6evm.c +@@ -26,6 +26,7 @@ + #include <linux/platform_device.h> + #include <linux/regulator/fixed.h> + #include <linux/regulator/machine.h> ++#include <linux/sh_clk.h> + #include <linux/smsc911x.h> + #include <mach/common.h> + #include <mach/irqs.h> +@@ -65,7 +66,21 @@ static const struct pinctrl_map ape6evm_pinctrl_map[] = { + + static void __init ape6evm_add_standard_devices(void) + { ++ ++ struct clk *parent; ++ struct clk *mp; ++ + r8a73a4_clock_init(); ++ ++ /* MP clock parent = extal2 */ ++ parent = clk_get(NULL, "extal2"); ++ mp = clk_get(NULL, "mp"); ++ BUG_ON(IS_ERR(parent) || IS_ERR(mp)); ++ ++ clk_set_parent(mp, parent); ++ clk_put(parent); ++ clk_put(mp); ++ + pinctrl_register_mappings(ape6evm_pinctrl_map, + ARRAY_SIZE(ape6evm_pinctrl_map)); + r8a73a4_pinmux_init(); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0238-ARM-shmobile-bockw-define-FPGA-address-and-rename-io.patch b/patches.renesas/0238-ARM-shmobile-bockw-define-FPGA-address-and-rename-io.patch new file mode 100644 index 00000000000..59c3dd30311 --- /dev/null +++ b/patches.renesas/0238-ARM-shmobile-bockw-define-FPGA-address-and-rename-io.patch @@ -0,0 +1,61 @@ +From f804c862abb7b1cabc5f930c71dc3ab187732095 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 16 Apr 2013 22:17:42 -0700 +Subject: ARM: shmobile: bockw: define FPGA address and rename iomem variable + +Bock-W board will needs more board specific ioremap() method. +This patch tidyup current FPGA specific settings + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 44bfe6847a088c6207a4a21974e5cfe8517d3e4f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-bockw.c | 13 +++++++------ + 1 file changed, 7 insertions(+), 6 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c +index dac4365c..badde08d 100644 +--- a/arch/arm/mach-shmobile/board-bockw.c ++++ b/arch/arm/mach-shmobile/board-bockw.c +@@ -46,10 +46,11 @@ static const struct pinctrl_map bockw_pinctrl_map[] = { + "scif0_ctrl", "scif0"), + }; + ++#define FPGA 0x18200000 + #define IRQ0MR 0x30 + static void __init bockw_init(void) + { +- void __iomem *fpga; ++ void __iomem *base; + + r8a7778_clock_init(); + r8a7778_init_irq_extpin(1); +@@ -59,8 +60,8 @@ static void __init bockw_init(void) + ARRAY_SIZE(bockw_pinctrl_map)); + r8a7778_pinmux_init(); + +- fpga = ioremap_nocache(0x18200000, SZ_1M); +- if (fpga) { ++ base = ioremap_nocache(FPGA, SZ_1M); ++ if (base) { + /* + * CAUTION + * +@@ -68,10 +69,10 @@ static void __init bockw_init(void) + * it should be cared in the future + * Now, it is assuming IRQ0 was used only from SMSC. + */ +- u16 val = ioread16(fpga + IRQ0MR); ++ u16 val = ioread16(base + IRQ0MR); + val &= ~(1 << 4); /* enable SMSC911x */ +- iowrite16(val, fpga + IRQ0MR); +- iounmap(fpga); ++ iowrite16(val, base + IRQ0MR); ++ iounmap(base); + + platform_device_register_resndata( + &platform_bus, "smsc911x", -1, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0239-ARM-shmobile-kzm9d-resigser-smsc911x-platform-device.patch b/patches.renesas/0239-ARM-shmobile-kzm9d-resigser-smsc911x-platform-device.patch new file mode 100644 index 00000000000..f6a94474d76 --- /dev/null +++ b/patches.renesas/0239-ARM-shmobile-kzm9d-resigser-smsc911x-platform-device.patch @@ -0,0 +1,42 @@ +From fb58eabfada91c94603ce70c12506d9deadcf812 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Thu, 4 Apr 2013 11:20:33 +0900 +Subject: ARM: shmobile: kzm9d: resigser smsc911x platform device with id -1 + +As the kzm9d only has one smsc911x device it +may be registered as a platform device with id -1. + +This allows the kzm9d board to access the smsc911x device +when CONFIG_REGULATOR (and CONFIG_REGULATOR_FIXED_VOLTAGE) +are set. The motivation for which is twofold: using regulators +seems to be generally a good thing; it will move the kzm9d defconfig +one step closer to being able to be consolidated with other +shmobile defconfigs. + +An alternate but so far untested approach would be to +update the definition of dummy_supplies in board-kzm9d.c +to use "smsc911x.0" instead of "smsc911x". + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit df53721a60022263017c5d72e17a7780d0e5dc4c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-kzm9d.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/board-kzm9d.c b/arch/arm/mach-shmobile/board-kzm9d.c +index c016ccd9..4368000e 100644 +--- a/arch/arm/mach-shmobile/board-kzm9d.c ++++ b/arch/arm/mach-shmobile/board-kzm9d.c +@@ -56,7 +56,7 @@ static struct smsc911x_platform_config smsc911x_platdata = { + + static struct platform_device smsc91x_device = { + .name = "smsc911x", +- .id = 0, ++ .id = -1, + .dev = { + .platform_data = &smsc911x_platdata, + }, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0240-ARM-shmobile-kzm9g-add-AS3711-PMIC-platform-data.patch b/patches.renesas/0240-ARM-shmobile-kzm9g-add-AS3711-PMIC-platform-data.patch new file mode 100644 index 00000000000..7c5b3904fd8 --- /dev/null +++ b/patches.renesas/0240-ARM-shmobile-kzm9g-add-AS3711-PMIC-platform-data.patch @@ -0,0 +1,249 @@ +From b32ba99b311f5c07e617bb078238475c7be2077e Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Tue, 12 Feb 2013 17:15:31 +0000 +Subject: ARM: shmobile: kzm9g: add AS3711 PMIC platform data + +KZM9G uses an AS3711 PMIC to supply power to the CPU and the LCD backlight. +The PMIC on the board is pre-programmed to supply correct voltages to the +CPU, power supply to the backlight has to be turned on at run-time. The +latter is currently performed by a hard-coded I2C command sequence in the +board file. This patch removes the backlight hack and instead adds an I2C +device to instantiate the AS3711 MFD driver, which will add a regulator +device to dynamically adjust CPU voltages and a backlight device. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 28307e0a7c3841f2d54876639235c07ebe3d2999) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-kzm9g.c | 193 +++++++++++++++++++++++++---------- + 1 file changed, 140 insertions(+), 53 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c +index 1fdf05cb..165483c9 100644 +--- a/arch/arm/mach-shmobile/board-kzm9g.c ++++ b/arch/arm/mach-shmobile/board-kzm9g.c +@@ -29,6 +29,7 @@ + #include <linux/mmc/host.h> + #include <linux/mmc/sh_mmcif.h> + #include <linux/mmc/sh_mobile_sdhi.h> ++#include <linux/mfd/as3711.h> + #include <linux/mfd/tmio.h> + #include <linux/pinctrl/machine.h> + #include <linux/pinctrl/pinconf-generic.h> +@@ -606,6 +607,140 @@ static struct platform_device fsi_ak4648_device = { + }; + + /* I2C */ ++ ++/* StepDown1 is used to supply 1.315V to the CPU */ ++static struct regulator_init_data as3711_sd1 = { ++ .constraints = { ++ .name = "1.315V CPU", ++ .boot_on = 1, ++ .always_on = 1, ++ .min_uV = 1315000, ++ .max_uV = 1335000, ++ }, ++}; ++ ++/* StepDown2 is used to supply 1.8V to the CPU and to the board */ ++static struct regulator_init_data as3711_sd2 = { ++ .constraints = { ++ .name = "1.8V", ++ .boot_on = 1, ++ .always_on = 1, ++ .min_uV = 1800000, ++ .max_uV = 1800000, ++ }, ++}; ++ ++/* ++ * StepDown3 is switched in parallel with StepDown2, seems to be off, ++ * according to read-back pre-set register values ++ */ ++ ++/* StepDown4 is used to supply 1.215V to the CPU and to the board */ ++static struct regulator_init_data as3711_sd4 = { ++ .constraints = { ++ .name = "1.215V", ++ .boot_on = 1, ++ .always_on = 1, ++ .min_uV = 1215000, ++ .max_uV = 1235000, ++ }, ++}; ++ ++/* LDO1 is unused and unconnected */ ++ ++/* LDO2 is used to supply 2.8V to the CPU */ ++static struct regulator_init_data as3711_ldo2 = { ++ .constraints = { ++ .name = "2.8V CPU", ++ .boot_on = 1, ++ .always_on = 1, ++ .min_uV = 2800000, ++ .max_uV = 2800000, ++ }, ++}; ++ ++/* LDO3 is used to supply 3.0V to the CPU */ ++static struct regulator_init_data as3711_ldo3 = { ++ .constraints = { ++ .name = "3.0V CPU", ++ .boot_on = 1, ++ .always_on = 1, ++ .min_uV = 3000000, ++ .max_uV = 3000000, ++ }, ++}; ++ ++/* LDO4 is used to supply 2.8V to the board */ ++static struct regulator_init_data as3711_ldo4 = { ++ .constraints = { ++ .name = "2.8V", ++ .boot_on = 1, ++ .always_on = 1, ++ .min_uV = 2800000, ++ .max_uV = 2800000, ++ }, ++}; ++ ++/* LDO5 is switched parallel to LDO4, also set to 2.8V */ ++static struct regulator_init_data as3711_ldo5 = { ++ .constraints = { ++ .name = "2.8V #2", ++ .boot_on = 1, ++ .always_on = 1, ++ .min_uV = 2800000, ++ .max_uV = 2800000, ++ }, ++}; ++ ++/* LDO6 is unused and unconnected */ ++ ++/* LDO7 is used to supply 1.15V to the CPU */ ++static struct regulator_init_data as3711_ldo7 = { ++ .constraints = { ++ .name = "1.15V CPU", ++ .boot_on = 1, ++ .always_on = 1, ++ .min_uV = 1150000, ++ .max_uV = 1150000, ++ }, ++}; ++ ++/* LDO8 is switched parallel to LDO7, also set to 1.15V */ ++static struct regulator_init_data as3711_ldo8 = { ++ .constraints = { ++ .name = "1.15V CPU #2", ++ .boot_on = 1, ++ .always_on = 1, ++ .min_uV = 1150000, ++ .max_uV = 1150000, ++ }, ++}; ++ ++static struct as3711_platform_data as3711_pdata = { ++ .regulator = { ++ .init_data = { ++ [AS3711_REGULATOR_SD_1] = &as3711_sd1, ++ [AS3711_REGULATOR_SD_2] = &as3711_sd2, ++ [AS3711_REGULATOR_SD_4] = &as3711_sd4, ++ [AS3711_REGULATOR_LDO_2] = &as3711_ldo2, ++ [AS3711_REGULATOR_LDO_3] = &as3711_ldo3, ++ [AS3711_REGULATOR_LDO_4] = &as3711_ldo4, ++ [AS3711_REGULATOR_LDO_5] = &as3711_ldo5, ++ [AS3711_REGULATOR_LDO_7] = &as3711_ldo7, ++ [AS3711_REGULATOR_LDO_8] = &as3711_ldo8, ++ }, ++ }, ++ .backlight = { ++ .su2_fb = "sh_mobile_lcdc_fb.0", ++ .su2_max_uA = 36000, ++ .su2_feedback = AS3711_SU2_CURR_AUTO, ++ .su2_fbprot = AS3711_SU2_GPIO4, ++ .su2_auto_curr1 = true, ++ .su2_auto_curr2 = true, ++ .su2_auto_curr3 = true, ++ }, ++}; ++ + static struct pcf857x_platform_data pcf8575_pdata = { + .gpio_base = GPIO_PCF8575_BASE, + }; +@@ -625,6 +760,11 @@ static struct i2c_board_info i2c0_devices[] = { + I2C_BOARD_INFO("adxl34x", 0x1d), + .irq = irq_pin(26), /* IRQ26 */ + }, ++ { ++ I2C_BOARD_INFO("as3711", 0x40), ++ .irq = intcs_evt2irq(0x3300), /* IRQ24 */ ++ .platform_data = &as3711_pdata, ++ }, + }; + + static struct i2c_board_info i2c1_devices[] = { +@@ -715,59 +855,6 @@ static const struct pinctrl_map kzm_pinctrl_map[] = { + "usb_vbus", "usb"), + }; + +-/* +- * FIXME +- * +- * This is quick hack for enabling LCDC backlight +- */ +-static int __init as3711_enable_lcdc_backlight(void) +-{ +- struct i2c_adapter *a = i2c_get_adapter(0); +- struct i2c_msg msg; +- int i, ret; +- __u8 magic[] = { +- 0x40, 0x2a, +- 0x43, 0x3c, +- 0x44, 0x3c, +- 0x45, 0x3c, +- 0x54, 0x03, +- 0x51, 0x00, +- 0x51, 0x01, +- 0xff, 0x00, /* wait */ +- 0x43, 0xf0, +- 0x44, 0xf0, +- 0x45, 0xf0, +- }; +- +- if (!of_machine_is_compatible("renesas,kzm9g")) +- return 0; +- +- if (!a) +- return 0; +- +- msg.addr = 0x40; +- msg.len = 2; +- msg.flags = 0; +- +- for (i = 0; i < ARRAY_SIZE(magic); i += 2) { +- msg.buf = magic + i; +- +- if (0xff == msg.buf[0]) { +- udelay(500); +- continue; +- } +- +- ret = i2c_transfer(a, &msg, 1); +- if (ret < 0) { +- pr_err("i2c transfer fail\n"); +- break; +- } +- } +- +- return 0; +-} +-device_initcall(as3711_enable_lcdc_backlight); +- + static void __init kzm_init(void) + { + regulator_register_always_on(2, "fixed-1.8V", fixed1v8_power_consumers, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0241-ARM-shmobile-bockw-add-CN9-SCIF-RCAN-selection-dipsw.patch b/patches.renesas/0241-ARM-shmobile-bockw-add-CN9-SCIF-RCAN-selection-dipsw.patch new file mode 100644 index 00000000000..67aef70fc20 --- /dev/null +++ b/patches.renesas/0241-ARM-shmobile-bockw-add-CN9-SCIF-RCAN-selection-dipsw.patch @@ -0,0 +1,41 @@ +From 46032125af73d1bae36250512b295d38ae6455c8 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Mon, 8 Apr 2013 23:54:16 -0700 +Subject: ARM: shmobile: bockw: add CN9 SCIF/RCAN selection dipswitch + explanation + +Debug serial (= SCIF0) is connected to CN9 upper side, +and it is shared by RCAN. +This patch adds SCIF/RCAN dipswitch explanation on +comment area for developers. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d998cef3fc7ccd52c0ea2c849453dfcde38c8a56) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-bockw.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c +index badde08d..3ce020a7 100644 +--- a/arch/arm/mach-shmobile/board-bockw.c ++++ b/arch/arm/mach-shmobile/board-bockw.c +@@ -26,6 +26,14 @@ + #include <mach/r8a7778.h> + #include <asm/mach/arch.h> + ++/* ++ * CN9(Upper side) SCIF/RCAN selection ++ * ++ * 1,4 3,6 ++ * SW40 SCIF RCAN ++ * SW41 SCIF RCAN ++ */ ++ + static struct smsc911x_platform_config smsc911x_data = { + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0242-ARM-shmobile-bockw-add-dummy-regulators-for-SMSC.patch b/patches.renesas/0242-ARM-shmobile-bockw-add-dummy-regulators-for-SMSC.patch new file mode 100644 index 00000000000..314d9511cfa --- /dev/null +++ b/patches.renesas/0242-ARM-shmobile-bockw-add-dummy-regulators-for-SMSC.patch @@ -0,0 +1,57 @@ +From 09d02bfee3a25baf3130806c88590178c2094eb0 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 9 Apr 2013 02:37:15 -0700 +Subject: ARM: shmobile: bockw: add dummy regulators for SMSC + +SMSC driver will try to get regulator if .config had CONFIG_REGULATOR, +and, shmobile_defconfig has it. +SMSC driver on Bock-W board will be failed if it doens't have +dummy regulator settings. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 741440e868f5f08f747292097620ebad43cc5ef0) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-bockw.c | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c +index 3ce020a7..4d657159 100644 +--- a/arch/arm/mach-shmobile/board-bockw.c ++++ b/arch/arm/mach-shmobile/board-bockw.c +@@ -20,6 +20,8 @@ + + #include <linux/pinctrl/machine.h> + #include <linux/platform_device.h> ++#include <linux/regulator/fixed.h> ++#include <linux/regulator/machine.h> + #include <linux/smsc911x.h> + #include <mach/common.h> + #include <mach/irqs.h> +@@ -34,6 +36,12 @@ + * SW41 SCIF RCAN + */ + ++/* Dummy supplies, where voltage doesn't matter */ ++static struct regulator_consumer_supply dummy_supplies[] = { ++ REGULATOR_SUPPLY("vddvario", "smsc911x"), ++ REGULATOR_SUPPLY("vdd33a", "smsc911x"), ++}; ++ + static struct smsc911x_platform_config smsc911x_data = { + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, +@@ -82,6 +90,9 @@ static void __init bockw_init(void) + iowrite16(val, base + IRQ0MR); + iounmap(base); + ++ regulator_register_fixed(0, dummy_supplies, ++ ARRAY_SIZE(dummy_supplies)); ++ + platform_device_register_resndata( + &platform_bus, "smsc911x", -1, + smsc911x_resources, ARRAY_SIZE(smsc911x_resources), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0243-ARM-shmobile-lager-Add-GPIO-LEDs.patch b/patches.renesas/0243-ARM-shmobile-lager-Add-GPIO-LEDs.patch new file mode 100644 index 00000000000..f156095345b --- /dev/null +++ b/patches.renesas/0243-ARM-shmobile-lager-Add-GPIO-LEDs.patch @@ -0,0 +1,73 @@ +From 23debda80adee932fe08190c8214a49eeebef998 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Tue, 23 Apr 2013 02:37:05 +0000 +Subject: ARM: shmobile: lager: Add GPIO LEDs + +The board has 3 LEDs connected to GPIOs. Add a led-gpio device to +support them. + +Based on "ARM: shmobile: marzen: Add GPIO LEDs" by Laurent Pinchart. + +Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 1034f4ee3f07b7d525c490d702b3dcbee3b56b54) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-lager.c | 27 +++++++++++++++++++++++++++ + 1 file changed, 27 insertions(+) + +diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c +index 6114edd0..6a1ba38f 100644 +--- a/arch/arm/mach-shmobile/board-lager.c ++++ b/arch/arm/mach-shmobile/board-lager.c +@@ -21,13 +21,37 @@ + #include <linux/interrupt.h> + #include <linux/irqchip.h> + #include <linux/kernel.h> ++#include <linux/leds.h> + #include <linux/pinctrl/machine.h> ++#include <linux/platform_data/gpio-rcar.h> + #include <linux/platform_device.h> + #include <mach/common.h> + #include <mach/r8a7790.h> + #include <asm/mach-types.h> + #include <asm/mach/arch.h> + ++/* LEDS */ ++static struct gpio_led lager_leds[] = { ++ { ++ .name = "led8", ++ .gpio = RCAR_GP_PIN(5, 17), ++ .default_state = LEDS_GPIO_DEFSTATE_ON, ++ }, { ++ .name = "led7", ++ .gpio = RCAR_GP_PIN(4, 23), ++ .default_state = LEDS_GPIO_DEFSTATE_ON, ++ }, { ++ .name = "led6", ++ .gpio = RCAR_GP_PIN(4, 22), ++ .default_state = LEDS_GPIO_DEFSTATE_ON, ++ }, ++}; ++ ++static struct gpio_led_platform_data lager_leds_pdata = { ++ .leds = lager_leds, ++ .num_leds = ARRAY_SIZE(lager_leds), ++}; ++ + static const struct pinctrl_map lager_pinctrl_map[] = { + /* SCIF0 (CN19: DEBUG SERIAL0) */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790", +@@ -46,6 +70,9 @@ static void __init lager_add_standard_devices(void) + r8a7790_pinmux_init(); + + r8a7790_add_standard_devices(); ++ platform_device_register_data(&platform_bus, "leds-gpio", -1, ++ &lager_leds_pdata, ++ sizeof(lager_leds_pdata)); + } + + static const char *lager_boards_compat_dt[] __initdata = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0244-ARM-shmobile-lager-support-GPIO-switches.patch b/patches.renesas/0244-ARM-shmobile-lager-support-GPIO-switches.patch new file mode 100644 index 00000000000..bd635ed2007 --- /dev/null +++ b/patches.renesas/0244-ARM-shmobile-lager-support-GPIO-switches.patch @@ -0,0 +1,72 @@ +From e61739925dbbd72ec179d5625eb31da4ac50ee1e Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Mon, 13 May 2013 16:04:31 +0900 +Subject: ARM: shmobile: lager: support GPIO switches + +The lager board has pins 1 - 4 of SW2 wired up to GPIO pins. +This patch allows access to those pins as KEYS 1 - 4 using +gpio-keys. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit c3842e4fcbb7664276443b79187b7808c2e80a35) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-lager.c | 24 +++++++++++++++++++++++- + 1 file changed, 23 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c +index 6a1ba38f..d73e21d3 100644 +--- a/arch/arm/mach-shmobile/board-lager.c ++++ b/arch/arm/mach-shmobile/board-lager.c +@@ -18,6 +18,9 @@ + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + ++#include <linux/gpio.h> ++#include <linux/gpio_keys.h> ++#include <linux/input.h> + #include <linux/interrupt.h> + #include <linux/irqchip.h> + #include <linux/kernel.h> +@@ -47,11 +50,27 @@ static struct gpio_led lager_leds[] = { + }, + }; + +-static struct gpio_led_platform_data lager_leds_pdata = { ++static __initdata struct gpio_led_platform_data lager_leds_pdata = { + .leds = lager_leds, + .num_leds = ARRAY_SIZE(lager_leds), + }; + ++/* GPIO KEY */ ++#define GPIO_KEY(c, g, d, ...) \ ++ { .code = c, .gpio = g, .desc = d, .active_low = 1 } ++ ++static __initdata struct gpio_keys_button gpio_buttons[] = { ++ GPIO_KEY(KEY_4, RCAR_GP_PIN(1, 28), "SW2-pin4"), ++ GPIO_KEY(KEY_3, RCAR_GP_PIN(1, 26), "SW2-pin3"), ++ GPIO_KEY(KEY_2, RCAR_GP_PIN(1, 24), "SW2-pin2"), ++ GPIO_KEY(KEY_1, RCAR_GP_PIN(1, 14), "SW2-pin1"), ++}; ++ ++static __initdata struct gpio_keys_platform_data lager_keys_pdata = { ++ .buttons = gpio_buttons, ++ .nbuttons = ARRAY_SIZE(gpio_buttons), ++}; ++ + static const struct pinctrl_map lager_pinctrl_map[] = { + /* SCIF0 (CN19: DEBUG SERIAL0) */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790", +@@ -73,6 +92,9 @@ static void __init lager_add_standard_devices(void) + platform_device_register_data(&platform_bus, "leds-gpio", -1, + &lager_leds_pdata, + sizeof(lager_leds_pdata)); ++ platform_device_register_data(&platform_bus, "gpio-keys", -1, ++ &lager_keys_pdata, ++ sizeof(lager_keys_pdata)); + } + + static const char *lager_boards_compat_dt[] __initdata = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0245-ARM-shmobile-marzen-Use-INTC-External-IRQ-pin-driver.patch b/patches.renesas/0245-ARM-shmobile-marzen-Use-INTC-External-IRQ-pin-driver.patch new file mode 100644 index 00000000000..defe1da82d5 --- /dev/null +++ b/patches.renesas/0245-ARM-shmobile-marzen-Use-INTC-External-IRQ-pin-driver.patch @@ -0,0 +1,43 @@ +From d7fe4e217997f572fc186aa70a58475f48694efd Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Thu, 18 Apr 2013 21:21:09 +0900 +Subject: ARM: shmobile: marzen: Use INTC External IRQ pin driver for SMSC + +Update the marzen board to use the INTC External IRQ pin driver for SMSC. + +This code was originally posted by Magnus Damm as part of +"ARM: shmobile: INTC External IRQ pin driver on r8a7779" +but somehow omitted when I applied that patch. + +Cc: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 6e267030252ab5309e074c3a19c92ceb7a01fc8b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-marzen.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c +index 9112faef..1e219745 100644 +--- a/arch/arm/mach-shmobile/board-marzen.c ++++ b/arch/arm/mach-shmobile/board-marzen.c +@@ -69,7 +69,7 @@ static struct resource smsc911x_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = gic_iid(0x3c), /* IRQ 1 */ ++ .start = irq_pin(1), /* IRQ 1 */ + .flags = IORESOURCE_IRQ, + }, + }; +@@ -405,6 +405,7 @@ static void __init marzen_init(void) + pinctrl_register_mappings(marzen_pinctrl_map, + ARRAY_SIZE(marzen_pinctrl_map)); + r8a7779_pinmux_init(); ++ r8a7779_init_irq_extpin(1); /* IRQ1 as individual interrupt */ + + r8a7779_add_standard_devices(); + platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices)); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0246-ARM-shmobile-bockw-add-SDHI0-support.patch b/patches.renesas/0246-ARM-shmobile-bockw-add-SDHI0-support.patch new file mode 100644 index 00000000000..90edba87e4a --- /dev/null +++ b/patches.renesas/0246-ARM-shmobile-bockw-add-SDHI0-support.patch @@ -0,0 +1,91 @@ +From c366a4885dfd784d89f01a7cd6d5ad5ba8a133af Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 17 Apr 2013 05:17:56 +0000 +Subject: ARM: shmobile: bockw: add SDHI0 support + +This patch is directly accessing to PUPR4 register which can +control SDHI0 CD/WP pin pull-up setting. +It should be replaced in the future. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit ca7bb309485e4ec89a9addd47beaa1d079841b7d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-bockw.c | 29 +++++++++++++++++++++++++++++ + 1 file changed, 29 insertions(+) + +diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c +index 4d657159..2b6103e5 100644 +--- a/arch/arm/mach-shmobile/board-bockw.c ++++ b/arch/arm/mach-shmobile/board-bockw.c +@@ -18,6 +18,8 @@ + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + ++#include <linux/mfd/tmio.h> ++#include <linux/mmc/host.h> + #include <linux/pinctrl/machine.h> + #include <linux/platform_device.h> + #include <linux/regulator/fixed.h> +@@ -54,16 +56,28 @@ static struct resource smsc911x_resources[] = { + DEFINE_RES_IRQ(irq_pin(0)), /* IRQ 0 */ + }; + ++/* SDHI */ ++static struct sh_mobile_sdhi_info sdhi0_info = { ++ .tmio_caps = MMC_CAP_SD_HIGHSPEED, ++ .tmio_ocr_mask = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, ++ .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT, ++}; ++ + static const struct pinctrl_map bockw_pinctrl_map[] = { + /* SCIF0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778", + "scif0_data_a", "scif0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778", + "scif0_ctrl", "scif0"), ++ /* SDHI0 */ ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778", ++ "sdhi0", "sdhi0"), + }; + + #define FPGA 0x18200000 + #define IRQ0MR 0x30 ++#define PFC 0xfffc0000 ++#define PUPR4 0x110 + static void __init bockw_init(void) + { + void __iomem *base; +@@ -76,6 +90,7 @@ static void __init bockw_init(void) + ARRAY_SIZE(bockw_pinctrl_map)); + r8a7778_pinmux_init(); + ++ /* for SMSC */ + base = ioremap_nocache(FPGA, SZ_1M); + if (base) { + /* +@@ -98,6 +113,20 @@ static void __init bockw_init(void) + smsc911x_resources, ARRAY_SIZE(smsc911x_resources), + &smsc911x_data, sizeof(smsc911x_data)); + } ++ ++ /* for SDHI */ ++ base = ioremap_nocache(PFC, 0x200); ++ if (base) { ++ /* ++ * FIXME ++ * ++ * SDHI CD/WP pin needs pull-up ++ */ ++ iowrite32(ioread32(base + PUPR4) | (3 << 26), base + PUPR4); ++ iounmap(base); ++ ++ r8a7778_sdhi_init(0, &sdhi0_info); ++ } + } + + static const char *bockw_boards_compat_dt[] __initdata = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0247-ARM-shmobile-marzen-keep-local-function-as-static.patch b/patches.renesas/0247-ARM-shmobile-marzen-keep-local-function-as-static.patch new file mode 100644 index 00000000000..687ad2280c0 --- /dev/null +++ b/patches.renesas/0247-ARM-shmobile-marzen-keep-local-function-as-static.patch @@ -0,0 +1,31 @@ +From 8febba8930bcba54b24743ec06bfb152f4a8d0e3 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 17 Apr 2013 23:33:47 -0700 +Subject: ARM: shmobile: marzen: keep local function as static + +marzen_init_late() should be static + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit f3031ff3f2e14f0ced4d45150316df2607b70a27) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-marzen.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c +index 1e219745..a3810b03 100644 +--- a/arch/arm/mach-shmobile/board-marzen.c ++++ b/arch/arm/mach-shmobile/board-marzen.c +@@ -350,7 +350,7 @@ static struct platform_device *marzen_late_devices[] __initdata = { + &ohci1_device, + }; + +-void __init marzen_init_late(void) ++static void __init marzen_init_late(void) + { + /* get usb phy */ + phy = usb_get_phy(USB_PHY_TYPE_USB2); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0248-arm-fix-up-ARM_ARCH_TIMER-selects.patch b/patches.renesas/0248-arm-fix-up-ARM_ARCH_TIMER-selects.patch new file mode 100644 index 00000000000..3478c014f92 --- /dev/null +++ b/patches.renesas/0248-arm-fix-up-ARM_ARCH_TIMER-selects.patch @@ -0,0 +1,94 @@ +From 95304b3055e2281993ec7d917e032942c2f8010c Mon Sep 17 00:00:00 2001 +From: Mark Rutland <mark.rutland@arm.com> +Date: Wed, 20 Mar 2013 13:57:38 +0000 +Subject: arm: fix up ARM_ARCH_TIMER selects + +In 8a4da6e: "arm: arch_timer: move core to drivers/clocksource", the +selection of ARM_ARCH_TIMER was indirected via HAVE_ARM_ARCH_TIMER, +though mach-exynos's selection of ARM_ARCH_TIMER was missed, and since +then mach-shmobile, mach-tegra, and mach-virt have begun selecting +ARM_ARCH_TIMER. This can lead to architected timer support erroneously +appearing to not be selected in menuconfig. + +This patch fixes up the Kconfigs for those platforms to select +HAVE_ARM_ARCH_TIMER. + +Signed-off-by: Mark Rutland <mark.rutland@arm.com> +Acked-by: Stephen Warren <swarren@nvidia.com> +Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> +Acked-by: Simon Horman <horms+renesas@verge.net.au> +Cc: Kukjin Kim <kgene.kim@samsung.com> +Cc: Marc Zyngier <marc.zyngier@arm.com> +(cherry picked from commit fb521a0da1551468a45f2e2a1c1941d0033357ea) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-exynos/Kconfig | 2 +- + arch/arm/mach-shmobile/Kconfig | 4 ++-- + arch/arm/mach-tegra/Kconfig | 2 +- + arch/arm/mach-virt/Kconfig | 2 +- + 4 files changed, 5 insertions(+), 5 deletions(-) + +diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig +index ff18fc2e..756970f6 100644 +--- a/arch/arm/mach-exynos/Kconfig ++++ b/arch/arm/mach-exynos/Kconfig +@@ -76,7 +76,7 @@ config SOC_EXYNOS5440 + default y + depends on ARCH_EXYNOS5 + select ARCH_HAS_OPP +- select ARM_ARCH_TIMER ++ select HAVE_ARM_ARCH_TIMER + select AUTO_ZRELADDR + select PINCTRL + select PINCTRL_EXYNOS5440 +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index b542d00d..bfe972b9 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -23,7 +23,7 @@ config ARCH_R8A73A4 + select ARCH_WANT_OPTIONAL_GPIOLIB + select ARM_GIC + select CPU_V7 +- select ARM_ARCH_TIMER ++ select HAVE_ARM_ARCH_TIMER + select SH_CLK_CPG + select RENESAS_IRQC + +@@ -57,7 +57,7 @@ config ARCH_R8A7790 + select ARCH_WANT_OPTIONAL_GPIOLIB + select ARM_GIC + select CPU_V7 +- select ARM_ARCH_TIMER ++ select HAVE_ARM_ARCH_TIMER + select SH_CLK_CPG + select RENESAS_IRQC + +diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig +index 84d72fc3..65c5ae6f 100644 +--- a/arch/arm/mach-tegra/Kconfig ++++ b/arch/arm/mach-tegra/Kconfig +@@ -60,7 +60,7 @@ config ARCH_TEGRA_3x_SOC + + config ARCH_TEGRA_114_SOC + bool "Enable support for Tegra114 family" +- select ARM_ARCH_TIMER ++ select HAVE_ARM_ARCH_TIMER + select ARM_GIC + select ARM_L1_CACHE_SHIFT_6 + select CPU_FREQ_TABLE if CPU_FREQ +diff --git a/arch/arm/mach-virt/Kconfig b/arch/arm/mach-virt/Kconfig +index 8958f0d8..081d4692 100644 +--- a/arch/arm/mach-virt/Kconfig ++++ b/arch/arm/mach-virt/Kconfig +@@ -2,7 +2,7 @@ config ARCH_VIRT + bool "Dummy Virtual Machine" if ARCH_MULTI_V7 + select ARCH_WANT_OPTIONAL_GPIOLIB + select ARM_GIC +- select ARM_ARCH_TIMER ++ select HAVE_ARM_ARCH_TIMER + select ARM_PSCI + select HAVE_SMP + select CPU_V7 +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0249-ARM-shmobile-r8a7779-fix-Ether-device-name.patch b/patches.renesas/0249-ARM-shmobile-r8a7779-fix-Ether-device-name.patch new file mode 100644 index 00000000000..cab8c3c1e87 --- /dev/null +++ b/patches.renesas/0249-ARM-shmobile-r8a7779-fix-Ether-device-name.patch @@ -0,0 +1,37 @@ +From 13b25c8af8b503aad8d64f7645f9e20f20b236cc Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Sun, 9 Jun 2013 01:24:35 +0400 +Subject: ARM: shmobile: r8a7779: fix Ether device name + +While recasting commit dace48d04dee46a3409d5e13cd98031522e46377 (ARM: shmobile: +R8A7779: add Ether support), I made a typo in the platform device's name: used +underscore instead of hyphen. + +However, there's now patch merged to net-next.git renaming the platform device +from "sh-eth" to "r8a777x-ehter", so it makes the most sense to change the name +straight to that one. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 4c370abbc11311d3753ea9145564ba1997c489fc) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a7779.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c +index dbb13f28..405ad665 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7779.c ++++ b/arch/arm/mach-shmobile/setup-r8a7779.c +@@ -432,7 +432,7 @@ void __init r8a7779_add_standard_devices(void) + + void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata) + { +- platform_device_register_resndata(&platform_bus, "sh_eth", -1, ++ platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1, + ether_resources, + ARRAY_SIZE(ether_resources), + pdata, sizeof(*pdata)); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0250-ARM-shmobile-r8a7778-fix-Ether-device-name.patch b/patches.renesas/0250-ARM-shmobile-r8a7778-fix-Ether-device-name.patch new file mode 100644 index 00000000000..4f3c506ac0a --- /dev/null +++ b/patches.renesas/0250-ARM-shmobile-r8a7778-fix-Ether-device-name.patch @@ -0,0 +1,37 @@ +From 1ca45f84b9a92242e0fb410a6f17d764c068b53f Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Sun, 9 Jun 2013 01:23:24 +0400 +Subject: ARM: shmobile: r8a7778: fix Ether device name + +While recasting commit 524219146a89aee5366326c225ccd71231419d89 (ARM: shmobile: +R8A7778: add Ether support), I made a typo in the platform device's name: used +underscore instead of hyphen. + +However, there's now patch merged to net-next.git renaming the platform device +from "sh-eth" to "r8a777x-ehter", so it makes the most sense to change the name +straight to that one. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit c02f846938fe64800240e97cb113a2bff0149c92) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a7778.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c +index 1b9b7f2a..3004aba2 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7778.c ++++ b/arch/arm/mach-shmobile/setup-r8a7778.c +@@ -97,7 +97,7 @@ static struct resource ether_resources[] = { + + void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata) + { +- platform_device_register_resndata(&platform_bus, "sh_eth", -1, ++ platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1, + ether_resources, + ARRAY_SIZE(ether_resources), + pdata, sizeof(*pdata)); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0251-ARM-shmobile-r8a7790-HSCIF-support.patch b/patches.renesas/0251-ARM-shmobile-r8a7790-HSCIF-support.patch new file mode 100644 index 00000000000..7629e36d6fd --- /dev/null +++ b/patches.renesas/0251-ARM-shmobile-r8a7790-HSCIF-support.patch @@ -0,0 +1,48 @@ +From 7f9f1e5f3e3d96824fb275a0c9314802b2bffa1d Mon Sep 17 00:00:00 2001 +From: Ulrich Hecht <ulrich.hecht@gmail.com> +Date: Fri, 31 May 2013 17:57:02 +0200 +Subject: ARM: shmobile: r8a7790: HSCIF support + +Adds support for HSCIF0 and HSCIF1 on the r8a7790. + +Signed-off-by: Ulrich Hecht <ulrich.hecht@gmail.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 729cb826d45cc2e58bb0256b66f1a8e42173bf54) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a7790.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c +index b393592e..379bce69 100644 +--- a/arch/arm/mach-shmobile/clock-r8a7790.c ++++ b/arch/arm/mach-shmobile/clock-r8a7790.c +@@ -181,6 +181,7 @@ static struct clk div6_clks[DIV6_NR] = { + /* MSTP */ + enum { + MSTP721, MSTP720, ++ MSTP717, MSTP716, + MSTP304, + MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, + MSTP_NR +@@ -196,6 +197,8 @@ static struct clk mstp_clks[MSTP_NR] = { + [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */ + [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */ + [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */ ++ [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */ ++ [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */ + }; + + static struct clk_lookup lookups[] = { +@@ -249,6 +252,8 @@ static struct clk_lookup lookups[] = { + CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]), + CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]), + CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), ++ CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]), ++ CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]), + }; + + #define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0252-ARM-shmobile-Marzen-move-USB-EHCI-OHCI-and-PHY-devic.patch b/patches.renesas/0252-ARM-shmobile-Marzen-move-USB-EHCI-OHCI-and-PHY-devic.patch new file mode 100644 index 00000000000..1cf6d3ad98f --- /dev/null +++ b/patches.renesas/0252-ARM-shmobile-Marzen-move-USB-EHCI-OHCI-and-PHY-devic.patch @@ -0,0 +1,496 @@ +From 5d2ca7b85fadf85bf538099a008babce7d088c15 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Sun, 2 Jun 2013 01:30:15 +0400 +Subject: ARM: shmobile: Marzen: move USB EHCI, OHCI, and PHY devices to + R8A7779 code + +USB EHCI, OHCI, and common PHY are the SoC devices but are wrongly defined and +registered in the Marzen board file. Move the data and code to their proper +place in setup-r8a7779.c; while at it, we have to rename r8a7779_late_devices[] +to r8a7779_standard_devices[] -- this seems legitimate since they are registered +from r8a7779_add_standard_devices() anyway. + +Note that I'm deliberately changing the USB PHY platform device's 'id' field +from (previously just omitted) 0 to -1 as the device is a single of its kind. + +Note also that the board and SoC code have to be in one patch to keep the code +bisectable... + +The patch has been tested on the Marzen board. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +[horms+renesas@verge.net.au: manually applied] +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit 2c8788bfd89bad424d3c288b5a52ce141271b862) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + arch/arm/mach-shmobile/board-marzen.c +--- + arch/arm/mach-shmobile/board-marzen.c | 178 +------------------------ + arch/arm/mach-shmobile/include/mach/r8a7779.h | 1 + + arch/arm/mach-shmobile/setup-r8a7779.c | 185 +++++++++++++++++++++++++- + 3 files changed, 184 insertions(+), 180 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c +index a3810b03..7e04c391 100644 +--- a/arch/arm/mach-shmobile/board-marzen.c ++++ b/arch/arm/mach-shmobile/board-marzen.c +@@ -37,10 +37,6 @@ + #include <linux/mmc/host.h> + #include <linux/mmc/sh_mobile_sdhi.h> + #include <linux/mfd/tmio.h> +-#include <linux/usb/otg.h> +-#include <linux/usb/ehci_pdriver.h> +-#include <linux/usb/ohci_pdriver.h> +-#include <linux/pm_runtime.h> + #include <mach/hardware.h> + #include <mach/r8a7779.h> + #include <mach/common.h> +@@ -150,26 +146,6 @@ static struct platform_device hspi_device = { + .num_resources = ARRAY_SIZE(hspi_resources), + }; + +-/* USB PHY */ +-static struct resource usb_phy_resources[] = { +- [0] = { +- .start = 0xffe70000, +- .end = 0xffe70900 - 1, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = 0xfff70000, +- .end = 0xfff70900 - 1, +- .flags = IORESOURCE_MEM, +- }, +-}; +- +-static struct platform_device usb_phy_device = { +- .name = "rcar_usb_phy", +- .resource = usb_phy_resources, +- .num_resources = ARRAY_SIZE(usb_phy_resources), +-}; +- + /* LEDS */ + static struct gpio_led marzen_leds[] = { + { +@@ -205,161 +181,9 @@ static struct platform_device *marzen_devices[] __initdata = { + &sdhi0_device, + &thermal_device, + &hspi_device, +- &usb_phy_device, + &leds_device, + }; + +-/* USB */ +-static struct usb_phy *phy; +-static int usb_power_on(struct platform_device *pdev) +-{ +- if (IS_ERR(phy)) +- return PTR_ERR(phy); +- +- pm_runtime_enable(&pdev->dev); +- pm_runtime_get_sync(&pdev->dev); +- +- usb_phy_init(phy); +- +- return 0; +-} +- +-static void usb_power_off(struct platform_device *pdev) +-{ +- if (IS_ERR(phy)) +- return; +- +- usb_phy_shutdown(phy); +- +- pm_runtime_put_sync(&pdev->dev); +- pm_runtime_disable(&pdev->dev); +-} +- +-static struct usb_ehci_pdata ehcix_pdata = { +- .power_on = usb_power_on, +- .power_off = usb_power_off, +- .power_suspend = usb_power_off, +-}; +- +-static struct resource ehci0_resources[] = { +- [0] = { +- .start = 0xffe70000, +- .end = 0xffe70400 - 1, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = gic_iid(0x4c), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device ehci0_device = { +- .name = "ehci-platform", +- .id = 0, +- .dev = { +- .dma_mask = &ehci0_device.dev.coherent_dma_mask, +- .coherent_dma_mask = 0xffffffff, +- .platform_data = &ehcix_pdata, +- }, +- .num_resources = ARRAY_SIZE(ehci0_resources), +- .resource = ehci0_resources, +-}; +- +-static struct resource ehci1_resources[] = { +- [0] = { +- .start = 0xfff70000, +- .end = 0xfff70400 - 1, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = gic_iid(0x4d), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device ehci1_device = { +- .name = "ehci-platform", +- .id = 1, +- .dev = { +- .dma_mask = &ehci1_device.dev.coherent_dma_mask, +- .coherent_dma_mask = 0xffffffff, +- .platform_data = &ehcix_pdata, +- }, +- .num_resources = ARRAY_SIZE(ehci1_resources), +- .resource = ehci1_resources, +-}; +- +-static struct usb_ohci_pdata ohcix_pdata = { +- .power_on = usb_power_on, +- .power_off = usb_power_off, +- .power_suspend = usb_power_off, +-}; +- +-static struct resource ohci0_resources[] = { +- [0] = { +- .start = 0xffe70400, +- .end = 0xffe70800 - 1, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = gic_iid(0x4c), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device ohci0_device = { +- .name = "ohci-platform", +- .id = 0, +- .dev = { +- .dma_mask = &ohci0_device.dev.coherent_dma_mask, +- .coherent_dma_mask = 0xffffffff, +- .platform_data = &ohcix_pdata, +- }, +- .num_resources = ARRAY_SIZE(ohci0_resources), +- .resource = ohci0_resources, +-}; +- +-static struct resource ohci1_resources[] = { +- [0] = { +- .start = 0xfff70400, +- .end = 0xfff70800 - 1, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = gic_iid(0x4d), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device ohci1_device = { +- .name = "ohci-platform", +- .id = 1, +- .dev = { +- .dma_mask = &ohci1_device.dev.coherent_dma_mask, +- .coherent_dma_mask = 0xffffffff, +- .platform_data = &ohcix_pdata, +- }, +- .num_resources = ARRAY_SIZE(ohci1_resources), +- .resource = ohci1_resources, +-}; +- +-static struct platform_device *marzen_late_devices[] __initdata = { +- &ehci0_device, +- &ehci1_device, +- &ohci0_device, +- &ohci1_device, +-}; +- +-static void __init marzen_init_late(void) +-{ +- /* get usb phy */ +- phy = usb_get_phy(USB_PHY_TYPE_USB2); +- +- shmobile_init_late(); +- platform_add_devices(marzen_late_devices, +- ARRAY_SIZE(marzen_late_devices)); +-} +- + static const struct pinctrl_map marzen_pinctrl_map[] = { + /* HSPI0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7779", +@@ -418,6 +242,6 @@ MACHINE_START(MARZEN, "marzen") + .nr_irqs = NR_IRQS_LEGACY, + .init_irq = r8a7779_init_irq, + .init_machine = marzen_init, +- .init_late = marzen_init_late, ++ .init_late = r8a7779_init_late, + .init_time = r8a7779_earlytimer_init, + MACHINE_END +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h +index 188b2959..f10727f7 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h +@@ -33,6 +33,7 @@ extern void r8a7779_add_early_devices(void); + extern void r8a7779_add_standard_devices(void); + extern void r8a7779_add_standard_devices_dt(void); + extern void r8a7779_add_ether_device(struct sh_eth_plat_data *pdata); ++extern void r8a7779_init_late(void); + extern void r8a7779_clock_init(void); + extern void r8a7779_pinmux_init(void); + extern void r8a7779_pm_init(void); +diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c +index 405ad665..a57495bd 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7779.c ++++ b/arch/arm/mach-shmobile/setup-r8a7779.c +@@ -32,6 +32,10 @@ + #include <linux/sh_intc.h> + #include <linux/sh_timer.h> + #include <linux/dma-mapping.h> ++#include <linux/usb/otg.h> ++#include <linux/usb/ehci_pdriver.h> ++#include <linux/usb/ohci_pdriver.h> ++#include <linux/pm_runtime.h> + #include <mach/hardware.h> + #include <mach/irqs.h> + #include <mach/r8a7779.h> +@@ -383,6 +387,162 @@ static struct platform_device sata_device = { + }, + }; + ++/* USB PHY */ ++static struct resource usb_phy_resources[] = { ++ [0] = { ++ .start = 0xffe70000, ++ .end = 0xffe70900 - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = 0xfff70000, ++ .end = 0xfff70900 - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++}; ++ ++static struct platform_device usb_phy_device = { ++ .name = "rcar_usb_phy", ++ .id = -1, ++ .resource = usb_phy_resources, ++ .num_resources = ARRAY_SIZE(usb_phy_resources), ++}; ++ ++/* USB */ ++static struct usb_phy *phy; ++ ++static int usb_power_on(struct platform_device *pdev) ++{ ++ if (IS_ERR(phy)) ++ return PTR_ERR(phy); ++ ++ pm_runtime_enable(&pdev->dev); ++ pm_runtime_get_sync(&pdev->dev); ++ ++ usb_phy_init(phy); ++ ++ return 0; ++} ++ ++static void usb_power_off(struct platform_device *pdev) ++{ ++ if (IS_ERR(phy)) ++ return; ++ ++ usb_phy_shutdown(phy); ++ ++ pm_runtime_put_sync(&pdev->dev); ++ pm_runtime_disable(&pdev->dev); ++} ++ ++static struct usb_ehci_pdata ehcix_pdata = { ++ .power_on = usb_power_on, ++ .power_off = usb_power_off, ++ .power_suspend = usb_power_off, ++}; ++ ++static struct resource ehci0_resources[] = { ++ [0] = { ++ .start = 0xffe70000, ++ .end = 0xffe70400 - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = gic_iid(0x4c), ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct platform_device ehci0_device = { ++ .name = "ehci-platform", ++ .id = 0, ++ .dev = { ++ .dma_mask = &ehci0_device.dev.coherent_dma_mask, ++ .coherent_dma_mask = 0xffffffff, ++ .platform_data = &ehcix_pdata, ++ }, ++ .num_resources = ARRAY_SIZE(ehci0_resources), ++ .resource = ehci0_resources, ++}; ++ ++static struct resource ehci1_resources[] = { ++ [0] = { ++ .start = 0xfff70000, ++ .end = 0xfff70400 - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = gic_iid(0x4d), ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct platform_device ehci1_device = { ++ .name = "ehci-platform", ++ .id = 1, ++ .dev = { ++ .dma_mask = &ehci1_device.dev.coherent_dma_mask, ++ .coherent_dma_mask = 0xffffffff, ++ .platform_data = &ehcix_pdata, ++ }, ++ .num_resources = ARRAY_SIZE(ehci1_resources), ++ .resource = ehci1_resources, ++}; ++ ++static struct usb_ohci_pdata ohcix_pdata = { ++ .power_on = usb_power_on, ++ .power_off = usb_power_off, ++ .power_suspend = usb_power_off, ++}; ++ ++static struct resource ohci0_resources[] = { ++ [0] = { ++ .start = 0xffe70400, ++ .end = 0xffe70800 - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = gic_iid(0x4c), ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct platform_device ohci0_device = { ++ .name = "ohci-platform", ++ .id = 0, ++ .dev = { ++ .dma_mask = &ohci0_device.dev.coherent_dma_mask, ++ .coherent_dma_mask = 0xffffffff, ++ .platform_data = &ohcix_pdata, ++ }, ++ .num_resources = ARRAY_SIZE(ohci0_resources), ++ .resource = ohci0_resources, ++}; ++ ++static struct resource ohci1_resources[] = { ++ [0] = { ++ .start = 0xfff70400, ++ .end = 0xfff70800 - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = gic_iid(0x4d), ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct platform_device ohci1_device = { ++ .name = "ohci-platform", ++ .id = 1, ++ .dev = { ++ .dma_mask = &ohci1_device.dev.coherent_dma_mask, ++ .coherent_dma_mask = 0xffffffff, ++ .platform_data = &ohcix_pdata, ++ }, ++ .num_resources = ARRAY_SIZE(ohci1_resources), ++ .resource = ohci1_resources, ++}; ++ + /* Ether */ + static struct resource ether_resources[] = { + { +@@ -404,9 +564,10 @@ static struct platform_device *r8a7779_devices_dt[] __initdata = { + &scif5_device, + &tmu00_device, + &tmu01_device, ++ &usb_phy_device, + }; + +-static struct platform_device *r8a7779_late_devices[] __initdata = { ++static struct platform_device *r8a7779_standard_devices[] __initdata = { + &i2c0_device, + &i2c1_device, + &i2c2_device, +@@ -426,8 +587,8 @@ void __init r8a7779_add_standard_devices(void) + + platform_add_devices(r8a7779_devices_dt, + ARRAY_SIZE(r8a7779_devices_dt)); +- platform_add_devices(r8a7779_late_devices, +- ARRAY_SIZE(r8a7779_late_devices)); ++ platform_add_devices(r8a7779_standard_devices, ++ ARRAY_SIZE(r8a7779_standard_devices)); + } + + void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata) +@@ -470,6 +631,23 @@ void __init r8a7779_add_early_devices(void) + */ + } + ++static struct platform_device *r8a7779_late_devices[] __initdata = { ++ &ehci0_device, ++ &ehci1_device, ++ &ohci0_device, ++ &ohci1_device, ++}; ++ ++void __init r8a7779_init_late(void) ++{ ++ /* get USB PHY */ ++ phy = usb_get_phy(USB_PHY_TYPE_USB2); ++ ++ shmobile_init_late(); ++ platform_add_devices(r8a7779_late_devices, ++ ARRAY_SIZE(r8a7779_late_devices)); ++} ++ + #ifdef CONFIG_USE_OF + void __init r8a7779_init_delay(void) + { +@@ -503,6 +681,7 @@ DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)") + .init_irq = r8a7779_init_irq_dt, + .init_machine = r8a7779_add_standard_devices_dt, + .init_time = shmobile_timer_init, ++ .init_late = r8a7779_init_late, + .dt_compat = r8a7779_compat_dt, + MACHINE_END + #endif /* CONFIG_USE_OF */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0253-ehci-platform-add-pre_setup-method-to-platform-data.patch b/patches.renesas/0253-ehci-platform-add-pre_setup-method-to-platform-data.patch new file mode 100644 index 00000000000..4bb416af494 --- /dev/null +++ b/patches.renesas/0253-ehci-platform-add-pre_setup-method-to-platform-data.patch @@ -0,0 +1,69 @@ +From c78947c1adb99d1287bb005b121c298d1299be1e Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Sun, 2 Jun 2013 01:33:56 +0400 +Subject: ehci-platform: add pre_setup() method to platform data + +Sometimes there is a need to initialize some non-standard registers mapped to +the EHCI region before accessing the standard EHCI registers. Add pre_setup() +method with 'struct usb_hcd *' parameter to be called just before ehci_setup() +to the 'ehci-platform' driver's platform data for this purpose... + +While at it, add the missing incomplete declaration of 'struct platform_device' +to <linux/usb/ehci_pdriver.h>... + +The patch has been tested on the Marzen and BOCK-W boards. + +Suggested-by: Alan Stern <stern@rowland.harvard.edu> +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Acked-by: Alan Stern <stern@rowland.harvard.edu> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 743fcce0a89e04dc511b4ea40eba8e3f7cec92d4) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/ehci-platform.c | 6 ++++++ + include/linux/usb/ehci_pdriver.h | 4 ++++ + 2 files changed, 10 insertions(+) + +diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c +index f47f2594..d1f5cea4 100644 +--- a/drivers/usb/host/ehci-platform.c ++++ b/drivers/usb/host/ehci-platform.c +@@ -48,6 +48,12 @@ static int ehci_platform_reset(struct usb_hcd *hcd) + ehci->big_endian_desc = pdata->big_endian_desc; + ehci->big_endian_mmio = pdata->big_endian_mmio; + ++ if (pdata->pre_setup) { ++ retval = pdata->pre_setup(hcd); ++ if (retval < 0) ++ return retval; ++ } ++ + ehci->caps = hcd->regs + pdata->caps_offset; + retval = ehci_setup(hcd); + if (retval) +diff --git a/include/linux/usb/ehci_pdriver.h b/include/linux/usb/ehci_pdriver.h +index 99238b09..7eb4dcd0 100644 +--- a/include/linux/usb/ehci_pdriver.h ++++ b/include/linux/usb/ehci_pdriver.h +@@ -19,6 +19,9 @@ + #ifndef __USB_CORE_EHCI_PDRIVER_H + #define __USB_CORE_EHCI_PDRIVER_H + ++struct platform_device; ++struct usb_hcd; ++ + /** + * struct usb_ehci_pdata - platform_data for generic ehci driver + * +@@ -50,6 +53,7 @@ struct usb_ehci_pdata { + /* Turn on only VBUS suspend power and hotplug detection, + * turn off everything else */ + void (*power_suspend)(struct platform_device *pdev); ++ int (*pre_setup)(struct usb_hcd *hcd); + }; + + #endif /* __USB_CORE_EHCI_PDRIVER_H */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0254-ARM-shmobile-r8a7779-setup-EHCI-internal-buffer.patch b/patches.renesas/0254-ARM-shmobile-r8a7779-setup-EHCI-internal-buffer.patch new file mode 100644 index 00000000000..1a1adb6be84 --- /dev/null +++ b/patches.renesas/0254-ARM-shmobile-r8a7779-setup-EHCI-internal-buffer.patch @@ -0,0 +1,60 @@ +From 506b69e1654ef414cbe6b6cc77a0b1b4bde48b27 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Sun, 2 Jun 2013 01:37:01 +0400 +Subject: ARM: shmobile: r8a7779: setup EHCI internal buffer + +Setup the EHCI internal buffer (before EHCI driver has a chance to touch the +registers) using the pre_setup() method in 'struct usb_ehci_pdata'. + +The patch has been tested on the Marzen board. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 84a812da09887a473f596a107096e8e1671505c9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a7779.c | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c +index a57495bd..09876545 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7779.c ++++ b/arch/arm/mach-shmobile/setup-r8a7779.c +@@ -33,6 +33,7 @@ + #include <linux/sh_timer.h> + #include <linux/dma-mapping.h> + #include <linux/usb/otg.h> ++#include <linux/usb/hcd.h> + #include <linux/usb/ehci_pdriver.h> + #include <linux/usb/ohci_pdriver.h> + #include <linux/pm_runtime.h> +@@ -435,10 +436,25 @@ static void usb_power_off(struct platform_device *pdev) + pm_runtime_disable(&pdev->dev); + } + ++static int ehci_init_internal_buffer(struct usb_hcd *hcd) ++{ ++ /* ++ * Below are recommended values from the datasheet; ++ * see [USB :: Setting of EHCI Internal Buffer]. ++ */ ++ /* EHCI IP internal buffer setting */ ++ iowrite32(0x00ff0040, hcd->regs + 0x0094); ++ /* EHCI IP internal buffer enable */ ++ iowrite32(0x00000001, hcd->regs + 0x009C); ++ ++ return 0; ++} ++ + static struct usb_ehci_pdata ehcix_pdata = { + .power_on = usb_power_on, + .power_off = usb_power_off, + .power_suspend = usb_power_off, ++ .pre_setup = ehci_init_internal_buffer, + }; + + static struct resource ehci0_resources[] = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0255-ARM-shmobile-r8a7779-remove-USB-PHY-2nd-memory-resou.patch b/patches.renesas/0255-ARM-shmobile-r8a7779-remove-USB-PHY-2nd-memory-resou.patch new file mode 100644 index 00000000000..49a1290f9b4 --- /dev/null +++ b/patches.renesas/0255-ARM-shmobile-r8a7779-remove-USB-PHY-2nd-memory-resou.patch @@ -0,0 +1,36 @@ +From e5a7345a9774019f7353d509717eea5156d88a2d Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Sun, 2 Jun 2013 01:48:42 +0400 +Subject: ARM: shmobile: r8a7779: remove USB PHY 2nd memory resource + +Now that 'drivers/usb/phy/phy-rcar-usb.c' doesn't require the second memory +resource anymore, we can remove it from the R8A7779's USB PHY platform device. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit bb6e7d61dd95153c8c5d0ee52f303e0f475b736e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a7779.c | 5 ----- + 1 file changed, 5 deletions(-) + +diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c +index 09876545..ef40d326 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7779.c ++++ b/arch/arm/mach-shmobile/setup-r8a7779.c +@@ -395,11 +395,6 @@ static struct resource usb_phy_resources[] = { + .end = 0xffe70900 - 1, + .flags = IORESOURCE_MEM, + }, +- [1] = { +- .start = 0xfff70000, +- .end = 0xfff70900 - 1, +- .flags = IORESOURCE_MEM, +- }, + }; + + static struct platform_device usb_phy_device = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0256-phy-rcar-usb-correct-base-address.patch b/patches.renesas/0256-phy-rcar-usb-correct-base-address.patch new file mode 100644 index 00000000000..d0feff1250b --- /dev/null +++ b/patches.renesas/0256-phy-rcar-usb-correct-base-address.patch @@ -0,0 +1,44 @@ +From 235de170447eb60b37d382d9ac5166df505bc41c Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Sun, 2 Jun 2013 01:50:25 +0400 +Subject: phy-rcar-usb: correct base address + +The memory region that is used by the driver overlaps EHCI and OHCI register +regions for absolutely no reason now -- fix it by adding offset of 0x800 to +the base address, changing the register #define's accordingly. This has extra +positive effect that we now can use devm_ioremap_resource()... + +Note that the driver and the SoC code have to be in one patch to keep the code +bisectable... + +The patch has been tested on the Marzen board. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Acked-by: Felipe Balbi <balbi@ti.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 725bf9dcafe16aa69c8ab34c63ba36c6eb4492f2) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + drivers/usb/phy/phy-rcar-usb.c +--- + arch/arm/mach-shmobile/setup-r8a7779.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c +index ef40d326..64ff4dc4 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7779.c ++++ b/arch/arm/mach-shmobile/setup-r8a7779.c +@@ -391,7 +391,7 @@ static struct platform_device sata_device = { + /* USB PHY */ + static struct resource usb_phy_resources[] = { + [0] = { +- .start = 0xffe70000, ++ .start = 0xffe70800, + .end = 0xffe70900 - 1, + .flags = IORESOURCE_MEM, + }, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0257-ARM-shmobile-Marzen-pass-platform-data-to-USB-PHY-de.patch b/patches.renesas/0257-ARM-shmobile-Marzen-pass-platform-data-to-USB-PHY-de.patch new file mode 100644 index 00000000000..0449765cfa3 --- /dev/null +++ b/patches.renesas/0257-ARM-shmobile-Marzen-pass-platform-data-to-USB-PHY-de.patch @@ -0,0 +1,130 @@ +From 2a715b448a5bdd7d887905c68c6df8c51602afd3 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Sun, 2 Jun 2013 01:55:04 +0400 +Subject: ARM: shmobile: Marzen: pass platform data to USB PHY device + +Since we're now going to setup the USBPCTRL0 register using the USB PHY device's +platform data, we now need a way to pass those platform data from the board file +to the device which is situated in setup-r8a7779.c -- and what I'm suggesting is +r8a7779_add_usb_phy_device() that will register USB PHY platform device with the +passed platform data using platform_device_register_resndata() call; creating +this function involves deletion of 'usb_phy_device' from r8a7779_devices_dt[], +so that it will no longer be registered for the generic R8A7779 machine (where +we can't provide the platform data anyway), hence EHCI/OHCI drivers will fail +to load as well. + +For the Marzen board, this new function will be called from marzen_init() to +register the USB PHY device early enough. + +Note that the board and the SoC code have to be in one patch to keep the code +bisectable... + +The patch has been tested on the Marzen board. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +[horms+renesas@verge.net.au: manually applied] +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit 2437b27c3a016b15183a720c06b23de2bf3f6a10) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-marzen.c | 3 +++ + arch/arm/mach-shmobile/include/mach/r8a7779.h | 2 ++ + arch/arm/mach-shmobile/setup-r8a7779.c | 18 +++++++++--------- + 3 files changed, 14 insertions(+), 9 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c +index 7e04c391..a7d10105 100644 +--- a/arch/arm/mach-shmobile/board-marzen.c ++++ b/arch/arm/mach-shmobile/board-marzen.c +@@ -57,6 +57,8 @@ static struct regulator_consumer_supply dummy_supplies[] = { + REGULATOR_SUPPLY("vdd33a", "smsc911x"), + }; + ++static struct rcar_phy_platform_data usb_phy_platform_data __initdata; ++ + /* SMSC LAN89218 */ + static struct resource smsc911x_resources[] = { + [0] = { +@@ -232,6 +234,7 @@ static void __init marzen_init(void) + r8a7779_init_irq_extpin(1); /* IRQ1 as individual interrupt */ + + r8a7779_add_standard_devices(); ++ r8a7779_add_usb_phy_device(&usb_phy_platform_data); + platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices)); + } + +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h +index f10727f7..fc47073c 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h +@@ -4,6 +4,7 @@ + #include <linux/sh_clk.h> + #include <linux/pm_domain.h> + #include <linux/sh_eth.h> ++#include <linux/platform_data/usb-rcar-phy.h> + + struct platform_device; + +@@ -33,6 +34,7 @@ extern void r8a7779_add_early_devices(void); + extern void r8a7779_add_standard_devices(void); + extern void r8a7779_add_standard_devices_dt(void); + extern void r8a7779_add_ether_device(struct sh_eth_plat_data *pdata); ++extern void r8a7779_add_usb_phy_device(struct rcar_phy_platform_data *pdata); + extern void r8a7779_init_late(void); + extern void r8a7779_clock_init(void); + extern void r8a7779_pinmux_init(void); +diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c +index 64ff4dc4..39868776 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7779.c ++++ b/arch/arm/mach-shmobile/setup-r8a7779.c +@@ -389,7 +389,7 @@ static struct platform_device sata_device = { + }; + + /* USB PHY */ +-static struct resource usb_phy_resources[] = { ++static struct resource usb_phy_resources[] __initdata = { + [0] = { + .start = 0xffe70800, + .end = 0xffe70900 - 1, +@@ -397,13 +397,6 @@ static struct resource usb_phy_resources[] = { + }, + }; + +-static struct platform_device usb_phy_device = { +- .name = "rcar_usb_phy", +- .id = -1, +- .resource = usb_phy_resources, +- .num_resources = ARRAY_SIZE(usb_phy_resources), +-}; +- + /* USB */ + static struct usb_phy *phy; + +@@ -575,7 +568,6 @@ static struct platform_device *r8a7779_devices_dt[] __initdata = { + &scif5_device, + &tmu00_device, + &tmu01_device, +- &usb_phy_device, + }; + + static struct platform_device *r8a7779_standard_devices[] __initdata = { +@@ -610,6 +602,14 @@ void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata) + pdata, sizeof(*pdata)); + } + ++void __init r8a7779_add_usb_phy_device(struct rcar_phy_platform_data *pdata) ++{ ++ platform_device_register_resndata(&platform_bus, "rcar_usb_phy", -1, ++ usb_phy_resources, ++ ARRAY_SIZE(usb_phy_resources), ++ pdata, sizeof(*pdata)); ++} ++ + /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ + void __init __weak r8a7779_register_twd(void) { } + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0258-ARM-shmobile-r8a7778-add-USB-support.patch b/patches.renesas/0258-ARM-shmobile-r8a7778-add-USB-support.patch new file mode 100644 index 00000000000..e0e26c57e06 --- /dev/null +++ b/patches.renesas/0258-ARM-shmobile-r8a7778-add-USB-support.patch @@ -0,0 +1,228 @@ +From 8871a3895167224404be96762ad996f3ff5d6fc5 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Sun, 9 Jun 2013 00:36:05 +0400 +Subject: ARM: shmobile: r8a7778: add USB support + +Add USB clock and EHCI, OHCI, and USB PHY platform devices for R8A7778 SoC; add +a function to register PHY device with board-specific platform data and register +EHCI and OHCI platfrom devices from the init_late() board method. + +Also, don't forget to enable CONFIG_ARCH_HAS_[EO]HCI options for R8A7778 SoC in +Kconfig... + +The patch has been tested on the BOCK-W board. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 02474a41e6180521a2b9b30b84888670e290dba0) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/Kconfig | 2 + + arch/arm/mach-shmobile/clock-r8a7778.c | 4 + + arch/arm/mach-shmobile/include/mach/r8a7778.h | 3 + + arch/arm/mach-shmobile/setup-r8a7778.c | 108 ++++++++++++++++++++++++++ + 4 files changed, 117 insertions(+) + +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index bfe972b9..70df9490 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -41,6 +41,8 @@ config ARCH_R8A7778 + select CPU_V7 + select SH_CLK_CPG + select ARM_GIC ++ select USB_ARCH_HAS_EHCI ++ select USB_ARCH_HAS_OHCI + + config ARCH_R8A7779 + bool "R-Car H1 (R8A77790)" +diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c +index b251e4d0..696d206a 100644 +--- a/arch/arm/mach-shmobile/clock-r8a7778.c ++++ b/arch/arm/mach-shmobile/clock-r8a7778.c +@@ -105,6 +105,7 @@ static struct clk *main_clks[] = { + enum { + MSTP323, MSTP322, MSTP321, + MSTP114, ++ MSTP100, + MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, + MSTP016, MSTP015, + MSTP_NR }; +@@ -114,6 +115,7 @@ static struct clk mstp_clks[MSTP_NR] = { + [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */ + [MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */ + [MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */ ++ [MSTP100] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 0, 0), /* USB0/1 */ + [MSTP026] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 26, 0), /* SCIF0 */ + [MSTP025] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 25, 0), /* SCIF1 */ + [MSTP024] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 24, 0), /* SCIF2 */ +@@ -130,6 +132,8 @@ static struct clk_lookup lookups[] = { + CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ + CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ + CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */ ++ CLKDEV_DEV_ID("ehci-platform", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */ ++ CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */ + CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */ + CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */ + CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */ +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h +index ae65b459..1d4207cc 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h +@@ -20,10 +20,13 @@ + + #include <linux/mmc/sh_mobile_sdhi.h> + #include <linux/sh_eth.h> ++#include <linux/platform_data/usb-rcar-phy.h> + + extern void r8a7778_add_standard_devices(void); + extern void r8a7778_add_standard_devices_dt(void); + extern void r8a7778_add_ether_device(struct sh_eth_plat_data *pdata); ++extern void r8a7778_add_usb_phy_device(struct rcar_phy_platform_data *pdata); ++extern void r8a7778_init_late(void); + extern void r8a7778_init_delay(void); + extern void r8a7778_init_irq(void); + extern void r8a7778_init_irq_dt(void); +diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c +index 3004aba2..94211335 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7778.c ++++ b/arch/arm/mach-shmobile/setup-r8a7778.c +@@ -30,6 +30,12 @@ + #include <linux/irqchip.h> + #include <linux/serial_sci.h> + #include <linux/sh_timer.h> ++#include <linux/pm_runtime.h> ++#include <linux/usb/phy.h> ++#include <linux/usb/hcd.h> ++#include <linux/usb/ehci_pdriver.h> ++#include <linux/usb/ohci_pdriver.h> ++#include <linux/dma-mapping.h> + #include <mach/irqs.h> + #include <mach/r8a7778.h> + #include <mach/common.h> +@@ -89,6 +95,99 @@ static struct sh_timer_config sh_tmu1_platform_data = { + &sh_tmu##idx##_platform_data, \ + sizeof(sh_tmu##idx##_platform_data)) + ++/* USB PHY */ ++static struct resource usb_phy_resources[] __initdata = { ++ DEFINE_RES_MEM(0xffe70800, 0x100), ++ DEFINE_RES_MEM(0xffe76000, 0x100), ++}; ++ ++void __init r8a7778_add_usb_phy_device(struct rcar_phy_platform_data *pdata) ++{ ++ platform_device_register_resndata(&platform_bus, "rcar_usb_phy", -1, ++ usb_phy_resources, ++ ARRAY_SIZE(usb_phy_resources), ++ pdata, sizeof(*pdata)); ++} ++ ++/* USB */ ++static struct usb_phy *phy; ++ ++static int usb_power_on(struct platform_device *pdev) ++{ ++ if (IS_ERR(phy)) ++ return PTR_ERR(phy); ++ ++ pm_runtime_enable(&pdev->dev); ++ pm_runtime_get_sync(&pdev->dev); ++ ++ usb_phy_init(phy); ++ ++ return 0; ++} ++ ++static void usb_power_off(struct platform_device *pdev) ++{ ++ if (IS_ERR(phy)) ++ return; ++ ++ usb_phy_shutdown(phy); ++ ++ pm_runtime_put_sync(&pdev->dev); ++ pm_runtime_disable(&pdev->dev); ++} ++ ++static int ehci_init_internal_buffer(struct usb_hcd *hcd) ++{ ++ /* ++ * Below are recommended values from the datasheet; ++ * see [USB :: Setting of EHCI Internal Buffer]. ++ */ ++ /* EHCI IP internal buffer setting */ ++ iowrite32(0x00ff0040, hcd->regs + 0x0094); ++ /* EHCI IP internal buffer enable */ ++ iowrite32(0x00000001, hcd->regs + 0x009C); ++ ++ return 0; ++} ++ ++static struct usb_ehci_pdata ehci_pdata __initdata = { ++ .power_on = usb_power_on, ++ .power_off = usb_power_off, ++ .power_suspend = usb_power_off, ++ .pre_setup = ehci_init_internal_buffer, ++}; ++ ++static struct resource ehci_resources[] __initdata = { ++ DEFINE_RES_MEM(0xffe70000, 0x400), ++ DEFINE_RES_IRQ(gic_iid(0x4c)), ++}; ++ ++static struct usb_ohci_pdata ohci_pdata __initdata = { ++ .power_on = usb_power_on, ++ .power_off = usb_power_off, ++ .power_suspend = usb_power_off, ++}; ++ ++static struct resource ohci_resources[] __initdata = { ++ DEFINE_RES_MEM(0xffe70400, 0x400), ++ DEFINE_RES_IRQ(gic_iid(0x4c)), ++}; ++ ++#define USB_PLATFORM_INFO(hci) \ ++static struct platform_device_info hci##_info __initdata = { \ ++ .parent = &platform_bus, \ ++ .name = #hci "-platform", \ ++ .id = -1, \ ++ .res = hci##_resources, \ ++ .num_res = ARRAY_SIZE(hci##_resources), \ ++ .data = &hci##_pdata, \ ++ .size_data = sizeof(hci##_pdata), \ ++ .dma_mask = DMA_BIT_MASK(32), \ ++} ++ ++USB_PLATFORM_INFO(ehci); ++USB_PLATFORM_INFO(ohci); ++ + /* Ether */ + static struct resource ether_resources[] = { + DEFINE_RES_MEM(0xfde00000, 0x400), +@@ -197,6 +296,14 @@ void __init r8a7778_add_standard_devices(void) + r8a7778_register_tmu(1); + } + ++void __init r8a7778_init_late(void) ++{ ++ phy = usb_get_phy(USB_PHY_TYPE_USB2); ++ ++ platform_device_register_full(&ehci_info); ++ platform_device_register_full(&ohci_info); ++} ++ + static struct renesas_intc_irqpin_config irqpin_platform_data = { + .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ + .sense_bitfield_width = 2, +@@ -310,6 +417,7 @@ DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)") + .init_machine = r8a7778_add_standard_devices_dt, + .init_time = shmobile_timer_init, + .dt_compat = r8a7778_compat_dt, ++ .init_late = r8a7778_init_late, + MACHINE_END + + #endif /* CONFIG_USE_OF */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0259-ARM-shmobile-BOCK-W-add-USB-support.patch b/patches.renesas/0259-ARM-shmobile-BOCK-W-add-USB-support.patch new file mode 100644 index 00000000000..9270c804766 --- /dev/null +++ b/patches.renesas/0259-ARM-shmobile-BOCK-W-add-USB-support.patch @@ -0,0 +1,65 @@ +From 53725d0d63d021983ea26d4fe0cfa0df3fd60efc Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Sun, 9 Jun 2013 00:38:41 +0400 +Subject: ARM: shmobile: BOCK-W: add USB support + +Register the USB PHY device from bockw_init(), passing the platform data to it. +Set machine's init_late() method to r8a7778_init_late() in order for [EO]HCI to +get registered too... + +Don't forget to add USB PENC0/1 pins to bockw_pinctrl_map[]. + +The patch has been tested on the BOCK-W board. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 1a87b01d3b18709ae240ec90ae612354dd44d9a9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + arch/arm/mach-shmobile/board-bockw.c +--- + arch/arm/mach-shmobile/board-bockw.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c +index 2b6103e5..f6ca2ae2 100644 +--- a/arch/arm/mach-shmobile/board-bockw.c ++++ b/arch/arm/mach-shmobile/board-bockw.c +@@ -56,6 +56,8 @@ static struct resource smsc911x_resources[] = { + DEFINE_RES_IRQ(irq_pin(0)), /* IRQ 0 */ + }; + ++static struct rcar_phy_platform_data usb_phy_platform_data __initdata; ++ + /* SDHI */ + static struct sh_mobile_sdhi_info sdhi0_info = { + .tmio_caps = MMC_CAP_SD_HIGHSPEED, +@@ -69,6 +71,10 @@ static const struct pinctrl_map bockw_pinctrl_map[] = { + "scif0_data_a", "scif0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778", + "scif0_ctrl", "scif0"), ++ PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform", "pfc-r8a7778", ++ "usb0", "usb0"), ++ PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform", "pfc-r8a7778", ++ "usb1", "usb1"), + /* SDHI0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778", + "sdhi0", "sdhi0"), +@@ -85,6 +91,7 @@ static void __init bockw_init(void) + r8a7778_clock_init(); + r8a7778_init_irq_extpin(1); + r8a7778_add_standard_devices(); ++ r8a7778_add_usb_phy_device(&usb_phy_platform_data); + + pinctrl_register_mappings(bockw_pinctrl_map, + ARRAY_SIZE(bockw_pinctrl_map)); +@@ -140,4 +147,5 @@ DT_MACHINE_START(BOCKW_DT, "bockw") + .init_machine = bockw_init, + .init_time = shmobile_timer_init, + .dt_compat = bockw_boards_compat_dt, ++ .init_late = r8a7778_init_late, + MACHINE_END +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0260-ARM-shmobile-r8a7778-add-support-I2C-clock.patch b/patches.renesas/0260-ARM-shmobile-r8a7778-add-support-I2C-clock.patch new file mode 100644 index 00000000000..8046e00a3de --- /dev/null +++ b/patches.renesas/0260-ARM-shmobile-r8a7778-add-support-I2C-clock.patch @@ -0,0 +1,70 @@ +From f00ed050f314379e4820624a126aeeb51053729c Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Mon, 3 Jun 2013 22:10:24 -0700 +Subject: ARM: shmobile: r8a7778: add support I2C clock + +This patch adds r8a7778 I2C clock support. +It also adds peripheral_clk which is requiested +from i2c-rcar driver + +Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com> +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit b6bb9a6426cab90216763374b9d2ebc4abc48016) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + arch/arm/mach-shmobile/clock-r8a7778.c +--- + arch/arm/mach-shmobile/clock-r8a7778.c | 14 +++++++++++++- + 1 file changed, 13 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c +index 696d206a..da39198e 100644 +--- a/arch/arm/mach-shmobile/clock-r8a7778.c ++++ b/arch/arm/mach-shmobile/clock-r8a7778.c +@@ -106,7 +106,8 @@ enum { + MSTP323, MSTP322, MSTP321, + MSTP114, + MSTP100, +- MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, ++ MSTP030, ++ MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, + MSTP016, MSTP015, + MSTP_NR }; + +@@ -116,6 +117,10 @@ static struct clk mstp_clks[MSTP_NR] = { + [MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */ + [MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */ + [MSTP100] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 0, 0), /* USB0/1 */ ++ [MSTP030] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 30, 0), /* I2C0 */ ++ [MSTP029] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 29, 0), /* I2C1 */ ++ [MSTP028] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 28, 0), /* I2C2 */ ++ [MSTP027] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 27, 0), /* I2C3 */ + [MSTP026] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 26, 0), /* SCIF0 */ + [MSTP025] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 25, 0), /* SCIF1 */ + [MSTP024] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 24, 0), /* SCIF2 */ +@@ -127,6 +132,9 @@ static struct clk mstp_clks[MSTP_NR] = { + }; + + static struct clk_lookup lookups[] = { ++ /* main */ ++ CLKDEV_CON_ID("peripheral_clk", &p_clk), ++ + /* MSTP32 clocks */ + CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */ + CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ +@@ -134,6 +142,10 @@ static struct clk_lookup lookups[] = { + CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */ + CLKDEV_DEV_ID("ehci-platform", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */ + CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */ ++ CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */ ++ CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */ ++ CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */ ++ CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */ + CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */ + CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */ + CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0261-ARM-shmobile-r8a7778-add-support-HSPI-clock.patch b/patches.renesas/0261-ARM-shmobile-r8a7778-add-support-HSPI-clock.patch new file mode 100644 index 00000000000..13ba0867967 --- /dev/null +++ b/patches.renesas/0261-ARM-shmobile-r8a7778-add-support-HSPI-clock.patch @@ -0,0 +1,56 @@ +From 7519f9fe2739374dec871e09c63a6f1123b6aecf Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Mon, 3 Jun 2013 22:11:24 -0700 +Subject: ARM: shmobile: r8a7778: add support HSPI clock + +This patch adds r8a7778 HSPI clock support. +It also adds shyway_clk which is requiested +from sh-hspi driver + +Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com> +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 3dd691ef07abd55154de913b241f9804fc78b979) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a7778.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c +index da39198e..796bc7e3 100644 +--- a/arch/arm/mach-shmobile/clock-r8a7778.c ++++ b/arch/arm/mach-shmobile/clock-r8a7778.c +@@ -109,6 +109,7 @@ enum { + MSTP030, + MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, + MSTP016, MSTP015, ++ MSTP007, + MSTP_NR }; + + static struct clk mstp_clks[MSTP_NR] = { +@@ -129,10 +130,12 @@ static struct clk mstp_clks[MSTP_NR] = { + [MSTP021] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 21, 0), /* SCIF5 */ + [MSTP016] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 16, 0), /* TMU0 */ + [MSTP015] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 15, 0), /* TMU1 */ ++ [MSTP007] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 7, 0), /* HSPI */ + }; + + static struct clk_lookup lookups[] = { + /* main */ ++ CLKDEV_CON_ID("shyway_clk", &s_clk), + CLKDEV_CON_ID("peripheral_clk", &p_clk), + + /* MSTP32 clocks */ +@@ -154,6 +157,9 @@ static struct clk_lookup lookups[] = { + CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */ + CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */ + CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */ ++ CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */ ++ CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */ ++ CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */ + }; + + void __init r8a7778_clock_init(void) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0262-ARM-shmobile-r8a7778-add-support-MMC-clock.patch b/patches.renesas/0262-ARM-shmobile-r8a7778-add-support-MMC-clock.patch new file mode 100644 index 00000000000..665693fd597 --- /dev/null +++ b/patches.renesas/0262-ARM-shmobile-r8a7778-add-support-MMC-clock.patch @@ -0,0 +1,47 @@ +From 9dd16b9c353e85c50c43079859473265157401a9 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Mon, 3 Jun 2013 22:11:39 -0700 +Subject: ARM: shmobile: r8a7778: add support MMC clock + +This patch adds r8a7778 MMC clock support. + +Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com> +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 2ad3c8eb17ac7aed7fad870ba85acd4639cc8cdf) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a7778.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c +index 796bc7e3..53798e50 100644 +--- a/arch/arm/mach-shmobile/clock-r8a7778.c ++++ b/arch/arm/mach-shmobile/clock-r8a7778.c +@@ -103,6 +103,7 @@ static struct clk *main_clks[] = { + }; + + enum { ++ MSTP331, + MSTP323, MSTP322, MSTP321, + MSTP114, + MSTP100, +@@ -113,6 +114,7 @@ enum { + MSTP_NR }; + + static struct clk mstp_clks[MSTP_NR] = { ++ [MSTP331] = SH_CLK_MSTP32(&s4_clk, MSTPCR3, 31, 0), /* MMC */ + [MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */ + [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */ + [MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */ +@@ -139,6 +141,7 @@ static struct clk_lookup lookups[] = { + CLKDEV_CON_ID("peripheral_clk", &p_clk), + + /* MSTP32 clocks */ ++ CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP331]), /* MMC */ + CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */ + CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ + CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0263-ARM-shmobile-r8a7778-add-support-I2C-driver.patch b/patches.renesas/0263-ARM-shmobile-r8a7778-add-support-I2C-driver.patch new file mode 100644 index 00000000000..c2221418370 --- /dev/null +++ b/patches.renesas/0263-ARM-shmobile-r8a7778-add-support-I2C-driver.patch @@ -0,0 +1,72 @@ +From d2233c152d926d5c44485e0f93f82fecbfb7140e Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Mon, 3 Jun 2013 22:11:58 -0700 +Subject: ARM: shmobile: r8a7778: add support I2C driver + +Add a platform device for the r8a7778 I2C. + +Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com> +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 46b9a092dacea4f30dbdfc58ca2c1ac4e97f6255) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + arch/arm/mach-shmobile/include/mach/r8a7778.h +--- + arch/arm/mach-shmobile/include/mach/r8a7778.h | 2 ++ + arch/arm/mach-shmobile/setup-r8a7778.c | 25 +++++++++++++++++++++++++ + 2 files changed, 27 insertions(+) + +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h +index 1d4207cc..184c727c 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h +@@ -26,6 +26,8 @@ extern void r8a7778_add_standard_devices(void); + extern void r8a7778_add_standard_devices_dt(void); + extern void r8a7778_add_ether_device(struct sh_eth_plat_data *pdata); + extern void r8a7778_add_usb_phy_device(struct rcar_phy_platform_data *pdata); ++extern void r8a7778_add_i2c_device(int id); ++ + extern void r8a7778_init_late(void); + extern void r8a7778_init_delay(void); + extern void r8a7778_init_irq(void); +diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c +index 94211335..67dfea7e 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7778.c ++++ b/arch/arm/mach-shmobile/setup-r8a7778.c +@@ -272,6 +272,31 @@ void __init r8a7778_sdhi_init(int id, + info, sizeof(*info)); + } + ++/* I2C */ ++static struct resource i2c_resources[] __initdata = { ++ /* I2C0 */ ++ DEFINE_RES_MEM(0xffc70000, 0x1000), ++ DEFINE_RES_IRQ(gic_iid(0x63)), ++ /* I2C1 */ ++ DEFINE_RES_MEM(0xffc71000, 0x1000), ++ DEFINE_RES_IRQ(gic_iid(0x6e)), ++ /* I2C2 */ ++ DEFINE_RES_MEM(0xffc72000, 0x1000), ++ DEFINE_RES_IRQ(gic_iid(0x6c)), ++ /* I2C3 */ ++ DEFINE_RES_MEM(0xffc73000, 0x1000), ++ DEFINE_RES_IRQ(gic_iid(0x6d)), ++}; ++ ++void __init r8a7778_add_i2c_device(int id) ++{ ++ BUG_ON(id < 0 || id > 3); ++ ++ platform_device_register_simple( ++ "i2c-rcar", id, ++ i2c_resources + (2 * id), 2); ++} ++ + void __init r8a7778_add_standard_devices(void) + { + int i; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0264-ARM-shmobile-r8a7778-add-support-HSPI-driver.patch b/patches.renesas/0264-ARM-shmobile-r8a7778-add-support-HSPI-driver.patch new file mode 100644 index 00000000000..687f517426a --- /dev/null +++ b/patches.renesas/0264-ARM-shmobile-r8a7778-add-support-HSPI-driver.patch @@ -0,0 +1,66 @@ +From 8db4345dc803396cfb4a6f9b4ca363df92d102fa Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Mon, 3 Jun 2013 22:12:08 -0700 +Subject: ARM: shmobile: r8a7778: add support HSPI driver + +Add a platform device for the r8a7778 HSPI. + +Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com> +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 8b89797f3273e6e1574e1727f73dc8ac7d5f5a9c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/include/mach/r8a7778.h | 1 + + arch/arm/mach-shmobile/setup-r8a7778.c | 23 +++++++++++++++++++++++ + 2 files changed, 24 insertions(+) + +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h +index 184c727c..301817ba 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h +@@ -27,6 +27,7 @@ extern void r8a7778_add_standard_devices_dt(void); + extern void r8a7778_add_ether_device(struct sh_eth_plat_data *pdata); + extern void r8a7778_add_usb_phy_device(struct rcar_phy_platform_data *pdata); + extern void r8a7778_add_i2c_device(int id); ++extern void r8a7778_add_hspi_device(int id); + + extern void r8a7778_init_late(void); + extern void r8a7778_init_delay(void); +diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c +index 67dfea7e..3b9bea8b 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7778.c ++++ b/arch/arm/mach-shmobile/setup-r8a7778.c +@@ -297,6 +297,29 @@ void __init r8a7778_add_i2c_device(int id) + i2c_resources + (2 * id), 2); + } + ++/* HSPI */ ++static struct resource hspi_resources[] __initdata = { ++ /* HSPI0 */ ++ DEFINE_RES_MEM(0xfffc7000, 0x18), ++ DEFINE_RES_IRQ(gic_iid(0x5f)), ++ /* HSPI1 */ ++ DEFINE_RES_MEM(0xfffc8000, 0x18), ++ DEFINE_RES_IRQ(gic_iid(0x74)), ++ /* HSPI2 */ ++ DEFINE_RES_MEM(0xfffc6000, 0x18), ++ DEFINE_RES_IRQ(gic_iid(0x75)), ++}; ++ ++void __init r8a7778_add_hspi_device(int id) ++{ ++ BUG_ON(id < 0 || id > 2); ++ ++ platform_device_register_simple( ++ "sh-hspi", id, ++ hspi_resources + (2 * id), 2); ++} ++ ++ + void __init r8a7778_add_standard_devices(void) + { + int i; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0265-ARM-shmobile-r8a7778-add-support-MMC-driver.patch b/patches.renesas/0265-ARM-shmobile-r8a7778-add-support-MMC-driver.patch new file mode 100644 index 00000000000..6b44ca82c53 --- /dev/null +++ b/patches.renesas/0265-ARM-shmobile-r8a7778-add-support-MMC-driver.patch @@ -0,0 +1,64 @@ +From f28e09c76620a503c73ce011204006ca090e4290 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Mon, 3 Jun 2013 22:12:22 -0700 +Subject: ARM: shmobile: r8a7778: add support MMC driver + +Add a platform device for the r8a7778 MMC. + +Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com> +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 31b2eaccd60c3480ad81a3302faed463fdc5df12) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/include/mach/r8a7778.h | 2 ++ + arch/arm/mach-shmobile/setup-r8a7778.c | 13 +++++++++++++ + 2 files changed, 15 insertions(+) + +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h +index 301817ba..851d027a 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h +@@ -18,6 +18,7 @@ + #ifndef __ASM_R8A7778_H__ + #define __ASM_R8A7778_H__ + ++#include <linux/mmc/sh_mmcif.h> + #include <linux/mmc/sh_mobile_sdhi.h> + #include <linux/sh_eth.h> + #include <linux/platform_data/usb-rcar-phy.h> +@@ -28,6 +29,7 @@ extern void r8a7778_add_ether_device(struct sh_eth_plat_data *pdata); + extern void r8a7778_add_usb_phy_device(struct rcar_phy_platform_data *pdata); + extern void r8a7778_add_i2c_device(int id); + extern void r8a7778_add_hspi_device(int id); ++extern void r8a7778_add_mmc_device(struct sh_mmcif_plat_data *info); + + extern void r8a7778_init_late(void); + extern void r8a7778_init_delay(void); +diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c +index 3b9bea8b..80c20392 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7778.c ++++ b/arch/arm/mach-shmobile/setup-r8a7778.c +@@ -319,6 +319,19 @@ void __init r8a7778_add_hspi_device(int id) + hspi_resources + (2 * id), 2); + } + ++/* MMC */ ++static struct resource mmc_resources[] __initdata = { ++ DEFINE_RES_MEM(0xffe4e000, 0x100), ++ DEFINE_RES_IRQ(gic_iid(0x5d)), ++}; ++ ++void __init r8a7778_add_mmc_device(struct sh_mmcif_plat_data *info) ++{ ++ platform_device_register_resndata( ++ &platform_bus, "sh_mmcif", -1, ++ mmc_resources, ARRAY_SIZE(mmc_resources), ++ info, sizeof(*info)); ++} + + void __init r8a7778_add_standard_devices(void) + { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0266-ARM-shmobile-bockw-defconfig-add-RTC-RX8581-support.patch b/patches.renesas/0266-ARM-shmobile-bockw-defconfig-add-RTC-RX8581-support.patch new file mode 100644 index 00000000000..dc6e7723160 --- /dev/null +++ b/patches.renesas/0266-ARM-shmobile-bockw-defconfig-add-RTC-RX8581-support.patch @@ -0,0 +1,29 @@ +From e689df0e7ea27a4657e3b2755b0b8b5f7a093846 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 11 Jun 2013 19:14:53 -0700 +Subject: ARM: shmobile: bockw defconfig: add RTC RX8581 support + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 76563bf4ba08beec91102e3790cb5d93fe23f484) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/configs/bockw_defconfig | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm/configs/bockw_defconfig b/arch/arm/configs/bockw_defconfig +index d6626086..cb7638d1 100644 +--- a/arch/arm/configs/bockw_defconfig ++++ b/arch/arm/configs/bockw_defconfig +@@ -86,6 +86,8 @@ CONFIG_USB_STORAGE=y + CONFIG_USB_RCAR_PHY=y + CONFIG_MMC=y + CONFIG_MMC_SDHI=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_DRV_RX8581=y + CONFIG_UIO=y + CONFIG_UIO_PDRV_GENIRQ=y + # CONFIG_IOMMU_SUPPORT is not set +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0267-ARM-shmobile-bockw-defconfig-add-M25P80-support.patch b/patches.renesas/0267-ARM-shmobile-bockw-defconfig-add-M25P80-support.patch new file mode 100644 index 00000000000..c4a8ff14081 --- /dev/null +++ b/patches.renesas/0267-ARM-shmobile-bockw-defconfig-add-M25P80-support.patch @@ -0,0 +1,42 @@ +From f2a99a8c7c072ff3a546823871bc5a0fc1ddd5d3 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 11 Jun 2013 19:16:38 -0700 +Subject: ARM: shmobile: bockw defconfig: add M25P80 support + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 206c0e7a1d15774cb4965e0e7a6a592063085240) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/configs/bockw_defconfig | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/arm/configs/bockw_defconfig b/arch/arm/configs/bockw_defconfig +index cb7638d1..55e00ff9 100644 +--- a/arch/arm/configs/bockw_defconfig ++++ b/arch/arm/configs/bockw_defconfig +@@ -49,6 +49,12 @@ CONFIG_DEVTMPFS_MOUNT=y + # CONFIG_STANDALONE is not set + # CONFIG_PREVENT_FIRMWARE_BUILD is not set + # CONFIG_FW_LOADER is not set ++CONFIG_MTD=y ++CONFIG_MTD_CHAR=y ++CONFIG_MTD_BLOCK=y ++CONFIG_MTD_CFI=y ++CONFIG_MTD_CFI_AMDSTD=y ++CONFIG_MTD_M25P80=y + CONFIG_SCSI=y + CONFIG_BLK_DEV_SD=y + CONFIG_NETDEVICES=y +@@ -76,6 +82,8 @@ CONFIG_SERIAL_SH_SCI_CONSOLE=y + # CONFIG_HWMON is not set + CONFIG_I2C=y + CONFIG_I2C_RCAR=y ++CONFIG_SPI=y ++CONFIG_SPI_SH_HSPI=y + CONFIG_USB=y + CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + CONFIG_USB_EHCI_HCD=y +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0268-ARM-shmobile-bockw-defconfig-add-MMCIF-support.patch b/patches.renesas/0268-ARM-shmobile-bockw-defconfig-add-MMCIF-support.patch new file mode 100644 index 00000000000..31a7e62d319 --- /dev/null +++ b/patches.renesas/0268-ARM-shmobile-bockw-defconfig-add-MMCIF-support.patch @@ -0,0 +1,28 @@ +From 68db5c2c5a08e3725c294184647b49c75ad0d706 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 11 Jun 2013 19:16:58 -0700 +Subject: ARM: shmobile: bockw defconfig: add MMCIF support + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d69626d8913ceeacaa2cd369a2487c85f818fef1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/configs/bockw_defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/configs/bockw_defconfig b/arch/arm/configs/bockw_defconfig +index 55e00ff9..845f5cdf 100644 +--- a/arch/arm/configs/bockw_defconfig ++++ b/arch/arm/configs/bockw_defconfig +@@ -94,6 +94,7 @@ CONFIG_USB_STORAGE=y + CONFIG_USB_RCAR_PHY=y + CONFIG_MMC=y + CONFIG_MMC_SDHI=y ++CONFIG_MMC_SH_MMCIF=y + CONFIG_RTC_CLASS=y + CONFIG_RTC_DRV_RX8581=y + CONFIG_UIO=y +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0269-pinctrl-r8a73a4-add-pinmux-data-for-MMCIF-and-SDHI-i.patch b/patches.renesas/0269-pinctrl-r8a73a4-add-pinmux-data-for-MMCIF-and-SDHI-i.patch new file mode 100644 index 00000000000..99d698f49a2 --- /dev/null +++ b/patches.renesas/0269-pinctrl-r8a73a4-add-pinmux-data-for-MMCIF-and-SDHI-i.patch @@ -0,0 +1,272 @@ +From 66dadafc21f5b27b045b71c7fe0d3a3e668aff9b Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Tue, 11 Jun 2013 13:37:48 +0200 +Subject: pinctrl: r8a73a4: add pinmux data for MMCIF and SDHI interfaces + +This patch adds pinmux groups and functions for the two MMCIF and three +SDHI interfaces on r8a73a4 (APE6). + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 6e8d1d41bba39e051c9c860efbd83078a94f59a3) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a73a4.c | 198 +++++++++++++++++++++++++++++++++++ + 1 file changed, 198 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +index bbff5596..82bf6aba 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +@@ -1488,6 +1488,66 @@ IRQC_PINS_MUX(326, 54); + IRQC_PINS_MUX(327, 55); + IRQC_PINS_MUX(328, 56); + IRQC_PINS_MUX(329, 57); ++/* - MMCIF0 ----------------------------------------------------------------- */ ++static const unsigned int mmc0_data1_pins[] = { ++ /* D[0] */ ++ 164, ++}; ++static const unsigned int mmc0_data1_mux[] = { ++ MMCD0_0_MARK, ++}; ++static const unsigned int mmc0_data4_pins[] = { ++ /* D[0:3] */ ++ 164, 165, 166, 167, ++}; ++static const unsigned int mmc0_data4_mux[] = { ++ MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, ++}; ++static const unsigned int mmc0_data8_pins[] = { ++ /* D[0:7] */ ++ 164, 165, 166, 167, 168, 169, 170, 171, ++}; ++static const unsigned int mmc0_data8_mux[] = { ++ MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, ++ MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK, ++}; ++static const unsigned int mmc0_ctrl_pins[] = { ++ /* CMD, CLK */ ++ 172, 173, ++}; ++static const unsigned int mmc0_ctrl_mux[] = { ++ MMCCMD0_MARK, MMCCLK0_MARK, ++}; ++/* - MMCIF1 ----------------------------------------------------------------- */ ++static const unsigned int mmc1_data1_pins[] = { ++ /* D[0] */ ++ 199, ++}; ++static const unsigned int mmc1_data1_mux[] = { ++ MMCD1_0_MARK, ++}; ++static const unsigned int mmc1_data4_pins[] = { ++ /* D[0:3] */ ++ 199, 198, 197, 196, ++}; ++static const unsigned int mmc1_data4_mux[] = { ++ MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, ++}; ++static const unsigned int mmc1_data8_pins[] = { ++ /* D[0:7] */ ++ 199, 198, 197, 196, 195, 194, 193, 192, ++}; ++static const unsigned int mmc1_data8_mux[] = { ++ MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, ++ MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK, ++}; ++static const unsigned int mmc1_ctrl_pins[] = { ++ /* CMD, CLK */ ++ 200, 203, ++}; ++static const unsigned int mmc1_ctrl_mux[] = { ++ MMCCMD1_MARK, MMCCLK1_MARK, ++}; + /* - SCIFA0 ----------------------------------------------------------------- */ + static const unsigned int scifa0_data_pins[] = { + /* SCIFA0_RXD, SCIFA0_TXD */ +@@ -1683,6 +1743,86 @@ static const unsigned int scifb3_ctrl_b_pins[] = { + static const unsigned int scifb3_ctrl_b_mux[] = { + SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK, + }; ++/* - SDHI0 ------------------------------------------------------------------ */ ++static const unsigned int sdhi0_data1_pins[] = { ++ /* D0 */ ++ 302, ++}; ++static const unsigned int sdhi0_data1_mux[] = { ++ SDHID0_0_MARK, ++}; ++static const unsigned int sdhi0_data4_pins[] = { ++ /* D[0:3] */ ++ 302, 303, 304, 305, ++}; ++static const unsigned int sdhi0_data4_mux[] = { ++ SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK, ++}; ++static const unsigned int sdhi0_ctrl_pins[] = { ++ /* CLK, CMD */ ++ 308, 306, ++}; ++static const unsigned int sdhi0_ctrl_mux[] = { ++ SDHICLK0_MARK, SDHICMD0_MARK, ++}; ++static const unsigned int sdhi0_cd_pins[] = { ++ /* CD */ ++ 301, ++}; ++static const unsigned int sdhi0_cd_mux[] = { ++ SDHICD0_MARK, ++}; ++static const unsigned int sdhi0_wp_pins[] = { ++ /* WP */ ++ 307, ++}; ++static const unsigned int sdhi0_wp_mux[] = { ++ SDHIWP0_MARK, ++}; ++/* - SDHI1 ------------------------------------------------------------------ */ ++static const unsigned int sdhi1_data1_pins[] = { ++ /* D0 */ ++ 289, ++}; ++static const unsigned int sdhi1_data1_mux[] = { ++ SDHID1_0_MARK, ++}; ++static const unsigned int sdhi1_data4_pins[] = { ++ /* D[0:3] */ ++ 289, 290, 291, 292, ++}; ++static const unsigned int sdhi1_data4_mux[] = { ++ SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK, ++}; ++static const unsigned int sdhi1_ctrl_pins[] = { ++ /* CLK, CMD */ ++ 293, 294, ++}; ++static const unsigned int sdhi1_ctrl_mux[] = { ++ SDHICLK1_MARK, SDHICMD1_MARK, ++}; ++/* - SDHI2 ------------------------------------------------------------------ */ ++static const unsigned int sdhi2_data1_pins[] = { ++ /* D0 */ ++ 295, ++}; ++static const unsigned int sdhi2_data1_mux[] = { ++ SDHID2_0_MARK, ++}; ++static const unsigned int sdhi2_data4_pins[] = { ++ /* D[0:3] */ ++ 295, 296, 297, 298, ++}; ++static const unsigned int sdhi2_data4_mux[] = { ++ SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK, ++}; ++static const unsigned int sdhi2_ctrl_pins[] = { ++ /* CLK, CMD */ ++ 299, 300, ++}; ++static const unsigned int sdhi2_ctrl_mux[] = { ++ SDHICLK2_MARK, SDHICMD2_MARK, ++}; + + static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(irqc_irq0), +@@ -1743,6 +1883,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(irqc_irq55), + SH_PFC_PIN_GROUP(irqc_irq56), + SH_PFC_PIN_GROUP(irqc_irq57), ++ SH_PFC_PIN_GROUP(mmc0_data1), ++ SH_PFC_PIN_GROUP(mmc0_data4), ++ SH_PFC_PIN_GROUP(mmc0_data8), ++ SH_PFC_PIN_GROUP(mmc0_ctrl), ++ SH_PFC_PIN_GROUP(mmc1_data1), ++ SH_PFC_PIN_GROUP(mmc1_data4), ++ SH_PFC_PIN_GROUP(mmc1_data8), ++ SH_PFC_PIN_GROUP(mmc1_ctrl), + SH_PFC_PIN_GROUP(scifa0_data), + SH_PFC_PIN_GROUP(scifa0_clk), + SH_PFC_PIN_GROUP(scifa0_ctrl), +@@ -1770,6 +1918,17 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(scifb3_data_b), + SH_PFC_PIN_GROUP(scifb3_clk_b), + SH_PFC_PIN_GROUP(scifb3_ctrl_b), ++ SH_PFC_PIN_GROUP(sdhi0_data1), ++ SH_PFC_PIN_GROUP(sdhi0_data4), ++ SH_PFC_PIN_GROUP(sdhi0_ctrl), ++ SH_PFC_PIN_GROUP(sdhi0_cd), ++ SH_PFC_PIN_GROUP(sdhi0_wp), ++ SH_PFC_PIN_GROUP(sdhi1_data1), ++ SH_PFC_PIN_GROUP(sdhi1_data4), ++ SH_PFC_PIN_GROUP(sdhi1_ctrl), ++ SH_PFC_PIN_GROUP(sdhi2_data1), ++ SH_PFC_PIN_GROUP(sdhi2_data4), ++ SH_PFC_PIN_GROUP(sdhi2_ctrl), + }; + + static const char * const irqc_groups[] = { +@@ -1833,6 +1992,20 @@ static const char * const irqc_groups[] = { + "irqc_irq57", + }; + ++static const char * const mmc0_groups[] = { ++ "mmc0_data1", ++ "mmc0_data4", ++ "mmc0_data8", ++ "mmc0_ctrl", ++}; ++ ++static const char * const mmc1_groups[] = { ++ "mmc1_data1", ++ "mmc1_data4", ++ "mmc1_data8", ++ "mmc1_ctrl", ++}; ++ + static const char * const scifa0_groups[] = { + "scifa0_data", + "scifa0_clk", +@@ -1878,14 +2051,39 @@ static const char * const scifb3_groups[] = { + "scifb3_ctrl_b", + }; + ++static const char * const sdhi0_groups[] = { ++ "sdhi0_data1", ++ "sdhi0_data4", ++ "sdhi0_ctrl", ++ "sdhi0_cd", ++ "sdhi0_wp", ++}; ++ ++static const char * const sdhi1_groups[] = { ++ "sdhi1_data1", ++ "sdhi1_data4", ++ "sdhi1_ctrl", ++}; ++ ++static const char * const sdhi2_groups[] = { ++ "sdhi2_data1", ++ "sdhi2_data4", ++ "sdhi2_ctrl", ++}; ++ + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(irqc), ++ SH_PFC_FUNCTION(mmc0), ++ SH_PFC_FUNCTION(mmc1), + SH_PFC_FUNCTION(scifa0), + SH_PFC_FUNCTION(scifa1), + SH_PFC_FUNCTION(scifb0), + SH_PFC_FUNCTION(scifb1), + SH_PFC_FUNCTION(scifb2), + SH_PFC_FUNCTION(scifb3), ++ SH_PFC_FUNCTION(sdhi0), ++ SH_PFC_FUNCTION(sdhi1), ++ SH_PFC_FUNCTION(sdhi2), + }; + + #undef PORTCR +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0270-sh-pfc-r8a7790-add-HSCIF-pin-groups.patch b/patches.renesas/0270-sh-pfc-r8a7790-add-HSCIF-pin-groups.patch new file mode 100644 index 00000000000..6a715704a7b --- /dev/null +++ b/patches.renesas/0270-sh-pfc-r8a7790-add-HSCIF-pin-groups.patch @@ -0,0 +1,292 @@ +From 7ff6edf534e2ff4aea721cef36cc795a96d84434 Mon Sep 17 00:00:00 2001 +From: Ulrich Hecht <ulrich.hecht@gmail.com> +Date: Fri, 31 May 2013 15:57:03 +0000 +Subject: sh-pfc: r8a7790: add HSCIF pin groups + +Adds HSCIF data/clk/ctrl groups to R8A7790 PFC driver. + +Signed-off-by: Ulrich Hecht <ulrich.hecht@gmail.com> +Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit fbd0ca3de1380cf1881e5e92fb8a97ad24171b4c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 211 ++++++++++++++++++++++++++++++++--- + 1 file changed, 196 insertions(+), 15 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +index 85d77a41..1e7a5eb7 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -1979,6 +1979,141 @@ static const unsigned int scif1_clk_e_pins[] = { + static const unsigned int scif1_clk_e_mux[] = { + SCK1_E_MARK, + }; ++/* - HSCIF0 ----------------------------------------------------------------- */ ++static const unsigned int hscif0_data_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), ++}; ++static const unsigned int hscif0_data_mux[] = { ++ HRX0_MARK, HTX0_MARK, ++}; ++static const unsigned int hscif0_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(5, 7), ++}; ++static const unsigned int hscif0_clk_mux[] = { ++ HSCK0_MARK, ++}; ++static const unsigned int hscif0_ctrl_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), ++}; ++static const unsigned int hscif0_ctrl_mux[] = { ++ HRTS0_N_MARK, HCTS0_N_MARK, ++}; ++static const unsigned int hscif0_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12), ++}; ++static const unsigned int hscif0_data_b_mux[] = { ++ HRX0_B_MARK, HTX0_B_MARK, ++}; ++static const unsigned int hscif0_ctrl_b_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), ++}; ++static const unsigned int hscif0_ctrl_b_mux[] = { ++ HRTS0_N_B_MARK, HCTS0_N_B_MARK, ++}; ++static const unsigned int hscif0_data_c_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16), ++}; ++static const unsigned int hscif0_data_c_mux[] = { ++ HRX0_C_MARK, HTX0_C_MARK, ++}; ++static const unsigned int hscif0_ctrl_c_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7), ++}; ++static const unsigned int hscif0_ctrl_c_mux[] = { ++ HRTS0_N_C_MARK, HCTS0_N_C_MARK, ++}; ++static const unsigned int hscif0_data_d_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), ++}; ++static const unsigned int hscif0_data_d_mux[] = { ++ HRX0_D_MARK, HTX0_D_MARK, ++}; ++static const unsigned int hscif0_ctrl_d_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), ++}; ++static const unsigned int hscif0_ctrl_d_mux[] = { ++ HRTS0_N_D_MARK, HCTS0_N_D_MARK, ++}; ++static const unsigned int hscif0_data_e_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), ++}; ++static const unsigned int hscif0_data_e_mux[] = { ++ HRX0_E_MARK, HTX0_E_MARK, ++}; ++static const unsigned int hscif0_ctrl_e_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23), ++}; ++static const unsigned int hscif0_ctrl_e_mux[] = { ++ HRTS0_N_E_MARK, HCTS0_N_E_MARK, ++}; ++static const unsigned int hscif0_data_f_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25), ++}; ++static const unsigned int hscif0_data_f_mux[] = { ++ HRX0_F_MARK, HTX0_F_MARK, ++}; ++static const unsigned int hscif0_ctrl_f_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24), ++}; ++static const unsigned int hscif0_ctrl_f_mux[] = { ++ HRTS0_N_F_MARK, HCTS0_N_F_MARK, ++}; ++/* - HSCIF1 ----------------------------------------------------------------- */ ++static const unsigned int hscif1_data_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), ++}; ++static const unsigned int hscif1_data_mux[] = { ++ HRX1_MARK, HTX1_MARK, ++}; ++static const unsigned int hscif1_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(4, 27), ++}; ++static const unsigned int hscif1_clk_mux[] = { ++ HSCK1_MARK, ++}; ++static const unsigned int hscif1_ctrl_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), ++}; ++static const unsigned int hscif1_ctrl_mux[] = { ++ HRTS1_N_MARK, HCTS1_N_MARK, ++}; ++static const unsigned int hscif1_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18), ++}; ++static const unsigned int hscif1_data_b_mux[] = { ++ HRX1_B_MARK, HTX1_B_MARK, ++}; ++static const unsigned int hscif1_clk_b_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(1, 28), ++}; ++static const unsigned int hscif1_clk_b_mux[] = { ++ HSCK1_B_MARK, ++}; ++static const unsigned int hscif1_ctrl_b_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), ++}; ++static const unsigned int hscif1_ctrl_b_mux[] = { ++ HRTS1_N_B_MARK, HCTS1_N_B_MARK, ++}; + /* - SCIFA0 ----------------------------------------------------------------- */ + static const unsigned int scifa0_data_pins[] = { + /* RXD, TXD */ +@@ -2591,10 +2726,37 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(eth_magic), + SH_PFC_PIN_GROUP(eth_mdio), + SH_PFC_PIN_GROUP(eth_rmii), ++ SH_PFC_PIN_GROUP(hscif0_data), ++ SH_PFC_PIN_GROUP(hscif0_clk), ++ SH_PFC_PIN_GROUP(hscif0_ctrl), ++ SH_PFC_PIN_GROUP(hscif0_data_b), ++ SH_PFC_PIN_GROUP(hscif0_ctrl_b), ++ SH_PFC_PIN_GROUP(hscif0_data_c), ++ SH_PFC_PIN_GROUP(hscif0_ctrl_c), ++ SH_PFC_PIN_GROUP(hscif0_data_d), ++ SH_PFC_PIN_GROUP(hscif0_ctrl_d), ++ SH_PFC_PIN_GROUP(hscif0_data_e), ++ SH_PFC_PIN_GROUP(hscif0_ctrl_e), ++ SH_PFC_PIN_GROUP(hscif0_data_f), ++ SH_PFC_PIN_GROUP(hscif0_ctrl_f), ++ SH_PFC_PIN_GROUP(hscif1_data), ++ SH_PFC_PIN_GROUP(hscif1_clk), ++ SH_PFC_PIN_GROUP(hscif1_ctrl), ++ SH_PFC_PIN_GROUP(hscif1_data_b), ++ SH_PFC_PIN_GROUP(hscif1_clk_b), ++ SH_PFC_PIN_GROUP(hscif1_ctrl_b), + SH_PFC_PIN_GROUP(intc_irq0), + SH_PFC_PIN_GROUP(intc_irq1), + SH_PFC_PIN_GROUP(intc_irq2), + SH_PFC_PIN_GROUP(intc_irq3), ++ SH_PFC_PIN_GROUP(mmc0_data1), ++ SH_PFC_PIN_GROUP(mmc0_data4), ++ SH_PFC_PIN_GROUP(mmc0_data8), ++ SH_PFC_PIN_GROUP(mmc0_ctrl), ++ SH_PFC_PIN_GROUP(mmc1_data1), ++ SH_PFC_PIN_GROUP(mmc1_data4), ++ SH_PFC_PIN_GROUP(mmc1_data8), ++ SH_PFC_PIN_GROUP(mmc1_ctrl), + SH_PFC_PIN_GROUP(scif0_data), + SH_PFC_PIN_GROUP(scif0_clk), + SH_PFC_PIN_GROUP(scif0_ctrl), +@@ -2659,18 +2821,6 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(scifb2_clk_b), + SH_PFC_PIN_GROUP(scifb2_ctrl_b), + SH_PFC_PIN_GROUP(scifb2_data_c), +- SH_PFC_PIN_GROUP(tpu0_to0), +- SH_PFC_PIN_GROUP(tpu0_to1), +- SH_PFC_PIN_GROUP(tpu0_to2), +- SH_PFC_PIN_GROUP(tpu0_to3), +- SH_PFC_PIN_GROUP(mmc0_data1), +- SH_PFC_PIN_GROUP(mmc0_data4), +- SH_PFC_PIN_GROUP(mmc0_data8), +- SH_PFC_PIN_GROUP(mmc0_ctrl), +- SH_PFC_PIN_GROUP(mmc1_data1), +- SH_PFC_PIN_GROUP(mmc1_data4), +- SH_PFC_PIN_GROUP(mmc1_data8), +- SH_PFC_PIN_GROUP(mmc1_ctrl), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), +@@ -2691,6 +2841,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(sdhi3_ctrl), + SH_PFC_PIN_GROUP(sdhi3_cd), + SH_PFC_PIN_GROUP(sdhi3_wp), ++ SH_PFC_PIN_GROUP(tpu0_to0), ++ SH_PFC_PIN_GROUP(tpu0_to1), ++ SH_PFC_PIN_GROUP(tpu0_to2), ++ SH_PFC_PIN_GROUP(tpu0_to3), + }; + + static const char * const eth_groups[] = { +@@ -2726,6 +2880,31 @@ static const char * const scif1_groups[] = { + "scif1_clk_e", + }; + ++static const char * const hscif0_groups[] = { ++ "hscif0_data", ++ "hscif0_clk", ++ "hscif0_ctrl", ++ "hscif0_data_b", ++ "hscif0_ctrl_b", ++ "hscif0_data_c", ++ "hscif0_ctrl_c", ++ "hscif0_data_d", ++ "hscif0_ctrl_d", ++ "hscif0_data_e", ++ "hscif0_ctrl_e", ++ "hscif0_data_f", ++ "hscif0_ctrl_f", ++}; ++ ++static const char * const hscif1_groups[] = { ++ "hscif1_data", ++ "hscif1_clk", ++ "hscif1_ctrl", ++ "hscif1_data_b", ++ "hscif1_clk_b", ++ "hscif1_ctrl_b", ++}; ++ + static const char * const scifa0_groups[] = { + "scifa0_data", + "scifa0_clk", +@@ -2850,7 +3029,11 @@ static const char * const sdhi3_groups[] = { + + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(eth), ++ SH_PFC_FUNCTION(hscif0), ++ SH_PFC_FUNCTION(hscif1), + SH_PFC_FUNCTION(intc), ++ SH_PFC_FUNCTION(mmc0), ++ SH_PFC_FUNCTION(mmc1), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scifa0), +@@ -2859,13 +3042,11 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(scifb0), + SH_PFC_FUNCTION(scifb1), + SH_PFC_FUNCTION(scifb2), +- SH_PFC_FUNCTION(tpu0), +- SH_PFC_FUNCTION(mmc0), +- SH_PFC_FUNCTION(mmc1), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(sdhi3), ++ SH_PFC_FUNCTION(tpu0), + }; + + static struct pinmux_cfg_reg pinmux_config_regs[] = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0271-ARM-shmobile-uImage-load-address-rework.patch b/patches.renesas/0271-ARM-shmobile-uImage-load-address-rework.patch new file mode 100644 index 00000000000..e74438f8a9a --- /dev/null +++ b/patches.renesas/0271-ARM-shmobile-uImage-load-address-rework.patch @@ -0,0 +1,57 @@ +From 3ffa6a032b75555a10834019e2704a8c3abe420d Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Mon, 10 Jun 2013 18:28:57 +0900 +Subject: ARM: shmobile: uImage load address rework + +This is V2 of the mach-shmobile uImage load address rework patch. + +Rework the mach-shmobile uImage load address calculation by storing +the per-board load addresses in Makefile.boot. This removes the +CONFIG_MEMORY_START dependency from Makefile.boot, and it also makes +it possible to create safe kernel images that boot on multiple boards. + +This is one of several series of code that reworks code not to rely on +CONFIG_MEMORY_START/SIZE which in turn is needed for ARCH_MULTIPLATFORM. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Reviewed-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 12dca809ef785e451263351325d4806198040b40) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/Makefile.boot | 20 ++++++++++++++++++-- + 1 file changed, 18 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot +index 498efd99..6b147ea2 100644 +--- a/arch/arm/mach-shmobile/Makefile.boot ++++ b/arch/arm/mach-shmobile/Makefile.boot +@@ -1,6 +1,22 @@ +-__ZRELADDR := $(shell /bin/bash -c 'printf "0x%08x" \ +- $$[$(CONFIG_MEMORY_START) + 0x8000]') ++# per-board load address for uImage ++loadaddr-y := ++loadaddr-$(CONFIG_MACH_AG5EVM) += 0x40008000 ++loadaddr-$(CONFIG_MACH_AP4EVB) += 0x40008000 ++loadaddr-$(CONFIG_MACH_APE6EVM) += 0x40008000 ++loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000 ++loadaddr-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += 0x40008000 ++loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000 ++loadaddr-$(CONFIG_MACH_BONITO) += 0x40008000 ++loadaddr-$(CONFIG_MACH_KOTA2) += 0x41008000 ++loadaddr-$(CONFIG_MACH_KZM9D) += 0x40008000 ++loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000 ++loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000 ++loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000 ++loadaddr-$(CONFIG_MACH_MACKEREL) += 0x40008000 ++loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000 ++loadaddr-$(CONFIG_MACH_MARZEN_REFERENCE) += 0x60008000 + ++__ZRELADDR := $(sort $(loadaddr-y)) + zreladdr-y += $(__ZRELADDR) + + # Unsupported legacy stuff +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0272-ARM-shmobile-Let-romImage-rely-on-default-ATAGS.patch b/patches.renesas/0272-ARM-shmobile-Let-romImage-rely-on-default-ATAGS.patch new file mode 100644 index 00000000000..3a44d64629b --- /dev/null +++ b/patches.renesas/0272-ARM-shmobile-Let-romImage-rely-on-default-ATAGS.patch @@ -0,0 +1,54 @@ +From e5f6a39d6ab4ca10e5ccd94194e510df02d6d07a Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Wed, 5 Jun 2013 07:55:22 +0000 +Subject: ARM: shmobile: Let romImage rely on default ATAGS + +Remove the ATAGS data structure from head-shmobile.S +since a default ATAGS is already provided by the code +in arch/arm/kernel/atags_parser.c. Passing a NULL as +ATAGS is valid. For actual hardware specific setup +the fixup callback in the board code may be used. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 2a58009599ff0d2bdbe7e3a9a11a0d838868634d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/compressed/head-shmobile.S | 19 +------------------ + 1 file changed, 1 insertion(+), 18 deletions(-) + +diff --git a/arch/arm/boot/compressed/head-shmobile.S b/arch/arm/boot/compressed/head-shmobile.S +index fe3719b5..19b23044 100644 +--- a/arch/arm/boot/compressed/head-shmobile.S ++++ b/arch/arm/boot/compressed/head-shmobile.S +@@ -55,26 +55,9 @@ __tmp_stack: + __continue: + #endif /* CONFIG_ZBOOT_ROM_MMC || CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI */ + +- b 1f +-__atags:@ tag #1 +- .long 12 @ tag->hdr.size = tag_size(tag_core); +- .long 0x54410001 @ tag->hdr.tag = ATAG_CORE; +- .long 0 @ tag->u.core.flags = 0; +- .long 0 @ tag->u.core.pagesize = 0; +- .long 0 @ tag->u.core.rootdev = 0; +- @ tag #2 +- .long 8 @ tag->hdr.size = tag_size(tag_mem32); +- .long 0x54410002 @ tag->hdr.tag = ATAG_MEM; +- .long CONFIG_MEMORY_SIZE @ tag->u.mem.size = CONFIG_MEMORY_SIZE; +- .long CONFIG_MEMORY_START @ @ tag->u.mem.start = CONFIG_MEMORY_START; +- @ tag #3 +- .long 0 @ tag->hdr.size = 0 +- .long 0 @ tag->hdr.tag = ATAG_NONE; +-1: +- + /* Set board ID necessary for boot */ + ldr r7, 1f @ Set machine type register +- adr r8, __atags @ Set atag register ++ mov r8, #0 @ pass null pointer as atag + b 2f + + 1 : .long MACH_TYPE +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0273-ARM-shmobile-Remove-romImage-CONFIG_MEMORY_START.patch b/patches.renesas/0273-ARM-shmobile-Remove-romImage-CONFIG_MEMORY_START.patch new file mode 100644 index 00000000000..f4eb830014f --- /dev/null +++ b/patches.renesas/0273-ARM-shmobile-Remove-romImage-CONFIG_MEMORY_START.patch @@ -0,0 +1,53 @@ +From f7975d4974b4843db8f2f8ba93667e88dd20671d Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Wed, 5 Jun 2013 16:55:31 +0900 +Subject: ARM: shmobile: Remove romImage CONFIG_MEMORY_START + +Instead of relying on CONFIG_MEMORY_START for memory +base address, let each romImage board header file +specify this information. + +This is reworks code not to rely on CONFIG_MEMORY_START +which in turn is needed for ARCH_MULTIPLATFORM. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 4f309d272f7139278f52cf1e2dcf5b2bc8c029d9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/compressed/head-shmobile.S | 2 +- + arch/arm/mach-shmobile/include/mach/zboot.h | 2 ++ + 2 files changed, 3 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/boot/compressed/head-shmobile.S b/arch/arm/boot/compressed/head-shmobile.S +index 19b23044..e2d63633 100644 +--- a/arch/arm/boot/compressed/head-shmobile.S ++++ b/arch/arm/boot/compressed/head-shmobile.S +@@ -46,7 +46,7 @@ __image_start: + __image_end: + .long _got_end + __load_base: +- .long CONFIG_MEMORY_START + 0x02000000 @ Load at 32Mb into SDRAM ++ .long MEMORY_START + 0x02000000 @ Load at 32Mb into SDRAM + __loaded: + .long __continue + .align +diff --git a/arch/arm/mach-shmobile/include/mach/zboot.h b/arch/arm/mach-shmobile/include/mach/zboot.h +index 9320aff0..308b5cfd 100644 +--- a/arch/arm/mach-shmobile/include/mach/zboot.h ++++ b/arch/arm/mach-shmobile/include/mach/zboot.h +@@ -12,9 +12,11 @@ + + #ifdef CONFIG_MACH_AP4EVB + #define MACH_TYPE MACH_TYPE_AP4EVB ++#define MEMORY_START 0x40000000 + #include "mach/head-ap4evb.txt" + #elif defined(CONFIG_MACH_MACKEREL) + #define MACH_TYPE MACH_TYPE_MACKEREL ++#define MEMORY_START 0x40000000 + #include "mach/head-mackerel.txt" + #else + #error "unsupported board." +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0274-ARM-shmobile-r8a73a4-add-clock-definitions-and-alias.patch b/patches.renesas/0274-ARM-shmobile-r8a73a4-add-clock-definitions-and-alias.patch new file mode 100644 index 00000000000..e71394169dd --- /dev/null +++ b/patches.renesas/0274-ARM-shmobile-r8a73a4-add-clock-definitions-and-alias.patch @@ -0,0 +1,81 @@ +From ce39c40bb28931df161c2eec1833e92ea0f666b5 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Fri, 17 May 2013 16:55:14 +0200 +Subject: ARM: shmobile: r8a73a4: add clock definitions and aliases for MMCIF + and SDHI + +Add MSTP clock definitions and fix aliases for the two MMCIF and three SDHI +interfaces on r8a73a4 (APE6). + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 111fad56a8e6b0478a5156a82f5f3709150f93a9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a73a4.c | 22 +++++++++++++++++----- + 1 file changed, 17 insertions(+), 5 deletions(-) + +diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c +index f6227bb1..5f7fe628 100644 +--- a/arch/arm/mach-shmobile/clock-r8a73a4.c ++++ b/arch/arm/mach-shmobile/clock-r8a73a4.c +@@ -29,6 +29,7 @@ + #define CPG_LEN 0x270 + + #define SMSTPCR2 0xe6150138 ++#define SMSTPCR3 0xe615013c + #define SMSTPCR5 0xe6150144 + + #define FRQCRA 0xE6150000 +@@ -348,6 +349,7 @@ static struct clk div6_clks[DIV6_NR] = { + /* MSTP */ + enum { + MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, ++ MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, + MSTP522, + MSTP_NR + }; +@@ -359,6 +361,11 @@ static struct clk mstp_clks[MSTP_NR] = { + [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 7, 0), /* SCIFB1 */ + [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 16, 0), /* SCIFB2 */ + [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 17, 0), /* SCIFB3 */ ++ [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */ ++ [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */ ++ [MSTP313] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI1],SMSTPCR3, 13, 0), /* SDHI1 */ ++ [MSTP314] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI0],SMSTPCR3, 14, 0), /* SDHI0 */ ++ [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0],SMSTPCR3, 15, 0), /* MMCIF0 */ + [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */ + }; + +@@ -381,11 +388,6 @@ static struct clk_lookup lookups[] = { + + /* DIV6 */ + CLKDEV_CON_ID("zb", &div6_clks[DIV6_ZB]), +- CLKDEV_CON_ID("sdhi0", &div6_clks[DIV6_SDHI0]), +- CLKDEV_CON_ID("sdhi1", &div6_clks[DIV6_SDHI1]), +- CLKDEV_CON_ID("sdhi2", &div6_clks[DIV6_SDHI2]), +- CLKDEV_CON_ID("mmc0", &div6_clks[DIV6_MMC0]), +- CLKDEV_CON_ID("mmc1", &div6_clks[DIV6_MMC1]), + CLKDEV_CON_ID("vck1", &div6_clks[DIV6_VCK1]), + CLKDEV_CON_ID("vck2", &div6_clks[DIV6_VCK2]), + CLKDEV_CON_ID("vck3", &div6_clks[DIV6_VCK3]), +@@ -406,6 +408,16 @@ static struct clk_lookup lookups[] = { + CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), + CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]), + CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), ++ CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), ++ CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]), ++ CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]), ++ CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP312]), ++ CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), ++ CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]), ++ CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), ++ CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), ++ CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), ++ CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), + + /* for DT */ + CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0275-ARM-shmobile-r8a7790-add-clock-definitions-and-alias.patch b/patches.renesas/0275-ARM-shmobile-r8a7790-add-clock-definitions-and-alias.patch new file mode 100644 index 00000000000..886ce6ae8a4 --- /dev/null +++ b/patches.renesas/0275-ARM-shmobile-r8a7790-add-clock-definitions-and-alias.patch @@ -0,0 +1,82 @@ +From 7d039a5c0a9ec6094a5371f29bf23ee5a4cac1b4 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Fri, 17 May 2013 16:55:15 +0200 +Subject: ARM: shmobile: r8a7790: add clock definitions and aliases for MMCIF + and SDHI + +Add MSTP clock definitions and fix aliases for the two MMCIF and four SDHI +interfaces on r8a7790 (H2). + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +[horms+renesas@verge.net.au: applied manually] +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit 018222f5d32bc5ca9fd830aebfeed10f1be96c93) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a7790.c | 26 +++++++++++++++++++------- + 1 file changed, 19 insertions(+), 7 deletions(-) + +diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c +index 379bce69..5d71313d 100644 +--- a/arch/arm/mach-shmobile/clock-r8a7790.c ++++ b/arch/arm/mach-shmobile/clock-r8a7790.c +@@ -182,7 +182,7 @@ static struct clk div6_clks[DIV6_NR] = { + enum { + MSTP721, MSTP720, + MSTP717, MSTP716, +- MSTP304, ++ MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304, + MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, + MSTP_NR + }; +@@ -190,6 +190,12 @@ enum { + static struct clk mstp_clks[MSTP_NR] = { + [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ + [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ ++ [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */ ++ [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */ ++ [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_SD1], SMSTPCR3, 13, 0), /* SDHI1 */ ++ [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SD2], SMSTPCR3, 12, 0), /* SDHI2 */ ++ [MSTP311] = SH_CLK_MSTP32(&div6_clks[DIV6_SD3], SMSTPCR3, 11, 0), /* SDHI3 */ ++ [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1], SMSTPCR3, 5, 0), /* MMC1 */ + [MSTP304] = SH_CLK_MSTP32(&cp_clk, SMSTPCR3, 4, 0), /* TPU0 */ + [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ + [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ +@@ -232,14 +238,8 @@ static struct clk_lookup lookups[] = { + + /* DIV4 */ + CLKDEV_CON_ID("sdh", &div4_clks[DIV4_SDH]), +- CLKDEV_CON_ID("sd0", &div4_clks[DIV4_SD0]), +- CLKDEV_CON_ID("sd1", &div4_clks[DIV4_SD1]), + + /* DIV6 */ +- CLKDEV_CON_ID("sd2", &div6_clks[DIV6_SD2]), +- CLKDEV_CON_ID("sd3", &div6_clks[DIV6_SD3]), +- CLKDEV_CON_ID("mmc0", &div6_clks[DIV6_MMC0]), +- CLKDEV_CON_ID("mmc1", &div6_clks[DIV6_MMC1]), + CLKDEV_CON_ID("ssp", &div6_clks[DIV6_SSP]), + CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]), + +@@ -254,6 +254,18 @@ static struct clk_lookup lookups[] = { + CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), + CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]), + CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]), ++ CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), ++ CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), ++ CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), ++ CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), ++ CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]), ++ CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), ++ CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP312]), ++ CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]), ++ CLKDEV_DEV_ID("ee160000.sdhi", &mstp_clks[MSTP311]), ++ CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]), ++ CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]), ++ CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), + }; + + #define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0276-ARM-shmobile-BOCK-W-add-Ether-support.patch b/patches.renesas/0276-ARM-shmobile-BOCK-W-add-Ether-support.patch new file mode 100644 index 00000000000..b20cd6f0c0c --- /dev/null +++ b/patches.renesas/0276-ARM-shmobile-BOCK-W-add-Ether-support.patch @@ -0,0 +1,64 @@ +From 983c8cb217db342c8a2a4fac3bf266baf29baced Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Sun, 2 Jun 2013 02:40:55 +0400 +Subject: ARM: shmobile: BOCK-W: add Ether support + +Register Ether device from bockw_init(), passing the platform data to it, adding +only the RMII pin group to bockw_pinctrl_map[]. Although the LINK signal exists +on the board, it's connected to the link/activity LED output of the PHY, thus +the link disappears and reappears after each packet. We'd be better off ignoring +such signal and getting the link state from the PHY indirectly. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +[horms+renesas@verge.net.au: manually applied] +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit 9aa3853a6f6652901f7ae42ed6bfd85a11bdc795) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + arch/arm/mach-shmobile/board-bockw.c +--- + arch/arm/mach-shmobile/board-bockw.c | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c +index f6ca2ae2..ce0fa38e 100644 +--- a/arch/arm/mach-shmobile/board-bockw.c ++++ b/arch/arm/mach-shmobile/board-bockw.c +@@ -65,7 +65,24 @@ static struct sh_mobile_sdhi_info sdhi0_info = { + .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT, + }; + ++static struct sh_eth_plat_data ether_platform_data __initdata = { ++ .phy = 0x01, ++ .edmac_endian = EDMAC_LITTLE_ENDIAN, ++ .register_type = SH_ETH_REG_FAST_RCAR, ++ .phy_interface = PHY_INTERFACE_MODE_RMII, ++ /* ++ * Although the LINK signal is available on the board, it's connected to ++ * the link/activity LED output of the PHY, thus the link disappears and ++ * reappears after each packet. We'd be better off ignoring such signal ++ * and getting the link state from the PHY indirectly. ++ */ ++ .no_ether_link = 1, ++}; ++ + static const struct pinctrl_map bockw_pinctrl_map[] = { ++ /* Ether */ ++ PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7778", ++ "ether_rmii", "ether"), + /* SCIF0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778", + "scif0_data_a", "scif0"), +@@ -92,6 +109,7 @@ static void __init bockw_init(void) + r8a7778_init_irq_extpin(1); + r8a7778_add_standard_devices(); + r8a7778_add_usb_phy_device(&usb_phy_platform_data); ++ r8a7778_add_ether_device(ðer_platform_data); + + pinctrl_register_mappings(bockw_pinctrl_map, + ARRAY_SIZE(bockw_pinctrl_map)); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0277-ARM-shmobile-bockw-add-I2C-device-support.patch b/patches.renesas/0277-ARM-shmobile-bockw-add-I2C-device-support.patch new file mode 100644 index 00000000000..07671b34d76 --- /dev/null +++ b/patches.renesas/0277-ARM-shmobile-bockw-add-I2C-device-support.patch @@ -0,0 +1,48 @@ +From f9cae32696beeb1f7df8d068239cdc74b9426053 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 11 Jun 2013 19:11:17 -0700 +Subject: ARM: shmobile: bockw: add I2C device support + +This patch enables rx8581 on I2C0 + +Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com> +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit ed17be92c00fde00b2431b31828736f8572d7ba7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-bockw.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c +index ce0fa38e..e1a988c4 100644 +--- a/arch/arm/mach-shmobile/board-bockw.c ++++ b/arch/arm/mach-shmobile/board-bockw.c +@@ -79,6 +79,13 @@ static struct sh_eth_plat_data ether_platform_data __initdata = { + .no_ether_link = 1, + }; + ++/* I2C */ ++static struct i2c_board_info i2c0_devices[] = { ++ { ++ I2C_BOARD_INFO("rx8581", 0x51), ++ }, ++}; ++ + static const struct pinctrl_map bockw_pinctrl_map[] = { + /* Ether */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7778", +@@ -110,7 +117,10 @@ static void __init bockw_init(void) + r8a7778_add_standard_devices(); + r8a7778_add_usb_phy_device(&usb_phy_platform_data); + r8a7778_add_ether_device(ðer_platform_data); ++ r8a7778_add_i2c_device(0); + ++ i2c_register_board_info(0, i2c0_devices, ++ ARRAY_SIZE(i2c0_devices)); + pinctrl_register_mappings(bockw_pinctrl_map, + ARRAY_SIZE(bockw_pinctrl_map)); + r8a7778_pinmux_init(); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0278-ARM-shmobile-bockw-add-SPI-FLASH-support.patch b/patches.renesas/0278-ARM-shmobile-bockw-add-SPI-FLASH-support.patch new file mode 100644 index 00000000000..ff0202522c4 --- /dev/null +++ b/patches.renesas/0278-ARM-shmobile-bockw-add-SPI-FLASH-support.patch @@ -0,0 +1,92 @@ +From 4e13b5b91f019b4b592a99a1e12a18b65749b7a7 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 11 Jun 2013 19:11:41 -0700 +Subject: ARM: shmobile: bockw: add SPI FLASH support + +This patch enables Spansion S25FL008K chip on HSPI0 + +Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com> +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit c06a164ce2f0f8791ac566a44eaf1d227a5b6b5b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-bockw.c | 36 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 36 insertions(+) + +diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c +index e1a988c4..d203b3eb 100644 +--- a/arch/arm/mach-shmobile/board-bockw.c ++++ b/arch/arm/mach-shmobile/board-bockw.c +@@ -20,11 +20,14 @@ + + #include <linux/mfd/tmio.h> + #include <linux/mmc/host.h> ++#include <linux/mtd/partitions.h> + #include <linux/pinctrl/machine.h> + #include <linux/platform_device.h> + #include <linux/regulator/fixed.h> + #include <linux/regulator/machine.h> + #include <linux/smsc911x.h> ++#include <linux/spi/spi.h> ++#include <linux/spi/flash.h> + #include <mach/common.h> + #include <mach/irqs.h> + #include <mach/r8a7778.h> +@@ -86,10 +89,40 @@ static struct i2c_board_info i2c0_devices[] = { + }, + }; + ++/* HSPI*/ ++static struct mtd_partition m25p80_spi_flash_partitions[] = { ++ { ++ .name = "data(spi)", ++ .size = 0x0100000, ++ .offset = 0, ++ }, ++}; ++ ++static struct flash_platform_data spi_flash_data = { ++ .name = "m25p80", ++ .type = "s25fl008k", ++ .parts = m25p80_spi_flash_partitions, ++ .nr_parts = ARRAY_SIZE(m25p80_spi_flash_partitions), ++}; ++ ++static struct spi_board_info spi_board_info[] __initdata = { ++ { ++ .modalias = "m25p80", ++ .max_speed_hz = 104000000, ++ .chip_select = 0, ++ .bus_num = 0, ++ .mode = SPI_MODE_0, ++ .platform_data = &spi_flash_data, ++ }, ++}; ++ + static const struct pinctrl_map bockw_pinctrl_map[] = { + /* Ether */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7778", + "ether_rmii", "ether"), ++ /* HSPI0 */ ++ PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7778", ++ "hspi0_a", "hspi0"), + /* SCIF0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778", + "scif0_data_a", "scif0"), +@@ -118,9 +151,12 @@ static void __init bockw_init(void) + r8a7778_add_usb_phy_device(&usb_phy_platform_data); + r8a7778_add_ether_device(ðer_platform_data); + r8a7778_add_i2c_device(0); ++ r8a7778_add_hspi_device(0); + + i2c_register_board_info(0, i2c0_devices, + ARRAY_SIZE(i2c0_devices)); ++ spi_register_board_info(spi_board_info, ++ ARRAY_SIZE(spi_board_info)); + pinctrl_register_mappings(bockw_pinctrl_map, + ARRAY_SIZE(bockw_pinctrl_map)); + r8a7778_pinmux_init(); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0279-ARM-shmobile-bockw-add-MMCIF-support.patch b/patches.renesas/0279-ARM-shmobile-bockw-add-MMCIF-support.patch new file mode 100644 index 00000000000..b29a7098cc5 --- /dev/null +++ b/patches.renesas/0279-ARM-shmobile-bockw-add-MMCIF-support.patch @@ -0,0 +1,83 @@ +From 97cff3a9ba3329071f0f59ad8a58e02d31362d8f Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 11 Jun 2013 19:12:06 -0700 +Subject: ARM: shmobile: bockw: add MMCIF support + +This patch enables CN26 MMCIF + +Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com> +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 1e0edb76e925927d396be60e22f9c5ab815f2ab0) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-bockw.c | 32 ++++++++++++++++++++++++++++++++ + 1 file changed, 32 insertions(+) + +diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c +index d203b3eb..394186c7 100644 +--- a/arch/arm/mach-shmobile/board-bockw.c ++++ b/arch/arm/mach-shmobile/board-bockw.c +@@ -41,6 +41,23 @@ + * SW41 SCIF RCAN + */ + ++/* ++ * MMC (CN26) pin ++ * ++ * SW6 (D2) 3 pin ++ * SW7 (D5) ON ++ * SW8 (D3) 3 pin ++ * SW10 (D4) 1 pin ++ * SW12 (CLK) 1 pin ++ * SW13 (D6) 3 pin ++ * SW14 (CMD) ON ++ * SW15 (D6) 1 pin ++ * SW16 (D0) ON ++ * SW17 (D1) ON ++ * SW18 (D7) 3 pin ++ * SW19 (MMC) 1 pin ++ */ ++ + /* Dummy supplies, where voltage doesn't matter */ + static struct regulator_consumer_supply dummy_supplies[] = { + REGULATOR_SUPPLY("vddvario", "smsc911x"), +@@ -116,6 +133,15 @@ static struct spi_board_info spi_board_info[] __initdata = { + }, + }; + ++/* MMC */ ++static struct sh_mmcif_plat_data sh_mmcif_plat = { ++ .sup_pclk = 0, ++ .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, ++ .caps = MMC_CAP_4_BIT_DATA | ++ MMC_CAP_8_BIT_DATA | ++ MMC_CAP_NEEDS_POLL, ++}; ++ + static const struct pinctrl_map bockw_pinctrl_map[] = { + /* Ether */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7778", +@@ -123,6 +149,11 @@ static const struct pinctrl_map bockw_pinctrl_map[] = { + /* HSPI0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7778", + "hspi0_a", "hspi0"), ++ /* MMC */ ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif", "pfc-r8a7778", ++ "mmc_data8", "mmc"), ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif", "pfc-r8a7778", ++ "mmc_ctrl", "mmc"), + /* SCIF0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778", + "scif0_data_a", "scif0"), +@@ -152,6 +183,7 @@ static void __init bockw_init(void) + r8a7778_add_ether_device(ðer_platform_data); + r8a7778_add_i2c_device(0); + r8a7778_add_hspi_device(0); ++ r8a7778_add_mmc_device(&sh_mmcif_plat); + + i2c_register_board_info(0, i2c0_devices, + ARRAY_SIZE(i2c0_devices)); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0280-ARM-shmobile-r8a7790-add-__initdata-on-resource-and-.patch b/patches.renesas/0280-ARM-shmobile-r8a7790-add-__initdata-on-resource-and-.patch new file mode 100644 index 00000000000..487519b877b --- /dev/null +++ b/patches.renesas/0280-ARM-shmobile-r8a7790-add-__initdata-on-resource-and-.patch @@ -0,0 +1,69 @@ +From aa390bb0217548342ce6262e2d0e6c11a73360a5 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 12 Jun 2013 02:03:59 +0000 +Subject: ARM: shmobile: r8a7790: add __initdata on resource and device data + +These data will be kmemdup()'ed on +platform_device_add_resources() and platform_device_add_data() +This patch removed "const" to avoid section type conflict +with r8a7790_boards_compat_dt + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit f9094c526bca3cc50ef7d409c22976fa0f47bbba) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a7790.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c +index b461d934..196bd732 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7790.c ++++ b/arch/arm/mach-shmobile/setup-r8a7790.c +@@ -30,17 +30,17 @@ + #include <mach/r8a7790.h> + #include <asm/mach/arch.h> + +-static const struct resource pfc_resources[] = { ++static struct resource pfc_resources[] __initdata = { + DEFINE_RES_MEM(0xe6060000, 0x250), + }; + + #define R8A7790_GPIO(idx) \ +-static struct resource r8a7790_gpio##idx##_resources[] = { \ ++static struct resource r8a7790_gpio##idx##_resources[] __initdata = { \ + DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50), \ + DEFINE_RES_IRQ(gic_spi(4 + (idx))), \ + }; \ + \ +-static struct gpio_rcar_config r8a7790_gpio##idx##_platform_data = { \ ++static struct gpio_rcar_config r8a7790_gpio##idx##_platform_data __initdata = { \ + .gpio_base = 32 * (idx), \ + .irq_base = 0, \ + .number_of_pins = 32, \ +@@ -103,7 +103,7 @@ void __init r8a7790_pinmux_init(void) + + enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1 }; + +-static const struct plat_sci_port scif[] = { ++static struct plat_sci_port scif[] __initdata = { + SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ + SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ + SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ +@@ -120,11 +120,11 @@ static inline void r8a7790_register_scif(int idx) + sizeof(struct plat_sci_port)); + } + +-static struct renesas_irqc_config irqc0_data = { ++static struct renesas_irqc_config irqc0_data __initdata = { + .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ + }; + +-static struct resource irqc0_resources[] = { ++static struct resource irqc0_resources[] __initdata = { + DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */ + DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */ + DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0281-pinctrl-r8a7790-fix-two-pin-numbers.patch b/patches.renesas/0281-pinctrl-r8a7790-fix-two-pin-numbers.patch new file mode 100644 index 00000000000..8f8da114c43 --- /dev/null +++ b/patches.renesas/0281-pinctrl-r8a7790-fix-two-pin-numbers.patch @@ -0,0 +1,88 @@ +From ffc02e84d24bdfd312a4ee970f7e0080f20182ed Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Tue, 11 Jun 2013 11:42:17 +0000 +Subject: pinctrl: r8a7790: fix two pin numbers + +Fix two erroneous MMCIF1 pin numbers on r8a7790. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 0a6ea54ff0fd1ac72223af44939fcd7197537b14) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 16 +++++++--------- + 1 file changed, 7 insertions(+), 9 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +index 1e7a5eb7..14f3ec26 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -2506,8 +2506,7 @@ static const unsigned int tpu0_to3_pins[] = { + static const unsigned int tpu0_to3_mux[] = { + TPU0TO3_MARK, + }; +- +-/* - MMCIF ------------------------------------------------------------------ */ ++/* - MMCIF0 ----------------------------------------------------------------- */ + static const unsigned int mmc0_data1_pins[] = { + /* D[0] */ + RCAR_GP_PIN(3, 18), +@@ -2541,7 +2540,7 @@ static const unsigned int mmc0_ctrl_pins[] = { + static const unsigned int mmc0_ctrl_mux[] = { + MMC0_CLK_MARK, MMC0_CMD_MARK, + }; +- ++/* - MMCIF1 ----------------------------------------------------------------- */ + static const unsigned int mmc1_data1_pins[] = { + /* D[0] */ + RCAR_GP_PIN(3, 26), +@@ -2562,7 +2561,7 @@ static const unsigned int mmc1_data8_pins[] = { + RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), + RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), + RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), +- RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), ++ RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), + }; + static const unsigned int mmc1_data8_mux[] = { + MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, +@@ -2575,8 +2574,7 @@ static const unsigned int mmc1_ctrl_pins[] = { + static const unsigned int mmc1_ctrl_mux[] = { + MMC1_CLK_MARK, MMC1_CMD_MARK, + }; +- +-/* - SDHI ------------------------------------------------------------------- */ ++/* - SDHI0 ------------------------------------------------------------------ */ + static const unsigned int sdhi0_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 2), +@@ -2612,7 +2610,7 @@ static const unsigned int sdhi0_wp_pins[] = { + static const unsigned int sdhi0_wp_mux[] = { + SD0_WP_MARK, + }; +- ++/* - SDHI1 ------------------------------------------------------------------ */ + static const unsigned int sdhi1_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 10), +@@ -2648,7 +2646,7 @@ static const unsigned int sdhi1_wp_pins[] = { + static const unsigned int sdhi1_wp_mux[] = { + SD1_WP_MARK, + }; +- ++/* - SDHI2 ------------------------------------------------------------------ */ + static const unsigned int sdhi2_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 18), +@@ -2684,7 +2682,7 @@ static const unsigned int sdhi2_wp_pins[] = { + static const unsigned int sdhi2_wp_mux[] = { + SD2_WP_MARK, + }; +- ++/* - SDHI3 ------------------------------------------------------------------ */ + static const unsigned int sdhi3_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 26), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0282-ARM-shmobile-Rework-sh7372-sleep-code-to-use-virt_to.patch b/patches.renesas/0282-ARM-shmobile-Rework-sh7372-sleep-code-to-use-virt_to.patch new file mode 100644 index 00000000000..c1ce993259d --- /dev/null +++ b/patches.renesas/0282-ARM-shmobile-Rework-sh7372-sleep-code-to-use-virt_to.patch @@ -0,0 +1,71 @@ +From 9e96bc6dc48ddebf53bb7caa91803db0c12a3f56 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Wed, 5 Jun 2013 16:45:53 +0900 +Subject: ARM: shmobile: Rework sh7372 sleep code to use virt_to_phys() + +Instead of having a hard coded virt-to-phys address +conversion code in sleep-sh7372.S, rework the code +to do the conversion in C using virt_to_phys(). + +This removes the need for PLAT_PHYS_OFFSET which +in turn is needed for ARCH_MULTIPLATFORM. + +Signed-off-by: Magnus Damm <damm@opensource.se> +[horms+renesas@verge.net.au: squashed in build fix posted as + "ARM: shmobile: sh7372 build fix for SUSPEND=n && CPU_IDLE=n"] +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit e26f4067405872b5d8b9efea9fc48cda97e39fc2) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/include/mach/sh7372.h | 2 ++ + arch/arm/mach-shmobile/pm-sh7372.c | 3 +++ + arch/arm/mach-shmobile/sleep-sh7372.S | 5 ++++- + 3 files changed, 9 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h +index e882717c..854a9f0c 100644 +--- a/arch/arm/mach-shmobile/include/mach/sh7372.h ++++ b/arch/arm/mach-shmobile/include/mach/sh7372.h +@@ -75,6 +75,8 @@ extern void sh7372_intcs_resume(void); + extern void sh7372_intca_suspend(void); + extern void sh7372_intca_resume(void); + ++extern unsigned long sh7372_cpu_resume; ++ + #ifdef CONFIG_PM + extern void __init sh7372_init_pm_domains(void); + #else +diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c +index dec9293b..0de75fd3 100644 +--- a/arch/arm/mach-shmobile/pm-sh7372.c ++++ b/arch/arm/mach-shmobile/pm-sh7372.c +@@ -351,6 +351,9 @@ static void sh7372_enter_a4s_common(int pllc0_on) + + static void sh7372_pm_setup_smfram(void) + { ++ /* pass physical address of cpu_resume() to assembly resume code */ ++ sh7372_cpu_resume = virt_to_phys(cpu_resume); ++ + memcpy((void *)SMFRAM, sh7372_resume_core_standby_sysc, 0x100); + } + #else +diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S +index a9df53b6..53f4840e 100644 +--- a/arch/arm/mach-shmobile/sleep-sh7372.S ++++ b/arch/arm/mach-shmobile/sleep-sh7372.S +@@ -40,7 +40,10 @@ + .global sh7372_resume_core_standby_sysc + sh7372_resume_core_standby_sysc: + ldr pc, 1f +-1: .long cpu_resume - PAGE_OFFSET + PLAT_PHYS_OFFSET ++ ++ .globl sh7372_cpu_resume ++sh7372_cpu_resume: ++1: .space 4 + + #define SPDCR 0xe6180008 + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0283-ARM-shmobile-Add-SMP-boot-function-and-argument.patch b/patches.renesas/0283-ARM-shmobile-Add-SMP-boot-function-and-argument.patch new file mode 100644 index 00000000000..a2884bba31c --- /dev/null +++ b/patches.renesas/0283-ARM-shmobile-Add-SMP-boot-function-and-argument.patch @@ -0,0 +1,59 @@ +From aa866793caf5e4bb86465e9bc7d9b59aef2895b0 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Mon, 10 Jun 2013 18:19:36 +0900 +Subject: ARM: shmobile: Add SMP boot function and argument + +Add code for mach-shmobile to allow specifying boot function +and argument. Will initially be used for SMP together with SCU +but may in the future also be used for deep sleep resume. This +patch removes one inline virtual to physical address conversion. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit ebe72ab90a5c1e3b69d89b841552fd02805dc4e4) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/headsmp.S | 13 ++++++++++--- + arch/arm/mach-shmobile/include/mach/common.h | 4 +++- + 2 files changed, 13 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S +index 96001fd4..559d1ce5 100644 +--- a/arch/arm/mach-shmobile/headsmp.S ++++ b/arch/arm/mach-shmobile/headsmp.S +@@ -27,7 +27,14 @@ ENDPROC(shmobile_invalidate_start) + * We need _long_ jump to the physical address. + */ + .align 12 +-ENTRY(shmobile_secondary_vector) ++ENTRY(shmobile_boot_vector) ++ ldr r0, 2f + ldr pc, 1f +-1: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET +-ENDPROC(shmobile_secondary_vector) ++ENDPROC(shmobile_boot_vector) ++ ++ .globl shmobile_boot_fn ++shmobile_boot_fn: ++1: .space 4 ++ .globl shmobile_boot_arg ++shmobile_boot_arg: ++2: .space 4 +diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h +index 4634a5d4..54472ef4 100644 +--- a/arch/arm/mach-shmobile/include/mach/common.h ++++ b/arch/arm/mach-shmobile/include/mach/common.h +@@ -7,7 +7,9 @@ extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz, + unsigned int mult, unsigned int div); + struct twd_local_timer; + extern void shmobile_setup_console(void); +-extern void shmobile_secondary_vector(void); ++extern void shmobile_boot_vector(void); ++extern unsigned long shmobile_boot_fn; ++extern unsigned long shmobile_boot_arg; + extern void shmobile_secondary_vector_scu(void); + struct clk; + extern int shmobile_clk_init(void); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0284-ARM-shmobile-Add-SCU-boot-function-using-argument.patch b/patches.renesas/0284-ARM-shmobile-Add-SCU-boot-function-using-argument.patch new file mode 100644 index 00000000000..1dec62c303e --- /dev/null +++ b/patches.renesas/0284-ARM-shmobile-Add-SCU-boot-function-using-argument.patch @@ -0,0 +1,57 @@ +From a4c75658f0d437a1aceff0d1bdc4d84b1b2a223f Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Mon, 10 Jun 2013 18:19:46 +0900 +Subject: ARM: shmobile: Add SCU boot function using argument + +Add a shmoible_boot_scu function that assumes that the base address +of the SCU is passed in r0. This code is free from inline virtual +to physical address conversion. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit bfabbcc679e86cfcaf0e7fd41563f14c29bc74d4) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/headsmp-scu.S | 13 +++++++++++++ + arch/arm/mach-shmobile/include/mach/common.h | 1 + + 2 files changed, 14 insertions(+) + +diff --git a/arch/arm/mach-shmobile/headsmp-scu.S b/arch/arm/mach-shmobile/headsmp-scu.S +index 7d113f89..c5c9106b 100644 +--- a/arch/arm/mach-shmobile/headsmp-scu.S ++++ b/arch/arm/mach-shmobile/headsmp-scu.S +@@ -51,6 +51,19 @@ ENTRY(shmobile_secondary_vector_scu) + 2: .long shmobile_scu_base - PAGE_OFFSET + PLAT_PHYS_OFFSET + ENDPROC(shmobile_secondary_vector_scu) + ++ENTRY(shmobile_boot_scu) ++ @ r0 = SCU base address ++ mrc p15, 0, r1, c0, c0, 5 @ read MIPDR ++ and r1, r1, #3 @ mask out cpu ID ++ lsl r1, r1, #3 @ we will shift by cpu_id * 8 bits ++ ldr r2, [r0, #8] @ SCU Power Status Register ++ mov r3, #3 ++ bic r2, r2, r3, lsl r1 @ Clear bits of our CPU (Run Mode) ++ str r2, [r0, #8] @ write back ++ ++ b shmobile_invalidate_start ++ENDPROC(shmobile_boot_scu) ++ + .text + .globl shmobile_scu_base + shmobile_scu_base: +diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h +index 54472ef4..8ef1c3c1 100644 +--- a/arch/arm/mach-shmobile/include/mach/common.h ++++ b/arch/arm/mach-shmobile/include/mach/common.h +@@ -11,6 +11,7 @@ extern void shmobile_boot_vector(void); + extern unsigned long shmobile_boot_fn; + extern unsigned long shmobile_boot_arg; + extern void shmobile_secondary_vector_scu(void); ++extern void shmobile_boot_scu(void); + struct clk; + extern int shmobile_clk_init(void); + extern void shmobile_handle_irq_intc(struct pt_regs *); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0285-ARM-shmobile-r8a7779-SMP-with-SCU-boot-fn-and-args.patch b/patches.renesas/0285-ARM-shmobile-r8a7779-SMP-with-SCU-boot-fn-and-args.patch new file mode 100644 index 00000000000..48d6fa00276 --- /dev/null +++ b/patches.renesas/0285-ARM-shmobile-r8a7779-SMP-with-SCU-boot-fn-and-args.patch @@ -0,0 +1,36 @@ +From 4f79397850fc1b78d64032c97447572f22e169ce Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Mon, 10 Jun 2013 18:19:56 +0900 +Subject: ARM: shmobile: r8a7779 SMP with SCU boot fn and args + +Let r8a7779 make use of shmobile_boot_fn and shmobile_boot_arg +together with shmobile_boot_scu and the SCU base address. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit af642310aaa491df6dabcca96bdf0d1b8465a834) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/smp-r8a7779.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c +index a853bf18..526cfaae 100644 +--- a/arch/arm/mach-shmobile/smp-r8a7779.c ++++ b/arch/arm/mach-shmobile/smp-r8a7779.c +@@ -101,8 +101,10 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) + { + scu_enable(shmobile_scu_base); + +- /* Map the reset vector (in headsmp-scu.S) */ +- __raw_writel(__pa(shmobile_secondary_vector_scu), AVECR); ++ /* Map the reset vector (in headsmp-scu.S, headsmp.S) */ ++ __raw_writel(__pa(shmobile_boot_vector), AVECR); ++ shmobile_boot_fn = virt_to_phys(shmobile_boot_scu); ++ shmobile_boot_arg = (unsigned long)shmobile_scu_base; + + /* enable cache coherency on booting CPU */ + scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0286-ARM-shmobile-sh73a0-SMP-with-SCU-boot-fn-and-args.patch b/patches.renesas/0286-ARM-shmobile-sh73a0-SMP-with-SCU-boot-fn-and-args.patch new file mode 100644 index 00000000000..4663265ed38 --- /dev/null +++ b/patches.renesas/0286-ARM-shmobile-sh73a0-SMP-with-SCU-boot-fn-and-args.patch @@ -0,0 +1,37 @@ +From 8d8a82599d2add7de68eecf9431cd04623c45f18 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Mon, 10 Jun 2013 18:20:06 +0900 +Subject: ARM: shmobile: sh73a0 SMP with SCU boot fn and args + +Let sh73a0 make use of shmobile_boot_fn and shmobile_boot_arg +together with shmobile_boot_scu and the SCU base address. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit abfa04eb12d34941e7c227e0e205a2075f9c52d5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/smp-sh73a0.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c +index 496592b6..d613113a 100644 +--- a/arch/arm/mach-shmobile/smp-sh73a0.c ++++ b/arch/arm/mach-shmobile/smp-sh73a0.c +@@ -64,9 +64,11 @@ static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) + { + scu_enable(shmobile_scu_base); + +- /* Map the reset vector (in headsmp-scu.S) */ ++ /* Map the reset vector (in headsmp-scu.S, headsmp.S) */ + __raw_writel(0, APARMBAREA); /* 4k */ +- __raw_writel(__pa(shmobile_secondary_vector_scu), SBAR); ++ __raw_writel(__pa(shmobile_boot_vector), SBAR); ++ shmobile_boot_fn = virt_to_phys(shmobile_boot_scu); ++ shmobile_boot_arg = (unsigned long)shmobile_scu_base; + + /* enable cache coherency on booting CPU */ + scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0287-ARM-shmobile-EMEV2-SMP-with-SCU-boot-fn-and-args.patch b/patches.renesas/0287-ARM-shmobile-EMEV2-SMP-with-SCU-boot-fn-and-args.patch new file mode 100644 index 00000000000..84b9d2bdc59 --- /dev/null +++ b/patches.renesas/0287-ARM-shmobile-EMEV2-SMP-with-SCU-boot-fn-and-args.patch @@ -0,0 +1,36 @@ +From 00d68bd635708b7886d62a3216cc2dc748e3c500 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Mon, 10 Jun 2013 18:20:15 +0900 +Subject: ARM: shmobile: EMEV2 SMP with SCU boot fn and args + +Let EMEV2 make use of shmobile_boot_fn and shmobile_boot_arg +together with shmobile_boot_scu and the SCU base address. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit a188bfcafa61f600877f3e2b4a27cbe42b72c818) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/smp-emev2.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c +index e38691b4..80991b35 100644 +--- a/arch/arm/mach-shmobile/smp-emev2.c ++++ b/arch/arm/mach-shmobile/smp-emev2.c +@@ -40,8 +40,10 @@ static void __init emev2_smp_prepare_cpus(unsigned int max_cpus) + { + scu_enable(shmobile_scu_base); + +- /* Tell ROM loader about our vector (in headsmp-scu.S) */ +- emev2_set_boot_vector(__pa(shmobile_secondary_vector_scu)); ++ /* Tell ROM loader about our vector (in headsmp-scu.S, headsmp.S) */ ++ emev2_set_boot_vector(__pa(shmobile_boot_vector)); ++ shmobile_boot_fn = virt_to_phys(shmobile_boot_scu); ++ shmobile_boot_arg = (unsigned long)shmobile_scu_base; + + /* enable cache coherency on booting CPU */ + scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0288-ARM-shmobile-Remove-old-SCU-boot-code.patch b/patches.renesas/0288-ARM-shmobile-Remove-old-SCU-boot-code.patch new file mode 100644 index 00000000000..4b61cce85d9 --- /dev/null +++ b/patches.renesas/0288-ARM-shmobile-Remove-old-SCU-boot-code.patch @@ -0,0 +1,71 @@ +From 5f7d962a38e805860284b139682b887d9646c9df Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Mon, 10 Jun 2013 18:20:25 +0900 +Subject: ARM: shmobile: Remove old SCU boot code + +Remove shmobile_secondary_vector_scu now when all SCU enabled +SMP platforms instead make use of shmobile_boot_scu. This +removes two inline virtual to physical address conversions. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 4f6da36f7edd57901638df84d1dcbece28831334) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/headsmp-scu.S | 22 +--------------------- + arch/arm/mach-shmobile/include/mach/common.h | 1 - + 2 files changed, 1 insertion(+), 22 deletions(-) + +diff --git a/arch/arm/mach-shmobile/headsmp-scu.S b/arch/arm/mach-shmobile/headsmp-scu.S +index c5c9106b..6f986546 100644 +--- a/arch/arm/mach-shmobile/headsmp-scu.S ++++ b/arch/arm/mach-shmobile/headsmp-scu.S +@@ -25,32 +25,12 @@ + + __CPUINIT + /* +- * Reset vector for secondary CPUs. ++ * Boot code for secondary CPUs. + * + * First we turn on L1 cache coherency for our CPU. Then we jump to + * shmobile_invalidate_start that invalidates the cache and hands over control + * to the common ARM startup code. +- * This function will be mapped to address 0 by the SBAR register. +- * A normal branch is out of range here so we need a long jump. We jump to +- * the physical address as the MMU is still turned off. + */ +- .align 12 +-ENTRY(shmobile_secondary_vector_scu) +- mrc p15, 0, r0, c0, c0, 5 @ read MIPDR +- and r0, r0, #3 @ mask out cpu ID +- lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits +- ldr r1, 2f +- ldr r1, [r1] @ SCU base address +- ldr r2, [r1, #8] @ SCU Power Status Register +- mov r3, #3 +- bic r2, r2, r3, lsl r0 @ Clear bits of our CPU (Run Mode) +- str r2, [r1, #8] @ write back +- +- ldr pc, 1f +-1: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET +-2: .long shmobile_scu_base - PAGE_OFFSET + PLAT_PHYS_OFFSET +-ENDPROC(shmobile_secondary_vector_scu) +- + ENTRY(shmobile_boot_scu) + @ r0 = SCU base address + mrc p15, 0, r1, c0, c0, 5 @ read MIPDR +diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h +index 8ef1c3c1..e818f029 100644 +--- a/arch/arm/mach-shmobile/include/mach/common.h ++++ b/arch/arm/mach-shmobile/include/mach/common.h +@@ -10,7 +10,6 @@ extern void shmobile_setup_console(void); + extern void shmobile_boot_vector(void); + extern unsigned long shmobile_boot_fn; + extern unsigned long shmobile_boot_arg; +-extern void shmobile_secondary_vector_scu(void); + extern void shmobile_boot_scu(void); + struct clk; + extern int shmobile_clk_init(void); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0289-ARM-shmobile-Remove-MEMORY_START-SIZE.patch b/patches.renesas/0289-ARM-shmobile-Remove-MEMORY_START-SIZE.patch new file mode 100644 index 00000000000..cd3e06bb2b5 --- /dev/null +++ b/patches.renesas/0289-ARM-shmobile-Remove-MEMORY_START-SIZE.patch @@ -0,0 +1,65 @@ +From 7e1a6d476600c9bfcce4d9526906c59c9e941f47 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Mon, 10 Jun 2013 18:46:57 +0900 +Subject: ARM: shmobile: Remove MEMORY_START/SIZE + +Remove CONFIG_MEMORY_START and CONFIG_MEMORY_SIZE from mach-shmobile. + +Boards should use DT to specify their memory setup. Boards that still +not support DT may pass ATAGS with memory information from the boot +loader. If those ATAGS turn out to be incorrect then appended DTB with +memory information should be used as a workaround. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 3c2b1042d2db50506b387611f7a60e81241cfabc) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/Kconfig | 31 ------------------------------- + 1 file changed, 31 deletions(-) + +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index 70df9490..935a661c 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -213,37 +213,6 @@ config CPU_HAS_INTEVT + bool + default y + +-menu "Memory configuration" +- +-config MEMORY_START +- hex "Physical memory start address" +- default "0x40000000" if MACH_AP4EVB || MACH_AG5EVM || \ +- MACH_MACKEREL || MACH_BONITO || \ +- MACH_ARMADILLO800EVA || MACH_APE6EVM || \ +- MACH_LAGER +- default "0x41000000" if MACH_KOTA2 +- default "0x00000000" +- ---help--- +- Tweak this only when porting to a new machine which does not +- already have a defconfig. Changing it from the known correct +- value on any of the known systems will only lead to disaster. +- +-config MEMORY_SIZE +- hex "Physical memory size" +- default "0x80000000" if MACH_LAGER +- default "0x40000000" if MACH_APE6EVM +- default "0x20000000" if MACH_AG5EVM || MACH_BONITO || \ +- MACH_ARMADILLO800EVA +- default "0x1e000000" if MACH_KOTA2 +- default "0x10000000" if MACH_AP4EVB || MACH_MACKEREL +- default "0x04000000" +- help +- This sets the default memory size assumed by your kernel. It can +- be overridden as normal by the 'mem=' argument on the kernel command +- line. +- +-endmenu +- + menu "Timer and clock configuration" + + config SHMOBILE_TIMER_HZ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0290-ARM-shmobile-Enable-ARM_PATCH_PHYS_VIRT.patch b/patches.renesas/0290-ARM-shmobile-Enable-ARM_PATCH_PHYS_VIRT.patch new file mode 100644 index 00000000000..d0e28660b19 --- /dev/null +++ b/patches.renesas/0290-ARM-shmobile-Enable-ARM_PATCH_PHYS_VIRT.patch @@ -0,0 +1,39 @@ +From 3bb7c61a3418091dbd205423416ae08a1d48b5b0 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Mon, 10 Jun 2013 18:46:47 +0900 +Subject: ARM: shmobile: Enable ARM_PATCH_PHYS_VIRT + +Adjust mach-shmobile to add a select for CONFIG_ARM_PATCH_PHYS_VIRT +and at the same time remove NEED_MACH_MEMORY_H. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 69469995980edab1a99f50a51e5e9525b4e11148) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index 18a9f5ef..9e4b5fd2 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -634,6 +634,7 @@ config ARCH_MSM + + config ARCH_SHMOBILE + bool "Renesas SH-Mobile / R-Mobile" ++ select ARM_PATCH_PHYS_VIRT + select CLKDEV_LOOKUP + select GENERIC_CLOCKEVENTS + select HAVE_ARM_SCU if SMP +@@ -643,7 +644,6 @@ config ARCH_SHMOBILE + select HAVE_SMP + select MIGHT_HAVE_CACHE_L2X0 + select MULTI_IRQ_HANDLER +- select NEED_MACH_MEMORY_H + select NO_IOPORT + select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB + select PM_GENERIC_DOMAINS if PM +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0291-ARM-shmobile-Remove-mach-memory.h.patch b/patches.renesas/0291-ARM-shmobile-Remove-mach-memory.h.patch new file mode 100644 index 00000000000..e70a219265c --- /dev/null +++ b/patches.renesas/0291-ARM-shmobile-Remove-mach-memory.h.patch @@ -0,0 +1,32 @@ +From 9206f5400013c490998e6b98869486b17ec5ff2b Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Mon, 10 Jun 2013 18:47:06 +0900 +Subject: ARM: shmobile: Remove mach/memory.h + +Remove mach-shmobile memory.h since it is no longer needed. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 21ba05a6c2defa228a5aa1100bd012e7a4f0fb30) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/include/mach/memory.h | 7 ------- + 1 file changed, 7 deletions(-) + delete mode 100644 arch/arm/mach-shmobile/include/mach/memory.h + +diff --git a/arch/arm/mach-shmobile/include/mach/memory.h b/arch/arm/mach-shmobile/include/mach/memory.h +deleted file mode 100644 +index 0ffbe815..00000000 +--- a/arch/arm/mach-shmobile/include/mach/memory.h ++++ /dev/null +@@ -1,7 +0,0 @@ +-#ifndef __ASM_MACH_MEMORY_H +-#define __ASM_MACH_MEMORY_H +- +-#define PLAT_PHYS_OFFSET UL(CONFIG_MEMORY_START) +-#define MEM_SIZE UL(CONFIG_MEMORY_SIZE) +- +-#endif /* __ASM_MACH_MEMORY_H */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0292-ARM-shmobile-Remove-AP4EVB-board-support.patch b/patches.renesas/0292-ARM-shmobile-Remove-AP4EVB-board-support.patch new file mode 100644 index 00000000000..b228278df43 --- /dev/null +++ b/patches.renesas/0292-ARM-shmobile-Remove-AP4EVB-board-support.patch @@ -0,0 +1,1634 @@ +From 51a79fc03bfe331520ac33982aebc4cfa58892ac Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Wed, 12 Jun 2013 18:18:19 +0900 +Subject: ARM: shmobile: Remove AP4EVB board support + +Remove board support for the sh7372 based AP4EVB board + +The sh7372 SoC support code is still kept around since it +is in use by the Mackerel board which is basically a more +recent board where the design is based on AP4EVB. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit b24bd7e97b3784afca6b808be1e5848e30e637ac) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/configs/ap4evb_defconfig | 56 - + arch/arm/mach-shmobile/Kconfig | 21 - + arch/arm/mach-shmobile/Makefile | 1 - + arch/arm/mach-shmobile/Makefile.boot | 1 - + arch/arm/mach-shmobile/board-ap4evb.c | 1310 -------------------- + .../arm/mach-shmobile/include/mach/head-ap4evb.txt | 93 -- + arch/arm/mach-shmobile/include/mach/mmc-ap4eb.h | 29 - + arch/arm/mach-shmobile/include/mach/mmc.h | 4 +- + arch/arm/mach-shmobile/include/mach/zboot.h | 6 +- + 9 files changed, 2 insertions(+), 1519 deletions(-) + delete mode 100644 arch/arm/configs/ap4evb_defconfig + delete mode 100644 arch/arm/mach-shmobile/board-ap4evb.c + delete mode 100644 arch/arm/mach-shmobile/include/mach/head-ap4evb.txt + delete mode 100644 arch/arm/mach-shmobile/include/mach/mmc-ap4eb.h + +diff --git a/arch/arm/configs/ap4evb_defconfig b/arch/arm/configs/ap4evb_defconfig +deleted file mode 100644 +index 66894f73..00000000 +--- a/arch/arm/configs/ap4evb_defconfig ++++ /dev/null +@@ -1,56 +0,0 @@ +-CONFIG_EXPERIMENTAL=y +-CONFIG_SYSVIPC=y +-CONFIG_IKCONFIG=y +-CONFIG_IKCONFIG_PROC=y +-CONFIG_LOG_BUF_SHIFT=16 +-CONFIG_BLK_DEV_INITRD=y +-CONFIG_SLAB=y +-# CONFIG_BLK_DEV_BSG is not set +-# CONFIG_IOSCHED_DEADLINE is not set +-# CONFIG_IOSCHED_CFQ is not set +-CONFIG_ARCH_SHMOBILE=y +-CONFIG_ARCH_SH7372=y +-CONFIG_MACH_AP4EVB=y +-CONFIG_AEABI=y +-# CONFIG_OABI_COMPAT is not set +-CONFIG_ZBOOT_ROM_TEXT=0x0 +-CONFIG_ZBOOT_ROM_BSS=0x0 +-CONFIG_CMDLINE="console=ttySC0,115200 earlyprintk=sh-sci.0,115200" +-CONFIG_KEXEC=y +-CONFIG_PM=y +-# CONFIG_SUSPEND is not set +-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +-# CONFIG_FIRMWARE_IN_KERNEL is not set +-CONFIG_MTD=y +-CONFIG_MTD_CONCAT=y +-CONFIG_MTD_PARTITIONS=y +-CONFIG_MTD_CHAR=y +-CONFIG_MTD_BLOCK=y +-CONFIG_MTD_CFI=y +-CONFIG_MTD_CFI_INTELEXT=y +-CONFIG_MTD_PHYSMAP=y +-CONFIG_MTD_NAND=y +-# CONFIG_BLK_DEV is not set +-# CONFIG_MISC_DEVICES is not set +-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +-# CONFIG_INPUT_KEYBOARD is not set +-# CONFIG_INPUT_MOUSE is not set +-# CONFIG_SERIO is not set +-CONFIG_SERIAL_SH_SCI=y +-CONFIG_SERIAL_SH_SCI_NR_UARTS=8 +-CONFIG_SERIAL_SH_SCI_CONSOLE=y +-# CONFIG_LEGACY_PTYS is not set +-# CONFIG_HW_RANDOM is not set +-# CONFIG_HWMON is not set +-# CONFIG_VGA_CONSOLE is not set +-# CONFIG_HID_SUPPORT is not set +-# CONFIG_USB_SUPPORT is not set +-# CONFIG_DNOTIFY is not set +-CONFIG_TMPFS=y +-# CONFIG_MISC_FILESYSTEMS is not set +-CONFIG_MAGIC_SYSRQ=y +-CONFIG_DEBUG_KERNEL=y +-# CONFIG_DETECT_SOFTLOCKUP is not set +-# CONFIG_RCU_CPU_STALL_DETECTOR is not set +-# CONFIG_FTRACE is not set +-# CONFIG_CRC32 is not set +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index 935a661c..810af004 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -71,27 +71,6 @@ config ARCH_EMEV2 + + comment "SH-Mobile Board Type" + +-config MACH_AP4EVB +- bool "AP4EVB board" +- depends on ARCH_SH7372 +- select ARCH_REQUIRE_GPIOLIB +- select REGULATOR_FIXED_VOLTAGE if REGULATOR +- select SH_LCD_MIPI_DSI +- select SND_SOC_AK4642 if SND_SIMPLE_CARD +- +-choice +- prompt "AP4EVB LCD panel selection" +- default AP4EVB_QHD +- depends on MACH_AP4EVB +- +-config AP4EVB_QHD +- bool "MIPI-DSI QHD (960x540)" +- +-config AP4EVB_WVGA +- bool "Parallel WVGA (800x480)" +- +-endchoice +- + config MACH_AG5EVM + bool "AG5EVM board" + depends on ARCH_SH73A0 +diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile +index 812de045..7f81b9a2 100644 +--- a/arch/arm/mach-shmobile/Makefile ++++ b/arch/arm/mach-shmobile/Makefile +@@ -35,7 +35,6 @@ obj-$(CONFIG_ARCH_R8A7779) += pm-r8a7779.o + obj-$(CONFIG_ARCH_SH73A0) += pm-sh73a0.o + + # Board objects +-obj-$(CONFIG_MACH_AP4EVB) += board-ap4evb.o + obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o + obj-$(CONFIG_MACH_APE6EVM) += board-ape6evm.o + obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o +diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot +index 6b147ea2..3030673e 100644 +--- a/arch/arm/mach-shmobile/Makefile.boot ++++ b/arch/arm/mach-shmobile/Makefile.boot +@@ -1,7 +1,6 @@ + # per-board load address for uImage + loadaddr-y := + loadaddr-$(CONFIG_MACH_AG5EVM) += 0x40008000 +-loadaddr-$(CONFIG_MACH_AP4EVB) += 0x40008000 + loadaddr-$(CONFIG_MACH_APE6EVM) += 0x40008000 + loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000 + loadaddr-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += 0x40008000 +diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c +deleted file mode 100644 +index 297bf5ee..00000000 +--- a/arch/arm/mach-shmobile/board-ap4evb.c ++++ /dev/null +@@ -1,1310 +0,0 @@ +-/* +- * AP4EVB board support +- * +- * Copyright (C) 2010 Magnus Damm +- * Copyright (C) 2008 Yoshihiro Shimoda +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; version 2 of the License. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +- */ +-#include <linux/clk.h> +-#include <linux/kernel.h> +-#include <linux/init.h> +-#include <linux/interrupt.h> +-#include <linux/irq.h> +-#include <linux/platform_device.h> +-#include <linux/delay.h> +-#include <linux/mfd/tmio.h> +-#include <linux/mmc/host.h> +-#include <linux/mmc/sh_mobile_sdhi.h> +-#include <linux/mtd/mtd.h> +-#include <linux/mtd/partitions.h> +-#include <linux/mtd/physmap.h> +-#include <linux/mmc/sh_mmcif.h> +-#include <linux/i2c.h> +-#include <linux/i2c/tsc2007.h> +-#include <linux/io.h> +-#include <linux/pinctrl/machine.h> +-#include <linux/regulator/fixed.h> +-#include <linux/regulator/machine.h> +-#include <linux/smsc911x.h> +-#include <linux/sh_intc.h> +-#include <linux/sh_clk.h> +-#include <linux/gpio.h> +-#include <linux/input.h> +-#include <linux/leds.h> +-#include <linux/input/sh_keysc.h> +-#include <linux/usb/r8a66597.h> +-#include <linux/pm_clock.h> +-#include <linux/dma-mapping.h> +- +-#include <media/sh_mobile_ceu.h> +-#include <media/sh_mobile_csi2.h> +-#include <media/soc_camera.h> +- +-#include <sound/sh_fsi.h> +-#include <sound/simple_card.h> +- +-#include <video/sh_mobile_hdmi.h> +-#include <video/sh_mobile_lcdc.h> +-#include <video/sh_mipi_dsi.h> +- +-#include <mach/common.h> +-#include <mach/irqs.h> +-#include <mach/sh7372.h> +- +-#include <asm/mach-types.h> +-#include <asm/mach/arch.h> +-#include <asm/setup.h> +- +-#include "sh-gpio.h" +- +-/* +- * Address Interface BusWidth note +- * ------------------------------------------------------------------ +- * 0x0000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = ON +- * 0x0800_0000 user area - +- * 0x1000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = OFF +- * 0x1400_0000 Ether (LAN9220) 16bit +- * 0x1600_0000 user area - cannot use with NAND +- * 0x1800_0000 user area - +- * 0x1A00_0000 - +- * 0x4000_0000 LPDDR2-SDRAM (POP) 32bit +- */ +- +-/* +- * NOR Flash ROM +- * +- * SW1 | SW2 | SW7 | NOR Flash ROM +- * bit1 | bit1 bit2 | bit1 | Memory allocation +- * ------+------------+------+------------------ +- * OFF | ON OFF | ON | Area 0 +- * OFF | ON OFF | OFF | Area 4 +- */ +- +-/* +- * NAND Flash ROM +- * +- * SW1 | SW2 | SW7 | NAND Flash ROM +- * bit1 | bit1 bit2 | bit2 | Memory allocation +- * ------+------------+------+------------------ +- * OFF | ON OFF | ON | FCE 0 +- * OFF | ON OFF | OFF | FCE 1 +- */ +- +-/* +- * SMSC 9220 +- * +- * SW1 SMSC 9220 +- * ----------------------- +- * ON access disable +- * OFF access enable +- */ +- +-/* +- * LCD / IRQ / KEYSC / IrDA +- * +- * IRQ = IRQ26 (TS), IRQ27 (VIO), IRQ28 (QHD-TouchScreen) +- * LCD = 2nd LCDC (WVGA) +- * +- * | SW43 | +- * SW3 | ON | OFF | +- * -------------+-----------------------+---------------+ +- * ON | KEY / IrDA | LCD | +- * OFF | KEY / IrDA / IRQ | IRQ | +- * +- * +- * QHD / WVGA display +- * +- * You can choice display type on menuconfig. +- * Then, check above dip-switch. +- */ +- +-/* +- * USB +- * +- * J7 : 1-2 MAX3355E VBUS +- * 2-3 DC 5.0V +- * +- * S39: bit2: off +- */ +- +-/* +- * FSI/FSMI +- * +- * SW41 : ON : SH-Mobile AP4 Audio Mode +- * : OFF : Bluetooth Audio Mode +- * +- * it needs amixer settings for playing +- * +- * amixer set "Headphone Enable" on +- */ +- +-/* +- * MMC0/SDHI1 (CN7) +- * +- * J22 : select card voltage +- * 1-2 pin : 1.8v +- * 2-3 pin : 3.3v +- * +- * SW1 | SW33 +- * | bit1 | bit2 | bit3 | bit4 +- * ------------+------+------+------+------- +- * MMC0 OFF | OFF | ON | ON | X +- * SDHI1 OFF | ON | X | OFF | ON +- * +- * voltage lebel +- * CN7 : 1.8v +- * CN12: 3.3v +- */ +- +-/* Dummy supplies, where voltage doesn't matter */ +-static struct regulator_consumer_supply fixed1v8_power_consumers[] = +-{ +- /* J22 default position: 1.8V */ +- REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"), +- REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"), +- REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"), +- REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"), +-}; +- +-static struct regulator_consumer_supply fixed3v3_power_consumers[] = +-{ +- REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"), +- REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"), +-}; +- +-static struct regulator_consumer_supply dummy_supplies[] = { +- REGULATOR_SUPPLY("vddvario", "smsc911x"), +- REGULATOR_SUPPLY("vdd33a", "smsc911x"), +-}; +- +-/* MTD */ +-static struct mtd_partition nor_flash_partitions[] = { +- { +- .name = "loader", +- .offset = 0x00000000, +- .size = 512 * 1024, +- .mask_flags = MTD_WRITEABLE, +- }, +- { +- .name = "bootenv", +- .offset = MTDPART_OFS_APPEND, +- .size = 512 * 1024, +- .mask_flags = MTD_WRITEABLE, +- }, +- { +- .name = "kernel_ro", +- .offset = MTDPART_OFS_APPEND, +- .size = 8 * 1024 * 1024, +- .mask_flags = MTD_WRITEABLE, +- }, +- { +- .name = "kernel", +- .offset = MTDPART_OFS_APPEND, +- .size = 8 * 1024 * 1024, +- }, +- { +- .name = "data", +- .offset = MTDPART_OFS_APPEND, +- .size = MTDPART_SIZ_FULL, +- }, +-}; +- +-static struct physmap_flash_data nor_flash_data = { +- .width = 2, +- .parts = nor_flash_partitions, +- .nr_parts = ARRAY_SIZE(nor_flash_partitions), +-}; +- +-static struct resource nor_flash_resources[] = { +- [0] = { +- .start = 0x20000000, /* CS0 shadow instead of regular CS0 */ +- .end = 0x28000000 - 1, /* needed by USB MASK ROM boot */ +- .flags = IORESOURCE_MEM, +- } +-}; +- +-static struct platform_device nor_flash_device = { +- .name = "physmap-flash", +- .dev = { +- .platform_data = &nor_flash_data, +- }, +- .num_resources = ARRAY_SIZE(nor_flash_resources), +- .resource = nor_flash_resources, +-}; +- +-/* SMSC 9220 */ +-static struct resource smc911x_resources[] = { +- { +- .start = 0x14000000, +- .end = 0x16000000 - 1, +- .flags = IORESOURCE_MEM, +- }, { +- .start = evt2irq(0x02c0) /* IRQ6A */, +- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, +- }, +-}; +- +-static struct smsc911x_platform_config smsc911x_info = { +- .flags = SMSC911X_USE_16BIT | SMSC911X_SAVE_MAC_ADDRESS, +- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, +- .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, +-}; +- +-static struct platform_device smc911x_device = { +- .name = "smsc911x", +- .id = -1, +- .num_resources = ARRAY_SIZE(smc911x_resources), +- .resource = smc911x_resources, +- .dev = { +- .platform_data = &smsc911x_info, +- }, +-}; +- +-/* +- * The card detect pin of the top SD/MMC slot (CN7) is active low and is +- * connected to GPIO A22 of SH7372 (GPIO 41). +- */ +-static int slot_cn7_get_cd(struct platform_device *pdev) +-{ +- return !gpio_get_value(41); +-} +-/* MERAM */ +-static struct sh_mobile_meram_info meram_info = { +- .addr_mode = SH_MOBILE_MERAM_MODE1, +-}; +- +-static struct resource meram_resources[] = { +- [0] = { +- .name = "regs", +- .start = 0xe8000000, +- .end = 0xe807ffff, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .name = "meram", +- .start = 0xe8080000, +- .end = 0xe81fffff, +- .flags = IORESOURCE_MEM, +- }, +-}; +- +-static struct platform_device meram_device = { +- .name = "sh_mobile_meram", +- .id = 0, +- .num_resources = ARRAY_SIZE(meram_resources), +- .resource = meram_resources, +- .dev = { +- .platform_data = &meram_info, +- }, +-}; +- +-/* SH_MMCIF */ +-static struct resource sh_mmcif_resources[] = { +- [0] = { +- .name = "MMCIF", +- .start = 0xE6BD0000, +- .end = 0xE6BD00FF, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- /* MMC ERR */ +- .start = evt2irq(0x1ac0), +- .flags = IORESOURCE_IRQ, +- }, +- [2] = { +- /* MMC NOR */ +- .start = evt2irq(0x1ae0), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct sh_mmcif_plat_data sh_mmcif_plat = { +- .sup_pclk = 0, +- .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, +- .caps = MMC_CAP_4_BIT_DATA | +- MMC_CAP_8_BIT_DATA | +- MMC_CAP_NEEDS_POLL, +- .get_cd = slot_cn7_get_cd, +- .slave_id_tx = SHDMA_SLAVE_MMCIF_TX, +- .slave_id_rx = SHDMA_SLAVE_MMCIF_RX, +-}; +- +-static struct platform_device sh_mmcif_device = { +- .name = "sh_mmcif", +- .id = 0, +- .dev = { +- .dma_mask = NULL, +- .coherent_dma_mask = 0xffffffff, +- .platform_data = &sh_mmcif_plat, +- }, +- .num_resources = ARRAY_SIZE(sh_mmcif_resources), +- .resource = sh_mmcif_resources, +-}; +- +-/* SDHI0 */ +-static struct sh_mobile_sdhi_info sdhi0_info = { +- .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, +- .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, +- .tmio_caps = MMC_CAP_SDIO_IRQ, +-}; +- +-static struct resource sdhi0_resources[] = { +- [0] = { +- .name = "SDHI0", +- .start = 0xe6850000, +- .end = 0xe68500ff, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = evt2irq(0x0e00) /* SDHI0_SDHI0I0 */, +- .flags = IORESOURCE_IRQ, +- }, +- [2] = { +- .start = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */, +- .flags = IORESOURCE_IRQ, +- }, +- [3] = { +- .start = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */, +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device sdhi0_device = { +- .name = "sh_mobile_sdhi", +- .num_resources = ARRAY_SIZE(sdhi0_resources), +- .resource = sdhi0_resources, +- .id = 0, +- .dev = { +- .platform_data = &sdhi0_info, +- }, +-}; +- +-/* SDHI1 */ +-static struct sh_mobile_sdhi_info sdhi1_info = { +- .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX, +- .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX, +- .tmio_ocr_mask = MMC_VDD_165_195, +- .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE, +- .tmio_caps = MMC_CAP_NEEDS_POLL | MMC_CAP_SDIO_IRQ, +- .get_cd = slot_cn7_get_cd, +-}; +- +-static struct resource sdhi1_resources[] = { +- [0] = { +- .name = "SDHI1", +- .start = 0xe6860000, +- .end = 0xe68600ff, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */ +- .flags = IORESOURCE_IRQ, +- }, +- [2] = { +- .start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */ +- .flags = IORESOURCE_IRQ, +- }, +- [3] = { +- .start = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */ +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device sdhi1_device = { +- .name = "sh_mobile_sdhi", +- .num_resources = ARRAY_SIZE(sdhi1_resources), +- .resource = sdhi1_resources, +- .id = 1, +- .dev = { +- .platform_data = &sdhi1_info, +- }, +-}; +- +-/* USB1 */ +-static void usb1_host_port_power(int port, int power) +-{ +- if (!power) /* only power-on supported for now */ +- return; +- +- /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */ +- __raw_writew(__raw_readw(IOMEM(0xE68B0008)) | 0x600, IOMEM(0xE68B0008)); +-} +- +-static struct r8a66597_platdata usb1_host_data = { +- .on_chip = 1, +- .port_power = usb1_host_port_power, +-}; +- +-static struct resource usb1_host_resources[] = { +- [0] = { +- .name = "USBHS", +- .start = 0xE68B0000, +- .end = 0xE68B00E6 - 1, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = evt2irq(0x1ce0) /* USB1_USB1I0 */, +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device usb1_host_device = { +- .name = "r8a66597_hcd", +- .id = 1, +- .dev = { +- .dma_mask = NULL, /* not use dma */ +- .coherent_dma_mask = 0xffffffff, +- .platform_data = &usb1_host_data, +- }, +- .num_resources = ARRAY_SIZE(usb1_host_resources), +- .resource = usb1_host_resources, +-}; +- +-/* +- * QHD display +- */ +-#ifdef CONFIG_AP4EVB_QHD +- +-/* KEYSC (Needs SW43 set to ON) */ +-static struct sh_keysc_info keysc_info = { +- .mode = SH_KEYSC_MODE_1, +- .scan_timing = 3, +- .delay = 2500, +- .keycodes = { +- KEY_0, KEY_1, KEY_2, KEY_3, KEY_4, +- KEY_5, KEY_6, KEY_7, KEY_8, KEY_9, +- KEY_A, KEY_B, KEY_C, KEY_D, KEY_E, +- KEY_F, KEY_G, KEY_H, KEY_I, KEY_J, +- KEY_K, KEY_L, KEY_M, KEY_N, KEY_O, +- }, +-}; +- +-static struct resource keysc_resources[] = { +- [0] = { +- .name = "KEYSC", +- .start = 0xe61b0000, +- .end = 0xe61b0063, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = evt2irq(0x0be0), /* KEYSC_KEY */ +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device keysc_device = { +- .name = "sh_keysc", +- .id = 0, /* "keysc0" clock */ +- .num_resources = ARRAY_SIZE(keysc_resources), +- .resource = keysc_resources, +- .dev = { +- .platform_data = &keysc_info, +- }, +-}; +- +-/* MIPI-DSI */ +-static int sh_mipi_set_dot_clock(struct platform_device *pdev, +- void __iomem *base, +- int enable) +-{ +- struct clk *pck = clk_get(&pdev->dev, "dsip_clk"); +- +- if (IS_ERR(pck)) +- return PTR_ERR(pck); +- +- if (enable) { +- /* +- * DSIPCLK = 24MHz +- * D-PHY = DSIPCLK * ((0x6*2)+1) = 312MHz (see .phyctrl) +- * HsByteCLK = D-PHY/8 = 39MHz +- * +- * X * Y * FPS = +- * (544+72+600+16) * (961+8+8+2) * 30 = 36.1MHz +- */ +- clk_set_rate(pck, clk_round_rate(pck, 24000000)); +- clk_enable(pck); +- } else { +- clk_disable(pck); +- } +- +- clk_put(pck); +- +- return 0; +-} +- +-static struct resource mipidsi0_resources[] = { +- [0] = { +- .start = 0xffc60000, +- .end = 0xffc63073, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = 0xffc68000, +- .end = 0xffc680ef, +- .flags = IORESOURCE_MEM, +- }, +-}; +- +-static struct sh_mipi_dsi_info mipidsi0_info = { +- .data_format = MIPI_RGB888, +- .channel = LCDC_CHAN_MAINLCD, +- .lane = 2, +- .vsynw_offset = 17, +- .phyctrl = 0x6 << 8, +- .flags = SH_MIPI_DSI_SYNC_PULSES_MODE | +- SH_MIPI_DSI_HSbyteCLK, +- .set_dot_clock = sh_mipi_set_dot_clock, +-}; +- +-static struct platform_device mipidsi0_device = { +- .name = "sh-mipi-dsi", +- .num_resources = ARRAY_SIZE(mipidsi0_resources), +- .resource = mipidsi0_resources, +- .id = 0, +- .dev = { +- .platform_data = &mipidsi0_info, +- }, +-}; +- +-static struct platform_device *qhd_devices[] __initdata = { +- &mipidsi0_device, +- &keysc_device, +-}; +-#endif /* CONFIG_AP4EVB_QHD */ +- +-/* LCDC0 */ +-static const struct fb_videomode ap4evb_lcdc_modes[] = { +- { +-#ifdef CONFIG_AP4EVB_QHD +- .name = "R63302(QHD)", +- .xres = 544, +- .yres = 961, +- .left_margin = 72, +- .right_margin = 600, +- .hsync_len = 16, +- .upper_margin = 8, +- .lower_margin = 8, +- .vsync_len = 2, +- .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT, +-#else +- .name = "WVGA Panel", +- .xres = 800, +- .yres = 480, +- .left_margin = 220, +- .right_margin = 110, +- .hsync_len = 70, +- .upper_margin = 20, +- .lower_margin = 5, +- .vsync_len = 5, +- .sync = 0, +-#endif +- }, +-}; +- +-static const struct sh_mobile_meram_cfg lcd_meram_cfg = { +- .icb[0] = { +- .meram_size = 0x40, +- }, +- .icb[1] = { +- .meram_size = 0x40, +- }, +-}; +- +-static struct sh_mobile_lcdc_info lcdc_info = { +- .meram_dev = &meram_info, +- .ch[0] = { +- .chan = LCDC_CHAN_MAINLCD, +- .fourcc = V4L2_PIX_FMT_RGB565, +- .lcd_modes = ap4evb_lcdc_modes, +- .num_modes = ARRAY_SIZE(ap4evb_lcdc_modes), +- .meram_cfg = &lcd_meram_cfg, +-#ifdef CONFIG_AP4EVB_QHD +- .tx_dev = &mipidsi0_device, +-#endif +- } +-}; +- +-static struct resource lcdc_resources[] = { +- [0] = { +- .name = "LCDC", +- .start = 0xfe940000, /* P4-only space */ +- .end = 0xfe943fff, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = intcs_evt2irq(0x580), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device lcdc_device = { +- .name = "sh_mobile_lcdc_fb", +- .num_resources = ARRAY_SIZE(lcdc_resources), +- .resource = lcdc_resources, +- .dev = { +- .platform_data = &lcdc_info, +- .coherent_dma_mask = ~0, +- }, +-}; +- +-/* FSI */ +-#define IRQ_FSI evt2irq(0x1840) +-static struct sh_fsi_platform_info fsi_info = { +- .port_b = { +- .flags = SH_FSI_CLK_CPG | +- SH_FSI_FMT_SPDIF, +- }, +-}; +- +-static struct resource fsi_resources[] = { +- [0] = { +- .name = "FSI", +- .start = 0xFE3C0000, +- .end = 0xFE3C0400 - 1, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = IRQ_FSI, +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device fsi_device = { +- .name = "sh_fsi2", +- .id = -1, +- .num_resources = ARRAY_SIZE(fsi_resources), +- .resource = fsi_resources, +- .dev = { +- .platform_data = &fsi_info, +- }, +-}; +- +-static struct asoc_simple_card_info fsi2_ak4643_info = { +- .name = "AK4643", +- .card = "FSI2A-AK4643", +- .codec = "ak4642-codec.0-0013", +- .platform = "sh_fsi2", +- .daifmt = SND_SOC_DAIFMT_LEFT_J, +- .cpu_dai = { +- .name = "fsia-dai", +- .fmt = SND_SOC_DAIFMT_CBS_CFS, +- }, +- .codec_dai = { +- .name = "ak4642-hifi", +- .fmt = SND_SOC_DAIFMT_CBM_CFM, +- .sysclk = 11289600, +- }, +-}; +- +-static struct platform_device fsi_ak4643_device = { +- .name = "asoc-simple-card", +- .dev = { +- .platform_data = &fsi2_ak4643_info, +- }, +-}; +- +-/* LCDC1 */ +-static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq, +- unsigned long *parent_freq); +- +-static struct sh_mobile_hdmi_info hdmi_info = { +- .flags = HDMI_SND_SRC_SPDIF, +- .clk_optimize_parent = ap4evb_clk_optimize, +-}; +- +-static struct resource hdmi_resources[] = { +- [0] = { +- .name = "HDMI", +- .start = 0xe6be0000, +- .end = 0xe6be00ff, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- /* There's also an HDMI interrupt on INTCS @ 0x18e0 */ +- .start = evt2irq(0x17e0), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device hdmi_device = { +- .name = "sh-mobile-hdmi", +- .num_resources = ARRAY_SIZE(hdmi_resources), +- .resource = hdmi_resources, +- .id = -1, +- .dev = { +- .platform_data = &hdmi_info, +- }, +-}; +- +-static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq, +- unsigned long *parent_freq) +-{ +- struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick"); +- long error; +- +- if (IS_ERR(hdmi_ick)) { +- int ret = PTR_ERR(hdmi_ick); +- pr_err("Cannot get HDMI ICK: %d\n", ret); +- return ret; +- } +- +- error = clk_round_parent(hdmi_ick, target, best_freq, parent_freq, 1, 64); +- +- clk_put(hdmi_ick); +- +- return error; +-} +- +-static const struct sh_mobile_meram_cfg hdmi_meram_cfg = { +- .icb[0] = { +- .meram_size = 0x100, +- }, +- .icb[1] = { +- .meram_size = 0x100, +- }, +-}; +- +-static struct sh_mobile_lcdc_info sh_mobile_lcdc1_info = { +- .clock_source = LCDC_CLK_EXTERNAL, +- .meram_dev = &meram_info, +- .ch[0] = { +- .chan = LCDC_CHAN_MAINLCD, +- .fourcc = V4L2_PIX_FMT_RGB565, +- .interface_type = RGB24, +- .clock_divider = 1, +- .flags = LCDC_FLAGS_DWPOL, +- .meram_cfg = &hdmi_meram_cfg, +- .tx_dev = &hdmi_device, +- } +-}; +- +-static struct resource lcdc1_resources[] = { +- [0] = { +- .name = "LCDC1", +- .start = 0xfe944000, +- .end = 0xfe947fff, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = intcs_evt2irq(0x1780), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device lcdc1_device = { +- .name = "sh_mobile_lcdc_fb", +- .num_resources = ARRAY_SIZE(lcdc1_resources), +- .resource = lcdc1_resources, +- .id = 1, +- .dev = { +- .platform_data = &sh_mobile_lcdc1_info, +- .coherent_dma_mask = ~0, +- }, +-}; +- +-static struct asoc_simple_card_info fsi2_hdmi_info = { +- .name = "HDMI", +- .card = "FSI2B-HDMI", +- .codec = "sh-mobile-hdmi", +- .platform = "sh_fsi2", +- .cpu_dai = { +- .name = "fsib-dai", +- .fmt = SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_IB_NF, +- }, +- .codec_dai = { +- .name = "sh_mobile_hdmi-hifi", +- }, +-}; +- +-static struct platform_device fsi_hdmi_device = { +- .name = "asoc-simple-card", +- .id = 1, +- .dev = { +- .platform_data = &fsi2_hdmi_info, +- }, +-}; +- +-static struct gpio_led ap4evb_leds[] = { +- { +- .name = "led4", +- .gpio = 185, +- .default_state = LEDS_GPIO_DEFSTATE_ON, +- }, +- { +- .name = "led2", +- .gpio = 186, +- .default_state = LEDS_GPIO_DEFSTATE_ON, +- }, +- { +- .name = "led3", +- .gpio = 187, +- .default_state = LEDS_GPIO_DEFSTATE_ON, +- }, +- { +- .name = "led1", +- .gpio = 188, +- .default_state = LEDS_GPIO_DEFSTATE_ON, +- } +-}; +- +-static struct gpio_led_platform_data ap4evb_leds_pdata = { +- .num_leds = ARRAY_SIZE(ap4evb_leds), +- .leds = ap4evb_leds, +-}; +- +-static struct platform_device leds_device = { +- .name = "leds-gpio", +- .id = 0, +- .dev = { +- .platform_data = &ap4evb_leds_pdata, +- }, +-}; +- +-static struct i2c_board_info imx074_info = { +- I2C_BOARD_INFO("imx074", 0x1a), +-}; +- +-static struct soc_camera_link imx074_link = { +- .bus_id = 0, +- .board_info = &imx074_info, +- .i2c_adapter_id = 0, +- .module_name = "imx074", +-}; +- +-static struct platform_device ap4evb_camera = { +- .name = "soc-camera-pdrv", +- .id = 0, +- .dev = { +- .platform_data = &imx074_link, +- }, +-}; +- +-static struct sh_csi2_client_config csi2_clients[] = { +- { +- .phy = SH_CSI2_PHY_MAIN, +- .lanes = 0, /* default: 2 lanes */ +- .channel = 0, +- .pdev = &ap4evb_camera, +- }, +-}; +- +-static struct sh_csi2_pdata csi2_info = { +- .type = SH_CSI2C, +- .clients = csi2_clients, +- .num_clients = ARRAY_SIZE(csi2_clients), +- .flags = SH_CSI2_ECC | SH_CSI2_CRC, +-}; +- +-static struct resource csi2_resources[] = { +- [0] = { +- .name = "CSI2", +- .start = 0xffc90000, +- .end = 0xffc90fff, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = intcs_evt2irq(0x17a0), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct sh_mobile_ceu_companion csi2 = { +- .id = 0, +- .num_resources = ARRAY_SIZE(csi2_resources), +- .resource = csi2_resources, +- .platform_data = &csi2_info, +-}; +- +-static struct sh_mobile_ceu_info sh_mobile_ceu_info = { +- .flags = SH_CEU_FLAG_USE_8BIT_BUS, +- .max_width = 8188, +- .max_height = 8188, +- .csi2 = &csi2, +-}; +- +-static struct resource ceu_resources[] = { +- [0] = { +- .name = "CEU", +- .start = 0xfe910000, +- .end = 0xfe91009f, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = intcs_evt2irq(0x880), +- .flags = IORESOURCE_IRQ, +- }, +- [2] = { +- /* place holder for contiguous memory */ +- }, +-}; +- +-static struct platform_device ceu_device = { +- .name = "sh_mobile_ceu", +- .id = 0, /* "ceu0" clock */ +- .num_resources = ARRAY_SIZE(ceu_resources), +- .resource = ceu_resources, +- .dev = { +- .platform_data = &sh_mobile_ceu_info, +- .coherent_dma_mask = 0xffffffff, +- }, +-}; +- +-static struct platform_device *ap4evb_devices[] __initdata = { +- &leds_device, +- &nor_flash_device, +- &smc911x_device, +- &sdhi0_device, +- &sdhi1_device, +- &usb1_host_device, +- &fsi_device, +- &fsi_ak4643_device, +- &fsi_hdmi_device, +- &sh_mmcif_device, +- &hdmi_device, +- &lcdc_device, +- &lcdc1_device, +- &ceu_device, +- &ap4evb_camera, +- &meram_device, +-}; +- +-static void __init hdmi_init_pm_clock(void) +-{ +- struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick"); +- int ret; +- long rate; +- +- if (IS_ERR(hdmi_ick)) { +- ret = PTR_ERR(hdmi_ick); +- pr_err("Cannot get HDMI ICK: %d\n", ret); +- goto out; +- } +- +- ret = clk_set_parent(&sh7372_pllc2_clk, &sh7372_dv_clki_div2_clk); +- if (ret < 0) { +- pr_err("Cannot set PLLC2 parent: %d, %d users\n", ret, sh7372_pllc2_clk.usecount); +- goto out; +- } +- +- pr_debug("PLLC2 initial frequency %lu\n", clk_get_rate(&sh7372_pllc2_clk)); +- +- rate = clk_round_rate(&sh7372_pllc2_clk, 594000000); +- if (rate < 0) { +- pr_err("Cannot get suitable rate: %ld\n", rate); +- ret = rate; +- goto out; +- } +- +- ret = clk_set_rate(&sh7372_pllc2_clk, rate); +- if (ret < 0) { +- pr_err("Cannot set rate %ld: %d\n", rate, ret); +- goto out; +- } +- +- pr_debug("PLLC2 set frequency %lu\n", rate); +- +- ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk); +- if (ret < 0) +- pr_err("Cannot set HDMI parent: %d\n", ret); +- +-out: +- if (!IS_ERR(hdmi_ick)) +- clk_put(hdmi_ick); +-} +- +-/* TouchScreen */ +-#ifdef CONFIG_AP4EVB_QHD +-# define GPIO_TSC_PORT 123 +-#else /* WVGA */ +-# define GPIO_TSC_PORT 40 +-#endif +- +-#define IRQ28 evt2irq(0x3380) /* IRQ28A */ +-#define IRQ7 evt2irq(0x02e0) /* IRQ7A */ +-static int ts_get_pendown_state(void) +-{ +- return !gpio_get_value(GPIO_TSC_PORT); +-} +- +-static int ts_init(void) +-{ +- gpio_request_one(GPIO_TSC_PORT, GPIOF_IN, NULL); +- +- return 0; +-} +- +-static struct tsc2007_platform_data tsc2007_info = { +- .model = 2007, +- .x_plate_ohms = 180, +- .get_pendown_state = ts_get_pendown_state, +- .init_platform_hw = ts_init, +-}; +- +-static struct i2c_board_info tsc_device = { +- I2C_BOARD_INFO("tsc2007", 0x48), +- .type = "tsc2007", +- .platform_data = &tsc2007_info, +- /*.irq is selected on ap4evb_init */ +-}; +- +-/* I2C */ +-static struct i2c_board_info i2c0_devices[] = { +- { +- I2C_BOARD_INFO("ak4643", 0x13), +- }, +-}; +- +-static struct i2c_board_info i2c1_devices[] = { +- { +- I2C_BOARD_INFO("r2025sd", 0x32), +- }, +-}; +- +- +-static const struct pinctrl_map ap4evb_pinctrl_map[] = { +- /* CEU */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372", +- "ceu_clk_0", "ceu"), +- /* FSIA (AK4643) */ +- PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372", +- "fsia_sclk_in", "fsia"), +- PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372", +- "fsia_data_in", "fsia"), +- PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372", +- "fsia_data_out", "fsia"), +- /* FSIB (HDMI) */ +- PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-sh7372", +- "fsib_mclk_in", "fsib"), +- /* HDMI */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-sh7372", +- "hdmi", "hdmi"), +- /* KEYSC */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc", "pfc-sh7372", +- "keysc_in04_0", "keysc"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc", "pfc-sh7372", +- "keysc_out5", "keysc"), +-#ifndef CONFIG_AP4EVB_QHD +- /* LCDC */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372", +- "lcd_data18", "lcd"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372", +- "lcd_sync", "lcd"), +-#endif +- /* MMCIF */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372", +- "mmc0_data8_0", "mmc0"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372", +- "mmc0_ctrl_0", "mmc0"), +- /* SCIFA0 */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-sh7372", +- "scifa0_data", "scifa0"), +- /* SDHI0 */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", +- "sdhi0_data4", "sdhi0"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", +- "sdhi0_ctrl", "sdhi0"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", +- "sdhi0_cd", "sdhi0"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", +- "sdhi0_wp", "sdhi0"), +- /* SDHI1 */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372", +- "sdhi1_data4", "sdhi1"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372", +- "sdhi1_ctrl", "sdhi1"), +- /* SMSC911X */ +- PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372", +- "bsc_cs5a", "bsc"), +- PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372", +- "intc_irq6_0", "intc"), +- /* TSC2007 */ +-#ifdef CONFIG_AP4EVB_QHD +- PIN_MAP_MUX_GROUP_DEFAULT("1-0048", "pfc-sh7372", +- "intc_irq28_0", "intc"), +-#else /* WVGA */ +- PIN_MAP_MUX_GROUP_DEFAULT("1-0048", "pfc-sh7372", +- "intc_irq7_0", "intc"), +-#endif +- /* USBHS1 */ +- PIN_MAP_MUX_GROUP_DEFAULT("r8a66597_hcd.1", "pfc-sh7372", +- "usb1_vbus", "usb1"), +- PIN_MAP_MUX_GROUP_DEFAULT("r8a66597_hcd.1", "pfc-sh7372", +- "usb1_otg_id_0", "usb1"), +- PIN_MAP_MUX_GROUP_DEFAULT("r8a66597_hcd.1", "pfc-sh7372", +- "usb1_otg_ctrl_0", "usb1"), +-}; +- +-#define GPIO_PORT9CR IOMEM(0xE6051009) +-#define GPIO_PORT10CR IOMEM(0xE605100A) +-#define USCCR1 IOMEM(0xE6058144) +-static void __init ap4evb_init(void) +-{ +- struct pm_domain_device domain_devices[] = { +- { "A4LC", &lcdc1_device, }, +- { "A4LC", &lcdc_device, }, +- { "A4MP", &fsi_device, }, +- { "A3SP", &sh_mmcif_device, }, +- { "A3SP", &sdhi0_device, }, +- { "A3SP", &sdhi1_device, }, +- { "A4R", &ceu_device, }, +- }; +- u32 srcr4; +- struct clk *clk; +- +- regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers, +- ARRAY_SIZE(fixed1v8_power_consumers), 1800000); +- regulator_register_always_on(1, "fixed-3.3V", fixed3v3_power_consumers, +- ARRAY_SIZE(fixed3v3_power_consumers), 3300000); +- regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies)); +- +- /* External clock source */ +- clk_set_rate(&sh7372_dv_clki_clk, 27000000); +- +- pinctrl_register_mappings(ap4evb_pinctrl_map, +- ARRAY_SIZE(ap4evb_pinctrl_map)); +- sh7372_pinmux_init(); +- +- /* enable Debug switch (S6) */ +- gpio_request_one(32, GPIOF_IN | GPIOF_EXPORT, NULL); +- gpio_request_one(33, GPIOF_IN | GPIOF_EXPORT, NULL); +- gpio_request_one(34, GPIOF_IN | GPIOF_EXPORT, NULL); +- gpio_request_one(35, GPIOF_IN | GPIOF_EXPORT, NULL); +- +- /* setup USB phy */ +- __raw_writew(0x8a0a, IOMEM(0xE6058130)); /* USBCR4 */ +- +- /* FSI2 port A (ak4643) */ +- gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */ +- +- gpio_request(9, NULL); +- gpio_request(10, NULL); +- gpio_direction_none(GPIO_PORT9CR); /* FSIAOBT needs no direction */ +- gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */ +- +- /* card detect pin for MMC slot (CN7) */ +- gpio_request_one(41, GPIOF_IN, NULL); +- +- /* FSI2 port B (HDMI) */ +- __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */ +- +- /* set SPU2 clock to 119.6 MHz */ +- clk = clk_get(NULL, "spu_clk"); +- if (!IS_ERR(clk)) { +- clk_set_rate(clk, clk_round_rate(clk, 119600000)); +- clk_put(clk); +- } +- +- /* +- * set irq priority, to avoid sound chopping +- * when NFS rootfs is used +- * FSI(3) > SMSC911X(2) +- */ +- intc_set_priority(IRQ_FSI, 3); +- +- i2c_register_board_info(0, i2c0_devices, +- ARRAY_SIZE(i2c0_devices)); +- +- i2c_register_board_info(1, i2c1_devices, +- ARRAY_SIZE(i2c1_devices)); +- +-#ifdef CONFIG_AP4EVB_QHD +- +- /* +- * For QHD Panel (MIPI-DSI, CONFIG_AP4EVB_QHD=y) and +- * IRQ28 for Touch Panel, set dip switches S3, S43 as OFF, ON. +- */ +- +- /* enable TouchScreen */ +- irq_set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW); +- +- tsc_device.irq = IRQ28; +- i2c_register_board_info(1, &tsc_device, 1); +- +- /* LCDC0 */ +- lcdc_info.clock_source = LCDC_CLK_PERIPHERAL; +- lcdc_info.ch[0].interface_type = RGB24; +- lcdc_info.ch[0].clock_divider = 1; +- lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL; +- lcdc_info.ch[0].panel_cfg.width = 44; +- lcdc_info.ch[0].panel_cfg.height = 79; +- +- platform_add_devices(qhd_devices, ARRAY_SIZE(qhd_devices)); +- +-#else +- /* +- * For WVGA Panel (18-bit RGB, CONFIG_AP4EVB_WVGA=y) and +- * IRQ7 for Touch Panel, set dip switches S3, S43 to ON, OFF. +- */ +- gpio_request_one(189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */ +- gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ +- +- lcdc_info.clock_source = LCDC_CLK_BUS; +- lcdc_info.ch[0].interface_type = RGB18; +- lcdc_info.ch[0].clock_divider = 3; +- lcdc_info.ch[0].flags = 0; +- lcdc_info.ch[0].panel_cfg.width = 152; +- lcdc_info.ch[0].panel_cfg.height = 91; +- +- /* enable TouchScreen */ +- irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); +- +- tsc_device.irq = IRQ7; +- i2c_register_board_info(0, &tsc_device, 1); +-#endif /* CONFIG_AP4EVB_QHD */ +- +- /* CEU */ +- +- /* +- * TODO: reserve memory for V4L2 DMA buffers, when a suitable API +- * becomes available +- */ +- +- /* MIPI-CSI stuff */ +- clk = clk_get(NULL, "vck1_clk"); +- if (!IS_ERR(clk)) { +- clk_set_rate(clk, clk_round_rate(clk, 13000000)); +- clk_enable(clk); +- clk_put(clk); +- } +- +- sh7372_add_standard_devices(); +- +- /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */ +-#define SRCR4 IOMEM(0xe61580bc) +- srcr4 = __raw_readl(SRCR4); +- __raw_writel(srcr4 | (1 << 13), SRCR4); +- udelay(50); +- __raw_writel(srcr4 & ~(1 << 13), SRCR4); +- +- platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices)); +- +- rmobile_add_devices_to_domains(domain_devices, +- ARRAY_SIZE(domain_devices)); +- +- hdmi_init_pm_clock(); +- sh7372_pm_init(); +- pm_clk_add(&fsi_device.dev, "spu2"); +- pm_clk_add(&lcdc1_device.dev, "hdmi"); +-} +- +-MACHINE_START(AP4EVB, "ap4evb") +- .map_io = sh7372_map_io, +- .init_early = sh7372_add_early_devices, +- .init_irq = sh7372_init_irq, +- .handle_irq = shmobile_handle_irq_intc, +- .init_machine = ap4evb_init, +- .init_late = sh7372_pm_init_late, +- .init_time = sh7372_earlytimer_init, +-MACHINE_END +diff --git a/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt b/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt +deleted file mode 100644 +index 9f134dfe..00000000 +--- a/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt ++++ /dev/null +@@ -1,93 +0,0 @@ +-LIST "partner-jet-setup.txt" +-LIST "(C) Copyright 2010 Renesas Solutions Corp" +-LIST "Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>" +- +-LIST "RWT Setting" +-EW 0xE6020004, 0xA500 +-EW 0xE6030004, 0xA500 +- +-LIST "GPIO Setting" +-EB 0xE6051013, 0xA2 +- +-LIST "CPG" +-ED 0xE61500C0, 0x00000002 +- +-WAIT 1, 0xFE40009C +- +-LIST "FRQCR" +-ED 0xE6150000, 0x2D1305C3 +-ED 0xE61500E0, 0x9E40358E +-ED 0xE6150004, 0x80331050 +- +-WAIT 1, 0xFE40009C +- +-ED 0xE61500E4, 0x00002000 +- +-WAIT 1, 0xFE40009C +- +-LIST "PLL" +-ED 0xE6150028, 0x00004000 +- +-WAIT 1, 0xFE40009C +- +-ED 0xE615002C, 0x93000040 +- +-WAIT 1, 0xFE40009C +- +-LIST "SUB/USBClk" +-ED 0xE6150080, 0x00000180 +- +-LIST "BSC" +-ED 0xFEC10000, 0x00E0001B +- +-LIST "SBSC1" +-ED 0xFE400354, 0x01AD8000 +-ED 0xFE400354, 0x01AD8001 +- +-WAIT 5, 0xFE40009C +- +-ED 0xFE400008, 0xBCC90151 +-ED 0xFE400040, 0x41774113 +-ED 0xFE400044, 0x2712E229 +-ED 0xFE400048, 0x20C18505 +-ED 0xFE40004C, 0x00110209 +-ED 0xFE400010, 0x00000087 +- +-WAIT 30, 0xFE40009C +- +-ED 0xFE400084, 0x0000003F +-EB 0xFE500000, 0x00 +- +-WAIT 5, 0xFE40009C +- +-ED 0xFE400084, 0x0000FF0A +-EB 0xFE500000, 0x00 +- +-WAIT 1, 0xFE40009C +- +-ED 0xFE400084, 0x00002201 +-EB 0xFE500000, 0x00 +-ED 0xFE400084, 0x00000302 +-EB 0xFE500000, 0x00 +-EB 0xFE5C0000, 0x00 +-ED 0xFE400008, 0xBCC90159 +-ED 0xFE40008C, 0x88800004 +-ED 0xFE400094, 0x00000004 +-ED 0xFE400028, 0xA55A0032 +-ED 0xFE40002C, 0xA55A000C +-ED 0xFE400020, 0xA55A2048 +-ED 0xFE400008, 0xBCC90959 +- +-LIST "Change CPGA setting" +-ED 0xE61500E0, 0x9E40352E +-ED 0xE6150004, 0x80331050 +- +-WAIT 1, 0xFE40009C +- +-ED 0xFE400354, 0x01AD8002 +- +-LIST "SCIF0 - Serial port for earlyprintk" +-EB 0xE6053098, 0xe1 +-EW 0xE6C40000, 0x0000 +-EB 0xE6C40004, 0x19 +-EW 0xE6C40008, 0x0030 +diff --git a/arch/arm/mach-shmobile/include/mach/mmc-ap4eb.h b/arch/arm/mach-shmobile/include/mach/mmc-ap4eb.h +deleted file mode 100644 +index db59fdbd..00000000 +--- a/arch/arm/mach-shmobile/include/mach/mmc-ap4eb.h ++++ /dev/null +@@ -1,29 +0,0 @@ +-#ifndef MMC_AP4EB_H +-#define MMC_AP4EB_H +- +-#define PORT185CR (void __iomem *)0xe60520b9 +-#define PORT186CR (void __iomem *)0xe60520ba +-#define PORT187CR (void __iomem *)0xe60520bb +-#define PORT188CR (void __iomem *)0xe60520bc +- +-#define PORTR191_160DR (void __iomem *)0xe6056014 +- +-static inline void mmc_init_progress(void) +-{ +- /* Initialise LEDS1-4 +- * registers: PORT185CR-PORT188CR (LED1-LED4 Control) +- * value: 0x10 - enable output +- */ +- __raw_writeb(0x10, PORT185CR); +- __raw_writeb(0x10, PORT186CR); +- __raw_writeb(0x10, PORT187CR); +- __raw_writeb(0x10, PORT188CR); +-} +- +-static inline void mmc_update_progress(int n) +-{ +- __raw_writel((__raw_readl(PORTR191_160DR) & ~(0xf << 25)) | +- (1 << (25 + n)), PORTR191_160DR); +-} +- +-#endif /* MMC_AP4EB_H */ +diff --git a/arch/arm/mach-shmobile/include/mach/mmc.h b/arch/arm/mach-shmobile/include/mach/mmc.h +index 21a59db6..e979b8fc 100644 +--- a/arch/arm/mach-shmobile/include/mach/mmc.h ++++ b/arch/arm/mach-shmobile/include/mach/mmc.h +@@ -7,9 +7,7 @@ + * + **************************************************/ + +-#ifdef CONFIG_MACH_AP4EVB +-#include "mach/mmc-ap4eb.h" +-#elif defined(CONFIG_MACH_MACKEREL) ++#ifdef CONFIG_MACH_MACKEREL + #include "mach/mmc-mackerel.h" + #else + #error "unsupported board." +diff --git a/arch/arm/mach-shmobile/include/mach/zboot.h b/arch/arm/mach-shmobile/include/mach/zboot.h +index 308b5cfd..f2d8744c 100644 +--- a/arch/arm/mach-shmobile/include/mach/zboot.h ++++ b/arch/arm/mach-shmobile/include/mach/zboot.h +@@ -10,11 +10,7 @@ + * + **************************************************/ + +-#ifdef CONFIG_MACH_AP4EVB +-#define MACH_TYPE MACH_TYPE_AP4EVB +-#define MEMORY_START 0x40000000 +-#include "mach/head-ap4evb.txt" +-#elif defined(CONFIG_MACH_MACKEREL) ++#ifdef CONFIG_MACH_MACKEREL + #define MACH_TYPE MACH_TYPE_MACKEREL + #define MEMORY_START 0x40000000 + #include "mach/head-mackerel.txt" +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0293-ARM-shmobile-Remove-Bonito-board-support.patch b/patches.renesas/0293-ARM-shmobile-Remove-Bonito-board-support.patch new file mode 100644 index 00000000000..23383dbb96c --- /dev/null +++ b/patches.renesas/0293-ARM-shmobile-Remove-Bonito-board-support.patch @@ -0,0 +1,655 @@ +From f7ca384488a9c3e6a770865a662be4f0add430f7 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 12 Jun 2013 22:11:46 -0700 +Subject: ARM: shmobile: Remove Bonito board support + +Remove board support for the r8a7740 based Bonito board + +The r8a7740 SoC support code is still kept around since it +is in use by the Armadillo800eva board which is basically a more +recent board where the design is based on Bonito. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 53332005bfde9d2e3c9a66030c0e8c2598eaa1d5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/configs/bonito_defconfig | 72 ----- + arch/arm/mach-shmobile/Kconfig | 6 - + arch/arm/mach-shmobile/Makefile | 1 - + arch/arm/mach-shmobile/Makefile.boot | 1 - + arch/arm/mach-shmobile/board-bonito.c | 502 ---------------------------------- + 5 files changed, 582 deletions(-) + delete mode 100644 arch/arm/configs/bonito_defconfig + delete mode 100644 arch/arm/mach-shmobile/board-bonito.c + +diff --git a/arch/arm/configs/bonito_defconfig b/arch/arm/configs/bonito_defconfig +deleted file mode 100644 +index 54571082..00000000 +--- a/arch/arm/configs/bonito_defconfig ++++ /dev/null +@@ -1,72 +0,0 @@ +-CONFIG_EXPERIMENTAL=y +-CONFIG_SYSVIPC=y +-CONFIG_IKCONFIG=y +-CONFIG_IKCONFIG_PROC=y +-CONFIG_LOG_BUF_SHIFT=16 +-# CONFIG_UTS_NS is not set +-# CONFIG_IPC_NS is not set +-# CONFIG_USER_NS is not set +-# CONFIG_PID_NS is not set +-CONFIG_BLK_DEV_INITRD=y +-CONFIG_INITRAMFS_SOURCE="" +-CONFIG_CC_OPTIMIZE_FOR_SIZE=y +-CONFIG_SLAB=y +-CONFIG_MODULES=y +-CONFIG_MODULE_UNLOAD=y +-CONFIG_MODULE_FORCE_UNLOAD=y +-# CONFIG_BLK_DEV_BSG is not set +-# CONFIG_IOSCHED_DEADLINE is not set +-# CONFIG_IOSCHED_CFQ is not set +-CONFIG_ARCH_SHMOBILE=y +-CONFIG_ARCH_R8A7740=y +-CONFIG_MACH_BONITO=y +-# CONFIG_SH_TIMER_TMU is not set +-CONFIG_AEABI=y +-# CONFIG_OABI_COMPAT is not set +-CONFIG_FORCE_MAX_ZONEORDER=12 +-CONFIG_ZBOOT_ROM_TEXT=0x0 +-CONFIG_ZBOOT_ROM_BSS=0x0 +-CONFIG_CMDLINE="console=ttySC5,115200 earlyprintk=sh-sci.5,115200 ignore_loglevel" +-CONFIG_KEXEC=y +-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +-# CONFIG_SUSPEND is not set +-CONFIG_PM_RUNTIME=y +-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +-# CONFIG_FIRMWARE_IN_KERNEL is not set +-CONFIG_MTD=y +-CONFIG_MTD_CHAR=y +-CONFIG_MTD_BLOCK=y +-CONFIG_MTD_CFI=y +-CONFIG_MTD_CFI_ADV_OPTIONS=y +-CONFIG_MTD_CFI_INTELEXT=y +-CONFIG_MTD_PHYSMAP=y +-CONFIG_MTD_ARM_INTEGRATOR=y +-CONFIG_MTD_BLOCK2MTD=y +-CONFIG_SCSI=y +-CONFIG_BLK_DEV_SD=y +-# CONFIG_SCSI_LOWLEVEL is not set +-# CONFIG_INPUT_KEYBOARD is not set +-# CONFIG_INPUT_MOUSE is not set +-# CONFIG_LEGACY_PTYS is not set +-CONFIG_SERIAL_SH_SCI=y +-CONFIG_SERIAL_SH_SCI_NR_UARTS=9 +-CONFIG_SERIAL_SH_SCI_CONSOLE=y +-# CONFIG_HW_RANDOM is not set +-CONFIG_I2C=y +-CONFIG_I2C_CHARDEV=y +-CONFIG_I2C_SH_MOBILE=y +-CONFIG_GPIO_SYSFS=y +-# CONFIG_HWMON is not set +-# CONFIG_MFD_SUPPORT is not set +-# CONFIG_HID_SUPPORT is not set +-# CONFIG_USB_SUPPORT is not set +-CONFIG_UIO=y +-CONFIG_UIO_PDRV=y +-CONFIG_UIO_PDRV_GENIRQ=y +-# CONFIG_DNOTIFY is not set +-# CONFIG_INOTIFY_USER is not set +-CONFIG_TMPFS=y +-# CONFIG_MISC_FILESYSTEMS is not set +-# CONFIG_ENABLE_WARN_DEPRECATED is not set +-# CONFIG_ENABLE_MUST_CHECK is not set +-# CONFIG_ARM_UNWIND is not set +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index 810af004..4b172453 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -97,12 +97,6 @@ config MACH_KOTA2 + select ARCH_REQUIRE_GPIOLIB + select REGULATOR_FIXED_VOLTAGE if REGULATOR + +-config MACH_BONITO +- bool "bonito board" +- depends on ARCH_R8A7740 +- select ARCH_REQUIRE_GPIOLIB +- select REGULATOR_FIXED_VOLTAGE if REGULATOR +- + config MACH_ARMADILLO800EVA + bool "Armadillo-800 EVA board" + depends on ARCH_R8A7740 +diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile +index 7f81b9a2..6165a517 100644 +--- a/arch/arm/mach-shmobile/Makefile ++++ b/arch/arm/mach-shmobile/Makefile +@@ -39,7 +39,6 @@ obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o + obj-$(CONFIG_MACH_APE6EVM) += board-ape6evm.o + obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o + obj-$(CONFIG_MACH_KOTA2) += board-kota2.o +-obj-$(CONFIG_MACH_BONITO) += board-bonito.o + obj-$(CONFIG_MACH_BOCKW) += board-bockw.o + obj-$(CONFIG_MACH_MARZEN) += board-marzen.o + obj-$(CONFIG_MACH_MARZEN_REFERENCE) += board-marzen-reference.o +diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot +index 3030673e..84c68685 100644 +--- a/arch/arm/mach-shmobile/Makefile.boot ++++ b/arch/arm/mach-shmobile/Makefile.boot +@@ -5,7 +5,6 @@ loadaddr-$(CONFIG_MACH_APE6EVM) += 0x40008000 + loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000 + loadaddr-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += 0x40008000 + loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000 +-loadaddr-$(CONFIG_MACH_BONITO) += 0x40008000 + loadaddr-$(CONFIG_MACH_KOTA2) += 0x41008000 + loadaddr-$(CONFIG_MACH_KZM9D) += 0x40008000 + loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000 +diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c +deleted file mode 100644 +index b373e9ce..00000000 +--- a/arch/arm/mach-shmobile/board-bonito.c ++++ /dev/null +@@ -1,502 +0,0 @@ +-/* +- * bonito board support +- * +- * Copyright (C) 2011 Renesas Solutions Corp. +- * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; version 2 of the License. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +- * +- */ +- +-#include <linux/kernel.h> +-#include <linux/i2c.h> +-#include <linux/init.h> +-#include <linux/interrupt.h> +-#include <linux/irq.h> +-#include <linux/pinctrl/machine.h> +-#include <linux/platform_device.h> +-#include <linux/gpio.h> +-#include <linux/regulator/fixed.h> +-#include <linux/regulator/machine.h> +-#include <linux/smsc911x.h> +-#include <linux/videodev2.h> +-#include <mach/common.h> +-#include <asm/mach-types.h> +-#include <asm/mach/arch.h> +-#include <asm/mach/map.h> +-#include <asm/mach/time.h> +-#include <asm/hardware/cache-l2x0.h> +-#include <mach/r8a7740.h> +-#include <mach/irqs.h> +-#include <video/sh_mobile_lcdc.h> +- +-/* +- * CS Address device note +- *---------------------------------------------------------------- +- * 0 0x0000_0000 NOR Flash (64MB) SW12 : bit3 = OFF +- * 2 0x0800_0000 ExtNOR (64MB) SW12 : bit3 = OFF +- * 4 - +- * 5A - +- * 5B 0x1600_0000 SRAM (8MB) +- * 6 0x1800_0000 FPGA (64K) +- * 0x1801_0000 Ether (4KB) +- * 0x1801_1000 USB (4KB) +- */ +- +-/* +- * SW12 +- * +- * bit1 bit2 bit3 +- *---------------------------------------------------------------------------- +- * ON NOR WriteProtect NAND WriteProtect CS0 ExtNOR / CS2 NOR +- * OFF NOR Not WriteProtect NAND Not WriteProtect CS0 NOR / CS2 ExtNOR +- */ +- +-/* +- * SCIFA5 (CN42) +- * +- * S38.3 = ON +- * S39.6 = ON +- * S43.1 = ON +- */ +- +-/* +- * LCDC0 (CN3/CN4/CN7) +- * +- * S38.1 = OFF +- * S38.2 = OFF +- */ +- +-/* Dummy supplies, where voltage doesn't matter */ +-static struct regulator_consumer_supply dummy_supplies[] = { +- REGULATOR_SUPPLY("vddvario", "smsc911x"), +- REGULATOR_SUPPLY("vdd33a", "smsc911x"), +-}; +- +-/* +- * FPGA +- */ +-#define IRQSR0 0x0020 +-#define IRQSR1 0x0022 +-#define IRQMR0 0x0030 +-#define IRQMR1 0x0032 +-#define BUSSWMR1 0x0070 +-#define BUSSWMR2 0x0072 +-#define BUSSWMR3 0x0074 +-#define BUSSWMR4 0x0076 +- +-#define LCDCR 0x10B4 +-#define DEVRSTCR1 0x10D0 +-#define DEVRSTCR2 0x10D2 +-#define A1MDSR 0x10E0 +-#define BVERR 0x1100 +- +-/* FPGA IRQ */ +-#define FPGA_IRQ_BASE (512) +-#define FPGA_IRQ0 (FPGA_IRQ_BASE) +-#define FPGA_IRQ1 (FPGA_IRQ_BASE + 16) +-#define FPGA_ETH_IRQ (FPGA_IRQ0 + 15) +-static u16 bonito_fpga_read(u32 offset) +-{ +- return __raw_readw(IOMEM(0xf0003000) + offset); +-} +- +-static void bonito_fpga_write(u32 offset, u16 val) +-{ +- __raw_writew(val, IOMEM(0xf0003000) + offset); +-} +- +-static void bonito_fpga_irq_disable(struct irq_data *data) +-{ +- unsigned int irq = data->irq; +- u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1; +- int shift = irq % 16; +- +- bonito_fpga_write(addr, bonito_fpga_read(addr) | (1 << shift)); +-} +- +-static void bonito_fpga_irq_enable(struct irq_data *data) +-{ +- unsigned int irq = data->irq; +- u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1; +- int shift = irq % 16; +- +- bonito_fpga_write(addr, bonito_fpga_read(addr) & ~(1 << shift)); +-} +- +-static struct irq_chip bonito_fpga_irq_chip __read_mostly = { +- .name = "bonito FPGA", +- .irq_mask = bonito_fpga_irq_disable, +- .irq_unmask = bonito_fpga_irq_enable, +-}; +- +-static void bonito_fpga_irq_demux(unsigned int irq, struct irq_desc *desc) +-{ +- u32 val = bonito_fpga_read(IRQSR1) << 16 | +- bonito_fpga_read(IRQSR0); +- u32 mask = bonito_fpga_read(IRQMR1) << 16 | +- bonito_fpga_read(IRQMR0); +- +- int i; +- +- val &= ~mask; +- +- for (i = 0; i < 32; i++) { +- if (!(val & (1 << i))) +- continue; +- +- generic_handle_irq(FPGA_IRQ_BASE + i); +- } +-} +- +-static void bonito_fpga_init(void) +-{ +- int i; +- +- bonito_fpga_write(IRQMR0, 0xffff); /* mask all */ +- bonito_fpga_write(IRQMR1, 0xffff); /* mask all */ +- +- /* Device reset */ +- bonito_fpga_write(DEVRSTCR1, +- (1 << 2)); /* Eth */ +- +- /* FPGA irq require special handling */ +- for (i = FPGA_IRQ_BASE; i < FPGA_IRQ_BASE + 32; i++) { +- irq_set_chip_and_handler_name(i, &bonito_fpga_irq_chip, +- handle_level_irq, "level"); +- set_irq_flags(i, IRQF_VALID); /* yuck */ +- } +- +- irq_set_chained_handler(evt2irq(0x0340), bonito_fpga_irq_demux); +- irq_set_irq_type(evt2irq(0x0340), IRQ_TYPE_LEVEL_LOW); +-} +- +-/* +-* PMIC settings +-* +-* FIXME +-* +-* bonito board needs some settings by pmic which use i2c access. +-* pmic settings use device_initcall() here for use it. +-*/ +-static __u8 *pmic_settings = NULL; +-static __u8 pmic_do_2A[] = { +- 0x1C, 0x09, +- 0x1A, 0x80, +- 0xff, 0xff, +-}; +- +-static int __init pmic_init(void) +-{ +- struct i2c_adapter *a = i2c_get_adapter(0); +- struct i2c_msg msg; +- __u8 buf[2]; +- int i, ret; +- +- if (!pmic_settings) +- return 0; +- if (!a) +- return 0; +- +- msg.addr = 0x46; +- msg.buf = buf; +- msg.len = 2; +- msg.flags = 0; +- +- for (i = 0; ; i += 2) { +- buf[0] = pmic_settings[i + 0]; +- buf[1] = pmic_settings[i + 1]; +- +- if ((0xff == buf[0]) && (0xff == buf[1])) +- break; +- +- ret = i2c_transfer(a, &msg, 1); +- if (ret < 0) { +- pr_err("i2c transfer fail\n"); +- break; +- } +- } +- +- return 0; +-} +-device_initcall(pmic_init); +- +-/* +- * LCDC0 +- */ +-static const struct fb_videomode lcdc0_mode = { +- .name = "WVGA Panel", +- .xres = 800, +- .yres = 480, +- .left_margin = 88, +- .right_margin = 40, +- .hsync_len = 128, +- .upper_margin = 20, +- .lower_margin = 5, +- .vsync_len = 5, +- .sync = 0, +-}; +- +-static struct sh_mobile_lcdc_info lcdc0_info = { +- .clock_source = LCDC_CLK_BUS, +- .ch[0] = { +- .chan = LCDC_CHAN_MAINLCD, +- .fourcc = V4L2_PIX_FMT_RGB565, +- .interface_type = RGB24, +- .clock_divider = 5, +- .flags = 0, +- .lcd_modes = &lcdc0_mode, +- .num_modes = 1, +- .panel_cfg = { +- .width = 152, +- .height = 91, +- }, +- }, +-}; +- +-static struct resource lcdc0_resources[] = { +- [0] = { +- .name = "LCDC0", +- .start = 0xfe940000, +- .end = 0xfe943fff, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = intcs_evt2irq(0x0580), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device lcdc0_device = { +- .name = "sh_mobile_lcdc_fb", +- .id = 0, +- .resource = lcdc0_resources, +- .num_resources = ARRAY_SIZE(lcdc0_resources), +- .dev = { +- .platform_data = &lcdc0_info, +- .coherent_dma_mask = ~0, +- }, +-}; +- +-static const struct pinctrl_map lcdc0_pinctrl_map[] = { +- /* LCD0 */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740", +- "lcd0_data24_1", "lcd0"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740", +- "lcd0_lclk_1", "lcd0"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740", +- "lcd0_sync", "lcd0"), +-}; +- +-/* +- * SMSC 9221 +- */ +-static struct resource smsc_resources[] = { +- [0] = { +- .start = 0x18010000, +- .end = 0x18011000 - 1, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = FPGA_ETH_IRQ, +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct smsc911x_platform_config smsc_platdata = { +- .flags = SMSC911X_USE_16BIT, +- .phy_interface = PHY_INTERFACE_MODE_MII, +- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, +- .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, +-}; +- +-static struct platform_device smsc_device = { +- .name = "smsc911x", +- .dev = { +- .platform_data = &smsc_platdata, +- }, +- .resource = smsc_resources, +- .num_resources = ARRAY_SIZE(smsc_resources), +-}; +- +-/* +- * base board devices +- */ +-static struct platform_device *bonito_base_devices[] __initdata = { +- &lcdc0_device, +- &smsc_device, +-}; +- +-/* +- * map I/O +- */ +-static struct map_desc bonito_io_desc[] __initdata = { +- /* +- * for FPGA (0x1800000-0x19ffffff) +- * 0x18000000-0x18002000 -> 0xf0003000-0xf0005000 +- */ +- { +- .virtual = 0xf0003000, +- .pfn = __phys_to_pfn(0x18000000), +- .length = PAGE_SIZE * 2, +- .type = MT_DEVICE_NONSHARED +- } +-}; +- +-static void __init bonito_map_io(void) +-{ +- r8a7740_map_io(); +- iotable_init(bonito_io_desc, ARRAY_SIZE(bonito_io_desc)); +-} +- +-/* +- * board init +- */ +-#define BIT_ON(sw, bit) (sw & (1 << bit)) +-#define BIT_OFF(sw, bit) (!(sw & (1 << bit))) +- +-#define VCCQ1CR IOMEM(0xE6058140) +-#define VCCQ1LCDCR IOMEM(0xE6058186) +- +-/* +- * HACK: The FPGA mappings should be associated with the FPGA device, but we +- * don't have one at the moment. Associate them with the PFC device to make +- * sure they will be applied. +- */ +-static const struct pinctrl_map fpga_pinctrl_map[] = { +- /* FPGA */ +- PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740", +- "bsc_cs5a_0", "bsc"), +- PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740", +- "bsc_cs5b", "bsc"), +- PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740", +- "bsc_cs6a", "bsc"), +- PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740", +- "intc_irq10", "intc"), +-}; +- +-static const struct pinctrl_map scifa5_pinctrl_map[] = { +- /* SCIFA5 */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.5", "pfc-r8a7740", +- "scifa5_data_2", "scifa5"), +-}; +- +-static void __init bonito_init(void) +-{ +- u16 val; +- +- regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); +- +- pinctrl_register_mappings(fpga_pinctrl_map, +- ARRAY_SIZE(fpga_pinctrl_map)); +- r8a7740_pinmux_init(); +- bonito_fpga_init(); +- +- pmic_settings = pmic_do_2A; +- +- /* +- * core board settings +- */ +- +-#ifdef CONFIG_CACHE_L2X0 +- /* Early BRESP enable, Shared attribute override enable, 32K*8way */ +- l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff); +-#endif +- +- r8a7740_add_standard_devices(); +- +- /* +- * base board settings +- */ +- gpio_request_one(176, GPIOF_IN, NULL); +- if (!gpio_get_value(176)) { +- u16 bsw2; +- u16 bsw3; +- u16 bsw4; +- +- val = bonito_fpga_read(BVERR); +- pr_info("bonito version: cpu %02x, base %02x\n", +- ((val >> 8) & 0xFF), +- ((val >> 0) & 0xFF)); +- +- bsw2 = bonito_fpga_read(BUSSWMR2); +- bsw3 = bonito_fpga_read(BUSSWMR3); +- bsw4 = bonito_fpga_read(BUSSWMR4); +- +- /* +- * SCIFA5 (CN42) +- */ +- if (BIT_OFF(bsw2, 1) && /* S38.3 = ON */ +- BIT_OFF(bsw3, 9) && /* S39.6 = ON */ +- BIT_OFF(bsw4, 4)) { /* S43.1 = ON */ +- pinctrl_register_mappings(scifa5_pinctrl_map, +- ARRAY_SIZE(scifa5_pinctrl_map)); +- } +- +- /* +- * LCDC0 (CN3) +- */ +- if (BIT_ON(bsw2, 3) && /* S38.1 = OFF */ +- BIT_ON(bsw2, 2)) { /* S38.2 = OFF */ +- pinctrl_register_mappings(lcdc0_pinctrl_map, +- ARRAY_SIZE(lcdc0_pinctrl_map)); +- +- gpio_request_one(61, GPIOF_OUT_INIT_HIGH, +- NULL); /* LCDDON */ +- +- /* backlight on */ +- bonito_fpga_write(LCDCR, 1); +- +- /* drivability Max */ +- __raw_writew(0x00FF , VCCQ1LCDCR); +- __raw_writew(0xFFFF , VCCQ1CR); +- } +- +- platform_add_devices(bonito_base_devices, +- ARRAY_SIZE(bonito_base_devices)); +- } +-} +- +-static void __init bonito_earlytimer_init(void) +-{ +- u16 val; +- u8 md_ck = 0; +- +- /* read MD_CK value */ +- val = bonito_fpga_read(A1MDSR); +- if (val & (1 << 10)) +- md_ck |= MD_CK2; +- if (val & (1 << 9)) +- md_ck |= MD_CK1; +- if (val & (1 << 8)) +- md_ck |= MD_CK0; +- +- r8a7740_clock_init(md_ck); +- shmobile_earlytimer_init(); +-} +- +-static void __init bonito_add_early_devices(void) +-{ +- r8a7740_add_early_devices(); +-} +- +-MACHINE_START(BONITO, "bonito") +- .map_io = bonito_map_io, +- .init_early = bonito_add_early_devices, +- .init_irq = r8a7740_init_irq, +- .handle_irq = shmobile_handle_irq_intc, +- .init_machine = bonito_init, +- .init_late = shmobile_init_late, +- .init_time = bonito_earlytimer_init, +-MACHINE_END +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0294-ARM-shmobile-r8a7790-HSCIF-support.patch b/patches.renesas/0294-ARM-shmobile-r8a7790-HSCIF-support.patch new file mode 100644 index 00000000000..ffc406a668d --- /dev/null +++ b/patches.renesas/0294-ARM-shmobile-r8a7790-HSCIF-support.patch @@ -0,0 +1,61 @@ +From a6d416b5d5e41fa04fc00cd156c6c5615eff5da3 Mon Sep 17 00:00:00 2001 +From: Ulrich Hecht <ulrich.hecht@gmail.com> +Date: Fri, 31 May 2013 17:57:02 +0200 +Subject: ARM: shmobile: r8a7790: HSCIF support + +Adds support for HSCIF0 and HSCIF1 on the r8a7790. + +Signed-off-by: Ulrich Hecht <ulrich.hecht@gmail.com> +[ horms+renesas@verge.net.au this is the setup-r8a7790.c + which I somehow miss-applied as part of another patch. + The clock-r8a7790.c portion of this patch has already been merged. ] +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit d44f8308cf7a65f4c97a041da07d872aefe47ca7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a7790.c | 14 +++++++++++++- + 1 file changed, 13 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c +index 196bd732..2d0c9bfd 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7790.c ++++ b/arch/arm/mach-shmobile/setup-r8a7790.c +@@ -101,7 +101,15 @@ void __init r8a7790_pinmux_init(void) + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ + } + +-enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1 }; ++#define HSCIF_DATA(index, baseaddr, irq) \ ++[index] = { \ ++ SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \ ++ .scbrr_algo_id = SCBRR_ALGO_6, \ ++ .scscr = SCSCR_RE | SCSCR_TE, \ ++} ++ ++enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1, ++ HSCIF0, HSCIF1 }; + + static struct plat_sci_port scif[] __initdata = { + SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ +@@ -112,6 +120,8 @@ static struct plat_sci_port scif[] __initdata = { + SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */ + SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */ + SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */ ++ HSCIF_DATA(HSCIF0, 0xe62c0000, gic_spi(154)), /* HSCIF0 */ ++ HSCIF_DATA(HSCIF1, 0xe62c8000, gic_spi(155)), /* HSCIF1 */ + }; + + static inline void r8a7790_register_scif(int idx) +@@ -149,6 +159,8 @@ void __init r8a7790_add_standard_devices(void) + r8a7790_register_scif(SCIFA2); + r8a7790_register_scif(SCIF0); + r8a7790_register_scif(SCIF1); ++ r8a7790_register_scif(HSCIF0); ++ r8a7790_register_scif(HSCIF1); + r8a7790_register_irqc(0); + } + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0295-ARM-shmobile-r8a7790-don-t-use-external-clock-for-SC.patch b/patches.renesas/0295-ARM-shmobile-r8a7790-don-t-use-external-clock-for-SC.patch new file mode 100644 index 00000000000..e939d4e81ff --- /dev/null +++ b/patches.renesas/0295-ARM-shmobile-r8a7790-don-t-use-external-clock-for-SC.patch @@ -0,0 +1,32 @@ +From 7914e359e3d902825f0cecdb5a8f0cef6fd37b3d Mon Sep 17 00:00:00 2001 +From: Ulrich Hecht <ulrich.hecht@gmail.com> +Date: Fri, 31 May 2013 17:57:04 +0200 +Subject: ARM: shmobile: r8a7790: don't use external clock for SCIFs + +This is an external component and may or may not be there, while the +internal clock always works. + +Signed-off-by: Ulrich Hecht <ulrich.hecht@gmail.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit c972f024c1097fa0798beafc21be1eeeba21ac34) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a7790.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c +index 2d0c9bfd..28f94752 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7790.c ++++ b/arch/arm/mach-shmobile/setup-r8a7790.c +@@ -98,7 +98,7 @@ void __init r8a7790_pinmux_init(void) + [index] = { \ + SCIF_COMMON(PORT_SCIF, baseaddr, irq), \ + .scbrr_algo_id = SCBRR_ALGO_2, \ +- .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ ++ .scscr = SCSCR_RE | SCSCR_TE, \ + } + + #define HSCIF_DATA(index, baseaddr, irq) \ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0296-sh-pfc-r8a7778-tidyup-MMC_D1-pin.patch b/patches.renesas/0296-sh-pfc-r8a7778-tidyup-MMC_D1-pin.patch new file mode 100644 index 00000000000..27b67515db4 --- /dev/null +++ b/patches.renesas/0296-sh-pfc-r8a7778-tidyup-MMC_D1-pin.patch @@ -0,0 +1,38 @@ +From e3b8b951fc7f0ddd1fbe1d2994aa79de244b2ebb Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 11 Jun 2013 19:02:20 -0700 +Subject: sh-pfc: r8a7778: tidyup MMC_D1 pin + +MMC_D1 is RCAR_GP_PIN(1, 8), not RCAR_GP_PIN(2, 8) + +Reported-by: Yusuke Goda <yusuke.goda.sx@renesas.com> +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit cd622017eb3e0ab841502df88fb7fda3c3a58eb9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +index 1dcbabcd..f9039102 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +@@ -1447,11 +1447,11 @@ MMC_PFC_PINS(mmc_ctrl, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6)); + MMC_PFC_CTRL(mmc_ctrl, MMC_CLK, MMC_CMD); + MMC_PFC_PINS(mmc_data1, RCAR_GP_PIN(1, 7)); + MMC_PFC_DAT1(mmc_data1, MMC_D0); +-MMC_PFC_PINS(mmc_data4, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(2, 8), ++MMC_PFC_PINS(mmc_data4, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6)); + MMC_PFC_DAT4(mmc_data4, MMC_D0, MMC_D1, + MMC_D2, MMC_D3); +-MMC_PFC_PINS(mmc_data8, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(2, 8), ++MMC_PFC_PINS(mmc_data8, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0), + RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31)); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0297-ARM-shmobile-sh73a0-remove-0x-prefix-from-DT-node-na.patch b/patches.renesas/0297-ARM-shmobile-sh73a0-remove-0x-prefix-from-DT-node-na.patch new file mode 100644 index 00000000000..2813e87ffc2 --- /dev/null +++ b/patches.renesas/0297-ARM-shmobile-sh73a0-remove-0x-prefix-from-DT-node-na.patch @@ -0,0 +1,105 @@ +From 3c5caca84217d2ce39fdf2423b9432add0a9b3c1 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Thu, 6 Jun 2013 17:38:12 +0200 +Subject: ARM: shmobile: sh73a0: remove "0x" prefix from DT node names + +The convention for Device Tree node names is <device>@<hex-address>, where +the part after '@' shouldn't contain the "0x" prefix. Fix the sh73a0.dtsi +DT names. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 561a1a31d232d0f2b1ce7b7480bd03aba97e818d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/sh73a0.dtsi | 18 +++++++++--------- + 1 file changed, 9 insertions(+), 9 deletions(-) + +diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi +index ec40bf78..b9775025 100644 +--- a/arch/arm/boot/dts/sh73a0.dtsi ++++ b/arch/arm/boot/dts/sh73a0.dtsi +@@ -119,7 +119,7 @@ + 0 32 0x4>; + }; + +- i2c0: i2c@0xe6820000 { ++ i2c0: i2c@e6820000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,rmobile-iic"; +@@ -131,7 +131,7 @@ + 0 170 0x4>; + }; + +- i2c1: i2c@0xe6822000 { ++ i2c1: i2c@e6822000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,rmobile-iic"; +@@ -143,7 +143,7 @@ + 0 54 0x4>; + }; + +- i2c2: i2c@0xe6824000 { ++ i2c2: i2c@e6824000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,rmobile-iic"; +@@ -155,7 +155,7 @@ + 0 174 0x4>; + }; + +- i2c3: i2c@0xe6826000 { ++ i2c3: i2c@e6826000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,rmobile-iic"; +@@ -167,7 +167,7 @@ + 0 186 0x4>; + }; + +- i2c4: i2c@0xe6828000 { ++ i2c4: i2c@e6828000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,rmobile-iic"; +@@ -179,7 +179,7 @@ + 0 190 0x4>; + }; + +- mmcif: mmcif@0x10010000 { ++ mmcif: mmcif@e6bd0000 { + compatible = "renesas,sh-mmcif"; + reg = <0xe6bd0000 0x100>; + interrupt-parent = <&gic>; +@@ -189,7 +189,7 @@ + status = "disabled"; + }; + +- sdhi0: sdhi@0xee100000 { ++ sdhi0: sdhi@ee100000 { + compatible = "renesas,r8a7740-sdhi"; + reg = <0xee100000 0x100>; + interrupt-parent = <&gic>; +@@ -201,7 +201,7 @@ + }; + + /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */ +- sdhi1: sdhi@0xee120000 { ++ sdhi1: sdhi@ee120000 { + compatible = "renesas,r8a7740-sdhi"; + reg = <0xee120000 0x100>; + interrupt-parent = <&gic>; +@@ -212,7 +212,7 @@ + status = "disabled"; + }; + +- sdhi2: sdhi@0xee140000 { ++ sdhi2: sdhi@ee140000 { + compatible = "renesas,r8a7740-sdhi"; + reg = <0xee140000 0x100>; + interrupt-parent = <&gic>; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0298-ARM-shmobile-BOCK-W-change-Ether-device-name.patch b/patches.renesas/0298-ARM-shmobile-BOCK-W-change-Ether-device-name.patch new file mode 100644 index 00000000000..e73bc6ea535 --- /dev/null +++ b/patches.renesas/0298-ARM-shmobile-BOCK-W-change-Ether-device-name.patch @@ -0,0 +1,36 @@ +From b6c7ac07a8e3fd5d5e3b4e4a125e76bbb8ac7719 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Mon, 17 Jun 2013 23:39:44 +0400 +Subject: ARM: shmobile: BOCK-W: change Ether device name + +When changing the name of Ether platform device in the commit c02f846938fe (ARM: +shmobile: r8a7778: fix Ether device name), I completely forgot that there's also +platform device name used in bockw_pinctrl_map[], so the commit "ARM: shmobile: +BOCK-W: add Ether support" went in with the old "sh-eth" device name. Now change +it to "r8a777x-ether" in accordance with the commits that are now in the 'net- +next.git' repository, otherwise BOCK-W Ether support won't work in 3.11. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 2c83322ce820bcf2d5e8265de831489076ee211e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-bockw.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c +index 394186c7..9936ad2e 100644 +--- a/arch/arm/mach-shmobile/board-bockw.c ++++ b/arch/arm/mach-shmobile/board-bockw.c +@@ -144,7 +144,7 @@ static struct sh_mmcif_plat_data sh_mmcif_plat = { + + static const struct pinctrl_map bockw_pinctrl_map[] = { + /* Ether */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7778", ++ PIN_MAP_MUX_GROUP_DEFAULT("r8a777x-ether", "pfc-r8a7778", + "ether_rmii", "ether"), + /* HSPI0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7778", +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0299-sh-pfc-Remove-support-for-platform-data.patch b/patches.renesas/0299-sh-pfc-Remove-support-for-platform-data.patch new file mode 100644 index 00000000000..159bf866142 --- /dev/null +++ b/patches.renesas/0299-sh-pfc-Remove-support-for-platform-data.patch @@ -0,0 +1,33 @@ +From 5a917f417b768b883512ea9aaf586dcf0797fd57 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 17 Jun 2013 20:50:01 +0200 +Subject: sh-pfc: Remove support for platform data + +Platform data isn't used, support can thus be removed. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Acked-by: Heiko Stuebner <heiko@sntech.de> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit 3a7f520e63727e14de9567515d8727c2c01fedb4) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/core.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c +index 3b2fd43f..ac45084f 100644 +--- a/drivers/pinctrl/sh-pfc/core.c ++++ b/drivers/pinctrl/sh-pfc/core.c +@@ -354,8 +354,7 @@ static int sh_pfc_probe(struct platform_device *pdev) + struct sh_pfc *pfc; + int ret; + +- info = pdev->id_entry->driver_data +- ? (void *)pdev->id_entry->driver_data : pdev->dev.platform_data; ++ info = (void *)pdev->id_entry->driver_data; + if (info == NULL) + return -ENODEV; + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0300-sh-pfc-Add-DT-support.patch b/patches.renesas/0300-sh-pfc-Add-DT-support.patch new file mode 100644 index 00000000000..8b900cfb893 --- /dev/null +++ b/patches.renesas/0300-sh-pfc-Add-DT-support.patch @@ -0,0 +1,403 @@ +From a6e7b7582b2e310c287e76215d1226a23b2e2d01 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 17 Jun 2013 20:50:02 +0200 +Subject: sh-pfc: Add DT support + +Support device instantiation through the device tree. The compatible +property is used to select the SoC pinmux information. + +Set the gpio_chip device field to the PFC device to enable automatic +GPIO OF support. + +Cc: devicetree-discuss@lists.ozlabs.org +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Acked-by: Heiko Stuebner <heiko@sntech.de> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit fe1c9a822ce72c6ec8476a2501c412265ee2172c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + .../bindings/pinctrl/renesas,pfc-pinctrl.txt | 135 +++++++++++++++++++++ + drivers/pinctrl/sh-pfc/core.c | 64 +++++++++- + drivers/pinctrl/sh-pfc/pinctrl.c | 116 ++++++++++++++++++ + 3 files changed, 314 insertions(+), 1 deletion(-) + create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt + +diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +new file mode 100644 +index 00000000..8264cbcd +--- /dev/null ++++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +@@ -0,0 +1,135 @@ ++* Renesas Pin Function Controller (GPIO and Pin Mux/Config) ++ ++The Pin Function Controller (PFC) is a Pin Mux/Config controller. On SH7372, ++SH73A0, R8A73A4 and R8A7740 it also acts as a GPIO controller. ++ ++ ++Pin Control ++----------- ++ ++Required Properties: ++ ++ - compatible: should be one of the following. ++ - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller. ++ - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller. ++ - "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller. ++ - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller. ++ - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller. ++ - "renesas,pfc-sh7372": for SH7372 (SH-Mobile AP4) compatible pin-controller. ++ - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller. ++ ++ - reg: Base address and length of each memory resource used by the pin ++ controller hardware module. ++ ++Optional properties: ++ ++ - #gpio-range-cells: Mandatory when the PFC doesn't handle GPIO, forbidden ++ otherwise. Should be 3. ++ ++The PFC node also acts as a container for pin configuration nodes. Please refer ++to pinctrl-bindings.txt in this directory for the definition of the term "pin ++configuration node" and for the common pinctrl bindings used by client devices. ++ ++Each pin configuration node represents desired functions to select on a pin ++group or a list of pin groups. The functions and pin groups can be specified ++directly in the pin configuration node, or grouped in child subnodes. Several ++functions can thus be referenced as a single pin configuration node by client ++devices. ++ ++A configuration node or subnode must contain a function and reference at least ++one pin group. ++ ++All pin configuration nodes and subnodes names are ignored. All of those nodes ++are parsed through phandles and processed purely based on their content. ++ ++Pin Configuration Node Properties: ++ ++- renesas,groups : An array of strings, each string containing the name of a pin ++ group. ++ ++- renesas,function: A string containing the name of the function to mux to the ++ pin group(s) specified by the renesas,groups property ++ ++ Valid values for pin, group and function names can be found in the group and ++ function arrays of the PFC data file corresponding to the SoC ++ (drivers/pinctrl/sh-pfc/pfc-*.c) ++ ++ ++GPIO ++---- ++ ++On SH7372, SH73A0, R8A73A4 and R8A7740 the PFC node is also a GPIO controller ++node. ++ ++Required Properties: ++ ++ - gpio-controller: Marks the device node as a gpio controller. ++ ++ - #gpio-cells: Should be 2. The first cell is the GPIO number and the second ++ cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the ++ GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported. ++ ++The syntax of the gpio specifier used by client nodes should be the following ++with values derived from the SoC user manual. ++ ++ <[phandle of the gpio controller node] ++ [pin number within the gpio controller] ++ [flags]> ++ ++On other mach-shmobile platforms GPIO is handled by the gpio-rcar driver. ++Please refer to Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt ++for documentation of the GPIO device tree bindings on those platforms. ++ ++ ++Examples ++-------- ++ ++Example 1: SH73A0 (SH-Mobile AG5) pin controller node ++ ++ pfc: pfc@e6050000 { ++ compatible = "renesas,pfc-sh73a0"; ++ reg = <0xe6050000 0x8000>, ++ <0xe605801c 0x1c>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; ++ ++Example 2: A GPIO LED node that references a GPIO ++ ++ #include <dt-bindings/gpio/gpio.h> ++ ++ leds { ++ compatible = "gpio-leds"; ++ led1 { ++ gpios = <&pfc 20 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++Example 3: KZM-A9-GT (SH-Mobile AG5) default pin state hog and pin control maps ++ for the MMCIF and SCIFA4 devices ++ ++ &pfc { ++ pinctrl-0 = <&scifa4_pins>; ++ pinctrl-names = "default"; ++ ++ mmcif_pins: mmcif { ++ renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0"; ++ renesas,function = "mmc0"; ++ }; ++ ++ scifa4_pins: scifa4 { ++ renesas,groups = "scifa4_data", "scifa4_ctrl"; ++ renesas,function = "scifa4"; ++ }; ++ }; ++ ++Example 4: KZM-A9-GT (SH-Mobile AG5) default pin state for the MMCIF device ++ ++ &mmcif { ++ pinctrl-0 = <&mmcif_pins>; ++ pinctrl-names = "default"; ++ ++ bus-width = <8>; ++ vmmc-supply = <®_1p8v>; ++ status = "okay"; ++ }; +diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c +index ac45084f..f3fc66b2 100644 +--- a/drivers/pinctrl/sh-pfc/core.c ++++ b/drivers/pinctrl/sh-pfc/core.c +@@ -18,6 +18,8 @@ + #include <linux/ioport.h> + #include <linux/kernel.h> + #include <linux/module.h> ++#include <linux/of.h> ++#include <linux/of_device.h> + #include <linux/pinctrl/machine.h> + #include <linux/platform_device.h> + #include <linux/slab.h> +@@ -348,13 +350,72 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) + return 0; + } + ++#ifdef CONFIG_OF ++static const struct of_device_id sh_pfc_of_table[] = { ++#ifdef CONFIG_PINCTRL_PFC_R8A73A4 ++ { ++ .compatible = "renesas,pfc-r8a73a4", ++ .data = &r8a73a4_pinmux_info, ++ }, ++#endif ++#ifdef CONFIG_PINCTRL_PFC_R8A7740 ++ { ++ .compatible = "renesas,pfc-r8a7740", ++ .data = &r8a7740_pinmux_info, ++ }, ++#endif ++#ifdef CONFIG_PINCTRL_PFC_R8A7778 ++ { ++ .compatible = "renesas,pfc-r8a7778", ++ .data = &r8a7778_pinmux_info, ++ }, ++#endif ++#ifdef CONFIG_PINCTRL_PFC_R8A7779 ++ { ++ .compatible = "renesas,pfc-r8a7779", ++ .data = &r8a7779_pinmux_info, ++ }, ++#endif ++#ifdef CONFIG_PINCTRL_PFC_R8A7790 ++ { ++ .compatible = "renesas,pfc-r8a7790", ++ .data = &r8a7790_pinmux_info, ++ }, ++#endif ++#ifdef CONFIG_PINCTRL_PFC_SH7372 ++ { ++ .compatible = "renesas,pfc-sh7372", ++ .data = &sh7372_pinmux_info, ++ }, ++#endif ++#ifdef CONFIG_PINCTRL_PFC_SH73A0 ++ { ++ .compatible = "renesas,pfc-sh73a0", ++ .data = &sh73a0_pinmux_info, ++ }, ++#endif ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, sh_pfc_of_table); ++#endif ++ + static int sh_pfc_probe(struct platform_device *pdev) + { ++ const struct platform_device_id *platid = platform_get_device_id(pdev); ++#ifdef CONFIG_OF ++ struct device_node *np = pdev->dev.of_node; ++#endif + const struct sh_pfc_soc_info *info; + struct sh_pfc *pfc; + int ret; + +- info = (void *)pdev->id_entry->driver_data; ++#ifdef CONFIG_OF ++ if (np) ++ info = of_match_device(sh_pfc_of_table, &pdev->dev)->data; ++ else ++#endif ++ info = platid ? (const void *)platid->driver_data : NULL; ++ + if (info == NULL) + return -ENODEV; + +@@ -500,6 +561,7 @@ static struct platform_driver sh_pfc_driver = { + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(sh_pfc_of_table), + }, + }; + +diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c +index 3492ec9a..7e32bb8c 100644 +--- a/drivers/pinctrl/sh-pfc/pinctrl.c ++++ b/drivers/pinctrl/sh-pfc/pinctrl.c +@@ -14,7 +14,9 @@ + #include <linux/err.h> + #include <linux/init.h> + #include <linux/module.h> ++#include <linux/of.h> + #include <linux/pinctrl/consumer.h> ++#include <linux/pinctrl/machine.h> + #include <linux/pinctrl/pinconf.h> + #include <linux/pinctrl/pinconf-generic.h> + #include <linux/pinctrl/pinctrl.h> +@@ -72,11 +74,125 @@ static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, + seq_printf(s, "%s", DRV_NAME); + } + ++static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np, ++ struct pinctrl_map **map, ++ unsigned int *num_maps, unsigned int *index) ++{ ++ struct pinctrl_map *maps = *map; ++ unsigned int nmaps = *num_maps; ++ unsigned int idx = *index; ++ const char *function = NULL; ++ struct property *prop; ++ const char *group; ++ int ret; ++ ++ /* Parse the function and configuration properties. At least a function ++ * or one configuration must be specified. ++ */ ++ ret = of_property_read_string(np, "renesas,function", &function); ++ if (ret < 0 && ret != -EINVAL) { ++ dev_err(dev, "Invalid function in DT\n"); ++ return ret; ++ } ++ ++ if (!function) { ++ dev_err(dev, "DT node must contain at least one function\n"); ++ goto done; ++ } ++ ++ /* Count the number of groups and reallocate mappings. */ ++ ret = of_property_count_strings(np, "renesas,groups"); ++ if (ret < 0 && ret != -EINVAL) { ++ dev_err(dev, "Invalid pin groups list in DT\n"); ++ goto done; ++ } ++ ++ if (!ret) { ++ dev_err(dev, "No group provided in DT node\n"); ++ ret = -ENODEV; ++ goto done; ++ } ++ ++ nmaps += ret; ++ ++ maps = krealloc(maps, sizeof(*maps) * nmaps, GFP_KERNEL); ++ if (maps == NULL) { ++ ret = -ENOMEM; ++ goto done; ++ } ++ ++ *map = maps; ++ *num_maps = nmaps; ++ ++ /* Iterate over pins and groups and create the mappings. */ ++ of_property_for_each_string(np, "renesas,groups", prop, group) { ++ maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; ++ maps[idx].data.mux.group = group; ++ maps[idx].data.mux.function = function; ++ idx++; ++ } ++ ++ ret = 0; ++ ++done: ++ *index = idx; ++ return ret; ++} ++ ++static void sh_pfc_dt_free_map(struct pinctrl_dev *pctldev, ++ struct pinctrl_map *map, unsigned num_maps) ++{ ++ kfree(map); ++} ++ ++static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev, ++ struct device_node *np, ++ struct pinctrl_map **map, unsigned *num_maps) ++{ ++ struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); ++ struct device *dev = pmx->pfc->dev; ++ struct device_node *child; ++ unsigned int index; ++ int ret; ++ ++ *map = NULL; ++ *num_maps = 0; ++ index = 0; ++ ++ for_each_child_of_node(np, child) { ++ ret = sh_pfc_dt_subnode_to_map(dev, child, map, num_maps, ++ &index); ++ if (ret < 0) ++ goto done; ++ } ++ ++ /* If no mapping has been found in child nodes try the config node. */ ++ if (*num_maps == 0) { ++ ret = sh_pfc_dt_subnode_to_map(dev, np, map, num_maps, &index); ++ if (ret < 0) ++ goto done; ++ } ++ ++ if (*num_maps) ++ return 0; ++ ++ dev_err(dev, "no mapping found in node %s\n", np->full_name); ++ ret = -EINVAL; ++ ++done: ++ if (ret < 0) ++ sh_pfc_dt_free_map(pctldev, *map, *num_maps); ++ ++ return ret; ++} ++ + static const struct pinctrl_ops sh_pfc_pinctrl_ops = { + .get_groups_count = sh_pfc_get_groups_count, + .get_group_name = sh_pfc_get_group_name, + .get_group_pins = sh_pfc_get_group_pins, + .pin_dbg_show = sh_pfc_pin_dbg_show, ++ .dt_node_to_map = sh_pfc_dt_node_to_map, ++ .dt_free_map = sh_pfc_dt_free_map, + }; + + static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0301-pinconf-generic-add-BIAS_BUS_HOLD-pinconf.patch b/patches.renesas/0301-pinconf-generic-add-BIAS_BUS_HOLD-pinconf.patch new file mode 100644 index 00000000000..0797b7accfb --- /dev/null +++ b/patches.renesas/0301-pinconf-generic-add-BIAS_BUS_HOLD-pinconf.patch @@ -0,0 +1,60 @@ +From 6a9c565246933b4d277cc31dd152f9b46eb58b28 Mon Sep 17 00:00:00 2001 +From: James Hogan <james.hogan@imgtec.com> +Date: Fri, 24 May 2013 17:21:12 +0100 +Subject: pinconf-generic: add BIAS_BUS_HOLD pinconf + +Add a new PIN_CONFIG_BIAS_BUS_HOLD pin configuration for a bus holder +pin mode (also known as bus keeper, or repeater). This is a weak latch +which drives the last value on a tristate bus. Another device on the bus +can drive the bus high or low before going tristate to change the value +driven by the pin. + +Signed-off-by: James Hogan <james.hogan@imgtec.com> +Cc: Linus Walleij <linus.walleij@linaro.org> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit a2df4269cad79635201587c5c5404f0b1cb0b05c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/pinconf-generic.c | 1 + + include/linux/pinctrl/pinconf-generic.h | 6 ++++++ + 2 files changed, 7 insertions(+) + +diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c +index 2ad5a8d3..7c593dbd 100644 +--- a/drivers/pinctrl/pinconf-generic.c ++++ b/drivers/pinctrl/pinconf-generic.c +@@ -37,6 +37,7 @@ struct pin_config_item { + static struct pin_config_item conf_items[] = { + PCONFDUMP(PIN_CONFIG_BIAS_DISABLE, "input bias disabled", NULL), + PCONFDUMP(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, "input bias high impedance", NULL), ++ PCONFDUMP(PIN_CONFIG_BIAS_BUS_HOLD, "input bias bus hold", NULL), + PCONFDUMP(PIN_CONFIG_BIAS_PULL_UP, "input bias pull up", NULL), + PCONFDUMP(PIN_CONFIG_BIAS_PULL_DOWN, "input bias pull down", NULL), + PCONFDUMP(PIN_CONFIG_DRIVE_PUSH_PULL, "output drive push pull", NULL), +diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h +index 6aa23809..ac05b3cf 100644 +--- a/include/linux/pinctrl/pinconf-generic.h ++++ b/include/linux/pinctrl/pinconf-generic.h +@@ -29,6 +29,11 @@ + * if for example some other pin is going to drive the signal connected + * to it for a while. Pins used for input are usually always high + * impedance. ++ * @PIN_CONFIG_BIAS_BUS_HOLD: the pin will be set to weakly latch so that it ++ * weakly drives the last value on a tristate bus, also known as a "bus ++ * holder", "bus keeper" or "repeater". This allows another device on the ++ * bus to change the value by driving the bus high or low and switching to ++ * tristate. The argument is ignored. + * @PIN_CONFIG_BIAS_PULL_UP: the pin will be pulled up (usually with high + * impedance to VDD). If the argument is != 0 pull-up is enabled, + * if it is 0, pull-up is disabled. +@@ -78,6 +83,7 @@ + enum pin_config_param { + PIN_CONFIG_BIAS_DISABLE, + PIN_CONFIG_BIAS_HIGH_IMPEDANCE, ++ PIN_CONFIG_BIAS_BUS_HOLD, + PIN_CONFIG_BIAS_PULL_UP, + PIN_CONFIG_BIAS_PULL_DOWN, + PIN_CONFIG_DRIVE_PUSH_PULL, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0302-pinctrl-add-pinconf-generic-define-for-a-pin-default.patch b/patches.renesas/0302-pinctrl-add-pinconf-generic-define-for-a-pin-default.patch new file mode 100644 index 00000000000..90d231a8833 --- /dev/null +++ b/patches.renesas/0302-pinctrl-add-pinconf-generic-define-for-a-pin-default.patch @@ -0,0 +1,63 @@ +From d233a3e6d42d6c68e71f5e1ca9e46af22474e3ed Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Heiko=20St=C3=BCbner?= <heiko@sntech.de> +Date: Thu, 6 Jun 2013 16:44:25 +0200 +Subject: pinctrl: add pinconf-generic define for a pin-default pull + +There exist controllers that don't support to set the pull to up or down +separately but instead automatically set the pull direction based on +embedded knowledge inside the controller, for example depending on the +selected mux function of the pin. + +Therefore this patch adds another config option to use this default +pull-state for a pin where it is not possible to know or decide if the +pin will be pulled up or down. + +Signed-off-by: Heiko Stuebner <heiko@sntech.de> +Reviewed-by: Stephen Warren <swarren@nvidia.com> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit 7970cb770dffa23cb20a36f46602e688e075f5d9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/pinconf-generic.c | 2 ++ + include/linux/pinctrl/pinconf-generic.h | 5 +++++ + 2 files changed, 7 insertions(+) + +diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c +index 7c593dbd..5810d150 100644 +--- a/drivers/pinctrl/pinconf-generic.c ++++ b/drivers/pinctrl/pinconf-generic.c +@@ -40,6 +40,8 @@ static struct pin_config_item conf_items[] = { + PCONFDUMP(PIN_CONFIG_BIAS_BUS_HOLD, "input bias bus hold", NULL), + PCONFDUMP(PIN_CONFIG_BIAS_PULL_UP, "input bias pull up", NULL), + PCONFDUMP(PIN_CONFIG_BIAS_PULL_DOWN, "input bias pull down", NULL), ++ PCONFDUMP(PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, ++ "input bias pull to pin specific state", NULL), + PCONFDUMP(PIN_CONFIG_DRIVE_PUSH_PULL, "output drive push pull", NULL), + PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_DRAIN, "output drive open drain", NULL), + PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_SOURCE, "output drive open source", NULL), +diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h +index ac05b3cf..d414a772 100644 +--- a/include/linux/pinctrl/pinconf-generic.h ++++ b/include/linux/pinctrl/pinconf-generic.h +@@ -40,6 +40,10 @@ + * @PIN_CONFIG_BIAS_PULL_DOWN: the pin will be pulled down (usually with high + * impedance to GROUND). If the argument is != 0 pull-down is enabled, + * if it is 0, pull-down is disabled. ++ * @PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: the pin will be pulled up or down based ++ * on embedded knowledge of the controller, like current mux function. ++ * If the argument is != 0 pull up/down is enabled, if it is 0, ++ * the pull is disabled. + * @PIN_CONFIG_DRIVE_PUSH_PULL: the pin will be driven actively high and + * low, this is the most typical case and is typically achieved with two + * active transistors on the output. Setting this config will enable +@@ -86,6 +90,7 @@ enum pin_config_param { + PIN_CONFIG_BIAS_BUS_HOLD, + PIN_CONFIG_BIAS_PULL_UP, + PIN_CONFIG_BIAS_PULL_DOWN, ++ PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, + PIN_CONFIG_DRIVE_PUSH_PULL, + PIN_CONFIG_DRIVE_OPEN_DRAIN, + PIN_CONFIG_DRIVE_OPEN_SOURCE, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0303-pinctrl-add-function-to-parse-generic-pinconfig-prop.patch b/patches.renesas/0303-pinctrl-add-function-to-parse-generic-pinconfig-prop.patch new file mode 100644 index 00000000000..8b699582708 --- /dev/null +++ b/patches.renesas/0303-pinctrl-add-function-to-parse-generic-pinconfig-prop.patch @@ -0,0 +1,182 @@ +From 593ee60159355138352679fe7bb7ee4213ea2369 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Heiko=20St=C3=BCbner?= <heiko@sntech.de> +Date: Mon, 10 Jun 2013 21:40:29 +0200 +Subject: pinctrl: add function to parse generic pinconfig properties from a dt + node + +pinconf_generic_parse_dt_config() takes a node as input and generates an +array of generic pinconfig values from the properties of this node. + +As I couldn't find a mechanism to count the number of properties of a node +the function uses internally an array to accept one of parameter and copies +the real present options to a smaller variable at its end. + +Signed-off-by: Heiko Stuebner <heiko@sntech.de> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit 7db9af4b6e41be599e0fcd50d687138a5add428c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + .../bindings/pinctrl/pinctrl-bindings.txt | 38 ++++++++++ + drivers/pinctrl/pinconf-generic.c | 81 ++++++++++++++++++++++ + drivers/pinctrl/pinconf.h | 6 ++ + 3 files changed, 125 insertions(+) + +diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +index c95ea827..ef7cd572 100644 +--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt ++++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +@@ -126,3 +126,41 @@ device; they may be grandchildren, for example. Whether this is legal, and + whether there is any interaction between the child and intermediate parent + nodes, is again defined entirely by the binding for the individual pin + controller device. ++ ++== Using generic pinconfig options == ++ ++Generic pinconfig parameters can be used by defining a separate node containing ++the applicable parameters (and optional values), like: ++ ++pcfg_pull_up: pcfg_pull_up { ++ bias-pull-up; ++ drive-strength = <20>; ++}; ++ ++This node should then be referenced in the appropriate pinctrl node as a phandle ++and parsed in the driver using the pinconf_generic_parse_dt_config function. ++ ++Supported configuration parameters are: ++ ++bias-disable - disable any pin bias ++bias-high-impedance - high impedance mode ("third-state", "floating") ++bias-bus-hold - latch weakly ++bias-pull-up - pull up the pin ++bias-pull-down - pull down the pin ++bias-pull-pin-default - use pin-default pull state ++drive-push-pull - drive actively high and low ++drive-open-drain - drive with open drain ++drive-open-source - drive with open source ++drive-strength - sink or source at most X mA ++input-schmitt-enable - enable schmitt-trigger mode ++input-schmitt-disable - disable schmitt-trigger mode ++input-schmitt - run in schmitt-trigger mode with hysteresis X ++input-debounce - debounce mode with debound time X ++power-source - select power source X ++slew-rate - use slew-rate X ++low-power-mode - low power mode ++output-low - set the pin to output mode with low level ++output-high - set the pin to output mode with high level ++ ++More in-depth documentation on these parameters can be found in ++<include/linux/pinctrl/pinconfig-generic.h> +diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c +index 5810d150..1ddddb95 100644 +--- a/drivers/pinctrl/pinconf-generic.c ++++ b/drivers/pinctrl/pinconf-generic.c +@@ -21,6 +21,7 @@ + #include <linux/pinctrl/pinctrl.h> + #include <linux/pinctrl/pinconf.h> + #include <linux/pinctrl/pinconf-generic.h> ++#include <linux/of.h> + #include "core.h" + #include "pinconf.h" + +@@ -138,3 +139,83 @@ void pinconf_generic_dump_config(struct pinctrl_dev *pctldev, + } + EXPORT_SYMBOL_GPL(pinconf_generic_dump_config); + #endif ++ ++#ifdef CONFIG_OF ++struct pinconf_generic_dt_params { ++ const char * const property; ++ enum pin_config_param param; ++ u32 default_value; ++}; ++ ++static struct pinconf_generic_dt_params dt_params[] = { ++ { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, ++ { "bias-high-impedance", PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0 }, ++ { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, ++ { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 0 }, ++ { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 0 }, ++ { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 0 }, ++ { "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 0 }, ++ { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 }, ++ { "drive-open-source", PIN_CONFIG_DRIVE_OPEN_SOURCE, 0 }, ++ { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, ++ { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, ++ { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, ++ { "input-schmitt", PIN_CONFIG_INPUT_SCHMITT, 0 }, ++ { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 }, ++ { "power-source", PIN_CONFIG_POWER_SOURCE, 0 }, ++ { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 }, ++ { "low-power-mode", PIN_CONFIG_LOW_POWER_MODE, 0 }, ++ { "output-low", PIN_CONFIG_OUTPUT, 0, }, ++ { "output-high", PIN_CONFIG_OUTPUT, 1, }, ++}; ++ ++/** ++ * pinconf_generic_parse_dt_config() ++ * parse the config properties into generic pinconfig values. ++ * @np: node containing the pinconfig properties ++ * @configs: array with nconfigs entries containing the generic pinconf values ++ * @nconfigs: umber of configurations ++ */ ++int pinconf_generic_parse_dt_config(struct device_node *np, ++ unsigned long **configs, ++ unsigned int *nconfigs) ++{ ++ unsigned long cfg[ARRAY_SIZE(dt_params)]; ++ unsigned int ncfg = 0; ++ int ret; ++ int i; ++ u32 val; ++ ++ if (!np) ++ return -EINVAL; ++ ++ for (i = 0; i < ARRAY_SIZE(dt_params); i++) { ++ struct pinconf_generic_dt_params *par = &dt_params[i]; ++ ret = of_property_read_u32(np, par->property, &val); ++ ++ /* property not found */ ++ if (ret == -EINVAL) ++ continue; ++ ++ /* use default value, when no value is specified */ ++ if (ret) ++ val = par->default_value; ++ ++ pr_debug("found %s with value %u\n", par->property, val); ++ cfg[ncfg] = pinconf_to_config_packed(par->param, val); ++ ncfg++; ++ } ++ ++ /* ++ * Now limit the number of configs to the real number of ++ * found properties. ++ */ ++ *configs = kzalloc(ncfg * sizeof(unsigned long), GFP_KERNEL); ++ if (!*configs) ++ return -ENOMEM; ++ ++ memcpy(*configs, &cfg, ncfg * sizeof(unsigned long)); ++ *nconfigs = ncfg; ++ return 0; ++} ++#endif +diff --git a/drivers/pinctrl/pinconf.h b/drivers/pinctrl/pinconf.h +index 92c72672..a4a5417e 100644 +--- a/drivers/pinctrl/pinconf.h ++++ b/drivers/pinctrl/pinconf.h +@@ -123,3 +123,9 @@ static inline void pinconf_generic_dump_config(struct pinctrl_dev *pctldev, + return; + } + #endif ++ ++#if defined(CONFIG_GENERIC_PINCONF) && defined(CONFIG_OF) ++int pinconf_generic_parse_dt_config(struct device_node *np, ++ unsigned long **configs, ++ unsigned int *nconfigs); ++#endif +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0304-sh-pfc-Add-pinconf-support-to-DT-bindings.patch b/patches.renesas/0304-sh-pfc-Add-pinconf-support-to-DT-bindings.patch new file mode 100644 index 00000000000..4302ec253bc --- /dev/null +++ b/patches.renesas/0304-sh-pfc-Add-pinconf-support-to-DT-bindings.patch @@ -0,0 +1,253 @@ +From 608fc77d559c960f4e0f68d5e218dc72815ebf41 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 17 Jun 2013 20:50:03 +0200 +Subject: sh-pfc: Add pinconf support to DT bindings + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Acked-by: Heiko Stuebner <heiko@sntech.de> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit 12f3ad8df7f58c61ff16ea851541583693d965e1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + .../bindings/pinctrl/renesas,pfc-pinctrl.txt | 36 +++++-- + drivers/pinctrl/sh-pfc/pinctrl.c | 109 ++++++++++++++++++--- + 2 files changed, 124 insertions(+), 21 deletions(-) + +diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +index 8264cbcd..d5dac7b8 100644 +--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt ++++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +@@ -30,20 +30,27 @@ The PFC node also acts as a container for pin configuration nodes. Please refer + to pinctrl-bindings.txt in this directory for the definition of the term "pin + configuration node" and for the common pinctrl bindings used by client devices. + +-Each pin configuration node represents desired functions to select on a pin +-group or a list of pin groups. The functions and pin groups can be specified +-directly in the pin configuration node, or grouped in child subnodes. Several +-functions can thus be referenced as a single pin configuration node by client +-devices. ++Each pin configuration node represents a desired configuration for a pin, a ++pin group, or a list of pins or pin groups. The configuration can include the ++function to select on those pin(s) and pin configuration parameters (such as ++pull-up and pull-down). + +-A configuration node or subnode must contain a function and reference at least +-one pin group. ++Pin configuration nodes contain pin configuration properties, either directly ++or grouped in child subnodes. Both pin muxing and configuration parameters can ++be grouped in that way and referenced as a single pin configuration node by ++client devices. ++ ++A configuration node or subnode must reference at least one pin (through the ++pins or pin groups properties) and contain at least a function or one ++configuration parameter. When the function is present only pin groups can be ++used to reference pins. + + All pin configuration nodes and subnodes names are ignored. All of those nodes + are parsed through phandles and processed purely based on their content. + + Pin Configuration Node Properties: + ++- renesas,pins : An array of strings, each string containing the name of a pin. + - renesas,groups : An array of strings, each string containing the name of a pin + group. + +@@ -54,6 +61,10 @@ Pin Configuration Node Properties: + function arrays of the PFC data file corresponding to the SoC + (drivers/pinctrl/sh-pfc/pfc-*.c) + ++The pin configuration parameters use the generic pinconf bindings defined in ++pinctrl-bindings.txt in this directory. The supported parameters are ++bias-disable, bias-pull-up and bias-pull-down. ++ + + GPIO + ---- +@@ -113,8 +124,15 @@ Example 3: KZM-A9-GT (SH-Mobile AG5) default pin state hog and pin control maps + pinctrl-names = "default"; + + mmcif_pins: mmcif { +- renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0"; +- renesas,function = "mmc0"; ++ mux { ++ renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0"; ++ renesas,function = "mmc0"; ++ }; ++ cfg { ++ renesas,groups = "mmc0_data8_0"; ++ renesas,pins = "PORT279"; ++ bias-pull-up; ++ }; + }; + + scifa4_pins: scifa4 { +diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c +index 7e32bb8c..2cf23476 100644 +--- a/drivers/pinctrl/sh-pfc/pinctrl.c ++++ b/drivers/pinctrl/sh-pfc/pinctrl.c +@@ -74,6 +74,27 @@ static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, + seq_printf(s, "%s", DRV_NAME); + } + ++static int sh_pfc_map_add_config(struct pinctrl_map *map, ++ const char *group_or_pin, ++ enum pinctrl_map_type type, ++ unsigned long *configs, ++ unsigned int num_configs) ++{ ++ unsigned long *cfgs; ++ ++ cfgs = kmemdup(configs, num_configs * sizeof(*cfgs), ++ GFP_KERNEL); ++ if (cfgs == NULL) ++ return -ENOMEM; ++ ++ map->type = type; ++ map->data.configs.group_or_pin = group_or_pin; ++ map->data.configs.configs = cfgs; ++ map->data.configs.num_configs = num_configs; ++ ++ return 0; ++} ++ + static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np, + struct pinctrl_map **map, + unsigned int *num_maps, unsigned int *index) +@@ -81,9 +102,14 @@ static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np, + struct pinctrl_map *maps = *map; + unsigned int nmaps = *num_maps; + unsigned int idx = *index; ++ unsigned int num_configs; + const char *function = NULL; ++ unsigned long *configs; + struct property *prop; ++ unsigned int num_groups; ++ unsigned int num_pins; + const char *group; ++ const char *pin; + int ret; + + /* Parse the function and configuration properties. At least a function +@@ -95,25 +121,47 @@ static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np, + return ret; + } + +- if (!function) { +- dev_err(dev, "DT node must contain at least one function\n"); ++ ret = pinconf_generic_parse_dt_config(np, &configs, &num_configs); ++ if (ret < 0) ++ return ret; ++ ++ if (!function && num_configs == 0) { ++ dev_err(dev, ++ "DT node must contain at least a function or config\n"); + goto done; + } + +- /* Count the number of groups and reallocate mappings. */ ++ /* Count the number of pins and groups and reallocate mappings. */ ++ ret = of_property_count_strings(np, "renesas,pins"); ++ if (ret == -EINVAL) { ++ num_pins = 0; ++ } else if (ret < 0) { ++ dev_err(dev, "Invalid pins list in DT\n"); ++ goto done; ++ } else { ++ num_pins = ret; ++ } ++ + ret = of_property_count_strings(np, "renesas,groups"); +- if (ret < 0 && ret != -EINVAL) { ++ if (ret == -EINVAL) { ++ num_groups = 0; ++ } else if (ret < 0) { + dev_err(dev, "Invalid pin groups list in DT\n"); + goto done; ++ } else { ++ num_groups = ret; + } + +- if (!ret) { +- dev_err(dev, "No group provided in DT node\n"); ++ if (!num_pins && !num_groups) { ++ dev_err(dev, "No pin or group provided in DT node\n"); + ret = -ENODEV; + goto done; + } + +- nmaps += ret; ++ if (function) ++ nmaps += num_groups; ++ if (configs) ++ nmaps += num_pins + num_groups; + + maps = krealloc(maps, sizeof(*maps) * nmaps, GFP_KERNEL); + if (maps == NULL) { +@@ -126,22 +174,59 @@ static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np, + + /* Iterate over pins and groups and create the mappings. */ + of_property_for_each_string(np, "renesas,groups", prop, group) { +- maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; +- maps[idx].data.mux.group = group; +- maps[idx].data.mux.function = function; +- idx++; ++ if (function) { ++ maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; ++ maps[idx].data.mux.group = group; ++ maps[idx].data.mux.function = function; ++ idx++; ++ } ++ ++ if (configs) { ++ ret = sh_pfc_map_add_config(&maps[idx], group, ++ PIN_MAP_TYPE_CONFIGS_GROUP, ++ configs, num_configs); ++ if (ret < 0) ++ goto done; ++ ++ idx++; ++ } + } + +- ret = 0; ++ if (!configs) { ++ ret = 0; ++ goto done; ++ } ++ ++ of_property_for_each_string(np, "renesas,pins", prop, pin) { ++ ret = sh_pfc_map_add_config(&maps[idx], pin, ++ PIN_MAP_TYPE_CONFIGS_PIN, ++ configs, num_configs); ++ if (ret < 0) ++ goto done; ++ ++ idx++; ++ } + + done: + *index = idx; ++ kfree(configs); + return ret; + } + + static void sh_pfc_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned num_maps) + { ++ unsigned int i; ++ ++ if (map == NULL) ++ return; ++ ++ for (i = 0; i < num_maps; ++i) { ++ if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP || ++ map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) ++ kfree(map[i].data.configs.configs); ++ } ++ + kfree(map); + } + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0305-sh-pfc-Guard-DT-parsing-with-ifdef-CONFIG_OF.patch b/patches.renesas/0305-sh-pfc-Guard-DT-parsing-with-ifdef-CONFIG_OF.patch new file mode 100644 index 00000000000..2f1308a2d9f --- /dev/null +++ b/patches.renesas/0305-sh-pfc-Guard-DT-parsing-with-ifdef-CONFIG_OF.patch @@ -0,0 +1,55 @@ +From 69e0bcaacadc2c58fc69d47d3178c2e525ddd248 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Wed, 19 Jun 2013 13:26:02 +0200 +Subject: sh-pfc: Guard DT parsing with #ifdef CONFIG_OF + +Fix a compilation error caused by pinconf_generic_parse_dt_config() not +being defined on !CONFIG_OF platforms by guarding the whole DT node +parsing code with #ifdef CONFIG_OF. + +Defining a pinconf_generic_parse_dt_config() on !CONFIG_OF would have +been possible as well, but would have resulted in a larger code size on +!CONFIG_OF platforms (such as arch/sh). + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit 3a8d63d4b4fdfa2563b85b4a6db0119cbdb537d1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pinctrl.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c +index 2cf23476..bc8b028b 100644 +--- a/drivers/pinctrl/sh-pfc/pinctrl.c ++++ b/drivers/pinctrl/sh-pfc/pinctrl.c +@@ -74,6 +74,7 @@ static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, + seq_printf(s, "%s", DRV_NAME); + } + ++#ifdef CONFIG_OF + static int sh_pfc_map_add_config(struct pinctrl_map *map, + const char *group_or_pin, + enum pinctrl_map_type type, +@@ -270,14 +271,17 @@ done: + + return ret; + } ++#endif /* CONFIG_OF */ + + static const struct pinctrl_ops sh_pfc_pinctrl_ops = { + .get_groups_count = sh_pfc_get_groups_count, + .get_group_name = sh_pfc_get_group_name, + .get_group_pins = sh_pfc_get_group_pins, + .pin_dbg_show = sh_pfc_pin_dbg_show, ++#ifdef CONFIG_OF + .dt_node_to_map = sh_pfc_dt_node_to_map, + .dt_free_map = sh_pfc_dt_free_map, ++#endif + }; + + static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0306-pinctrl-sh-pfc-fix-SDHI0-VccQ-regulator-on-sh73a0-wi.patch b/patches.renesas/0306-pinctrl-sh-pfc-fix-SDHI0-VccQ-regulator-on-sh73a0-wi.patch new file mode 100644 index 00000000000..9cd3af57481 --- /dev/null +++ b/patches.renesas/0306-pinctrl-sh-pfc-fix-SDHI0-VccQ-regulator-on-sh73a0-wi.patch @@ -0,0 +1,35 @@ +From 033fc4686772c06d5aa5ee9a050272f81ca9578c Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Tue, 9 Jul 2013 16:27:24 +0200 +Subject: pinctrl: sh-pfc: fix SDHI0 VccQ regulator on sh73a0 with DT + +The PFC pinctrl driver on sh73a0 is also regiatering a VccQ regulator for +SDHI0. However, its consumers list only included the platform-data based +SDHI device name. When booted with DT SDHI0 couldn't enable VccQ and +therefore was unusable. Fix this by adding a consumer with DT-based name. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Acked-by: Simon Horman <horms+renesas@verge.net.au> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit 74b843512906e60be24ed6aafa2fa2876f294fab) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +index 7956df58..31f7d0e0 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +@@ -3785,6 +3785,7 @@ static const struct regulator_desc sh73a0_vccq_mc0_desc = { + + static struct regulator_consumer_supply sh73a0_vccq_mc0_consumers[] = { + REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"), ++ REGULATOR_SUPPLY("vqmmc", "ee100000.sdhi"), + }; + + static const struct regulator_init_data sh73a0_vccq_mc0_init_data = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0307-ARM-shmobile-armadillo800eva-Don-t-request-GPIO-166-.patch b/patches.renesas/0307-ARM-shmobile-armadillo800eva-Don-t-request-GPIO-166-.patch new file mode 100644 index 00000000000..ad55cdcdc98 --- /dev/null +++ b/patches.renesas/0307-ARM-shmobile-armadillo800eva-Don-t-request-GPIO-166-.patch @@ -0,0 +1,41 @@ +From 69dea236408297626e463a714bb59e639296e112 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 24 Jul 2013 17:50:50 -0700 +Subject: ARM: shmobile: armadillo800eva: Don't request GPIO 166 in board code + +89ae7b5bbd3e65bc6ab7a577ca5ec18569589c8c +(ARM: shmobile: armadillo800eva: Register pinctrl mapping for INTC) +mistakenly requests GPIO 166 in board code, +most probably due to a wrong merge conflict resolution. +As the GPIO is passed to the st1232 driver through platform +data and requested by the driver, +there's no need to request it in board code. Fix it. + +Tested by: Cao Minh Hiep <cm-hiep@jinso.co.jp> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit 16b551dd22cc7edacb952f7a2e175f36c3aa4bdb) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-armadillo800eva.c | 3 --- + 1 file changed, 3 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c +index 44a62150..e80088d1 100644 +--- a/arch/arm/mach-shmobile/board-armadillo800eva.c ++++ b/arch/arm/mach-shmobile/board-armadillo800eva.c +@@ -1161,9 +1161,6 @@ static void __init eva_init(void) + gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ + gpio_request_one(202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */ + +- /* Touchscreen */ +- gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */ +- + /* GETHER */ + gpio_request_one(18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */ + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0308-ARM-shmobile-BOCK-W-fix-SDHI0-PFC-settings.patch b/patches.renesas/0308-ARM-shmobile-BOCK-W-fix-SDHI0-PFC-settings.patch new file mode 100644 index 00000000000..707b5f7c658 --- /dev/null +++ b/patches.renesas/0308-ARM-shmobile-BOCK-W-fix-SDHI0-PFC-settings.patch @@ -0,0 +1,47 @@ +From 930f1337cf779ba1e69a516e8c70a6270413fa6f Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Sat, 27 Jul 2013 03:46:33 +0400 +Subject: ARM: shmobile: BOCK-W: fix SDHI0 PFC settings + +The following message is printed on the BOCK-W kernel bootup: + +sh-pfc pfc-r8a7778: invalid group "sdhi0" for function "sdhi0" + +In addition, SD card cannot be detected. The reason is apparently that commit +ca7bb309485e4ec89a9addd47bea (ARM: shmobile: bockw: add SDHI0 support) matched +the previous version of commit 564617d2f92473031d035deb273da5 (sh-pfc: r8a7778: +add SDHI support). + +Add the missing pin groups according to the BOCK-W board schematics. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit fa3e0cee12fbdd9e0b03470b2b8cf968f537c161) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-bockw.c | 8 +++++++- + 1 file changed, 7 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c +index 9936ad2e..c7a0f9ba 100644 +--- a/arch/arm/mach-shmobile/board-bockw.c ++++ b/arch/arm/mach-shmobile/board-bockw.c +@@ -165,7 +165,13 @@ static const struct pinctrl_map bockw_pinctrl_map[] = { + "usb1", "usb1"), + /* SDHI0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778", +- "sdhi0", "sdhi0"), ++ "sdhi0_data4", "sdhi0"), ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778", ++ "sdhi0_ctrl", "sdhi0"), ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778", ++ "sdhi0_cd", "sdhi0"), ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778", ++ "sdhi0_wp", "sdhi0"), + }; + + #define FPGA 0x18200000 +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0309-ARM-shmobile-lager-do-not-annotate-gpio_buttons-as-_.patch b/patches.renesas/0309-ARM-shmobile-lager-do-not-annotate-gpio_buttons-as-_.patch new file mode 100644 index 00000000000..d786c572b8b --- /dev/null +++ b/patches.renesas/0309-ARM-shmobile-lager-do-not-annotate-gpio_buttons-as-_.patch @@ -0,0 +1,44 @@ +From 95b769e4ccef2f79cdf01b467ea1696fcbafedf1 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Fri, 26 Jul 2013 17:53:42 +0900 +Subject: ARM: shmobile: lager: do not annotate gpio_buttons as __initdata + +When the gpio-keys device is registered using +platform_device_register_data() the platform data argument, +lager_keys_pdata is duplicated and thus should be marked as __initdata +to avoid wasting memory. However, this is not true of gpio_buttons, +a reference to it rather than its value is duplicated when lager_keys_pdata +is duplicated. + +This avoids accessing freed memory if gpio-key events occur +after unused kernel memory is freed late in the kernel's boot. + +This but was added when support for gpio-keys was added to lager +in c3842e4fcbb7664276443b79187b7808c2e80a35 +("ARM: shmobile: lager: support GPIO switches") which was included +in v3.11-rc1. + +Tested-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit a601469386b543df2a4d97ad7d524716945278a3) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-lager.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c +index d73e21d3..8d6bd5c5 100644 +--- a/arch/arm/mach-shmobile/board-lager.c ++++ b/arch/arm/mach-shmobile/board-lager.c +@@ -59,7 +59,7 @@ static __initdata struct gpio_led_platform_data lager_leds_pdata = { + #define GPIO_KEY(c, g, d, ...) \ + { .code = c, .gpio = g, .desc = d, .active_low = 1 } + +-static __initdata struct gpio_keys_button gpio_buttons[] = { ++static struct gpio_keys_button gpio_buttons[] = { + GPIO_KEY(KEY_4, RCAR_GP_PIN(1, 28), "SW2-pin4"), + GPIO_KEY(KEY_3, RCAR_GP_PIN(1, 26), "SW2-pin3"), + GPIO_KEY(KEY_2, RCAR_GP_PIN(1, 24), "SW2-pin2"), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0310-ARM-shmobile-r8a7778-correct-model-name-in-Kconfig.patch b/patches.renesas/0310-ARM-shmobile-r8a7778-correct-model-name-in-Kconfig.patch new file mode 100644 index 00000000000..59f2c198964 --- /dev/null +++ b/patches.renesas/0310-ARM-shmobile-r8a7778-correct-model-name-in-Kconfig.patch @@ -0,0 +1,38 @@ +From 008c5734c22eaeec3ff9d2b9e8f09e18b8486f84 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Thu, 9 May 2013 00:05:40 +0000 +Subject: ARM: shmobile: r8a7778: correct model name in Kconfig + +The correct model name is R-Car M1A or R8A77781; R8A77780 corresponds to R-Car +M1S which is a SH based SoC. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +[horms+renesas@verge.net.au: manually applied] +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit 45fa9295a0215c99019653b06f11dcda0340a7f7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + arch/arm/mach-shmobile/Kconfig +--- + arch/arm/mach-shmobile/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index 4b172453..3912ce91 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -36,7 +36,7 @@ config ARCH_R8A7740 + select RENESAS_INTC_IRQPIN + + config ARCH_R8A7778 +- bool "R-Car M1 (R8A777801)" ++ bool "R-Car M1A (R8A77781)" + select ARCH_WANT_OPTIONAL_GPIOLIB + select CPU_V7 + select SH_CLK_CPG +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0311-ARM-shmobile-armadillo800eva-remove-left-overs.patch b/patches.renesas/0311-ARM-shmobile-armadillo800eva-remove-left-overs.patch new file mode 100644 index 00000000000..adac3b9bf1b --- /dev/null +++ b/patches.renesas/0311-ARM-shmobile-armadillo800eva-remove-left-overs.patch @@ -0,0 +1,39 @@ +From a064e9ee82d776558c3c17bc5e147af65bb6e932 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Thu, 6 Jun 2013 17:38:11 +0200 +Subject: ARM: shmobile: armadillo800eva: remove left-overs + +A comment and a #define in board-armadillo800eva.c have been left over +after recent changes and are no longer relevant or needed, remove them. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit bcfed2a8a61a0f6ee7769f5093a8279a9e50c526) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-armadillo800eva.c | 9 --------- + 1 file changed, 9 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c +index e80088d1..99cea1ee 100644 +--- a/arch/arm/mach-shmobile/board-armadillo800eva.c ++++ b/arch/arm/mach-shmobile/board-armadillo800eva.c +@@ -678,15 +678,6 @@ static struct platform_device vcc_sdhi1 = { + }; + + /* SDHI0 */ +-/* +- * FIXME +- * +- * It use polling mode here, since +- * CD (= Card Detect) pin is not connected to SDHI0_CD. +- * We can use IRQ31 as card detect irq, +- * but it needs chattering removal operation +- */ +-#define IRQ31 irq_pin(31) + static struct sh_mobile_sdhi_info sdhi0_info = { + .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, + .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0312-ARM-shmobile-r8a7778-add-__initdata-on-resource-and-.patch b/patches.renesas/0312-ARM-shmobile-r8a7778-add-__initdata-on-resource-and-.patch new file mode 100644 index 00000000000..bc11ba969b5 --- /dev/null +++ b/patches.renesas/0312-ARM-shmobile-r8a7778-add-__initdata-on-resource-and-.patch @@ -0,0 +1,115 @@ +From 08b9f323311f7def6a7630f0373b35cd48293c51 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Sun, 26 May 2013 17:53:37 -0700 +Subject: ARM: shmobile: r8a7778: add __initdata on resource and device data + +These data will be kmemdup()'ed on +platform_device_add_resources() and platform_device_add_data() + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms@verge.net.au> +(cherry picked from commit c9031fbb35bd44d99c5cfe7d3c97ec238d63643a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a7778.c | 24 ++++++++++++------------ + 1 file changed, 12 insertions(+), 12 deletions(-) + +diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c +index 80c20392..b70bfeef 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7778.c ++++ b/arch/arm/mach-shmobile/setup-r8a7778.c +@@ -53,7 +53,7 @@ + .irqs = SCIx_IRQ_MUXED(irq), \ + } + +-static struct plat_sci_port scif_platform_data[] = { ++static struct plat_sci_port scif_platform_data[] __initdata = { + SCIF_INFO(0xffe40000, gic_iid(0x66)), + SCIF_INFO(0xffe41000, gic_iid(0x67)), + SCIF_INFO(0xffe42000, gic_iid(0x68)), +@@ -63,24 +63,24 @@ static struct plat_sci_port scif_platform_data[] = { + }; + + /* TMU */ +-static struct resource sh_tmu0_resources[] = { ++static struct resource sh_tmu0_resources[] __initdata = { + DEFINE_RES_MEM(0xffd80008, 12), + DEFINE_RES_IRQ(gic_iid(0x40)), + }; + +-static struct sh_timer_config sh_tmu0_platform_data = { ++static struct sh_timer_config sh_tmu0_platform_data __initdata = { + .name = "TMU00", + .channel_offset = 0x4, + .timer_bit = 0, + .clockevent_rating = 200, + }; + +-static struct resource sh_tmu1_resources[] = { ++static struct resource sh_tmu1_resources[] __initdata = { + DEFINE_RES_MEM(0xffd80014, 12), + DEFINE_RES_IRQ(gic_iid(0x41)), + }; + +-static struct sh_timer_config sh_tmu1_platform_data = { ++static struct sh_timer_config sh_tmu1_platform_data __initdata = { + .name = "TMU01", + .channel_offset = 0x10, + .timer_bit = 1, +@@ -189,7 +189,7 @@ USB_PLATFORM_INFO(ehci); + USB_PLATFORM_INFO(ohci); + + /* Ether */ +-static struct resource ether_resources[] = { ++static struct resource ether_resources[] __initdata = { + DEFINE_RES_MEM(0xfde00000, 0x400), + DEFINE_RES_IRQ(gic_iid(0x89)), + }; +@@ -203,17 +203,17 @@ void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata) + } + + /* PFC/GPIO */ +-static struct resource pfc_resources[] = { ++static struct resource pfc_resources[] __initdata = { + DEFINE_RES_MEM(0xfffc0000, 0x118), + }; + + #define R8A7778_GPIO(idx) \ +-static struct resource r8a7778_gpio##idx##_resources[] = { \ ++static struct resource r8a7778_gpio##idx##_resources[] __initdata = { \ + DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30), \ + DEFINE_RES_IRQ(gic_iid(0x87)), \ + }; \ + \ +-static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data = { \ ++static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data __initdata = { \ + .gpio_base = 32 * (idx), \ + .irq_base = GPIO_IRQ_BASE(idx), \ + .number_of_pins = 32, \ +@@ -249,7 +249,7 @@ void __init r8a7778_pinmux_init(void) + }; + + /* SDHI */ +-static struct resource sdhi_resources[] = { ++static struct resource sdhi_resources[] __initdata = { + /* SDHI0 */ + DEFINE_RES_MEM(0xFFE4C000, 0x100), + DEFINE_RES_IRQ(gic_iid(0x77)), +@@ -365,12 +365,12 @@ void __init r8a7778_init_late(void) + platform_device_register_full(&ohci_info); + } + +-static struct renesas_intc_irqpin_config irqpin_platform_data = { ++static struct renesas_intc_irqpin_config irqpin_platform_data __initdata = { + .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ + .sense_bitfield_width = 2, + }; + +-static struct resource irqpin_resources[] = { ++static struct resource irqpin_resources[] __initdata = { + DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ + DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ + DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0313-ARM-shmobile-sh73a0-pinmux-platform-device-cleanup.patch b/patches.renesas/0313-ARM-shmobile-sh73a0-pinmux-platform-device-cleanup.patch new file mode 100644 index 00000000000..b1488f24b62 --- /dev/null +++ b/patches.renesas/0313-ARM-shmobile-sh73a0-pinmux-platform-device-cleanup.patch @@ -0,0 +1,63 @@ +From 72b99e0dd14dccab90e7926f3774f96154c4346f Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Thu, 27 Jun 2013 17:09:01 +0900 +Subject: ARM: shmobile: sh73a0 pinmux platform device cleanup + +Use DEFINE_RES_MEM() and platform_device_register_simple() +to save a couple of lines of code. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +[ remove const from resource pfc_resources to avoid section miss-match + reported by 4.4.5 ] +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit 474f67587345bf7b32bbd9d2b5621e85500103c5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-sh73a0.c | 25 ++++++------------------- + 1 file changed, 6 insertions(+), 19 deletions(-) + +diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c +index 96e7ca1e..79a60407 100644 +--- a/arch/arm/mach-shmobile/setup-sh73a0.c ++++ b/arch/arm/mach-shmobile/setup-sh73a0.c +@@ -61,29 +61,16 @@ void __init sh73a0_map_io(void) + iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc)); + } + +-static struct resource sh73a0_pfc_resources[] = { +- [0] = { +- .start = 0xe6050000, +- .end = 0xe6057fff, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = 0xe605801c, +- .end = 0xe6058027, +- .flags = IORESOURCE_MEM, +- } +-}; +- +-static struct platform_device sh73a0_pfc_device = { +- .name = "pfc-sh73a0", +- .id = -1, +- .resource = sh73a0_pfc_resources, +- .num_resources = ARRAY_SIZE(sh73a0_pfc_resources), ++/* PFC */ ++static struct resource pfc_resources[] __initdata = { ++ DEFINE_RES_MEM(0xe6050000, 0x8000), ++ DEFINE_RES_MEM(0xe605801c, 0x000c), + }; + + void __init sh73a0_pinmux_init(void) + { +- platform_device_register(&sh73a0_pfc_device); ++ platform_device_register_simple("pfc-sh73a0", -1, pfc_resources, ++ ARRAY_SIZE(pfc_resources)); + } + + static struct plat_sci_port scif0_platform_data = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0314-ARM-shmobile-emev2-Remove-init_irq-declaration-in-ma.patch b/patches.renesas/0314-ARM-shmobile-emev2-Remove-init_irq-declaration-in-ma.patch new file mode 100644 index 00000000000..d6b2c45d0b7 --- /dev/null +++ b/patches.renesas/0314-ARM-shmobile-emev2-Remove-init_irq-declaration-in-ma.patch @@ -0,0 +1,42 @@ +From d5f8176271e63798d7de990e25df5ec3fa1d79d1 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard <maxime.ripard@free-electrons.com> +Date: Sun, 26 May 2013 22:05:23 +0900 +Subject: ARM: shmobile: emev2: Remove init_irq declaration in machine + description + +Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is +specified") removed the need to explictly setup the init_irq field in +the machine description when using only irqchip_init. Remove that +declaration for shmobile as well. + +Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 34dd9fc04a028edad7658006764c4d18ac3dca73) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-emev2.c | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c +index 1ccddd22..6e8b6ac3 100644 +--- a/arch/arm/mach-shmobile/setup-emev2.c ++++ b/arch/arm/mach-shmobile/setup-emev2.c +@@ -20,7 +20,6 @@ + #include <linux/init.h> + #include <linux/interrupt.h> + #include <linux/irq.h> +-#include <linux/irqchip.h> + #include <linux/platform_device.h> + #include <linux/platform_data/gpio-em.h> + #include <linux/of_platform.h> +@@ -454,7 +453,6 @@ DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)") + .smp = smp_ops(emev2_smp_ops), + .init_early = emev2_init_delay, + .nr_irqs = NR_IRQS_LEGACY, +- .init_irq = irqchip_init, + .init_machine = emev2_add_standard_devices_dt, + .dt_compat = emev2_boards_compat_dt, + MACHINE_END +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0315-ARM-shmobile-r8a73a4-Remove-init_irq-declaration-in-.patch b/patches.renesas/0315-ARM-shmobile-r8a73a4-Remove-init_irq-declaration-in-.patch new file mode 100644 index 00000000000..7490efe533e --- /dev/null +++ b/patches.renesas/0315-ARM-shmobile-r8a73a4-Remove-init_irq-declaration-in-.patch @@ -0,0 +1,42 @@ +From 50537521dd9e19af55208f0a6320b086a43d3c86 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard <maxime.ripard@free-electrons.com> +Date: Sun, 26 May 2013 22:05:56 +0900 +Subject: ARM: shmobile: r8a73a4: Remove init_irq declaration in machine + description + +Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is +specified") removed the need to explictly setup the init_irq field in +the machine description when using only irqchip_init. Remove that +declaration for shmobile as well. + +Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 0bdbe04db005e025d3522ad3ae9797a4954528e9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a73a4.c | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c +index 7f45c2ed..a8c4e41b 100644 +--- a/arch/arm/mach-shmobile/setup-r8a73a4.c ++++ b/arch/arm/mach-shmobile/setup-r8a73a4.c +@@ -18,7 +18,6 @@ + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <linux/irq.h> +-#include <linux/irqchip.h> + #include <linux/kernel.h> + #include <linux/of_platform.h> + #include <linux/platform_data/irq-renesas-irqc.h> +@@ -194,7 +193,6 @@ static const char *r8a73a4_boards_compat_dt[] __initdata = { + }; + + DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)") +- .init_irq = irqchip_init, + .init_machine = r8a73a4_add_standard_devices_dt, + .init_time = shmobile_timer_init, + .dt_compat = r8a73a4_boards_compat_dt, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0316-ARM-shmobile-ape6evm-Remove-init_irq-declaration-in-.patch b/patches.renesas/0316-ARM-shmobile-ape6evm-Remove-init_irq-declaration-in-.patch new file mode 100644 index 00000000000..971df0f8489 --- /dev/null +++ b/patches.renesas/0316-ARM-shmobile-ape6evm-Remove-init_irq-declaration-in-.patch @@ -0,0 +1,44 @@ +From a7020cfc29743e8187b8a7ae4a51f9cdc6fa6c6c Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Mon, 1 Jul 2013 15:01:21 +0900 +Subject: ARM: shmobile: ape6evm: Remove init_irq declaration in machine + description + +Remove redundant irqchip_init() callback. The default case +of NULL will result in invoking irqchip_init() anyway. + +Signed-off-by: Magnus Damm <damm@opensource.se> +[ horms+renesas@verge.net.au: Trimmed patch to remove portion + that updates the r8a73a4 SoC and altered the subject to + use the same format as the patch that updates the r8a73a4. ] +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit c7f6085f6ea7b7cf155f470431cf1b12cd999450) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-ape6evm.c | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c +index 5eb0caa6..1fbc39a1 100644 +--- a/arch/arm/mach-shmobile/board-ape6evm.c ++++ b/arch/arm/mach-shmobile/board-ape6evm.c +@@ -20,7 +20,6 @@ + + #include <linux/gpio.h> + #include <linux/interrupt.h> +-#include <linux/irqchip.h> + #include <linux/kernel.h> + #include <linux/pinctrl/machine.h> + #include <linux/platform_device.h> +@@ -102,7 +101,6 @@ static const char *ape6evm_boards_compat_dt[] __initdata = { + }; + + DT_MACHINE_START(APE6EVM_DT, "ape6evm") +- .init_irq = irqchip_init, + .init_time = shmobile_timer_init, + .init_machine = ape6evm_add_standard_devices, + .dt_compat = ape6evm_boards_compat_dt, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0317-ARM-shmobile-r8a7790-Remove-init_irq-declaration-in-.patch b/patches.renesas/0317-ARM-shmobile-r8a7790-Remove-init_irq-declaration-in-.patch new file mode 100644 index 00000000000..4c688089be4 --- /dev/null +++ b/patches.renesas/0317-ARM-shmobile-r8a7790-Remove-init_irq-declaration-in-.patch @@ -0,0 +1,42 @@ +From 24451c0ccc09a408a7337f3afaf7e85f075aa7d6 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard <maxime.ripard@free-electrons.com> +Date: Mon, 27 May 2013 18:00:22 +0900 +Subject: ARM: shmobile: r8a7790: Remove init_irq declaration in machine + description + +Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is +specified") removed the need to explictly setup the init_irq field in +the machine description when using only irqchip_init. Remove that +declaration for shmobile as well. + +Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 125332daf2e4119614c561bc8cbf1f49cd243023) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a7790.c | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c +index 28f94752..d405dbd4 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7790.c ++++ b/arch/arm/mach-shmobile/setup-r8a7790.c +@@ -19,7 +19,6 @@ + */ + + #include <linux/irq.h> +-#include <linux/irqchip.h> + #include <linux/kernel.h> + #include <linux/of_platform.h> + #include <linux/serial_sci.h> +@@ -188,7 +187,6 @@ static const char *r8a7790_boards_compat_dt[] __initdata = { + }; + + DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)") +- .init_irq = irqchip_init, + .init_machine = r8a7790_add_standard_devices_dt, + .init_time = r8a7790_timer_init, + .dt_compat = r8a7790_boards_compat_dt, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0318-ARM-shmobile-lager-Remove-init_irq-declaration-in-ma.patch b/patches.renesas/0318-ARM-shmobile-lager-Remove-init_irq-declaration-in-ma.patch new file mode 100644 index 00000000000..30a22621d02 --- /dev/null +++ b/patches.renesas/0318-ARM-shmobile-lager-Remove-init_irq-declaration-in-ma.patch @@ -0,0 +1,44 @@ +From 0cadc7b2f86565454ea75ddf8a6ec34c83aba1dd Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Mon, 1 Jul 2013 15:01:31 +0900 +Subject: ARM: shmobile: lager: Remove init_irq declaration in machine + description + +Remove redundant irqchip_init() callback. The default case +of NULL will result in invoking irqchip_init() anyway. + +Signed-off-by: Magnus Damm <damm@opensource.se> +[ horms+renesas@verge.net.au: Trimmed patch to remove portion + that updates the r8a7790 SoC and altered the subject to + use the same format as the patch that updates the r8a7790. ] +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit 5f85052c606e38c98de28170a2df72f78931aa30) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-lager.c | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c +index 8d6bd5c5..78d92d34 100644 +--- a/arch/arm/mach-shmobile/board-lager.c ++++ b/arch/arm/mach-shmobile/board-lager.c +@@ -22,7 +22,6 @@ + #include <linux/gpio_keys.h> + #include <linux/input.h> + #include <linux/interrupt.h> +-#include <linux/irqchip.h> + #include <linux/kernel.h> + #include <linux/leds.h> + #include <linux/pinctrl/machine.h> +@@ -103,7 +102,6 @@ static const char *lager_boards_compat_dt[] __initdata = { + }; + + DT_MACHINE_START(LAGER_DT, "lager") +- .init_irq = irqchip_init, + .init_time = r8a7790_timer_init, + .init_machine = lager_add_standard_devices, + .dt_compat = lager_boards_compat_dt, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0319-ARM-shmobile-sh73a0-Remove-init_irq-declaration-in-m.patch b/patches.renesas/0319-ARM-shmobile-sh73a0-Remove-init_irq-declaration-in-m.patch new file mode 100644 index 00000000000..50552acde49 --- /dev/null +++ b/patches.renesas/0319-ARM-shmobile-sh73a0-Remove-init_irq-declaration-in-m.patch @@ -0,0 +1,42 @@ +From 89921647f8cf27d8bf49b706cc9ac3334ccf1756 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard <maxime.ripard@free-electrons.com> +Date: Mon, 27 May 2013 18:00:49 +0900 +Subject: ARM: shmobile: sh73a0: Remove init_irq declaration in machine + description + +Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is +specified") removed the need to explictly setup the init_irq field in +the machine description when using only irqchip_init. Remove that +declaration for shmobile as well. + +Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 7d6b8883547feacc705c476cdb7f272e309d9fb0) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-sh73a0.c | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c +index 79a60407..bd9370f2 100644 +--- a/arch/arm/mach-shmobile/setup-sh73a0.c ++++ b/arch/arm/mach-shmobile/setup-sh73a0.c +@@ -22,7 +22,6 @@ + #include <linux/init.h> + #include <linux/interrupt.h> + #include <linux/irq.h> +-#include <linux/irqchip.h> + #include <linux/platform_device.h> + #include <linux/of_platform.h> + #include <linux/delay.h> +@@ -975,7 +974,6 @@ DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)") + .map_io = sh73a0_map_io, + .init_early = sh73a0_init_delay, + .nr_irqs = NR_IRQS_LEGACY, +- .init_irq = irqchip_init, + .init_machine = sh73a0_add_standard_devices_dt, + .dt_compat = sh73a0_boards_compat_dt, + MACHINE_END +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0320-ARM-shmobile-kzm9g-Remove-init_irq-declaration-in-ma.patch b/patches.renesas/0320-ARM-shmobile-kzm9g-Remove-init_irq-declaration-in-ma.patch new file mode 100644 index 00000000000..f7688dc89b0 --- /dev/null +++ b/patches.renesas/0320-ARM-shmobile-kzm9g-Remove-init_irq-declaration-in-ma.patch @@ -0,0 +1,44 @@ +From 633e3548f60e716dd726af48cea453556f7b1f55 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Mon, 1 Jul 2013 15:01:40 +0900 +Subject: ARM: shmobile: kzm9g: Remove init_irq declaration in machine + description + +Remove redundant irqchip_init() callback. The default case +of NULL will result in invoking irqchip_init() anyway. + +Signed-off-by: Magnus Damm <damm@opensource.se> +[ horms+renesas@verge.net.au: Trimmed patch to remove portion + that updates the sh73a0 SoC and altered the subject to + use the same format as the patch that updates the sh73a0. ] +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit fc492ba58aa6642f34eba716daf6ec4d2715e492) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-kzm9g-reference.c | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c +index 44055fe8..41092bb0 100644 +--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c ++++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c +@@ -24,7 +24,6 @@ + #include <linux/gpio.h> + #include <linux/io.h> + #include <linux/irq.h> +-#include <linux/irqchip.h> + #include <linux/input.h> + #include <linux/of_platform.h> + #include <linux/pinctrl/machine.h> +@@ -99,7 +98,6 @@ DT_MACHINE_START(KZM9G_DT, "kzm9g-reference") + .map_io = sh73a0_map_io, + .init_early = sh73a0_init_delay, + .nr_irqs = NR_IRQS_LEGACY, +- .init_irq = irqchip_init, + .init_machine = kzm_init, + .init_time = shmobile_timer_init, + .dt_compat = kzm9g_boards_compat_dt, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0321-ARM-shmobile-Remove-unused-EMEV2-auxdata-and-callbac.patch b/patches.renesas/0321-ARM-shmobile-Remove-unused-EMEV2-auxdata-and-callbac.patch new file mode 100644 index 00000000000..8898c510660 --- /dev/null +++ b/patches.renesas/0321-ARM-shmobile-Remove-unused-EMEV2-auxdata-and-callbac.patch @@ -0,0 +1,48 @@ +From ee1fbd49bb33d4b6847d4d8bad551d1780c2c637 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Mon, 1 Jul 2013 14:41:15 +0900 +Subject: ARM: shmobile: Remove unused EMEV2 auxdata and callback + +Replace the SoC-specific callback init_machine() with +a NULL to use the default code. This cleans up the code +and reduces the number of lines. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit a597d8df88143f7a409b260b1e89735eb0bdca05) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-emev2.c | 10 ---------- + 1 file changed, 10 deletions(-) + +diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c +index 6e8b6ac3..b0564ce1 100644 +--- a/arch/arm/mach-shmobile/setup-emev2.c ++++ b/arch/arm/mach-shmobile/setup-emev2.c +@@ -434,15 +434,6 @@ void __init emev2_init_irq(void) + } + + #ifdef CONFIG_USE_OF +-static const struct of_dev_auxdata emev2_auxdata_lookup[] __initconst = { +- { } +-}; +- +-static void __init emev2_add_standard_devices_dt(void) +-{ +- of_platform_populate(NULL, of_default_bus_match_table, +- emev2_auxdata_lookup, NULL); +-} + + static const char *emev2_boards_compat_dt[] __initdata = { + "renesas,emev2", +@@ -453,7 +444,6 @@ DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)") + .smp = smp_ops(emev2_smp_ops), + .init_early = emev2_init_delay, + .nr_irqs = NR_IRQS_LEGACY, +- .init_machine = emev2_add_standard_devices_dt, + .dt_compat = emev2_boards_compat_dt, + MACHINE_END + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0322-ARM-shmobile-Remove-unused-r8a7740-auxdata-table.patch b/patches.renesas/0322-ARM-shmobile-Remove-unused-r8a7740-auxdata-table.patch new file mode 100644 index 00000000000..4747e0b00f2 --- /dev/null +++ b/patches.renesas/0322-ARM-shmobile-Remove-unused-r8a7740-auxdata-table.patch @@ -0,0 +1,52 @@ +From b306d0cedc421e0cb3e21b42d48cafd9f1409bd7 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Mon, 1 Jul 2013 14:41:24 +0900 +Subject: ARM: shmobile: Remove unused r8a7740 auxdata table + +Pass NULL to of_platform_populate instead of passing +an empty list. This cleans up the code and reduces the +number of lines. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 88378837780166d67a11142cd6f76596c0a2d8c3) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a7740.c | 16 +++++++++++----- + 1 file changed, 11 insertions(+), 5 deletions(-) + +diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c +index 00c5a707..ac29c2ee 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7740.c ++++ b/arch/arm/mach-shmobile/setup-r8a7740.c +@@ -986,16 +986,22 @@ void __init r8a7740_add_early_devices(void) + + #ifdef CONFIG_USE_OF + +-static const struct of_dev_auxdata r8a7740_auxdata_lookup[] __initconst = { +- { } +-}; ++void __init r8a7740_add_early_devices_dt(void) ++{ ++ shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */ ++ ++ early_platform_add_devices(r8a7740_early_devices, ++ ARRAY_SIZE(r8a7740_early_devices)); ++ ++ /* setup early console here as well */ ++ shmobile_setup_console(); ++} + + void __init r8a7740_add_standard_devices_dt(void) + { + platform_add_devices(r8a7740_devices_dt, + ARRAY_SIZE(r8a7740_devices_dt)); +- of_platform_populate(NULL, of_default_bus_match_table, +- r8a7740_auxdata_lookup, NULL); ++ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + } + + void __init r8a7740_init_delay(void) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0323-ARM-shmobile-Remove-unused-r8a7778-auxdata-and-callb.patch b/patches.renesas/0323-ARM-shmobile-Remove-unused-r8a7778-auxdata-and-callb.patch new file mode 100644 index 00000000000..bc4841e36c0 --- /dev/null +++ b/patches.renesas/0323-ARM-shmobile-Remove-unused-r8a7778-auxdata-and-callb.patch @@ -0,0 +1,49 @@ +From 5df0763f88fbf629404113aed711b3c3b3b81ccc Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Mon, 1 Jul 2013 14:41:33 +0900 +Subject: ARM: shmobile: Remove unused r8a7778 auxdata and callback + +Replace the SoC-specific callback init_machine() with +a NULL to use the default code. This cleans up the code +and reduces the number of lines. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 40216263d3d0b9b46688a28a96daf66fe75caa28) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a7778.c | 11 ----------- + 1 file changed, 11 deletions(-) + +diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c +index b70bfeef..2a101ebd 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7778.c ++++ b/arch/arm/mach-shmobile/setup-r8a7778.c +@@ -457,16 +457,6 @@ void __init r8a7778_init_irq_dt(void) + r8a7778_init_irq_common(); + } + +-static const struct of_dev_auxdata r8a7778_auxdata_lookup[] __initconst = { +- {}, +-}; +- +-void __init r8a7778_add_standard_devices_dt(void) +-{ +- of_platform_populate(NULL, of_default_bus_match_table, +- r8a7778_auxdata_lookup, NULL); +-} +- + static const char *r8a7778_compat_dt[] __initdata = { + "renesas,r8a7778", + NULL, +@@ -475,7 +465,6 @@ static const char *r8a7778_compat_dt[] __initdata = { + DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)") + .init_early = r8a7778_init_delay, + .init_irq = r8a7778_init_irq_dt, +- .init_machine = r8a7778_add_standard_devices_dt, + .init_time = shmobile_timer_init, + .dt_compat = r8a7778_compat_dt, + .init_late = r8a7778_init_late, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0324-ARM-shmobile-Remove-unused-r8a7779-auxdata-table.patch b/patches.renesas/0324-ARM-shmobile-Remove-unused-r8a7779-auxdata-table.patch new file mode 100644 index 00000000000..7521bbaeddf --- /dev/null +++ b/patches.renesas/0324-ARM-shmobile-Remove-unused-r8a7779-auxdata-table.patch @@ -0,0 +1,45 @@ +From b43f133f7119e116c86f2088652b270b4d782b53 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Mon, 1 Jul 2013 14:41:46 +0900 +Subject: ARM: shmobile: Remove unused r8a7779 auxdata table + +Pass NULL to of_platform_populate instead of passing +an empty list. This cleans up the code and reduces the +number of lines. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 41b0156ca5a1460f8f6dde7e57baf1b80d6a7030) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a7779.c | 7 +------ + 1 file changed, 1 insertion(+), 6 deletions(-) + +diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c +index 39868776..66d38261 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7779.c ++++ b/arch/arm/mach-shmobile/setup-r8a7779.c +@@ -665,10 +665,6 @@ void __init r8a7779_init_delay(void) + shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */ + } + +-static const struct of_dev_auxdata r8a7779_auxdata_lookup[] __initconst = { +- {}, +-}; +- + void __init r8a7779_add_standard_devices_dt(void) + { + /* clocks are setup late during boot in the case of DT */ +@@ -676,8 +672,7 @@ void __init r8a7779_add_standard_devices_dt(void) + + platform_add_devices(r8a7779_devices_dt, + ARRAY_SIZE(r8a7779_devices_dt)); +- of_platform_populate(NULL, of_default_bus_match_table, +- r8a7779_auxdata_lookup, NULL); ++ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + } + + static const char *r8a7779_compat_dt[] __initdata = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0325-ARM-shmobile-Remove-unused-sh7372-auxdata-table.patch b/patches.renesas/0325-ARM-shmobile-Remove-unused-sh7372-auxdata-table.patch new file mode 100644 index 00000000000..3b5a6e9d9f2 --- /dev/null +++ b/patches.renesas/0325-ARM-shmobile-Remove-unused-sh7372-auxdata-table.patch @@ -0,0 +1,45 @@ +From 176ee5ef359f332b98ef1de3bc72e28016a3cc79 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Mon, 1 Jul 2013 14:41:55 +0900 +Subject: ARM: shmobile: Remove unused sh7372 auxdata table + +Pass NULL to of_platform_populate instead of passing +an empty list. This cleans up the code and reduces the +number of lines. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 975e5af958916f8b76a8926cd4d50c04936d7079) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-sh7372.c | 7 +------ + 1 file changed, 1 insertion(+), 6 deletions(-) + +diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c +index 5502d624..13e6fdbd 100644 +--- a/arch/arm/mach-shmobile/setup-sh7372.c ++++ b/arch/arm/mach-shmobile/setup-sh7372.c +@@ -1147,10 +1147,6 @@ void __init sh7372_add_early_devices_dt(void) + shmobile_setup_console(); + } + +-static const struct of_dev_auxdata sh7372_auxdata_lookup[] __initconst = { +- { } +-}; +- + void __init sh7372_add_standard_devices_dt(void) + { + /* clocks are setup late during boot in the case of DT */ +@@ -1159,8 +1155,7 @@ void __init sh7372_add_standard_devices_dt(void) + platform_add_devices(sh7372_early_devices, + ARRAY_SIZE(sh7372_early_devices)); + +- of_platform_populate(NULL, of_default_bus_match_table, +- sh7372_auxdata_lookup, NULL); ++ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + } + + static const char *sh7372_boards_compat_dt[] __initdata = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0326-ARM-shmobile-Remove-unused-sh73a0-auxdata-table.patch b/patches.renesas/0326-ARM-shmobile-Remove-unused-sh73a0-auxdata-table.patch new file mode 100644 index 00000000000..0551a7c54ad --- /dev/null +++ b/patches.renesas/0326-ARM-shmobile-Remove-unused-sh73a0-auxdata-table.patch @@ -0,0 +1,45 @@ +From 177c8a2f3dde5153a399c10a9eab752376d45185 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Mon, 1 Jul 2013 14:42:04 +0900 +Subject: ARM: shmobile: Remove unused sh73a0 auxdata table + +Pass NULL to of_platform_populate instead of passing +an empty list. This cleans up the code and reduces the +number of lines. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit ea31597fe72245985e9d2521ea7e87acf2f14252) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-sh73a0.c | 7 +------ + 1 file changed, 1 insertion(+), 6 deletions(-) + +diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c +index bd9370f2..516c2391 100644 +--- a/arch/arm/mach-shmobile/setup-sh73a0.c ++++ b/arch/arm/mach-shmobile/setup-sh73a0.c +@@ -944,10 +944,6 @@ void __init sh73a0_add_early_devices(void) + + #ifdef CONFIG_USE_OF + +-static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = { +- {}, +-}; +- + void __init sh73a0_add_standard_devices_dt(void) + { + struct platform_device_info devinfo = { .name = "cpufreq-cpu0", .id = -1, }; +@@ -957,8 +953,7 @@ void __init sh73a0_add_standard_devices_dt(void) + + platform_add_devices(sh73a0_devices_dt, + ARRAY_SIZE(sh73a0_devices_dt)); +- of_platform_populate(NULL, of_default_bus_match_table, +- sh73a0_auxdata_lookup, NULL); ++ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + + /* Instantiate cpufreq-cpu0 */ + platform_device_register_full(&devinfo); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0327-ARM-shmobile-Remove-redundant-r8a7790-callback.patch b/patches.renesas/0327-ARM-shmobile-Remove-redundant-r8a7790-callback.patch new file mode 100644 index 00000000000..c5815d588ef --- /dev/null +++ b/patches.renesas/0327-ARM-shmobile-Remove-redundant-r8a7790-callback.patch @@ -0,0 +1,43 @@ +From 0347449bd0c863b480048ef365a9d3abbccc64d5 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Mon, 1 Jul 2013 14:42:13 +0900 +Subject: ARM: shmobile: Remove redundant r8a7790 callback + +Replace the SoC-specific callback init_machine() with +a NULL to use the default code. This cleans up the code +and reduces the number of lines. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit fdbc45dbbe5a69a2c665630ab577726e01eadf23) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a7790.c | 5 ----- + 1 file changed, 5 deletions(-) + +diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c +index d405dbd4..b7e78b9a 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7790.c ++++ b/arch/arm/mach-shmobile/setup-r8a7790.c +@@ -176,10 +176,6 @@ void __init r8a7790_timer_init(void) + } + + #ifdef CONFIG_USE_OF +-void __init r8a7790_add_standard_devices_dt(void) +-{ +- of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +-} + + static const char *r8a7790_boards_compat_dt[] __initdata = { + "renesas,r8a7790", +@@ -187,7 +183,6 @@ static const char *r8a7790_boards_compat_dt[] __initdata = { + }; + + DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)") +- .init_machine = r8a7790_add_standard_devices_dt, + .init_time = r8a7790_timer_init, + .dt_compat = r8a7790_boards_compat_dt, + MACHINE_END +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0328-ARM-shmobile-Remove-unused-EMEV2-KZM9D-early-console.patch b/patches.renesas/0328-ARM-shmobile-Remove-unused-EMEV2-KZM9D-early-console.patch new file mode 100644 index 00000000000..259d0470b4f --- /dev/null +++ b/patches.renesas/0328-ARM-shmobile-Remove-unused-EMEV2-KZM9D-early-console.patch @@ -0,0 +1,102 @@ +From a3d7e5372efaeeffdf4de806edf62b8d945232c5 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Tue, 2 Jul 2013 18:27:33 +0900 +Subject: ARM: shmobile: Remove unused EMEV2/KZM9D early console + +Remove EMEV2 early console code from KZM9D and instead +rely on console setup during regular platform device +probe time. This makes the DT code and the KZM9D board +support behave the same. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Acked-by: Arnd Bergmann <arnd@arndb.de> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 4146fa8861419ac0d2c3607168339621586f6c03) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-kzm9d.c | 2 +- + arch/arm/mach-shmobile/include/mach/emev2.h | 2 +- + arch/arm/mach-shmobile/setup-emev2.c | 24 +++--------------------- + 3 files changed, 5 insertions(+), 23 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-kzm9d.c b/arch/arm/mach-shmobile/board-kzm9d.c +index 4368000e..15900f1f 100644 +--- a/arch/arm/mach-shmobile/board-kzm9d.c ++++ b/arch/arm/mach-shmobile/board-kzm9d.c +@@ -85,7 +85,7 @@ static const char *kzm9d_boards_compat_dt[] __initdata = { + DT_MACHINE_START(KZM9D_DT, "kzm9d") + .smp = smp_ops(emev2_smp_ops), + .map_io = emev2_map_io, +- .init_early = emev2_add_early_devices, ++ .init_early = emev2_init_delay, + .nr_irqs = NR_IRQS_LEGACY, + .init_irq = emev2_init_irq, + .init_machine = kzm9d_add_standard_devices, +diff --git a/arch/arm/mach-shmobile/include/mach/emev2.h b/arch/arm/mach-shmobile/include/mach/emev2.h +index ac375170..3e0c0441 100644 +--- a/arch/arm/mach-shmobile/include/mach/emev2.h ++++ b/arch/arm/mach-shmobile/include/mach/emev2.h +@@ -3,7 +3,7 @@ + + extern void emev2_map_io(void); + extern void emev2_init_irq(void); +-extern void emev2_add_early_devices(void); ++extern void emev2_init_delay(void); + extern void emev2_add_standard_devices(void); + extern void emev2_clock_init(void); + extern void emev2_set_boot_vector(unsigned long value); +diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c +index b0564ce1..f6edd190 100644 +--- a/arch/arm/mach-shmobile/setup-emev2.c ++++ b/arch/arm/mach-shmobile/setup-emev2.c +@@ -375,14 +375,11 @@ static struct platform_device pmu_device = { + .resource = pmu_resources, + }; + +-static struct platform_device *emev2_early_devices[] __initdata = { ++static struct platform_device *emev2_devices[] __initdata = { + &uart0_device, + &uart1_device, + &uart2_device, + &uart3_device, +-}; +- +-static struct platform_device *emev2_late_devices[] __initdata = { + &sti_device, + &gio0_device, + &gio1_device, +@@ -396,29 +393,14 @@ void __init emev2_add_standard_devices(void) + { + emev2_clock_init(); + +- platform_add_devices(emev2_early_devices, +- ARRAY_SIZE(emev2_early_devices)); +- +- platform_add_devices(emev2_late_devices, +- ARRAY_SIZE(emev2_late_devices)); ++ platform_add_devices(emev2_devices, ARRAY_SIZE(emev2_devices)); + } + +-static void __init emev2_init_delay(void) ++void __init emev2_init_delay(void) + { + shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */ + } + +-void __init emev2_add_early_devices(void) +-{ +- emev2_init_delay(); +- +- early_platform_add_devices(emev2_early_devices, +- ARRAY_SIZE(emev2_early_devices)); +- +- /* setup early console here as well */ +- shmobile_setup_console(); +-} +- + void __init emev2_init_irq(void) + { + void __iomem *gic_dist_base; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0329-ARM-shmobile-Make-EMEV2-platform-devices-more-compac.patch b/patches.renesas/0329-ARM-shmobile-Make-EMEV2-platform-devices-more-compac.patch new file mode 100644 index 00000000000..9846fb68e5b --- /dev/null +++ b/patches.renesas/0329-ARM-shmobile-Make-EMEV2-platform-devices-more-compac.patch @@ -0,0 +1,416 @@ +From c97dd1598688341fc1c62d3e172ea7ea58d67fe6 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Tue, 2 Jul 2013 18:27:49 +0900 +Subject: ARM: shmobile: Make EMEV2 platform devices more compact + +Convert the EMEV2 SoC device setup code from using very +verbose resources and static platform devices to the +same style as more recent boards. This reduces the size +of the code. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Acked-by: Arnd Bergmann <arnd@arndb.de> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 210e179da2e39c965872b941a36e55ab78328e49) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-emev2.c | 321 +++++++---------------------------- + 1 file changed, 61 insertions(+), 260 deletions(-) + +diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c +index f6edd190..e4b46930 100644 +--- a/arch/arm/mach-shmobile/setup-emev2.c ++++ b/arch/arm/mach-shmobile/setup-emev2.c +@@ -62,102 +62,40 @@ void __init emev2_map_io(void) + + /* UART */ + static struct resource uart0_resources[] = { +- [0] = { +- .start = 0xe1020000, +- .end = 0xe1020037, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = 40, +- .flags = IORESOURCE_IRQ, +- } +-}; +- +-static struct platform_device uart0_device = { +- .name = "serial8250-em", +- .id = 0, +- .num_resources = ARRAY_SIZE(uart0_resources), +- .resource = uart0_resources, ++ DEFINE_RES_MEM(0xe1020000, 0x38), ++ DEFINE_RES_IRQ(40), + }; + + static struct resource uart1_resources[] = { +- [0] = { +- .start = 0xe1030000, +- .end = 0xe1030037, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = 41, +- .flags = IORESOURCE_IRQ, +- } +-}; +- +-static struct platform_device uart1_device = { +- .name = "serial8250-em", +- .id = 1, +- .num_resources = ARRAY_SIZE(uart1_resources), +- .resource = uart1_resources, ++ DEFINE_RES_MEM(0xe1030000, 0x38), ++ DEFINE_RES_IRQ(41), + }; + + static struct resource uart2_resources[] = { +- [0] = { +- .start = 0xe1040000, +- .end = 0xe1040037, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = 42, +- .flags = IORESOURCE_IRQ, +- } +-}; +- +-static struct platform_device uart2_device = { +- .name = "serial8250-em", +- .id = 2, +- .num_resources = ARRAY_SIZE(uart2_resources), +- .resource = uart2_resources, ++ DEFINE_RES_MEM(0xe1040000, 0x38), ++ DEFINE_RES_IRQ(42), + }; + + static struct resource uart3_resources[] = { +- [0] = { +- .start = 0xe1050000, +- .end = 0xe1050037, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = 43, +- .flags = IORESOURCE_IRQ, +- } ++ DEFINE_RES_MEM(0xe1050000, 0x38), ++ DEFINE_RES_IRQ(43), + }; + +-static struct platform_device uart3_device = { +- .name = "serial8250-em", +- .id = 3, +- .num_resources = ARRAY_SIZE(uart3_resources), +- .resource = uart3_resources, +-}; ++#define emev2_register_uart(idx) \ ++ platform_device_register_simple("serial8250-em", idx, \ ++ uart##idx##_resources, \ ++ ARRAY_SIZE(uart##idx##_resources)) + + /* STI */ + static struct resource sti_resources[] = { +- [0] = { +- .name = "STI", +- .start = 0xe0180000, +- .end = 0xe0180053, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = 157, +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device sti_device = { +- .name = "em_sti", +- .id = 0, +- .resource = sti_resources, +- .num_resources = ARRAY_SIZE(sti_resources), ++ DEFINE_RES_MEM(0xe0180000, 0x54), ++ DEFINE_RES_IRQ(157), + }; + ++#define emev2_register_sti() \ ++ platform_device_register_simple("em_sti", 0, \ ++ sti_resources, \ ++ ARRAY_SIZE(sti_resources)) + + /* GIO */ + static struct gpio_em_config gio0_config = { +@@ -167,36 +105,10 @@ static struct gpio_em_config gio0_config = { + }; + + static struct resource gio0_resources[] = { +- [0] = { +- .name = "GIO_000", +- .start = 0xe0050000, +- .end = 0xe005002b, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .name = "GIO_000", +- .start = 0xe0050040, +- .end = 0xe005005f, +- .flags = IORESOURCE_MEM, +- }, +- [2] = { +- .start = 99, +- .flags = IORESOURCE_IRQ, +- }, +- [3] = { +- .start = 100, +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device gio0_device = { +- .name = "em_gio", +- .id = 0, +- .resource = gio0_resources, +- .num_resources = ARRAY_SIZE(gio0_resources), +- .dev = { +- .platform_data = &gio0_config, +- }, ++ DEFINE_RES_MEM(0xe0050000, 0x2c), ++ DEFINE_RES_MEM(0xe0050040, 0x20), ++ DEFINE_RES_IRQ(99), ++ DEFINE_RES_IRQ(100), + }; + + static struct gpio_em_config gio1_config = { +@@ -206,36 +118,10 @@ static struct gpio_em_config gio1_config = { + }; + + static struct resource gio1_resources[] = { +- [0] = { +- .name = "GIO_032", +- .start = 0xe0050080, +- .end = 0xe00500ab, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .name = "GIO_032", +- .start = 0xe00500c0, +- .end = 0xe00500df, +- .flags = IORESOURCE_MEM, +- }, +- [2] = { +- .start = 101, +- .flags = IORESOURCE_IRQ, +- }, +- [3] = { +- .start = 102, +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device gio1_device = { +- .name = "em_gio", +- .id = 1, +- .resource = gio1_resources, +- .num_resources = ARRAY_SIZE(gio1_resources), +- .dev = { +- .platform_data = &gio1_config, +- }, ++ DEFINE_RES_MEM(0xe0050080, 0x2c), ++ DEFINE_RES_MEM(0xe00500c0, 0x20), ++ DEFINE_RES_IRQ(101), ++ DEFINE_RES_IRQ(102), + }; + + static struct gpio_em_config gio2_config = { +@@ -245,36 +131,10 @@ static struct gpio_em_config gio2_config = { + }; + + static struct resource gio2_resources[] = { +- [0] = { +- .name = "GIO_064", +- .start = 0xe0050100, +- .end = 0xe005012b, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .name = "GIO_064", +- .start = 0xe0050140, +- .end = 0xe005015f, +- .flags = IORESOURCE_MEM, +- }, +- [2] = { +- .start = 103, +- .flags = IORESOURCE_IRQ, +- }, +- [3] = { +- .start = 104, +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device gio2_device = { +- .name = "em_gio", +- .id = 2, +- .resource = gio2_resources, +- .num_resources = ARRAY_SIZE(gio2_resources), +- .dev = { +- .platform_data = &gio2_config, +- }, ++ DEFINE_RES_MEM(0xe0050100, 0x2c), ++ DEFINE_RES_MEM(0xe0050140, 0x20), ++ DEFINE_RES_IRQ(103), ++ DEFINE_RES_IRQ(104), + }; + + static struct gpio_em_config gio3_config = { +@@ -284,36 +144,10 @@ static struct gpio_em_config gio3_config = { + }; + + static struct resource gio3_resources[] = { +- [0] = { +- .name = "GIO_096", +- .start = 0xe0050180, +- .end = 0xe00501ab, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .name = "GIO_096", +- .start = 0xe00501c0, +- .end = 0xe00501df, +- .flags = IORESOURCE_MEM, +- }, +- [2] = { +- .start = 105, +- .flags = IORESOURCE_IRQ, +- }, +- [3] = { +- .start = 106, +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device gio3_device = { +- .name = "em_gio", +- .id = 3, +- .resource = gio3_resources, +- .num_resources = ARRAY_SIZE(gio3_resources), +- .dev = { +- .platform_data = &gio3_config, +- }, ++ DEFINE_RES_MEM(0xe0050180, 0x2c), ++ DEFINE_RES_MEM(0xe00501c0, 0x20), ++ DEFINE_RES_IRQ(105), ++ DEFINE_RES_IRQ(106), + }; + + static struct gpio_em_config gio4_config = { +@@ -323,77 +157,44 @@ static struct gpio_em_config gio4_config = { + }; + + static struct resource gio4_resources[] = { +- [0] = { +- .name = "GIO_128", +- .start = 0xe0050200, +- .end = 0xe005022b, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .name = "GIO_128", +- .start = 0xe0050240, +- .end = 0xe005025f, +- .flags = IORESOURCE_MEM, +- }, +- [2] = { +- .start = 107, +- .flags = IORESOURCE_IRQ, +- }, +- [3] = { +- .start = 108, +- .flags = IORESOURCE_IRQ, +- }, ++ DEFINE_RES_MEM(0xe0050200, 0x2c), ++ DEFINE_RES_MEM(0xe0050240, 0x20), ++ DEFINE_RES_IRQ(107), ++ DEFINE_RES_IRQ(108), + }; + +-static struct platform_device gio4_device = { +- .name = "em_gio", +- .id = 4, +- .resource = gio4_resources, +- .num_resources = ARRAY_SIZE(gio4_resources), +- .dev = { +- .platform_data = &gio4_config, +- }, +-}; ++#define emev2_register_gio(idx) \ ++ platform_device_register_resndata(&platform_bus, "em_gio", \ ++ idx, gio##idx##_resources, \ ++ ARRAY_SIZE(gio##idx##_resources), \ ++ &gio##idx##_config, \ ++ sizeof(struct gpio_em_config)) + + static struct resource pmu_resources[] = { +- [0] = { +- .start = 152, +- .end = 152, +- .flags = IORESOURCE_IRQ, +- }, +- [1] = { +- .start = 153, +- .end = 153, +- .flags = IORESOURCE_IRQ, +- }, ++ DEFINE_RES_IRQ(152), ++ DEFINE_RES_IRQ(153), + }; + +-static struct platform_device pmu_device = { +- .name = "arm-pmu", +- .id = -1, +- .num_resources = ARRAY_SIZE(pmu_resources), +- .resource = pmu_resources, +-}; +- +-static struct platform_device *emev2_devices[] __initdata = { +- &uart0_device, +- &uart1_device, +- &uart2_device, +- &uart3_device, +- &sti_device, +- &gio0_device, +- &gio1_device, +- &gio2_device, +- &gio3_device, +- &gio4_device, +- &pmu_device, +-}; ++#define emev2_register_pmu() \ ++ platform_device_register_simple("arm-pmu", -1, \ ++ pmu_resources, \ ++ ARRAY_SIZE(pmu_resources)) + + void __init emev2_add_standard_devices(void) + { + emev2_clock_init(); + +- platform_add_devices(emev2_devices, ARRAY_SIZE(emev2_devices)); ++ emev2_register_uart(0); ++ emev2_register_uart(1); ++ emev2_register_uart(2); ++ emev2_register_uart(3); ++ emev2_register_sti(); ++ emev2_register_gio(0); ++ emev2_register_gio(1); ++ emev2_register_gio(2); ++ emev2_register_gio(3); ++ emev2_register_gio(4); ++ emev2_register_pmu(); + } + + void __init emev2_init_delay(void) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0330-ARM-shmobile-Fix-EMEV2-clock-comment-typo.patch b/patches.renesas/0330-ARM-shmobile-Fix-EMEV2-clock-comment-typo.patch new file mode 100644 index 00000000000..e1a5ca82a45 --- /dev/null +++ b/patches.renesas/0330-ARM-shmobile-Fix-EMEV2-clock-comment-typo.patch @@ -0,0 +1,32 @@ +From 4bb8bf0a1b3ae2064604bef04e50a5beb096b705 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Mon, 8 Jul 2013 15:20:05 +0900 +Subject: ARM: shmobile: Fix EMEV2 clock comment typo + +Update the STI timer frequency comment to 32.768 kHz to +fix 37 kHz typo. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 09cb2e366737ac70f1d7c6c0a3747a75c8f90f1e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-emev2.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/clock-emev2.c b/arch/arm/mach-shmobile/clock-emev2.c +index 4710f184..56dd0cfc 100644 +--- a/arch/arm/mach-shmobile/clock-emev2.c ++++ b/arch/arm/mach-shmobile/clock-emev2.c +@@ -221,7 +221,7 @@ void __init emev2_clock_init(void) + smu_base = ioremap(EMEV2_SMU_BASE, PAGE_SIZE); + BUG_ON(!smu_base); + +- /* setup STI timer to run on 37.768 kHz and deassert reset */ ++ /* setup STI timer to run on 32.768 kHz and deassert reset */ + emev2_smu_write(0, STI_CLKSEL); + emev2_smu_write(1, STI_RSTCTRL); + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0331-ARM-shmobile-r8a7778-remove-r8a7778_init_irq.patch b/patches.renesas/0331-ARM-shmobile-r8a7778-remove-r8a7778_init_irq.patch new file mode 100644 index 00000000000..59cdd4f2bce --- /dev/null +++ b/patches.renesas/0331-ARM-shmobile-r8a7778-remove-r8a7778_init_irq.patch @@ -0,0 +1,99 @@ +From a4b90b94740c37bab74fd467ab2344e656cc9b92 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 9 Jul 2013 01:48:34 -0700 +Subject: ARM: shmobile: r8a7778: remove r8a7778_init_irq() + +This patch removes r8a7778_init_irq(), since no-one is using it. +And now, there is no reason to have r8a7778_init_irq_common(). +r8a7778_init_irq_dt() includes it. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Acked-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 54aa4c48bc0d364565e7d1c722b07314efdc2a10) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/include/mach/r8a7778.h | 1 - + arch/arm/mach-shmobile/setup-r8a7778.c | 37 +++++++-------------------- + 2 files changed, 9 insertions(+), 29 deletions(-) + +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h +index 851d027a..9b561bf4 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h +@@ -33,7 +33,6 @@ extern void r8a7778_add_mmc_device(struct sh_mmcif_plat_data *info); + + extern void r8a7778_init_late(void); + extern void r8a7778_init_delay(void); +-extern void r8a7778_init_irq(void); + extern void r8a7778_init_irq_dt(void); + extern void r8a7778_clock_init(void); + extern void r8a7778_init_irq_extpin(int irlm); +diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c +index 2a101ebd..a3a2e37b 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7778.c ++++ b/arch/arm/mach-shmobile/setup-r8a7778.c +@@ -408,17 +408,25 @@ void __init r8a7778_init_irq_extpin(int irlm) + &irqpin_platform_data, sizeof(irqpin_platform_data)); + } + ++void __init r8a7778_init_delay(void) ++{ ++ shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */ ++} ++ ++#ifdef CONFIG_USE_OF + #define INT2SMSKCR0 0x82288 /* 0xfe782288 */ + #define INT2SMSKCR1 0x8228c /* 0xfe78228c */ + + #define INT2NTSR0 0x00018 /* 0xfe700018 */ + #define INT2NTSR1 0x0002c /* 0xfe70002c */ +-static void __init r8a7778_init_irq_common(void) ++void __init r8a7778_init_irq_dt(void) + { + void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000); + + BUG_ON(!base); + ++ irqchip_init(); ++ + /* route all interrupts to ARM */ + __raw_writel(0x73ffffff, base + INT2NTSR0); + __raw_writel(0xffffffff, base + INT2NTSR1); +@@ -430,33 +438,6 @@ static void __init r8a7778_init_irq_common(void) + iounmap(base); + } + +-void __init r8a7778_init_irq(void) +-{ +- void __iomem *gic_dist_base; +- void __iomem *gic_cpu_base; +- +- gic_dist_base = ioremap_nocache(0xfe438000, PAGE_SIZE); +- gic_cpu_base = ioremap_nocache(0xfe430000, PAGE_SIZE); +- BUG_ON(!gic_dist_base || !gic_cpu_base); +- +- /* use GIC to handle interrupts */ +- gic_init(0, 29, gic_dist_base, gic_cpu_base); +- +- r8a7778_init_irq_common(); +-} +- +-void __init r8a7778_init_delay(void) +-{ +- shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */ +-} +- +-#ifdef CONFIG_USE_OF +-void __init r8a7778_init_irq_dt(void) +-{ +- irqchip_init(); +- r8a7778_init_irq_common(); +-} +- + static const char *r8a7778_compat_dt[] __initdata = { + "renesas,r8a7778", + NULL, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0332-ARM-shmobile-Remove-unused-mach-dma.h.patch b/patches.renesas/0332-ARM-shmobile-Remove-unused-mach-dma.h.patch new file mode 100644 index 00000000000..807191a45a4 --- /dev/null +++ b/patches.renesas/0332-ARM-shmobile-Remove-unused-mach-dma.h.patch @@ -0,0 +1,27 @@ +From 34b1ce5b204fa48dac0f9c2fb36ace5f3f3dc8e5 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Tue, 9 Jul 2013 19:40:16 +0900 +Subject: ARM: shmobile: Remove unused mach/dma.h + +Remove mach-shmobile mach/dma.h since it only +seems to be used on non-mach-shmobile platforms. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit ebd9616f439a8a46b9dca9a272b342f34c5f3614) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/include/mach/dma.h | 1 - + 1 file changed, 1 deletion(-) + delete mode 100644 arch/arm/mach-shmobile/include/mach/dma.h + +diff --git a/arch/arm/mach-shmobile/include/mach/dma.h b/arch/arm/mach-shmobile/include/mach/dma.h +deleted file mode 100644 +index 40a8c178..00000000 +--- a/arch/arm/mach-shmobile/include/mach/dma.h ++++ /dev/null +@@ -1 +0,0 @@ +-/* empty */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0333-ARM-shmobile-Update-romImage-to-relocate-appended-DT.patch b/patches.renesas/0333-ARM-shmobile-Update-romImage-to-relocate-appended-DT.patch new file mode 100644 index 00000000000..1236fae51dd --- /dev/null +++ b/patches.renesas/0333-ARM-shmobile-Update-romImage-to-relocate-appended-DT.patch @@ -0,0 +1,105 @@ +From a525334825811a408225b449440a19fc42af42b7 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Thu, 27 Jun 2013 08:48:07 +0900 +Subject: ARM: shmobile: Update romImage to relocate appended DTB + +Instead of relying of MACH_TYPE for board identification, +update the romImage code to relocate an appended DTB to +the beginning of RAM. This implementation is independent +of ARM_APPENDED_DTB, this because it is necessary to copy +the DTB to memory so the kernel can access it. + +Without this patch Mackerel does not boot via the Mask ROM +over USB (r_usb_boot) - this since non-DT boot was broken +ages ago in commit: + +0ce53cd ARM: mach-shmobile: Use DT_MACHINE for mackerel + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 2c408d149299e99c89fc4be80fb4fe00a7016f02) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/compressed/head-shmobile.S | 43 ++++++++++++++++++++++++++--- + arch/arm/mach-shmobile/include/mach/zboot.h | 2 -- + 2 files changed, 39 insertions(+), 6 deletions(-) + +diff --git a/arch/arm/boot/compressed/head-shmobile.S b/arch/arm/boot/compressed/head-shmobile.S +index e2d63633..e7f80928 100644 +--- a/arch/arm/boot/compressed/head-shmobile.S ++++ b/arch/arm/boot/compressed/head-shmobile.S +@@ -55,12 +55,47 @@ __tmp_stack: + __continue: + #endif /* CONFIG_ZBOOT_ROM_MMC || CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI */ + +- /* Set board ID necessary for boot */ +- ldr r7, 1f @ Set machine type register +- mov r8, #0 @ pass null pointer as atag ++ adr r0, dtb_info ++ ldmia r0, {r1, r3, r4, r5, r7} ++ ++ sub r0, r0, r1 @ calculate the delta offset ++ add r5, r5, r0 @ _edata ++ ++ ldr lr, [r5, #0] @ check if valid DTB is present ++ cmp lr, r3 ++ bne 0f ++ ++ add r9, r7, #31 @ rounded up to a multiple ++ bic r9, r9, #31 @ ... of 32 bytes ++ ++ add r6, r9, r5 @ copy from _edata ++ add r9, r9, r4 @ to MEMORY_START ++ ++1: ldmdb r6!, {r0 - r3, r10 - r12, lr} ++ cmp r6, r5 ++ stmdb r9!, {r0 - r3, r10 - r12, lr} ++ bhi 1b ++ ++ /* Success: Zero board ID, pointer to start of memory for atag/dtb */ ++ mov r7, #0 ++ mov r8, r4 + b 2f + +-1 : .long MACH_TYPE ++ .align 2 ++dtb_info: ++ .word dtb_info ++#ifndef __ARMEB__ ++ .word 0xedfe0dd0 @ sig is 0xd00dfeed big endian ++#else ++ .word 0xd00dfeed ++#endif ++ .word MEMORY_START ++ .word _edata ++ .word 0x4000 @ maximum DTB size ++0: ++ /* Failure: Zero board ID, NULL atag/dtb */ ++ mov r7, #0 ++ mov r8, #0 @ pass null pointer as atag + 2 : + + #endif /* CONFIG_ZBOOT_ROM */ +diff --git a/arch/arm/mach-shmobile/include/mach/zboot.h b/arch/arm/mach-shmobile/include/mach/zboot.h +index f2d8744c..c3c4669a 100644 +--- a/arch/arm/mach-shmobile/include/mach/zboot.h ++++ b/arch/arm/mach-shmobile/include/mach/zboot.h +@@ -1,7 +1,6 @@ + #ifndef ZBOOT_H + #define ZBOOT_H + +-#include <asm/mach-types.h> + #include <mach/zboot_macros.h> + + /************************************************** +@@ -11,7 +10,6 @@ + **************************************************/ + + #ifdef CONFIG_MACH_MACKEREL +-#define MACH_TYPE MACH_TYPE_MACKEREL + #define MEMORY_START 0x40000000 + #include "mach/head-mackerel.txt" + #else +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0334-ARM-mach-shmobile-mackerel-Use-gpio-backlight.patch b/patches.renesas/0334-ARM-mach-shmobile-mackerel-Use-gpio-backlight.patch new file mode 100644 index 00000000000..ce0be98d5b8 --- /dev/null +++ b/patches.renesas/0334-ARM-mach-shmobile-mackerel-Use-gpio-backlight.patch @@ -0,0 +1,112 @@ +From 2b661778a8ceeb1b6f6beccfb52fc711c25e2ae7 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 4 Jul 2013 21:13:27 +0200 +Subject: ARM: mach-shmobile: mackerel: Use gpio-backlight + +Replace the backlight callback with a gpio-backlight platform device. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 14bd03e08831a52035e601ae85b05a4849214ec4) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-mackerel.c | 34 ++++++++++++++++----------------- + 1 file changed, 17 insertions(+), 17 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c +index 85f51a84..af06753e 100644 +--- a/arch/arm/mach-shmobile/board-mackerel.c ++++ b/arch/arm/mach-shmobile/board-mackerel.c +@@ -41,6 +41,7 @@ + #include <linux/mtd/physmap.h> + #include <linux/mtd/sh_flctl.h> + #include <linux/pinctrl/machine.h> ++#include <linux/platform_data/gpio_backlight.h> + #include <linux/pm_clock.h> + #include <linux/regulator/fixed.h> + #include <linux/regulator/machine.h> +@@ -49,7 +50,6 @@ + #include <linux/tca6416_keypad.h> + #include <linux/usb/renesas_usbhs.h> + #include <linux/dma-mapping.h> +- + #include <video/sh_mobile_hdmi.h> + #include <video/sh_mobile_lcdc.h> + #include <media/sh_mobile_ceu.h> +@@ -346,7 +346,7 @@ static struct platform_device meram_device = { + }, + }; + +-/* LCDC */ ++/* LCDC and backlight */ + static struct fb_videomode mackerel_lcdc_modes[] = { + { + .name = "WVGA Panel", +@@ -362,13 +362,6 @@ static struct fb_videomode mackerel_lcdc_modes[] = { + }, + }; + +-static int mackerel_set_brightness(int brightness) +-{ +- gpio_set_value(31, brightness); +- +- return 0; +-} +- + static const struct sh_mobile_meram_cfg lcd_meram_cfg = { + .icb[0] = { + .meram_size = 0x40, +@@ -393,11 +386,6 @@ static struct sh_mobile_lcdc_info lcdc_info = { + .width = 152, + .height = 91, + }, +- .bl_info = { +- .name = "sh_mobile_lcdc_bl", +- .max_brightness = 1, +- .set_brightness = mackerel_set_brightness, +- }, + .meram_cfg = &lcd_meram_cfg, + } + }; +@@ -425,6 +413,20 @@ static struct platform_device lcdc_device = { + }, + }; + ++static struct gpio_backlight_platform_data gpio_backlight_data = { ++ .fbdev = &lcdc_device.dev, ++ .gpio = 31, ++ .def_value = 1, ++ .name = "backlight", ++}; ++ ++static struct platform_device gpio_backlight_device = { ++ .name = "gpio-backlight", ++ .dev = { ++ .platform_data = &gpio_backlight_data, ++ }, ++}; ++ + /* HDMI */ + static struct sh_mobile_hdmi_info hdmi_info = { + .flags = HDMI_SND_SRC_SPDIF, +@@ -1231,6 +1233,7 @@ static struct platform_device *mackerel_devices[] __initdata = { + &nor_flash_device, + &smc911x_device, + &lcdc_device, ++ &gpio_backlight_device, + &usbhs0_device, + &usbhs1_device, + &leds_device, +@@ -1441,9 +1444,6 @@ static void __init mackerel_init(void) + ARRAY_SIZE(mackerel_pinctrl_map)); + sh7372_pinmux_init(); + +- /* backlight, off by default */ +- gpio_request_one(31, GPIOF_OUT_INIT_LOW, NULL); +- + gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ + + /* USBHS0 */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0335-ARM-mach-shmobile-ag5evm-Use-bd6107-backlight-driver.patch b/patches.renesas/0335-ARM-mach-shmobile-ag5evm-Use-bd6107-backlight-driver.patch new file mode 100644 index 00000000000..a85540b9b9f --- /dev/null +++ b/patches.renesas/0335-ARM-mach-shmobile-ag5evm-Use-bd6107-backlight-driver.patch @@ -0,0 +1,128 @@ +From 7933f07ae617c0a58033375d471b513da4341ca7 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 4 Jul 2013 21:13:30 +0200 +Subject: ARM: mach-shmobile: ag5evm: Use bd6107 backlight driver + +Replace the backlight callback with a bd6107 backlight platform device. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 0fb19cdabfc3f8884bac53fd81b02bf61c7904af) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-ag5evm.c | 65 +++++++++-------------------------- + 1 file changed, 16 insertions(+), 49 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c +index c7540710..f6d64495 100644 +--- a/arch/arm/mach-shmobile/board-ag5evm.c ++++ b/arch/arm/mach-shmobile/board-ag5evm.c +@@ -41,6 +41,7 @@ + #include <linux/mmc/sh_mmcif.h> + #include <linux/mmc/sh_mobile_sdhi.h> + #include <linux/mfd/tmio.h> ++#include <linux/platform_data/bd6107.h> + #include <linux/sh_clk.h> + #include <linux/irqchip/arm-gic.h> + #include <video/sh_mobile_lcdc.h> +@@ -291,47 +292,7 @@ static struct platform_device mipidsi0_device = { + }, + }; + +-static unsigned char lcd_backlight_seq[3][2] = { +- { 0x04, 0x07 }, +- { 0x23, 0x80 }, +- { 0x03, 0x01 }, +-}; +- +-static int lcd_backlight_set_brightness(int brightness) +-{ +- struct i2c_adapter *adap; +- struct i2c_msg msg; +- unsigned int i; +- int ret; +- +- if (brightness == 0) { +- /* Reset the chip */ +- gpio_set_value(235, 0); +- mdelay(24); +- gpio_set_value(235, 1); +- return 0; +- } +- +- adap = i2c_get_adapter(1); +- if (adap == NULL) +- return -ENODEV; +- +- for (i = 0; i < ARRAY_SIZE(lcd_backlight_seq); i++) { +- msg.addr = 0x6d; +- msg.buf = &lcd_backlight_seq[i][0]; +- msg.len = 2; +- msg.flags = 0; +- +- ret = i2c_transfer(adap, &msg, 1); +- if (ret < 0) +- break; +- } +- +- i2c_put_adapter(adap); +- return ret < 0 ? ret : 0; +-} +- +-/* LCDC0 */ ++/* LCDC0 and backlight */ + static const struct fb_videomode lcdc0_modes[] = { + { + .name = "R63302(QHD)", +@@ -361,11 +322,6 @@ static struct sh_mobile_lcdc_info lcdc0_info = { + .width = 44, + .height = 79, + }, +- .bl_info = { +- .name = "sh_mobile_lcdc_bl", +- .max_brightness = 1, +- .set_brightness = lcd_backlight_set_brightness, +- }, + .tx_dev = &mipidsi0_device, + } + }; +@@ -394,6 +350,17 @@ static struct platform_device lcdc0_device = { + }, + }; + ++static struct bd6107_platform_data backlight_data = { ++ .fbdev = &lcdc0_device.dev, ++ .reset = 235, ++ .def_value = 0, ++}; ++ ++static struct i2c_board_info backlight_board_info = { ++ I2C_BOARD_INFO("bd6107", 0x6d), ++ .platform_data = &backlight_data, ++}; ++ + /* Fixed 2.8V regulators to be used by SDHI0 */ + static struct regulator_consumer_supply fixed2v8_power_consumers[] = + { +@@ -648,15 +615,15 @@ static void __init ag5evm_init(void) + gpio_set_value(217, 1); + mdelay(100); + +- /* LCD backlight controller */ +- gpio_request_one(235, GPIOF_OUT_INIT_LOW, NULL); /* RESET */ +- lcd_backlight_set_brightness(0); + + #ifdef CONFIG_CACHE_L2X0 + /* Shared attribute override enable, 64K*8way */ + l2x0_init(IOMEM(0xf0100000), 0x00460000, 0xc2000fff); + #endif + sh73a0_add_standard_devices(); ++ ++ i2c_register_board_info(1, &backlight_board_info, 1); ++ + platform_add_devices(ag5evm_devices, ARRAY_SIZE(ag5evm_devices)); + } + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0336-ARM-shmobile-r8a73a4-add-I2C-controller-DT-nodes.patch b/patches.renesas/0336-ARM-shmobile-r8a73a4-add-I2C-controller-DT-nodes.patch new file mode 100644 index 00000000000..3d8473d0385 --- /dev/null +++ b/patches.renesas/0336-ARM-shmobile-r8a73a4-add-I2C-controller-DT-nodes.patch @@ -0,0 +1,110 @@ +From 1f17000eead4e767cdad8058c93b49e36886ef6a Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Thu, 27 Jun 2013 11:47:57 +0200 +Subject: ARM: shmobile: r8a73a4: add I2C controller DT nodes + +Add Device Tree nodes for the 9 I2C controllers on r8a73a4, compatible with +the i2c-sh_mobile.c driver. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit f98c1069bf1748ffa18cbebbc3a9f88dfc19a631) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a73a4.dtsi | 81 ++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 81 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi +index 4ff2019c..4e1ddf0d 100644 +--- a/arch/arm/boot/dts/r8a73a4.dtsi ++++ b/arch/arm/boot/dts/r8a73a4.dtsi +@@ -85,4 +85,85 @@ + interrupt-parent = <&gic>; + interrupts = <0 69 4>; + }; ++ ++ i2c0: i2c@e6500000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "renesas,rmobile-iic"; ++ reg = <0 0xe6500000 0 0x428>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 174 0x4>; ++ }; ++ ++ i2c1: i2c@e6510000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "renesas,rmobile-iic"; ++ reg = <0 0xe6510000 0 0x428>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 175 0x4>; ++ }; ++ ++ i2c2: i2c@e6520000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "renesas,rmobile-iic"; ++ reg = <0 0xe6520000 0 0x428>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 176 0x4>; ++ }; ++ ++ i2c3: i2c@e6530000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "renesas,rmobile-iic"; ++ reg = <0 0xe6530000 0 0x428>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 177 0x4>; ++ }; ++ ++ i2c4: i2c@e6540000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "renesas,rmobile-iic"; ++ reg = <0 0xe6540000 0 0x428>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 178 0x4>; ++ }; ++ ++ i2c5: i2c@e60b0000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "renesas,rmobile-iic"; ++ reg = <0 0xe60b0000 0 0x428>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 179 0x4>; ++ }; ++ ++ i2c6: i2c@e6550000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "renesas,rmobile-iic"; ++ reg = <0 0xe6550000 0 0x428>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 184 0x4>; ++ }; ++ ++ i2c7: i2c@e6560000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "renesas,rmobile-iic"; ++ reg = <0 0xe6560000 0 0x428>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 185 0x4>; ++ }; ++ ++ i2c8: i2c@e6570000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "renesas,rmobile-iic"; ++ reg = <0 0xe6570000 0 0x428>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 173 0x4>; ++ }; + }; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0337-ARM-shmobile-ape6evm-add-CPUFreq-support.patch b/patches.renesas/0337-ARM-shmobile-ape6evm-add-CPUFreq-support.patch new file mode 100644 index 00000000000..a832a2720a6 --- /dev/null +++ b/patches.renesas/0337-ARM-shmobile-ape6evm-add-CPUFreq-support.patch @@ -0,0 +1,50 @@ +From c0a11a29c12ed10a9922b3a7972ad7ddc6ce9898 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Thu, 27 Jun 2013 11:47:58 +0200 +Subject: ARM: shmobile: ape6evm: add CPUFreq support + +This patch adds OPPs to the CA15 DT node and a max8973 DT node to support +clock and voltage scaling, using the cpufreq-cpu0 CPUFreq driver. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 463a2432a435ea3eda4714626f231b7b22f0ac3d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a73a4-ape6evm.dts | 22 ++++++++++++++++++++++ + 1 file changed, 22 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts +index f603c694..e657a9db 100644 +--- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts ++++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts +@@ -50,3 +50,25 @@ + }; + }; + }; ++ ++&i2c5 { ++ vdd_dvfs: max8973@1b { ++ compatible = "maxim,max8973"; ++ reg = <0x1b>; ++ ++ regulator-min-microvolt = <935000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++}; ++ ++&cpu0 { ++ cpu0-supply = <&vdd_dvfs>; ++ operating-points = < ++ /* kHz uV */ ++ 1950000 1115000 ++ 1462500 995000 ++ >; ++ voltage-tolerance = <1>; /* 1% */ ++}; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0338-ARM-shmobile-Update-KZM9D-dts-command-line.patch b/patches.renesas/0338-ARM-shmobile-Update-KZM9D-dts-command-line.patch new file mode 100644 index 00000000000..49e2a5e60cf --- /dev/null +++ b/patches.renesas/0338-ARM-shmobile-Update-KZM9D-dts-command-line.patch @@ -0,0 +1,34 @@ +From b1418a0eea00131ebb8893be810ab0dcb7a90cad Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Tue, 2 Jul 2013 18:27:41 +0900 +Subject: ARM: shmobile: Update KZM9D dts command line + +Update the KZM9D DTS command line to remove following cruft: + - console=tty0 - no graphic support upstream anyway + - earlyprintk= - not supported by the 8250-em driver anyway + - mem= - this is provided via DT anyway + +Signed-off-by: Magnus Damm <damm@opensource.se> +Acked-by: Arnd Bergmann <arnd@arndb.de> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 8f675493f4706a9f92a822121fe38892a08e0161) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/emev2-kzm9d.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts +index b9b3241f..dda13bc0 100644 +--- a/arch/arm/boot/dts/emev2-kzm9d.dts ++++ b/arch/arm/boot/dts/emev2-kzm9d.dts +@@ -21,6 +21,6 @@ + }; + + chosen { +- bootargs = "console=tty0 console=ttyS1,115200n81 earlyprintk=serial8250-em.1,115200n81 mem=128M@0x40000000 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096"; ++ bootargs = "console=ttyS1,115200n81 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096"; + }; + }; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0339-ARM-shmobile-Add-GIO-to-EMEV2-dtsi.patch b/patches.renesas/0339-ARM-shmobile-Add-GIO-to-EMEV2-dtsi.patch new file mode 100644 index 00000000000..84ccc040c98 --- /dev/null +++ b/patches.renesas/0339-ARM-shmobile-Add-GIO-to-EMEV2-dtsi.patch @@ -0,0 +1,94 @@ +From 9583d010e5d626e50778fc8056855ddc86c18bd0 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Tue, 2 Jul 2013 18:27:57 +0900 +Subject: ARM: shmobile: Add GIO to EMEV2 dtsi + +Add GIO0->GIO4 device nodes to the EMEV2 dtsi file. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Acked-by: Arnd Bergmann <arnd@arndb.de> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 12d035b13b224ee69886b64fd33d1c1224e79187) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/emev2.dtsi | 59 ++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 59 insertions(+) + +diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi +index c8a8c08b..99ad2b2e 100644 +--- a/arch/arm/boot/dts/emev2.dtsi ++++ b/arch/arm/boot/dts/emev2.dtsi +@@ -14,6 +14,14 @@ + compatible = "renesas,emev2"; + interrupt-parent = <&gic>; + ++ aliases { ++ gpio0 = &gpio0; ++ gpio1 = &gpio1; ++ gpio2 = &gpio2; ++ gpio3 = &gpio3; ++ gpio4 = &gpio4; ++ }; ++ + cpus { + #address-cells = <1>; + #size-cells = <0>; +@@ -67,4 +75,55 @@ + reg = <0xe1050000 0x38>; + interrupts = <0 11 0>; + }; ++ ++ gpio0: gpio@e0050000 { ++ compatible = "renesas,em-gio"; ++ reg = <0xe0050000 0x2c>, <0xe0050040 0x20>; ++ interrupts = <0 67 0>, <0 68 0>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ngpios = <32>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ gpio1: gpio@e0050080 { ++ compatible = "renesas,em-gio"; ++ reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>; ++ interrupts = <0 69 0>, <0 70 0>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ngpios = <32>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ gpio2: gpio@e0050100 { ++ compatible = "renesas,em-gio"; ++ reg = <0xe0050100 0x2c>, <0xe0050140 0x20>; ++ interrupts = <0 71 0>, <0 72 0>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ngpios = <32>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ gpio3: gpio@e0050180 { ++ compatible = "renesas,em-gio"; ++ reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>; ++ interrupts = <0 73 0>, <0 74 0>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ngpios = <32>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ gpio4: gpio@e0050200 { ++ compatible = "renesas,em-gio"; ++ reg = <0xe0050200 0x2c>, <0xe0050240 0x20>; ++ interrupts = <0 75 0>, <0 76 0>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ngpios = <31>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; + }; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0340-ARM-shmobile-Use-DT-for-GIC-on-EMEV2-and-KZM9D.patch b/patches.renesas/0340-ARM-shmobile-Use-DT-for-GIC-on-EMEV2-and-KZM9D.patch new file mode 100644 index 00000000000..a79a5f6e44c --- /dev/null +++ b/patches.renesas/0340-ARM-shmobile-Use-DT-for-GIC-on-EMEV2-and-KZM9D.patch @@ -0,0 +1,80 @@ +From a06bfc9f3212d5a57302b6b1028b3c90e562ed64 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Tue, 2 Jul 2013 18:28:06 +0900 +Subject: ARM: shmobile: Use DT for GIC on EMEV2 and KZM9D + +Remove the C version of the EMEV2 GIC setup code, +instead rely on GIC information provided by DT. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Acked-by: Arnd Bergmann <arnd@arndb.de> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 23260e1b417843ea875bd7b21f17c5c80031c4cd) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-kzm9d.c | 2 -- + arch/arm/mach-shmobile/include/mach/emev2.h | 1 - + arch/arm/mach-shmobile/setup-emev2.c | 15 --------------- + 3 files changed, 18 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-kzm9d.c b/arch/arm/mach-shmobile/board-kzm9d.c +index 15900f1f..30c2cc69 100644 +--- a/arch/arm/mach-shmobile/board-kzm9d.c ++++ b/arch/arm/mach-shmobile/board-kzm9d.c +@@ -86,8 +86,6 @@ DT_MACHINE_START(KZM9D_DT, "kzm9d") + .smp = smp_ops(emev2_smp_ops), + .map_io = emev2_map_io, + .init_early = emev2_init_delay, +- .nr_irqs = NR_IRQS_LEGACY, +- .init_irq = emev2_init_irq, + .init_machine = kzm9d_add_standard_devices, + .init_late = shmobile_init_late, + .dt_compat = kzm9d_boards_compat_dt, +diff --git a/arch/arm/mach-shmobile/include/mach/emev2.h b/arch/arm/mach-shmobile/include/mach/emev2.h +index 3e0c0441..b0ab4b72 100644 +--- a/arch/arm/mach-shmobile/include/mach/emev2.h ++++ b/arch/arm/mach-shmobile/include/mach/emev2.h +@@ -2,7 +2,6 @@ + #define __ASM_EMEV2_H__ + + extern void emev2_map_io(void); +-extern void emev2_init_irq(void); + extern void emev2_init_delay(void); + extern void emev2_add_standard_devices(void); + extern void emev2_clock_init(void); +diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c +index e4b46930..6fa485da 100644 +--- a/arch/arm/mach-shmobile/setup-emev2.c ++++ b/arch/arm/mach-shmobile/setup-emev2.c +@@ -202,20 +202,6 @@ void __init emev2_init_delay(void) + shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */ + } + +-void __init emev2_init_irq(void) +-{ +- void __iomem *gic_dist_base; +- void __iomem *gic_cpu_base; +- +- /* Static mappings, never released */ +- gic_dist_base = ioremap(0xe0028000, PAGE_SIZE); +- gic_cpu_base = ioremap(0xe0020000, PAGE_SIZE); +- BUG_ON(!gic_dist_base || !gic_cpu_base); +- +- /* Use GIC to handle interrupts */ +- gic_init(0, 29, gic_dist_base, gic_cpu_base); +-} +- + #ifdef CONFIG_USE_OF + + static const char *emev2_boards_compat_dt[] __initdata = { +@@ -226,7 +212,6 @@ static const char *emev2_boards_compat_dt[] __initdata = { + DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)") + .smp = smp_ops(emev2_smp_ops), + .init_early = emev2_init_delay, +- .nr_irqs = NR_IRQS_LEGACY, + .dt_compat = emev2_boards_compat_dt, + MACHINE_END + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0341-ARM-shmobile-Use-DT-for-SMP-on-EMEV2-and-KZM9D.patch b/patches.renesas/0341-ARM-shmobile-Use-DT-for-SMP-on-EMEV2-and-KZM9D.patch new file mode 100644 index 00000000000..b54fc7f7af0 --- /dev/null +++ b/patches.renesas/0341-ARM-shmobile-Use-DT-for-SMP-on-EMEV2-and-KZM9D.patch @@ -0,0 +1,59 @@ +From 8ee97c3dfe2c8d004a29f1508cefabb67c94856c Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Tue, 2 Jul 2013 18:28:14 +0900 +Subject: ARM: shmobile: Use DT for SMP on EMEV2 and KZM9D + +Rework the EMEV2 SMP code to rely on DT for CPU information +instead of reading out number of CPU cores from the SCU. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Acked-by: Arnd Bergmann <arnd@arndb.de> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 683101a66203149da96e93fb8c0740c726bc114f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/smp-emev2.c | 17 +++-------------- + 1 file changed, 3 insertions(+), 14 deletions(-) + +diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c +index 80991b35..97871655 100644 +--- a/arch/arm/mach-shmobile/smp-emev2.c ++++ b/arch/arm/mach-shmobile/smp-emev2.c +@@ -38,9 +38,12 @@ static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct * + + static void __init emev2_smp_prepare_cpus(unsigned int max_cpus) + { ++ /* setup EMEV2 specific SCU base, enable */ ++ shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE); + scu_enable(shmobile_scu_base); + + /* Tell ROM loader about our vector (in headsmp-scu.S, headsmp.S) */ ++ emev2_clock_init(); /* need ioremapped SMU */ + emev2_set_boot_vector(__pa(shmobile_boot_vector)); + shmobile_boot_fn = virt_to_phys(shmobile_boot_scu); + shmobile_boot_arg = (unsigned long)shmobile_scu_base; +@@ -49,21 +52,7 @@ static void __init emev2_smp_prepare_cpus(unsigned int max_cpus) + scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); + } + +-static void __init emev2_smp_init_cpus(void) +-{ +- unsigned int ncores; +- +- /* setup EMEV2 specific SCU base */ +- shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE); +- emev2_clock_init(); /* need ioremapped SMU */ +- +- ncores = shmobile_scu_base ? scu_get_core_count(shmobile_scu_base) : 1; +- +- shmobile_smp_init_cpus(ncores); +-} +- + struct smp_operations emev2_smp_ops __initdata = { +- .smp_init_cpus = emev2_smp_init_cpus, + .smp_prepare_cpus = emev2_smp_prepare_cpus, + .smp_boot_secondary = emev2_boot_secondary, + }; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0342-ARM-shmobile-EMEV2-map_io-update.patch b/patches.renesas/0342-ARM-shmobile-EMEV2-map_io-update.patch new file mode 100644 index 00000000000..53f323b23f2 --- /dev/null +++ b/patches.renesas/0342-ARM-shmobile-EMEV2-map_io-update.patch @@ -0,0 +1,53 @@ +From 4488e71e979312d1be60a082997f73d8ea3e35c7 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Tue, 2 Jul 2013 18:28:22 +0900 +Subject: ARM: shmobile: EMEV2 map_io update + +Update the EMEV2 struct map_desc to exclude the SMU +and also include the ->map_io() callback in the DT +version of EMEV2 board support. + +The EMEV2 SMP code can these days perform ioremap() +early on without the SMU information in the io_desc[]. + +To correctly support SMP in case of DT-only board +support then the ->map_io() callback is needed. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Acked-by: Arnd Bergmann <arnd@arndb.de> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 0ea2b5389ab1b63aa880c5735c15be0b26b91b1a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-emev2.c | 8 +------- + 1 file changed, 1 insertion(+), 7 deletions(-) + +diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c +index 6fa485da..19980be7 100644 +--- a/arch/arm/mach-shmobile/setup-emev2.c ++++ b/arch/arm/mach-shmobile/setup-emev2.c +@@ -38,13 +38,6 @@ + + static struct map_desc emev2_io_desc[] __initdata = { + #ifdef CONFIG_SMP +- /* 128K entity map for 0xe0100000 (SMU) */ +- { +- .virtual = 0xe0100000, +- .pfn = __phys_to_pfn(0xe0100000), +- .length = SZ_128K, +- .type = MT_DEVICE +- }, + /* 2M mapping for SCU + L2 controller */ + { + .virtual = 0xf0000000, +@@ -211,6 +204,7 @@ static const char *emev2_boards_compat_dt[] __initdata = { + + DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)") + .smp = smp_ops(emev2_smp_ops), ++ .map_io = emev2_map_io, + .init_early = emev2_init_delay, + .dt_compat = emev2_boards_compat_dt, + MACHINE_END +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0343-ARM-shmobile-r8a73a4-add-MMCIF-and-SDHI-DT-templates.patch b/patches.renesas/0343-ARM-shmobile-r8a73a4-add-MMCIF-and-SDHI-DT-templates.patch new file mode 100644 index 00000000000..eb85c83e585 --- /dev/null +++ b/patches.renesas/0343-ARM-shmobile-r8a73a4-add-MMCIF-and-SDHI-DT-templates.patch @@ -0,0 +1,74 @@ +From 8dec1e8ce2890c27ae05bfcbce4d6865f20b7f36 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Mon, 8 Jul 2013 17:54:45 +0200 +Subject: ARM: shmobile: r8a73a4: add MMCIF and SDHI DT templates + +This adds DT templates for all MMCIF and SDHI controllers on r8a73a4. +They are added with status="disabled". To use them platform-specific +DTs have to enable the required ones. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 369ee2db438cc0adc6952b424743e9ed21a0edee) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a73a4.dtsi | 45 ++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 45 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi +index 4e1ddf0d..6ce699be 100644 +--- a/arch/arm/boot/dts/r8a73a4.dtsi ++++ b/arch/arm/boot/dts/r8a73a4.dtsi +@@ -166,4 +166,49 @@ + interrupt-parent = <&gic>; + interrupts = <0 173 0x4>; + }; ++ ++ mmcif0: mmcif@ee200000 { ++ compatible = "renesas,sh-mmcif"; ++ reg = <0 0xee200000 0 0x80>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 169 0x4>; ++ reg-io-width = <4>; ++ status = "disabled"; ++ }; ++ ++ mmcif1: mmcif@ee220000 { ++ compatible = "renesas,sh-mmcif"; ++ reg = <0 0xee220000 0 0x80>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 170 0x4>; ++ reg-io-width = <4>; ++ status = "disabled"; ++ }; ++ ++ sdhi0: sdhi@ee100000 { ++ compatible = "renesas,r8a73a4-sdhi"; ++ reg = <0 0xee100000 0 0x100>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 165 4>; ++ cap-sd-highspeed; ++ status = "disabled"; ++ }; ++ ++ sdhi1: sdhi@ee120000 { ++ compatible = "renesas,r8a73a4-sdhi"; ++ reg = <0 0xee120000 0 0x100>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 166 4>; ++ cap-sd-highspeed; ++ status = "disabled"; ++ }; ++ ++ sdhi2: sdhi@ee140000 { ++ compatible = "renesas,r8a73a4-sdhi"; ++ reg = <0 0xee140000 0 0x100>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 167 4>; ++ cap-sd-highspeed; ++ status = "disabled"; ++ }; + }; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0344-ARM-shmobile-r8a7790-add-MMCIF-and-SDHI-DT-templates.patch b/patches.renesas/0344-ARM-shmobile-r8a7790-add-MMCIF-and-SDHI-DT-templates.patch new file mode 100644 index 00000000000..3112c211143 --- /dev/null +++ b/patches.renesas/0344-ARM-shmobile-r8a7790-add-MMCIF-and-SDHI-DT-templates.patch @@ -0,0 +1,83 @@ +From c245ab06ef594187df2b948242fe281d17b6c290 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Mon, 8 Jul 2013 17:54:46 +0200 +Subject: ARM: shmobile: r8a7790: add MMCIF and SDHI DT templates + +This adds DT templates for all MMCIF and SDHI controllers on r8a7790. +They are added with status="disabled". To use them platform-specific +DTs have to enable the required ones. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 8c9b1aa41853272adf505cc22be541f1eac2f94c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7790.dtsi | 54 ++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 54 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi +index 339d9b11..9cd88202 100644 +--- a/arch/arm/boot/dts/r8a7790.dtsi ++++ b/arch/arm/boot/dts/r8a7790.dtsi +@@ -54,4 +54,58 @@ + interrupt-parent = <&gic>; + interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>; + }; ++ ++ mmcif0: mmcif@ee200000 { ++ compatible = "renesas,sh-mmcif"; ++ reg = <0 0xee200000 0 0x80>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 169 0x4>; ++ reg-io-width = <4>; ++ status = "disabled"; ++ }; ++ ++ mmcif1: mmcif@ee220000 { ++ compatible = "renesas,sh-mmcif"; ++ reg = <0 0xee220000 0 0x80>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 170 0x4>; ++ reg-io-width = <4>; ++ status = "disabled"; ++ }; ++ ++ sdhi0: sdhi@ee100000 { ++ compatible = "renesas,r8a7790-sdhi"; ++ reg = <0 0xee100000 0 0x100>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 165 4>; ++ cap-sd-highspeed; ++ status = "disabled"; ++ }; ++ ++ sdhi1: sdhi@ee120000 { ++ compatible = "renesas,r8a7790-sdhi"; ++ reg = <0 0xee120000 0 0x100>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 166 4>; ++ cap-sd-highspeed; ++ status = "disabled"; ++ }; ++ ++ sdhi2: sdhi@ee140000 { ++ compatible = "renesas,r8a7790-sdhi"; ++ reg = <0 0xee140000 0 0x100>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 167 4>; ++ cap-sd-highspeed; ++ status = "disabled"; ++ }; ++ ++ sdhi3: sdhi@ee160000 { ++ compatible = "renesas,r8a7790-sdhi"; ++ reg = <0 0xee160000 0 0x100>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 168 4>; ++ cap-sd-highspeed; ++ status = "disabled"; ++ }; + }; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0345-ARM-shmobile-KZM9D-DT-reference-implementation.patch b/patches.renesas/0345-ARM-shmobile-KZM9D-DT-reference-implementation.patch new file mode 100644 index 00000000000..31495861283 --- /dev/null +++ b/patches.renesas/0345-ARM-shmobile-KZM9D-DT-reference-implementation.patch @@ -0,0 +1,178 @@ +From f951af65ec627cfef358c74ec5b5ac9eb56571a6 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Mon, 8 Jul 2013 15:00:30 +0900 +Subject: ARM: shmobile: KZM9D DT reference implementation + +Add a DT reference implementation for the KZM9D board. + +Only DT devices are used in this case. UART, STI, GPIO +and SMP / GIC are all provided by emev2.dtsi. + +There is still a board specific C file used for enabling +legacy SH clocks. This file will be removed after we have +moved over to common clocks. + +Signed-off-by: Magnus Damm <damm@opensource.se> +[horms+renesas@verge.net.au: Do not include trailing blank line in + board-kzm9d-reference.c ] +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit 03393e8fe651aaf8824c519effbb51bf460ca57f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/Makefile | 1 + + arch/arm/boot/dts/emev2-kzm9d-reference.dts | 26 +++++++++++++++ + arch/arm/mach-shmobile/Kconfig | 12 +++++++ + arch/arm/mach-shmobile/Makefile | 1 + + arch/arm/mach-shmobile/Makefile.boot | 1 + + arch/arm/mach-shmobile/board-kzm9d-reference.c | 46 ++++++++++++++++++++++++++ + 6 files changed, 87 insertions(+) + create mode 100644 arch/arm/boot/dts/emev2-kzm9d-reference.dts + create mode 100644 arch/arm/mach-shmobile/board-kzm9d-reference.c + +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index 389725e5..a77ed45c 100644 +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -160,6 +160,7 @@ dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \ + hrefv60plus.dtb \ + ccu9540.dtb + dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ ++ emev2-kzm9d-reference.dtb \ + r8a7740-armadillo800eva.dtb \ + r8a7778-bockw.dtb \ + r8a7740-armadillo800eva-reference.dtb \ +diff --git a/arch/arm/boot/dts/emev2-kzm9d-reference.dts b/arch/arm/boot/dts/emev2-kzm9d-reference.dts +new file mode 100644 +index 00000000..5ec065ed +--- /dev/null ++++ b/arch/arm/boot/dts/emev2-kzm9d-reference.dts +@@ -0,0 +1,26 @@ ++/* ++ * Device Tree Source for the KZM9D board ++ * ++ * Copyright (C) 2013 Renesas Solutions Corp. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++/dts-v1/; ++ ++/include/ "emev2.dtsi" ++ ++/ { ++ model = "EMEV2 KZM9D Board"; ++ compatible = "renesas,kzm9d-reference", "renesas,emev2"; ++ ++ memory { ++ device_type = "memory"; ++ reg = <0x40000000 0x8000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS1,115200n81 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096"; ++ }; ++}; +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index 3912ce91..7c5034aa 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -156,6 +156,18 @@ config MACH_KZM9D + select REGULATOR_FIXED_VOLTAGE if REGULATOR + select USE_OF + ++config MACH_KZM9D_REFERENCE ++ bool "KZM9D board - Reference Device Tree Implementation" ++ depends on ARCH_EMEV2 ++ select REGULATOR_FIXED_VOLTAGE if REGULATOR ++ select USE_OF ++ ---help--- ++ Use reference implementation of KZM9D board support ++ which makes a greater use of device tree at the expense ++ of not supporting a number of devices. ++ ++ This is intended to aid developers ++ + config MACH_KZM9G + bool "KZM-A9-GT board" + depends on ARCH_SH73A0 +diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile +index 6165a517..e8d0a2c9 100644 +--- a/arch/arm/mach-shmobile/Makefile ++++ b/arch/arm/mach-shmobile/Makefile +@@ -46,6 +46,7 @@ obj-$(CONFIG_MACH_LAGER) += board-lager.o + obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o + obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += board-armadillo800eva-reference.o + obj-$(CONFIG_MACH_KZM9D) += board-kzm9d.o ++obj-$(CONFIG_MACH_KZM9D_REFERENCE) += board-kzm9d-reference.o + obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o + obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o + +diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot +index 84c68685..7785c52b 100644 +--- a/arch/arm/mach-shmobile/Makefile.boot ++++ b/arch/arm/mach-shmobile/Makefile.boot +@@ -7,6 +7,7 @@ loadaddr-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += 0x40008000 + loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000 + loadaddr-$(CONFIG_MACH_KOTA2) += 0x41008000 + loadaddr-$(CONFIG_MACH_KZM9D) += 0x40008000 ++loadaddr-$(CONFIG_MACH_KZM9D_REFERENCE) += 0x40008000 + loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000 + loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000 + loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000 +diff --git a/arch/arm/mach-shmobile/board-kzm9d-reference.c b/arch/arm/mach-shmobile/board-kzm9d-reference.c +new file mode 100644 +index 00000000..a7b28b24 +--- /dev/null ++++ b/arch/arm/mach-shmobile/board-kzm9d-reference.c +@@ -0,0 +1,46 @@ ++/* ++ * kzm9d board support - Reference DT implementation ++ * ++ * Copyright (C) 2013 Renesas Solutions Corp. ++ * Copyright (C) 2013 Magnus Damm ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ++ */ ++ ++#include <linux/init.h> ++#include <linux/of_platform.h> ++#include <mach/emev2.h> ++#include <mach/common.h> ++#include <asm/mach/arch.h> ++ ++static void __init kzm9d_add_standard_devices(void) ++{ ++ emev2_clock_init(); ++ ++ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); ++} ++ ++static const char *kzm9d_boards_compat_dt[] __initdata = { ++ "renesas,kzm9d-reference", ++ NULL, ++}; ++ ++DT_MACHINE_START(KZM9D_DT, "kzm9d") ++ .smp = smp_ops(emev2_smp_ops), ++ .map_io = emev2_map_io, ++ .init_early = emev2_init_delay, ++ .init_machine = kzm9d_add_standard_devices, ++ .init_late = shmobile_init_late, ++ .dt_compat = kzm9d_boards_compat_dt, ++MACHINE_END +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0346-ARM-shmobile-Add-SMSC-ethernet-chip-to-KZM9D-DT-refe.patch b/patches.renesas/0346-ARM-shmobile-Add-SMSC-ethernet-chip-to-KZM9D-DT-refe.patch new file mode 100644 index 00000000000..f22d6e12c6f --- /dev/null +++ b/patches.renesas/0346-ARM-shmobile-Add-SMSC-ethernet-chip-to-KZM9D-DT-refe.patch @@ -0,0 +1,59 @@ +From 95290c24f8bf0c5fcdb4a767c3c6810f44cecb14 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Tue, 9 Jul 2013 13:26:54 +0900 +Subject: ARM: shmobile: Add SMSC ethernet chip to KZM9D DT reference + +Add support for the SMSC ethernet controller found +on the KZM9D board to the KZM9D DT Reference code. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 66a5cab04d339d02b93a4671eadf8e251dbfdc2c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/emev2-kzm9d-reference.dts | 31 +++++++++++++++++++++++++++++ + 1 file changed, 31 insertions(+) + +diff --git a/arch/arm/boot/dts/emev2-kzm9d-reference.dts b/arch/arm/boot/dts/emev2-kzm9d-reference.dts +index 5ec065ed..bed676b9 100644 +--- a/arch/arm/boot/dts/emev2-kzm9d-reference.dts ++++ b/arch/arm/boot/dts/emev2-kzm9d-reference.dts +@@ -23,4 +23,35 @@ + chosen { + bootargs = "console=ttyS1,115200n81 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096"; + }; ++ ++ reg_1p8v: regulator@0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-1.8V"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ reg_3p3v: regulator@1 { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-3.3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ lan9220@20000000 { ++ compatible = "smsc,lan9220", "smsc,lan9115"; ++ reg = <0x20000000 0x10000>; ++ phy-mode = "mii"; ++ interrupt-parent = <&gpio0>; ++ interrupts = <1 1>; /* active high */ ++ reg-io-width = <4>; ++ smsc,irq-active-high; ++ smsc,irq-push-pull; ++ vddvario-supply = <®_1p8v>; ++ vdd33a-supply = <®_3p3v>; ++ }; + }; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0347-ARM-shmobile-r8a7790-add-clocks-for-thermal.patch b/patches.renesas/0347-ARM-shmobile-r8a7790-add-clocks-for-thermal.patch new file mode 100644 index 00000000000..dddbae9bbe1 --- /dev/null +++ b/patches.renesas/0347-ARM-shmobile-r8a7790-add-clocks-for-thermal.patch @@ -0,0 +1,52 @@ +From d0ea31e836a58e9432cdb58f4f5d2998e525cb44 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Wed, 26 Jun 2013 17:34:34 +0900 +Subject: ARM: shmobile: r8a7790: add clocks for thermal + +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit a4b91be0b607ffecf6cf9dacdefcaa0797340e3c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a7790.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c +index 5d71313d..28eccd11 100644 +--- a/arch/arm/mach-shmobile/clock-r8a7790.c ++++ b/arch/arm/mach-shmobile/clock-r8a7790.c +@@ -49,6 +49,7 @@ + + #define SMSTPCR2 0xe6150138 + #define SMSTPCR3 0xe615013c ++#define SMSTPCR5 0xe6150144 + #define SMSTPCR7 0xe615014c + + #define MODEMR 0xE6160060 +@@ -182,6 +183,7 @@ static struct clk div6_clks[DIV6_NR] = { + enum { + MSTP721, MSTP720, + MSTP717, MSTP716, ++ MSTP522, + MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304, + MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, + MSTP_NR +@@ -203,6 +205,7 @@ static struct clk mstp_clks[MSTP_NR] = { + [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */ + [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */ + [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */ ++ [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */ + [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */ + [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */ + }; +@@ -254,6 +257,7 @@ static struct clk_lookup lookups[] = { + CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), + CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]), + CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]), ++ CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), + CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), + CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), + CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0348-ARM-shmobile-r8a7790-add-thermal-driver-support.patch b/patches.renesas/0348-ARM-shmobile-r8a7790-add-thermal-driver-support.patch new file mode 100644 index 00000000000..872f46f6aab --- /dev/null +++ b/patches.renesas/0348-ARM-shmobile-r8a7790-add-thermal-driver-support.patch @@ -0,0 +1,51 @@ +From 095346f86fa0820bc67ae05ba268ac4d285a67c9 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Wed, 26 Jun 2013 16:22:21 +0900 +Subject: ARM: shmobile: r8a7790: add thermal driver support + +The current temperature may be read using: +cat /sys/class/thermal/thermal_zone0/temp + +Based on similar work for the r8a73a4 by Kuninori Morimoto. + +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 0b8eeba45143030e29ec39c43daa1383146581e6) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a7790.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c +index b7e78b9a..bc40a44d 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7790.c ++++ b/arch/arm/mach-shmobile/setup-r8a7790.c +@@ -148,6 +148,17 @@ static struct resource irqc0_resources[] __initdata = { + &irqc##idx##_data, \ + sizeof(struct renesas_irqc_config)) + ++static struct resource thermal_resources[] __initdata = { ++ DEFINE_RES_MEM(0xe61f0000, 0x14), ++ DEFINE_RES_MEM(0xe61f0100, 0x38), ++ DEFINE_RES_IRQ(gic_spi(69)), ++}; ++ ++#define r8a7790_register_thermal() \ ++ platform_device_register_simple("rcar_thermal", -1, \ ++ thermal_resources, \ ++ ARRAY_SIZE(thermal_resources)) ++ + void __init r8a7790_add_standard_devices(void) + { + r8a7790_register_scif(SCIFA0); +@@ -161,6 +172,7 @@ void __init r8a7790_add_standard_devices(void) + r8a7790_register_scif(HSCIF0); + r8a7790_register_scif(HSCIF1); + r8a7790_register_irqc(0); ++ r8a7790_register_thermal(); + } + + void __init r8a7790_timer_init(void) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0349-ARM-shmobile-r8a73a4-wait-for-completion-when-kickin.patch b/patches.renesas/0349-ARM-shmobile-r8a73a4-wait-for-completion-when-kickin.patch new file mode 100644 index 00000000000..6751caf2e05 --- /dev/null +++ b/patches.renesas/0349-ARM-shmobile-r8a73a4-wait-for-completion-when-kickin.patch @@ -0,0 +1,62 @@ +From 51236622278ba440fdc9332bd63faefa21493d58 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Wed, 22 May 2013 11:12:33 +0200 +Subject: ARM: shmobile: r8a73a4: wait for completion when kicking the clock + +To reconfigure clocks, controlled by FRQCRA and FRQCRB, a kick bit has to +be set and to make sure the setting has taken effect, it has to be read +back repeatedly until it is cleared by the hardware. This patch adds the +waiting part, that was missing until now. + +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 8d27657286a1e9e6ee7adaf4d0638cefd708a6fa) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a73a4.c | 22 ++++++++++++++++------ + 1 file changed, 16 insertions(+), 6 deletions(-) + +diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c +index 5f7fe628..d5176d08 100644 +--- a/arch/arm/mach-shmobile/clock-r8a73a4.c ++++ b/arch/arm/mach-shmobile/clock-r8a73a4.c +@@ -184,6 +184,21 @@ PLL_CLOCK(pll2h_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2HCR, 5); + + SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2); + ++static int frqcr_kick_do(struct clk *clk) ++{ ++ int i; ++ ++ /* set KICK bit in FRQCRB to update hardware setting, check success */ ++ iowrite32(ioread32(CPG_MAP(FRQCRB)) | BIT(31), CPG_MAP(FRQCRB)); ++ for (i = 1000; i; i--) ++ if (ioread32(CPG_MAP(FRQCRB)) & BIT(31)) ++ cpu_relax(); ++ else ++ return 0; ++ ++ return -ETIMEDOUT; ++} ++ + static struct clk *main_clks[] = { + &extalr_clk, + &extal1_clk, +@@ -205,12 +220,7 @@ static struct clk *main_clks[] = { + /* DIV4 */ + static void div4_kick(struct clk *clk) + { +- unsigned long value; +- +- /* set KICK bit in FRQCRB to update hardware setting */ +- value = ioread32(CPG_MAP(FRQCRB)); +- value |= (1 << 31); +- iowrite32(value, CPG_MAP(FRQCRB)); ++ frqcr_kick_do(clk); + } + + static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10}; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0350-ARM-shmobile-r8a73a4-implement-CPU-clock-scaling-for.patch b/patches.renesas/0350-ARM-shmobile-r8a73a4-implement-CPU-clock-scaling-for.patch new file mode 100644 index 00000000000..1b20e4adbe0 --- /dev/null +++ b/patches.renesas/0350-ARM-shmobile-r8a73a4-implement-CPU-clock-scaling-for.patch @@ -0,0 +1,243 @@ +From 5827424148199c559c8145e540f5be9f32927154 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Wed, 22 May 2013 11:12:37 +0200 +Subject: ARM: shmobile: r8a73a4: implement CPU clock scaling for CPUFreq + +This patch adds support for the Z-clock on r8a73a4 SoCs, which is driving +the Cortex A15 core, and a "cpufreq-cpu0" platform device. Adding an +"operating-points" property to the CPU0 DT node and a regulator, this +patch allows platforms to use the generic cpufreq-cpu0 driver to use +SoC's DVFS capabilities. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 181135e0b7f58735969619c89548f6a37cd0ee36) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/Kconfig | 2 + + arch/arm/mach-shmobile/clock-r8a73a4.c | 123 ++++++++++++++++++++++++++++++++- + arch/arm/mach-shmobile/setup-r8a73a4.c | 1 + + 3 files changed, 125 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index 7c5034aa..734b3eec 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -26,6 +26,8 @@ config ARCH_R8A73A4 + select HAVE_ARM_ARCH_TIMER + select SH_CLK_CPG + select RENESAS_IRQC ++ select ARCH_HAS_CPUFREQ ++ select ARCH_HAS_OPP + + config ARCH_R8A7740 + bool "R-Mobile A1 (R8A77400)" +diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c +index d5176d08..824789c2 100644 +--- a/arch/arm/mach-shmobile/clock-r8a73a4.c ++++ b/arch/arm/mach-shmobile/clock-r8a73a4.c +@@ -34,6 +34,7 @@ + + #define FRQCRA 0xE6150000 + #define FRQCRB 0xE6150004 ++#define FRQCRC 0xE61500E0 + #define VCLKCR1 0xE6150008 + #define VCLKCR2 0xE615000C + #define VCLKCR3 0xE615001C +@@ -52,6 +53,7 @@ + #define HSICKCR 0xE615026C + #define M4CKCR 0xE6150098 + #define PLLECR 0xE61500D0 ++#define PLL0CR 0xE61500D8 + #define PLL1CR 0xE6150028 + #define PLL2CR 0xE615002C + #define PLL2SCR 0xE61501F4 +@@ -177,6 +179,7 @@ static struct sh_clk_ops pll_clk_ops = { + .mapping = &cpg_mapping, \ + } + ++PLL_CLOCK(pll0_clk, &main_clk, pll_parent_main, 1, 20, PLL0CR, 0); + PLL_CLOCK(pll1_clk, &main_clk, pll_parent_main, 1, 7, PLL1CR, 1); + PLL_CLOCK(pll2_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2CR, 2); + PLL_CLOCK(pll2s_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2SCR, 4); +@@ -184,6 +187,14 @@ PLL_CLOCK(pll2h_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2HCR, 5); + + SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2); + ++static atomic_t frqcr_lock; ++ ++/* Several clocks need to access FRQCRB, have to lock */ ++static bool frqcr_kick_check(struct clk *clk) ++{ ++ return !(ioread32(CPG_MAP(FRQCRB)) & BIT(31)); ++} ++ + static int frqcr_kick_do(struct clk *clk) + { + int i; +@@ -199,6 +210,107 @@ static int frqcr_kick_do(struct clk *clk) + return -ETIMEDOUT; + } + ++static int zclk_set_rate(struct clk *clk, unsigned long rate) ++{ ++ void __iomem *frqcrc; ++ int ret; ++ unsigned long step, p_rate; ++ u32 val; ++ ++ if (!clk->parent || !__clk_get(clk->parent)) ++ return -ENODEV; ++ ++ if (!atomic_inc_and_test(&frqcr_lock) || !frqcr_kick_check(clk)) { ++ ret = -EBUSY; ++ goto done; ++ } ++ ++ frqcrc = clk->mapped_reg + (FRQCRC - (u32)clk->enable_reg); ++ ++ p_rate = clk_get_rate(clk->parent); ++ if (rate == p_rate) { ++ val = 0; ++ } else { ++ step = DIV_ROUND_CLOSEST(p_rate, 32); ++ val = 32 - rate / step; ++ } ++ ++ iowrite32((ioread32(frqcrc) & ~(clk->div_mask << clk->enable_bit)) | ++ (val << clk->enable_bit), frqcrc); ++ ++ ret = frqcr_kick_do(clk); ++ ++done: ++ atomic_dec(&frqcr_lock); ++ __clk_put(clk->parent); ++ return ret; ++} ++ ++static long zclk_round_rate(struct clk *clk, unsigned long rate) ++{ ++ /* ++ * theoretical rate = parent rate * multiplier / 32, ++ * where 1 <= multiplier <= 32. Therefore we should do ++ * multiplier = rate * 32 / parent rate ++ * rounded rate = parent rate * multiplier / 32. ++ * However, multiplication before division won't fit in 32 bits, so ++ * we sacrifice some precision by first dividing and then multiplying. ++ * To find the nearest divisor we calculate both and pick up the best ++ * one. This avoids 64-bit arithmetics. ++ */ ++ unsigned long step, mul_min, mul_max, rate_min, rate_max; ++ ++ rate_max = clk_get_rate(clk->parent); ++ ++ /* output freq <= parent */ ++ if (rate >= rate_max) ++ return rate_max; ++ ++ step = DIV_ROUND_CLOSEST(rate_max, 32); ++ /* output freq >= parent / 32 */ ++ if (step >= rate) ++ return step; ++ ++ mul_min = rate / step; ++ mul_max = DIV_ROUND_UP(rate, step); ++ rate_min = step * mul_min; ++ if (mul_max == mul_min) ++ return rate_min; ++ ++ rate_max = step * mul_max; ++ ++ if (rate_max - rate < rate - rate_min) ++ return rate_max; ++ ++ return rate_min; ++} ++ ++static unsigned long zclk_recalc(struct clk *clk) ++{ ++ void __iomem *frqcrc = FRQCRC - (u32)clk->enable_reg + clk->mapped_reg; ++ unsigned int max = clk->div_mask + 1; ++ unsigned long val = ((ioread32(frqcrc) >> clk->enable_bit) & ++ clk->div_mask); ++ ++ return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), max) * ++ (max - val); ++} ++ ++static struct sh_clk_ops zclk_ops = { ++ .recalc = zclk_recalc, ++ .set_rate = zclk_set_rate, ++ .round_rate = zclk_round_rate, ++}; ++ ++static struct clk z_clk = { ++ .parent = &pll0_clk, ++ .div_mask = 0x1f, ++ .enable_bit = 8, ++ /* We'll need to access FRQCRB and FRQCRC */ ++ .enable_reg = (void __iomem *)FRQCRB, ++ .ops = &zclk_ops, ++}; ++ + static struct clk *main_clks[] = { + &extalr_clk, + &extal1_clk, +@@ -210,17 +322,21 @@ static struct clk *main_clks[] = { + &main_div2_clk, + &fsiack_clk, + &fsibck_clk, ++ &pll0_clk, + &pll1_clk, + &pll1_div2_clk, + &pll2_clk, + &pll2s_clk, + &pll2h_clk, ++ &z_clk, + }; + + /* DIV4 */ + static void div4_kick(struct clk *clk) + { +- frqcr_kick_do(clk); ++ if (!WARN(!atomic_inc_and_test(&frqcr_lock), "FRQCR* lock broken!\n")) ++ frqcr_kick_do(clk); ++ atomic_dec(&frqcr_lock); + } + + static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10}; +@@ -396,6 +512,9 @@ static struct clk_lookup lookups[] = { + CLKDEV_CON_ID("pll2s", &pll2s_clk), + CLKDEV_CON_ID("pll2h", &pll2h_clk), + ++ /* CPU clock */ ++ CLKDEV_DEV_ID("cpufreq-cpu0", &z_clk), ++ + /* DIV6 */ + CLKDEV_CON_ID("zb", &div6_clks[DIV6_ZB]), + CLKDEV_CON_ID("vck1", &div6_clks[DIV6_VCK1]), +@@ -439,6 +558,8 @@ void __init r8a73a4_clock_init(void) + int k, ret = 0; + u32 ckscr; + ++ atomic_set(&frqcr_lock, -1); ++ + reg = ioremap_nocache(CKSCR, PAGE_SIZE); + BUG_ON(!reg); + ckscr = ioread32(reg); +diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c +index a8c4e41b..9c52096a 100644 +--- a/arch/arm/mach-shmobile/setup-r8a73a4.c ++++ b/arch/arm/mach-shmobile/setup-r8a73a4.c +@@ -184,6 +184,7 @@ void __init r8a73a4_add_standard_devices(void) + #ifdef CONFIG_USE_OF + void __init r8a73a4_add_standard_devices_dt(void) + { ++ platform_device_register_simple("cpufreq-cpu0", -1, NULL, 0); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + } + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0351-ARM-shmobile-r8a73a4-safeguard-against-wrong-clk_set.patch b/patches.renesas/0351-ARM-shmobile-r8a73a4-safeguard-against-wrong-clk_set.patch new file mode 100644 index 00000000000..46caff28cc1 --- /dev/null +++ b/patches.renesas/0351-ARM-shmobile-r8a73a4-safeguard-against-wrong-clk_set.patch @@ -0,0 +1,56 @@ +From 7f23ada85cac9bd9892c5571a62dfb2cebe1dc53 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Fri, 21 Jun 2013 09:10:35 +0200 +Subject: ARM: shmobile: r8a73a4: safeguard against wrong clk_set_rate() uses + +clk_set_rate() should only be called with exact rates, returned by +clk_round_rate(). However, it is still good to verify, that the value, +passed to clock's .set_rate() method is at least valid. This patch adds +such a check for the Z-clock on r8a73a4. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d1c3c959f2206dad0582876af2510aded4f9eac5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a73a4.c | 14 +++++++++++++- + 1 file changed, 13 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c +index 824789c2..22f10ff4 100644 +--- a/arch/arm/mach-shmobile/clock-r8a73a4.c ++++ b/arch/arm/mach-shmobile/clock-r8a73a4.c +@@ -225,16 +225,28 @@ static int zclk_set_rate(struct clk *clk, unsigned long rate) + goto done; + } + +- frqcrc = clk->mapped_reg + (FRQCRC - (u32)clk->enable_reg); ++ /* ++ * Users are supposed to first call clk_set_rate() only with ++ * clk_round_rate() results. So, we don't fix wrong rates here, but ++ * guard against them anyway ++ */ + + p_rate = clk_get_rate(clk->parent); + if (rate == p_rate) { + val = 0; + } else { + step = DIV_ROUND_CLOSEST(p_rate, 32); ++ ++ if (rate > p_rate || rate < step) { ++ ret = -EINVAL; ++ goto done; ++ } ++ + val = 32 - rate / step; + } + ++ frqcrc = clk->mapped_reg + (FRQCRC - (u32)clk->enable_reg); ++ + iowrite32((ioread32(frqcrc) & ~(clk->div_mask << clk->enable_bit)) | + (val << clk->enable_bit), frqcrc); + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0352-ARM-shmobile-r8a73a4-add-Z2-clock-support.patch b/patches.renesas/0352-ARM-shmobile-r8a73a4-add-Z2-clock-support.patch new file mode 100644 index 00000000000..0a427ef04d7 --- /dev/null +++ b/patches.renesas/0352-ARM-shmobile-r8a73a4-add-Z2-clock-support.patch @@ -0,0 +1,56 @@ +From 1180be9d70666cf7ebeae0a7a16342e4eecd2bb1 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Fri, 21 Jun 2013 09:10:38 +0200 +Subject: ARM: shmobile: r8a73a4: add Z2 clock support + +The Z2 clock on r8a73a4 is used to clock the 4 Cortex A7 cores on the SoC. +Add a definition for this clock to later use it from the arm_big_little +CPUFreq driver. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit a040f22d2c2e82347f978b52e7402a7387e5dee5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a73a4.c | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c +index 22f10ff4..27ff58c8 100644 +--- a/arch/arm/mach-shmobile/clock-r8a73a4.c ++++ b/arch/arm/mach-shmobile/clock-r8a73a4.c +@@ -323,6 +323,21 @@ static struct clk z_clk = { + .ops = &zclk_ops, + }; + ++/* ++ * It seems only 1/2 divider is usable in manual mode. 1/2 / 2/3 ++ * switching is only available in auto-DVFS mode ++ */ ++SH_FIXED_RATIO_CLK(pll0_div2_clk, pll0_clk, div2); ++ ++static struct clk z2_clk = { ++ .parent = &pll0_div2_clk, ++ .div_mask = 0x1f, ++ .enable_bit = 0, ++ /* We'll need to access FRQCRB and FRQCRC */ ++ .enable_reg = (void __iomem *)FRQCRB, ++ .ops = &zclk_ops, ++}; ++ + static struct clk *main_clks[] = { + &extalr_clk, + &extal1_clk, +@@ -341,6 +356,8 @@ static struct clk *main_clks[] = { + &pll2s_clk, + &pll2h_clk, + &z_clk, ++ &pll0_div2_clk, ++ &z2_clk, + }; + + /* DIV4 */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0353-ARM-shmobile-r8a73a4-add-clocks-for-I2C-controllers.patch b/patches.renesas/0353-ARM-shmobile-r8a73a4-add-clocks-for-I2C-controllers.patch new file mode 100644 index 00000000000..f538e988c0b --- /dev/null +++ b/patches.renesas/0353-ARM-shmobile-r8a73a4-add-clocks-for-I2C-controllers.patch @@ -0,0 +1,90 @@ +From e76146f8a0c60e6a3d33a992cdab1ab362d71d30 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Thu, 27 Jun 2013 11:47:56 +0200 +Subject: ARM: shmobile: r8a73a4: add clocks for I2C controllers + +r8a73a4 SoCs have numerous I2C controllers, of which 9 are compatible with +the i2c-sh_mobile.c driver. This patch adds clock definitions for them. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 1e453df90047f052cdce2041a572830c8eb32084) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a73a4.c | 25 +++++++++++++++++++++++-- + 1 file changed, 23 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c +index 27ff58c8..f831b3bb 100644 +--- a/arch/arm/mach-shmobile/clock-r8a73a4.c ++++ b/arch/arm/mach-shmobile/clock-r8a73a4.c +@@ -30,6 +30,7 @@ + + #define SMSTPCR2 0xe6150138 + #define SMSTPCR3 0xe615013c ++#define SMSTPCR4 0xe6150140 + #define SMSTPCR5 0xe6150144 + + #define FRQCRA 0xE6150000 +@@ -504,8 +505,10 @@ static struct clk div6_clks[DIV6_NR] = { + /* MSTP */ + enum { + MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, +- MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, +- MSTP522, ++ MSTP323, MSTP318, MSTP317, MSTP316, ++ MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, MSTP300, ++ MSTP411, MSTP410, MSTP409, ++ MSTP522, MSTP515, + MSTP_NR + }; + +@@ -516,12 +519,21 @@ static struct clk mstp_clks[MSTP_NR] = { + [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 7, 0), /* SCIFB1 */ + [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 16, 0), /* SCIFB2 */ + [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 17, 0), /* SCIFB3 */ ++ [MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 0, 0), /* IIC2 */ + [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */ + [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */ + [MSTP313] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI1],SMSTPCR3, 13, 0), /* SDHI1 */ + [MSTP314] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI0],SMSTPCR3, 14, 0), /* SDHI0 */ + [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0],SMSTPCR3, 15, 0), /* MMCIF0 */ ++ [MSTP316] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 16, 0), /* IIC6 */ ++ [MSTP317] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 17, 0), /* IIC7 */ ++ [MSTP318] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 18, 0), /* IIC0 */ ++ [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */ ++ [MSTP409] = SH_CLK_MSTP32(&main_div2_clk, SMSTPCR4, 9, 0), /* IIC5 */ ++ [MSTP410] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */ ++ [MSTP411] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */ + [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */ ++ [MSTP515] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR5, 15, 0), /* IIC8 */ + }; + + static struct clk_lookup lookups[] = { +@@ -566,6 +578,7 @@ static struct clk_lookup lookups[] = { + CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), + CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]), + CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), ++ CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]), + CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), + CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]), + CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]), +@@ -576,6 +589,14 @@ static struct clk_lookup lookups[] = { + CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), + CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), + CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), ++ CLKDEV_DEV_ID("e6550000.i2c", &mstp_clks[MSTP316]), ++ CLKDEV_DEV_ID("e6560000.i2c", &mstp_clks[MSTP317]), ++ CLKDEV_DEV_ID("e6500000.i2c", &mstp_clks[MSTP318]), ++ CLKDEV_DEV_ID("e6510000.i2c", &mstp_clks[MSTP323]), ++ CLKDEV_DEV_ID("e60b0000.i2c", &mstp_clks[MSTP409]), ++ CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP410]), ++ CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP411]), ++ CLKDEV_DEV_ID("e6570000.i2c", &mstp_clks[MSTP515]), + + /* for DT */ + CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0354-ARM-shmobile-Sort-r8a7790-MSTP-entries.patch b/patches.renesas/0354-ARM-shmobile-Sort-r8a7790-MSTP-entries.patch new file mode 100644 index 00000000000..0f976bc700d --- /dev/null +++ b/patches.renesas/0354-ARM-shmobile-Sort-r8a7790-MSTP-entries.patch @@ -0,0 +1,44 @@ +From fe46e52c8414a492b22c2f29c0eee12f9813c490 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Fri, 28 Jun 2013 19:13:27 +0900 +Subject: ARM: shmobile: Sort r8a7790 MSTP entries + +The r8a7790 MSTP bits should be kept sorted in the same way +as on other mach-shmobile SoCs. Move the HSCIF and thermal +bits to clean up the current state. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 29eb2ba89c63c6f57dc3a8b1a89241c7a877a3c8) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a7790.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c +index 28eccd11..10d99b3f 100644 +--- a/arch/arm/mach-shmobile/clock-r8a7790.c ++++ b/arch/arm/mach-shmobile/clock-r8a7790.c +@@ -192,6 +192,9 @@ enum { + static struct clk mstp_clks[MSTP_NR] = { + [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ + [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ ++ [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */ ++ [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */ ++ [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */ + [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */ + [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */ + [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_SD1], SMSTPCR3, 13, 0), /* SDHI1 */ +@@ -205,9 +208,6 @@ static struct clk mstp_clks[MSTP_NR] = { + [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */ + [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */ + [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */ +- [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */ +- [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */ +- [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */ + }; + + static struct clk_lookup lookups[] = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0355-ARM-shmobile-Add-r8a7790-CMT00-clock-event.patch b/patches.renesas/0355-ARM-shmobile-Add-r8a7790-CMT00-clock-event.patch new file mode 100644 index 00000000000..c434f32939b --- /dev/null +++ b/patches.renesas/0355-ARM-shmobile-Add-r8a7790-CMT00-clock-event.patch @@ -0,0 +1,108 @@ +From 50efb77ed7baaa141ebd65c3a1fe41fe1e86aea8 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Fri, 28 Jun 2013 20:27:04 +0900 +Subject: ARM: shmobile: Add r8a7790 CMT00 clock event + +Add clock event support for CMT0 timer channel 0 +to the r8a7790 SoC code. On most ARM mach-shmobile +the CMT is hooked up to a 32KHz clock but on r8a7790 +a 31.7KHz clock is instead used. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 99ade1a0f02e086248874d9908def3e8e4539418) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a7790.c | 4 ++++ + arch/arm/mach-shmobile/setup-r8a7790.c | 23 ++++++++++++++++++++++- + 2 files changed, 26 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c +index 10d99b3f..62d8162c 100644 +--- a/arch/arm/mach-shmobile/clock-r8a7790.c ++++ b/arch/arm/mach-shmobile/clock-r8a7790.c +@@ -47,6 +47,7 @@ + #define CPG_BASE 0xe6150000 + #define CPG_LEN 0x1000 + ++#define SMSTPCR1 0xe6150134 + #define SMSTPCR2 0xe6150138 + #define SMSTPCR3 0xe615013c + #define SMSTPCR5 0xe6150144 +@@ -186,6 +187,7 @@ enum { + MSTP522, + MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304, + MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, ++ MSTP124, + MSTP_NR + }; + +@@ -208,6 +210,7 @@ static struct clk mstp_clks[MSTP_NR] = { + [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */ + [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */ + [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */ ++ [MSTP124] = SH_CLK_MSTP32(&rclk_clk, SMSTPCR1, 24, 0), /* CMT0 */ + }; + + static struct clk_lookup lookups[] = { +@@ -270,6 +273,7 @@ static struct clk_lookup lookups[] = { + CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]), + CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]), + CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), ++ CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]), + }; + + #define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ +diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c +index bc40a44d..ece60c63 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7790.c ++++ b/arch/arm/mach-shmobile/setup-r8a7790.c +@@ -21,9 +21,10 @@ + #include <linux/irq.h> + #include <linux/kernel.h> + #include <linux/of_platform.h> +-#include <linux/serial_sci.h> + #include <linux/platform_data/gpio-rcar.h> + #include <linux/platform_data/irq-renesas-irqc.h> ++#include <linux/serial_sci.h> ++#include <linux/sh_timer.h> + #include <mach/common.h> + #include <mach/irqs.h> + #include <mach/r8a7790.h> +@@ -159,6 +160,25 @@ static struct resource thermal_resources[] __initdata = { + thermal_resources, \ + ARRAY_SIZE(thermal_resources)) + ++static struct sh_timer_config cmt00_platform_data = { ++ .name = "CMT00", ++ .timer_bit = 0, ++ .clockevent_rating = 80, ++}; ++ ++static struct resource cmt00_resources[] = { ++ DEFINE_RES_MEM(0xffca0510, 0x0c), ++ DEFINE_RES_MEM(0xffca0500, 0x04), ++ DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */ ++}; ++ ++#define r8a7790_register_cmt(idx) \ ++ platform_device_register_resndata(&platform_bus, "sh_cmt", \ ++ idx, cmt##idx##_resources, \ ++ ARRAY_SIZE(cmt##idx##_resources), \ ++ &cmt##idx##_platform_data, \ ++ sizeof(struct sh_timer_config)) ++ + void __init r8a7790_add_standard_devices(void) + { + r8a7790_register_scif(SCIFA0); +@@ -173,6 +193,7 @@ void __init r8a7790_add_standard_devices(void) + r8a7790_register_scif(HSCIF1); + r8a7790_register_irqc(0); + r8a7790_register_thermal(); ++ r8a7790_register_cmt(00); + } + + void __init r8a7790_timer_init(void) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0356-ARM-shmobile-Make-r8a7790-Arch-timer-optional.patch b/patches.renesas/0356-ARM-shmobile-Make-r8a7790-Arch-timer-optional.patch new file mode 100644 index 00000000000..6754189f74c --- /dev/null +++ b/patches.renesas/0356-ARM-shmobile-Make-r8a7790-Arch-timer-optional.patch @@ -0,0 +1,84 @@ +From b8ee7a5e2aa957955a7ef1d0c6587c242d5852d8 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Fri, 28 Jun 2013 20:27:13 +0900 +Subject: ARM: shmobile: Make r8a7790 Arch timer optional + +Update the r8a7790 code to allow using other +timers than Arch timer for clock events. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 8333d8c995169e489a81241bd632a4b9370ed7c3) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/Kconfig | 1 - + arch/arm/mach-shmobile/board-lager.c | 1 + + arch/arm/mach-shmobile/include/mach/r8a7790.h | 1 + + arch/arm/mach-shmobile/setup-r8a7790.c | 8 ++++++++ + 4 files changed, 10 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index 734b3eec..406077c9 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -61,7 +61,6 @@ config ARCH_R8A7790 + select ARCH_WANT_OPTIONAL_GPIOLIB + select ARM_GIC + select CPU_V7 +- select HAVE_ARM_ARCH_TIMER + select SH_CLK_CPG + select RENESAS_IRQC + +diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c +index 78d92d34..f89f1665 100644 +--- a/arch/arm/mach-shmobile/board-lager.c ++++ b/arch/arm/mach-shmobile/board-lager.c +@@ -102,6 +102,7 @@ static const char *lager_boards_compat_dt[] __initdata = { + }; + + DT_MACHINE_START(LAGER_DT, "lager") ++ .init_early = r8a7790_init_delay, + .init_time = r8a7790_timer_init, + .init_machine = lager_add_standard_devices, + .dt_compat = lager_boards_compat_dt, +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h +index 2e919e61..7851cc1b 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7790.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h +@@ -4,6 +4,7 @@ + void r8a7790_add_standard_devices(void); + void r8a7790_clock_init(void); + void r8a7790_pinmux_init(void); ++void r8a7790_init_delay(void); + void r8a7790_timer_init(void); + + #endif /* __ASM_R8A7790_H__ */ +diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c +index ece60c63..f01542e1 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7790.c ++++ b/arch/arm/mach-shmobile/setup-r8a7790.c +@@ -208,6 +208,13 @@ void __init r8a7790_timer_init(void) + shmobile_timer_init(); + } + ++void __init r8a7790_init_delay(void) ++{ ++#ifndef CONFIG_ARM_ARCH_TIMER ++ shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */ ++#endif ++} ++ + #ifdef CONFIG_USE_OF + + static const char *r8a7790_boards_compat_dt[] __initdata = { +@@ -216,6 +223,7 @@ static const char *r8a7790_boards_compat_dt[] __initdata = { + }; + + DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)") ++ .init_early = r8a7790_init_delay, + .init_time = r8a7790_timer_init, + .dt_compat = r8a7790_boards_compat_dt, + MACHINE_END +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0357-ARM-shmobile-Add-r8a73a4-CMT10-clock-event.patch b/patches.renesas/0357-ARM-shmobile-Add-r8a73a4-CMT10-clock-event.patch new file mode 100644 index 00000000000..3aaafed1f7d --- /dev/null +++ b/patches.renesas/0357-ARM-shmobile-Add-r8a73a4-CMT10-clock-event.patch @@ -0,0 +1,96 @@ +From d4be3c3523518a0a56d7d7f39dd0c13e6b7828ba Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Fri, 28 Jun 2013 20:27:23 +0900 +Subject: ARM: shmobile: Add r8a73a4 CMT10 clock event + +Add clock event support for CMT1 timer channel 0 +to the r8a73a4 SoC code. The CMT is used together +with a 32KHz clock in this case. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit a7b99f27a260a25f856ea37090cea997d50fe112) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a73a4.c | 4 +++- + arch/arm/mach-shmobile/setup-r8a73a4.c | 21 +++++++++++++++++++++ + 2 files changed, 24 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c +index f831b3bb..8ea5ef6c 100644 +--- a/arch/arm/mach-shmobile/clock-r8a73a4.c ++++ b/arch/arm/mach-shmobile/clock-r8a73a4.c +@@ -505,7 +505,7 @@ static struct clk div6_clks[DIV6_NR] = { + /* MSTP */ + enum { + MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, +- MSTP323, MSTP318, MSTP317, MSTP316, ++ MSTP329, MSTP323, MSTP318, MSTP317, MSTP316, + MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, MSTP300, + MSTP411, MSTP410, MSTP409, + MSTP522, MSTP515, +@@ -529,6 +529,7 @@ static struct clk mstp_clks[MSTP_NR] = { + [MSTP317] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 17, 0), /* IIC7 */ + [MSTP318] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 18, 0), /* IIC0 */ + [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */ ++ [MSTP329] = SH_CLK_MSTP32(&extalr_clk, SMSTPCR3, 29, 0), /* CMT10 */ + [MSTP409] = SH_CLK_MSTP32(&main_div2_clk, SMSTPCR4, 9, 0), /* IIC5 */ + [MSTP410] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */ + [MSTP411] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */ +@@ -593,6 +594,7 @@ static struct clk_lookup lookups[] = { + CLKDEV_DEV_ID("e6560000.i2c", &mstp_clks[MSTP317]), + CLKDEV_DEV_ID("e6500000.i2c", &mstp_clks[MSTP318]), + CLKDEV_DEV_ID("e6510000.i2c", &mstp_clks[MSTP323]), ++ CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), + CLKDEV_DEV_ID("e60b0000.i2c", &mstp_clks[MSTP409]), + CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP410]), + CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP411]), +diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c +index 9c52096a..b8dddf4a 100644 +--- a/arch/arm/mach-shmobile/setup-r8a73a4.c ++++ b/arch/arm/mach-shmobile/setup-r8a73a4.c +@@ -22,6 +22,7 @@ + #include <linux/of_platform.h> + #include <linux/platform_data/irq-renesas-irqc.h> + #include <linux/serial_sci.h> ++#include <linux/sh_timer.h> + #include <mach/common.h> + #include <mach/irqs.h> + #include <mach/r8a73a4.h> +@@ -168,6 +169,25 @@ static const struct resource thermal0_resources[] = { + thermal0_resources, \ + ARRAY_SIZE(thermal0_resources)) + ++static struct sh_timer_config cmt10_platform_data = { ++ .name = "CMT10", ++ .timer_bit = 0, ++ .clockevent_rating = 80, ++}; ++ ++static struct resource cmt10_resources[] = { ++ DEFINE_RES_MEM(0xe6130010, 0x0c), ++ DEFINE_RES_MEM(0xe6130000, 0x04), ++ DEFINE_RES_IRQ(gic_spi(120)), /* CMT1_0 */ ++}; ++ ++#define r8a7790_register_cmt(idx) \ ++ platform_device_register_resndata(&platform_bus, "sh_cmt", \ ++ idx, cmt##idx##_resources, \ ++ ARRAY_SIZE(cmt##idx##_resources), \ ++ &cmt##idx##_platform_data, \ ++ sizeof(struct sh_timer_config)) ++ + void __init r8a73a4_add_standard_devices(void) + { + r8a73a4_register_scif(SCIFA0); +@@ -179,6 +199,7 @@ void __init r8a73a4_add_standard_devices(void) + r8a73a4_register_irqc(0); + r8a73a4_register_irqc(1); + r8a73a4_register_thermal(); ++ r8a7790_register_cmt(10); + } + + #ifdef CONFIG_USE_OF +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0358-ARM-shmobile-Make-r8a73a4-Arch-timer-optional.patch b/patches.renesas/0358-ARM-shmobile-Make-r8a73a4-Arch-timer-optional.patch new file mode 100644 index 00000000000..dbaa6a13414 --- /dev/null +++ b/patches.renesas/0358-ARM-shmobile-Make-r8a73a4-Arch-timer-optional.patch @@ -0,0 +1,83 @@ +From f27a8753c74c940e0e60fac7f3a0df2bab61a094 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Fri, 28 Jun 2013 20:27:32 +0900 +Subject: ARM: shmobile: Make r8a73a4 Arch timer optional + +Update the r8a73a4 code to allow using other +timers than Arch timer for clock event + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit b9a30ef1d354c0bc0cc6d973bbe7ede9f00716ee) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/Kconfig | 1 - + arch/arm/mach-shmobile/board-ape6evm.c | 1 + + arch/arm/mach-shmobile/include/mach/r8a73a4.h | 1 + + arch/arm/mach-shmobile/setup-r8a73a4.c | 8 ++++++++ + 4 files changed, 10 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index 406077c9..dd80f215 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -23,7 +23,6 @@ config ARCH_R8A73A4 + select ARCH_WANT_OPTIONAL_GPIOLIB + select ARM_GIC + select CPU_V7 +- select HAVE_ARM_ARCH_TIMER + select SH_CLK_CPG + select RENESAS_IRQC + select ARCH_HAS_CPUFREQ +diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c +index 1fbc39a1..af6dd39d 100644 +--- a/arch/arm/mach-shmobile/board-ape6evm.c ++++ b/arch/arm/mach-shmobile/board-ape6evm.c +@@ -101,6 +101,7 @@ static const char *ape6evm_boards_compat_dt[] __initdata = { + }; + + DT_MACHINE_START(APE6EVM_DT, "ape6evm") ++ .init_early = r8a73a4_init_delay, + .init_time = shmobile_timer_init, + .init_machine = ape6evm_add_standard_devices, + .dt_compat = ape6evm_boards_compat_dt, +diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h +index f043103e..144a85e2 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h +@@ -4,5 +4,6 @@ + void r8a73a4_add_standard_devices(void); + void r8a73a4_clock_init(void); + void r8a73a4_pinmux_init(void); ++void r8a73a4_init_delay(void); + + #endif /* __ASM_R8A73A4_H__ */ +diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c +index b8dddf4a..d533bd23 100644 +--- a/arch/arm/mach-shmobile/setup-r8a73a4.c ++++ b/arch/arm/mach-shmobile/setup-r8a73a4.c +@@ -202,6 +202,13 @@ void __init r8a73a4_add_standard_devices(void) + r8a7790_register_cmt(10); + } + ++void __init r8a73a4_init_delay(void) ++{ ++#ifndef CONFIG_ARM_ARCH_TIMER ++ shmobile_setup_delay(1500, 2, 4); /* Cortex-A15 @ 1500MHz */ ++#endif ++} ++ + #ifdef CONFIG_USE_OF + void __init r8a73a4_add_standard_devices_dt(void) + { +@@ -215,6 +222,7 @@ static const char *r8a73a4_boards_compat_dt[] __initdata = { + }; + + DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)") ++ .init_early = r8a73a4_init_delay, + .init_machine = r8a73a4_add_standard_devices_dt, + .init_time = shmobile_timer_init, + .dt_compat = r8a73a4_boards_compat_dt, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0359-ARM-shmobile-Disconnect-EMEV2-SMP-code-from-clocks.patch b/patches.renesas/0359-ARM-shmobile-Disconnect-EMEV2-SMP-code-from-clocks.patch new file mode 100644 index 00000000000..db230353d4b --- /dev/null +++ b/patches.renesas/0359-ARM-shmobile-Disconnect-EMEV2-SMP-code-from-clocks.patch @@ -0,0 +1,113 @@ +From 6905b38094d7507b74837742f21a2ff03f1803c3 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Tue, 2 Jul 2013 18:28:30 +0900 +Subject: ARM: shmobile: Disconnect EMEV2 SMP code from clocks + +Update the EMEV2 SMP code to access the SMU directly +instead of relying on help from the legacy clock code. + +This change moves us one step closer to common clocks. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Acked-by: Arnd Bergmann <arnd@arndb.de> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 8d7217e5d74966e1016dad1f48fdaebb85deb685) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-emev2.c | 18 ------------------ + arch/arm/mach-shmobile/include/mach/emev2.h | 1 - + arch/arm/mach-shmobile/smp-emev2.c | 11 +++++++++-- + 3 files changed, 9 insertions(+), 21 deletions(-) + +diff --git a/arch/arm/mach-shmobile/clock-emev2.c b/arch/arm/mach-shmobile/clock-emev2.c +index 56dd0cfc..5ac13ba7 100644 +--- a/arch/arm/mach-shmobile/clock-emev2.c ++++ b/arch/arm/mach-shmobile/clock-emev2.c +@@ -40,7 +40,6 @@ + #define USIB2SCLKDIV 0x65c + #define USIB3SCLKDIV 0x660 + #define STI_CLKSEL 0x688 +-#define SMU_GENERAL_REG0 0x7c0 + + /* not pretty, but hey */ + static void __iomem *smu_base; +@@ -51,11 +50,6 @@ static void emev2_smu_write(unsigned long value, int offs) + iowrite32(value, smu_base + offs); + } + +-void emev2_set_boot_vector(unsigned long value) +-{ +- emev2_smu_write(value, SMU_GENERAL_REG0); +-} +- + static struct clk_mapping smu_mapping = { + .phys = EMEV2_SMU_BASE, + .len = PAGE_SIZE, +@@ -205,18 +199,6 @@ static struct clk_lookup lookups[] = { + void __init emev2_clock_init(void) + { + int k, ret = 0; +- static int is_setup; +- +- /* yuck, this is ugly as hell, but the non-smp case of clocks +- * code is now designed to rely on ioremap() instead of static +- * entity maps. in the case of smp we need access to the SMU +- * register earlier than ioremap() is actually working without +- * any static maps. to enable SMP in ugly but with dynamic +- * mappings we have to call emev2_clock_init() from different +- * places depending on UP and SMP... +- */ +- if (is_setup++) +- return; + + smu_base = ioremap(EMEV2_SMU_BASE, PAGE_SIZE); + BUG_ON(!smu_base); +diff --git a/arch/arm/mach-shmobile/include/mach/emev2.h b/arch/arm/mach-shmobile/include/mach/emev2.h +index b0ab4b72..c2eb7568 100644 +--- a/arch/arm/mach-shmobile/include/mach/emev2.h ++++ b/arch/arm/mach-shmobile/include/mach/emev2.h +@@ -5,7 +5,6 @@ extern void emev2_map_io(void); + extern void emev2_init_delay(void); + extern void emev2_add_standard_devices(void); + extern void emev2_clock_init(void); +-extern void emev2_set_boot_vector(unsigned long value); + + #define EMEV2_GPIO_BASE 200 + #define EMEV2_GPIO_IRQ(n) (EMEV2_GPIO_BASE + (n)) +diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c +index 97871655..1bf8bc7e 100644 +--- a/arch/arm/mach-shmobile/smp-emev2.c ++++ b/arch/arm/mach-shmobile/smp-emev2.c +@@ -29,6 +29,8 @@ + #include <asm/smp_scu.h> + + #define EMEV2_SCU_BASE 0x1e000000 ++#define EMEV2_SMU_BASE 0xe0110000 ++#define SMU_GENERAL_REG0 0x7c0 + + static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle) + { +@@ -38,13 +40,18 @@ static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct * + + static void __init emev2_smp_prepare_cpus(unsigned int max_cpus) + { ++ void __iomem *smu; ++ + /* setup EMEV2 specific SCU base, enable */ + shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE); + scu_enable(shmobile_scu_base); + + /* Tell ROM loader about our vector (in headsmp-scu.S, headsmp.S) */ +- emev2_clock_init(); /* need ioremapped SMU */ +- emev2_set_boot_vector(__pa(shmobile_boot_vector)); ++ smu = ioremap(EMEV2_SMU_BASE, PAGE_SIZE); ++ if (smu) { ++ iowrite32(__pa(shmobile_boot_vector), smu + SMU_GENERAL_REG0); ++ iounmap(smu); ++ } + shmobile_boot_fn = virt_to_phys(shmobile_boot_scu); + shmobile_boot_arg = (unsigned long)shmobile_scu_base; + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0360-ARM-shmobile-r8a7740-add-MMCIF-DMA-definitions.patch b/patches.renesas/0360-ARM-shmobile-r8a7740-add-MMCIF-DMA-definitions.patch new file mode 100644 index 00000000000..c1eac8a0591 --- /dev/null +++ b/patches.renesas/0360-ARM-shmobile-r8a7740-add-MMCIF-DMA-definitions.patch @@ -0,0 +1,54 @@ +From 5c54840b58b58565e6d512901dbf2bbc2fdccfcd Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Wed, 26 Jun 2013 16:40:53 +0200 +Subject: ARM: shmobile: r8a7740: add MMCIF DMA definitions + +Add DMA channel slave IDs and configuration entries for the r8a7740 +MMCIF controller. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 9a1456242c7c644d0032032ba80e8538b8322d3c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/include/mach/r8a7740.h | 2 ++ + arch/arm/mach-shmobile/setup-r8a7740.c | 10 ++++++++++ + 2 files changed, 12 insertions(+) + +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h +index b34d19b5..56f37500 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h +@@ -42,6 +42,8 @@ enum { + SHDMA_SLAVE_FSIB_TX, + SHDMA_SLAVE_USBHS_TX, + SHDMA_SLAVE_USBHS_RX, ++ SHDMA_SLAVE_MMCIF_TX, ++ SHDMA_SLAVE_MMCIF_RX, + }; + + extern void r8a7740_meram_workaround(void); +diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c +index ac29c2ee..84c5bb6d 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7740.c ++++ b/arch/arm/mach-shmobile/setup-r8a7740.c +@@ -588,6 +588,16 @@ static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = { + .addr = 0xfe1f0064, + .chcr = CHCR_TX(XMIT_SZ_32BIT), + .mid_rid = 0xb5, ++ }, { ++ .slave_id = SHDMA_SLAVE_MMCIF_TX, ++ .addr = 0xe6bd0034, ++ .chcr = CHCR_TX(XMIT_SZ_32BIT), ++ .mid_rid = 0xd1, ++ }, { ++ .slave_id = SHDMA_SLAVE_MMCIF_RX, ++ .addr = 0xe6bd0034, ++ .chcr = CHCR_RX(XMIT_SZ_32BIT), ++ .mid_rid = 0xd2, + }, + }; + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0361-ARM-shmobile-Introduce-r8a7790_read_mode_pins.patch b/patches.renesas/0361-ARM-shmobile-Introduce-r8a7790_read_mode_pins.patch new file mode 100644 index 00000000000..da79106ace9 --- /dev/null +++ b/patches.renesas/0361-ARM-shmobile-Introduce-r8a7790_read_mode_pins.patch @@ -0,0 +1,103 @@ +From 48400473eeacd7901ad1769c70c84d095ab37941 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Fri, 12 Jul 2013 01:22:19 +0900 +Subject: ARM: shmobile: Introduce r8a7790_read_mode_pins() + +Break out the r8a7790 boot mode code into a separate +function so it can be shared by multiple users. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 512e53bc7f0088e3adfd89b3fea3447495fc8423) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a7790.c | 11 ++--------- + arch/arm/mach-shmobile/include/mach/r8a7790.h | 3 +++ + arch/arm/mach-shmobile/setup-r8a7790.c | 14 ++++++++++++++ + 3 files changed, 19 insertions(+), 9 deletions(-) + +diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c +index 62d8162c..50d96f9c 100644 +--- a/arch/arm/mach-shmobile/clock-r8a7790.c ++++ b/arch/arm/mach-shmobile/clock-r8a7790.c +@@ -24,6 +24,7 @@ + #include <linux/clkdev.h> + #include <mach/clock.h> + #include <mach/common.h> ++#include <mach/r8a7790.h> + + /* + * MD EXTAL PLL0 PLL1 PLL3 +@@ -42,8 +43,6 @@ + * see "p1 / 2" on R8A7790_CLOCK_ROOT() below + */ + +-#define MD(nr) (1 << nr) +- + #define CPG_BASE 0xe6150000 + #define CPG_LEN 0x1000 + +@@ -53,7 +52,6 @@ + #define SMSTPCR5 0xe6150144 + #define SMSTPCR7 0xe615014c + +-#define MODEMR 0xE6160060 + #define SDCKCR 0xE6150074 + #define SD2CKCR 0xE6150078 + #define SD3CKCR 0xE615007C +@@ -288,14 +286,9 @@ static struct clk_lookup lookups[] = { + + void __init r8a7790_clock_init(void) + { +- void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE); +- u32 mode; ++ u32 mode = r8a7790_read_mode_pins(); + int k, ret = 0; + +- BUG_ON(!modemr); +- mode = ioread32(modemr); +- iounmap(modemr); +- + switch (mode & (MD(14) | MD(13))) { + case 0: + R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88); +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h +index 7851cc1b..7aaef409 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7790.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h +@@ -7,4 +7,7 @@ void r8a7790_pinmux_init(void); + void r8a7790_init_delay(void); + void r8a7790_timer_init(void); + ++#define MD(nr) BIT(nr) ++u32 r8a7790_read_mode_pins(void); ++ + #endif /* __ASM_R8A7790_H__ */ +diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c +index f01542e1..6acddc13 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7790.c ++++ b/arch/arm/mach-shmobile/setup-r8a7790.c +@@ -196,6 +196,20 @@ void __init r8a7790_add_standard_devices(void) + r8a7790_register_cmt(00); + } + ++#define MODEMR 0xe6160060 ++ ++u32 __init r8a7790_read_mode_pins(void) ++{ ++ void __iomem *modemr = ioremap_nocache(MODEMR, 4); ++ u32 mode; ++ ++ BUG_ON(!modemr); ++ mode = ioread32(modemr); ++ iounmap(modemr); ++ ++ return mode; ++} ++ + void __init r8a7790_timer_init(void) + { + void __iomem *cntcr; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0362-ARM-shmobile-Setup-r8a7790-arch-timer-based-on-MD-pi.patch b/patches.renesas/0362-ARM-shmobile-Setup-r8a7790-arch-timer-based-on-MD-pi.patch new file mode 100644 index 00000000000..a7c5102945c --- /dev/null +++ b/patches.renesas/0362-ARM-shmobile-Setup-r8a7790-arch-timer-based-on-MD-pi.patch @@ -0,0 +1,97 @@ +From 9ea08ecbad130d0c15b42d494cbf80760eb18efe Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Fri, 12 Jul 2013 01:22:29 +0900 +Subject: ARM: shmobile: Setup r8a7790 arch timer based on MD pins + +Update the r8a7790 arch timer setup code to configure the +frequency dynamically at boot time. This means that the arch +timer driver will be able to detect a timer frequency that +has been calculated based on the MD pins instead of a fixed +and potentially incorrect 13 MHz. + +With this patch applied the Linux kernel will correctly +support the r8a7790 Lager board that uses a 20 Mhz EXTAL. +The arch timer will operate on 10 MHz and the Linux arch +timer driver will be correctly configured to use 10 MHz. + +Without this patch the 20 MHz EXTAL will be used to drive +the arch timer at 10 MHz, but the Linux arch timer driver +will believe it is counting at 13 Mhz. + +Reported-by: Ulrich Hecht <ulrich.hecht@gmail.com> +Signed-off-by: Magnus Damm <damm@opensource.se> +Tested-by: Ulrich Hecht <ulrich.hecht@gmail.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 81b9d5351fa96caad4accc6711bc1b9342927d4a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a7790.c | 51 ++++++++++++++++++++++++++++++---- + 1 file changed, 45 insertions(+), 6 deletions(-) + +diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c +index 6acddc13..4c96dad2 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7790.c ++++ b/arch/arm/mach-shmobile/setup-r8a7790.c +@@ -210,14 +210,53 @@ u32 __init r8a7790_read_mode_pins(void) + return mode; + } + ++#define CNTCR 0 ++#define CNTFID0 0x20 ++ + void __init r8a7790_timer_init(void) + { +- void __iomem *cntcr; +- +- /* make sure arch timer is started by setting bit 0 of CNTCT */ +- cntcr = ioremap(0xe6080000, PAGE_SIZE); +- iowrite32(1, cntcr); +- iounmap(cntcr); ++#ifdef CONFIG_ARM_ARCH_TIMER ++ u32 mode = r8a7790_read_mode_pins(); ++ void __iomem *base; ++ int extal_mhz = 0; ++ u32 freq; ++ ++ /* At Linux boot time the r8a7790 arch timer comes up ++ * with the counter disabled. Moreover, it may also report ++ * a potentially incorrect fixed 13 MHz frequency. To be ++ * correct these registers need to be updated to use the ++ * frequency EXTAL / 2 which can be determined by the MD pins. ++ */ ++ ++ switch (mode & (MD(14) | MD(13))) { ++ case 0: ++ extal_mhz = 15; ++ break; ++ case MD(13): ++ extal_mhz = 20; ++ break; ++ case MD(14): ++ extal_mhz = 26; ++ break; ++ case MD(13) | MD(14): ++ extal_mhz = 30; ++ break; ++ } ++ ++ /* The arch timer frequency equals EXTAL / 2 */ ++ freq = extal_mhz * (1000000 / 2); ++ ++ /* Remap "armgcnt address map" space */ ++ base = ioremap(0xe6080000, PAGE_SIZE); ++ ++ /* Update registers with correct frequency */ ++ iowrite32(freq, base + CNTFID0); ++ asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); ++ ++ /* make sure arch timer is started by setting bit 0 of CNTCR */ ++ iowrite32(1, base + CNTCR); ++ iounmap(base); ++#endif /* CONFIG_ARM_ARCH_TIMER */ + + shmobile_timer_init(); + } +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0363-ARM-shmobile-ape6evm-add-DT-reference.patch b/patches.renesas/0363-ARM-shmobile-ape6evm-add-DT-reference.patch new file mode 100644 index 00000000000..c3fe2764e45 --- /dev/null +++ b/patches.renesas/0363-ARM-shmobile-ape6evm-add-DT-reference.patch @@ -0,0 +1,246 @@ +From 3e0f1839de7e3ee5320e8dc9c8720c51f2a449a2 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Mon, 8 Jul 2013 18:04:57 +0200 +Subject: ARM: shmobile: ape6evm: add DT reference + +This patch adds a sample DT-based APE6EVM "reference" implementation. The +use of platform-specific C-code should be avoided with this configuration +as much as possible. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Acked-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 69f366615e950cb0d5af89da228796af5208ad8f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/Makefile | 1 + + arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts | 33 +++++++++++ + arch/arm/mach-shmobile/Kconfig | 11 ++++ + arch/arm/mach-shmobile/Makefile | 1 + + arch/arm/mach-shmobile/Makefile.boot | 1 + + arch/arm/mach-shmobile/board-ape6evm-reference.c | 71 ++++++++++++++++++++++++ + arch/arm/mach-shmobile/include/mach/r8a73a4.h | 1 + + arch/arm/mach-shmobile/setup-r8a73a4.c | 9 ++- + 8 files changed, 126 insertions(+), 2 deletions(-) + create mode 100644 arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts + create mode 100644 arch/arm/mach-shmobile/board-ape6evm-reference.c + +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index a77ed45c..1f8d1e4c 100644 +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -169,6 +169,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ + sh73a0-kzm9g.dtb \ + sh73a0-kzm9g-reference.dtb \ + r8a73a4-ape6evm.dtb \ ++ r8a73a4-ape6evm-reference.dtb \ + sh7372-mackerel.dtb + dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \ + socfpga_vt.dtb +diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts +new file mode 100644 +index 00000000..3251f059 +--- /dev/null ++++ b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts +@@ -0,0 +1,33 @@ ++/* ++ * Device Tree Source for the APE6EVM board ++ * ++ * Copyright (C) 2013 Renesas Solutions Corp. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++/dts-v1/; ++/include/ "r8a73a4.dtsi" ++ ++/ { ++ model = "APE6EVM"; ++ compatible = "renesas,ape6evm-reference", "renesas,r8a73a4"; ++ ++ chosen { ++ bootargs = "console=ttySC0,115200 ignore_loglevel"; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0 0x40000000 0 0x40000000>; ++ }; ++ ++ lbsc { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0 0 0x80000000>; ++ }; ++}; +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index dd80f215..ad28f91b 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -83,6 +83,17 @@ config MACH_APE6EVM + depends on ARCH_R8A73A4 + select USE_OF + ++config MACH_APE6EVM_REFERENCE ++ bool "APE6EVM board - Reference Device Tree Implementation" ++ depends on ARCH_R8A73A4 ++ select USE_OF ++ ---help--- ++ Use reference implementation of APE6EVM board support ++ which makes a greater use of device tree at the expense ++ of not supporting a number of devices. ++ ++ This is intended to aid developers ++ + config MACH_MACKEREL + bool "mackerel board" + depends on ARCH_SH7372 +diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile +index e8d0a2c9..26a57842 100644 +--- a/arch/arm/mach-shmobile/Makefile ++++ b/arch/arm/mach-shmobile/Makefile +@@ -37,6 +37,7 @@ obj-$(CONFIG_ARCH_SH73A0) += pm-sh73a0.o + # Board objects + obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o + obj-$(CONFIG_MACH_APE6EVM) += board-ape6evm.o ++obj-$(CONFIG_MACH_APE6EVM_REFERENCE) += board-ape6evm-reference.o + obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o + obj-$(CONFIG_MACH_KOTA2) += board-kota2.o + obj-$(CONFIG_MACH_BOCKW) += board-bockw.o +diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot +index 7785c52b..c938b58f 100644 +--- a/arch/arm/mach-shmobile/Makefile.boot ++++ b/arch/arm/mach-shmobile/Makefile.boot +@@ -2,6 +2,7 @@ + loadaddr-y := + loadaddr-$(CONFIG_MACH_AG5EVM) += 0x40008000 + loadaddr-$(CONFIG_MACH_APE6EVM) += 0x40008000 ++loadaddr-$(CONFIG_MACH_APE6EVM_REFERENCE) += 0x40008000 + loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000 + loadaddr-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += 0x40008000 + loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000 +diff --git a/arch/arm/mach-shmobile/board-ape6evm-reference.c b/arch/arm/mach-shmobile/board-ape6evm-reference.c +new file mode 100644 +index 00000000..c8288749 +--- /dev/null ++++ b/arch/arm/mach-shmobile/board-ape6evm-reference.c +@@ -0,0 +1,71 @@ ++/* ++ * APE6EVM board support ++ * ++ * Copyright (C) 2013 Renesas Solutions Corp. ++ * Copyright (C) 2013 Magnus Damm ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ++ */ ++ ++#include <linux/gpio.h> ++#include <linux/kernel.h> ++#include <linux/of_platform.h> ++#include <linux/pinctrl/machine.h> ++#include <linux/sh_clk.h> ++#include <mach/common.h> ++#include <mach/r8a73a4.h> ++#include <asm/mach-types.h> ++#include <asm/mach/arch.h> ++ ++static const struct pinctrl_map ape6evm_pinctrl_map[] = { ++ /* SCIFA0 console */ ++ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a73a4", ++ "scifa0_data", "scifa0"), ++}; ++ ++static void __init ape6evm_add_standard_devices(void) ++{ ++ ++ struct clk *parent; ++ struct clk *mp; ++ ++ r8a73a4_clock_init(); ++ ++ /* MP clock parent = extal2 */ ++ parent = clk_get(NULL, "extal2"); ++ mp = clk_get(NULL, "mp"); ++ BUG_ON(IS_ERR(parent) || IS_ERR(mp)); ++ ++ clk_set_parent(mp, parent); ++ clk_put(parent); ++ clk_put(mp); ++ ++ pinctrl_register_mappings(ape6evm_pinctrl_map, ++ ARRAY_SIZE(ape6evm_pinctrl_map)); ++ r8a73a4_pinmux_init(); ++ r8a73a4_add_dt_devices(); ++ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); ++} ++ ++static const char *ape6evm_boards_compat_dt[] __initdata = { ++ "renesas,ape6evm-reference", ++ NULL, ++}; ++ ++DT_MACHINE_START(APE6EVM_DT, "ape6evm") ++ .init_early = r8a73a4_init_delay, ++ .init_time = shmobile_timer_init, ++ .init_machine = ape6evm_add_standard_devices, ++ .dt_compat = ape6evm_boards_compat_dt, ++MACHINE_END +diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h +index 144a85e2..f3a9b702 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h +@@ -2,6 +2,7 @@ + #define __ASM_R8A73A4_H__ + + void r8a73a4_add_standard_devices(void); ++void r8a73a4_add_dt_devices(void); + void r8a73a4_clock_init(void); + void r8a73a4_pinmux_init(void); + void r8a73a4_init_delay(void); +diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c +index d533bd23..630ea4eb 100644 +--- a/arch/arm/mach-shmobile/setup-r8a73a4.c ++++ b/arch/arm/mach-shmobile/setup-r8a73a4.c +@@ -188,7 +188,7 @@ static struct resource cmt10_resources[] = { + &cmt##idx##_platform_data, \ + sizeof(struct sh_timer_config)) + +-void __init r8a73a4_add_standard_devices(void) ++void __init r8a73a4_add_dt_devices(void) + { + r8a73a4_register_scif(SCIFA0); + r8a73a4_register_scif(SCIFA1); +@@ -196,10 +196,15 @@ void __init r8a73a4_add_standard_devices(void) + r8a73a4_register_scif(SCIFB1); + r8a73a4_register_scif(SCIFB2); + r8a73a4_register_scif(SCIFB3); ++ r8a7790_register_cmt(10); ++} ++ ++void __init r8a73a4_add_standard_devices(void) ++{ ++ r8a73a4_add_dt_devices(); + r8a73a4_register_irqc(0); + r8a73a4_register_irqc(1); + r8a73a4_register_thermal(); +- r8a7790_register_cmt(10); + } + + void __init r8a73a4_init_delay(void) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0364-ARM-shmobile-ape6evm-reference-add-CPUFreq-support.patch b/patches.renesas/0364-ARM-shmobile-ape6evm-reference-add-CPUFreq-support.patch new file mode 100644 index 00000000000..8ed9aec62ef --- /dev/null +++ b/patches.renesas/0364-ARM-shmobile-ape6evm-reference-add-CPUFreq-support.patch @@ -0,0 +1,71 @@ +From ffe4d831f81e1bbb396173ca2146bfb7fefcf562 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Mon, 8 Jul 2013 18:04:58 +0200 +Subject: ARM: shmobile: ape6evm-reference: add CPUFreq support + +Add CPUFreq support to ape6evm-reference, using a max8973 regulator, that +is supplying V_DVFS for the 4 CA15 cores on r8a73a4. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Acked-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit b88cf6f732946874aaf3e0528459e0f0271dfcec) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts | 22 ++++++++++++++++++++++ + arch/arm/mach-shmobile/board-ape6evm-reference.c | 2 ++ + 2 files changed, 24 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts +index 3251f059..6f4506e7 100644 +--- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts ++++ b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts +@@ -31,3 +31,25 @@ + ranges = <0 0 0 0x80000000>; + }; + }; ++ ++&i2c5 { ++ vdd_dvfs: max8973@1b { ++ compatible = "maxim,max8973"; ++ reg = <0x1b>; ++ ++ regulator-min-microvolt = <935000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++}; ++ ++&cpu0 { ++ cpu0-supply = <&vdd_dvfs>; ++ operating-points = < ++ /* kHz uV */ ++ 1950000 1115000 ++ 1462500 995000 ++ >; ++ voltage-tolerance = <1>; /* 1% */ ++}; +diff --git a/arch/arm/mach-shmobile/board-ape6evm-reference.c b/arch/arm/mach-shmobile/board-ape6evm-reference.c +index c8288749..46b41dec 100644 +--- a/arch/arm/mach-shmobile/board-ape6evm-reference.c ++++ b/arch/arm/mach-shmobile/board-ape6evm-reference.c +@@ -22,6 +22,7 @@ + #include <linux/kernel.h> + #include <linux/of_platform.h> + #include <linux/pinctrl/machine.h> ++#include <linux/platform_device.h> + #include <linux/sh_clk.h> + #include <mach/common.h> + #include <mach/r8a73a4.h> +@@ -56,6 +57,7 @@ static void __init ape6evm_add_standard_devices(void) + r8a73a4_pinmux_init(); + r8a73a4_add_dt_devices(); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); ++ platform_device_register_simple("cpufreq-cpu0", -1, NULL, 0); + } + + static const char *ape6evm_boards_compat_dt[] __initdata = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0365-ARM-shmobile-lager-Add-DT-reference.patch b/patches.renesas/0365-ARM-shmobile-lager-Add-DT-reference.patch new file mode 100644 index 00000000000..17dcab471a9 --- /dev/null +++ b/patches.renesas/0365-ARM-shmobile-lager-Add-DT-reference.patch @@ -0,0 +1,223 @@ +From 4e656ba16c58f61c6ef8942827a22d06a576f6c3 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Fri, 28 Jun 2013 13:42:16 +0900 +Subject: ARM: shmobile: lager: Add DT reference + +This is sufficient to allow boot of the Lager board with +a console without boards-lager.c compiled into the kernel. +This is an example of a minimal but still useful initialisation +of the board using DT as much as possible. + +As such it is the same as the boot of Lager that can be achieved +without a board file. The intention of adding this file +is to facilitate further work to allow board specific devices to be +initialised via DT. + +Acked-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 6dace67f9bd43cdfc2de3ff1a573420ecfc33390) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/Makefile | 1 + + arch/arm/boot/dts/r8a7790-lager-reference.dts | 31 +++++++++++++++++ + arch/arm/mach-shmobile/Kconfig | 11 ++++++ + arch/arm/mach-shmobile/Makefile | 1 + + arch/arm/mach-shmobile/Makefile.boot | 1 + + arch/arm/mach-shmobile/board-lager-reference.c | 46 ++++++++++++++++++++++++++ + arch/arm/mach-shmobile/include/mach/r8a7790.h | 1 + + arch/arm/mach-shmobile/setup-r8a7790.c | 9 +++-- + 8 files changed, 99 insertions(+), 2 deletions(-) + create mode 100644 arch/arm/boot/dts/r8a7790-lager-reference.dts + create mode 100644 arch/arm/mach-shmobile/board-lager-reference.c + +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index 1f8d1e4c..7c9fddc7 100644 +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -166,6 +166,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ + r8a7740-armadillo800eva-reference.dtb \ + r8a7779-marzen-reference.dtb \ + r8a7790-lager.dtb \ ++ r8a7790-lager-reference.dtb \ + sh73a0-kzm9g.dtb \ + sh73a0-kzm9g-reference.dtb \ + r8a73a4-ape6evm.dtb \ +diff --git a/arch/arm/boot/dts/r8a7790-lager-reference.dts b/arch/arm/boot/dts/r8a7790-lager-reference.dts +new file mode 100644 +index 00000000..fa5b81bd +--- /dev/null ++++ b/arch/arm/boot/dts/r8a7790-lager-reference.dts +@@ -0,0 +1,31 @@ ++/* ++ * Device Tree Source for the Lager board ++ * ++ * Copyright (C) 2013 Renesas Solutions Corp. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++/dts-v1/; ++/include/ "r8a7790.dtsi" ++ ++/ { ++ model = "Lager"; ++ compatible = "renesas,lager-reference", "renesas,r8a7790"; ++ ++ chosen { ++ bootargs = "console=ttySC6,115200 ignore_loglevel"; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0 0x40000000 0 0x80000000>; ++ }; ++ ++ lbsc { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ }; ++}; +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index ad28f91b..05ea1031 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -161,6 +161,17 @@ config MACH_LAGER + depends on ARCH_R8A7790 + select USE_OF + ++config MACH_LAGER_REFERENCE ++ bool "Lager board - Reference Device Tree Implementation" ++ depends on ARCH_R8A7790 ++ select USE_OF ++ ---help--- ++ Use reference implementation of Lager board support ++ which makes use of device tree at the expense ++ of not supporting a number of devices. ++ ++ This is intended to aid developers ++ + config MACH_KZM9D + bool "KZM9D board" + depends on ARCH_EMEV2 +diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile +index 26a57842..397bb360 100644 +--- a/arch/arm/mach-shmobile/Makefile ++++ b/arch/arm/mach-shmobile/Makefile +@@ -44,6 +44,7 @@ obj-$(CONFIG_MACH_BOCKW) += board-bockw.o + obj-$(CONFIG_MACH_MARZEN) += board-marzen.o + obj-$(CONFIG_MACH_MARZEN_REFERENCE) += board-marzen-reference.o + obj-$(CONFIG_MACH_LAGER) += board-lager.o ++obj-$(CONFIG_MACH_LAGER_REFERENCE) += board-lager-reference.o + obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o + obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += board-armadillo800eva-reference.o + obj-$(CONFIG_MACH_KZM9D) += board-kzm9d.o +diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot +index c938b58f..761d7b14 100644 +--- a/arch/arm/mach-shmobile/Makefile.boot ++++ b/arch/arm/mach-shmobile/Makefile.boot +@@ -12,6 +12,7 @@ loadaddr-$(CONFIG_MACH_KZM9D_REFERENCE) += 0x40008000 + loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000 + loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000 + loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000 ++loadaddr-$(CONFIG_MACH_LAGER_REFERENCE) += 0x40008000 + loadaddr-$(CONFIG_MACH_MACKEREL) += 0x40008000 + loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000 + loadaddr-$(CONFIG_MACH_MARZEN_REFERENCE) += 0x60008000 +diff --git a/arch/arm/mach-shmobile/board-lager-reference.c b/arch/arm/mach-shmobile/board-lager-reference.c +new file mode 100644 +index 00000000..eb6c55e1 +--- /dev/null ++++ b/arch/arm/mach-shmobile/board-lager-reference.c +@@ -0,0 +1,46 @@ ++/* ++ * Lager board support - Reference DT implementation ++ * ++ * Copyright (C) 2013 Renesas Solutions Corp. ++ * Copyright (C) 2013 Simon Horman ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ++ */ ++ ++#include <linux/init.h> ++#include <linux/irqchip.h> ++#include <linux/of_platform.h> ++#include <mach/r8a7790.h> ++#include <asm/mach/arch.h> ++ ++void __init lager_add_standard_devices(void) ++{ ++ /* clocks are setup late during boot in the case of DT */ ++ r8a7790_clock_init(); ++ ++ r8a7790_add_dt_devices(); ++ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); ++} ++ ++static const char *lager_boards_compat_dt[] __initdata = { ++ "renesas,lager-reference", ++ NULL, ++}; ++ ++DT_MACHINE_START(LAGER_DT, "lager") ++ .init_early = r8a7790_init_delay, ++ .init_machine = lager_add_standard_devices, ++ .init_time = r8a7790_timer_init, ++ .dt_compat = lager_boards_compat_dt, ++MACHINE_END +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h +index 7aaef409..788d5595 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7790.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h +@@ -2,6 +2,7 @@ + #define __ASM_R8A7790_H__ + + void r8a7790_add_standard_devices(void); ++void r8a7790_add_dt_devices(void); + void r8a7790_clock_init(void); + void r8a7790_pinmux_init(void); + void r8a7790_init_delay(void); +diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c +index 4c96dad2..86cf507b 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7790.c ++++ b/arch/arm/mach-shmobile/setup-r8a7790.c +@@ -179,7 +179,7 @@ static struct resource cmt00_resources[] = { + &cmt##idx##_platform_data, \ + sizeof(struct sh_timer_config)) + +-void __init r8a7790_add_standard_devices(void) ++void __init r8a7790_add_dt_devices(void) + { + r8a7790_register_scif(SCIFA0); + r8a7790_register_scif(SCIFA1); +@@ -191,9 +191,14 @@ void __init r8a7790_add_standard_devices(void) + r8a7790_register_scif(SCIF1); + r8a7790_register_scif(HSCIF0); + r8a7790_register_scif(HSCIF1); ++ r8a7790_register_cmt(00); ++} ++ ++void __init r8a7790_add_standard_devices(void) ++{ ++ r8a7790_add_dt_devices(); + r8a7790_register_irqc(0); + r8a7790_register_thermal(); +- r8a7790_register_cmt(00); + } + + #define MODEMR 0xe6160060 +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0366-ARM-shmobile-Minor-update-for-the-Lager-DT-reference.patch b/patches.renesas/0366-ARM-shmobile-Minor-update-for-the-Lager-DT-reference.patch new file mode 100644 index 00000000000..7a9cfb20646 --- /dev/null +++ b/patches.renesas/0366-ARM-shmobile-Minor-update-for-the-Lager-DT-reference.patch @@ -0,0 +1,37 @@ +From 1c9ac4183c200e7c70ea26e90379f365387d0d2f Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Mon, 8 Jul 2013 15:16:46 +0900 +Subject: ARM: shmobile: Minor update for the Lager DT reference code + +Update the Lager DT reference code to get rid of the redundant +irqchip header and also make lager_add_standard_devices() static. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d144f3623ab37c8cd8365533217e9059d8eb4636) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-lager-reference.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-lager-reference.c b/arch/arm/mach-shmobile/board-lager-reference.c +index eb6c55e1..9c316a1b 100644 +--- a/arch/arm/mach-shmobile/board-lager-reference.c ++++ b/arch/arm/mach-shmobile/board-lager-reference.c +@@ -19,12 +19,11 @@ + */ + + #include <linux/init.h> +-#include <linux/irqchip.h> + #include <linux/of_platform.h> + #include <mach/r8a7790.h> + #include <asm/mach/arch.h> + +-void __init lager_add_standard_devices(void) ++static void __init lager_add_standard_devices(void) + { + /* clocks are setup late during boot in the case of DT */ + r8a7790_clock_init(); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0367-ARM-shmobile-armadillo800eva-add-DMA-support-to-MMCI.patch b/patches.renesas/0367-ARM-shmobile-armadillo800eva-add-DMA-support-to-MMCI.patch new file mode 100644 index 00000000000..af790f6277d --- /dev/null +++ b/patches.renesas/0367-ARM-shmobile-armadillo800eva-add-DMA-support-to-MMCI.patch @@ -0,0 +1,31 @@ +From 21816af89dcc9ebbf8c84bf02d0d89f1e69cbd43 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Tue, 2 Jul 2013 17:24:58 +0200 +Subject: ARM: shmobile: armadillo800eva: add DMA support to MMCIF + +Add DMA slave IDs to MMCIF Tx and Rx channels. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 872842084c6f01d5f9d1a4c9b7e39a3d68d0630d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-armadillo800eva.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c +index 99cea1ee..701104c9 100644 +--- a/arch/arm/mach-shmobile/board-armadillo800eva.c ++++ b/arch/arm/mach-shmobile/board-armadillo800eva.c +@@ -778,6 +778,8 @@ static struct sh_mmcif_plat_data sh_mmcif_plat = { + .caps = MMC_CAP_4_BIT_DATA | + MMC_CAP_8_BIT_DATA | + MMC_CAP_NONREMOVABLE, ++ .slave_id_tx = SHDMA_SLAVE_MMCIF_TX, ++ .slave_id_rx = SHDMA_SLAVE_MMCIF_RX, + }; + + static struct resource sh_mmcif_resources[] = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0368-ARM-shmobile-lager-add-MMCIF-support.patch b/patches.renesas/0368-ARM-shmobile-lager-add-MMCIF-support.patch new file mode 100644 index 00000000000..175b4d274a1 --- /dev/null +++ b/patches.renesas/0368-ARM-shmobile-lager-add-MMCIF-support.patch @@ -0,0 +1,85 @@ +From f270c5341eadccb0d9ae0cb074ecf02ce5bdbe3e Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Mon, 8 Jul 2013 17:54:43 +0200 +Subject: ARM: shmobile: lager: add MMCIF support + +Add support for the MMCIF1 interface on Lager. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 63d0539e5466e1c5765b9dfdffafd619d4115ba5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-lager.c | 31 +++++++++++++++++++++++++++++++ + 1 file changed, 31 insertions(+) + +diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c +index f89f1665..3a1a6fdc 100644 +--- a/arch/arm/mach-shmobile/board-lager.c ++++ b/arch/arm/mach-shmobile/board-lager.c +@@ -24,10 +24,15 @@ + #include <linux/interrupt.h> + #include <linux/kernel.h> + #include <linux/leds.h> ++#include <linux/mmc/host.h> ++#include <linux/mmc/sh_mmcif.h> + #include <linux/pinctrl/machine.h> + #include <linux/platform_data/gpio-rcar.h> + #include <linux/platform_device.h> ++#include <linux/regulator/fixed.h> ++#include <linux/regulator/machine.h> + #include <mach/common.h> ++#include <mach/irqs.h> + #include <mach/r8a7790.h> + #include <asm/mach-types.h> + #include <asm/mach/arch.h> +@@ -70,6 +75,22 @@ static __initdata struct gpio_keys_platform_data lager_keys_pdata = { + .nbuttons = ARRAY_SIZE(gpio_buttons), + }; + ++/* Fixed 3.3V regulator to be used by MMCIF */ ++static struct regulator_consumer_supply fixed3v3_power_consumers[] = ++{ ++ REGULATOR_SUPPLY("vmmc", "sh_mmcif.1"), ++}; ++ ++/* MMCIF */ ++static struct sh_mmcif_plat_data mmcif1_pdata = { ++ .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, ++}; ++ ++static struct resource mmcif1_resources[] = { ++ DEFINE_RES_MEM_NAMED(0xee220000, 0x80, "MMCIF1"), ++ DEFINE_RES_IRQ(gic_spi(170)), ++}; ++ + static const struct pinctrl_map lager_pinctrl_map[] = { + /* SCIF0 (CN19: DEBUG SERIAL0) */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790", +@@ -77,6 +98,11 @@ static const struct pinctrl_map lager_pinctrl_map[] = { + /* SCIF1 (CN20: DEBUG SERIAL1) */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7790", + "scif1_data", "scif1"), ++ /* MMCIF1 */ ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.1", "pfc-r8a7790", ++ "mmc1_data8", "mmc1"), ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.1", "pfc-r8a7790", ++ "mmc1_ctrl", "mmc1"), + }; + + static void __init lager_add_standard_devices(void) +@@ -94,6 +120,11 @@ static void __init lager_add_standard_devices(void) + platform_device_register_data(&platform_bus, "gpio-keys", -1, + &lager_keys_pdata, + sizeof(lager_keys_pdata)); ++ regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers, ++ ARRAY_SIZE(fixed3v3_power_consumers), 3300000); ++ platform_device_register_resndata(&platform_bus, "sh_mmcif", 1, ++ mmcif1_resources, ARRAY_SIZE(mmcif1_resources), ++ &mmcif1_pdata, sizeof(mmcif1_pdata)); + } + + static const char *lager_boards_compat_dt[] __initdata = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0369-ARM-shmobile-select-the-fixed-regulator-driver-on-Bo.patch b/patches.renesas/0369-ARM-shmobile-select-the-fixed-regulator-driver-on-Bo.patch new file mode 100644 index 00000000000..cd471263b5d --- /dev/null +++ b/patches.renesas/0369-ARM-shmobile-select-the-fixed-regulator-driver-on-Bo.patch @@ -0,0 +1,35 @@ +From 636925d15a3633fc4be2a23748538cdd623bcde3 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 9 Jul 2013 02:07:13 -0700 +Subject: ARM: shmobile: select the fixed regulator driver on BockW + +34767f8dccc326026f97cd63f759dd36bd83502d +(ARM: mach-shmobile: select the fixed regulator driver on several boards) +decided to select fixed regulator driver on Kconfig. +BockW follows same style. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +[horms+renesas@verge.net.au: Change mach-shmobile to shmobile in changelog] +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit c9996e51e45df0630cf5493fa0359a257a191eee) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index 05ea1031..5ae27f21 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -135,6 +135,7 @@ config MACH_BOCKW + depends on ARCH_R8A7778 + select ARCH_REQUIRE_GPIOLIB + select RENESAS_INTC_IRQPIN ++ select REGULATOR_FIXED_VOLTAGE if REGULATOR + select USE_OF + + config MACH_MARZEN +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0370-ARM-shmobile-fix-compile-error-when-CONFIG_THUMB2_KE.patch b/patches.renesas/0370-ARM-shmobile-fix-compile-error-when-CONFIG_THUMB2_KE.patch new file mode 100644 index 00000000000..8068d2d40b0 --- /dev/null +++ b/patches.renesas/0370-ARM-shmobile-fix-compile-error-when-CONFIG_THUMB2_KE.patch @@ -0,0 +1,42 @@ +From 52a6d690e864068808500eb47a2503b4c3bc8b80 Mon Sep 17 00:00:00 2001 +From: Tetsuyuki Kobayashi <koba@kmckk.co.jp> +Date: Wed, 10 Jul 2013 10:56:35 +0900 +Subject: ARM: shmobile: fix compile error when CONFIG_THUMB2_KERNEL=y + +On KZM-A9-GT board (SMP), when CONFIG_THUMB2_KERNEL=y it fails to compile + + AS arch/arm/mach-shmobile/headsmp-scu.o +/proj/koba/kernel/arm-soc/arch/arm/mach-shmobile/headsmp-scu.S: Assembler messages: +/proj/koba/kernel/arm-soc/arch/arm/mach-shmobile/headsmp-scu.S:41: Error: shift must be constant -- `bic r2,r2,r3,lsl r1' +make[2]: *** [arch/arm/mach-shmobile/headsmp-scu.o] Error 1 +make[1]: *** [arch/arm/mach-shmobile] Error 2 +make: *** [sub-make] Error 2 + +Instruction `bic r2,r2,r3,lsl r1' is not supported in thumb mode. This patch split it into 2 instructions. + +Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> +Acked-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit bdea6c657e15a709e666ea707e72327c555e8e04) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/headsmp-scu.S | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/headsmp-scu.S b/arch/arm/mach-shmobile/headsmp-scu.S +index 6f986546..5ce416c0 100644 +--- a/arch/arm/mach-shmobile/headsmp-scu.S ++++ b/arch/arm/mach-shmobile/headsmp-scu.S +@@ -38,7 +38,8 @@ ENTRY(shmobile_boot_scu) + lsl r1, r1, #3 @ we will shift by cpu_id * 8 bits + ldr r2, [r0, #8] @ SCU Power Status Register + mov r3, #3 +- bic r2, r2, r3, lsl r1 @ Clear bits of our CPU (Run Mode) ++ lsl r3, r3, r1 ++ bic r2, r2, r3 @ Clear bits of our CPU (Run Mode) + str r2, [r0, #8] @ write back + + b shmobile_invalidate_start +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0371-ARM-shmobile-Force-ARM-mode-to-compile-reset-vector-.patch b/patches.renesas/0371-ARM-shmobile-Force-ARM-mode-to-compile-reset-vector-.patch new file mode 100644 index 00000000000..8ee91fbdc43 --- /dev/null +++ b/patches.renesas/0371-ARM-shmobile-Force-ARM-mode-to-compile-reset-vector-.patch @@ -0,0 +1,41 @@ +From 6f1dd5532f13e37764869c1c040fb327e2bb74e1 Mon Sep 17 00:00:00 2001 +From: Tetsuyuki Kobayashi <koba@kmckk.co.jp> +Date: Wed, 10 Jul 2013 10:56:36 +0900 +Subject: ARM: shmobile: Force ARM mode to compile reset vector for secondary + CPUs + +Instructions start from boot vector must be ARM mode. +This patch specify ARM mode explicitly and use 'bx' instruction to be +able to change to Thumb mode. + +Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> +Acked-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit c1d7e2e80079148626e6c411e56708d86311d31a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/headsmp.S | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S +index 559d1ce5..afed58e5 100644 +--- a/arch/arm/mach-shmobile/headsmp.S ++++ b/arch/arm/mach-shmobile/headsmp.S +@@ -26,10 +26,13 @@ ENDPROC(shmobile_invalidate_start) + * This will be mapped at address 0 by SBAR register. + * We need _long_ jump to the physical address. + */ ++ .arm + .align 12 + ENTRY(shmobile_boot_vector) + ldr r0, 2f +- ldr pc, 1f ++ ldr r1, 1f ++ bx r1 ++ + ENDPROC(shmobile_boot_vector) + + .globl shmobile_boot_fn +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0372-ARM-shmobile-Insert-align-directives-before-4-bytes-.patch b/patches.renesas/0372-ARM-shmobile-Insert-align-directives-before-4-bytes-.patch new file mode 100644 index 00000000000..2a04b7226b0 --- /dev/null +++ b/patches.renesas/0372-ARM-shmobile-Insert-align-directives-before-4-bytes-.patch @@ -0,0 +1,66 @@ +From 329755966b87202b0df59c1b8a9a04d500a31098 Mon Sep 17 00:00:00 2001 +From: Tetsuyuki Kobayashi <koba@kmckk.co.jp> +Date: Wed, 10 Jul 2013 10:56:37 +0900 +Subject: ARM: shmobile: Insert align directives before 4 bytes data + +In thumb2 mode instructions are not align to 4 byte. This patch insert +align directives before putting 4 byte data. + +Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> +Acked-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 0b933cb305e7a987e0a711ee15457bd70055d682) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/headsmp-scu.S | 1 + + arch/arm/mach-shmobile/headsmp.S | 1 + + arch/arm/mach-shmobile/sleep-sh7372.S | 2 ++ + 3 files changed, 4 insertions(+) + +diff --git a/arch/arm/mach-shmobile/headsmp-scu.S b/arch/arm/mach-shmobile/headsmp-scu.S +index 5ce416c0..0a77488d 100644 +--- a/arch/arm/mach-shmobile/headsmp-scu.S ++++ b/arch/arm/mach-shmobile/headsmp-scu.S +@@ -46,6 +46,7 @@ ENTRY(shmobile_boot_scu) + ENDPROC(shmobile_boot_scu) + + .text ++ .align 2 + .globl shmobile_scu_base + shmobile_scu_base: + .space 4 +diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S +index afed58e5..dfb41dfc 100644 +--- a/arch/arm/mach-shmobile/headsmp.S ++++ b/arch/arm/mach-shmobile/headsmp.S +@@ -35,6 +35,7 @@ ENTRY(shmobile_boot_vector) + + ENDPROC(shmobile_boot_vector) + ++ .align 2 + .globl shmobile_boot_fn + shmobile_boot_fn: + 1: .space 4 +diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S +index 53f4840e..97828628 100644 +--- a/arch/arm/mach-shmobile/sleep-sh7372.S ++++ b/arch/arm/mach-shmobile/sleep-sh7372.S +@@ -41,6 +41,7 @@ + sh7372_resume_core_standby_sysc: + ldr pc, 1f + ++ .align 2 + .globl sh7372_cpu_resume + sh7372_cpu_resume: + 1: .space 4 +@@ -96,6 +97,7 @@ sh7372_do_idle_sysc: + 1: + b 1b + ++ .align 2 + kernel_flush: + .word v7_flush_dcache_all + #endif +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0373-ARM-shmobile-r8a7740-Fix-TPU-clock-name.patch b/patches.renesas/0373-ARM-shmobile-r8a7740-Fix-TPU-clock-name.patch new file mode 100644 index 00000000000..bfafda680ba --- /dev/null +++ b/patches.renesas/0373-ARM-shmobile-r8a7740-Fix-TPU-clock-name.patch @@ -0,0 +1,32 @@ +From 9a15ea1be9a9c13413313c7036742c1736ff80b5 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 16 Jul 2013 12:32:04 +0200 +Subject: ARM: shmobile: r8a7740: Fix TPU clock name + +The TPU device is called renesas-tpu-pwm, not renesas_tpu_pwm. Fix the +clock name accordingly. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 93d8a6fbe69a629a7bb37bb546699a5c49963dc5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a7740.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c +index 7fd32d60..f5b7bbe4 100644 +--- a/arch/arm/mach-shmobile/clock-r8a7740.c ++++ b/arch/arm/mach-shmobile/clock-r8a7740.c +@@ -596,7 +596,7 @@ static struct clk_lookup lookups[] = { + CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), + CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP309]), + CLKDEV_DEV_ID("e9a00000.sh-eth", &mstp_clks[MSTP309]), +- CLKDEV_DEV_ID("renesas_tpu_pwm", &mstp_clks[MSTP304]), ++ CLKDEV_DEV_ID("renesas-tpu-pwm", &mstp_clks[MSTP304]), + + CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), + CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0374-ARM-shmobile-armadillo800eva-Add-backlight-support.patch b/patches.renesas/0374-ARM-shmobile-armadillo800eva-Add-backlight-support.patch new file mode 100644 index 00000000000..98fbff363f5 --- /dev/null +++ b/patches.renesas/0374-ARM-shmobile-armadillo800eva-Add-backlight-support.patch @@ -0,0 +1,119 @@ +From 2dcfe97aea7f6c061b4b0d3045d8c64feaaac1bb Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 16 Jul 2013 12:32:05 +0200 +Subject: ARM: shmobile: armadillo800eva: Add backlight support + +The flat panel backlight on the Armadillo 800 EVA board is driven by the +TPU PWM output. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Tested-by: Simon Horman <horms@verge.net.au> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d58226a21a7b84a3f82265821f24ce2aad267f1c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-armadillo800eva.c | 54 +++++++++++++++++++++++++- + 1 file changed, 52 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c +index 701104c9..9bb74729 100644 +--- a/arch/arm/mach-shmobile/board-armadillo800eva.c ++++ b/arch/arm/mach-shmobile/board-armadillo800eva.c +@@ -31,6 +31,8 @@ + #include <linux/gpio_keys.h> + #include <linux/regulator/driver.h> + #include <linux/pinctrl/machine.h> ++#include <linux/platform_data/pwm-renesas-tpu.h> ++#include <linux/pwm_backlight.h> + #include <linux/regulator/fixed.h> + #include <linux/regulator/gpio-regulator.h> + #include <linux/regulator/machine.h> +@@ -386,7 +388,50 @@ static struct platform_device sh_eth_device = { + .num_resources = ARRAY_SIZE(sh_eth_resources), + }; + +-/* LCDC */ ++/* PWM */ ++static struct resource pwm_resources[] = { ++ [0] = { ++ .start = 0xe6600000, ++ .end = 0xe66000ff, ++ .flags = IORESOURCE_MEM, ++ }, ++}; ++ ++static struct tpu_pwm_platform_data pwm_device_data = { ++ .channels[2] = { ++ .polarity = PWM_POLARITY_INVERSED, ++ } ++}; ++ ++static struct platform_device pwm_device = { ++ .name = "renesas-tpu-pwm", ++ .id = -1, ++ .dev = { ++ .platform_data = &pwm_device_data, ++ }, ++ .num_resources = ARRAY_SIZE(pwm_resources), ++ .resource = pwm_resources, ++}; ++ ++static struct pwm_lookup pwm_lookup[] = { ++ PWM_LOOKUP("renesas-tpu-pwm", 2, "pwm-backlight.0", NULL), ++}; ++ ++/* LCDC and backlight */ ++static struct platform_pwm_backlight_data pwm_backlight_data = { ++ .lth_brightness = 50, ++ .max_brightness = 255, ++ .dft_brightness = 255, ++ .pwm_period_ns = 33333, /* 30kHz */ ++}; ++ ++static struct platform_device pwm_backlight_device = { ++ .name = "pwm-backlight", ++ .dev = { ++ .platform_data = &pwm_backlight_data, ++ }, ++}; ++ + static struct fb_videomode lcdc0_mode = { + .name = "AMPIER/AM-800480", + .xres = 800, +@@ -1022,6 +1067,8 @@ static struct i2c_board_info i2c2_devices[] = { + */ + static struct platform_device *eva_devices[] __initdata = { + &lcdc0_device, ++ &pwm_device, ++ &pwm_backlight_device, + &gpio_keys_device, + &sh_eth_device, + &vcc_sdhi0, +@@ -1093,6 +1140,9 @@ static const struct pinctrl_map eva_pinctrl_map[] = { + /* ST1232 */ + PIN_MAP_MUX_GROUP_DEFAULT("0-0055", "pfc-r8a7740", + "intc_irq10", "intc"), ++ /* TPU0 */ ++ PIN_MAP_MUX_GROUP_DEFAULT("renesas-tpu-pwm", "pfc-r8a7740", ++ "tpu0_to2_1", "tpu0"), + /* USBHS */ + PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-r8a7740", + "intc_irq7_1", "intc"), +@@ -1146,13 +1196,13 @@ static void __init eva_init(void) + ARRAY_SIZE(fixed3v3_power_consumers), 3300000); + + pinctrl_register_mappings(eva_pinctrl_map, ARRAY_SIZE(eva_pinctrl_map)); ++ pwm_add_table(pwm_lookup, ARRAY_SIZE(pwm_lookup)); + + r8a7740_pinmux_init(); + r8a7740_meram_workaround(); + + /* LCDC0 */ + gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ +- gpio_request_one(202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */ + + /* GETHER */ + gpio_request_one(18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0375-ARM-shmobile-kota2-Use-leds-pwm-pwm-rmob.patch b/patches.renesas/0375-ARM-shmobile-kota2-Use-leds-pwm-pwm-rmob.patch new file mode 100644 index 00000000000..4ae838bcd98 --- /dev/null +++ b/patches.renesas/0375-ARM-shmobile-kota2-Use-leds-pwm-pwm-rmob.patch @@ -0,0 +1,302 @@ +From 8fa9b9d29518469fd9d401be2888339b04259f77 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 16 Jul 2013 12:32:06 +0200 +Subject: ARM: shmobile: kota2: Use leds-pwm + pwm-rmob + +Instead of using the LED-specific TPU PWM driver, switch to the generic +TPU PWM driver with leds-pwm. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit b885966f61b349baccf5c8c266f03407cfcea5ea) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-kota2.c | 169 +++++++++++++++++----------------- + arch/arm/mach-shmobile/clock-sh73a0.c | 12 ++- + 2 files changed, 90 insertions(+), 91 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c +index ef5ca0ef..6af20d90 100644 +--- a/arch/arm/mach-shmobile/board-kota2.c ++++ b/arch/arm/mach-shmobile/board-kota2.c +@@ -26,6 +26,7 @@ + #include <linux/irq.h> + #include <linux/pinctrl/machine.h> + #include <linux/pinctrl/pinconf-generic.h> ++#include <linux/platform_data/pwm-renesas-tpu.h> + #include <linux/platform_device.h> + #include <linux/delay.h> + #include <linux/io.h> +@@ -37,8 +38,8 @@ + #include <linux/input/sh_keysc.h> + #include <linux/gpio_keys.h> + #include <linux/leds.h> ++#include <linux/leds_pwm.h> + #include <linux/irqchip/arm-gic.h> +-#include <linux/platform_data/leds-renesas-tpu.h> + #include <linux/mmc/host.h> + #include <linux/mmc/sh_mmcif.h> + #include <linux/mfd/tmio.h> +@@ -186,116 +187,100 @@ static struct platform_device gpio_leds_device = { + }; + + /* TPU LED */ +-static struct led_renesas_tpu_config led_renesas_tpu12_pdata = { +- .name = "V2513", +- .pin_gpio_fn = GPIO_FN_TPU1TO2, +- .pin_gpio = 153, +- .channel_offset = 0x90, +- .timer_bit = 2, +- .max_brightness = 1000, +-}; +- +-static struct resource tpu12_resources[] = { ++static struct resource tpu1_pwm_resources[] = { + [0] = { +- .name = "TPU12", +- .start = 0xe6610090, +- .end = 0xe66100b5, ++ .start = 0xe6610000, ++ .end = 0xe66100ff, + .flags = IORESOURCE_MEM, + }, + }; + +-static struct platform_device leds_tpu12_device = { +- .name = "leds-renesas-tpu", +- .id = 12, +- .dev = { +- .platform_data = &led_renesas_tpu12_pdata, +- }, +- .num_resources = ARRAY_SIZE(tpu12_resources), +- .resource = tpu12_resources, ++static struct platform_device tpu1_pwm_device = { ++ .name = "renesas-tpu-pwm", ++ .id = 1, ++ .num_resources = ARRAY_SIZE(tpu1_pwm_resources), ++ .resource = tpu1_pwm_resources, + }; + +-static struct led_renesas_tpu_config led_renesas_tpu41_pdata = { +- .name = "V2514", +- .pin_gpio_fn = GPIO_FN_TPU4TO1, +- .pin_gpio = 199, +- .channel_offset = 0x50, +- .timer_bit = 1, +- .max_brightness = 1000, +-}; +- +-static struct resource tpu41_resources[] = { ++static struct resource tpu2_pwm_resources[] = { + [0] = { +- .name = "TPU41", +- .start = 0xe6640050, +- .end = 0xe6640075, ++ .start = 0xe6620000, ++ .end = 0xe66200ff, + .flags = IORESOURCE_MEM, + }, + }; + +-static struct platform_device leds_tpu41_device = { +- .name = "leds-renesas-tpu", +- .id = 41, +- .dev = { +- .platform_data = &led_renesas_tpu41_pdata, ++static struct platform_device tpu2_pwm_device = { ++ .name = "renesas-tpu-pwm", ++ .id = 2, ++ .num_resources = ARRAY_SIZE(tpu2_pwm_resources), ++ .resource = tpu2_pwm_resources, ++}; ++ ++static struct resource tpu3_pwm_resources[] = { ++ [0] = { ++ .start = 0xe6630000, ++ .end = 0xe66300ff, ++ .flags = IORESOURCE_MEM, + }, +- .num_resources = ARRAY_SIZE(tpu41_resources), +- .resource = tpu41_resources, + }; + +-static struct led_renesas_tpu_config led_renesas_tpu21_pdata = { +- .name = "V2515", +- .pin_gpio_fn = GPIO_FN_TPU2TO1, +- .pin_gpio = 197, +- .channel_offset = 0x50, +- .timer_bit = 1, +- .max_brightness = 1000, ++static struct platform_device tpu3_pwm_device = { ++ .name = "renesas-tpu-pwm", ++ .id = 3, ++ .num_resources = ARRAY_SIZE(tpu3_pwm_resources), ++ .resource = tpu3_pwm_resources, + }; + +-static struct resource tpu21_resources[] = { ++static struct resource tpu4_pwm_resources[] = { + [0] = { +- .name = "TPU21", +- .start = 0xe6620050, +- .end = 0xe6620075, ++ .start = 0xe6640000, ++ .end = 0xe66400ff, + .flags = IORESOURCE_MEM, + }, + }; + +-static struct platform_device leds_tpu21_device = { +- .name = "leds-renesas-tpu", +- .id = 21, +- .dev = { +- .platform_data = &led_renesas_tpu21_pdata, ++static struct platform_device tpu4_pwm_device = { ++ .name = "renesas-tpu-pwm", ++ .id = 4, ++ .num_resources = ARRAY_SIZE(tpu4_pwm_resources), ++ .resource = tpu4_pwm_resources, ++}; ++ ++static struct pwm_lookup pwm_lookup[] = { ++ PWM_LOOKUP("renesas-tpu-pwm.1", 2, "leds-pwm.0", "V2513"), ++ PWM_LOOKUP("renesas-tpu-pwm.2", 1, "leds-pwm.0", "V2515"), ++ PWM_LOOKUP("renesas-tpu-pwm.3", 0, "leds-pwm.0", "KEYLED"), ++ PWM_LOOKUP("renesas-tpu-pwm.4", 1, "leds-pwm.0", "V2514"), ++}; ++ ++static struct led_pwm tpu_pwm_leds[] = { ++ { ++ .name = "V2513", ++ .max_brightness = 1000, ++ }, { ++ .name = "V2515", ++ .max_brightness = 1000, ++ }, { ++ .name = "KEYLED", ++ .max_brightness = 1000, ++ }, { ++ .name = "V2514", ++ .max_brightness = 1000, + }, +- .num_resources = ARRAY_SIZE(tpu21_resources), +- .resource = tpu21_resources, + }; + +-static struct led_renesas_tpu_config led_renesas_tpu30_pdata = { +- .name = "KEYLED", +- .pin_gpio_fn = GPIO_FN_TPU3TO0, +- .pin_gpio = 163, +- .channel_offset = 0x10, +- .timer_bit = 0, +- .max_brightness = 1000, ++static struct led_pwm_platform_data leds_pwm_pdata = { ++ .num_leds = ARRAY_SIZE(tpu_pwm_leds), ++ .leds = tpu_pwm_leds, + }; + +-static struct resource tpu30_resources[] = { +- [0] = { +- .name = "TPU30", +- .start = 0xe6630010, +- .end = 0xe6630035, +- .flags = IORESOURCE_MEM, +- }, +-}; +- +-static struct platform_device leds_tpu30_device = { +- .name = "leds-renesas-tpu", +- .id = 30, ++static struct platform_device leds_pwm_device = { ++ .name = "leds-pwm", ++ .id = 0, + .dev = { +- .platform_data = &led_renesas_tpu30_pdata, ++ .platform_data = &leds_pwm_pdata, + }, +- .num_resources = ARRAY_SIZE(tpu30_resources), +- .resource = tpu30_resources, + }; + + /* Fixed 1.8V regulator to be used by MMCIF */ +@@ -426,10 +411,11 @@ static struct platform_device *kota2_devices[] __initdata = { + &keysc_device, + &gpio_keys_device, + &gpio_leds_device, +- &leds_tpu12_device, +- &leds_tpu41_device, +- &leds_tpu21_device, +- &leds_tpu30_device, ++ &tpu1_pwm_device, ++ &tpu2_pwm_device, ++ &tpu3_pwm_device, ++ &tpu4_pwm_device, ++ &leds_pwm_device, + &mmcif_device, + &sdhi0_device, + &sdhi1_device, +@@ -512,6 +498,15 @@ static const struct pinctrl_map kota2_pinctrl_map[] = { + "bsc_cs5_a", "bsc"), + PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0", + "bsc_we0", "bsc"), ++ /* TPU */ ++ PIN_MAP_MUX_GROUP_DEFAULT("renesas-tpu-pwm.1", "pfc-sh73a0", ++ "tpu1_to2", "tpu1"), ++ PIN_MAP_MUX_GROUP_DEFAULT("renesas-tpu-pwm.2", "pfc-sh73a0", ++ "tpu2_to1", "tpu2"), ++ PIN_MAP_MUX_GROUP_DEFAULT("renesas-tpu-pwm.3", "pfc-sh73a0", ++ "tpu3_to0", "tpu3"), ++ PIN_MAP_MUX_GROUP_DEFAULT("renesas-tpu-pwm.4", "pfc-sh73a0", ++ "tpu4_to1", "tpu4"), + }; + + static void __init kota2_init(void) +@@ -524,6 +519,8 @@ static void __init kota2_init(void) + + pinctrl_register_mappings(kota2_pinctrl_map, + ARRAY_SIZE(kota2_pinctrl_map)); ++ pwm_add_table(pwm_lookup, ARRAY_SIZE(pwm_lookup)); ++ + sh73a0_pinmux_init(); + + /* SMSC911X */ +diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c +index d9fd0336..1942eaef 100644 +--- a/arch/arm/mach-shmobile/clock-sh73a0.c ++++ b/arch/arm/mach-shmobile/clock-sh73a0.c +@@ -555,7 +555,7 @@ enum { MSTP001, + MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, + MSTP331, MSTP329, MSTP328, MSTP325, MSTP323, MSTP322, + MSTP314, MSTP313, MSTP312, MSTP311, +- MSTP303, MSTP302, MSTP301, MSTP300, ++ MSTP304, MSTP303, MSTP302, MSTP301, MSTP300, + MSTP411, MSTP410, MSTP403, + MSTP_NR }; + +@@ -593,6 +593,7 @@ static struct clk mstp_clks[MSTP_NR] = { + [MSTP313] = MSTP(&div6_clks[DIV6_SDHI1], SMSTPCR3, 13, 0), /* SDHI1 */ + [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */ + [MSTP311] = MSTP(&div6_clks[DIV6_SDHI2], SMSTPCR3, 11, 0), /* SDHI2 */ ++ [MSTP304] = MSTP(&main_div2_clk, SMSTPCR3, 4, 0), /* TPU0 */ + [MSTP303] = MSTP(&main_div2_clk, SMSTPCR3, 3, 0), /* TPU1 */ + [MSTP302] = MSTP(&main_div2_clk, SMSTPCR3, 2, 0), /* TPU2 */ + [MSTP301] = MSTP(&main_div2_clk, SMSTPCR3, 1, 0), /* TPU3 */ +@@ -669,10 +670,11 @@ static struct clk_lookup lookups[] = { + CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMCIF0 */ + CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */ + CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP311]), /* SDHI2 */ +- CLKDEV_DEV_ID("leds-renesas-tpu.12", &mstp_clks[MSTP303]), /* TPU1 */ +- CLKDEV_DEV_ID("leds-renesas-tpu.21", &mstp_clks[MSTP302]), /* TPU2 */ +- CLKDEV_DEV_ID("leds-renesas-tpu.30", &mstp_clks[MSTP301]), /* TPU3 */ +- CLKDEV_DEV_ID("leds-renesas-tpu.41", &mstp_clks[MSTP300]), /* TPU4 */ ++ CLKDEV_DEV_ID("renesas-tpu-pwm.0", &mstp_clks[MSTP304]), /* TPU0 */ ++ CLKDEV_DEV_ID("renesas-tpu-pwm.1", &mstp_clks[MSTP303]), /* TPU1 */ ++ CLKDEV_DEV_ID("renesas-tpu-pwm.2", &mstp_clks[MSTP302]), /* TPU2 */ ++ CLKDEV_DEV_ID("renesas-tpu-pwm.3", &mstp_clks[MSTP301]), /* TPU3 */ ++ CLKDEV_DEV_ID("renesas-tpu-pwm.4", &mstp_clks[MSTP300]), /* TPU4 */ + CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* I2C3 */ + CLKDEV_DEV_ID("e6826000.i2c", &mstp_clks[MSTP411]), /* I2C3 */ + CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0376-ARM-shmobile-sh73a0-Remove-all-GPIOs.patch b/patches.renesas/0376-ARM-shmobile-sh73a0-Remove-all-GPIOs.patch new file mode 100644 index 00000000000..8de03762130 --- /dev/null +++ b/patches.renesas/0376-ARM-shmobile-sh73a0-Remove-all-GPIOs.patch @@ -0,0 +1,403 @@ +From 7724b0e8f9f3c1e3826db8d9d205e8bbbe3ed730 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 16 Jul 2013 12:32:07 +0200 +Subject: ARM: shmobile: sh73a0: Remove all GPIOs + +Function GPIOs are not used anymore, and all code use the GPIO numbers +directly. Remove the GPIOs enumeration. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit e6909dcedb55b8790f5b79599987d84eea5888b1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/include/mach/sh73a0.h | 373 +-------------------------- + 1 file changed, 1 insertion(+), 372 deletions(-) + +diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h +index eb7a4320..680dc5f1 100644 +--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h ++++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h +@@ -1,378 +1,7 @@ + #ifndef __ASM_SH73A0_H__ + #define __ASM_SH73A0_H__ + +-/* Pin Function Controller: +- * GPIO_FN_xx - GPIO used to select pin function and MSEL switch +- * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU +- */ +-enum { +- /* Hardware manual Table 25-1 (GPIO) */ +- GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4, +- GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9, +- +- GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14, +- GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19, +- +- GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24, +- GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29, +- +- GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34, +- GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39, +- +- GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44, +- GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49, +- +- GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54, +- GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59, +- +- GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64, +- GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69, +- +- GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74, +- GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79, +- +- GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84, +- GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89, +- +- GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94, +- GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99, +- +- GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104, +- GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109, +- +- GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114, +- GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, +- +- GPIO_PORT128, GPIO_PORT129, +- +- GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134, +- GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139, +- +- GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144, +- GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149, +- +- GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154, +- GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159, +- +- GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164, +- +- GPIO_PORT192, GPIO_PORT193, GPIO_PORT194, +- GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199, +- +- GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204, +- GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209, +- +- GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214, +- GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219, +- +- GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224, +- GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229, +- +- GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234, +- GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239, +- +- GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244, +- GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249, +- +- GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254, +- GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259, +- +- GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264, +- GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269, +- +- GPIO_PORT270, GPIO_PORT271, GPIO_PORT272, GPIO_PORT273, GPIO_PORT274, +- GPIO_PORT275, GPIO_PORT276, GPIO_PORT277, GPIO_PORT278, GPIO_PORT279, +- +- GPIO_PORT280, GPIO_PORT281, GPIO_PORT282, +- +- GPIO_PORT288, GPIO_PORT289, +- +- GPIO_PORT290, GPIO_PORT291, GPIO_PORT292, GPIO_PORT293, GPIO_PORT294, +- GPIO_PORT295, GPIO_PORT296, GPIO_PORT297, GPIO_PORT298, GPIO_PORT299, +- +- GPIO_PORT300, GPIO_PORT301, GPIO_PORT302, GPIO_PORT303, GPIO_PORT304, +- GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309, +- +- /* Table 25-1 (Function 0-7) */ +- GPIO_FN_GPI0 = 310, +- GPIO_FN_GPI1, +- GPIO_FN_GPI2, +- GPIO_FN_GPI3, +- GPIO_FN_GPI4, +- GPIO_FN_GPI5, +- GPIO_FN_GPI6, +- GPIO_FN_GPI7, +- GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2, +- GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2, +- GPIO_FN_GPO5, +- GPIO_FN_PORT16_VIO_CKOR, +- GPIO_FN_PORT19_VIO_CKO2, +- GPIO_FN_GPO0, +- GPIO_FN_GPO1, +- GPIO_FN_GPO2, GPIO_FN_STATUS0, +- GPIO_FN_GPO3, GPIO_FN_STATUS1, +- GPIO_FN_GPO4, GPIO_FN_STATUS2, +- GPIO_FN_VINT, +- GPIO_FN_TCKON, +- GPIO_FN_XDVFS1, +- GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT, +- GPIO_FN_XDVFS2, +- GPIO_FN_PORT28_TPU1TO1, +- GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1, +- GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR, +- GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT, +- GPIO_FN_XWUP, +- GPIO_FN_VACK, +- GPIO_FN_XTAL1L, +- GPIO_FN_PORT49_IROUT, +- GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, +- +- GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, +- GPIO_FN_BBIF2_TXD2, +- GPIO_FN_TPU3TO3, +- GPIO_FN_TPU3TO2, +- GPIO_FN_TPU0TO0, +- GPIO_FN_A0, GPIO_FN_BS_, +- GPIO_FN_A12, GPIO_FN_TPU4TO2, +- GPIO_FN_A13, GPIO_FN_TPU0TO1, +- GPIO_FN_A14, +- GPIO_FN_A15, +- GPIO_FN_A16, GPIO_FN_MSIOF0_SS1, +- GPIO_FN_A17, GPIO_FN_MSIOF0_TSYNC, +- GPIO_FN_A18, GPIO_FN_MSIOF0_TSCK, +- GPIO_FN_A19, GPIO_FN_MSIOF0_TXD, +- GPIO_FN_A20, GPIO_FN_MSIOF0_RSCK, +- GPIO_FN_A21, GPIO_FN_MSIOF0_RSYNC, +- GPIO_FN_A22, GPIO_FN_MSIOF0_MCK0, +- GPIO_FN_A23, GPIO_FN_MSIOF0_MCK1, +- GPIO_FN_A24, GPIO_FN_MSIOF0_RXD, +- GPIO_FN_A25, GPIO_FN_MSIOF0_SS2, +- GPIO_FN_A26, +- GPIO_FN_FCE1_, +- GPIO_FN_DACK0, +- GPIO_FN_FCE0_, +- GPIO_FN_WAIT_, GPIO_FN_DREQ0, +- GPIO_FN_FRB, +- GPIO_FN_CKO, +- GPIO_FN_NBRSTOUT_, +- GPIO_FN_NBRST_, +- GPIO_FN_BBIF2_TXD, +- GPIO_FN_BBIF2_RXD, +- GPIO_FN_BBIF2_SYNC, +- GPIO_FN_BBIF2_SCK, +- GPIO_FN_MFG3_IN2, +- GPIO_FN_MFG3_IN1, +- GPIO_FN_BBIF1_SS2, GPIO_FN_MFG3_OUT1, +- GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD, +- GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK, +- GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC, +- GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD, +- GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK, +- GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC, +- GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW, +- GPIO_FN_HSI_TX_FLAG, +- GPIO_FN_VIO_VD, GPIO_FN_VIO2_VD, +- +- GPIO_FN_VIO_HD, +- GPIO_FN_VIO2_HD, +- GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, +- GPIO_FN_VIO_D1, GPIO_FN_PORT131_MSIOF2_SS1, +- GPIO_FN_VIO_D2, GPIO_FN_PORT132_MSIOF2_SS2, +- GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, +- GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, +- GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, +- GPIO_FN_VIO_D6, +- GPIO_FN_VIO_D7, +- GPIO_FN_VIO_D8, GPIO_FN_VIO2_D0, +- GPIO_FN_VIO_D9, GPIO_FN_VIO2_D1, +- GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, +- GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, +- GPIO_FN_VIO_D12, GPIO_FN_VIO2_D4, +- GPIO_FN_VIO_D13, +- GPIO_FN_VIO2_D5, +- GPIO_FN_VIO_D14, GPIO_FN_VIO2_D6, +- GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, +- GPIO_FN_VIO2_D7, +- GPIO_FN_VIO_CLK, +- GPIO_FN_VIO2_CLK, +- GPIO_FN_VIO_FIELD, GPIO_FN_VIO2_FIELD, +- GPIO_FN_VIO_CKO, +- GPIO_FN_A27, GPIO_FN_MFG0_IN1, +- GPIO_FN_MFG0_IN2, +- GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK, +- GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC, +- GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1, +- GPIO_FN_MSIOF2_MCK0, +- GPIO_FN_MSIOF2_MCK1, +- GPIO_FN_PORT156_MSIOF2_SS2, +- GPIO_FN_PORT157_MSIOF2_RXD, +- GPIO_FN_DINT_, GPIO_FN_TS_SCK3, +- GPIO_FN_NMI, +- GPIO_FN_TPU3TO0, +- GPIO_FN_BBIF2_TSYNC1, +- GPIO_FN_BBIF2_TSCK1, +- GPIO_FN_BBIF2_TXD1, +- GPIO_FN_MFG2_OUT2, +- GPIO_FN_TPU2TO1, +- GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2, +- GPIO_FN_D16, +- GPIO_FN_D17, +- GPIO_FN_D18, +- GPIO_FN_D19, +- GPIO_FN_D20, +- GPIO_FN_D21, +- GPIO_FN_D22, +- GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23, +- GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24, +- GPIO_FN_D25, +- GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26, +- GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27, +- GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28, +- GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29, +- GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30, +- GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31, +- GPIO_FN_DACK2, +- GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3, +- GPIO_FN_DACK3, +- GPIO_FN_PORT218_VIO_CKOR, +- GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \ +- GPIO_FN_DREQ1, +- GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \ +- GPIO_FN_DACK1, GPIO_FN_OVCN, +- GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, +- +- GPIO_FN_OVCN2, +- GPIO_FN_EXTLP, GPIO_FN_PORT226_VIO_CKO2, +- GPIO_FN_IDIN, +- GPIO_FN_MFG1_IN1, +- GPIO_FN_MSIOF1_TXD, +- GPIO_FN_MSIOF1_TSYNC, +- GPIO_FN_MSIOF1_TSCK, +- GPIO_FN_MSIOF1_RXD, +- GPIO_FN_MSIOF1_RSCK, GPIO_FN_VIO2_CLK2, +- GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \ +- GPIO_FN_MSIOF1_MCK0, +- GPIO_FN_MSIOF1_MCK1, +- GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, +- GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, +- GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \ +- GPIO_FN_TPU4TO0, +- GPIO_FN_MFG4_IN2, +- GPIO_FN_PORT243_VIO_CKO2, +- GPIO_FN_MFG2_IN1, +- GPIO_FN_MSIOF2R_RXD, +- GPIO_FN_MFG2_IN2, +- GPIO_FN_MSIOF2R_TXD, +- GPIO_FN_MFG1_OUT1, +- GPIO_FN_TPU1TO0, +- GPIO_FN_MFG3_OUT2, +- GPIO_FN_TPU3TO1, +- GPIO_FN_MFG2_OUT1, +- GPIO_FN_TPU2TO0, +- GPIO_FN_MSIOF2R_TSCK, +- GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \ +- GPIO_FN_MSIOF2R_TSYNC, +- GPIO_FN_SDHICLK0, +- GPIO_FN_SDHICD0, +- GPIO_FN_SDHID0_0, +- GPIO_FN_SDHID0_1, +- GPIO_FN_SDHID0_2, +- GPIO_FN_SDHID0_3, +- GPIO_FN_SDHICMD0, +- GPIO_FN_SDHIWP0, +- GPIO_FN_SDHICLK1, +- GPIO_FN_SDHID1_0, GPIO_FN_TS_SPSYNC2, +- GPIO_FN_SDHID1_1, GPIO_FN_TS_SDAT2, +- GPIO_FN_SDHID1_2, GPIO_FN_TS_SDEN2, +- GPIO_FN_SDHID1_3, GPIO_FN_TS_SCK2, +- GPIO_FN_SDHICMD1, +- GPIO_FN_SDHICLK2, +- GPIO_FN_SDHID2_0, GPIO_FN_TS_SPSYNC4, +- GPIO_FN_SDHID2_1, GPIO_FN_TS_SDAT4, +- GPIO_FN_SDHID2_2, GPIO_FN_TS_SDEN4, +- GPIO_FN_SDHID2_3, GPIO_FN_TS_SCK4, +- GPIO_FN_SDHICMD2, +- GPIO_FN_MMCCLK0, +- GPIO_FN_MMCD0_0, +- GPIO_FN_MMCD0_1, +- GPIO_FN_MMCD0_2, +- GPIO_FN_MMCD0_3, +- GPIO_FN_MMCD0_4, GPIO_FN_TS_SPSYNC5, +- GPIO_FN_MMCD0_5, GPIO_FN_TS_SDAT5, +- GPIO_FN_MMCD0_6, GPIO_FN_TS_SDEN5, +- GPIO_FN_MMCD0_7, GPIO_FN_TS_SCK5, +- GPIO_FN_MMCCMD0, +- GPIO_FN_RESETOUTS_, GPIO_FN_EXTAL2OUT, +- GPIO_FN_MCP_WAIT__MCP_FRB, +- GPIO_FN_MCP_CKO, GPIO_FN_MMCCLK1, +- GPIO_FN_MCP_D15_MCP_NAF15, +- GPIO_FN_MCP_D14_MCP_NAF14, +- GPIO_FN_MCP_D13_MCP_NAF13, +- GPIO_FN_MCP_D12_MCP_NAF12, +- GPIO_FN_MCP_D11_MCP_NAF11, +- GPIO_FN_MCP_D10_MCP_NAF10, +- GPIO_FN_MCP_D9_MCP_NAF9, +- GPIO_FN_MCP_D8_MCP_NAF8, GPIO_FN_MMCCMD1, +- GPIO_FN_MCP_D7_MCP_NAF7, GPIO_FN_MMCD1_7, +- +- GPIO_FN_MCP_D6_MCP_NAF6, GPIO_FN_MMCD1_6, +- GPIO_FN_MCP_D5_MCP_NAF5, GPIO_FN_MMCD1_5, +- GPIO_FN_MCP_D4_MCP_NAF4, GPIO_FN_MMCD1_4, +- GPIO_FN_MCP_D3_MCP_NAF3, GPIO_FN_MMCD1_3, +- GPIO_FN_MCP_D2_MCP_NAF2, GPIO_FN_MMCD1_2, +- GPIO_FN_MCP_D1_MCP_NAF1, GPIO_FN_MMCD1_1, +- GPIO_FN_MCP_D0_MCP_NAF0, GPIO_FN_MMCD1_0, +- GPIO_FN_MCP_NBRSTOUT_, +- GPIO_FN_MCP_WE0__MCP_FWE, GPIO_FN_MCP_RDWR_MCP_FWE, +- +- /* MSEL2 special case */ +- GPIO_FN_TSIF2_TS_XX1, +- GPIO_FN_TSIF2_TS_XX2, +- GPIO_FN_TSIF2_TS_XX3, +- GPIO_FN_TSIF2_TS_XX4, +- GPIO_FN_TSIF2_TS_XX5, +- GPIO_FN_TSIF1_TS_XX1, +- GPIO_FN_TSIF1_TS_XX2, +- GPIO_FN_TSIF1_TS_XX3, +- GPIO_FN_TSIF1_TS_XX4, +- GPIO_FN_TSIF1_TS_XX5, +- GPIO_FN_TSIF0_TS_XX1, +- GPIO_FN_TSIF0_TS_XX2, +- GPIO_FN_TSIF0_TS_XX3, +- GPIO_FN_TSIF0_TS_XX4, +- GPIO_FN_TSIF0_TS_XX5, +- GPIO_FN_MST1_TS_XX1, +- GPIO_FN_MST1_TS_XX2, +- GPIO_FN_MST1_TS_XX3, +- GPIO_FN_MST1_TS_XX4, +- GPIO_FN_MST1_TS_XX5, +- GPIO_FN_MST0_TS_XX1, +- GPIO_FN_MST0_TS_XX2, +- GPIO_FN_MST0_TS_XX3, +- GPIO_FN_MST0_TS_XX4, +- GPIO_FN_MST0_TS_XX5, +- +- /* MSEL3 special cases */ +- GPIO_FN_SDHI0_VCCQ_MC0_ON, +- GPIO_FN_SDHI0_VCCQ_MC0_OFF, +- GPIO_FN_DEBUG_MON_VIO, +- GPIO_FN_DEBUG_MON_LCDD, +- GPIO_FN_LCDC_LCDC0, +- GPIO_FN_LCDC_LCDC1, +- +- /* MSEL4 special cases */ +- GPIO_FN_IRQ9_MEM_INT, +- GPIO_FN_IRQ9_MCP_INT, +- GPIO_FN_A11, +- GPIO_FN_TPU4TO3, +- GPIO_FN_RESETA_N_PU_ON, +- GPIO_FN_RESETA_N_PU_OFF, +- GPIO_FN_EDBGREQ_PD, +- GPIO_FN_EDBGREQ_PU, +- +- /* end of GPIO */ +- GPIO_NR, +-}; ++#define GPIO_NR 310 + + /* DMA slave IDs */ + enum { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0377-ARM-shmobile-r8a73a4-Add-pin-control-device-to-devic.patch b/patches.renesas/0377-ARM-shmobile-r8a73a4-Add-pin-control-device-to-devic.patch new file mode 100644 index 00000000000..78895e984b3 --- /dev/null +++ b/patches.renesas/0377-ARM-shmobile-r8a73a4-Add-pin-control-device-to-devic.patch @@ -0,0 +1,42 @@ +From 19c094af67dc56268d8961d19056fb3cf8fef0ed Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 9 May 2013 15:05:57 +0200 +Subject: ARM: shmobile: r8a73a4: Add pin control device to device tree + +Add a pfc node to the r8a73a4 device tree. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +[g.liakhovetski+renesas@gmail.com use 2 nodes for address and size] +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit 803d319cb2fb41e646669061b45701f3ea78e611) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + arch/arm/boot/dts/r8a73a4.dtsi +--- + arch/arm/boot/dts/r8a73a4.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi +index 6ce699be..6c26caa8 100644 +--- a/arch/arm/boot/dts/r8a73a4.dtsi ++++ b/arch/arm/boot/dts/r8a73a4.dtsi +@@ -185,6 +185,13 @@ + status = "disabled"; + }; + ++ pfc: pfc@e6050000 { ++ compatible = "renesas,pfc-r8a73a4"; ++ reg = <0 0xe6050000 0 0x9000>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; ++ + sdhi0: sdhi@ee100000 { + compatible = "renesas,r8a73a4-sdhi"; + reg = <0 0xee100000 0 0x100>; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0378-ARM-shmobile-r8a7740-Add-pin-control-device-to-devic.patch b/patches.renesas/0378-ARM-shmobile-r8a7740-Add-pin-control-device-to-devic.patch new file mode 100644 index 00000000000..d110fb5fb2b --- /dev/null +++ b/patches.renesas/0378-ARM-shmobile-r8a7740-Add-pin-control-device-to-devic.patch @@ -0,0 +1,80 @@ +From 2bc32d05a584a7b8675f2445c1275b9b29f94f2b Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 20 Nov 2012 14:02:54 +0100 +Subject: ARM: shmobile: r8a7740: Add pin control device to device tree + +Add a pfc node to the r8a7740 device tree and remove manual pinmux +initialization from the corresponding board files. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit f36218d25f2388775a06b6091d881b7a45b7595f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7740.dtsi | 8 ++++++++ + arch/arm/mach-shmobile/board-armadillo800eva-reference.c | 16 ++++++++-------- + 2 files changed, 16 insertions(+), 8 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi +index 24e93064..e18a195b 100644 +--- a/arch/arm/boot/dts/r8a7740.dtsi ++++ b/arch/arm/boot/dts/r8a7740.dtsi +@@ -139,4 +139,12 @@ + 0 72 0x4 + 0 73 0x4>; + }; ++ ++ pfc: pfc@e6050000 { ++ compatible = "renesas,pfc-r8a7740"; ++ reg = <0xe6050000 0x8000>, ++ <0xe605800c 0x20>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; + }; +diff --git a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c +index 03b85fec..f25b6aab 100644 +--- a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c ++++ b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c +@@ -121,7 +121,7 @@ + + static const struct pinctrl_map eva_pinctrl_map[] = { + /* SCIFA1 */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.1", "pfc-r8a7740", ++ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.1", "e6050000.pfc", + "scifa1_data", "scifa1"), + }; + +@@ -170,22 +170,22 @@ static void __init eva_init(void) + eva_clock_init(); + + pinctrl_register_mappings(eva_pinctrl_map, ARRAY_SIZE(eva_pinctrl_map)); +- r8a7740_pinmux_init(); + + r8a7740_meram_workaround(); + +- /* +- * Touchscreen +- * TODO: Move reset GPIO over to .dts when we can reference it +- */ +- gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */ +- + #ifdef CONFIG_CACHE_L2X0 + /* Early BRESP enable, Shared attribute override enable, 32K*8way */ + l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff); + #endif + + r8a7740_add_standard_devices_dt(); ++ ++ /* ++ * Touchscreen ++ * TODO: Move reset GPIO over to .dts when we can reference it ++ */ ++ gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */ ++ + r8a7740_pm_init(); + } + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0379-ARM-shmobile-r8a7778-Add-pin-control-device-to-devic.patch b/patches.renesas/0379-ARM-shmobile-r8a7778-Add-pin-control-device-to-devic.patch new file mode 100644 index 00000000000..70fbf07b5a8 --- /dev/null +++ b/patches.renesas/0379-ARM-shmobile-r8a7778-Add-pin-control-device-to-devic.patch @@ -0,0 +1,32 @@ +From c245ba45297170a5bcd8e6acfc0089fa71ab653e Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 9 May 2013 15:05:57 +0200 +Subject: ARM: shmobile: r8a7778: Add pin control device to device tree + +Add a pfc node to the r8a7778 device tree. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 0697ccc05473083cb9e1cdf16cd1f425f0f9395f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7778.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi +index 47437355..c8dbf148 100644 +--- a/arch/arm/boot/dts/r8a7778.dtsi ++++ b/arch/arm/boot/dts/r8a7778.dtsi +@@ -32,4 +32,9 @@ + reg = <0xfe438000 0x1000>, + <0xfe430000 0x100>; + }; ++ ++ pfc: pfc@fffc0000 { ++ compatible = "renesas,pfc-r8a7778"; ++ reg = <0xfffc000 0x118>; ++ }; + }; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0380-ARM-shmobile-r8a7778-Add-GPIO-controller-devices-to-.patch b/patches.renesas/0380-ARM-shmobile-r8a7778-Add-GPIO-controller-devices-to-.patch new file mode 100644 index 00000000000..f171b1ca2b7 --- /dev/null +++ b/patches.renesas/0380-ARM-shmobile-r8a7778-Add-GPIO-controller-devices-to-.patch @@ -0,0 +1,92 @@ +From 7a973614a011511d43ea63fe33a7a4f3114178f9 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 10 May 2013 15:51:14 +0200 +Subject: ARM: shmobile: r8a7778: Add GPIO controller devices to device tree + +Add GPIO controller nodes to the r8a7778 core device tree. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit aaf7eda80cb8371bbf26d7171241cfb94b787b0f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7778.dtsi | 61 ++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 61 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi +index c8dbf148..45ac404a 100644 +--- a/arch/arm/boot/dts/r8a7778.dtsi ++++ b/arch/arm/boot/dts/r8a7778.dtsi +@@ -33,8 +33,69 @@ + <0xfe430000 0x100>; + }; + ++ gpio0: gpio@ffc40000 { ++ compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; ++ reg = <0xffc40000 0x2c>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 103 0x4>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ gpio-ranges = <&pfc 0 0 32>; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ }; ++ ++ gpio1: gpio@ffc41000 { ++ compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; ++ reg = <0xffc41000 0x2c>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 103 0x4>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ gpio-ranges = <&pfc 0 32 32>; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ }; ++ ++ gpio2: gpio@ffc42000 { ++ compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; ++ reg = <0xffc42000 0x2c>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 103 0x4>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ gpio-ranges = <&pfc 0 64 32>; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ }; ++ ++ gpio3: gpio@ffc43000 { ++ compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; ++ reg = <0xffc43000 0x2c>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 103 0x4>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ gpio-ranges = <&pfc 0 96 32>; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ }; ++ ++ gpio4: gpio@ffc44000 { ++ compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; ++ reg = <0xffc44000 0x2c>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 103 0x4>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ gpio-ranges = <&pfc 0 128 27>; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ }; ++ + pfc: pfc@fffc0000 { + compatible = "renesas,pfc-r8a7778"; + reg = <0xfffc000 0x118>; ++ #gpio-range-cells = <3>; + }; + }; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0381-ARM-shmobile-r8a7779-Add-pin-control-device-to-devic.patch b/patches.renesas/0381-ARM-shmobile-r8a7779-Add-pin-control-device-to-devic.patch new file mode 100644 index 00000000000..82ab0c2a37a --- /dev/null +++ b/patches.renesas/0381-ARM-shmobile-r8a7779-Add-pin-control-device-to-devic.patch @@ -0,0 +1,81 @@ +From 89da1f26fca254c66b79499c6f40aab8edab274b Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 9 May 2013 15:05:57 +0200 +Subject: ARM: shmobile: r8a7779: Add pin control device to device tree + +Add a pfc node to the r8a7779 device tree and remove manual pinmux +initialization from the corresponding board files. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 3ab03d01a989e4d77ed6ba0bc8c2efd9211df7c8) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7779.dtsi | 5 +++++ + arch/arm/mach-shmobile/board-marzen-reference.c | 17 ++++++++--------- + 2 files changed, 13 insertions(+), 9 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi +index 7f146c6b..9dfc4384 100644 +--- a/arch/arm/boot/dts/r8a7779.dtsi ++++ b/arch/arm/boot/dts/r8a7779.dtsi +@@ -101,6 +101,11 @@ + interrupts = <0 81 0x4>; + }; + ++ pfc: pfc@fffc0000 { ++ compatible = "renesas,pfc-r8a7779"; ++ reg = <0xfffc0000 0x23c>; ++ }; ++ + thermal@ffc48000 { + compatible = "renesas,rcar-thermal"; + reg = <0xffc48000 0x38>; +diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c +index 480d882e..94804f3c 100644 +--- a/arch/arm/mach-shmobile/board-marzen-reference.c ++++ b/arch/arm/mach-shmobile/board-marzen-reference.c +@@ -28,24 +28,24 @@ + + static const struct pinctrl_map marzen_pinctrl_map[] = { + /* SCIF2 (CN18: DEBUG0) */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-r8a7779", ++ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "fffc0000.pfc", + "scif2_data_c", "scif2"), + /* SCIF4 (CN19: DEBUG1) */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-r8a7779", ++ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "fffc0000.pfc", + "scif4_data", "scif4"), + /* SDHI0 */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "fffc0000.pfc", + "sdhi0_data4", "sdhi0"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "fffc0000.pfc", + "sdhi0_ctrl", "sdhi0"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "fffc0000.pfc", + "sdhi0_cd", "sdhi0"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "fffc0000.pfc", + "sdhi0_wp", "sdhi0"), + /* SMSC */ +- PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779", ++ PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "fffc0000.pfc", + "intc_irq1_b", "intc"), +- PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779", ++ PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "fffc0000.pfc", + "lbsc_ex_cs0", "lbsc"), + }; + +@@ -53,7 +53,6 @@ static void __init marzen_init(void) + { + pinctrl_register_mappings(marzen_pinctrl_map, + ARRAY_SIZE(marzen_pinctrl_map)); +- r8a7779_pinmux_init(); + + r8a7779_add_standard_devices_dt(); + } +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0382-ARM-shmobile-r8a7779-Add-GPIO-controller-devices-to-.patch b/patches.renesas/0382-ARM-shmobile-r8a7779-Add-GPIO-controller-devices-to-.patch new file mode 100644 index 00000000000..b5cb7de73fe --- /dev/null +++ b/patches.renesas/0382-ARM-shmobile-r8a7779-Add-GPIO-controller-devices-to-.patch @@ -0,0 +1,121 @@ +From 715096510f91ca13452eac4757466a900add4aac Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 10 May 2013 15:51:14 +0200 +Subject: ARM: shmobile: r8a7779: Add GPIO controller devices to device tree + +Add GPIO controller nodes to the r8a7779 core device tree. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit f5c771b5610b4c0d4daf9729aa03539ef1779a92) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7779.dtsi | 85 ++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 85 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi +index 9dfc4384..e9fbe3d5 100644 +--- a/arch/arm/boot/dts/r8a7779.dtsi ++++ b/arch/arm/boot/dts/r8a7779.dtsi +@@ -48,6 +48,90 @@ + <0xf0000100 0x100>; + }; + ++ gpio0: gpio@ffc40000 { ++ compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; ++ reg = <0xffc40000 0x2c>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 141 0x4>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ gpio-ranges = <&pfc 0 0 32>; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ }; ++ ++ gpio1: gpio@ffc41000 { ++ compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; ++ reg = <0xffc41000 0x2c>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 142 0x4>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ gpio-ranges = <&pfc 0 32 32>; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ }; ++ ++ gpio2: gpio@ffc42000 { ++ compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; ++ reg = <0xffc42000 0x2c>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 143 0x4>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ gpio-ranges = <&pfc 0 64 32>; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ }; ++ ++ gpio3: gpio@ffc43000 { ++ compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; ++ reg = <0xffc43000 0x2c>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 144 0x4>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ gpio-ranges = <&pfc 0 96 32>; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ }; ++ ++ gpio4: gpio@ffc44000 { ++ compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; ++ reg = <0xffc44000 0x2c>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 145 0x4>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ gpio-ranges = <&pfc 0 128 32>; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ }; ++ ++ gpio5: gpio@ffc45000 { ++ compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; ++ reg = <0xffc45000 0x2c>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 146 0x4>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ gpio-ranges = <&pfc 0 160 32>; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ }; ++ ++ gpio6: gpio@ffc46000 { ++ compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; ++ reg = <0xffc46000 0x2c>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 147 0x4>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ gpio-ranges = <&pfc 0 192 9>; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ }; ++ + irqpin0: irqpin@fe780010 { + compatible = "renesas,intc-irqpin"; + #interrupt-cells = <2>; +@@ -104,6 +188,7 @@ + pfc: pfc@fffc0000 { + compatible = "renesas,pfc-r8a7779"; + reg = <0xfffc0000 0x23c>; ++ #gpio-range-cells = <3>; + }; + + thermal@ffc48000 { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0383-ARM-shmobile-r8a7790-Add-pin-control-device-to-devic.patch b/patches.renesas/0383-ARM-shmobile-r8a7790-Add-pin-control-device-to-devic.patch new file mode 100644 index 00000000000..019fb366555 --- /dev/null +++ b/patches.renesas/0383-ARM-shmobile-r8a7790-Add-pin-control-device-to-devic.patch @@ -0,0 +1,37 @@ +From 60180ae7107aaf7d87d6fff5b52070f3e3f88492 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 9 May 2013 15:05:57 +0200 +Subject: ARM: shmobile: r8a7790: Add pin control device to device tree + +Add a pfc node to the r8a7790 device tree. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 9694c778048e006604c3fbade6b0aefa5dd0b516) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + arch/arm/boot/dts/r8a7790.dtsi +--- + arch/arm/boot/dts/r8a7790.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi +index 9cd88202..bfe93128 100644 +--- a/arch/arm/boot/dts/r8a7790.dtsi ++++ b/arch/arm/boot/dts/r8a7790.dtsi +@@ -73,6 +73,11 @@ + status = "disabled"; + }; + ++ pfc: pfc@e6060000 { ++ compatible = "renesas,pfc-r8a7790"; ++ reg = <0 0xe6060000 0 0x250>; ++ }; ++ + sdhi0: sdhi@ee100000 { + compatible = "renesas,r8a7790-sdhi"; + reg = <0 0xee100000 0 0x100>; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0384-ARM-shmobile-r8a7790-Add-GPIO-controller-devices-to-.patch b/patches.renesas/0384-ARM-shmobile-r8a7790-Add-GPIO-controller-devices-to-.patch new file mode 100644 index 00000000000..b36dfeaba25 --- /dev/null +++ b/patches.renesas/0384-ARM-shmobile-r8a7790-Add-GPIO-controller-devices-to-.patch @@ -0,0 +1,109 @@ +From d8db1ec2607c33d70ad6355c8b35c3cfda426b9f Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 10 May 2013 15:51:14 +0200 +Subject: ARM: shmobile: r8a7790: Add GPIO controller devices to device tree + +Add GPIO controller nodes to the r8a7790 core device tree. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit f98e10c88aa95bf7d37cce6dbacec0820dd6ecc2) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7790.dtsi | 73 ++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 73 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi +index bfe93128..3b879e7c 100644 +--- a/arch/arm/boot/dts/r8a7790.dtsi ++++ b/arch/arm/boot/dts/r8a7790.dtsi +@@ -38,6 +38,78 @@ + interrupts = <1 9 0xf04>; + }; + ++ gpio0: gpio@ffc40000 { ++ compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; ++ reg = <0 0xffc40000 0 0x2c>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 4 0x4>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ gpio-ranges = <&pfc 0 0 32>; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ }; ++ ++ gpio1: gpio@ffc41000 { ++ compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; ++ reg = <0 0xffc41000 0 0x2c>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 5 0x4>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ gpio-ranges = <&pfc 0 32 32>; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ }; ++ ++ gpio2: gpio@ffc42000 { ++ compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; ++ reg = <0 0xffc42000 0 0x2c>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 6 0x4>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ gpio-ranges = <&pfc 0 64 32>; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ }; ++ ++ gpio3: gpio@ffc43000 { ++ compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; ++ reg = <0 0xffc43000 0 0x2c>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 7 0x4>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ gpio-ranges = <&pfc 0 96 32>; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ }; ++ ++ gpio4: gpio@ffc44000 { ++ compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; ++ reg = <0 0xffc44000 0 0x2c>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 8 0x4>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ gpio-ranges = <&pfc 0 128 32>; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ }; ++ ++ gpio5: gpio@ffc45000 { ++ compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; ++ reg = <0 0xffc45000 0 0x2c>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 9 0x4>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ gpio-ranges = <&pfc 0 160 32>; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ }; ++ + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>, +@@ -76,6 +148,7 @@ + pfc: pfc@e6060000 { + compatible = "renesas,pfc-r8a7790"; + reg = <0 0xe6060000 0 0x250>; ++ #gpio-range-cells = <3>; + }; + + sdhi0: sdhi@ee100000 { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0385-ARM-shmobile-sh7372-Add-pin-control-device-to-device.patch b/patches.renesas/0385-ARM-shmobile-sh7372-Add-pin-control-device-to-device.patch new file mode 100644 index 00000000000..abc69ce9586 --- /dev/null +++ b/patches.renesas/0385-ARM-shmobile-sh7372-Add-pin-control-device-to-device.patch @@ -0,0 +1,35 @@ +From 5b383754ce4e62d383824fcf631715399b27a2bb Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 9 May 2013 15:05:57 +0200 +Subject: ARM: shmobile: sh7372: Add pin control device to device tree + +Add a pfc node to the sh7372 device tree. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 871e4b3e9e437b48287c635c5e66ba80b5cd365a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/sh7372.dtsi | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi +index 7bf020ec..249f65be2 100644 +--- a/arch/arm/boot/dts/sh7372.dtsi ++++ b/arch/arm/boot/dts/sh7372.dtsi +@@ -23,4 +23,12 @@ + reg = <0x0>; + }; + }; ++ ++ pfc: pfc@e6050000 { ++ compatible = "renesas,pfc-sh7372"; ++ reg = <0xe6050000 0x8000>, ++ <0xe605801c 0x1c>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; + }; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0386-ARM-shmobile-sh73a0-Add-pin-control-device-to-device.patch b/patches.renesas/0386-ARM-shmobile-sh73a0-Add-pin-control-device-to-device.patch new file mode 100644 index 00000000000..d995a3fb31f --- /dev/null +++ b/patches.renesas/0386-ARM-shmobile-sh73a0-Add-pin-control-device-to-device.patch @@ -0,0 +1,98 @@ +From 2f7570dfc3ef469b67d2825ad73b2546f6cc66ae Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 20 Nov 2012 14:02:54 +0100 +Subject: ARM: shmobile: sh73a0: Add pin control device to device tree + +Add a pfc node to the sh73a0 device tree and remove manual pinmux +initialization from the corresponding board files. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 3f59007e8efc29bb6cce08329bf010bcd9b19101) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/sh73a0.dtsi | 8 ++++++++ + arch/arm/mach-shmobile/board-kzm9g-reference.c | 27 +++++++++++++------------- + 2 files changed, 21 insertions(+), 14 deletions(-) + +diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi +index b9775025..86e79feb 100644 +--- a/arch/arm/boot/dts/sh73a0.dtsi ++++ b/arch/arm/boot/dts/sh73a0.dtsi +@@ -222,4 +222,12 @@ + cap-sd-highspeed; + status = "disabled"; + }; ++ ++ pfc: pfc@e6050000 { ++ compatible = "renesas,pfc-sh73a0"; ++ reg = <0xe6050000 0x8000>, ++ <0xe605801c 0x1c>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; + }; +diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c +index 41092bb0..d7bbd29a 100644 +--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c ++++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c +@@ -39,35 +39,35 @@ static unsigned long pin_pullup_conf[] = { + }; + + static const struct pinctrl_map kzm_pinctrl_map[] = { +- PIN_MAP_MUX_GROUP_DEFAULT("e6826000.i2c", "pfc-sh73a0", ++ PIN_MAP_MUX_GROUP_DEFAULT("e6826000.i2c", "e6050000.pfc", + "i2c3_1", "i2c3"), + /* MMCIF */ +- PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0", ++ PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "e6050000.pfc", + "mmc0_data8_0", "mmc0"), +- PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0", ++ PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "e6050000.pfc", + "mmc0_ctrl_0", "mmc0"), +- PIN_MAP_CONFIGS_PIN_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0", ++ PIN_MAP_CONFIGS_PIN_DEFAULT("e6bd0000.mmcif", "e6050000.pfc", + "PORT279", pin_pullup_conf), +- PIN_MAP_CONFIGS_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0", ++ PIN_MAP_CONFIGS_GROUP_DEFAULT("e6bd0000.mmcif", "e6050000.pfc", + "mmc0_data8_0", pin_pullup_conf), + /* SCIFA4 */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0", ++ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "e6050000.pfc", + "scifa4_data", "scifa4"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0", ++ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "e6050000.pfc", + "scifa4_ctrl", "scifa4"), + /* SDHI0 */ +- PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0", ++ PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "e6050000.pfc", + "sdhi0_data4", "sdhi0"), +- PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0", ++ PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "e6050000.pfc", + "sdhi0_ctrl", "sdhi0"), +- PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0", ++ PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "e6050000.pfc", + "sdhi0_cd", "sdhi0"), +- PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0", ++ PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "e6050000.pfc", + "sdhi0_wp", "sdhi0"), + /* SDHI2 */ +- PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "pfc-sh73a0", ++ PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "e6050000.pfc", + "sdhi2_data4", "sdhi2"), +- PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "pfc-sh73a0", ++ PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "e6050000.pfc", + "sdhi2_ctrl", "sdhi2"), + }; + +@@ -75,7 +75,6 @@ static void __init kzm_init(void) + { + sh73a0_add_standard_devices_dt(); + pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map)); +- sh73a0_pinmux_init(); + + /* enable SD */ + gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0387-ARM-shmobile-armadillo-reference-Move-pinctrl-mappin.patch b/patches.renesas/0387-ARM-shmobile-armadillo-reference-Move-pinctrl-mappin.patch new file mode 100644 index 00000000000..5011df5e0d0 --- /dev/null +++ b/patches.renesas/0387-ARM-shmobile-armadillo-reference-Move-pinctrl-mappin.patch @@ -0,0 +1,74 @@ +From c0159f812437f5eec1f4743ca954c58a12a928b0 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 9 May 2013 17:41:59 +0200 +Subject: ARM: shmobile: armadillo-reference: Move pinctrl mappings to device + tree + +Replace the pinctrl mappings in board code by device tree mappings. +For devices that are still instantiated from board code reference the +mappings as the default pin controller state to apply them at boot time. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 5d244563da5326d66ca839b06dbc6f632d2f24df) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts | 10 ++++++++++ + arch/arm/mach-shmobile/board-armadillo800eva-reference.c | 9 --------- + 2 files changed, 10 insertions(+), 9 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +index 09ea22c2..4a7ae32d 100644 +--- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts ++++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +@@ -43,3 +43,13 @@ + interrupts = <2 0>; /* IRQ10: hwirq 2 on irqpin1 */ + }; + }; ++ ++&pfc { ++ pinctrl-0 = <&scifa1_pins>; ++ pinctrl-names = "default"; ++ ++ scifa1_pins: scifa1 { ++ renesas,groups = "scifa1_data"; ++ renesas,function = "scifa1"; ++ }; ++}; +diff --git a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c +index f25b6aab..4ddd2999 100644 +--- a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c ++++ b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c +@@ -24,7 +24,6 @@ + #include <linux/kernel.h> + #include <linux/gpio.h> + #include <linux/io.h> +-#include <linux/pinctrl/machine.h> + #include <mach/common.h> + #include <mach/r8a7740.h> + #include <asm/mach/arch.h> +@@ -119,12 +118,6 @@ + * usbhsf_power_ctrl() + */ + +-static const struct pinctrl_map eva_pinctrl_map[] = { +- /* SCIFA1 */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.1", "e6050000.pfc", +- "scifa1_data", "scifa1"), +-}; +- + static void __init eva_clock_init(void) + { + struct clk *system = clk_get(NULL, "system_clk"); +@@ -169,8 +162,6 @@ static void __init eva_init(void) + r8a7740_clock_init(MD_CK0 | MD_CK2); + eva_clock_init(); + +- pinctrl_register_mappings(eva_pinctrl_map, ARRAY_SIZE(eva_pinctrl_map)); +- + r8a7740_meram_workaround(); + + #ifdef CONFIG_CACHE_L2X0 +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0388-ARM-shmobile-armadillo-reference-Add-st1232-pin-mapp.patch b/patches.renesas/0388-ARM-shmobile-armadillo-reference-Add-st1232-pin-mapp.patch new file mode 100644 index 00000000000..e50469cd2b1 --- /dev/null +++ b/patches.renesas/0388-ARM-shmobile-armadillo-reference-Add-st1232-pin-mapp.patch @@ -0,0 +1,42 @@ +From 8c14344f519d8573b70dbe802518fdb97d8301db Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 9 May 2013 17:41:59 +0200 +Subject: ARM: shmobile: armadillo-reference: Add st1232 pin mappings + +Add pin mappings for the st1232 device to the device tree and reference +them as the default state for the device. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit f46a6b0f6a54e80ebf1003134f2e6f4258e53688) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +index 4a7ae32d..a6c6606d 100644 +--- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts ++++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +@@ -41,6 +41,8 @@ + reg = <0x55>; + interrupt-parent = <&irqpin1>; + interrupts = <2 0>; /* IRQ10: hwirq 2 on irqpin1 */ ++ pinctrl-0 = <&st1232_pins>; ++ pinctrl-names = "default"; + }; + }; + +@@ -52,4 +54,9 @@ + renesas,groups = "scifa1_data"; + renesas,function = "scifa1"; + }; ++ ++ st1232_pins: st1232 { ++ renesas,groups = "intc_irq10"; ++ renesas,function = "intc"; ++ }; + }; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0389-ARM-shmobile-armadillo-reference-Move-st1232-reset-G.patch b/patches.renesas/0389-ARM-shmobile-armadillo-reference-Move-st1232-reset-G.patch new file mode 100644 index 00000000000..692b2622ec7 --- /dev/null +++ b/patches.renesas/0389-ARM-shmobile-armadillo-reference-Move-st1232-reset-G.patch @@ -0,0 +1,65 @@ +From 54aabbfc65940d556b0392a0eec2e2d52196a513 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 9 May 2013 17:41:59 +0200 +Subject: ARM: shmobile: armadillo-reference: Move st1232 reset GPIO to DT + +Reference the st1232 reset GPIO from the device tree and remove it from +board code. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 14d0a2b79623e4773e5fc78950dadac213a30400) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts | 2 ++ + arch/arm/mach-shmobile/board-armadillo800eva-reference.c | 7 ------- + 2 files changed, 2 insertions(+), 7 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +index a6c6606d..8ec4cd17 100644 +--- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts ++++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +@@ -10,6 +10,7 @@ + + /dts-v1/; + /include/ "r8a7740.dtsi" ++#include <dt-bindings/gpio/gpio.h> + + / { + model = "armadillo 800 eva reference"; +@@ -43,6 +44,7 @@ + interrupts = <2 0>; /* IRQ10: hwirq 2 on irqpin1 */ + pinctrl-0 = <&st1232_pins>; + pinctrl-names = "default"; ++ gpios = <&pfc 166 GPIO_ACTIVE_LOW>; + }; + }; + +diff --git a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c +index 4ddd2999..002d8d3d 100644 +--- a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c ++++ b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c +@@ -158,7 +158,6 @@ clock_error: + */ + static void __init eva_init(void) + { +- + r8a7740_clock_init(MD_CK0 | MD_CK2); + eva_clock_init(); + +@@ -171,12 +170,6 @@ static void __init eva_init(void) + + r8a7740_add_standard_devices_dt(); + +- /* +- * Touchscreen +- * TODO: Move reset GPIO over to .dts when we can reference it +- */ +- gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */ +- + r8a7740_pm_init(); + } + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0390-ARM-shmobile-armadillo-reference-Add-LED1-LED4-to-th.patch b/patches.renesas/0390-ARM-shmobile-armadillo-reference-Add-LED1-LED4-to-th.patch new file mode 100644 index 00000000000..1a449b2b095 --- /dev/null +++ b/patches.renesas/0390-ARM-shmobile-armadillo-reference-Add-LED1-LED4-to-th.patch @@ -0,0 +1,44 @@ +From 8313d7175a1ee2cb2adf6f2002c975bb4a2b0494 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 10 May 2013 00:23:04 +0200 +Subject: ARM: shmobile: armadillo-reference: Add LED1-LED4 to the device tree + +LED1 to LED4 are GPIO LEDs. Add corresponding DT nodes. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 0a4f788961f196baa3e8ffd840a2c5931434854e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +index 8ec4cd17..366f7298 100644 +--- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts ++++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +@@ -34,6 +34,21 @@ + regulator-boot-on; + }; + ++ leds { ++ compatible = "gpio-leds"; ++ led1 { ++ gpios = <&pfc 102 GPIO_ACTIVE_HIGH>; ++ }; ++ led2 { ++ gpios = <&pfc 111 GPIO_ACTIVE_HIGH>; ++ }; ++ led3 { ++ gpios = <&pfc 110 GPIO_ACTIVE_HIGH>; ++ }; ++ led4 { ++ gpios = <&pfc 177 GPIO_ACTIVE_HIGH>; ++ }; ++ }; + }; + + &i2c0 { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0391-ARM-shmobile-marzen-reference-Move-pinctrl-mappings-.patch b/patches.renesas/0391-ARM-shmobile-marzen-reference-Move-pinctrl-mappings-.patch new file mode 100644 index 00000000000..80c12bd6657 --- /dev/null +++ b/patches.renesas/0391-ARM-shmobile-marzen-reference-Move-pinctrl-mappings-.patch @@ -0,0 +1,117 @@ +From 69a3b0876a79563f51d026ca653f15eea8c91489 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 9 May 2013 17:41:59 +0200 +Subject: ARM: shmobile: marzen-reference: Move pinctrl mappings to device tree + +Replace the pinctrl mappings in board code by device tree mappings. +For devices that are still instantiated from board code reference the +mappings as the default pin controller state to apply them at boot time. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit c4a003f6075c8e3e4e5a0d8958518882d779ef74) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7779-marzen-reference.dts | 35 +++++++++++++++++++++++++ + arch/arm/mach-shmobile/board-marzen-reference.c | 27 ------------------- + 2 files changed, 35 insertions(+), 27 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts +index 72be4c87..6d202478 100644 +--- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts ++++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts +@@ -37,6 +37,9 @@ + lan0@18000000 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0x18000000 0x100>; ++ pinctrl-0 = <&lan0_pins>; ++ pinctrl-names = "default"; ++ + phy-mode = "mii"; + interrupt-parent = <&gic>; + interrupts = <0 28 0x4>; +@@ -45,3 +48,35 @@ + vdd33a-supply = <&fixedregulator3v3>; + }; + }; ++ ++&pfc { ++ pinctrl-0 = <&scif2_pins &scif4_pins &sdhi0_pins>; ++ pinctrl-names = "default"; ++ ++ lan0_pins: lan0 { ++ intc { ++ renesas,groups = "intc_irq1_b"; ++ renesas,function = "intc"; ++ }; ++ lbsc { ++ renesas,groups = "lbsc_ex_cs0"; ++ renesas,function = "lbsc"; ++ }; ++ }; ++ ++ scif2_pins: scif2 { ++ renesas,groups = "scif2_data_c"; ++ renesas,function = "scif2"; ++ }; ++ ++ scif4_pins: scif4 { ++ renesas,groups = "scif4_data"; ++ renesas,function = "scif4"; ++ }; ++ ++ sdhi0_pins: sdhi0 { ++ renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", ++ "sdhi0_wp"; ++ renesas,function = "sdhi0"; ++ }; ++}; +diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c +index 94804f3c..3d1c439b 100644 +--- a/arch/arm/mach-shmobile/board-marzen-reference.c ++++ b/arch/arm/mach-shmobile/board-marzen-reference.c +@@ -19,41 +19,14 @@ + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +-#include <linux/pinctrl/machine.h> + #include <mach/r8a7779.h> + #include <mach/common.h> + #include <mach/irqs.h> + #include <asm/irq.h> + #include <asm/mach/arch.h> + +-static const struct pinctrl_map marzen_pinctrl_map[] = { +- /* SCIF2 (CN18: DEBUG0) */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "fffc0000.pfc", +- "scif2_data_c", "scif2"), +- /* SCIF4 (CN19: DEBUG1) */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "fffc0000.pfc", +- "scif4_data", "scif4"), +- /* SDHI0 */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "fffc0000.pfc", +- "sdhi0_data4", "sdhi0"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "fffc0000.pfc", +- "sdhi0_ctrl", "sdhi0"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "fffc0000.pfc", +- "sdhi0_cd", "sdhi0"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "fffc0000.pfc", +- "sdhi0_wp", "sdhi0"), +- /* SMSC */ +- PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "fffc0000.pfc", +- "intc_irq1_b", "intc"), +- PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "fffc0000.pfc", +- "lbsc_ex_cs0", "lbsc"), +-}; +- + static void __init marzen_init(void) + { +- pinctrl_register_mappings(marzen_pinctrl_map, +- ARRAY_SIZE(marzen_pinctrl_map)); +- + r8a7779_add_standard_devices_dt(); + } + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0392-ARM-shmobile-marzen-reference-Add-LED2-LED4-to-the-d.patch b/patches.renesas/0392-ARM-shmobile-marzen-reference-Add-LED2-LED4-to-the-d.patch new file mode 100644 index 00000000000..d5482d2dfe5 --- /dev/null +++ b/patches.renesas/0392-ARM-shmobile-marzen-reference-Add-LED2-LED4-to-the-d.patch @@ -0,0 +1,50 @@ +From 527945dc6673dc8cef67a0cdf3ec9c4976280a29 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 10 May 2013 00:23:04 +0200 +Subject: ARM: shmobile: marzen-reference: Add LED2-LED4 to the device tree + +LED2 to LED4 are GPIO LEDs. Add corresponding DT nodes. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 80d1126fae07fd4bd6a93ad626ad14e753f9d892) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7779-marzen-reference.dts | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts +index 6d202478..b64705be 100644 +--- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts ++++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts +@@ -11,6 +11,7 @@ + + /dts-v1/; + /include/ "r8a7779.dtsi" ++#include <dt-bindings/gpio/gpio.h> + + / { + model = "marzen"; +@@ -47,6 +48,19 @@ + vddvario-supply = <&fixedregulator3v3>; + vdd33a-supply = <&fixedregulator3v3>; + }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ led2 { ++ gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; ++ }; ++ led3 { ++ gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; ++ }; ++ led4 { ++ gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; ++ }; ++ }; + }; + + &pfc { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0393-ARM-shmobile-kzm9g-reference-Move-pinctrl-mappings-t.patch b/patches.renesas/0393-ARM-shmobile-kzm9g-reference-Move-pinctrl-mappings-t.patch new file mode 100644 index 00000000000..0d2378c8924 --- /dev/null +++ b/patches.renesas/0393-ARM-shmobile-kzm9g-reference-Move-pinctrl-mappings-t.patch @@ -0,0 +1,156 @@ +From e1e53987e8f32e8b1289e950be498934e1b99a88 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 9 May 2013 17:41:59 +0200 +Subject: ARM: shmobile: kzm9g-reference: Move pinctrl mappings to device tree + +Replace the pinctrl mappings in board code by device tree mappings. +For devices that are still instantiated from board code reference the +mappings as the default pin controller state to apply them at boot time. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit ec028600f4a4bd1b272465caea3e2ff066e40377) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/sh73a0-kzm9g-reference.dts | 51 ++++++++++++++++++++++++++ + arch/arm/mach-shmobile/board-kzm9g-reference.c | 40 -------------------- + 2 files changed, 51 insertions(+), 40 deletions(-) + +diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +index b6f759e8..11ae9ade 100644 +--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts ++++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +@@ -145,19 +145,70 @@ + }; + }; + ++&i2c3 { ++ pinctrl-0 = <&i2c3_pins>; ++ pinctrl-names = "default"; ++}; ++ + &mmcif { ++ pinctrl-0 = <&mmcif_pins>; ++ pinctrl-names = "default"; ++ + bus-width = <8>; + vmmc-supply = <®_1p8v>; + status = "okay"; + }; + ++&pfc { ++ pinctrl-0 = <&scifa4_pins>; ++ pinctrl-names = "default"; ++ ++ i2c3_pins: i2c3 { ++ renesas,groups = "i2c3_1"; ++ renesas,function = "i2c3"; ++ }; ++ ++ mmcif_pins: mmcif { ++ mux { ++ renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0"; ++ renesas,function = "mmc0"; ++ }; ++ cfg { ++ renesas,groups = "mmc0_data8_0"; ++ renesas,pins = "PORT279"; ++ bias-pull-up; ++ }; ++ }; ++ ++ scifa4_pins: scifa4 { ++ renesas,groups = "scifa4_data", "scifa4_ctrl"; ++ renesas,function = "scifa4"; ++ }; ++ ++ sdhi0_pins: sdhi0 { ++ renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp"; ++ renesas,function = "sdhi0"; ++ }; ++ ++ sdhi2_pins: sdhi2 { ++ renesas,groups = "sdhi2_data4", "sdhi2_ctrl"; ++ renesas,function = "sdhi2"; ++ }; ++}; ++ + &sdhi0 { ++ pinctrl-0 = <&sdhi0_pins>; ++ pinctrl-names = "default"; ++ + vmmc-supply = <®_3p3v>; + bus-width = <4>; + status = "okay"; + }; + + &sdhi2 { ++ pinctrl-0 = <&sdhi2_pins>; ++ pinctrl-names = "default"; ++ + vmmc-supply = <®_3p3v>; + bus-width = <4>; + broken-cd; +diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c +index d7bbd29a..6a9f6a3a 100644 +--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c ++++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c +@@ -26,55 +26,15 @@ + #include <linux/irq.h> + #include <linux/input.h> + #include <linux/of_platform.h> +-#include <linux/pinctrl/machine.h> +-#include <linux/pinctrl/pinconf-generic.h> + #include <mach/sh73a0.h> + #include <mach/common.h> + #include <asm/hardware/cache-l2x0.h> + #include <asm/mach-types.h> + #include <asm/mach/arch.h> + +-static unsigned long pin_pullup_conf[] = { +- PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0), +-}; +- +-static const struct pinctrl_map kzm_pinctrl_map[] = { +- PIN_MAP_MUX_GROUP_DEFAULT("e6826000.i2c", "e6050000.pfc", +- "i2c3_1", "i2c3"), +- /* MMCIF */ +- PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "e6050000.pfc", +- "mmc0_data8_0", "mmc0"), +- PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "e6050000.pfc", +- "mmc0_ctrl_0", "mmc0"), +- PIN_MAP_CONFIGS_PIN_DEFAULT("e6bd0000.mmcif", "e6050000.pfc", +- "PORT279", pin_pullup_conf), +- PIN_MAP_CONFIGS_GROUP_DEFAULT("e6bd0000.mmcif", "e6050000.pfc", +- "mmc0_data8_0", pin_pullup_conf), +- /* SCIFA4 */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "e6050000.pfc", +- "scifa4_data", "scifa4"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "e6050000.pfc", +- "scifa4_ctrl", "scifa4"), +- /* SDHI0 */ +- PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "e6050000.pfc", +- "sdhi0_data4", "sdhi0"), +- PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "e6050000.pfc", +- "sdhi0_ctrl", "sdhi0"), +- PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "e6050000.pfc", +- "sdhi0_cd", "sdhi0"), +- PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "e6050000.pfc", +- "sdhi0_wp", "sdhi0"), +- /* SDHI2 */ +- PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "e6050000.pfc", +- "sdhi2_data4", "sdhi2"), +- PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "e6050000.pfc", +- "sdhi2_ctrl", "sdhi2"), +-}; +- + static void __init kzm_init(void) + { + sh73a0_add_standard_devices_dt(); +- pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map)); + + /* enable SD */ + gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0394-ARM-shmobile-kzm9g-reference-Move-SDHI-regulators-to.patch b/patches.renesas/0394-ARM-shmobile-kzm9g-reference-Move-SDHI-regulators-to.patch new file mode 100644 index 00000000000..5e94d20c147 --- /dev/null +++ b/patches.renesas/0394-ARM-shmobile-kzm9g-reference-Move-SDHI-regulators-to.patch @@ -0,0 +1,100 @@ +From aa354ccaba22f862b9d293817bd308f96463332d Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 9 May 2013 17:41:59 +0200 +Subject: ARM: shmobile: kzm9g-reference: Move SDHI regulators to DT + +Create two GPIO-controlled fixed-voltage regulators in the +kzm9g-reference DT and remove manual configuration of the corresponding +GPIOs from board code. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit f8f77ce940b84c17378db432a05186476bd8dd04) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/sh73a0-kzm9g-reference.dts | 23 +++++++++++++++++++++-- + arch/arm/mach-shmobile/board-kzm9g-reference.c | 6 ------ + 2 files changed, 21 insertions(+), 8 deletions(-) + +diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +index 11ae9ade..d2b2c9f5 100644 +--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts ++++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +@@ -13,6 +13,7 @@ + + /dts-v1/; + /include/ "sh73a0.dtsi" ++#include <dt-bindings/gpio/gpio.h> + + / { + model = "KZM-A9-GT"; +@@ -58,6 +59,24 @@ + regulator-boot-on; + }; + ++ vmmc_sdhi0: regulator@2 { ++ compatible = "regulator-fixed"; ++ regulator-name = "SDHI0 Vcc"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&pfc 15 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ vmmc_sdhi2: regulator@3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "SDHI2 Vcc"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&pfc 14 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ + lan9220@10000000 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0x10000000 0x100>; +@@ -200,7 +219,7 @@ + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + +- vmmc-supply = <®_3p3v>; ++ vmmc-supply = <&vmmc_sdhi0>; + bus-width = <4>; + status = "okay"; + }; +@@ -209,7 +228,7 @@ + pinctrl-0 = <&sdhi2_pins>; + pinctrl-names = "default"; + +- vmmc-supply = <®_3p3v>; ++ vmmc-supply = <&vmmc_sdhi2>; + bus-width = <4>; + broken-cd; + status = "okay"; +diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c +index 6a9f6a3a..a66a808d 100644 +--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c ++++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c +@@ -21,7 +21,6 @@ + */ + + #include <linux/delay.h> +-#include <linux/gpio.h> + #include <linux/io.h> + #include <linux/irq.h> + #include <linux/input.h> +@@ -36,11 +35,6 @@ static void __init kzm_init(void) + { + sh73a0_add_standard_devices_dt(); + +- /* enable SD */ +- gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */ +- +- gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */ +- + #ifdef CONFIG_CACHE_L2X0 + /* Early BRESP enable, Shared attribute override enable, 64K*8way */ + l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0395-ARM-shmobile-kzm9g-reference-Add-LED1-LED4-to-the-de.patch b/patches.renesas/0395-ARM-shmobile-kzm9g-reference-Add-LED1-LED4-to-the-de.patch new file mode 100644 index 00000000000..55ab8647316 --- /dev/null +++ b/patches.renesas/0395-ARM-shmobile-kzm9g-reference-Add-LED1-LED4-to-the-de.patch @@ -0,0 +1,45 @@ +From 825dd228ed6e5692ed0ba8001107ef7e2752569e Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 10 May 2013 00:23:04 +0200 +Subject: ARM: shmobile: kzm9g-reference: Add LED1-LED4 to the device tree + +LED1 to LED4 are GPIO LEDs. Add corresponding DT nodes. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 1469273960de45275f33276c7254456edcba9da2) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/sh73a0-kzm9g-reference.dts | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +index d2b2c9f5..b99e890d 100644 +--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts ++++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +@@ -89,6 +89,22 @@ + vddvario-supply = <®_1p8v>; + vdd33a-supply = <®_3p3v>; + }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ led1 { ++ gpios = <&pfc 20 GPIO_ACTIVE_LOW>; ++ }; ++ led2 { ++ gpios = <&pfc 21 GPIO_ACTIVE_LOW>; ++ }; ++ led3 { ++ gpios = <&pfc 22 GPIO_ACTIVE_LOW>; ++ }; ++ led4 { ++ gpios = <&pfc 23 GPIO_ACTIVE_LOW>; ++ }; ++ }; + }; + + &i2c0 { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0396-ARM-shmobile-Only-build-clocks-when-COMMON_CLK-n.patch b/patches.renesas/0396-ARM-shmobile-Only-build-clocks-when-COMMON_CLK-n.patch new file mode 100644 index 00000000000..202de79a28b --- /dev/null +++ b/patches.renesas/0396-ARM-shmobile-Only-build-clocks-when-COMMON_CLK-n.patch @@ -0,0 +1,67 @@ +From 4c63a361723a55126c0e06542e20aed37a2850fe Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Thu, 18 Jul 2013 05:30:59 +0900 +Subject: ARM: shmobile: Only build clocks when COMMON_CLK=n + +Move shared clock.c file and per-SoC clock-xxx.c files +to only build when CONFIG_COMMON_CLK != y. + +The regular ARCH_SHMOBILE case with legacy SH clock framework +will build just as before with this patch applied, however +the case when COMMON_CLK=y will exclude all the clock files. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit a360feb9e9e6cc36d61e683c03dc13974663298b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/Makefile | 31 ++++++++++++++++++++++--------- + 1 file changed, 22 insertions(+), 9 deletions(-) + +diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile +index 397bb360..28dc9ab3 100644 +--- a/arch/arm/mach-shmobile/Makefile ++++ b/arch/arm/mach-shmobile/Makefile +@@ -3,17 +3,30 @@ + # + + # Common objects +-obj-y := timer.o console.o clock.o ++obj-y := timer.o console.o + + # CPU objects +-obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o +-obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o +-obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o clock-r8a73a4.o +-obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o +-obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o clock-r8a7778.o +-obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o +-obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o clock-r8a7790.o +-obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o ++obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o intc-sh7372.o ++obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o intc-sh73a0.o ++obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o ++obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o intc-r8a7740.o ++obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o ++obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o intc-r8a7779.o ++obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o ++obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o ++ ++# Clock objects ++ifndef CONFIG_COMMON_CLK ++obj-y += clock.o ++obj-$(CONFIG_ARCH_SH7372) += clock-sh7372.o ++obj-$(CONFIG_ARCH_SH73A0) += clock-sh73a0.o ++obj-$(CONFIG_ARCH_R8A73A4) += clock-r8a73a4.o ++obj-$(CONFIG_ARCH_R8A7740) += clock-r8a7740.o ++obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o ++obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o ++obj-$(CONFIG_ARCH_R8A7790) += clock-r8a7790.o ++obj-$(CONFIG_ARCH_EMEV2) += clock-emev2.o ++endif + + # SMP objects + smp-y := platsmp.o headsmp.o +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0397-ARM-shmobile-Introduce-ARCH_SHMOBILE_MULTI.patch b/patches.renesas/0397-ARM-shmobile-Introduce-ARCH_SHMOBILE_MULTI.patch new file mode 100644 index 00000000000..9f183422f02 --- /dev/null +++ b/patches.renesas/0397-ARM-shmobile-Introduce-ARCH_SHMOBILE_MULTI.patch @@ -0,0 +1,78 @@ +From c22d03e14635ecd4200062fa4fbd777754eb46db Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Thu, 18 Jul 2013 05:31:09 +0900 +Subject: ARM: shmobile: Introduce ARCH_SHMOBILE_MULTI + +Add ARCH_SHMOBILE_MULTI to mach-shmobile that can be used +to enable ARCH_MULTIPLATFORM on selected SoCs and boards. + +The headers stay under arch/arm/mach-shmobile/include/mach/ +for now, they can and will be migrated independently over time. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit efacfce5f8a523457e9419a25d52fe39db00b26a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/Makefile | 1 + + arch/arm/mach-shmobile/Kconfig | 21 +++++++++++++++++++++ + arch/arm/mach-shmobile/Makefile | 2 ++ + 3 files changed, 24 insertions(+) + +diff --git a/arch/arm/Makefile b/arch/arm/Makefile +index 1ba358ba..f56df13d 100644 +--- a/arch/arm/Makefile ++++ b/arch/arm/Makefile +@@ -181,6 +181,7 @@ machine-$(CONFIG_ARCH_EXYNOS) += exynos + machine-$(CONFIG_ARCH_SA1100) += sa1100 + machine-$(CONFIG_ARCH_SHARK) += shark + machine-$(CONFIG_ARCH_SHMOBILE) += shmobile ++machine-$(CONFIG_ARCH_SHMOBILE_MULTI) += shmobile + machine-$(CONFIG_ARCH_TEGRA) += tegra + machine-$(CONFIG_ARCH_U300) += u300 + machine-$(CONFIG_ARCH_U8500) += ux500 +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index 5ae27f21..b6ba366a 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -1,3 +1,24 @@ ++config ARCH_SHMOBILE_MULTI ++ bool "SH-Mobile Series" if ARCH_MULTI_V7 ++ depends on MMU ++ select CPU_V7 ++ select GENERIC_CLOCKEVENTS ++ select HAVE_ARM_SCU if SMP ++ select HAVE_ARM_TWD if LOCAL_TIMERS ++ select HAVE_SMP ++ select ARM_GIC ++ select MIGHT_HAVE_CACHE_L2X0 ++ select NO_IOPORT ++ select PINCTRL ++ select ARCH_REQUIRE_GPIOLIB ++ select CLKDEV_LOOKUP ++ ++if ARCH_SHMOBILE_MULTI ++ ++comment "SH-Mobile System Type" ++ ++endif ++ + if ARCH_SHMOBILE + + comment "SH-Mobile System Type" +diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile +index 28dc9ab3..8bda014c 100644 +--- a/arch/arm/mach-shmobile/Makefile ++++ b/arch/arm/mach-shmobile/Makefile +@@ -2,6 +2,8 @@ + # Makefile for the linux kernel. + # + ++ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/mach-shmobile/include ++ + # Common objects + obj-y := timer.o console.o + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0398-ARM-shmobile-Add-EMEV2-and-KZM9D-to-ARCH_SHMOBILE_MU.patch b/patches.renesas/0398-ARM-shmobile-Add-EMEV2-and-KZM9D-to-ARCH_SHMOBILE_MU.patch new file mode 100644 index 00000000000..4d505529b57 --- /dev/null +++ b/patches.renesas/0398-ARM-shmobile-Add-EMEV2-and-KZM9D-to-ARCH_SHMOBILE_MU.patch @@ -0,0 +1,91 @@ +From 9077cc954932805e7e9dbba6c91f7a261b42896b Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Thu, 18 Jul 2013 05:31:18 +0900 +Subject: ARM: shmobile: Add EMEV2 and KZM9D to ARCH_SHMOBILE_MULTI + +Enable build of EMEV2 and KZM9D DT Reference in +case of ARCH_MULTIPLATFORM and ARCH_SHMOBILE_MULTI. + +IS_ENABLED() is leaves the clock-emev2.c file out +in case of COMMON_CLK=y. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit cbc60e7c04f3c1390144d4a881f0a7b98b49da98) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/Makefile | 1 + + arch/arm/mach-shmobile/Kconfig | 15 +++++++++++++++ + arch/arm/mach-shmobile/board-kzm9d-reference.c | 3 ++- + arch/arm/mach-shmobile/setup-emev2.c | 3 ++- + 4 files changed, 20 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index 7c9fddc7..1d38ff07 100644 +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -172,6 +172,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ + r8a73a4-ape6evm.dtb \ + r8a73a4-ape6evm-reference.dtb \ + sh7372-mackerel.dtb ++dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d-reference.dtb + dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \ + socfpga_vt.dtb + dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \ +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index b6ba366a..e7c399c1 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -17,6 +17,21 @@ if ARCH_SHMOBILE_MULTI + + comment "SH-Mobile System Type" + ++config ARCH_EMEV2 ++ bool "Emma Mobile EV2" ++ ++comment "SH-Mobile Board Type" ++ ++config MACH_KZM9D_REFERENCE ++ bool "KZM9D board - Reference Device Tree Implementation" ++ depends on ARCH_EMEV2 ++ select REGULATOR_FIXED_VOLTAGE if REGULATOR ++ ---help--- ++ Use reference implementation of KZM9D board support ++ which makes a greater use of device tree at the expense ++ of not supporting a number of devices. ++ ++ This is intended to aid developers + endif + + if ARCH_SHMOBILE +diff --git a/arch/arm/mach-shmobile/board-kzm9d-reference.c b/arch/arm/mach-shmobile/board-kzm9d-reference.c +index a7b28b24..8f8bb2fa 100644 +--- a/arch/arm/mach-shmobile/board-kzm9d-reference.c ++++ b/arch/arm/mach-shmobile/board-kzm9d-reference.c +@@ -26,7 +26,8 @@ + + static void __init kzm9d_add_standard_devices(void) + { +- emev2_clock_init(); ++ if (!IS_ENABLED(CONFIG_COMMON_CLK)) ++ emev2_clock_init(); + + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + } +diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c +index 19980be7..1553af8e 100644 +--- a/arch/arm/mach-shmobile/setup-emev2.c ++++ b/arch/arm/mach-shmobile/setup-emev2.c +@@ -175,7 +175,8 @@ static struct resource pmu_resources[] = { + + void __init emev2_add_standard_devices(void) + { +- emev2_clock_init(); ++ if (!IS_ENABLED(CONFIG_COMMON_CLK)) ++ emev2_clock_init(); + + emev2_register_uart(0); + emev2_register_uart(1); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0399-ARM-shmobile-Allow-ARCH_SHMOBILE_MULTI-timer-configu.patch b/patches.renesas/0399-ARM-shmobile-Allow-ARCH_SHMOBILE_MULTI-timer-configu.patch new file mode 100644 index 00000000000..ba778c74e51 --- /dev/null +++ b/patches.renesas/0399-ARM-shmobile-Allow-ARCH_SHMOBILE_MULTI-timer-configu.patch @@ -0,0 +1,61 @@ +From 85724d89ea3373bff63887efcfb17f94b95a1e28 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Thu, 18 Jul 2013 05:31:27 +0900 +Subject: ARM: shmobile: Allow ARCH_SHMOBILE_MULTI timer configuration + +Move the timer configuration bits to allow use in +case of ARCH_SHMOBILE or ARCH_SHMOBILE_MULTI. + +The timers all make use of the regular driver model +so they are safe to enable for ARCH_MULTIPLATFORM. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit fd071b669ee2405e986636e389a3d1b6776e50a0) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/Kconfig | 16 +++++++++++----- + 1 file changed, 11 insertions(+), 5 deletions(-) + +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index e7c399c1..af946061 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -32,6 +32,8 @@ config MACH_KZM9D_REFERENCE + of not supporting a number of devices. + + This is intended to aid developers ++ ++comment "SH-Mobile System Configuration" + endif + + if ARCH_SHMOBILE +@@ -257,6 +259,15 @@ config CPU_HAS_INTEVT + bool + default y + ++config SH_CLK_CPG ++ bool ++ ++source "drivers/sh/Kconfig" ++ ++endif ++ ++if ARCH_SHMOBILE || ARCH_SHMOBILE_MULTI ++ + menu "Timer and clock configuration" + + config SHMOBILE_TIMER_HZ +@@ -291,9 +302,4 @@ config EM_TIMER_STI + + endmenu + +-config SH_CLK_CPG +- bool +- +-source "drivers/sh/Kconfig" +- + endif +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0400-ARM-shmobile-lager-reference-Add-LED6-LED8-to-the-de.patch b/patches.renesas/0400-ARM-shmobile-lager-reference-Add-LED6-LED8-to-the-de.patch new file mode 100644 index 00000000000..13bf48421e9 --- /dev/null +++ b/patches.renesas/0400-ARM-shmobile-lager-reference-Add-LED6-LED8-to-the-de.patch @@ -0,0 +1,48 @@ +From 6600086d728fa905fe3ade165cfb977be5178f80 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 16 Jul 2013 11:45:56 +0200 +Subject: ARM: shmobile: lager-reference: Add LED6-LED8 to the device tree + +LED6 to LED8 are GPIO LEDs. Add corresponding DT nodes. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 466f302e076236a4796079681ca2a2f34a5792a3) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7790-lager-reference.dts | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a7790-lager-reference.dts b/arch/arm/boot/dts/r8a7790-lager-reference.dts +index fa5b81bd..5ee71cf5 100644 +--- a/arch/arm/boot/dts/r8a7790-lager-reference.dts ++++ b/arch/arm/boot/dts/r8a7790-lager-reference.dts +@@ -10,6 +10,7 @@ + + /dts-v1/; + /include/ "r8a7790.dtsi" ++#include <dt-bindings/gpio/gpio.h> + + / { + model = "Lager"; +@@ -28,4 +29,17 @@ + #address-cells = <1>; + #size-cells = <1>; + }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ led6 { ++ gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; ++ }; ++ led7 { ++ gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; ++ }; ++ led8 { ++ gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; ++ }; ++ }; + }; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0401-ARCH-ARM-shmobile-Remove-kota2-board-support.patch b/patches.renesas/0401-ARCH-ARM-shmobile-Remove-kota2-board-support.patch new file mode 100644 index 00000000000..796952aeb55 --- /dev/null +++ b/patches.renesas/0401-ARCH-ARM-shmobile-Remove-kota2-board-support.patch @@ -0,0 +1,751 @@ +From 8d25a0766302eb96ce9a4f25d1cb67ceb068d867 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Mon, 22 Jul 2013 10:23:09 +0900 +Subject: ARCH: ARM: shmobile: Remove kota2 board support + +Remove support for the sh73a0 based kota2 board. + +The sh73a0 SoC is continued to be supported using +the kzm9g board. + +Acked-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 5fa6d27612635f4b3e6c19d763c0a65275933898) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/configs/kota2_defconfig | 121 -------- + arch/arm/mach-shmobile/Kconfig | 6 - + arch/arm/mach-shmobile/Makefile | 1 - + arch/arm/mach-shmobile/Makefile.boot | 1 - + arch/arm/mach-shmobile/board-kota2.c | 550 ----------------------------------- + 5 files changed, 679 deletions(-) + delete mode 100644 arch/arm/configs/kota2_defconfig + delete mode 100644 arch/arm/mach-shmobile/board-kota2.c + +diff --git a/arch/arm/configs/kota2_defconfig b/arch/arm/configs/kota2_defconfig +deleted file mode 100644 +index 57ad3d47..00000000 +--- a/arch/arm/configs/kota2_defconfig ++++ /dev/null +@@ -1,121 +0,0 @@ +-# CONFIG_ARM_PATCH_PHYS_VIRT is not set +-CONFIG_EXPERIMENTAL=y +-CONFIG_SYSVIPC=y +-CONFIG_IKCONFIG=y +-CONFIG_IKCONFIG_PROC=y +-CONFIG_LOG_BUF_SHIFT=16 +-CONFIG_CGROUPS=y +-CONFIG_CPUSETS=y +-CONFIG_NAMESPACES=y +-# CONFIG_UTS_NS is not set +-# CONFIG_IPC_NS is not set +-# CONFIG_USER_NS is not set +-# CONFIG_PID_NS is not set +-CONFIG_SYSCTL_SYSCALL=y +-CONFIG_EMBEDDED=y +-CONFIG_SLAB=y +-# CONFIG_BLK_DEV_BSG is not set +-# CONFIG_IOSCHED_DEADLINE is not set +-# CONFIG_IOSCHED_CFQ is not set +-CONFIG_ARCH_SHMOBILE=y +-CONFIG_KEYBOARD_GPIO_POLLED=y +-CONFIG_ARCH_SH73A0=y +-CONFIG_MACH_KOTA2=y +-CONFIG_MEMORY_SIZE=0x1e000000 +-# CONFIG_SH_TIMER_TMU is not set +-# CONFIG_SWP_EMULATE is not set +-CONFIG_CPU_BPREDICT_DISABLE=y +-CONFIG_ARM_ERRATA_460075=y +-CONFIG_ARM_ERRATA_742230=y +-CONFIG_ARM_ERRATA_742231=y +-CONFIG_PL310_ERRATA_588369=y +-CONFIG_ARM_ERRATA_720789=y +-CONFIG_PL310_ERRATA_727915=y +-CONFIG_ARM_ERRATA_743622=y +-CONFIG_ARM_ERRATA_751472=y +-CONFIG_PL310_ERRATA_753970=y +-CONFIG_ARM_ERRATA_754322=y +-CONFIG_PL310_ERRATA_769419=y +-CONFIG_NO_HZ=y +-CONFIG_SMP=y +-CONFIG_AEABI=y +-# CONFIG_OABI_COMPAT is not set +-CONFIG_HIGHMEM=y +-CONFIG_ZBOOT_ROM_TEXT=0x0 +-CONFIG_ZBOOT_ROM_BSS=0x0 +-CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel" +-CONFIG_CMDLINE_FORCE=y +-CONFIG_KEXEC=y +-CONFIG_CPU_IDLE=y +-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +-CONFIG_PM_RUNTIME=y +-CONFIG_NET=y +-CONFIG_PACKET=y +-CONFIG_UNIX=y +-CONFIG_INET=y +-CONFIG_IP_PNP=y +-CONFIG_IP_PNP_DHCP=y +-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +-# CONFIG_INET_XFRM_MODE_TUNNEL is not set +-# CONFIG_INET_XFRM_MODE_BEET is not set +-# CONFIG_INET_LRO is not set +-# CONFIG_INET_DIAG is not set +-# CONFIG_IPV6 is not set +-CONFIG_CFG80211=y +-CONFIG_WIRELESS_EXT_SYSFS=y +-CONFIG_MAC80211=y +-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +-# CONFIG_BLK_DEV is not set +-CONFIG_NETDEVICES=y +-# CONFIG_NET_VENDOR_BROADCOM is not set +-# CONFIG_NET_VENDOR_CHELSIO is not set +-# CONFIG_NET_VENDOR_FARADAY is not set +-# CONFIG_NET_VENDOR_INTEL is not set +-# CONFIG_NET_VENDOR_MARVELL is not set +-# CONFIG_NET_VENDOR_MICREL is not set +-# CONFIG_NET_VENDOR_NATSEMI is not set +-# CONFIG_NET_VENDOR_SEEQ is not set +-CONFIG_SMSC911X=y +-# CONFIG_NET_VENDOR_STMICRO is not set +-CONFIG_B43=y +-CONFIG_B43_PHY_N=y +-CONFIG_B43_DEBUG=y +-CONFIG_INPUT_SPARSEKMAP=y +-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +-CONFIG_INPUT_EVDEV=y +-# CONFIG_KEYBOARD_ATKBD is not set +-CONFIG_KEYBOARD_GPIO=y +-CONFIG_KEYBOARD_SH_KEYSC=y +-# CONFIG_INPUT_MOUSE is not set +-# CONFIG_LEGACY_PTYS is not set +-CONFIG_SERIAL_SH_SCI=y +-CONFIG_SERIAL_SH_SCI_NR_UARTS=9 +-CONFIG_SERIAL_SH_SCI_CONSOLE=y +-# CONFIG_HW_RANDOM is not set +-CONFIG_I2C_SH_MOBILE=y +-# CONFIG_HWMON is not set +-CONFIG_BCMA=y +-CONFIG_BCMA_DEBUG=y +-CONFIG_FB=y +-CONFIG_FB_SH_MOBILE_LCDC=y +-CONFIG_LCD_PLATFORM=y +-CONFIG_FRAMEBUFFER_CONSOLE=y +-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +-# CONFIG_HID_SUPPORT is not set +-# CONFIG_USB_SUPPORT is not set +-CONFIG_MMC=y +-CONFIG_MMC_SDHI=y +-CONFIG_MMC_SH_MMCIF=y +-CONFIG_NEW_LEDS=y +-CONFIG_LEDS_CLASS=y +-CONFIG_LEDS_GPIO=y +-CONFIG_LEDS_RENESAS_TPU=y +-CONFIG_LEDS_TRIGGERS=y +-# CONFIG_DNOTIFY is not set +-CONFIG_TMPFS=y +-# CONFIG_MISC_FILESYSTEMS is not set +-CONFIG_MAGIC_SYSRQ=y +-CONFIG_DEBUG_INFO=y +-CONFIG_DEBUG_INFO_REDUCED=y +-# CONFIG_FTRACE is not set +-CONFIG_DEBUG_USER=y +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index af946061..e14cd2a0 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -140,12 +140,6 @@ config MACH_MACKEREL + select SND_SOC_AK4642 if SND_SIMPLE_CARD + select USE_OF + +-config MACH_KOTA2 +- bool "KOTA2 board" +- depends on ARCH_SH73A0 +- select ARCH_REQUIRE_GPIOLIB +- select REGULATOR_FIXED_VOLTAGE if REGULATOR +- + config MACH_ARMADILLO800EVA + bool "Armadillo-800 EVA board" + depends on ARCH_R8A7740 +diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile +index 8bda014c..de530b2f 100644 +--- a/arch/arm/mach-shmobile/Makefile ++++ b/arch/arm/mach-shmobile/Makefile +@@ -54,7 +54,6 @@ obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o + obj-$(CONFIG_MACH_APE6EVM) += board-ape6evm.o + obj-$(CONFIG_MACH_APE6EVM_REFERENCE) += board-ape6evm-reference.o + obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o +-obj-$(CONFIG_MACH_KOTA2) += board-kota2.o + obj-$(CONFIG_MACH_BOCKW) += board-bockw.o + obj-$(CONFIG_MACH_MARZEN) += board-marzen.o + obj-$(CONFIG_MACH_MARZEN_REFERENCE) += board-marzen-reference.o +diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot +index 761d7b14..0930c683 100644 +--- a/arch/arm/mach-shmobile/Makefile.boot ++++ b/arch/arm/mach-shmobile/Makefile.boot +@@ -6,7 +6,6 @@ loadaddr-$(CONFIG_MACH_APE6EVM_REFERENCE) += 0x40008000 + loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000 + loadaddr-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += 0x40008000 + loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000 +-loadaddr-$(CONFIG_MACH_KOTA2) += 0x41008000 + loadaddr-$(CONFIG_MACH_KZM9D) += 0x40008000 + loadaddr-$(CONFIG_MACH_KZM9D_REFERENCE) += 0x40008000 + loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000 +diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c +deleted file mode 100644 +index 6af20d90..00000000 +--- a/arch/arm/mach-shmobile/board-kota2.c ++++ /dev/null +@@ -1,550 +0,0 @@ +-/* +- * kota2 board support +- * +- * Copyright (C) 2011 Renesas Solutions Corp. +- * Copyright (C) 2011 Magnus Damm +- * Copyright (C) 2010 Takashi Yoshii <yoshii.takashi.zj@renesas.com> +- * Copyright (C) 2009 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; version 2 of the License. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +- */ +- +-#include <linux/kernel.h> +-#include <linux/init.h> +-#include <linux/interrupt.h> +-#include <linux/irq.h> +-#include <linux/pinctrl/machine.h> +-#include <linux/pinctrl/pinconf-generic.h> +-#include <linux/platform_data/pwm-renesas-tpu.h> +-#include <linux/platform_device.h> +-#include <linux/delay.h> +-#include <linux/io.h> +-#include <linux/regulator/fixed.h> +-#include <linux/regulator/machine.h> +-#include <linux/smsc911x.h> +-#include <linux/gpio.h> +-#include <linux/input.h> +-#include <linux/input/sh_keysc.h> +-#include <linux/gpio_keys.h> +-#include <linux/leds.h> +-#include <linux/leds_pwm.h> +-#include <linux/irqchip/arm-gic.h> +-#include <linux/mmc/host.h> +-#include <linux/mmc/sh_mmcif.h> +-#include <linux/mfd/tmio.h> +-#include <linux/mmc/sh_mobile_sdhi.h> +-#include <mach/hardware.h> +-#include <mach/irqs.h> +-#include <mach/sh73a0.h> +-#include <mach/common.h> +-#include <asm/mach-types.h> +-#include <asm/mach/arch.h> +-#include <asm/mach/time.h> +-#include <asm/hardware/cache-l2x0.h> +-#include <asm/traps.h> +- +-/* Dummy supplies, where voltage doesn't matter */ +-static struct regulator_consumer_supply dummy_supplies[] = { +- REGULATOR_SUPPLY("vddvario", "smsc911x"), +- REGULATOR_SUPPLY("vdd33a", "smsc911x"), +-}; +- +-/* SMSC 9220 */ +-static struct resource smsc9220_resources[] = { +- [0] = { +- .start = 0x14000000, /* CS5A */ +- .end = 0x140000ff, /* A1->A7 */ +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = SH73A0_PINT0_IRQ(2), /* PINTA2 */ +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct smsc911x_platform_config smsc9220_platdata = { +- .flags = SMSC911X_USE_32BIT, /* 32-bit SW on 16-bit HW bus */ +- .phy_interface = PHY_INTERFACE_MODE_MII, +- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, +- .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, +-}; +- +-static struct platform_device eth_device = { +- .name = "smsc911x", +- .id = 0, +- .dev = { +- .platform_data = &smsc9220_platdata, +- }, +- .resource = smsc9220_resources, +- .num_resources = ARRAY_SIZE(smsc9220_resources), +-}; +- +-/* KEYSC */ +-static struct sh_keysc_info keysc_platdata = { +- .mode = SH_KEYSC_MODE_6, +- .scan_timing = 3, +- .delay = 100, +- .keycodes = { +- KEY_NUMERIC_STAR, KEY_NUMERIC_0, KEY_NUMERIC_POUND, +- 0, 0, 0, 0, 0, +- KEY_NUMERIC_7, KEY_NUMERIC_8, KEY_NUMERIC_9, +- 0, KEY_DOWN, 0, 0, 0, +- KEY_NUMERIC_4, KEY_NUMERIC_5, KEY_NUMERIC_6, +- KEY_LEFT, KEY_ENTER, KEY_RIGHT, 0, 0, +- KEY_NUMERIC_1, KEY_NUMERIC_2, KEY_NUMERIC_3, +- 0, KEY_UP, 0, 0, 0, +- 0, 0, 0, 0, 0, 0, 0, 0, +- 0, 0, 0, 0, 0, 0, 0, 0, +- 0, 0, 0, 0, 0, 0, 0, 0, +- 0, 0, 0, 0, 0, 0, 0, 0, +- }, +-}; +- +-static struct resource keysc_resources[] = { +- [0] = { +- .name = "KEYSC", +- .start = 0xe61b0000, +- .end = 0xe61b0098 - 1, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = gic_spi(71), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device keysc_device = { +- .name = "sh_keysc", +- .id = 0, +- .num_resources = ARRAY_SIZE(keysc_resources), +- .resource = keysc_resources, +- .dev = { +- .platform_data = &keysc_platdata, +- }, +-}; +- +-/* GPIO KEY */ +-#define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 } +- +-static struct gpio_keys_button gpio_buttons[] = { +- GPIO_KEY(KEY_VOLUMEUP, 56, "+"), /* S2: VOL+ [IRQ9] */ +- GPIO_KEY(KEY_VOLUMEDOWN, 54, "-"), /* S3: VOL- [IRQ10] */ +- GPIO_KEY(KEY_MENU, 27, "Menu"), /* S4: MENU [IRQ30] */ +- GPIO_KEY(KEY_HOMEPAGE, 26, "Home"), /* S5: HOME [IRQ31] */ +- GPIO_KEY(KEY_BACK, 11, "Back"), /* S6: BACK [IRQ0] */ +- GPIO_KEY(KEY_PHONE, 238, "Tel"), /* S7: TEL [IRQ11] */ +- GPIO_KEY(KEY_POWER, 239, "C1"), /* S8: CAM [IRQ13] */ +- GPIO_KEY(KEY_MAIL, 224, "Mail"), /* S9: MAIL [IRQ3] */ +- /* Omitted button "C3?": 223 - S10: CUST [IRQ8] */ +- GPIO_KEY(KEY_CAMERA, 164, "C2"), /* S11: CAM_HALF [IRQ25] */ +- /* Omitted button "?": 152 - S12: CAM_FULL [No IRQ] */ +-}; +- +-static struct gpio_keys_platform_data gpio_key_info = { +- .buttons = gpio_buttons, +- .nbuttons = ARRAY_SIZE(gpio_buttons), +-}; +- +-static struct platform_device gpio_keys_device = { +- .name = "gpio-keys", +- .id = -1, +- .dev = { +- .platform_data = &gpio_key_info, +- }, +-}; +- +-/* GPIO LED */ +-#define GPIO_LED(n, g) { .name = n, .gpio = g } +- +-static struct gpio_led gpio_leds[] = { +- GPIO_LED("G", 20), /* PORT20 [GPO0] -> LED7 -> "G" */ +- GPIO_LED("H", 21), /* PORT21 [GPO1] -> LED8 -> "H" */ +- GPIO_LED("J", 22), /* PORT22 [GPO2] -> LED9 -> "J" */ +-}; +- +-static struct gpio_led_platform_data gpio_leds_info = { +- .leds = gpio_leds, +- .num_leds = ARRAY_SIZE(gpio_leds), +-}; +- +-static struct platform_device gpio_leds_device = { +- .name = "leds-gpio", +- .id = -1, +- .dev = { +- .platform_data = &gpio_leds_info, +- }, +-}; +- +-/* TPU LED */ +-static struct resource tpu1_pwm_resources[] = { +- [0] = { +- .start = 0xe6610000, +- .end = 0xe66100ff, +- .flags = IORESOURCE_MEM, +- }, +-}; +- +-static struct platform_device tpu1_pwm_device = { +- .name = "renesas-tpu-pwm", +- .id = 1, +- .num_resources = ARRAY_SIZE(tpu1_pwm_resources), +- .resource = tpu1_pwm_resources, +-}; +- +-static struct resource tpu2_pwm_resources[] = { +- [0] = { +- .start = 0xe6620000, +- .end = 0xe66200ff, +- .flags = IORESOURCE_MEM, +- }, +-}; +- +-static struct platform_device tpu2_pwm_device = { +- .name = "renesas-tpu-pwm", +- .id = 2, +- .num_resources = ARRAY_SIZE(tpu2_pwm_resources), +- .resource = tpu2_pwm_resources, +-}; +- +-static struct resource tpu3_pwm_resources[] = { +- [0] = { +- .start = 0xe6630000, +- .end = 0xe66300ff, +- .flags = IORESOURCE_MEM, +- }, +-}; +- +-static struct platform_device tpu3_pwm_device = { +- .name = "renesas-tpu-pwm", +- .id = 3, +- .num_resources = ARRAY_SIZE(tpu3_pwm_resources), +- .resource = tpu3_pwm_resources, +-}; +- +-static struct resource tpu4_pwm_resources[] = { +- [0] = { +- .start = 0xe6640000, +- .end = 0xe66400ff, +- .flags = IORESOURCE_MEM, +- }, +-}; +- +-static struct platform_device tpu4_pwm_device = { +- .name = "renesas-tpu-pwm", +- .id = 4, +- .num_resources = ARRAY_SIZE(tpu4_pwm_resources), +- .resource = tpu4_pwm_resources, +-}; +- +-static struct pwm_lookup pwm_lookup[] = { +- PWM_LOOKUP("renesas-tpu-pwm.1", 2, "leds-pwm.0", "V2513"), +- PWM_LOOKUP("renesas-tpu-pwm.2", 1, "leds-pwm.0", "V2515"), +- PWM_LOOKUP("renesas-tpu-pwm.3", 0, "leds-pwm.0", "KEYLED"), +- PWM_LOOKUP("renesas-tpu-pwm.4", 1, "leds-pwm.0", "V2514"), +-}; +- +-static struct led_pwm tpu_pwm_leds[] = { +- { +- .name = "V2513", +- .max_brightness = 1000, +- }, { +- .name = "V2515", +- .max_brightness = 1000, +- }, { +- .name = "KEYLED", +- .max_brightness = 1000, +- }, { +- .name = "V2514", +- .max_brightness = 1000, +- }, +-}; +- +-static struct led_pwm_platform_data leds_pwm_pdata = { +- .num_leds = ARRAY_SIZE(tpu_pwm_leds), +- .leds = tpu_pwm_leds, +-}; +- +-static struct platform_device leds_pwm_device = { +- .name = "leds-pwm", +- .id = 0, +- .dev = { +- .platform_data = &leds_pwm_pdata, +- }, +-}; +- +-/* Fixed 1.8V regulator to be used by MMCIF */ +-static struct regulator_consumer_supply fixed1v8_power_consumers[] = +-{ +- REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"), +- REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"), +-}; +- +-/* MMCIF */ +-static struct resource mmcif_resources[] = { +- [0] = { +- .name = "MMCIF", +- .start = 0xe6bd0000, +- .end = 0xe6bd00ff, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = gic_spi(140), +- .flags = IORESOURCE_IRQ, +- }, +- [2] = { +- .start = gic_spi(141), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct sh_mmcif_plat_data mmcif_info = { +- .ocr = MMC_VDD_165_195, +- .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, +-}; +- +-static struct platform_device mmcif_device = { +- .name = "sh_mmcif", +- .id = 0, +- .dev = { +- .platform_data = &mmcif_info, +- }, +- .num_resources = ARRAY_SIZE(mmcif_resources), +- .resource = mmcif_resources, +-}; +- +-/* Fixed 3.3V regulator to be used by SDHI0 and SDHI1 */ +-static struct regulator_consumer_supply fixed3v3_power_consumers[] = +-{ +- REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"), +- REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"), +- REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"), +- REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"), +-}; +- +-/* SDHI0 */ +-static struct sh_mobile_sdhi_info sdhi0_info = { +- .tmio_caps = MMC_CAP_SD_HIGHSPEED, +- .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT, +-}; +- +-static struct resource sdhi0_resources[] = { +- [0] = { +- .name = "SDHI0", +- .start = 0xee100000, +- .end = 0xee1000ff, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = gic_spi(83), +- .flags = IORESOURCE_IRQ, +- }, +- [2] = { +- .start = gic_spi(84), +- .flags = IORESOURCE_IRQ, +- }, +- [3] = { +- .start = gic_spi(85), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device sdhi0_device = { +- .name = "sh_mobile_sdhi", +- .id = 0, +- .num_resources = ARRAY_SIZE(sdhi0_resources), +- .resource = sdhi0_resources, +- .dev = { +- .platform_data = &sdhi0_info, +- }, +-}; +- +-/* SDHI1 */ +-static struct sh_mobile_sdhi_info sdhi1_info = { +- .tmio_caps = MMC_CAP_NONREMOVABLE | MMC_CAP_SDIO_IRQ, +- .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT, +-}; +- +-static struct resource sdhi1_resources[] = { +- [0] = { +- .name = "SDHI1", +- .start = 0xee120000, +- .end = 0xee1200ff, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = gic_spi(87), +- .flags = IORESOURCE_IRQ, +- }, +- [2] = { +- .start = gic_spi(88), +- .flags = IORESOURCE_IRQ, +- }, +- [3] = { +- .start = gic_spi(89), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device sdhi1_device = { +- .name = "sh_mobile_sdhi", +- .id = 1, +- .num_resources = ARRAY_SIZE(sdhi1_resources), +- .resource = sdhi1_resources, +- .dev = { +- .platform_data = &sdhi1_info, +- }, +-}; +- +-static struct platform_device *kota2_devices[] __initdata = { +- ð_device, +- &keysc_device, +- &gpio_keys_device, +- &gpio_leds_device, +- &tpu1_pwm_device, +- &tpu2_pwm_device, +- &tpu3_pwm_device, +- &tpu4_pwm_device, +- &leds_pwm_device, +- &mmcif_device, +- &sdhi0_device, +- &sdhi1_device, +-}; +- +-static unsigned long pin_pullup_conf[] = { +- PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0), +-}; +- +-static const struct pinctrl_map kota2_pinctrl_map[] = { +- /* KEYSC */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", +- "keysc_in8", "keysc"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", +- "keysc_out04", "keysc"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", +- "keysc_out5", "keysc"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", +- "keysc_out6_0", "keysc"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", +- "keysc_out7_0", "keysc"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", +- "keysc_out8_0", "keysc"), +- PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", +- "keysc_in8", pin_pullup_conf), +- /* MMCIF */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", +- "mmc0_data8_0", "mmc0"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", +- "mmc0_ctrl_0", "mmc0"), +- PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0", +- "PORT279", pin_pullup_conf), +- PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", +- "mmc0_data8_0", pin_pullup_conf), +- /* SCIFA2 (UART2) */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0", +- "scifa2_data_0", "scifa2"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0", +- "scifa2_ctrl_0", "scifa2"), +- /* SCIFA4 (UART1) */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0", +- "scifa4_data", "scifa4"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0", +- "scifa4_ctrl", "scifa4"), +- /* SCIFB (BT) */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0", +- "scifb_data_0", "scifb"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0", +- "scifb_clk_0", "scifb"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0", +- "scifb_ctrl_0", "scifb"), +- /* SDHI0 (microSD) */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", +- "sdhi0_data4", "sdhi0"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", +- "sdhi0_ctrl", "sdhi0"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", +- "sdhi0_cd", "sdhi0"), +- PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", +- "sdhi0_data4", pin_pullup_conf), +- PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", +- "PORT256", pin_pullup_conf), +- PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", +- "PORT251", pin_pullup_conf), +- /* SDHI1 (BCM4330) */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0", +- "sdhi1_data4", "sdhi1"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0", +- "sdhi1_ctrl", "sdhi1"), +- PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0", +- "sdhi1_data4", pin_pullup_conf), +- PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0", +- "PORT263", pin_pullup_conf), +- /* SMSC911X */ +- PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0", +- "bsc_data_0_7", "bsc"), +- PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0", +- "bsc_data_8_15", "bsc"), +- PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0", +- "bsc_cs5_a", "bsc"), +- PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0", +- "bsc_we0", "bsc"), +- /* TPU */ +- PIN_MAP_MUX_GROUP_DEFAULT("renesas-tpu-pwm.1", "pfc-sh73a0", +- "tpu1_to2", "tpu1"), +- PIN_MAP_MUX_GROUP_DEFAULT("renesas-tpu-pwm.2", "pfc-sh73a0", +- "tpu2_to1", "tpu2"), +- PIN_MAP_MUX_GROUP_DEFAULT("renesas-tpu-pwm.3", "pfc-sh73a0", +- "tpu3_to0", "tpu3"), +- PIN_MAP_MUX_GROUP_DEFAULT("renesas-tpu-pwm.4", "pfc-sh73a0", +- "tpu4_to1", "tpu4"), +-}; +- +-static void __init kota2_init(void) +-{ +- regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers, +- ARRAY_SIZE(fixed1v8_power_consumers), 1800000); +- regulator_register_always_on(1, "fixed-3.3V", fixed3v3_power_consumers, +- ARRAY_SIZE(fixed3v3_power_consumers), 3300000); +- regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies)); +- +- pinctrl_register_mappings(kota2_pinctrl_map, +- ARRAY_SIZE(kota2_pinctrl_map)); +- pwm_add_table(pwm_lookup, ARRAY_SIZE(pwm_lookup)); +- +- sh73a0_pinmux_init(); +- +- /* SMSC911X */ +- gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */ +- gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */ +- +- /* MMCIF */ +- gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */ +- +-#ifdef CONFIG_CACHE_L2X0 +- /* Early BRESP enable, Shared attribute override enable, 64K*8way */ +- l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff); +-#endif +- sh73a0_add_standard_devices(); +- platform_add_devices(kota2_devices, ARRAY_SIZE(kota2_devices)); +-} +- +-MACHINE_START(KOTA2, "kota2") +- .smp = smp_ops(sh73a0_smp_ops), +- .map_io = sh73a0_map_io, +- .init_early = sh73a0_add_early_devices, +- .nr_irqs = NR_IRQS_LEGACY, +- .init_irq = sh73a0_init_irq, +- .init_machine = kota2_init, +- .init_late = shmobile_init_late, +- .init_time = sh73a0_earlytimer_init, +-MACHINE_END +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0402-ARCH-ARM-shmobile-Remove-ag5evm-board-support.patch b/patches.renesas/0402-ARCH-ARM-shmobile-Remove-ag5evm-board-support.patch new file mode 100644 index 00000000000..c456a878556 --- /dev/null +++ b/patches.renesas/0402-ARCH-ARM-shmobile-Remove-ag5evm-board-support.patch @@ -0,0 +1,802 @@ +From 7ec795033fa4821e91978394a4d5adbc98f73bc9 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Mon, 22 Jul 2013 10:23:09 +0900 +Subject: ARCH: ARM: shmobile: Remove ag5evm board support + +Remove support for the sh73a0 based ag5evm board. + +The sh73a0 SoC is continued to be supported using +the kzm9g board. + +Acked-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit c0bb9b3027690e10cf8f20a027039db3c7a50d98) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/configs/ag5evm_defconfig | 83 ----- + arch/arm/mach-shmobile/Kconfig | 7 - + arch/arm/mach-shmobile/Makefile | 1 - + arch/arm/mach-shmobile/Makefile.boot | 1 - + arch/arm/mach-shmobile/board-ag5evm.c | 639 ---------------------------------- + 5 files changed, 731 deletions(-) + delete mode 100644 arch/arm/configs/ag5evm_defconfig + delete mode 100644 arch/arm/mach-shmobile/board-ag5evm.c + +diff --git a/arch/arm/configs/ag5evm_defconfig b/arch/arm/configs/ag5evm_defconfig +deleted file mode 100644 +index 212ead35..00000000 +--- a/arch/arm/configs/ag5evm_defconfig ++++ /dev/null +@@ -1,83 +0,0 @@ +-CONFIG_EXPERIMENTAL=y +-CONFIG_SYSVIPC=y +-CONFIG_IKCONFIG=y +-CONFIG_IKCONFIG_PROC=y +-CONFIG_LOG_BUF_SHIFT=16 +-CONFIG_NAMESPACES=y +-# CONFIG_UTS_NS is not set +-# CONFIG_IPC_NS is not set +-# CONFIG_USER_NS is not set +-# CONFIG_PID_NS is not set +-CONFIG_BLK_DEV_INITRD=y +-CONFIG_INITRAMFS_SOURCE="" +-CONFIG_EXPERT=y +-CONFIG_SLAB=y +-# CONFIG_BLK_DEV_BSG is not set +-# CONFIG_IOSCHED_DEADLINE is not set +-# CONFIG_IOSCHED_CFQ is not set +-CONFIG_ARCH_SHMOBILE=y +-CONFIG_ARCH_SH73A0=y +-CONFIG_MACH_AG5EVM=y +-CONFIG_MEMORY_SIZE=0x10000000 +-CONFIG_CPU_BPREDICT_DISABLE=y +-CONFIG_ARM_ERRATA_430973=y +-CONFIG_ARM_ERRATA_458693=y +-CONFIG_NO_HZ=y +-CONFIG_AEABI=y +-# CONFIG_OABI_COMPAT is not set +-CONFIG_HIGHMEM=y +-CONFIG_ZBOOT_ROM_TEXT=0x0 +-CONFIG_ZBOOT_ROM_BSS=0x0 +-CONFIG_CMDLINE="console=tty0 console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel" +-CONFIG_CMDLINE_FORCE=y +-CONFIG_KEXEC=y +-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +-CONFIG_PM=y +-# CONFIG_SUSPEND is not set +-CONFIG_PM_RUNTIME=y +-CONFIG_NET=y +-CONFIG_PACKET=y +-CONFIG_UNIX=y +-CONFIG_INET=y +-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +-# CONFIG_INET_XFRM_MODE_TUNNEL is not set +-# CONFIG_INET_XFRM_MODE_BEET is not set +-# CONFIG_INET_LRO is not set +-# CONFIG_INET_DIAG is not set +-# CONFIG_IPV6 is not set +-# CONFIG_WIRELESS is not set +-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +-# CONFIG_BLK_DEV is not set +-CONFIG_NETDEVICES=y +-CONFIG_NET_ETHERNET=y +-CONFIG_SMSC911X=y +-# CONFIG_NETDEV_1000 is not set +-# CONFIG_NETDEV_10000 is not set +-# CONFIG_WLAN is not set +-CONFIG_INPUT_SPARSEKMAP=y +-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +-CONFIG_INPUT_EVDEV=y +-# CONFIG_INPUT_KEYBOARD is not set +-# CONFIG_INPUT_MOUSE is not set +-CONFIG_SERIAL_SH_SCI=y +-CONFIG_SERIAL_SH_SCI_NR_UARTS=9 +-CONFIG_SERIAL_SH_SCI_CONSOLE=y +-# CONFIG_LEGACY_PTYS is not set +-# CONFIG_HW_RANDOM is not set +-CONFIG_I2C=y +-CONFIG_I2C_SH_MOBILE=y +-# CONFIG_HWMON is not set +-# CONFIG_MFD_SUPPORT is not set +-CONFIG_FB=y +-CONFIG_FB_SH_MOBILE_LCDC=y +-CONFIG_FRAMEBUFFER_CONSOLE=y +-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +-# CONFIG_HID_SUPPORT is not set +-# CONFIG_USB_SUPPORT is not set +-# CONFIG_DNOTIFY is not set +-# CONFIG_INOTIFY_USER is not set +-CONFIG_TMPFS=y +-# CONFIG_MISC_FILESYSTEMS is not set +-CONFIG_MAGIC_SYSRQ=y +-CONFIG_DEBUG_KERNEL=y +-# CONFIG_FTRACE is not set +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index e14cd2a0..6f71c94c 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -109,13 +109,6 @@ config ARCH_EMEV2 + + comment "SH-Mobile Board Type" + +-config MACH_AG5EVM +- bool "AG5EVM board" +- depends on ARCH_SH73A0 +- select ARCH_REQUIRE_GPIOLIB +- select REGULATOR_FIXED_VOLTAGE if REGULATOR +- select SH_LCD_MIPI_DSI +- + config MACH_APE6EVM + bool "APE6EVM board" + depends on ARCH_R8A73A4 +diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile +index de530b2f..91b4958b 100644 +--- a/arch/arm/mach-shmobile/Makefile ++++ b/arch/arm/mach-shmobile/Makefile +@@ -50,7 +50,6 @@ obj-$(CONFIG_ARCH_R8A7779) += pm-r8a7779.o + obj-$(CONFIG_ARCH_SH73A0) += pm-sh73a0.o + + # Board objects +-obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o + obj-$(CONFIG_MACH_APE6EVM) += board-ape6evm.o + obj-$(CONFIG_MACH_APE6EVM_REFERENCE) += board-ape6evm-reference.o + obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o +diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot +index 0930c683..c20435ef 100644 +--- a/arch/arm/mach-shmobile/Makefile.boot ++++ b/arch/arm/mach-shmobile/Makefile.boot +@@ -1,6 +1,5 @@ + # per-board load address for uImage + loadaddr-y := +-loadaddr-$(CONFIG_MACH_AG5EVM) += 0x40008000 + loadaddr-$(CONFIG_MACH_APE6EVM) += 0x40008000 + loadaddr-$(CONFIG_MACH_APE6EVM_REFERENCE) += 0x40008000 + loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000 +diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c +deleted file mode 100644 +index f6d64495..00000000 +--- a/arch/arm/mach-shmobile/board-ag5evm.c ++++ /dev/null +@@ -1,639 +0,0 @@ +-/* +- * arch/arm/mach-shmobile/board-ag5evm.c +- * +- * Copyright (C) 2010 Takashi Yoshii <yoshii.takashi.zj@renesas.com> +- * Copyright (C) 2009 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; version 2 of the License. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +- * +- */ +- +-#include <linux/kernel.h> +-#include <linux/init.h> +-#include <linux/interrupt.h> +-#include <linux/irq.h> +-#include <linux/pinctrl/machine.h> +-#include <linux/pinctrl/pinconf-generic.h> +-#include <linux/platform_device.h> +-#include <linux/delay.h> +-#include <linux/io.h> +-#include <linux/dma-mapping.h> +-#include <linux/regulator/fixed.h> +-#include <linux/regulator/machine.h> +-#include <linux/serial_sci.h> +-#include <linux/smsc911x.h> +-#include <linux/gpio.h> +-#include <linux/videodev2.h> +-#include <linux/input.h> +-#include <linux/input/sh_keysc.h> +-#include <linux/mmc/host.h> +-#include <linux/mmc/sh_mmcif.h> +-#include <linux/mmc/sh_mobile_sdhi.h> +-#include <linux/mfd/tmio.h> +-#include <linux/platform_data/bd6107.h> +-#include <linux/sh_clk.h> +-#include <linux/irqchip/arm-gic.h> +-#include <video/sh_mobile_lcdc.h> +-#include <video/sh_mipi_dsi.h> +-#include <sound/sh_fsi.h> +-#include <mach/hardware.h> +-#include <mach/irqs.h> +-#include <mach/sh73a0.h> +-#include <mach/common.h> +-#include <asm/mach-types.h> +-#include <asm/mach/arch.h> +-#include <asm/hardware/cache-l2x0.h> +-#include <asm/traps.h> +- +-/* Dummy supplies, where voltage doesn't matter */ +-static struct regulator_consumer_supply dummy_supplies[] = { +- REGULATOR_SUPPLY("vddvario", "smsc911x"), +- REGULATOR_SUPPLY("vdd33a", "smsc911x"), +-}; +- +-static struct resource smsc9220_resources[] = { +- [0] = { +- .start = 0x14000000, +- .end = 0x14000000 + SZ_64K - 1, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = SH73A0_PINT0_IRQ(2), /* PINTA2 */ +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct smsc911x_platform_config smsc9220_platdata = { +- .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS, +- .phy_interface = PHY_INTERFACE_MODE_MII, +- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, +- .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, +-}; +- +-static struct platform_device eth_device = { +- .name = "smsc911x", +- .id = 0, +- .dev = { +- .platform_data = &smsc9220_platdata, +- }, +- .resource = smsc9220_resources, +- .num_resources = ARRAY_SIZE(smsc9220_resources), +-}; +- +-static struct sh_keysc_info keysc_platdata = { +- .mode = SH_KEYSC_MODE_6, +- .scan_timing = 3, +- .delay = 100, +- .keycodes = { +- KEY_A, KEY_B, KEY_C, KEY_D, KEY_E, KEY_F, KEY_G, +- KEY_H, KEY_I, KEY_J, KEY_K, KEY_L, KEY_M, KEY_N, +- KEY_O, KEY_P, KEY_Q, KEY_R, KEY_S, KEY_T, KEY_U, +- KEY_V, KEY_W, KEY_X, KEY_Y, KEY_Z, KEY_HOME, KEY_SLEEP, +- KEY_SPACE, KEY_9, KEY_6, KEY_3, KEY_WAKEUP, KEY_RIGHT, \ +- KEY_COFFEE, +- KEY_0, KEY_8, KEY_5, KEY_2, KEY_DOWN, KEY_ENTER, KEY_UP, +- KEY_KPASTERISK, KEY_7, KEY_4, KEY_1, KEY_STOP, KEY_LEFT, \ +- KEY_COMPUTER, +- }, +-}; +- +-static struct resource keysc_resources[] = { +- [0] = { +- .name = "KEYSC", +- .start = 0xe61b0000, +- .end = 0xe61b0098 - 1, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = gic_spi(71), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device keysc_device = { +- .name = "sh_keysc", +- .id = 0, +- .num_resources = ARRAY_SIZE(keysc_resources), +- .resource = keysc_resources, +- .dev = { +- .platform_data = &keysc_platdata, +- }, +-}; +- +-/* FSI A */ +-static struct resource fsi_resources[] = { +- [0] = { +- .name = "FSI", +- .start = 0xEC230000, +- .end = 0xEC230400 - 1, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = gic_spi(146), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device fsi_device = { +- .name = "sh_fsi2", +- .id = -1, +- .num_resources = ARRAY_SIZE(fsi_resources), +- .resource = fsi_resources, +-}; +- +-/* Fixed 1.8V regulator to be used by MMCIF */ +-static struct regulator_consumer_supply fixed1v8_power_consumers[] = +-{ +- REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"), +- REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"), +-}; +- +-static struct resource sh_mmcif_resources[] = { +- [0] = { +- .name = "MMCIF", +- .start = 0xe6bd0000, +- .end = 0xe6bd00ff, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = gic_spi(141), +- .flags = IORESOURCE_IRQ, +- }, +- [2] = { +- .start = gic_spi(140), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct sh_mmcif_plat_data sh_mmcif_platdata = { +- .sup_pclk = 0, +- .ocr = MMC_VDD_165_195, +- .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, +- .slave_id_tx = SHDMA_SLAVE_MMCIF_TX, +- .slave_id_rx = SHDMA_SLAVE_MMCIF_RX, +-}; +- +-static struct platform_device mmc_device = { +- .name = "sh_mmcif", +- .id = 0, +- .dev = { +- .dma_mask = NULL, +- .coherent_dma_mask = 0xffffffff, +- .platform_data = &sh_mmcif_platdata, +- }, +- .num_resources = ARRAY_SIZE(sh_mmcif_resources), +- .resource = sh_mmcif_resources, +-}; +- +-/* IrDA */ +-static struct resource irda_resources[] = { +- [0] = { +- .start = 0xE6D00000, +- .end = 0xE6D01FD4 - 1, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = gic_spi(95), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device irda_device = { +- .name = "sh_irda", +- .id = 0, +- .resource = irda_resources, +- .num_resources = ARRAY_SIZE(irda_resources), +-}; +- +-/* MIPI-DSI */ +-static struct resource mipidsi0_resources[] = { +- [0] = { +- .name = "DSI0", +- .start = 0xfeab0000, +- .end = 0xfeab3fff, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .name = "DSI0", +- .start = 0xfeab4000, +- .end = 0xfeab7fff, +- .flags = IORESOURCE_MEM, +- }, +-}; +- +-static int sh_mipi_set_dot_clock(struct platform_device *pdev, +- void __iomem *base, +- int enable) +-{ +- struct clk *pck, *phy; +- int ret; +- +- pck = clk_get(&pdev->dev, "dsip_clk"); +- if (IS_ERR(pck)) { +- ret = PTR_ERR(pck); +- goto sh_mipi_set_dot_clock_pck_err; +- } +- +- phy = clk_get(&pdev->dev, "dsiphy_clk"); +- if (IS_ERR(phy)) { +- ret = PTR_ERR(phy); +- goto sh_mipi_set_dot_clock_phy_err; +- } +- +- if (enable) { +- clk_set_rate(pck, clk_round_rate(pck, 24000000)); +- clk_set_rate(phy, clk_round_rate(pck, 510000000)); +- clk_enable(pck); +- clk_enable(phy); +- } else { +- clk_disable(pck); +- clk_disable(phy); +- } +- +- ret = 0; +- +- clk_put(phy); +-sh_mipi_set_dot_clock_phy_err: +- clk_put(pck); +-sh_mipi_set_dot_clock_pck_err: +- return ret; +-} +- +-static struct sh_mipi_dsi_info mipidsi0_info = { +- .data_format = MIPI_RGB888, +- .channel = LCDC_CHAN_MAINLCD, +- .lane = 2, +- .vsynw_offset = 20, +- .clksrc = 1, +- .flags = SH_MIPI_DSI_HSABM | +- SH_MIPI_DSI_SYNC_PULSES_MODE | +- SH_MIPI_DSI_HSbyteCLK, +- .set_dot_clock = sh_mipi_set_dot_clock, +-}; +- +-static struct platform_device mipidsi0_device = { +- .name = "sh-mipi-dsi", +- .num_resources = ARRAY_SIZE(mipidsi0_resources), +- .resource = mipidsi0_resources, +- .id = 0, +- .dev = { +- .platform_data = &mipidsi0_info, +- }, +-}; +- +-/* LCDC0 and backlight */ +-static const struct fb_videomode lcdc0_modes[] = { +- { +- .name = "R63302(QHD)", +- .xres = 544, +- .yres = 961, +- .left_margin = 72, +- .right_margin = 600, +- .hsync_len = 16, +- .upper_margin = 8, +- .lower_margin = 8, +- .vsync_len = 2, +- .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT, +- }, +-}; +- +-static struct sh_mobile_lcdc_info lcdc0_info = { +- .clock_source = LCDC_CLK_PERIPHERAL, +- .ch[0] = { +- .chan = LCDC_CHAN_MAINLCD, +- .interface_type = RGB24, +- .clock_divider = 1, +- .flags = LCDC_FLAGS_DWPOL, +- .fourcc = V4L2_PIX_FMT_RGB565, +- .lcd_modes = lcdc0_modes, +- .num_modes = ARRAY_SIZE(lcdc0_modes), +- .panel_cfg = { +- .width = 44, +- .height = 79, +- }, +- .tx_dev = &mipidsi0_device, +- } +-}; +- +-static struct resource lcdc0_resources[] = { +- [0] = { +- .name = "LCDC0", +- .start = 0xfe940000, /* P4-only space */ +- .end = 0xfe943fff, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = intcs_evt2irq(0x580), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device lcdc0_device = { +- .name = "sh_mobile_lcdc_fb", +- .num_resources = ARRAY_SIZE(lcdc0_resources), +- .resource = lcdc0_resources, +- .id = 0, +- .dev = { +- .platform_data = &lcdc0_info, +- .coherent_dma_mask = ~0, +- }, +-}; +- +-static struct bd6107_platform_data backlight_data = { +- .fbdev = &lcdc0_device.dev, +- .reset = 235, +- .def_value = 0, +-}; +- +-static struct i2c_board_info backlight_board_info = { +- I2C_BOARD_INFO("bd6107", 0x6d), +- .platform_data = &backlight_data, +-}; +- +-/* Fixed 2.8V regulators to be used by SDHI0 */ +-static struct regulator_consumer_supply fixed2v8_power_consumers[] = +-{ +- REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"), +- REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"), +-}; +- +-/* SDHI0 */ +-static struct sh_mobile_sdhi_info sdhi0_info = { +- .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, +- .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, +- .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD, +- .tmio_caps = MMC_CAP_SD_HIGHSPEED, +- .tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29, +- .cd_gpio = 251, +-}; +- +-static struct resource sdhi0_resources[] = { +- [0] = { +- .name = "SDHI0", +- .start = 0xee100000, +- .end = 0xee1000ff, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT, +- .start = gic_spi(83), +- .flags = IORESOURCE_IRQ, +- }, +- [2] = { +- .name = SH_MOBILE_SDHI_IRQ_SDCARD, +- .start = gic_spi(84), +- .flags = IORESOURCE_IRQ, +- }, +- [3] = { +- .name = SH_MOBILE_SDHI_IRQ_SDIO, +- .start = gic_spi(85), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device sdhi0_device = { +- .name = "sh_mobile_sdhi", +- .id = 0, +- .num_resources = ARRAY_SIZE(sdhi0_resources), +- .resource = sdhi0_resources, +- .dev = { +- .platform_data = &sdhi0_info, +- }, +-}; +- +-/* Fixed 3.3V regulator to be used by SDHI1 */ +-static struct regulator_consumer_supply cn4_power_consumers[] = +-{ +- REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"), +- REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"), +-}; +- +-static struct regulator_init_data cn4_power_init_data = { +- .constraints = { +- .valid_ops_mask = REGULATOR_CHANGE_STATUS, +- }, +- .num_consumer_supplies = ARRAY_SIZE(cn4_power_consumers), +- .consumer_supplies = cn4_power_consumers, +-}; +- +-static struct fixed_voltage_config cn4_power_info = { +- .supply_name = "CN4 SD/MMC Vdd", +- .microvolts = 3300000, +- .gpio = 114, +- .enable_high = 1, +- .init_data = &cn4_power_init_data, +-}; +- +-static struct platform_device cn4_power = { +- .name = "reg-fixed-voltage", +- .id = 2, +- .dev = { +- .platform_data = &cn4_power_info, +- }, +-}; +- +-static void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state) +-{ +- static int power_gpio = -EINVAL; +- +- if (power_gpio < 0) { +- int ret = gpio_request_one(114, GPIOF_OUT_INIT_LOW, +- "sdhi1_power"); +- if (!ret) +- power_gpio = 114; +- } +- +- /* +- * If requesting the GPIO above failed, it means, that the regulator got +- * probed and grabbed the GPIO, but we don't know, whether the sdhi +- * driver already uses the regulator. If it doesn't, we have to toggle +- * the GPIO ourselves, even though it is now owned by the fixed +- * regulator driver. We have to live with the race in case the driver +- * gets unloaded and the GPIO freed between these two steps. +- */ +- gpio_set_value(114, state); +-} +- +-static struct sh_mobile_sdhi_info sh_sdhi1_info = { +- .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT, +- .tmio_caps = MMC_CAP_NONREMOVABLE | MMC_CAP_SDIO_IRQ, +- .tmio_ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, +- .set_pwr = ag5evm_sdhi1_set_pwr, +-}; +- +-static struct resource sdhi1_resources[] = { +- [0] = { +- .name = "SDHI1", +- .start = 0xee120000, +- .end = 0xee1200ff, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT, +- .start = gic_spi(87), +- .flags = IORESOURCE_IRQ, +- }, +- [2] = { +- .name = SH_MOBILE_SDHI_IRQ_SDCARD, +- .start = gic_spi(88), +- .flags = IORESOURCE_IRQ, +- }, +- [3] = { +- .name = SH_MOBILE_SDHI_IRQ_SDIO, +- .start = gic_spi(89), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device sdhi1_device = { +- .name = "sh_mobile_sdhi", +- .id = 1, +- .dev = { +- .platform_data = &sh_sdhi1_info, +- }, +- .num_resources = ARRAY_SIZE(sdhi1_resources), +- .resource = sdhi1_resources, +-}; +- +-static struct platform_device *ag5evm_devices[] __initdata = { +- &cn4_power, +- ð_device, +- &keysc_device, +- &fsi_device, +- &mmc_device, +- &irda_device, +- &mipidsi0_device, +- &lcdc0_device, +- &sdhi0_device, +- &sdhi1_device, +-}; +- +-static unsigned long pin_pullup_conf[] = { +- PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0), +-}; +- +-static const struct pinctrl_map ag5evm_pinctrl_map[] = { +- /* FSIA */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", +- "fsia_mclk_in", "fsia"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", +- "fsia_sclk_in", "fsia"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", +- "fsia_data_in", "fsia"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", +- "fsia_data_out", "fsia"), +- /* I2C2 & I2C3 */ +- PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.2", "pfc-sh73a0", +- "i2c2_0", "i2c2"), +- PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0", +- "i2c3_0", "i2c3"), +- /* IrDA */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh_irda.0", "pfc-sh73a0", +- "irda_0", "irda"), +- /* KEYSC */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", +- "keysc_in8", "keysc"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", +- "keysc_out04", "keysc"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", +- "keysc_out5", "keysc"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", +- "keysc_out6_0", "keysc"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", +- "keysc_out7_0", "keysc"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", +- "keysc_out8_0", "keysc"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", +- "keysc_out9_2", "keysc"), +- PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", +- "keysc_in8", pin_pullup_conf), +- /* MMCIF */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", +- "mmc0_data8_0", "mmc0"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", +- "mmc0_ctrl_0", "mmc0"), +- PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0", +- "PORT279", pin_pullup_conf), +- PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", +- "mmc0_data8_0", pin_pullup_conf), +- /* SCIFA2 */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0", +- "scifa2_data_0", "scifa2"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0", +- "scifa2_ctrl_0", "scifa2"), +- /* SDHI0 (CN15 [SD I/F]) */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", +- "sdhi0_data4", "sdhi0"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", +- "sdhi0_ctrl", "sdhi0"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", +- "sdhi0_wp", "sdhi0"), +- /* SDHI1 (CN4 [WLAN I/F]) */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0", +- "sdhi1_data4", "sdhi1"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0", +- "sdhi1_ctrl", "sdhi1"), +- PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0", +- "sdhi1_data4", pin_pullup_conf), +- PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0", +- "PORT263", pin_pullup_conf), +-}; +- +-static void __init ag5evm_init(void) +-{ +- regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers, +- ARRAY_SIZE(fixed1v8_power_consumers), 1800000); +- regulator_register_always_on(1, "fixed-2.8V", fixed2v8_power_consumers, +- ARRAY_SIZE(fixed2v8_power_consumers), 3300000); +- regulator_register_fixed(3, dummy_supplies, ARRAY_SIZE(dummy_supplies)); +- +- pinctrl_register_mappings(ag5evm_pinctrl_map, +- ARRAY_SIZE(ag5evm_pinctrl_map)); +- sh73a0_pinmux_init(); +- +- /* enable MMCIF */ +- gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */ +- +- /* enable SMSC911X */ +- gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */ +- gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */ +- +- /* LCD panel */ +- gpio_request_one(217, GPIOF_OUT_INIT_LOW, NULL); /* RESET */ +- mdelay(1); +- gpio_set_value(217, 1); +- mdelay(100); +- +- +-#ifdef CONFIG_CACHE_L2X0 +- /* Shared attribute override enable, 64K*8way */ +- l2x0_init(IOMEM(0xf0100000), 0x00460000, 0xc2000fff); +-#endif +- sh73a0_add_standard_devices(); +- +- i2c_register_board_info(1, &backlight_board_info, 1); +- +- platform_add_devices(ag5evm_devices, ARRAY_SIZE(ag5evm_devices)); +-} +- +-MACHINE_START(AG5EVM, "ag5evm") +- .smp = smp_ops(sh73a0_smp_ops), +- .map_io = sh73a0_map_io, +- .init_early = sh73a0_add_early_devices, +- .nr_irqs = NR_IRQS_LEGACY, +- .init_irq = sh73a0_init_irq, +- .init_machine = ag5evm_init, +- .init_late = shmobile_init_late, +- .init_time = sh73a0_earlytimer_init, +-MACHINE_END +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0403-ARM-shmobile-Remove-sh73a0-use-of-mach-hardware.h.patch b/patches.renesas/0403-ARM-shmobile-Remove-sh73a0-use-of-mach-hardware.h.patch new file mode 100644 index 00000000000..b28eefb005c --- /dev/null +++ b/patches.renesas/0403-ARM-shmobile-Remove-sh73a0-use-of-mach-hardware.h.patch @@ -0,0 +1,30 @@ +From b6f396f53a78937442f146d31ecdfde22fface2b Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Wed, 24 Jul 2013 12:37:24 +0900 +Subject: ARM: shmobile: Remove sh73a0 use of <mach/hardware.h> + +Remove unused <mach/hardware.h> on sh73a0. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit fb0724805eb7369a75a434873f409b42e33ecb85) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-sh73a0.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c +index 516c2391..22de1741 100644 +--- a/arch/arm/mach-shmobile/setup-sh73a0.c ++++ b/arch/arm/mach-shmobile/setup-sh73a0.c +@@ -34,7 +34,6 @@ + #include <linux/platform_data/sh_ipmmu.h> + #include <linux/platform_data/irq-renesas-intc-irqpin.h> + #include <mach/dma-register.h> +-#include <mach/hardware.h> + #include <mach/irqs.h> + #include <mach/sh73a0.h> + #include <mach/common.h> +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0404-ARM-shmobile-Remove-sh7372-use-of-mach-hardware.h.patch b/patches.renesas/0404-ARM-shmobile-Remove-sh7372-use-of-mach-hardware.h.patch new file mode 100644 index 00000000000..0be9c647669 --- /dev/null +++ b/patches.renesas/0404-ARM-shmobile-Remove-sh7372-use-of-mach-hardware.h.patch @@ -0,0 +1,30 @@ +From 4361cbb013d32f22e087baf31c71ef460621cb62 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Wed, 24 Jul 2013 12:37:34 +0900 +Subject: ARM: shmobile: Remove sh7372 use of <mach/hardware.h> + +Remove unused <mach/hardware.h> on sh7372. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 3a8e257f2464870cff1c4257838af2698b9e23fd) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-sh7372.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c +index 13e6fdbd..31187839 100644 +--- a/arch/arm/mach-shmobile/setup-sh7372.c ++++ b/arch/arm/mach-shmobile/setup-sh7372.c +@@ -35,7 +35,6 @@ + #include <linux/dma-mapping.h> + #include <linux/platform_data/sh_ipmmu.h> + #include <mach/dma-register.h> +-#include <mach/hardware.h> + #include <mach/irqs.h> + #include <mach/sh7372.h> + #include <mach/common.h> +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0405-ARM-shmobile-Remove-EMEV2-use-of-mach-hardware.h.patch b/patches.renesas/0405-ARM-shmobile-Remove-EMEV2-use-of-mach-hardware.h.patch new file mode 100644 index 00000000000..49191c17ef3 --- /dev/null +++ b/patches.renesas/0405-ARM-shmobile-Remove-EMEV2-use-of-mach-hardware.h.patch @@ -0,0 +1,30 @@ +From 4c4880ffc785525d4ff2f8b3dfd33c755706c22b Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Wed, 24 Jul 2013 12:37:43 +0900 +Subject: ARM: shmobile: Remove EMEV2 use of <mach/hardware.h> + +Remove unused <mach/hardware.h> on EMEV2. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 7ffdc70e14756135da5949a6c9bc32e2086f3d02) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-emev2.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c +index 1553af8e..3ad531ca 100644 +--- a/arch/arm/mach-shmobile/setup-emev2.c ++++ b/arch/arm/mach-shmobile/setup-emev2.c +@@ -27,7 +27,6 @@ + #include <linux/input.h> + #include <linux/io.h> + #include <linux/irqchip/arm-gic.h> +-#include <mach/hardware.h> + #include <mach/common.h> + #include <mach/emev2.h> + #include <mach/irqs.h> +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0406-ARM-shmobile-Remove-r8a7779-use-of-mach-hardware.h.patch b/patches.renesas/0406-ARM-shmobile-Remove-r8a7779-use-of-mach-hardware.h.patch new file mode 100644 index 00000000000..9ccde662117 --- /dev/null +++ b/patches.renesas/0406-ARM-shmobile-Remove-r8a7779-use-of-mach-hardware.h.patch @@ -0,0 +1,30 @@ +From df76c4a3f2251848c9e9f635015f9f5001753164 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Wed, 24 Jul 2013 12:37:52 +0900 +Subject: ARM: shmobile: Remove r8a7779 use of <mach/hardware.h> + +Remove unused <mach/hardware.h> on r8a7779. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 603e45827b4a565506417fbdc3400eedf8846c3d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a7779.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c +index 66d38261..6ab7405e 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7779.c ++++ b/arch/arm/mach-shmobile/setup-r8a7779.c +@@ -37,7 +37,6 @@ + #include <linux/usb/ehci_pdriver.h> + #include <linux/usb/ohci_pdriver.h> + #include <linux/pm_runtime.h> +-#include <mach/hardware.h> + #include <mach/irqs.h> + #include <mach/r8a7779.h> + #include <mach/common.h> +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0407-ARM-shmobile-Remove-Marzen-use-of-mach-hardware.h.patch b/patches.renesas/0407-ARM-shmobile-Remove-Marzen-use-of-mach-hardware.h.patch new file mode 100644 index 00000000000..37512d4609b --- /dev/null +++ b/patches.renesas/0407-ARM-shmobile-Remove-Marzen-use-of-mach-hardware.h.patch @@ -0,0 +1,30 @@ +From 8bebaab70d21de53914e0b14113fc5ab047d0519 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Wed, 24 Jul 2013 12:38:20 +0900 +Subject: ARM: shmobile: Remove Marzen use of <mach/hardware.h> + +Remove unused <mach/hardware.h> on Marzen. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 85469abe4930fb001c79ac5f0ca17b65c7b2580d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-marzen.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c +index a7d10105..1f57865a 100644 +--- a/arch/arm/mach-shmobile/board-marzen.c ++++ b/arch/arm/mach-shmobile/board-marzen.c +@@ -37,7 +37,6 @@ + #include <linux/mmc/host.h> + #include <linux/mmc/sh_mobile_sdhi.h> + #include <linux/mfd/tmio.h> +-#include <mach/hardware.h> + #include <mach/r8a7779.h> + #include <mach/common.h> + #include <mach/irqs.h> +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0408-ARM-shmobile-Remove-include-mach-hardware.h.patch b/patches.renesas/0408-ARM-shmobile-Remove-include-mach-hardware.h.patch new file mode 100644 index 00000000000..38404858931 --- /dev/null +++ b/patches.renesas/0408-ARM-shmobile-Remove-include-mach-hardware.h.patch @@ -0,0 +1,29 @@ +From 90964f5418e4c5ca5149f5fde43f29aa7af373cb Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Wed, 24 Jul 2013 12:38:29 +0900 +Subject: ARM: shmobile: Remove include <mach/hardware.h> + +Now when no one is using this file, remove <mach/hardware.h>. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 5717bcf3712fc30c8b4b7f714ebbf0bfcb922bb6) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/include/mach/hardware.h | 4 ---- + 1 file changed, 4 deletions(-) + delete mode 100644 arch/arm/mach-shmobile/include/mach/hardware.h + +diff --git a/arch/arm/mach-shmobile/include/mach/hardware.h b/arch/arm/mach-shmobile/include/mach/hardware.h +deleted file mode 100644 +index 99264a5c..00000000 +--- a/arch/arm/mach-shmobile/include/mach/hardware.h ++++ /dev/null +@@ -1,4 +0,0 @@ +-#ifndef __ASM_MACH_HARDWARE_H +-#define __ASM_MACH_HARDWARE_H +- +-#endif /* __ASM_MACH_HARDWARE_H */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0409-ARM-shmobile-r8a73a4-Remove-init_machine-special-cas.patch b/patches.renesas/0409-ARM-shmobile-r8a73a4-Remove-init_machine-special-cas.patch new file mode 100644 index 00000000000..d6a69fe8e30 --- /dev/null +++ b/patches.renesas/0409-ARM-shmobile-r8a73a4-Remove-init_machine-special-cas.patch @@ -0,0 +1,54 @@ +From 28be204d7e76fb1b22a3d7ce1f6412af1363c513 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Wed, 24 Jul 2013 12:53:15 +0900 +Subject: ARM: shmobile: r8a73a4: Remove ->init_machine() special case + +No need to special case r8a73a4 ->init_machine(), +so get rid of undesired cpufreq platform device +from the generic long term r8a73a4 DT support code. + +For short term support on APE6EVM the DT reference +implementation already adds a "cpufreq-cpu0" platform +device so that can be used for development. + +Regarding more long term cpufreq support, perhaps +it makes sense to adjust the cpufreq driver to check +for DT information directly instead of using a +platform device for software configuration and DT +for hardware parameters. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 67fde41ea4251f722b4466597c479fb42fccac2c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a73a4.c | 6 ------ + 1 file changed, 6 deletions(-) + +diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c +index 630ea4eb..2ee45d52 100644 +--- a/arch/arm/mach-shmobile/setup-r8a73a4.c ++++ b/arch/arm/mach-shmobile/setup-r8a73a4.c +@@ -215,11 +215,6 @@ void __init r8a73a4_init_delay(void) + } + + #ifdef CONFIG_USE_OF +-void __init r8a73a4_add_standard_devices_dt(void) +-{ +- platform_device_register_simple("cpufreq-cpu0", -1, NULL, 0); +- of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +-} + + static const char *r8a73a4_boards_compat_dt[] __initdata = { + "renesas,r8a73a4", +@@ -228,7 +223,6 @@ static const char *r8a73a4_boards_compat_dt[] __initdata = { + + DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)") + .init_early = r8a73a4_init_delay, +- .init_machine = r8a73a4_add_standard_devices_dt, + .init_time = shmobile_timer_init, + .dt_compat = r8a73a4_boards_compat_dt, + MACHINE_END +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0410-ARM-shmobile-Use-pm-rmobile-on-sh7372-and-r8a7740-on.patch b/patches.renesas/0410-ARM-shmobile-Use-pm-rmobile-on-sh7372-and-r8a7740-on.patch new file mode 100644 index 00000000000..da0c60ac9fa --- /dev/null +++ b/patches.renesas/0410-ARM-shmobile-Use-pm-rmobile-on-sh7372-and-r8a7740-on.patch @@ -0,0 +1,39 @@ +From 7933e1448d7db55dda80976636f6373f971ece8d Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Tue, 9 Jul 2013 19:40:01 +0900 +Subject: ARM: shmobile: Use pm-rmobile on sh7372 and r8a7740 only + +The functions in pm-rmobile.c are only used on sh7372 and +r8a7740, so adjust the Makefile to only link in that file +in case those SoCs are selected. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 0173a741e19e072ae34fda4a32d004e52c9da8e7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/Makefile | 7 +++---- + 1 file changed, 3 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile +index 91b4958b..2afab454 100644 +--- a/arch/arm/mach-shmobile/Makefile ++++ b/arch/arm/mach-shmobile/Makefile +@@ -43,11 +43,10 @@ obj-$(CONFIG_ARCH_R8A7740) += entry-intc.o + # PM objects + obj-$(CONFIG_SUSPEND) += suspend.o + obj-$(CONFIG_CPU_IDLE) += cpuidle.o +-obj-$(CONFIG_ARCH_SHMOBILE) += pm-rmobile.o +-obj-$(CONFIG_ARCH_SH7372) += pm-sh7372.o sleep-sh7372.o +-obj-$(CONFIG_ARCH_R8A7740) += pm-r8a7740.o +-obj-$(CONFIG_ARCH_R8A7779) += pm-r8a7779.o ++obj-$(CONFIG_ARCH_SH7372) += pm-sh7372.o sleep-sh7372.o pm-rmobile.o + obj-$(CONFIG_ARCH_SH73A0) += pm-sh73a0.o ++obj-$(CONFIG_ARCH_R8A7740) += pm-r8a7740.o pm-rmobile.o ++obj-$(CONFIG_ARCH_R8A7779) += pm-r8a7779.o + + # Board objects + obj-$(CONFIG_MACH_APE6EVM) += board-ape6evm.o +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0411-ARM-shmobile-No-need-to-use-INTC-demux-on-r8a7740.patch b/patches.renesas/0411-ARM-shmobile-No-need-to-use-INTC-demux-on-r8a7740.patch new file mode 100644 index 00000000000..07b18dc38d9 --- /dev/null +++ b/patches.renesas/0411-ARM-shmobile-No-need-to-use-INTC-demux-on-r8a7740.patch @@ -0,0 +1,33 @@ +From e1b43909b5afc8fa97e232e750d336751c3d22f9 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Tue, 9 Jul 2013 19:40:08 +0900 +Subject: ARM: shmobile: No need to use INTC demux on r8a7740 + +Now when the r8a7740 code has been converted to make use of +GIC instead of INTC for root interrupt controller it is +possible to exclude the low level INTC demux function +shmobile_handle_irq_intc from linking. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d76c626d31d5632aa0ee02fc3e99087070cd556e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/Makefile | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile +index 2afab454..ec38a16b 100644 +--- a/arch/arm/mach-shmobile/Makefile ++++ b/arch/arm/mach-shmobile/Makefile +@@ -38,7 +38,6 @@ smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o + + # IRQ objects + obj-$(CONFIG_ARCH_SH7372) += entry-intc.o +-obj-$(CONFIG_ARCH_R8A7740) += entry-intc.o + + # PM objects + obj-$(CONFIG_SUSPEND) += suspend.o +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0412-ARM-shmobile-ape6evm-add-MMCIF-support.patch b/patches.renesas/0412-ARM-shmobile-ape6evm-add-MMCIF-support.patch new file mode 100644 index 00000000000..9950f093735 --- /dev/null +++ b/patches.renesas/0412-ARM-shmobile-ape6evm-add-MMCIF-support.patch @@ -0,0 +1,84 @@ +From 04d1e7771f90d3688b9a6bca2cac7a277aa92658 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Wed, 10 Jul 2013 10:13:08 +0200 +Subject: ARM: shmobile: ape6evm: add MMCIF support + +Add MMCIF support to the APE6EVM board in PIO mode only. Power supply is +fixed for now, eventually support for the tps80032 regulator, also +supplying both VDD and VccQ to the MMCIF slot should be added to APE6EVM. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Acked-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 8711613252ed931037f9e9f8646935519dd8f362) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-ape6evm.c | 31 +++++++++++++++++++++++++++++++ + 1 file changed, 31 insertions(+) + +diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c +index af6dd39d..8c7529cc 100644 +--- a/arch/arm/mach-shmobile/board-ape6evm.c ++++ b/arch/arm/mach-shmobile/board-ape6evm.c +@@ -21,6 +21,8 @@ + #include <linux/gpio.h> + #include <linux/interrupt.h> + #include <linux/kernel.h> ++#include <linux/mmc/host.h> ++#include <linux/mmc/sh_mmcif.h> + #include <linux/pinctrl/machine.h> + #include <linux/platform_device.h> + #include <linux/regulator/fixed.h> +@@ -54,6 +56,25 @@ static const struct smsc911x_platform_config lan9220_data = { + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, + }; + ++/* ++ * On APE6EVM power is supplied to MMCIF by a tps80032 regulator. For now we ++ * model a VDD supply to MMCIF, using a fixed 3.3V regulator. ++ */ ++static struct regulator_consumer_supply fixed3v3_power_consumers[] = ++{ ++ REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"), ++}; ++ ++/* MMCIF */ ++static struct sh_mmcif_plat_data mmcif0_pdata = { ++ .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, ++}; ++ ++static struct resource mmcif0_resources[] = { ++ DEFINE_RES_MEM_NAMED(0xee200000, 0x100, "MMCIF0"), ++ DEFINE_RES_IRQ(gic_spi(169)), ++}; ++ + static const struct pinctrl_map ape6evm_pinctrl_map[] = { + /* SCIFA0 console */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a73a4", +@@ -61,6 +82,11 @@ static const struct pinctrl_map ape6evm_pinctrl_map[] = { + /* SMSC */ + PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a73a4", + "irqc_irq40", "irqc"), ++ /* MMCIF0 */ ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a73a4", ++ "mmc0_data8", "mmc0"), ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a73a4", ++ "mmc0_ctrl", "mmc0"), + }; + + static void __init ape6evm_add_standard_devices(void) +@@ -93,6 +119,11 @@ static void __init ape6evm_add_standard_devices(void) + platform_device_register_resndata(&platform_bus, "smsc911x", -1, + lan9220_res, ARRAY_SIZE(lan9220_res), + &lan9220_data, sizeof(lan9220_data)); ++ regulator_register_always_on(1, "fixed-3.3V", fixed3v3_power_consumers, ++ ARRAY_SIZE(fixed3v3_power_consumers), 3300000); ++ platform_device_register_resndata(&platform_bus, "sh_mmcif", 0, ++ mmcif0_resources, ARRAY_SIZE(mmcif0_resources), ++ &mmcif0_pdata, sizeof(mmcif0_pdata)); + } + + static const char *ape6evm_boards_compat_dt[] __initdata = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0413-ARM-shmobile-ape6evm-add-SDHI-interfaces.patch b/patches.renesas/0413-ARM-shmobile-ape6evm-add-SDHI-interfaces.patch new file mode 100644 index 00000000000..05355e87c08 --- /dev/null +++ b/patches.renesas/0413-ARM-shmobile-ape6evm-add-SDHI-interfaces.patch @@ -0,0 +1,113 @@ +From c0764ee7be5c4be0c14135da6a720dc066ea74e6 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Mon, 8 Jul 2013 17:54:42 +0200 +Subject: ARM: shmobile: ape6evm: add SDHI interfaces + +Add support for SDHI0 and SDHI1 on APE6EVM in PIO mode only. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit f79d68da510bf1b95beff4d556b78d06801f11dc) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-ape6evm.c | 50 +++++++++++++++++++++++++++++++++- + 1 file changed, 49 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c +index 8c7529cc..ccf8b042 100644 +--- a/arch/arm/mach-shmobile/board-ape6evm.c ++++ b/arch/arm/mach-shmobile/board-ape6evm.c +@@ -21,8 +21,10 @@ + #include <linux/gpio.h> + #include <linux/interrupt.h> + #include <linux/kernel.h> ++#include <linux/mfd/tmio.h> + #include <linux/mmc/host.h> + #include <linux/mmc/sh_mmcif.h> ++#include <linux/mmc/sh_mobile_sdhi.h> + #include <linux/pinctrl/machine.h> + #include <linux/platform_device.h> + #include <linux/regulator/fixed.h> +@@ -58,11 +60,16 @@ static const struct smsc911x_platform_config lan9220_data = { + + /* + * On APE6EVM power is supplied to MMCIF by a tps80032 regulator. For now we +- * model a VDD supply to MMCIF, using a fixed 3.3V regulator. ++ * model a VDD supply to MMCIF, using a fixed 3.3V regulator. Also use the ++ * static power supply for SDHI0 and SDHI1, whereas SDHI0's VccQ is also ++ * supplied by the same tps80032 regulator and thus can also be adjusted ++ * dynamically. + */ + static struct regulator_consumer_supply fixed3v3_power_consumers[] = + { + REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"), ++ REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"), ++ REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"), + }; + + /* MMCIF */ +@@ -75,6 +82,29 @@ static struct resource mmcif0_resources[] = { + DEFINE_RES_IRQ(gic_spi(169)), + }; + ++/* SDHI0 */ ++static struct sh_mobile_sdhi_info sdhi0_pdata = { ++ .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE, ++ .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ, ++}; ++ ++static struct resource sdhi0_resources[] = { ++ DEFINE_RES_MEM_NAMED(0xee100000, 0x100, "SDHI0"), ++ DEFINE_RES_IRQ(gic_spi(165)), ++}; ++ ++/* SDHI1 */ ++static struct sh_mobile_sdhi_info sdhi1_pdata = { ++ .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE, ++ .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | ++ MMC_CAP_NEEDS_POLL, ++}; ++ ++static struct resource sdhi1_resources[] = { ++ DEFINE_RES_MEM_NAMED(0xee120000, 0x100, "SDHI1"), ++ DEFINE_RES_IRQ(gic_spi(166)), ++}; ++ + static const struct pinctrl_map ape6evm_pinctrl_map[] = { + /* SCIFA0 console */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a73a4", +@@ -87,6 +117,18 @@ static const struct pinctrl_map ape6evm_pinctrl_map[] = { + "mmc0_data8", "mmc0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a73a4", + "mmc0_ctrl", "mmc0"), ++ /* SDHI0: uSD: no WP */ ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a73a4", ++ "sdhi0_data4", "sdhi0"), ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a73a4", ++ "sdhi0_ctrl", "sdhi0"), ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a73a4", ++ "sdhi0_cd", "sdhi0"), ++ /* SDHI1 */ ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a73a4", ++ "sdhi1_data4", "sdhi1"), ++ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a73a4", ++ "sdhi1_ctrl", "sdhi1"), + }; + + static void __init ape6evm_add_standard_devices(void) +@@ -124,6 +166,12 @@ static void __init ape6evm_add_standard_devices(void) + platform_device_register_resndata(&platform_bus, "sh_mmcif", 0, + mmcif0_resources, ARRAY_SIZE(mmcif0_resources), + &mmcif0_pdata, sizeof(mmcif0_pdata)); ++ platform_device_register_resndata(&platform_bus, "sh_mobile_sdhi", 0, ++ sdhi0_resources, ARRAY_SIZE(sdhi0_resources), ++ &sdhi0_pdata, sizeof(sdhi0_pdata)); ++ platform_device_register_resndata(&platform_bus, "sh_mobile_sdhi", 1, ++ sdhi1_resources, ARRAY_SIZE(sdhi1_resources), ++ &sdhi1_pdata, sizeof(sdhi1_pdata)); + } + + static const char *ape6evm_boards_compat_dt[] __initdata = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0414-ARM-shmobile-No-need-to-use-INTC-header-on-r8a7779.patch b/patches.renesas/0414-ARM-shmobile-No-need-to-use-INTC-header-on-r8a7779.patch new file mode 100644 index 00000000000..dea3e9437f2 --- /dev/null +++ b/patches.renesas/0414-ARM-shmobile-No-need-to-use-INTC-header-on-r8a7779.patch @@ -0,0 +1,45 @@ +From e45d294b314f1a8b4e93cb8c89e01b0c1b7c93ff Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Tue, 9 Jul 2013 19:39:52 +0900 +Subject: ARM: shmobile: No need to use INTC header on r8a7779 + +Now when the intc-irqpin driver is used for external +IRQ pins on r8a7779 it possible to get rid of unused +INTC headers mach/intc.h and linux/sh_intc.h. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d2ef0b9a5192e921490d2f66f4467f26235412bd) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/intc-r8a7779.c | 1 - + arch/arm/mach-shmobile/setup-r8a7779.c | 1 - + 2 files changed, 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c +index b86dc890..5f9e5dc0 100644 +--- a/arch/arm/mach-shmobile/intc-r8a7779.c ++++ b/arch/arm/mach-shmobile/intc-r8a7779.c +@@ -27,7 +27,6 @@ + #include <linux/platform_data/irq-renesas-intc-irqpin.h> + #include <linux/irqchip.h> + #include <mach/common.h> +-#include <mach/intc.h> + #include <mach/irqs.h> + #include <mach/r8a7779.h> + #include <asm/mach-types.h> +diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c +index 6ab7405e..bb8b9678 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7779.c ++++ b/arch/arm/mach-shmobile/setup-r8a7779.c +@@ -29,7 +29,6 @@ + #include <linux/input.h> + #include <linux/io.h> + #include <linux/serial_sci.h> +-#include <linux/sh_intc.h> + #include <linux/sh_timer.h> + #include <linux/dma-mapping.h> + #include <linux/usb/otg.h> +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0415-ARM-shmobile-bockw-add-DT-reference.patch b/patches.renesas/0415-ARM-shmobile-bockw-add-DT-reference.patch new file mode 100644 index 00000000000..aa4976500b2 --- /dev/null +++ b/patches.renesas/0415-ARM-shmobile-bockw-add-DT-reference.patch @@ -0,0 +1,240 @@ +From 844b157cbb1249e29fed8e3aeaf11ad9c79dad10 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 24 Jul 2013 00:36:51 -0700 +Subject: ARM: shmobile: bockw: add DT reference + +This patch adds a sample DT-based Bock-W "reference" implementation. +The use of platform-specific C-code should be avoided +with this configuration as much as possible. + +This patch adds new r8a7778_add_dt_devices() which was same stance +of r8a7790_add_dt_devices() + +Acked-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit cfa66a81621d0e85ac03c0de25adc7edd7f2649e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + arch/arm/mach-shmobile/Makefile.boot +--- + arch/arm/boot/dts/Makefile | 1 + + arch/arm/boot/dts/r8a7778-bockw-reference.dts | 32 +++++++++++++ + arch/arm/mach-shmobile/Kconfig | 14 ++++++ + arch/arm/mach-shmobile/Makefile | 1 + + arch/arm/mach-shmobile/Makefile.boot | 1 + + arch/arm/mach-shmobile/board-bockw-reference.c | 62 ++++++++++++++++++++++++++ + arch/arm/mach-shmobile/include/mach/r8a7778.h | 1 + + arch/arm/mach-shmobile/setup-r8a7778.c | 7 ++- + 8 files changed, 118 insertions(+), 1 deletion(-) + create mode 100644 arch/arm/boot/dts/r8a7778-bockw-reference.dts + create mode 100644 arch/arm/mach-shmobile/board-bockw-reference.c + +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index 1d38ff07..471bed78 100644 +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -163,6 +163,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ + emev2-kzm9d-reference.dtb \ + r8a7740-armadillo800eva.dtb \ + r8a7778-bockw.dtb \ ++ r8a7778-bockw-reference.dtb \ + r8a7740-armadillo800eva-reference.dtb \ + r8a7779-marzen-reference.dtb \ + r8a7790-lager.dtb \ +diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts +new file mode 100644 +index 00000000..f5b8d774 +--- /dev/null ++++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts +@@ -0,0 +1,32 @@ ++/* ++ * Reference Device Tree Source for the Bock-W board ++ * ++ * Copyright (C) 2013 Renesas Solutions Corp. ++ * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> ++ * ++ * based on r8a7779 ++ * ++ * Copyright (C) 2013 Renesas Solutions Corp. ++ * Copyright (C) 2013 Simon Horman ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++/dts-v1/; ++/include/ "r8a7778.dtsi" ++ ++/ { ++ model = "bockw"; ++ compatible = "renesas,bockw-reference", "renesas,r8a7778"; ++ ++ chosen { ++ bootargs = "console=ttySC0,115200 ignore_loglevel"; ++ }; ++ ++ memory { ++ device_type = "memory"; ++ reg = <0x60000000 0x10000000>; ++ }; ++}; +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index 6f71c94c..01308056 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -163,6 +163,20 @@ config MACH_BOCKW + select REGULATOR_FIXED_VOLTAGE if REGULATOR + select USE_OF + ++config MACH_BOCKW_REFERENCE ++ bool "BOCK-W - Reference Device Tree Implementation" ++ depends on ARCH_R8A7778 ++ select ARCH_REQUIRE_GPIOLIB ++ select RENESAS_INTC_IRQPIN ++ select REGULATOR_FIXED_VOLTAGE if REGULATOR ++ select USE_OF ++ ---help--- ++ Use reference implementation of BockW board support ++ which makes use of device tree at the expense ++ of not supporting a number of devices. ++ ++ This is intended to aid developers ++ + config MACH_MARZEN + bool "MARZEN board" + depends on ARCH_R8A7779 +diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile +index ec38a16b..6f44c51b 100644 +--- a/arch/arm/mach-shmobile/Makefile ++++ b/arch/arm/mach-shmobile/Makefile +@@ -52,6 +52,7 @@ obj-$(CONFIG_MACH_APE6EVM) += board-ape6evm.o + obj-$(CONFIG_MACH_APE6EVM_REFERENCE) += board-ape6evm-reference.o + obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o + obj-$(CONFIG_MACH_BOCKW) += board-bockw.o ++obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o + obj-$(CONFIG_MACH_MARZEN) += board-marzen.o + obj-$(CONFIG_MACH_MARZEN_REFERENCE) += board-marzen-reference.o + obj-$(CONFIG_MACH_LAGER) += board-lager.o +diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot +index c20435ef..6a504fe7 100644 +--- a/arch/arm/mach-shmobile/Makefile.boot ++++ b/arch/arm/mach-shmobile/Makefile.boot +@@ -5,6 +5,7 @@ loadaddr-$(CONFIG_MACH_APE6EVM_REFERENCE) += 0x40008000 + loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000 + loadaddr-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += 0x40008000 + loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000 ++loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000 + loadaddr-$(CONFIG_MACH_KZM9D) += 0x40008000 + loadaddr-$(CONFIG_MACH_KZM9D_REFERENCE) += 0x40008000 + loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000 +diff --git a/arch/arm/mach-shmobile/board-bockw-reference.c b/arch/arm/mach-shmobile/board-bockw-reference.c +new file mode 100644 +index 00000000..24db8de7 +--- /dev/null ++++ b/arch/arm/mach-shmobile/board-bockw-reference.c +@@ -0,0 +1,62 @@ ++/* ++ * Bock-W board support ++ * ++ * Copyright (C) 2013 Renesas Solutions Corp. ++ * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ++ */ ++ ++#include <linux/of_platform.h> ++#include <linux/pinctrl/machine.h> ++#include <mach/common.h> ++#include <mach/r8a7778.h> ++#include <asm/mach/arch.h> ++ ++/* ++ * see board-bock.c for checking detail of dip-switch ++ */ ++ ++static const struct pinctrl_map bockw_pinctrl_map[] = { ++ /* SCIF0 */ ++ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778", ++ "scif0_data_a", "scif0"), ++ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778", ++ "scif0_ctrl", "scif0"), ++}; ++ ++static void __init bockw_init(void) ++{ ++ r8a7778_clock_init(); ++ ++ pinctrl_register_mappings(bockw_pinctrl_map, ++ ARRAY_SIZE(bockw_pinctrl_map)); ++ r8a7778_pinmux_init(); ++ r8a7778_add_dt_devices(); ++ ++ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); ++} ++ ++static const char *bockw_boards_compat_dt[] __initdata = { ++ "renesas,bockw-reference", ++ NULL, ++}; ++ ++DT_MACHINE_START(BOCKW_DT, "bockw") ++ .init_early = r8a7778_init_delay, ++ .init_irq = r8a7778_init_irq_dt, ++ .init_machine = bockw_init, ++ .init_time = shmobile_timer_init, ++ .dt_compat = bockw_boards_compat_dt, ++MACHINE_END +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h +index 9b561bf4..8d24f73d 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h +@@ -30,6 +30,7 @@ extern void r8a7778_add_usb_phy_device(struct rcar_phy_platform_data *pdata); + extern void r8a7778_add_i2c_device(int id); + extern void r8a7778_add_hspi_device(int id); + extern void r8a7778_add_mmc_device(struct sh_mmcif_plat_data *info); ++extern void r8a7778_add_dt_devices(void); + + extern void r8a7778_init_late(void); + extern void r8a7778_init_delay(void); +diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c +index a3a2e37b..9d4b6bf4 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7778.c ++++ b/arch/arm/mach-shmobile/setup-r8a7778.c +@@ -333,7 +333,7 @@ void __init r8a7778_add_mmc_device(struct sh_mmcif_plat_data *info) + info, sizeof(*info)); + } + +-void __init r8a7778_add_standard_devices(void) ++void __init r8a7778_add_dt_devices(void) + { + int i; + +@@ -357,6 +357,11 @@ void __init r8a7778_add_standard_devices(void) + r8a7778_register_tmu(1); + } + ++void __init r8a7778_add_standard_devices(void) ++{ ++ r8a7778_add_dt_devices(); ++} ++ + void __init r8a7778_init_late(void) + { + phy = usb_get_phy(USB_PHY_TYPE_USB2); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0416-ARM-shmobile-sh73a0-Rely-on-DT-for-SMP-CPU-info.patch b/patches.renesas/0416-ARM-shmobile-sh73a0-Rely-on-DT-for-SMP-CPU-info.patch new file mode 100644 index 00000000000..202b2a91043 --- /dev/null +++ b/patches.renesas/0416-ARM-shmobile-sh73a0-Rely-on-DT-for-SMP-CPU-info.patch @@ -0,0 +1,59 @@ +From eea1c90ec457f62220be101368a213e24e33e992 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Wed, 24 Jul 2013 16:27:39 +0900 +Subject: ARM: shmobile: sh73a0: Rely on DT for SMP CPU info + +Remove sh73a0 specific ->smp_init_cpus() callback and +instead of relying on shmobile_smp_init_cpus() simply +use DT for CPU core information. + +This assumes that DT_MACHINE_START is used which is +the case when AG5EVM and Kota2 are removed. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 5489cde560f2b13dc9fb34e2d7dfd09a69fa21b1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/smp-sh73a0.c | 11 ++--------- + 1 file changed, 2 insertions(+), 9 deletions(-) + +diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c +index d613113a..1b3dc7c1 100644 +--- a/arch/arm/mach-shmobile/smp-sh73a0.c ++++ b/arch/arm/mach-shmobile/smp-sh73a0.c +@@ -62,6 +62,8 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct + + static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) + { ++ /* setup sh73a0 specific SCU base */ ++ shmobile_scu_base = IOMEM(SH73A0_SCU_BASE); + scu_enable(shmobile_scu_base); + + /* Map the reset vector (in headsmp-scu.S, headsmp.S) */ +@@ -74,14 +76,6 @@ static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) + scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); + } + +-static void __init sh73a0_smp_init_cpus(void) +-{ +- /* setup sh73a0 specific SCU base */ +- shmobile_scu_base = IOMEM(SH73A0_SCU_BASE); +- +- shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base)); +-} +- + #ifdef CONFIG_HOTPLUG_CPU + static int sh73a0_cpu_kill(unsigned int cpu) + { +@@ -120,7 +114,6 @@ static int sh73a0_cpu_disable(unsigned int cpu) + #endif /* CONFIG_HOTPLUG_CPU */ + + struct smp_operations sh73a0_smp_ops __initdata = { +- .smp_init_cpus = sh73a0_smp_init_cpus, + .smp_prepare_cpus = sh73a0_smp_prepare_cpus, + .smp_boot_secondary = sh73a0_boot_secondary, + #ifdef CONFIG_HOTPLUG_CPU +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0417-ARM-shmobile-ape6evm-reference-switch-PFC-to-DT.patch b/patches.renesas/0417-ARM-shmobile-ape6evm-reference-switch-PFC-to-DT.patch new file mode 100644 index 00000000000..8f9c2a9044e --- /dev/null +++ b/patches.renesas/0417-ARM-shmobile-ape6evm-reference-switch-PFC-to-DT.patch @@ -0,0 +1,66 @@ +From b58c1bdb9cd986fbc3f42004e8909652f6a4ba17 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Tue, 23 Jul 2013 13:19:07 +0200 +Subject: ARM: shmobile: ape6evm-reference: switch PFC to DT + +PFC pinctrl configuration can now be performed via DT. Update +ape6evm-reference to use this. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 59b2bc34aaa5d4c85c5c868ea6da42c1d06ff27c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts | 10 ++++++++++ + arch/arm/mach-shmobile/board-ape6evm-reference.c | 9 --------- + 2 files changed, 10 insertions(+), 9 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts +index 6f4506e7..bbd09d8c 100644 +--- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts ++++ b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts +@@ -53,3 +53,13 @@ + >; + voltage-tolerance = <1>; /* 1% */ + }; ++ ++&pfc { ++ pinctrl-0 = <&scifa0_pins>; ++ pinctrl-names = "default"; ++ ++ scifa0_pins: scifa0 { ++ renesas,groups = "scifa0_data"; ++ renesas,function = "scifa0"; ++ }; ++}; +diff --git a/arch/arm/mach-shmobile/board-ape6evm-reference.c b/arch/arm/mach-shmobile/board-ape6evm-reference.c +index 46b41dec..52cc5fa5 100644 +--- a/arch/arm/mach-shmobile/board-ape6evm-reference.c ++++ b/arch/arm/mach-shmobile/board-ape6evm-reference.c +@@ -29,12 +29,6 @@ + #include <asm/mach-types.h> + #include <asm/mach/arch.h> + +-static const struct pinctrl_map ape6evm_pinctrl_map[] = { +- /* SCIFA0 console */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a73a4", +- "scifa0_data", "scifa0"), +-}; +- + static void __init ape6evm_add_standard_devices(void) + { + +@@ -52,9 +46,6 @@ static void __init ape6evm_add_standard_devices(void) + clk_put(parent); + clk_put(mp); + +- pinctrl_register_mappings(ape6evm_pinctrl_map, +- ARRAY_SIZE(ape6evm_pinctrl_map)); +- r8a73a4_pinmux_init(); + r8a73a4_add_dt_devices(); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + platform_device_register_simple("cpufreq-cpu0", -1, NULL, 0); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0418-ARM-shmobile-r8a7779-cleanup-registration-of-usb-phy.patch b/patches.renesas/0418-ARM-shmobile-r8a7779-cleanup-registration-of-usb-phy.patch new file mode 100644 index 00000000000..9be1a3a4116 --- /dev/null +++ b/patches.renesas/0418-ARM-shmobile-r8a7779-cleanup-registration-of-usb-phy.patch @@ -0,0 +1,140 @@ +From 445c61bd440c584ff2996d49611d1c8a74c918fe Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Fri, 26 Jul 2013 00:35:29 -0700 +Subject: ARM: shmobile: r8a7779: cleanup registration of usb phy + +usb phy driver which needs platform data at the time of +registration is used from Marzen only. +Now, ARM/shmobile aims to support DT, +and the C code base board support will be removed +if DT support is completed. +Current driver registration method which needs platform data +and which is not shared complicates codes. +This means legacy C code cleanup after DT supporting +will be more complicated +This patch registers it on board code as cleanup C code + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit fee529df76ffb95ede5020266820f2a0e1f64adc) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-marzen.c | 24 ++++++++++++++++++++++-- + arch/arm/mach-shmobile/include/mach/r8a7779.h | 2 -- + arch/arm/mach-shmobile/setup-r8a7779.c | 17 ----------------- + 3 files changed, 22 insertions(+), 21 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c +index 1f57865a..7474a60f 100644 +--- a/arch/arm/mach-shmobile/board-marzen.c ++++ b/arch/arm/mach-shmobile/board-marzen.c +@@ -29,6 +29,7 @@ + #include <linux/dma-mapping.h> + #include <linux/pinctrl/machine.h> + #include <linux/platform_data/gpio-rcar.h> ++#include <linux/platform_data/usb-rcar-phy.h> + #include <linux/regulator/fixed.h> + #include <linux/regulator/machine.h> + #include <linux/smsc911x.h> +@@ -56,7 +57,26 @@ static struct regulator_consumer_supply dummy_supplies[] = { + REGULATOR_SUPPLY("vdd33a", "smsc911x"), + }; + +-static struct rcar_phy_platform_data usb_phy_platform_data __initdata; ++/* USB PHY */ ++static struct resource usb_phy_resources[] = { ++ [0] = { ++ .start = 0xffe70800, ++ .end = 0xffe70900 - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++}; ++ ++static struct rcar_phy_platform_data usb_phy_platform_data; ++ ++static struct platform_device usb_phy = { ++ .name = "rcar_usb_phy", ++ .id = -1, ++ .dev = { ++ .platform_data = &usb_phy_platform_data, ++ }, ++ .resource = usb_phy_resources, ++ .num_resources = ARRAY_SIZE(usb_phy_resources), ++}; + + /* SMSC LAN89218 */ + static struct resource smsc911x_resources[] = { +@@ -183,6 +203,7 @@ static struct platform_device *marzen_devices[] __initdata = { + &thermal_device, + &hspi_device, + &leds_device, ++ &usb_phy, + }; + + static const struct pinctrl_map marzen_pinctrl_map[] = { +@@ -233,7 +254,6 @@ static void __init marzen_init(void) + r8a7779_init_irq_extpin(1); /* IRQ1 as individual interrupt */ + + r8a7779_add_standard_devices(); +- r8a7779_add_usb_phy_device(&usb_phy_platform_data); + platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices)); + } + +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h +index fc47073c..f10727f7 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h +@@ -4,7 +4,6 @@ + #include <linux/sh_clk.h> + #include <linux/pm_domain.h> + #include <linux/sh_eth.h> +-#include <linux/platform_data/usb-rcar-phy.h> + + struct platform_device; + +@@ -34,7 +33,6 @@ extern void r8a7779_add_early_devices(void); + extern void r8a7779_add_standard_devices(void); + extern void r8a7779_add_standard_devices_dt(void); + extern void r8a7779_add_ether_device(struct sh_eth_plat_data *pdata); +-extern void r8a7779_add_usb_phy_device(struct rcar_phy_platform_data *pdata); + extern void r8a7779_init_late(void); + extern void r8a7779_clock_init(void); + extern void r8a7779_pinmux_init(void); +diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c +index bb8b9678..ddee4aa8 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7779.c ++++ b/arch/arm/mach-shmobile/setup-r8a7779.c +@@ -386,15 +386,6 @@ static struct platform_device sata_device = { + }, + }; + +-/* USB PHY */ +-static struct resource usb_phy_resources[] __initdata = { +- [0] = { +- .start = 0xffe70800, +- .end = 0xffe70900 - 1, +- .flags = IORESOURCE_MEM, +- }, +-}; +- + /* USB */ + static struct usb_phy *phy; + +@@ -600,14 +591,6 @@ void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata) + pdata, sizeof(*pdata)); + } + +-void __init r8a7779_add_usb_phy_device(struct rcar_phy_platform_data *pdata) +-{ +- platform_device_register_resndata(&platform_bus, "rcar_usb_phy", -1, +- usb_phy_resources, +- ARRAY_SIZE(usb_phy_resources), +- pdata, sizeof(*pdata)); +-} +- + /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ + void __init __weak r8a7779_register_twd(void) { } + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0419-ARM-shmobile-marzen-Add-r8a7779-marzen.dtb.patch b/patches.renesas/0419-ARM-shmobile-marzen-Add-r8a7779-marzen.dtb.patch new file mode 100644 index 00000000000..3a4f760b27f --- /dev/null +++ b/patches.renesas/0419-ARM-shmobile-marzen-Add-r8a7779-marzen.dtb.patch @@ -0,0 +1,66 @@ +From 476a1eb2537347af585431878be032e63992d23a Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Fri, 26 Jul 2013 09:36:16 +0900 +Subject: ARM: shmobile: marzen: Add r8a7779-marzen.dtb + +This is in preparation for converting the marzen board to +use DT_MACHINE_START. + +Acked-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d6b51d6b6a33974dfa7b091f61e7a2bedd62f298) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/Makefile | 1 + + arch/arm/boot/dts/r8a7779-marzen.dts | 27 +++++++++++++++++++++++++++ + 2 files changed, 28 insertions(+) + create mode 100644 arch/arm/boot/dts/r8a7779-marzen.dts + +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index 471bed78..fa0ae75f 100644 +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -165,6 +165,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ + r8a7778-bockw.dtb \ + r8a7778-bockw-reference.dtb \ + r8a7740-armadillo800eva-reference.dtb \ ++ r8a7779-marzen.dtb \ + r8a7779-marzen-reference.dtb \ + r8a7790-lager.dtb \ + r8a7790-lager-reference.dtb \ +diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts +new file mode 100644 +index 00000000..f3f7f799 +--- /dev/null ++++ b/arch/arm/boot/dts/r8a7779-marzen.dts +@@ -0,0 +1,27 @@ ++/* ++ * Device Tree Source for the Marzen board ++ * ++ * Copyright (C) 2013 Renesas Solutions Corp. ++ * Copyright (C) 2013 Simon Horman ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++/dts-v1/; ++/include/ "r8a7779.dtsi" ++ ++/ { ++ model = "marzen"; ++ compatible = "renesas,marzen", "renesas,r8a7779"; ++ ++ chosen { ++ bootargs = "console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on"; ++ }; ++ ++ memory { ++ device_type = "memory"; ++ reg = <0x60000000 0x40000000>; ++ }; ++}; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0420-ARM-shmobile-marzen-Switch-to-DT_MACHINE_START.patch b/patches.renesas/0420-ARM-shmobile-marzen-Switch-to-DT_MACHINE_START.patch new file mode 100644 index 00000000000..6a30ad0cb6e --- /dev/null +++ b/patches.renesas/0420-ARM-shmobile-marzen-Switch-to-DT_MACHINE_START.patch @@ -0,0 +1,61 @@ +From d32a6be473e6f924ef1b546ccf612da961757db9 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Wed, 24 Jul 2013 16:30:42 +0900 +Subject: ARM: shmobile: marzen: Switch to DT_MACHINE_START + +Convert the marzen board to use DT_MACHINE_START. With this in +place all mach-shmobile boards use DT_MACHINE_START. Also, this +makes it possible for the r8a7779 SMP code to use DT for CPUs. + +Signed-off-by: Magnus Damm <damm@opensource.se> +[horms+renesas@verge.net.au: Select USE_OF in Kconfig] +[horms+renesas@verge.net.au: Provide dt_compat in DT_MACHINE_START] +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit 7ebbb4ae6f2d6242178d332c67ad49772f9fe88d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/Kconfig | 1 + + arch/arm/mach-shmobile/board-marzen.c | 8 +++++++- + 2 files changed, 8 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index 01308056..1f94c310 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -182,6 +182,7 @@ config MACH_MARZEN + depends on ARCH_R8A7779 + select ARCH_REQUIRE_GPIOLIB + select REGULATOR_FIXED_VOLTAGE if REGULATOR ++ select USE_OF + + config MACH_MARZEN_REFERENCE + bool "MARZEN board - Reference Device Tree Implementation" +diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c +index 7474a60f..2bf86c41 100644 +--- a/arch/arm/mach-shmobile/board-marzen.c ++++ b/arch/arm/mach-shmobile/board-marzen.c +@@ -257,7 +257,12 @@ static void __init marzen_init(void) + platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices)); + } + +-MACHINE_START(MARZEN, "marzen") ++static const char *marzen_boards_compat_dt[] __initdata = { ++ "renesas,marzen", ++ NULL, ++}; ++ ++DT_MACHINE_START(MARZEN, "marzen") + .smp = smp_ops(r8a7779_smp_ops), + .map_io = r8a7779_map_io, + .init_early = r8a7779_add_early_devices, +@@ -265,5 +270,6 @@ MACHINE_START(MARZEN, "marzen") + .init_irq = r8a7779_init_irq, + .init_machine = marzen_init, + .init_late = r8a7779_init_late, ++ .dt_compat = marzen_boards_compat_dt, + .init_time = r8a7779_earlytimer_init, + MACHINE_END +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0421-ARM-shmobile-r8a7779-Rely-on-DT-for-SMP-CPU-info.patch b/patches.renesas/0421-ARM-shmobile-r8a7779-Rely-on-DT-for-SMP-CPU-info.patch new file mode 100644 index 00000000000..408c55cda9a --- /dev/null +++ b/patches.renesas/0421-ARM-shmobile-r8a7779-Rely-on-DT-for-SMP-CPU-info.patch @@ -0,0 +1,59 @@ +From 4d8e6c8f5d6b4de942a2653f1fd3128059bb8be7 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Wed, 24 Jul 2013 17:11:46 +0900 +Subject: ARM: shmobile: r8a7779: Rely on DT for SMP CPU info + +Remove r8a7779 specific ->smp_init_cpus() callback and +instead of relying on shmobile_smp_init_cpus() simply +use DT for CPU core information. + +Based on work for the sh73a0 by Magnus Damm. + +Acked-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit afad20105a58c06407ad9ad85c1cd9ca79d99e00) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/smp-r8a7779.c | 12 +++--------- + 1 file changed, 3 insertions(+), 9 deletions(-) + +diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c +index 526cfaae..bb3adae7 100644 +--- a/arch/arm/mach-shmobile/smp-r8a7779.c ++++ b/arch/arm/mach-shmobile/smp-r8a7779.c +@@ -99,6 +99,9 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct + + static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) + { ++ ++ /* setup r8a7779 specific SCU base */ ++ shmobile_scu_base = IOMEM(R8A7779_SCU_BASE); + scu_enable(shmobile_scu_base); + + /* Map the reset vector (in headsmp-scu.S, headsmp.S) */ +@@ -117,14 +120,6 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) + r8a7779_platform_cpu_kill(3); + } + +-static void __init r8a7779_smp_init_cpus(void) +-{ +- /* setup r8a7779 specific SCU base */ +- shmobile_scu_base = IOMEM(R8A7779_SCU_BASE); +- +- shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base)); +-} +- + #ifdef CONFIG_HOTPLUG_CPU + static int r8a7779_scu_psr_core_disabled(int cpu) + { +@@ -175,7 +170,6 @@ static int r8a7779_cpu_disable(unsigned int cpu) + #endif /* CONFIG_HOTPLUG_CPU */ + + struct smp_operations r8a7779_smp_ops __initdata = { +- .smp_init_cpus = r8a7779_smp_init_cpus, + .smp_prepare_cpus = r8a7779_smp_prepare_cpus, + .smp_boot_secondary = r8a7779_boot_secondary, + #ifdef CONFIG_HOTPLUG_CPU +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0422-ARM-shmobile-marzen-Enable-ARM_APPENDED_DTB-in-defco.patch b/patches.renesas/0422-ARM-shmobile-marzen-Enable-ARM_APPENDED_DTB-in-defco.patch new file mode 100644 index 00000000000..f27bf2e83da --- /dev/null +++ b/patches.renesas/0422-ARM-shmobile-marzen-Enable-ARM_APPENDED_DTB-in-defco.patch @@ -0,0 +1,35 @@ +From 54fcb50948ce582390fc075be072d3715b007b94 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Wed, 24 Jul 2013 17:36:29 +0900 +Subject: ARM: shmobile: marzen: Enable ARM_APPENDED_DTB in defconfig + +"ARM: shmobile: marzen: Switch to DT_MACHINE_START" moves marzen +over to use DT_MACHINE_START, however, the prevalent boot loader +does not support booting with a separate dtb. Thus, it makes +sense to use ARM_APPENDED_DTB by default. + +This is consistent with other shmobile defconfigs. + +Acked-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 8c167a825d56e9946bb54d91017a53efb04ffdaf) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/configs/marzen_defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig +index 494e70ae..82e4040b 100644 +--- a/arch/arm/configs/marzen_defconfig ++++ b/arch/arm/configs/marzen_defconfig +@@ -29,6 +29,7 @@ CONFIG_AEABI=y + CONFIG_HIGHMEM=y + CONFIG_ZBOOT_ROM_TEXT=0x0 + CONFIG_ZBOOT_ROM_BSS=0x0 ++CONFIG_ARM_APPENDED_DTB=y + CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on" + CONFIG_CMDLINE_FORCE=y + CONFIG_KEXEC=y +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0423-ARM-shmobile-r8a7779-Remove-0x-s-from-R8A7779-DTS-fi.patch b/patches.renesas/0423-ARM-shmobile-r8a7779-Remove-0x-s-from-R8A7779-DTS-fi.patch new file mode 100644 index 00000000000..6b8d6860715 --- /dev/null +++ b/patches.renesas/0423-ARM-shmobile-r8a7779-Remove-0x-s-from-R8A7779-DTS-fi.patch @@ -0,0 +1,56 @@ +From 02f012add0d17aa0980470d261b86c97f8604f09 Mon Sep 17 00:00:00 2001 +From: Lee Jones <lee.jones@linaro.org> +Date: Mon, 22 Jul 2013 11:52:38 +0100 +Subject: ARM: shmobile: r8a7779: Remove '0x's from R8A7779 DTS file + +Signed-off-by: Lee Jones <lee.jones@linaro.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 98724b7ec9d34d875fc193660c87d6dd0d17ceb7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7779.dtsi | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi +index e9fbe3d5..23a62447 100644 +--- a/arch/arm/boot/dts/r8a7779.dtsi ++++ b/arch/arm/boot/dts/r8a7779.dtsi +@@ -149,7 +149,7 @@ + sense-bitfield-width = <2>; + }; + +- i2c0: i2c@0xffc70000 { ++ i2c0: i2c@ffc70000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,rmobile-iic"; +@@ -158,7 +158,7 @@ + interrupts = <0 79 0x4>; + }; + +- i2c1: i2c@0xffc71000 { ++ i2c1: i2c@ffc71000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,rmobile-iic"; +@@ -167,7 +167,7 @@ + interrupts = <0 82 0x4>; + }; + +- i2c2: i2c@0xffc72000 { ++ i2c2: i2c@ffc72000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,rmobile-iic"; +@@ -176,7 +176,7 @@ + interrupts = <0 80 0x4>; + }; + +- i2c3: i2c@0xffc73000 { ++ i2c3: i2c@ffc73000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,rmobile-iic"; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0424-ARM-shmobile-r8a7740-add-PMU-information-to-r8a7740..patch b/patches.renesas/0424-ARM-shmobile-r8a7740-add-PMU-information-to-r8a7740..patch new file mode 100644 index 00000000000..778ec308880 --- /dev/null +++ b/patches.renesas/0424-ARM-shmobile-r8a7740-add-PMU-information-to-r8a7740..patch @@ -0,0 +1,35 @@ +From e7f58a38be2f3fffff97c79d45e92542064c1118 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Wed, 24 Jul 2013 12:59:09 +0900 +Subject: ARM: shmobile: r8a7740: add PMU information to r8a7740.dtsi + +Add PMU information to r8a7740.dtsi. With this +included Armadillo800eva DT reference may use the PMU. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit b21ed4eb948e6c59dea30a7102d9736903bff26e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7740.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi +index e18a195b..1d1aeb6d 100644 +--- a/arch/arm/boot/dts/r8a7740.dtsi ++++ b/arch/arm/boot/dts/r8a7740.dtsi +@@ -32,6 +32,11 @@ + <0xc2000000 0x1000>; + }; + ++ pmu { ++ compatible = "arm,cortex-a9-pmu"; ++ interrupts = <0 83 4>; ++ }; ++ + /* irqpin0: IRQ0 - IRQ7 */ + irqpin0: irqpin@e6900000 { + compatible = "renesas,intc-irqpin"; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0425-ARM-shmobile-sh73a0-add-PMU-information-to-sh73a0.dt.patch b/patches.renesas/0425-ARM-shmobile-sh73a0-add-PMU-information-to-sh73a0.dt.patch new file mode 100644 index 00000000000..de1bbfb6619 --- /dev/null +++ b/patches.renesas/0425-ARM-shmobile-sh73a0-add-PMU-information-to-sh73a0.dt.patch @@ -0,0 +1,36 @@ +From e74cceba6b0221267d967c8eab37a5022efbce3d Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Wed, 24 Jul 2013 12:45:03 +0900 +Subject: ARM: shmobile: sh73a0: add PMU information to sh73a0.dtsi + +Add PMU information to sh73a0.dtsi. With this +included KZM9G DT reference may use the PMU. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 4c90483a9c09ac8c18df43901c493e546bdaaabe) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/sh73a0.dtsi | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi +index 86e79feb..ba59a587 100644 +--- a/arch/arm/boot/dts/sh73a0.dtsi ++++ b/arch/arm/boot/dts/sh73a0.dtsi +@@ -38,6 +38,12 @@ + <0xf0000100 0x100>; + }; + ++ pmu { ++ compatible = "arm,cortex-a9-pmu"; ++ interrupts = <0 55 4>, ++ <0 56 4>; ++ }; ++ + irqpin0: irqpin@e6900000 { + compatible = "renesas,intc-irqpin"; + #interrupt-cells = <2>; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0426-ARM-shmobile-emev2-add-PMU-information-to-emev2.dtsi.patch b/patches.renesas/0426-ARM-shmobile-emev2-add-PMU-information-to-emev2.dtsi.patch new file mode 100644 index 00000000000..1638c10c360 --- /dev/null +++ b/patches.renesas/0426-ARM-shmobile-emev2-add-PMU-information-to-emev2.dtsi.patch @@ -0,0 +1,36 @@ +From 49e213828c11c83528f85ba6251bf20f5ce8482c Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Wed, 24 Jul 2013 12:42:40 +0900 +Subject: ARM: shmobile: emev2: add PMU information to emev2.dtsi + +Add PMU information to emev2.dtsi. With this +included KZM9D DT reference may use the PMU. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit c95ebbb298e698836979ab28ce49383402c22d93) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/emev2.dtsi | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi +index 99ad2b2e..9063a443 100644 +--- a/arch/arm/boot/dts/emev2.dtsi ++++ b/arch/arm/boot/dts/emev2.dtsi +@@ -46,6 +46,12 @@ + <0xe0020000 0x0100>; + }; + ++ pmu { ++ compatible = "arm,cortex-a9-pmu"; ++ interrupts = <0 120 4>, ++ <0 121 4>; ++ }; ++ + sti@e0180000 { + compatible = "renesas,em-sti"; + reg = <0xe0180000 0x54>; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0427-ARM-shmobile-Add-lager-defconfig.patch b/patches.renesas/0427-ARM-shmobile-Add-lager-defconfig.patch new file mode 100644 index 00000000000..b7ca7c21235 --- /dev/null +++ b/patches.renesas/0427-ARM-shmobile-Add-lager-defconfig.patch @@ -0,0 +1,147 @@ +From 2ac3c2f45d04e03586f3fe9982aa12753cd0d4fb Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Wed, 31 Jul 2013 15:29:25 +0900 +Subject: ARM: shmobile: Add lager defconfig + +This is intended to be used until multi-arch is able to be +used for the lager board at which time a more generic configuration +will be used in place of this one. + +Acked-by: Magnus Damm <magnus.damm@gmail.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 7c7d3d596c33f5cde22fd5744b6c9bb571637715) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/configs/lager_defconfig | 120 +++++++++++++++++++++++++++++++++++++++ + 1 file changed, 120 insertions(+) + create mode 100644 arch/arm/configs/lager_defconfig + +diff --git a/arch/arm/configs/lager_defconfig b/arch/arm/configs/lager_defconfig +new file mode 100644 +index 00000000..e777ef22 +--- /dev/null ++++ b/arch/arm/configs/lager_defconfig +@@ -0,0 +1,120 @@ ++CONFIG_SYSVIPC=y ++CONFIG_NO_HZ=y ++CONFIG_IKCONFIG=y ++CONFIG_IKCONFIG_PROC=y ++CONFIG_LOG_BUF_SHIFT=16 ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_EMBEDDED=y ++CONFIG_PERF_EVENTS=y ++CONFIG_SLAB=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_IOSCHED_DEADLINE is not set ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_ARCH_SHMOBILE=y ++CONFIG_ARCH_R8A7790=y ++CONFIG_MACH_LAGER=y ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++CONFIG_ARM_ERRATA_430973=y ++CONFIG_ARM_ERRATA_458693=y ++CONFIG_ARM_ERRATA_460075=y ++CONFIG_ARM_ERRATA_743622=y ++CONFIG_ARM_ERRATA_754322=y ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_AEABI=y ++# CONFIG_OABI_COMPAT is not set ++CONFIG_FORCE_MAX_ZONEORDER=13 ++CONFIG_ZBOOT_ROM_TEXT=0x0 ++CONFIG_ZBOOT_ROM_BSS=0x0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_KEXEC=y ++CONFIG_AUTO_ZRELADDR=y ++CONFIG_VFP=y ++CONFIG_NEON=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_PM_RUNTIME=y ++CONFIG_NET=y ++CONFIG_PACKET=y ++CONFIG_UNIX=y ++CONFIG_INET=y ++CONFIG_IP_PNP=y ++CONFIG_IP_PNP_DHCP=y ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++# CONFIG_INET_DIAG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_WIRELESS is not set ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_NETDEVICES=y ++# CONFIG_NET_CORE is not set ++# CONFIG_NET_VENDOR_ARC is not set ++# CONFIG_NET_CADENCE is not set ++# CONFIG_NET_VENDOR_BROADCOM is not set ++# CONFIG_NET_VENDOR_CIRRUS is not set ++# CONFIG_NET_VENDOR_FARADAY is not set ++# CONFIG_NET_VENDOR_INTEL is not set ++# CONFIG_NET_VENDOR_MARVELL is not set ++# CONFIG_NET_VENDOR_MICREL is not set ++# CONFIG_NET_VENDOR_NATSEMI is not set ++CONFIG_SH_ETH=y ++# CONFIG_NET_VENDOR_SEEQ is not set ++# CONFIG_NET_VENDOR_SMSC is not set ++# CONFIG_NET_VENDOR_STMICRO is not set ++# CONFIG_NET_VENDOR_VIA is not set ++# CONFIG_NET_VENDOR_WIZNET is not set ++# CONFIG_WLAN is not set ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_KEYBOARD_ATKBD is not set ++CONFIG_KEYBOARD_GPIO=y ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_SERIO is not set ++# CONFIG_LEGACY_PTYS is not set ++CONFIG_SERIAL_SH_SCI=y ++CONFIG_SERIAL_SH_SCI_NR_UARTS=10 ++CONFIG_SERIAL_SH_SCI_CONSOLE=y ++# CONFIG_HW_RANDOM is not set ++CONFIG_I2C=y ++CONFIG_I2C_GPIO=y ++CONFIG_I2C_SH_MOBILE=y ++CONFIG_GPIO_SH_PFC=y ++CONFIG_GPIOLIB=y ++CONFIG_GPIO_RCAR=y ++# CONFIG_HWMON is not set ++CONFIG_THERMAL=y ++CONFIG_RCAR_THERMAL=y ++CONFIG_REGULATOR=y ++CONFIG_REGULATOR_FIXED_VOLTAGE=y ++# CONFIG_USB_SUPPORT is not set ++CONFIG_MMC=y ++CONFIG_MMC_SDHI=y ++CONFIG_MMC_SH_MMCIF=y ++CONFIG_NEW_LEDS=y ++CONFIG_LEDS_CLASS=y ++CONFIG_LEDS_GPIO=y ++CONFIG_RTC_CLASS=y ++CONFIG_DMADEVICES=y ++CONFIG_SH_DMAE=y ++# CONFIG_IOMMU_SUPPORT is not set ++# CONFIG_DNOTIFY is not set ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_TMPFS=y ++CONFIG_CONFIGFS_FS=y ++# CONFIG_MISC_FILESYSTEMS is not set ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3_ACL=y ++CONFIG_NFS_V4=y ++CONFIG_NFS_V4_1=y ++CONFIG_ROOT_NFS=y ++CONFIG_NLS_CODEPAGE_437=y ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_ENABLE_WARN_DEPRECATED is not set ++# CONFIG_ENABLE_MUST_CHECK is not set ++# CONFIG_ARM_UNWIND is not set ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++# CONFIG_CRYPTO_HW is not set +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0428-ARM-shmobile-ape6evm-add-__initconst-annotations-whe.patch b/patches.renesas/0428-ARM-shmobile-ape6evm-add-__initconst-annotations-whe.patch new file mode 100644 index 00000000000..1dcdbc2140d --- /dev/null +++ b/patches.renesas/0428-ARM-shmobile-ape6evm-add-__initconst-annotations-whe.patch @@ -0,0 +1,91 @@ +From 5b64006979c3399eeee0dc07c7b1035f609dc707 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Wed, 31 Jul 2013 14:40:14 +0200 +Subject: ARM: shmobile: ape6evm: add "__initconst" annotations where needed + +This patch adds __initconst markers to the platform data and resources, +used on ape6evm as parameters to platform_device_register_resndata(). +The data is duplicated inside that function, therefore original data +can be discarded after initialisation is completed. + +Reported-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 23f1751c5fef5c33e6a58ed2448774aeae436a39) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-ape6evm.c | 18 +++++++++--------- + 1 file changed, 9 insertions(+), 9 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c +index ccf8b042..c5e6cba8 100644 +--- a/arch/arm/mach-shmobile/board-ape6evm.c ++++ b/arch/arm/mach-shmobile/board-ape6evm.c +@@ -44,7 +44,7 @@ static struct regulator_consumer_supply dummy_supplies[] = { + }; + + /* SMSC LAN9220 */ +-static const struct resource lan9220_res[] = { ++static const struct resource lan9220_res[] __initconst = { + DEFINE_RES_MEM(0x08000000, 0x1000), + { + .start = irq_pin(40), /* IRQ40 */ +@@ -52,7 +52,7 @@ static const struct resource lan9220_res[] = { + }, + }; + +-static const struct smsc911x_platform_config lan9220_data = { ++static const struct smsc911x_platform_config lan9220_data __initconst = { + .flags = SMSC911X_USE_32BIT, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, +@@ -73,39 +73,39 @@ static struct regulator_consumer_supply fixed3v3_power_consumers[] = + }; + + /* MMCIF */ +-static struct sh_mmcif_plat_data mmcif0_pdata = { ++static const struct sh_mmcif_plat_data mmcif0_pdata __initconst = { + .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, + }; + +-static struct resource mmcif0_resources[] = { ++static const struct resource mmcif0_resources[] __initconst = { + DEFINE_RES_MEM_NAMED(0xee200000, 0x100, "MMCIF0"), + DEFINE_RES_IRQ(gic_spi(169)), + }; + + /* SDHI0 */ +-static struct sh_mobile_sdhi_info sdhi0_pdata = { ++static const struct sh_mobile_sdhi_info sdhi0_pdata __initconst = { + .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE, + .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ, + }; + +-static struct resource sdhi0_resources[] = { ++static const struct resource sdhi0_resources[] __initconst = { + DEFINE_RES_MEM_NAMED(0xee100000, 0x100, "SDHI0"), + DEFINE_RES_IRQ(gic_spi(165)), + }; + + /* SDHI1 */ +-static struct sh_mobile_sdhi_info sdhi1_pdata = { ++static const struct sh_mobile_sdhi_info sdhi1_pdata __initconst = { + .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE, + .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | + MMC_CAP_NEEDS_POLL, + }; + +-static struct resource sdhi1_resources[] = { ++static const struct resource sdhi1_resources[] __initconst = { + DEFINE_RES_MEM_NAMED(0xee120000, 0x100, "SDHI1"), + DEFINE_RES_IRQ(gic_spi(166)), + }; + +-static const struct pinctrl_map ape6evm_pinctrl_map[] = { ++static const struct pinctrl_map ape6evm_pinctrl_map[] __initconst = { + /* SCIFA0 console */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a73a4", + "scifa0_data", "scifa0"), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0429-ARM-shmobile-Mount-root-file-systems-in-r-w-mode-for.patch b/patches.renesas/0429-ARM-shmobile-Mount-root-file-systems-in-r-w-mode-for.patch new file mode 100644 index 00000000000..911e022166d --- /dev/null +++ b/patches.renesas/0429-ARM-shmobile-Mount-root-file-systems-in-r-w-mode-for.patch @@ -0,0 +1,147 @@ +From 52a1befa5e65569f9e5a79ae2944cbefbffa9957 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 29 Jul 2013 22:31:41 +0200 +Subject: ARM: shmobile: Mount root file systems in r/w mode for all DT + platforms + +The shmobile DT files available in the kernel are reference +implementations intended to be used as sample code, as well as for +development. As such, it makes sense to mount the root file system in +read/write mode by default. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d2f463a66abb1edc3b0ab6cc8252d9fa4e3d30e8) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts | 2 +- + arch/arm/boot/dts/r8a73a4-ape6evm.dts | 2 +- + arch/arm/boot/dts/r8a7778-bockw-reference.dts | 2 +- + arch/arm/boot/dts/r8a7778-bockw.dts | 2 +- + arch/arm/boot/dts/r8a7779-marzen-reference.dts | 2 +- + arch/arm/boot/dts/r8a7790-lager-reference.dts | 2 +- + arch/arm/boot/dts/r8a7790-lager.dts | 2 +- + arch/arm/boot/dts/sh73a0-kzm9g-reference.dts | 2 +- + arch/arm/boot/dts/sh73a0-kzm9g.dts | 2 +- + 9 files changed, 9 insertions(+), 9 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts +index bbd09d8c..f444624e 100644 +--- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts ++++ b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts +@@ -16,7 +16,7 @@ + compatible = "renesas,ape6evm-reference", "renesas,r8a73a4"; + + chosen { +- bootargs = "console=ttySC0,115200 ignore_loglevel"; ++ bootargs = "console=ttySC0,115200 ignore_loglevel rw"; + }; + + memory@40000000 { +diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts +index e657a9db..72f867e6 100644 +--- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts ++++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts +@@ -16,7 +16,7 @@ + compatible = "renesas,ape6evm", "renesas,r8a73a4"; + + chosen { +- bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp"; ++ bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw"; + }; + + memory@40000000 { +diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts +index f5b8d774..9bb903a3 100644 +--- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts ++++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts +@@ -22,7 +22,7 @@ + compatible = "renesas,bockw-reference", "renesas,r8a7778"; + + chosen { +- bootargs = "console=ttySC0,115200 ignore_loglevel"; ++ bootargs = "console=ttySC0,115200 ignore_loglevel rw"; + }; + + memory { +diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts +index 0076b1e8..12bbebc9 100644 +--- a/arch/arm/boot/dts/r8a7778-bockw.dts ++++ b/arch/arm/boot/dts/r8a7778-bockw.dts +@@ -22,7 +22,7 @@ + compatible = "renesas,bockw", "renesas,r8a7778"; + + chosen { +- bootargs = "console=ttySC0,115200 ignore_loglevel ip=dhcp root=/dev/nfs"; ++ bootargs = "console=ttySC0,115200 ignore_loglevel ip=dhcp root=/dev/nfs rw"; + }; + + memory { +diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts +index b64705be..6d550839 100644 +--- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts ++++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts +@@ -18,7 +18,7 @@ + compatible = "renesas,marzen-reference", "renesas,r8a7779"; + + chosen { +- bootargs = "console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on"; ++ bootargs = "console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on rw"; + }; + + memory { +diff --git a/arch/arm/boot/dts/r8a7790-lager-reference.dts b/arch/arm/boot/dts/r8a7790-lager-reference.dts +index 5ee71cf5..c462ef13 100644 +--- a/arch/arm/boot/dts/r8a7790-lager-reference.dts ++++ b/arch/arm/boot/dts/r8a7790-lager-reference.dts +@@ -17,7 +17,7 @@ + compatible = "renesas,lager-reference", "renesas,r8a7790"; + + chosen { +- bootargs = "console=ttySC6,115200 ignore_loglevel"; ++ bootargs = "console=ttySC6,115200 ignore_loglevel rw"; + }; + + memory@40000000 { +diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts +index 09a84fce..631b93bc 100644 +--- a/arch/arm/boot/dts/r8a7790-lager.dts ++++ b/arch/arm/boot/dts/r8a7790-lager.dts +@@ -16,7 +16,7 @@ + compatible = "renesas,lager", "renesas,r8a7790"; + + chosen { +- bootargs = "console=ttySC6,115200 ignore_loglevel"; ++ bootargs = "console=ttySC6,115200 ignore_loglevel rw"; + }; + + memory@40000000 { +diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +index b99e890d..21223062 100644 +--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts ++++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +@@ -33,7 +33,7 @@ + }; + + chosen { +- bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200"; ++ bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200 rw"; + }; + + memory { +diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts +index 7c4071e7..0f1ca779 100644 +--- a/arch/arm/boot/dts/sh73a0-kzm9g.dts ++++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts +@@ -16,7 +16,7 @@ + compatible = "renesas,kzm9g", "renesas,sh73a0"; + + chosen { +- bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200"; ++ bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200 rw"; + }; + + memory { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0430-ARM-shmobile-lager-add-missing-__initdata.patch b/patches.renesas/0430-ARM-shmobile-lager-add-missing-__initdata.patch new file mode 100644 index 00000000000..e7b827934b2 --- /dev/null +++ b/patches.renesas/0430-ARM-shmobile-lager-add-missing-__initdata.patch @@ -0,0 +1,37 @@ +From 283809123ae34d23446ca1d691746c393ebda009 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Thu, 1 Aug 2013 18:34:37 -0700 +Subject: ARM: shmobile: lager: add missing __initdata + +This patch adds missing __initdata to driver data/resource +which are used from platform_device_register_xxx() + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 8c8881b50691e17864cc54e5824b140e62fc2035) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-lager.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c +index 3a1a6fdc..aa8be240 100644 +--- a/arch/arm/mach-shmobile/board-lager.c ++++ b/arch/arm/mach-shmobile/board-lager.c +@@ -82,11 +82,11 @@ static struct regulator_consumer_supply fixed3v3_power_consumers[] = + }; + + /* MMCIF */ +-static struct sh_mmcif_plat_data mmcif1_pdata = { ++static struct sh_mmcif_plat_data mmcif1_pdata __initdata = { + .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, + }; + +-static struct resource mmcif1_resources[] = { ++static struct resource mmcif1_resources[] __initdata = { + DEFINE_RES_MEM_NAMED(0xee220000, 0x80, "MMCIF1"), + DEFINE_RES_IRQ(gic_spi(170)), + }; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0431-ARM-shmobile-ape6evm-Enable-gpio-keys-in-defconfig.patch b/patches.renesas/0431-ARM-shmobile-ape6evm-Enable-gpio-keys-in-defconfig.patch new file mode 100644 index 00000000000..f46e1751e9c --- /dev/null +++ b/patches.renesas/0431-ARM-shmobile-ape6evm-Enable-gpio-keys-in-defconfig.patch @@ -0,0 +1,30 @@ +From 754b82dedea3db5adf5c38dde8c9d89089cf9cb0 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Tue, 30 Jul 2013 10:59:01 +0900 +Subject: ARM: shmobile: ape6evm: Enable gpio-keys in defconfig + +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit ab4d2cd1c9543efdf7e9bf942c0199d199abf3e0) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/configs/ape6evm_defconfig | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/configs/ape6evm_defconfig b/arch/arm/configs/ape6evm_defconfig +index dab5a7df..e4359c7e 100644 +--- a/arch/arm/configs/ape6evm_defconfig ++++ b/arch/arm/configs/ape6evm_defconfig +@@ -54,7 +54,8 @@ CONFIG_NETDEVICES=y + CONFIG_SMC91X=y + CONFIG_SMSC911X=y + # CONFIG_INPUT_MOUSEDEV is not set +-# CONFIG_INPUT_KEYBOARD is not set ++CONFIG_INPUT_EVDEV=y ++CONFIG_KEYBOARD_GPIO=y + # CONFIG_INPUT_MOUSE is not set + # CONFIG_SERIO is not set + CONFIG_SERIAL_NONSTANDARD=y +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0432-ARM-shmobile-ape6evm-Enable-gpio-leds-in-defconfig.patch b/patches.renesas/0432-ARM-shmobile-ape6evm-Enable-gpio-leds-in-defconfig.patch new file mode 100644 index 00000000000..c125ffbf28d --- /dev/null +++ b/patches.renesas/0432-ARM-shmobile-ape6evm-Enable-gpio-leds-in-defconfig.patch @@ -0,0 +1,30 @@ +From 6afee03fbbcb417c1afc64218ca08908c405c924 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Tue, 30 Jul 2013 10:59:03 +0900 +Subject: ARM: shmobile: ape6evm: Enable gpio-leds in defconfig + +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 461cd47a65f5d8513a983ebd21ef7c23d4b4730f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/configs/ape6evm_defconfig | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/arch/arm/configs/ape6evm_defconfig b/arch/arm/configs/ape6evm_defconfig +index e4359c7e..1ce39940 100644 +--- a/arch/arm/configs/ape6evm_defconfig ++++ b/arch/arm/configs/ape6evm_defconfig +@@ -72,6 +72,9 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y + CONFIG_REGULATOR_GPIO=y + # CONFIG_HID is not set + # CONFIG_USB_SUPPORT is not set ++CONFIG_NEW_LEDS=y ++CONFIG_LEDS_CLASS=y ++CONFIG_LEDS_GPIO=y + # CONFIG_IOMMU_SUPPORT is not set + # CONFIG_DNOTIFY is not set + CONFIG_TMPFS=y +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0433-ARM-shmobile-armadillo800eva-Use-DT-for-GIC.patch b/patches.renesas/0433-ARM-shmobile-armadillo800eva-Use-DT-for-GIC.patch new file mode 100644 index 00000000000..859eab0a208 --- /dev/null +++ b/patches.renesas/0433-ARM-shmobile-armadillo800eva-Use-DT-for-GIC.patch @@ -0,0 +1,93 @@ +From c70cb4f3542000200273579d887bf786d3b51079 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Thu, 1 Aug 2013 23:39:13 -0700 +Subject: ARM: shmobile: armadillo800eva: Use DT for GIC + +Current Armadillo800eva is using DT booting, +and r8a7740.dtsi already has GIC settings. + +So, we can remove the C version of the GIC setup code, +instead rely on GIC information provided by DT. + +This patch removes r8a7740_init_irq() which has +no user any more + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Acked-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 15645581a9401cf2370d2c975e2673d289d5e561) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-armadillo800eva.c | 2 +- + arch/arm/mach-shmobile/include/mach/r8a7740.h | 1 - + arch/arm/mach-shmobile/intc-r8a7740.c | 20 +++----------------- + 3 files changed, 4 insertions(+), 19 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c +index 9bb74729..471440ba 100644 +--- a/arch/arm/mach-shmobile/board-armadillo800eva.c ++++ b/arch/arm/mach-shmobile/board-armadillo800eva.c +@@ -1313,7 +1313,7 @@ static const char *eva_boards_compat_dt[] __initdata = { + DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva") + .map_io = r8a7740_map_io, + .init_early = eva_add_early_devices, +- .init_irq = r8a7740_init_irq, ++ .init_irq = r8a7740_init_irq_of, + .init_machine = eva_init, + .init_late = shmobile_init_late, + .init_time = eva_earlytimer_init, +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h +index 56f37500..d07932f8 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h +@@ -48,7 +48,6 @@ enum { + + extern void r8a7740_meram_workaround(void); + extern void r8a7740_init_delay(void); +-extern void r8a7740_init_irq(void); + extern void r8a7740_init_irq_of(void); + extern void r8a7740_map_io(void); + extern void r8a7740_add_early_devices(void); +diff --git a/arch/arm/mach-shmobile/intc-r8a7740.c b/arch/arm/mach-shmobile/intc-r8a7740.c +index 8871f771..75193539 100644 +--- a/arch/arm/mach-shmobile/intc-r8a7740.c ++++ b/arch/arm/mach-shmobile/intc-r8a7740.c +@@ -23,12 +23,14 @@ + #include <linux/irqchip.h> + #include <linux/irqchip/arm-gic.h> + +-static void __init r8a7740_init_irq_common(void) ++void __init r8a7740_init_irq_of(void) + { + void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10); + void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10); + void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4); + ++ irqchip_init(); ++ + /* route signals to GIC */ + iowrite32(0x0, pfc_inta_ctrl); + +@@ -50,19 +52,3 @@ static void __init r8a7740_init_irq_common(void) + iounmap(intc_msk_base); + iounmap(pfc_inta_ctrl); + } +- +-void __init r8a7740_init_irq_of(void) +-{ +- irqchip_init(); +- r8a7740_init_irq_common(); +-} +- +-void __init r8a7740_init_irq(void) +-{ +- void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000); +- void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000); +- +- /* initialize the Generic Interrupt Controller PL390 r0p0 */ +- gic_init(0, 29, gic_dist_base, gic_cpu_base); +- r8a7740_init_irq_common(); +-} +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0434-ARM-shmobile-marzen-Use-DT-for-GIC.patch b/patches.renesas/0434-ARM-shmobile-marzen-Use-DT-for-GIC.patch new file mode 100644 index 00000000000..d0f53ef0c45 --- /dev/null +++ b/patches.renesas/0434-ARM-shmobile-marzen-Use-DT-for-GIC.patch @@ -0,0 +1,99 @@ +From 336ee8f2e1854cb249182f6834dc82d824c67706 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Thu, 1 Aug 2013 23:39:34 -0700 +Subject: ARM: shmobile: marzen: Use DT for GIC + +Current Marzen is using DT booting, +and r8a7779.dtsi already has GIC settings. + +So, we can remove the C version of the GIC setup code, +instead rely on GIC information provided by DT. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Acked-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 693ac41df314289d655123e6ded519244fa1d951) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-marzen.c | 3 +-- + arch/arm/mach-shmobile/include/mach/r8a7779.h | 1 - + arch/arm/mach-shmobile/intc-r8a7779.c | 22 ++++------------------ + 3 files changed, 5 insertions(+), 21 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c +index 2bf86c41..3551b548 100644 +--- a/arch/arm/mach-shmobile/board-marzen.c ++++ b/arch/arm/mach-shmobile/board-marzen.c +@@ -266,8 +266,7 @@ DT_MACHINE_START(MARZEN, "marzen") + .smp = smp_ops(r8a7779_smp_ops), + .map_io = r8a7779_map_io, + .init_early = r8a7779_add_early_devices, +- .nr_irqs = NR_IRQS_LEGACY, +- .init_irq = r8a7779_init_irq, ++ .init_irq = r8a7779_init_irq_dt, + .init_machine = marzen_init, + .init_late = r8a7779_init_late, + .dt_compat = marzen_boards_compat_dt, +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h +index f10727f7..f08d6ecf 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h +@@ -24,7 +24,6 @@ static inline struct r8a7779_pm_ch *to_r8a7779_ch(struct generic_pm_domain *d) + } + + extern void r8a7779_init_delay(void); +-extern void r8a7779_init_irq(void); + extern void r8a7779_init_irq_extpin(int irlm); + extern void r8a7779_init_irq_dt(void); + extern void r8a7779_map_io(void); +diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c +index 5f9e5dc0..e992a68b 100644 +--- a/arch/arm/mach-shmobile/intc-r8a7779.c ++++ b/arch/arm/mach-shmobile/intc-r8a7779.c +@@ -89,15 +89,18 @@ void __init r8a7779_init_irq_extpin(int irlm) + pr_warn("r8a7779: unable to setup external irq pin mode\n"); + } + ++#ifdef CONFIG_OF + static int r8a7779_set_wake(struct irq_data *data, unsigned int on) + { + return 0; /* always allow wakeup */ + } + +-static void __init r8a7779_init_irq_common(void) ++void __init r8a7779_init_irq_dt(void) + { + gic_arch_extn.irq_set_wake = r8a7779_set_wake; + ++ irqchip_init(); ++ + /* route all interrupts to ARM */ + __raw_writel(0xffffffff, INT2NTSR0); + __raw_writel(0x3fffffff, INT2NTSR1); +@@ -108,23 +111,6 @@ static void __init r8a7779_init_irq_common(void) + __raw_writel(0xfffbffdf, INT2SMSKCR2); + __raw_writel(0xbffffffc, INT2SMSKCR3); + __raw_writel(0x003fee3f, INT2SMSKCR4); +-} +- +-void __init r8a7779_init_irq(void) +-{ +- void __iomem *gic_dist_base = IOMEM(0xf0001000); +- void __iomem *gic_cpu_base = IOMEM(0xf0000100); + +- /* use GIC to handle interrupts */ +- gic_init(0, 29, gic_dist_base, gic_cpu_base); +- +- r8a7779_init_irq_common(); +-} +- +-#ifdef CONFIG_OF +-void __init r8a7779_init_irq_dt(void) +-{ +- irqchip_init(); +- r8a7779_init_irq_common(); + } + #endif +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0435-ARM-shmobile-r8a7790-clocks-for-Ether-support.patch b/patches.renesas/0435-ARM-shmobile-r8a7790-clocks-for-Ether-support.patch new file mode 100644 index 00000000000..b10a4e3c31e --- /dev/null +++ b/patches.renesas/0435-ARM-shmobile-r8a7790-clocks-for-Ether-support.patch @@ -0,0 +1,52 @@ +From 1e4ea70025568e90cd1c03cfcc0b66e86c153c44 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Tue, 6 Aug 2013 16:50:09 +0900 +Subject: ARM: shmobile: r8a7790: clocks for Ether support + +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 9b0b9c0151a8e7d263cee180857068940463bd5f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a7790.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c +index 50d96f9c..fc36d3db 100644 +--- a/arch/arm/mach-shmobile/clock-r8a7790.c ++++ b/arch/arm/mach-shmobile/clock-r8a7790.c +@@ -51,6 +51,7 @@ + #define SMSTPCR3 0xe615013c + #define SMSTPCR5 0xe6150144 + #define SMSTPCR7 0xe615014c ++#define SMSTPCR8 0xe6150990 + + #define SDCKCR 0xE6150074 + #define SD2CKCR 0xE6150078 +@@ -180,6 +181,7 @@ static struct clk div6_clks[DIV6_NR] = { + + /* MSTP */ + enum { ++ MSTP813, + MSTP721, MSTP720, + MSTP717, MSTP716, + MSTP522, +@@ -190,6 +192,7 @@ enum { + }; + + static struct clk mstp_clks[MSTP_NR] = { ++ [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */ + [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ + [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ + [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */ +@@ -258,6 +261,7 @@ static struct clk_lookup lookups[] = { + CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), + CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]), + CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]), ++ CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]), + CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), + CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), + CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0436-ARM-shmobile-r8a7740-Add-TPU-clock-entry-for-DT-plat.patch b/patches.renesas/0436-ARM-shmobile-r8a7740-Add-TPU-clock-entry-for-DT-plat.patch new file mode 100644 index 00000000000..691c240007a --- /dev/null +++ b/patches.renesas/0436-ARM-shmobile-r8a7740-Add-TPU-clock-entry-for-DT-plat.patch @@ -0,0 +1,28 @@ +From a87b3e4698f7c14b9747e0daca28064572fc9fd4 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 26 Jul 2013 00:50:59 +0200 +Subject: ARM: shmobile: r8a7740: Add TPU clock entry for DT platforms + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d687f4d1993fa046171dbb1ca1970a3172ce11b9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a7740.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c +index f5b7bbe4..664321c8 100644 +--- a/arch/arm/mach-shmobile/clock-r8a7740.c ++++ b/arch/arm/mach-shmobile/clock-r8a7740.c +@@ -597,6 +597,7 @@ static struct clk_lookup lookups[] = { + CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP309]), + CLKDEV_DEV_ID("e9a00000.sh-eth", &mstp_clks[MSTP309]), + CLKDEV_DEV_ID("renesas-tpu-pwm", &mstp_clks[MSTP304]), ++ CLKDEV_DEV_ID("e6600000.pwm", &mstp_clks[MSTP304]), + + CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), + CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0437-ARM-shmobile-lager-enable-nfsroot-in-DTS.patch b/patches.renesas/0437-ARM-shmobile-lager-enable-nfsroot-in-DTS.patch new file mode 100644 index 00000000000..38f0572504b --- /dev/null +++ b/patches.renesas/0437-ARM-shmobile-lager-enable-nfsroot-in-DTS.patch @@ -0,0 +1,33 @@ +From 41b5ad51fe3c931278ef144ba601094d347b4132 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Tue, 6 Aug 2013 16:50:11 +0900 +Subject: ARM: shmobile: lager: enable nfsroot in DTS + +Now that Ether support has been added to the lager board +it is possible to use nfsroot. This configuration is +in line with that of other shmobile boards. + +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit dcbbbaf2ca8bd25c5cfad1396a01495760261e47) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7790-lager.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts +index 631b93bc..203bd089 100644 +--- a/arch/arm/boot/dts/r8a7790-lager.dts ++++ b/arch/arm/boot/dts/r8a7790-lager.dts +@@ -16,7 +16,7 @@ + compatible = "renesas,lager", "renesas,r8a7790"; + + chosen { +- bootargs = "console=ttySC6,115200 ignore_loglevel rw"; ++ bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp"; + }; + + memory@40000000 { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0438-ARM-shmobile-r8a7740-Add-TPU-node-to-the-device-tree.patch b/patches.renesas/0438-ARM-shmobile-r8a7740-Add-TPU-node-to-the-device-tree.patch new file mode 100644 index 00000000000..6941944a768 --- /dev/null +++ b/patches.renesas/0438-ARM-shmobile-r8a7740-Add-TPU-node-to-the-device-tree.patch @@ -0,0 +1,35 @@ +From 35c6ac2e0dcfd136ec2cf5f5f5b49afbe6e5d0e7 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 26 Jul 2013 00:51:00 +0200 +Subject: ARM: shmobile: r8a7740: Add TPU node to the device tree + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 8b3e32c1fe5dce55e28e76b20361841dc863ec17) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + arch/arm/boot/dts/r8a7740.dtsi +--- + arch/arm/boot/dts/r8a7740.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi +index 1d1aeb6d..44d3d520 100644 +--- a/arch/arm/boot/dts/r8a7740.dtsi ++++ b/arch/arm/boot/dts/r8a7740.dtsi +@@ -152,4 +152,11 @@ + gpio-controller; + #gpio-cells = <2>; + }; ++ ++ tpu: pwm@e6600000 { ++ compatible = "renesas,tpu-r8a7740", "renesas,tpu"; ++ reg = <0xe6600000 0x100>; ++ status = "disabled"; ++ #pwm-cells = <3>; ++ }; + }; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0439-ARM-shmobile-r8a7778-cleanup-registration-of-mmcif.patch b/patches.renesas/0439-ARM-shmobile-r8a7778-cleanup-registration-of-mmcif.patch new file mode 100644 index 00000000000..4c6c76b20a0 --- /dev/null +++ b/patches.renesas/0439-ARM-shmobile-r8a7778-cleanup-registration-of-mmcif.patch @@ -0,0 +1,118 @@ +From 33fb167dfec0eded9f33dca7b61f07178b801c2f Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Fri, 26 Jul 2013 00:33:48 -0700 +Subject: ARM: shmobile: r8a7778: cleanup registration of mmcif + +sh_mmcif driver which needs platform data at the time of +registration is used from BockW only. +Now, ARM/shmobile aims to support DT, +and the C code base board support will be removed +if DT support is completed. +Current driver registration method which needs platform data +and which is not shared complicates codes. +This means legacy C code cleanup after DT supporting +will be more complicated +This patch registers it on board code as cleanup C code + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit a66c9744574c0e7b5c935c7c1ec84e0e741fb725) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-bockw.c | 12 +++++++++++- + arch/arm/mach-shmobile/include/mach/r8a7778.h | 2 -- + arch/arm/mach-shmobile/setup-r8a7778.c | 14 -------------- + 3 files changed, 11 insertions(+), 17 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c +index c7a0f9ba..5add79c9 100644 +--- a/arch/arm/mach-shmobile/board-bockw.c ++++ b/arch/arm/mach-shmobile/board-bockw.c +@@ -20,6 +20,7 @@ + + #include <linux/mfd/tmio.h> + #include <linux/mmc/host.h> ++#include <linux/mmc/sh_mmcif.h> + #include <linux/mtd/partitions.h> + #include <linux/pinctrl/machine.h> + #include <linux/platform_device.h> +@@ -134,6 +135,11 @@ static struct spi_board_info spi_board_info[] __initdata = { + }; + + /* MMC */ ++static struct resource mmc_resources[] __initdata = { ++ DEFINE_RES_MEM(0xffe4e000, 0x100), ++ DEFINE_RES_IRQ(gic_iid(0x5d)), ++}; ++ + static struct sh_mmcif_plat_data sh_mmcif_plat = { + .sup_pclk = 0, + .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, +@@ -189,7 +195,6 @@ static void __init bockw_init(void) + r8a7778_add_ether_device(ðer_platform_data); + r8a7778_add_i2c_device(0); + r8a7778_add_hspi_device(0); +- r8a7778_add_mmc_device(&sh_mmcif_plat); + + i2c_register_board_info(0, i2c0_devices, + ARRAY_SIZE(i2c0_devices)); +@@ -199,6 +204,11 @@ static void __init bockw_init(void) + ARRAY_SIZE(bockw_pinctrl_map)); + r8a7778_pinmux_init(); + ++ platform_device_register_resndata( ++ &platform_bus, "sh_mmcif", -1, ++ mmc_resources, ARRAY_SIZE(mmc_resources), ++ &sh_mmcif_plat, sizeof(struct sh_mmcif_plat_data)); ++ + /* for SMSC */ + base = ioremap_nocache(FPGA, SZ_1M); + if (base) { +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h +index 8d24f73d..2f456071 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h +@@ -18,7 +18,6 @@ + #ifndef __ASM_R8A7778_H__ + #define __ASM_R8A7778_H__ + +-#include <linux/mmc/sh_mmcif.h> + #include <linux/mmc/sh_mobile_sdhi.h> + #include <linux/sh_eth.h> + #include <linux/platform_data/usb-rcar-phy.h> +@@ -29,7 +28,6 @@ extern void r8a7778_add_ether_device(struct sh_eth_plat_data *pdata); + extern void r8a7778_add_usb_phy_device(struct rcar_phy_platform_data *pdata); + extern void r8a7778_add_i2c_device(int id); + extern void r8a7778_add_hspi_device(int id); +-extern void r8a7778_add_mmc_device(struct sh_mmcif_plat_data *info); + extern void r8a7778_add_dt_devices(void); + + extern void r8a7778_init_late(void); +diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c +index 9d4b6bf4..96008462 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7778.c ++++ b/arch/arm/mach-shmobile/setup-r8a7778.c +@@ -319,20 +319,6 @@ void __init r8a7778_add_hspi_device(int id) + hspi_resources + (2 * id), 2); + } + +-/* MMC */ +-static struct resource mmc_resources[] __initdata = { +- DEFINE_RES_MEM(0xffe4e000, 0x100), +- DEFINE_RES_IRQ(gic_iid(0x5d)), +-}; +- +-void __init r8a7778_add_mmc_device(struct sh_mmcif_plat_data *info) +-{ +- platform_device_register_resndata( +- &platform_bus, "sh_mmcif", -1, +- mmc_resources, ARRAY_SIZE(mmc_resources), +- info, sizeof(*info)); +-} +- + void __init r8a7778_add_dt_devices(void) + { + int i; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0440-ARM-shmobile-r8a7778-cleanup-registration-of-usb-phy.patch b/patches.renesas/0440-ARM-shmobile-r8a7778-cleanup-registration-of-usb-phy.patch new file mode 100644 index 00000000000..47a1c44c657 --- /dev/null +++ b/patches.renesas/0440-ARM-shmobile-r8a7778-cleanup-registration-of-usb-phy.patch @@ -0,0 +1,130 @@ +From de99ca4a76025a704cf74705de310181be44867a Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Fri, 26 Jul 2013 15:54:44 +0900 +Subject: ARM: shmobile: r8a7778: cleanup registration of usb phy + +usb phy driver which needs platform data at the time of +registration is used from BockW only. +Now, ARM/shmobile aims to support DT, +and the C code base board support will be removed +if DT support is completed. +Current driver registration method which needs platform data +and which is not shared complicates codes. +This means legacy C code cleanup after DT supporting +will be more complicated +This patch registers it on board code as cleanup C code + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 044e2121466a2bf528aeb91099df7e37723fb36b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + arch/arm/mach-shmobile/board-bockw.c +--- + arch/arm/mach-shmobile/board-bockw.c | 17 ++++++++++++++++- + arch/arm/mach-shmobile/include/mach/r8a7778.h | 2 -- + arch/arm/mach-shmobile/setup-r8a7778.c | 14 -------------- + 3 files changed, 16 insertions(+), 17 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c +index 5add79c9..d6270c6a 100644 +--- a/arch/arm/mach-shmobile/board-bockw.c ++++ b/arch/arm/mach-shmobile/board-bockw.c +@@ -23,6 +23,7 @@ + #include <linux/mmc/sh_mmcif.h> + #include <linux/mtd/partitions.h> + #include <linux/pinctrl/machine.h> ++#include <linux/platform_data/usb-rcar-phy.h> + #include <linux/platform_device.h> + #include <linux/regulator/fixed.h> + #include <linux/regulator/machine.h> +@@ -77,6 +78,12 @@ static struct resource smsc911x_resources[] = { + DEFINE_RES_IRQ(irq_pin(0)), /* IRQ 0 */ + }; + ++/* USB */ ++static struct resource usb_phy_resources[] __initdata = { ++ DEFINE_RES_MEM(0xffe70800, 0x100), ++ DEFINE_RES_MEM(0xffe76000, 0x100), ++}; ++ + static struct rcar_phy_platform_data usb_phy_platform_data __initdata; + + /* SDHI */ +@@ -165,6 +172,7 @@ static const struct pinctrl_map bockw_pinctrl_map[] = { + "scif0_data_a", "scif0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778", + "scif0_ctrl", "scif0"), ++ /* USB */ + PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform", "pfc-r8a7778", + "usb0", "usb0"), + PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform", "pfc-r8a7778", +@@ -191,7 +199,6 @@ static void __init bockw_init(void) + r8a7778_clock_init(); + r8a7778_init_irq_extpin(1); + r8a7778_add_standard_devices(); +- r8a7778_add_usb_phy_device(&usb_phy_platform_data); + r8a7778_add_ether_device(ðer_platform_data); + r8a7778_add_i2c_device(0); + r8a7778_add_hspi_device(0); +@@ -209,6 +216,14 @@ static void __init bockw_init(void) + mmc_resources, ARRAY_SIZE(mmc_resources), + &sh_mmcif_plat, sizeof(struct sh_mmcif_plat_data)); + ++ platform_device_register_resndata( ++ &platform_bus, "rcar_usb_phy", -1, ++ usb_phy_resources, ++ ARRAY_SIZE(usb_phy_resources), ++ &usb_phy_platform_data, ++ sizeof(struct rcar_phy_platform_data)); ++ ++ + /* for SMSC */ + base = ioremap_nocache(FPGA, SZ_1M); + if (base) { +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h +index 2f456071..a184a133 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h +@@ -20,12 +20,10 @@ + + #include <linux/mmc/sh_mobile_sdhi.h> + #include <linux/sh_eth.h> +-#include <linux/platform_data/usb-rcar-phy.h> + + extern void r8a7778_add_standard_devices(void); + extern void r8a7778_add_standard_devices_dt(void); + extern void r8a7778_add_ether_device(struct sh_eth_plat_data *pdata); +-extern void r8a7778_add_usb_phy_device(struct rcar_phy_platform_data *pdata); + extern void r8a7778_add_i2c_device(int id); + extern void r8a7778_add_hspi_device(int id); + extern void r8a7778_add_dt_devices(void); +diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c +index 96008462..89475079 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7778.c ++++ b/arch/arm/mach-shmobile/setup-r8a7778.c +@@ -95,20 +95,6 @@ static struct sh_timer_config sh_tmu1_platform_data __initdata = { + &sh_tmu##idx##_platform_data, \ + sizeof(sh_tmu##idx##_platform_data)) + +-/* USB PHY */ +-static struct resource usb_phy_resources[] __initdata = { +- DEFINE_RES_MEM(0xffe70800, 0x100), +- DEFINE_RES_MEM(0xffe76000, 0x100), +-}; +- +-void __init r8a7778_add_usb_phy_device(struct rcar_phy_platform_data *pdata) +-{ +- platform_device_register_resndata(&platform_bus, "rcar_usb_phy", -1, +- usb_phy_resources, +- ARRAY_SIZE(usb_phy_resources), +- pdata, sizeof(*pdata)); +-} +- + /* USB */ + static struct usb_phy *phy; + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0441-ARM-shmobile-r8a7778-cleanup-registration-of-sdhi.patch b/patches.renesas/0441-ARM-shmobile-r8a7778-cleanup-registration-of-sdhi.patch new file mode 100644 index 00000000000..1738356c54e --- /dev/null +++ b/patches.renesas/0441-ARM-shmobile-r8a7778-cleanup-registration-of-sdhi.patch @@ -0,0 +1,119 @@ +From 260bb68c12e23e88ba4c20452c8e45fe367c6930 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Fri, 26 Jul 2013 00:34:58 -0700 +Subject: ARM: shmobile: r8a7778: cleanup registration of sdhi + +sdhi driver which needs platform data at the time of +registration is used from BockW only. +Now, ARM/shmobile aims to support DT, +and the C code base board support will be removed +if DT support is completed. +Current driver registration method which needs platform data +and which is not shared complicates codes. +This means legacy C code cleanup after DT supporting +will be more complicated +This patch registers it on board code as cleanup C code + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit fc55190835e02ba5ae23dff40c92ea96db8ec8b6) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-bockw.c | 11 ++++++++++- + arch/arm/mach-shmobile/include/mach/r8a7778.h | 2 -- + arch/arm/mach-shmobile/setup-r8a7778.c | 24 ------------------------ + 3 files changed, 10 insertions(+), 27 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c +index d6270c6a..959ccc86 100644 +--- a/arch/arm/mach-shmobile/board-bockw.c ++++ b/arch/arm/mach-shmobile/board-bockw.c +@@ -20,6 +20,7 @@ + + #include <linux/mfd/tmio.h> + #include <linux/mmc/host.h> ++#include <linux/mmc/sh_mobile_sdhi.h> + #include <linux/mmc/sh_mmcif.h> + #include <linux/mtd/partitions.h> + #include <linux/pinctrl/machine.h> +@@ -93,6 +94,11 @@ static struct sh_mobile_sdhi_info sdhi0_info = { + .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT, + }; + ++static struct resource sdhi0_resources[] __initdata = { ++ DEFINE_RES_MEM(0xFFE4C000, 0x100), ++ DEFINE_RES_IRQ(gic_iid(0x77)), ++}; ++ + static struct sh_eth_plat_data ether_platform_data __initdata = { + .phy = 0x01, + .edmac_endian = EDMAC_LITTLE_ENDIAN, +@@ -259,7 +265,10 @@ static void __init bockw_init(void) + iowrite32(ioread32(base + PUPR4) | (3 << 26), base + PUPR4); + iounmap(base); + +- r8a7778_sdhi_init(0, &sdhi0_info); ++ platform_device_register_resndata( ++ &platform_bus, "sh_mobile_sdhi", 0, ++ sdhi0_resources, ARRAY_SIZE(sdhi0_resources), ++ &sdhi0_info, sizeof(struct sh_mobile_sdhi_info)); + } + } + +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h +index a184a133..aaa05449 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h +@@ -18,7 +18,6 @@ + #ifndef __ASM_R8A7778_H__ + #define __ASM_R8A7778_H__ + +-#include <linux/mmc/sh_mobile_sdhi.h> + #include <linux/sh_eth.h> + + extern void r8a7778_add_standard_devices(void); +@@ -34,6 +33,5 @@ extern void r8a7778_init_irq_dt(void); + extern void r8a7778_clock_init(void); + extern void r8a7778_init_irq_extpin(int irlm); + extern void r8a7778_pinmux_init(void); +-extern void r8a7778_sdhi_init(int id, struct sh_mobile_sdhi_info *info); + + #endif /* __ASM_R8A7778_H__ */ +diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c +index 89475079..c585ee0e 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7778.c ++++ b/arch/arm/mach-shmobile/setup-r8a7778.c +@@ -234,30 +234,6 @@ void __init r8a7778_pinmux_init(void) + r8a7778_register_gpio(4); + }; + +-/* SDHI */ +-static struct resource sdhi_resources[] __initdata = { +- /* SDHI0 */ +- DEFINE_RES_MEM(0xFFE4C000, 0x100), +- DEFINE_RES_IRQ(gic_iid(0x77)), +- /* SDHI1 */ +- DEFINE_RES_MEM(0xFFE4D000, 0x100), +- DEFINE_RES_IRQ(gic_iid(0x78)), +- /* SDHI2 */ +- DEFINE_RES_MEM(0xFFE4F000, 0x100), +- DEFINE_RES_IRQ(gic_iid(0x76)), +-}; +- +-void __init r8a7778_sdhi_init(int id, +- struct sh_mobile_sdhi_info *info) +-{ +- BUG_ON(id < 0 || id > 2); +- +- platform_device_register_resndata( +- &platform_bus, "sh_mobile_sdhi", id, +- sdhi_resources + (2 * id), 2, +- info, sizeof(*info)); +-} +- + /* I2C */ + static struct resource i2c_resources[] __initdata = { + /* I2C0 */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0442-ARM-shmobile-r8a7778-cleanup-registration-of-i2c.patch b/patches.renesas/0442-ARM-shmobile-r8a7778-cleanup-registration-of-i2c.patch new file mode 100644 index 00000000000..f0dc1c3b57d --- /dev/null +++ b/patches.renesas/0442-ARM-shmobile-r8a7778-cleanup-registration-of-i2c.patch @@ -0,0 +1,73 @@ +From 8b583af5ba17545306bf4d52f629a65f0b9b5350 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Fri, 26 Jul 2013 00:35:08 -0700 +Subject: ARM: shmobile: r8a7778: cleanup registration of i2c + +i2c-rcar driver which doesn't need platform data at the time of +registration can be registerd on SoC. +And, registering these drivers in the SoC code can avoid +unwanted device numbering issue. +(ex. the i2c3 device number will be i2c.0 if i2c3 only registered) +This patch registers it on SoC code as cleanup C code + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 1fd4eecd480b82e11900ae6a8f44d92efeb96004) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-bockw.c | 1 - + arch/arm/mach-shmobile/include/mach/r8a7778.h | 1 - + arch/arm/mach-shmobile/setup-r8a7778.c | 6 +++++- + 3 files changed, 5 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c +index 959ccc86..12b7396b 100644 +--- a/arch/arm/mach-shmobile/board-bockw.c ++++ b/arch/arm/mach-shmobile/board-bockw.c +@@ -206,7 +206,6 @@ static void __init bockw_init(void) + r8a7778_init_irq_extpin(1); + r8a7778_add_standard_devices(); + r8a7778_add_ether_device(ðer_platform_data); +- r8a7778_add_i2c_device(0); + r8a7778_add_hspi_device(0); + + i2c_register_board_info(0, i2c0_devices, +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h +index aaa05449..9874511b 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h +@@ -23,7 +23,6 @@ + extern void r8a7778_add_standard_devices(void); + extern void r8a7778_add_standard_devices_dt(void); + extern void r8a7778_add_ether_device(struct sh_eth_plat_data *pdata); +-extern void r8a7778_add_i2c_device(int id); + extern void r8a7778_add_hspi_device(int id); + extern void r8a7778_add_dt_devices(void); + +diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c +index c585ee0e..ce3b54df 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7778.c ++++ b/arch/arm/mach-shmobile/setup-r8a7778.c +@@ -250,7 +250,7 @@ static struct resource i2c_resources[] __initdata = { + DEFINE_RES_IRQ(gic_iid(0x6d)), + }; + +-void __init r8a7778_add_i2c_device(int id) ++static void __init r8a7778_register_i2c(int id) + { + BUG_ON(id < 0 || id > 3); + +@@ -308,6 +308,10 @@ void __init r8a7778_add_dt_devices(void) + void __init r8a7778_add_standard_devices(void) + { + r8a7778_add_dt_devices(); ++ r8a7778_register_i2c(0); ++ r8a7778_register_i2c(1); ++ r8a7778_register_i2c(2); ++ r8a7778_register_i2c(3); + } + + void __init r8a7778_init_late(void) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0443-ARM-shmobile-r8a7778-cleanup-registration-of-hspi.patch b/patches.renesas/0443-ARM-shmobile-r8a7778-cleanup-registration-of-hspi.patch new file mode 100644 index 00000000000..e0e5edbc87d --- /dev/null +++ b/patches.renesas/0443-ARM-shmobile-r8a7778-cleanup-registration-of-hspi.patch @@ -0,0 +1,72 @@ +From d1f52e9b9408ad362c1aa5b208ba02161ca886c3 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 30 Jul 2013 00:02:24 -0700 +Subject: ARM: shmobile: r8a7778: cleanup registration of hspi + +sh-hspi driver which doesn't need platform data at the time of +registration can be registerd on SoC. +And, registering these drivers in the SoC code can avoid +unwanted device numbering issue. +(ex. the hspi2 device number will be spi.0 if hspi2 only registered) +This patch registers it on SoC code as cleanup C code + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 3c7b5362323cd4b5d09a5b21ba8e74b3de05fc73) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-bockw.c | 1 - + arch/arm/mach-shmobile/include/mach/r8a7778.h | 1 - + arch/arm/mach-shmobile/setup-r8a7778.c | 5 ++++- + 3 files changed, 4 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c +index 12b7396b..07009f5f 100644 +--- a/arch/arm/mach-shmobile/board-bockw.c ++++ b/arch/arm/mach-shmobile/board-bockw.c +@@ -206,7 +206,6 @@ static void __init bockw_init(void) + r8a7778_init_irq_extpin(1); + r8a7778_add_standard_devices(); + r8a7778_add_ether_device(ðer_platform_data); +- r8a7778_add_hspi_device(0); + + i2c_register_board_info(0, i2c0_devices, + ARRAY_SIZE(i2c0_devices)); +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h +index 9874511b..41fd6da2 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h +@@ -23,7 +23,6 @@ + extern void r8a7778_add_standard_devices(void); + extern void r8a7778_add_standard_devices_dt(void); + extern void r8a7778_add_ether_device(struct sh_eth_plat_data *pdata); +-extern void r8a7778_add_hspi_device(int id); + extern void r8a7778_add_dt_devices(void); + + extern void r8a7778_init_late(void); +diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c +index ce3b54df..1a154d4a 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7778.c ++++ b/arch/arm/mach-shmobile/setup-r8a7778.c +@@ -272,7 +272,7 @@ static struct resource hspi_resources[] __initdata = { + DEFINE_RES_IRQ(gic_iid(0x75)), + }; + +-void __init r8a7778_add_hspi_device(int id) ++void __init r8a7778_register_hspi(int id) + { + BUG_ON(id < 0 || id > 2); + +@@ -312,6 +312,9 @@ void __init r8a7778_add_standard_devices(void) + r8a7778_register_i2c(1); + r8a7778_register_i2c(2); + r8a7778_register_i2c(3); ++ r8a7778_register_hspi(0); ++ r8a7778_register_hspi(1); ++ r8a7778_register_hspi(2); + } + + void __init r8a7778_init_late(void) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0444-ARM-shmobile-Use-default-init_time-on-r8a73a4.patch b/patches.renesas/0444-ARM-shmobile-Use-default-init_time-on-r8a73a4.patch new file mode 100644 index 00000000000..9a2e1b848d8 --- /dev/null +++ b/patches.renesas/0444-ARM-shmobile-Use-default-init_time-on-r8a73a4.patch @@ -0,0 +1,30 @@ +From 07a20856cca0417ede8bed05c65cdd997d4e8908 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Thu, 1 Aug 2013 04:01:19 +0900 +Subject: ARM: shmobile: Use default ->init_time() on r8a73a4 + +Leave ->init_time() set to NULL to use the default ARM behaviour. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 58909ae593e8e6fc7e89d88ffe61effedf09389a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a73a4.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c +index 2ee45d52..89491700 100644 +--- a/arch/arm/mach-shmobile/setup-r8a73a4.c ++++ b/arch/arm/mach-shmobile/setup-r8a73a4.c +@@ -223,7 +223,6 @@ static const char *r8a73a4_boards_compat_dt[] __initdata = { + + DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)") + .init_early = r8a73a4_init_delay, +- .init_time = shmobile_timer_init, + .dt_compat = r8a73a4_boards_compat_dt, + MACHINE_END + #endif /* CONFIG_USE_OF */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0445-ARM-shmobile-Use-default-init_time-on-r8a7740.patch b/patches.renesas/0445-ARM-shmobile-Use-default-init_time-on-r8a7740.patch new file mode 100644 index 00000000000..5a11c9bfd13 --- /dev/null +++ b/patches.renesas/0445-ARM-shmobile-Use-default-init_time-on-r8a7740.patch @@ -0,0 +1,30 @@ +From ca04d8268799850eaa7e52ab1dbdc758f4358a78 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Thu, 1 Aug 2013 04:01:28 +0900 +Subject: ARM: shmobile: Use default ->init_time() on r8a7740 + +Leave ->init_time() set to NULL to use the default ARM behaviour. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 8adacad26f1db14dd3a5bc08f632e74ba7ed7b8b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a7740.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c +index 84c5bb6d..21026b34 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7740.c ++++ b/arch/arm/mach-shmobile/setup-r8a7740.c +@@ -1035,7 +1035,6 @@ DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)") + .init_early = r8a7740_init_delay, + .init_irq = r8a7740_init_irq_of, + .init_machine = r8a7740_generic_init, +- .init_time = shmobile_timer_init, + .dt_compat = r8a7740_boards_compat_dt, + MACHINE_END + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0446-ARM-shmobile-Use-default-init_time-on-r8a7778.patch b/patches.renesas/0446-ARM-shmobile-Use-default-init_time-on-r8a7778.patch new file mode 100644 index 00000000000..94d052470e9 --- /dev/null +++ b/patches.renesas/0446-ARM-shmobile-Use-default-init_time-on-r8a7778.patch @@ -0,0 +1,30 @@ +From 46de344f345a6d62ab1340132dcdd0d0099047e6 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Thu, 1 Aug 2013 04:01:37 +0900 +Subject: ARM: shmobile: Use default ->init_time() on r8a7778 + +Leave ->init_time() set to NULL to use the default ARM behaviour. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 0765f48a214af1ea9dd5ac7e3804c00ad6d16e15) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a7778.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c +index 1a154d4a..604cf36b 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7778.c ++++ b/arch/arm/mach-shmobile/setup-r8a7778.c +@@ -406,7 +406,6 @@ static const char *r8a7778_compat_dt[] __initdata = { + DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)") + .init_early = r8a7778_init_delay, + .init_irq = r8a7778_init_irq_dt, +- .init_time = shmobile_timer_init, + .dt_compat = r8a7778_compat_dt, + .init_late = r8a7778_init_late, + MACHINE_END +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0447-ARM-shmobile-Use-default-init_time-on-r8a7779.patch b/patches.renesas/0447-ARM-shmobile-Use-default-init_time-on-r8a7779.patch new file mode 100644 index 00000000000..f23c84a61cd --- /dev/null +++ b/patches.renesas/0447-ARM-shmobile-Use-default-init_time-on-r8a7779.patch @@ -0,0 +1,30 @@ +From fb035223e3a6b2a0a66805108d2fbbe5dfc6054a Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Thu, 1 Aug 2013 04:01:46 +0900 +Subject: ARM: shmobile: Use default ->init_time() on r8a7779 + +Leave ->init_time() set to NULL to use the default ARM behaviour. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 67ac21f65fc45a016fd999c67ff4a6a7a452bf58) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a7779.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c +index ddee4aa8..111e953a 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7779.c ++++ b/arch/arm/mach-shmobile/setup-r8a7779.c +@@ -667,7 +667,6 @@ DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)") + .nr_irqs = NR_IRQS_LEGACY, + .init_irq = r8a7779_init_irq_dt, + .init_machine = r8a7779_add_standard_devices_dt, +- .init_time = shmobile_timer_init, + .init_late = r8a7779_init_late, + .dt_compat = r8a7779_compat_dt, + MACHINE_END +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0448-ARM-shmobile-Use-default-init_time-on-Bockw.patch b/patches.renesas/0448-ARM-shmobile-Use-default-init_time-on-Bockw.patch new file mode 100644 index 00000000000..a0000faaea4 --- /dev/null +++ b/patches.renesas/0448-ARM-shmobile-Use-default-init_time-on-Bockw.patch @@ -0,0 +1,30 @@ +From 25407b8fb8f8f541c394b5b2854a5557391b14d4 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Thu, 1 Aug 2013 04:01:55 +0900 +Subject: ARM: shmobile: Use default ->init_time() on Bockw + +Leave ->init_time() set to NULL to use the default ARM behaviour. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 9808f79327806e00e681c18ac84e8abfa4373dbf) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-bockw.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c +index 07009f5f..adf054d8 100644 +--- a/arch/arm/mach-shmobile/board-bockw.c ++++ b/arch/arm/mach-shmobile/board-bockw.c +@@ -279,7 +279,6 @@ DT_MACHINE_START(BOCKW_DT, "bockw") + .init_early = r8a7778_init_delay, + .init_irq = r8a7778_init_irq_dt, + .init_machine = bockw_init, +- .init_time = shmobile_timer_init, + .dt_compat = bockw_boards_compat_dt, + .init_late = r8a7778_init_late, + MACHINE_END +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0449-ARM-shmobile-Use-default-init_time-on-Bockw-DT-ref.patch b/patches.renesas/0449-ARM-shmobile-Use-default-init_time-on-Bockw-DT-ref.patch new file mode 100644 index 00000000000..0f31707d3ea --- /dev/null +++ b/patches.renesas/0449-ARM-shmobile-Use-default-init_time-on-Bockw-DT-ref.patch @@ -0,0 +1,29 @@ +From 5f817e136747ab0a3dbaf80e3dcb7901405c5f5d Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Thu, 1 Aug 2013 04:02:05 +0900 +Subject: ARM: shmobile: Use default ->init_time() on Bockw DT ref + +Leave ->init_time() set to NULL to use the default ARM behaviour. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 3bdbd1c9dbff686e375696543577c8a7ad6ef801) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-bockw-reference.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/board-bockw-reference.c b/arch/arm/mach-shmobile/board-bockw-reference.c +index 24db8de7..1a7c893e 100644 +--- a/arch/arm/mach-shmobile/board-bockw-reference.c ++++ b/arch/arm/mach-shmobile/board-bockw-reference.c +@@ -57,6 +57,5 @@ DT_MACHINE_START(BOCKW_DT, "bockw") + .init_early = r8a7778_init_delay, + .init_irq = r8a7778_init_irq_dt, + .init_machine = bockw_init, +- .init_time = shmobile_timer_init, + .dt_compat = bockw_boards_compat_dt, + MACHINE_END +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0450-ARM-shmobile-Use-default-init_time-on-Armadillo-DT-r.patch b/patches.renesas/0450-ARM-shmobile-Use-default-init_time-on-Armadillo-DT-r.patch new file mode 100644 index 00000000000..5cc607d807e --- /dev/null +++ b/patches.renesas/0450-ARM-shmobile-Use-default-init_time-on-Armadillo-DT-r.patch @@ -0,0 +1,30 @@ +From cecf59a130d602a3278a0e12dcfa13ad9decdf2d Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Thu, 1 Aug 2013 04:02:14 +0900 +Subject: ARM: shmobile: Use default ->init_time() on Armadillo DT ref + +Leave ->init_time() set to NULL to use the default ARM behaviour. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 70ce77f77ea4d768074ef9a2549a3a6f627d7241) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-armadillo800eva-reference.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c +index 002d8d3d..e30af4ce5 100644 +--- a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c ++++ b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c +@@ -190,7 +190,6 @@ DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva-reference") + .init_early = r8a7740_init_delay, + .init_irq = r8a7740_init_irq_of, + .init_machine = eva_init, +- .init_time = shmobile_timer_init, + .init_late = shmobile_init_late, + .dt_compat = eva_boards_compat_dt, + .restart = eva_restart, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0451-ARM-shmobile-Use-default-init_time-on-APE6EVM.patch b/patches.renesas/0451-ARM-shmobile-Use-default-init_time-on-APE6EVM.patch new file mode 100644 index 00000000000..3c444173265 --- /dev/null +++ b/patches.renesas/0451-ARM-shmobile-Use-default-init_time-on-APE6EVM.patch @@ -0,0 +1,30 @@ +From d5f27fd305d0e26a9f11868ec0a9258b467bfadb Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Thu, 1 Aug 2013 04:02:24 +0900 +Subject: ARM: shmobile: Use default ->init_time() on APE6EVM + +Leave ->init_time() set to NULL to use the default ARM behaviour. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit fb185bcb892875c56edc50f5d82d4a8eac90f0d8) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-ape6evm.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c +index c5e6cba8..7f3d85bc 100644 +--- a/arch/arm/mach-shmobile/board-ape6evm.c ++++ b/arch/arm/mach-shmobile/board-ape6evm.c +@@ -181,7 +181,6 @@ static const char *ape6evm_boards_compat_dt[] __initdata = { + + DT_MACHINE_START(APE6EVM_DT, "ape6evm") + .init_early = r8a73a4_init_delay, +- .init_time = shmobile_timer_init, + .init_machine = ape6evm_add_standard_devices, + .dt_compat = ape6evm_boards_compat_dt, + MACHINE_END +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0452-ARM-shmobile-Use-default-init_time-on-APE6EVM-DT-ref.patch b/patches.renesas/0452-ARM-shmobile-Use-default-init_time-on-APE6EVM-DT-ref.patch new file mode 100644 index 00000000000..74c34089404 --- /dev/null +++ b/patches.renesas/0452-ARM-shmobile-Use-default-init_time-on-APE6EVM-DT-ref.patch @@ -0,0 +1,30 @@ +From 87dd269d08ef633fb89b37bfcd9c55dd528e71fe Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Thu, 1 Aug 2013 04:02:33 +0900 +Subject: ARM: shmobile: Use default ->init_time() on APE6EVM DT ref + +Leave ->init_time() set to NULL to use the default ARM behaviour. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 364185f3ceab16db80a4cf9f8022ae5684700723) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-ape6evm-reference.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/board-ape6evm-reference.c b/arch/arm/mach-shmobile/board-ape6evm-reference.c +index 52cc5fa5..a23fa714 100644 +--- a/arch/arm/mach-shmobile/board-ape6evm-reference.c ++++ b/arch/arm/mach-shmobile/board-ape6evm-reference.c +@@ -58,7 +58,6 @@ static const char *ape6evm_boards_compat_dt[] __initdata = { + + DT_MACHINE_START(APE6EVM_DT, "ape6evm") + .init_early = r8a73a4_init_delay, +- .init_time = shmobile_timer_init, + .init_machine = ape6evm_add_standard_devices, + .dt_compat = ape6evm_boards_compat_dt, + MACHINE_END +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0453-ARM-shmobile-Use-default-init_time-on-Marzen-DT-ref.patch b/patches.renesas/0453-ARM-shmobile-Use-default-init_time-on-Marzen-DT-ref.patch new file mode 100644 index 00000000000..0c7cc14196b --- /dev/null +++ b/patches.renesas/0453-ARM-shmobile-Use-default-init_time-on-Marzen-DT-ref.patch @@ -0,0 +1,29 @@ +From 410859a0a0aee43e016051882f3bdd99f520e45e Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Thu, 1 Aug 2013 04:02:42 +0900 +Subject: ARM: shmobile: Use default ->init_time() on Marzen DT ref + +Leave ->init_time() set to NULL to use the default ARM behaviour. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 3b2e2aa319a886ab15052b513813ced39503dfa7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-marzen-reference.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c +index 3d1c439b..3f4250a2 100644 +--- a/arch/arm/mach-shmobile/board-marzen-reference.c ++++ b/arch/arm/mach-shmobile/board-marzen-reference.c +@@ -42,6 +42,5 @@ DT_MACHINE_START(MARZEN, "marzen") + .nr_irqs = NR_IRQS_LEGACY, + .init_irq = r8a7779_init_irq_dt, + .init_machine = marzen_init, +- .init_time = shmobile_timer_init, + .dt_compat = marzen_boards_compat_dt, + MACHINE_END +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0454-ARM-shmobile-Use-default-init_time-on-KZM9G-DT-ref.patch b/patches.renesas/0454-ARM-shmobile-Use-default-init_time-on-KZM9G-DT-ref.patch new file mode 100644 index 00000000000..b08ff239d60 --- /dev/null +++ b/patches.renesas/0454-ARM-shmobile-Use-default-init_time-on-KZM9G-DT-ref.patch @@ -0,0 +1,29 @@ +From 718fc8c1080a88c8a1a9e876ee07351244c8ef9e Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Thu, 1 Aug 2013 04:02:51 +0900 +Subject: ARM: shmobile: Use default ->init_time() on KZM9G DT ref + +Leave ->init_time() set to NULL to use the default ARM behaviour. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit f6110210347fea5599223fba6ecce14f1683f510) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-kzm9g-reference.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c +index a66a808d..598e3248 100644 +--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c ++++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c +@@ -52,6 +52,5 @@ DT_MACHINE_START(KZM9G_DT, "kzm9g-reference") + .init_early = sh73a0_init_delay, + .nr_irqs = NR_IRQS_LEGACY, + .init_machine = kzm_init, +- .init_time = shmobile_timer_init, + .dt_compat = kzm9g_boards_compat_dt, + MACHINE_END +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0455-ARM-shmobile-Use-clocksource_of_init-on-r8a7790.patch b/patches.renesas/0455-ARM-shmobile-Use-clocksource_of_init-on-r8a7790.patch new file mode 100644 index 00000000000..7bbe3db9a5f --- /dev/null +++ b/patches.renesas/0455-ARM-shmobile-Use-clocksource_of_init-on-r8a7790.patch @@ -0,0 +1,43 @@ +From da1efd252d3c839c3b3cf4b4bfd8332fcb1db7cc Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Thu, 1 Aug 2013 04:03:00 +0900 +Subject: ARM: shmobile: Use clocksource_of_init() on r8a7790 + +Replace the call to shmobile_timer_init() with +clocksource_of_init(). This will allow us to +get rid of shmobile_timer_init(). + +Signed-off-by: Magnus Damm <damm@opensource.se> +[horms+renesas@verge.net.au: include linux/clocksource.h] +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit c4a62a5f79f515056d9293ee0e9ce0869a326021) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a7790.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c +index 86cf507b..6d4aa041 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7790.c ++++ b/arch/arm/mach-shmobile/setup-r8a7790.c +@@ -18,6 +18,7 @@ + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + ++#include <linux/clocksource.h> + #include <linux/irq.h> + #include <linux/kernel.h> + #include <linux/of_platform.h> +@@ -263,7 +264,7 @@ void __init r8a7790_timer_init(void) + iounmap(base); + #endif /* CONFIG_ARM_ARCH_TIMER */ + +- shmobile_timer_init(); ++ clocksource_of_init(); + } + + void __init r8a7790_init_delay(void) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0456-ARM-shmobile-Remove-unused-shmobile_init_time.patch b/patches.renesas/0456-ARM-shmobile-Remove-unused-shmobile_init_time.patch new file mode 100644 index 00000000000..986800a4e00 --- /dev/null +++ b/patches.renesas/0456-ARM-shmobile-Remove-unused-shmobile_init_time.patch @@ -0,0 +1,43 @@ +From c299a947f65212d1e6a6fff60e93c4a42d2b478c Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Thu, 1 Aug 2013 04:03:09 +0900 +Subject: ARM: shmobile: Remove unused shmobile_init_time() + +Remove shmobile_timer_init() since it now is unused. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 13eb604665c94d4cd9d7e2aeceef974cf1f30701) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/include/mach/common.h | 1 - + arch/arm/mach-shmobile/timer.c | 4 ---- + 2 files changed, 5 deletions(-) + +diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h +index e818f029..18a76f91 100644 +--- a/arch/arm/mach-shmobile/include/mach/common.h ++++ b/arch/arm/mach-shmobile/include/mach/common.h +@@ -2,7 +2,6 @@ + #define __ARCH_MACH_COMMON_H + + extern void shmobile_earlytimer_init(void); +-extern void shmobile_timer_init(void); + extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz, + unsigned int mult, unsigned int div); + struct twd_local_timer; +diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c +index f321dbeb..62d7052d 100644 +--- a/arch/arm/mach-shmobile/timer.c ++++ b/arch/arm/mach-shmobile/timer.c +@@ -59,7 +59,3 @@ void __init shmobile_earlytimer_init(void) + late_time_init = shmobile_late_time_init; + } + +-void __init shmobile_timer_init(void) +-{ +- clocksource_of_init(); +-} +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0457-ARM-shmobile-r8a7779-add-missing-__initdata.patch b/patches.renesas/0457-ARM-shmobile-r8a7779-add-missing-__initdata.patch new file mode 100644 index 00000000000..efc258aa1fd --- /dev/null +++ b/patches.renesas/0457-ARM-shmobile-r8a7779-add-missing-__initdata.patch @@ -0,0 +1,32 @@ +From b075ceed35a3ff05a258e026669ecf7018204726 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Thu, 1 Aug 2013 18:33:38 -0700 +Subject: ARM: shmobile: r8a7779: add missing __initdata + +This patch adds missing __initdata to driver data/resource +which are used from platform_device_register_xxx() + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit c7537655c6ce1d769bd6d4ec368cdf8c36ebb6ea) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a7779.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c +index 111e953a..f0b6c7de 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7779.c ++++ b/arch/arm/mach-shmobile/setup-r8a7779.c +@@ -537,7 +537,7 @@ static struct platform_device ohci1_device = { + }; + + /* Ether */ +-static struct resource ether_resources[] = { ++static struct resource ether_resources[] __initdata = { + { + .start = 0xfde00000, + .end = 0xfde003ff, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0458-ARM-shmobile-r8a7790-add-missing-__initdata.patch b/patches.renesas/0458-ARM-shmobile-r8a7790-add-missing-__initdata.patch new file mode 100644 index 00000000000..5e1a024cce0 --- /dev/null +++ b/patches.renesas/0458-ARM-shmobile-r8a7790-add-missing-__initdata.patch @@ -0,0 +1,39 @@ +From cdd99ac6f8772f4f0ef1cd7b703e5728bf6f36ae Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Thu, 1 Aug 2013 18:33:48 -0700 +Subject: ARM: shmobile: r8a7790: add missing __initdata + +This patch adds missing __initdata to driver data/resource +which are used from platform_device_register_xxx() + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 163a2a6cf1fa1d20c6c9e89d358180f409bcc7ce) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a7790.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c +index 6d4aa041..d0f5c9f9 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7790.c ++++ b/arch/arm/mach-shmobile/setup-r8a7790.c +@@ -161,13 +161,13 @@ static struct resource thermal_resources[] __initdata = { + thermal_resources, \ + ARRAY_SIZE(thermal_resources)) + +-static struct sh_timer_config cmt00_platform_data = { ++static struct sh_timer_config cmt00_platform_data __initdata = { + .name = "CMT00", + .timer_bit = 0, + .clockevent_rating = 80, + }; + +-static struct resource cmt00_resources[] = { ++static struct resource cmt00_resources[] __initdata = { + DEFINE_RES_MEM(0xffca0510, 0x0c), + DEFINE_RES_MEM(0xffca0500, 0x04), + DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0459-ARM-shmobile-bockw-add-missing-__initdata.patch b/patches.renesas/0459-ARM-shmobile-bockw-add-missing-__initdata.patch new file mode 100644 index 00000000000..b2aa88575f6 --- /dev/null +++ b/patches.renesas/0459-ARM-shmobile-bockw-add-missing-__initdata.patch @@ -0,0 +1,58 @@ +From afeb55f87706319f5ecd01474f9500ab438b5fde Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Thu, 1 Aug 2013 18:34:09 -0700 +Subject: ARM: shmobile: bockw: add missing __initdata + +This patch adds missing __initdata to driver data/resource +which are used from platform_device_register_xxx() + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 8c23c7caeb5750fcf6d7a0258692071b06fdc772) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-bockw.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c +index adf054d8..255e97e5 100644 +--- a/arch/arm/mach-shmobile/board-bockw.c ++++ b/arch/arm/mach-shmobile/board-bockw.c +@@ -67,14 +67,14 @@ static struct regulator_consumer_supply dummy_supplies[] = { + REGULATOR_SUPPLY("vdd33a", "smsc911x"), + }; + +-static struct smsc911x_platform_config smsc911x_data = { ++static struct smsc911x_platform_config smsc911x_data __initdata = { + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, + .flags = SMSC911X_USE_32BIT, + .phy_interface = PHY_INTERFACE_MODE_MII, + }; + +-static struct resource smsc911x_resources[] = { ++static struct resource smsc911x_resources[] __initdata = { + DEFINE_RES_MEM(0x18300000, 0x1000), + DEFINE_RES_IRQ(irq_pin(0)), /* IRQ 0 */ + }; +@@ -88,7 +88,7 @@ static struct resource usb_phy_resources[] __initdata = { + static struct rcar_phy_platform_data usb_phy_platform_data __initdata; + + /* SDHI */ +-static struct sh_mobile_sdhi_info sdhi0_info = { ++static struct sh_mobile_sdhi_info sdhi0_info __initdata = { + .tmio_caps = MMC_CAP_SD_HIGHSPEED, + .tmio_ocr_mask = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, + .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT, +@@ -153,7 +153,7 @@ static struct resource mmc_resources[] __initdata = { + DEFINE_RES_IRQ(gic_iid(0x5d)), + }; + +-static struct sh_mmcif_plat_data sh_mmcif_plat = { ++static struct sh_mmcif_plat_data sh_mmcif_plat __initdata = { + .sup_pclk = 0, + .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, + .caps = MMC_CAP_4_BIT_DATA | +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0460-ARM-shmobile-r8a7740-move-r8a7740_init_irq_of-to-set.patch b/patches.renesas/0460-ARM-shmobile-r8a7740-move-r8a7740_init_irq_of-to-set.patch new file mode 100644 index 00000000000..3793a2ade97 --- /dev/null +++ b/patches.renesas/0460-ARM-shmobile-r8a7740-move-r8a7740_init_irq_of-to-set.patch @@ -0,0 +1,148 @@ +From 6e5ce7f3ed1cee9e902967112e311052c0e19c69 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Thu, 1 Aug 2013 23:39:44 -0700 +Subject: ARM: shmobile: r8a7740: move r8a7740_init_irq_of() to setup + +This patch moves r8a7740_init_irq_of() to setup code, +and remove intc-r8a7740 + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 70e3f3d4f40fe5ecdb351acf33db06df077fb0c1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + arch/arm/mach-shmobile/Makefile +--- + arch/arm/mach-shmobile/Makefile | 2 +- + arch/arm/mach-shmobile/intc-r8a7740.c | 54 ---------------------------------- + arch/arm/mach-shmobile/setup-r8a7740.c | 32 ++++++++++++++++++++ + 3 files changed, 33 insertions(+), 55 deletions(-) + delete mode 100644 arch/arm/mach-shmobile/intc-r8a7740.c + +diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile +index 6f44c51b..25d88900 100644 +--- a/arch/arm/mach-shmobile/Makefile ++++ b/arch/arm/mach-shmobile/Makefile +@@ -11,7 +11,7 @@ obj-y := timer.o console.o + obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o intc-sh7372.o + obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o intc-sh73a0.o + obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o +-obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o intc-r8a7740.o ++obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o + obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o + obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o intc-r8a7779.o + obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o +diff --git a/arch/arm/mach-shmobile/intc-r8a7740.c b/arch/arm/mach-shmobile/intc-r8a7740.c +deleted file mode 100644 +index 75193539..00000000 +--- a/arch/arm/mach-shmobile/intc-r8a7740.c ++++ /dev/null +@@ -1,54 +0,0 @@ +-/* +- * R8A7740 processor support +- * +- * Copyright (C) 2011 Renesas Solutions Corp. +- * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; version 2 of the License. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +- */ +- +-#include <linux/init.h> +-#include <linux/io.h> +-#include <linux/irqchip.h> +-#include <linux/irqchip/arm-gic.h> +- +-void __init r8a7740_init_irq_of(void) +-{ +- void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10); +- void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10); +- void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4); +- +- irqchip_init(); +- +- /* route signals to GIC */ +- iowrite32(0x0, pfc_inta_ctrl); +- +- /* +- * To mask the shared interrupt to SPI 149 we must ensure to set +- * PRIO *and* MASK. Else we run into IRQ floods when registering +- * the intc_irqpin devices +- */ +- iowrite32(0x0, intc_prio_base + 0x0); +- iowrite32(0x0, intc_prio_base + 0x4); +- iowrite32(0x0, intc_prio_base + 0x8); +- iowrite32(0x0, intc_prio_base + 0xc); +- iowrite8(0xff, intc_msk_base + 0x0); +- iowrite8(0xff, intc_msk_base + 0x4); +- iowrite8(0xff, intc_msk_base + 0x8); +- iowrite8(0xff, intc_msk_base + 0xc); +- +- iounmap(intc_prio_base); +- iounmap(intc_msk_base); +- iounmap(pfc_inta_ctrl); +-} +diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c +index 21026b34..b7d4b2c3 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7740.c ++++ b/arch/arm/mach-shmobile/setup-r8a7740.c +@@ -22,6 +22,8 @@ + #include <linux/kernel.h> + #include <linux/init.h> + #include <linux/io.h> ++#include <linux/irqchip.h> ++#include <linux/irqchip/arm-gic.h> + #include <linux/platform_data/irq-renesas-intc-irqpin.h> + #include <linux/platform_device.h> + #include <linux/of_platform.h> +@@ -1019,6 +1021,36 @@ void __init r8a7740_init_delay(void) + shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */ + }; + ++void __init r8a7740_init_irq_of(void) ++{ ++ void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10); ++ void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10); ++ void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4); ++ ++ irqchip_init(); ++ ++ /* route signals to GIC */ ++ iowrite32(0x0, pfc_inta_ctrl); ++ ++ /* ++ * To mask the shared interrupt to SPI 149 we must ensure to set ++ * PRIO *and* MASK. Else we run into IRQ floods when registering ++ * the intc_irqpin devices ++ */ ++ iowrite32(0x0, intc_prio_base + 0x0); ++ iowrite32(0x0, intc_prio_base + 0x4); ++ iowrite32(0x0, intc_prio_base + 0x8); ++ iowrite32(0x0, intc_prio_base + 0xc); ++ iowrite8(0xff, intc_msk_base + 0x0); ++ iowrite8(0xff, intc_msk_base + 0x4); ++ iowrite8(0xff, intc_msk_base + 0x8); ++ iowrite8(0xff, intc_msk_base + 0xc); ++ ++ iounmap(intc_prio_base); ++ iounmap(intc_msk_base); ++ iounmap(pfc_inta_ctrl); ++} ++ + static void __init r8a7740_generic_init(void) + { + r8a7740_clock_init(0); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0461-ARM-shmobile-r8a7779-move-r8a7779_init_irq_xxx-to-se.patch b/patches.renesas/0461-ARM-shmobile-r8a7779-move-r8a7779_init_irq_xxx-to-se.patch new file mode 100644 index 00000000000..974e4f09d92 --- /dev/null +++ b/patches.renesas/0461-ARM-shmobile-r8a7779-move-r8a7779_init_irq_xxx-to-se.patch @@ -0,0 +1,271 @@ +From be5afe19e89af3b13813fcdcac9d0f7653ed052a Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Thu, 1 Aug 2013 23:39:56 -0700 +Subject: ARM: shmobile: r8a7779: move r8a7779_init_irq_xxx() to setup + +This patch moves r8a7779_init_irq_xxx() to setup code, +and remove intc-r8a7779. + +Now, r8a7779_init_irq_extpin() uses +platform_device_register_resndata() instead of +platform_device_register() + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 5b3859d7b2c10419e1cc7ce6c456995e757f4390) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + arch/arm/mach-shmobile/Makefile +--- + arch/arm/mach-shmobile/Makefile | 2 +- + arch/arm/mach-shmobile/intc-r8a7779.c | 116 --------------------------------- + arch/arm/mach-shmobile/setup-r8a7779.c | 80 +++++++++++++++++++++++ + 3 files changed, 81 insertions(+), 117 deletions(-) + delete mode 100644 arch/arm/mach-shmobile/intc-r8a7779.c + +diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile +index 25d88900..c30867cc 100644 +--- a/arch/arm/mach-shmobile/Makefile ++++ b/arch/arm/mach-shmobile/Makefile +@@ -13,7 +13,7 @@ obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o intc-sh73a0.o + obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o + obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o + obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o +-obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o intc-r8a7779.o ++obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o + obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o + obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o + +diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c +deleted file mode 100644 +index e992a68b..00000000 +--- a/arch/arm/mach-shmobile/intc-r8a7779.c ++++ /dev/null +@@ -1,116 +0,0 @@ +-/* +- * r8a7779 processor support - INTC hardware block +- * +- * Copyright (C) 2011 Renesas Solutions Corp. +- * Copyright (C) 2011 Magnus Damm +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; version 2 of the License. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +- */ +-#include <linux/kernel.h> +-#include <linux/init.h> +-#include <linux/platform_device.h> +-#include <linux/interrupt.h> +-#include <linux/irq.h> +-#include <linux/io.h> +-#include <linux/irqchip/arm-gic.h> +-#include <linux/platform_data/irq-renesas-intc-irqpin.h> +-#include <linux/irqchip.h> +-#include <mach/common.h> +-#include <mach/irqs.h> +-#include <mach/r8a7779.h> +-#include <asm/mach-types.h> +-#include <asm/mach/arch.h> +- +-#define INT2SMSKCR0 IOMEM(0xfe7822a0) +-#define INT2SMSKCR1 IOMEM(0xfe7822a4) +-#define INT2SMSKCR2 IOMEM(0xfe7822a8) +-#define INT2SMSKCR3 IOMEM(0xfe7822ac) +-#define INT2SMSKCR4 IOMEM(0xfe7822b0) +- +-#define INT2NTSR0 IOMEM(0xfe700060) +-#define INT2NTSR1 IOMEM(0xfe700064) +- +-static struct renesas_intc_irqpin_config irqpin0_platform_data = { +- .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ +- .sense_bitfield_width = 2, +-}; +- +-static struct resource irqpin0_resources[] = { +- DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ +- DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ +- DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ +- DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ +- DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ +- DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */ +- DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */ +- DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */ +- DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */ +-}; +- +-static struct platform_device irqpin0_device = { +- .name = "renesas_intc_irqpin", +- .id = 0, +- .resource = irqpin0_resources, +- .num_resources = ARRAY_SIZE(irqpin0_resources), +- .dev = { +- .platform_data = &irqpin0_platform_data, +- }, +-}; +- +-void __init r8a7779_init_irq_extpin(int irlm) +-{ +- void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); +- unsigned long tmp; +- +- if (icr0) { +- tmp = ioread32(icr0); +- if (irlm) +- tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */ +- else +- tmp &= ~(1 << 23); /* IRL mode - not supported */ +- tmp |= (1 << 21); /* LVLMODE = 1 */ +- iowrite32(tmp, icr0); +- iounmap(icr0); +- +- if (irlm) +- platform_device_register(&irqpin0_device); +- } else +- pr_warn("r8a7779: unable to setup external irq pin mode\n"); +-} +- +-#ifdef CONFIG_OF +-static int r8a7779_set_wake(struct irq_data *data, unsigned int on) +-{ +- return 0; /* always allow wakeup */ +-} +- +-void __init r8a7779_init_irq_dt(void) +-{ +- gic_arch_extn.irq_set_wake = r8a7779_set_wake; +- +- irqchip_init(); +- +- /* route all interrupts to ARM */ +- __raw_writel(0xffffffff, INT2NTSR0); +- __raw_writel(0x3fffffff, INT2NTSR1); +- +- /* unmask all known interrupts in INTCS2 */ +- __raw_writel(0xfffffff0, INT2SMSKCR0); +- __raw_writel(0xfff7ffff, INT2SMSKCR1); +- __raw_writel(0xfffbffdf, INT2SMSKCR2); +- __raw_writel(0xbffffffc, INT2SMSKCR3); +- __raw_writel(0x003fee3f, INT2SMSKCR4); +- +-} +-#endif +diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c +index f0b6c7de..6a993339 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7779.c ++++ b/arch/arm/mach-shmobile/setup-r8a7779.c +@@ -22,8 +22,11 @@ + #include <linux/init.h> + #include <linux/interrupt.h> + #include <linux/irq.h> ++#include <linux/irqchip.h> ++#include <linux/irqchip/arm-gic.h> + #include <linux/of_platform.h> + #include <linux/platform_data/gpio-rcar.h> ++#include <linux/platform_data/irq-renesas-intc-irqpin.h> + #include <linux/platform_device.h> + #include <linux/delay.h> + #include <linux/input.h> +@@ -67,6 +70,60 @@ void __init r8a7779_map_io(void) + iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc)); + } + ++/* IRQ */ ++#define INT2SMSKCR0 IOMEM(0xfe7822a0) ++#define INT2SMSKCR1 IOMEM(0xfe7822a4) ++#define INT2SMSKCR2 IOMEM(0xfe7822a8) ++#define INT2SMSKCR3 IOMEM(0xfe7822ac) ++#define INT2SMSKCR4 IOMEM(0xfe7822b0) ++ ++#define INT2NTSR0 IOMEM(0xfe700060) ++#define INT2NTSR1 IOMEM(0xfe700064) ++ ++static struct renesas_intc_irqpin_config irqpin0_platform_data __initdata = { ++ .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ ++ .sense_bitfield_width = 2, ++}; ++ ++static struct resource irqpin0_resources[] __initdata = { ++ DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ ++ DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ ++ DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ ++ DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ ++ DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ ++ DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */ ++ DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */ ++ DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */ ++ DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */ ++}; ++ ++void __init r8a7779_init_irq_extpin(int irlm) ++{ ++ void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); ++ u32 tmp; ++ ++ if (!icr0) { ++ pr_warn("r8a7779: unable to setup external irq pin mode\n"); ++ return; ++ } ++ ++ tmp = ioread32(icr0); ++ if (irlm) ++ tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */ ++ else ++ tmp &= ~(1 << 23); /* IRL mode - not supported */ ++ tmp |= (1 << 21); /* LVLMODE = 1 */ ++ iowrite32(tmp, icr0); ++ iounmap(icr0); ++ ++ if (irlm) ++ platform_device_register_resndata( ++ &platform_bus, "renesas_intc_irqpin", -1, ++ irqpin0_resources, ARRAY_SIZE(irqpin0_resources), ++ &irqpin0_platform_data, sizeof(irqpin0_platform_data)); ++} ++ ++/* PFC/GPIO */ + static struct resource r8a7779_pfc_resources[] = { + DEFINE_RES_MEM(0xfffc0000, 0x023c), + }; +@@ -641,6 +698,29 @@ void __init r8a7779_init_late(void) + } + + #ifdef CONFIG_USE_OF ++static int r8a7779_set_wake(struct irq_data *data, unsigned int on) ++{ ++ return 0; /* always allow wakeup */ ++} ++ ++void __init r8a7779_init_irq_dt(void) ++{ ++ gic_arch_extn.irq_set_wake = r8a7779_set_wake; ++ ++ irqchip_init(); ++ ++ /* route all interrupts to ARM */ ++ __raw_writel(0xffffffff, INT2NTSR0); ++ __raw_writel(0x3fffffff, INT2NTSR1); ++ ++ /* unmask all known interrupts in INTCS2 */ ++ __raw_writel(0xfffffff0, INT2SMSKCR0); ++ __raw_writel(0xfff7ffff, INT2SMSKCR1); ++ __raw_writel(0xfffbffdf, INT2SMSKCR2); ++ __raw_writel(0xbffffffc, INT2SMSKCR3); ++ __raw_writel(0x003fee3f, INT2SMSKCR4); ++} ++ + void __init r8a7779_init_delay(void) + { + shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0462-ARM-shmobile-armadillo800eva-remove-nfsroot-settings.patch b/patches.renesas/0462-ARM-shmobile-armadillo800eva-remove-nfsroot-settings.patch new file mode 100644 index 00000000000..e6886554ad4 --- /dev/null +++ b/patches.renesas/0462-ARM-shmobile-armadillo800eva-remove-nfsroot-settings.patch @@ -0,0 +1,45 @@ +From 6649f5c17f0cd975568abf3cc662ce2179c37e23 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Mon, 5 Aug 2013 20:17:06 -0700 +Subject: ARM: shmobile: armadillo800eva: remove nfsroot settings from bootargs + +NFS detail settings like "nfsroot=,rsize=4096,wsize=4096" are no longer needed + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 3d814499ad80d7876d6d484e4d37fae79cb403c6) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts | 2 +- + arch/arm/boot/dts/r8a7740-armadillo800eva.dts | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +index 366f7298..c638e4ab 100644 +--- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts ++++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +@@ -17,7 +17,7 @@ + compatible = "renesas,armadillo800eva-reference", "renesas,r8a7740"; + + chosen { +- bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096 rw"; ++ bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw"; + }; + + memory { +diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts +index 93da655b..426cd9c3 100644 +--- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts ++++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts +@@ -16,7 +16,7 @@ + compatible = "renesas,armadillo800eva"; + + chosen { +- bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096 rw"; ++ bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw"; + }; + + memory { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0463-ARM-shmobile-kzm9d-remove-nfsroot-settings-from-boot.patch b/patches.renesas/0463-ARM-shmobile-kzm9d-remove-nfsroot-settings-from-boot.patch new file mode 100644 index 00000000000..94e93f3d2ca --- /dev/null +++ b/patches.renesas/0463-ARM-shmobile-kzm9d-remove-nfsroot-settings-from-boot.patch @@ -0,0 +1,44 @@ +From d6c4beb3c6ff439199a643bd173f2f1bd1175ef2 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Mon, 5 Aug 2013 20:17:33 -0700 +Subject: ARM: shmobile: kzm9d: remove nfsroot settings from bootargs + +NFS detail settings like "nfsroot=,rsize=4096,wsize=4096" are no longer needed + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 6de69131854501dcc9585d44087430584f8ccdf4) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/emev2-kzm9d-reference.dts | 2 +- + arch/arm/boot/dts/emev2-kzm9d.dts | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/emev2-kzm9d-reference.dts b/arch/arm/boot/dts/emev2-kzm9d-reference.dts +index bed676b9..cceefda2 100644 +--- a/arch/arm/boot/dts/emev2-kzm9d-reference.dts ++++ b/arch/arm/boot/dts/emev2-kzm9d-reference.dts +@@ -21,7 +21,7 @@ + }; + + chosen { +- bootargs = "console=ttyS1,115200n81 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096"; ++ bootargs = "console=ttyS1,115200n81 ignore_loglevel root=/dev/nfs ip=dhcp"; + }; + + reg_1p8v: regulator@0 { +diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts +index dda13bc0..f92e812f 100644 +--- a/arch/arm/boot/dts/emev2-kzm9d.dts ++++ b/arch/arm/boot/dts/emev2-kzm9d.dts +@@ -21,6 +21,6 @@ + }; + + chosen { +- bootargs = "console=ttyS1,115200n81 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096"; ++ bootargs = "console=ttyS1,115200n81 ignore_loglevel root=/dev/nfs ip=dhcp"; + }; + }; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0464-ARM-shmobile-sh73a0-Remove-global-GPIO_NR-definition.patch b/patches.renesas/0464-ARM-shmobile-sh73a0-Remove-global-GPIO_NR-definition.patch new file mode 100644 index 00000000000..c7ad140e06a --- /dev/null +++ b/patches.renesas/0464-ARM-shmobile-sh73a0-Remove-global-GPIO_NR-definition.patch @@ -0,0 +1,63 @@ +From c3a441172b4d1d2dca11583c4bfde0cbed085c55 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 29 Jul 2013 21:33:54 +0200 +Subject: ARM: shmobile: sh73a0: Remove global GPIO_NR definition + +The total number of SoC GPIOs is only used to compute the base GPIO +number of th PCF8575 GPIO extender on the KZM9G board. As GPIO +allocation became fully dynamic with DT, no other SH73A0 board will use +the GPIO_NR macro. Move it to the KZM9G board file. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 282b583f752f996ee5c33b0cdc18adf3b5094ee0) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-kzm9g.c | 16 ++++++++-------- + arch/arm/mach-shmobile/include/mach/sh73a0.h | 2 -- + 2 files changed, 8 insertions(+), 10 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c +index 165483c9..b30ef47d 100644 +--- a/arch/arm/mach-shmobile/board-kzm9g.c ++++ b/arch/arm/mach-shmobile/board-kzm9g.c +@@ -53,14 +53,14 @@ + /* + * external GPIO + */ +-#define GPIO_PCF8575_BASE (GPIO_NR) +-#define GPIO_PCF8575_PORT10 (GPIO_NR + 8) +-#define GPIO_PCF8575_PORT11 (GPIO_NR + 9) +-#define GPIO_PCF8575_PORT12 (GPIO_NR + 10) +-#define GPIO_PCF8575_PORT13 (GPIO_NR + 11) +-#define GPIO_PCF8575_PORT14 (GPIO_NR + 12) +-#define GPIO_PCF8575_PORT15 (GPIO_NR + 13) +-#define GPIO_PCF8575_PORT16 (GPIO_NR + 14) ++#define GPIO_PCF8575_BASE (310) ++#define GPIO_PCF8575_PORT10 (GPIO_PCF8575_BASE + 8) ++#define GPIO_PCF8575_PORT11 (GPIO_PCF8575_BASE + 9) ++#define GPIO_PCF8575_PORT12 (GPIO_PCF8575_BASE + 10) ++#define GPIO_PCF8575_PORT13 (GPIO_PCF8575_BASE + 11) ++#define GPIO_PCF8575_PORT14 (GPIO_PCF8575_BASE + 12) ++#define GPIO_PCF8575_PORT15 (GPIO_PCF8575_BASE + 13) ++#define GPIO_PCF8575_PORT16 (GPIO_PCF8575_BASE + 14) + + /* Dummy supplies, where voltage doesn't matter */ + static struct regulator_consumer_supply dummy_supplies[] = { +diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h +index 680dc5f1..359b582d 100644 +--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h ++++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h +@@ -1,8 +1,6 @@ + #ifndef __ASM_SH73A0_H__ + #define __ASM_SH73A0_H__ + +-#define GPIO_NR 310 +- + /* DMA slave IDs */ + enum { + SHDMA_SLAVE_INVALID, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0465-ARM-shmobile-Introduce-shared-SCU-SMP-boot-code.patch b/patches.renesas/0465-ARM-shmobile-Introduce-shared-SCU-SMP-boot-code.patch new file mode 100644 index 00000000000..0bb2460a6bd --- /dev/null +++ b/patches.renesas/0465-ARM-shmobile-Introduce-shared-SCU-SMP-boot-code.patch @@ -0,0 +1,77 @@ +From 5481c5987c45b2c5592b3665c130897c08ebef3e Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Wed, 31 Jul 2013 16:07:12 +0900 +Subject: ARM: shmobile: Introduce shared SCU SMP boot code + +Add SMP boot functions for SCU equipped mach-shmobile SoCs. + +At this point shmobile_smp_scu_prepare_cpus() controls the SCU and +installs boot fn and arg, while shmobile_smp_scu_boot_secondary() +currently does nothing. In the future the boot function and arg +install code will be reworked, so the empty function is ground +work for that. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit c970d4ef3ac6d56f5fd02902ad2ad80377c0bca1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/include/mach/common.h | 3 +++ + arch/arm/mach-shmobile/platsmp-scu.c | 31 ++++++++++++++++++++++++++++ + 2 files changed, 34 insertions(+) + create mode 100644 arch/arm/mach-shmobile/platsmp-scu.c + +diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h +index 18a76f91..08d7cacc 100644 +--- a/arch/arm/mach-shmobile/include/mach/common.h ++++ b/arch/arm/mach-shmobile/include/mach/common.h +@@ -10,6 +10,9 @@ extern void shmobile_boot_vector(void); + extern unsigned long shmobile_boot_fn; + extern unsigned long shmobile_boot_arg; + extern void shmobile_boot_scu(void); ++extern void shmobile_smp_scu_prepare_cpus(unsigned int max_cpus); ++extern int shmobile_smp_scu_boot_secondary(unsigned int cpu, ++ struct task_struct *idle); + struct clk; + extern int shmobile_clk_init(void); + extern void shmobile_handle_irq_intc(struct pt_regs *); +diff --git a/arch/arm/mach-shmobile/platsmp-scu.c b/arch/arm/mach-shmobile/platsmp-scu.c +new file mode 100644 +index 00000000..8f478e4d +--- /dev/null ++++ b/arch/arm/mach-shmobile/platsmp-scu.c +@@ -0,0 +1,31 @@ ++/* ++ * SMP support for SoCs with SCU covered by mach-shmobile ++ * ++ * Copyright (C) 2013 Magnus Damm ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++#include <linux/init.h> ++#include <linux/io.h> ++#include <linux/smp.h> ++#include <asm/smp_plat.h> ++#include <asm/smp_scu.h> ++#include <mach/common.h> ++ ++void __init shmobile_smp_scu_prepare_cpus(unsigned int max_cpus) ++{ ++ shmobile_boot_fn = virt_to_phys(shmobile_boot_scu); ++ shmobile_boot_arg = (unsigned long)shmobile_scu_base; ++ ++ /* enable SCU and cache coherency on booting CPU */ ++ scu_enable(shmobile_scu_base); ++ scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); ++} ++ ++int shmobile_smp_scu_boot_secondary(unsigned int cpu, struct task_struct *idle) ++{ ++ /* do nothing for now */ ++ return 0; ++} +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0466-ARM-shmobile-Use-shared-SCU-SMP-boot-code-on-sh73a0.patch b/patches.renesas/0466-ARM-shmobile-Use-shared-SCU-SMP-boot-code-on-sh73a0.patch new file mode 100644 index 00000000000..892a3973778 --- /dev/null +++ b/patches.renesas/0466-ARM-shmobile-Use-shared-SCU-SMP-boot-code-on-sh73a0.patch @@ -0,0 +1,80 @@ +From e7b8d48fe8d27bb35c03f110bb88ca7e82517d0b Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Wed, 31 Jul 2013 16:07:21 +0900 +Subject: ARM: shmobile: Use shared SCU SMP boot code on sh73a0 + +Use shared SCU code on sh73a0 for SMP boot. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 12eb8474386228c91e35be031d7c3eaa1318b5cf) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/Makefile | 2 +- + arch/arm/mach-shmobile/smp-sh73a0.c | 26 +++++++++++++------------- + 2 files changed, 14 insertions(+), 14 deletions(-) + +diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile +index c30867cc..af7c6ccb 100644 +--- a/arch/arm/mach-shmobile/Makefile ++++ b/arch/arm/mach-shmobile/Makefile +@@ -32,7 +32,7 @@ endif + + # SMP objects + smp-y := platsmp.o headsmp.o +-smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-scu.o ++smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-scu.o platsmp-scu.o + smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o headsmp-scu.o + smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o + +diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c +index 1b3dc7c1..1096b0eb 100644 +--- a/arch/arm/mach-shmobile/smp-sh73a0.c ++++ b/arch/arm/mach-shmobile/smp-sh73a0.c +@@ -50,30 +50,30 @@ void __init sh73a0_register_twd(void) + + static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle) + { +- cpu = cpu_logical_map(cpu); ++ unsigned int lcpu = cpu_logical_map(cpu); ++ int ret; + +- if (((__raw_readl(PSTR) >> (4 * cpu)) & 3) == 3) +- __raw_writel(1 << cpu, WUPCR); /* wake up */ ++ ret = shmobile_smp_scu_boot_secondary(cpu, idle); ++ if (ret) ++ return ret; ++ ++ if (((__raw_readl(PSTR) >> (4 * lcpu)) & 3) == 3) ++ __raw_writel(1 << lcpu, WUPCR); /* wake up */ + else +- __raw_writel(1 << cpu, SRESCR); /* reset */ ++ __raw_writel(1 << lcpu, SRESCR); /* reset */ + + return 0; + } + + static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) + { +- /* setup sh73a0 specific SCU base */ +- shmobile_scu_base = IOMEM(SH73A0_SCU_BASE); +- scu_enable(shmobile_scu_base); +- +- /* Map the reset vector (in headsmp-scu.S, headsmp.S) */ ++ /* Map the reset vector (in headsmp.S) */ + __raw_writel(0, APARMBAREA); /* 4k */ + __raw_writel(__pa(shmobile_boot_vector), SBAR); +- shmobile_boot_fn = virt_to_phys(shmobile_boot_scu); +- shmobile_boot_arg = (unsigned long)shmobile_scu_base; + +- /* enable cache coherency on booting CPU */ +- scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); ++ /* setup sh73a0 specific SCU bits */ ++ shmobile_scu_base = IOMEM(SH73A0_SCU_BASE); ++ shmobile_smp_scu_prepare_cpus(max_cpus); + } + + #ifdef CONFIG_HOTPLUG_CPU +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0467-ARM-shmobile-Use-shared-SCU-SMP-boot-code-on-r8a7779.patch b/patches.renesas/0467-ARM-shmobile-Use-shared-SCU-SMP-boot-code-on-r8a7779.patch new file mode 100644 index 00000000000..798214b774f --- /dev/null +++ b/patches.renesas/0467-ARM-shmobile-Use-shared-SCU-SMP-boot-code-on-r8a7779.patch @@ -0,0 +1,82 @@ +From 3540a0ddf4af5a4e1782baf21d9d9dd153f075ad Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Wed, 31 Jul 2013 16:07:31 +0900 +Subject: ARM: shmobile: Use shared SCU SMP boot code on r8a7779 + +Use shared SCU code on r8a7779 for SMP boot. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 0ca2894b5a9007091ad1a4d82b9f3132d4dd9410) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/Makefile | 2 +- + arch/arm/mach-shmobile/smp-r8a7779.c | 23 ++++++++++++----------- + 2 files changed, 13 insertions(+), 12 deletions(-) + +diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile +index af7c6ccb..1682b9d3 100644 +--- a/arch/arm/mach-shmobile/Makefile ++++ b/arch/arm/mach-shmobile/Makefile +@@ -33,7 +33,7 @@ endif + # SMP objects + smp-y := platsmp.o headsmp.o + smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-scu.o platsmp-scu.o +-smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o headsmp-scu.o ++smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o headsmp-scu.o platsmp-scu.o + smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o + + # IRQ objects +diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c +index bb3adae7..1963d0d4 100644 +--- a/arch/arm/mach-shmobile/smp-r8a7779.c ++++ b/arch/arm/mach-shmobile/smp-r8a7779.c +@@ -84,33 +84,34 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu) + static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle) + { + struct r8a7779_pm_ch *ch = NULL; +- int ret = -EIO; ++ unsigned int lcpu = cpu_logical_map(cpu); ++ int ret; + +- cpu = cpu_logical_map(cpu); ++ ret = shmobile_smp_scu_boot_secondary(cpu, idle); ++ if (ret) ++ return ret; + +- if (cpu < ARRAY_SIZE(r8a7779_ch_cpu)) +- ch = r8a7779_ch_cpu[cpu]; ++ if (lcpu < ARRAY_SIZE(r8a7779_ch_cpu)) ++ ch = r8a7779_ch_cpu[lcpu]; + + if (ch) + ret = r8a7779_sysc_power_up(ch); ++ else ++ ret = -EIO; + + return ret; + } + + static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) + { +- +- /* setup r8a7779 specific SCU base */ +- shmobile_scu_base = IOMEM(R8A7779_SCU_BASE); +- scu_enable(shmobile_scu_base); +- + /* Map the reset vector (in headsmp-scu.S, headsmp.S) */ + __raw_writel(__pa(shmobile_boot_vector), AVECR); + shmobile_boot_fn = virt_to_phys(shmobile_boot_scu); + shmobile_boot_arg = (unsigned long)shmobile_scu_base; + +- /* enable cache coherency on booting CPU */ +- scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); ++ /* setup r8a7779 specific SCU bits */ ++ shmobile_scu_base = IOMEM(R8A7779_SCU_BASE); ++ shmobile_smp_scu_prepare_cpus(max_cpus); + + r8a7779_pm_init(); + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0468-ARM-shmobile-Use-shared-SCU-SMP-boot-code-on-emev2.patch b/patches.renesas/0468-ARM-shmobile-Use-shared-SCU-SMP-boot-code-on-emev2.patch new file mode 100644 index 00000000000..5192f1582ba --- /dev/null +++ b/patches.renesas/0468-ARM-shmobile-Use-shared-SCU-SMP-boot-code-on-emev2.patch @@ -0,0 +1,75 @@ +From d8400d1035ed052c5beaf750e3381a75a1ac8798 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Wed, 31 Jul 2013 16:07:40 +0900 +Subject: ARM: shmobile: Use shared SCU SMP boot code on emev2 + +Use shared SCU code on emev2 for SMP boot. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 0da60225dee270a4a4b86c08509e772e78961b82) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/Makefile | 2 +- + arch/arm/mach-shmobile/smp-emev2.c | 19 ++++++++++--------- + 2 files changed, 11 insertions(+), 10 deletions(-) + +diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile +index 1682b9d3..2705bfa8 100644 +--- a/arch/arm/mach-shmobile/Makefile ++++ b/arch/arm/mach-shmobile/Makefile +@@ -34,7 +34,7 @@ endif + smp-y := platsmp.o headsmp.o + smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-scu.o platsmp-scu.o + smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o headsmp-scu.o platsmp-scu.o +-smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o ++smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o platsmp-scu.o + + # IRQ objects + obj-$(CONFIG_ARCH_SH7372) += entry-intc.o +diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c +index 1bf8bc7e..d1c101db 100644 +--- a/arch/arm/mach-shmobile/smp-emev2.c ++++ b/arch/arm/mach-shmobile/smp-emev2.c +@@ -34,6 +34,12 @@ + + static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle) + { ++ int ret; ++ ++ ret = shmobile_smp_scu_boot_secondary(cpu, idle); ++ if (ret) ++ return ret; ++ + arch_send_wakeup_ipi_mask(cpumask_of(cpu_logical_map(cpu))); + return 0; + } +@@ -42,21 +48,16 @@ static void __init emev2_smp_prepare_cpus(unsigned int max_cpus) + { + void __iomem *smu; + +- /* setup EMEV2 specific SCU base, enable */ +- shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE); +- scu_enable(shmobile_scu_base); +- +- /* Tell ROM loader about our vector (in headsmp-scu.S, headsmp.S) */ ++ /* Tell ROM loader about our vector (in headsmp.S) */ + smu = ioremap(EMEV2_SMU_BASE, PAGE_SIZE); + if (smu) { + iowrite32(__pa(shmobile_boot_vector), smu + SMU_GENERAL_REG0); + iounmap(smu); + } +- shmobile_boot_fn = virt_to_phys(shmobile_boot_scu); +- shmobile_boot_arg = (unsigned long)shmobile_scu_base; + +- /* enable cache coherency on booting CPU */ +- scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); ++ /* setup EMEV2 specific SCU bits */ ++ shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE); ++ shmobile_smp_scu_prepare_cpus(max_cpus); + } + + struct smp_operations emev2_smp_ops __initdata = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0469-ARM-shmobile-Add-shared-SCU-CPU-Hotplug-code.patch b/patches.renesas/0469-ARM-shmobile-Add-shared-SCU-CPU-Hotplug-code.patch new file mode 100644 index 00000000000..affcee42846 --- /dev/null +++ b/patches.renesas/0469-ARM-shmobile-Add-shared-SCU-CPU-Hotplug-code.patch @@ -0,0 +1,100 @@ +From ae7f732e421913a955120f5f221fd6917cd87fde Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Wed, 31 Jul 2013 16:07:49 +0900 +Subject: ARM: shmobile: Add shared SCU CPU Hotplug code + +Add CPU Hotplug functions for SCU equipped mach-shmobile SoCs. + +The functions shmobile_smp_scu_cpu_die() together with +shmobile_smp_scu_cpu_kill() perform basic shutdown and +allows checking of shutdown status. These are written +to work together with SMP boot code in headsmp-scu.S. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit e7b1c96384181d690950530f5a64167965226744) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/include/mach/common.h | 2 ++ + arch/arm/mach-shmobile/platsmp-scu.c | 45 ++++++++++++++++++++++++++++ + 2 files changed, 47 insertions(+) + +diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h +index 08d7cacc..2731dd71 100644 +--- a/arch/arm/mach-shmobile/include/mach/common.h ++++ b/arch/arm/mach-shmobile/include/mach/common.h +@@ -13,6 +13,8 @@ extern void shmobile_boot_scu(void); + extern void shmobile_smp_scu_prepare_cpus(unsigned int max_cpus); + extern int shmobile_smp_scu_boot_secondary(unsigned int cpu, + struct task_struct *idle); ++extern void shmobile_smp_scu_cpu_die(unsigned int cpu); ++extern int shmobile_smp_scu_cpu_kill(unsigned int cpu); + struct clk; + extern int shmobile_clk_init(void); + extern void shmobile_handle_irq_intc(struct pt_regs *); +diff --git a/arch/arm/mach-shmobile/platsmp-scu.c b/arch/arm/mach-shmobile/platsmp-scu.c +index 8f478e4d..7a0c066d 100644 +--- a/arch/arm/mach-shmobile/platsmp-scu.c ++++ b/arch/arm/mach-shmobile/platsmp-scu.c +@@ -7,9 +7,11 @@ + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ ++#include <linux/delay.h> + #include <linux/init.h> + #include <linux/io.h> + #include <linux/smp.h> ++#include <asm/cacheflush.h> + #include <asm/smp_plat.h> + #include <asm/smp_scu.h> + #include <mach/common.h> +@@ -29,3 +31,46 @@ int shmobile_smp_scu_boot_secondary(unsigned int cpu, struct task_struct *idle) + /* do nothing for now */ + return 0; + } ++ ++#ifdef CONFIG_HOTPLUG_CPU ++void shmobile_smp_scu_cpu_die(unsigned int cpu) ++{ ++ dsb(); ++ flush_cache_all(); ++ ++ /* disable cache coherency */ ++ scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF); ++ ++ /* Endless loop until reset */ ++ while (1) ++ cpu_do_idle(); ++} ++ ++static int shmobile_smp_scu_psr_core_disabled(int cpu) ++{ ++ unsigned long mask = SCU_PM_POWEROFF << (cpu * 8); ++ ++ if ((__raw_readl(shmobile_scu_base + 8) & mask) == mask) ++ return 1; ++ ++ return 0; ++} ++ ++int shmobile_smp_scu_cpu_kill(unsigned int cpu) ++{ ++ int k; ++ ++ /* this function is running on another CPU than the offline target, ++ * here we need wait for shutdown code in platform_cpu_die() to ++ * finish before asking SoC-specific code to power off the CPU core. ++ */ ++ for (k = 0; k < 1000; k++) { ++ if (shmobile_smp_scu_psr_core_disabled(cpu)) ++ return 1; ++ ++ mdelay(1); ++ } ++ ++ return 0; ++} ++#endif +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0470-ARM-shmobile-Use-shared-SCU-CPU-Hotplug-code-on-sh73.patch b/patches.renesas/0470-ARM-shmobile-Use-shared-SCU-CPU-Hotplug-code-on-sh73.patch new file mode 100644 index 00000000000..79e2b8e4447 --- /dev/null +++ b/patches.renesas/0470-ARM-shmobile-Use-shared-SCU-CPU-Hotplug-code-on-sh73.patch @@ -0,0 +1,99 @@ +From 3d30ea697e0684c8780cad1e8d0f86f6ee137e53 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Wed, 31 Jul 2013 16:07:59 +0900 +Subject: ARM: shmobile: Use shared SCU CPU Hotplug code on sh73a0 + +Update the sh73a0 specific CPU Hotplug code to make use of +the recently introduced shared SCU functions. The sh73a0 +power control hardware relies on SCU_PM_POWEROFF with WFI +so the shared SCU code will as-is power down the hardware +as expected. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 352e57a3af195825767d0f638cb9ec3517f93de4) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/smp-sh73a0.c | 41 +++---------------------------------- + 1 file changed, 3 insertions(+), 38 deletions(-) + +diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c +index 1096b0eb..8b3b9777 100644 +--- a/arch/arm/mach-shmobile/smp-sh73a0.c ++++ b/arch/arm/mach-shmobile/smp-sh73a0.c +@@ -20,14 +20,11 @@ + #include <linux/kernel.h> + #include <linux/init.h> + #include <linux/smp.h> +-#include <linux/spinlock.h> + #include <linux/io.h> + #include <linux/delay.h> + #include <mach/common.h> +-#include <asm/cacheflush.h> +-#include <asm/smp_plat.h> + #include <mach/sh73a0.h> +-#include <asm/smp_scu.h> ++#include <asm/smp_plat.h> + #include <asm/smp_twd.h> + + #define WUPCR IOMEM(0xe6151010) +@@ -36,8 +33,6 @@ + #define SBAR IOMEM(0xe6180020) + #define APARMBAREA IOMEM(0xe6f10020) + +-#define PSTR_SHUTDOWN_MODE 3 +- + #define SH73A0_SCU_BASE 0xf0000000 + + #ifdef CONFIG_HAVE_ARM_TWD +@@ -77,36 +72,6 @@ static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) + } + + #ifdef CONFIG_HOTPLUG_CPU +-static int sh73a0_cpu_kill(unsigned int cpu) +-{ +- +- int k; +- u32 pstr; +- +- /* +- * wait until the power status register confirms the shutdown of the +- * offline target +- */ +- for (k = 0; k < 1000; k++) { +- pstr = (__raw_readl(PSTR) >> (4 * cpu)) & 3; +- if (pstr == PSTR_SHUTDOWN_MODE) +- return 1; +- +- mdelay(1); +- } +- +- return 0; +-} +- +-static void sh73a0_cpu_die(unsigned int cpu) +-{ +- /* Set power off mode. This takes the CPU out of the MP cluster */ +- scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF); +- +- /* Enter shutdown mode */ +- cpu_do_idle(); +-} +- + static int sh73a0_cpu_disable(unsigned int cpu) + { + return 0; /* CPU0 and CPU1 supported */ +@@ -117,8 +82,8 @@ struct smp_operations sh73a0_smp_ops __initdata = { + .smp_prepare_cpus = sh73a0_smp_prepare_cpus, + .smp_boot_secondary = sh73a0_boot_secondary, + #ifdef CONFIG_HOTPLUG_CPU +- .cpu_kill = sh73a0_cpu_kill, +- .cpu_die = sh73a0_cpu_die, + .cpu_disable = sh73a0_cpu_disable, ++ .cpu_die = shmobile_smp_scu_cpu_die, ++ .cpu_kill = shmobile_smp_scu_cpu_kill, + #endif + }; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0471-ARM-shmobile-Use-shared-SCU-CPU-Hotplug-code-on-r8a7.patch b/patches.renesas/0471-ARM-shmobile-Use-shared-SCU-CPU-Hotplug-code-on-r8a7.patch new file mode 100644 index 00000000000..264f15d99c6 --- /dev/null +++ b/patches.renesas/0471-ARM-shmobile-Use-shared-SCU-CPU-Hotplug-code-on-r8a7.patch @@ -0,0 +1,86 @@ +From 10b1cbc230430b5fc09df5ec5c7c78a0643b928d Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Wed, 31 Jul 2013 16:08:09 +0900 +Subject: ARM: shmobile: Use shared SCU CPU Hotplug code on r8a7779 + +Update the r8a7779 specific CPU Hotplug code to make use of +the recently introduced shared SCU functions. The r8a7779 +power domain hardware requires special power down handling +at ->kill() time. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit e9e7c4fbf468e205387b21463dddacfe44da2d9a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/smp-r8a7779.c | 41 ++++-------------------------------- + 1 file changed, 4 insertions(+), 37 deletions(-) + +diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c +index 1963d0d4..c159964e 100644 +--- a/arch/arm/mach-shmobile/smp-r8a7779.c ++++ b/arch/arm/mach-shmobile/smp-r8a7779.c +@@ -122,47 +122,14 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) + } + + #ifdef CONFIG_HOTPLUG_CPU +-static int r8a7779_scu_psr_core_disabled(int cpu) +-{ +- unsigned long mask = 3 << (cpu * 8); +- +- if ((__raw_readl(shmobile_scu_base + 8) & mask) == mask) +- return 1; +- +- return 0; +-} +- + static int r8a7779_cpu_kill(unsigned int cpu) + { +- int k; +- +- /* this function is running on another CPU than the offline target, +- * here we need wait for shutdown code in platform_cpu_die() to +- * finish before asking SoC-specific code to power off the CPU core. +- */ +- for (k = 0; k < 1000; k++) { +- if (r8a7779_scu_psr_core_disabled(cpu)) +- return r8a7779_platform_cpu_kill(cpu); +- +- mdelay(1); +- } ++ if (shmobile_smp_scu_cpu_kill(cpu)) ++ return r8a7779_platform_cpu_kill(cpu); + + return 0; + } + +-static void r8a7779_cpu_die(unsigned int cpu) +-{ +- dsb(); +- flush_cache_all(); +- +- /* disable cache coherency */ +- scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF); +- +- /* Endless loop until power off from r8a7779_cpu_kill() */ +- while (1) +- cpu_do_idle(); +-} +- + static int r8a7779_cpu_disable(unsigned int cpu) + { + /* only CPU1->3 have power domains, do not allow hotplug of CPU0 */ +@@ -174,8 +141,8 @@ struct smp_operations r8a7779_smp_ops __initdata = { + .smp_prepare_cpus = r8a7779_smp_prepare_cpus, + .smp_boot_secondary = r8a7779_boot_secondary, + #ifdef CONFIG_HOTPLUG_CPU +- .cpu_kill = r8a7779_cpu_kill, +- .cpu_die = r8a7779_cpu_die, + .cpu_disable = r8a7779_cpu_disable, ++ .cpu_die = shmobile_smp_scu_cpu_die, ++ .cpu_kill = r8a7779_cpu_kill, + #endif + }; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0472-ARM-shmobile-Introduce-per-CPU-SMP-boot-sleep-code.patch b/patches.renesas/0472-ARM-shmobile-Introduce-per-CPU-SMP-boot-sleep-code.patch new file mode 100644 index 00000000000..da3f0db28c3 --- /dev/null +++ b/patches.renesas/0472-ARM-shmobile-Introduce-per-CPU-SMP-boot-sleep-code.patch @@ -0,0 +1,137 @@ +From 53bc71f8c9ec057982e54804e0bab75e34f33d38 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Thu, 1 Aug 2013 03:38:18 +0900 +Subject: ARM: shmobile: Introduce per-CPU SMP boot / sleep code + +Add per-CPU SMP boot / sleep code that can be used by all +SoCs included in mach-shmobile. + +The boot code reads out the per-CPU MPIDR id value and +matches it with the value stored for any CPU number, and +if there is a match and the boot function is set as well +then the boot function will be executed. + +The sleep code simply uses WFI and then jumps back to the +boot code to see if anyone has asked to wake up that CPU, +if not it will sleep again. + +Signed-off-by: Magnus Damm <damm@opensource.se> +[horms+renesas@verge.net.au: Remove trailing whitespace] +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit cc61591e45c0457139ddd4cd7e57f75928acaaf2) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/headsmp.S | 49 ++++++++++++++++++++++++++++ + arch/arm/mach-shmobile/include/mach/common.h | 4 +++ + arch/arm/mach-shmobile/platsmp.c | 18 ++++++++++ + 3 files changed, 71 insertions(+) + +diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S +index dfb41dfc..a8cabee4 100644 +--- a/arch/arm/mach-shmobile/headsmp.S ++++ b/arch/arm/mach-shmobile/headsmp.S +@@ -42,3 +42,52 @@ shmobile_boot_fn: + .globl shmobile_boot_arg + shmobile_boot_arg: + 2: .space 4 ++ ++/* ++ * Per-CPU SMP boot function/argument selection code based on MPIDR ++ */ ++ ++ENTRY(shmobile_smp_boot) ++ @ r0 = MPIDR_HWID_BITMASK ++ mrc p15, 0, r1, c0, c0, 5 @ r1 = MPIDR ++ and r0, r1, r0 @ r0 = cpu_logical_map() value ++ mov r1, #0 @ r1 = CPU index ++ adr r5, 1f @ array of per-cpu mpidr values ++ adr r6, 2f @ array of per-cpu functions ++ adr r7, 3f @ array of per-cpu arguments ++ ++shmobile_smp_boot_find_mpidr: ++ ldr r8, [r5, r1, lsl #2] ++ cmp r8, r0 ++ bne shmobile_smp_boot_next ++ ++ ldr r9, [r6, r1, lsl #2] ++ cmp r9, #0 ++ bne shmobile_smp_boot_found ++ ++shmobile_smp_boot_next: ++ add r1, r1, #1 ++ cmp r1, #CONFIG_NR_CPUS ++ blo shmobile_smp_boot_find_mpidr ++ ++ b shmobile_smp_sleep ++ ++shmobile_smp_boot_found: ++ ldr r0, [r7, r1, lsl #2] ++ mov pc, r9 ++ENDPROC(shmobile_smp_boot) ++ ++ENTRY(shmobile_smp_sleep) ++ wfi ++ b shmobile_smp_boot ++ENDPROC(shmobile_smp_sleep) ++ ++ .globl shmobile_smp_mpidr ++shmobile_smp_mpidr: ++1: .space CONFIG_NR_CPUS * 4 ++ .globl shmobile_smp_fn ++shmobile_smp_fn: ++2: .space CONFIG_NR_CPUS * 4 ++ .globl shmobile_smp_arg ++shmobile_smp_arg: ++3: .space CONFIG_NR_CPUS * 4 +diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h +index 2731dd71..7b938681 100644 +--- a/arch/arm/mach-shmobile/include/mach/common.h ++++ b/arch/arm/mach-shmobile/include/mach/common.h +@@ -9,6 +9,10 @@ extern void shmobile_setup_console(void); + extern void shmobile_boot_vector(void); + extern unsigned long shmobile_boot_fn; + extern unsigned long shmobile_boot_arg; ++extern void shmobile_smp_boot(void); ++extern void shmobile_smp_sleep(void); ++extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn, ++ unsigned long arg); + extern void shmobile_boot_scu(void); + extern void shmobile_smp_scu_prepare_cpus(unsigned int max_cpus); + extern int shmobile_smp_scu_boot_secondary(unsigned int cpu, +diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c +index 1f958d7b..d4ae616b 100644 +--- a/arch/arm/mach-shmobile/platsmp.c ++++ b/arch/arm/mach-shmobile/platsmp.c +@@ -12,6 +12,9 @@ + */ + #include <linux/init.h> + #include <linux/smp.h> ++#include <asm/cacheflush.h> ++#include <asm/smp_plat.h> ++#include <mach/common.h> + + void __init shmobile_smp_init_cpus(unsigned int ncores) + { +@@ -26,3 +29,18 @@ void __init shmobile_smp_init_cpus(unsigned int ncores) + for (i = 0; i < ncores; i++) + set_cpu_possible(i, true); + } ++ ++extern unsigned long shmobile_smp_fn[]; ++extern unsigned long shmobile_smp_arg[]; ++extern unsigned long shmobile_smp_mpidr[]; ++ ++void shmobile_smp_hook(unsigned int cpu, unsigned long fn, unsigned long arg) ++{ ++ shmobile_smp_fn[cpu] = 0; ++ flush_cache_all(); ++ ++ shmobile_smp_mpidr[cpu] = cpu_logical_map(cpu); ++ shmobile_smp_fn[cpu] = fn; ++ shmobile_smp_arg[cpu] = arg; ++ flush_cache_all(); ++} +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0473-ARM-shmobile-Per-CPU-SMP-boot-sleep-code-for-SCU-SoC.patch b/patches.renesas/0473-ARM-shmobile-Per-CPU-SMP-boot-sleep-code-for-SCU-SoC.patch new file mode 100644 index 00000000000..94cf95bcfcc --- /dev/null +++ b/patches.renesas/0473-ARM-shmobile-Per-CPU-SMP-boot-sleep-code-for-SCU-SoC.patch @@ -0,0 +1,69 @@ +From 48fff0acf4211af07e5f7cf4fe66d695ec7628f2 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm@opensource.se> +Date: Thu, 1 Aug 2013 03:38:27 +0900 +Subject: ARM: shmobile: Per-CPU SMP boot / sleep code for SCU SoCs + +Hook in the per-CPU boot and sleep code in the shared +mach-shmobile SCU code. CPUs may be kept in the asm +routine until ->boot_secondary() when the per-CPU +boot vector is installed. At the end of ->die() the +asm sleep routine is invoked. + +Signed-off-by: Magnus Damm <damm@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 1d33a354bbb618ba578bb372ebc18fe58457f6f3) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/platsmp-scu.c | 17 +++++++++++------ + 1 file changed, 11 insertions(+), 6 deletions(-) + +diff --git a/arch/arm/mach-shmobile/platsmp-scu.c b/arch/arm/mach-shmobile/platsmp-scu.c +index 7a0c066d..c96f5016 100644 +--- a/arch/arm/mach-shmobile/platsmp-scu.c ++++ b/arch/arm/mach-shmobile/platsmp-scu.c +@@ -18,8 +18,9 @@ + + void __init shmobile_smp_scu_prepare_cpus(unsigned int max_cpus) + { +- shmobile_boot_fn = virt_to_phys(shmobile_boot_scu); +- shmobile_boot_arg = (unsigned long)shmobile_scu_base; ++ /* install boot code shared by all CPUs */ ++ shmobile_boot_fn = virt_to_phys(shmobile_smp_boot); ++ shmobile_boot_arg = MPIDR_HWID_BITMASK; + + /* enable SCU and cache coherency on booting CPU */ + scu_enable(shmobile_scu_base); +@@ -28,22 +29,26 @@ void __init shmobile_smp_scu_prepare_cpus(unsigned int max_cpus) + + int shmobile_smp_scu_boot_secondary(unsigned int cpu, struct task_struct *idle) + { +- /* do nothing for now */ ++ /* For this particular CPU register SCU boot vector */ ++ shmobile_smp_hook(cpu, virt_to_phys(shmobile_boot_scu), ++ (unsigned long)shmobile_scu_base); + return 0; + } + + #ifdef CONFIG_HOTPLUG_CPU + void shmobile_smp_scu_cpu_die(unsigned int cpu) + { ++ /* For this particular CPU deregister boot vector */ ++ shmobile_smp_hook(cpu, 0, 0); ++ + dsb(); + flush_cache_all(); + + /* disable cache coherency */ + scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF); + +- /* Endless loop until reset */ +- while (1) +- cpu_do_idle(); ++ /* jump to shared mach-shmobile sleep / reset code */ ++ shmobile_smp_sleep(); + } + + static int shmobile_smp_scu_psr_core_disabled(int cpu) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0474-ARM-shmobile-ape6evm-support-GPIO-switches.patch b/patches.renesas/0474-ARM-shmobile-ape6evm-support-GPIO-switches.patch new file mode 100644 index 00000000000..291660f8f23 --- /dev/null +++ b/patches.renesas/0474-ARM-shmobile-ape6evm-support-GPIO-switches.patch @@ -0,0 +1,67 @@ +From 5abcb2fab84d9514f3a009d65ed997e1af986955 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Tue, 30 Jul 2013 10:59:00 +0900 +Subject: ARM: shmobile: ape6evm: support GPIO switches + +The ape6evm board has switches S16 - S23 wired up to GPIO pins. +This patch allows access to those pins as gpio-keys. + +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 5c6db1a421c6ceef199a956c7e0c1244ea6dfef7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-ape6evm.c | 23 +++++++++++++++++++++++ + 1 file changed, 23 insertions(+) + +diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c +index 7f3d85bc..19394286 100644 +--- a/arch/arm/mach-shmobile/board-ape6evm.c ++++ b/arch/arm/mach-shmobile/board-ape6evm.c +@@ -19,6 +19,8 @@ + */ + + #include <linux/gpio.h> ++#include <linux/gpio_keys.h> ++#include <linux/input.h> + #include <linux/interrupt.h> + #include <linux/kernel.h> + #include <linux/mfd/tmio.h> +@@ -37,6 +39,24 @@ + #include <asm/mach-types.h> + #include <asm/mach/arch.h> + ++/* GPIO KEY */ ++#define GPIO_KEY(c, g, d, ...) \ ++ { .code = c, .gpio = g, .desc = d, .active_low = 1 } ++ ++static struct gpio_keys_button gpio_buttons[] = { ++ GPIO_KEY(KEY_0, 324, "S16"), ++ GPIO_KEY(KEY_MENU, 325, "S17"), ++ GPIO_KEY(KEY_HOME, 326, "S18"), ++ GPIO_KEY(KEY_BACK, 327, "S19"), ++ GPIO_KEY(KEY_VOLUMEUP, 328, "S20"), ++ GPIO_KEY(KEY_VOLUMEDOWN, 329, "S21"), ++}; ++ ++static struct __initdata gpio_keys_platform_data ape6evm_keys_pdata = { ++ .buttons = gpio_buttons, ++ .nbuttons = ARRAY_SIZE(gpio_buttons), ++}; ++ + /* Dummy supplies, where voltage doesn't matter */ + static struct regulator_consumer_supply dummy_supplies[] = { + REGULATOR_SUPPLY("vddvario", "smsc911x"), +@@ -172,6 +192,9 @@ static void __init ape6evm_add_standard_devices(void) + platform_device_register_resndata(&platform_bus, "sh_mobile_sdhi", 1, + sdhi1_resources, ARRAY_SIZE(sdhi1_resources), + &sdhi1_pdata, sizeof(sdhi1_pdata)); ++ platform_device_register_data(&platform_bus, "gpio-keys", -1, ++ &ape6evm_keys_pdata, ++ sizeof(ape6evm_keys_pdata)); + } + + static const char *ape6evm_boards_compat_dt[] __initdata = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0475-ARM-shmobile-ape6evm-Add-GPIO-LEDs.patch b/patches.renesas/0475-ARM-shmobile-ape6evm-Add-GPIO-LEDs.patch new file mode 100644 index 00000000000..a833a4d41b9 --- /dev/null +++ b/patches.renesas/0475-ARM-shmobile-ape6evm-Add-GPIO-LEDs.patch @@ -0,0 +1,74 @@ +From eb0a75cb81fae8eea8edab7df90c3d4e5c3ee82f Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Tue, 30 Jul 2013 10:59:02 +0900 +Subject: ARM: shmobile: ape6evm: Add GPIO LEDs + +The board has 6 LEDs connected to GPIOs. Add a led-gpio device to +support them. + +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 9adad788583c735eb14ddd5cca79a4e2ca2d707c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-ape6evm.c | 37 ++++++++++++++++++++++++++++++++++ + 1 file changed, 37 insertions(+) + +diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c +index 19394286..24b87eea 100644 +--- a/arch/arm/mach-shmobile/board-ape6evm.c ++++ b/arch/arm/mach-shmobile/board-ape6evm.c +@@ -39,6 +39,40 @@ + #include <asm/mach-types.h> + #include <asm/mach/arch.h> + ++/* LEDS */ ++static struct gpio_led ape6evm_leds[] = { ++ { ++ .name = "gnss-en", ++ .gpio = 28, ++ .default_state = LEDS_GPIO_DEFSTATE_OFF, ++ }, { ++ .name = "nfc-nrst", ++ .gpio = 126, ++ .default_state = LEDS_GPIO_DEFSTATE_OFF, ++ }, { ++ .name = "gnss-nrst", ++ .gpio = 132, ++ .default_state = LEDS_GPIO_DEFSTATE_OFF, ++ }, { ++ .name = "bt-wakeup", ++ .gpio = 232, ++ .default_state = LEDS_GPIO_DEFSTATE_OFF, ++ }, { ++ .name = "strobe", ++ .gpio = 250, ++ .default_state = LEDS_GPIO_DEFSTATE_OFF, ++ }, { ++ .name = "bbresetout", ++ .gpio = 288, ++ .default_state = LEDS_GPIO_DEFSTATE_OFF, ++ }, ++}; ++ ++static __initdata struct gpio_led_platform_data ape6evm_leds_pdata = { ++ .leds = ape6evm_leds, ++ .num_leds = ARRAY_SIZE(ape6evm_leds), ++}; ++ + /* GPIO KEY */ + #define GPIO_KEY(c, g, d, ...) \ + { .code = c, .gpio = g, .desc = d, .active_low = 1 } +@@ -195,6 +229,9 @@ static void __init ape6evm_add_standard_devices(void) + platform_device_register_data(&platform_bus, "gpio-keys", -1, + &ape6evm_keys_pdata, + sizeof(ape6evm_keys_pdata)); ++ platform_device_register_data(&platform_bus, "leds-gpio", -1, ++ &ape6evm_leds_pdata, ++ sizeof(ape6evm_leds_pdata)); + } + + static const char *ape6evm_boards_compat_dt[] __initdata = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0476-ARM-shmobile-lager-enable-Ether.patch b/patches.renesas/0476-ARM-shmobile-lager-enable-Ether.patch new file mode 100644 index 00000000000..5c6285f8b0c --- /dev/null +++ b/patches.renesas/0476-ARM-shmobile-lager-enable-Ether.patch @@ -0,0 +1,77 @@ +From 5513c831f7f4e16340e1ea0dee037ef1fbf5a833 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Tue, 6 Aug 2013 16:50:10 +0900 +Subject: ARM: shmobile: lager: enable Ether + +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 4901e136aa5c35873701156c4c0af5b3c2c8faee) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-lager.c | 29 +++++++++++++++++++++++++++++ + 1 file changed, 29 insertions(+) + +diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c +index aa8be240..4872939c 100644 +--- a/arch/arm/mach-shmobile/board-lager.c ++++ b/arch/arm/mach-shmobile/board-lager.c +@@ -31,6 +31,7 @@ + #include <linux/platform_device.h> + #include <linux/regulator/fixed.h> + #include <linux/regulator/machine.h> ++#include <linux/sh_eth.h> + #include <mach/common.h> + #include <mach/irqs.h> + #include <mach/r8a7790.h> +@@ -91,6 +92,20 @@ static struct resource mmcif1_resources[] __initdata = { + DEFINE_RES_IRQ(gic_spi(170)), + }; + ++/* Ether */ ++static struct sh_eth_plat_data ether_pdata __initdata = { ++ .phy = 0x1, ++ .edmac_endian = EDMAC_LITTLE_ENDIAN, ++ .register_type = SH_ETH_REG_FAST_RCAR, ++ .phy_interface = PHY_INTERFACE_MODE_RMII, ++ .ether_link_active_low = 1, ++}; ++ ++static struct resource ether_resources[] __initdata = { ++ DEFINE_RES_MEM(0xee700000, 0x400), ++ DEFINE_RES_IRQ(gic_spi(162)), ++}; ++ + static const struct pinctrl_map lager_pinctrl_map[] = { + /* SCIF0 (CN19: DEBUG SERIAL0) */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790", +@@ -103,6 +118,15 @@ static const struct pinctrl_map lager_pinctrl_map[] = { + "mmc1_data8", "mmc1"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.1", "pfc-r8a7790", + "mmc1_ctrl", "mmc1"), ++ /* Ether */ ++ PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790", ++ "eth_link", "eth"), ++ PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790", ++ "eth_mdio", "eth"), ++ PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790", ++ "eth_rmii", "eth"), ++ PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790", ++ "intc_irq0", "intc"), + }; + + static void __init lager_add_standard_devices(void) +@@ -125,6 +149,11 @@ static void __init lager_add_standard_devices(void) + platform_device_register_resndata(&platform_bus, "sh_mmcif", 1, + mmcif1_resources, ARRAY_SIZE(mmcif1_resources), + &mmcif1_pdata, sizeof(mmcif1_pdata)); ++ ++ platform_device_register_resndata(&platform_bus, "r8a7790-ether", -1, ++ ether_resources, ++ ARRAY_SIZE(ether_resources), ++ ðer_pdata, sizeof(ether_pdata)); + } + + static const char *lager_boards_compat_dt[] __initdata = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0477-media-ARM-shmobile-r8a7778-add-VIN-support.patch b/patches.renesas/0477-media-ARM-shmobile-r8a7778-add-VIN-support.patch new file mode 100644 index 00000000000..0579aeb89b2 --- /dev/null +++ b/patches.renesas/0477-media-ARM-shmobile-r8a7778-add-VIN-support.patch @@ -0,0 +1,124 @@ +From b103f1c92961ce58578d075876d16a06fd7504c1 Mon Sep 17 00:00:00 2001 +From: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Date: Thu, 22 Aug 2013 17:36:36 -0300 +Subject: [media] ARM: shmobile: r8a7778: add VIN support + +Add VIN clocks and platform devices on R8A7778 SoC; add function to register +the VIN platform devices. +[Sergei: added 'id' parameter check to r8a7778_add_vin_device(), used '*pdata' +in *sizeof* operator, and added an empty line there; renamed some variables, +annotated 'vin[01]_info' and vin[01]_resources[] as '__initdata'.] + +Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com> +(cherry picked from commit 803c2df217525495fc440fc9b314b22427dc5db6) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + arch/arm/mach-shmobile/clock-r8a7778.c + arch/arm/mach-shmobile/include/mach/r8a7778.h + arch/arm/mach-shmobile/setup-r8a7778.c +--- + arch/arm/mach-shmobile/clock-r8a7778.c | 5 ++++ + arch/arm/mach-shmobile/include/mach/r8a7778.h | 3 +++ + arch/arm/mach-shmobile/setup-r8a7778.c | 34 +++++++++++++++++++++++++++ + 3 files changed, 42 insertions(+) + +diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c +index 53798e50..dea199d4 100644 +--- a/arch/arm/mach-shmobile/clock-r8a7778.c ++++ b/arch/arm/mach-shmobile/clock-r8a7778.c +@@ -106,6 +106,7 @@ enum { + MSTP331, + MSTP323, MSTP322, MSTP321, + MSTP114, ++ MSTP110, MSTP109, + MSTP100, + MSTP030, + MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, +@@ -119,6 +120,8 @@ static struct clk mstp_clks[MSTP_NR] = { + [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */ + [MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */ + [MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */ ++ [MSTP110] = SH_CLK_MSTP32(&s_clk, MSTPCR1, 10, 0), /* VIN0 */ ++ [MSTP109] = SH_CLK_MSTP32(&s_clk, MSTPCR1, 9, 0), /* VIN1 */ + [MSTP100] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 0, 0), /* USB0/1 */ + [MSTP030] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 30, 0), /* I2C0 */ + [MSTP029] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 29, 0), /* I2C1 */ +@@ -146,6 +149,8 @@ static struct clk_lookup lookups[] = { + CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ + CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ + CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */ ++ CLKDEV_DEV_ID("r8a7778-vin.0", &mstp_clks[MSTP110]), /* VIN0 */ ++ CLKDEV_DEV_ID("r8a7778-vin.1", &mstp_clks[MSTP109]), /* VIN1 */ + CLKDEV_DEV_ID("ehci-platform", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */ + CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */ + CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */ +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h +index 41fd6da2..adfcf51b 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h +@@ -19,10 +19,13 @@ + #define __ASM_R8A7778_H__ + + #include <linux/sh_eth.h> ++#include <linux/platform_data/camera-rcar.h> + + extern void r8a7778_add_standard_devices(void); + extern void r8a7778_add_standard_devices_dt(void); + extern void r8a7778_add_ether_device(struct sh_eth_plat_data *pdata); ++extern void r8a7778_add_vin_device(int id, ++ struct rcar_vin_platform_data *pdata); + extern void r8a7778_add_dt_devices(void); + + extern void r8a7778_init_late(void); +diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c +index 604cf36b..6a2657eb 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7778.c ++++ b/arch/arm/mach-shmobile/setup-r8a7778.c +@@ -281,6 +281,40 @@ void __init r8a7778_register_hspi(int id) + hspi_resources + (2 * id), 2); + } + ++/* VIN */ ++#define R8A7778_VIN(idx) \ ++static struct resource vin##idx##_resources[] __initdata = { \ ++ DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000), \ ++ DEFINE_RES_IRQ(gic_iid(0x5a)), \ ++}; \ ++ \ ++static struct platform_device_info vin##idx##_info __initdata = { \ ++ .parent = &platform_bus, \ ++ .name = "r8a7778-vin", \ ++ .id = idx, \ ++ .res = vin##idx##_resources, \ ++ .num_res = ARRAY_SIZE(vin##idx##_resources), \ ++ .dma_mask = DMA_BIT_MASK(32), \ ++} ++ ++R8A7778_VIN(0); ++R8A7778_VIN(1); ++ ++static struct platform_device_info *vin_info_table[] __initdata = { ++ &vin0_info, ++ &vin1_info, ++}; ++ ++void __init r8a7778_add_vin_device(int id, struct rcar_vin_platform_data *pdata) ++{ ++ BUG_ON(id < 0 || id > 1); ++ ++ vin_info_table[id]->data = pdata; ++ vin_info_table[id]->size_data = sizeof(*pdata); ++ ++ platform_device_register_full(vin_info_table[id]); ++} ++ + void __init r8a7778_add_dt_devices(void) + { + int i; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0478-media-ARM-shmobile-BOCK-W-add-VIN-and-ML86V7667-supp.patch b/patches.renesas/0478-media-ARM-shmobile-BOCK-W-add-VIN-and-ML86V7667-supp.patch new file mode 100644 index 00000000000..3c053bd1026 --- /dev/null +++ b/patches.renesas/0478-media-ARM-shmobile-BOCK-W-add-VIN-and-ML86V7667-supp.patch @@ -0,0 +1,107 @@ +From 9cc7aa635dc2095543a2dcc9570477164cf07477 Mon Sep 17 00:00:00 2001 +From: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Date: Thu, 22 Aug 2013 17:38:50 -0300 +Subject: [media] ARM: shmobile: BOCK-W: add VIN and ML86V7667 support + +Add ML86V7667 platform devices on BOCK-W board, configure VIN0/1 pins, and +register VIN0/1 devices with the ML86V7667 specific platform data. +[Sergei: some macro/comment cleanup; updated the copyrights, removed duplicate +'sh_eth' driver being enabled before registering VIN1 due to a pin conflict, +removed superfluous semicolon after iclink[01]_ml86v7667' initializer.] + +Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com> +(cherry picked from commit 9c43952d0f1e7da943cb697f902e5a0e62abfc63) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + arch/arm/mach-shmobile/board-bockw.c +--- + arch/arm/mach-shmobile/board-bockw.c | 41 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 41 insertions(+) + +diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c +index 255e97e5..127ad3a0 100644 +--- a/arch/arm/mach-shmobile/board-bockw.c ++++ b/arch/arm/mach-shmobile/board-bockw.c +@@ -3,6 +3,7 @@ + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> ++ * Copyright (C) 2013 Cogent Embedded, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by +@@ -31,6 +32,7 @@ + #include <linux/smsc911x.h> + #include <linux/spi/spi.h> + #include <linux/spi/flash.h> ++#include <media/soc_camera.h> + #include <mach/common.h> + #include <mach/irqs.h> + #include <mach/r8a7778.h> +@@ -161,6 +163,25 @@ static struct sh_mmcif_plat_data sh_mmcif_plat __initdata = { + MMC_CAP_NEEDS_POLL, + }; + ++static struct rcar_vin_platform_data vin_platform_data __initdata = { ++ .flags = RCAR_VIN_BT656, ++}; ++ ++/* In the default configuration both decoders reside on I2C bus 0 */ ++#define BOCKW_CAMERA(idx) \ ++static struct i2c_board_info camera##idx##_info = { \ ++ I2C_BOARD_INFO("ml86v7667", 0x41 + 2 * (idx)), \ ++}; \ ++ \ ++static struct soc_camera_link iclink##idx##_ml86v7667 __initdata = { \ ++ .bus_id = idx, \ ++ .i2c_adapter_id = 0, \ ++ .board_info = &camera##idx##_info, \ ++} ++ ++BOCKW_CAMERA(0); ++BOCKW_CAMERA(1); ++ + static const struct pinctrl_map bockw_pinctrl_map[] = { + /* Ether */ + PIN_MAP_MUX_GROUP_DEFAULT("r8a777x-ether", "pfc-r8a7778", +@@ -192,6 +213,16 @@ static const struct pinctrl_map bockw_pinctrl_map[] = { + "sdhi0_cd", "sdhi0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778", + "sdhi0_wp", "sdhi0"), ++ /* VIN0 */ ++ PIN_MAP_MUX_GROUP_DEFAULT("r8a7778-vin.0", "pfc-r8a7778", ++ "vin0_clk", "vin0"), ++ PIN_MAP_MUX_GROUP_DEFAULT("r8a7778-vin.0", "pfc-r8a7778", ++ "vin0_data8", "vin0"), ++ /* VIN1 */ ++ PIN_MAP_MUX_GROUP_DEFAULT("r8a7778-vin.1", "pfc-r8a7778", ++ "vin1_clk", "vin1"), ++ PIN_MAP_MUX_GROUP_DEFAULT("r8a7778-vin.1", "pfc-r8a7778", ++ "vin1_data8", "vin1"), + }; + + #define FPGA 0x18200000 +@@ -206,6 +237,16 @@ static void __init bockw_init(void) + r8a7778_init_irq_extpin(1); + r8a7778_add_standard_devices(); + r8a7778_add_ether_device(ðer_platform_data); ++ r8a7778_add_vin_device(0, &vin_platform_data); ++ /* VIN1 has a pin conflict with Ether */ ++ if (!IS_ENABLED(CONFIG_SH_ETH)) ++ r8a7778_add_vin_device(1, &vin_platform_data); ++ platform_device_register_data(&platform_bus, "soc-camera-pdrv", 0, ++ &iclink0_ml86v7667, ++ sizeof(iclink0_ml86v7667)); ++ platform_device_register_data(&platform_bus, "soc-camera-pdrv", 1, ++ &iclink1_ml86v7667, ++ sizeof(iclink1_ml86v7667)); + + i2c_register_board_info(0, i2c0_devices, + ARRAY_SIZE(i2c0_devices)); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0479-media-ARM-shmobile-BOCK-W-enable-VIN-and-ML86V7667-i.patch b/patches.renesas/0479-media-ARM-shmobile-BOCK-W-enable-VIN-and-ML86V7667-i.patch new file mode 100644 index 00000000000..e79e1650c85 --- /dev/null +++ b/patches.renesas/0479-media-ARM-shmobile-BOCK-W-enable-VIN-and-ML86V7667-i.patch @@ -0,0 +1,38 @@ +From bd72a6d8bdd24d2109a8da077cd9c4d7399651fc Mon Sep 17 00:00:00 2001 +From: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Date: Thu, 22 Aug 2013 17:40:36 -0300 +Subject: [media] ARM: shmobile: BOCK-W: enable VIN and ML86V7667 in defconfig + +Add the VIN and ML86V7667 drivers to 'bockw_defconfig'. + +Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com> +(cherry picked from commit a3fbba0e39de102bcc65bcc66abeb73d3cf7f633) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/configs/bockw_defconfig | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/arm/configs/bockw_defconfig b/arch/arm/configs/bockw_defconfig +index 845f5cdf..e7e94948 100644 +--- a/arch/arm/configs/bockw_defconfig ++++ b/arch/arm/configs/bockw_defconfig +@@ -82,6 +82,13 @@ CONFIG_SERIAL_SH_SCI_CONSOLE=y + # CONFIG_HWMON is not set + CONFIG_I2C=y + CONFIG_I2C_RCAR=y ++CONFIG_MEDIA_SUPPORT=y ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++CONFIG_V4L_PLATFORM_DRIVERS=y ++CONFIG_SOC_CAMERA=y ++CONFIG_VIDEO_RCAR_VIN=y ++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set ++CONFIG_VIDEO_ML86V7667=y + CONFIG_SPI=y + CONFIG_SPI_SH_HSPI=y + CONFIG_USB=y +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0480-media-ARM-shmobile-r8a7779-add-VIN-support.patch b/patches.renesas/0480-media-ARM-shmobile-r8a7779-add-VIN-support.patch new file mode 100644 index 00000000000..6f1102e8cff --- /dev/null +++ b/patches.renesas/0480-media-ARM-shmobile-r8a7779-add-VIN-support.patch @@ -0,0 +1,150 @@ +From d70c8d1f461a5e8aed417399c7900883be15dac0 Mon Sep 17 00:00:00 2001 +From: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Date: Thu, 22 Aug 2013 17:23:13 -0300 +Subject: [media] ARM: shmobile: r8a7779: add VIN support + +Add VIN clocks and platform devices for R8A7779 SoC; add function to register +the VIN platform devices. +[Sergei: added 'id' parameter check to r8a7779_add_vin_device(), used '*pdata' +in *sizeof* operator there, renamed some variables, annotated vin[0-3]_resources +[] and 'vin[0-3]_info' as '__initdata'.] + +Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com> +(cherry picked from commit 4714a0255eee45b87634ab28f8a7e66038f645ba) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + arch/arm/mach-shmobile/clock-r8a7779.c + arch/arm/mach-shmobile/include/mach/r8a7779.h + arch/arm/mach-shmobile/setup-r8a7779.c +--- + arch/arm/mach-shmobile/clock-r8a7779.c | 10 ++++++++ + arch/arm/mach-shmobile/include/mach/r8a7779.h | 3 +++ + arch/arm/mach-shmobile/setup-r8a7779.c | 37 +++++++++++++++++++++++++++ + 3 files changed, 50 insertions(+) + +diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c +index 9daeb8c3..6070f3a4 100644 +--- a/arch/arm/mach-shmobile/clock-r8a7779.c ++++ b/arch/arm/mach-shmobile/clock-r8a7779.c +@@ -112,7 +112,9 @@ static struct clk *main_clks[] = { + }; + + enum { MSTP323, MSTP322, MSTP321, MSTP320, ++ MSTP120, + MSTP116, MSTP115, MSTP114, ++ MSTP110, MSTP109, MSTP108, + MSTP103, MSTP101, MSTP100, + MSTP030, + MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, +@@ -125,9 +127,13 @@ static struct clk mstp_clks[MSTP_NR] = { + [MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */ + [MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */ + [MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */ ++ [MSTP120] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 20, 0), /* VIN3 */ + [MSTP116] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 16, 0), /* PCIe */ + [MSTP115] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 15, 0), /* SATA */ + [MSTP114] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 14, 0), /* Ether */ ++ [MSTP110] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 10, 0), /* VIN0 */ ++ [MSTP109] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 9, 0), /* VIN1 */ ++ [MSTP108] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 8, 0), /* VIN2 */ + [MSTP103] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 3, 0), /* DU */ + [MSTP101] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 1, 0), /* USB2 */ + [MSTP100] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 0, 0), /* USB0/1 */ +@@ -162,10 +168,14 @@ static struct clk_lookup lookups[] = { + CLKDEV_CON_ID("peripheral_clk", &clkp_clk), + + /* MSTP32 clocks */ ++ CLKDEV_DEV_ID("r8a7779-vin.3", &mstp_clks[MSTP120]), /* VIN3 */ + CLKDEV_DEV_ID("rcar-pcie", &mstp_clks[MSTP116]), /* PCIe */ + CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */ + CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */ + CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */ ++ CLKDEV_DEV_ID("r8a7779-vin.0", &mstp_clks[MSTP110]), /* VIN0 */ ++ CLKDEV_DEV_ID("r8a7779-vin.1", &mstp_clks[MSTP109]), /* VIN1 */ ++ CLKDEV_DEV_ID("r8a7779-vin.2", &mstp_clks[MSTP108]), /* VIN2 */ + CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */ + CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */ + CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */ +diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h +index f08d6ecf..11c74004 100644 +--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h ++++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h +@@ -4,6 +4,7 @@ + #include <linux/sh_clk.h> + #include <linux/pm_domain.h> + #include <linux/sh_eth.h> ++#include <linux/platform_data/camera-rcar.h> + + struct platform_device; + +@@ -32,6 +33,8 @@ extern void r8a7779_add_early_devices(void); + extern void r8a7779_add_standard_devices(void); + extern void r8a7779_add_standard_devices_dt(void); + extern void r8a7779_add_ether_device(struct sh_eth_plat_data *pdata); ++extern void r8a7779_add_vin_device(int idx, ++ struct rcar_vin_platform_data *pdata); + extern void r8a7779_init_late(void); + extern void r8a7779_clock_init(void); + extern void r8a7779_pinmux_init(void); +diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c +index 6a993339..b5b2f787 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7779.c ++++ b/arch/arm/mach-shmobile/setup-r8a7779.c +@@ -605,6 +605,33 @@ static struct resource ether_resources[] __initdata = { + }, + }; + ++#define R8A7779_VIN(idx) \ ++static struct resource vin##idx##_resources[] __initdata = { \ ++ DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000), \ ++ DEFINE_RES_IRQ(gic_iid(0x5f + (idx))), \ ++}; \ ++ \ ++static struct platform_device_info vin##idx##_info __initdata = { \ ++ .parent = &platform_bus, \ ++ .name = "r8a7779-vin", \ ++ .id = idx, \ ++ .res = vin##idx##_resources, \ ++ .num_res = ARRAY_SIZE(vin##idx##_resources), \ ++ .dma_mask = DMA_BIT_MASK(32), \ ++} ++ ++R8A7779_VIN(0); ++R8A7779_VIN(1); ++R8A7779_VIN(2); ++R8A7779_VIN(3); ++ ++static struct platform_device_info *vin_info_table[] __initdata = { ++ &vin0_info, ++ &vin1_info, ++ &vin2_info, ++ &vin3_info, ++}; ++ + static struct platform_device *r8a7779_devices_dt[] __initdata = { + &scif0_device, + &scif1_device, +@@ -648,6 +675,16 @@ void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata) + pdata, sizeof(*pdata)); + } + ++void __init r8a7779_add_vin_device(int id, struct rcar_vin_platform_data *pdata) ++{ ++ BUG_ON(id < 0 || id > 3); ++ ++ vin_info_table[id]->data = pdata; ++ vin_info_table[id]->size_data = sizeof(*pdata); ++ ++ platform_device_register_full(vin_info_table[id]); ++} ++ + /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ + void __init __weak r8a7779_register_twd(void) { } + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0481-media-ARM-shmobile-Marzen-add-VIN-and-ADV7180-suppor.patch b/patches.renesas/0481-media-ARM-shmobile-Marzen-add-VIN-and-ADV7180-suppor.patch new file mode 100644 index 00000000000..07fe4f310b9 --- /dev/null +++ b/patches.renesas/0481-media-ARM-shmobile-Marzen-add-VIN-and-ADV7180-suppor.patch @@ -0,0 +1,117 @@ +From 1219a94a13e065ee56bd0c6c863225a00c5c7409 Mon Sep 17 00:00:00 2001 +From: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Date: Thu, 22 Aug 2013 17:25:25 -0300 +Subject: [media] ARM: shmobile: Marzen: add VIN and ADV7180 support + +Add ADV7180 platform devices on the Marzen board, configure VIN1/3 pins, and +register VIN1/3 devices with the ADV7180 specific platform data. +[Sergei: removed superfluous tabulation and inserted empty lines in the macro +definition, updated the copyrights, annotated VIN platform data as '__initdata'] + +Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com> +(cherry picked from commit 7cef5e7fd1ab891bc59c269a1a55b8e8d8ca5bc8) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + arch/arm/mach-shmobile/board-marzen.c +--- + arch/arm/mach-shmobile/board-marzen.c | 44 ++++++++++++++++++++++++++++++++++- + 1 file changed, 43 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c +index 3551b548..3f5044fd 100644 +--- a/arch/arm/mach-shmobile/board-marzen.c ++++ b/arch/arm/mach-shmobile/board-marzen.c +@@ -1,8 +1,9 @@ + /* + * marzen board support + * +- * Copyright (C) 2011 Renesas Solutions Corp. ++ * Copyright (C) 2011, 2013 Renesas Solutions Corp. + * Copyright (C) 2011 Magnus Damm ++ * Copyright (C) 2013 Cogent Embedded, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by +@@ -38,6 +39,7 @@ + #include <linux/mmc/host.h> + #include <linux/mmc/sh_mobile_sdhi.h> + #include <linux/mfd/tmio.h> ++#include <media/soc_camera.h> + #include <mach/r8a7779.h> + #include <mach/common.h> + #include <mach/irqs.h> +@@ -197,6 +199,32 @@ static struct platform_device leds_device = { + }, + }; + ++static struct rcar_vin_platform_data vin_platform_data __initdata = { ++ .flags = RCAR_VIN_BT656, ++}; ++ ++#define MARZEN_CAMERA(idx) \ ++static struct i2c_board_info camera##idx##_info = { \ ++ I2C_BOARD_INFO("adv7180", 0x20 + (idx)), \ ++}; \ ++ \ ++static struct soc_camera_link iclink##idx##_adv7180 = { \ ++ .bus_id = 1 + 2 * (idx), \ ++ .i2c_adapter_id = 0, \ ++ .board_info = &camera##idx##_info, \ ++}; \ ++ \ ++static struct platform_device camera##idx##_device = { \ ++ .name = "soc-camera-pdrv", \ ++ .id = idx, \ ++ .dev = { \ ++ .platform_data = &iclink##idx##_adv7180, \ ++ }, \ ++}; ++ ++MARZEN_CAMERA(0); ++MARZEN_CAMERA(1); ++ + static struct platform_device *marzen_devices[] __initdata = { + ð_device, + &sdhi0_device, +@@ -204,6 +232,8 @@ static struct platform_device *marzen_devices[] __initdata = { + &hspi_device, + &leds_device, + &usb_phy, ++ &camera0_device, ++ &camera1_device, + }; + + static const struct pinctrl_map marzen_pinctrl_map[] = { +@@ -239,6 +269,16 @@ static const struct pinctrl_map marzen_pinctrl_map[] = { + /* USB2 */ + PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.1", "pfc-r8a7779", + "usb2", "usb2"), ++ /* VIN1 */ ++ PIN_MAP_MUX_GROUP_DEFAULT("r8a7779-vin.1", "pfc-r8a7779", ++ "vin1_clk", "vin1"), ++ PIN_MAP_MUX_GROUP_DEFAULT("r8a7779-vin.1", "pfc-r8a7779", ++ "vin1_data8", "vin1"), ++ /* VIN3 */ ++ PIN_MAP_MUX_GROUP_DEFAULT("r8a7779-vin.3", "pfc-r8a7779", ++ "vin3_clk", "vin3"), ++ PIN_MAP_MUX_GROUP_DEFAULT("r8a7779-vin.3", "pfc-r8a7779", ++ "vin3_data8", "vin3"), + }; + + static void __init marzen_init(void) +@@ -254,6 +294,8 @@ static void __init marzen_init(void) + r8a7779_init_irq_extpin(1); /* IRQ1 as individual interrupt */ + + r8a7779_add_standard_devices(); ++ r8a7779_add_vin_device(1, &vin_platform_data); ++ r8a7779_add_vin_device(3, &vin_platform_data); + platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices)); + } + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0482-media-ARM-shmobile-Marzen-enable-VIN-and-ADV7180-in-.patch b/patches.renesas/0482-media-ARM-shmobile-Marzen-enable-VIN-and-ADV7180-in-.patch new file mode 100644 index 00000000000..fbb52d2ab81 --- /dev/null +++ b/patches.renesas/0482-media-ARM-shmobile-Marzen-enable-VIN-and-ADV7180-in-.patch @@ -0,0 +1,38 @@ +From aa14a1a19729de1a8f9ad889306bd0a54bc333ee Mon Sep 17 00:00:00 2001 +From: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Date: Thu, 22 Aug 2013 17:27:08 -0300 +Subject: [media] ARM: shmobile: Marzen: enable VIN and ADV7180 in defconfig + +Add the VIN and ADV7180 drivers to 'marzen_defconfig'. + +Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com> +(cherry picked from commit e0c332c671e71941e0bd4a339972ee4af15df676) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/configs/marzen_defconfig | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig +index 82e4040b..000e9205 100644 +--- a/arch/arm/configs/marzen_defconfig ++++ b/arch/arm/configs/marzen_defconfig +@@ -85,6 +85,13 @@ CONFIG_GPIO_RCAR=y + CONFIG_THERMAL=y + CONFIG_RCAR_THERMAL=y + CONFIG_SSB=y ++CONFIG_MEDIA_SUPPORT=y ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++CONFIG_V4L_PLATFORM_DRIVERS=y ++CONFIG_SOC_CAMERA=y ++CONFIG_VIDEO_RCAR_VIN=y ++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set ++CONFIG_VIDEO_ADV7180=y + CONFIG_USB=y + CONFIG_USB_RCAR_PHY=y + CONFIG_MMC=y +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0483-ARM-shmobile-r8a7779-Update-early-timer-initialisati.patch b/patches.renesas/0483-ARM-shmobile-r8a7779-Update-early-timer-initialisati.patch new file mode 100644 index 00000000000..18ff2dc1e9c --- /dev/null +++ b/patches.renesas/0483-ARM-shmobile-r8a7779-Update-early-timer-initialisati.patch @@ -0,0 +1,44 @@ +From b26590879c16fd9a9575d36796899d4cb73f4b99 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Thu, 8 Aug 2013 17:59:17 +0900 +Subject: ARM: shmobile: r8a7779: Update early timer initialisation order + +a894fcc2d01a89e6fe3da0845a4d80a5312e1124 ("ARM: smp_twd: Divorce smp_twd +from local timer API") altered twd_local_timer_common_register() so that it +may make use of late_timer_init. + +This is problematic on marzen with Magnus's recent patch "ARM: shmobile: +marzen: Switch to DT_MACHINE_START" which switches marzen around to enable +USE_OF and thus shmobile_timer_init(), which is registered as +late_time_init by shmobile_earlytimer_init() stops being a no-op. + +As a work-around I have updated r8a7779_earlytimer_init() so that +shmobile_earlytimer_init() is called after r8a7779_register_twd(). +Or in other words, the shmobile_earlytimer_init() setting of +late_time_init overwrites that of twd_local_timer_common_register(). + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Acked-by: Magnus Damm <damm@opensource.se> +(cherry picked from commit 7658ea2fb57831c6836ffcfb20bcb84f3ff55dfb) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a7779.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c +index b5b2f787..ecd0148e 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7779.c ++++ b/arch/arm/mach-shmobile/setup-r8a7779.c +@@ -691,8 +691,8 @@ void __init __weak r8a7779_register_twd(void) { } + void __init r8a7779_earlytimer_init(void) + { + r8a7779_clock_init(); +- shmobile_earlytimer_init(); + r8a7779_register_twd(); ++ shmobile_earlytimer_init(); + } + + void __init r8a7779_add_early_devices(void) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0484-ARM-shmobile-lager-Do-not-use-register_type-field-of.patch b/patches.renesas/0484-ARM-shmobile-lager-Do-not-use-register_type-field-of.patch new file mode 100644 index 00000000000..8f234626479 --- /dev/null +++ b/patches.renesas/0484-ARM-shmobile-lager-Do-not-use-register_type-field-of.patch @@ -0,0 +1,34 @@ +From 30ffc33137dc46b2d6014ef8b50ba3907544dbd8 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Thu, 22 Aug 2013 16:36:38 +0900 +Subject: ARM: shmobile: lager: Do not use register_type field of struct + sh_eth_plat_data + +As of 8d3214c ("sh_eth: remove 'register_type' field from 'struct +sh_eth_plat_data'") is is no longer necessary or correct to use the +'register_type' field from 'struct sh_eth_plat_data' and doing so results +in a build error. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: Olof Johansson <olof@lixom.net> +(cherry picked from commit 3a116a5eaa68046646e557b4988a49e18f129ce8) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-lager.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c +index 4872939c..ffb6f0ac 100644 +--- a/arch/arm/mach-shmobile/board-lager.c ++++ b/arch/arm/mach-shmobile/board-lager.c +@@ -96,7 +96,6 @@ static struct resource mmcif1_resources[] __initdata = { + static struct sh_eth_plat_data ether_pdata __initdata = { + .phy = 0x1, + .edmac_endian = EDMAC_LITTLE_ENDIAN, +- .register_type = SH_ETH_REG_FAST_RCAR, + .phy_interface = PHY_INTERFACE_MODE_RMII, + .ether_link_active_low = 1, + }; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0485-ARM-shmobile-change-dev_id-to-cpu0-while-registering.patch b/patches.renesas/0485-ARM-shmobile-change-dev_id-to-cpu0-while-registering.patch new file mode 100644 index 00000000000..e35de449b5b --- /dev/null +++ b/patches.renesas/0485-ARM-shmobile-change-dev_id-to-cpu0-while-registering.patch @@ -0,0 +1,52 @@ +From 5c8722c5f7bceb1577c42b03cdd04bb441f55ecd Mon Sep 17 00:00:00 2001 +From: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com> +Date: Tue, 10 Sep 2013 18:59:49 +0100 +Subject: ARM: shmobile: change dev_id to cpu0 while registering cpu clock + +Currently all clkdev registration use "cpufreq-cpu0.0" as dev_id +for cpu clock which refers to virtual platform device. It needs to +be "cpu0" instead which is actual cpu0 device id. + +This patch changes the dev_id from "cpufreq-cpu0.0" to "cpu0". + +Reported-and-tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Cc: Shawn Guo <shawn.guo@linaro.org> +Cc: Magnus Damm <damm@opensource.se> +Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com> +Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> +(cherry picked from commit e4a6a29d1250022a885123cc0a04bd176b508854) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a73a4.c | 2 +- + arch/arm/mach-shmobile/clock-sh73a0.c | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c +index 8ea5ef6c..5bd2e851 100644 +--- a/arch/arm/mach-shmobile/clock-r8a73a4.c ++++ b/arch/arm/mach-shmobile/clock-r8a73a4.c +@@ -555,7 +555,7 @@ static struct clk_lookup lookups[] = { + CLKDEV_CON_ID("pll2h", &pll2h_clk), + + /* CPU clock */ +- CLKDEV_DEV_ID("cpufreq-cpu0", &z_clk), ++ CLKDEV_DEV_ID("cpu0", &z_clk), + + /* DIV6 */ + CLKDEV_CON_ID("zb", &div6_clks[DIV6_ZB]), +diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c +index 1942eaef..c92c023f 100644 +--- a/arch/arm/mach-shmobile/clock-sh73a0.c ++++ b/arch/arm/mach-shmobile/clock-sh73a0.c +@@ -616,7 +616,7 @@ static struct clk_lookup lookups[] = { + CLKDEV_DEV_ID("smp_twd", &twd_clk), /* smp_twd */ + + /* DIV4 clocks */ +- CLKDEV_DEV_ID("cpufreq-cpu0", &div4_clks[DIV4_Z]), ++ CLKDEV_DEV_ID("cpu0", &div4_clks[DIV4_Z]), + + /* DIV6 clocks */ + CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0486-ARM-shmobile-Lager-add-Micrel-KSZ8041-PHY-fixup.patch b/patches.renesas/0486-ARM-shmobile-Lager-add-Micrel-KSZ8041-PHY-fixup.patch new file mode 100644 index 00000000000..75814c31147 --- /dev/null +++ b/patches.renesas/0486-ARM-shmobile-Lager-add-Micrel-KSZ8041-PHY-fixup.patch @@ -0,0 +1,77 @@ +From 10a564a4c2b4ec90b1cb77f15a229e46f7af02e7 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Sat, 14 Sep 2013 04:29:22 +0400 +Subject: ARM: shmobile: Lager: add Micrel KSZ8041 PHY fixup + +Currently on the Lager board NFS timeouts/delays are seen when booting. That +turned out to happen because the SoC's ETH_LINK signal turns on and off after +each packet. It is connected to Micrel KSZ8041 PHY's LED0 signal. Ether LEDs +on the Lager board are named LINK and ACTIVE which corresponds to non-default +01 setting of the PHY control register 1 bits 14-15. The 'sh_eth' driver resets +the PHY when opening the network device, so we have to set the mentioned bits +back to 01 from the default 00 value which causes bouncing of ETH_LINK. That +can be achieved using the PHY platform fixup mechanism if we also modify the +driver to use it.. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 48c8b96f21817aad695246ef020b849d466cc502) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-lager.c | 27 ++++++++++++++++++++++++++- + 1 file changed, 26 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c +index ffb6f0ac..5930af8d 100644 +--- a/arch/arm/mach-shmobile/board-lager.c ++++ b/arch/arm/mach-shmobile/board-lager.c +@@ -29,6 +29,7 @@ + #include <linux/pinctrl/machine.h> + #include <linux/platform_data/gpio-rcar.h> + #include <linux/platform_device.h> ++#include <linux/phy.h> + #include <linux/regulator/fixed.h> + #include <linux/regulator/machine.h> + #include <linux/sh_eth.h> +@@ -155,6 +156,30 @@ static void __init lager_add_standard_devices(void) + ðer_pdata, sizeof(ether_pdata)); + } + ++/* ++ * Ether LEDs on the Lager board are named LINK and ACTIVE which corresponds ++ * to non-default 01 setting of the Micrel KSZ8041 PHY control register 1 bits ++ * 14-15. We have to set them back to 01 from the default 00 value each time ++ * the PHY is reset. It's also important because the PHY's LED0 signal is ++ * connected to SoC's ETH_LINK signal and in the PHY's default mode it will ++ * bounce on and off after each packet, which we apparently want to avoid. ++ */ ++static int lager_ksz8041_fixup(struct phy_device *phydev) ++{ ++ u16 phyctrl1 = phy_read(phydev, 0x1e); ++ ++ phyctrl1 &= ~0xc000; ++ phyctrl1 |= 0x4000; ++ return phy_write(phydev, 0x1e, phyctrl1); ++} ++ ++static void __init lager_init(void) ++{ ++ lager_add_standard_devices(); ++ ++ phy_register_fixup_for_id("r8a7790-ether-ff:01", lager_ksz8041_fixup); ++} ++ + static const char *lager_boards_compat_dt[] __initdata = { + "renesas,lager", + NULL, +@@ -163,6 +188,6 @@ static const char *lager_boards_compat_dt[] __initdata = { + DT_MACHINE_START(LAGER_DT, "lager") + .init_early = r8a7790_init_delay, + .init_time = r8a7790_timer_init, +- .init_machine = lager_add_standard_devices, ++ .init_machine = lager_init, + .dt_compat = lager_boards_compat_dt, + MACHINE_END +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0487-ARM-shmobile-armadillo-fixup-ether-pinctrl-naming.patch b/patches.renesas/0487-ARM-shmobile-armadillo-fixup-ether-pinctrl-naming.patch new file mode 100644 index 00000000000..567f0ec3494 --- /dev/null +++ b/patches.renesas/0487-ARM-shmobile-armadillo-fixup-ether-pinctrl-naming.patch @@ -0,0 +1,37 @@ +From 645c7ecb2552808a939ef8ae54d5f917991a15e2 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Sun, 1 Sep 2013 20:33:49 -0700 +Subject: ARM: shmobile: armadillo: fixup ether pinctrl naming + +e5c9b4cd665106d9b5397114ea81a53059410b6a ("sh_eth: get R8A7740 support +out of #ifdef") exchanged sh-eth driver name to r8a7740-gether, but, +eva_pinctrl_map[] didn't follow it. Fixes it. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 7cd402b30a701c2b4d38a98281a00fc5e3680b13) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/board-armadillo800eva.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c +index 471440ba..2ef31a69 100644 +--- a/arch/arm/mach-shmobile/board-armadillo800eva.c ++++ b/arch/arm/mach-shmobile/board-armadillo800eva.c +@@ -1108,9 +1108,9 @@ static const struct pinctrl_map eva_pinctrl_map[] = { + PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-r8a7740", + "fsib_mclk_in", "fsib"), + /* GETHER */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740", ++ PIN_MAP_MUX_GROUP_DEFAULT("r8a7740-gether", "pfc-r8a7740", + "gether_mii", "gether"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740", ++ PIN_MAP_MUX_GROUP_DEFAULT("r8a7740-gether", "pfc-r8a7740", + "gether_int", "gether"), + /* HDMI */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-r8a7740", +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0488-ARM-shmobile-Remove-gpio-ranges-cells-DT-property.patch b/patches.renesas/0488-ARM-shmobile-Remove-gpio-ranges-cells-DT-property.patch new file mode 100644 index 00000000000..52eab1414eb --- /dev/null +++ b/patches.renesas/0488-ARM-shmobile-Remove-gpio-ranges-cells-DT-property.patch @@ -0,0 +1,55 @@ +From 85519ebc6a3e57a4d2bc00d184b6a615fa8f39d3 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Wed, 11 Sep 2013 15:51:02 +0200 +Subject: ARM: shmobile: Remove #gpio-ranges-cells DT property + +This property is no longer required by the GPIO binding. Remove it. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 3786f86b60833f32e3eeb016fcf8c324f8147e00) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7778.dtsi | 1 - + arch/arm/boot/dts/r8a7779.dtsi | 1 - + arch/arm/boot/dts/r8a7790.dtsi | 1 - + 3 files changed, 3 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi +index 45ac404a..3577aba8 100644 +--- a/arch/arm/boot/dts/r8a7778.dtsi ++++ b/arch/arm/boot/dts/r8a7778.dtsi +@@ -96,6 +96,5 @@ + pfc: pfc@fffc0000 { + compatible = "renesas,pfc-r8a7778"; + reg = <0xfffc000 0x118>; +- #gpio-range-cells = <3>; + }; + }; +diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi +index 23a62447..ebbe507f 100644 +--- a/arch/arm/boot/dts/r8a7779.dtsi ++++ b/arch/arm/boot/dts/r8a7779.dtsi +@@ -188,7 +188,6 @@ + pfc: pfc@fffc0000 { + compatible = "renesas,pfc-r8a7779"; + reg = <0xfffc0000 0x23c>; +- #gpio-range-cells = <3>; + }; + + thermal@ffc48000 { +diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi +index 3b879e7c..98513984 100644 +--- a/arch/arm/boot/dts/r8a7790.dtsi ++++ b/arch/arm/boot/dts/r8a7790.dtsi +@@ -148,7 +148,6 @@ + pfc: pfc@e6060000 { + compatible = "renesas,pfc-r8a7790"; + reg = <0 0xe6060000 0 0x250>; +- #gpio-range-cells = <3>; + }; + + sdhi0: sdhi@ee100000 { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0489-sh_eth-remove-ifdef-around-EDSR-and-GECMR-bit-defini.patch b/patches.renesas/0489-sh_eth-remove-ifdef-around-EDSR-and-GECMR-bit-defini.patch new file mode 100644 index 00000000000..05c1d6cdce3 --- /dev/null +++ b/patches.renesas/0489-sh_eth-remove-ifdef-around-EDSR-and-GECMR-bit-defini.patch @@ -0,0 +1,51 @@ +From 9206105698487d79571b34225455363f8eaaf371 Mon Sep 17 00:00:00 2001 +From: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> +Date: Thu, 6 Jun 2013 09:43:16 +0000 +Subject: sh_eth: remove #ifdef around EDSR and GECMR bit definitions + +Remove #ifdef around 'enum EDSR_BIT' and 'enum GECMR_BIT', replacing it with the +comments on which SoCs these registers exist. + +SH7757 also has EDSR, so add a comment about it to 'enum EDSR_BIT'. + +Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> +[Sergei: folded in the former patch #2, updated the changelog, reworded the +subject, changing the prefix.] +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> + +(cherry picked from commit 41d5ffeb9d12f760722f00ba0756389d32435124) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.h | 7 ++----- + 1 file changed, 2 insertions(+), 5 deletions(-) + +diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h +index 62689a58..034bee94 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.h ++++ b/drivers/net/ethernet/renesas/sh_eth.h +@@ -166,19 +166,16 @@ enum { + /* + * Register's bits + */ +-#if defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763) ||\ +- defined(CONFIG_ARCH_R8A7740) +-/* EDSR */ ++/* EDSR : sh7734, sh7757, sh7763, and r8a7740 only */ + enum EDSR_BIT { + EDSR_ENT = 0x01, EDSR_ENR = 0x02, + }; + #define EDSR_ENALL (EDSR_ENT|EDSR_ENR) + +-/* GECMR */ ++/* GECMR : sh7734, sh7763 and r8a7740 only */ + enum GECMR_BIT { + GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01, + }; +-#endif + + /* EDMR */ + enum DMAC_M_BIT { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0490-sh_eth-use-EDSR_ENALL-to-set-EDSR.patch b/patches.renesas/0490-sh_eth-use-EDSR_ENALL-to-set-EDSR.patch new file mode 100644 index 00000000000..4dc8a306d41 --- /dev/null +++ b/patches.renesas/0490-sh_eth-use-EDSR_ENALL-to-set-EDSR.patch @@ -0,0 +1,34 @@ +From 48b354ed45d89cc15417e4c15ca71985c96b7370 Mon Sep 17 00:00:00 2001 +From: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> +Date: Thu, 6 Jun 2013 09:44:27 +0000 +Subject: sh_eth: use EDSR_ENALL to set EDSR + +Use now always available EDSR_ENALL instead of the bare number to set EDSR. + +Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> +[Sergei: added the changelog, reworded the subject, changing the prefix.] +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> + +(cherry picked from commit ddcd91c6b8ec60a6bd5d3691d2cfaf4447215da1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index e29fe8db..fd3f99f8 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -526,7 +526,7 @@ static int sh_eth_reset(struct net_device *ndev) + int ret = 0; + + if (sh_eth_is_gether(mdp)) { +- sh_eth_write(ndev, 0x03, EDSR); ++ sh_eth_write(ndev, EDSR_ENALL, EDSR); + sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, + EDMR); + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0491-sh_eth-remove-duplicate-sh_eth_set_duplex-definition.patch b/patches.renesas/0491-sh_eth-remove-duplicate-sh_eth_set_duplex-definition.patch new file mode 100644 index 00000000000..e74cd0ebe16 --- /dev/null +++ b/patches.renesas/0491-sh_eth-remove-duplicate-sh_eth_set_duplex-definition.patch @@ -0,0 +1,143 @@ +From e2ccda73a0d8f4ada60370ed9d08973976605cbf Mon Sep 17 00:00:00 2001 +From: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> +Date: Thu, 6 Jun 2013 09:45:25 +0000 +Subject: sh_eth: remove duplicate sh_eth_set_duplex() definitions + +Remove all the duplicate definitions of sh_eth_set_duplex() under different +#ifdef's, leaving only one outside the #ifdef's. We have to annotate it with +'__maybe_unused' since it's called not from all SoC #ifdef blocks. + +Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> +[Sergei: annotated sh_eth_set_duplex() as '__maybe_unused', added the changelog, +reworded the subject, changing the prefix.] +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> + +(cherry picked from commit 04b0ed2ad49834fe47d3c4171ad189c688a222b9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 59 +++-------------------------------- + 1 file changed, 5 insertions(+), 54 deletions(-) + +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index fd3f99f8..1dba3c9d 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -341,10 +341,7 @@ static void sh_eth_select_mii(struct net_device *ndev) + } + #endif + +-/* There is CPU dependent code */ +-#if defined(CONFIG_ARCH_R8A7778) || defined(CONFIG_ARCH_R8A7779) +-#define SH_ETH_RESET_DEFAULT 1 +-static void sh_eth_set_duplex(struct net_device *ndev) ++static void __maybe_unused sh_eth_set_duplex(struct net_device *ndev) + { + struct sh_eth_private *mdp = netdev_priv(ndev); + +@@ -354,6 +351,9 @@ static void sh_eth_set_duplex(struct net_device *ndev) + sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR); + } + ++/* There is CPU dependent code */ ++#if defined(CONFIG_ARCH_R8A7778) || defined(CONFIG_ARCH_R8A7779) ++#define SH_ETH_RESET_DEFAULT 1 + static void sh_eth_set_rate(struct net_device *ndev) + { + struct sh_eth_private *mdp = netdev_priv(ndev); +@@ -392,15 +392,6 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = { + }; + #elif defined(CONFIG_CPU_SUBTYPE_SH7724) + #define SH_ETH_RESET_DEFAULT 1 +-static void sh_eth_set_duplex(struct net_device *ndev) +-{ +- struct sh_eth_private *mdp = netdev_priv(ndev); +- +- if (mdp->duplex) /* Full */ +- sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR); +- else /* Half */ +- sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR); +-} + + static void sh_eth_set_rate(struct net_device *ndev) + { +@@ -445,16 +436,6 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = { + #define SH_ETH_HAS_TSU 1 + static int sh_eth_check_reset(struct net_device *ndev); + +-static void sh_eth_set_duplex(struct net_device *ndev) +-{ +- struct sh_eth_private *mdp = netdev_priv(ndev); +- +- if (mdp->duplex) /* Full */ +- sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR); +- else /* Half */ +- sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR); +-} +- + static void sh_eth_set_rate(struct net_device *ndev) + { + struct sh_eth_private *mdp = netdev_priv(ndev); +@@ -555,16 +536,6 @@ out: + return ret; + } + +-static void sh_eth_set_duplex_giga(struct net_device *ndev) +-{ +- struct sh_eth_private *mdp = netdev_priv(ndev); +- +- if (mdp->duplex) /* Full */ +- sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR); +- else /* Half */ +- sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR); +-} +- + static void sh_eth_set_rate_giga(struct net_device *ndev) + { + struct sh_eth_private *mdp = netdev_priv(ndev); +@@ -587,7 +558,7 @@ static void sh_eth_set_rate_giga(struct net_device *ndev) + /* SH7757(GETHERC) */ + static struct sh_eth_cpu_data sh_eth_my_cpu_data_giga = { + .chip_reset = sh_eth_chip_reset_giga, +- .set_duplex = sh_eth_set_duplex_giga, ++ .set_duplex = sh_eth_set_duplex, + .set_rate = sh_eth_set_rate_giga, + + .ecsr_value = ECSR_ICD | ECSR_MPD, +@@ -637,16 +608,6 @@ static void sh_eth_chip_reset(struct net_device *ndev) + mdelay(1); + } + +-static void sh_eth_set_duplex(struct net_device *ndev) +-{ +- struct sh_eth_private *mdp = netdev_priv(ndev); +- +- if (mdp->duplex) /* Full */ +- sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR); +- else /* Half */ +- sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR); +-} +- + static void sh_eth_set_rate(struct net_device *ndev) + { + struct sh_eth_private *mdp = netdev_priv(ndev); +@@ -774,16 +735,6 @@ out: + return ret; + } + +-static void sh_eth_set_duplex(struct net_device *ndev) +-{ +- struct sh_eth_private *mdp = netdev_priv(ndev); +- +- if (mdp->duplex) /* Full */ +- sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR); +- else /* Half */ +- sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR); +-} +- + static void sh_eth_set_rate(struct net_device *ndev) + { + struct sh_eth_private *mdp = netdev_priv(ndev); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0492-sh_eth-remove-SH_ETH_HAS_TSU.patch b/patches.renesas/0492-sh_eth-remove-SH_ETH_HAS_TSU.patch new file mode 100644 index 00000000000..3567ab2c1c4 --- /dev/null +++ b/patches.renesas/0492-sh_eth-remove-SH_ETH_HAS_TSU.patch @@ -0,0 +1,108 @@ +From f034001aeab26d3c9a71bf136dac4878ec8f4011 Mon Sep 17 00:00:00 2001 +From: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> +Date: Thu, 6 Jun 2013 09:48:09 +0000 +Subject: sh_eth: remove SH_ETH_HAS_TSU + +Remove SH_ETH_HAS_TSU #define's and #ifdef's. Set three 'struct net_device_ops' +methods that depend on the presence of TSU basing on the 'tsu' field of 'struct +sh_eth_cpu_data'. + +Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> +[Sergei: made two method assignments one-liners, added the changelog, reworded +the subject, changing the prefix.] +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> + +(cherry picked from commit 9f86134155047720a3685cda21467f68695152d2) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 20 ++++++++------------ + 1 file changed, 8 insertions(+), 12 deletions(-) + +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index 1dba3c9d..c821339a 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -433,7 +433,6 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = { + }; + #elif defined(CONFIG_CPU_SUBTYPE_SH7757) + #define SH_ETH_HAS_BOTH_MODULES 1 +-#define SH_ETH_HAS_TSU 1 + static int sh_eth_check_reset(struct net_device *ndev); + + static void sh_eth_set_rate(struct net_device *ndev) +@@ -595,7 +594,6 @@ static struct sh_eth_cpu_data *sh_eth_get_cpu_data(struct sh_eth_private *mdp) + } + + #elif defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763) +-#define SH_ETH_HAS_TSU 1 + static int sh_eth_check_reset(struct net_device *ndev); + static void sh_eth_reset_hw_crc(struct net_device *ndev); + +@@ -696,7 +694,6 @@ static void sh_eth_reset_hw_crc(struct net_device *ndev) + } + + #elif defined(CONFIG_ARCH_R8A7740) +-#define SH_ETH_HAS_TSU 1 + static int sh_eth_check_reset(struct net_device *ndev); + + static void sh_eth_chip_reset(struct net_device *ndev) +@@ -794,7 +791,6 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = { + }; + #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) + #define SH_ETH_RESET_DEFAULT 1 +-#define SH_ETH_HAS_TSU 1 + static struct sh_eth_cpu_data sh_eth_my_cpu_data = { + .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, + .tsu = 1, +@@ -2116,7 +2112,6 @@ static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, + return phy_mii_ioctl(phydev, rq, cmd); + } + +-#if defined(SH_ETH_HAS_TSU) + /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */ + static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp, + int entry) +@@ -2459,7 +2454,6 @@ static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev, + + return 0; + } +-#endif /* SH_ETH_HAS_TSU */ + + /* SuperH's TSU register init function */ + static void sh_eth_tsu_init(struct sh_eth_private *mdp) +@@ -2598,16 +2592,11 @@ static const u16 *sh_eth_get_register_offset(int register_type) + return reg_offset; + } + +-static const struct net_device_ops sh_eth_netdev_ops = { ++static struct net_device_ops sh_eth_netdev_ops = { + .ndo_open = sh_eth_open, + .ndo_stop = sh_eth_close, + .ndo_start_xmit = sh_eth_start_xmit, + .ndo_get_stats = sh_eth_get_stats, +-#if defined(SH_ETH_HAS_TSU) +- .ndo_set_rx_mode = sh_eth_set_multicast_list, +- .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid, +- .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid, +-#endif + .ndo_tx_timeout = sh_eth_tx_timeout, + .ndo_do_ioctl = sh_eth_do_ioctl, + .ndo_validate_addr = eth_validate_addr, +@@ -2688,6 +2677,13 @@ static int sh_eth_drv_probe(struct platform_device *pdev) + sh_eth_set_default_cpu_data(mdp->cd); + + /* set function */ ++ if (mdp->cd->tsu) { ++ sh_eth_netdev_ops.ndo_set_rx_mode = sh_eth_set_multicast_list; ++ sh_eth_netdev_ops.ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid; ++ sh_eth_netdev_ops.ndo_vlan_rx_kill_vid = ++ sh_eth_vlan_rx_kill_vid; ++ } ++ + ndev->netdev_ops = &sh_eth_netdev_ops; + SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops); + ndev->watchdog_timeo = TX_TIMEOUT; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0493-sh_eth-add-IRQ-flags-to-struct-sh_eth_cpu_data.patch b/patches.renesas/0493-sh_eth-add-IRQ-flags-to-struct-sh_eth_cpu_data.patch new file mode 100644 index 00000000000..62a121cbf70 --- /dev/null +++ b/patches.renesas/0493-sh_eth-add-IRQ-flags-to-struct-sh_eth_cpu_data.patch @@ -0,0 +1,82 @@ +From eab7fbe5159409031d16a41f59e674c46f55a8bf Mon Sep 17 00:00:00 2001 +From: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> +Date: Thu, 6 Jun 2013 09:49:30 +0000 +Subject: sh_eth: add IRQ flags to 'struct sh_eth_cpu_data' + +The driver supports some SH and SH-Mobile SOCs. There are SOCs with two or more +Ethernet devices, for these we need to pass IRQF_SHARED to request_irq(). Add +the 'irq_flags' field to the 'struct sh_eth_cpu_data' instead of #ifdef'fery. + +Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> +[Sergei: properly aligned request_irq() call continuation line, reworded the +changelog, reworded the subject, changing the prefix.] +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> + +(cherry picked from commit 5b3dfd13ae8bdebea67c02612fe282baff850bb0) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 13 +++++-------- + drivers/net/ethernet/renesas/sh_eth.h | 1 + + 2 files changed, 6 insertions(+), 8 deletions(-) + +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index c821339a..7ca34a52 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -465,6 +465,7 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = { + EESR_ECI, + .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE, + ++ .irq_flags = IRQF_SHARED, + .apr = 1, + .mpr = 1, + .tpauser = 1, +@@ -573,6 +574,7 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data_giga = { + .fdr_value = 0x0000072f, + .rmcr_value = 0x00000001, + ++ .irq_flags = IRQF_SHARED, + .apr = 1, + .mpr = 1, + .tpauser = 1, +@@ -653,6 +655,8 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = { + #if defined(CONFIG_CPU_SUBTYPE_SH7734) + .hw_crc = 1, + .select_mii = 1, ++#else ++ .irq_flags = IRQF_SHARED, + #endif + }; + +@@ -1919,14 +1923,7 @@ static int sh_eth_open(struct net_device *ndev) + pm_runtime_get_sync(&mdp->pdev->dev); + + ret = request_irq(ndev->irq, sh_eth_interrupt, +-#if defined(CONFIG_CPU_SUBTYPE_SH7763) || \ +- defined(CONFIG_CPU_SUBTYPE_SH7764) || \ +- defined(CONFIG_CPU_SUBTYPE_SH7757) +- IRQF_SHARED, +-#else +- 0, +-#endif +- ndev->name, ndev); ++ mdp->cd->irq_flags, ndev->name, ndev); + if (ret) { + dev_err(&ndev->dev, "Can not assign IRQ number\n"); + return ret; +diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h +index 034bee94..040d010b 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.h ++++ b/drivers/net/ethernet/renesas/sh_eth.h +@@ -463,6 +463,7 @@ struct sh_eth_cpu_data { + unsigned long tx_error_check; + + /* hardware features */ ++ unsigned long irq_flags; /* IRQ configuration flags */ + unsigned no_psr:1; /* EtherC DO NOT have PSR */ + unsigned apr:1; /* EtherC have APR */ + unsigned mpr:1; /* EtherC have MPR */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0494-sh_eth-remove-ifdef-around-sh_eth_select_mii.patch b/patches.renesas/0494-sh_eth-remove-ifdef-around-sh_eth_select_mii.patch new file mode 100644 index 00000000000..7ca777d88c5 --- /dev/null +++ b/patches.renesas/0494-sh_eth-remove-ifdef-around-sh_eth_select_mii.patch @@ -0,0 +1,46 @@ +From 0f4dfed19a45fb9f470eb56f6a840a8b7d9164fb Mon Sep 17 00:00:00 2001 +From: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> +Date: Thu, 6 Jun 2013 09:50:30 +0000 +Subject: sh_eth: remove #ifdef around sh_eth_select_mii() + +We can simply remove #ifdef'fery around sh_eth_select_mii(). We have to annotate +it with '__maybe_unused' then. + +Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> +[Sergei: added the changelog, reworded the subject, changing the prefix.] +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> + +(cherry picked from commit b7feacf1ee6944fc571802d58dcffaf13b4fb4cc) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 6 +----- + 1 file changed, 1 insertion(+), 5 deletions(-) + +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index 7ca34a52..2dd7be1f 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -313,10 +313,7 @@ static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = { + [TSU_ADRL31] = 0x01fc, + }; + +-#if defined(CONFIG_CPU_SUBTYPE_SH7734) || \ +- defined(CONFIG_CPU_SUBTYPE_SH7763) || \ +- defined(CONFIG_ARCH_R8A7740) +-static void sh_eth_select_mii(struct net_device *ndev) ++static void __maybe_unused sh_eth_select_mii(struct net_device *ndev) + { + u32 value = 0x0; + struct sh_eth_private *mdp = netdev_priv(ndev); +@@ -339,7 +336,6 @@ static void sh_eth_select_mii(struct net_device *ndev) + + sh_eth_write(ndev, value, RMII_MII); + } +-#endif + + static void __maybe_unused sh_eth_set_duplex(struct net_device *ndev) + { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0495-sh_eth-consolidate-sh_eth_reset.patch b/patches.renesas/0495-sh_eth-consolidate-sh_eth_reset.patch new file mode 100644 index 00000000000..cfb9c394ade --- /dev/null +++ b/patches.renesas/0495-sh_eth-consolidate-sh_eth_reset.patch @@ -0,0 +1,299 @@ +From d09388fe7133cac585f16ec3d53b2c99787d5bf5 Mon Sep 17 00:00:00 2001 +From: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> +Date: Thu, 6 Jun 2013 09:51:39 +0000 +Subject: sh_eth: consolidate sh_eth_reset() + +This driver has sh_eth_reset() function for each SoC and this function is almost +always the same, except for the several a bit different variations for Gigabit +Ethernet. Consolidate every variation into a single function -- which allows +us to get rid of some more #ifdef'fery. + +Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> +[Sergei: moved the new sh_eth_reset() and sh_eth_is_gether() up to decrease the +patch size, fixed function call continuation lines' indentation, reworded the +changelog, reworded the subject, changing the prefix.] +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> + +(cherry picked from commit dabdde9ea77d4a77094726c82468a3bd767fb29b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 176 ++++++++++------------------------ + 1 file changed, 51 insertions(+), 125 deletions(-) + +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index 2dd7be1f..cae8576a 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -313,6 +313,14 @@ static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = { + [TSU_ADRL31] = 0x01fc, + }; + ++static int sh_eth_is_gether(struct sh_eth_private *mdp) ++{ ++ if (mdp->reg_offset == sh_eth_offset_gigabit) ++ return 1; ++ else ++ return 0; ++} ++ + static void __maybe_unused sh_eth_select_mii(struct net_device *ndev) + { + u32 value = 0x0; +@@ -349,7 +357,6 @@ static void __maybe_unused sh_eth_set_duplex(struct net_device *ndev) + + /* There is CPU dependent code */ + #if defined(CONFIG_ARCH_R8A7778) || defined(CONFIG_ARCH_R8A7779) +-#define SH_ETH_RESET_DEFAULT 1 + static void sh_eth_set_rate(struct net_device *ndev) + { + struct sh_eth_private *mdp = netdev_priv(ndev); +@@ -387,7 +394,6 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = { + .hw_swap = 1, + }; + #elif defined(CONFIG_CPU_SUBTYPE_SH7724) +-#define SH_ETH_RESET_DEFAULT 1 + + static void sh_eth_set_rate(struct net_device *ndev) + { +@@ -429,7 +435,6 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = { + }; + #elif defined(CONFIG_CPU_SUBTYPE_SH7757) + #define SH_ETH_HAS_BOTH_MODULES 1 +-static int sh_eth_check_reset(struct net_device *ndev); + + static void sh_eth_set_rate(struct net_device *ndev) + { +@@ -496,42 +501,6 @@ static void sh_eth_chip_reset_giga(struct net_device *ndev) + } + } + +-static int sh_eth_is_gether(struct sh_eth_private *mdp); +-static int sh_eth_reset(struct net_device *ndev) +-{ +- struct sh_eth_private *mdp = netdev_priv(ndev); +- int ret = 0; +- +- if (sh_eth_is_gether(mdp)) { +- sh_eth_write(ndev, EDSR_ENALL, EDSR); +- sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, +- EDMR); +- +- ret = sh_eth_check_reset(ndev); +- if (ret) +- goto out; +- +- /* Table Init */ +- sh_eth_write(ndev, 0x0, TDLAR); +- sh_eth_write(ndev, 0x0, TDFAR); +- sh_eth_write(ndev, 0x0, TDFXR); +- sh_eth_write(ndev, 0x0, TDFFR); +- sh_eth_write(ndev, 0x0, RDLAR); +- sh_eth_write(ndev, 0x0, RDFAR); +- sh_eth_write(ndev, 0x0, RDFXR); +- sh_eth_write(ndev, 0x0, RDFFR); +- } else { +- sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, +- EDMR); +- mdelay(3); +- sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, +- EDMR); +- } +- +-out: +- return ret; +-} +- + static void sh_eth_set_rate_giga(struct net_device *ndev) + { + struct sh_eth_private *mdp = netdev_priv(ndev); +@@ -592,8 +561,6 @@ static struct sh_eth_cpu_data *sh_eth_get_cpu_data(struct sh_eth_private *mdp) + } + + #elif defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763) +-static int sh_eth_check_reset(struct net_device *ndev); +-static void sh_eth_reset_hw_crc(struct net_device *ndev); + + static void sh_eth_chip_reset(struct net_device *ndev) + { +@@ -656,45 +623,8 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = { + #endif + }; + +-static int sh_eth_reset(struct net_device *ndev) +-{ +- int ret = 0; +- +- sh_eth_write(ndev, EDSR_ENALL, EDSR); +- sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR); +- +- ret = sh_eth_check_reset(ndev); +- if (ret) +- goto out; +- +- /* Table Init */ +- sh_eth_write(ndev, 0x0, TDLAR); +- sh_eth_write(ndev, 0x0, TDFAR); +- sh_eth_write(ndev, 0x0, TDFXR); +- sh_eth_write(ndev, 0x0, TDFFR); +- sh_eth_write(ndev, 0x0, RDLAR); +- sh_eth_write(ndev, 0x0, RDFAR); +- sh_eth_write(ndev, 0x0, RDFXR); +- sh_eth_write(ndev, 0x0, RDFFR); +- +- /* Reset HW CRC register */ +- sh_eth_reset_hw_crc(ndev); +- +- /* Select MII mode */ +- if (sh_eth_my_cpu_data.select_mii) +- sh_eth_select_mii(ndev); +-out: +- return ret; +-} +- +-static void sh_eth_reset_hw_crc(struct net_device *ndev) +-{ +- if (sh_eth_my_cpu_data.hw_crc) +- sh_eth_write(ndev, 0x0, CSMR); +-} + + #elif defined(CONFIG_ARCH_R8A7740) +-static int sh_eth_check_reset(struct net_device *ndev); + + static void sh_eth_chip_reset(struct net_device *ndev) + { +@@ -707,31 +637,6 @@ static void sh_eth_chip_reset(struct net_device *ndev) + sh_eth_select_mii(ndev); + } + +-static int sh_eth_reset(struct net_device *ndev) +-{ +- int ret = 0; +- +- sh_eth_write(ndev, EDSR_ENALL, EDSR); +- sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR); +- +- ret = sh_eth_check_reset(ndev); +- if (ret) +- goto out; +- +- /* Table Init */ +- sh_eth_write(ndev, 0x0, TDLAR); +- sh_eth_write(ndev, 0x0, TDFAR); +- sh_eth_write(ndev, 0x0, TDFXR); +- sh_eth_write(ndev, 0x0, TDFFR); +- sh_eth_write(ndev, 0x0, RDLAR); +- sh_eth_write(ndev, 0x0, RDFAR); +- sh_eth_write(ndev, 0x0, RDFXR); +- sh_eth_write(ndev, 0x0, RDFFR); +- +-out: +- return ret; +-} +- + static void sh_eth_set_rate(struct net_device *ndev) + { + struct sh_eth_private *mdp = netdev_priv(ndev); +@@ -780,7 +685,6 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = { + }; + + #elif defined(CONFIG_CPU_SUBTYPE_SH7619) +-#define SH_ETH_RESET_DEFAULT 1 + static struct sh_eth_cpu_data sh_eth_my_cpu_data = { + .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, + +@@ -790,7 +694,6 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = { + .hw_swap = 1, + }; + #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) +-#define SH_ETH_RESET_DEFAULT 1 + static struct sh_eth_cpu_data sh_eth_my_cpu_data = { + .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, + .tsu = 1, +@@ -825,17 +728,6 @@ static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) + cd->tx_error_check = DEFAULT_TX_ERROR_CHECK; + } + +-#if defined(SH_ETH_RESET_DEFAULT) +-/* Chip Reset */ +-static int sh_eth_reset(struct net_device *ndev) +-{ +- sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, EDMR); +- mdelay(3); +- sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, EDMR); +- +- return 0; +-} +-#else + static int sh_eth_check_reset(struct net_device *ndev) + { + int ret = 0; +@@ -853,7 +745,49 @@ static int sh_eth_check_reset(struct net_device *ndev) + } + return ret; + } +-#endif ++ ++static int sh_eth_reset(struct net_device *ndev) ++{ ++ struct sh_eth_private *mdp = netdev_priv(ndev); ++ int ret = 0; ++ ++ if (sh_eth_is_gether(mdp)) { ++ sh_eth_write(ndev, EDSR_ENALL, EDSR); ++ sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, ++ EDMR); ++ ++ ret = sh_eth_check_reset(ndev); ++ if (ret) ++ goto out; ++ ++ /* Table Init */ ++ sh_eth_write(ndev, 0x0, TDLAR); ++ sh_eth_write(ndev, 0x0, TDFAR); ++ sh_eth_write(ndev, 0x0, TDFXR); ++ sh_eth_write(ndev, 0x0, TDFFR); ++ sh_eth_write(ndev, 0x0, RDLAR); ++ sh_eth_write(ndev, 0x0, RDFAR); ++ sh_eth_write(ndev, 0x0, RDFXR); ++ sh_eth_write(ndev, 0x0, RDFFR); ++ ++ /* Reset HW CRC register */ ++ if (mdp->cd->hw_crc) ++ sh_eth_write(ndev, 0x0, CSMR); ++ ++ /* Select MII mode */ ++ if (mdp->cd->select_mii) ++ sh_eth_select_mii(ndev); ++ } else { ++ sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, ++ EDMR); ++ mdelay(3); ++ sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, ++ EDMR); ++ } ++ ++out: ++ return ret; ++} + + #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) + static void sh_eth_set_receive_align(struct sk_buff *skb) +@@ -929,14 +863,6 @@ static void read_mac_address(struct net_device *ndev, unsigned char *mac) + } + } + +-static int sh_eth_is_gether(struct sh_eth_private *mdp) +-{ +- if (mdp->reg_offset == sh_eth_offset_gigabit) +- return 1; +- else +- return 0; +-} +- + static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp) + { + if (sh_eth_is_gether(mdp)) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0496-sh_eth-enclose-PM-code-into-ifdef-CONFIG_PM.patch b/patches.renesas/0496-sh_eth-enclose-PM-code-into-ifdef-CONFIG_PM.patch new file mode 100644 index 00000000000..465fe835783 --- /dev/null +++ b/patches.renesas/0496-sh_eth-enclose-PM-code-into-ifdef-CONFIG_PM.patch @@ -0,0 +1,59 @@ +From 6da0c0140db880075424d043c5ce6055421c3c74 Mon Sep 17 00:00:00 2001 +From: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> +Date: Thu, 6 Jun 2013 09:52:37 +0000 +Subject: sh_eth: enclose PM code into #ifdef CONFIG_PM + +Put '#ifdef CONFIG_PM' around sh_eth_runtime_nop() and 'sh_eth_dev_pm_ops'. +Add '#define SH_ETH_PM_OPS' to facilitate initialization of driver's 'pm' field +depending on whether CONFIG_PM is enabled. + +Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> +[Sergei: added the changelog, reworded the subject, changing the prefix.] +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> + +(cherry picked from commit 540ad1b888ad9564520c1c8c48ad675f76ffce62) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 9 +++++++-- + 1 file changed, 7 insertions(+), 2 deletions(-) + +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index cae8576a..0a7990a1 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -2685,6 +2685,7 @@ static int sh_eth_drv_remove(struct platform_device *pdev) + return 0; + } + ++#ifdef CONFIG_PM + static int sh_eth_runtime_nop(struct device *dev) + { + /* +@@ -2698,17 +2699,21 @@ static int sh_eth_runtime_nop(struct device *dev) + return 0; + } + +-static struct dev_pm_ops sh_eth_dev_pm_ops = { ++static const struct dev_pm_ops sh_eth_dev_pm_ops = { + .runtime_suspend = sh_eth_runtime_nop, + .runtime_resume = sh_eth_runtime_nop, + }; ++#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops) ++#else ++#define SH_ETH_PM_OPS NULL ++#endif + + static struct platform_driver sh_eth_driver = { + .probe = sh_eth_drv_probe, + .remove = sh_eth_drv_remove, + .driver = { + .name = CARDNAME, +- .pm = &sh_eth_dev_pm_ops, ++ .pm = SH_ETH_PM_OPS, + }, + }; + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0497-sh_eth-create-initial-ID-table.patch b/patches.renesas/0497-sh_eth-create-initial-ID-table.patch new file mode 100644 index 00000000000..bf835f4bbdc --- /dev/null +++ b/patches.renesas/0497-sh_eth-create-initial-ID-table.patch @@ -0,0 +1,61 @@ +From 87248a9cf0a516e4100e13d2adb90e75be32576b Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Fri, 7 Jun 2013 13:54:02 +0000 +Subject: sh_eth: create initial ID table + +We are trying to get away from the current driver's scheme of identifying a SoC +based on #ifdef's and the platform device ID table matching seems to be a good +replacement -- we can use the 'driver_data' field of 'struct platform_device_id' +as a pointer to a 'struct sh_eth_cpu_data'. Start by creating the initial table +with driver's name as the only entry without the driver data. Check the driver +data in the probe() method and if it's not NULL override 'mdp->cd' from it. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit afe391ad4b05f8f00ca955e165f3b37b480506b7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index 0a7990a1..ede2db2e 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -2530,6 +2530,7 @@ static int sh_eth_drv_probe(struct platform_device *pdev) + struct net_device *ndev = NULL; + struct sh_eth_private *mdp = NULL; + struct sh_eth_plat_data *pd = pdev->dev.platform_data; ++ const struct platform_device_id *id = platform_get_device_id(pdev); + + /* get base addr */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +@@ -2593,6 +2594,8 @@ static int sh_eth_drv_probe(struct platform_device *pdev) + #else + mdp->cd = &sh_eth_my_cpu_data; + #endif ++ if (id->driver_data) ++ mdp->cd = (struct sh_eth_cpu_data *)id->driver_data; + sh_eth_set_default_cpu_data(mdp->cd); + + /* set function */ +@@ -2708,9 +2711,16 @@ static const struct dev_pm_ops sh_eth_dev_pm_ops = { + #define SH_ETH_PM_OPS NULL + #endif + ++static struct platform_device_id sh_eth_id_table[] = { ++ { CARDNAME }, ++ { } ++}; ++MODULE_DEVICE_TABLE(platform, sh_eth_id_table); ++ + static struct platform_driver sh_eth_driver = { + .probe = sh_eth_drv_probe, + .remove = sh_eth_drv_remove, ++ .id_table = sh_eth_id_table, + .driver = { + .name = CARDNAME, + .pm = SH_ETH_PM_OPS, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0498-sh_eth-get-SH771x-support-out-of-ifdef.patch b/patches.renesas/0498-sh_eth-get-SH771x-support-out-of-ifdef.patch new file mode 100644 index 00000000000..b013a0eb846 --- /dev/null +++ b/patches.renesas/0498-sh_eth-get-SH771x-support-out-of-ifdef.patch @@ -0,0 +1,75 @@ +From 6b19db4f2c460792dda88c47d2290c4120ecab05 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Fri, 7 Jun 2013 13:55:08 +0000 +Subject: sh_eth: get SH771x support out of #ifdef + +Get the SH771[02] data in the driver out of #ifdef by adding "sh771x-ether" to +the platform driver's ID table. Change the Ether platform device's name in the +SH platform code accordingly. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 7bbe150d8c57c59689c8c50fd7b9915f4a7e10da) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/sh/boards/mach-se/770x/setup.c | 8 ++++---- + drivers/net/ethernet/renesas/sh_eth.c | 7 ++++--- + 2 files changed, 8 insertions(+), 7 deletions(-) + +diff --git a/arch/sh/boards/mach-se/770x/setup.c b/arch/sh/boards/mach-se/770x/setup.c +index 9759d6ba..658326f4 100644 +--- a/arch/sh/boards/mach-se/770x/setup.c ++++ b/arch/sh/boards/mach-se/770x/setup.c +@@ -128,8 +128,8 @@ static struct resource sh_eth0_resources[] = { + }; + + static struct platform_device sh_eth0_device = { +- .name = "sh-eth", +- .id = 0, ++ .name = "sh771x-ether", ++ .id = 0, + .dev = { + .platform_data = PHY_ID, + }, +@@ -151,8 +151,8 @@ static struct resource sh_eth1_resources[] = { + }; + + static struct platform_device sh_eth1_device = { +- .name = "sh-eth", +- .id = 1, ++ .name = "sh771x-ether", ++ .id = 1, + .dev = { + .platform_data = PHY_ID, + }, +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index ede2db2e..bb83b116 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -693,12 +693,12 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = { + .tpauser = 1, + .hw_swap = 1, + }; +-#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) +-static struct sh_eth_cpu_data sh_eth_my_cpu_data = { ++#endif ++ ++static struct sh_eth_cpu_data sh771x_data = { + .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, + .tsu = 1, + }; +-#endif + + static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) + { +@@ -2712,6 +2712,7 @@ static const struct dev_pm_ops sh_eth_dev_pm_ops = { + #endif + + static struct platform_device_id sh_eth_id_table[] = { ++ { "sh771x-ether", (kernel_ulong_t)&sh771x_data }, + { CARDNAME }, + { } + }; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0499-sh_eth-get-SH7619-support-out-of-ifdef.patch b/patches.renesas/0499-sh_eth-get-SH7619-support-out-of-ifdef.patch new file mode 100644 index 00000000000..ea39fccbbe5 --- /dev/null +++ b/patches.renesas/0499-sh_eth-get-SH7619-support-out-of-ifdef.patch @@ -0,0 +1,68 @@ +From da28d65329053e276847c7cbc3ad6f9534bc65d7 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Fri, 7 Jun 2013 13:56:05 +0000 +Subject: sh_eth: get SH7619 support out of #ifdef + +Get the SH7619 data in the driver out of #ifdef by adding "sh7619-ether" to the +platform driver's ID table. Change the Ether platform device's name in the SH +platform code accordingly. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit c18a79abe31f555ec3b363b5b8c1d003230053b6) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/sh/kernel/cpu/sh2/setup-sh7619.c | 4 ++-- + drivers/net/ethernet/renesas/sh_eth.c | 6 +++--- + 2 files changed, 5 insertions(+), 5 deletions(-) + +diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c +index e0b740c8..bb11e192 100644 +--- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c ++++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c +@@ -124,8 +124,8 @@ static struct resource eth_resources[] = { + }; + + static struct platform_device eth_device = { +- .name = "sh-eth", +- .id = -1, ++ .name = "sh7619-ether", ++ .id = -1, + .dev = { + .platform_data = (void *)1, + }, +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index bb83b116..96ec5783 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -683,9 +683,9 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = { + .tsu = 1, + .select_mii = 1, + }; ++#endif + +-#elif defined(CONFIG_CPU_SUBTYPE_SH7619) +-static struct sh_eth_cpu_data sh_eth_my_cpu_data = { ++static struct sh_eth_cpu_data sh7619_data = { + .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, + + .apr = 1, +@@ -693,7 +693,6 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = { + .tpauser = 1, + .hw_swap = 1, + }; +-#endif + + static struct sh_eth_cpu_data sh771x_data = { + .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, +@@ -2712,6 +2711,7 @@ static const struct dev_pm_ops sh_eth_dev_pm_ops = { + #endif + + static struct platform_device_id sh_eth_id_table[] = { ++ { "sh7619-ether", (kernel_ulong_t)&sh7619_data }, + { "sh771x-ether", (kernel_ulong_t)&sh771x_data }, + { CARDNAME }, + { } +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0500-sh_eth-get-R8A7740-support-out-of-ifdef.patch b/patches.renesas/0500-sh_eth-get-R8A7740-support-out-of-ifdef.patch new file mode 100644 index 00000000000..a7952f572b0 --- /dev/null +++ b/patches.renesas/0500-sh_eth-get-R8A7740-support-out-of-ifdef.patch @@ -0,0 +1,108 @@ +From 8448f88cf46ac5d2b771073b913733d1be639c30 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Fri, 7 Jun 2013 13:57:12 +0000 +Subject: sh_eth: get R8A7740 support out of #ifdef + +Get the R8A7740 code/data in the driver out of #ifdef by adding "r8a7740-gether" +to the platform driver's ID table. Change the GEther platform device's name in +the ARM platform code accordingly. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit e5c9b4cd665106d9b5397114ea81a53059410b6a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + arch/arm/mach-shmobile/clock-r8a7740.c +--- + arch/arm/mach-shmobile/board-armadillo800eva.c | 2 +- + arch/arm/mach-shmobile/clock-r8a7740.c | 2 +- + drivers/net/ethernet/renesas/sh_eth.c | 16 +++++++--------- + 3 files changed, 9 insertions(+), 11 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c +index 2ef31a69..4b247407 100644 +--- a/arch/arm/mach-shmobile/board-armadillo800eva.c ++++ b/arch/arm/mach-shmobile/board-armadillo800eva.c +@@ -379,7 +379,7 @@ static struct resource sh_eth_resources[] = { + }; + + static struct platform_device sh_eth_device = { +- .name = "sh-eth", ++ .name = "r8a7740-gether", + .id = -1, + .dev = { + .platform_data = &sh_eth_platdata, +diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c +index 664321c8..c826bca4 100644 +--- a/arch/arm/mach-shmobile/clock-r8a7740.c ++++ b/arch/arm/mach-shmobile/clock-r8a7740.c +@@ -594,7 +594,7 @@ static struct clk_lookup lookups[] = { + CLKDEV_DEV_ID("e6860000.sdhi", &mstp_clks[MSTP313]), + CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP312]), + CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), +- CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP309]), ++ CLKDEV_DEV_ID("r8a7740-gether", &mstp_clks[MSTP309]), + CLKDEV_DEV_ID("e9a00000.sh-eth", &mstp_clks[MSTP309]), + CLKDEV_DEV_ID("renesas-tpu-pwm", &mstp_clks[MSTP304]), + CLKDEV_DEV_ID("e6600000.pwm", &mstp_clks[MSTP304]), +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index 96ec5783..403b055f 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -622,11 +622,9 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = { + .irq_flags = IRQF_SHARED, + #endif + }; ++#endif + +- +-#elif defined(CONFIG_ARCH_R8A7740) +- +-static void sh_eth_chip_reset(struct net_device *ndev) ++static void sh_eth_chip_reset_r8a7740(struct net_device *ndev) + { + struct sh_eth_private *mdp = netdev_priv(ndev); + +@@ -637,7 +635,7 @@ static void sh_eth_chip_reset(struct net_device *ndev) + sh_eth_select_mii(ndev); + } + +-static void sh_eth_set_rate(struct net_device *ndev) ++static void sh_eth_set_rate_gether(struct net_device *ndev) + { + struct sh_eth_private *mdp = netdev_priv(ndev); + +@@ -657,10 +655,10 @@ static void sh_eth_set_rate(struct net_device *ndev) + } + + /* R8A7740 */ +-static struct sh_eth_cpu_data sh_eth_my_cpu_data = { +- .chip_reset = sh_eth_chip_reset, ++static struct sh_eth_cpu_data r8a7740_data = { ++ .chip_reset = sh_eth_chip_reset_r8a7740, + .set_duplex = sh_eth_set_duplex, +- .set_rate = sh_eth_set_rate, ++ .set_rate = sh_eth_set_rate_gether, + + .ecsr_value = ECSR_ICD | ECSR_MPD, + .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, +@@ -683,7 +681,6 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = { + .tsu = 1, + .select_mii = 1, + }; +-#endif + + static struct sh_eth_cpu_data sh7619_data = { + .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, +@@ -2713,6 +2710,7 @@ static const struct dev_pm_ops sh_eth_dev_pm_ops = { + static struct platform_device_id sh_eth_id_table[] = { + { "sh7619-ether", (kernel_ulong_t)&sh7619_data }, + { "sh771x-ether", (kernel_ulong_t)&sh771x_data }, ++ { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data }, + { CARDNAME }, + { } + }; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0501-sh_eth-get-SH77-34-63-support-out-of-ifdef.patch b/patches.renesas/0501-sh_eth-get-SH77-34-63-support-out-of-ifdef.patch new file mode 100644 index 00000000000..1abe852dbc1 --- /dev/null +++ b/patches.renesas/0501-sh_eth-get-SH77-34-63-support-out-of-ifdef.patch @@ -0,0 +1,181 @@ +From 1a92651a9dd29f035ce933d7d28ed800596d8acb Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Fri, 7 Jun 2013 13:58:18 +0000 +Subject: sh_eth: get SH77{34|63} support out of #ifdef + +Get the SH77{34|63} specific code/data in the driver out of #ifdef by adding +"sh7734-gether" and "sh7763-gether" to the platform driver's ID table. Note +that we have to split the 'struct sh_eth_cpu_data' instance into two due to +#ifdef inside it; note that we can kill the duplicate sh_eth_set_rate_gether(). +Change the GEther platform device's name in the SH platform code accordingly. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit f5d12767c8fd77e29d3d6771de59fd9ac3e540bb) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/sh/boards/board-espt.c | 2 +- + arch/sh/boards/mach-sh7763rdp/setup.c | 2 +- + arch/sh/kernel/cpu/sh4a/clock-sh7734.c | 2 +- + drivers/net/ethernet/renesas/sh_eth.c | 67 ++++++++++++++++++---------------- + 4 files changed, 39 insertions(+), 34 deletions(-) + +diff --git a/arch/sh/boards/board-espt.c b/arch/sh/boards/board-espt.c +index d71a0bcf..4d94dff9 100644 +--- a/arch/sh/boards/board-espt.c ++++ b/arch/sh/boards/board-espt.c +@@ -85,7 +85,7 @@ static struct sh_eth_plat_data sh7763_eth_pdata = { + }; + + static struct platform_device espt_eth_device = { +- .name = "sh-eth", ++ .name = "sh7763-gether", + .resource = sh_eth_resources, + .num_resources = ARRAY_SIZE(sh_eth_resources), + .dev = { +diff --git a/arch/sh/boards/mach-sh7763rdp/setup.c b/arch/sh/boards/mach-sh7763rdp/setup.c +index b7c75298..50ba481f 100644 +--- a/arch/sh/boards/mach-sh7763rdp/setup.c ++++ b/arch/sh/boards/mach-sh7763rdp/setup.c +@@ -93,7 +93,7 @@ static struct sh_eth_plat_data sh7763_eth_pdata = { + }; + + static struct platform_device sh7763rdp_eth_device = { +- .name = "sh-eth", ++ .name = "sh7763-gether", + .resource = sh_eth_resources, + .num_resources = ARRAY_SIZE(sh_eth_resources), + .dev = { +diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7734.c b/arch/sh/kernel/cpu/sh4a/clock-sh7734.c +index deb683ab..ed950151 100644 +--- a/arch/sh/kernel/cpu/sh4a/clock-sh7734.c ++++ b/arch/sh/kernel/cpu/sh4a/clock-sh7734.c +@@ -238,7 +238,7 @@ static struct clk_lookup lookups[] = { + CLKDEV_CON_ID("adc0", &mstp_clks[MSTP313]), + CLKDEV_CON_ID("mtu0", &mstp_clks[MSTP312]), + CLKDEV_CON_ID("iebus0", &mstp_clks[MSTP304]), +- CLKDEV_DEV_ID("sh-eth.0", &mstp_clks[MSTP114]), ++ CLKDEV_DEV_ID("sh7734-gether.0", &mstp_clks[MSTP114]), + CLKDEV_CON_ID("rtc0", &mstp_clks[MSTP303]), + CLKDEV_CON_ID("hif0", &mstp_clks[MSTP302]), + CLKDEV_CON_ID("stif0", &mstp_clks[MSTP301]), +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index 403b055f..bdc3f20f 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -559,8 +559,7 @@ static struct sh_eth_cpu_data *sh_eth_get_cpu_data(struct sh_eth_private *mdp) + else + return &sh_eth_my_cpu_data; + } +- +-#elif defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763) ++#endif + + static void sh_eth_chip_reset(struct net_device *ndev) + { +@@ -571,7 +570,7 @@ static void sh_eth_chip_reset(struct net_device *ndev) + mdelay(1); + } + +-static void sh_eth_set_rate(struct net_device *ndev) ++static void sh_eth_set_rate_gether(struct net_device *ndev) + { + struct sh_eth_private *mdp = netdev_priv(ndev); + +@@ -590,11 +589,40 @@ static void sh_eth_set_rate(struct net_device *ndev) + } + } + +-/* sh7763 */ +-static struct sh_eth_cpu_data sh_eth_my_cpu_data = { ++/* SH7734 */ ++static struct sh_eth_cpu_data sh7734_data = { + .chip_reset = sh_eth_chip_reset, + .set_duplex = sh_eth_set_duplex, +- .set_rate = sh_eth_set_rate, ++ .set_rate = sh_eth_set_rate_gether, ++ ++ .ecsr_value = ECSR_ICD | ECSR_MPD, ++ .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, ++ .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, ++ ++ .tx_check = EESR_TC1 | EESR_FTC, ++ .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \ ++ EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \ ++ EESR_ECI, ++ .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \ ++ EESR_TFE, ++ ++ .apr = 1, ++ .mpr = 1, ++ .tpauser = 1, ++ .bculr = 1, ++ .hw_swap = 1, ++ .no_trimd = 1, ++ .no_ade = 1, ++ .tsu = 1, ++ .hw_crc = 1, ++ .select_mii = 1, ++}; ++ ++/* SH7763 */ ++static struct sh_eth_cpu_data sh7763_data = { ++ .chip_reset = sh_eth_chip_reset, ++ .set_duplex = sh_eth_set_duplex, ++ .set_rate = sh_eth_set_rate_gether, + + .ecsr_value = ECSR_ICD | ECSR_MPD, + .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, +@@ -615,14 +643,8 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = { + .no_trimd = 1, + .no_ade = 1, + .tsu = 1, +-#if defined(CONFIG_CPU_SUBTYPE_SH7734) +- .hw_crc = 1, +- .select_mii = 1, +-#else + .irq_flags = IRQF_SHARED, +-#endif + }; +-#endif + + static void sh_eth_chip_reset_r8a7740(struct net_device *ndev) + { +@@ -635,25 +657,6 @@ static void sh_eth_chip_reset_r8a7740(struct net_device *ndev) + sh_eth_select_mii(ndev); + } + +-static void sh_eth_set_rate_gether(struct net_device *ndev) +-{ +- struct sh_eth_private *mdp = netdev_priv(ndev); +- +- switch (mdp->speed) { +- case 10: /* 10BASE */ +- sh_eth_write(ndev, GECMR_10, GECMR); +- break; +- case 100:/* 100BASE */ +- sh_eth_write(ndev, GECMR_100, GECMR); +- break; +- case 1000: /* 1000BASE */ +- sh_eth_write(ndev, GECMR_1000, GECMR); +- break; +- default: +- break; +- } +-} +- + /* R8A7740 */ + static struct sh_eth_cpu_data r8a7740_data = { + .chip_reset = sh_eth_chip_reset_r8a7740, +@@ -2710,6 +2713,8 @@ static const struct dev_pm_ops sh_eth_dev_pm_ops = { + static struct platform_device_id sh_eth_id_table[] = { + { "sh7619-ether", (kernel_ulong_t)&sh7619_data }, + { "sh771x-ether", (kernel_ulong_t)&sh771x_data }, ++ { "sh7734-gether", (kernel_ulong_t)&sh7734_data }, ++ { "sh7763-gether", (kernel_ulong_t)&sh7763_data }, + { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data }, + { CARDNAME }, + { } +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0502-sh_eth-get-SH7757-support-out-of-ifdef.patch b/patches.renesas/0502-sh_eth-get-SH7757-support-out-of-ifdef.patch new file mode 100644 index 00000000000..67314cb5739 --- /dev/null +++ b/patches.renesas/0502-sh_eth-get-SH7757-support-out-of-ifdef.patch @@ -0,0 +1,139 @@ +From bdd0eb06ad089d1dbdf30e0709bed488224faa9a Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Fri, 7 Jun 2013 13:59:21 +0000 +Subject: sh_eth: get SH7757 support out of #ifdef + +Get the SH7757 code/data in the driver out of #ifdef by adding "sh7757-ether" +and "sh7757-gether" to the platform driver's ID table. Note that we can remove +SH_ETH_HAS_BOTH_MODULES and sh_eth_get_cpu_data(). +Change the Ether/GEther platform devices' names in the SH platform code +accordingly. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 24549e2a0f33628b5160eac16c6aebf1cfaf22f1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/sh/boards/board-sh7757lcr.c | 8 ++++---- + drivers/net/ethernet/renesas/sh_eth.c | 28 ++++++++-------------------- + 2 files changed, 12 insertions(+), 24 deletions(-) + +diff --git a/arch/sh/boards/board-sh7757lcr.c b/arch/sh/boards/board-sh7757lcr.c +index 41f86702..4f114d1c 100644 +--- a/arch/sh/boards/board-sh7757lcr.c ++++ b/arch/sh/boards/board-sh7757lcr.c +@@ -82,7 +82,7 @@ static struct sh_eth_plat_data sh7757_eth0_pdata = { + }; + + static struct platform_device sh7757_eth0_device = { +- .name = "sh-eth", ++ .name = "sh7757-ether", + .resource = sh_eth0_resources, + .id = 0, + .num_resources = ARRAY_SIZE(sh_eth0_resources), +@@ -111,7 +111,7 @@ static struct sh_eth_plat_data sh7757_eth1_pdata = { + }; + + static struct platform_device sh7757_eth1_device = { +- .name = "sh-eth", ++ .name = "sh7757-ether", + .resource = sh_eth1_resources, + .id = 1, + .num_resources = ARRAY_SIZE(sh_eth1_resources), +@@ -157,7 +157,7 @@ static struct sh_eth_plat_data sh7757_eth_giga0_pdata = { + }; + + static struct platform_device sh7757_eth_giga0_device = { +- .name = "sh-eth", ++ .name = "sh7757-gether", + .resource = sh_eth_giga0_resources, + .id = 2, + .num_resources = ARRAY_SIZE(sh_eth_giga0_resources), +@@ -192,7 +192,7 @@ static struct sh_eth_plat_data sh7757_eth_giga1_pdata = { + }; + + static struct platform_device sh7757_eth_giga1_device = { +- .name = "sh-eth", ++ .name = "sh7757-gether", + .resource = sh_eth_giga1_resources, + .id = 3, + .num_resources = ARRAY_SIZE(sh_eth_giga1_resources), +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index bdc3f20f..9da357f1 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -433,10 +433,9 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = { + .rpadir = 1, + .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */ + }; +-#elif defined(CONFIG_CPU_SUBTYPE_SH7757) +-#define SH_ETH_HAS_BOTH_MODULES 1 ++#endif + +-static void sh_eth_set_rate(struct net_device *ndev) ++static void sh_eth_set_rate_sh7757(struct net_device *ndev) + { + struct sh_eth_private *mdp = netdev_priv(ndev); + +@@ -453,9 +452,9 @@ static void sh_eth_set_rate(struct net_device *ndev) + } + + /* SH7757 */ +-static struct sh_eth_cpu_data sh_eth_my_cpu_data = { +- .set_duplex = sh_eth_set_duplex, +- .set_rate = sh_eth_set_rate, ++static struct sh_eth_cpu_data sh7757_data = { ++ .set_duplex = sh_eth_set_duplex, ++ .set_rate = sh_eth_set_rate_sh7757, + + .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, + .rmcr_value = 0x00000001, +@@ -521,7 +520,7 @@ static void sh_eth_set_rate_giga(struct net_device *ndev) + } + + /* SH7757(GETHERC) */ +-static struct sh_eth_cpu_data sh_eth_my_cpu_data_giga = { ++static struct sh_eth_cpu_data sh7757_data_giga = { + .chip_reset = sh_eth_chip_reset_giga, + .set_duplex = sh_eth_set_duplex, + .set_rate = sh_eth_set_rate_giga, +@@ -552,15 +551,6 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data_giga = { + .tsu = 1, + }; + +-static struct sh_eth_cpu_data *sh_eth_get_cpu_data(struct sh_eth_private *mdp) +-{ +- if (sh_eth_is_gether(mdp)) +- return &sh_eth_my_cpu_data_giga; +- else +- return &sh_eth_my_cpu_data; +-} +-#endif +- + static void sh_eth_chip_reset(struct net_device *ndev) + { + struct sh_eth_private *mdp = netdev_priv(ndev); +@@ -2588,11 +2578,7 @@ static int sh_eth_drv_probe(struct platform_device *pdev) + mdp->reg_offset = sh_eth_get_register_offset(pd->register_type); + + /* set cpu data */ +-#if defined(SH_ETH_HAS_BOTH_MODULES) +- mdp->cd = sh_eth_get_cpu_data(mdp); +-#else + mdp->cd = &sh_eth_my_cpu_data; +-#endif + if (id->driver_data) + mdp->cd = (struct sh_eth_cpu_data *)id->driver_data; + sh_eth_set_default_cpu_data(mdp->cd); +@@ -2714,6 +2700,8 @@ static struct platform_device_id sh_eth_id_table[] = { + { "sh7619-ether", (kernel_ulong_t)&sh7619_data }, + { "sh771x-ether", (kernel_ulong_t)&sh771x_data }, + { "sh7734-gether", (kernel_ulong_t)&sh7734_data }, ++ { "sh7757-ether", (kernel_ulong_t)&sh7757_data }, ++ { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga }, + { "sh7763-gether", (kernel_ulong_t)&sh7763_data }, + { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data }, + { CARDNAME }, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0503-sh_eth-get-SH7724-support-out-of-ifdef.patch b/patches.renesas/0503-sh_eth-get-SH7724-support-out-of-ifdef.patch new file mode 100644 index 00000000000..c2d4c3f74cb --- /dev/null +++ b/patches.renesas/0503-sh_eth-get-SH7724-support-out-of-ifdef.patch @@ -0,0 +1,110 @@ +From 3a58fc67a2e4db1db7540517306c68580a8e5513 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Fri, 7 Jun 2013 14:03:37 +0000 +Subject: sh_eth: get SH7724 support out of #ifdef + +Get the SH7724 code/data in the driver out of #ifdef by adding "r8a7724-ether" +to the platform driver's ID table. Change the Ether platform device's name in +the SH platform code accordingly. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 9c3beaabb951d672b1534c7f56f84054b088f879) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/sh/boards/mach-ecovec24/setup.c | 4 ++-- + arch/sh/boards/mach-se/7724/setup.c | 4 ++-- + arch/sh/kernel/cpu/sh4a/clock-sh7724.c | 2 +- + drivers/net/ethernet/renesas/sh_eth.c | 10 +++++----- + 4 files changed, 10 insertions(+), 10 deletions(-) + +diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c +index 764530c8..61fade0f 100644 +--- a/arch/sh/boards/mach-ecovec24/setup.c ++++ b/arch/sh/boards/mach-ecovec24/setup.c +@@ -165,8 +165,8 @@ static struct sh_eth_plat_data sh_eth_plat = { + }; + + static struct platform_device sh_eth_device = { +- .name = "sh-eth", +- .id = 0, ++ .name = "sh7724-ether", ++ .id = 0, + .dev = { + .platform_data = &sh_eth_plat, + }, +diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c +index 4010e63e..b70180ef 100644 +--- a/arch/sh/boards/mach-se/7724/setup.c ++++ b/arch/sh/boards/mach-se/7724/setup.c +@@ -380,8 +380,8 @@ static struct sh_eth_plat_data sh_eth_plat = { + }; + + static struct platform_device sh_eth_device = { +- .name = "sh-eth", +- .id = 0, ++ .name = "sh7724-ether", ++ .id = 0, + .dev = { + .platform_data = &sh_eth_plat, + }, +diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c +index 5f30f805..0128af33 100644 +--- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c ++++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c +@@ -329,7 +329,7 @@ static struct clk_lookup lookups[] = { + CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC0]), + CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[HWBLK_IIC1]), + CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[HWBLK_MMC]), +- CLKDEV_DEV_ID("sh-eth.0", &mstp_clks[HWBLK_ETHER]), ++ CLKDEV_DEV_ID("sh7724-ether.0", &mstp_clks[HWBLK_ETHER]), + CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]), + CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]), + CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]), +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index 9da357f1..4af9cdba 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -393,9 +393,9 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = { + .tpauser = 1, + .hw_swap = 1, + }; +-#elif defined(CONFIG_CPU_SUBTYPE_SH7724) ++#endif + +-static void sh_eth_set_rate(struct net_device *ndev) ++static void sh_eth_set_rate_sh7724(struct net_device *ndev) + { + struct sh_eth_private *mdp = netdev_priv(ndev); + +@@ -412,9 +412,9 @@ static void sh_eth_set_rate(struct net_device *ndev) + } + + /* SH7724 */ +-static struct sh_eth_cpu_data sh_eth_my_cpu_data = { ++static struct sh_eth_cpu_data sh7724_data = { + .set_duplex = sh_eth_set_duplex, +- .set_rate = sh_eth_set_rate, ++ .set_rate = sh_eth_set_rate_sh7724, + + .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, + .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, +@@ -433,7 +433,6 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = { + .rpadir = 1, + .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */ + }; +-#endif + + static void sh_eth_set_rate_sh7757(struct net_device *ndev) + { +@@ -2699,6 +2698,7 @@ static const struct dev_pm_ops sh_eth_dev_pm_ops = { + static struct platform_device_id sh_eth_id_table[] = { + { "sh7619-ether", (kernel_ulong_t)&sh7619_data }, + { "sh771x-ether", (kernel_ulong_t)&sh771x_data }, ++ { "sh7724-ether", (kernel_ulong_t)&sh7724_data }, + { "sh7734-gether", (kernel_ulong_t)&sh7734_data }, + { "sh7757-ether", (kernel_ulong_t)&sh7757_data }, + { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga }, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0504-sh_eth-get-R8A777x-support-out-of-ifdef.patch b/patches.renesas/0504-sh_eth-get-R8A777x-support-out-of-ifdef.patch new file mode 100644 index 00000000000..2c148baa9de --- /dev/null +++ b/patches.renesas/0504-sh_eth-get-R8A777x-support-out-of-ifdef.patch @@ -0,0 +1,108 @@ +From b065eb241bb4db6c028fe7a0b37c438038664cca Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Fri, 7 Jun 2013 14:05:59 +0000 +Subject: sh_eth: get R8A777x support out of #ifdef + +Get the R-Car code/data in the driver out of #ifdef by adding "r8a777x-ether" to +the platfrom driver's ID table; since it's the last #ifdef, we remove CARDNAME +from the ID table and no longer check the driver data before assigning it to +'mdp->cd'... +Change the Ether platform device's name in the ARM platform code accordingly. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 589ebdef7e3107401bf96a9c660753d397329ee9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + arch/arm/mach-shmobile/clock-r8a7778.c + arch/arm/mach-shmobile/clock-r8a7779.c +--- + arch/arm/mach-shmobile/clock-r8a7778.c | 2 +- + arch/arm/mach-shmobile/clock-r8a7779.c | 2 +- + drivers/net/ethernet/renesas/sh_eth.c | 14 +++++--------- + 3 files changed, 7 insertions(+), 11 deletions(-) + +diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c +index dea199d4..c4bf2d8f 100644 +--- a/arch/arm/mach-shmobile/clock-r8a7778.c ++++ b/arch/arm/mach-shmobile/clock-r8a7778.c +@@ -148,7 +148,7 @@ static struct clk_lookup lookups[] = { + CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */ + CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ + CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ +- CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */ ++ CLKDEV_DEV_ID("r8a777x-ether", &mstp_clks[MSTP114]), /* Ether */ + CLKDEV_DEV_ID("r8a7778-vin.0", &mstp_clks[MSTP110]), /* VIN0 */ + CLKDEV_DEV_ID("r8a7778-vin.1", &mstp_clks[MSTP109]), /* VIN1 */ + CLKDEV_DEV_ID("ehci-platform", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */ +diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c +index 6070f3a4..bd6ad922 100644 +--- a/arch/arm/mach-shmobile/clock-r8a7779.c ++++ b/arch/arm/mach-shmobile/clock-r8a7779.c +@@ -172,7 +172,7 @@ static struct clk_lookup lookups[] = { + CLKDEV_DEV_ID("rcar-pcie", &mstp_clks[MSTP116]), /* PCIe */ + CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */ + CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */ +- CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */ ++ CLKDEV_DEV_ID("r8a777x-ether", &mstp_clks[MSTP114]), /* Ether */ + CLKDEV_DEV_ID("r8a7779-vin.0", &mstp_clks[MSTP110]), /* VIN0 */ + CLKDEV_DEV_ID("r8a7779-vin.1", &mstp_clks[MSTP109]), /* VIN1 */ + CLKDEV_DEV_ID("r8a7779-vin.2", &mstp_clks[MSTP108]), /* VIN2 */ +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index 4af9cdba..0e1f89bb 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -356,8 +356,7 @@ static void __maybe_unused sh_eth_set_duplex(struct net_device *ndev) + } + + /* There is CPU dependent code */ +-#if defined(CONFIG_ARCH_R8A7778) || defined(CONFIG_ARCH_R8A7779) +-static void sh_eth_set_rate(struct net_device *ndev) ++static void sh_eth_set_rate_r8a777x(struct net_device *ndev) + { + struct sh_eth_private *mdp = netdev_priv(ndev); + +@@ -374,9 +373,9 @@ static void sh_eth_set_rate(struct net_device *ndev) + } + + /* R8A7778/9 */ +-static struct sh_eth_cpu_data sh_eth_my_cpu_data = { ++static struct sh_eth_cpu_data r8a777x_data = { + .set_duplex = sh_eth_set_duplex, +- .set_rate = sh_eth_set_rate, ++ .set_rate = sh_eth_set_rate_r8a777x, + + .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, + .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, +@@ -393,7 +392,6 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = { + .tpauser = 1, + .hw_swap = 1, + }; +-#endif + + static void sh_eth_set_rate_sh7724(struct net_device *ndev) + { +@@ -2577,9 +2575,7 @@ static int sh_eth_drv_probe(struct platform_device *pdev) + mdp->reg_offset = sh_eth_get_register_offset(pd->register_type); + + /* set cpu data */ +- mdp->cd = &sh_eth_my_cpu_data; +- if (id->driver_data) +- mdp->cd = (struct sh_eth_cpu_data *)id->driver_data; ++ mdp->cd = (struct sh_eth_cpu_data *)id->driver_data; + sh_eth_set_default_cpu_data(mdp->cd); + + /* set function */ +@@ -2704,7 +2700,7 @@ static struct platform_device_id sh_eth_id_table[] = { + { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga }, + { "sh7763-gether", (kernel_ulong_t)&sh7763_data }, + { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data }, +- { CARDNAME }, ++ { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data }, + { } + }; + MODULE_DEVICE_TABLE(platform, sh_eth_id_table); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0505-sh_eth-remove-dependencies-from-Kconfig.patch b/patches.renesas/0505-sh_eth-remove-dependencies-from-Kconfig.patch new file mode 100644 index 00000000000..5c61790c7c5 --- /dev/null +++ b/patches.renesas/0505-sh_eth-remove-dependencies-from-Kconfig.patch @@ -0,0 +1,37 @@ +From 999239629ebad32a58535b0ffb225c1827675ce8 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Fri, 7 Jun 2013 14:07:13 +0000 +Subject: sh_eth: remove dependencies from Kconfig + +Since dependence on the certain SoCs is no longer necessary to compile the +driver, remove the dependency list from its Kconfig entry which is a popular +demand anyway... + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit eb770bf430bc1d4e1d23af353a80cfae2b237e66) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/Kconfig | 6 ------ + 1 file changed, 6 deletions(-) + +diff --git a/drivers/net/ethernet/renesas/Kconfig b/drivers/net/ethernet/renesas/Kconfig +index bed9841d..267eac05 100644 +--- a/drivers/net/ethernet/renesas/Kconfig ++++ b/drivers/net/ethernet/renesas/Kconfig +@@ -4,12 +4,6 @@ + + config SH_ETH + tristate "Renesas SuperH Ethernet support" +- depends on (SUPERH || ARCH_SHMOBILE) && \ +- (CPU_SUBTYPE_SH7710 || CPU_SUBTYPE_SH7712 || \ +- CPU_SUBTYPE_SH7763 || CPU_SUBTYPE_SH7619 || \ +- CPU_SUBTYPE_SH7724 || CPU_SUBTYPE_SH7734 || \ +- CPU_SUBTYPE_SH7757 || ARCH_R8A7740 || \ +- ARCH_R8A7778 || ARCH_R8A7779) + select CRC32 + select NET_CORE + select MII +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0506-sh_eth-Fix-warnings-on-64-bit.patch b/patches.renesas/0506-sh_eth-Fix-warnings-on-64-bit.patch new file mode 100644 index 00000000000..8481c979c19 --- /dev/null +++ b/patches.renesas/0506-sh_eth-Fix-warnings-on-64-bit.patch @@ -0,0 +1,39 @@ +From f2649bdb1df6020e1c10d4cf8a0b7553a6db8ea4 Mon Sep 17 00:00:00 2001 +From: "David S. Miller" <davem@davemloft.net> +Date: Fri, 7 Jun 2013 23:40:41 -0700 +Subject: sh_eth: Fix warnings on 64-bit. +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Don't cast a plain integer to a pointer. + +drivers/net/ethernet/renesas/sh_eth.c: In function ‘sh_eth_chip_reset_giga’: +drivers/net/ethernet/renesas/sh_eth.c:482:22: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] +drivers/net/ethernet/renesas/sh_eth.c:483:22: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] +drivers/net/ethernet/renesas/sh_eth.c:492:22: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] +drivers/net/ethernet/renesas/sh_eth.c:493:22: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit e403d295817cf9f8be3110eb7ee1a03981287495) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index 0e1f89bb..f5cb5416 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -472,7 +472,7 @@ static struct sh_eth_cpu_data sh7757_data = { + .rpadir_value = 2 << 16, + }; + +-#define SH_GIGA_ETH_BASE 0xfee00000 ++#define SH_GIGA_ETH_BASE 0xfee00000UL + #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8) + #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0) + static void sh_eth_chip_reset_giga(struct net_device *ndev) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0507-sh_eth-split-sh_eth_netdev_ops.patch b/patches.renesas/0507-sh_eth-split-sh_eth_netdev_ops.patch new file mode 100644 index 00000000000..5cb7c487056 --- /dev/null +++ b/patches.renesas/0507-sh_eth-split-sh_eth_netdev_ops.patch @@ -0,0 +1,77 @@ +From 14983cd66d94a51d6bc3eab41f8069979c8037c4 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Thu, 13 Jun 2013 00:55:34 +0400 +Subject: sh_eth: split 'sh_eth_netdev_ops' + +Commit 9f86134155047720a3685cda21467f68695152d2 (sh_eth: remove SH_ETH_HAS_TSU) +removes 'const' from 'sh_eth_netdev_ops' and modifies it in case TSU registers +are present. I've originally suggested to Iwamatsu-san to split this structure +in two instead and afterwards Dave M. suggested doing the same. +Split 'sh_eth_netdev_ops_tsu' from 'sh_eth_netdev_ops', making both 'const', and +assigning 'ndev->detdev_ops' depending on the presence of TSU registers. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 8f728d7934c77f63e89abcc96b46a7a98416d5c1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 29 ++++++++++++++++++++--------- + 1 file changed, 20 insertions(+), 9 deletions(-) + +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index f5cb5416..a651f766 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -2497,7 +2497,7 @@ static const u16 *sh_eth_get_register_offset(int register_type) + return reg_offset; + } + +-static struct net_device_ops sh_eth_netdev_ops = { ++static const struct net_device_ops sh_eth_netdev_ops = { + .ndo_open = sh_eth_open, + .ndo_stop = sh_eth_close, + .ndo_start_xmit = sh_eth_start_xmit, +@@ -2509,6 +2509,21 @@ static struct net_device_ops sh_eth_netdev_ops = { + .ndo_change_mtu = eth_change_mtu, + }; + ++static const struct net_device_ops sh_eth_netdev_ops_tsu = { ++ .ndo_open = sh_eth_open, ++ .ndo_stop = sh_eth_close, ++ .ndo_start_xmit = sh_eth_start_xmit, ++ .ndo_get_stats = sh_eth_get_stats, ++ .ndo_set_rx_mode = sh_eth_set_multicast_list, ++ .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid, ++ .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid, ++ .ndo_tx_timeout = sh_eth_tx_timeout, ++ .ndo_do_ioctl = sh_eth_do_ioctl, ++ .ndo_validate_addr = eth_validate_addr, ++ .ndo_set_mac_address = eth_mac_addr, ++ .ndo_change_mtu = eth_change_mtu, ++}; ++ + static int sh_eth_drv_probe(struct platform_device *pdev) + { + int ret, devno = 0; +@@ -2579,14 +2594,10 @@ static int sh_eth_drv_probe(struct platform_device *pdev) + sh_eth_set_default_cpu_data(mdp->cd); + + /* set function */ +- if (mdp->cd->tsu) { +- sh_eth_netdev_ops.ndo_set_rx_mode = sh_eth_set_multicast_list; +- sh_eth_netdev_ops.ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid; +- sh_eth_netdev_ops.ndo_vlan_rx_kill_vid = +- sh_eth_vlan_rx_kill_vid; +- } +- +- ndev->netdev_ops = &sh_eth_netdev_ops; ++ if (mdp->cd->tsu) ++ ndev->netdev_ops = &sh_eth_netdev_ops_tsu; ++ else ++ ndev->netdev_ops = &sh_eth_netdev_ops; + SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops); + ndev->watchdog_timeo = TX_TIMEOUT; + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0508-sh_eth-remove-__maybe_unused-annotations.patch b/patches.renesas/0508-sh_eth-remove-__maybe_unused-annotations.patch new file mode 100644 index 00000000000..0dd9c577597 --- /dev/null +++ b/patches.renesas/0508-sh_eth-remove-__maybe_unused-annotations.patch @@ -0,0 +1,42 @@ +From 5a9bf69e708354c299191567802f47586b5bf6b1 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Wed, 12 Jun 2013 03:07:29 +0400 +Subject: sh_eth: remove '__maybe_unused' annotations + +Now that the SoC specific support is no longer done with help of #ifdef'fery, +we no longer need '__maybe_unused' annotations to sh_eth_select_mii() and +sh_eth_set_duplex()... + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 8e994402ad5e6ae3d391c0935f9f1dc2eeb92a5e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index a651f766..56de4a6b 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -321,7 +321,7 @@ static int sh_eth_is_gether(struct sh_eth_private *mdp) + return 0; + } + +-static void __maybe_unused sh_eth_select_mii(struct net_device *ndev) ++static void sh_eth_select_mii(struct net_device *ndev) + { + u32 value = 0x0; + struct sh_eth_private *mdp = netdev_priv(ndev); +@@ -345,7 +345,7 @@ static void __maybe_unused sh_eth_select_mii(struct net_device *ndev) + sh_eth_write(ndev, value, RMII_MII); + } + +-static void __maybe_unused sh_eth_set_duplex(struct net_device *ndev) ++static void sh_eth_set_duplex(struct net_device *ndev) + { + struct sh_eth_private *mdp = netdev_priv(ndev); + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0509-sh_eth-define-use-EESR_RX_CHECK-macro.patch b/patches.renesas/0509-sh_eth-define-use-EESR_RX_CHECK-macro.patch new file mode 100644 index 00000000000..0bd2165a804 --- /dev/null +++ b/patches.renesas/0509-sh_eth-define-use-EESR_RX_CHECK-macro.patch @@ -0,0 +1,69 @@ +From 3d2dbcaa3c5537719dee8411c7e6df892f1f7c97 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Wed, 19 Jun 2013 23:29:23 +0400 +Subject: sh_eth: define/use EESR_RX_CHECK macro + +sh_eth_interrupt() uses the same Rx interrupt mask twice to check the interrupt +status register -- #define EESR_RX_CHECK and use it instead. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit ea7d69e75ac06daa7bc2fca2a8317197e5e3c81c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 13 ++----------- + drivers/net/ethernet/renesas/sh_eth.h | 8 ++++++++ + 2 files changed, 10 insertions(+), 11 deletions(-) + +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index 56de4a6b..cc9886cb 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -1508,23 +1508,14 @@ static irqreturn_t sh_eth_interrupt(int irq, void *netdev) + */ + intr_status &= sh_eth_read(ndev, EESIPR) | DMAC_M_ECI; + /* Clear interrupt */ +- if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF | +- EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF | +- cd->tx_check | cd->eesr_err_check)) { ++ if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check)) { + sh_eth_write(ndev, intr_status, EESR); + ret = IRQ_HANDLED; + } else + goto other_irq; + +- if (intr_status & (EESR_FRC | /* Frame recv*/ +- EESR_RMAF | /* Multi cast address recv*/ +- EESR_RRF | /* Bit frame recv */ +- EESR_RTLF | /* Long frame recv*/ +- EESR_RTSF | /* short frame recv */ +- EESR_PRE | /* PHY-LSI recv error */ +- EESR_CERF)){ /* recv frame CRC error */ ++ if (intr_status & EESR_RX_CHECK) + sh_eth_rx(ndev, intr_status); +- } + + /* Tx Check */ + if (intr_status & cd->tx_check) { +diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h +index 040d010b..117b3241 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.h ++++ b/drivers/net/ethernet/renesas/sh_eth.h +@@ -248,6 +248,14 @@ enum EESR_BIT { + EESR_CERF = 0x00000001, + }; + ++#define EESR_RX_CHECK (EESR_FRC | /* Frame recv */ \ ++ EESR_RMAF | /* Multicast address recv */ \ ++ EESR_RRF | /* Bit frame recv */ \ ++ EESR_RTLF | /* Long frame recv */ \ ++ EESR_RTSF | /* Short frame recv */ \ ++ EESR_PRE | /* PHY-LSI recv error */ \ ++ EESR_CERF) /* Recv frame CRC error */ ++ + #define DEFAULT_TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \ + EESR_RTO) + #define DEFAULT_EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | \ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0510-sh_eth-add-NAPI-support.patch b/patches.renesas/0510-sh_eth-add-NAPI-support.patch new file mode 100644 index 00000000000..58a7b8f8cce --- /dev/null +++ b/patches.renesas/0510-sh_eth-add-NAPI-support.patch @@ -0,0 +1,223 @@ +From 23522967989e4c40e5757c4e123362cad09a38cc Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Wed, 19 Jun 2013 23:30:23 +0400 +Subject: sh_eth: add NAPI support + +The driver hasn't used NAPI so far; implement its support at last... + +The patch was tested on Renesas R8A77781 BOCK-W board. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 3719109d61ca96746c733538ec776d02a6952640) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 85 ++++++++++++++++++++++++++++++----- + drivers/net/ethernet/renesas/sh_eth.h | 1 + + 2 files changed, 74 insertions(+), 12 deletions(-) + +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index cc9886cb..0389ac0e 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -1247,7 +1247,7 @@ static int sh_eth_txfree(struct net_device *ndev) + } + + /* Packet receive function */ +-static int sh_eth_rx(struct net_device *ndev, u32 intr_status) ++static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) + { + struct sh_eth_private *mdp = netdev_priv(ndev); + struct sh_eth_rxdesc *rxdesc; +@@ -1255,6 +1255,7 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status) + int entry = mdp->cur_rx % mdp->num_rx_ring; + int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx; + struct sk_buff *skb; ++ int exceeded = 0; + u16 pkt_len = 0; + u32 desc_status; + +@@ -1266,6 +1267,12 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status) + if (--boguscnt < 0) + break; + ++ if (*quota <= 0) { ++ exceeded = 1; ++ break; ++ } ++ (*quota)--; ++ + if (!(desc_status & RDFEND)) + ndev->stats.rx_length_errors++; + +@@ -1353,7 +1360,7 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status) + sh_eth_write(ndev, EDRRR_R, EDRRR); + } + +- return 0; ++ return exceeded; + } + + static void sh_eth_rcv_snd_disable(struct net_device *ndev) +@@ -1495,7 +1502,7 @@ static irqreturn_t sh_eth_interrupt(int irq, void *netdev) + struct sh_eth_private *mdp = netdev_priv(ndev); + struct sh_eth_cpu_data *cd = mdp->cd; + irqreturn_t ret = IRQ_NONE; +- unsigned long intr_status; ++ unsigned long intr_status, intr_enable; + + spin_lock(&mdp->lock); + +@@ -1506,25 +1513,41 @@ static irqreturn_t sh_eth_interrupt(int irq, void *netdev) + * and we need to fully handle it in sh_eth_error() in order to quench + * it as it doesn't get cleared by just writing 1 to the ECI bit... + */ +- intr_status &= sh_eth_read(ndev, EESIPR) | DMAC_M_ECI; +- /* Clear interrupt */ +- if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check)) { +- sh_eth_write(ndev, intr_status, EESR); ++ intr_enable = sh_eth_read(ndev, EESIPR); ++ intr_status &= intr_enable | DMAC_M_ECI; ++ if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check)) + ret = IRQ_HANDLED; +- } else ++ else + goto other_irq; + +- if (intr_status & EESR_RX_CHECK) +- sh_eth_rx(ndev, intr_status); ++ if (intr_status & EESR_RX_CHECK) { ++ if (napi_schedule_prep(&mdp->napi)) { ++ /* Mask Rx interrupts */ ++ sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK, ++ EESIPR); ++ __napi_schedule(&mdp->napi); ++ } else { ++ dev_warn(&ndev->dev, ++ "ignoring interrupt, status 0x%08lx, mask 0x%08lx.\n", ++ intr_status, intr_enable); ++ } ++ } + + /* Tx Check */ + if (intr_status & cd->tx_check) { ++ /* Clear Tx interrupts */ ++ sh_eth_write(ndev, intr_status & cd->tx_check, EESR); ++ + sh_eth_txfree(ndev); + netif_wake_queue(ndev); + } + +- if (intr_status & cd->eesr_err_check) ++ if (intr_status & cd->eesr_err_check) { ++ /* Clear error interrupts */ ++ sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR); ++ + sh_eth_error(ndev, intr_status); ++ } + + other_irq: + spin_unlock(&mdp->lock); +@@ -1532,6 +1555,33 @@ other_irq: + return ret; + } + ++static int sh_eth_poll(struct napi_struct *napi, int budget) ++{ ++ struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private, ++ napi); ++ struct net_device *ndev = napi->dev; ++ int quota = budget; ++ unsigned long intr_status; ++ ++ for (;;) { ++ intr_status = sh_eth_read(ndev, EESR); ++ if (!(intr_status & EESR_RX_CHECK)) ++ break; ++ /* Clear Rx interrupts */ ++ sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR); ++ ++ if (sh_eth_rx(ndev, intr_status, "a)) ++ goto out; ++ } ++ ++ napi_complete(napi); ++ ++ /* Reenable Rx interrupts */ ++ sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); ++out: ++ return budget - quota; ++} ++ + /* PHY state control function */ + static void sh_eth_adjust_link(struct net_device *ndev) + { +@@ -1843,6 +1893,8 @@ static int sh_eth_open(struct net_device *ndev) + if (ret) + goto out_free_irq; + ++ napi_enable(&mdp->napi); ++ + return ret; + + out_free_irq: +@@ -1938,6 +1990,8 @@ static int sh_eth_close(struct net_device *ndev) + { + struct sh_eth_private *mdp = netdev_priv(ndev); + ++ napi_disable(&mdp->napi); ++ + netif_stop_queue(ndev); + + /* Disable interrupts by clearing the interrupt mask. */ +@@ -2627,10 +2681,12 @@ static int sh_eth_drv_probe(struct platform_device *pdev) + } + } + ++ netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64); ++ + /* network device register */ + ret = register_netdev(ndev); + if (ret) +- goto out_release; ++ goto out_napi_del; + + /* mdio bus init */ + ret = sh_mdio_init(ndev, pdev->id, pd); +@@ -2648,6 +2704,9 @@ static int sh_eth_drv_probe(struct platform_device *pdev) + out_unregister: + unregister_netdev(ndev); + ++out_napi_del: ++ netif_napi_del(&mdp->napi); ++ + out_release: + /* net_dev free */ + if (ndev) +@@ -2660,9 +2719,11 @@ out: + static int sh_eth_drv_remove(struct platform_device *pdev) + { + struct net_device *ndev = platform_get_drvdata(pdev); ++ struct sh_eth_private *mdp = netdev_priv(ndev); + + sh_mdio_release(ndev); + unregister_netdev(ndev); ++ netif_napi_del(&mdp->napi); + pm_runtime_disable(&pdev->dev); + free_netdev(ndev); + platform_set_drvdata(pdev, NULL); +diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h +index 117b3241..99beb393 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.h ++++ b/drivers/net/ethernet/renesas/sh_eth.h +@@ -505,6 +505,7 @@ struct sh_eth_private { + u32 cur_tx, dirty_tx; + u32 rx_buf_sz; /* Based on MTU+slack. */ + int edmac_endian; ++ struct napi_struct napi; + /* MII transceiver section. */ + u32 phy_id; /* PHY ID */ + struct mii_bus *mii_bus; /* MDIO bus control */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0511-sh_eth-remove-tx_error_check-field-of-struct-sh_eth_.patch b/patches.renesas/0511-sh_eth-remove-tx_error_check-field-of-struct-sh_eth_.patch new file mode 100644 index 00000000000..4be0a72fb1b --- /dev/null +++ b/patches.renesas/0511-sh_eth-remove-tx_error_check-field-of-struct-sh_eth_.patch @@ -0,0 +1,118 @@ +From b26562eed71621d335808185a2b467a62ef01827 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Thu, 20 Jun 2013 02:22:56 +0400 +Subject: sh_eth: remove 'tx_error_check' field of 'struct sh_eth_cpu_data' + +The 'tx_error_check' field of 'struct sh_eth_cpu_data' is write-only, so remove +it along with the DEFAULT_TX_ERROR_CHECK macro. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 8f80899665c4baca5fe18e919a18db818c3e11fa) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + drivers/net/ethernet/renesas/sh_eth.c +--- + drivers/net/ethernet/renesas/sh_eth.c | 14 -------------- + drivers/net/ethernet/renesas/sh_eth.h | 3 --- + 2 files changed, 17 deletions(-) + +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index 0389ac0e..d8899f63 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -385,7 +385,6 @@ static struct sh_eth_cpu_data r8a777x_data = { + .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | + EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | + EESR_ECI, +- .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE, + + .apr = 1, + .mpr = 1, +@@ -422,7 +421,6 @@ static struct sh_eth_cpu_data sh7724_data = { + .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | + EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | + EESR_ECI, +- .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE, + + .apr = 1, + .mpr = 1, +@@ -460,7 +458,6 @@ static struct sh_eth_cpu_data sh7757_data = { + .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | + EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | + EESR_ECI, +- .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE, + + .irq_flags = IRQF_SHARED, + .apr = 1, +@@ -530,8 +527,6 @@ static struct sh_eth_cpu_data sh7757_data_giga = { + .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | + EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | + EESR_TDE | EESR_ECI, +- .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \ +- EESR_TFE, + .fdr_value = 0x0000072f, + .rmcr_value = 0x00000001, + +@@ -590,8 +585,6 @@ static struct sh_eth_cpu_data sh7734_data = { + .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \ + EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \ + EESR_ECI, +- .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \ +- EESR_TFE, + + .apr = 1, + .mpr = 1, +@@ -619,8 +612,6 @@ static struct sh_eth_cpu_data sh7763_data = { + .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | + EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | + EESR_TDE | EESR_ECI, +- .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \ +- EESR_TFE, + + .apr = 1, + .mpr = 1, +@@ -658,8 +649,6 @@ static struct sh_eth_cpu_data r8a7740_data = { + .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | + EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | + EESR_TDE | EESR_ECI, +- .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \ +- EESR_TFE, + + .apr = 1, + .mpr = 1, +@@ -709,9 +698,6 @@ static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) + + if (!cd->eesr_err_check) + cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK; +- +- if (!cd->tx_error_check) +- cd->tx_error_check = DEFAULT_TX_ERROR_CHECK; + } + + static int sh_eth_check_reset(struct net_device *ndev) +diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h +index 99beb393..5a06aaf1 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.h ++++ b/drivers/net/ethernet/renesas/sh_eth.h +@@ -261,8 +261,6 @@ enum EESR_BIT { + #define DEFAULT_EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | \ + EESR_RDE | EESR_RFRMER | EESR_ADE | \ + EESR_TFE | EESR_TDE | EESR_ECI) +-#define DEFAULT_TX_ERROR_CHECK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | \ +- EESR_TFE) + + /* EESIPR */ + enum DMAC_IM_BIT { +@@ -468,7 +466,6 @@ struct sh_eth_cpu_data { + /* interrupt checking mask */ + unsigned long tx_check; + unsigned long eesr_err_check; +- unsigned long tx_error_check; + + /* hardware features */ + unsigned long irq_flags; /* IRQ configuration flags */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0512-sh_eth-remove-redundant-bits-from-eesipr_value-field.patch b/patches.renesas/0512-sh_eth-remove-redundant-bits-from-eesipr_value-field.patch new file mode 100644 index 00000000000..ba46ecde431 --- /dev/null +++ b/patches.renesas/0512-sh_eth-remove-redundant-bits-from-eesipr_value-field.patch @@ -0,0 +1,32 @@ +From 2cd11e0ae55bac093bb99ab311d4a82d3295e77d Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Thu, 20 Jun 2013 02:24:54 +0400 +Subject: sh_eth: remove redundant bits from 'eesipr_value' field initializer + +For SH7724 'eesipr_value' field initializer includes DMAC_M_RFRMER & DMAC_M_ECI +bits which are already contained in 0x01ff009f -- remove them. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit a80c3de714bc4855747faf5f00e8203fb800e6bb) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index d8899f63..110aa717 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -415,7 +415,7 @@ static struct sh_eth_cpu_data sh7724_data = { + + .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, + .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, +- .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f, ++ .eesipr_value = 0x01ff009f, + + .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, + .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0513-sh_eth-cleanup-enum-TD_STS_BIT.patch b/patches.renesas/0513-sh_eth-cleanup-enum-TD_STS_BIT.patch new file mode 100644 index 00000000000..afd8d43cffc --- /dev/null +++ b/patches.renesas/0513-sh_eth-cleanup-enum-TD_STS_BIT.patch @@ -0,0 +1,39 @@ +From 56c2d49912b76156790a726de1ab39cca150e463 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Thu, 20 Jun 2013 02:26:14 +0400 +Subject: sh_eth: cleanup 'enum TD_STS_BIT' + +Fix the comment to 'enum TD_STS_BIT', reformat the values, and add a couple of +values missing before (though unused by the driver). + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit c8bbe37aa60a3ef694df65fed4e905bd4b1bd73c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.h | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h +index 5a06aaf1..a0257f40 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.h ++++ b/drivers/net/ethernet/renesas/sh_eth.h +@@ -302,11 +302,11 @@ enum FCFTR_BIT { + #define DEFAULT_FIFO_F_D_RFF (FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0) + #define DEFAULT_FIFO_F_D_RFD (FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0) + +-/* Transfer descriptor bit */ ++/* Transmit descriptor bit */ + enum TD_STS_BIT { +- TD_TACT = 0x80000000, +- TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000, +- TD_TFP0 = 0x10000000, ++ TD_TACT = 0x80000000, TD_TDLE = 0x40000000, ++ TD_TFP1 = 0x20000000, TD_TFP0 = 0x10000000, ++ TD_TFE = 0x08000000, TD_TWBI = 0x04000000, + }; + #define TDF1ST TD_TFP1 + #define TDFEND TD_TFP0 +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0514-sh_eth-get-R8A7740-Rx-descriptor-word-0-shift-out-of.patch b/patches.renesas/0514-sh_eth-get-R8A7740-Rx-descriptor-word-0-shift-out-of.patch new file mode 100644 index 00000000000..f84b3c3a271 --- /dev/null +++ b/patches.renesas/0514-sh_eth-get-R8A7740-Rx-descriptor-word-0-shift-out-of.patch @@ -0,0 +1,65 @@ +From 3d60fb22bd1b426f26924810233909d1610e9cbc Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Thu, 13 Jun 2013 22:12:45 +0400 +Subject: sh_eth: get R8A7740 Rx descriptor word 0 shift out of #ifdef + +The only R8A7740 specific #ifdef hindering ARM multiplatform build is left in +sh_eth_rx(): it covers the code shifting Rx buffer descriptor word 0 by 16. Get +rid of the #ifdef by adding 'shift_rd0' field to the 'struct sh_eth_cpu_data', +making the shift dependent on it, and setting it to 1 for the R8A7740 case... + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit ac8025a643a0e0beb81f3f37ca693364c6b77858) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 6 +++--- + drivers/net/ethernet/renesas/sh_eth.h | 1 + + 2 files changed, 4 insertions(+), 3 deletions(-) + +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index 110aa717..6ea2b9c4 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -659,6 +659,7 @@ static struct sh_eth_cpu_data r8a7740_data = { + .no_ade = 1, + .tsu = 1, + .select_mii = 1, ++ .shift_rd0 = 1, + }; + + static struct sh_eth_cpu_data sh7619_data = { +@@ -1262,7 +1263,6 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) + if (!(desc_status & RDFEND)) + ndev->stats.rx_length_errors++; + +-#if defined(CONFIG_ARCH_R8A7740) + /* + * In case of almost all GETHER/ETHERs, the Receive Frame State + * (RFS) bits in the Receive Descriptor 0 are from bit 9 to +@@ -1270,8 +1270,8 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) + * bits are from bit 25 to bit 16. So, the driver needs right + * shifting by 16. + */ +- desc_status >>= 16; +-#endif ++ if (mdp->cd->shift_rd0) ++ desc_status >>= 16; + + if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 | + RD_RFS5 | RD_RFS6 | RD_RFS10)) { +diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h +index a0257f40..99995bf3 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.h ++++ b/drivers/net/ethernet/renesas/sh_eth.h +@@ -481,6 +481,7 @@ struct sh_eth_cpu_data { + unsigned no_ade:1; /* E-DMAC DO NOT have ADE bit in EESR */ + unsigned hw_crc:1; /* E-DMAC have CSMR */ + unsigned select_mii:1; /* EtherC have RMII_MII (MII select register) */ ++ unsigned shift_rd0:1; /* shift Rx descriptor word 0 right by 16 */ + }; + + struct sh_eth_private { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0515-sh_eth-SH_ETH-should-depend-on-HAS_DMA.patch b/patches.renesas/0515-sh_eth-SH_ETH-should-depend-on-HAS_DMA.patch new file mode 100644 index 00000000000..eae6fe81ed3 --- /dev/null +++ b/patches.renesas/0515-sh_eth-SH_ETH-should-depend-on-HAS_DMA.patch @@ -0,0 +1,45 @@ +From 66e48a0d668ae8bc3c4acb8de00b192ae6d9d55d Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert@linux-m68k.org> +Date: Wed, 10 Jul 2013 23:03:34 +0200 +Subject: sh_eth: SH_ETH should depend on HAS_DMA + +If NO_DMA=y: + +drivers/built-in.o: In function `sh_eth_free_dma_buffer': +drivers/net/ethernet/renesas/sh_eth.c:1103: undefined reference to `dma_free_coherent' +drivers/net/ethernet/renesas/sh_eth.c:1110: undefined reference to `dma_free_coherent' +drivers/built-in.o: In function `sh_eth_ring_init': +drivers/net/ethernet/renesas/sh_eth.c:1065: undefined reference to `dma_alloc_coherent' +drivers/net/ethernet/renesas/sh_eth.c:1086: undefined reference to `dma_free_coherent' +drivers/built-in.o: In function `sh_eth_ring_format': +drivers/net/ethernet/renesas/sh_eth.c:988: undefined reference to `dma_map_single' +drivers/built-in.o: In function `sh_eth_txfree': +drivers/net/ethernet/renesas/sh_eth.c:1220: undefined reference to `dma_unmap_single' +drivers/built-in.o: In function `sh_eth_rx': +drivers/net/ethernet/renesas/sh_eth.c:1323: undefined reference to `dma_map_single' +drivers/built-in.o: In function `sh_eth_start_xmit': +drivers/net/ethernet/renesas/sh_eth.c:1954: undefined reference to `dma_map_single' + +Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit b41e6a51d57e231d2ed237f17f002cc536c0987c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/net/ethernet/renesas/Kconfig b/drivers/net/ethernet/renesas/Kconfig +index 267eac05..55527a12 100644 +--- a/drivers/net/ethernet/renesas/Kconfig ++++ b/drivers/net/ethernet/renesas/Kconfig +@@ -4,6 +4,7 @@ + + config SH_ETH + tristate "Renesas SuperH Ethernet support" ++ depends on HAS_DMA + select CRC32 + select NET_CORE + select MII +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0516-sh_eth-add-support-for-RMIIMODE-register.patch b/patches.renesas/0516-sh_eth-add-support-for-RMIIMODE-register.patch new file mode 100644 index 00000000000..1d3671345bd --- /dev/null +++ b/patches.renesas/0516-sh_eth-add-support-for-RMIIMODE-register.patch @@ -0,0 +1,61 @@ +From f11cc108bccc4550276fd532b587669366459d9a Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Tue, 23 Jul 2013 10:18:04 +0900 +Subject: sh_eth: add support for RMIIMODE register + +This register is prsent on the r8a7790 SoC. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 55754f19d7ee4fa3633f55a4a084af8590c35efa) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 4 ++++ + drivers/net/ethernet/renesas/sh_eth.h | 2 ++ + 2 files changed, 6 insertions(+) + +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index 6ea2b9c4..fb1c8c75 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -189,6 +189,7 @@ static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = { + [RMCR] = 0x0258, + [TFUCR] = 0x0264, + [RFOCR] = 0x0268, ++ [RMIIMODE] = 0x026c, + [FCFTR] = 0x0270, + [TRIMD] = 0x027c, + }; +@@ -1124,6 +1125,9 @@ static int sh_eth_dev_init(struct net_device *ndev, bool start) + if (ret) + goto out; + ++ if (mdp->cd->rmiimode) ++ sh_eth_write(ndev, 0x1, RMIIMODE); ++ + /* Descriptor format */ + sh_eth_ring_format(ndev); + if (mdp->cd->rpadir) +diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h +index 99995bf3..da93f5cf 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.h ++++ b/drivers/net/ethernet/renesas/sh_eth.h +@@ -60,6 +60,7 @@ enum { + EDOCR, + TFUCR, + RFOCR, ++ RMIIMODE, + FCFTR, + RPADIR, + TRIMD, +@@ -482,6 +483,7 @@ struct sh_eth_cpu_data { + unsigned hw_crc:1; /* E-DMAC have CSMR */ + unsigned select_mii:1; /* EtherC have RMII_MII (MII select register) */ + unsigned shift_rd0:1; /* shift Rx descriptor word 0 right by 16 */ ++ unsigned rmiimode:1; /* EtherC has RMIIMODE register */ + }; + + struct sh_eth_private { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0517-sh_eth-Add-support-for-r8a7790-SoC.patch b/patches.renesas/0517-sh_eth-Add-support-for-r8a7790-SoC.patch new file mode 100644 index 00000000000..99f56ee01c4 --- /dev/null +++ b/patches.renesas/0517-sh_eth-Add-support-for-r8a7790-SoC.patch @@ -0,0 +1,71 @@ +From 405cab1f5ee97b031d3f7e2b840aa1626591f1eb Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Tue, 23 Jul 2013 10:18:05 +0900 +Subject: sh_eth: Add support for r8a7790 SoC + +This is a copy of support for r8a7778/9 with the .rmiimode mode bit +of struct sh_eth_cpu_data set. + +Also update R8A7779 to R8A777x. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit e18dbf7efcb7a727e5db773597ddfd6981a530e6) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/Kconfig | 2 +- + drivers/net/ethernet/renesas/sh_eth.c | 21 +++++++++++++++++++++ + 2 files changed, 22 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/renesas/Kconfig b/drivers/net/ethernet/renesas/Kconfig +index 55527a12..c299e7f0 100644 +--- a/drivers/net/ethernet/renesas/Kconfig ++++ b/drivers/net/ethernet/renesas/Kconfig +@@ -14,4 +14,4 @@ config SH_ETH + Renesas SuperH Ethernet device driver. + This driver supporting CPUs are: + - SH7619, SH7710, SH7712, SH7724, SH7734, SH7763, SH7757, +- R8A7740 and R8A7779. ++ R8A7740, R8A777x and R8A7790. +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index fb1c8c75..9427ed9c 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -393,6 +393,26 @@ static struct sh_eth_cpu_data r8a777x_data = { + .hw_swap = 1, + }; + ++/* R8A7790 */ ++static struct sh_eth_cpu_data r8a7790_data = { ++ .set_duplex = sh_eth_set_duplex, ++ .set_rate = sh_eth_set_rate_r8a777x, ++ ++ .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, ++ .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, ++ .eesipr_value = 0x01ff009f, ++ ++ .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, ++ .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE | ++ EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI, ++ ++ .apr = 1, ++ .mpr = 1, ++ .tpauser = 1, ++ .hw_swap = 1, ++ .rmiimode = 1, ++}; ++ + static void sh_eth_set_rate_sh7724(struct net_device *ndev) + { + struct sh_eth_private *mdp = netdev_priv(ndev); +@@ -2754,6 +2774,7 @@ static struct platform_device_id sh_eth_id_table[] = { + { "sh7763-gether", (kernel_ulong_t)&sh7763_data }, + { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data }, + { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data }, ++ { "r8a7790-ether", (kernel_ulong_t)&r8a7790_data }, + { } + }; + MODULE_DEVICE_TABLE(platform, sh_eth_id_table); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0518-sh_eth-r8a7790-Handle-the-RFE-Receive-FIFO-overflow-.patch b/patches.renesas/0518-sh_eth-r8a7790-Handle-the-RFE-Receive-FIFO-overflow-.patch new file mode 100644 index 00000000000..fc2365e3cb2 --- /dev/null +++ b/patches.renesas/0518-sh_eth-r8a7790-Handle-the-RFE-Receive-FIFO-overflow-.patch @@ -0,0 +1,41 @@ +From 11011706857d4f65a3273f5c3584d76abbca1561 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Wed, 31 Jul 2013 16:42:11 +0900 +Subject: sh_eth: r8a7790: Handle the RFE (Receive FIFO overflow Error) + interrupt + +The RFE interrupt is enabled for the r8a7790 but isn't handled, +resulting in the interrupts core noticing unhandled interrupts, and +eventually disabling the ethernet IRQ. + +Fix it by adding RFE to the bitmask of error interrupts to be handled +for r8a7790. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit ba361cb3d4c977e2b94b5d97905f66b4d48964de) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index 9427ed9c..52ab996a 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -403,8 +403,9 @@ static struct sh_eth_cpu_data r8a7790_data = { + .eesipr_value = 0x01ff009f, + + .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, +- .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE | +- EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI, ++ .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | ++ EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | ++ EESR_ECI, + + .apr = 1, + .mpr = 1, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0519-sh_eth-get-register-layout-from-struct-sh_eth_cpu_da.patch b/patches.renesas/0519-sh_eth-get-register-layout-from-struct-sh_eth_cpu_da.patch new file mode 100644 index 00000000000..32f3b5e0cd7 --- /dev/null +++ b/patches.renesas/0519-sh_eth-get-register-layout-from-struct-sh_eth_cpu_da.patch @@ -0,0 +1,140 @@ +From 3ff32b6164d7bb13e58ec52c4a8d40e2e787605a Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Sun, 18 Aug 2013 03:11:28 +0400 +Subject: sh_eth: get register layout from 'struct sh_eth_cpu_data' + +The register layout is a SoC characteristic, so it's wrong that it's stored +in the otherwise board specific platform data. Add 'register_type' field to +'struct sh_eth_cpu_data', initialize it properly for each SoC, and read it +from this structure instead of the platfrom data from now on... + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit a3153d8c41132d6fda080a4b3e53b7ee25d3c125) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 22 +++++++++++++++++++++- + drivers/net/ethernet/renesas/sh_eth.h | 1 + + 2 files changed, 22 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index 52ab996a..ebce05b1 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -378,6 +378,8 @@ static struct sh_eth_cpu_data r8a777x_data = { + .set_duplex = sh_eth_set_duplex, + .set_rate = sh_eth_set_rate_r8a777x, + ++ .register_type = SH_ETH_REG_FAST_RCAR, ++ + .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, + .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, + .eesipr_value = 0x01ff009f, +@@ -398,6 +400,8 @@ static struct sh_eth_cpu_data r8a7790_data = { + .set_duplex = sh_eth_set_duplex, + .set_rate = sh_eth_set_rate_r8a777x, + ++ .register_type = SH_ETH_REG_FAST_RCAR, ++ + .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, + .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, + .eesipr_value = 0x01ff009f, +@@ -435,6 +439,8 @@ static struct sh_eth_cpu_data sh7724_data = { + .set_duplex = sh_eth_set_duplex, + .set_rate = sh_eth_set_rate_sh7724, + ++ .register_type = SH_ETH_REG_FAST_SH4, ++ + .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, + .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, + .eesipr_value = 0x01ff009f, +@@ -473,6 +479,8 @@ static struct sh_eth_cpu_data sh7757_data = { + .set_duplex = sh_eth_set_duplex, + .set_rate = sh_eth_set_rate_sh7757, + ++ .register_type = SH_ETH_REG_FAST_SH4, ++ + .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, + .rmcr_value = 0x00000001, + +@@ -541,6 +549,8 @@ static struct sh_eth_cpu_data sh7757_data_giga = { + .set_duplex = sh_eth_set_duplex, + .set_rate = sh_eth_set_rate_giga, + ++ .register_type = SH_ETH_REG_GIGABIT, ++ + .ecsr_value = ECSR_ICD | ECSR_MPD, + .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, + .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, +@@ -599,6 +609,8 @@ static struct sh_eth_cpu_data sh7734_data = { + .set_duplex = sh_eth_set_duplex, + .set_rate = sh_eth_set_rate_gether, + ++ .register_type = SH_ETH_REG_GIGABIT, ++ + .ecsr_value = ECSR_ICD | ECSR_MPD, + .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, + .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, +@@ -626,6 +638,8 @@ static struct sh_eth_cpu_data sh7763_data = { + .set_duplex = sh_eth_set_duplex, + .set_rate = sh_eth_set_rate_gether, + ++ .register_type = SH_ETH_REG_GIGABIT, ++ + .ecsr_value = ECSR_ICD | ECSR_MPD, + .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, + .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, +@@ -663,6 +677,8 @@ static struct sh_eth_cpu_data r8a7740_data = { + .set_duplex = sh_eth_set_duplex, + .set_rate = sh_eth_set_rate_gether, + ++ .register_type = SH_ETH_REG_GIGABIT, ++ + .ecsr_value = ECSR_ICD | ECSR_MPD, + .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, + .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, +@@ -685,6 +701,8 @@ static struct sh_eth_cpu_data r8a7740_data = { + }; + + static struct sh_eth_cpu_data sh7619_data = { ++ .register_type = SH_ETH_REG_FAST_SH3_SH2, ++ + .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, + + .apr = 1, +@@ -694,6 +712,8 @@ static struct sh_eth_cpu_data sh7619_data = { + }; + + static struct sh_eth_cpu_data sh771x_data = { ++ .register_type = SH_ETH_REG_FAST_SH3_SH2, ++ + .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, + .tsu = 1, + }; +@@ -2643,10 +2663,10 @@ static int sh_eth_drv_probe(struct platform_device *pdev) + mdp->edmac_endian = pd->edmac_endian; + mdp->no_ether_link = pd->no_ether_link; + mdp->ether_link_active_low = pd->ether_link_active_low; +- mdp->reg_offset = sh_eth_get_register_offset(pd->register_type); + + /* set cpu data */ + mdp->cd = (struct sh_eth_cpu_data *)id->driver_data; ++ mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type); + sh_eth_set_default_cpu_data(mdp->cd); + + /* set function */ +diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h +index da93f5cf..1e785281 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.h ++++ b/drivers/net/ethernet/renesas/sh_eth.h +@@ -454,6 +454,7 @@ struct sh_eth_cpu_data { + void (*set_rate)(struct net_device *ndev); + + /* mandatory initialize value */ ++ int register_type; + unsigned long eesipr_value; + + /* optional initialize value */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0520-sh_eth-remove-register_type-field-from-struct-sh_eth.patch b/patches.renesas/0520-sh_eth-remove-register_type-field-from-struct-sh_eth.patch new file mode 100644 index 00000000000..8f75984af18 --- /dev/null +++ b/patches.renesas/0520-sh_eth-remove-register_type-field-from-struct-sh_eth.patch @@ -0,0 +1,169 @@ +From 17c1ddfff070927bd8b1d07d6b4ce2bd84ef2918 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Sun, 18 Aug 2013 03:13:26 +0400 +Subject: sh_eth: remove 'register_type' field from 'struct sh_eth_plat_data' + +Now that the 'register_type' field of the 'sh_eth' driver's platform data is not +used by the driver anymore, it's time to remove it and its initializers from +the SH platform code. Also move *enum* declaring values for this field from +<linux/sh_eth.h> to the local driver's header file as they're only needed +by the driver itself now... + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 8d3214c4e8c8be6efd8ec7a172239ebbd4deb04b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + arch/sh/boards/mach-se/7724/setup.c + arch/sh/kernel/cpu/sh2/setup-sh7619.c +--- + arch/arm/mach-shmobile/board-armadillo800eva.c | 1 - + arch/arm/mach-shmobile/board-bockw.c | 1 - + arch/sh/boards/board-espt.c | 1 - + arch/sh/boards/board-sh7757lcr.c | 4 ---- + arch/sh/boards/mach-ecovec24/setup.c | 1 - + arch/sh/boards/mach-sh7763rdp/setup.c | 1 - + drivers/net/ethernet/renesas/sh_eth.h | 7 +++++++ + include/linux/sh_eth.h | 7 ------- + 8 files changed, 7 insertions(+), 16 deletions(-) + +diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c +index 4b247407..06802584 100644 +--- a/arch/arm/mach-shmobile/board-armadillo800eva.c ++++ b/arch/arm/mach-shmobile/board-armadillo800eva.c +@@ -359,7 +359,6 @@ static struct platform_device usbhsf_device = { + static struct sh_eth_plat_data sh_eth_platdata = { + .phy = 0x00, /* LAN8710A */ + .edmac_endian = EDMAC_LITTLE_ENDIAN, +- .register_type = SH_ETH_REG_GIGABIT, + .phy_interface = PHY_INTERFACE_MODE_MII, + }; + +diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c +index 127ad3a0..6b9faf39 100644 +--- a/arch/arm/mach-shmobile/board-bockw.c ++++ b/arch/arm/mach-shmobile/board-bockw.c +@@ -104,7 +104,6 @@ static struct resource sdhi0_resources[] __initdata = { + static struct sh_eth_plat_data ether_platform_data __initdata = { + .phy = 0x01, + .edmac_endian = EDMAC_LITTLE_ENDIAN, +- .register_type = SH_ETH_REG_FAST_RCAR, + .phy_interface = PHY_INTERFACE_MODE_RMII, + /* + * Although the LINK signal is available on the board, it's connected to +diff --git a/arch/sh/boards/board-espt.c b/arch/sh/boards/board-espt.c +index 4d94dff9..7291e2f1 100644 +--- a/arch/sh/boards/board-espt.c ++++ b/arch/sh/boards/board-espt.c +@@ -80,7 +80,6 @@ static struct resource sh_eth_resources[] = { + static struct sh_eth_plat_data sh7763_eth_pdata = { + .phy = 0, + .edmac_endian = EDMAC_LITTLE_ENDIAN, +- .register_type = SH_ETH_REG_GIGABIT, + .phy_interface = PHY_INTERFACE_MODE_MII, + }; + +diff --git a/arch/sh/boards/board-sh7757lcr.c b/arch/sh/boards/board-sh7757lcr.c +index 4f114d1c..25c5a932 100644 +--- a/arch/sh/boards/board-sh7757lcr.c ++++ b/arch/sh/boards/board-sh7757lcr.c +@@ -77,7 +77,6 @@ static struct resource sh_eth0_resources[] = { + static struct sh_eth_plat_data sh7757_eth0_pdata = { + .phy = 1, + .edmac_endian = EDMAC_LITTLE_ENDIAN, +- .register_type = SH_ETH_REG_FAST_SH4, + .set_mdio_gate = sh7757_eth_set_mdio_gate, + }; + +@@ -106,7 +105,6 @@ static struct resource sh_eth1_resources[] = { + static struct sh_eth_plat_data sh7757_eth1_pdata = { + .phy = 1, + .edmac_endian = EDMAC_LITTLE_ENDIAN, +- .register_type = SH_ETH_REG_FAST_SH4, + .set_mdio_gate = sh7757_eth_set_mdio_gate, + }; + +@@ -151,7 +149,6 @@ static struct resource sh_eth_giga0_resources[] = { + static struct sh_eth_plat_data sh7757_eth_giga0_pdata = { + .phy = 18, + .edmac_endian = EDMAC_LITTLE_ENDIAN, +- .register_type = SH_ETH_REG_GIGABIT, + .set_mdio_gate = sh7757_eth_giga_set_mdio_gate, + .phy_interface = PHY_INTERFACE_MODE_RGMII_ID, + }; +@@ -186,7 +183,6 @@ static struct resource sh_eth_giga1_resources[] = { + static struct sh_eth_plat_data sh7757_eth_giga1_pdata = { + .phy = 19, + .edmac_endian = EDMAC_LITTLE_ENDIAN, +- .register_type = SH_ETH_REG_GIGABIT, + .set_mdio_gate = sh7757_eth_giga_set_mdio_gate, + .phy_interface = PHY_INTERFACE_MODE_RGMII_ID, + }; +diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c +index 61fade0f..a4f630f0 100644 +--- a/arch/sh/boards/mach-ecovec24/setup.c ++++ b/arch/sh/boards/mach-ecovec24/setup.c +@@ -159,7 +159,6 @@ static struct resource sh_eth_resources[] = { + static struct sh_eth_plat_data sh_eth_plat = { + .phy = 0x1f, /* SMSC LAN8700 */ + .edmac_endian = EDMAC_LITTLE_ENDIAN, +- .register_type = SH_ETH_REG_FAST_SH4, + .phy_interface = PHY_INTERFACE_MODE_MII, + .ether_link_active_low = 1 + }; +diff --git a/arch/sh/boards/mach-sh7763rdp/setup.c b/arch/sh/boards/mach-sh7763rdp/setup.c +index 50ba481f..2c8fb046 100644 +--- a/arch/sh/boards/mach-sh7763rdp/setup.c ++++ b/arch/sh/boards/mach-sh7763rdp/setup.c +@@ -88,7 +88,6 @@ static struct resource sh_eth_resources[] = { + static struct sh_eth_plat_data sh7763_eth_pdata = { + .phy = 1, + .edmac_endian = EDMAC_LITTLE_ENDIAN, +- .register_type = SH_ETH_REG_GIGABIT, + .phy_interface = PHY_INTERFACE_MODE_MII, + }; + +diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h +index 1e785281..a0db02c6 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.h ++++ b/drivers/net/ethernet/renesas/sh_eth.h +@@ -157,6 +157,13 @@ enum { + SH_ETH_MAX_REGISTER_OFFSET, + }; + ++enum { ++ SH_ETH_REG_GIGABIT, ++ SH_ETH_REG_FAST_RCAR, ++ SH_ETH_REG_FAST_SH4, ++ SH_ETH_REG_FAST_SH3_SH2 ++}; ++ + /* Driver's parameters */ + #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) + #define SH4_SKB_RX_ALIGN 32 +diff --git a/include/linux/sh_eth.h b/include/linux/sh_eth.h +index fc305713..15b2ea93 100644 +--- a/include/linux/sh_eth.h ++++ b/include/linux/sh_eth.h +@@ -4,17 +4,10 @@ + #include <linux/phy.h> + + enum {EDMAC_LITTLE_ENDIAN, EDMAC_BIG_ENDIAN}; +-enum { +- SH_ETH_REG_GIGABIT, +- SH_ETH_REG_FAST_RCAR, +- SH_ETH_REG_FAST_SH4, +- SH_ETH_REG_FAST_SH3_SH2 +-}; + + struct sh_eth_plat_data { + int phy; + int edmac_endian; +- int register_type; + phy_interface_t phy_interface; + void (*set_mdio_gate)(void *addr); + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0521-sh_eth-no-need-to-call-ether_setup.patch b/patches.renesas/0521-sh_eth-no-need-to-call-ether_setup.patch new file mode 100644 index 00000000000..4ad9e06645e --- /dev/null +++ b/patches.renesas/0521-sh_eth-no-need-to-call-ether_setup.patch @@ -0,0 +1,34 @@ +From a8d83262c60b31c311400349d1a32e2e92da9981 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Fri, 30 Aug 2013 00:24:47 +0400 +Subject: sh_eth: no need to call ether_setup() + +There's no need to call ether_setup() in the driver since prior alloc_etherdev() +call already arranges for it. + +Suggested-by: Denis Kirjanov <kda@linux-powerpc.org> +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 488594883e25cc6e40df067a9a7b39737ebb18d8) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 3 --- + 1 file changed, 3 deletions(-) + +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index ebce05b1..c6dad5f6 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -2639,9 +2639,6 @@ static int sh_eth_drv_probe(struct platform_device *pdev) + + SET_NETDEV_DEV(ndev, &pdev->dev); + +- /* Fill in the fields of the device structure with ethernet values. */ +- ether_setup(ndev); +- + mdp = netdev_priv(ndev); + mdp->num_tx_ring = TX_RING_SIZE; + mdp->num_rx_ring = RX_RING_SIZE; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0522-sh_eth-Fix-cache-invalidation-omission-of-receive-bu.patch b/patches.renesas/0522-sh_eth-Fix-cache-invalidation-omission-of-receive-bu.patch new file mode 100644 index 00000000000..663eb11bfcf --- /dev/null +++ b/patches.renesas/0522-sh_eth-Fix-cache-invalidation-omission-of-receive-bu.patch @@ -0,0 +1,31 @@ +From 1ae0eaf241bcf29e94ade3007d7dbf61801c4309 Mon Sep 17 00:00:00 2001 +From: Kouei Abe <kouei.abe.cp@renesas.com> +Date: Fri, 30 Aug 2013 12:41:07 +0900 +Subject: sh_eth: Fix cache invalidation omission of receive buffer + +Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 7db8e0c14c9cb4adb667b4c558d8ffec8d5b40f2) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index c6dad5f6..fb8479f4 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -1342,6 +1342,9 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) + mdp->rx_skbuff[entry] = NULL; + if (mdp->cd->rpadir) + skb_reserve(skb, NET_IP_ALIGN); ++ dma_sync_single_for_cpu(&ndev->dev, rxdesc->addr, ++ mdp->rx_buf_sz, ++ DMA_FROM_DEVICE); + skb_put(skb, pkt_len); + skb->protocol = eth_type_trans(skb, ndev); + netif_rx(skb); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0523-sh_eth-Enable-Rx-descriptor-word-0-shift-for-r8a7790.patch b/patches.renesas/0523-sh_eth-Enable-Rx-descriptor-word-0-shift-for-r8a7790.patch new file mode 100644 index 00000000000..7123953e452 --- /dev/null +++ b/patches.renesas/0523-sh_eth-Enable-Rx-descriptor-word-0-shift-for-r8a7790.patch @@ -0,0 +1,31 @@ +From 24f39918b5018f1228e7913a2587057ae7a50054 Mon Sep 17 00:00:00 2001 +From: Kouei Abe <kouei.abe.cp@renesas.com> +Date: Fri, 30 Aug 2013 12:41:08 +0900 +Subject: sh_eth: Enable Rx descriptor word 0 shift for r8a7790 + +This corrects an oversight when r8a7790 support was added to sh_eth. + +Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit fd9af07c3404ac9ecbd0d859563360f51ce1ffde) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index fb8479f4..08b3050e 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -416,6 +416,7 @@ static struct sh_eth_cpu_data r8a7790_data = { + .tpauser = 1, + .hw_swap = 1, + .rmiimode = 1, ++ .shift_rd0 = 1, + }; + + static void sh_eth_set_rate_sh7724(struct net_device *ndev) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0524-sh_eth-NAPI-requires-netif_receive_skb.patch b/patches.renesas/0524-sh_eth-NAPI-requires-netif_receive_skb.patch new file mode 100644 index 00000000000..30b8a3fa830 --- /dev/null +++ b/patches.renesas/0524-sh_eth-NAPI-requires-netif_receive_skb.patch @@ -0,0 +1,32 @@ +From a5cb389053b00c663f46403cc9cb5d53a89f8135 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Tue, 3 Sep 2013 03:03:10 +0400 +Subject: sh_eth: NAPI requires netif_receive_skb() + +Driver supporting NAPI should use NAPI-specific function for receiving packets, +so netif_rx() should be changed to netif_receive_skb(). + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit a8e9fd0f7462f5cada5189513d12fe6c9cce2105) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index 08b3050e..16e7b9b5 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -1348,7 +1348,7 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) + DMA_FROM_DEVICE); + skb_put(skb, pkt_len); + skb->protocol = eth_type_trans(skb, ndev); +- netif_rx(skb); ++ netif_receive_skb(skb); + ndev->stats.rx_packets++; + ndev->stats.rx_bytes += pkt_len; + } +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0525-sh_eth-fix-napi_-en-dis-able-calls-racing-against-in.patch b/patches.renesas/0525-sh_eth-fix-napi_-en-dis-able-calls-racing-against-in.patch new file mode 100644 index 00000000000..ba319addfbe --- /dev/null +++ b/patches.renesas/0525-sh_eth-fix-napi_-en-dis-able-calls-racing-against-in.patch @@ -0,0 +1,81 @@ +From 63a25646ed48425f7cfd4bd4f8d77db134e50a80 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Wed, 4 Sep 2013 02:41:27 +0400 +Subject: sh_eth: fix napi_{en|dis}able() calls racing against interrupts + +While implementing NAPI for the driver, I overlooked the race conditions where +interrupt handler might have called napi_schedule_prep() before napi_enable() +was called or after napi_disable() was called. If RX interrupt happens, this +would cause the endless interrupts and messages like: + +sh-eth eth0: ignoring interrupt, status 0x00040000, mask 0x01ff009f. + +The interrupt wouldn't even be masked by the kernel eventually since the handler +would return IRQ_HANDLED all the time. + +As a fix, move napi_enable() call before request_irq() call and napi_disable() +call after free_irq() call. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit d2779e99468fd83ef1493c34f3803fec9aad8345) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 12 +++++++----- + 1 file changed, 7 insertions(+), 5 deletions(-) + +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index 16e7b9b5..dfb208f0 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -1906,11 +1906,13 @@ static int sh_eth_open(struct net_device *ndev) + + pm_runtime_get_sync(&mdp->pdev->dev); + ++ napi_enable(&mdp->napi); ++ + ret = request_irq(ndev->irq, sh_eth_interrupt, + mdp->cd->irq_flags, ndev->name, ndev); + if (ret) { + dev_err(&ndev->dev, "Can not assign IRQ number\n"); +- return ret; ++ goto out_napi_off; + } + + /* Descriptor set */ +@@ -1928,12 +1930,12 @@ static int sh_eth_open(struct net_device *ndev) + if (ret) + goto out_free_irq; + +- napi_enable(&mdp->napi); +- + return ret; + + out_free_irq: + free_irq(ndev->irq, ndev); ++out_napi_off: ++ napi_disable(&mdp->napi); + pm_runtime_put_sync(&mdp->pdev->dev); + return ret; + } +@@ -2025,8 +2027,6 @@ static int sh_eth_close(struct net_device *ndev) + { + struct sh_eth_private *mdp = netdev_priv(ndev); + +- napi_disable(&mdp->napi); +- + netif_stop_queue(ndev); + + /* Disable interrupts by clearing the interrupt mask. */ +@@ -2044,6 +2044,8 @@ static int sh_eth_close(struct net_device *ndev) + + free_irq(ndev->irq, ndev); + ++ napi_disable(&mdp->napi); ++ + /* Free all the skbuffs in the Rx queue. */ + sh_eth_ring_free(ndev); + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0526-net-sh_eth-Fix-RX-packets-errors-on-R8A7740.patch b/patches.renesas/0526-net-sh_eth-Fix-RX-packets-errors-on-R8A7740.patch new file mode 100644 index 00000000000..832da8e90cd --- /dev/null +++ b/patches.renesas/0526-net-sh_eth-Fix-RX-packets-errors-on-R8A7740.patch @@ -0,0 +1,58 @@ +From 6dbc5cc93029eb031a1bcae8690392f5e39065f4 Mon Sep 17 00:00:00 2001 +From: Nguyen Hong Ky <nh-ky@jinso.co.jp> +Date: Mon, 7 Oct 2013 15:29:25 +0900 +Subject: net: sh_eth: Fix RX packets errors on R8A7740 + +This patch will fix RX packets errors when receiving big size +of data by set bit RNC = 1. + +RNC - Receive Enable Control + +0: Upon completion of reception of one frame, the E-DMAC writes +the receive status to the descriptor and clears the RR bit in +EDRRR to 0. + +1: Upon completion of reception of one frame, the E-DMAC writes +(writes back) the receive status to the descriptor. In addition, +the E-DMAC reads the next descriptor and prepares for reception +of the next frame. + +In addition, for get more stable when receiving packets, I set +maximum size for the transmit/receive FIFO and inserts padding +in receive data. + +Signed-off-by: Nguyen Hong Ky <nh-ky@jinso.co.jp> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 2c6221e4a5aab417cb18bef6f1130d1374240258) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + drivers/net/ethernet/renesas/sh_eth.c +--- + drivers/net/ethernet/renesas/sh_eth.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index dfb208f0..bfa7a201 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -620,12 +620,16 @@ static struct sh_eth_cpu_data sh7734_data = { + .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \ + EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \ + EESR_ECI, ++ .fdr_value = 0x0000070f, ++ .rmcr_value = 0x00000001, + + .apr = 1, + .mpr = 1, + .tpauser = 1, + .bculr = 1, + .hw_swap = 1, ++ .rpadir = 1, ++ .rpadir_value = 2 << 16, + .no_trimd = 1, + .no_ade = 1, + .tsu = 1, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0527-net-sh_eth-Correct-fix-for-RX-packet-errors-on-R8A77.patch b/patches.renesas/0527-net-sh_eth-Correct-fix-for-RX-packet-errors-on-R8A77.patch new file mode 100644 index 00000000000..4f399155c3b --- /dev/null +++ b/patches.renesas/0527-net-sh_eth-Correct-fix-for-RX-packet-errors-on-R8A77.patch @@ -0,0 +1,67 @@ +From 810e035088db52878190eb438d157d3a9a243fa0 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Thu, 10 Oct 2013 14:51:16 +0900 +Subject: net: sh_eth: Correct fix for RX packet errors on R8A7740 + +Nguyen Hong Ky posted a patch to correct RX packet errors on R8A7740 which +was applied as 2c6221e4a5aab417 ("net: sh_eth: Fix RX packets errors on +R8A7740"). Unfortunately sh_eth.c contains many similar instances +of struct sh_eth_cpu_data and the patch was miss-applied, updating +sh7734_data instead of r8a7740_data. + +This patch corrects this problem by. +1. Reverting the change to sh7734_data and; +2. Applying the change to r8a7740_data. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit cc23528db0300d5c8c0b98670a577bf1dc3e0e82) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + drivers/net/ethernet/renesas/sh_eth.c +--- + drivers/net/ethernet/renesas/sh_eth.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index bfa7a201..b54bbbd5 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -620,16 +620,12 @@ static struct sh_eth_cpu_data sh7734_data = { + .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \ + EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \ + EESR_ECI, +- .fdr_value = 0x0000070f, +- .rmcr_value = 0x00000001, + + .apr = 1, + .mpr = 1, + .tpauser = 1, + .bculr = 1, + .hw_swap = 1, +- .rpadir = 1, +- .rpadir_value = 2 << 16, + .no_trimd = 1, + .no_ade = 1, + .tsu = 1, +@@ -692,12 +688,16 @@ static struct sh_eth_cpu_data r8a7740_data = { + .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | + EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | + EESR_TDE | EESR_ECI, ++ .fdr_value = 0x0000070f, ++ .rmcr_value = 0x00000001, + + .apr = 1, + .mpr = 1, + .tpauser = 1, + .bculr = 1, + .hw_swap = 1, ++ .rpadir = 1, ++ .rpadir_value = 2 << 16, + .no_trimd = 1, + .no_ade = 1, + .tsu = 1, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0528-sh-pfc-sh7720-Remove-unused-input_pu-range.patch b/patches.renesas/0528-sh-pfc-sh7720-Remove-unused-input_pu-range.patch new file mode 100644 index 00000000000..bd2d48fd922 --- /dev/null +++ b/patches.renesas/0528-sh-pfc-sh7720-Remove-unused-input_pu-range.patch @@ -0,0 +1,625 @@ +From 975b2a9770e516fa369a57af073c750ed8cd6b87 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 16 Jul 2013 01:54:13 +0200 +Subject: sh-pfc: sh7720: Remove unused input_pu range + +The PFC SH7720 SoC data contains a input_pu range used to configure +pull-up resistors using the legacy non-pinconf API. That API has been +removed from the driver, the range is thus not used anymore. Remove it. + +If required, configuring pull-up resistors for the SH7720 can be +implemented using the pinconf API, as done for the SH-Mobile, R-Mobile +and R-Car platforms. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit 7f975b3f1e2b1416d02863fb10e0f69f3d668c77) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-sh7720.c | 465 +++++++++++++++++------------------- + 1 file changed, 217 insertions(+), 248 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7720.c b/drivers/pinctrl/sh-pfc/pfc-sh7720.c +index 52e9f6be..3b96d612 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7720.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7720.c +@@ -81,36 +81,6 @@ enum { + PTV4_IN, PTV3_IN, PTV2_IN, PTV1_IN, PTV0_IN, + PINMUX_INPUT_END, + +- PINMUX_INPUT_PULLUP_BEGIN, +- PTA7_IN_PU, PTA6_IN_PU, PTA5_IN_PU, PTA4_IN_PU, +- PTA3_IN_PU, PTA2_IN_PU, PTA1_IN_PU, PTA0_IN_PU, +- PTB7_IN_PU, PTB6_IN_PU, PTB5_IN_PU, PTB4_IN_PU, +- PTB3_IN_PU, PTB2_IN_PU, PTB1_IN_PU, PTB0_IN_PU, +- PTC7_IN_PU, PTC6_IN_PU, PTC5_IN_PU, PTC4_IN_PU, +- PTC3_IN_PU, PTC2_IN_PU, PTC1_IN_PU, PTC0_IN_PU, +- PTD7_IN_PU, PTD6_IN_PU, PTD5_IN_PU, PTD4_IN_PU, +- PTD3_IN_PU, PTD2_IN_PU, PTD1_IN_PU, PTD0_IN_PU, +- PTE4_IN_PU, PTE3_IN_PU, PTE2_IN_PU, PTE1_IN_PU, PTE0_IN_PU, +- PTF0_IN_PU, +- PTG6_IN_PU, PTG5_IN_PU, PTG4_IN_PU, +- PTG3_IN_PU, PTG2_IN_PU, PTG1_IN_PU, PTG0_IN_PU, +- PTH6_IN_PU, PTH5_IN_PU, PTH4_IN_PU, +- PTH3_IN_PU, PTH2_IN_PU, PTH1_IN_PU, PTH0_IN_PU, +- PTJ6_IN_PU, PTJ5_IN_PU, PTJ4_IN_PU, +- PTJ3_IN_PU, PTJ2_IN_PU, PTJ1_IN_PU, PTJ0_IN_PU, +- PTK3_IN_PU, PTK2_IN_PU, PTK1_IN_PU, PTK0_IN_PU, +- PTL7_IN_PU, PTL6_IN_PU, PTL5_IN_PU, PTL4_IN_PU, PTL3_IN_PU, +- PTM7_IN_PU, PTM6_IN_PU, PTM5_IN_PU, PTM4_IN_PU, +- PTM3_IN_PU, PTM2_IN_PU, PTM1_IN_PU, PTM0_IN_PU, +- PTP4_IN_PU, PTP3_IN_PU, PTP2_IN_PU, PTP1_IN_PU, PTP0_IN_PU, +- PTR7_IN_PU, PTR6_IN_PU, PTR5_IN_PU, PTR4_IN_PU, +- PTR3_IN_PU, PTR2_IN_PU, PTR1_IN_PU, PTR0_IN_PU, +- PTS4_IN_PU, PTS3_IN_PU, PTS2_IN_PU, PTS1_IN_PU, PTS0_IN_PU, +- PTT4_IN_PU, PTT3_IN_PU, PTT2_IN_PU, PTT1_IN_PU, PTT0_IN_PU, +- PTU4_IN_PU, PTU3_IN_PU, PTU2_IN_PU, PTU1_IN_PU, PTU0_IN_PU, +- PTV4_IN_PU, PTV3_IN_PU, PTV2_IN_PU, PTV1_IN_PU, PTV0_IN_PU, +- PINMUX_INPUT_PULLUP_END, +- + PINMUX_OUTPUT_BEGIN, + PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT, + PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT, +@@ -264,53 +234,53 @@ enum { + + static const pinmux_enum_t pinmux_data[] = { + /* PTA GPIO */ +- PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT, PTA7_IN_PU), +- PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT, PTA6_IN_PU), +- PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT, PTA5_IN_PU), +- PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT, PTA4_IN_PU), +- PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT, PTA3_IN_PU), +- PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT, PTA2_IN_PU), +- PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT, PTA1_IN_PU), +- PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT, PTA0_IN_PU), ++ PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT), ++ PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT), ++ PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT), ++ PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT), ++ PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT), ++ PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT), ++ PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT), ++ PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT), + + /* PTB GPIO */ +- PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT, PTB7_IN_PU), +- PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT, PTB6_IN_PU), +- PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT, PTB5_IN_PU), +- PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT, PTB4_IN_PU), +- PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT, PTB3_IN_PU), +- PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT, PTB2_IN_PU), +- PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT, PTB1_IN_PU), +- PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT, PTB0_IN_PU), ++ PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT), ++ PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT), ++ PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT), ++ PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT), ++ PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT), ++ PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT), ++ PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT), ++ PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT), + + /* PTC GPIO */ +- PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT, PTC7_IN_PU), +- PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT, PTC6_IN_PU), +- PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT, PTC5_IN_PU), +- PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT, PTC4_IN_PU), +- PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT, PTC3_IN_PU), +- PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT, PTC2_IN_PU), +- PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT, PTC1_IN_PU), +- PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT, PTC0_IN_PU), ++ PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT), ++ PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT), ++ PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT), ++ PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT), ++ PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT), ++ PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT), ++ PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT), ++ PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT), + + /* PTD GPIO */ +- PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT, PTD7_IN_PU), +- PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT, PTD6_IN_PU), +- PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT, PTD5_IN_PU), +- PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT, PTD4_IN_PU), +- PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT, PTD3_IN_PU), +- PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT, PTD2_IN_PU), +- PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT, PTD1_IN_PU), +- PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT, PTD0_IN_PU), ++ PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT), ++ PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT), ++ PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT), ++ PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT), ++ PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT), ++ PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT), ++ PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT), ++ PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT), + + /* PTE GPIO */ + PINMUX_DATA(PTE6_DATA, PTE6_IN), + PINMUX_DATA(PTE5_DATA, PTE5_IN), +- PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT, PTE4_IN_PU), +- PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT, PTE3_IN_PU), +- PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT, PTE2_IN_PU), +- PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT, PTE1_IN_PU), +- PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT, PTE0_IN_PU), ++ PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT), ++ PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT), ++ PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT), ++ PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT), ++ PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT), + + /* PTF GPIO */ + PINMUX_DATA(PTF6_DATA, PTF6_IN), +@@ -319,102 +289,102 @@ static const pinmux_enum_t pinmux_data[] = { + PINMUX_DATA(PTF3_DATA, PTF3_IN), + PINMUX_DATA(PTF2_DATA, PTF2_IN), + PINMUX_DATA(PTF1_DATA, PTF1_IN), +- PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT, PTF0_IN_PU), ++ PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT), + + /* PTG GPIO */ +- PINMUX_DATA(PTG6_DATA, PTG6_IN, PTG6_OUT, PTG6_IN_PU), +- PINMUX_DATA(PTG5_DATA, PTG5_IN, PTG5_OUT, PTG5_IN_PU), +- PINMUX_DATA(PTG4_DATA, PTG4_IN, PTG4_OUT, PTG4_IN_PU), +- PINMUX_DATA(PTG3_DATA, PTG3_IN, PTG3_OUT, PTG3_IN_PU), +- PINMUX_DATA(PTG2_DATA, PTG2_IN, PTG2_OUT, PTG2_IN_PU), +- PINMUX_DATA(PTG1_DATA, PTG1_IN, PTG1_OUT, PTG1_IN_PU), +- PINMUX_DATA(PTG0_DATA, PTG0_IN, PTG0_OUT, PTG0_IN_PU), ++ PINMUX_DATA(PTG6_DATA, PTG6_IN, PTG6_OUT), ++ PINMUX_DATA(PTG5_DATA, PTG5_IN, PTG5_OUT), ++ PINMUX_DATA(PTG4_DATA, PTG4_IN, PTG4_OUT), ++ PINMUX_DATA(PTG3_DATA, PTG3_IN, PTG3_OUT), ++ PINMUX_DATA(PTG2_DATA, PTG2_IN, PTG2_OUT), ++ PINMUX_DATA(PTG1_DATA, PTG1_IN, PTG1_OUT), ++ PINMUX_DATA(PTG0_DATA, PTG0_IN, PTG0_OUT), + + /* PTH GPIO */ +- PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT, PTH6_IN_PU), +- PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT, PTH5_IN_PU), +- PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT, PTH4_IN_PU), +- PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT, PTH3_IN_PU), +- PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT, PTH2_IN_PU), +- PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT, PTH1_IN_PU), +- PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT, PTH0_IN_PU), ++ PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT), ++ PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT), ++ PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT), ++ PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT), ++ PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT), ++ PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT), ++ PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT), + + /* PTJ GPIO */ +- PINMUX_DATA(PTJ6_DATA, PTJ6_IN, PTJ6_OUT, PTJ6_IN_PU), +- PINMUX_DATA(PTJ5_DATA, PTJ5_IN, PTJ5_OUT, PTJ5_IN_PU), +- PINMUX_DATA(PTJ4_DATA, PTJ4_IN, PTJ4_OUT, PTJ4_IN_PU), +- PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT, PTJ3_IN_PU), +- PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT, PTJ2_IN_PU), +- PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT, PTJ1_IN_PU), +- PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT, PTJ0_IN_PU), ++ PINMUX_DATA(PTJ6_DATA, PTJ6_IN, PTJ6_OUT), ++ PINMUX_DATA(PTJ5_DATA, PTJ5_IN, PTJ5_OUT), ++ PINMUX_DATA(PTJ4_DATA, PTJ4_IN, PTJ4_OUT), ++ PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT), ++ PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT), ++ PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT), ++ PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT), + + /* PTK GPIO */ +- PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT, PTK3_IN_PU), +- PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT, PTK2_IN_PU), +- PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT, PTK1_IN_PU), +- PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT, PTK0_IN_PU), ++ PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT), ++ PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT), ++ PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT), ++ PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT), + + /* PTL GPIO */ +- PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT, PTL7_IN_PU), +- PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT, PTL6_IN_PU), +- PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT, PTL5_IN_PU), +- PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT, PTL4_IN_PU), +- PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT, PTL3_IN_PU), ++ PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT), ++ PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT), ++ PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT), ++ PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT), ++ PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT), + + /* PTM GPIO */ +- PINMUX_DATA(PTM7_DATA, PTM7_IN, PTM7_OUT, PTM7_IN_PU), +- PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT, PTM6_IN_PU), +- PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT, PTM5_IN_PU), +- PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT, PTM4_IN_PU), +- PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT, PTM3_IN_PU), +- PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT, PTM2_IN_PU), +- PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT, PTM1_IN_PU), +- PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT, PTM0_IN_PU), ++ PINMUX_DATA(PTM7_DATA, PTM7_IN, PTM7_OUT), ++ PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT), ++ PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT), ++ PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT), ++ PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT), ++ PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT), ++ PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT), ++ PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT), + + /* PTP GPIO */ +- PINMUX_DATA(PTP4_DATA, PTP4_IN, PTP4_OUT, PTP4_IN_PU), +- PINMUX_DATA(PTP3_DATA, PTP3_IN, PTP3_OUT, PTP3_IN_PU), +- PINMUX_DATA(PTP2_DATA, PTP2_IN, PTP2_OUT, PTP2_IN_PU), +- PINMUX_DATA(PTP1_DATA, PTP1_IN, PTP1_OUT, PTP1_IN_PU), +- PINMUX_DATA(PTP0_DATA, PTP0_IN, PTP0_OUT, PTP0_IN_PU), ++ PINMUX_DATA(PTP4_DATA, PTP4_IN, PTP4_OUT), ++ PINMUX_DATA(PTP3_DATA, PTP3_IN, PTP3_OUT), ++ PINMUX_DATA(PTP2_DATA, PTP2_IN, PTP2_OUT), ++ PINMUX_DATA(PTP1_DATA, PTP1_IN, PTP1_OUT), ++ PINMUX_DATA(PTP0_DATA, PTP0_IN, PTP0_OUT), + + /* PTR GPIO */ +- PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT, PTR7_IN_PU), +- PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT, PTR6_IN_PU), +- PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT, PTR5_IN_PU), +- PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT, PTR4_IN_PU), +- PINMUX_DATA(PTR3_DATA, PTR3_IN, PTR3_OUT, PTR3_IN_PU), +- PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_OUT, PTR2_IN_PU), +- PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT, PTR1_IN_PU), +- PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT, PTR0_IN_PU), ++ PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT), ++ PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT), ++ PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT), ++ PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT), ++ PINMUX_DATA(PTR3_DATA, PTR3_IN, PTR3_OUT), ++ PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_OUT), ++ PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT), ++ PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT), + + /* PTS GPIO */ +- PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT, PTS4_IN_PU), +- PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT, PTS3_IN_PU), +- PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT, PTS2_IN_PU), +- PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT, PTS1_IN_PU), +- PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT, PTS0_IN_PU), ++ PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT), ++ PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT), ++ PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT), ++ PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT), ++ PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT), + + /* PTT GPIO */ +- PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT, PTT4_IN_PU), +- PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT, PTT3_IN_PU), +- PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT, PTT2_IN_PU), +- PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT, PTT1_IN_PU), +- PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT, PTT0_IN_PU), ++ PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT), ++ PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT), ++ PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT), ++ PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT), ++ PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT), + + /* PTU GPIO */ +- PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT, PTU4_IN_PU), +- PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT, PTU3_IN_PU), +- PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT, PTU2_IN_PU), +- PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT, PTU1_IN_PU), +- PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT, PTU0_IN_PU), ++ PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT), ++ PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT), ++ PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT), ++ PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT), ++ PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT), + + /* PTV GPIO */ +- PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT, PTV4_IN_PU), +- PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT, PTV3_IN_PU), +- PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT, PTV2_IN_PU), +- PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT, PTV1_IN_PU), +- PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT, PTV0_IN_PU), ++ PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT), ++ PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT), ++ PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT), ++ PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT), ++ PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT), + + /* PTA FN */ + PINMUX_DATA(D23_MARK, PTA7_FN), +@@ -959,54 +929,54 @@ static const struct pinmux_func pinmux_func_gpios[] = { + + static const struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { +- PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN, +- PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN, +- PTA5_FN, PTA5_OUT, PTA5_IN_PU, PTA5_IN, +- PTA4_FN, PTA4_OUT, PTA4_IN_PU, PTA4_IN, +- PTA3_FN, PTA3_OUT, PTA3_IN_PU, PTA3_IN, +- PTA2_FN, PTA2_OUT, PTA2_IN_PU, PTA2_IN, +- PTA1_FN, PTA1_OUT, PTA1_IN_PU, PTA1_IN, +- PTA0_FN, PTA0_OUT, PTA0_IN_PU, PTA0_IN } ++ PTA7_FN, PTA7_OUT, 0, PTA7_IN, ++ PTA6_FN, PTA6_OUT, 0, PTA6_IN, ++ PTA5_FN, PTA5_OUT, 0, PTA5_IN, ++ PTA4_FN, PTA4_OUT, 0, PTA4_IN, ++ PTA3_FN, PTA3_OUT, 0, PTA3_IN, ++ PTA2_FN, PTA2_OUT, 0, PTA2_IN, ++ PTA1_FN, PTA1_OUT, 0, PTA1_IN, ++ PTA0_FN, PTA0_OUT, 0, PTA0_IN } + }, + { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) { +- PTB7_FN, PTB7_OUT, PTB7_IN_PU, PTB7_IN, +- PTB6_FN, PTB6_OUT, PTB6_IN_PU, PTB6_IN, +- PTB5_FN, PTB5_OUT, PTB5_IN_PU, PTB5_IN, +- PTB4_FN, PTB4_OUT, PTB4_IN_PU, PTB4_IN, +- PTB3_FN, PTB3_OUT, PTB3_IN_PU, PTB3_IN, +- PTB2_FN, PTB2_OUT, PTB2_IN_PU, PTB2_IN, +- PTB1_FN, PTB1_OUT, PTB1_IN_PU, PTB1_IN, +- PTB0_FN, PTB0_OUT, PTB0_IN_PU, PTB0_IN } ++ PTB7_FN, PTB7_OUT, 0, PTB7_IN, ++ PTB6_FN, PTB6_OUT, 0, PTB6_IN, ++ PTB5_FN, PTB5_OUT, 0, PTB5_IN, ++ PTB4_FN, PTB4_OUT, 0, PTB4_IN, ++ PTB3_FN, PTB3_OUT, 0, PTB3_IN, ++ PTB2_FN, PTB2_OUT, 0, PTB2_IN, ++ PTB1_FN, PTB1_OUT, 0, PTB1_IN, ++ PTB0_FN, PTB0_OUT, 0, PTB0_IN } + }, + { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) { +- PTC7_FN, PTC7_OUT, PTC7_IN_PU, PTC7_IN, +- PTC6_FN, PTC6_OUT, PTC6_IN_PU, PTC6_IN, +- PTC5_FN, PTC5_OUT, PTC5_IN_PU, PTC5_IN, +- PTC4_FN, PTC4_OUT, PTC4_IN_PU, PTC4_IN, +- PTC3_FN, PTC3_OUT, PTC3_IN_PU, PTC3_IN, +- PTC2_FN, PTC2_OUT, PTC2_IN_PU, PTC2_IN, +- PTC1_FN, PTC1_OUT, PTC1_IN_PU, PTC1_IN, +- PTC0_FN, PTC0_OUT, PTC0_IN_PU, PTC0_IN } ++ PTC7_FN, PTC7_OUT, 0, PTC7_IN, ++ PTC6_FN, PTC6_OUT, 0, PTC6_IN, ++ PTC5_FN, PTC5_OUT, 0, PTC5_IN, ++ PTC4_FN, PTC4_OUT, 0, PTC4_IN, ++ PTC3_FN, PTC3_OUT, 0, PTC3_IN, ++ PTC2_FN, PTC2_OUT, 0, PTC2_IN, ++ PTC1_FN, PTC1_OUT, 0, PTC1_IN, ++ PTC0_FN, PTC0_OUT, 0, PTC0_IN } + }, + { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) { +- PTD7_FN, PTD7_OUT, PTD7_IN_PU, PTD7_IN, +- PTD6_FN, PTD6_OUT, PTD6_IN_PU, PTD6_IN, +- PTD5_FN, PTD5_OUT, PTD5_IN_PU, PTD5_IN, +- PTD4_FN, PTD4_OUT, PTD4_IN_PU, PTD4_IN, +- PTD3_FN, PTD3_OUT, PTD3_IN_PU, PTD3_IN, +- PTD2_FN, PTD2_OUT, PTD2_IN_PU, PTD2_IN, +- PTD1_FN, PTD1_OUT, PTD1_IN_PU, PTD1_IN, +- PTD0_FN, PTD0_OUT, PTD0_IN_PU, PTD0_IN } ++ PTD7_FN, PTD7_OUT, 0, PTD7_IN, ++ PTD6_FN, PTD6_OUT, 0, PTD6_IN, ++ PTD5_FN, PTD5_OUT, 0, PTD5_IN, ++ PTD4_FN, PTD4_OUT, 0, PTD4_IN, ++ PTD3_FN, PTD3_OUT, 0, PTD3_IN, ++ PTD2_FN, PTD2_OUT, 0, PTD2_IN, ++ PTD1_FN, PTD1_OUT, 0, PTD1_IN, ++ PTD0_FN, PTD0_OUT, 0, PTD0_IN } + }, + { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) { + 0, 0, 0, 0, + PTE6_FN, 0, 0, PTE6_IN, + PTE5_FN, 0, 0, PTE5_IN, +- PTE4_FN, PTE4_OUT, PTE4_IN_PU, PTE4_IN, +- PTE3_FN, PTE3_OUT, PTE3_IN_PU, PTE3_IN, +- PTE2_FN, PTE2_OUT, PTE2_IN_PU, PTE2_IN, +- PTE1_FN, PTE1_OUT, PTE1_IN_PU, PTE1_IN, +- PTE0_FN, PTE0_OUT, PTE0_IN_PU, PTE0_IN } ++ PTE4_FN, PTE4_OUT, 0, PTE4_IN, ++ PTE3_FN, PTE3_OUT, 0, PTE3_IN, ++ PTE2_FN, PTE2_OUT, 0, PTE2_IN, ++ PTE1_FN, PTE1_OUT, 0, PTE1_IN, ++ PTE0_FN, PTE0_OUT, 0, PTE0_IN } + }, + { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) { + 0, 0, 0, 0, +@@ -1020,123 +990,123 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + }, + { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) { + 0, 0, 0, 0, +- PTG6_FN, PTG6_OUT, PTG6_IN_PU, PTG6_IN, +- PTG5_FN, PTG5_OUT, PTG5_IN_PU, PTG5_IN, +- PTG4_FN, PTG4_OUT, PTG4_IN_PU, PTG4_IN, +- PTG3_FN, PTG3_OUT, PTG3_IN_PU, PTG3_IN, +- PTG2_FN, PTG2_OUT, PTG2_IN_PU, PTG2_IN, +- PTG1_FN, PTG1_OUT, PTG1_IN_PU, PTG1_IN, +- PTG0_FN, PTG0_OUT, PTG0_IN_PU, PTG0_IN } ++ PTG6_FN, PTG6_OUT, 0, PTG6_IN, ++ PTG5_FN, PTG5_OUT, 0, PTG5_IN, ++ PTG4_FN, PTG4_OUT, 0, PTG4_IN, ++ PTG3_FN, PTG3_OUT, 0, PTG3_IN, ++ PTG2_FN, PTG2_OUT, 0, PTG2_IN, ++ PTG1_FN, PTG1_OUT, 0, PTG1_IN, ++ PTG0_FN, PTG0_OUT, 0, PTG0_IN } + }, + { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) { + 0, 0, 0, 0, +- PTH6_FN, PTH6_OUT, PTH6_IN_PU, PTH6_IN, +- PTH5_FN, PTH5_OUT, PTH5_IN_PU, PTH5_IN, +- PTH4_FN, PTH4_OUT, PTH4_IN_PU, PTH4_IN, +- PTH3_FN, PTH3_OUT, PTH3_IN_PU, PTH3_IN, +- PTH2_FN, PTH2_OUT, PTH2_IN_PU, PTH2_IN, +- PTH1_FN, PTH1_OUT, PTH1_IN_PU, PTH1_IN, +- PTH0_FN, PTH0_OUT, PTH0_IN_PU, PTH0_IN } ++ PTH6_FN, PTH6_OUT, 0, PTH6_IN, ++ PTH5_FN, PTH5_OUT, 0, PTH5_IN, ++ PTH4_FN, PTH4_OUT, 0, PTH4_IN, ++ PTH3_FN, PTH3_OUT, 0, PTH3_IN, ++ PTH2_FN, PTH2_OUT, 0, PTH2_IN, ++ PTH1_FN, PTH1_OUT, 0, PTH1_IN, ++ PTH0_FN, PTH0_OUT, 0, PTH0_IN } + }, + { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) { + 0, 0, 0, 0, +- PTJ6_FN, PTJ6_OUT, PTJ6_IN_PU, PTJ6_IN, +- PTJ5_FN, PTJ5_OUT, PTJ5_IN_PU, PTJ5_IN, +- PTJ4_FN, PTJ4_OUT, PTJ4_IN_PU, PTJ4_IN, +- PTJ3_FN, PTJ3_OUT, PTJ3_IN_PU, PTJ3_IN, +- PTJ2_FN, PTJ2_OUT, PTJ2_IN_PU, PTJ2_IN, +- PTJ1_FN, PTJ1_OUT, PTJ1_IN_PU, PTJ1_IN, +- PTJ0_FN, PTJ0_OUT, PTJ0_IN_PU, PTJ0_IN } ++ PTJ6_FN, PTJ6_OUT, 0, PTJ6_IN, ++ PTJ5_FN, PTJ5_OUT, 0, PTJ5_IN, ++ PTJ4_FN, PTJ4_OUT, 0, PTJ4_IN, ++ PTJ3_FN, PTJ3_OUT, 0, PTJ3_IN, ++ PTJ2_FN, PTJ2_OUT, 0, PTJ2_IN, ++ PTJ1_FN, PTJ1_OUT, 0, PTJ1_IN, ++ PTJ0_FN, PTJ0_OUT, 0, PTJ0_IN } + }, + { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, +- PTK3_FN, PTK3_OUT, PTK3_IN_PU, PTK3_IN, +- PTK2_FN, PTK2_OUT, PTK2_IN_PU, PTK2_IN, +- PTK1_FN, PTK1_OUT, PTK1_IN_PU, PTK1_IN, +- PTK0_FN, PTK0_OUT, PTK0_IN_PU, PTK0_IN } ++ PTK3_FN, PTK3_OUT, 0, PTK3_IN, ++ PTK2_FN, PTK2_OUT, 0, PTK2_IN, ++ PTK1_FN, PTK1_OUT, 0, PTK1_IN, ++ PTK0_FN, PTK0_OUT, 0, PTK0_IN } + }, + { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) { +- PTL7_FN, PTL7_OUT, PTL7_IN_PU, PTL7_IN, +- PTL6_FN, PTL6_OUT, PTL6_IN_PU, PTL6_IN, +- PTL5_FN, PTL5_OUT, PTL5_IN_PU, PTL5_IN, +- PTL4_FN, PTL4_OUT, PTL4_IN_PU, PTL4_IN, +- PTL3_FN, PTL3_OUT, PTL3_IN_PU, PTL3_IN, ++ PTL7_FN, PTL7_OUT, 0, PTL7_IN, ++ PTL6_FN, PTL6_OUT, 0, PTL6_IN, ++ PTL5_FN, PTL5_OUT, 0, PTL5_IN, ++ PTL4_FN, PTL4_OUT, 0, PTL4_IN, ++ PTL3_FN, PTL3_OUT, 0, PTL3_IN, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) { +- PTM7_FN, PTM7_OUT, PTM7_IN_PU, PTM7_IN, +- PTM6_FN, PTM6_OUT, PTM6_IN_PU, PTM6_IN, +- PTM5_FN, PTM5_OUT, PTM5_IN_PU, PTM5_IN, +- PTM4_FN, PTM4_OUT, PTM4_IN_PU, PTM4_IN, +- PTM3_FN, PTM3_OUT, PTM3_IN_PU, PTM3_IN, +- PTM2_FN, PTM2_OUT, PTM2_IN_PU, PTM2_IN, +- PTM1_FN, PTM1_OUT, PTM1_IN_PU, PTM1_IN, +- PTM0_FN, PTM0_OUT, PTM0_IN_PU, PTM0_IN } ++ PTM7_FN, PTM7_OUT, 0, PTM7_IN, ++ PTM6_FN, PTM6_OUT, 0, PTM6_IN, ++ PTM5_FN, PTM5_OUT, 0, PTM5_IN, ++ PTM4_FN, PTM4_OUT, 0, PTM4_IN, ++ PTM3_FN, PTM3_OUT, 0, PTM3_IN, ++ PTM2_FN, PTM2_OUT, 0, PTM2_IN, ++ PTM1_FN, PTM1_OUT, 0, PTM1_IN, ++ PTM0_FN, PTM0_OUT, 0, PTM0_IN } + }, + { PINMUX_CFG_REG("PPCR", 0xa4050118, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, +- PTP4_FN, PTP4_OUT, PTP4_IN_PU, PTP4_IN, +- PTP3_FN, PTP3_OUT, PTP3_IN_PU, PTP3_IN, +- PTP2_FN, PTP2_OUT, PTP2_IN_PU, PTP2_IN, +- PTP1_FN, PTP1_OUT, PTP1_IN_PU, PTP1_IN, +- PTP0_FN, PTP0_OUT, PTP0_IN_PU, PTP0_IN } ++ PTP4_FN, PTP4_OUT, 0, PTP4_IN, ++ PTP3_FN, PTP3_OUT, 0, PTP3_IN, ++ PTP2_FN, PTP2_OUT, 0, PTP2_IN, ++ PTP1_FN, PTP1_OUT, 0, PTP1_IN, ++ PTP0_FN, PTP0_OUT, 0, PTP0_IN } + }, + { PINMUX_CFG_REG("PRCR", 0xa405011a, 16, 2) { +- PTR7_FN, PTR7_OUT, PTR7_IN_PU, PTR7_IN, +- PTR6_FN, PTR6_OUT, PTR6_IN_PU, PTR6_IN, +- PTR5_FN, PTR5_OUT, PTR5_IN_PU, PTR5_IN, +- PTR4_FN, PTR4_OUT, PTR4_IN_PU, PTR4_IN, +- PTR3_FN, PTR3_OUT, PTR3_IN_PU, PTR3_IN, +- PTR2_FN, PTR2_OUT, PTR2_IN_PU, PTR2_IN, +- PTR1_FN, PTR1_OUT, PTR1_IN_PU, PTR1_IN, +- PTR0_FN, PTR0_OUT, PTR0_IN_PU, PTR0_IN } ++ PTR7_FN, PTR7_OUT, 0, PTR7_IN, ++ PTR6_FN, PTR6_OUT, 0, PTR6_IN, ++ PTR5_FN, PTR5_OUT, 0, PTR5_IN, ++ PTR4_FN, PTR4_OUT, 0, PTR4_IN, ++ PTR3_FN, PTR3_OUT, 0, PTR3_IN, ++ PTR2_FN, PTR2_OUT, 0, PTR2_IN, ++ PTR1_FN, PTR1_OUT, 0, PTR1_IN, ++ PTR0_FN, PTR0_OUT, 0, PTR0_IN } + }, + { PINMUX_CFG_REG("PSCR", 0xa405011c, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, +- PTS4_FN, PTS4_OUT, PTS4_IN_PU, PTS4_IN, +- PTS3_FN, PTS3_OUT, PTS3_IN_PU, PTS3_IN, +- PTS2_FN, PTS2_OUT, PTS2_IN_PU, PTS2_IN, +- PTS1_FN, PTS1_OUT, PTS1_IN_PU, PTS1_IN, +- PTS0_FN, PTS0_OUT, PTS0_IN_PU, PTS0_IN } ++ PTS4_FN, PTS4_OUT, 0, PTS4_IN, ++ PTS3_FN, PTS3_OUT, 0, PTS3_IN, ++ PTS2_FN, PTS2_OUT, 0, PTS2_IN, ++ PTS1_FN, PTS1_OUT, 0, PTS1_IN, ++ PTS0_FN, PTS0_OUT, 0, PTS0_IN } + }, + { PINMUX_CFG_REG("PTCR", 0xa405011e, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, +- PTT4_FN, PTT4_OUT, PTT4_IN_PU, PTT4_IN, +- PTT3_FN, PTT3_OUT, PTT3_IN_PU, PTT3_IN, +- PTT2_FN, PTT2_OUT, PTT2_IN_PU, PTT2_IN, +- PTT1_FN, PTT1_OUT, PTT1_IN_PU, PTT1_IN, +- PTT0_FN, PTT0_OUT, PTT0_IN_PU, PTT0_IN } ++ PTT4_FN, PTT4_OUT, 0, PTT4_IN, ++ PTT3_FN, PTT3_OUT, 0, PTT3_IN, ++ PTT2_FN, PTT2_OUT, 0, PTT2_IN, ++ PTT1_FN, PTT1_OUT, 0, PTT1_IN, ++ PTT0_FN, PTT0_OUT, 0, PTT0_IN } + }, + { PINMUX_CFG_REG("PUCR", 0xa4050120, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, +- PTU4_FN, PTU4_OUT, PTU4_IN_PU, PTU4_IN, +- PTU3_FN, PTU3_OUT, PTU3_IN_PU, PTU3_IN, +- PTU2_FN, PTU2_OUT, PTU2_IN_PU, PTU2_IN, +- PTU1_FN, PTU1_OUT, PTU1_IN_PU, PTU1_IN, +- PTU0_FN, PTU0_OUT, PTU0_IN_PU, PTU0_IN } ++ PTU4_FN, PTU4_OUT, 0, PTU4_IN, ++ PTU3_FN, PTU3_OUT, 0, PTU3_IN, ++ PTU2_FN, PTU2_OUT, 0, PTU2_IN, ++ PTU1_FN, PTU1_OUT, 0, PTU1_IN, ++ PTU0_FN, PTU0_OUT, 0, PTU0_IN } + }, + { PINMUX_CFG_REG("PVCR", 0xa4050122, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, +- PTV4_FN, PTV4_OUT, PTV4_IN_PU, PTV4_IN, +- PTV3_FN, PTV3_OUT, PTV3_IN_PU, PTV3_IN, +- PTV2_FN, PTV2_OUT, PTV2_IN_PU, PTV2_IN, +- PTV1_FN, PTV1_OUT, PTV1_IN_PU, PTV1_IN, +- PTV0_FN, PTV0_OUT, PTV0_IN_PU, PTV0_IN } ++ PTV4_FN, PTV4_OUT, 0, PTV4_IN, ++ PTV3_FN, PTV3_OUT, 0, PTV3_IN, ++ PTV2_FN, PTV2_OUT, 0, PTV2_IN, ++ PTV1_FN, PTV1_OUT, 0, PTV1_IN, ++ PTV0_FN, PTV0_OUT, 0, PTV0_IN } + }, + {} + }; +@@ -1220,7 +1190,6 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { + const struct sh_pfc_soc_info sh7720_pinmux_info = { + .name = "sh7720_pfc", + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, +- .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0529-sh-pfc-sh7722-Remove-unused-input_pd-and-input_pu-ra.patch b/patches.renesas/0529-sh-pfc-sh7722-Remove-unused-input_pd-and-input_pu-ra.patch new file mode 100644 index 00000000000..646dc44c06c --- /dev/null +++ b/patches.renesas/0529-sh-pfc-sh7722-Remove-unused-input_pd-and-input_pu-ra.patch @@ -0,0 +1,682 @@ +From 7b4c073619d7e34a62e5715aa878307adae09c1d Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Sun, 14 Jul 2013 19:56:02 +0200 +Subject: sh-pfc: sh7722: Remove unused input_pd and input_pu ranges + +The PFC SH7722 SoC data contains input_pd and input_pu ranges used to +configure pull-down and pull-up resistors using the legacy non-pinconf +API. That API has been removed from the driver, the ranges are thus not +used anymore. Remove them. + +If required, configuring pull-down and pull-up resistors for the SH7722 +can be implemented using the pinconf API, as done for the SH-Mobile, +R-Mobile and R-Car platforms. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit 48b888b17fb1387b264b24083206db73fbad8fdd) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-sh7722.c | 447 +++++++++++++++++------------------- + 1 file changed, 206 insertions(+), 241 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7722.c b/drivers/pinctrl/sh-pfc/pfc-sh7722.c +index 32034387..0982c4ff 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7722.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7722.c +@@ -77,39 +77,6 @@ enum { + PTZ5_IN, PTZ4_IN, PTZ3_IN, PTZ2_IN, PTZ1_IN, + PINMUX_INPUT_END, + +- PINMUX_INPUT_PULLDOWN_BEGIN, +- PTA7_IN_PD, PTA6_IN_PD, PTA5_IN_PD, PTA4_IN_PD, +- PTA3_IN_PD, PTA2_IN_PD, PTA1_IN_PD, PTA0_IN_PD, +- PTE7_IN_PD, PTE6_IN_PD, PTE5_IN_PD, PTE4_IN_PD, PTE1_IN_PD, PTE0_IN_PD, +- PTF6_IN_PD, PTF5_IN_PD, PTF4_IN_PD, PTF3_IN_PD, PTF2_IN_PD, PTF1_IN_PD, +- PTH6_IN_PD, PTH5_IN_PD, PTH1_IN_PD, PTH0_IN_PD, +- PTK6_IN_PD, PTK5_IN_PD, PTK4_IN_PD, PTK3_IN_PD, PTK2_IN_PD, PTK0_IN_PD, +- PTL7_IN_PD, PTL6_IN_PD, PTL5_IN_PD, PTL4_IN_PD, +- PTL3_IN_PD, PTL2_IN_PD, PTL1_IN_PD, PTL0_IN_PD, +- PTM7_IN_PD, PTM6_IN_PD, PTM5_IN_PD, PTM4_IN_PD, +- PTM3_IN_PD, PTM2_IN_PD, PTM1_IN_PD, PTM0_IN_PD, +- PTQ5_IN_PD, PTQ4_IN_PD, PTQ3_IN_PD, PTQ2_IN_PD, +- PTS4_IN_PD, PTS2_IN_PD, PTS1_IN_PD, +- PTT4_IN_PD, PTT3_IN_PD, PTT2_IN_PD, PTT1_IN_PD, +- PTU4_IN_PD, PTU3_IN_PD, PTU2_IN_PD, PTU1_IN_PD, PTU0_IN_PD, +- PTV4_IN_PD, PTV3_IN_PD, PTV2_IN_PD, PTV1_IN_PD, PTV0_IN_PD, +- PTW6_IN_PD, PTW4_IN_PD, PTW3_IN_PD, PTW2_IN_PD, PTW1_IN_PD, PTW0_IN_PD, +- PTX6_IN_PD, PTX5_IN_PD, PTX4_IN_PD, +- PTX3_IN_PD, PTX2_IN_PD, PTX1_IN_PD, PTX0_IN_PD, +- PINMUX_INPUT_PULLDOWN_END, +- +- PINMUX_INPUT_PULLUP_BEGIN, +- PTC7_IN_PU, PTC5_IN_PU, +- PTD7_IN_PU, PTD6_IN_PU, PTD5_IN_PU, PTD4_IN_PU, +- PTD3_IN_PU, PTD2_IN_PU, PTD1_IN_PU, +- PTJ1_IN_PU, PTJ0_IN_PU, +- PTQ0_IN_PU, +- PTR2_IN_PU, +- PTX6_IN_PU, +- PTY5_IN_PU, PTY4_IN_PU, PTY3_IN_PU, PTY2_IN_PU, PTY0_IN_PU, +- PTZ5_IN_PU, PTZ4_IN_PU, PTZ3_IN_PU, PTZ2_IN_PU, PTZ1_IN_PU, +- PINMUX_INPUT_PULLUP_END, +- + PINMUX_OUTPUT_BEGIN, + PTA7_OUT, PTA5_OUT, + PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT, +@@ -298,14 +265,14 @@ enum { + + static const pinmux_enum_t pinmux_data[] = { + /* PTA */ +- PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_IN_PD, PTA7_OUT), +- PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_IN_PD), +- PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_IN_PD, PTA5_OUT), +- PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_IN_PD), +- PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_IN_PD), +- PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_IN_PD), +- PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_IN_PD), +- PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_IN_PD), ++ PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT), ++ PINMUX_DATA(PTA6_DATA, PTA6_IN), ++ PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT), ++ PINMUX_DATA(PTA4_DATA, PTA4_IN), ++ PINMUX_DATA(PTA3_DATA, PTA3_IN), ++ PINMUX_DATA(PTA2_DATA, PTA2_IN), ++ PINMUX_DATA(PTA1_DATA, PTA1_IN), ++ PINMUX_DATA(PTA0_DATA, PTA0_IN), + + /* PTB */ + PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT), +@@ -318,38 +285,38 @@ static const pinmux_enum_t pinmux_data[] = { + PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT), + + /* PTC */ +- PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_IN_PU), +- PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_IN_PU), ++ PINMUX_DATA(PTC7_DATA, PTC7_IN), ++ PINMUX_DATA(PTC5_DATA, PTC5_IN), + PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT), + PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT), + PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT), + PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT), + + /* PTD */ +- PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_IN_PU), +- PINMUX_DATA(PTD6_DATA, PTD6_OUT, PTD6_IN, PTD6_IN_PU), +- PINMUX_DATA(PTD5_DATA, PTD5_OUT, PTD5_IN, PTD5_IN_PU), +- PINMUX_DATA(PTD4_DATA, PTD4_OUT, PTD4_IN, PTD4_IN_PU), +- PINMUX_DATA(PTD3_DATA, PTD3_OUT, PTD3_IN, PTD3_IN_PU), +- PINMUX_DATA(PTD2_DATA, PTD2_OUT, PTD2_IN, PTD2_IN_PU), +- PINMUX_DATA(PTD1_DATA, PTD1_OUT, PTD1_IN, PTD1_IN_PU), ++ PINMUX_DATA(PTD7_DATA, PTD7_IN), ++ PINMUX_DATA(PTD6_DATA, PTD6_OUT, PTD6_IN), ++ PINMUX_DATA(PTD5_DATA, PTD5_OUT, PTD5_IN), ++ PINMUX_DATA(PTD4_DATA, PTD4_OUT, PTD4_IN), ++ PINMUX_DATA(PTD3_DATA, PTD3_OUT, PTD3_IN), ++ PINMUX_DATA(PTD2_DATA, PTD2_OUT, PTD2_IN), ++ PINMUX_DATA(PTD1_DATA, PTD1_OUT, PTD1_IN), + PINMUX_DATA(PTD0_DATA, PTD0_OUT), + + /* PTE */ +- PINMUX_DATA(PTE7_DATA, PTE7_OUT, PTE7_IN, PTE7_IN_PD), +- PINMUX_DATA(PTE6_DATA, PTE6_OUT, PTE6_IN, PTE6_IN_PD), +- PINMUX_DATA(PTE5_DATA, PTE5_OUT, PTE5_IN, PTE5_IN_PD), +- PINMUX_DATA(PTE4_DATA, PTE4_OUT, PTE4_IN, PTE4_IN_PD), +- PINMUX_DATA(PTE1_DATA, PTE1_OUT, PTE1_IN, PTE1_IN_PD), +- PINMUX_DATA(PTE0_DATA, PTE0_OUT, PTE0_IN, PTE0_IN_PD), ++ PINMUX_DATA(PTE7_DATA, PTE7_OUT, PTE7_IN), ++ PINMUX_DATA(PTE6_DATA, PTE6_OUT, PTE6_IN), ++ PINMUX_DATA(PTE5_DATA, PTE5_OUT, PTE5_IN), ++ PINMUX_DATA(PTE4_DATA, PTE4_OUT, PTE4_IN), ++ PINMUX_DATA(PTE1_DATA, PTE1_OUT, PTE1_IN), ++ PINMUX_DATA(PTE0_DATA, PTE0_OUT, PTE0_IN), + + /* PTF */ +- PINMUX_DATA(PTF6_DATA, PTF6_OUT, PTF6_IN, PTF6_IN_PD), +- PINMUX_DATA(PTF5_DATA, PTF5_OUT, PTF5_IN, PTF5_IN_PD), +- PINMUX_DATA(PTF4_DATA, PTF4_OUT, PTF4_IN, PTF4_IN_PD), +- PINMUX_DATA(PTF3_DATA, PTF3_OUT, PTF3_IN, PTF3_IN_PD), +- PINMUX_DATA(PTF2_DATA, PTF2_OUT, PTF2_IN, PTF2_IN_PD), +- PINMUX_DATA(PTF1_DATA, PTF1_IN, PTF1_IN_PD), ++ PINMUX_DATA(PTF6_DATA, PTF6_OUT, PTF6_IN), ++ PINMUX_DATA(PTF5_DATA, PTF5_OUT, PTF5_IN), ++ PINMUX_DATA(PTF4_DATA, PTF4_OUT, PTF4_IN), ++ PINMUX_DATA(PTF3_DATA, PTF3_OUT, PTF3_IN), ++ PINMUX_DATA(PTF2_DATA, PTF2_OUT, PTF2_IN), ++ PINMUX_DATA(PTF1_DATA, PTF1_IN), + PINMUX_DATA(PTF0_DATA, PTF0_OUT), + + /* PTG */ +@@ -361,49 +328,49 @@ static const pinmux_enum_t pinmux_data[] = { + + /* PTH */ + PINMUX_DATA(PTH7_DATA, PTH7_OUT), +- PINMUX_DATA(PTH6_DATA, PTH6_OUT, PTH6_IN, PTH6_IN_PD), +- PINMUX_DATA(PTH5_DATA, PTH5_OUT, PTH5_IN, PTH5_IN_PD), ++ PINMUX_DATA(PTH6_DATA, PTH6_OUT, PTH6_IN), ++ PINMUX_DATA(PTH5_DATA, PTH5_OUT, PTH5_IN), + PINMUX_DATA(PTH4_DATA, PTH4_OUT), + PINMUX_DATA(PTH3_DATA, PTH3_OUT), + PINMUX_DATA(PTH2_DATA, PTH2_OUT), +- PINMUX_DATA(PTH1_DATA, PTH1_OUT, PTH1_IN, PTH1_IN_PD), +- PINMUX_DATA(PTH0_DATA, PTH0_OUT, PTH0_IN, PTH0_IN_PD), ++ PINMUX_DATA(PTH1_DATA, PTH1_OUT, PTH1_IN), ++ PINMUX_DATA(PTH0_DATA, PTH0_OUT, PTH0_IN), + + /* PTJ */ + PINMUX_DATA(PTJ7_DATA, PTJ7_OUT), + PINMUX_DATA(PTJ6_DATA, PTJ6_OUT), + PINMUX_DATA(PTJ5_DATA, PTJ5_OUT), +- PINMUX_DATA(PTJ1_DATA, PTJ1_OUT, PTJ1_IN, PTJ1_IN_PU), +- PINMUX_DATA(PTJ0_DATA, PTJ0_OUT, PTJ0_IN, PTJ0_IN_PU), ++ PINMUX_DATA(PTJ1_DATA, PTJ1_OUT, PTJ1_IN), ++ PINMUX_DATA(PTJ0_DATA, PTJ0_OUT, PTJ0_IN), + + /* PTK */ +- PINMUX_DATA(PTK6_DATA, PTK6_OUT, PTK6_IN, PTK6_IN_PD), +- PINMUX_DATA(PTK5_DATA, PTK5_OUT, PTK5_IN, PTK5_IN_PD), +- PINMUX_DATA(PTK4_DATA, PTK4_OUT, PTK4_IN, PTK4_IN_PD), +- PINMUX_DATA(PTK3_DATA, PTK3_OUT, PTK3_IN, PTK3_IN_PD), +- PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_IN_PD), ++ PINMUX_DATA(PTK6_DATA, PTK6_OUT, PTK6_IN), ++ PINMUX_DATA(PTK5_DATA, PTK5_OUT, PTK5_IN), ++ PINMUX_DATA(PTK4_DATA, PTK4_OUT, PTK4_IN), ++ PINMUX_DATA(PTK3_DATA, PTK3_OUT, PTK3_IN), ++ PINMUX_DATA(PTK2_DATA, PTK2_IN), + PINMUX_DATA(PTK1_DATA, PTK1_OUT), +- PINMUX_DATA(PTK0_DATA, PTK0_OUT, PTK0_IN, PTK0_IN_PD), ++ PINMUX_DATA(PTK0_DATA, PTK0_OUT, PTK0_IN), + + /* PTL */ +- PINMUX_DATA(PTL7_DATA, PTL7_OUT, PTL7_IN, PTL7_IN_PD), +- PINMUX_DATA(PTL6_DATA, PTL6_OUT, PTL6_IN, PTL6_IN_PD), +- PINMUX_DATA(PTL5_DATA, PTL5_OUT, PTL5_IN, PTL5_IN_PD), +- PINMUX_DATA(PTL4_DATA, PTL4_OUT, PTL4_IN, PTL4_IN_PD), +- PINMUX_DATA(PTL3_DATA, PTL3_OUT, PTL3_IN, PTL3_IN_PD), +- PINMUX_DATA(PTL2_DATA, PTL2_OUT, PTL2_IN, PTL2_IN_PD), +- PINMUX_DATA(PTL1_DATA, PTL1_OUT, PTL1_IN, PTL1_IN_PD), +- PINMUX_DATA(PTL0_DATA, PTL0_OUT, PTL0_IN, PTL0_IN_PD), ++ PINMUX_DATA(PTL7_DATA, PTL7_OUT, PTL7_IN), ++ PINMUX_DATA(PTL6_DATA, PTL6_OUT, PTL6_IN), ++ PINMUX_DATA(PTL5_DATA, PTL5_OUT, PTL5_IN), ++ PINMUX_DATA(PTL4_DATA, PTL4_OUT, PTL4_IN), ++ PINMUX_DATA(PTL3_DATA, PTL3_OUT, PTL3_IN), ++ PINMUX_DATA(PTL2_DATA, PTL2_OUT, PTL2_IN), ++ PINMUX_DATA(PTL1_DATA, PTL1_OUT, PTL1_IN), ++ PINMUX_DATA(PTL0_DATA, PTL0_OUT, PTL0_IN), + + /* PTM */ +- PINMUX_DATA(PTM7_DATA, PTM7_OUT, PTM7_IN, PTM7_IN_PD), +- PINMUX_DATA(PTM6_DATA, PTM6_OUT, PTM6_IN, PTM6_IN_PD), +- PINMUX_DATA(PTM5_DATA, PTM5_OUT, PTM5_IN, PTM5_IN_PD), +- PINMUX_DATA(PTM4_DATA, PTM4_OUT, PTM4_IN, PTM4_IN_PD), +- PINMUX_DATA(PTM3_DATA, PTM3_OUT, PTM3_IN, PTM3_IN_PD), +- PINMUX_DATA(PTM2_DATA, PTM2_OUT, PTM2_IN, PTM2_IN_PD), +- PINMUX_DATA(PTM1_DATA, PTM1_OUT, PTM1_IN, PTM1_IN_PD), +- PINMUX_DATA(PTM0_DATA, PTM0_OUT, PTM0_IN, PTM0_IN_PD), ++ PINMUX_DATA(PTM7_DATA, PTM7_OUT, PTM7_IN), ++ PINMUX_DATA(PTM6_DATA, PTM6_OUT, PTM6_IN), ++ PINMUX_DATA(PTM5_DATA, PTM5_OUT, PTM5_IN), ++ PINMUX_DATA(PTM4_DATA, PTM4_OUT, PTM4_IN), ++ PINMUX_DATA(PTM3_DATA, PTM3_OUT, PTM3_IN), ++ PINMUX_DATA(PTM2_DATA, PTM2_OUT, PTM2_IN), ++ PINMUX_DATA(PTM1_DATA, PTM1_OUT, PTM1_IN), ++ PINMUX_DATA(PTM0_DATA, PTM0_OUT, PTM0_IN), + + /* PTN */ + PINMUX_DATA(PTN7_DATA, PTN7_OUT, PTN7_IN), +@@ -417,80 +384,80 @@ static const pinmux_enum_t pinmux_data[] = { + + /* PTQ */ + PINMUX_DATA(PTQ6_DATA, PTQ6_OUT), +- PINMUX_DATA(PTQ5_DATA, PTQ5_OUT, PTQ5_IN, PTQ5_IN_PD), +- PINMUX_DATA(PTQ4_DATA, PTQ4_OUT, PTQ4_IN, PTQ4_IN_PD), +- PINMUX_DATA(PTQ3_DATA, PTQ3_OUT, PTQ3_IN, PTQ3_IN_PD), +- PINMUX_DATA(PTQ2_DATA, PTQ2_IN, PTQ2_IN_PD), ++ PINMUX_DATA(PTQ5_DATA, PTQ5_OUT, PTQ5_IN), ++ PINMUX_DATA(PTQ4_DATA, PTQ4_OUT, PTQ4_IN), ++ PINMUX_DATA(PTQ3_DATA, PTQ3_OUT, PTQ3_IN), ++ PINMUX_DATA(PTQ2_DATA, PTQ2_IN), + PINMUX_DATA(PTQ1_DATA, PTQ1_OUT), +- PINMUX_DATA(PTQ0_DATA, PTQ0_OUT, PTQ0_IN, PTQ0_IN_PU), ++ PINMUX_DATA(PTQ0_DATA, PTQ0_OUT, PTQ0_IN), + + /* PTR */ + PINMUX_DATA(PTR4_DATA, PTR4_OUT), + PINMUX_DATA(PTR3_DATA, PTR3_OUT), +- PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_IN_PU), ++ PINMUX_DATA(PTR2_DATA, PTR2_IN), + PINMUX_DATA(PTR1_DATA, PTR1_OUT), + PINMUX_DATA(PTR0_DATA, PTR0_OUT), + + /* PTS */ +- PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_IN_PD), ++ PINMUX_DATA(PTS4_DATA, PTS4_IN), + PINMUX_DATA(PTS3_DATA, PTS3_OUT), +- PINMUX_DATA(PTS2_DATA, PTS2_OUT, PTS2_IN, PTS2_IN_PD), +- PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_IN_PD), ++ PINMUX_DATA(PTS2_DATA, PTS2_OUT, PTS2_IN), ++ PINMUX_DATA(PTS1_DATA, PTS1_IN), + PINMUX_DATA(PTS0_DATA, PTS0_OUT), + + /* PTT */ +- PINMUX_DATA(PTT4_DATA, PTT4_OUT, PTT4_IN, PTT4_IN_PD), +- PINMUX_DATA(PTT3_DATA, PTT3_OUT, PTT3_IN, PTT3_IN_PD), +- PINMUX_DATA(PTT2_DATA, PTT2_OUT, PTT2_IN, PTT2_IN_PD), +- PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_IN_PD), ++ PINMUX_DATA(PTT4_DATA, PTT4_OUT, PTT4_IN), ++ PINMUX_DATA(PTT3_DATA, PTT3_OUT, PTT3_IN), ++ PINMUX_DATA(PTT2_DATA, PTT2_OUT, PTT2_IN), ++ PINMUX_DATA(PTT1_DATA, PTT1_IN), + PINMUX_DATA(PTT0_DATA, PTT0_OUT), + + /* PTU */ +- PINMUX_DATA(PTU4_DATA, PTU4_OUT, PTU4_IN, PTU4_IN_PD), +- PINMUX_DATA(PTU3_DATA, PTU3_OUT, PTU3_IN, PTU3_IN_PD), +- PINMUX_DATA(PTU2_DATA, PTU2_OUT, PTU2_IN, PTU2_IN_PD), +- PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_IN_PD), +- PINMUX_DATA(PTU0_DATA, PTU0_OUT, PTU0_IN, PTU0_IN_PD), ++ PINMUX_DATA(PTU4_DATA, PTU4_OUT, PTU4_IN), ++ PINMUX_DATA(PTU3_DATA, PTU3_OUT, PTU3_IN), ++ PINMUX_DATA(PTU2_DATA, PTU2_OUT, PTU2_IN), ++ PINMUX_DATA(PTU1_DATA, PTU1_IN), ++ PINMUX_DATA(PTU0_DATA, PTU0_OUT, PTU0_IN), + + /* PTV */ +- PINMUX_DATA(PTV4_DATA, PTV4_OUT, PTV4_IN, PTV4_IN_PD), +- PINMUX_DATA(PTV3_DATA, PTV3_OUT, PTV3_IN, PTV3_IN_PD), +- PINMUX_DATA(PTV2_DATA, PTV2_OUT, PTV2_IN, PTV2_IN_PD), +- PINMUX_DATA(PTV1_DATA, PTV1_OUT, PTV1_IN, PTV1_IN_PD), +- PINMUX_DATA(PTV0_DATA, PTV0_OUT, PTV0_IN, PTV0_IN_PD), ++ PINMUX_DATA(PTV4_DATA, PTV4_OUT, PTV4_IN), ++ PINMUX_DATA(PTV3_DATA, PTV3_OUT, PTV3_IN), ++ PINMUX_DATA(PTV2_DATA, PTV2_OUT, PTV2_IN), ++ PINMUX_DATA(PTV1_DATA, PTV1_OUT, PTV1_IN), ++ PINMUX_DATA(PTV0_DATA, PTV0_OUT, PTV0_IN), + + /* PTW */ +- PINMUX_DATA(PTW6_DATA, PTW6_IN, PTW6_IN_PD), ++ PINMUX_DATA(PTW6_DATA, PTW6_IN), + PINMUX_DATA(PTW5_DATA, PTW5_OUT), +- PINMUX_DATA(PTW4_DATA, PTW4_OUT, PTW4_IN, PTW4_IN_PD), +- PINMUX_DATA(PTW3_DATA, PTW3_OUT, PTW3_IN, PTW3_IN_PD), +- PINMUX_DATA(PTW2_DATA, PTW2_OUT, PTW2_IN, PTW2_IN_PD), +- PINMUX_DATA(PTW1_DATA, PTW1_OUT, PTW1_IN, PTW1_IN_PD), +- PINMUX_DATA(PTW0_DATA, PTW0_OUT, PTW0_IN, PTW0_IN_PD), ++ PINMUX_DATA(PTW4_DATA, PTW4_OUT, PTW4_IN), ++ PINMUX_DATA(PTW3_DATA, PTW3_OUT, PTW3_IN), ++ PINMUX_DATA(PTW2_DATA, PTW2_OUT, PTW2_IN), ++ PINMUX_DATA(PTW1_DATA, PTW1_OUT, PTW1_IN), ++ PINMUX_DATA(PTW0_DATA, PTW0_OUT, PTW0_IN), + + /* PTX */ +- PINMUX_DATA(PTX6_DATA, PTX6_OUT, PTX6_IN, PTX6_IN_PD), +- PINMUX_DATA(PTX5_DATA, PTX5_OUT, PTX5_IN, PTX5_IN_PD), +- PINMUX_DATA(PTX4_DATA, PTX4_OUT, PTX4_IN, PTX4_IN_PD), +- PINMUX_DATA(PTX3_DATA, PTX3_OUT, PTX3_IN, PTX3_IN_PD), +- PINMUX_DATA(PTX2_DATA, PTX2_OUT, PTX2_IN, PTX2_IN_PD), +- PINMUX_DATA(PTX1_DATA, PTX1_OUT, PTX1_IN, PTX1_IN_PD), +- PINMUX_DATA(PTX0_DATA, PTX0_OUT, PTX0_IN, PTX0_IN_PD), ++ PINMUX_DATA(PTX6_DATA, PTX6_OUT, PTX6_IN), ++ PINMUX_DATA(PTX5_DATA, PTX5_OUT, PTX5_IN), ++ PINMUX_DATA(PTX4_DATA, PTX4_OUT, PTX4_IN), ++ PINMUX_DATA(PTX3_DATA, PTX3_OUT, PTX3_IN), ++ PINMUX_DATA(PTX2_DATA, PTX2_OUT, PTX2_IN), ++ PINMUX_DATA(PTX1_DATA, PTX1_OUT, PTX1_IN), ++ PINMUX_DATA(PTX0_DATA, PTX0_OUT, PTX0_IN), + + /* PTY */ +- PINMUX_DATA(PTY5_DATA, PTY5_OUT, PTY5_IN, PTY5_IN_PU), +- PINMUX_DATA(PTY4_DATA, PTY4_OUT, PTY4_IN, PTY4_IN_PU), +- PINMUX_DATA(PTY3_DATA, PTY3_OUT, PTY3_IN, PTY3_IN_PU), +- PINMUX_DATA(PTY2_DATA, PTY2_OUT, PTY2_IN, PTY2_IN_PU), ++ PINMUX_DATA(PTY5_DATA, PTY5_OUT, PTY5_IN), ++ PINMUX_DATA(PTY4_DATA, PTY4_OUT, PTY4_IN), ++ PINMUX_DATA(PTY3_DATA, PTY3_OUT, PTY3_IN), ++ PINMUX_DATA(PTY2_DATA, PTY2_OUT, PTY2_IN), + PINMUX_DATA(PTY1_DATA, PTY1_OUT), +- PINMUX_DATA(PTY0_DATA, PTY0_OUT, PTY0_IN, PTY0_IN_PU), ++ PINMUX_DATA(PTY0_DATA, PTY0_OUT, PTY0_IN), + + /* PTZ */ +- PINMUX_DATA(PTZ5_DATA, PTZ5_IN, PTZ5_IN_PU), +- PINMUX_DATA(PTZ4_DATA, PTZ4_IN, PTZ4_IN_PU), +- PINMUX_DATA(PTZ3_DATA, PTZ3_IN, PTZ3_IN_PU), +- PINMUX_DATA(PTZ2_DATA, PTZ2_IN, PTZ2_IN_PU), +- PINMUX_DATA(PTZ1_DATA, PTZ1_IN, PTZ1_IN_PU), ++ PINMUX_DATA(PTZ5_DATA, PTZ5_IN), ++ PINMUX_DATA(PTZ4_DATA, PTZ4_IN), ++ PINMUX_DATA(PTZ3_DATA, PTZ3_IN), ++ PINMUX_DATA(PTZ2_DATA, PTZ2_IN), ++ PINMUX_DATA(PTZ1_DATA, PTZ1_IN), + + /* SCIF0 */ + PINMUX_DATA(SCIF0_TXD_MARK, SCIF0_TXD), +@@ -1270,14 +1237,14 @@ static const struct pinmux_func pinmux_func_gpios[] = { + + static const struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { +- VIO_D7_SCIF1_SCK, PTA7_OUT, PTA7_IN_PD, PTA7_IN, +- VIO_D6_SCIF1_RXD, 0, PTA6_IN_PD, PTA6_IN, +- VIO_D5_SCIF1_TXD, PTA5_OUT, PTA5_IN_PD, PTA5_IN, +- VIO_D4, 0, PTA4_IN_PD, PTA4_IN, +- VIO_D3, 0, PTA3_IN_PD, PTA3_IN, +- VIO_D2, 0, PTA2_IN_PD, PTA2_IN, +- VIO_D1, 0, PTA1_IN_PD, PTA1_IN, +- VIO_D0_LCDLCLK, 0, PTA0_IN_PD, PTA0_IN } ++ VIO_D7_SCIF1_SCK, PTA7_OUT, 0, PTA7_IN, ++ VIO_D6_SCIF1_RXD, 0, 0, PTA6_IN, ++ VIO_D5_SCIF1_TXD, PTA5_OUT, 0, PTA5_IN, ++ VIO_D4, 0, 0, PTA4_IN, ++ VIO_D3, 0, 0, PTA3_IN, ++ VIO_D2, 0, 0, PTA2_IN, ++ VIO_D1, 0, 0, PTA1_IN, ++ VIO_D0_LCDLCLK, 0, 0, PTA0_IN } + }, + { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) { + HPD55, PTB7_OUT, 0, PTB7_IN, +@@ -1290,9 +1257,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + HPD48, PTB0_OUT, 0, PTB0_IN } + }, + { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) { +- 0, 0, PTC7_IN_PU, PTC7_IN, ++ 0, 0, 0, PTC7_IN, + 0, 0, 0, 0, +- IOIS16, 0, PTC5_IN_PU, PTC5_IN, ++ IOIS16, 0, 0, PTC5_IN, + HPDQM7, PTC4_OUT, 0, PTC4_IN, + HPDQM6, PTC3_OUT, 0, PTC3_IN, + HPDQM5, PTC2_OUT, 0, PTC2_IN, +@@ -1300,33 +1267,33 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + HPDQM4, PTC0_OUT, 0, PTC0_IN } + }, + { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) { +- SDHICD, 0, PTD7_IN_PU, PTD7_IN, +- SDHIWP, PTD6_OUT, PTD6_IN_PU, PTD6_IN, +- SDHID3, PTD5_OUT, PTD5_IN_PU, PTD5_IN, +- IRQ2_SDHID2, PTD4_OUT, PTD4_IN_PU, PTD4_IN, +- SDHID1, PTD3_OUT, PTD3_IN_PU, PTD3_IN, +- SDHID0, PTD2_OUT, PTD2_IN_PU, PTD2_IN, +- SDHICMD, PTD1_OUT, PTD1_IN_PU, PTD1_IN, ++ SDHICD, 0, 0, PTD7_IN, ++ SDHIWP, PTD6_OUT, 0, PTD6_IN, ++ SDHID3, PTD5_OUT, 0, PTD5_IN, ++ IRQ2_SDHID2, PTD4_OUT, 0, PTD4_IN, ++ SDHID1, PTD3_OUT, 0, PTD3_IN, ++ SDHID0, PTD2_OUT, 0, PTD2_IN, ++ SDHICMD, PTD1_OUT, 0, PTD1_IN, + SDHICLK, PTD0_OUT, 0, 0 } + }, + { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) { +- A25, PTE7_OUT, PTE7_IN_PD, PTE7_IN, +- A24, PTE6_OUT, PTE6_IN_PD, PTE6_IN, +- A23, PTE5_OUT, PTE5_IN_PD, PTE5_IN, +- A22, PTE4_OUT, PTE4_IN_PD, PTE4_IN, ++ A25, PTE7_OUT, 0, PTE7_IN, ++ A24, PTE6_OUT, 0, PTE6_IN, ++ A23, PTE5_OUT, 0, PTE5_IN, ++ A22, PTE4_OUT, 0, PTE4_IN, + 0, 0, 0, 0, + 0, 0, 0, 0, +- IRQ5, PTE1_OUT, PTE1_IN_PD, PTE1_IN, +- IRQ4_BS, PTE0_OUT, PTE0_IN_PD, PTE0_IN } ++ IRQ5, PTE1_OUT, 0, PTE1_IN, ++ IRQ4_BS, PTE0_OUT, 0, PTE0_IN } + }, + { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) { + 0, 0, 0, 0, +- PTF6, PTF6_OUT, PTF6_IN_PD, PTF6_IN, +- SIOSCK_SIUBOBT, PTF5_OUT, PTF5_IN_PD, PTF5_IN, +- SIOSTRB1_SIUBOLR, PTF4_OUT, PTF4_IN_PD, PTF4_IN, +- SIOSTRB0_SIUBIBT, PTF3_OUT, PTF3_IN_PD, PTF3_IN, +- SIOD_SIUBILR, PTF2_OUT, PTF2_IN_PD, PTF2_IN, +- SIORXD_SIUBISLD, 0, PTF1_IN_PD, PTF1_IN, ++ PTF6, PTF6_OUT, 0, PTF6_IN, ++ SIOSCK_SIUBOBT, PTF5_OUT, 0, PTF5_IN, ++ SIOSTRB1_SIUBOLR, PTF4_OUT, 0, PTF4_IN, ++ SIOSTRB0_SIUBIBT, PTF3_OUT, 0, PTF3_IN, ++ SIOD_SIUBILR, PTF2_OUT, 0, PTF2_IN, ++ SIORXD_SIUBISLD, 0, 0, PTF1_IN, + SIOTXD_SIUBOSLD, PTF0_OUT, 0, 0 } + }, + { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) { +@@ -1341,13 +1308,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + }, + { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) { + LCDVCPWC_LCDVCPWC2, PTH7_OUT, 0, 0, +- LCDVSYN2_DACK, PTH6_OUT, PTH6_IN_PD, PTH6_IN, +- LCDVSYN, PTH5_OUT, PTH5_IN_PD, PTH5_IN, ++ LCDVSYN2_DACK, PTH6_OUT, 0, PTH6_IN, ++ LCDVSYN, PTH5_OUT, 0, PTH5_IN, + LCDDISP_LCDRS, PTH4_OUT, 0, 0, + LCDHSYN_LCDCS, PTH3_OUT, 0, 0, + LCDDON_LCDDON2, PTH2_OUT, 0, 0, +- LCDD17_DV_HSYNC, PTH1_OUT, PTH1_IN_PD, PTH1_IN, +- LCDD16_DV_VSYNC, PTH0_OUT, PTH0_IN_PD, PTH0_IN } ++ LCDD17_DV_HSYNC, PTH1_OUT, 0, PTH1_IN, ++ LCDD16_DV_VSYNC, PTH0_OUT, 0, PTH0_IN } + }, + { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) { + STATUS0, PTJ7_OUT, 0, 0, +@@ -1356,38 +1323,38 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, +- IRQ1, PTJ1_OUT, PTJ1_IN_PU, PTJ1_IN, +- IRQ0, PTJ0_OUT, PTJ0_IN_PU, PTJ0_IN } ++ IRQ1, PTJ1_OUT, 0, PTJ1_IN, ++ IRQ0, PTJ0_OUT, 0, PTJ0_IN } + }, + { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) { + 0, 0, 0, 0, +- SIUAILR_SIOF1_SS2, PTK6_OUT, PTK6_IN_PD, PTK6_IN, +- SIUAIBT_SIOF1_SS1, PTK5_OUT, PTK5_IN_PD, PTK5_IN, +- SIUAOLR_SIOF1_SYNC, PTK4_OUT, PTK4_IN_PD, PTK4_IN, +- SIUAOBT_SIOF1_SCK, PTK3_OUT, PTK3_IN_PD, PTK3_IN, +- SIUAISLD_SIOF1_RXD, 0, PTK2_IN_PD, PTK2_IN, ++ SIUAILR_SIOF1_SS2, PTK6_OUT, 0, PTK6_IN, ++ SIUAIBT_SIOF1_SS1, PTK5_OUT, 0, PTK5_IN, ++ SIUAOLR_SIOF1_SYNC, PTK4_OUT, 0, PTK4_IN, ++ SIUAOBT_SIOF1_SCK, PTK3_OUT, 0, PTK3_IN, ++ SIUAISLD_SIOF1_RXD, 0, 0, PTK2_IN, + SIUAOSLD_SIOF1_TXD, PTK1_OUT, 0, 0, +- PTK0, PTK0_OUT, PTK0_IN_PD, PTK0_IN } ++ PTK0, PTK0_OUT, 0, PTK0_IN } + }, + { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) { +- LCDD15_DV_D15, PTL7_OUT, PTL7_IN_PD, PTL7_IN, +- LCDD14_DV_D14, PTL6_OUT, PTL6_IN_PD, PTL6_IN, +- LCDD13_DV_D13, PTL5_OUT, PTL5_IN_PD, PTL5_IN, +- LCDD12_DV_D12, PTL4_OUT, PTL4_IN_PD, PTL4_IN, +- LCDD11_DV_D11, PTL3_OUT, PTL3_IN_PD, PTL3_IN, +- LCDD10_DV_D10, PTL2_OUT, PTL2_IN_PD, PTL2_IN, +- LCDD9_DV_D9, PTL1_OUT, PTL1_IN_PD, PTL1_IN, +- LCDD8_DV_D8, PTL0_OUT, PTL0_IN_PD, PTL0_IN } ++ LCDD15_DV_D15, PTL7_OUT, 0, PTL7_IN, ++ LCDD14_DV_D14, PTL6_OUT, 0, PTL6_IN, ++ LCDD13_DV_D13, PTL5_OUT, 0, PTL5_IN, ++ LCDD12_DV_D12, PTL4_OUT, 0, PTL4_IN, ++ LCDD11_DV_D11, PTL3_OUT, 0, PTL3_IN, ++ LCDD10_DV_D10, PTL2_OUT, 0, PTL2_IN, ++ LCDD9_DV_D9, PTL1_OUT, 0, PTL1_IN, ++ LCDD8_DV_D8, PTL0_OUT, 0, PTL0_IN } + }, + { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) { +- LCDD7_DV_D7, PTM7_OUT, PTM7_IN_PD, PTM7_IN, +- LCDD6_DV_D6, PTM6_OUT, PTM6_IN_PD, PTM6_IN, +- LCDD5_DV_D5, PTM5_OUT, PTM5_IN_PD, PTM5_IN, +- LCDD4_DV_D4, PTM4_OUT, PTM4_IN_PD, PTM4_IN, +- LCDD3_DV_D3, PTM3_OUT, PTM3_IN_PD, PTM3_IN, +- LCDD2_DV_D2, PTM2_OUT, PTM2_IN_PD, PTM2_IN, +- LCDD1_DV_D1, PTM1_OUT, PTM1_IN_PD, PTM1_IN, +- LCDD0_DV_D0, PTM0_OUT, PTM0_IN_PD, PTM0_IN } ++ LCDD7_DV_D7, PTM7_OUT, 0, PTM7_IN, ++ LCDD6_DV_D6, PTM6_OUT, 0, PTM6_IN, ++ LCDD5_DV_D5, PTM5_OUT, 0, PTM5_IN, ++ LCDD4_DV_D4, PTM4_OUT, 0, PTM4_IN, ++ LCDD3_DV_D3, PTM3_OUT, 0, PTM3_IN, ++ LCDD2_DV_D2, PTM2_OUT, 0, PTM2_IN, ++ LCDD1_DV_D1, PTM1_OUT, 0, PTM1_IN, ++ LCDD0_DV_D0, PTM0_OUT, 0, PTM0_IN } + }, + { PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2) { + HPD63, PTN7_OUT, 0, PTN7_IN, +@@ -1402,12 +1369,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2) { + 0, 0, 0, 0, + SIOF0_SS2_SIM_RST, PTQ6_OUT, 0, 0, +- SIOF0_SS1_TS_SPSYNC, PTQ5_OUT, PTQ5_IN_PD, PTQ5_IN, +- SIOF0_SYNC_TS_SDEN, PTQ4_OUT, PTQ4_IN_PD, PTQ4_IN, +- SIOF0_SCK_TS_SCK, PTQ3_OUT, PTQ3_IN_PD, PTQ3_IN, +- PTQ2, 0, PTQ2_IN_PD, PTQ2_IN, ++ SIOF0_SS1_TS_SPSYNC, PTQ5_OUT, 0, PTQ5_IN, ++ SIOF0_SYNC_TS_SDEN, PTQ4_OUT, 0, PTQ4_IN, ++ SIOF0_SCK_TS_SCK, PTQ3_OUT, 0, PTQ3_IN, ++ PTQ2, 0, 0, PTQ2_IN, + PTQ1, PTQ1_OUT, 0, 0, +- PTQ0, PTQ0_OUT, PTQ0_IN_PU, PTQ0_IN } ++ PTQ0, PTQ0_OUT, 0, PTQ0_IN } + }, + { PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2) { + 0, 0, 0, 0, +@@ -1415,7 +1382,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + 0, 0, 0, 0, + LCDRD, PTR4_OUT, 0, 0, + CS6B_CE1B_LCDCS2, PTR3_OUT, 0, 0, +- WAIT, 0, PTR2_IN_PU, PTR2_IN, ++ WAIT, 0, 0, PTR2_IN, + LCDDCK_LCDWR, PTR1_OUT, 0, 0, + LCDVEPWC_LCDVEPWC2, PTR0_OUT, 0, 0 } + }, +@@ -1423,80 +1390,80 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, +- SCIF0_CTS_SIUAISPD, 0, PTS4_IN_PD, PTS4_IN, ++ SCIF0_CTS_SIUAISPD, 0, 0, PTS4_IN, + SCIF0_RTS_SIUAOSPD, PTS3_OUT, 0, 0, +- SCIF0_SCK_TPUTO, PTS2_OUT, PTS2_IN_PD, PTS2_IN, +- SCIF0_RXD, 0, PTS1_IN_PD, PTS1_IN, ++ SCIF0_SCK_TPUTO, PTS2_OUT, 0, PTS2_IN, ++ SCIF0_RXD, 0, 0, PTS1_IN, + SCIF0_TXD, PTS0_OUT, 0, 0 } + }, + { PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, +- FOE_VIO_VD2, PTT4_OUT, PTT4_IN_PD, PTT4_IN, +- FWE, PTT3_OUT, PTT3_IN_PD, PTT3_IN, +- FSC, PTT2_OUT, PTT2_IN_PD, PTT2_IN, +- DREQ0, 0, PTT1_IN_PD, PTT1_IN, ++ FOE_VIO_VD2, PTT4_OUT, 0, PTT4_IN, ++ FWE, PTT3_OUT, 0, PTT3_IN, ++ FSC, PTT2_OUT, 0, PTT2_IN, ++ DREQ0, 0, 0, PTT1_IN, + FCDE, PTT0_OUT, 0, 0 } + }, + { PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, +- NAF2_VIO_D10, PTU4_OUT, PTU4_IN_PD, PTU4_IN, +- NAF1_VIO_D9, PTU3_OUT, PTU3_IN_PD, PTU3_IN, +- NAF0_VIO_D8, PTU2_OUT, PTU2_IN_PD, PTU2_IN, +- FRB_VIO_CLK2, 0, PTU1_IN_PD, PTU1_IN, +- FCE_VIO_HD2, PTU0_OUT, PTU0_IN_PD, PTU0_IN } ++ NAF2_VIO_D10, PTU4_OUT, 0, PTU4_IN, ++ NAF1_VIO_D9, PTU3_OUT, 0, PTU3_IN, ++ NAF0_VIO_D8, PTU2_OUT, 0, PTU2_IN, ++ FRB_VIO_CLK2, 0, 0, PTU1_IN, ++ FCE_VIO_HD2, PTU0_OUT, 0, PTU0_IN } + }, + { PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, +- NAF7_VIO_D15, PTV4_OUT, PTV4_IN_PD, PTV4_IN, +- NAF6_VIO_D14, PTV3_OUT, PTV3_IN_PD, PTV3_IN, +- NAF5_VIO_D13, PTV2_OUT, PTV2_IN_PD, PTV2_IN, +- NAF4_VIO_D12, PTV1_OUT, PTV1_IN_PD, PTV1_IN, +- NAF3_VIO_D11, PTV0_OUT, PTV0_IN_PD, PTV0_IN } ++ NAF7_VIO_D15, PTV4_OUT, 0, PTV4_IN, ++ NAF6_VIO_D14, PTV3_OUT, 0, PTV3_IN, ++ NAF5_VIO_D13, PTV2_OUT, 0, PTV2_IN, ++ NAF4_VIO_D12, PTV1_OUT, 0, PTV1_IN, ++ NAF3_VIO_D11, PTV0_OUT, 0, PTV0_IN } + }, + { PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2) { + 0, 0, 0, 0, +- VIO_FLD_SCIF2_CTS, 0, PTW6_IN_PD, PTW6_IN, ++ VIO_FLD_SCIF2_CTS, 0, 0, PTW6_IN, + VIO_CKO_SCIF2_RTS, PTW5_OUT, 0, 0, +- VIO_STEX_SCIF2_SCK, PTW4_OUT, PTW4_IN_PD, PTW4_IN, +- VIO_STEM_SCIF2_TXD, PTW3_OUT, PTW3_IN_PD, PTW3_IN, +- VIO_HD_SCIF2_RXD, PTW2_OUT, PTW2_IN_PD, PTW2_IN, +- VIO_VD_SCIF1_CTS, PTW1_OUT, PTW1_IN_PD, PTW1_IN, +- VIO_CLK_SCIF1_RTS, PTW0_OUT, PTW0_IN_PD, PTW0_IN } ++ VIO_STEX_SCIF2_SCK, PTW4_OUT, 0, PTW4_IN, ++ VIO_STEM_SCIF2_TXD, PTW3_OUT, 0, PTW3_IN, ++ VIO_HD_SCIF2_RXD, PTW2_OUT, 0, PTW2_IN, ++ VIO_VD_SCIF1_CTS, PTW1_OUT, 0, PTW1_IN, ++ VIO_CLK_SCIF1_RTS, PTW0_OUT, 0, PTW0_IN } + }, + { PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2) { + 0, 0, 0, 0, +- CS6A_CE2B, PTX6_OUT, PTX6_IN_PU, PTX6_IN, +- LCDD23, PTX5_OUT, PTX5_IN_PD, PTX5_IN, +- LCDD22, PTX4_OUT, PTX4_IN_PD, PTX4_IN, +- LCDD21, PTX3_OUT, PTX3_IN_PD, PTX3_IN, +- LCDD20, PTX2_OUT, PTX2_IN_PD, PTX2_IN, +- LCDD19_DV_CLKI, PTX1_OUT, PTX1_IN_PD, PTX1_IN, +- LCDD18_DV_CLK, PTX0_OUT, PTX0_IN_PD, PTX0_IN } ++ CS6A_CE2B, PTX6_OUT, 0, PTX6_IN, ++ LCDD23, PTX5_OUT, 0, PTX5_IN, ++ LCDD22, PTX4_OUT, 0, PTX4_IN, ++ LCDD21, PTX3_OUT, 0, PTX3_IN, ++ LCDD20, PTX2_OUT, 0, PTX2_IN, ++ LCDD19_DV_CLKI, PTX1_OUT, 0, PTX1_IN, ++ LCDD18_DV_CLK, PTX0_OUT, 0, PTX0_IN } + }, + { PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, +- KEYOUT5_IN5, PTY5_OUT, PTY5_IN_PU, PTY5_IN, +- KEYOUT4_IN6, PTY4_OUT, PTY4_IN_PU, PTY4_IN, +- KEYOUT3, PTY3_OUT, PTY3_IN_PU, PTY3_IN, +- KEYOUT2, PTY2_OUT, PTY2_IN_PU, PTY2_IN, ++ KEYOUT5_IN5, PTY5_OUT, 0, PTY5_IN, ++ KEYOUT4_IN6, PTY4_OUT, 0, PTY4_IN, ++ KEYOUT3, PTY3_OUT, 0, PTY3_IN, ++ KEYOUT2, PTY2_OUT, 0, PTY2_IN, + KEYOUT1, PTY1_OUT, 0, 0, +- KEYOUT0, PTY0_OUT, PTY0_IN_PU, PTY0_IN } ++ KEYOUT0, PTY0_OUT, 0, PTY0_IN } + }, + { PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, +- KEYIN4_IRQ7, 0, PTZ5_IN_PU, PTZ5_IN, +- KEYIN3, 0, PTZ4_IN_PU, PTZ4_IN, +- KEYIN2, 0, PTZ3_IN_PU, PTZ3_IN, +- KEYIN1, 0, PTZ2_IN_PU, PTZ2_IN, +- KEYIN0_IRQ6, 0, PTZ1_IN_PU, PTZ1_IN, ++ KEYIN4_IRQ7, 0, 0, PTZ5_IN, ++ KEYIN3, 0, 0, PTZ4_IN, ++ KEYIN2, 0, 0, PTZ3_IN, ++ KEYIN1, 0, 0, PTZ2_IN, ++ KEYIN0_IRQ6, 0, 0, PTZ1_IN, + 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 1) { +@@ -1763,8 +1730,6 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { + const struct sh_pfc_soc_info sh7722_pinmux_info = { + .name = "sh7722_pfc", + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, +- .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, +- .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0530-sh-pfc-sh7723-Remove-unused-input_pu-range.patch b/patches.renesas/0530-sh-pfc-sh7723-Remove-unused-input_pu-range.patch new file mode 100644 index 00000000000..3264be630b3 --- /dev/null +++ b/patches.renesas/0530-sh-pfc-sh7723-Remove-unused-input_pu-range.patch @@ -0,0 +1,122 @@ +From 761c3d73e73e404c86765afe4cb3797e6b246b30 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 16 Jul 2013 01:54:13 +0200 +Subject: sh-pfc: sh7723: Remove unused input_pu range + +The PFC SH7723 SoC data contains a input_pu range used to configure +pull-up resistors using the legacy non-pinconf API. That API has been +removed from the driver, the range is thus not used anymore. Remove it. + +If required, configuring pull-up resistors for the SH7723 can be +implemented using the pinconf API, as done for the SH-Mobile, R-Mobile +and R-Car platforms. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit 52331350b47daf0d7718cb9ee983f9e4b0318758) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-sh7723.c | 39 +++++++++++++++---------------------- + 1 file changed, 16 insertions(+), 23 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7723.c b/drivers/pinctrl/sh-pfc/pfc-sh7723.c +index 07ad1d8d..da0dbb0b 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7723.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7723.c +@@ -102,12 +102,6 @@ enum { + PTZ3_IN, PTZ2_IN, PTZ1_IN, PTZ0_IN, + PINMUX_INPUT_END, + +- PINMUX_INPUT_PULLUP_BEGIN, +- PTA4_IN_PU, PTA3_IN_PU, PTA2_IN_PU, PTA1_IN_PU, PTA0_IN_PU, +- PTB2_IN_PU, PTB1_IN_PU, +- PTR2_IN_PU, +- PINMUX_INPUT_PULLUP_END, +- + PINMUX_OUTPUT_BEGIN, + PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT, + PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT, +@@ -355,11 +349,11 @@ static const pinmux_enum_t pinmux_data[] = { + PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT), + PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT), + PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT), +- PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT, PTA4_IN_PU), +- PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT, PTA3_IN_PU), +- PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT, PTA2_IN_PU), +- PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT, PTA1_IN_PU), +- PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT, PTA0_IN_PU), ++ PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT), ++ PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT), ++ PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT), ++ PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT), ++ PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT), + + /* PTB GPIO */ + PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT), +@@ -367,8 +361,8 @@ static const pinmux_enum_t pinmux_data[] = { + PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT), + PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT), + PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT), +- PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT, PTB2_IN_PU), +- PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT, PTB1_IN_PU), ++ PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT), ++ PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT), + PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT), + + /* PTC GPIO */ +@@ -487,7 +481,7 @@ static const pinmux_enum_t pinmux_data[] = { + PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT), + PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT), + PINMUX_DATA(PTR3_DATA, PTR3_IN), +- PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_IN_PU), ++ PINMUX_DATA(PTR2_DATA, PTR2_IN), + PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT), + PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT), + +@@ -1520,11 +1514,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + PTA7_FN, PTA7_OUT, 0, PTA7_IN, + PTA6_FN, PTA6_OUT, 0, PTA6_IN, + PTA5_FN, PTA5_OUT, 0, PTA5_IN, +- PTA4_FN, PTA4_OUT, PTA4_IN_PU, PTA4_IN, +- PTA3_FN, PTA3_OUT, PTA3_IN_PU, PTA3_IN, +- PTA2_FN, PTA2_OUT, PTA2_IN_PU, PTA2_IN, +- PTA1_FN, PTA1_OUT, PTA1_IN_PU, PTA1_IN, +- PTA0_FN, PTA0_OUT, PTA0_IN_PU, PTA0_IN } ++ PTA4_FN, PTA4_OUT, 0, PTA4_IN, ++ PTA3_FN, PTA3_OUT, 0, PTA3_IN, ++ PTA2_FN, PTA2_OUT, 0, PTA2_IN, ++ PTA1_FN, PTA1_OUT, 0, PTA1_IN, ++ PTA0_FN, PTA0_OUT, 0, PTA0_IN } + }, + { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) { + PTB7_FN, PTB7_OUT, 0, PTB7_IN, +@@ -1532,8 +1526,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + PTB5_FN, PTB5_OUT, 0, PTB5_IN, + PTB4_FN, PTB4_OUT, 0, PTB4_IN, + PTB3_FN, PTB3_OUT, 0, PTB3_IN, +- PTB2_FN, PTB2_OUT, PTB2_IN_PU, PTB2_IN, +- PTB1_FN, PTB1_OUT, PTB1_IN_PU, PTB1_IN, ++ PTB2_FN, PTB2_OUT, 0, PTB2_IN, ++ PTB1_FN, PTB1_OUT, 0, PTB1_IN, + PTB0_FN, PTB0_OUT, 0, PTB0_IN } + }, + { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) { +@@ -1662,7 +1656,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + PTR5_FN, PTR5_OUT, 0, PTR5_IN, + PTR4_FN, PTR4_OUT, 0, PTR4_IN, + PTR3_FN, 0, 0, PTR3_IN, +- PTR2_FN, 0, PTR2_IN_PU, PTR2_IN, ++ PTR2_FN, 0, 0, PTR2_IN, + PTR1_FN, PTR1_OUT, 0, PTR1_IN, + PTR0_FN, PTR0_OUT, 0, PTR0_IN } + }, +@@ -1888,7 +1882,6 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { + const struct sh_pfc_soc_info sh7723_pinmux_info = { + .name = "sh7723_pfc", + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, +- .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0531-sh-pfc-sh7724-Remove-unused-input_pu-range.patch b/patches.renesas/0531-sh-pfc-sh7724-Remove-unused-input_pu-range.patch new file mode 100644 index 00000000000..34cc3a35741 --- /dev/null +++ b/patches.renesas/0531-sh-pfc-sh7724-Remove-unused-input_pu-range.patch @@ -0,0 +1,888 @@ +From 9444e0b675afad1e34be924c5fc6da62869a5481 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 16 Jul 2013 01:54:13 +0200 +Subject: sh-pfc: sh7724: Remove unused input_pu range + +The PFC SH7724 SoC data contains a input_pu range used to configure +pull-up resistors using the legacy non-pinconf API. That API has been +removed from the driver, the range is thus not used anymore. Remove it. + +If required, configuring pull-up resistors for the SH7724 can be +implemented using the pinconf API, as done for the SH-Mobile, R-Mobile +and R-Car platforms. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit c5361517bbd494d1c268ac06d022f8da08da89b4) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-sh7724.c | 731 +++++++++++++++++------------------- + 1 file changed, 342 insertions(+), 389 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7724.c b/drivers/pinctrl/sh-pfc/pfc-sh7724.c +index 35e55160..e8563cf6 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7724.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7724.c +@@ -117,52 +117,6 @@ enum { + PTZ3_IN, PTZ2_IN, PTZ1_IN, PTZ0_IN, + PINMUX_INPUT_END, + +- PINMUX_INPUT_PULLUP_BEGIN, +- PTA7_IN_PU, PTA6_IN_PU, PTA5_IN_PU, PTA4_IN_PU, +- PTA3_IN_PU, PTA2_IN_PU, PTA1_IN_PU, PTA0_IN_PU, +- PTB7_IN_PU, PTB6_IN_PU, PTB5_IN_PU, PTB4_IN_PU, +- PTB3_IN_PU, PTB2_IN_PU, PTB1_IN_PU, PTB0_IN_PU, +- PTC7_IN_PU, PTC6_IN_PU, PTC5_IN_PU, PTC4_IN_PU, +- PTC3_IN_PU, PTC2_IN_PU, PTC1_IN_PU, PTC0_IN_PU, +- PTD7_IN_PU, PTD6_IN_PU, PTD5_IN_PU, PTD4_IN_PU, +- PTD3_IN_PU, PTD2_IN_PU, PTD1_IN_PU, PTD0_IN_PU, +- PTE7_IN_PU, PTE6_IN_PU, PTE5_IN_PU, PTE4_IN_PU, +- PTE3_IN_PU, PTE2_IN_PU, PTE1_IN_PU, PTE0_IN_PU, +- PTF7_IN_PU, PTF6_IN_PU, PTF5_IN_PU, PTF4_IN_PU, +- PTF3_IN_PU, PTF2_IN_PU, PTF1_IN_PU, PTF0_IN_PU, +- PTH7_IN_PU, PTH6_IN_PU, PTH5_IN_PU, PTH4_IN_PU, +- PTH3_IN_PU, PTH2_IN_PU, PTH1_IN_PU, PTH0_IN_PU, +- PTJ3_IN_PU, PTJ2_IN_PU, PTJ1_IN_PU, PTJ0_IN_PU, +- PTK7_IN_PU, PTK6_IN_PU, PTK5_IN_PU, PTK4_IN_PU, +- PTK3_IN_PU, PTK2_IN_PU, PTK1_IN_PU, PTK0_IN_PU, +- PTL7_IN_PU, PTL6_IN_PU, PTL5_IN_PU, PTL4_IN_PU, +- PTL3_IN_PU, PTL2_IN_PU, PTL1_IN_PU, PTL0_IN_PU, +- PTM7_IN_PU, PTM6_IN_PU, PTM5_IN_PU, PTM4_IN_PU, +- PTM3_IN_PU, PTM2_IN_PU, PTM1_IN_PU, PTM0_IN_PU, +- PTN7_IN_PU, PTN6_IN_PU, PTN5_IN_PU, PTN4_IN_PU, +- PTN3_IN_PU, PTN2_IN_PU, PTN1_IN_PU, PTN0_IN_PU, +- PTQ7_IN_PU, PTQ6_IN_PU, PTQ5_IN_PU, PTQ4_IN_PU, +- PTQ3_IN_PU, PTQ2_IN_PU, PTQ1_IN_PU, PTQ0_IN_PU, +- PTR7_IN_PU, PTR6_IN_PU, PTR5_IN_PU, PTR4_IN_PU, +- PTR3_IN_PU, PTR2_IN_PU, PTR1_IN_PU, PTR0_IN_PU, +- PTS6_IN_PU, PTS5_IN_PU, PTS4_IN_PU, +- PTS3_IN_PU, PTS2_IN_PU, PTS1_IN_PU, PTS0_IN_PU, +- PTT7_IN_PU, PTT6_IN_PU, PTT5_IN_PU, PTT4_IN_PU, +- PTT3_IN_PU, PTT2_IN_PU, PTT1_IN_PU, PTT0_IN_PU, +- PTU7_IN_PU, PTU6_IN_PU, PTU5_IN_PU, PTU4_IN_PU, +- PTU3_IN_PU, PTU2_IN_PU, PTU1_IN_PU, PTU0_IN_PU, +- PTV7_IN_PU, PTV6_IN_PU, PTV5_IN_PU, PTV4_IN_PU, +- PTV3_IN_PU, PTV2_IN_PU, PTV1_IN_PU, PTV0_IN_PU, +- PTW7_IN_PU, PTW6_IN_PU, PTW5_IN_PU, PTW4_IN_PU, +- PTW3_IN_PU, PTW2_IN_PU, PTW1_IN_PU, PTW0_IN_PU, +- PTX7_IN_PU, PTX6_IN_PU, PTX5_IN_PU, PTX4_IN_PU, +- PTX3_IN_PU, PTX2_IN_PU, PTX1_IN_PU, PTX0_IN_PU, +- PTY7_IN_PU, PTY6_IN_PU, PTY5_IN_PU, PTY4_IN_PU, +- PTY3_IN_PU, PTY2_IN_PU, PTY1_IN_PU, PTY0_IN_PU, +- PTZ7_IN_PU, PTZ6_IN_PU, PTZ5_IN_PU, PTZ4_IN_PU, +- PTZ3_IN_PU, PTZ2_IN_PU, PTZ1_IN_PU, PTZ0_IN_PU, +- PINMUX_INPUT_PULLUP_END, +- + PINMUX_OUTPUT_BEGIN, + PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT, + PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT, +@@ -574,64 +528,64 @@ enum { + + static const pinmux_enum_t pinmux_data[] = { + /* PTA GPIO */ +- PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT, PTA7_IN_PU), +- PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT, PTA6_IN_PU), +- PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT, PTA5_IN_PU), +- PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT, PTA4_IN_PU), +- PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT, PTA3_IN_PU), +- PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT, PTA2_IN_PU), +- PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT, PTA1_IN_PU), +- PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT, PTA0_IN_PU), ++ PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT), ++ PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT), ++ PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT), ++ PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT), ++ PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT), ++ PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT), ++ PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT), ++ PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT), + + /* PTB GPIO */ +- PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT, PTB7_IN_PU), +- PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT, PTB6_IN_PU), +- PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT, PTB5_IN_PU), +- PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT, PTB4_IN_PU), +- PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT, PTB3_IN_PU), +- PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT, PTB2_IN_PU), +- PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT, PTB1_IN_PU), +- PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT, PTB0_IN_PU), ++ PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT), ++ PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT), ++ PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT), ++ PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT), ++ PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT), ++ PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT), ++ PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT), ++ PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT), + + /* PTC GPIO */ +- PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT, PTC7_IN_PU), +- PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT, PTC6_IN_PU), +- PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT, PTC5_IN_PU), +- PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT, PTC4_IN_PU), +- PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT, PTC3_IN_PU), +- PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT, PTC2_IN_PU), +- PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT, PTC1_IN_PU), +- PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT, PTC0_IN_PU), ++ PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT), ++ PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT), ++ PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT), ++ PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT), ++ PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT), ++ PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT), ++ PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT), ++ PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT), + + /* PTD GPIO */ +- PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT, PTD7_IN_PU), +- PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT, PTD6_IN_PU), +- PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT, PTD5_IN_PU), +- PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT, PTD4_IN_PU), +- PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT, PTD3_IN_PU), +- PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT, PTD2_IN_PU), +- PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT, PTD1_IN_PU), +- PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT, PTD0_IN_PU), ++ PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT), ++ PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT), ++ PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT), ++ PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT), ++ PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT), ++ PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT), ++ PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT), ++ PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT), + + /* PTE GPIO */ +- PINMUX_DATA(PTE7_DATA, PTE7_IN, PTE7_OUT, PTE7_IN_PU), +- PINMUX_DATA(PTE6_DATA, PTE6_IN, PTE6_OUT, PTE6_IN_PU), +- PINMUX_DATA(PTE5_DATA, PTE5_IN, PTE5_OUT, PTE5_IN_PU), +- PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT, PTE4_IN_PU), +- PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT, PTE3_IN_PU), +- PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT, PTE2_IN_PU), +- PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT, PTE1_IN_PU), +- PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT, PTE0_IN_PU), ++ PINMUX_DATA(PTE7_DATA, PTE7_IN, PTE7_OUT), ++ PINMUX_DATA(PTE6_DATA, PTE6_IN, PTE6_OUT), ++ PINMUX_DATA(PTE5_DATA, PTE5_IN, PTE5_OUT), ++ PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT), ++ PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT), ++ PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT), ++ PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT), ++ PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT), + + /* PTF GPIO */ +- PINMUX_DATA(PTF7_DATA, PTF7_IN, PTF7_OUT, PTF7_IN_PU), +- PINMUX_DATA(PTF6_DATA, PTF6_IN, PTF6_OUT, PTF6_IN_PU), +- PINMUX_DATA(PTF5_DATA, PTF5_IN, PTF5_OUT, PTF5_IN_PU), +- PINMUX_DATA(PTF4_DATA, PTF4_IN, PTF4_OUT, PTF4_IN_PU), +- PINMUX_DATA(PTF3_DATA, PTF3_IN, PTF3_OUT, PTF3_IN_PU), +- PINMUX_DATA(PTF2_DATA, PTF2_IN, PTF2_OUT, PTF2_IN_PU), +- PINMUX_DATA(PTF1_DATA, PTF1_IN, PTF1_OUT, PTF1_IN_PU), +- PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT, PTF0_IN_PU), ++ PINMUX_DATA(PTF7_DATA, PTF7_IN, PTF7_OUT), ++ PINMUX_DATA(PTF6_DATA, PTF6_IN, PTF6_OUT), ++ PINMUX_DATA(PTF5_DATA, PTF5_IN, PTF5_OUT), ++ PINMUX_DATA(PTF4_DATA, PTF4_IN, PTF4_OUT), ++ PINMUX_DATA(PTF3_DATA, PTF3_IN, PTF3_OUT), ++ PINMUX_DATA(PTF2_DATA, PTF2_IN, PTF2_OUT), ++ PINMUX_DATA(PTF1_DATA, PTF1_IN, PTF1_OUT), ++ PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT), + + /* PTG GPIO */ + PINMUX_DATA(PTG5_DATA, PTG5_OUT), +@@ -642,162 +596,162 @@ static const pinmux_enum_t pinmux_data[] = { + PINMUX_DATA(PTG0_DATA, PTG0_OUT), + + /* PTH GPIO */ +- PINMUX_DATA(PTH7_DATA, PTH7_IN, PTH7_OUT, PTH7_IN_PU), +- PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT, PTH6_IN_PU), +- PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT, PTH5_IN_PU), +- PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT, PTH4_IN_PU), +- PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT, PTH3_IN_PU), +- PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT, PTH2_IN_PU), +- PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT, PTH1_IN_PU), +- PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT, PTH0_IN_PU), ++ PINMUX_DATA(PTH7_DATA, PTH7_IN, PTH7_OUT), ++ PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT), ++ PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT), ++ PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT), ++ PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT), ++ PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT), ++ PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT), ++ PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT), + + /* PTJ GPIO */ + PINMUX_DATA(PTJ7_DATA, PTJ7_OUT), + PINMUX_DATA(PTJ6_DATA, PTJ6_OUT), + PINMUX_DATA(PTJ5_DATA, PTJ5_OUT), +- PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT, PTJ3_IN_PU), +- PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT, PTJ2_IN_PU), +- PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT, PTJ1_IN_PU), +- PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT, PTJ0_IN_PU), ++ PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT), ++ PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT), ++ PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT), ++ PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT), + + /* PTK GPIO */ +- PINMUX_DATA(PTK7_DATA, PTK7_IN, PTK7_OUT, PTK7_IN_PU), +- PINMUX_DATA(PTK6_DATA, PTK6_IN, PTK6_OUT, PTK6_IN_PU), +- PINMUX_DATA(PTK5_DATA, PTK5_IN, PTK5_OUT, PTK5_IN_PU), +- PINMUX_DATA(PTK4_DATA, PTK4_IN, PTK4_OUT, PTK4_IN_PU), +- PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT, PTK3_IN_PU), +- PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT, PTK2_IN_PU), +- PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT, PTK1_IN_PU), +- PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT, PTK0_IN_PU), ++ PINMUX_DATA(PTK7_DATA, PTK7_IN, PTK7_OUT), ++ PINMUX_DATA(PTK6_DATA, PTK6_IN, PTK6_OUT), ++ PINMUX_DATA(PTK5_DATA, PTK5_IN, PTK5_OUT), ++ PINMUX_DATA(PTK4_DATA, PTK4_IN, PTK4_OUT), ++ PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT), ++ PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT), ++ PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT), ++ PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT), + + /* PTL GPIO */ +- PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT, PTL7_IN_PU), +- PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT, PTL6_IN_PU), +- PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT, PTL5_IN_PU), +- PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT, PTL4_IN_PU), +- PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT, PTL3_IN_PU), +- PINMUX_DATA(PTL2_DATA, PTL2_IN, PTL2_OUT, PTL2_IN_PU), +- PINMUX_DATA(PTL1_DATA, PTL1_IN, PTL1_OUT, PTL1_IN_PU), +- PINMUX_DATA(PTL0_DATA, PTL0_IN, PTL0_OUT, PTL0_IN_PU), ++ PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT), ++ PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT), ++ PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT), ++ PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT), ++ PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT), ++ PINMUX_DATA(PTL2_DATA, PTL2_IN, PTL2_OUT), ++ PINMUX_DATA(PTL1_DATA, PTL1_IN, PTL1_OUT), ++ PINMUX_DATA(PTL0_DATA, PTL0_IN, PTL0_OUT), + + /* PTM GPIO */ +- PINMUX_DATA(PTM7_DATA, PTM7_IN, PTM7_OUT, PTM7_IN_PU), +- PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT, PTM6_IN_PU), +- PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT, PTM5_IN_PU), +- PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT, PTM4_IN_PU), +- PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT, PTM3_IN_PU), +- PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT, PTM2_IN_PU), +- PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT, PTM1_IN_PU), +- PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT, PTM0_IN_PU), ++ PINMUX_DATA(PTM7_DATA, PTM7_IN, PTM7_OUT), ++ PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT), ++ PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT), ++ PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT), ++ PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT), ++ PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT), ++ PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT), ++ PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT), + + /* PTN GPIO */ +- PINMUX_DATA(PTN7_DATA, PTN7_IN, PTN7_OUT, PTN7_IN_PU), +- PINMUX_DATA(PTN6_DATA, PTN6_IN, PTN6_OUT, PTN6_IN_PU), +- PINMUX_DATA(PTN5_DATA, PTN5_IN, PTN5_OUT, PTN5_IN_PU), +- PINMUX_DATA(PTN4_DATA, PTN4_IN, PTN4_OUT, PTN4_IN_PU), +- PINMUX_DATA(PTN3_DATA, PTN3_IN, PTN3_OUT, PTN3_IN_PU), +- PINMUX_DATA(PTN2_DATA, PTN2_IN, PTN2_OUT, PTN2_IN_PU), +- PINMUX_DATA(PTN1_DATA, PTN1_IN, PTN1_OUT, PTN1_IN_PU), +- PINMUX_DATA(PTN0_DATA, PTN0_IN, PTN0_OUT, PTN0_IN_PU), ++ PINMUX_DATA(PTN7_DATA, PTN7_IN, PTN7_OUT), ++ PINMUX_DATA(PTN6_DATA, PTN6_IN, PTN6_OUT), ++ PINMUX_DATA(PTN5_DATA, PTN5_IN, PTN5_OUT), ++ PINMUX_DATA(PTN4_DATA, PTN4_IN, PTN4_OUT), ++ PINMUX_DATA(PTN3_DATA, PTN3_IN, PTN3_OUT), ++ PINMUX_DATA(PTN2_DATA, PTN2_IN, PTN2_OUT), ++ PINMUX_DATA(PTN1_DATA, PTN1_IN, PTN1_OUT), ++ PINMUX_DATA(PTN0_DATA, PTN0_IN, PTN0_OUT), + + /* PTQ GPIO */ +- PINMUX_DATA(PTQ7_DATA, PTQ7_IN, PTQ7_OUT, PTQ7_IN_PU), +- PINMUX_DATA(PTQ6_DATA, PTQ6_IN, PTQ6_OUT, PTQ6_IN_PU), +- PINMUX_DATA(PTQ5_DATA, PTQ5_IN, PTQ5_OUT, PTQ5_IN_PU), +- PINMUX_DATA(PTQ4_DATA, PTQ4_IN, PTQ4_OUT, PTQ4_IN_PU), +- PINMUX_DATA(PTQ3_DATA, PTQ3_IN, PTQ3_OUT, PTQ3_IN_PU), +- PINMUX_DATA(PTQ2_DATA, PTQ2_IN, PTQ2_OUT, PTQ2_IN_PU), +- PINMUX_DATA(PTQ1_DATA, PTQ1_IN, PTQ1_OUT, PTQ1_IN_PU), +- PINMUX_DATA(PTQ0_DATA, PTQ0_IN, PTQ0_OUT, PTQ0_IN_PU), ++ PINMUX_DATA(PTQ7_DATA, PTQ7_IN, PTQ7_OUT), ++ PINMUX_DATA(PTQ6_DATA, PTQ6_IN, PTQ6_OUT), ++ PINMUX_DATA(PTQ5_DATA, PTQ5_IN, PTQ5_OUT), ++ PINMUX_DATA(PTQ4_DATA, PTQ4_IN, PTQ4_OUT), ++ PINMUX_DATA(PTQ3_DATA, PTQ3_IN, PTQ3_OUT), ++ PINMUX_DATA(PTQ2_DATA, PTQ2_IN, PTQ2_OUT), ++ PINMUX_DATA(PTQ1_DATA, PTQ1_IN, PTQ1_OUT), ++ PINMUX_DATA(PTQ0_DATA, PTQ0_IN, PTQ0_OUT), + + /* PTR GPIO */ +- PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT, PTR7_IN_PU), +- PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT, PTR6_IN_PU), +- PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT, PTR5_IN_PU), +- PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT, PTR4_IN_PU), +- PINMUX_DATA(PTR3_DATA, PTR3_IN, PTR3_IN_PU), +- PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_IN_PU), +- PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT, PTR1_IN_PU), +- PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT, PTR0_IN_PU), ++ PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT), ++ PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT), ++ PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT), ++ PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT), ++ PINMUX_DATA(PTR3_DATA, PTR3_IN), ++ PINMUX_DATA(PTR2_DATA, PTR2_IN), ++ PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT), ++ PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT), + + /* PTS GPIO */ +- PINMUX_DATA(PTS6_DATA, PTS6_IN, PTS6_OUT, PTS6_IN_PU), +- PINMUX_DATA(PTS5_DATA, PTS5_IN, PTS5_OUT, PTS5_IN_PU), +- PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT, PTS4_IN_PU), +- PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT, PTS3_IN_PU), +- PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT, PTS2_IN_PU), +- PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT, PTS1_IN_PU), +- PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT, PTS0_IN_PU), ++ PINMUX_DATA(PTS6_DATA, PTS6_IN, PTS6_OUT), ++ PINMUX_DATA(PTS5_DATA, PTS5_IN, PTS5_OUT), ++ PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT), ++ PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT), ++ PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT), ++ PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT), ++ PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT), + + /* PTT GPIO */ +- PINMUX_DATA(PTT7_DATA, PTT7_IN, PTT7_OUT, PTT7_IN_PU), +- PINMUX_DATA(PTT6_DATA, PTT6_IN, PTT6_OUT, PTT6_IN_PU), +- PINMUX_DATA(PTT5_DATA, PTT5_IN, PTT5_OUT, PTT5_IN_PU), +- PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT, PTT4_IN_PU), +- PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT, PTT3_IN_PU), +- PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT, PTT2_IN_PU), +- PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT, PTT1_IN_PU), +- PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT, PTT0_IN_PU), ++ PINMUX_DATA(PTT7_DATA, PTT7_IN, PTT7_OUT), ++ PINMUX_DATA(PTT6_DATA, PTT6_IN, PTT6_OUT), ++ PINMUX_DATA(PTT5_DATA, PTT5_IN, PTT5_OUT), ++ PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT), ++ PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT), ++ PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT), ++ PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT), ++ PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT), + + /* PTU GPIO */ +- PINMUX_DATA(PTU7_DATA, PTU7_IN, PTU7_OUT, PTU7_IN_PU), +- PINMUX_DATA(PTU6_DATA, PTU6_IN, PTU6_OUT, PTU6_IN_PU), +- PINMUX_DATA(PTU5_DATA, PTU5_IN, PTU5_OUT, PTU5_IN_PU), +- PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT, PTU4_IN_PU), +- PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT, PTU3_IN_PU), +- PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT, PTU2_IN_PU), +- PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT, PTU1_IN_PU), +- PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT, PTU0_IN_PU), ++ PINMUX_DATA(PTU7_DATA, PTU7_IN, PTU7_OUT), ++ PINMUX_DATA(PTU6_DATA, PTU6_IN, PTU6_OUT), ++ PINMUX_DATA(PTU5_DATA, PTU5_IN, PTU5_OUT), ++ PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT), ++ PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT), ++ PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT), ++ PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT), ++ PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT), + + /* PTV GPIO */ +- PINMUX_DATA(PTV7_DATA, PTV7_IN, PTV7_OUT, PTV7_IN_PU), +- PINMUX_DATA(PTV6_DATA, PTV6_IN, PTV6_OUT, PTV6_IN_PU), +- PINMUX_DATA(PTV5_DATA, PTV5_IN, PTV5_OUT, PTV5_IN_PU), +- PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT, PTV4_IN_PU), +- PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT, PTV3_IN_PU), +- PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT, PTV2_IN_PU), +- PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT, PTV1_IN_PU), +- PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT, PTV0_IN_PU), ++ PINMUX_DATA(PTV7_DATA, PTV7_IN, PTV7_OUT), ++ PINMUX_DATA(PTV6_DATA, PTV6_IN, PTV6_OUT), ++ PINMUX_DATA(PTV5_DATA, PTV5_IN, PTV5_OUT), ++ PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT), ++ PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT), ++ PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT), ++ PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT), ++ PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT), + + /* PTW GPIO */ +- PINMUX_DATA(PTW7_DATA, PTW7_IN, PTW7_OUT, PTW7_IN_PU), +- PINMUX_DATA(PTW6_DATA, PTW6_IN, PTW6_OUT, PTW6_IN_PU), +- PINMUX_DATA(PTW5_DATA, PTW5_IN, PTW5_OUT, PTW5_IN_PU), +- PINMUX_DATA(PTW4_DATA, PTW4_IN, PTW4_OUT, PTW4_IN_PU), +- PINMUX_DATA(PTW3_DATA, PTW3_IN, PTW3_OUT, PTW3_IN_PU), +- PINMUX_DATA(PTW2_DATA, PTW2_IN, PTW2_OUT, PTW2_IN_PU), +- PINMUX_DATA(PTW1_DATA, PTW1_IN, PTW1_OUT, PTW1_IN_PU), +- PINMUX_DATA(PTW0_DATA, PTW0_IN, PTW0_OUT, PTW0_IN_PU), ++ PINMUX_DATA(PTW7_DATA, PTW7_IN, PTW7_OUT), ++ PINMUX_DATA(PTW6_DATA, PTW6_IN, PTW6_OUT), ++ PINMUX_DATA(PTW5_DATA, PTW5_IN, PTW5_OUT), ++ PINMUX_DATA(PTW4_DATA, PTW4_IN, PTW4_OUT), ++ PINMUX_DATA(PTW3_DATA, PTW3_IN, PTW3_OUT), ++ PINMUX_DATA(PTW2_DATA, PTW2_IN, PTW2_OUT), ++ PINMUX_DATA(PTW1_DATA, PTW1_IN, PTW1_OUT), ++ PINMUX_DATA(PTW0_DATA, PTW0_IN, PTW0_OUT), + + /* PTX GPIO */ +- PINMUX_DATA(PTX7_DATA, PTX7_IN, PTX7_OUT, PTX7_IN_PU), +- PINMUX_DATA(PTX6_DATA, PTX6_IN, PTX6_OUT, PTX6_IN_PU), +- PINMUX_DATA(PTX5_DATA, PTX5_IN, PTX5_OUT, PTX5_IN_PU), +- PINMUX_DATA(PTX4_DATA, PTX4_IN, PTX4_OUT, PTX4_IN_PU), +- PINMUX_DATA(PTX3_DATA, PTX3_IN, PTX3_OUT, PTX3_IN_PU), +- PINMUX_DATA(PTX2_DATA, PTX2_IN, PTX2_OUT, PTX2_IN_PU), +- PINMUX_DATA(PTX1_DATA, PTX1_IN, PTX1_OUT, PTX1_IN_PU), +- PINMUX_DATA(PTX0_DATA, PTX0_IN, PTX0_OUT, PTX0_IN_PU), ++ PINMUX_DATA(PTX7_DATA, PTX7_IN, PTX7_OUT), ++ PINMUX_DATA(PTX6_DATA, PTX6_IN, PTX6_OUT), ++ PINMUX_DATA(PTX5_DATA, PTX5_IN, PTX5_OUT), ++ PINMUX_DATA(PTX4_DATA, PTX4_IN, PTX4_OUT), ++ PINMUX_DATA(PTX3_DATA, PTX3_IN, PTX3_OUT), ++ PINMUX_DATA(PTX2_DATA, PTX2_IN, PTX2_OUT), ++ PINMUX_DATA(PTX1_DATA, PTX1_IN, PTX1_OUT), ++ PINMUX_DATA(PTX0_DATA, PTX0_IN, PTX0_OUT), + + /* PTY GPIO */ +- PINMUX_DATA(PTY7_DATA, PTY7_IN, PTY7_OUT, PTY7_IN_PU), +- PINMUX_DATA(PTY6_DATA, PTY6_IN, PTY6_OUT, PTY6_IN_PU), +- PINMUX_DATA(PTY5_DATA, PTY5_IN, PTY5_OUT, PTY5_IN_PU), +- PINMUX_DATA(PTY4_DATA, PTY4_IN, PTY4_OUT, PTY4_IN_PU), +- PINMUX_DATA(PTY3_DATA, PTY3_IN, PTY3_OUT, PTY3_IN_PU), +- PINMUX_DATA(PTY2_DATA, PTY2_IN, PTY2_OUT, PTY2_IN_PU), +- PINMUX_DATA(PTY1_DATA, PTY1_IN, PTY1_OUT, PTY1_IN_PU), +- PINMUX_DATA(PTY0_DATA, PTY0_IN, PTY0_OUT, PTY0_IN_PU), ++ PINMUX_DATA(PTY7_DATA, PTY7_IN, PTY7_OUT), ++ PINMUX_DATA(PTY6_DATA, PTY6_IN, PTY6_OUT), ++ PINMUX_DATA(PTY5_DATA, PTY5_IN, PTY5_OUT), ++ PINMUX_DATA(PTY4_DATA, PTY4_IN, PTY4_OUT), ++ PINMUX_DATA(PTY3_DATA, PTY3_IN, PTY3_OUT), ++ PINMUX_DATA(PTY2_DATA, PTY2_IN, PTY2_OUT), ++ PINMUX_DATA(PTY1_DATA, PTY1_IN, PTY1_OUT), ++ PINMUX_DATA(PTY0_DATA, PTY0_IN, PTY0_OUT), + + /* PTZ GPIO */ +- PINMUX_DATA(PTZ7_DATA, PTZ7_IN, PTZ7_OUT, PTZ7_IN_PU), +- PINMUX_DATA(PTZ6_DATA, PTZ6_IN, PTZ6_OUT, PTZ6_IN_PU), +- PINMUX_DATA(PTZ5_DATA, PTZ5_IN, PTZ5_OUT, PTZ5_IN_PU), +- PINMUX_DATA(PTZ4_DATA, PTZ4_IN, PTZ4_OUT, PTZ4_IN_PU), +- PINMUX_DATA(PTZ3_DATA, PTZ3_IN, PTZ3_OUT, PTZ3_IN_PU), +- PINMUX_DATA(PTZ2_DATA, PTZ2_IN, PTZ2_OUT, PTZ2_IN_PU), +- PINMUX_DATA(PTZ1_DATA, PTZ1_IN, PTZ1_OUT, PTZ1_IN_PU), +- PINMUX_DATA(PTZ0_DATA, PTZ0_IN, PTZ0_OUT, PTZ0_IN_PU), ++ PINMUX_DATA(PTZ7_DATA, PTZ7_IN, PTZ7_OUT), ++ PINMUX_DATA(PTZ6_DATA, PTZ6_IN, PTZ6_OUT), ++ PINMUX_DATA(PTZ5_DATA, PTZ5_IN, PTZ5_OUT), ++ PINMUX_DATA(PTZ4_DATA, PTZ4_IN, PTZ4_OUT), ++ PINMUX_DATA(PTZ3_DATA, PTZ3_IN, PTZ3_OUT), ++ PINMUX_DATA(PTZ2_DATA, PTZ2_IN, PTZ2_OUT), ++ PINMUX_DATA(PTZ1_DATA, PTZ1_IN, PTZ1_OUT), ++ PINMUX_DATA(PTZ0_DATA, PTZ0_IN, PTZ0_OUT), + + /* PTA FN */ + PINMUX_DATA(D23_MARK, PSA15_0, PSA14_0, PTA7_FN), +@@ -1789,64 +1743,64 @@ static const struct pinmux_func pinmux_func_gpios[] = { + + static const struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { +- PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN, +- PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN, +- PTA5_FN, PTA5_OUT, PTA5_IN_PU, PTA5_IN, +- PTA4_FN, PTA4_OUT, PTA4_IN_PU, PTA4_IN, +- PTA3_FN, PTA3_OUT, PTA3_IN_PU, PTA3_IN, +- PTA2_FN, PTA2_OUT, PTA2_IN_PU, PTA2_IN, +- PTA1_FN, PTA1_OUT, PTA1_IN_PU, PTA1_IN, +- PTA0_FN, PTA0_OUT, PTA0_IN_PU, PTA0_IN } ++ PTA7_FN, PTA7_OUT, 0, PTA7_IN, ++ PTA6_FN, PTA6_OUT, 0, PTA6_IN, ++ PTA5_FN, PTA5_OUT, 0, PTA5_IN, ++ PTA4_FN, PTA4_OUT, 0, PTA4_IN, ++ PTA3_FN, PTA3_OUT, 0, PTA3_IN, ++ PTA2_FN, PTA2_OUT, 0, PTA2_IN, ++ PTA1_FN, PTA1_OUT, 0, PTA1_IN, ++ PTA0_FN, PTA0_OUT, 0, PTA0_IN } + }, + { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) { +- PTB7_FN, PTB7_OUT, PTB7_IN_PU, PTB7_IN, +- PTB6_FN, PTB6_OUT, PTB6_IN_PU, PTB6_IN, +- PTB5_FN, PTB5_OUT, PTB5_IN_PU, PTB5_IN, +- PTB4_FN, PTB4_OUT, PTB4_IN_PU, PTB4_IN, +- PTB3_FN, PTB3_OUT, PTB3_IN_PU, PTB3_IN, +- PTB2_FN, PTB2_OUT, PTB2_IN_PU, PTB2_IN, +- PTB1_FN, PTB1_OUT, PTB1_IN_PU, PTB1_IN, +- PTB0_FN, PTB0_OUT, PTB0_IN_PU, PTB0_IN } ++ PTB7_FN, PTB7_OUT, 0, PTB7_IN, ++ PTB6_FN, PTB6_OUT, 0, PTB6_IN, ++ PTB5_FN, PTB5_OUT, 0, PTB5_IN, ++ PTB4_FN, PTB4_OUT, 0, PTB4_IN, ++ PTB3_FN, PTB3_OUT, 0, PTB3_IN, ++ PTB2_FN, PTB2_OUT, 0, PTB2_IN, ++ PTB1_FN, PTB1_OUT, 0, PTB1_IN, ++ PTB0_FN, PTB0_OUT, 0, PTB0_IN } + }, + { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) { +- PTC7_FN, PTC7_OUT, PTC7_IN_PU, PTC7_IN, +- PTC6_FN, PTC6_OUT, PTC6_IN_PU, PTC6_IN, +- PTC5_FN, PTC5_OUT, PTC5_IN_PU, PTC5_IN, +- PTC4_FN, PTC4_OUT, PTC4_IN_PU, PTC4_IN, +- PTC3_FN, PTC3_OUT, PTC3_IN_PU, PTC3_IN, +- PTC2_FN, PTC2_OUT, PTC2_IN_PU, PTC2_IN, +- PTC1_FN, PTC1_OUT, PTC1_IN_PU, PTC1_IN, +- PTC0_FN, PTC0_OUT, PTC0_IN_PU, PTC0_IN } ++ PTC7_FN, PTC7_OUT, 0, PTC7_IN, ++ PTC6_FN, PTC6_OUT, 0, PTC6_IN, ++ PTC5_FN, PTC5_OUT, 0, PTC5_IN, ++ PTC4_FN, PTC4_OUT, 0, PTC4_IN, ++ PTC3_FN, PTC3_OUT, 0, PTC3_IN, ++ PTC2_FN, PTC2_OUT, 0, PTC2_IN, ++ PTC1_FN, PTC1_OUT, 0, PTC1_IN, ++ PTC0_FN, PTC0_OUT, 0, PTC0_IN } + }, + { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) { +- PTD7_FN, PTD7_OUT, PTD7_IN_PU, PTD7_IN, +- PTD6_FN, PTD6_OUT, PTD6_IN_PU, PTD6_IN, +- PTD5_FN, PTD5_OUT, PTD5_IN_PU, PTD5_IN, +- PTD4_FN, PTD4_OUT, PTD4_IN_PU, PTD4_IN, +- PTD3_FN, PTD3_OUT, PTD3_IN_PU, PTD3_IN, +- PTD2_FN, PTD2_OUT, PTD2_IN_PU, PTD2_IN, +- PTD1_FN, PTD1_OUT, PTD1_IN_PU, PTD1_IN, +- PTD0_FN, PTD0_OUT, PTD0_IN_PU, PTD0_IN } ++ PTD7_FN, PTD7_OUT, 0, PTD7_IN, ++ PTD6_FN, PTD6_OUT, 0, PTD6_IN, ++ PTD5_FN, PTD5_OUT, 0, PTD5_IN, ++ PTD4_FN, PTD4_OUT, 0, PTD4_IN, ++ PTD3_FN, PTD3_OUT, 0, PTD3_IN, ++ PTD2_FN, PTD2_OUT, 0, PTD2_IN, ++ PTD1_FN, PTD1_OUT, 0, PTD1_IN, ++ PTD0_FN, PTD0_OUT, 0, PTD0_IN } + }, + { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) { +- PTE7_FN, PTE7_OUT, PTE7_IN_PU, PTE7_IN, +- PTE6_FN, PTE6_OUT, PTE6_IN_PU, PTE6_IN, +- PTE5_FN, PTE5_OUT, PTE5_IN_PU, PTE5_IN, +- PTE4_FN, PTE4_OUT, PTE4_IN_PU, PTE4_IN, +- PTE3_FN, PTE3_OUT, PTE3_IN_PU, PTE3_IN, +- PTE2_FN, PTE2_OUT, PTE2_IN_PU, PTE2_IN, +- PTE1_FN, PTE1_OUT, PTE1_IN_PU, PTE1_IN, +- PTE0_FN, PTE0_OUT, PTE0_IN_PU, PTE0_IN } ++ PTE7_FN, PTE7_OUT, 0, PTE7_IN, ++ PTE6_FN, PTE6_OUT, 0, PTE6_IN, ++ PTE5_FN, PTE5_OUT, 0, PTE5_IN, ++ PTE4_FN, PTE4_OUT, 0, PTE4_IN, ++ PTE3_FN, PTE3_OUT, 0, PTE3_IN, ++ PTE2_FN, PTE2_OUT, 0, PTE2_IN, ++ PTE1_FN, PTE1_OUT, 0, PTE1_IN, ++ PTE0_FN, PTE0_OUT, 0, PTE0_IN } + }, + { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) { +- PTF7_FN, PTF7_OUT, PTF7_IN_PU, PTF7_IN, +- PTF6_FN, PTF6_OUT, PTF6_IN_PU, PTF6_IN, +- PTF5_FN, PTF5_OUT, PTF5_IN_PU, PTF5_IN, +- PTF4_FN, PTF4_OUT, PTF4_IN_PU, PTF4_IN, +- PTF3_FN, PTF3_OUT, PTF3_IN_PU, PTF3_IN, +- PTF2_FN, PTF2_OUT, PTF2_IN_PU, PTF2_IN, +- PTF1_FN, PTF1_OUT, PTF1_IN_PU, PTF1_IN, +- PTF0_FN, PTF0_OUT, PTF0_IN_PU, PTF0_IN } ++ PTF7_FN, PTF7_OUT, 0, PTF7_IN, ++ PTF6_FN, PTF6_OUT, 0, PTF6_IN, ++ PTF5_FN, PTF5_OUT, 0, PTF5_IN, ++ PTF4_FN, PTF4_OUT, 0, PTF4_IN, ++ PTF3_FN, PTF3_OUT, 0, PTF3_IN, ++ PTF2_FN, PTF2_OUT, 0, PTF2_IN, ++ PTF1_FN, PTF1_OUT, 0, PTF1_IN, ++ PTF0_FN, PTF0_OUT, 0, PTF0_IN } + }, + { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) { + 0, 0, 0, 0, +@@ -1859,164 +1813,164 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + PTG0_FN, PTG0_OUT, 0, 0 } + }, + { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) { +- PTH7_FN, PTH7_OUT, PTH7_IN_PU, PTH7_IN, +- PTH6_FN, PTH6_OUT, PTH6_IN_PU, PTH6_IN, +- PTH5_FN, PTH5_OUT, PTH5_IN_PU, PTH5_IN, +- PTH4_FN, PTH4_OUT, PTH4_IN_PU, PTH4_IN, +- PTH3_FN, PTH3_OUT, PTH3_IN_PU, PTH3_IN, +- PTH2_FN, PTH2_OUT, PTH2_IN_PU, PTH2_IN, +- PTH1_FN, PTH1_OUT, PTH1_IN_PU, PTH1_IN, +- PTH0_FN, PTH0_OUT, PTH0_IN_PU, PTH0_IN } ++ PTH7_FN, PTH7_OUT, 0, PTH7_IN, ++ PTH6_FN, PTH6_OUT, 0, PTH6_IN, ++ PTH5_FN, PTH5_OUT, 0, PTH5_IN, ++ PTH4_FN, PTH4_OUT, 0, PTH4_IN, ++ PTH3_FN, PTH3_OUT, 0, PTH3_IN, ++ PTH2_FN, PTH2_OUT, 0, PTH2_IN, ++ PTH1_FN, PTH1_OUT, 0, PTH1_IN, ++ PTH0_FN, PTH0_OUT, 0, PTH0_IN } + }, + { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) { + PTJ7_FN, PTJ7_OUT, 0, 0, + PTJ6_FN, PTJ6_OUT, 0, 0, + PTJ5_FN, PTJ5_OUT, 0, 0, + 0, 0, 0, 0, +- PTJ3_FN, PTJ3_OUT, PTJ3_IN_PU, PTJ3_IN, +- PTJ2_FN, PTJ2_OUT, PTJ2_IN_PU, PTJ2_IN, +- PTJ1_FN, PTJ1_OUT, PTJ1_IN_PU, PTJ1_IN, +- PTJ0_FN, PTJ0_OUT, PTJ0_IN_PU, PTJ0_IN } ++ PTJ3_FN, PTJ3_OUT, 0, PTJ3_IN, ++ PTJ2_FN, PTJ2_OUT, 0, PTJ2_IN, ++ PTJ1_FN, PTJ1_OUT, 0, PTJ1_IN, ++ PTJ0_FN, PTJ0_OUT, 0, PTJ0_IN } + }, + { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) { +- PTK7_FN, PTK7_OUT, PTK7_IN_PU, PTK7_IN, +- PTK6_FN, PTK6_OUT, PTK6_IN_PU, PTK6_IN, +- PTK5_FN, PTK5_OUT, PTK5_IN_PU, PTK5_IN, +- PTK4_FN, PTK4_OUT, PTK4_IN_PU, PTK4_IN, +- PTK3_FN, PTK3_OUT, PTK3_IN_PU, PTK3_IN, +- PTK2_FN, PTK2_OUT, PTK2_IN_PU, PTK2_IN, +- PTK1_FN, PTK1_OUT, PTK1_IN_PU, PTK1_IN, +- PTK0_FN, PTK0_OUT, PTK0_IN_PU, PTK0_IN } ++ PTK7_FN, PTK7_OUT, 0, PTK7_IN, ++ PTK6_FN, PTK6_OUT, 0, PTK6_IN, ++ PTK5_FN, PTK5_OUT, 0, PTK5_IN, ++ PTK4_FN, PTK4_OUT, 0, PTK4_IN, ++ PTK3_FN, PTK3_OUT, 0, PTK3_IN, ++ PTK2_FN, PTK2_OUT, 0, PTK2_IN, ++ PTK1_FN, PTK1_OUT, 0, PTK1_IN, ++ PTK0_FN, PTK0_OUT, 0, PTK0_IN } + }, + { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) { +- PTL7_FN, PTL7_OUT, PTL7_IN_PU, PTL7_IN, +- PTL6_FN, PTL6_OUT, PTL6_IN_PU, PTL6_IN, +- PTL5_FN, PTL5_OUT, PTL5_IN_PU, PTL5_IN, +- PTL4_FN, PTL4_OUT, PTL4_IN_PU, PTL4_IN, +- PTL3_FN, PTL3_OUT, PTL3_IN_PU, PTL3_IN, +- PTL2_FN, PTL2_OUT, PTL2_IN_PU, PTL2_IN, +- PTL1_FN, PTL1_OUT, PTL1_IN_PU, PTL1_IN, +- PTL0_FN, PTL0_OUT, PTL0_IN_PU, PTL0_IN } ++ PTL7_FN, PTL7_OUT, 0, PTL7_IN, ++ PTL6_FN, PTL6_OUT, 0, PTL6_IN, ++ PTL5_FN, PTL5_OUT, 0, PTL5_IN, ++ PTL4_FN, PTL4_OUT, 0, PTL4_IN, ++ PTL3_FN, PTL3_OUT, 0, PTL3_IN, ++ PTL2_FN, PTL2_OUT, 0, PTL2_IN, ++ PTL1_FN, PTL1_OUT, 0, PTL1_IN, ++ PTL0_FN, PTL0_OUT, 0, PTL0_IN } + }, + { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) { +- PTM7_FN, PTM7_OUT, PTM7_IN_PU, PTM7_IN, +- PTM6_FN, PTM6_OUT, PTM6_IN_PU, PTM6_IN, +- PTM5_FN, PTM5_OUT, PTM5_IN_PU, PTM5_IN, +- PTM4_FN, PTM4_OUT, PTM4_IN_PU, PTM4_IN, +- PTM3_FN, PTM3_OUT, PTM3_IN_PU, PTM3_IN, +- PTM2_FN, PTM2_OUT, PTM2_IN_PU, PTM2_IN, +- PTM1_FN, PTM1_OUT, PTM1_IN_PU, PTM1_IN, +- PTM0_FN, PTM0_OUT, PTM0_IN_PU, PTM0_IN } ++ PTM7_FN, PTM7_OUT, 0, PTM7_IN, ++ PTM6_FN, PTM6_OUT, 0, PTM6_IN, ++ PTM5_FN, PTM5_OUT, 0, PTM5_IN, ++ PTM4_FN, PTM4_OUT, 0, PTM4_IN, ++ PTM3_FN, PTM3_OUT, 0, PTM3_IN, ++ PTM2_FN, PTM2_OUT, 0, PTM2_IN, ++ PTM1_FN, PTM1_OUT, 0, PTM1_IN, ++ PTM0_FN, PTM0_OUT, 0, PTM0_IN } + }, + { PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2) { +- PTN7_FN, PTN7_OUT, PTN7_IN_PU, PTN7_IN, +- PTN6_FN, PTN6_OUT, PTN6_IN_PU, PTN6_IN, +- PTN5_FN, PTN5_OUT, PTN5_IN_PU, PTN5_IN, +- PTN4_FN, PTN4_OUT, PTN4_IN_PU, PTN4_IN, +- PTN3_FN, PTN3_OUT, PTN3_IN_PU, PTN3_IN, +- PTN2_FN, PTN2_OUT, PTN2_IN_PU, PTN2_IN, +- PTN1_FN, PTN1_OUT, PTN1_IN_PU, PTN1_IN, +- PTN0_FN, PTN0_OUT, PTN0_IN_PU, PTN0_IN } ++ PTN7_FN, PTN7_OUT, 0, PTN7_IN, ++ PTN6_FN, PTN6_OUT, 0, PTN6_IN, ++ PTN5_FN, PTN5_OUT, 0, PTN5_IN, ++ PTN4_FN, PTN4_OUT, 0, PTN4_IN, ++ PTN3_FN, PTN3_OUT, 0, PTN3_IN, ++ PTN2_FN, PTN2_OUT, 0, PTN2_IN, ++ PTN1_FN, PTN1_OUT, 0, PTN1_IN, ++ PTN0_FN, PTN0_OUT, 0, PTN0_IN } + }, + { PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2) { +- PTQ7_FN, PTQ7_OUT, PTQ7_IN_PU, PTQ7_IN, +- PTQ6_FN, PTQ6_OUT, PTQ6_IN_PU, PTQ6_IN, +- PTQ5_FN, PTQ5_OUT, PTQ5_IN_PU, PTQ5_IN, +- PTQ4_FN, PTQ4_OUT, PTQ4_IN_PU, PTQ4_IN, +- PTQ3_FN, PTQ3_OUT, PTQ3_IN_PU, PTQ3_IN, +- PTQ2_FN, PTQ2_OUT, PTQ2_IN_PU, PTQ2_IN, +- PTQ1_FN, PTQ1_OUT, PTQ1_IN_PU, PTQ1_IN, +- PTQ0_FN, PTQ0_OUT, PTQ0_IN_PU, PTQ0_IN } ++ PTQ7_FN, PTQ7_OUT, 0, PTQ7_IN, ++ PTQ6_FN, PTQ6_OUT, 0, PTQ6_IN, ++ PTQ5_FN, PTQ5_OUT, 0, PTQ5_IN, ++ PTQ4_FN, PTQ4_OUT, 0, PTQ4_IN, ++ PTQ3_FN, PTQ3_OUT, 0, PTQ3_IN, ++ PTQ2_FN, PTQ2_OUT, 0, PTQ2_IN, ++ PTQ1_FN, PTQ1_OUT, 0, PTQ1_IN, ++ PTQ0_FN, PTQ0_OUT, 0, PTQ0_IN } + }, + { PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2) { +- PTR7_FN, PTR7_OUT, PTR7_IN_PU, PTR7_IN, +- PTR6_FN, PTR6_OUT, PTR6_IN_PU, PTR6_IN, +- PTR5_FN, PTR5_OUT, PTR5_IN_PU, PTR5_IN, +- PTR4_FN, PTR4_OUT, PTR4_IN_PU, PTR4_IN, +- PTR3_FN, 0, PTR3_IN_PU, PTR3_IN, +- PTR2_FN, 0, PTR2_IN_PU, PTR2_IN, +- PTR1_FN, PTR1_OUT, PTR1_IN_PU, PTR1_IN, +- PTR0_FN, PTR0_OUT, PTR0_IN_PU, PTR0_IN } ++ PTR7_FN, PTR7_OUT, 0, PTR7_IN, ++ PTR6_FN, PTR6_OUT, 0, PTR6_IN, ++ PTR5_FN, PTR5_OUT, 0, PTR5_IN, ++ PTR4_FN, PTR4_OUT, 0, PTR4_IN, ++ PTR3_FN, 0, 0, PTR3_IN, ++ PTR2_FN, 0, 0, PTR2_IN, ++ PTR1_FN, PTR1_OUT, 0, PTR1_IN, ++ PTR0_FN, PTR0_OUT, 0, PTR0_IN } + }, + { PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2) { + 0, 0, 0, 0, +- PTS6_FN, PTS6_OUT, PTS6_IN_PU, PTS6_IN, +- PTS5_FN, PTS5_OUT, PTS5_IN_PU, PTS5_IN, +- PTS4_FN, PTS4_OUT, PTS4_IN_PU, PTS4_IN, +- PTS3_FN, PTS3_OUT, PTS3_IN_PU, PTS3_IN, +- PTS2_FN, PTS2_OUT, PTS2_IN_PU, PTS2_IN, +- PTS1_FN, PTS1_OUT, PTS1_IN_PU, PTS1_IN, +- PTS0_FN, PTS0_OUT, PTS0_IN_PU, PTS0_IN } ++ PTS6_FN, PTS6_OUT, 0, PTS6_IN, ++ PTS5_FN, PTS5_OUT, 0, PTS5_IN, ++ PTS4_FN, PTS4_OUT, 0, PTS4_IN, ++ PTS3_FN, PTS3_OUT, 0, PTS3_IN, ++ PTS2_FN, PTS2_OUT, 0, PTS2_IN, ++ PTS1_FN, PTS1_OUT, 0, PTS1_IN, ++ PTS0_FN, PTS0_OUT, 0, PTS0_IN } + }, + { PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2) { +- PTT7_FN, PTT7_OUT, PTT7_IN_PU, PTT7_IN, +- PTT6_FN, PTT6_OUT, PTT6_IN_PU, PTT6_IN, +- PTT5_FN, PTT5_OUT, PTT5_IN_PU, PTT5_IN, +- PTT4_FN, PTT4_OUT, PTT4_IN_PU, PTT4_IN, +- PTT3_FN, PTT3_OUT, PTT3_IN_PU, PTT3_IN, +- PTT2_FN, PTT2_OUT, PTT2_IN_PU, PTT2_IN, +- PTT1_FN, PTT1_OUT, PTT1_IN_PU, PTT1_IN, +- PTT0_FN, PTT0_OUT, PTT0_IN_PU, PTT0_IN } ++ PTT7_FN, PTT7_OUT, 0, PTT7_IN, ++ PTT6_FN, PTT6_OUT, 0, PTT6_IN, ++ PTT5_FN, PTT5_OUT, 0, PTT5_IN, ++ PTT4_FN, PTT4_OUT, 0, PTT4_IN, ++ PTT3_FN, PTT3_OUT, 0, PTT3_IN, ++ PTT2_FN, PTT2_OUT, 0, PTT2_IN, ++ PTT1_FN, PTT1_OUT, 0, PTT1_IN, ++ PTT0_FN, PTT0_OUT, 0, PTT0_IN } + }, + { PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2) { +- PTU7_FN, PTU7_OUT, PTU7_IN_PU, PTU7_IN, +- PTU6_FN, PTU6_OUT, PTU6_IN_PU, PTU6_IN, +- PTU5_FN, PTU5_OUT, PTU5_IN_PU, PTU5_IN, +- PTU4_FN, PTU4_OUT, PTU4_IN_PU, PTU4_IN, +- PTU3_FN, PTU3_OUT, PTU3_IN_PU, PTU3_IN, +- PTU2_FN, PTU2_OUT, PTU2_IN_PU, PTU2_IN, +- PTU1_FN, PTU1_OUT, PTU1_IN_PU, PTU1_IN, +- PTU0_FN, PTU0_OUT, PTU0_IN_PU, PTU0_IN } ++ PTU7_FN, PTU7_OUT, 0, PTU7_IN, ++ PTU6_FN, PTU6_OUT, 0, PTU6_IN, ++ PTU5_FN, PTU5_OUT, 0, PTU5_IN, ++ PTU4_FN, PTU4_OUT, 0, PTU4_IN, ++ PTU3_FN, PTU3_OUT, 0, PTU3_IN, ++ PTU2_FN, PTU2_OUT, 0, PTU2_IN, ++ PTU1_FN, PTU1_OUT, 0, PTU1_IN, ++ PTU0_FN, PTU0_OUT, 0, PTU0_IN } + }, + { PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2) { +- PTV7_FN, PTV7_OUT, PTV7_IN_PU, PTV7_IN, +- PTV6_FN, PTV6_OUT, PTV6_IN_PU, PTV6_IN, +- PTV5_FN, PTV5_OUT, PTV5_IN_PU, PTV5_IN, +- PTV4_FN, PTV4_OUT, PTV4_IN_PU, PTV4_IN, +- PTV3_FN, PTV3_OUT, PTV3_IN_PU, PTV3_IN, +- PTV2_FN, PTV2_OUT, PTV2_IN_PU, PTV2_IN, +- PTV1_FN, PTV1_OUT, PTV1_IN_PU, PTV1_IN, +- PTV0_FN, PTV0_OUT, PTV0_IN_PU, PTV0_IN } ++ PTV7_FN, PTV7_OUT, 0, PTV7_IN, ++ PTV6_FN, PTV6_OUT, 0, PTV6_IN, ++ PTV5_FN, PTV5_OUT, 0, PTV5_IN, ++ PTV4_FN, PTV4_OUT, 0, PTV4_IN, ++ PTV3_FN, PTV3_OUT, 0, PTV3_IN, ++ PTV2_FN, PTV2_OUT, 0, PTV2_IN, ++ PTV1_FN, PTV1_OUT, 0, PTV1_IN, ++ PTV0_FN, PTV0_OUT, 0, PTV0_IN } + }, + { PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2) { +- PTW7_FN, PTW7_OUT, PTW7_IN_PU, PTW7_IN, +- PTW6_FN, PTW6_OUT, PTW6_IN_PU, PTW6_IN, +- PTW5_FN, PTW5_OUT, PTW5_IN_PU, PTW5_IN, +- PTW4_FN, PTW4_OUT, PTW4_IN_PU, PTW4_IN, +- PTW3_FN, PTW3_OUT, PTW3_IN_PU, PTW3_IN, +- PTW2_FN, PTW2_OUT, PTW2_IN_PU, PTW2_IN, +- PTW1_FN, PTW1_OUT, PTW1_IN_PU, PTW1_IN, +- PTW0_FN, PTW0_OUT, PTW0_IN_PU, PTW0_IN } ++ PTW7_FN, PTW7_OUT, 0, PTW7_IN, ++ PTW6_FN, PTW6_OUT, 0, PTW6_IN, ++ PTW5_FN, PTW5_OUT, 0, PTW5_IN, ++ PTW4_FN, PTW4_OUT, 0, PTW4_IN, ++ PTW3_FN, PTW3_OUT, 0, PTW3_IN, ++ PTW2_FN, PTW2_OUT, 0, PTW2_IN, ++ PTW1_FN, PTW1_OUT, 0, PTW1_IN, ++ PTW0_FN, PTW0_OUT, 0, PTW0_IN } + }, + { PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2) { +- PTX7_FN, PTX7_OUT, PTX7_IN_PU, PTX7_IN, +- PTX6_FN, PTX6_OUT, PTX6_IN_PU, PTX6_IN, +- PTX5_FN, PTX5_OUT, PTX5_IN_PU, PTX5_IN, +- PTX4_FN, PTX4_OUT, PTX4_IN_PU, PTX4_IN, +- PTX3_FN, PTX3_OUT, PTX3_IN_PU, PTX3_IN, +- PTX2_FN, PTX2_OUT, PTX2_IN_PU, PTX2_IN, +- PTX1_FN, PTX1_OUT, PTX1_IN_PU, PTX1_IN, +- PTX0_FN, PTX0_OUT, PTX0_IN_PU, PTX0_IN } ++ PTX7_FN, PTX7_OUT, 0, PTX7_IN, ++ PTX6_FN, PTX6_OUT, 0, PTX6_IN, ++ PTX5_FN, PTX5_OUT, 0, PTX5_IN, ++ PTX4_FN, PTX4_OUT, 0, PTX4_IN, ++ PTX3_FN, PTX3_OUT, 0, PTX3_IN, ++ PTX2_FN, PTX2_OUT, 0, PTX2_IN, ++ PTX1_FN, PTX1_OUT, 0, PTX1_IN, ++ PTX0_FN, PTX0_OUT, 0, PTX0_IN } + }, + { PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2) { +- PTY7_FN, PTY7_OUT, PTY7_IN_PU, PTY7_IN, +- PTY6_FN, PTY6_OUT, PTY6_IN_PU, PTY6_IN, +- PTY5_FN, PTY5_OUT, PTY5_IN_PU, PTY5_IN, +- PTY4_FN, PTY4_OUT, PTY4_IN_PU, PTY4_IN, +- PTY3_FN, PTY3_OUT, PTY3_IN_PU, PTY3_IN, +- PTY2_FN, PTY2_OUT, PTY2_IN_PU, PTY2_IN, +- PTY1_FN, PTY1_OUT, PTY1_IN_PU, PTY1_IN, +- PTY0_FN, PTY0_OUT, PTY0_IN_PU, PTY0_IN } ++ PTY7_FN, PTY7_OUT, 0, PTY7_IN, ++ PTY6_FN, PTY6_OUT, 0, PTY6_IN, ++ PTY5_FN, PTY5_OUT, 0, PTY5_IN, ++ PTY4_FN, PTY4_OUT, 0, PTY4_IN, ++ PTY3_FN, PTY3_OUT, 0, PTY3_IN, ++ PTY2_FN, PTY2_OUT, 0, PTY2_IN, ++ PTY1_FN, PTY1_OUT, 0, PTY1_IN, ++ PTY0_FN, PTY0_OUT, 0, PTY0_IN } + }, + { PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2) { +- PTZ7_FN, PTZ7_OUT, PTZ7_IN_PU, PTZ7_IN, +- PTZ6_FN, PTZ6_OUT, PTZ6_IN_PU, PTZ6_IN, +- PTZ5_FN, PTZ5_OUT, PTZ5_IN_PU, PTZ5_IN, +- PTZ4_FN, PTZ4_OUT, PTZ4_IN_PU, PTZ4_IN, +- PTZ3_FN, PTZ3_OUT, PTZ3_IN_PU, PTZ3_IN, +- PTZ2_FN, PTZ2_OUT, PTZ2_IN_PU, PTZ2_IN, +- PTZ1_FN, PTZ1_OUT, PTZ1_IN_PU, PTZ1_IN, +- PTZ0_FN, PTZ0_OUT, PTZ0_IN_PU, PTZ0_IN } ++ PTZ7_FN, PTZ7_OUT, 0, PTZ7_IN, ++ PTZ6_FN, PTZ6_OUT, 0, PTZ6_IN, ++ PTZ5_FN, PTZ5_OUT, 0, PTZ5_IN, ++ PTZ4_FN, PTZ4_OUT, 0, PTZ4_IN, ++ PTZ3_FN, PTZ3_OUT, 0, PTZ3_IN, ++ PTZ2_FN, PTZ2_OUT, 0, PTZ2_IN, ++ PTZ1_FN, PTZ1_OUT, 0, PTZ1_IN, ++ PTZ0_FN, PTZ0_OUT, 0, PTZ0_IN } + }, + { PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 1) { + PSA15_0, PSA15_1, +@@ -2210,7 +2164,6 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { + const struct sh_pfc_soc_info sh7724_pinmux_info = { + .name = "sh7724_pfc", + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, +- .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0532-sh-pfc-sh7757-Remove-unused-input_pu-range.patch b/patches.renesas/0532-sh-pfc-sh7757-Remove-unused-input_pu-range.patch new file mode 100644 index 00000000000..c4a649c9c90 --- /dev/null +++ b/patches.renesas/0532-sh-pfc-sh7757-Remove-unused-input_pu-range.patch @@ -0,0 +1,411 @@ +From 2fc345b3b8a83f8853ab1048db7259ab90b4d083 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 16 Jul 2013 01:54:13 +0200 +Subject: sh-pfc: sh7757: Remove unused input_pu range + +The PFC SH7757 SoC data contains a input_pu range used to configure +pull-up resistors using the legacy non-pinconf API. That API has been +removed from the driver, the range is thus not used anymore. Remove it. + +If required, configuring pull-up resistors for the SH7757 can be +implemented using the pinconf API, as done for the SH-Mobile, R-Mobile +and R-Car platforms. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit 5f86072afb29519deb3f14bee52ccc6e3f997991) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-sh7757.c | 299 ++++++++++++++++-------------------- + 1 file changed, 129 insertions(+), 170 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7757.c b/drivers/pinctrl/sh-pfc/pfc-sh7757.c +index e074230e..d974b085 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7757.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7757.c +@@ -132,46 +132,6 @@ enum { + PTZ3_IN, PTZ2_IN, PTZ1_IN, PTZ0_IN, + PINMUX_INPUT_END, + +- PINMUX_INPUT_PULLUP_BEGIN, +- PTA7_IN_PU, PTA6_IN_PU, PTA5_IN_PU, PTA4_IN_PU, +- PTA3_IN_PU, PTA2_IN_PU, PTA1_IN_PU, PTA0_IN_PU, +- PTD7_IN_PU, PTD6_IN_PU, PTD5_IN_PU, PTD4_IN_PU, +- PTD3_IN_PU, PTD2_IN_PU, PTD1_IN_PU, PTD0_IN_PU, +- PTE7_IN_PU, PTE6_IN_PU, PTE5_IN_PU, PTE4_IN_PU, +- PTE3_IN_PU, PTE2_IN_PU, PTE1_IN_PU, PTE0_IN_PU, +- PTF7_IN_PU, PTF6_IN_PU, PTF5_IN_PU, PTF4_IN_PU, +- PTF3_IN_PU, PTF2_IN_PU, PTF1_IN_PU, PTF0_IN_PU, +- PTG7_IN_PU, PTG6_IN_PU, PTG4_IN_PU, +- PTH7_IN_PU, PTH6_IN_PU, PTH5_IN_PU, PTH4_IN_PU, +- PTH3_IN_PU, PTH2_IN_PU, PTH1_IN_PU, PTH0_IN_PU, +- PTI7_IN_PU, PTI6_IN_PU, PTI4_IN_PU, +- PTI3_IN_PU, PTI2_IN_PU, PTI1_IN_PU, PTI0_IN_PU, +- PTJ6_IN_PU, PTJ5_IN_PU, PTJ4_IN_PU, +- PTJ3_IN_PU, PTJ2_IN_PU, PTJ1_IN_PU, PTJ0_IN_PU, +- PTK7_IN_PU, PTK6_IN_PU, PTK5_IN_PU, PTK4_IN_PU, +- PTK3_IN_PU, PTK2_IN_PU, PTK1_IN_PU, PTK0_IN_PU, +- PTL6_IN_PU, PTL5_IN_PU, PTL4_IN_PU, +- PTL3_IN_PU, PTL2_IN_PU, PTL1_IN_PU, PTL0_IN_PU, +- PTM7_IN_PU, PTM6_IN_PU, PTM5_IN_PU, PTM4_IN_PU, +- PTN4_IN_PU, +- PTN3_IN_PU, PTN2_IN_PU, PTN1_IN_PU, PTN0_IN_PU, +- PTO7_IN_PU, PTO6_IN_PU, PTO5_IN_PU, PTO4_IN_PU, +- PTO3_IN_PU, PTO2_IN_PU, PTO1_IN_PU, PTO0_IN_PU, +- PTT7_IN_PU, PTT6_IN_PU, PTT5_IN_PU, PTT4_IN_PU, +- PTT3_IN_PU, PTT2_IN_PU, PTT1_IN_PU, PTT0_IN_PU, +- PTU7_IN_PU, PTU6_IN_PU, PTU5_IN_PU, PTU4_IN_PU, +- PTU3_IN_PU, PTU2_IN_PU, PTU1_IN_PU, PTU0_IN_PU, +- PTV7_IN_PU, PTV6_IN_PU, PTV5_IN_PU, PTV4_IN_PU, +- PTV3_IN_PU, PTV2_IN_PU, +- PTW1_IN_PU, PTW0_IN_PU, +- PTX7_IN_PU, PTX6_IN_PU, PTX5_IN_PU, PTX4_IN_PU, +- PTX3_IN_PU, PTX2_IN_PU, PTX1_IN_PU, PTX0_IN_PU, +- PTY7_IN_PU, PTY6_IN_PU, PTY5_IN_PU, PTY4_IN_PU, +- PTY3_IN_PU, PTY2_IN_PU, PTY1_IN_PU, PTY0_IN_PU, +- PTZ7_IN_PU, PTZ6_IN_PU, PTZ5_IN_PU, PTZ4_IN_PU, +- PTZ3_IN_PU, PTZ2_IN_PU, PTZ1_IN_PU, PTZ0_IN_PU, +- PINMUX_INPUT_PULLUP_END, +- + PINMUX_OUTPUT_BEGIN, + PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT, + PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT, +@@ -1728,14 +1688,14 @@ static const struct pinmux_func pinmux_func_gpios[] = { + + static const struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("PACR", 0xffec0000, 16, 2) { +- PTA7_FN, PTA7_OUT, PTA7_IN, PTA7_IN_PU, +- PTA6_FN, PTA6_OUT, PTA6_IN, PTA6_IN_PU, +- PTA5_FN, PTA5_OUT, PTA5_IN, PTA5_IN_PU, +- PTA4_FN, PTA4_OUT, PTA4_IN, PTA4_IN_PU, +- PTA3_FN, PTA3_OUT, PTA3_IN, PTA3_IN_PU, +- PTA2_FN, PTA2_OUT, PTA2_IN, PTA2_IN_PU, +- PTA1_FN, PTA1_OUT, PTA1_IN, PTA1_IN_PU, +- PTA0_FN, PTA0_OUT, PTA0_IN, PTA0_IN_PU } ++ PTA7_FN, PTA7_OUT, PTA7_IN, 0, ++ PTA6_FN, PTA6_OUT, PTA6_IN, 0, ++ PTA5_FN, PTA5_OUT, PTA5_IN, 0, ++ PTA4_FN, PTA4_OUT, PTA4_IN, 0, ++ PTA3_FN, PTA3_OUT, PTA3_IN, 0, ++ PTA2_FN, PTA2_OUT, PTA2_IN, 0, ++ PTA1_FN, PTA1_OUT, PTA1_IN, 0, ++ PTA0_FN, PTA0_OUT, PTA0_IN, 0 } + }, + { PINMUX_CFG_REG("PBCR", 0xffec0002, 16, 2) { + PTB7_FN, PTB7_OUT, PTB7_IN, 0, +@@ -1758,100 +1718,100 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + PTC0_FN, PTC0_OUT, PTC0_IN, 0 } + }, + { PINMUX_CFG_REG("PDCR", 0xffec0006, 16, 2) { +- PTD7_FN, PTD7_OUT, PTD7_IN, PTD7_IN_PU, +- PTD6_FN, PTD6_OUT, PTD6_IN, PTD6_IN_PU, +- PTD5_FN, PTD5_OUT, PTD5_IN, PTD5_IN_PU, +- PTD4_FN, PTD4_OUT, PTD4_IN, PTD4_IN_PU, +- PTD3_FN, PTD3_OUT, PTD3_IN, PTD3_IN_PU, +- PTD2_FN, PTD2_OUT, PTD2_IN, PTD2_IN_PU, +- PTD1_FN, PTD1_OUT, PTD1_IN, PTD1_IN_PU, +- PTD0_FN, PTD0_OUT, PTD0_IN, PTD0_IN_PU } ++ PTD7_FN, PTD7_OUT, PTD7_IN, 0, ++ PTD6_FN, PTD6_OUT, PTD6_IN, 0, ++ PTD5_FN, PTD5_OUT, PTD5_IN, 0, ++ PTD4_FN, PTD4_OUT, PTD4_IN, 0, ++ PTD3_FN, PTD3_OUT, PTD3_IN, 0, ++ PTD2_FN, PTD2_OUT, PTD2_IN, 0, ++ PTD1_FN, PTD1_OUT, PTD1_IN, 0, ++ PTD0_FN, PTD0_OUT, PTD0_IN, 0 } + }, + { PINMUX_CFG_REG("PECR", 0xffec0008, 16, 2) { +- PTE7_FN, PTE7_OUT, PTE7_IN, PTE7_IN_PU, +- PTE6_FN, PTE6_OUT, PTE6_IN, PTE6_IN_PU, +- PTE5_FN, PTE5_OUT, PTE5_IN, PTE5_IN_PU, +- PTE4_FN, PTE4_OUT, PTE4_IN, PTE4_IN_PU, +- PTE3_FN, PTE3_OUT, PTE3_IN, PTE3_IN_PU, +- PTE2_FN, PTE2_OUT, PTE2_IN, PTE2_IN_PU, +- PTE1_FN, PTE1_OUT, PTE1_IN, PTE1_IN_PU, +- PTE0_FN, PTE0_OUT, PTE0_IN, PTE0_IN_PU } ++ PTE7_FN, PTE7_OUT, PTE7_IN, 0, ++ PTE6_FN, PTE6_OUT, PTE6_IN, 0, ++ PTE5_FN, PTE5_OUT, PTE5_IN, 0, ++ PTE4_FN, PTE4_OUT, PTE4_IN, 0, ++ PTE3_FN, PTE3_OUT, PTE3_IN, 0, ++ PTE2_FN, PTE2_OUT, PTE2_IN, 0, ++ PTE1_FN, PTE1_OUT, PTE1_IN, 0, ++ PTE0_FN, PTE0_OUT, PTE0_IN, 0 } + }, + { PINMUX_CFG_REG("PFCR", 0xffec000a, 16, 2) { +- PTF7_FN, PTF7_OUT, PTF7_IN, PTF7_IN_PU, +- PTF6_FN, PTF6_OUT, PTF6_IN, PTF6_IN_PU, +- PTF5_FN, PTF5_OUT, PTF5_IN, PTF5_IN_PU, +- PTF4_FN, PTF4_OUT, PTF4_IN, PTF4_IN_PU, +- PTF3_FN, PTF3_OUT, PTF3_IN, PTF3_IN_PU, +- PTF2_FN, PTF2_OUT, PTF2_IN, PTF2_IN_PU, +- PTF1_FN, PTF1_OUT, PTF1_IN, PTF1_IN_PU, +- PTF0_FN, PTF0_OUT, PTF0_IN, PTF0_IN_PU } ++ PTF7_FN, PTF7_OUT, PTF7_IN, 0, ++ PTF6_FN, PTF6_OUT, PTF6_IN, 0, ++ PTF5_FN, PTF5_OUT, PTF5_IN, 0, ++ PTF4_FN, PTF4_OUT, PTF4_IN, 0, ++ PTF3_FN, PTF3_OUT, PTF3_IN, 0, ++ PTF2_FN, PTF2_OUT, PTF2_IN, 0, ++ PTF1_FN, PTF1_OUT, PTF1_IN, 0, ++ PTF0_FN, PTF0_OUT, PTF0_IN, 0 } + }, + { PINMUX_CFG_REG("PGCR", 0xffec000c, 16, 2) { +- PTG7_FN, PTG7_OUT, PTG7_IN, PTG7_IN_PU , +- PTG6_FN, PTG6_OUT, PTG6_IN, PTG6_IN_PU , ++ PTG7_FN, PTG7_OUT, PTG7_IN, 0, ++ PTG6_FN, PTG6_OUT, PTG6_IN, 0, + PTG5_FN, PTG5_OUT, PTG5_IN, 0, +- PTG4_FN, PTG4_OUT, PTG4_IN, PTG4_IN_PU , ++ PTG4_FN, PTG4_OUT, PTG4_IN, 0, + PTG3_FN, PTG3_OUT, PTG3_IN, 0, + PTG2_FN, PTG2_OUT, PTG2_IN, 0, + PTG1_FN, PTG1_OUT, PTG1_IN, 0, + PTG0_FN, PTG0_OUT, PTG0_IN, 0 } + }, + { PINMUX_CFG_REG("PHCR", 0xffec000e, 16, 2) { +- PTH7_FN, PTH7_OUT, PTH7_IN, PTH7_IN_PU, +- PTH6_FN, PTH6_OUT, PTH6_IN, PTH6_IN_PU, +- PTH5_FN, PTH5_OUT, PTH5_IN, PTH5_IN_PU, +- PTH4_FN, PTH4_OUT, PTH4_IN, PTH4_IN_PU, +- PTH3_FN, PTH3_OUT, PTH3_IN, PTH3_IN_PU, +- PTH2_FN, PTH2_OUT, PTH2_IN, PTH2_IN_PU, +- PTH1_FN, PTH1_OUT, PTH1_IN, PTH1_IN_PU, +- PTH0_FN, PTH0_OUT, PTH0_IN, PTH0_IN_PU } ++ PTH7_FN, PTH7_OUT, PTH7_IN, 0, ++ PTH6_FN, PTH6_OUT, PTH6_IN, 0, ++ PTH5_FN, PTH5_OUT, PTH5_IN, 0, ++ PTH4_FN, PTH4_OUT, PTH4_IN, 0, ++ PTH3_FN, PTH3_OUT, PTH3_IN, 0, ++ PTH2_FN, PTH2_OUT, PTH2_IN, 0, ++ PTH1_FN, PTH1_OUT, PTH1_IN, 0, ++ PTH0_FN, PTH0_OUT, PTH0_IN, 0 } + }, + { PINMUX_CFG_REG("PICR", 0xffec0010, 16, 2) { +- PTI7_FN, PTI7_OUT, PTI7_IN, PTI7_IN_PU, +- PTI6_FN, PTI6_OUT, PTI6_IN, PTI6_IN_PU, ++ PTI7_FN, PTI7_OUT, PTI7_IN, 0, ++ PTI6_FN, PTI6_OUT, PTI6_IN, 0, + PTI5_FN, PTI5_OUT, PTI5_IN, 0, +- PTI4_FN, PTI4_OUT, PTI4_IN, PTI4_IN_PU, +- PTI3_FN, PTI3_OUT, PTI3_IN, PTI3_IN_PU, +- PTI2_FN, PTI2_OUT, PTI2_IN, PTI2_IN_PU, +- PTI1_FN, PTI1_OUT, PTI1_IN, PTI1_IN_PU, +- PTI0_FN, PTI0_OUT, PTI0_IN, PTI0_IN_PU } ++ PTI4_FN, PTI4_OUT, PTI4_IN, 0, ++ PTI3_FN, PTI3_OUT, PTI3_IN, 0, ++ PTI2_FN, PTI2_OUT, PTI2_IN, 0, ++ PTI1_FN, PTI1_OUT, PTI1_IN, 0, ++ PTI0_FN, PTI0_OUT, PTI0_IN, 0 } + }, + { PINMUX_CFG_REG("PJCR", 0xffec0012, 16, 2) { + 0, 0, 0, 0, /* reserved: always set 1 */ +- PTJ6_FN, PTJ6_OUT, PTJ6_IN, PTJ6_IN_PU, +- PTJ5_FN, PTJ5_OUT, PTJ5_IN, PTJ5_IN_PU, +- PTJ4_FN, PTJ4_OUT, PTJ4_IN, PTJ4_IN_PU, +- PTJ3_FN, PTJ3_OUT, PTJ3_IN, PTJ3_IN_PU, +- PTJ2_FN, PTJ2_OUT, PTJ2_IN, PTJ2_IN_PU, +- PTJ1_FN, PTJ1_OUT, PTJ1_IN, PTJ1_IN_PU, +- PTJ0_FN, PTJ0_OUT, PTJ0_IN, PTJ0_IN_PU } ++ PTJ6_FN, PTJ6_OUT, PTJ6_IN, 0, ++ PTJ5_FN, PTJ5_OUT, PTJ5_IN, 0, ++ PTJ4_FN, PTJ4_OUT, PTJ4_IN, 0, ++ PTJ3_FN, PTJ3_OUT, PTJ3_IN, 0, ++ PTJ2_FN, PTJ2_OUT, PTJ2_IN, 0, ++ PTJ1_FN, PTJ1_OUT, PTJ1_IN, 0, ++ PTJ0_FN, PTJ0_OUT, PTJ0_IN, 0 } + }, + { PINMUX_CFG_REG("PKCR", 0xffec0014, 16, 2) { +- PTK7_FN, PTK7_OUT, PTK7_IN, PTK7_IN_PU, +- PTK6_FN, PTK6_OUT, PTK6_IN, PTK6_IN_PU, +- PTK5_FN, PTK5_OUT, PTK5_IN, PTK5_IN_PU, +- PTK4_FN, PTK4_OUT, PTK4_IN, PTK4_IN_PU, +- PTK3_FN, PTK3_OUT, PTK3_IN, PTK3_IN_PU, +- PTK2_FN, PTK2_OUT, PTK2_IN, PTK2_IN_PU, +- PTK1_FN, PTK1_OUT, PTK1_IN, PTK1_IN_PU, +- PTK0_FN, PTK0_OUT, PTK0_IN, PTK0_IN_PU } ++ PTK7_FN, PTK7_OUT, PTK7_IN, 0, ++ PTK6_FN, PTK6_OUT, PTK6_IN, 0, ++ PTK5_FN, PTK5_OUT, PTK5_IN, 0, ++ PTK4_FN, PTK4_OUT, PTK4_IN, 0, ++ PTK3_FN, PTK3_OUT, PTK3_IN, 0, ++ PTK2_FN, PTK2_OUT, PTK2_IN, 0, ++ PTK1_FN, PTK1_OUT, PTK1_IN, 0, ++ PTK0_FN, PTK0_OUT, PTK0_IN, 0 } + }, + { PINMUX_CFG_REG("PLCR", 0xffec0016, 16, 2) { + 0, 0, 0, 0, /* reserved: always set 1 */ +- PTL6_FN, PTL6_OUT, PTL6_IN, PTL6_IN_PU, +- PTL5_FN, PTL5_OUT, PTL5_IN, PTL5_IN_PU, +- PTL4_FN, PTL4_OUT, PTL4_IN, PTL4_IN_PU, +- PTL3_FN, PTL3_OUT, PTL3_IN, PTL3_IN_PU, +- PTL2_FN, PTL2_OUT, PTL2_IN, PTL2_IN_PU, +- PTL1_FN, PTL1_OUT, PTL1_IN, PTL1_IN_PU, +- PTL0_FN, PTL0_OUT, PTL0_IN, PTL0_IN_PU } ++ PTL6_FN, PTL6_OUT, PTL6_IN, 0, ++ PTL5_FN, PTL5_OUT, PTL5_IN, 0, ++ PTL4_FN, PTL4_OUT, PTL4_IN, 0, ++ PTL3_FN, PTL3_OUT, PTL3_IN, 0, ++ PTL2_FN, PTL2_OUT, PTL2_IN, 0, ++ PTL1_FN, PTL1_OUT, PTL1_IN, 0, ++ PTL0_FN, PTL0_OUT, PTL0_IN, 0 } + }, + { PINMUX_CFG_REG("PMCR", 0xffec0018, 16, 2) { +- PTM7_FN, PTM7_OUT, PTM7_IN, PTM7_IN_PU, +- PTM6_FN, PTM6_OUT, PTM6_IN, PTM6_IN_PU, +- PTM5_FN, PTM5_OUT, PTM5_IN, PTM5_IN_PU, +- PTM4_FN, PTM4_OUT, PTM4_IN, PTM4_IN_PU, ++ PTM7_FN, PTM7_OUT, PTM7_IN, 0, ++ PTM6_FN, PTM6_OUT, PTM6_IN, 0, ++ PTM5_FN, PTM5_OUT, PTM5_IN, 0, ++ PTM4_FN, PTM4_OUT, PTM4_IN, 0, + PTM3_FN, PTM3_OUT, PTM3_IN, 0, + PTM2_FN, PTM2_OUT, PTM2_IN, 0, + PTM1_FN, PTM1_OUT, PTM1_IN, 0, +@@ -1861,21 +1821,21 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + 0, 0, 0, 0, /* reserved: always set 1 */ + PTN6_FN, PTN6_OUT, PTN6_IN, 0, + PTN5_FN, PTN5_OUT, PTN5_IN, 0, +- PTN4_FN, PTN4_OUT, PTN4_IN, PTN4_IN_PU, +- PTN3_FN, PTN3_OUT, PTN3_IN, PTN3_IN_PU, +- PTN2_FN, PTN2_OUT, PTN2_IN, PTN2_IN_PU, +- PTN1_FN, PTN1_OUT, PTN1_IN, PTN1_IN_PU, +- PTN0_FN, PTN0_OUT, PTN0_IN, PTN0_IN_PU } ++ PTN4_FN, PTN4_OUT, PTN4_IN, 0, ++ PTN3_FN, PTN3_OUT, PTN3_IN, 0, ++ PTN2_FN, PTN2_OUT, PTN2_IN, 0, ++ PTN1_FN, PTN1_OUT, PTN1_IN, 0, ++ PTN0_FN, PTN0_OUT, PTN0_IN, 0 } + }, + { PINMUX_CFG_REG("POCR", 0xffec001c, 16, 2) { +- PTO7_FN, PTO7_OUT, PTO7_IN, PTO7_IN_PU, +- PTO6_FN, PTO6_OUT, PTO6_IN, PTO6_IN_PU, +- PTO5_FN, PTO5_OUT, PTO5_IN, PTO5_IN_PU, +- PTO4_FN, PTO4_OUT, PTO4_IN, PTO4_IN_PU, +- PTO3_FN, PTO3_OUT, PTO3_IN, PTO3_IN_PU, +- PTO2_FN, PTO2_OUT, PTO2_IN, PTO2_IN_PU, +- PTO1_FN, PTO1_OUT, PTO1_IN, PTO1_IN_PU, +- PTO0_FN, PTO0_OUT, PTO0_IN, PTO0_IN_PU } ++ PTO7_FN, PTO7_OUT, PTO7_IN, 0, ++ PTO6_FN, PTO6_OUT, PTO6_IN, 0, ++ PTO5_FN, PTO5_OUT, PTO5_IN, 0, ++ PTO4_FN, PTO4_OUT, PTO4_IN, 0, ++ PTO3_FN, PTO3_OUT, PTO3_IN, 0, ++ PTO2_FN, PTO2_OUT, PTO2_IN, 0, ++ PTO1_FN, PTO1_OUT, PTO1_IN, 0, ++ PTO0_FN, PTO0_OUT, PTO0_IN, 0 } + }, + #if 0 /* FIXME: Remove it? */ + { PINMUX_CFG_REG("PPCR", 0xffec001e, 16, 2) { +@@ -1920,32 +1880,32 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + PTS0_FN, PTS0_OUT, PTS0_IN, 0 } + }, + { PINMUX_CFG_REG("PTCR", 0xffec0026, 16, 2) { +- PTT7_FN, PTT7_OUT, PTT7_IN, PTO7_IN_PU, +- PTT6_FN, PTT6_OUT, PTT6_IN, PTO6_IN_PU, +- PTT5_FN, PTT5_OUT, PTT5_IN, PTO5_IN_PU, +- PTT4_FN, PTT4_OUT, PTT4_IN, PTO4_IN_PU, +- PTT3_FN, PTT3_OUT, PTT3_IN, PTO3_IN_PU, +- PTT2_FN, PTT2_OUT, PTT2_IN, PTO2_IN_PU, +- PTT1_FN, PTT1_OUT, PTT1_IN, PTO1_IN_PU, +- PTT0_FN, PTT0_OUT, PTT0_IN, PTO0_IN_PU } ++ PTT7_FN, PTT7_OUT, PTT7_IN, 0, ++ PTT6_FN, PTT6_OUT, PTT6_IN, 0, ++ PTT5_FN, PTT5_OUT, PTT5_IN, 0, ++ PTT4_FN, PTT4_OUT, PTT4_IN, 0, ++ PTT3_FN, PTT3_OUT, PTT3_IN, 0, ++ PTT2_FN, PTT2_OUT, PTT2_IN, 0, ++ PTT1_FN, PTT1_OUT, PTT1_IN, 0, ++ PTT0_FN, PTT0_OUT, PTT0_IN, 0 } + }, + { PINMUX_CFG_REG("PUCR", 0xffec0028, 16, 2) { +- PTU7_FN, PTU7_OUT, PTU7_IN, PTU7_IN_PU, +- PTU6_FN, PTU6_OUT, PTU6_IN, PTU6_IN_PU, +- PTU5_FN, PTU5_OUT, PTU5_IN, PTU5_IN_PU, +- PTU4_FN, PTU4_OUT, PTU4_IN, PTU4_IN_PU, +- PTU3_FN, PTU3_OUT, PTU3_IN, PTU3_IN_PU, +- PTU2_FN, PTU2_OUT, PTU2_IN, PTU2_IN_PU, +- PTU1_FN, PTU1_OUT, PTU1_IN, PTU1_IN_PU, +- PTU0_FN, PTU0_OUT, PTU0_IN, PTU0_IN_PU } ++ PTU7_FN, PTU7_OUT, PTU7_IN, 0, ++ PTU6_FN, PTU6_OUT, PTU6_IN, 0, ++ PTU5_FN, PTU5_OUT, PTU5_IN, 0, ++ PTU4_FN, PTU4_OUT, PTU4_IN, 0, ++ PTU3_FN, PTU3_OUT, PTU3_IN, 0, ++ PTU2_FN, PTU2_OUT, PTU2_IN, 0, ++ PTU1_FN, PTU1_OUT, PTU1_IN, 0, ++ PTU0_FN, PTU0_OUT, PTU0_IN, 0 } + }, + { PINMUX_CFG_REG("PVCR", 0xffec002a, 16, 2) { +- PTV7_FN, PTV7_OUT, PTV7_IN, PTV7_IN_PU, +- PTV6_FN, PTV6_OUT, PTV6_IN, PTV6_IN_PU, +- PTV5_FN, PTV5_OUT, PTV5_IN, PTV5_IN_PU, +- PTV4_FN, PTV4_OUT, PTV4_IN, PTV4_IN_PU, +- PTV3_FN, PTV3_OUT, PTV3_IN, PTV3_IN_PU, +- PTV2_FN, PTV2_OUT, PTV2_IN, PTV2_IN_PU, ++ PTV7_FN, PTV7_OUT, PTV7_IN, 0, ++ PTV6_FN, PTV6_OUT, PTV6_IN, 0, ++ PTV5_FN, PTV5_OUT, PTV5_IN, 0, ++ PTV4_FN, PTV4_OUT, PTV4_IN, 0, ++ PTV3_FN, PTV3_OUT, PTV3_IN, 0, ++ PTV2_FN, PTV2_OUT, PTV2_IN, 0, + PTV1_FN, PTV1_OUT, PTV1_IN, 0, + PTV0_FN, PTV0_OUT, PTV0_IN, 0 } + }, +@@ -1956,28 +1916,28 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + PTW4_FN, PTW4_OUT, PTW4_IN, 0, + PTW3_FN, PTW3_OUT, PTW3_IN, 0, + PTW2_FN, PTW2_OUT, PTW2_IN, 0, +- PTW1_FN, PTW1_OUT, PTW1_IN, PTW1_IN_PU, +- PTW0_FN, PTW0_OUT, PTW0_IN, PTW0_IN_PU } ++ PTW1_FN, PTW1_OUT, PTW1_IN, 0, ++ PTW0_FN, PTW0_OUT, PTW0_IN, 0 } + }, + { PINMUX_CFG_REG("PXCR", 0xffec002e, 16, 2) { +- PTX7_FN, PTX7_OUT, PTX7_IN, PTX7_IN_PU, +- PTX6_FN, PTX6_OUT, PTX6_IN, PTX6_IN_PU, +- PTX5_FN, PTX5_OUT, PTX5_IN, PTX5_IN_PU, +- PTX4_FN, PTX4_OUT, PTX4_IN, PTX4_IN_PU, +- PTX3_FN, PTX3_OUT, PTX3_IN, PTX3_IN_PU, +- PTX2_FN, PTX2_OUT, PTX2_IN, PTX2_IN_PU, +- PTX1_FN, PTX1_OUT, PTX1_IN, PTX1_IN_PU, +- PTX0_FN, PTX0_OUT, PTX0_IN, PTX0_IN_PU } ++ PTX7_FN, PTX7_OUT, PTX7_IN, 0, ++ PTX6_FN, PTX6_OUT, PTX6_IN, 0, ++ PTX5_FN, PTX5_OUT, PTX5_IN, 0, ++ PTX4_FN, PTX4_OUT, PTX4_IN, 0, ++ PTX3_FN, PTX3_OUT, PTX3_IN, 0, ++ PTX2_FN, PTX2_OUT, PTX2_IN, 0, ++ PTX1_FN, PTX1_OUT, PTX1_IN, 0, ++ PTX0_FN, PTX0_OUT, PTX0_IN, 0 } + }, + { PINMUX_CFG_REG("PYCR", 0xffec0030, 16, 2) { +- PTY7_FN, PTY7_OUT, PTY7_IN, PTY7_IN_PU, +- PTY6_FN, PTY6_OUT, PTY6_IN, PTY6_IN_PU, +- PTY5_FN, PTY5_OUT, PTY5_IN, PTY5_IN_PU, +- PTY4_FN, PTY4_OUT, PTY4_IN, PTY4_IN_PU, +- PTY3_FN, PTY3_OUT, PTY3_IN, PTY3_IN_PU, +- PTY2_FN, PTY2_OUT, PTY2_IN, PTY2_IN_PU, +- PTY1_FN, PTY1_OUT, PTY1_IN, PTY1_IN_PU, +- PTY0_FN, PTY0_OUT, PTY0_IN, PTY0_IN_PU } ++ PTY7_FN, PTY7_OUT, PTY7_IN, 0, ++ PTY6_FN, PTY6_OUT, PTY6_IN, 0, ++ PTY5_FN, PTY5_OUT, PTY5_IN, 0, ++ PTY4_FN, PTY4_OUT, PTY4_IN, 0, ++ PTY3_FN, PTY3_OUT, PTY3_IN, 0, ++ PTY2_FN, PTY2_OUT, PTY2_IN, 0, ++ PTY1_FN, PTY1_OUT, PTY1_IN, 0, ++ PTY0_FN, PTY0_OUT, PTY0_IN, 0 } + }, + { PINMUX_CFG_REG("PZCR", 0xffec0032, 16, 2) { + PTZ7_FN, PTZ7_OUT, PTZ7_IN, 0, +@@ -2267,7 +2227,6 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { + const struct sh_pfc_soc_info sh7757_pinmux_info = { + .name = "sh7757_pfc", + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, +- .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0533-sh-pfc-sh7785-Remove-unused-input_pu-range.patch b/patches.renesas/0533-sh-pfc-sh7785-Remove-unused-input_pu-range.patch new file mode 100644 index 00000000000..a474b7da051 --- /dev/null +++ b/patches.renesas/0533-sh-pfc-sh7785-Remove-unused-input_pu-range.patch @@ -0,0 +1,606 @@ +From 2ee40bc5874be45180a19655aa4e7ea7eda3eb2e Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 16 Jul 2013 01:54:13 +0200 +Subject: sh-pfc: sh7785: Remove unused input_pu range + +The PFC SH7785 SoC data contains a input_pu range used to configure +pull-up resistors using the legacy non-pinconf API. That API has been +removed from the driver, the range is thus not used anymore. Remove it. + +If required, configuring pull-up resistors for the SH7785 can be +implemented using the pinconf API, as done for the SH-Mobile, R-Mobile +and R-Car platforms. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit 2afb9681265c1f63e9ee7a1bfdd0f118bce68e3f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-sh7785.c | 475 +++++++++++++++++------------------- + 1 file changed, 222 insertions(+), 253 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7785.c b/drivers/pinctrl/sh-pfc/pfc-sh7785.c +index c176b794..ddae4260 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7785.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7785.c +@@ -77,36 +77,6 @@ enum { + PR3_IN, PR2_IN, PR1_IN, PR0_IN, + PINMUX_INPUT_END, + +- PINMUX_INPUT_PULLUP_BEGIN, +- PA7_IN_PU, PA6_IN_PU, PA5_IN_PU, PA4_IN_PU, +- PA3_IN_PU, PA2_IN_PU, PA1_IN_PU, PA0_IN_PU, +- PB7_IN_PU, PB6_IN_PU, PB5_IN_PU, PB4_IN_PU, +- PB3_IN_PU, PB2_IN_PU, PB1_IN_PU, PB0_IN_PU, +- PC7_IN_PU, PC6_IN_PU, PC5_IN_PU, PC4_IN_PU, +- PC3_IN_PU, PC2_IN_PU, PC1_IN_PU, PC0_IN_PU, +- PD7_IN_PU, PD6_IN_PU, PD5_IN_PU, PD4_IN_PU, +- PD3_IN_PU, PD2_IN_PU, PD1_IN_PU, PD0_IN_PU, +- PE5_IN_PU, PE4_IN_PU, PE3_IN_PU, PE2_IN_PU, PE1_IN_PU, PE0_IN_PU, +- PF7_IN_PU, PF6_IN_PU, PF5_IN_PU, PF4_IN_PU, +- PF3_IN_PU, PF2_IN_PU, PF1_IN_PU, PF0_IN_PU, +- PG7_IN_PU, PG6_IN_PU, PG5_IN_PU, PG4_IN_PU, +- PG3_IN_PU, PG2_IN_PU, PG1_IN_PU, PG0_IN_PU, +- PH7_IN_PU, PH6_IN_PU, PH5_IN_PU, PH4_IN_PU, +- PH3_IN_PU, PH2_IN_PU, PH1_IN_PU, PH0_IN_PU, +- PJ7_IN_PU, PJ6_IN_PU, PJ5_IN_PU, PJ4_IN_PU, +- PJ3_IN_PU, PJ2_IN_PU, PJ1_IN_PU, PJ0_IN_PU, +- PK7_IN_PU, PK6_IN_PU, PK5_IN_PU, PK4_IN_PU, +- PK3_IN_PU, PK2_IN_PU, PK1_IN_PU, PK0_IN_PU, +- PL7_IN_PU, PL6_IN_PU, PL5_IN_PU, PL4_IN_PU, +- PL3_IN_PU, PL2_IN_PU, PL1_IN_PU, PL0_IN_PU, +- PM1_IN_PU, PM0_IN_PU, +- PN7_IN_PU, PN6_IN_PU, PN5_IN_PU, PN4_IN_PU, +- PN3_IN_PU, PN2_IN_PU, PN1_IN_PU, PN0_IN_PU, +- PP5_IN_PU, PP4_IN_PU, PP3_IN_PU, PP2_IN_PU, PP1_IN_PU, PP0_IN_PU, +- PQ4_IN_PU, PQ3_IN_PU, PQ2_IN_PU, PQ1_IN_PU, PQ0_IN_PU, +- PR3_IN_PU, PR2_IN_PU, PR1_IN_PU, PR0_IN_PU, +- PINMUX_INPUT_PULLUP_END, +- + PINMUX_OUTPUT_BEGIN, + PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT, + PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT, +@@ -358,147 +328,147 @@ enum { + static const pinmux_enum_t pinmux_data[] = { + + /* PA GPIO */ +- PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU), +- PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT, PA6_IN_PU), +- PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT, PA5_IN_PU), +- PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT, PA4_IN_PU), +- PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT, PA3_IN_PU), +- PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT, PA2_IN_PU), +- PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT, PA1_IN_PU), +- PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT, PA0_IN_PU), ++ PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT), ++ PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT), ++ PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT), ++ PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT), ++ PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT), ++ PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT), ++ PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT), ++ PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT), + + /* PB GPIO */ +- PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT, PB7_IN_PU), +- PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT, PB6_IN_PU), +- PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT, PB5_IN_PU), +- PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT, PB4_IN_PU), +- PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT, PB3_IN_PU), +- PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT, PB2_IN_PU), +- PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT, PB1_IN_PU), +- PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT, PB0_IN_PU), ++ PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT), ++ PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT), ++ PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT), ++ PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT), ++ PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT), ++ PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT), ++ PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT), ++ PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT), + + /* PC GPIO */ +- PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT, PC7_IN_PU), +- PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT, PC6_IN_PU), +- PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT, PC5_IN_PU), +- PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT, PC4_IN_PU), +- PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT, PC3_IN_PU), +- PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT, PC2_IN_PU), +- PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT, PC1_IN_PU), +- PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT, PC0_IN_PU), ++ PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT), ++ PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT), ++ PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT), ++ PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT), ++ PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT), ++ PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT), ++ PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT), ++ PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT), + + /* PD GPIO */ +- PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT, PD7_IN_PU), +- PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT, PD6_IN_PU), +- PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT, PD5_IN_PU), +- PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT, PD4_IN_PU), +- PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT, PD3_IN_PU), +- PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT, PD2_IN_PU), +- PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT, PD1_IN_PU), +- PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT, PD0_IN_PU), ++ PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT), ++ PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT), ++ PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT), ++ PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT), ++ PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT), ++ PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT), ++ PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT), ++ PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT), + + /* PE GPIO */ +- PINMUX_DATA(PE5_DATA, PE5_IN, PE5_OUT, PE5_IN_PU), +- PINMUX_DATA(PE4_DATA, PE4_IN, PE4_OUT, PE4_IN_PU), +- PINMUX_DATA(PE3_DATA, PE3_IN, PE3_OUT, PE3_IN_PU), +- PINMUX_DATA(PE2_DATA, PE2_IN, PE2_OUT, PE2_IN_PU), +- PINMUX_DATA(PE1_DATA, PE1_IN, PE1_OUT, PE1_IN_PU), +- PINMUX_DATA(PE0_DATA, PE0_IN, PE0_OUT, PE0_IN_PU), ++ PINMUX_DATA(PE5_DATA, PE5_IN, PE5_OUT), ++ PINMUX_DATA(PE4_DATA, PE4_IN, PE4_OUT), ++ PINMUX_DATA(PE3_DATA, PE3_IN, PE3_OUT), ++ PINMUX_DATA(PE2_DATA, PE2_IN, PE2_OUT), ++ PINMUX_DATA(PE1_DATA, PE1_IN, PE1_OUT), ++ PINMUX_DATA(PE0_DATA, PE0_IN, PE0_OUT), + + /* PF GPIO */ +- PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT, PF7_IN_PU), +- PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT, PF6_IN_PU), +- PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT, PF5_IN_PU), +- PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT, PF4_IN_PU), +- PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT, PF3_IN_PU), +- PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT, PF2_IN_PU), +- PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT, PF1_IN_PU), +- PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT, PF0_IN_PU), ++ PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT), ++ PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT), ++ PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT), ++ PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT), ++ PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT), ++ PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT), ++ PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT), ++ PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT), + + /* PG GPIO */ +- PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT, PG7_IN_PU), +- PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT, PG6_IN_PU), +- PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT, PG5_IN_PU), +- PINMUX_DATA(PG4_DATA, PG4_IN, PG4_OUT, PG4_IN_PU), +- PINMUX_DATA(PG3_DATA, PG3_IN, PG3_OUT, PG3_IN_PU), +- PINMUX_DATA(PG2_DATA, PG2_IN, PG2_OUT, PG2_IN_PU), +- PINMUX_DATA(PG1_DATA, PG1_IN, PG1_OUT, PG1_IN_PU), +- PINMUX_DATA(PG0_DATA, PG0_IN, PG0_OUT, PG0_IN_PU), ++ PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT), ++ PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT), ++ PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT), ++ PINMUX_DATA(PG4_DATA, PG4_IN, PG4_OUT), ++ PINMUX_DATA(PG3_DATA, PG3_IN, PG3_OUT), ++ PINMUX_DATA(PG2_DATA, PG2_IN, PG2_OUT), ++ PINMUX_DATA(PG1_DATA, PG1_IN, PG1_OUT), ++ PINMUX_DATA(PG0_DATA, PG0_IN, PG0_OUT), + + /* PH GPIO */ +- PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT, PH7_IN_PU), +- PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT, PH6_IN_PU), +- PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT, PH5_IN_PU), +- PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT, PH4_IN_PU), +- PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT, PH3_IN_PU), +- PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT, PH2_IN_PU), +- PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT, PH1_IN_PU), +- PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT, PH0_IN_PU), ++ PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT), ++ PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT), ++ PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT), ++ PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT), ++ PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT), ++ PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT), ++ PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT), ++ PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT), + + /* PJ GPIO */ +- PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT, PJ7_IN_PU), +- PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT, PJ6_IN_PU), +- PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT, PJ5_IN_PU), +- PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT, PJ4_IN_PU), +- PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT, PJ3_IN_PU), +- PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT, PJ2_IN_PU), +- PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT, PJ1_IN_PU), +- PINMUX_DATA(PJ0_DATA, PJ0_IN, PJ0_OUT, PJ0_IN_PU), ++ PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT), ++ PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT), ++ PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT), ++ PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT), ++ PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT), ++ PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT), ++ PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT), ++ PINMUX_DATA(PJ0_DATA, PJ0_IN, PJ0_OUT), + + /* PK GPIO */ +- PINMUX_DATA(PK7_DATA, PK7_IN, PK7_OUT, PK7_IN_PU), +- PINMUX_DATA(PK6_DATA, PK6_IN, PK6_OUT, PK6_IN_PU), +- PINMUX_DATA(PK5_DATA, PK5_IN, PK5_OUT, PK5_IN_PU), +- PINMUX_DATA(PK4_DATA, PK4_IN, PK4_OUT, PK4_IN_PU), +- PINMUX_DATA(PK3_DATA, PK3_IN, PK3_OUT, PK3_IN_PU), +- PINMUX_DATA(PK2_DATA, PK2_IN, PK2_OUT, PK2_IN_PU), +- PINMUX_DATA(PK1_DATA, PK1_IN, PK1_OUT, PK1_IN_PU), +- PINMUX_DATA(PK0_DATA, PK0_IN, PK0_OUT, PK0_IN_PU), ++ PINMUX_DATA(PK7_DATA, PK7_IN, PK7_OUT), ++ PINMUX_DATA(PK6_DATA, PK6_IN, PK6_OUT), ++ PINMUX_DATA(PK5_DATA, PK5_IN, PK5_OUT), ++ PINMUX_DATA(PK4_DATA, PK4_IN, PK4_OUT), ++ PINMUX_DATA(PK3_DATA, PK3_IN, PK3_OUT), ++ PINMUX_DATA(PK2_DATA, PK2_IN, PK2_OUT), ++ PINMUX_DATA(PK1_DATA, PK1_IN, PK1_OUT), ++ PINMUX_DATA(PK0_DATA, PK0_IN, PK0_OUT), + + /* PL GPIO */ +- PINMUX_DATA(PL7_DATA, PL7_IN, PL7_OUT, PL7_IN_PU), +- PINMUX_DATA(PL6_DATA, PL6_IN, PL6_OUT, PL6_IN_PU), +- PINMUX_DATA(PL5_DATA, PL5_IN, PL5_OUT, PL5_IN_PU), +- PINMUX_DATA(PL4_DATA, PL4_IN, PL4_OUT, PL4_IN_PU), +- PINMUX_DATA(PL3_DATA, PL3_IN, PL3_OUT, PL3_IN_PU), +- PINMUX_DATA(PL2_DATA, PL2_IN, PL2_OUT, PL2_IN_PU), +- PINMUX_DATA(PL1_DATA, PL1_IN, PL1_OUT, PL1_IN_PU), +- PINMUX_DATA(PL0_DATA, PL0_IN, PL0_OUT, PL0_IN_PU), ++ PINMUX_DATA(PL7_DATA, PL7_IN, PL7_OUT), ++ PINMUX_DATA(PL6_DATA, PL6_IN, PL6_OUT), ++ PINMUX_DATA(PL5_DATA, PL5_IN, PL5_OUT), ++ PINMUX_DATA(PL4_DATA, PL4_IN, PL4_OUT), ++ PINMUX_DATA(PL3_DATA, PL3_IN, PL3_OUT), ++ PINMUX_DATA(PL2_DATA, PL2_IN, PL2_OUT), ++ PINMUX_DATA(PL1_DATA, PL1_IN, PL1_OUT), ++ PINMUX_DATA(PL0_DATA, PL0_IN, PL0_OUT), + + /* PM GPIO */ +- PINMUX_DATA(PM1_DATA, PM1_IN, PM1_OUT, PM1_IN_PU), +- PINMUX_DATA(PM0_DATA, PM0_IN, PM0_OUT, PM0_IN_PU), ++ PINMUX_DATA(PM1_DATA, PM1_IN, PM1_OUT), ++ PINMUX_DATA(PM0_DATA, PM0_IN, PM0_OUT), + + /* PN GPIO */ +- PINMUX_DATA(PN7_DATA, PN7_IN, PN7_OUT, PN7_IN_PU), +- PINMUX_DATA(PN6_DATA, PN6_IN, PN6_OUT, PN6_IN_PU), +- PINMUX_DATA(PN5_DATA, PN5_IN, PN5_OUT, PN5_IN_PU), +- PINMUX_DATA(PN4_DATA, PN4_IN, PN4_OUT, PN4_IN_PU), +- PINMUX_DATA(PN3_DATA, PN3_IN, PN3_OUT, PN3_IN_PU), +- PINMUX_DATA(PN2_DATA, PN2_IN, PN2_OUT, PN2_IN_PU), +- PINMUX_DATA(PN1_DATA, PN1_IN, PN1_OUT, PN1_IN_PU), +- PINMUX_DATA(PN0_DATA, PN0_IN, PN0_OUT, PN0_IN_PU), ++ PINMUX_DATA(PN7_DATA, PN7_IN, PN7_OUT), ++ PINMUX_DATA(PN6_DATA, PN6_IN, PN6_OUT), ++ PINMUX_DATA(PN5_DATA, PN5_IN, PN5_OUT), ++ PINMUX_DATA(PN4_DATA, PN4_IN, PN4_OUT), ++ PINMUX_DATA(PN3_DATA, PN3_IN, PN3_OUT), ++ PINMUX_DATA(PN2_DATA, PN2_IN, PN2_OUT), ++ PINMUX_DATA(PN1_DATA, PN1_IN, PN1_OUT), ++ PINMUX_DATA(PN0_DATA, PN0_IN, PN0_OUT), + + /* PP GPIO */ +- PINMUX_DATA(PP5_DATA, PP5_IN, PP5_OUT, PP5_IN_PU), +- PINMUX_DATA(PP4_DATA, PP4_IN, PP4_OUT, PP4_IN_PU), +- PINMUX_DATA(PP3_DATA, PP3_IN, PP3_OUT, PP3_IN_PU), +- PINMUX_DATA(PP2_DATA, PP2_IN, PP2_OUT, PP2_IN_PU), +- PINMUX_DATA(PP1_DATA, PP1_IN, PP1_OUT, PP1_IN_PU), +- PINMUX_DATA(PP0_DATA, PP0_IN, PP0_OUT, PP0_IN_PU), ++ PINMUX_DATA(PP5_DATA, PP5_IN, PP5_OUT), ++ PINMUX_DATA(PP4_DATA, PP4_IN, PP4_OUT), ++ PINMUX_DATA(PP3_DATA, PP3_IN, PP3_OUT), ++ PINMUX_DATA(PP2_DATA, PP2_IN, PP2_OUT), ++ PINMUX_DATA(PP1_DATA, PP1_IN, PP1_OUT), ++ PINMUX_DATA(PP0_DATA, PP0_IN, PP0_OUT), + + /* PQ GPIO */ +- PINMUX_DATA(PQ4_DATA, PQ4_IN, PQ4_OUT, PQ4_IN_PU), +- PINMUX_DATA(PQ3_DATA, PQ3_IN, PQ3_OUT, PQ3_IN_PU), +- PINMUX_DATA(PQ2_DATA, PQ2_IN, PQ2_OUT, PQ2_IN_PU), +- PINMUX_DATA(PQ1_DATA, PQ1_IN, PQ1_OUT, PQ1_IN_PU), +- PINMUX_DATA(PQ0_DATA, PQ0_IN, PQ0_OUT, PQ0_IN_PU), ++ PINMUX_DATA(PQ4_DATA, PQ4_IN, PQ4_OUT), ++ PINMUX_DATA(PQ3_DATA, PQ3_IN, PQ3_OUT), ++ PINMUX_DATA(PQ2_DATA, PQ2_IN, PQ2_OUT), ++ PINMUX_DATA(PQ1_DATA, PQ1_IN, PQ1_OUT), ++ PINMUX_DATA(PQ0_DATA, PQ0_IN, PQ0_OUT), + + /* PR GPIO */ +- PINMUX_DATA(PR3_DATA, PR3_IN, PR3_OUT, PR3_IN_PU), +- PINMUX_DATA(PR2_DATA, PR2_IN, PR2_OUT, PR2_IN_PU), +- PINMUX_DATA(PR1_DATA, PR1_IN, PR1_OUT, PR1_IN_PU), +- PINMUX_DATA(PR0_DATA, PR0_IN, PR0_OUT, PR0_IN_PU), ++ PINMUX_DATA(PR3_DATA, PR3_IN, PR3_OUT), ++ PINMUX_DATA(PR2_DATA, PR2_IN, PR2_OUT), ++ PINMUX_DATA(PR1_DATA, PR1_IN, PR1_OUT), ++ PINMUX_DATA(PR0_DATA, PR0_IN, PR0_OUT), + + /* PA FN */ + PINMUX_DATA(D63_AD31_MARK, PA7_FN), +@@ -1020,114 +990,114 @@ static const struct pinmux_func pinmux_func_gpios[] = { + + static const struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("PACR", 0xffe70000, 16, 2) { +- PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU, +- PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU, +- PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU, +- PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU, +- PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU, +- PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU, +- PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU, +- PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU } ++ PA7_FN, PA7_OUT, PA7_IN, 0, ++ PA6_FN, PA6_OUT, PA6_IN, 0, ++ PA5_FN, PA5_OUT, PA5_IN, 0, ++ PA4_FN, PA4_OUT, PA4_IN, 0, ++ PA3_FN, PA3_OUT, PA3_IN, 0, ++ PA2_FN, PA2_OUT, PA2_IN, 0, ++ PA1_FN, PA1_OUT, PA1_IN, 0, ++ PA0_FN, PA0_OUT, PA0_IN, 0 } + }, + { PINMUX_CFG_REG("PBCR", 0xffe70002, 16, 2) { +- PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU, +- PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU, +- PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU, +- PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU, +- PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU, +- PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU, +- PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU, +- PB0_FN, PB0_OUT, PB0_IN, PB0_IN_PU } ++ PB7_FN, PB7_OUT, PB7_IN, 0, ++ PB6_FN, PB6_OUT, PB6_IN, 0, ++ PB5_FN, PB5_OUT, PB5_IN, 0, ++ PB4_FN, PB4_OUT, PB4_IN, 0, ++ PB3_FN, PB3_OUT, PB3_IN, 0, ++ PB2_FN, PB2_OUT, PB2_IN, 0, ++ PB1_FN, PB1_OUT, PB1_IN, 0, ++ PB0_FN, PB0_OUT, PB0_IN, 0 } + }, + { PINMUX_CFG_REG("PCCR", 0xffe70004, 16, 2) { +- PC7_FN, PC7_OUT, PC7_IN, PC7_IN_PU, +- PC6_FN, PC6_OUT, PC6_IN, PC6_IN_PU, +- PC5_FN, PC5_OUT, PC5_IN, PC5_IN_PU, +- PC4_FN, PC4_OUT, PC4_IN, PC4_IN_PU, +- PC3_FN, PC3_OUT, PC3_IN, PC3_IN_PU, +- PC2_FN, PC2_OUT, PC2_IN, PC2_IN_PU, +- PC1_FN, PC1_OUT, PC1_IN, PC1_IN_PU, +- PC0_FN, PC0_OUT, PC0_IN, PC0_IN_PU } ++ PC7_FN, PC7_OUT, PC7_IN, 0, ++ PC6_FN, PC6_OUT, PC6_IN, 0, ++ PC5_FN, PC5_OUT, PC5_IN, 0, ++ PC4_FN, PC4_OUT, PC4_IN, 0, ++ PC3_FN, PC3_OUT, PC3_IN, 0, ++ PC2_FN, PC2_OUT, PC2_IN, 0, ++ PC1_FN, PC1_OUT, PC1_IN, 0, ++ PC0_FN, PC0_OUT, PC0_IN, 0 } + }, + { PINMUX_CFG_REG("PDCR", 0xffe70006, 16, 2) { +- PD7_FN, PD7_OUT, PD7_IN, PD7_IN_PU, +- PD6_FN, PD6_OUT, PD6_IN, PD6_IN_PU, +- PD5_FN, PD5_OUT, PD5_IN, PD5_IN_PU, +- PD4_FN, PD4_OUT, PD4_IN, PD4_IN_PU, +- PD3_FN, PD3_OUT, PD3_IN, PD3_IN_PU, +- PD2_FN, PD2_OUT, PD2_IN, PD2_IN_PU, +- PD1_FN, PD1_OUT, PD1_IN, PD1_IN_PU, +- PD0_FN, PD0_OUT, PD0_IN, PD0_IN_PU } ++ PD7_FN, PD7_OUT, PD7_IN, 0, ++ PD6_FN, PD6_OUT, PD6_IN, 0, ++ PD5_FN, PD5_OUT, PD5_IN, 0, ++ PD4_FN, PD4_OUT, PD4_IN, 0, ++ PD3_FN, PD3_OUT, PD3_IN, 0, ++ PD2_FN, PD2_OUT, PD2_IN, 0, ++ PD1_FN, PD1_OUT, PD1_IN, 0, ++ PD0_FN, PD0_OUT, PD0_IN, 0 } + }, + { PINMUX_CFG_REG("PECR", 0xffe70008, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, +- PE5_FN, PE5_OUT, PE5_IN, PE5_IN_PU, +- PE4_FN, PE4_OUT, PE4_IN, PE4_IN_PU, +- PE3_FN, PE3_OUT, PE3_IN, PE3_IN_PU, +- PE2_FN, PE2_OUT, PE2_IN, PE2_IN_PU, +- PE1_FN, PE1_OUT, PE1_IN, PE1_IN_PU, +- PE0_FN, PE0_OUT, PE0_IN, PE0_IN_PU } ++ PE5_FN, PE5_OUT, PE5_IN, 0, ++ PE4_FN, PE4_OUT, PE4_IN, 0, ++ PE3_FN, PE3_OUT, PE3_IN, 0, ++ PE2_FN, PE2_OUT, PE2_IN, 0, ++ PE1_FN, PE1_OUT, PE1_IN, 0, ++ PE0_FN, PE0_OUT, PE0_IN, 0 } + }, + { PINMUX_CFG_REG("PFCR", 0xffe7000a, 16, 2) { +- PF7_FN, PF7_OUT, PF7_IN, PF7_IN_PU, +- PF6_FN, PF6_OUT, PF6_IN, PF6_IN_PU, +- PF5_FN, PF5_OUT, PF5_IN, PF5_IN_PU, +- PF4_FN, PF4_OUT, PF4_IN, PF4_IN_PU, +- PF3_FN, PF3_OUT, PF3_IN, PF3_IN_PU, +- PF2_FN, PF2_OUT, PF2_IN, PF2_IN_PU, +- PF1_FN, PF1_OUT, PF1_IN, PF1_IN_PU, +- PF0_FN, PF0_OUT, PF0_IN, PF0_IN_PU } ++ PF7_FN, PF7_OUT, PF7_IN, 0, ++ PF6_FN, PF6_OUT, PF6_IN, 0, ++ PF5_FN, PF5_OUT, PF5_IN, 0, ++ PF4_FN, PF4_OUT, PF4_IN, 0, ++ PF3_FN, PF3_OUT, PF3_IN, 0, ++ PF2_FN, PF2_OUT, PF2_IN, 0, ++ PF1_FN, PF1_OUT, PF1_IN, 0, ++ PF0_FN, PF0_OUT, PF0_IN, 0 } + }, + { PINMUX_CFG_REG("PGCR", 0xffe7000c, 16, 2) { +- PG7_FN, PG7_OUT, PG7_IN, PG7_IN_PU, +- PG6_FN, PG6_OUT, PG6_IN, PG6_IN_PU, +- PG5_FN, PG5_OUT, PG5_IN, PG5_IN_PU, +- PG4_FN, PG4_OUT, PG4_IN, PG4_IN_PU, +- PG3_FN, PG3_OUT, PG3_IN, PG3_IN_PU, +- PG2_FN, PG2_OUT, PG2_IN, PG2_IN_PU, +- PG1_FN, PG1_OUT, PG1_IN, PG1_IN_PU, +- PG0_FN, PG0_OUT, PG0_IN, PG0_IN_PU } ++ PG7_FN, PG7_OUT, PG7_IN, 0, ++ PG6_FN, PG6_OUT, PG6_IN, 0, ++ PG5_FN, PG5_OUT, PG5_IN, 0, ++ PG4_FN, PG4_OUT, PG4_IN, 0, ++ PG3_FN, PG3_OUT, PG3_IN, 0, ++ PG2_FN, PG2_OUT, PG2_IN, 0, ++ PG1_FN, PG1_OUT, PG1_IN, 0, ++ PG0_FN, PG0_OUT, PG0_IN, 0 } + }, + { PINMUX_CFG_REG("PHCR", 0xffe7000e, 16, 2) { +- PH7_FN, PH7_OUT, PH7_IN, PH7_IN_PU, +- PH6_FN, PH6_OUT, PH6_IN, PH6_IN_PU, +- PH5_FN, PH5_OUT, PH5_IN, PH5_IN_PU, +- PH4_FN, PH4_OUT, PH4_IN, PH4_IN_PU, +- PH3_FN, PH3_OUT, PH3_IN, PH3_IN_PU, +- PH2_FN, PH2_OUT, PH2_IN, PH2_IN_PU, +- PH1_FN, PH1_OUT, PH1_IN, PH1_IN_PU, +- PH0_FN, PH0_OUT, PH0_IN, PH0_IN_PU } ++ PH7_FN, PH7_OUT, PH7_IN, 0, ++ PH6_FN, PH6_OUT, PH6_IN, 0, ++ PH5_FN, PH5_OUT, PH5_IN, 0, ++ PH4_FN, PH4_OUT, PH4_IN, 0, ++ PH3_FN, PH3_OUT, PH3_IN, 0, ++ PH2_FN, PH2_OUT, PH2_IN, 0, ++ PH1_FN, PH1_OUT, PH1_IN, 0, ++ PH0_FN, PH0_OUT, PH0_IN, 0 } + }, + { PINMUX_CFG_REG("PJCR", 0xffe70010, 16, 2) { +- PJ7_FN, PJ7_OUT, PJ7_IN, PJ7_IN_PU, +- PJ6_FN, PJ6_OUT, PJ6_IN, PJ6_IN_PU, +- PJ5_FN, PJ5_OUT, PJ5_IN, PJ5_IN_PU, +- PJ4_FN, PJ4_OUT, PJ4_IN, PJ4_IN_PU, +- PJ3_FN, PJ3_OUT, PJ3_IN, PJ3_IN_PU, +- PJ2_FN, PJ2_OUT, PJ2_IN, PJ2_IN_PU, +- PJ1_FN, PJ1_OUT, PJ1_IN, PJ1_IN_PU, +- PJ0_FN, PJ0_OUT, PJ0_IN, PJ0_IN_PU } ++ PJ7_FN, PJ7_OUT, PJ7_IN, 0, ++ PJ6_FN, PJ6_OUT, PJ6_IN, 0, ++ PJ5_FN, PJ5_OUT, PJ5_IN, 0, ++ PJ4_FN, PJ4_OUT, PJ4_IN, 0, ++ PJ3_FN, PJ3_OUT, PJ3_IN, 0, ++ PJ2_FN, PJ2_OUT, PJ2_IN, 0, ++ PJ1_FN, PJ1_OUT, PJ1_IN, 0, ++ PJ0_FN, PJ0_OUT, PJ0_IN, 0 } + }, + { PINMUX_CFG_REG("PKCR", 0xffe70012, 16, 2) { +- PK7_FN, PK7_OUT, PK7_IN, PK7_IN_PU, +- PK6_FN, PK6_OUT, PK6_IN, PK6_IN_PU, +- PK5_FN, PK5_OUT, PK5_IN, PK5_IN_PU, +- PK4_FN, PK4_OUT, PK4_IN, PK4_IN_PU, +- PK3_FN, PK3_OUT, PK3_IN, PK3_IN_PU, +- PK2_FN, PK2_OUT, PK2_IN, PK2_IN_PU, +- PK1_FN, PK1_OUT, PK1_IN, PK1_IN_PU, +- PK0_FN, PK0_OUT, PK0_IN, PK0_IN_PU } ++ PK7_FN, PK7_OUT, PK7_IN, 0, ++ PK6_FN, PK6_OUT, PK6_IN, 0, ++ PK5_FN, PK5_OUT, PK5_IN, 0, ++ PK4_FN, PK4_OUT, PK4_IN, 0, ++ PK3_FN, PK3_OUT, PK3_IN, 0, ++ PK2_FN, PK2_OUT, PK2_IN, 0, ++ PK1_FN, PK1_OUT, PK1_IN, 0, ++ PK0_FN, PK0_OUT, PK0_IN, 0 } + }, + { PINMUX_CFG_REG("PLCR", 0xffe70014, 16, 2) { +- PL7_FN, PL7_OUT, PL7_IN, PL7_IN_PU, +- PL6_FN, PL6_OUT, PL6_IN, PL6_IN_PU, +- PL5_FN, PL5_OUT, PL5_IN, PL5_IN_PU, +- PL4_FN, PL4_OUT, PL4_IN, PL4_IN_PU, +- PL3_FN, PL3_OUT, PL3_IN, PL3_IN_PU, +- PL2_FN, PL2_OUT, PL2_IN, PL2_IN_PU, +- PL1_FN, PL1_OUT, PL1_IN, PL1_IN_PU, +- PL0_FN, PL0_OUT, PL0_IN, PL0_IN_PU } ++ PL7_FN, PL7_OUT, PL7_IN, 0, ++ PL6_FN, PL6_OUT, PL6_IN, 0, ++ PL5_FN, PL5_OUT, PL5_IN, 0, ++ PL4_FN, PL4_OUT, PL4_IN, 0, ++ PL3_FN, PL3_OUT, PL3_IN, 0, ++ PL2_FN, PL2_OUT, PL2_IN, 0, ++ PL1_FN, PL1_OUT, PL1_IN, 0, ++ PL0_FN, PL0_OUT, PL0_IN, 0 } + }, + { PINMUX_CFG_REG("PMCR", 0xffe70016, 16, 2) { + 0, 0, 0, 0, +@@ -1136,48 +1106,48 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, +- PM1_FN, PM1_OUT, PM1_IN, PM1_IN_PU, +- PM0_FN, PM0_OUT, PM0_IN, PM0_IN_PU } ++ PM1_FN, PM1_OUT, PM1_IN, 0, ++ PM0_FN, PM0_OUT, PM0_IN, 0 } + }, + { PINMUX_CFG_REG("PNCR", 0xffe70018, 16, 2) { +- PN7_FN, PN7_OUT, PN7_IN, PN7_IN_PU, +- PN6_FN, PN6_OUT, PN6_IN, PN6_IN_PU, +- PN5_FN, PN5_OUT, PN5_IN, PN5_IN_PU, +- PN4_FN, PN4_OUT, PN4_IN, PN4_IN_PU, +- PN3_FN, PN3_OUT, PN3_IN, PN3_IN_PU, +- PN2_FN, PN2_OUT, PN2_IN, PN2_IN_PU, +- PN1_FN, PN1_OUT, PN1_IN, PN1_IN_PU, +- PN0_FN, PN0_OUT, PN0_IN, PN0_IN_PU } ++ PN7_FN, PN7_OUT, PN7_IN, 0, ++ PN6_FN, PN6_OUT, PN6_IN, 0, ++ PN5_FN, PN5_OUT, PN5_IN, 0, ++ PN4_FN, PN4_OUT, PN4_IN, 0, ++ PN3_FN, PN3_OUT, PN3_IN, 0, ++ PN2_FN, PN2_OUT, PN2_IN, 0, ++ PN1_FN, PN1_OUT, PN1_IN, 0, ++ PN0_FN, PN0_OUT, PN0_IN, 0 } + }, + { PINMUX_CFG_REG("PPCR", 0xffe7001a, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, +- PP5_FN, PP5_OUT, PP5_IN, PP5_IN_PU, +- PP4_FN, PP4_OUT, PP4_IN, PP4_IN_PU, +- PP3_FN, PP3_OUT, PP3_IN, PP3_IN_PU, +- PP2_FN, PP2_OUT, PP2_IN, PP2_IN_PU, +- PP1_FN, PP1_OUT, PP1_IN, PP1_IN_PU, +- PP0_FN, PP0_OUT, PP0_IN, PP0_IN_PU } ++ PP5_FN, PP5_OUT, PP5_IN, 0, ++ PP4_FN, PP4_OUT, PP4_IN, 0, ++ PP3_FN, PP3_OUT, PP3_IN, 0, ++ PP2_FN, PP2_OUT, PP2_IN, 0, ++ PP1_FN, PP1_OUT, PP1_IN, 0, ++ PP0_FN, PP0_OUT, PP0_IN, 0 } + }, + { PINMUX_CFG_REG("PQCR", 0xffe7001c, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, +- PQ4_FN, PQ4_OUT, PQ4_IN, PQ4_IN_PU, +- PQ3_FN, PQ3_OUT, PQ3_IN, PQ3_IN_PU, +- PQ2_FN, PQ2_OUT, PQ2_IN, PQ2_IN_PU, +- PQ1_FN, PQ1_OUT, PQ1_IN, PQ1_IN_PU, +- PQ0_FN, PQ0_OUT, PQ0_IN, PQ0_IN_PU } ++ PQ4_FN, PQ4_OUT, PQ4_IN, 0, ++ PQ3_FN, PQ3_OUT, PQ3_IN, 0, ++ PQ2_FN, PQ2_OUT, PQ2_IN, 0, ++ PQ1_FN, PQ1_OUT, PQ1_IN, 0, ++ PQ0_FN, PQ0_OUT, PQ0_IN, 0 } + }, + { PINMUX_CFG_REG("PRCR", 0xffe7001e, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, +- PR3_FN, PR3_OUT, PR3_IN, PR3_IN_PU, +- PR2_FN, PR2_OUT, PR2_IN, PR2_IN_PU, +- PR1_FN, PR1_OUT, PR1_IN, PR1_IN_PU, +- PR0_FN, PR0_OUT, PR0_IN, PR0_IN_PU } ++ PR3_FN, PR3_OUT, PR3_IN, 0, ++ PR2_FN, PR2_OUT, PR2_IN, 0, ++ PR1_FN, PR1_OUT, PR1_IN, 0, ++ PR0_FN, PR0_OUT, PR0_IN, 0 } + }, + { PINMUX_CFG_REG("P1MSELR", 0xffe70080, 16, 1) { + P1MSEL15_0, P1MSEL15_1, +@@ -1289,7 +1259,6 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { + const struct sh_pfc_soc_info sh7785_pinmux_info = { + .name = "sh7785_pfc", + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, +- .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0534-sh-pfc-sh7786-Remove-unused-input_pu-range.patch b/patches.renesas/0534-sh-pfc-sh7786-Remove-unused-input_pu-range.patch new file mode 100644 index 00000000000..e8d85fbcb67 --- /dev/null +++ b/patches.renesas/0534-sh-pfc-sh7786-Remove-unused-input_pu-range.patch @@ -0,0 +1,357 @@ +From 893aed6ea107ac691fdc22d5b20315ccfb3b68c8 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 16 Jul 2013 01:54:13 +0200 +Subject: sh-pfc: sh7786: Remove unused input_pu range + +The PFC SH7786 SoC data contains a input_pu range used to configure +pull-up resistors using the legacy non-pinconf API. That API has been +removed from the driver, the range is thus not used anymore. Remove it. + +If required, configuring pull-up resistors for the SH7786 can be +implemented using the pinconf API, as done for the SH-Mobile, R-Mobile +and R-Car platforms. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit 082ab8ff33f250c519b364224263b44a86c71c2d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-sh7786.c | 260 +++++++++++++++++------------------- + 1 file changed, 120 insertions(+), 140 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7786.c b/drivers/pinctrl/sh-pfc/pfc-sh7786.c +index 8ae0e328..c855fca5 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7786.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7786.c +@@ -60,25 +60,6 @@ enum { + PJ3_IN, PJ2_IN, PJ1_IN, + PINMUX_INPUT_END, + +- PINMUX_INPUT_PULLUP_BEGIN, +- PA7_IN_PU, PA6_IN_PU, PA5_IN_PU, PA4_IN_PU, +- PA3_IN_PU, PA2_IN_PU, PA1_IN_PU, PA0_IN_PU, +- PB7_IN_PU, PB6_IN_PU, PB5_IN_PU, PB4_IN_PU, +- PB3_IN_PU, PB2_IN_PU, PB1_IN_PU, PB0_IN_PU, +- PC7_IN_PU, PC6_IN_PU, PC5_IN_PU, PC4_IN_PU, +- PC3_IN_PU, PC2_IN_PU, PC1_IN_PU, PC0_IN_PU, +- PD7_IN_PU, PD6_IN_PU, PD5_IN_PU, PD4_IN_PU, +- PD3_IN_PU, PD2_IN_PU, PD1_IN_PU, PD0_IN_PU, +- PE7_IN_PU, PE6_IN_PU, +- PF7_IN_PU, PF6_IN_PU, PF5_IN_PU, PF4_IN_PU, +- PF3_IN_PU, PF2_IN_PU, PF1_IN_PU, PF0_IN_PU, +- PG7_IN_PU, PG6_IN_PU, PG5_IN_PU, +- PH7_IN_PU, PH6_IN_PU, PH5_IN_PU, PH4_IN_PU, +- PH3_IN_PU, PH2_IN_PU, PH1_IN_PU, PH0_IN_PU, +- PJ7_IN_PU, PJ6_IN_PU, PJ5_IN_PU, PJ4_IN_PU, +- PJ3_IN_PU, PJ2_IN_PU, PJ1_IN_PU, +- PINMUX_INPUT_PULLUP_END, +- + PINMUX_OUTPUT_BEGIN, + PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT, + PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT, +@@ -194,82 +175,82 @@ enum { + static const pinmux_enum_t pinmux_data[] = { + + /* PA GPIO */ +- PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU), +- PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT, PA6_IN_PU), +- PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT, PA5_IN_PU), +- PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT, PA4_IN_PU), +- PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT, PA3_IN_PU), +- PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT, PA2_IN_PU), +- PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT, PA1_IN_PU), +- PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT, PA0_IN_PU), ++ PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT), ++ PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT), ++ PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT), ++ PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT), ++ PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT), ++ PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT), ++ PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT), ++ PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT), + + /* PB GPIO */ +- PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT, PB7_IN_PU), +- PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT, PB6_IN_PU), +- PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT, PB5_IN_PU), +- PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT, PB4_IN_PU), +- PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT, PB3_IN_PU), +- PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT, PB2_IN_PU), +- PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT, PB1_IN_PU), +- PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT, PB0_IN_PU), ++ PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT), ++ PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT), ++ PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT), ++ PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT), ++ PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT), ++ PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT), ++ PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT), ++ PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT), + + /* PC GPIO */ +- PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT, PC7_IN_PU), +- PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT, PC6_IN_PU), +- PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT, PC5_IN_PU), +- PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT, PC4_IN_PU), +- PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT, PC3_IN_PU), +- PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT, PC2_IN_PU), +- PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT, PC1_IN_PU), +- PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT, PC0_IN_PU), ++ PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT), ++ PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT), ++ PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT), ++ PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT), ++ PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT), ++ PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT), ++ PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT), ++ PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT), + + /* PD GPIO */ +- PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT, PD7_IN_PU), +- PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT, PD6_IN_PU), +- PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT, PD5_IN_PU), +- PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT, PD4_IN_PU), +- PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT, PD3_IN_PU), +- PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT, PD2_IN_PU), +- PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT, PD1_IN_PU), +- PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT, PD0_IN_PU), ++ PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT), ++ PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT), ++ PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT), ++ PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT), ++ PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT), ++ PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT), ++ PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT), ++ PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT), + + /* PE GPIO */ +- PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT, PE7_IN_PU), +- PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT, PE6_IN_PU), ++ PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT), ++ PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT), + + /* PF GPIO */ +- PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT, PF7_IN_PU), +- PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT, PF6_IN_PU), +- PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT, PF5_IN_PU), +- PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT, PF4_IN_PU), +- PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT, PF3_IN_PU), +- PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT, PF2_IN_PU), +- PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT, PF1_IN_PU), +- PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT, PF0_IN_PU), ++ PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT), ++ PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT), ++ PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT), ++ PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT), ++ PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT), ++ PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT), ++ PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT), ++ PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT), + + /* PG GPIO */ +- PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT, PG7_IN_PU), +- PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT, PG6_IN_PU), +- PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT, PG5_IN_PU), ++ PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT), ++ PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT), ++ PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT), + + /* PH GPIO */ +- PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT, PH7_IN_PU), +- PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT, PH6_IN_PU), +- PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT, PH5_IN_PU), +- PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT, PH4_IN_PU), +- PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT, PH3_IN_PU), +- PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT, PH2_IN_PU), +- PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT, PH1_IN_PU), +- PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT, PH0_IN_PU), ++ PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT), ++ PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT), ++ PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT), ++ PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT), ++ PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT), ++ PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT), ++ PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT), ++ PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT), + + /* PJ GPIO */ +- PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT, PJ7_IN_PU), +- PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT, PJ6_IN_PU), +- PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT, PJ5_IN_PU), +- PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT, PJ4_IN_PU), +- PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT, PJ3_IN_PU), +- PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT, PJ2_IN_PU), +- PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT, PJ1_IN_PU), ++ PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT), ++ PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT), ++ PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT), ++ PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT), ++ PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT), ++ PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT), ++ PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT), + + /* PA FN */ + PINMUX_DATA(CDE_MARK, P1MSEL2_0, PA7_FN), +@@ -651,48 +632,48 @@ static const struct pinmux_func pinmux_func_gpios[] = { + + static const struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2) { +- PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU, +- PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU, +- PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU, +- PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU, +- PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU, +- PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU, +- PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU, +- PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU } ++ PA7_FN, PA7_OUT, PA7_IN, 0, ++ PA6_FN, PA6_OUT, PA6_IN, 0, ++ PA5_FN, PA5_OUT, PA5_IN, 0, ++ PA4_FN, PA4_OUT, PA4_IN, 0, ++ PA3_FN, PA3_OUT, PA3_IN, 0, ++ PA2_FN, PA2_OUT, PA2_IN, 0, ++ PA1_FN, PA1_OUT, PA1_IN, 0, ++ PA0_FN, PA0_OUT, PA0_IN, 0 } + }, + { PINMUX_CFG_REG("PBCR", 0xffcc0002, 16, 2) { +- PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU, +- PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU, +- PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU, +- PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU, +- PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU, +- PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU, +- PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU, +- PB0_FN, PB0_OUT, PB0_IN, PB0_IN_PU } ++ PB7_FN, PB7_OUT, PB7_IN, 0, ++ PB6_FN, PB6_OUT, PB6_IN, 0, ++ PB5_FN, PB5_OUT, PB5_IN, 0, ++ PB4_FN, PB4_OUT, PB4_IN, 0, ++ PB3_FN, PB3_OUT, PB3_IN, 0, ++ PB2_FN, PB2_OUT, PB2_IN, 0, ++ PB1_FN, PB1_OUT, PB1_IN, 0, ++ PB0_FN, PB0_OUT, PB0_IN, 0 } + }, + { PINMUX_CFG_REG("PCCR", 0xffcc0004, 16, 2) { +- PC7_FN, PC7_OUT, PC7_IN, PC7_IN_PU, +- PC6_FN, PC6_OUT, PC6_IN, PC6_IN_PU, +- PC5_FN, PC5_OUT, PC5_IN, PC5_IN_PU, +- PC4_FN, PC4_OUT, PC4_IN, PC4_IN_PU, +- PC3_FN, PC3_OUT, PC3_IN, PC3_IN_PU, +- PC2_FN, PC2_OUT, PC2_IN, PC2_IN_PU, +- PC1_FN, PC1_OUT, PC1_IN, PC1_IN_PU, +- PC0_FN, PC0_OUT, PC0_IN, PC0_IN_PU } ++ PC7_FN, PC7_OUT, PC7_IN, 0, ++ PC6_FN, PC6_OUT, PC6_IN, 0, ++ PC5_FN, PC5_OUT, PC5_IN, 0, ++ PC4_FN, PC4_OUT, PC4_IN, 0, ++ PC3_FN, PC3_OUT, PC3_IN, 0, ++ PC2_FN, PC2_OUT, PC2_IN, 0, ++ PC1_FN, PC1_OUT, PC1_IN, 0, ++ PC0_FN, PC0_OUT, PC0_IN, 0 } + }, + { PINMUX_CFG_REG("PDCR", 0xffcc0006, 16, 2) { +- PD7_FN, PD7_OUT, PD7_IN, PD7_IN_PU, +- PD6_FN, PD6_OUT, PD6_IN, PD6_IN_PU, +- PD5_FN, PD5_OUT, PD5_IN, PD5_IN_PU, +- PD4_FN, PD4_OUT, PD4_IN, PD4_IN_PU, +- PD3_FN, PD3_OUT, PD3_IN, PD3_IN_PU, +- PD2_FN, PD2_OUT, PD2_IN, PD2_IN_PU, +- PD1_FN, PD1_OUT, PD1_IN, PD1_IN_PU, +- PD0_FN, PD0_OUT, PD0_IN, PD0_IN_PU } ++ PD7_FN, PD7_OUT, PD7_IN, 0, ++ PD6_FN, PD6_OUT, PD6_IN, 0, ++ PD5_FN, PD5_OUT, PD5_IN, 0, ++ PD4_FN, PD4_OUT, PD4_IN, 0, ++ PD3_FN, PD3_OUT, PD3_IN, 0, ++ PD2_FN, PD2_OUT, PD2_IN, 0, ++ PD1_FN, PD1_OUT, PD1_IN, 0, ++ PD0_FN, PD0_OUT, PD0_IN, 0 } + }, + { PINMUX_CFG_REG("PECR", 0xffcc0008, 16, 2) { +- PE7_FN, PE7_OUT, PE7_IN, PE7_IN_PU, +- PE6_FN, PE6_OUT, PE6_IN, PE6_IN_PU, ++ PE7_FN, PE7_OUT, PE7_IN, 0, ++ PE6_FN, PE6_OUT, PE6_IN, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, +@@ -701,19 +682,19 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG("PFCR", 0xffcc000a, 16, 2) { +- PF7_FN, PF7_OUT, PF7_IN, PF7_IN_PU, +- PF6_FN, PF6_OUT, PF6_IN, PF6_IN_PU, +- PF5_FN, PF5_OUT, PF5_IN, PF5_IN_PU, +- PF4_FN, PF4_OUT, PF4_IN, PF4_IN_PU, +- PF3_FN, PF3_OUT, PF3_IN, PF3_IN_PU, +- PF2_FN, PF2_OUT, PF2_IN, PF2_IN_PU, +- PF1_FN, PF1_OUT, PF1_IN, PF1_IN_PU, +- PF0_FN, PF0_OUT, PF0_IN, PF0_IN_PU } ++ PF7_FN, PF7_OUT, PF7_IN, 0, ++ PF6_FN, PF6_OUT, PF6_IN, 0, ++ PF5_FN, PF5_OUT, PF5_IN, 0, ++ PF4_FN, PF4_OUT, PF4_IN, 0, ++ PF3_FN, PF3_OUT, PF3_IN, 0, ++ PF2_FN, PF2_OUT, PF2_IN, 0, ++ PF1_FN, PF1_OUT, PF1_IN, 0, ++ PF0_FN, PF0_OUT, PF0_IN, 0 } + }, + { PINMUX_CFG_REG("PGCR", 0xffcc000c, 16, 2) { +- PG7_FN, PG7_OUT, PG7_IN, PG7_IN_PU, +- PG6_FN, PG6_OUT, PG6_IN, PG6_IN_PU, +- PG5_FN, PG5_OUT, PG5_IN, PG5_IN_PU, ++ PG7_FN, PG7_OUT, PG7_IN, 0, ++ PG6_FN, PG6_OUT, PG6_IN, 0, ++ PG5_FN, PG5_OUT, PG5_IN, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, +@@ -721,23 +702,23 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG("PHCR", 0xffcc000e, 16, 2) { +- PH7_FN, PH7_OUT, PH7_IN, PH7_IN_PU, +- PH6_FN, PH6_OUT, PH6_IN, PH6_IN_PU, +- PH5_FN, PH5_OUT, PH5_IN, PH5_IN_PU, +- PH4_FN, PH4_OUT, PH4_IN, PH4_IN_PU, +- PH3_FN, PH3_OUT, PH3_IN, PH3_IN_PU, +- PH2_FN, PH2_OUT, PH2_IN, PH2_IN_PU, +- PH1_FN, PH1_OUT, PH1_IN, PH1_IN_PU, +- PH0_FN, PH0_OUT, PH0_IN, PH0_IN_PU } ++ PH7_FN, PH7_OUT, PH7_IN, 0, ++ PH6_FN, PH6_OUT, PH6_IN, 0, ++ PH5_FN, PH5_OUT, PH5_IN, 0, ++ PH4_FN, PH4_OUT, PH4_IN, 0, ++ PH3_FN, PH3_OUT, PH3_IN, 0, ++ PH2_FN, PH2_OUT, PH2_IN, 0, ++ PH1_FN, PH1_OUT, PH1_IN, 0, ++ PH0_FN, PH0_OUT, PH0_IN, 0 } + }, + { PINMUX_CFG_REG("PJCR", 0xffcc0010, 16, 2) { +- PJ7_FN, PJ7_OUT, PJ7_IN, PJ7_IN_PU, +- PJ6_FN, PJ6_OUT, PJ6_IN, PJ6_IN_PU, +- PJ5_FN, PJ5_OUT, PJ5_IN, PJ5_IN_PU, +- PJ4_FN, PJ4_OUT, PJ4_IN, PJ4_IN_PU, +- PJ3_FN, PJ3_OUT, PJ3_IN, PJ3_IN_PU, +- PJ2_FN, PJ2_OUT, PJ2_IN, PJ2_IN_PU, +- PJ1_FN, PJ1_OUT, PJ1_IN, PJ1_IN_PU, ++ PJ7_FN, PJ7_OUT, PJ7_IN, 0, ++ PJ6_FN, PJ6_OUT, PJ6_IN, 0, ++ PJ5_FN, PJ5_OUT, PJ5_IN, 0, ++ PJ4_FN, PJ4_OUT, PJ4_IN, 0, ++ PJ3_FN, PJ3_OUT, PJ3_IN, 0, ++ PJ2_FN, PJ2_OUT, PJ2_IN, 0, ++ PJ1_FN, PJ1_OUT, PJ1_IN, 0, + 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG("P1MSELR", 0xffcc0080, 16, 1) { +@@ -822,7 +803,6 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { + const struct sh_pfc_soc_info sh7786_pinmux_info = { + .name = "sh7786_pfc", + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, +- .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0535-sh-pfc-shx3-Remove-unused-input_pu-range.patch b/patches.renesas/0535-sh-pfc-shx3-Remove-unused-input_pu-range.patch new file mode 100644 index 00000000000..6ee76835257 --- /dev/null +++ b/patches.renesas/0535-sh-pfc-shx3-Remove-unused-input_pu-range.patch @@ -0,0 +1,347 @@ +From a5a537442dd969813778ef269b4ff370879bcb32 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 16 Jul 2013 01:54:13 +0200 +Subject: sh-pfc: shx3: Remove unused input_pu range + +The PFC SHX3 SoC data contains a input_pu range used to configure +pull-up resistors using the legacy non-pinconf API. That API has been +removed from the driver, the range is thus not used anymore. Remove it. + +If required, configuring pull-up resistors for the SHX3 can be +implemented using the pinconf API, as done for the SH-Mobile, R-Mobile +and R-Car platforms. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit 4e5ca4a1e65d6c9f7a26b8af26ec6cf1c516f31b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-shx3.c | 270 +++++++++++++++++--------------------- + 1 file changed, 124 insertions(+), 146 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-shx3.c b/drivers/pinctrl/sh-pfc/pfc-shx3.c +index 6594c8c4..50d9c5d8 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-shx3.c ++++ b/drivers/pinctrl/sh-pfc/pfc-shx3.c +@@ -56,26 +56,6 @@ enum { + PH3_IN, PH2_IN, PH1_IN, PH0_IN, + PINMUX_INPUT_END, + +- PINMUX_INPUT_PULLUP_BEGIN, +- PA7_IN_PU, PA6_IN_PU, PA5_IN_PU, PA4_IN_PU, +- PA3_IN_PU, PA2_IN_PU, PA1_IN_PU, PA0_IN_PU, +- PB7_IN_PU, PB6_IN_PU, PB5_IN_PU, PB4_IN_PU, +- PB3_IN_PU, PB2_IN_PU, PB1_IN_PU, PB0_IN_PU, +- PC7_IN_PU, PC6_IN_PU, PC5_IN_PU, PC4_IN_PU, +- PC3_IN_PU, PC2_IN_PU, PC1_IN_PU, PC0_IN_PU, +- PD7_IN_PU, PD6_IN_PU, PD5_IN_PU, PD4_IN_PU, +- PD3_IN_PU, PD2_IN_PU, PD1_IN_PU, PD0_IN_PU, +- PE7_IN_PU, PE6_IN_PU, PE5_IN_PU, PE4_IN_PU, +- PE3_IN_PU, PE2_IN_PU, PE1_IN_PU, PE0_IN_PU, +- PF7_IN_PU, PF6_IN_PU, PF5_IN_PU, PF4_IN_PU, +- PF3_IN_PU, PF2_IN_PU, PF1_IN_PU, PF0_IN_PU, +- PG7_IN_PU, PG6_IN_PU, PG5_IN_PU, PG4_IN_PU, +- PG3_IN_PU, PG2_IN_PU, PG1_IN_PU, PG0_IN_PU, +- +- PH5_IN_PU, PH4_IN_PU, +- PH3_IN_PU, PH2_IN_PU, PH1_IN_PU, PH0_IN_PU, +- PINMUX_INPUT_PULLUP_END, +- + PINMUX_OUTPUT_BEGIN, + PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT, + PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT, +@@ -150,82 +130,82 @@ enum { + static const pinmux_enum_t shx3_pinmux_data[] = { + + /* PA GPIO */ +- PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU), +- PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT, PA6_IN_PU), +- PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT, PA5_IN_PU), +- PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT, PA4_IN_PU), +- PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT, PA3_IN_PU), +- PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT, PA2_IN_PU), +- PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT, PA1_IN_PU), +- PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT, PA0_IN_PU), ++ PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT), ++ PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT), ++ PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT), ++ PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT), ++ PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT), ++ PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT), ++ PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT), ++ PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT), + + /* PB GPIO */ +- PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT, PB7_IN_PU), +- PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT, PB6_IN_PU), +- PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT, PB5_IN_PU), +- PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT, PB4_IN_PU), +- PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT, PB3_IN_PU), +- PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT, PB2_IN_PU), +- PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT, PB1_IN_PU), +- PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT, PB0_IN_PU), ++ PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT), ++ PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT), ++ PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT), ++ PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT), ++ PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT), ++ PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT), ++ PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT), ++ PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT), + + /* PC GPIO */ +- PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT, PC7_IN_PU), +- PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT, PC6_IN_PU), +- PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT, PC5_IN_PU), +- PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT, PC4_IN_PU), +- PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT, PC3_IN_PU), +- PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT, PC2_IN_PU), +- PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT, PC1_IN_PU), +- PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT, PC0_IN_PU), ++ PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT), ++ PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT), ++ PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT), ++ PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT), ++ PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT), ++ PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT), ++ PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT), ++ PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT), + + /* PD GPIO */ +- PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT, PD7_IN_PU), +- PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT, PD6_IN_PU), +- PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT, PD5_IN_PU), +- PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT, PD4_IN_PU), +- PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT, PD3_IN_PU), +- PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT, PD2_IN_PU), +- PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT, PD1_IN_PU), +- PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT, PD0_IN_PU), ++ PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT), ++ PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT), ++ PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT), ++ PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT), ++ PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT), ++ PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT), ++ PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT), ++ PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT), + + /* PE GPIO */ +- PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT, PE7_IN_PU), +- PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT, PE6_IN_PU), +- PINMUX_DATA(PE5_DATA, PE5_IN, PE5_OUT, PE5_IN_PU), +- PINMUX_DATA(PE4_DATA, PE4_IN, PE4_OUT, PE4_IN_PU), +- PINMUX_DATA(PE3_DATA, PE3_IN, PE3_OUT, PE3_IN_PU), +- PINMUX_DATA(PE2_DATA, PE2_IN, PE2_OUT, PE2_IN_PU), +- PINMUX_DATA(PE1_DATA, PE1_IN, PE1_OUT, PE1_IN_PU), +- PINMUX_DATA(PE0_DATA, PE0_IN, PE0_OUT, PE0_IN_PU), ++ PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT), ++ PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT), ++ PINMUX_DATA(PE5_DATA, PE5_IN, PE5_OUT), ++ PINMUX_DATA(PE4_DATA, PE4_IN, PE4_OUT), ++ PINMUX_DATA(PE3_DATA, PE3_IN, PE3_OUT), ++ PINMUX_DATA(PE2_DATA, PE2_IN, PE2_OUT), ++ PINMUX_DATA(PE1_DATA, PE1_IN, PE1_OUT), ++ PINMUX_DATA(PE0_DATA, PE0_IN, PE0_OUT), + + /* PF GPIO */ +- PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT, PF7_IN_PU), +- PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT, PF6_IN_PU), +- PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT, PF5_IN_PU), +- PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT, PF4_IN_PU), +- PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT, PF3_IN_PU), +- PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT, PF2_IN_PU), +- PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT, PF1_IN_PU), +- PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT, PF0_IN_PU), ++ PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT), ++ PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT), ++ PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT), ++ PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT), ++ PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT), ++ PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT), ++ PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT), ++ PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT), + + /* PG GPIO */ +- PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT, PG7_IN_PU), +- PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT, PG6_IN_PU), +- PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT, PG5_IN_PU), +- PINMUX_DATA(PG4_DATA, PG4_IN, PG4_OUT, PG4_IN_PU), +- PINMUX_DATA(PG3_DATA, PG3_IN, PG3_OUT, PG3_IN_PU), +- PINMUX_DATA(PG2_DATA, PG2_IN, PG2_OUT, PG2_IN_PU), +- PINMUX_DATA(PG1_DATA, PG1_IN, PG1_OUT, PG1_IN_PU), +- PINMUX_DATA(PG0_DATA, PG0_IN, PG0_OUT, PG0_IN_PU), ++ PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT), ++ PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT), ++ PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT), ++ PINMUX_DATA(PG4_DATA, PG4_IN, PG4_OUT), ++ PINMUX_DATA(PG3_DATA, PG3_IN, PG3_OUT), ++ PINMUX_DATA(PG2_DATA, PG2_IN, PG2_OUT), ++ PINMUX_DATA(PG1_DATA, PG1_IN, PG1_OUT), ++ PINMUX_DATA(PG0_DATA, PG0_IN, PG0_OUT), + + /* PH GPIO */ +- PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT, PH5_IN_PU), +- PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT, PH4_IN_PU), +- PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT, PH3_IN_PU), +- PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT, PH2_IN_PU), +- PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT, PH1_IN_PU), +- PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT, PH0_IN_PU), ++ PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT), ++ PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT), ++ PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT), ++ PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT), ++ PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT), ++ PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT), + + /* PA FN */ + PINMUX_DATA(D31_MARK, PA7_FN), +@@ -456,76 +436,76 @@ static const struct pinmux_func shx3_pinmux_func_gpios[] = { + + static const struct pinmux_cfg_reg shx3_pinmux_config_regs[] = { + { PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2) { +- PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU, +- PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU, +- PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU, +- PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU, +- PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU, +- PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU, +- PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU, +- PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU, +- PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU, +- PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU, +- PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU, +- PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU, +- PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU, +- PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU, +- PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU, +- PB0_FN, PB0_OUT, PB0_IN, PB0_IN_PU, }, ++ PA7_FN, PA7_OUT, PA7_IN, 0, ++ PA6_FN, PA6_OUT, PA6_IN, 0, ++ PA5_FN, PA5_OUT, PA5_IN, 0, ++ PA4_FN, PA4_OUT, PA4_IN, 0, ++ PA3_FN, PA3_OUT, PA3_IN, 0, ++ PA2_FN, PA2_OUT, PA2_IN, 0, ++ PA1_FN, PA1_OUT, PA1_IN, 0, ++ PA0_FN, PA0_OUT, PA0_IN, 0, ++ PB7_FN, PB7_OUT, PB7_IN, 0, ++ PB6_FN, PB6_OUT, PB6_IN, 0, ++ PB5_FN, PB5_OUT, PB5_IN, 0, ++ PB4_FN, PB4_OUT, PB4_IN, 0, ++ PB3_FN, PB3_OUT, PB3_IN, 0, ++ PB2_FN, PB2_OUT, PB2_IN, 0, ++ PB1_FN, PB1_OUT, PB1_IN, 0, ++ PB0_FN, PB0_OUT, PB0_IN, 0, }, + }, + { PINMUX_CFG_REG("PCDCR", 0xffc70004, 32, 2) { +- PC7_FN, PC7_OUT, PC7_IN, PC7_IN_PU, +- PC6_FN, PC6_OUT, PC6_IN, PC6_IN_PU, +- PC5_FN, PC5_OUT, PC5_IN, PC5_IN_PU, +- PC4_FN, PC4_OUT, PC4_IN, PC4_IN_PU, +- PC3_FN, PC3_OUT, PC3_IN, PC3_IN_PU, +- PC2_FN, PC2_OUT, PC2_IN, PC2_IN_PU, +- PC1_FN, PC1_OUT, PC1_IN, PC1_IN_PU, +- PC0_FN, PC0_OUT, PC0_IN, PC0_IN_PU, +- PD7_FN, PD7_OUT, PD7_IN, PD7_IN_PU, +- PD6_FN, PD6_OUT, PD6_IN, PD6_IN_PU, +- PD5_FN, PD5_OUT, PD5_IN, PD5_IN_PU, +- PD4_FN, PD4_OUT, PD4_IN, PD4_IN_PU, +- PD3_FN, PD3_OUT, PD3_IN, PD3_IN_PU, +- PD2_FN, PD2_OUT, PD2_IN, PD2_IN_PU, +- PD1_FN, PD1_OUT, PD1_IN, PD1_IN_PU, +- PD0_FN, PD0_OUT, PD0_IN, PD0_IN_PU, }, ++ PC7_FN, PC7_OUT, PC7_IN, 0, ++ PC6_FN, PC6_OUT, PC6_IN, 0, ++ PC5_FN, PC5_OUT, PC5_IN, 0, ++ PC4_FN, PC4_OUT, PC4_IN, 0, ++ PC3_FN, PC3_OUT, PC3_IN, 0, ++ PC2_FN, PC2_OUT, PC2_IN, 0, ++ PC1_FN, PC1_OUT, PC1_IN, 0, ++ PC0_FN, PC0_OUT, PC0_IN, 0, ++ PD7_FN, PD7_OUT, PD7_IN, 0, ++ PD6_FN, PD6_OUT, PD6_IN, 0, ++ PD5_FN, PD5_OUT, PD5_IN, 0, ++ PD4_FN, PD4_OUT, PD4_IN, 0, ++ PD3_FN, PD3_OUT, PD3_IN, 0, ++ PD2_FN, PD2_OUT, PD2_IN, 0, ++ PD1_FN, PD1_OUT, PD1_IN, 0, ++ PD0_FN, PD0_OUT, PD0_IN, 0, }, + }, + { PINMUX_CFG_REG("PEFCR", 0xffc70008, 32, 2) { +- PE7_FN, PE7_OUT, PE7_IN, PE7_IN_PU, +- PE6_FN, PE6_OUT, PE6_IN, PE6_IN_PU, +- PE5_FN, PE5_OUT, PE5_IN, PE5_IN_PU, +- PE4_FN, PE4_OUT, PE4_IN, PE4_IN_PU, +- PE3_FN, PE3_OUT, PE3_IN, PE3_IN_PU, +- PE2_FN, PE2_OUT, PE2_IN, PE2_IN_PU, +- PE1_FN, PE1_OUT, PE1_IN, PE1_IN_PU, +- PE0_FN, PE0_OUT, PE0_IN, PE0_IN_PU, +- PF7_FN, PF7_OUT, PF7_IN, PF7_IN_PU, +- PF6_FN, PF6_OUT, PF6_IN, PF6_IN_PU, +- PF5_FN, PF5_OUT, PF5_IN, PF5_IN_PU, +- PF4_FN, PF4_OUT, PF4_IN, PF4_IN_PU, +- PF3_FN, PF3_OUT, PF3_IN, PF3_IN_PU, +- PF2_FN, PF2_OUT, PF2_IN, PF2_IN_PU, +- PF1_FN, PF1_OUT, PF1_IN, PF1_IN_PU, +- PF0_FN, PF0_OUT, PF0_IN, PF0_IN_PU, }, ++ PE7_FN, PE7_OUT, PE7_IN, 0, ++ PE6_FN, PE6_OUT, PE6_IN, 0, ++ PE5_FN, PE5_OUT, PE5_IN, 0, ++ PE4_FN, PE4_OUT, PE4_IN, 0, ++ PE3_FN, PE3_OUT, PE3_IN, 0, ++ PE2_FN, PE2_OUT, PE2_IN, 0, ++ PE1_FN, PE1_OUT, PE1_IN, 0, ++ PE0_FN, PE0_OUT, PE0_IN, 0, ++ PF7_FN, PF7_OUT, PF7_IN, 0, ++ PF6_FN, PF6_OUT, PF6_IN, 0, ++ PF5_FN, PF5_OUT, PF5_IN, 0, ++ PF4_FN, PF4_OUT, PF4_IN, 0, ++ PF3_FN, PF3_OUT, PF3_IN, 0, ++ PF2_FN, PF2_OUT, PF2_IN, 0, ++ PF1_FN, PF1_OUT, PF1_IN, 0, ++ PF0_FN, PF0_OUT, PF0_IN, 0, }, + }, + { PINMUX_CFG_REG("PGHCR", 0xffc7000c, 32, 2) { +- PG7_FN, PG7_OUT, PG7_IN, PG7_IN_PU, +- PG6_FN, PG6_OUT, PG6_IN, PG6_IN_PU, +- PG5_FN, PG5_OUT, PG5_IN, PG5_IN_PU, +- PG4_FN, PG4_OUT, PG4_IN, PG4_IN_PU, +- PG3_FN, PG3_OUT, PG3_IN, PG3_IN_PU, +- PG2_FN, PG2_OUT, PG2_IN, PG2_IN_PU, +- PG1_FN, PG1_OUT, PG1_IN, PG1_IN_PU, +- PG0_FN, PG0_OUT, PG0_IN, PG0_IN_PU, ++ PG7_FN, PG7_OUT, PG7_IN, 0, ++ PG6_FN, PG6_OUT, PG6_IN, 0, ++ PG5_FN, PG5_OUT, PG5_IN, 0, ++ PG4_FN, PG4_OUT, PG4_IN, 0, ++ PG3_FN, PG3_OUT, PG3_IN, 0, ++ PG2_FN, PG2_OUT, PG2_IN, 0, ++ PG1_FN, PG1_OUT, PG1_IN, 0, ++ PG0_FN, PG0_OUT, PG0_IN, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, +- PH5_FN, PH5_OUT, PH5_IN, PH5_IN_PU, +- PH4_FN, PH4_OUT, PH4_IN, PH4_IN_PU, +- PH3_FN, PH3_OUT, PH3_IN, PH3_IN_PU, +- PH2_FN, PH2_OUT, PH2_IN, PH2_IN_PU, +- PH1_FN, PH1_OUT, PH1_IN, PH1_IN_PU, +- PH0_FN, PH0_OUT, PH0_IN, PH0_IN_PU, }, ++ PH5_FN, PH5_OUT, PH5_IN, 0, ++ PH4_FN, PH4_OUT, PH4_IN, 0, ++ PH3_FN, PH3_OUT, PH3_IN, 0, ++ PH2_FN, PH2_OUT, PH2_IN, 0, ++ PH1_FN, PH1_OUT, PH1_IN, 0, ++ PH0_FN, PH0_OUT, PH0_IN, 0, }, + }, + { }, + }; +@@ -569,8 +549,6 @@ static const struct pinmux_data_reg shx3_pinmux_data_regs[] = { + const struct sh_pfc_soc_info shx3_pinmux_info = { + .name = "shx3_pfc", + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, +- .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, +- PINMUX_INPUT_PULLUP_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + .pins = shx3_pinmux_pins, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0536-sh-pfc-Remove-unused-input_pd-and-input_pu-ranges.patch b/patches.renesas/0536-sh-pfc-Remove-unused-input_pd-and-input_pu-ranges.patch new file mode 100644 index 00000000000..87db9ef7e6d --- /dev/null +++ b/patches.renesas/0536-sh-pfc-Remove-unused-input_pd-and-input_pu-ranges.patch @@ -0,0 +1,60 @@ +From 1ad4494de598849e03e68aed52ffe43cdc4874f3 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 16 Jul 2013 02:01:00 +0200 +Subject: sh-pfc: Remove unused input_pd and input_pu ranges + +The ranges are not used anymore, remove them. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com> +(cherry picked from commit 75906431564c85738189a000e6e81c29123c61da) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/core.c | 8 -------- + drivers/pinctrl/sh-pfc/sh_pfc.h | 4 ---- + 2 files changed, 12 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c +index f3fc66b2..1c8597cf 100644 +--- a/drivers/pinctrl/sh-pfc/core.c ++++ b/drivers/pinctrl/sh-pfc/core.c +@@ -283,14 +283,6 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) + range = &pfc->info->input; + break; + +- case PINMUX_TYPE_INPUT_PULLUP: +- range = &pfc->info->input_pu; +- break; +- +- case PINMUX_TYPE_INPUT_PULLDOWN: +- range = &pfc->info->input_pd; +- break; +- + default: + return -EINVAL; + } +diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h +index 830ae1ff..64219f6b 100644 +--- a/drivers/pinctrl/sh-pfc/sh_pfc.h ++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h +@@ -25,8 +25,6 @@ enum { + PINMUX_TYPE_GPIO, + PINMUX_TYPE_OUTPUT, + PINMUX_TYPE_INPUT, +- PINMUX_TYPE_INPUT_PULLUP, +- PINMUX_TYPE_INPUT_PULLDOWN, + + PINMUX_FLAG_TYPE, /* must be last */ + }; +@@ -141,8 +139,6 @@ struct sh_pfc_soc_info { + const struct sh_pfc_soc_operations *ops; + + struct pinmux_range input; +- struct pinmux_range input_pd; +- struct pinmux_range input_pu; + struct pinmux_range output; + struct pinmux_range function; + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0537-sh-pfc-Remove-unused-PORT_DATA_-macros.patch b/patches.renesas/0537-sh-pfc-Remove-unused-PORT_DATA_-macros.patch new file mode 100644 index 00000000000..9e0b2b053cd --- /dev/null +++ b/patches.renesas/0537-sh-pfc-Remove-unused-PORT_DATA_-macros.patch @@ -0,0 +1,63 @@ +From 2d01248af781e3a88a679ae9c56e66e5991965ae Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Sun, 14 Jul 2013 19:58:57 +0200 +Subject: sh-pfc: Remove unused PORT_DATA_* macros + +Most of the PORT_DATA_* macros are not used, remove them. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com> +(cherry picked from commit b7e760e0b80ba236b5db96e921c5a8fc3d61f2af) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/sh_pfc.h | 30 ------------------------------ + 1 file changed, 30 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h +index 64219f6b..0e3e00fa 100644 +--- a/drivers/pinctrl/sh-pfc/sh_pfc.h ++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h +@@ -209,40 +209,10 @@ enum { GPIO_CFG_REQ, GPIO_CFG_FREE }; + #define GPIO_FN(str) PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK) + + /* helper macro for pinmux_enum_t */ +-#define PORT_DATA_I(nr) \ +- PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN) +- +-#define PORT_DATA_I_PD(nr) \ +- PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ +- PORT##nr##_IN, PORT##nr##_IN_PD) +- +-#define PORT_DATA_I_PU(nr) \ +- PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ +- PORT##nr##_IN, PORT##nr##_IN_PU) +- +-#define PORT_DATA_I_PU_PD(nr) \ +- PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ +- PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU) +- +-#define PORT_DATA_O(nr) \ +- PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT) +- + #define PORT_DATA_IO(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ + PORT##nr##_IN) + +-#define PORT_DATA_IO_PD(nr) \ +- PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ +- PORT##nr##_IN, PORT##nr##_IN_PD) +- +-#define PORT_DATA_IO_PU(nr) \ +- PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ +- PORT##nr##_IN, PORT##nr##_IN_PU) +- +-#define PORT_DATA_IO_PU_PD(nr) \ +- PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ +- PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU) +- + /* helper macro for top 4 bits in PORTnCR */ + #define _PCRH(in, in_pd, in_pu, out) \ + 0, (out), (in), 0, \ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0538-sh-pfc-Remove-unused-macro-and-enum-entries.patch b/patches.renesas/0538-sh-pfc-Remove-unused-macro-and-enum-entries.patch new file mode 100644 index 00000000000..a84e51a8bbc --- /dev/null +++ b/patches.renesas/0538-sh-pfc-Remove-unused-macro-and-enum-entries.patch @@ -0,0 +1,50 @@ +From d90b807f45429fd19ea5be604e73d3457d83c921 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Sun, 14 Jul 2013 19:59:50 +0200 +Subject: sh-pfc: Remove unused macro and enum entries + +The SH_PFC_MARK_INVALID macro and the PINMUX_FLAG_TYPE, GPIO_CFG_REQ and +GPIO_CFG_FREE enum entries are used, remove them. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com> +(cherry picked from commit 487bca0390ad8f78ab9e885897e72218ef704ff5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/sh_pfc.h | 7 ------- + 1 file changed, 7 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h +index 0e3e00fa..d0a8ff8d 100644 +--- a/drivers/pinctrl/sh-pfc/sh_pfc.h ++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h +@@ -16,17 +16,12 @@ + + typedef unsigned short pinmux_enum_t; + +-#define SH_PFC_MARK_INVALID ((pinmux_enum_t)-1) +- + enum { + PINMUX_TYPE_NONE, +- + PINMUX_TYPE_FUNCTION, + PINMUX_TYPE_GPIO, + PINMUX_TYPE_OUTPUT, + PINMUX_TYPE_INPUT, +- +- PINMUX_FLAG_TYPE, /* must be last */ + }; + + #define SH_PFC_PIN_CFG_INPUT (1 << 0) +@@ -166,8 +161,6 @@ struct sh_pfc_soc_info { + unsigned long unlock_reg; + }; + +-enum { GPIO_CFG_REQ, GPIO_CFG_FREE }; +- + /* helper macro for port */ + #define PORT_1(fn, pfx, sfx) fn(pfx, sfx) + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0539-sh-pfc-Remove-unneeded-const-keywords.patch b/patches.renesas/0539-sh-pfc-Remove-unneeded-const-keywords.patch new file mode 100644 index 00000000000..1c611aeba4e --- /dev/null +++ b/patches.renesas/0539-sh-pfc-Remove-unneeded-const-keywords.patch @@ -0,0 +1,41 @@ +From b88e8e5782a03c7a22ab5ea705eaa224eab0bfe4 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Sun, 14 Jul 2013 20:04:53 +0200 +Subject: sh-pfc: Remove unneeded const keywords + +Two integer field structures are needlesly defined as const. Remove the +const keyword. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com> +(cherry picked from commit 94e74601384da5605087c176501e4fb17d7c4252) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/sh_pfc.h | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h +index d0a8ff8d..2105487d 100644 +--- a/drivers/pinctrl/sh-pfc/sh_pfc.h ++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h +@@ -30,7 +30,7 @@ enum { + #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3) + + struct sh_pfc_pin { +- const pinmux_enum_t enum_id; ++ pinmux_enum_t enum_id; + const char *name; + unsigned int configs; + }; +@@ -64,7 +64,7 @@ struct sh_pfc_function { + }; + + struct pinmux_func { +- const pinmux_enum_t enum_id; ++ pinmux_enum_t enum_id; + const char *name; + }; + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0540-sh-pfc-Remove-unused-GPIO_PORT_ALL-macro.patch b/patches.renesas/0540-sh-pfc-Remove-unused-GPIO_PORT_ALL-macro.patch new file mode 100644 index 00000000000..bc30fefd159 --- /dev/null +++ b/patches.renesas/0540-sh-pfc-Remove-unused-GPIO_PORT_ALL-macro.patch @@ -0,0 +1,70 @@ +From 213552740f10bd12e534291c9433f42034c8bf4b Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 15 Jul 2013 15:21:28 +0200 +Subject: sh-pfc: Remove unused GPIO_PORT_ALL macro + +The macro isn't used, remove it. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com> +(cherry picked from commit 08d3868ec7644e142a63652b01bc7c12b0f6ed75) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 7 ------- + drivers/pinctrl/sh-pfc/pfc-sh7372.c | 7 ------- + drivers/pinctrl/sh-pfc/sh_pfc.h | 2 -- + 3 files changed, 16 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +index f6ea47c4..3fb1e0b4 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +@@ -34,13 +34,6 @@ + PORT_10(fn, pfx##20, sfx), \ + PORT_1(fn, pfx##210, sfx), PORT_1(fn, pfx##211, sfx) + +-#undef _GPIO_PORT +-#define _GPIO_PORT(gpio, sfx) \ +- [gpio] = { \ +- .name = __stringify(PORT##gpio), \ +- .enum_id = PORT##gpio##_DATA, \ +- } +- + #define IRQC_PIN_MUX(irq, pin) \ + static const unsigned int intc_irq##irq##_pins[] = { \ + pin, \ +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +index 6dfb1877..cd431e45 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +@@ -38,13 +38,6 @@ + PORT_10(fn, pfx##16, sfx), PORT_10(fn, pfx##17, sfx), \ + PORT_10(fn, pfx##18, sfx), PORT_1(fn, pfx##190, sfx) + +-#undef _GPIO_PORT +-#define _GPIO_PORT(gpio, sfx) \ +- [gpio] = { \ +- .name = __stringify(PORT##gpio), \ +- .enum_id = PORT##gpio##_DATA, \ +- } +- + #define IRQC_PIN_MUX(irq, pin) \ + static const unsigned int intc_irq##irq##_pins[] = { \ + pin, \ +diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h +index 2105487d..363ea8cb 100644 +--- a/drivers/pinctrl/sh-pfc/sh_pfc.h ++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h +@@ -196,9 +196,7 @@ struct sh_pfc_soc_info { + PORT_10(fn, pfx##9, sfx) + + #define _PORT_ALL(pfx, sfx) pfx##_##sfx +-#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA) + #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str) +-#define GPIO_PORT_ALL() CPU_ALL_PORT(_GPIO_PORT, , unused) + #define GPIO_FN(str) PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK) + + /* helper macro for pinmux_enum_t */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0541-sh-pfc-Don-t-overallocate-memory-for-the-GPIO-chip-p.patch b/patches.renesas/0541-sh-pfc-Don-t-overallocate-memory-for-the-GPIO-chip-p.patch new file mode 100644 index 00000000000..c73006ab1cd --- /dev/null +++ b/patches.renesas/0541-sh-pfc-Don-t-overallocate-memory-for-the-GPIO-chip-p.patch @@ -0,0 +1,36 @@ +From 3aaf4b15a4e3d742d2206a0ae15c7480caccc38e Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 15 Jul 2013 13:36:39 +0200 +Subject: sh-pfc: Don't overallocate memory for the GPIO chip pins array + +The GPIO driver uses an array of sh_pfc_gpio_pin structures to store +per-GPIO pin data. The array size is miscomputed at allocation time by +using the number of the last pin instead of the number of pins. When the +pin space contains holes this leads to memory overallocation. Fix it. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com> +(cherry picked from commit a1a3580cb322f71cc5aa7e9180ffb6df609b530d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/gpio.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c +index d37efa7d..3620bd84 100644 +--- a/drivers/pinctrl/sh-pfc/gpio.c ++++ b/drivers/pinctrl/sh-pfc/gpio.c +@@ -224,8 +224,8 @@ static int gpio_pin_setup(struct sh_pfc_chip *chip) + struct gpio_chip *gc = &chip->gpio_chip; + int ret; + +- chip->pins = devm_kzalloc(pfc->dev, pfc->nr_pins * sizeof(*chip->pins), +- GFP_KERNEL); ++ chip->pins = devm_kzalloc(pfc->dev, pfc->info->nr_pins * ++ sizeof(*chip->pins), GFP_KERNEL); + if (chip->pins == NULL) + return -ENOMEM; + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0542-sh-pfc-Replace-pinmux_enum_id-typedef-with-u16.patch b/patches.renesas/0542-sh-pfc-Replace-pinmux_enum_id-typedef-with-u16.patch new file mode 100644 index 00000000000..5cd6637c8aa --- /dev/null +++ b/patches.renesas/0542-sh-pfc-Replace-pinmux_enum_id-typedef-with-u16.patch @@ -0,0 +1,435 @@ +From 3bc0be9adb3e83cd2f4518569fbdfb521973a80c Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 15 Jul 2013 13:03:20 +0200 +Subject: sh-pfc: Replace pinmux_enum_id typedef with u16 + +The typedef only conceals the real variable type without bringing any +additional value (see Documentation/CodingStyle, section 5.b). Moreover, +it polutes the pinmux namespace. Replace it with the integer type it +used to hide. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com> +(cherry picked from commit 533743dccb517b0331eccc111e3c2b8f021559b5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/core.c | 13 ++++++------- + drivers/pinctrl/sh-pfc/pfc-r8a73a4.c | 2 +- + drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 2 +- + drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 2 +- + drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 2 +- + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 2 +- + drivers/pinctrl/sh-pfc/pfc-sh7203.c | 3 +-- + drivers/pinctrl/sh-pfc/pfc-sh7264.c | 3 +-- + drivers/pinctrl/sh-pfc/pfc-sh7269.c | 3 +-- + drivers/pinctrl/sh-pfc/pfc-sh7372.c | 2 +- + drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 2 +- + drivers/pinctrl/sh-pfc/pfc-sh7720.c | 2 +- + drivers/pinctrl/sh-pfc/pfc-sh7722.c | 2 +- + drivers/pinctrl/sh-pfc/pfc-sh7723.c | 2 +- + drivers/pinctrl/sh-pfc/pfc-sh7724.c | 2 +- + drivers/pinctrl/sh-pfc/pfc-sh7734.c | 2 +- + drivers/pinctrl/sh-pfc/pfc-sh7757.c | 2 +- + drivers/pinctrl/sh-pfc/pfc-sh7785.c | 3 +-- + drivers/pinctrl/sh-pfc/pfc-sh7786.c | 3 +-- + drivers/pinctrl/sh-pfc/pfc-shx3.c | 3 +-- + drivers/pinctrl/sh-pfc/sh_pfc.h | 26 ++++++++++++-------------- + 21 files changed, 37 insertions(+), 46 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c +index 1c8597cf..96b02246 100644 +--- a/drivers/pinctrl/sh-pfc/core.c ++++ b/drivers/pinctrl/sh-pfc/core.c +@@ -98,8 +98,7 @@ int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin) + return -EINVAL; + } + +-static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, +- const struct pinmux_range *r) ++static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r) + { + if (enum_id < r->begin) + return 0; +@@ -194,7 +193,7 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc, + sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data); + } + +-static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id, ++static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id, + const struct pinmux_cfg_reg **crp, int *fieldp, + int *valuep) + { +@@ -238,10 +237,10 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id, + return -EINVAL; + } + +-static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos, +- pinmux_enum_t *enum_idp) ++static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos, ++ u16 *enum_idp) + { +- const pinmux_enum_t *data = pfc->info->gpio_data; ++ const u16 *data = pfc->info->gpio_data; + int k; + + if (pos) { +@@ -264,7 +263,7 @@ static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos, + int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) + { + const struct pinmux_cfg_reg *cr = NULL; +- pinmux_enum_t enum_id; ++ u16 enum_id; + const struct pinmux_range *range; + int in_range, pos, field, value; + int ret; +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +index 82bf6aba..d5cbbc72 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +@@ -431,7 +431,7 @@ enum { + #define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx) + #define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) + +-static const pinmux_enum_t pinmux_data[] = { ++static const u16 pinmux_data[] = { + /* specify valid pin states for each pin in GPIO mode */ + PINMUX_DATA_ALL(), + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +index 3fb1e0b4..214ac6ce 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +@@ -586,7 +586,7 @@ enum { + #define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx) + #define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) + +-static const pinmux_enum_t pinmux_data[] = { ++static const u16 pinmux_data[] = { + PINMUX_DATA_GP_ALL(), + + /* Port0 */ +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +index f9039102..018d8bcb 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +@@ -579,7 +579,7 @@ enum { + PINMUX_MARK_END, + }; + +-static const pinmux_enum_t pinmux_data[] = { ++static const u16 pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ + + PINMUX_DATA(PENC0_MARK, FN_PENC0), +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +index 8e22ca6c..290de9a9 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +@@ -664,7 +664,7 @@ enum { + PINMUX_MARK_END, + }; + +-static const pinmux_enum_t pinmux_data[] = { ++static const u16 pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ + + PINMUX_DATA(AVS1_MARK, FN_AVS1), +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +index 14f3ec26..3713c008 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -844,7 +844,7 @@ enum { + PINMUX_MARK_END, + }; + +-static const pinmux_enum_t pinmux_data[] = { ++static const u16 pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ + + PINMUX_DATA(VI1_DATA7_VI1_B7_MARK, FN_VI1_DATA7_VI1_B7), +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7203.c b/drivers/pinctrl/sh-pfc/pfc-sh7203.c +index f63d51dc..44878140 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7203.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7203.c +@@ -272,8 +272,7 @@ enum { + PINMUX_MARK_END, + }; + +-static const pinmux_enum_t pinmux_data[] = { +- ++static const u16 pinmux_data[] = { + /* PA */ + PINMUX_DATA(PA7_DATA, PA7_IN), + PINMUX_DATA(PA6_DATA, PA6_IN), +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c +index 28467524..641c6af3 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7264.c +@@ -604,8 +604,7 @@ enum { + PINMUX_MARK_END, + }; + +-static const pinmux_enum_t pinmux_data[] = { +- ++static const u16 pinmux_data[] = { + /* Port A */ + PINMUX_DATA(PA3_DATA, PA3_IN), + PINMUX_DATA(PA2_DATA, PA2_IN), +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c +index 4c401a74..415812ff 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7269.c +@@ -781,8 +781,7 @@ enum { + PINMUX_MARK_END, + }; + +-static const pinmux_enum_t pinmux_data[] = { +- ++static const u16 pinmux_data[] = { + /* Port A */ + PINMUX_DATA(PA1_DATA, PA1_IN), + PINMUX_DATA(PA0_DATA, PA0_IN), +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +index cd431e45..f269c46a 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +@@ -387,7 +387,7 @@ enum { + #define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx) + #define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) + +-static const pinmux_enum_t pinmux_data[] = { ++static const u16 pinmux_data[] = { + PINMUX_DATA_GP_ALL(), + + /* IRQ */ +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +index 31f7d0e0..7935afbe 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +@@ -469,7 +469,7 @@ enum { + #define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx) + #define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) + +-static const pinmux_enum_t pinmux_data[] = { ++static const u16 pinmux_data[] = { + /* specify valid pin states for each pin in GPIO mode */ + PINMUX_DATA_GP_ALL(), + +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7720.c b/drivers/pinctrl/sh-pfc/pfc-sh7720.c +index 3b96d612..1009fc9c 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7720.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7720.c +@@ -232,7 +232,7 @@ enum { + PINMUX_MARK_END, + }; + +-static const pinmux_enum_t pinmux_data[] = { ++static const u16 pinmux_data[] = { + /* PTA GPIO */ + PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT), + PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT), +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7722.c b/drivers/pinctrl/sh-pfc/pfc-sh7722.c +index 0982c4ff..0c8d011f 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7722.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7722.c +@@ -263,7 +263,7 @@ enum { + PINMUX_FUNCTION_END, + }; + +-static const pinmux_enum_t pinmux_data[] = { ++static const u16 pinmux_data[] = { + /* PTA */ + PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT), + PINMUX_DATA(PTA6_DATA, PTA6_IN), +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7723.c b/drivers/pinctrl/sh-pfc/pfc-sh7723.c +index da0dbb0b..853093ef 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7723.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7723.c +@@ -344,7 +344,7 @@ enum { + PINMUX_MARK_END, + }; + +-static const pinmux_enum_t pinmux_data[] = { ++static const u16 pinmux_data[] = { + /* PTA GPIO */ + PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT), + PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT), +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7724.c b/drivers/pinctrl/sh-pfc/pfc-sh7724.c +index e8563cf6..fe2693f6 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7724.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7724.c +@@ -526,7 +526,7 @@ enum { + PINMUX_MARK_END, + }; + +-static const pinmux_enum_t pinmux_data[] = { ++static const u16 pinmux_data[] = { + /* PTA GPIO */ + PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT), + PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT), +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c +index 2fd5b7d4..1e1e3e02 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c +@@ -592,7 +592,7 @@ enum { + PINMUX_MARK_END, + }; + +-static const pinmux_enum_t pinmux_data[] = { ++static const u16 pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ + + PINMUX_DATA(CLKOUT_MARK, FN_CLKOUT), +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7757.c b/drivers/pinctrl/sh-pfc/pfc-sh7757.c +index d974b085..f4271167 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7757.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7757.c +@@ -486,7 +486,7 @@ enum { + PINMUX_MARK_END, + }; + +-static const pinmux_enum_t pinmux_data[] = { ++static const u16 pinmux_data[] = { + /* PTA GPIO */ + PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT), + PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT), +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7785.c b/drivers/pinctrl/sh-pfc/pfc-sh7785.c +index ddae4260..209289c8 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7785.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7785.c +@@ -325,8 +325,7 @@ enum { + PINMUX_MARK_END, + }; + +-static const pinmux_enum_t pinmux_data[] = { +- ++static const u16 pinmux_data[] = { + /* PA GPIO */ + PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT), + PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT), +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7786.c b/drivers/pinctrl/sh-pfc/pfc-sh7786.c +index c855fca5..353fde1f 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7786.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7786.c +@@ -172,8 +172,7 @@ enum { + PINMUX_MARK_END, + }; + +-static const pinmux_enum_t pinmux_data[] = { +- ++static const u16 pinmux_data[] = { + /* PA GPIO */ + PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT), + PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT), +diff --git a/drivers/pinctrl/sh-pfc/pfc-shx3.c b/drivers/pinctrl/sh-pfc/pfc-shx3.c +index 50d9c5d8..48a6c60f 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-shx3.c ++++ b/drivers/pinctrl/sh-pfc/pfc-shx3.c +@@ -127,8 +127,7 @@ enum { + PINMUX_MARK_END, + }; + +-static const pinmux_enum_t shx3_pinmux_data[] = { +- ++static const u16 shx3_pinmux_data[] = { + /* PA GPIO */ + PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT), + PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT), +diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h +index 363ea8cb..7ad1b040 100644 +--- a/drivers/pinctrl/sh-pfc/sh_pfc.h ++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h +@@ -14,8 +14,6 @@ + #include <linux/bug.h> + #include <linux/stringify.h> + +-typedef unsigned short pinmux_enum_t; +- + enum { + PINMUX_TYPE_NONE, + PINMUX_TYPE_FUNCTION, +@@ -30,7 +28,7 @@ enum { + #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3) + + struct sh_pfc_pin { +- pinmux_enum_t enum_id; ++ u16 enum_id; + const char *name; + unsigned int configs; + }; +@@ -64,7 +62,7 @@ struct sh_pfc_function { + }; + + struct pinmux_func { +- pinmux_enum_t enum_id; ++ u16 enum_id; + const char *name; + }; + +@@ -83,27 +81,27 @@ struct pinmux_func { + + struct pinmux_cfg_reg { + unsigned long reg, reg_width, field_width; +- const pinmux_enum_t *enum_ids; ++ const u16 *enum_ids; + const unsigned long *var_field_width; + }; + + #define PINMUX_CFG_REG(name, r, r_width, f_width) \ + .reg = r, .reg_width = r_width, .field_width = f_width, \ +- .enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)]) ++ .enum_ids = (u16 [(r_width / f_width) * (1 << f_width)]) + + #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ + .reg = r, .reg_width = r_width, \ + .var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \ +- .enum_ids = (pinmux_enum_t []) ++ .enum_ids = (u16 []) + + struct pinmux_data_reg { + unsigned long reg, reg_width; +- const pinmux_enum_t *enum_ids; ++ const u16 *enum_ids; + }; + + #define PINMUX_DATA_REG(name, r, r_width) \ + .reg = r, .reg_width = r_width, \ +- .enum_ids = (pinmux_enum_t [r_width]) \ ++ .enum_ids = (u16 [r_width]) \ + + struct pinmux_irq { + int irq; +@@ -114,9 +112,9 @@ struct pinmux_irq { + { .irq = irq_nr, .gpios = (unsigned short []) { ids, 0 } } \ + + struct pinmux_range { +- pinmux_enum_t begin; +- pinmux_enum_t end; +- pinmux_enum_t force; ++ u16 begin; ++ u16 end; ++ u16 force; + }; + + struct sh_pfc; +@@ -152,7 +150,7 @@ struct sh_pfc_soc_info { + const struct pinmux_cfg_reg *cfg_regs; + const struct pinmux_data_reg *data_regs; + +- const pinmux_enum_t *gpio_data; ++ const u16 *gpio_data; + unsigned int gpio_data_size; + + const struct pinmux_irq *gpio_irq; +@@ -199,7 +197,7 @@ struct sh_pfc_soc_info { + #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str) + #define GPIO_FN(str) PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK) + +-/* helper macro for pinmux_enum_t */ ++/* helper macro for pinmux data arrays */ + #define PORT_DATA_IO(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ + PORT##nr##_IN) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0543-sh-pfc-Rename-gpio-arguments-to-be-consistent-with-t.patch b/patches.renesas/0543-sh-pfc-Rename-gpio-arguments-to-be-consistent-with-t.patch new file mode 100644 index 00000000000..55c471e5251 --- /dev/null +++ b/patches.renesas/0543-sh-pfc-Rename-gpio-arguments-to-be-consistent-with-t.patch @@ -0,0 +1,55 @@ +From 564b6f12caff523266575f11ffbab8c6a57b239e Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 15 Jul 2013 13:25:08 +0200 +Subject: sh-pfc: Rename gpio arguments to be consistent with the rest of the + code + +The gpio_get_data_reg() and gpio_setup_data_reg() functions both take an +argument named gpio. The argument contains a GPIO offset for the first +function and a pin index for the second one. Rename them to offset and +idx respectively to match the rest of the code. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com> +(cherry picked from commit 757b055a65c5e0f84185012ef45cc2e15a337b63) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/gpio.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c +index 3620bd84..87ae38b9 100644 +--- a/drivers/pinctrl/sh-pfc/gpio.c ++++ b/drivers/pinctrl/sh-pfc/gpio.c +@@ -48,11 +48,11 @@ static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc) + return gpio_to_pfc_chip(gc)->pfc; + } + +-static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int gpio, ++static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int offset, + struct sh_pfc_gpio_data_reg **reg, + unsigned int *bit) + { +- int idx = sh_pfc_get_pin_index(chip->pfc, gpio); ++ int idx = sh_pfc_get_pin_index(chip->pfc, offset); + struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx]; + + *reg = &chip->regs[gpio_pin->dreg]; +@@ -76,11 +76,11 @@ static void gpio_write_data_reg(struct sh_pfc_chip *chip, + sh_pfc_write_raw_reg(mem, dreg->reg_width, value); + } + +-static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned gpio) ++static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned idx) + { + struct sh_pfc *pfc = chip->pfc; +- struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[gpio]; +- const struct sh_pfc_pin *pin = &pfc->info->pins[gpio]; ++ struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx]; ++ const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; + const struct pinmux_data_reg *dreg; + unsigned int bit; + unsigned int i; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0544-sh-pfc-Consolidate-PFC-SoC-data-macros.patch b/patches.renesas/0544-sh-pfc-Consolidate-PFC-SoC-data-macros.patch new file mode 100644 index 00000000000..f0cfba80766 --- /dev/null +++ b/patches.renesas/0544-sh-pfc-Consolidate-PFC-SoC-data-macros.patch @@ -0,0 +1,542 @@ +From 72e83481d1fd361df8bbac5874cc25121d6b2682 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 15 Jul 2013 15:14:22 +0200 +Subject: sh-pfc: Consolidate PFC SoC data macros + +Move macros defined in several SoC data files to a common location and +document them. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com> +(cherry picked from commit e3d93b46718f12924128e5e70e2f3f992a95fa3b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a73a4.c | 3 - + drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 5 +- + drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 40 --------- + drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 61 +------------ + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 57 ------------ + drivers/pinctrl/sh-pfc/pfc-sh7372.c | 5 +- + drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 5 +- + drivers/pinctrl/sh-pfc/pfc-sh7734.c | 10 ++- + drivers/pinctrl/sh-pfc/sh_pfc.h | 168 +++++++++++++++++++++++++++-------- + 9 files changed, 140 insertions(+), 214 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +index d5cbbc72..d8115331 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +@@ -428,9 +428,6 @@ enum { + PINMUX_MARK_END, + }; + +-#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx) +-#define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) +- + static const u16 pinmux_data[] = { + /* specify valid pin states for each pin in GPIO mode */ + PINMUX_DATA_ALL(), +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +index 214ac6ce..e6900511 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +@@ -583,11 +583,8 @@ enum { + PINMUX_MARK_END, + }; + +-#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx) +-#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) +- + static const u16 pinmux_data[] = { +- PINMUX_DATA_GP_ALL(), ++ PINMUX_DATA_ALL(), + + /* Port0 */ + PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1), +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +index 018d8bcb..40aecfee 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +@@ -23,26 +23,6 @@ + #include <linux/kernel.h> + #include "sh_pfc.h" + +-#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx) +- +-#define PORT_GP_32(bank, fn, sfx) \ +- PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ +- PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ +- PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ +- PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ +- PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ +- PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ +- PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ +- PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ +- PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ +- PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ +- PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ +- PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ +- PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \ +- PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \ +- PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \ +- PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx) +- + #define PORT_GP_27(bank, fn, sfx) \ + PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ + PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ +@@ -66,26 +46,6 @@ + PORT_GP_32(3, fn, sfx), \ + PORT_GP_27(4, fn, sfx) + +-#define _GP_PORT_ALL(bank, pin, name, sfx) name##_##sfx +- +-#define _GP_GPIO(bank, pin, _name, sfx) \ +- [RCAR_GP_PIN(bank, pin)] = { \ +- .name = __stringify(_name), \ +- .enum_id = _name##_DATA, \ +- } +- +-#define _GP_DATA(bank, pin, name, sfx) \ +- PINMUX_DATA(name##_DATA, name##_FN) +- +-#define GP_ALL(str) CPU_ALL_PORT(_GP_PORT_ALL, str) +-#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused) +-#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused) +- +-#define PINMUX_IPSR_NOGP(ispr, fn) PINMUX_DATA(fn##_MARK, FN_##fn) +-#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr) +-#define PINMUX_IPSR_MSEL(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr, FN_##ms) +-#define PINMUX_IPSR_NOGM(ispr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ms) +- + enum { + PINMUX_RESERVED = 0, + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +index 290de9a9..be832dcd 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +@@ -24,51 +24,13 @@ + + #include "sh_pfc.h" + +-#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx) +- +-#define PORT_GP_32(bank, fn, sfx) \ +- PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ +- PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ +- PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ +- PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ +- PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ +- PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ +- PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ +- PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ +- PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ +- PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ +- PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ +- PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ +- PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \ +- PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \ +- PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \ +- PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx) +- +-#define PORT_GP_32_9(bank, fn, sfx) \ ++#define PORT_GP_9(bank, fn, sfx) \ + PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ + PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ + PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ + PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ + PORT_GP_1(bank, 8, fn, sfx) + +-#define PORT_GP_32_REV(bank, fn, sfx) \ +- PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \ +- PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \ +- PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \ +- PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \ +- PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \ +- PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \ +- PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \ +- PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \ +- PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \ +- PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \ +- PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \ +- PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \ +- PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \ +- PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \ +- PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \ +- PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx) +- + #define CPU_ALL_PORT(fn, sfx) \ + PORT_GP_32(0, fn, sfx), \ + PORT_GP_32(1, fn, sfx), \ +@@ -76,26 +38,7 @@ + PORT_GP_32(3, fn, sfx), \ + PORT_GP_32(4, fn, sfx), \ + PORT_GP_32(5, fn, sfx), \ +- PORT_GP_32_9(6, fn, sfx) +- +-#define _GP_PORT_ALL(bank, pin, name, sfx) name##_##sfx +- +-#define _GP_GPIO(bank, pin, _name, sfx) \ +- [RCAR_GP_PIN(bank, pin)] = { \ +- .name = __stringify(_name), \ +- .enum_id = _name##_DATA, \ +- } +- +-#define _GP_DATA(bank, pin, name, sfx) \ +- PINMUX_DATA(name##_DATA, name##_FN) +- +-#define GP_ALL(str) CPU_ALL_PORT(_GP_PORT_ALL, str) +-#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused) +-#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused) +- +-#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) +-#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ +- FN_##ipsr, FN_##fn) ++ PORT_GP_9(6, fn, sfx) + + enum { + PINMUX_RESERVED = 0, +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +index 3713c008..95b38faf 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -27,44 +27,6 @@ + #include "core.h" + #include "sh_pfc.h" + +-#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx) +- +-#define PORT_GP_32(bank, fn, sfx) \ +- PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ +- PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ +- PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ +- PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ +- PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ +- PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ +- PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ +- PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ +- PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ +- PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ +- PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ +- PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ +- PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \ +- PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \ +- PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \ +- PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx) +- +-#define PORT_GP_32_REV(bank, fn, sfx) \ +- PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \ +- PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \ +- PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \ +- PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \ +- PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \ +- PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \ +- PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \ +- PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \ +- PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \ +- PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \ +- PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \ +- PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \ +- PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \ +- PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \ +- PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \ +- PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx) +- + #define CPU_ALL_PORT(fn, sfx) \ + PORT_GP_32(0, fn, sfx), \ + PORT_GP_32(1, fn, sfx), \ +@@ -73,25 +35,6 @@ + PORT_GP_32(4, fn, sfx), \ + PORT_GP_32(5, fn, sfx) + +-#define _GP_PORT_ALL(bank, pin, name, sfx) name##_##sfx +- +-#define _GP_GPIO(bank, pin, _name, sfx) \ +- [(bank * 32) + pin] = { \ +- .name = __stringify(_name), \ +- .enum_id = _name##_DATA, \ +- } +- +-#define _GP_DATA(bank, pin, name, sfx) \ +- PINMUX_DATA(name##_DATA, name##_FN) +- +-#define GP_ALL(str) CPU_ALL_PORT(_GP_PORT_ALL, str) +-#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused) +-#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused) +- +-#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) +-#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ +- FN_##ipsr, FN_##fn) +- + enum { + PINMUX_RESERVED = 0, + +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +index f269c46a..9174ff26 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +@@ -384,11 +384,8 @@ enum { + PINMUX_MARK_END, + }; + +-#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx) +-#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) +- + static const u16 pinmux_data[] = { +- PINMUX_DATA_GP_ALL(), ++ PINMUX_DATA_ALL(), + + /* IRQ */ + PINMUX_DATA(IRQ0_6_MARK, PORT6_FN0, MSEL1CR_0_0), +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +index 7935afbe..b275e507 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +@@ -466,12 +466,9 @@ enum { + PINMUX_MARK_END, + }; + +-#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx) +-#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) +- + static const u16 pinmux_data[] = { + /* specify valid pin states for each pin in GPIO mode */ +- PINMUX_DATA_GP_ALL(), ++ PINMUX_DATA_ALL(), + + /* Table 25-1 (Function 0-7) */ + PINMUX_DATA(VBUS_0_MARK, PORT0_FN1), +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c +index 1e1e3e02..537a639e 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c +@@ -31,6 +31,12 @@ + PORT_32(fn, pfx##_4_, sfx), \ + CPU_32_PORT5(fn, pfx##_5_, sfx) + ++#undef _GP_GPIO ++#undef _GP_DATA ++#undef GP_ALL ++#undef PINMUX_GPIO_GP_ALL ++#undef PINMUX_DATA_GP_ALL ++ + #define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) + #define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ + GP##pfx##_IN, GP##pfx##_OUT) +@@ -45,10 +51,6 @@ + #define GP_INOUTSEL(bank) PORT_32_REV(_GP_INOUTSEL, _##bank##_, unused) + #define GP_INDT(bank) PORT_32_REV(_GP_INDT, _##bank##_, unused) + +-#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) +-#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ +- FN_##ipsr, FN_##fn) +- + enum { + PINMUX_RESERVED = 0, + +diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h +index 7ad1b040..ebddfe03 100644 +--- a/drivers/pinctrl/sh-pfc/sh_pfc.h ++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h +@@ -66,19 +66,6 @@ struct pinmux_func { + const char *name; + }; + +-#define PINMUX_GPIO(gpio, data_or_mark) \ +- [gpio] = { \ +- .name = __stringify(gpio), \ +- .enum_id = data_or_mark, \ +- } +-#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \ +- [gpio - (base)] = { \ +- .name = __stringify(gpio), \ +- .enum_id = data_or_mark, \ +- } +- +-#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0 +- + struct pinmux_cfg_reg { + unsigned long reg, reg_width, field_width; + const u16 *enum_ids; +@@ -159,26 +146,108 @@ struct sh_pfc_soc_info { + unsigned long unlock_reg; + }; + +-/* helper macro for port */ ++/* ----------------------------------------------------------------------------- ++ * Helper macros to create pin and port lists ++ */ ++ ++/* ++ * sh_pfc_soc_info gpio_data array macros ++ */ ++ ++#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0 ++ ++#define PINMUX_IPSR_NOGP(ispr, fn) \ ++ PINMUX_DATA(fn##_MARK, FN_##fn) ++#define PINMUX_IPSR_DATA(ipsr, fn) \ ++ PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr) ++#define PINMUX_IPSR_NOGM(ispr, fn, ms) \ ++ PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ms) ++#define PINMUX_IPSR_MSEL(ipsr, fn, ms) \ ++ PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr, FN_##ms) ++#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) \ ++ PINMUX_DATA(fn##_MARK, FN_##ms, FN_##ipsr, FN_##fn) ++ ++/* ++ * GP port style (32 ports banks) ++ */ ++ ++#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx) ++ ++#define PORT_GP_32(bank, fn, sfx) \ ++ PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ ++ PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ ++ PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ ++ PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ ++ PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ ++ PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ ++ PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ ++ PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ ++ PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ ++ PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ ++ PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ ++ PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ ++ PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \ ++ PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \ ++ PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \ ++ PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx) ++ ++#define PORT_GP_32_REV(bank, fn, sfx) \ ++ PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \ ++ PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \ ++ PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \ ++ PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \ ++ PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \ ++ PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \ ++ PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \ ++ PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \ ++ PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \ ++ PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \ ++ PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \ ++ PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \ ++ PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \ ++ PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \ ++ PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \ ++ PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx) ++ ++/* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */ ++#define _GP_ALL(bank, pin, name, sfx) name##_##sfx ++#define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str) ++ ++/* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */ ++#define _GP_GPIO(bank, pin, _name, sfx) \ ++ [(bank * 32) + pin] = { \ ++ .name = __stringify(_name), \ ++ .enum_id = _name##_DATA, \ ++ } ++#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused) ++ ++/* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */ ++#define _GP_DATA(bank, pin, name, sfx) PINMUX_DATA(name##_DATA, name##_FN) ++#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused) ++ ++/* ++ * PORT style (linear pin space) ++ */ ++ + #define PORT_1(fn, pfx, sfx) fn(pfx, sfx) + +-#define PORT_10(fn, pfx, sfx) \ +- PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \ +- PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \ +- PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \ +- PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \ ++#define PORT_10(fn, pfx, sfx) \ ++ PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \ ++ PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \ ++ PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \ ++ PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \ + PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx) + +-#define PORT_10_REV(fn, pfx, sfx) \ +- PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ +- PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ +- PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ +- PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ ++#define PORT_10_REV(fn, pfx, sfx) \ ++ PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ ++ PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ ++ PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ ++ PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ + PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) + +-#define PORT_32(fn, pfx, sfx) \ +- PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ +- PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ ++#define PORT_32(fn, pfx, sfx) \ ++ PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ ++ PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_1(fn, pfx##31, sfx) + + #define PORT_32_REV(fn, pfx, sfx) \ +@@ -187,22 +256,43 @@ struct sh_pfc_soc_info { + PORT_10_REV(fn, pfx, sfx) + + #define PORT_90(fn, pfx, sfx) \ +- PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx), \ +- PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx), \ +- PORT_10(fn, pfx##5, sfx), PORT_10(fn, pfx##6, sfx), \ +- PORT_10(fn, pfx##7, sfx), PORT_10(fn, pfx##8, sfx), \ ++ PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx), \ ++ PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx), \ ++ PORT_10(fn, pfx##5, sfx), PORT_10(fn, pfx##6, sfx), \ ++ PORT_10(fn, pfx##7, sfx), PORT_10(fn, pfx##8, sfx), \ + PORT_10(fn, pfx##9, sfx) + +-#define _PORT_ALL(pfx, sfx) pfx##_##sfx +-#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str) +-#define GPIO_FN(str) PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK) ++/* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */ ++#define _PORT_ALL(pfx, sfx) pfx##_##sfx ++#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str) + +-/* helper macro for pinmux data arrays */ +-#define PORT_DATA_IO(nr) \ +- PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ +- PORT##nr##_IN) ++/* PINMUX_GPIO - Expand to a sh_pfc_pin entry */ ++#define PINMUX_GPIO(gpio, data_or_mark) \ ++ [gpio] = { \ ++ .name = __stringify(gpio), \ ++ .enum_id = data_or_mark, \ ++ } ++ ++/* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0, ++ * PORT_name_OUT, PORT_name_IN marks ++ */ ++#define _PORT_DATA(pfx, sfx) \ ++ PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \ ++ PORT##pfx##_OUT, PORT##pfx##_IN) ++#define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) ++ ++/* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */ ++#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \ ++ [gpio - (base)] = { \ ++ .name = __stringify(gpio), \ ++ .enum_id = data_or_mark, \ ++ } ++#define GPIO_FN(str) \ ++ PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK) + +-/* helper macro for top 4 bits in PORTnCR */ ++/* ++ * PORTnCR macro ++ */ + #define _PCRH(in, in_pd, in_pu, out) \ + 0, (out), (in), 0, \ + 0, 0, 0, 0, \ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0545-sh-pfc-Consolidate-pin-definition-macros.patch b/patches.renesas/0545-sh-pfc-Consolidate-pin-definition-macros.patch new file mode 100644 index 00000000000..d3ca3a428b3 --- /dev/null +++ b/patches.renesas/0545-sh-pfc-Consolidate-pin-definition-macros.patch @@ -0,0 +1,194 @@ +From b457ae8c115a7bd5c8fbe9bc741dd8ac95c20502 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 15 Jul 2013 17:42:48 +0200 +Subject: sh-pfc: Consolidate pin definition macros + +Move the pin definition macros to a common header file. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com> +(cherry picked from commit df020272abd6e30673f397fea31e5e133a87c0fe) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a73a4.c | 11 ++--------- + drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 25 +++++++++---------------- + drivers/pinctrl/sh-pfc/pfc-sh7372.c | 25 +++++++++---------------- + drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 23 ++++++++--------------- + drivers/pinctrl/sh-pfc/sh_pfc.h | 8 ++++++++ + 5 files changed, 36 insertions(+), 56 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +index d8115331..288821b6 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +@@ -1266,19 +1266,12 @@ static const u16 pinmux_data[] = { + PINMUX_DATA(IRQ57_MARK, PORT329_FN0), + }; + +-#define R8A73A4_PIN(pin, cfgs) \ +- { \ +- .name = __stringify(PORT##pin), \ +- .enum_id = PORT##pin##_DATA, \ +- .configs = cfgs, \ +- } +- + #define __O (SH_PFC_PIN_CFG_OUTPUT) + #define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT) + #define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP) + +-#define R8A73A4_PIN_IO_PU_PD(pin) R8A73A4_PIN(pin, __IO | __PUD) +-#define R8A73A4_PIN_O(pin) R8A73A4_PIN(pin, __O) ++#define R8A73A4_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD) ++#define R8A73A4_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O) + + static struct sh_pfc_pin pinmux_pins[] = { + R8A73A4_PIN_IO_PU_PD(0), R8A73A4_PIN_IO_PU_PD(1), +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +index e6900511..b5bc1d09 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +@@ -1527,13 +1527,6 @@ static const u16 pinmux_data[] = { + PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0), + }; + +-#define R8A7740_PIN(pin, cfgs) \ +- { \ +- .name = __stringify(PORT##pin), \ +- .enum_id = PORT##pin##_DATA, \ +- .configs = cfgs, \ +- } +- + #define __I (SH_PFC_PIN_CFG_INPUT) + #define __O (SH_PFC_PIN_CFG_OUTPUT) + #define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT) +@@ -1541,15 +1534,15 @@ static const u16 pinmux_data[] = { + #define __PU (SH_PFC_PIN_CFG_PULL_UP) + #define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP) + +-#define R8A7740_PIN_I_PD(pin) R8A7740_PIN(pin, __I | __PD) +-#define R8A7740_PIN_I_PU(pin) R8A7740_PIN(pin, __I | __PU) +-#define R8A7740_PIN_I_PU_PD(pin) R8A7740_PIN(pin, __I | __PUD) +-#define R8A7740_PIN_IO(pin) R8A7740_PIN(pin, __IO) +-#define R8A7740_PIN_IO_PD(pin) R8A7740_PIN(pin, __IO | __PD) +-#define R8A7740_PIN_IO_PU(pin) R8A7740_PIN(pin, __IO | __PU) +-#define R8A7740_PIN_IO_PU_PD(pin) R8A7740_PIN(pin, __IO | __PUD) +-#define R8A7740_PIN_O(pin) R8A7740_PIN(pin, __O) +-#define R8A7740_PIN_O_PU_PD(pin) R8A7740_PIN(pin, __O | __PUD) ++#define R8A7740_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD) ++#define R8A7740_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU) ++#define R8A7740_PIN_I_PU_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PUD) ++#define R8A7740_PIN_IO(pin) SH_PFC_PIN_CFG(pin, __IO) ++#define R8A7740_PIN_IO_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PD) ++#define R8A7740_PIN_IO_PU(pin) SH_PFC_PIN_CFG(pin, __IO | __PU) ++#define R8A7740_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD) ++#define R8A7740_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O) ++#define R8A7740_PIN_O_PU_PD(pin) SH_PFC_PIN_CFG(pin, __O | __PUD) + + static struct sh_pfc_pin pinmux_pins[] = { + /* Table 56-1 (I/O and Pull U/D) */ +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +index 9174ff26..17f1c179 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +@@ -829,13 +829,6 @@ static const u16 pinmux_data[] = { + PINMUX_DATA(MFIv4_MARK, MSEL4CR_6_1), + }; + +-#define SH7372_PIN(pin, cfgs) \ +- { \ +- .name = __stringify(PORT##pin), \ +- .enum_id = PORT##pin##_DATA, \ +- .configs = cfgs, \ +- } +- + #define __I (SH_PFC_PIN_CFG_INPUT) + #define __O (SH_PFC_PIN_CFG_OUTPUT) + #define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT) +@@ -843,15 +836,15 @@ static const u16 pinmux_data[] = { + #define __PU (SH_PFC_PIN_CFG_PULL_UP) + #define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP) + +-#define SH7372_PIN_I_PD(pin) SH7372_PIN(pin, __I | __PD) +-#define SH7372_PIN_I_PU(pin) SH7372_PIN(pin, __I | __PU) +-#define SH7372_PIN_I_PU_PD(pin) SH7372_PIN(pin, __I | __PUD) +-#define SH7372_PIN_IO(pin) SH7372_PIN(pin, __IO) +-#define SH7372_PIN_IO_PD(pin) SH7372_PIN(pin, __IO | __PD) +-#define SH7372_PIN_IO_PU(pin) SH7372_PIN(pin, __IO | __PU) +-#define SH7372_PIN_IO_PU_PD(pin) SH7372_PIN(pin, __IO | __PUD) +-#define SH7372_PIN_O(pin) SH7372_PIN(pin, __O) +-#define SH7372_PIN_O_PU_PD(pin) SH7372_PIN(pin, __O | __PUD) ++#define SH7372_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD) ++#define SH7372_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU) ++#define SH7372_PIN_I_PU_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PUD) ++#define SH7372_PIN_IO(pin) SH_PFC_PIN_CFG(pin, __IO) ++#define SH7372_PIN_IO_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PD) ++#define SH7372_PIN_IO_PU(pin) SH_PFC_PIN_CFG(pin, __IO | __PU) ++#define SH7372_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD) ++#define SH7372_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O) ++#define SH7372_PIN_O_PU_PD(pin) SH_PFC_PIN_CFG(pin, __O | __PUD) + + static struct sh_pfc_pin pinmux_pins[] = { + /* Table 57-1 (I/O and Pull U/D) */ +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +index b275e507..21d2726c 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +@@ -1157,13 +1157,6 @@ static const u16 pinmux_data[] = { + PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1), + }; + +-#define SH73A0_PIN(pin, cfgs) \ +- { \ +- .name = __stringify(PORT##pin), \ +- .enum_id = PORT##pin##_DATA, \ +- .configs = cfgs, \ +- } +- + #define __I (SH_PFC_PIN_CFG_INPUT) + #define __O (SH_PFC_PIN_CFG_OUTPUT) + #define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT) +@@ -1171,14 +1164,14 @@ static const u16 pinmux_data[] = { + #define __PU (SH_PFC_PIN_CFG_PULL_UP) + #define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP) + +-#define SH73A0_PIN_I_PD(pin) SH73A0_PIN(pin, __I | __PD) +-#define SH73A0_PIN_I_PU(pin) SH73A0_PIN(pin, __I | __PU) +-#define SH73A0_PIN_I_PU_PD(pin) SH73A0_PIN(pin, __I | __PUD) +-#define SH73A0_PIN_IO(pin) SH73A0_PIN(pin, __IO) +-#define SH73A0_PIN_IO_PD(pin) SH73A0_PIN(pin, __IO | __PD) +-#define SH73A0_PIN_IO_PU(pin) SH73A0_PIN(pin, __IO | __PU) +-#define SH73A0_PIN_IO_PU_PD(pin) SH73A0_PIN(pin, __IO | __PUD) +-#define SH73A0_PIN_O(pin) SH73A0_PIN(pin, __O) ++#define SH73A0_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD) ++#define SH73A0_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU) ++#define SH73A0_PIN_I_PU_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PUD) ++#define SH73A0_PIN_IO(pin) SH_PFC_PIN_CFG(pin, __IO) ++#define SH73A0_PIN_IO_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PD) ++#define SH73A0_PIN_IO_PU(pin) SH_PFC_PIN_CFG(pin, __IO | __PU) ++#define SH73A0_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD) ++#define SH73A0_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O) + + static struct sh_pfc_pin pinmux_pins[] = { + /* Table 25-1 (I/O and Pull U/D) */ +diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h +index ebddfe03..f7c5b808 100644 +--- a/drivers/pinctrl/sh-pfc/sh_pfc.h ++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h +@@ -273,6 +273,14 @@ struct sh_pfc_soc_info { + .enum_id = data_or_mark, \ + } + ++/* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */ ++#define SH_PFC_PIN_CFG(pin, cfgs) \ ++ { \ ++ .name = __stringify(PORT##pin), \ ++ .enum_id = PORT##pin##_DATA, \ ++ .configs = cfgs, \ ++ } ++ + /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0, + * PORT_name_OUT, PORT_name_IN marks + */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0546-sh-pfc-sh7734-Use-the-common-GP-port-style-macros.patch b/patches.renesas/0546-sh-pfc-sh7734-Use-the-common-GP-port-style-macros.patch new file mode 100644 index 00000000000..75bc86c5888 --- /dev/null +++ b/patches.renesas/0546-sh-pfc-sh7734-Use-the-common-GP-port-style-macros.patch @@ -0,0 +1,116 @@ +From 42ae8487b3ab16f4e96a19191affc44e128edde9 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 15 Jul 2013 16:07:08 +0200 +Subject: sh-pfc: sh7734: Use the common GP port style macros + +The SoC has a bank-style PFC. Replace the custom-defined macros with +common macros from sh-pfc.h. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit 8157b964290ae7483ea67cf65c3707b23a8be5c0) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-sh7734.c | 56 +++++++++++++++---------------------- + drivers/pinctrl/sh-pfc/sh_pfc.h | 17 ----------- + 2 files changed, 22 insertions(+), 51 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c +index 537a639e..ec0c47c4 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c +@@ -14,42 +14,30 @@ + + #include "sh_pfc.h" + +-#define CPU_32_PORT5(fn, pfx, sfx) \ +- PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \ +- PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \ +- PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \ +- PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \ +- PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx), \ +- PORT_1(fn, pfx##10, sfx), PORT_1(fn, pfx##11, sfx) +- +-/* GPSR0 - GPSR5 */ +-#define CPU_ALL_PORT(fn, pfx, sfx) \ +- PORT_32(fn, pfx##_0_, sfx), \ +- PORT_32(fn, pfx##_1_, sfx), \ +- PORT_32(fn, pfx##_2_, sfx), \ +- PORT_32(fn, pfx##_3_, sfx), \ +- PORT_32(fn, pfx##_4_, sfx), \ +- CPU_32_PORT5(fn, pfx##_5_, sfx) +- +-#undef _GP_GPIO +-#undef _GP_DATA +-#undef GP_ALL +-#undef PINMUX_GPIO_GP_ALL +-#undef PINMUX_DATA_GP_ALL +- +-#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) +-#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ +- GP##pfx##_IN, GP##pfx##_OUT) ++#define PORT_GP_12(bank, fn, sfx) \ ++ PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ ++ PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ ++ PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ ++ PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ ++ PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ ++ PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx) ++ ++#define CPU_ALL_PORT(fn, sfx) \ ++ PORT_GP_32(0, fn, sfx), \ ++ PORT_GP_32(1, fn, sfx), \ ++ PORT_GP_32(2, fn, sfx), \ ++ PORT_GP_32(3, fn, sfx), \ ++ PORT_GP_32(4, fn, sfx), \ ++ PORT_GP_12(5, fn, sfx) + +-#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT +-#define _GP_INDT(pfx, sfx) GP##pfx##_DATA +- +-#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) +-#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) +-#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) ++#undef _GP_DATA ++#define _GP_DATA(bank, pin, name, sfx) \ ++ PINMUX_DATA(name##_DATA, name##_FN, name##_IN, name##_OUT) + +-#define GP_INOUTSEL(bank) PORT_32_REV(_GP_INOUTSEL, _##bank##_, unused) +-#define GP_INDT(bank) PORT_32_REV(_GP_INDT, _##bank##_, unused) ++#define _GP_INOUTSEL(bank, pin, name, sfx) name##_IN, name##_OUT ++#define _GP_INDT(bank, pin, name, sfx) name##_DATA ++#define GP_INOUTSEL(bank) PORT_GP_32_REV(bank, _GP_INOUTSEL, unused) ++#define GP_INDT(bank) PORT_GP_32_REV(bank, _GP_INDT, unused) + + enum { + PINMUX_RESERVED = 0, +diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h +index f7c5b808..05b905fa 100644 +--- a/drivers/pinctrl/sh-pfc/sh_pfc.h ++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h +@@ -238,23 +238,6 @@ struct sh_pfc_soc_info { + PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \ + PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx) + +-#define PORT_10_REV(fn, pfx, sfx) \ +- PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ +- PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ +- PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ +- PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ +- PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) +- +-#define PORT_32(fn, pfx, sfx) \ +- PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ +- PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ +- PORT_1(fn, pfx##31, sfx) +- +-#define PORT_32_REV(fn, pfx, sfx) \ +- PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ +- PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ +- PORT_10_REV(fn, pfx, sfx) +- + #define PORT_90(fn, pfx, sfx) \ + PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx), \ + PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx), \ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0547-sh-pfc-shx3-Remove-shx3_-prefix-from-static-symbols.patch b/patches.renesas/0547-sh-pfc-shx3-Remove-shx3_-prefix-from-static-symbols.patch new file mode 100644 index 00000000000..6b2fabadb80 --- /dev/null +++ b/patches.renesas/0547-sh-pfc-shx3-Remove-shx3_-prefix-from-static-symbols.patch @@ -0,0 +1,92 @@ +From e84ae7155faca785eb8fba9a97f46f26102b6544 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 15 Jul 2013 17:13:51 +0200 +Subject: sh-pfc: shx3: Remove shx3_ prefix from static symbols + +Unlike all other PFC SoC data, the shx3 data prefix all static symbols +with shx3_. Remove the prefix to be consistent with the other source +files. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit 18dcc58341e4094a2799acfd1e8779a94e97fd13) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-shx3.c | 28 ++++++++++++++-------------- + 1 file changed, 14 insertions(+), 14 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-shx3.c b/drivers/pinctrl/sh-pfc/pfc-shx3.c +index 48a6c60f..775a622b 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-shx3.c ++++ b/drivers/pinctrl/sh-pfc/pfc-shx3.c +@@ -127,7 +127,7 @@ enum { + PINMUX_MARK_END, + }; + +-static const u16 shx3_pinmux_data[] = { ++static const u16 pinmux_data[] = { + /* PA GPIO */ + PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT), + PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT), +@@ -285,7 +285,7 @@ static const u16 shx3_pinmux_data[] = { + PINMUX_DATA(IRQOUT_MARK, PH0_FN), + }; + +-static struct sh_pfc_pin shx3_pinmux_pins[] = { ++static struct sh_pfc_pin pinmux_pins[] = { + /* PA */ + PINMUX_GPIO(GPIO_PA7, PA7_DATA), + PINMUX_GPIO(GPIO_PA6, PA6_DATA), +@@ -365,9 +365,9 @@ static struct sh_pfc_pin shx3_pinmux_pins[] = { + PINMUX_GPIO(GPIO_PH0, PH0_DATA), + }; + +-#define PINMUX_FN_BASE ARRAY_SIZE(shx3_pinmux_pins) ++#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) + +-static const struct pinmux_func shx3_pinmux_func_gpios[] = { ++static const struct pinmux_func pinmux_func_gpios[] = { + /* FN */ + GPIO_FN(D31), + GPIO_FN(D30), +@@ -433,7 +433,7 @@ static const struct pinmux_func shx3_pinmux_func_gpios[] = { + GPIO_FN(IRQOUT), + }; + +-static const struct pinmux_cfg_reg shx3_pinmux_config_regs[] = { ++static const struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2) { + PA7_FN, PA7_OUT, PA7_IN, 0, + PA6_FN, PA6_OUT, PA6_IN, 0, +@@ -509,7 +509,7 @@ static const struct pinmux_cfg_reg shx3_pinmux_config_regs[] = { + { }, + }; + +-static const struct pinmux_data_reg shx3_pinmux_data_regs[] = { ++static const struct pinmux_data_reg pinmux_data_regs[] = { + { PINMUX_DATA_REG("PABDR", 0xffc70010, 32) { + 0, 0, 0, 0, 0, 0, 0, 0, + PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, +@@ -550,12 +550,12 @@ const struct sh_pfc_soc_info shx3_pinmux_info = { + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, +- .pins = shx3_pinmux_pins, +- .nr_pins = ARRAY_SIZE(shx3_pinmux_pins), +- .func_gpios = shx3_pinmux_func_gpios, +- .nr_func_gpios = ARRAY_SIZE(shx3_pinmux_func_gpios), +- .gpio_data = shx3_pinmux_data, +- .gpio_data_size = ARRAY_SIZE(shx3_pinmux_data), +- .cfg_regs = shx3_pinmux_config_regs, +- .data_regs = shx3_pinmux_data_regs, ++ .pins = pinmux_pins, ++ .nr_pins = ARRAY_SIZE(pinmux_pins), ++ .func_gpios = pinmux_func_gpios, ++ .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), ++ .gpio_data = pinmux_data, ++ .gpio_data_size = ARRAY_SIZE(pinmux_data), ++ .cfg_regs = pinmux_config_regs, ++ .data_regs = pinmux_data_regs, + }; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0548-sh-pfc-Don-t-duplicate-argument-to-PINMUX_GPIO-macro.patch b/patches.renesas/0548-sh-pfc-Don-t-duplicate-argument-to-PINMUX_GPIO-macro.patch new file mode 100644 index 00000000000..e1e181971f9 --- /dev/null +++ b/patches.renesas/0548-sh-pfc-Don-t-duplicate-argument-to-PINMUX_GPIO-macro.patch @@ -0,0 +1,3327 @@ +From 48271b576b56606ed0d572cfe838b6f415acfc28 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 15 Jul 2013 21:16:25 +0200 +Subject: sh-pfc: Don't duplicate argument to PINMUX_GPIO macro + +The PINMUX_GPIO macro takes a port name and a data mark, respectively of +the form GPIO_name and name_DATA. Modify the macro to take the name as a +single argument and derive the port name and data mark from it. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com> +(cherry picked from commit 7cbb0e55e27e6b8134813849f0cb899773d59548) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-sh7203.c | 199 +++++++++--------- + drivers/pinctrl/sh-pfc/pfc-sh7264.c | 243 +++++++++++---------- + drivers/pinctrl/sh-pfc/pfc-sh7269.c | 282 ++++++++++++------------- + drivers/pinctrl/sh-pfc/pfc-sh7720.c | 234 ++++++++++----------- + drivers/pinctrl/sh-pfc/pfc-sh7722.c | 298 +++++++++++++------------- + drivers/pinctrl/sh-pfc/pfc-sh7723.c | 340 +++++++++++++++--------------- + drivers/pinctrl/sh-pfc/pfc-sh7724.c | 360 +++++++++++++++---------------- + drivers/pinctrl/sh-pfc/pfc-sh7757.c | 408 ++++++++++++++++++------------------ + drivers/pinctrl/sh-pfc/pfc-sh7785.c | 222 ++++++++++---------- + drivers/pinctrl/sh-pfc/pfc-sh7786.c | 120 +++++------ + drivers/pinctrl/sh-pfc/pfc-shx3.c | 124 +++++------ + drivers/pinctrl/sh-pfc/sh_pfc.h | 8 +- + 12 files changed, 1418 insertions(+), 1420 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7203.c b/drivers/pinctrl/sh-pfc/pfc-sh7203.c +index 44878140..bf3d8f28 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7203.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7203.c +@@ -703,117 +703,116 @@ static const u16 pinmux_data[] = { + }; + + static struct sh_pfc_pin pinmux_pins[] = { +- + /* PA */ +- PINMUX_GPIO(GPIO_PA7, PA7_DATA), +- PINMUX_GPIO(GPIO_PA6, PA6_DATA), +- PINMUX_GPIO(GPIO_PA5, PA5_DATA), +- PINMUX_GPIO(GPIO_PA4, PA4_DATA), +- PINMUX_GPIO(GPIO_PA3, PA3_DATA), +- PINMUX_GPIO(GPIO_PA2, PA2_DATA), +- PINMUX_GPIO(GPIO_PA1, PA1_DATA), +- PINMUX_GPIO(GPIO_PA0, PA0_DATA), ++ PINMUX_GPIO(PA7), ++ PINMUX_GPIO(PA6), ++ PINMUX_GPIO(PA5), ++ PINMUX_GPIO(PA4), ++ PINMUX_GPIO(PA3), ++ PINMUX_GPIO(PA2), ++ PINMUX_GPIO(PA1), ++ PINMUX_GPIO(PA0), + + /* PB */ +- PINMUX_GPIO(GPIO_PB12, PB12_DATA), +- PINMUX_GPIO(GPIO_PB11, PB11_DATA), +- PINMUX_GPIO(GPIO_PB10, PB10_DATA), +- PINMUX_GPIO(GPIO_PB9, PB9_DATA), +- PINMUX_GPIO(GPIO_PB8, PB8_DATA), +- PINMUX_GPIO(GPIO_PB7, PB7_DATA), +- PINMUX_GPIO(GPIO_PB6, PB6_DATA), +- PINMUX_GPIO(GPIO_PB5, PB5_DATA), +- PINMUX_GPIO(GPIO_PB4, PB4_DATA), +- PINMUX_GPIO(GPIO_PB3, PB3_DATA), +- PINMUX_GPIO(GPIO_PB2, PB2_DATA), +- PINMUX_GPIO(GPIO_PB1, PB1_DATA), +- PINMUX_GPIO(GPIO_PB0, PB0_DATA), ++ PINMUX_GPIO(PB12), ++ PINMUX_GPIO(PB11), ++ PINMUX_GPIO(PB10), ++ PINMUX_GPIO(PB9), ++ PINMUX_GPIO(PB8), ++ PINMUX_GPIO(PB7), ++ PINMUX_GPIO(PB6), ++ PINMUX_GPIO(PB5), ++ PINMUX_GPIO(PB4), ++ PINMUX_GPIO(PB3), ++ PINMUX_GPIO(PB2), ++ PINMUX_GPIO(PB1), ++ PINMUX_GPIO(PB0), + + /* PC */ +- PINMUX_GPIO(GPIO_PC14, PC14_DATA), +- PINMUX_GPIO(GPIO_PC13, PC13_DATA), +- PINMUX_GPIO(GPIO_PC12, PC12_DATA), +- PINMUX_GPIO(GPIO_PC11, PC11_DATA), +- PINMUX_GPIO(GPIO_PC10, PC10_DATA), +- PINMUX_GPIO(GPIO_PC9, PC9_DATA), +- PINMUX_GPIO(GPIO_PC8, PC8_DATA), +- PINMUX_GPIO(GPIO_PC7, PC7_DATA), +- PINMUX_GPIO(GPIO_PC6, PC6_DATA), +- PINMUX_GPIO(GPIO_PC5, PC5_DATA), +- PINMUX_GPIO(GPIO_PC4, PC4_DATA), +- PINMUX_GPIO(GPIO_PC3, PC3_DATA), +- PINMUX_GPIO(GPIO_PC2, PC2_DATA), +- PINMUX_GPIO(GPIO_PC1, PC1_DATA), +- PINMUX_GPIO(GPIO_PC0, PC0_DATA), ++ PINMUX_GPIO(PC14), ++ PINMUX_GPIO(PC13), ++ PINMUX_GPIO(PC12), ++ PINMUX_GPIO(PC11), ++ PINMUX_GPIO(PC10), ++ PINMUX_GPIO(PC9), ++ PINMUX_GPIO(PC8), ++ PINMUX_GPIO(PC7), ++ PINMUX_GPIO(PC6), ++ PINMUX_GPIO(PC5), ++ PINMUX_GPIO(PC4), ++ PINMUX_GPIO(PC3), ++ PINMUX_GPIO(PC2), ++ PINMUX_GPIO(PC1), ++ PINMUX_GPIO(PC0), + + /* PD */ +- PINMUX_GPIO(GPIO_PD15, PD15_DATA), +- PINMUX_GPIO(GPIO_PD14, PD14_DATA), +- PINMUX_GPIO(GPIO_PD13, PD13_DATA), +- PINMUX_GPIO(GPIO_PD12, PD12_DATA), +- PINMUX_GPIO(GPIO_PD11, PD11_DATA), +- PINMUX_GPIO(GPIO_PD10, PD10_DATA), +- PINMUX_GPIO(GPIO_PD9, PD9_DATA), +- PINMUX_GPIO(GPIO_PD8, PD8_DATA), +- PINMUX_GPIO(GPIO_PD7, PD7_DATA), +- PINMUX_GPIO(GPIO_PD6, PD6_DATA), +- PINMUX_GPIO(GPIO_PD5, PD5_DATA), +- PINMUX_GPIO(GPIO_PD4, PD4_DATA), +- PINMUX_GPIO(GPIO_PD3, PD3_DATA), +- PINMUX_GPIO(GPIO_PD2, PD2_DATA), +- PINMUX_GPIO(GPIO_PD1, PD1_DATA), +- PINMUX_GPIO(GPIO_PD0, PD0_DATA), ++ PINMUX_GPIO(PD15), ++ PINMUX_GPIO(PD14), ++ PINMUX_GPIO(PD13), ++ PINMUX_GPIO(PD12), ++ PINMUX_GPIO(PD11), ++ PINMUX_GPIO(PD10), ++ PINMUX_GPIO(PD9), ++ PINMUX_GPIO(PD8), ++ PINMUX_GPIO(PD7), ++ PINMUX_GPIO(PD6), ++ PINMUX_GPIO(PD5), ++ PINMUX_GPIO(PD4), ++ PINMUX_GPIO(PD3), ++ PINMUX_GPIO(PD2), ++ PINMUX_GPIO(PD1), ++ PINMUX_GPIO(PD0), + + /* PE */ +- PINMUX_GPIO(GPIO_PE15, PE15_DATA), +- PINMUX_GPIO(GPIO_PE14, PE14_DATA), +- PINMUX_GPIO(GPIO_PE13, PE13_DATA), +- PINMUX_GPIO(GPIO_PE12, PE12_DATA), +- PINMUX_GPIO(GPIO_PE11, PE11_DATA), +- PINMUX_GPIO(GPIO_PE10, PE10_DATA), +- PINMUX_GPIO(GPIO_PE9, PE9_DATA), +- PINMUX_GPIO(GPIO_PE8, PE8_DATA), +- PINMUX_GPIO(GPIO_PE7, PE7_DATA), +- PINMUX_GPIO(GPIO_PE6, PE6_DATA), +- PINMUX_GPIO(GPIO_PE5, PE5_DATA), +- PINMUX_GPIO(GPIO_PE4, PE4_DATA), +- PINMUX_GPIO(GPIO_PE3, PE3_DATA), +- PINMUX_GPIO(GPIO_PE2, PE2_DATA), +- PINMUX_GPIO(GPIO_PE1, PE1_DATA), +- PINMUX_GPIO(GPIO_PE0, PE0_DATA), ++ PINMUX_GPIO(PE15), ++ PINMUX_GPIO(PE14), ++ PINMUX_GPIO(PE13), ++ PINMUX_GPIO(PE12), ++ PINMUX_GPIO(PE11), ++ PINMUX_GPIO(PE10), ++ PINMUX_GPIO(PE9), ++ PINMUX_GPIO(PE8), ++ PINMUX_GPIO(PE7), ++ PINMUX_GPIO(PE6), ++ PINMUX_GPIO(PE5), ++ PINMUX_GPIO(PE4), ++ PINMUX_GPIO(PE3), ++ PINMUX_GPIO(PE2), ++ PINMUX_GPIO(PE1), ++ PINMUX_GPIO(PE0), + + /* PF */ +- PINMUX_GPIO(GPIO_PF30, PF30_DATA), +- PINMUX_GPIO(GPIO_PF29, PF29_DATA), +- PINMUX_GPIO(GPIO_PF28, PF28_DATA), +- PINMUX_GPIO(GPIO_PF27, PF27_DATA), +- PINMUX_GPIO(GPIO_PF26, PF26_DATA), +- PINMUX_GPIO(GPIO_PF25, PF25_DATA), +- PINMUX_GPIO(GPIO_PF24, PF24_DATA), +- PINMUX_GPIO(GPIO_PF23, PF23_DATA), +- PINMUX_GPIO(GPIO_PF22, PF22_DATA), +- PINMUX_GPIO(GPIO_PF21, PF21_DATA), +- PINMUX_GPIO(GPIO_PF20, PF20_DATA), +- PINMUX_GPIO(GPIO_PF19, PF19_DATA), +- PINMUX_GPIO(GPIO_PF18, PF18_DATA), +- PINMUX_GPIO(GPIO_PF17, PF17_DATA), +- PINMUX_GPIO(GPIO_PF16, PF16_DATA), +- PINMUX_GPIO(GPIO_PF15, PF15_DATA), +- PINMUX_GPIO(GPIO_PF14, PF14_DATA), +- PINMUX_GPIO(GPIO_PF13, PF13_DATA), +- PINMUX_GPIO(GPIO_PF12, PF12_DATA), +- PINMUX_GPIO(GPIO_PF11, PF11_DATA), +- PINMUX_GPIO(GPIO_PF10, PF10_DATA), +- PINMUX_GPIO(GPIO_PF9, PF9_DATA), +- PINMUX_GPIO(GPIO_PF8, PF8_DATA), +- PINMUX_GPIO(GPIO_PF7, PF7_DATA), +- PINMUX_GPIO(GPIO_PF6, PF6_DATA), +- PINMUX_GPIO(GPIO_PF5, PF5_DATA), +- PINMUX_GPIO(GPIO_PF4, PF4_DATA), +- PINMUX_GPIO(GPIO_PF3, PF3_DATA), +- PINMUX_GPIO(GPIO_PF2, PF2_DATA), +- PINMUX_GPIO(GPIO_PF1, PF1_DATA), +- PINMUX_GPIO(GPIO_PF0, PF0_DATA), ++ PINMUX_GPIO(PF30), ++ PINMUX_GPIO(PF29), ++ PINMUX_GPIO(PF28), ++ PINMUX_GPIO(PF27), ++ PINMUX_GPIO(PF26), ++ PINMUX_GPIO(PF25), ++ PINMUX_GPIO(PF24), ++ PINMUX_GPIO(PF23), ++ PINMUX_GPIO(PF22), ++ PINMUX_GPIO(PF21), ++ PINMUX_GPIO(PF20), ++ PINMUX_GPIO(PF19), ++ PINMUX_GPIO(PF18), ++ PINMUX_GPIO(PF17), ++ PINMUX_GPIO(PF16), ++ PINMUX_GPIO(PF15), ++ PINMUX_GPIO(PF14), ++ PINMUX_GPIO(PF13), ++ PINMUX_GPIO(PF12), ++ PINMUX_GPIO(PF11), ++ PINMUX_GPIO(PF10), ++ PINMUX_GPIO(PF9), ++ PINMUX_GPIO(PF8), ++ PINMUX_GPIO(PF7), ++ PINMUX_GPIO(PF6), ++ PINMUX_GPIO(PF5), ++ PINMUX_GPIO(PF4), ++ PINMUX_GPIO(PF3), ++ PINMUX_GPIO(PF2), ++ PINMUX_GPIO(PF1), ++ PINMUX_GPIO(PF0), + }; + + #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c +index 641c6af3..673a5950 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7264.c +@@ -1072,149 +1072,148 @@ static const u16 pinmux_data[] = { + }; + + static struct sh_pfc_pin pinmux_pins[] = { +- + /* Port A */ +- PINMUX_GPIO(GPIO_PA3, PA3_DATA), +- PINMUX_GPIO(GPIO_PA2, PA2_DATA), +- PINMUX_GPIO(GPIO_PA1, PA1_DATA), +- PINMUX_GPIO(GPIO_PA0, PA0_DATA), ++ PINMUX_GPIO(PA3), ++ PINMUX_GPIO(PA2), ++ PINMUX_GPIO(PA1), ++ PINMUX_GPIO(PA0), + + /* Port B */ +- PINMUX_GPIO(GPIO_PB22, PB22_DATA), +- PINMUX_GPIO(GPIO_PB21, PB21_DATA), +- PINMUX_GPIO(GPIO_PB20, PB20_DATA), +- PINMUX_GPIO(GPIO_PB19, PB19_DATA), +- PINMUX_GPIO(GPIO_PB18, PB18_DATA), +- PINMUX_GPIO(GPIO_PB17, PB17_DATA), +- PINMUX_GPIO(GPIO_PB16, PB16_DATA), +- PINMUX_GPIO(GPIO_PB15, PB15_DATA), +- PINMUX_GPIO(GPIO_PB14, PB14_DATA), +- PINMUX_GPIO(GPIO_PB13, PB13_DATA), +- PINMUX_GPIO(GPIO_PB12, PB12_DATA), +- PINMUX_GPIO(GPIO_PB11, PB11_DATA), +- PINMUX_GPIO(GPIO_PB10, PB10_DATA), +- PINMUX_GPIO(GPIO_PB9, PB9_DATA), +- PINMUX_GPIO(GPIO_PB8, PB8_DATA), +- PINMUX_GPIO(GPIO_PB7, PB7_DATA), +- PINMUX_GPIO(GPIO_PB6, PB6_DATA), +- PINMUX_GPIO(GPIO_PB5, PB5_DATA), +- PINMUX_GPIO(GPIO_PB4, PB4_DATA), +- PINMUX_GPIO(GPIO_PB3, PB3_DATA), +- PINMUX_GPIO(GPIO_PB2, PB2_DATA), +- PINMUX_GPIO(GPIO_PB1, PB1_DATA), ++ PINMUX_GPIO(PB22), ++ PINMUX_GPIO(PB21), ++ PINMUX_GPIO(PB20), ++ PINMUX_GPIO(PB19), ++ PINMUX_GPIO(PB18), ++ PINMUX_GPIO(PB17), ++ PINMUX_GPIO(PB16), ++ PINMUX_GPIO(PB15), ++ PINMUX_GPIO(PB14), ++ PINMUX_GPIO(PB13), ++ PINMUX_GPIO(PB12), ++ PINMUX_GPIO(PB11), ++ PINMUX_GPIO(PB10), ++ PINMUX_GPIO(PB9), ++ PINMUX_GPIO(PB8), ++ PINMUX_GPIO(PB7), ++ PINMUX_GPIO(PB6), ++ PINMUX_GPIO(PB5), ++ PINMUX_GPIO(PB4), ++ PINMUX_GPIO(PB3), ++ PINMUX_GPIO(PB2), ++ PINMUX_GPIO(PB1), + + /* Port C */ +- PINMUX_GPIO(GPIO_PC10, PC10_DATA), +- PINMUX_GPIO(GPIO_PC9, PC9_DATA), +- PINMUX_GPIO(GPIO_PC8, PC8_DATA), +- PINMUX_GPIO(GPIO_PC7, PC7_DATA), +- PINMUX_GPIO(GPIO_PC6, PC6_DATA), +- PINMUX_GPIO(GPIO_PC5, PC5_DATA), +- PINMUX_GPIO(GPIO_PC4, PC4_DATA), +- PINMUX_GPIO(GPIO_PC3, PC3_DATA), +- PINMUX_GPIO(GPIO_PC2, PC2_DATA), +- PINMUX_GPIO(GPIO_PC1, PC1_DATA), +- PINMUX_GPIO(GPIO_PC0, PC0_DATA), ++ PINMUX_GPIO(PC10), ++ PINMUX_GPIO(PC9), ++ PINMUX_GPIO(PC8), ++ PINMUX_GPIO(PC7), ++ PINMUX_GPIO(PC6), ++ PINMUX_GPIO(PC5), ++ PINMUX_GPIO(PC4), ++ PINMUX_GPIO(PC3), ++ PINMUX_GPIO(PC2), ++ PINMUX_GPIO(PC1), ++ PINMUX_GPIO(PC0), + + /* Port D */ +- PINMUX_GPIO(GPIO_PD15, PD15_DATA), +- PINMUX_GPIO(GPIO_PD14, PD14_DATA), +- PINMUX_GPIO(GPIO_PD13, PD13_DATA), +- PINMUX_GPIO(GPIO_PD12, PD12_DATA), +- PINMUX_GPIO(GPIO_PD11, PD11_DATA), +- PINMUX_GPIO(GPIO_PD10, PD10_DATA), +- PINMUX_GPIO(GPIO_PD9, PD9_DATA), +- PINMUX_GPIO(GPIO_PD8, PD8_DATA), +- PINMUX_GPIO(GPIO_PD7, PD7_DATA), +- PINMUX_GPIO(GPIO_PD6, PD6_DATA), +- PINMUX_GPIO(GPIO_PD5, PD5_DATA), +- PINMUX_GPIO(GPIO_PD4, PD4_DATA), +- PINMUX_GPIO(GPIO_PD3, PD3_DATA), +- PINMUX_GPIO(GPIO_PD2, PD2_DATA), +- PINMUX_GPIO(GPIO_PD1, PD1_DATA), +- PINMUX_GPIO(GPIO_PD0, PD0_DATA), ++ PINMUX_GPIO(PD15), ++ PINMUX_GPIO(PD14), ++ PINMUX_GPIO(PD13), ++ PINMUX_GPIO(PD12), ++ PINMUX_GPIO(PD11), ++ PINMUX_GPIO(PD10), ++ PINMUX_GPIO(PD9), ++ PINMUX_GPIO(PD8), ++ PINMUX_GPIO(PD7), ++ PINMUX_GPIO(PD6), ++ PINMUX_GPIO(PD5), ++ PINMUX_GPIO(PD4), ++ PINMUX_GPIO(PD3), ++ PINMUX_GPIO(PD2), ++ PINMUX_GPIO(PD1), ++ PINMUX_GPIO(PD0), + + /* Port E */ +- PINMUX_GPIO(GPIO_PE5, PE5_DATA), +- PINMUX_GPIO(GPIO_PE4, PE4_DATA), +- PINMUX_GPIO(GPIO_PE3, PE3_DATA), +- PINMUX_GPIO(GPIO_PE2, PE2_DATA), +- PINMUX_GPIO(GPIO_PE1, PE1_DATA), +- PINMUX_GPIO(GPIO_PE0, PE0_DATA), ++ PINMUX_GPIO(PE5), ++ PINMUX_GPIO(PE4), ++ PINMUX_GPIO(PE3), ++ PINMUX_GPIO(PE2), ++ PINMUX_GPIO(PE1), ++ PINMUX_GPIO(PE0), + + /* Port F */ +- PINMUX_GPIO(GPIO_PF12, PF12_DATA), +- PINMUX_GPIO(GPIO_PF11, PF11_DATA), +- PINMUX_GPIO(GPIO_PF10, PF10_DATA), +- PINMUX_GPIO(GPIO_PF9, PF9_DATA), +- PINMUX_GPIO(GPIO_PF8, PF8_DATA), +- PINMUX_GPIO(GPIO_PF7, PF7_DATA), +- PINMUX_GPIO(GPIO_PF6, PF6_DATA), +- PINMUX_GPIO(GPIO_PF5, PF5_DATA), +- PINMUX_GPIO(GPIO_PF4, PF4_DATA), +- PINMUX_GPIO(GPIO_PF3, PF3_DATA), +- PINMUX_GPIO(GPIO_PF2, PF2_DATA), +- PINMUX_GPIO(GPIO_PF1, PF1_DATA), +- PINMUX_GPIO(GPIO_PF0, PF0_DATA), ++ PINMUX_GPIO(PF12), ++ PINMUX_GPIO(PF11), ++ PINMUX_GPIO(PF10), ++ PINMUX_GPIO(PF9), ++ PINMUX_GPIO(PF8), ++ PINMUX_GPIO(PF7), ++ PINMUX_GPIO(PF6), ++ PINMUX_GPIO(PF5), ++ PINMUX_GPIO(PF4), ++ PINMUX_GPIO(PF3), ++ PINMUX_GPIO(PF2), ++ PINMUX_GPIO(PF1), ++ PINMUX_GPIO(PF0), + + /* Port G */ +- PINMUX_GPIO(GPIO_PG24, PG24_DATA), +- PINMUX_GPIO(GPIO_PG23, PG23_DATA), +- PINMUX_GPIO(GPIO_PG22, PG22_DATA), +- PINMUX_GPIO(GPIO_PG21, PG21_DATA), +- PINMUX_GPIO(GPIO_PG20, PG20_DATA), +- PINMUX_GPIO(GPIO_PG19, PG19_DATA), +- PINMUX_GPIO(GPIO_PG18, PG18_DATA), +- PINMUX_GPIO(GPIO_PG17, PG17_DATA), +- PINMUX_GPIO(GPIO_PG16, PG16_DATA), +- PINMUX_GPIO(GPIO_PG15, PG15_DATA), +- PINMUX_GPIO(GPIO_PG14, PG14_DATA), +- PINMUX_GPIO(GPIO_PG13, PG13_DATA), +- PINMUX_GPIO(GPIO_PG12, PG12_DATA), +- PINMUX_GPIO(GPIO_PG11, PG11_DATA), +- PINMUX_GPIO(GPIO_PG10, PG10_DATA), +- PINMUX_GPIO(GPIO_PG9, PG9_DATA), +- PINMUX_GPIO(GPIO_PG8, PG8_DATA), +- PINMUX_GPIO(GPIO_PG7, PG7_DATA), +- PINMUX_GPIO(GPIO_PG6, PG6_DATA), +- PINMUX_GPIO(GPIO_PG5, PG5_DATA), +- PINMUX_GPIO(GPIO_PG4, PG4_DATA), +- PINMUX_GPIO(GPIO_PG3, PG3_DATA), +- PINMUX_GPIO(GPIO_PG2, PG2_DATA), +- PINMUX_GPIO(GPIO_PG1, PG1_DATA), +- PINMUX_GPIO(GPIO_PG0, PG0_DATA), ++ PINMUX_GPIO(PG24), ++ PINMUX_GPIO(PG23), ++ PINMUX_GPIO(PG22), ++ PINMUX_GPIO(PG21), ++ PINMUX_GPIO(PG20), ++ PINMUX_GPIO(PG19), ++ PINMUX_GPIO(PG18), ++ PINMUX_GPIO(PG17), ++ PINMUX_GPIO(PG16), ++ PINMUX_GPIO(PG15), ++ PINMUX_GPIO(PG14), ++ PINMUX_GPIO(PG13), ++ PINMUX_GPIO(PG12), ++ PINMUX_GPIO(PG11), ++ PINMUX_GPIO(PG10), ++ PINMUX_GPIO(PG9), ++ PINMUX_GPIO(PG8), ++ PINMUX_GPIO(PG7), ++ PINMUX_GPIO(PG6), ++ PINMUX_GPIO(PG5), ++ PINMUX_GPIO(PG4), ++ PINMUX_GPIO(PG3), ++ PINMUX_GPIO(PG2), ++ PINMUX_GPIO(PG1), ++ PINMUX_GPIO(PG0), + + /* Port H - Port H does not have a Data Register */ + + /* Port I - not on device */ + + /* Port J */ +- PINMUX_GPIO(GPIO_PJ11, PJ11_DATA), +- PINMUX_GPIO(GPIO_PJ10, PJ10_DATA), +- PINMUX_GPIO(GPIO_PJ9, PJ9_DATA), +- PINMUX_GPIO(GPIO_PJ8, PJ8_DATA), +- PINMUX_GPIO(GPIO_PJ7, PJ7_DATA), +- PINMUX_GPIO(GPIO_PJ6, PJ6_DATA), +- PINMUX_GPIO(GPIO_PJ5, PJ5_DATA), +- PINMUX_GPIO(GPIO_PJ4, PJ4_DATA), +- PINMUX_GPIO(GPIO_PJ3, PJ3_DATA), +- PINMUX_GPIO(GPIO_PJ2, PJ2_DATA), +- PINMUX_GPIO(GPIO_PJ1, PJ1_DATA), +- PINMUX_GPIO(GPIO_PJ0, PJ0_DATA), ++ PINMUX_GPIO(PJ11), ++ PINMUX_GPIO(PJ10), ++ PINMUX_GPIO(PJ9), ++ PINMUX_GPIO(PJ8), ++ PINMUX_GPIO(PJ7), ++ PINMUX_GPIO(PJ6), ++ PINMUX_GPIO(PJ5), ++ PINMUX_GPIO(PJ4), ++ PINMUX_GPIO(PJ3), ++ PINMUX_GPIO(PJ2), ++ PINMUX_GPIO(PJ1), ++ PINMUX_GPIO(PJ0), + + /* Port K */ +- PINMUX_GPIO(GPIO_PK11, PK11_DATA), +- PINMUX_GPIO(GPIO_PK10, PK10_DATA), +- PINMUX_GPIO(GPIO_PK9, PK9_DATA), +- PINMUX_GPIO(GPIO_PK8, PK8_DATA), +- PINMUX_GPIO(GPIO_PK7, PK7_DATA), +- PINMUX_GPIO(GPIO_PK6, PK6_DATA), +- PINMUX_GPIO(GPIO_PK5, PK5_DATA), +- PINMUX_GPIO(GPIO_PK4, PK4_DATA), +- PINMUX_GPIO(GPIO_PK3, PK3_DATA), +- PINMUX_GPIO(GPIO_PK2, PK2_DATA), +- PINMUX_GPIO(GPIO_PK1, PK1_DATA), +- PINMUX_GPIO(GPIO_PK0, PK0_DATA), ++ PINMUX_GPIO(PK11), ++ PINMUX_GPIO(PK10), ++ PINMUX_GPIO(PK9), ++ PINMUX_GPIO(PK8), ++ PINMUX_GPIO(PK7), ++ PINMUX_GPIO(PK6), ++ PINMUX_GPIO(PK5), ++ PINMUX_GPIO(PK4), ++ PINMUX_GPIO(PK3), ++ PINMUX_GPIO(PK2), ++ PINMUX_GPIO(PK1), ++ PINMUX_GPIO(PK0), + }; + + #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c +index 415812ff..a19b60f7 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7269.c +@@ -1453,165 +1453,165 @@ static const u16 pinmux_data[] = { + + static struct sh_pfc_pin pinmux_pins[] = { + /* Port A */ +- PINMUX_GPIO(GPIO_PA1, PA1_DATA), +- PINMUX_GPIO(GPIO_PA0, PA0_DATA), ++ PINMUX_GPIO(PA1), ++ PINMUX_GPIO(PA0), + + /* Port B */ +- PINMUX_GPIO(GPIO_PB22, PB22_DATA), +- PINMUX_GPIO(GPIO_PB21, PB21_DATA), +- PINMUX_GPIO(GPIO_PB20, PB20_DATA), +- PINMUX_GPIO(GPIO_PB19, PB19_DATA), +- PINMUX_GPIO(GPIO_PB18, PB18_DATA), +- PINMUX_GPIO(GPIO_PB17, PB17_DATA), +- PINMUX_GPIO(GPIO_PB16, PB16_DATA), +- PINMUX_GPIO(GPIO_PB15, PB15_DATA), +- PINMUX_GPIO(GPIO_PB14, PB14_DATA), +- PINMUX_GPIO(GPIO_PB13, PB13_DATA), +- PINMUX_GPIO(GPIO_PB12, PB12_DATA), +- PINMUX_GPIO(GPIO_PB11, PB11_DATA), +- PINMUX_GPIO(GPIO_PB10, PB10_DATA), +- PINMUX_GPIO(GPIO_PB9, PB9_DATA), +- PINMUX_GPIO(GPIO_PB8, PB8_DATA), +- PINMUX_GPIO(GPIO_PB7, PB7_DATA), +- PINMUX_GPIO(GPIO_PB6, PB6_DATA), +- PINMUX_GPIO(GPIO_PB5, PB5_DATA), +- PINMUX_GPIO(GPIO_PB4, PB4_DATA), +- PINMUX_GPIO(GPIO_PB3, PB3_DATA), +- PINMUX_GPIO(GPIO_PB2, PB2_DATA), +- PINMUX_GPIO(GPIO_PB1, PB1_DATA), ++ PINMUX_GPIO(PB22), ++ PINMUX_GPIO(PB21), ++ PINMUX_GPIO(PB20), ++ PINMUX_GPIO(PB19), ++ PINMUX_GPIO(PB18), ++ PINMUX_GPIO(PB17), ++ PINMUX_GPIO(PB16), ++ PINMUX_GPIO(PB15), ++ PINMUX_GPIO(PB14), ++ PINMUX_GPIO(PB13), ++ PINMUX_GPIO(PB12), ++ PINMUX_GPIO(PB11), ++ PINMUX_GPIO(PB10), ++ PINMUX_GPIO(PB9), ++ PINMUX_GPIO(PB8), ++ PINMUX_GPIO(PB7), ++ PINMUX_GPIO(PB6), ++ PINMUX_GPIO(PB5), ++ PINMUX_GPIO(PB4), ++ PINMUX_GPIO(PB3), ++ PINMUX_GPIO(PB2), ++ PINMUX_GPIO(PB1), + + /* Port C */ +- PINMUX_GPIO(GPIO_PC8, PC8_DATA), +- PINMUX_GPIO(GPIO_PC7, PC7_DATA), +- PINMUX_GPIO(GPIO_PC6, PC6_DATA), +- PINMUX_GPIO(GPIO_PC5, PC5_DATA), +- PINMUX_GPIO(GPIO_PC4, PC4_DATA), +- PINMUX_GPIO(GPIO_PC3, PC3_DATA), +- PINMUX_GPIO(GPIO_PC2, PC2_DATA), +- PINMUX_GPIO(GPIO_PC1, PC1_DATA), +- PINMUX_GPIO(GPIO_PC0, PC0_DATA), ++ PINMUX_GPIO(PC8), ++ PINMUX_GPIO(PC7), ++ PINMUX_GPIO(PC6), ++ PINMUX_GPIO(PC5), ++ PINMUX_GPIO(PC4), ++ PINMUX_GPIO(PC3), ++ PINMUX_GPIO(PC2), ++ PINMUX_GPIO(PC1), ++ PINMUX_GPIO(PC0), + + /* Port D */ +- PINMUX_GPIO(GPIO_PD15, PD15_DATA), +- PINMUX_GPIO(GPIO_PD14, PD14_DATA), +- PINMUX_GPIO(GPIO_PD13, PD13_DATA), +- PINMUX_GPIO(GPIO_PD12, PD12_DATA), +- PINMUX_GPIO(GPIO_PD11, PD11_DATA), +- PINMUX_GPIO(GPIO_PD10, PD10_DATA), +- PINMUX_GPIO(GPIO_PD9, PD9_DATA), +- PINMUX_GPIO(GPIO_PD8, PD8_DATA), +- PINMUX_GPIO(GPIO_PD7, PD7_DATA), +- PINMUX_GPIO(GPIO_PD6, PD6_DATA), +- PINMUX_GPIO(GPIO_PD5, PD5_DATA), +- PINMUX_GPIO(GPIO_PD4, PD4_DATA), +- PINMUX_GPIO(GPIO_PD3, PD3_DATA), +- PINMUX_GPIO(GPIO_PD2, PD2_DATA), +- PINMUX_GPIO(GPIO_PD1, PD1_DATA), +- PINMUX_GPIO(GPIO_PD0, PD0_DATA), ++ PINMUX_GPIO(PD15), ++ PINMUX_GPIO(PD14), ++ PINMUX_GPIO(PD13), ++ PINMUX_GPIO(PD12), ++ PINMUX_GPIO(PD11), ++ PINMUX_GPIO(PD10), ++ PINMUX_GPIO(PD9), ++ PINMUX_GPIO(PD8), ++ PINMUX_GPIO(PD7), ++ PINMUX_GPIO(PD6), ++ PINMUX_GPIO(PD5), ++ PINMUX_GPIO(PD4), ++ PINMUX_GPIO(PD3), ++ PINMUX_GPIO(PD2), ++ PINMUX_GPIO(PD1), ++ PINMUX_GPIO(PD0), + + /* Port E */ +- PINMUX_GPIO(GPIO_PE7, PE7_DATA), +- PINMUX_GPIO(GPIO_PE6, PE6_DATA), +- PINMUX_GPIO(GPIO_PE5, PE5_DATA), +- PINMUX_GPIO(GPIO_PE4, PE4_DATA), +- PINMUX_GPIO(GPIO_PE3, PE3_DATA), +- PINMUX_GPIO(GPIO_PE2, PE2_DATA), +- PINMUX_GPIO(GPIO_PE1, PE1_DATA), +- PINMUX_GPIO(GPIO_PE0, PE0_DATA), ++ PINMUX_GPIO(PE7), ++ PINMUX_GPIO(PE6), ++ PINMUX_GPIO(PE5), ++ PINMUX_GPIO(PE4), ++ PINMUX_GPIO(PE3), ++ PINMUX_GPIO(PE2), ++ PINMUX_GPIO(PE1), ++ PINMUX_GPIO(PE0), + + /* Port F */ +- PINMUX_GPIO(GPIO_PF23, PF23_DATA), +- PINMUX_GPIO(GPIO_PF22, PF22_DATA), +- PINMUX_GPIO(GPIO_PF21, PF21_DATA), +- PINMUX_GPIO(GPIO_PF20, PF20_DATA), +- PINMUX_GPIO(GPIO_PF19, PF19_DATA), +- PINMUX_GPIO(GPIO_PF18, PF18_DATA), +- PINMUX_GPIO(GPIO_PF17, PF17_DATA), +- PINMUX_GPIO(GPIO_PF16, PF16_DATA), +- PINMUX_GPIO(GPIO_PF15, PF15_DATA), +- PINMUX_GPIO(GPIO_PF14, PF14_DATA), +- PINMUX_GPIO(GPIO_PF13, PF13_DATA), +- PINMUX_GPIO(GPIO_PF12, PF12_DATA), +- PINMUX_GPIO(GPIO_PF11, PF11_DATA), +- PINMUX_GPIO(GPIO_PF10, PF10_DATA), +- PINMUX_GPIO(GPIO_PF9, PF9_DATA), +- PINMUX_GPIO(GPIO_PF8, PF8_DATA), +- PINMUX_GPIO(GPIO_PF7, PF7_DATA), +- PINMUX_GPIO(GPIO_PF6, PF6_DATA), +- PINMUX_GPIO(GPIO_PF5, PF5_DATA), +- PINMUX_GPIO(GPIO_PF4, PF4_DATA), +- PINMUX_GPIO(GPIO_PF3, PF3_DATA), +- PINMUX_GPIO(GPIO_PF2, PF2_DATA), +- PINMUX_GPIO(GPIO_PF1, PF1_DATA), +- PINMUX_GPIO(GPIO_PF0, PF0_DATA), ++ PINMUX_GPIO(PF23), ++ PINMUX_GPIO(PF22), ++ PINMUX_GPIO(PF21), ++ PINMUX_GPIO(PF20), ++ PINMUX_GPIO(PF19), ++ PINMUX_GPIO(PF18), ++ PINMUX_GPIO(PF17), ++ PINMUX_GPIO(PF16), ++ PINMUX_GPIO(PF15), ++ PINMUX_GPIO(PF14), ++ PINMUX_GPIO(PF13), ++ PINMUX_GPIO(PF12), ++ PINMUX_GPIO(PF11), ++ PINMUX_GPIO(PF10), ++ PINMUX_GPIO(PF9), ++ PINMUX_GPIO(PF8), ++ PINMUX_GPIO(PF7), ++ PINMUX_GPIO(PF6), ++ PINMUX_GPIO(PF5), ++ PINMUX_GPIO(PF4), ++ PINMUX_GPIO(PF3), ++ PINMUX_GPIO(PF2), ++ PINMUX_GPIO(PF1), ++ PINMUX_GPIO(PF0), + + /* Port G */ +- PINMUX_GPIO(GPIO_PG27, PG27_DATA), +- PINMUX_GPIO(GPIO_PG26, PG26_DATA), +- PINMUX_GPIO(GPIO_PG25, PG25_DATA), +- PINMUX_GPIO(GPIO_PG24, PG24_DATA), +- PINMUX_GPIO(GPIO_PG23, PG23_DATA), +- PINMUX_GPIO(GPIO_PG22, PG22_DATA), +- PINMUX_GPIO(GPIO_PG21, PG21_DATA), +- PINMUX_GPIO(GPIO_PG20, PG20_DATA), +- PINMUX_GPIO(GPIO_PG19, PG19_DATA), +- PINMUX_GPIO(GPIO_PG18, PG18_DATA), +- PINMUX_GPIO(GPIO_PG17, PG17_DATA), +- PINMUX_GPIO(GPIO_PG16, PG16_DATA), +- PINMUX_GPIO(GPIO_PG15, PG15_DATA), +- PINMUX_GPIO(GPIO_PG14, PG14_DATA), +- PINMUX_GPIO(GPIO_PG13, PG13_DATA), +- PINMUX_GPIO(GPIO_PG12, PG12_DATA), +- PINMUX_GPIO(GPIO_PG11, PG11_DATA), +- PINMUX_GPIO(GPIO_PG10, PG10_DATA), +- PINMUX_GPIO(GPIO_PG9, PG9_DATA), +- PINMUX_GPIO(GPIO_PG8, PG8_DATA), +- PINMUX_GPIO(GPIO_PG7, PG7_DATA), +- PINMUX_GPIO(GPIO_PG6, PG6_DATA), +- PINMUX_GPIO(GPIO_PG5, PG5_DATA), +- PINMUX_GPIO(GPIO_PG4, PG4_DATA), +- PINMUX_GPIO(GPIO_PG3, PG3_DATA), +- PINMUX_GPIO(GPIO_PG2, PG2_DATA), +- PINMUX_GPIO(GPIO_PG1, PG1_DATA), +- PINMUX_GPIO(GPIO_PG0, PG0_DATA), ++ PINMUX_GPIO(PG27), ++ PINMUX_GPIO(PG26), ++ PINMUX_GPIO(PG25), ++ PINMUX_GPIO(PG24), ++ PINMUX_GPIO(PG23), ++ PINMUX_GPIO(PG22), ++ PINMUX_GPIO(PG21), ++ PINMUX_GPIO(PG20), ++ PINMUX_GPIO(PG19), ++ PINMUX_GPIO(PG18), ++ PINMUX_GPIO(PG17), ++ PINMUX_GPIO(PG16), ++ PINMUX_GPIO(PG15), ++ PINMUX_GPIO(PG14), ++ PINMUX_GPIO(PG13), ++ PINMUX_GPIO(PG12), ++ PINMUX_GPIO(PG11), ++ PINMUX_GPIO(PG10), ++ PINMUX_GPIO(PG9), ++ PINMUX_GPIO(PG8), ++ PINMUX_GPIO(PG7), ++ PINMUX_GPIO(PG6), ++ PINMUX_GPIO(PG5), ++ PINMUX_GPIO(PG4), ++ PINMUX_GPIO(PG3), ++ PINMUX_GPIO(PG2), ++ PINMUX_GPIO(PG1), ++ PINMUX_GPIO(PG0), + + /* Port H - Port H does not have a Data Register */ + + /* Port I - not on device */ + + /* Port J */ +- PINMUX_GPIO(GPIO_PJ31, PJ31_DATA), +- PINMUX_GPIO(GPIO_PJ30, PJ30_DATA), +- PINMUX_GPIO(GPIO_PJ29, PJ29_DATA), +- PINMUX_GPIO(GPIO_PJ28, PJ28_DATA), +- PINMUX_GPIO(GPIO_PJ27, PJ27_DATA), +- PINMUX_GPIO(GPIO_PJ26, PJ26_DATA), +- PINMUX_GPIO(GPIO_PJ25, PJ25_DATA), +- PINMUX_GPIO(GPIO_PJ24, PJ24_DATA), +- PINMUX_GPIO(GPIO_PJ23, PJ23_DATA), +- PINMUX_GPIO(GPIO_PJ22, PJ22_DATA), +- PINMUX_GPIO(GPIO_PJ21, PJ21_DATA), +- PINMUX_GPIO(GPIO_PJ20, PJ20_DATA), +- PINMUX_GPIO(GPIO_PJ19, PJ19_DATA), +- PINMUX_GPIO(GPIO_PJ18, PJ18_DATA), +- PINMUX_GPIO(GPIO_PJ17, PJ17_DATA), +- PINMUX_GPIO(GPIO_PJ16, PJ16_DATA), +- PINMUX_GPIO(GPIO_PJ15, PJ15_DATA), +- PINMUX_GPIO(GPIO_PJ14, PJ14_DATA), +- PINMUX_GPIO(GPIO_PJ13, PJ13_DATA), +- PINMUX_GPIO(GPIO_PJ12, PJ12_DATA), +- PINMUX_GPIO(GPIO_PJ11, PJ11_DATA), +- PINMUX_GPIO(GPIO_PJ10, PJ10_DATA), +- PINMUX_GPIO(GPIO_PJ9, PJ9_DATA), +- PINMUX_GPIO(GPIO_PJ8, PJ8_DATA), +- PINMUX_GPIO(GPIO_PJ7, PJ7_DATA), +- PINMUX_GPIO(GPIO_PJ6, PJ6_DATA), +- PINMUX_GPIO(GPIO_PJ5, PJ5_DATA), +- PINMUX_GPIO(GPIO_PJ4, PJ4_DATA), +- PINMUX_GPIO(GPIO_PJ3, PJ3_DATA), +- PINMUX_GPIO(GPIO_PJ2, PJ2_DATA), +- PINMUX_GPIO(GPIO_PJ1, PJ1_DATA), +- PINMUX_GPIO(GPIO_PJ0, PJ0_DATA), ++ PINMUX_GPIO(PJ31), ++ PINMUX_GPIO(PJ30), ++ PINMUX_GPIO(PJ29), ++ PINMUX_GPIO(PJ28), ++ PINMUX_GPIO(PJ27), ++ PINMUX_GPIO(PJ26), ++ PINMUX_GPIO(PJ25), ++ PINMUX_GPIO(PJ24), ++ PINMUX_GPIO(PJ23), ++ PINMUX_GPIO(PJ22), ++ PINMUX_GPIO(PJ21), ++ PINMUX_GPIO(PJ20), ++ PINMUX_GPIO(PJ19), ++ PINMUX_GPIO(PJ18), ++ PINMUX_GPIO(PJ17), ++ PINMUX_GPIO(PJ16), ++ PINMUX_GPIO(PJ15), ++ PINMUX_GPIO(PJ14), ++ PINMUX_GPIO(PJ13), ++ PINMUX_GPIO(PJ12), ++ PINMUX_GPIO(PJ11), ++ PINMUX_GPIO(PJ10), ++ PINMUX_GPIO(PJ9), ++ PINMUX_GPIO(PJ8), ++ PINMUX_GPIO(PJ7), ++ PINMUX_GPIO(PJ6), ++ PINMUX_GPIO(PJ5), ++ PINMUX_GPIO(PJ4), ++ PINMUX_GPIO(PJ3), ++ PINMUX_GPIO(PJ2), ++ PINMUX_GPIO(PJ1), ++ PINMUX_GPIO(PJ0), + }; + + #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7720.c b/drivers/pinctrl/sh-pfc/pfc-sh7720.c +index 1009fc9c..7a26809e 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7720.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7720.c +@@ -578,157 +578,157 @@ static const u16 pinmux_data[] = { + + static struct sh_pfc_pin pinmux_pins[] = { + /* PTA */ +- PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), +- PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), +- PINMUX_GPIO(GPIO_PTA5, PTA5_DATA), +- PINMUX_GPIO(GPIO_PTA4, PTA4_DATA), +- PINMUX_GPIO(GPIO_PTA3, PTA3_DATA), +- PINMUX_GPIO(GPIO_PTA2, PTA2_DATA), +- PINMUX_GPIO(GPIO_PTA1, PTA1_DATA), +- PINMUX_GPIO(GPIO_PTA0, PTA0_DATA), ++ PINMUX_GPIO(PTA7), ++ PINMUX_GPIO(PTA6), ++ PINMUX_GPIO(PTA5), ++ PINMUX_GPIO(PTA4), ++ PINMUX_GPIO(PTA3), ++ PINMUX_GPIO(PTA2), ++ PINMUX_GPIO(PTA1), ++ PINMUX_GPIO(PTA0), + + /* PTB */ +- PINMUX_GPIO(GPIO_PTB7, PTB7_DATA), +- PINMUX_GPIO(GPIO_PTB6, PTB6_DATA), +- PINMUX_GPIO(GPIO_PTB5, PTB5_DATA), +- PINMUX_GPIO(GPIO_PTB4, PTB4_DATA), +- PINMUX_GPIO(GPIO_PTB3, PTB3_DATA), +- PINMUX_GPIO(GPIO_PTB2, PTB2_DATA), +- PINMUX_GPIO(GPIO_PTB1, PTB1_DATA), +- PINMUX_GPIO(GPIO_PTB0, PTB0_DATA), ++ PINMUX_GPIO(PTB7), ++ PINMUX_GPIO(PTB6), ++ PINMUX_GPIO(PTB5), ++ PINMUX_GPIO(PTB4), ++ PINMUX_GPIO(PTB3), ++ PINMUX_GPIO(PTB2), ++ PINMUX_GPIO(PTB1), ++ PINMUX_GPIO(PTB0), + + /* PTC */ +- PINMUX_GPIO(GPIO_PTC7, PTC7_DATA), +- PINMUX_GPIO(GPIO_PTC6, PTC6_DATA), +- PINMUX_GPIO(GPIO_PTC5, PTC5_DATA), +- PINMUX_GPIO(GPIO_PTC4, PTC4_DATA), +- PINMUX_GPIO(GPIO_PTC3, PTC3_DATA), +- PINMUX_GPIO(GPIO_PTC2, PTC2_DATA), +- PINMUX_GPIO(GPIO_PTC1, PTC1_DATA), +- PINMUX_GPIO(GPIO_PTC0, PTC0_DATA), ++ PINMUX_GPIO(PTC7), ++ PINMUX_GPIO(PTC6), ++ PINMUX_GPIO(PTC5), ++ PINMUX_GPIO(PTC4), ++ PINMUX_GPIO(PTC3), ++ PINMUX_GPIO(PTC2), ++ PINMUX_GPIO(PTC1), ++ PINMUX_GPIO(PTC0), + + /* PTD */ +- PINMUX_GPIO(GPIO_PTD7, PTD7_DATA), +- PINMUX_GPIO(GPIO_PTD6, PTD6_DATA), +- PINMUX_GPIO(GPIO_PTD5, PTD5_DATA), +- PINMUX_GPIO(GPIO_PTD4, PTD4_DATA), +- PINMUX_GPIO(GPIO_PTD3, PTD3_DATA), +- PINMUX_GPIO(GPIO_PTD2, PTD2_DATA), +- PINMUX_GPIO(GPIO_PTD1, PTD1_DATA), +- PINMUX_GPIO(GPIO_PTD0, PTD0_DATA), ++ PINMUX_GPIO(PTD7), ++ PINMUX_GPIO(PTD6), ++ PINMUX_GPIO(PTD5), ++ PINMUX_GPIO(PTD4), ++ PINMUX_GPIO(PTD3), ++ PINMUX_GPIO(PTD2), ++ PINMUX_GPIO(PTD1), ++ PINMUX_GPIO(PTD0), + + /* PTE */ +- PINMUX_GPIO(GPIO_PTE6, PTE6_DATA), +- PINMUX_GPIO(GPIO_PTE5, PTE5_DATA), +- PINMUX_GPIO(GPIO_PTE4, PTE4_DATA), +- PINMUX_GPIO(GPIO_PTE3, PTE3_DATA), +- PINMUX_GPIO(GPIO_PTE2, PTE2_DATA), +- PINMUX_GPIO(GPIO_PTE1, PTE1_DATA), +- PINMUX_GPIO(GPIO_PTE0, PTE0_DATA), ++ PINMUX_GPIO(PTE6), ++ PINMUX_GPIO(PTE5), ++ PINMUX_GPIO(PTE4), ++ PINMUX_GPIO(PTE3), ++ PINMUX_GPIO(PTE2), ++ PINMUX_GPIO(PTE1), ++ PINMUX_GPIO(PTE0), + + /* PTF */ +- PINMUX_GPIO(GPIO_PTF6, PTF6_DATA), +- PINMUX_GPIO(GPIO_PTF5, PTF5_DATA), +- PINMUX_GPIO(GPIO_PTF4, PTF4_DATA), +- PINMUX_GPIO(GPIO_PTF3, PTF3_DATA), +- PINMUX_GPIO(GPIO_PTF2, PTF2_DATA), +- PINMUX_GPIO(GPIO_PTF1, PTF1_DATA), +- PINMUX_GPIO(GPIO_PTF0, PTF0_DATA), ++ PINMUX_GPIO(PTF6), ++ PINMUX_GPIO(PTF5), ++ PINMUX_GPIO(PTF4), ++ PINMUX_GPIO(PTF3), ++ PINMUX_GPIO(PTF2), ++ PINMUX_GPIO(PTF1), ++ PINMUX_GPIO(PTF0), + + /* PTG */ +- PINMUX_GPIO(GPIO_PTG6, PTG6_DATA), +- PINMUX_GPIO(GPIO_PTG5, PTG5_DATA), +- PINMUX_GPIO(GPIO_PTG4, PTG4_DATA), +- PINMUX_GPIO(GPIO_PTG3, PTG3_DATA), +- PINMUX_GPIO(GPIO_PTG2, PTG2_DATA), +- PINMUX_GPIO(GPIO_PTG1, PTG1_DATA), +- PINMUX_GPIO(GPIO_PTG0, PTG0_DATA), ++ PINMUX_GPIO(PTG6), ++ PINMUX_GPIO(PTG5), ++ PINMUX_GPIO(PTG4), ++ PINMUX_GPIO(PTG3), ++ PINMUX_GPIO(PTG2), ++ PINMUX_GPIO(PTG1), ++ PINMUX_GPIO(PTG0), + + /* PTH */ +- PINMUX_GPIO(GPIO_PTH6, PTH6_DATA), +- PINMUX_GPIO(GPIO_PTH5, PTH5_DATA), +- PINMUX_GPIO(GPIO_PTH4, PTH4_DATA), +- PINMUX_GPIO(GPIO_PTH3, PTH3_DATA), +- PINMUX_GPIO(GPIO_PTH2, PTH2_DATA), +- PINMUX_GPIO(GPIO_PTH1, PTH1_DATA), +- PINMUX_GPIO(GPIO_PTH0, PTH0_DATA), ++ PINMUX_GPIO(PTH6), ++ PINMUX_GPIO(PTH5), ++ PINMUX_GPIO(PTH4), ++ PINMUX_GPIO(PTH3), ++ PINMUX_GPIO(PTH2), ++ PINMUX_GPIO(PTH1), ++ PINMUX_GPIO(PTH0), + + /* PTJ */ +- PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA), +- PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA), +- PINMUX_GPIO(GPIO_PTJ4, PTJ4_DATA), +- PINMUX_GPIO(GPIO_PTJ3, PTJ3_DATA), +- PINMUX_GPIO(GPIO_PTJ2, PTJ2_DATA), +- PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA), +- PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA), ++ PINMUX_GPIO(PTJ6), ++ PINMUX_GPIO(PTJ5), ++ PINMUX_GPIO(PTJ4), ++ PINMUX_GPIO(PTJ3), ++ PINMUX_GPIO(PTJ2), ++ PINMUX_GPIO(PTJ1), ++ PINMUX_GPIO(PTJ0), + + /* PTK */ +- PINMUX_GPIO(GPIO_PTK3, PTK3_DATA), +- PINMUX_GPIO(GPIO_PTK2, PTK2_DATA), +- PINMUX_GPIO(GPIO_PTK1, PTK1_DATA), +- PINMUX_GPIO(GPIO_PTK0, PTK0_DATA), ++ PINMUX_GPIO(PTK3), ++ PINMUX_GPIO(PTK2), ++ PINMUX_GPIO(PTK1), ++ PINMUX_GPIO(PTK0), + + /* PTL */ +- PINMUX_GPIO(GPIO_PTL7, PTL7_DATA), +- PINMUX_GPIO(GPIO_PTL6, PTL6_DATA), +- PINMUX_GPIO(GPIO_PTL5, PTL5_DATA), +- PINMUX_GPIO(GPIO_PTL4, PTL4_DATA), +- PINMUX_GPIO(GPIO_PTL3, PTL3_DATA), ++ PINMUX_GPIO(PTL7), ++ PINMUX_GPIO(PTL6), ++ PINMUX_GPIO(PTL5), ++ PINMUX_GPIO(PTL4), ++ PINMUX_GPIO(PTL3), + + /* PTM */ +- PINMUX_GPIO(GPIO_PTM7, PTM7_DATA), +- PINMUX_GPIO(GPIO_PTM6, PTM6_DATA), +- PINMUX_GPIO(GPIO_PTM5, PTM5_DATA), +- PINMUX_GPIO(GPIO_PTM4, PTM4_DATA), +- PINMUX_GPIO(GPIO_PTM3, PTM3_DATA), +- PINMUX_GPIO(GPIO_PTM2, PTM2_DATA), +- PINMUX_GPIO(GPIO_PTM1, PTM1_DATA), +- PINMUX_GPIO(GPIO_PTM0, PTM0_DATA), ++ PINMUX_GPIO(PTM7), ++ PINMUX_GPIO(PTM6), ++ PINMUX_GPIO(PTM5), ++ PINMUX_GPIO(PTM4), ++ PINMUX_GPIO(PTM3), ++ PINMUX_GPIO(PTM2), ++ PINMUX_GPIO(PTM1), ++ PINMUX_GPIO(PTM0), + + /* PTP */ +- PINMUX_GPIO(GPIO_PTP4, PTP4_DATA), +- PINMUX_GPIO(GPIO_PTP3, PTP3_DATA), +- PINMUX_GPIO(GPIO_PTP2, PTP2_DATA), +- PINMUX_GPIO(GPIO_PTP1, PTP1_DATA), +- PINMUX_GPIO(GPIO_PTP0, PTP0_DATA), ++ PINMUX_GPIO(PTP4), ++ PINMUX_GPIO(PTP3), ++ PINMUX_GPIO(PTP2), ++ PINMUX_GPIO(PTP1), ++ PINMUX_GPIO(PTP0), + + /* PTR */ +- PINMUX_GPIO(GPIO_PTR7, PTR7_DATA), +- PINMUX_GPIO(GPIO_PTR6, PTR6_DATA), +- PINMUX_GPIO(GPIO_PTR5, PTR5_DATA), +- PINMUX_GPIO(GPIO_PTR4, PTR4_DATA), +- PINMUX_GPIO(GPIO_PTR3, PTR3_DATA), +- PINMUX_GPIO(GPIO_PTR2, PTR2_DATA), +- PINMUX_GPIO(GPIO_PTR1, PTR1_DATA), +- PINMUX_GPIO(GPIO_PTR0, PTR0_DATA), ++ PINMUX_GPIO(PTR7), ++ PINMUX_GPIO(PTR6), ++ PINMUX_GPIO(PTR5), ++ PINMUX_GPIO(PTR4), ++ PINMUX_GPIO(PTR3), ++ PINMUX_GPIO(PTR2), ++ PINMUX_GPIO(PTR1), ++ PINMUX_GPIO(PTR0), + + /* PTS */ +- PINMUX_GPIO(GPIO_PTS4, PTS4_DATA), +- PINMUX_GPIO(GPIO_PTS3, PTS3_DATA), +- PINMUX_GPIO(GPIO_PTS2, PTS2_DATA), +- PINMUX_GPIO(GPIO_PTS1, PTS1_DATA), +- PINMUX_GPIO(GPIO_PTS0, PTS0_DATA), ++ PINMUX_GPIO(PTS4), ++ PINMUX_GPIO(PTS3), ++ PINMUX_GPIO(PTS2), ++ PINMUX_GPIO(PTS1), ++ PINMUX_GPIO(PTS0), + + /* PTT */ +- PINMUX_GPIO(GPIO_PTT4, PTT4_DATA), +- PINMUX_GPIO(GPIO_PTT3, PTT3_DATA), +- PINMUX_GPIO(GPIO_PTT2, PTT2_DATA), +- PINMUX_GPIO(GPIO_PTT1, PTT1_DATA), +- PINMUX_GPIO(GPIO_PTT0, PTT0_DATA), ++ PINMUX_GPIO(PTT4), ++ PINMUX_GPIO(PTT3), ++ PINMUX_GPIO(PTT2), ++ PINMUX_GPIO(PTT1), ++ PINMUX_GPIO(PTT0), + + /* PTU */ +- PINMUX_GPIO(GPIO_PTU4, PTU4_DATA), +- PINMUX_GPIO(GPIO_PTU3, PTU3_DATA), +- PINMUX_GPIO(GPIO_PTU2, PTU2_DATA), +- PINMUX_GPIO(GPIO_PTU1, PTU1_DATA), +- PINMUX_GPIO(GPIO_PTU0, PTU0_DATA), ++ PINMUX_GPIO(PTU4), ++ PINMUX_GPIO(PTU3), ++ PINMUX_GPIO(PTU2), ++ PINMUX_GPIO(PTU1), ++ PINMUX_GPIO(PTU0), + + /* PTV */ +- PINMUX_GPIO(GPIO_PTV4, PTV4_DATA), +- PINMUX_GPIO(GPIO_PTV3, PTV3_DATA), +- PINMUX_GPIO(GPIO_PTV2, PTV2_DATA), +- PINMUX_GPIO(GPIO_PTV1, PTV1_DATA), +- PINMUX_GPIO(GPIO_PTV0, PTV0_DATA), ++ PINMUX_GPIO(PTV4), ++ PINMUX_GPIO(PTV3), ++ PINMUX_GPIO(PTV2), ++ PINMUX_GPIO(PTV1), ++ PINMUX_GPIO(PTV0), + }; + + #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7722.c b/drivers/pinctrl/sh-pfc/pfc-sh7722.c +index 0c8d011f..add30934 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7722.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7722.c +@@ -756,199 +756,199 @@ static const u16 pinmux_data[] = { + + static struct sh_pfc_pin pinmux_pins[] = { + /* PTA */ +- PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), +- PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), +- PINMUX_GPIO(GPIO_PTA5, PTA5_DATA), +- PINMUX_GPIO(GPIO_PTA4, PTA4_DATA), +- PINMUX_GPIO(GPIO_PTA3, PTA3_DATA), +- PINMUX_GPIO(GPIO_PTA2, PTA2_DATA), +- PINMUX_GPIO(GPIO_PTA1, PTA1_DATA), +- PINMUX_GPIO(GPIO_PTA0, PTA0_DATA), ++ PINMUX_GPIO(PTA7), ++ PINMUX_GPIO(PTA6), ++ PINMUX_GPIO(PTA5), ++ PINMUX_GPIO(PTA4), ++ PINMUX_GPIO(PTA3), ++ PINMUX_GPIO(PTA2), ++ PINMUX_GPIO(PTA1), ++ PINMUX_GPIO(PTA0), + + /* PTB */ +- PINMUX_GPIO(GPIO_PTB7, PTB7_DATA), +- PINMUX_GPIO(GPIO_PTB6, PTB6_DATA), +- PINMUX_GPIO(GPIO_PTB5, PTB5_DATA), +- PINMUX_GPIO(GPIO_PTB4, PTB4_DATA), +- PINMUX_GPIO(GPIO_PTB3, PTB3_DATA), +- PINMUX_GPIO(GPIO_PTB2, PTB2_DATA), +- PINMUX_GPIO(GPIO_PTB1, PTB1_DATA), +- PINMUX_GPIO(GPIO_PTB0, PTB0_DATA), ++ PINMUX_GPIO(PTB7), ++ PINMUX_GPIO(PTB6), ++ PINMUX_GPIO(PTB5), ++ PINMUX_GPIO(PTB4), ++ PINMUX_GPIO(PTB3), ++ PINMUX_GPIO(PTB2), ++ PINMUX_GPIO(PTB1), ++ PINMUX_GPIO(PTB0), + + /* PTC */ +- PINMUX_GPIO(GPIO_PTC7, PTC7_DATA), +- PINMUX_GPIO(GPIO_PTC5, PTC5_DATA), +- PINMUX_GPIO(GPIO_PTC4, PTC4_DATA), +- PINMUX_GPIO(GPIO_PTC3, PTC3_DATA), +- PINMUX_GPIO(GPIO_PTC2, PTC2_DATA), +- PINMUX_GPIO(GPIO_PTC0, PTC0_DATA), ++ PINMUX_GPIO(PTC7), ++ PINMUX_GPIO(PTC5), ++ PINMUX_GPIO(PTC4), ++ PINMUX_GPIO(PTC3), ++ PINMUX_GPIO(PTC2), ++ PINMUX_GPIO(PTC0), + + /* PTD */ +- PINMUX_GPIO(GPIO_PTD7, PTD7_DATA), +- PINMUX_GPIO(GPIO_PTD6, PTD6_DATA), +- PINMUX_GPIO(GPIO_PTD5, PTD5_DATA), +- PINMUX_GPIO(GPIO_PTD4, PTD4_DATA), +- PINMUX_GPIO(GPIO_PTD3, PTD3_DATA), +- PINMUX_GPIO(GPIO_PTD2, PTD2_DATA), +- PINMUX_GPIO(GPIO_PTD1, PTD1_DATA), +- PINMUX_GPIO(GPIO_PTD0, PTD0_DATA), ++ PINMUX_GPIO(PTD7), ++ PINMUX_GPIO(PTD6), ++ PINMUX_GPIO(PTD5), ++ PINMUX_GPIO(PTD4), ++ PINMUX_GPIO(PTD3), ++ PINMUX_GPIO(PTD2), ++ PINMUX_GPIO(PTD1), ++ PINMUX_GPIO(PTD0), + + /* PTE */ +- PINMUX_GPIO(GPIO_PTE7, PTE7_DATA), +- PINMUX_GPIO(GPIO_PTE6, PTE6_DATA), +- PINMUX_GPIO(GPIO_PTE5, PTE5_DATA), +- PINMUX_GPIO(GPIO_PTE4, PTE4_DATA), +- PINMUX_GPIO(GPIO_PTE1, PTE1_DATA), +- PINMUX_GPIO(GPIO_PTE0, PTE0_DATA), ++ PINMUX_GPIO(PTE7), ++ PINMUX_GPIO(PTE6), ++ PINMUX_GPIO(PTE5), ++ PINMUX_GPIO(PTE4), ++ PINMUX_GPIO(PTE1), ++ PINMUX_GPIO(PTE0), + + /* PTF */ +- PINMUX_GPIO(GPIO_PTF6, PTF6_DATA), +- PINMUX_GPIO(GPIO_PTF5, PTF5_DATA), +- PINMUX_GPIO(GPIO_PTF4, PTF4_DATA), +- PINMUX_GPIO(GPIO_PTF3, PTF3_DATA), +- PINMUX_GPIO(GPIO_PTF2, PTF2_DATA), +- PINMUX_GPIO(GPIO_PTF1, PTF1_DATA), +- PINMUX_GPIO(GPIO_PTF0, PTF0_DATA), ++ PINMUX_GPIO(PTF6), ++ PINMUX_GPIO(PTF5), ++ PINMUX_GPIO(PTF4), ++ PINMUX_GPIO(PTF3), ++ PINMUX_GPIO(PTF2), ++ PINMUX_GPIO(PTF1), ++ PINMUX_GPIO(PTF0), + + /* PTG */ +- PINMUX_GPIO(GPIO_PTG4, PTG4_DATA), +- PINMUX_GPIO(GPIO_PTG3, PTG3_DATA), +- PINMUX_GPIO(GPIO_PTG2, PTG2_DATA), +- PINMUX_GPIO(GPIO_PTG1, PTG1_DATA), +- PINMUX_GPIO(GPIO_PTG0, PTG0_DATA), ++ PINMUX_GPIO(PTG4), ++ PINMUX_GPIO(PTG3), ++ PINMUX_GPIO(PTG2), ++ PINMUX_GPIO(PTG1), ++ PINMUX_GPIO(PTG0), + + /* PTH */ +- PINMUX_GPIO(GPIO_PTH7, PTH7_DATA), +- PINMUX_GPIO(GPIO_PTH6, PTH6_DATA), +- PINMUX_GPIO(GPIO_PTH5, PTH5_DATA), +- PINMUX_GPIO(GPIO_PTH4, PTH4_DATA), +- PINMUX_GPIO(GPIO_PTH3, PTH3_DATA), +- PINMUX_GPIO(GPIO_PTH2, PTH2_DATA), +- PINMUX_GPIO(GPIO_PTH1, PTH1_DATA), +- PINMUX_GPIO(GPIO_PTH0, PTH0_DATA), ++ PINMUX_GPIO(PTH7), ++ PINMUX_GPIO(PTH6), ++ PINMUX_GPIO(PTH5), ++ PINMUX_GPIO(PTH4), ++ PINMUX_GPIO(PTH3), ++ PINMUX_GPIO(PTH2), ++ PINMUX_GPIO(PTH1), ++ PINMUX_GPIO(PTH0), + + /* PTJ */ +- PINMUX_GPIO(GPIO_PTJ7, PTJ7_DATA), +- PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA), +- PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA), +- PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA), +- PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA), ++ PINMUX_GPIO(PTJ7), ++ PINMUX_GPIO(PTJ6), ++ PINMUX_GPIO(PTJ5), ++ PINMUX_GPIO(PTJ1), ++ PINMUX_GPIO(PTJ0), + + /* PTK */ +- PINMUX_GPIO(GPIO_PTK6, PTK6_DATA), +- PINMUX_GPIO(GPIO_PTK5, PTK5_DATA), +- PINMUX_GPIO(GPIO_PTK4, PTK4_DATA), +- PINMUX_GPIO(GPIO_PTK3, PTK3_DATA), +- PINMUX_GPIO(GPIO_PTK2, PTK2_DATA), +- PINMUX_GPIO(GPIO_PTK1, PTK1_DATA), +- PINMUX_GPIO(GPIO_PTK0, PTK0_DATA), ++ PINMUX_GPIO(PTK6), ++ PINMUX_GPIO(PTK5), ++ PINMUX_GPIO(PTK4), ++ PINMUX_GPIO(PTK3), ++ PINMUX_GPIO(PTK2), ++ PINMUX_GPIO(PTK1), ++ PINMUX_GPIO(PTK0), + + /* PTL */ +- PINMUX_GPIO(GPIO_PTL7, PTL7_DATA), +- PINMUX_GPIO(GPIO_PTL6, PTL6_DATA), +- PINMUX_GPIO(GPIO_PTL5, PTL5_DATA), +- PINMUX_GPIO(GPIO_PTL4, PTL4_DATA), +- PINMUX_GPIO(GPIO_PTL3, PTL3_DATA), +- PINMUX_GPIO(GPIO_PTL2, PTL2_DATA), +- PINMUX_GPIO(GPIO_PTL1, PTL1_DATA), +- PINMUX_GPIO(GPIO_PTL0, PTL0_DATA), ++ PINMUX_GPIO(PTL7), ++ PINMUX_GPIO(PTL6), ++ PINMUX_GPIO(PTL5), ++ PINMUX_GPIO(PTL4), ++ PINMUX_GPIO(PTL3), ++ PINMUX_GPIO(PTL2), ++ PINMUX_GPIO(PTL1), ++ PINMUX_GPIO(PTL0), + + /* PTM */ +- PINMUX_GPIO(GPIO_PTM7, PTM7_DATA), +- PINMUX_GPIO(GPIO_PTM6, PTM6_DATA), +- PINMUX_GPIO(GPIO_PTM5, PTM5_DATA), +- PINMUX_GPIO(GPIO_PTM4, PTM4_DATA), +- PINMUX_GPIO(GPIO_PTM3, PTM3_DATA), +- PINMUX_GPIO(GPIO_PTM2, PTM2_DATA), +- PINMUX_GPIO(GPIO_PTM1, PTM1_DATA), +- PINMUX_GPIO(GPIO_PTM0, PTM0_DATA), ++ PINMUX_GPIO(PTM7), ++ PINMUX_GPIO(PTM6), ++ PINMUX_GPIO(PTM5), ++ PINMUX_GPIO(PTM4), ++ PINMUX_GPIO(PTM3), ++ PINMUX_GPIO(PTM2), ++ PINMUX_GPIO(PTM1), ++ PINMUX_GPIO(PTM0), + + /* PTN */ +- PINMUX_GPIO(GPIO_PTN7, PTN7_DATA), +- PINMUX_GPIO(GPIO_PTN6, PTN6_DATA), +- PINMUX_GPIO(GPIO_PTN5, PTN5_DATA), +- PINMUX_GPIO(GPIO_PTN4, PTN4_DATA), +- PINMUX_GPIO(GPIO_PTN3, PTN3_DATA), +- PINMUX_GPIO(GPIO_PTN2, PTN2_DATA), +- PINMUX_GPIO(GPIO_PTN1, PTN1_DATA), +- PINMUX_GPIO(GPIO_PTN0, PTN0_DATA), ++ PINMUX_GPIO(PTN7), ++ PINMUX_GPIO(PTN6), ++ PINMUX_GPIO(PTN5), ++ PINMUX_GPIO(PTN4), ++ PINMUX_GPIO(PTN3), ++ PINMUX_GPIO(PTN2), ++ PINMUX_GPIO(PTN1), ++ PINMUX_GPIO(PTN0), + + /* PTQ */ +- PINMUX_GPIO(GPIO_PTQ6, PTQ6_DATA), +- PINMUX_GPIO(GPIO_PTQ5, PTQ5_DATA), +- PINMUX_GPIO(GPIO_PTQ4, PTQ4_DATA), +- PINMUX_GPIO(GPIO_PTQ3, PTQ3_DATA), +- PINMUX_GPIO(GPIO_PTQ2, PTQ2_DATA), +- PINMUX_GPIO(GPIO_PTQ1, PTQ1_DATA), +- PINMUX_GPIO(GPIO_PTQ0, PTQ0_DATA), ++ PINMUX_GPIO(PTQ6), ++ PINMUX_GPIO(PTQ5), ++ PINMUX_GPIO(PTQ4), ++ PINMUX_GPIO(PTQ3), ++ PINMUX_GPIO(PTQ2), ++ PINMUX_GPIO(PTQ1), ++ PINMUX_GPIO(PTQ0), + + /* PTR */ +- PINMUX_GPIO(GPIO_PTR4, PTR4_DATA), +- PINMUX_GPIO(GPIO_PTR3, PTR3_DATA), +- PINMUX_GPIO(GPIO_PTR2, PTR2_DATA), +- PINMUX_GPIO(GPIO_PTR1, PTR1_DATA), +- PINMUX_GPIO(GPIO_PTR0, PTR0_DATA), ++ PINMUX_GPIO(PTR4), ++ PINMUX_GPIO(PTR3), ++ PINMUX_GPIO(PTR2), ++ PINMUX_GPIO(PTR1), ++ PINMUX_GPIO(PTR0), + + /* PTS */ +- PINMUX_GPIO(GPIO_PTS4, PTS4_DATA), +- PINMUX_GPIO(GPIO_PTS3, PTS3_DATA), +- PINMUX_GPIO(GPIO_PTS2, PTS2_DATA), +- PINMUX_GPIO(GPIO_PTS1, PTS1_DATA), +- PINMUX_GPIO(GPIO_PTS0, PTS0_DATA), ++ PINMUX_GPIO(PTS4), ++ PINMUX_GPIO(PTS3), ++ PINMUX_GPIO(PTS2), ++ PINMUX_GPIO(PTS1), ++ PINMUX_GPIO(PTS0), + + /* PTT */ +- PINMUX_GPIO(GPIO_PTT4, PTT4_DATA), +- PINMUX_GPIO(GPIO_PTT3, PTT3_DATA), +- PINMUX_GPIO(GPIO_PTT2, PTT2_DATA), +- PINMUX_GPIO(GPIO_PTT1, PTT1_DATA), +- PINMUX_GPIO(GPIO_PTT0, PTT0_DATA), ++ PINMUX_GPIO(PTT4), ++ PINMUX_GPIO(PTT3), ++ PINMUX_GPIO(PTT2), ++ PINMUX_GPIO(PTT1), ++ PINMUX_GPIO(PTT0), + + /* PTU */ +- PINMUX_GPIO(GPIO_PTU4, PTU4_DATA), +- PINMUX_GPIO(GPIO_PTU3, PTU3_DATA), +- PINMUX_GPIO(GPIO_PTU2, PTU2_DATA), +- PINMUX_GPIO(GPIO_PTU1, PTU1_DATA), +- PINMUX_GPIO(GPIO_PTU0, PTU0_DATA), ++ PINMUX_GPIO(PTU4), ++ PINMUX_GPIO(PTU3), ++ PINMUX_GPIO(PTU2), ++ PINMUX_GPIO(PTU1), ++ PINMUX_GPIO(PTU0), + + /* PTV */ +- PINMUX_GPIO(GPIO_PTV4, PTV4_DATA), +- PINMUX_GPIO(GPIO_PTV3, PTV3_DATA), +- PINMUX_GPIO(GPIO_PTV2, PTV2_DATA), +- PINMUX_GPIO(GPIO_PTV1, PTV1_DATA), +- PINMUX_GPIO(GPIO_PTV0, PTV0_DATA), ++ PINMUX_GPIO(PTV4), ++ PINMUX_GPIO(PTV3), ++ PINMUX_GPIO(PTV2), ++ PINMUX_GPIO(PTV1), ++ PINMUX_GPIO(PTV0), + + /* PTW */ +- PINMUX_GPIO(GPIO_PTW6, PTW6_DATA), +- PINMUX_GPIO(GPIO_PTW5, PTW5_DATA), +- PINMUX_GPIO(GPIO_PTW4, PTW4_DATA), +- PINMUX_GPIO(GPIO_PTW3, PTW3_DATA), +- PINMUX_GPIO(GPIO_PTW2, PTW2_DATA), +- PINMUX_GPIO(GPIO_PTW1, PTW1_DATA), +- PINMUX_GPIO(GPIO_PTW0, PTW0_DATA), ++ PINMUX_GPIO(PTW6), ++ PINMUX_GPIO(PTW5), ++ PINMUX_GPIO(PTW4), ++ PINMUX_GPIO(PTW3), ++ PINMUX_GPIO(PTW2), ++ PINMUX_GPIO(PTW1), ++ PINMUX_GPIO(PTW0), + + /* PTX */ +- PINMUX_GPIO(GPIO_PTX6, PTX6_DATA), +- PINMUX_GPIO(GPIO_PTX5, PTX5_DATA), +- PINMUX_GPIO(GPIO_PTX4, PTX4_DATA), +- PINMUX_GPIO(GPIO_PTX3, PTX3_DATA), +- PINMUX_GPIO(GPIO_PTX2, PTX2_DATA), +- PINMUX_GPIO(GPIO_PTX1, PTX1_DATA), +- PINMUX_GPIO(GPIO_PTX0, PTX0_DATA), ++ PINMUX_GPIO(PTX6), ++ PINMUX_GPIO(PTX5), ++ PINMUX_GPIO(PTX4), ++ PINMUX_GPIO(PTX3), ++ PINMUX_GPIO(PTX2), ++ PINMUX_GPIO(PTX1), ++ PINMUX_GPIO(PTX0), + + /* PTY */ +- PINMUX_GPIO(GPIO_PTY5, PTY5_DATA), +- PINMUX_GPIO(GPIO_PTY4, PTY4_DATA), +- PINMUX_GPIO(GPIO_PTY3, PTY3_DATA), +- PINMUX_GPIO(GPIO_PTY2, PTY2_DATA), +- PINMUX_GPIO(GPIO_PTY1, PTY1_DATA), +- PINMUX_GPIO(GPIO_PTY0, PTY0_DATA), ++ PINMUX_GPIO(PTY5), ++ PINMUX_GPIO(PTY4), ++ PINMUX_GPIO(PTY3), ++ PINMUX_GPIO(PTY2), ++ PINMUX_GPIO(PTY1), ++ PINMUX_GPIO(PTY0), + + /* PTZ */ +- PINMUX_GPIO(GPIO_PTZ5, PTZ5_DATA), +- PINMUX_GPIO(GPIO_PTZ4, PTZ4_DATA), +- PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA), +- PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA), +- PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), ++ PINMUX_GPIO(PTZ5), ++ PINMUX_GPIO(PTZ4), ++ PINMUX_GPIO(PTZ3), ++ PINMUX_GPIO(PTZ2), ++ PINMUX_GPIO(PTZ1), + }; + + #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7723.c b/drivers/pinctrl/sh-pfc/pfc-sh7723.c +index 853093ef..1cecc910 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7723.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7723.c +@@ -919,220 +919,220 @@ static const u16 pinmux_data[] = { + + static struct sh_pfc_pin pinmux_pins[] = { + /* PTA */ +- PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), +- PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), +- PINMUX_GPIO(GPIO_PTA5, PTA5_DATA), +- PINMUX_GPIO(GPIO_PTA4, PTA4_DATA), +- PINMUX_GPIO(GPIO_PTA3, PTA3_DATA), +- PINMUX_GPIO(GPIO_PTA2, PTA2_DATA), +- PINMUX_GPIO(GPIO_PTA1, PTA1_DATA), +- PINMUX_GPIO(GPIO_PTA0, PTA0_DATA), ++ PINMUX_GPIO(PTA7), ++ PINMUX_GPIO(PTA6), ++ PINMUX_GPIO(PTA5), ++ PINMUX_GPIO(PTA4), ++ PINMUX_GPIO(PTA3), ++ PINMUX_GPIO(PTA2), ++ PINMUX_GPIO(PTA1), ++ PINMUX_GPIO(PTA0), + + /* PTB */ +- PINMUX_GPIO(GPIO_PTB7, PTB7_DATA), +- PINMUX_GPIO(GPIO_PTB6, PTB6_DATA), +- PINMUX_GPIO(GPIO_PTB5, PTB5_DATA), +- PINMUX_GPIO(GPIO_PTB4, PTB4_DATA), +- PINMUX_GPIO(GPIO_PTB3, PTB3_DATA), +- PINMUX_GPIO(GPIO_PTB2, PTB2_DATA), +- PINMUX_GPIO(GPIO_PTB1, PTB1_DATA), +- PINMUX_GPIO(GPIO_PTB0, PTB0_DATA), ++ PINMUX_GPIO(PTB7), ++ PINMUX_GPIO(PTB6), ++ PINMUX_GPIO(PTB5), ++ PINMUX_GPIO(PTB4), ++ PINMUX_GPIO(PTB3), ++ PINMUX_GPIO(PTB2), ++ PINMUX_GPIO(PTB1), ++ PINMUX_GPIO(PTB0), + + /* PTC */ +- PINMUX_GPIO(GPIO_PTC7, PTC7_DATA), +- PINMUX_GPIO(GPIO_PTC6, PTC6_DATA), +- PINMUX_GPIO(GPIO_PTC5, PTC5_DATA), +- PINMUX_GPIO(GPIO_PTC4, PTC4_DATA), +- PINMUX_GPIO(GPIO_PTC3, PTC3_DATA), +- PINMUX_GPIO(GPIO_PTC2, PTC2_DATA), +- PINMUX_GPIO(GPIO_PTC1, PTC1_DATA), +- PINMUX_GPIO(GPIO_PTC0, PTC0_DATA), ++ PINMUX_GPIO(PTC7), ++ PINMUX_GPIO(PTC6), ++ PINMUX_GPIO(PTC5), ++ PINMUX_GPIO(PTC4), ++ PINMUX_GPIO(PTC3), ++ PINMUX_GPIO(PTC2), ++ PINMUX_GPIO(PTC1), ++ PINMUX_GPIO(PTC0), + + /* PTD */ +- PINMUX_GPIO(GPIO_PTD7, PTD7_DATA), +- PINMUX_GPIO(GPIO_PTD6, PTD6_DATA), +- PINMUX_GPIO(GPIO_PTD5, PTD5_DATA), +- PINMUX_GPIO(GPIO_PTD4, PTD4_DATA), +- PINMUX_GPIO(GPIO_PTD3, PTD3_DATA), +- PINMUX_GPIO(GPIO_PTD2, PTD2_DATA), +- PINMUX_GPIO(GPIO_PTD1, PTD1_DATA), +- PINMUX_GPIO(GPIO_PTD0, PTD0_DATA), ++ PINMUX_GPIO(PTD7), ++ PINMUX_GPIO(PTD6), ++ PINMUX_GPIO(PTD5), ++ PINMUX_GPIO(PTD4), ++ PINMUX_GPIO(PTD3), ++ PINMUX_GPIO(PTD2), ++ PINMUX_GPIO(PTD1), ++ PINMUX_GPIO(PTD0), + + /* PTE */ +- PINMUX_GPIO(GPIO_PTE5, PTE5_DATA), +- PINMUX_GPIO(GPIO_PTE4, PTE4_DATA), +- PINMUX_GPIO(GPIO_PTE3, PTE3_DATA), +- PINMUX_GPIO(GPIO_PTE2, PTE2_DATA), +- PINMUX_GPIO(GPIO_PTE1, PTE1_DATA), +- PINMUX_GPIO(GPIO_PTE0, PTE0_DATA), ++ PINMUX_GPIO(PTE5), ++ PINMUX_GPIO(PTE4), ++ PINMUX_GPIO(PTE3), ++ PINMUX_GPIO(PTE2), ++ PINMUX_GPIO(PTE1), ++ PINMUX_GPIO(PTE0), + + /* PTF */ +- PINMUX_GPIO(GPIO_PTF7, PTF7_DATA), +- PINMUX_GPIO(GPIO_PTF6, PTF6_DATA), +- PINMUX_GPIO(GPIO_PTF5, PTF5_DATA), +- PINMUX_GPIO(GPIO_PTF4, PTF4_DATA), +- PINMUX_GPIO(GPIO_PTF3, PTF3_DATA), +- PINMUX_GPIO(GPIO_PTF2, PTF2_DATA), +- PINMUX_GPIO(GPIO_PTF1, PTF1_DATA), +- PINMUX_GPIO(GPIO_PTF0, PTF0_DATA), ++ PINMUX_GPIO(PTF7), ++ PINMUX_GPIO(PTF6), ++ PINMUX_GPIO(PTF5), ++ PINMUX_GPIO(PTF4), ++ PINMUX_GPIO(PTF3), ++ PINMUX_GPIO(PTF2), ++ PINMUX_GPIO(PTF1), ++ PINMUX_GPIO(PTF0), + + /* PTG */ +- PINMUX_GPIO(GPIO_PTG5, PTG5_DATA), +- PINMUX_GPIO(GPIO_PTG4, PTG4_DATA), +- PINMUX_GPIO(GPIO_PTG3, PTG3_DATA), +- PINMUX_GPIO(GPIO_PTG2, PTG2_DATA), +- PINMUX_GPIO(GPIO_PTG1, PTG1_DATA), +- PINMUX_GPIO(GPIO_PTG0, PTG0_DATA), ++ PINMUX_GPIO(PTG5), ++ PINMUX_GPIO(PTG4), ++ PINMUX_GPIO(PTG3), ++ PINMUX_GPIO(PTG2), ++ PINMUX_GPIO(PTG1), ++ PINMUX_GPIO(PTG0), + + /* PTH */ +- PINMUX_GPIO(GPIO_PTH7, PTH7_DATA), +- PINMUX_GPIO(GPIO_PTH6, PTH6_DATA), +- PINMUX_GPIO(GPIO_PTH5, PTH5_DATA), +- PINMUX_GPIO(GPIO_PTH4, PTH4_DATA), +- PINMUX_GPIO(GPIO_PTH3, PTH3_DATA), +- PINMUX_GPIO(GPIO_PTH2, PTH2_DATA), +- PINMUX_GPIO(GPIO_PTH1, PTH1_DATA), +- PINMUX_GPIO(GPIO_PTH0, PTH0_DATA), ++ PINMUX_GPIO(PTH7), ++ PINMUX_GPIO(PTH6), ++ PINMUX_GPIO(PTH5), ++ PINMUX_GPIO(PTH4), ++ PINMUX_GPIO(PTH3), ++ PINMUX_GPIO(PTH2), ++ PINMUX_GPIO(PTH1), ++ PINMUX_GPIO(PTH0), + + /* PTJ */ +- PINMUX_GPIO(GPIO_PTJ7, PTJ7_DATA), +- PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA), +- PINMUX_GPIO(GPIO_PTJ3, PTJ3_DATA), +- PINMUX_GPIO(GPIO_PTJ2, PTJ2_DATA), +- PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA), +- PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA), ++ PINMUX_GPIO(PTJ7), ++ PINMUX_GPIO(PTJ5), ++ PINMUX_GPIO(PTJ3), ++ PINMUX_GPIO(PTJ2), ++ PINMUX_GPIO(PTJ1), ++ PINMUX_GPIO(PTJ0), + + /* PTK */ +- PINMUX_GPIO(GPIO_PTK7, PTK7_DATA), +- PINMUX_GPIO(GPIO_PTK6, PTK6_DATA), +- PINMUX_GPIO(GPIO_PTK5, PTK5_DATA), +- PINMUX_GPIO(GPIO_PTK4, PTK4_DATA), +- PINMUX_GPIO(GPIO_PTK3, PTK3_DATA), +- PINMUX_GPIO(GPIO_PTK2, PTK2_DATA), +- PINMUX_GPIO(GPIO_PTK1, PTK1_DATA), +- PINMUX_GPIO(GPIO_PTK0, PTK0_DATA), ++ PINMUX_GPIO(PTK7), ++ PINMUX_GPIO(PTK6), ++ PINMUX_GPIO(PTK5), ++ PINMUX_GPIO(PTK4), ++ PINMUX_GPIO(PTK3), ++ PINMUX_GPIO(PTK2), ++ PINMUX_GPIO(PTK1), ++ PINMUX_GPIO(PTK0), + + /* PTL */ +- PINMUX_GPIO(GPIO_PTL7, PTL7_DATA), +- PINMUX_GPIO(GPIO_PTL6, PTL6_DATA), +- PINMUX_GPIO(GPIO_PTL5, PTL5_DATA), +- PINMUX_GPIO(GPIO_PTL4, PTL4_DATA), +- PINMUX_GPIO(GPIO_PTL3, PTL3_DATA), +- PINMUX_GPIO(GPIO_PTL2, PTL2_DATA), +- PINMUX_GPIO(GPIO_PTL1, PTL1_DATA), +- PINMUX_GPIO(GPIO_PTL0, PTL0_DATA), ++ PINMUX_GPIO(PTL7), ++ PINMUX_GPIO(PTL6), ++ PINMUX_GPIO(PTL5), ++ PINMUX_GPIO(PTL4), ++ PINMUX_GPIO(PTL3), ++ PINMUX_GPIO(PTL2), ++ PINMUX_GPIO(PTL1), ++ PINMUX_GPIO(PTL0), + + /* PTM */ +- PINMUX_GPIO(GPIO_PTM7, PTM7_DATA), +- PINMUX_GPIO(GPIO_PTM6, PTM6_DATA), +- PINMUX_GPIO(GPIO_PTM5, PTM5_DATA), +- PINMUX_GPIO(GPIO_PTM4, PTM4_DATA), +- PINMUX_GPIO(GPIO_PTM3, PTM3_DATA), +- PINMUX_GPIO(GPIO_PTM2, PTM2_DATA), +- PINMUX_GPIO(GPIO_PTM1, PTM1_DATA), +- PINMUX_GPIO(GPIO_PTM0, PTM0_DATA), ++ PINMUX_GPIO(PTM7), ++ PINMUX_GPIO(PTM6), ++ PINMUX_GPIO(PTM5), ++ PINMUX_GPIO(PTM4), ++ PINMUX_GPIO(PTM3), ++ PINMUX_GPIO(PTM2), ++ PINMUX_GPIO(PTM1), ++ PINMUX_GPIO(PTM0), + + /* PTN */ +- PINMUX_GPIO(GPIO_PTN7, PTN7_DATA), +- PINMUX_GPIO(GPIO_PTN6, PTN6_DATA), +- PINMUX_GPIO(GPIO_PTN5, PTN5_DATA), +- PINMUX_GPIO(GPIO_PTN4, PTN4_DATA), +- PINMUX_GPIO(GPIO_PTN3, PTN3_DATA), +- PINMUX_GPIO(GPIO_PTN2, PTN2_DATA), +- PINMUX_GPIO(GPIO_PTN1, PTN1_DATA), +- PINMUX_GPIO(GPIO_PTN0, PTN0_DATA), ++ PINMUX_GPIO(PTN7), ++ PINMUX_GPIO(PTN6), ++ PINMUX_GPIO(PTN5), ++ PINMUX_GPIO(PTN4), ++ PINMUX_GPIO(PTN3), ++ PINMUX_GPIO(PTN2), ++ PINMUX_GPIO(PTN1), ++ PINMUX_GPIO(PTN0), + + /* PTQ */ +- PINMUX_GPIO(GPIO_PTQ3, PTQ3_DATA), +- PINMUX_GPIO(GPIO_PTQ2, PTQ2_DATA), +- PINMUX_GPIO(GPIO_PTQ1, PTQ1_DATA), +- PINMUX_GPIO(GPIO_PTQ0, PTQ0_DATA), ++ PINMUX_GPIO(PTQ3), ++ PINMUX_GPIO(PTQ2), ++ PINMUX_GPIO(PTQ1), ++ PINMUX_GPIO(PTQ0), + + /* PTR */ +- PINMUX_GPIO(GPIO_PTR7, PTR7_DATA), +- PINMUX_GPIO(GPIO_PTR6, PTR6_DATA), +- PINMUX_GPIO(GPIO_PTR5, PTR5_DATA), +- PINMUX_GPIO(GPIO_PTR4, PTR4_DATA), +- PINMUX_GPIO(GPIO_PTR3, PTR3_DATA), +- PINMUX_GPIO(GPIO_PTR2, PTR2_DATA), +- PINMUX_GPIO(GPIO_PTR1, PTR1_DATA), +- PINMUX_GPIO(GPIO_PTR0, PTR0_DATA), ++ PINMUX_GPIO(PTR7), ++ PINMUX_GPIO(PTR6), ++ PINMUX_GPIO(PTR5), ++ PINMUX_GPIO(PTR4), ++ PINMUX_GPIO(PTR3), ++ PINMUX_GPIO(PTR2), ++ PINMUX_GPIO(PTR1), ++ PINMUX_GPIO(PTR0), + + /* PTS */ +- PINMUX_GPIO(GPIO_PTS7, PTS7_DATA), +- PINMUX_GPIO(GPIO_PTS6, PTS6_DATA), +- PINMUX_GPIO(GPIO_PTS5, PTS5_DATA), +- PINMUX_GPIO(GPIO_PTS4, PTS4_DATA), +- PINMUX_GPIO(GPIO_PTS3, PTS3_DATA), +- PINMUX_GPIO(GPIO_PTS2, PTS2_DATA), +- PINMUX_GPIO(GPIO_PTS1, PTS1_DATA), +- PINMUX_GPIO(GPIO_PTS0, PTS0_DATA), ++ PINMUX_GPIO(PTS7), ++ PINMUX_GPIO(PTS6), ++ PINMUX_GPIO(PTS5), ++ PINMUX_GPIO(PTS4), ++ PINMUX_GPIO(PTS3), ++ PINMUX_GPIO(PTS2), ++ PINMUX_GPIO(PTS1), ++ PINMUX_GPIO(PTS0), + + /* PTT */ +- PINMUX_GPIO(GPIO_PTT5, PTT5_DATA), +- PINMUX_GPIO(GPIO_PTT4, PTT4_DATA), +- PINMUX_GPIO(GPIO_PTT3, PTT3_DATA), +- PINMUX_GPIO(GPIO_PTT2, PTT2_DATA), +- PINMUX_GPIO(GPIO_PTT1, PTT1_DATA), +- PINMUX_GPIO(GPIO_PTT0, PTT0_DATA), ++ PINMUX_GPIO(PTT5), ++ PINMUX_GPIO(PTT4), ++ PINMUX_GPIO(PTT3), ++ PINMUX_GPIO(PTT2), ++ PINMUX_GPIO(PTT1), ++ PINMUX_GPIO(PTT0), + + /* PTU */ +- PINMUX_GPIO(GPIO_PTU5, PTU5_DATA), +- PINMUX_GPIO(GPIO_PTU4, PTU4_DATA), +- PINMUX_GPIO(GPIO_PTU3, PTU3_DATA), +- PINMUX_GPIO(GPIO_PTU2, PTU2_DATA), +- PINMUX_GPIO(GPIO_PTU1, PTU1_DATA), +- PINMUX_GPIO(GPIO_PTU0, PTU0_DATA), ++ PINMUX_GPIO(PTU5), ++ PINMUX_GPIO(PTU4), ++ PINMUX_GPIO(PTU3), ++ PINMUX_GPIO(PTU2), ++ PINMUX_GPIO(PTU1), ++ PINMUX_GPIO(PTU0), + + /* PTV */ +- PINMUX_GPIO(GPIO_PTV7, PTV7_DATA), +- PINMUX_GPIO(GPIO_PTV6, PTV6_DATA), +- PINMUX_GPIO(GPIO_PTV5, PTV5_DATA), +- PINMUX_GPIO(GPIO_PTV4, PTV4_DATA), +- PINMUX_GPIO(GPIO_PTV3, PTV3_DATA), +- PINMUX_GPIO(GPIO_PTV2, PTV2_DATA), +- PINMUX_GPIO(GPIO_PTV1, PTV1_DATA), +- PINMUX_GPIO(GPIO_PTV0, PTV0_DATA), ++ PINMUX_GPIO(PTV7), ++ PINMUX_GPIO(PTV6), ++ PINMUX_GPIO(PTV5), ++ PINMUX_GPIO(PTV4), ++ PINMUX_GPIO(PTV3), ++ PINMUX_GPIO(PTV2), ++ PINMUX_GPIO(PTV1), ++ PINMUX_GPIO(PTV0), + + /* PTW */ +- PINMUX_GPIO(GPIO_PTW7, PTW7_DATA), +- PINMUX_GPIO(GPIO_PTW6, PTW6_DATA), +- PINMUX_GPIO(GPIO_PTW5, PTW5_DATA), +- PINMUX_GPIO(GPIO_PTW4, PTW4_DATA), +- PINMUX_GPIO(GPIO_PTW3, PTW3_DATA), +- PINMUX_GPIO(GPIO_PTW2, PTW2_DATA), +- PINMUX_GPIO(GPIO_PTW1, PTW1_DATA), +- PINMUX_GPIO(GPIO_PTW0, PTW0_DATA), ++ PINMUX_GPIO(PTW7), ++ PINMUX_GPIO(PTW6), ++ PINMUX_GPIO(PTW5), ++ PINMUX_GPIO(PTW4), ++ PINMUX_GPIO(PTW3), ++ PINMUX_GPIO(PTW2), ++ PINMUX_GPIO(PTW1), ++ PINMUX_GPIO(PTW0), + + /* PTX */ +- PINMUX_GPIO(GPIO_PTX7, PTX7_DATA), +- PINMUX_GPIO(GPIO_PTX6, PTX6_DATA), +- PINMUX_GPIO(GPIO_PTX5, PTX5_DATA), +- PINMUX_GPIO(GPIO_PTX4, PTX4_DATA), +- PINMUX_GPIO(GPIO_PTX3, PTX3_DATA), +- PINMUX_GPIO(GPIO_PTX2, PTX2_DATA), +- PINMUX_GPIO(GPIO_PTX1, PTX1_DATA), +- PINMUX_GPIO(GPIO_PTX0, PTX0_DATA), ++ PINMUX_GPIO(PTX7), ++ PINMUX_GPIO(PTX6), ++ PINMUX_GPIO(PTX5), ++ PINMUX_GPIO(PTX4), ++ PINMUX_GPIO(PTX3), ++ PINMUX_GPIO(PTX2), ++ PINMUX_GPIO(PTX1), ++ PINMUX_GPIO(PTX0), + + /* PTY */ +- PINMUX_GPIO(GPIO_PTY7, PTY7_DATA), +- PINMUX_GPIO(GPIO_PTY6, PTY6_DATA), +- PINMUX_GPIO(GPIO_PTY5, PTY5_DATA), +- PINMUX_GPIO(GPIO_PTY4, PTY4_DATA), +- PINMUX_GPIO(GPIO_PTY3, PTY3_DATA), +- PINMUX_GPIO(GPIO_PTY2, PTY2_DATA), +- PINMUX_GPIO(GPIO_PTY1, PTY1_DATA), +- PINMUX_GPIO(GPIO_PTY0, PTY0_DATA), ++ PINMUX_GPIO(PTY7), ++ PINMUX_GPIO(PTY6), ++ PINMUX_GPIO(PTY5), ++ PINMUX_GPIO(PTY4), ++ PINMUX_GPIO(PTY3), ++ PINMUX_GPIO(PTY2), ++ PINMUX_GPIO(PTY1), ++ PINMUX_GPIO(PTY0), + + /* PTZ */ +- PINMUX_GPIO(GPIO_PTZ7, PTZ7_DATA), +- PINMUX_GPIO(GPIO_PTZ6, PTZ6_DATA), +- PINMUX_GPIO(GPIO_PTZ5, PTZ5_DATA), +- PINMUX_GPIO(GPIO_PTZ4, PTZ4_DATA), +- PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA), +- PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA), +- PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), +- PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA), ++ PINMUX_GPIO(PTZ7), ++ PINMUX_GPIO(PTZ6), ++ PINMUX_GPIO(PTZ5), ++ PINMUX_GPIO(PTZ4), ++ PINMUX_GPIO(PTZ3), ++ PINMUX_GPIO(PTZ2), ++ PINMUX_GPIO(PTZ1), ++ PINMUX_GPIO(PTZ0), + }; + + #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7724.c b/drivers/pinctrl/sh-pfc/pfc-sh7724.c +index fe2693f6..1085ab55 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7724.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7724.c +@@ -1148,230 +1148,230 @@ static const u16 pinmux_data[] = { + + static struct sh_pfc_pin pinmux_pins[] = { + /* PTA */ +- PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), +- PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), +- PINMUX_GPIO(GPIO_PTA5, PTA5_DATA), +- PINMUX_GPIO(GPIO_PTA4, PTA4_DATA), +- PINMUX_GPIO(GPIO_PTA3, PTA3_DATA), +- PINMUX_GPIO(GPIO_PTA2, PTA2_DATA), +- PINMUX_GPIO(GPIO_PTA1, PTA1_DATA), +- PINMUX_GPIO(GPIO_PTA0, PTA0_DATA), ++ PINMUX_GPIO(PTA7), ++ PINMUX_GPIO(PTA6), ++ PINMUX_GPIO(PTA5), ++ PINMUX_GPIO(PTA4), ++ PINMUX_GPIO(PTA3), ++ PINMUX_GPIO(PTA2), ++ PINMUX_GPIO(PTA1), ++ PINMUX_GPIO(PTA0), + + /* PTB */ +- PINMUX_GPIO(GPIO_PTB7, PTB7_DATA), +- PINMUX_GPIO(GPIO_PTB6, PTB6_DATA), +- PINMUX_GPIO(GPIO_PTB5, PTB5_DATA), +- PINMUX_GPIO(GPIO_PTB4, PTB4_DATA), +- PINMUX_GPIO(GPIO_PTB3, PTB3_DATA), +- PINMUX_GPIO(GPIO_PTB2, PTB2_DATA), +- PINMUX_GPIO(GPIO_PTB1, PTB1_DATA), +- PINMUX_GPIO(GPIO_PTB0, PTB0_DATA), ++ PINMUX_GPIO(PTB7), ++ PINMUX_GPIO(PTB6), ++ PINMUX_GPIO(PTB5), ++ PINMUX_GPIO(PTB4), ++ PINMUX_GPIO(PTB3), ++ PINMUX_GPIO(PTB2), ++ PINMUX_GPIO(PTB1), ++ PINMUX_GPIO(PTB0), + + /* PTC */ +- PINMUX_GPIO(GPIO_PTC7, PTC7_DATA), +- PINMUX_GPIO(GPIO_PTC6, PTC6_DATA), +- PINMUX_GPIO(GPIO_PTC5, PTC5_DATA), +- PINMUX_GPIO(GPIO_PTC4, PTC4_DATA), +- PINMUX_GPIO(GPIO_PTC3, PTC3_DATA), +- PINMUX_GPIO(GPIO_PTC2, PTC2_DATA), +- PINMUX_GPIO(GPIO_PTC1, PTC1_DATA), +- PINMUX_GPIO(GPIO_PTC0, PTC0_DATA), ++ PINMUX_GPIO(PTC7), ++ PINMUX_GPIO(PTC6), ++ PINMUX_GPIO(PTC5), ++ PINMUX_GPIO(PTC4), ++ PINMUX_GPIO(PTC3), ++ PINMUX_GPIO(PTC2), ++ PINMUX_GPIO(PTC1), ++ PINMUX_GPIO(PTC0), + + /* PTD */ +- PINMUX_GPIO(GPIO_PTD7, PTD7_DATA), +- PINMUX_GPIO(GPIO_PTD6, PTD6_DATA), +- PINMUX_GPIO(GPIO_PTD5, PTD5_DATA), +- PINMUX_GPIO(GPIO_PTD4, PTD4_DATA), +- PINMUX_GPIO(GPIO_PTD3, PTD3_DATA), +- PINMUX_GPIO(GPIO_PTD2, PTD2_DATA), +- PINMUX_GPIO(GPIO_PTD1, PTD1_DATA), +- PINMUX_GPIO(GPIO_PTD0, PTD0_DATA), ++ PINMUX_GPIO(PTD7), ++ PINMUX_GPIO(PTD6), ++ PINMUX_GPIO(PTD5), ++ PINMUX_GPIO(PTD4), ++ PINMUX_GPIO(PTD3), ++ PINMUX_GPIO(PTD2), ++ PINMUX_GPIO(PTD1), ++ PINMUX_GPIO(PTD0), + + /* PTE */ +- PINMUX_GPIO(GPIO_PTE7, PTE7_DATA), +- PINMUX_GPIO(GPIO_PTE6, PTE6_DATA), +- PINMUX_GPIO(GPIO_PTE5, PTE5_DATA), +- PINMUX_GPIO(GPIO_PTE4, PTE4_DATA), +- PINMUX_GPIO(GPIO_PTE3, PTE3_DATA), +- PINMUX_GPIO(GPIO_PTE2, PTE2_DATA), +- PINMUX_GPIO(GPIO_PTE1, PTE1_DATA), +- PINMUX_GPIO(GPIO_PTE0, PTE0_DATA), ++ PINMUX_GPIO(PTE7), ++ PINMUX_GPIO(PTE6), ++ PINMUX_GPIO(PTE5), ++ PINMUX_GPIO(PTE4), ++ PINMUX_GPIO(PTE3), ++ PINMUX_GPIO(PTE2), ++ PINMUX_GPIO(PTE1), ++ PINMUX_GPIO(PTE0), + + /* PTF */ +- PINMUX_GPIO(GPIO_PTF7, PTF7_DATA), +- PINMUX_GPIO(GPIO_PTF6, PTF6_DATA), +- PINMUX_GPIO(GPIO_PTF5, PTF5_DATA), +- PINMUX_GPIO(GPIO_PTF4, PTF4_DATA), +- PINMUX_GPIO(GPIO_PTF3, PTF3_DATA), +- PINMUX_GPIO(GPIO_PTF2, PTF2_DATA), +- PINMUX_GPIO(GPIO_PTF1, PTF1_DATA), +- PINMUX_GPIO(GPIO_PTF0, PTF0_DATA), ++ PINMUX_GPIO(PTF7), ++ PINMUX_GPIO(PTF6), ++ PINMUX_GPIO(PTF5), ++ PINMUX_GPIO(PTF4), ++ PINMUX_GPIO(PTF3), ++ PINMUX_GPIO(PTF2), ++ PINMUX_GPIO(PTF1), ++ PINMUX_GPIO(PTF0), + + /* PTG */ +- PINMUX_GPIO(GPIO_PTG5, PTG5_DATA), +- PINMUX_GPIO(GPIO_PTG4, PTG4_DATA), +- PINMUX_GPIO(GPIO_PTG3, PTG3_DATA), +- PINMUX_GPIO(GPIO_PTG2, PTG2_DATA), +- PINMUX_GPIO(GPIO_PTG1, PTG1_DATA), +- PINMUX_GPIO(GPIO_PTG0, PTG0_DATA), ++ PINMUX_GPIO(PTG5), ++ PINMUX_GPIO(PTG4), ++ PINMUX_GPIO(PTG3), ++ PINMUX_GPIO(PTG2), ++ PINMUX_GPIO(PTG1), ++ PINMUX_GPIO(PTG0), + + /* PTH */ +- PINMUX_GPIO(GPIO_PTH7, PTH7_DATA), +- PINMUX_GPIO(GPIO_PTH6, PTH6_DATA), +- PINMUX_GPIO(GPIO_PTH5, PTH5_DATA), +- PINMUX_GPIO(GPIO_PTH4, PTH4_DATA), +- PINMUX_GPIO(GPIO_PTH3, PTH3_DATA), +- PINMUX_GPIO(GPIO_PTH2, PTH2_DATA), +- PINMUX_GPIO(GPIO_PTH1, PTH1_DATA), +- PINMUX_GPIO(GPIO_PTH0, PTH0_DATA), ++ PINMUX_GPIO(PTH7), ++ PINMUX_GPIO(PTH6), ++ PINMUX_GPIO(PTH5), ++ PINMUX_GPIO(PTH4), ++ PINMUX_GPIO(PTH3), ++ PINMUX_GPIO(PTH2), ++ PINMUX_GPIO(PTH1), ++ PINMUX_GPIO(PTH0), + + /* PTJ */ +- PINMUX_GPIO(GPIO_PTJ7, PTJ7_DATA), +- PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA), +- PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA), +- PINMUX_GPIO(GPIO_PTJ3, PTJ3_DATA), +- PINMUX_GPIO(GPIO_PTJ2, PTJ2_DATA), +- PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA), +- PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA), ++ PINMUX_GPIO(PTJ7), ++ PINMUX_GPIO(PTJ6), ++ PINMUX_GPIO(PTJ5), ++ PINMUX_GPIO(PTJ3), ++ PINMUX_GPIO(PTJ2), ++ PINMUX_GPIO(PTJ1), ++ PINMUX_GPIO(PTJ0), + + /* PTK */ +- PINMUX_GPIO(GPIO_PTK7, PTK7_DATA), +- PINMUX_GPIO(GPIO_PTK6, PTK6_DATA), +- PINMUX_GPIO(GPIO_PTK5, PTK5_DATA), +- PINMUX_GPIO(GPIO_PTK4, PTK4_DATA), +- PINMUX_GPIO(GPIO_PTK3, PTK3_DATA), +- PINMUX_GPIO(GPIO_PTK2, PTK2_DATA), +- PINMUX_GPIO(GPIO_PTK1, PTK1_DATA), +- PINMUX_GPIO(GPIO_PTK0, PTK0_DATA), ++ PINMUX_GPIO(PTK7), ++ PINMUX_GPIO(PTK6), ++ PINMUX_GPIO(PTK5), ++ PINMUX_GPIO(PTK4), ++ PINMUX_GPIO(PTK3), ++ PINMUX_GPIO(PTK2), ++ PINMUX_GPIO(PTK1), ++ PINMUX_GPIO(PTK0), + + /* PTL */ +- PINMUX_GPIO(GPIO_PTL7, PTL7_DATA), +- PINMUX_GPIO(GPIO_PTL6, PTL6_DATA), +- PINMUX_GPIO(GPIO_PTL5, PTL5_DATA), +- PINMUX_GPIO(GPIO_PTL4, PTL4_DATA), +- PINMUX_GPIO(GPIO_PTL3, PTL3_DATA), +- PINMUX_GPIO(GPIO_PTL2, PTL2_DATA), +- PINMUX_GPIO(GPIO_PTL1, PTL1_DATA), +- PINMUX_GPIO(GPIO_PTL0, PTL0_DATA), ++ PINMUX_GPIO(PTL7), ++ PINMUX_GPIO(PTL6), ++ PINMUX_GPIO(PTL5), ++ PINMUX_GPIO(PTL4), ++ PINMUX_GPIO(PTL3), ++ PINMUX_GPIO(PTL2), ++ PINMUX_GPIO(PTL1), ++ PINMUX_GPIO(PTL0), + + /* PTM */ +- PINMUX_GPIO(GPIO_PTM7, PTM7_DATA), +- PINMUX_GPIO(GPIO_PTM6, PTM6_DATA), +- PINMUX_GPIO(GPIO_PTM5, PTM5_DATA), +- PINMUX_GPIO(GPIO_PTM4, PTM4_DATA), +- PINMUX_GPIO(GPIO_PTM3, PTM3_DATA), +- PINMUX_GPIO(GPIO_PTM2, PTM2_DATA), +- PINMUX_GPIO(GPIO_PTM1, PTM1_DATA), +- PINMUX_GPIO(GPIO_PTM0, PTM0_DATA), ++ PINMUX_GPIO(PTM7), ++ PINMUX_GPIO(PTM6), ++ PINMUX_GPIO(PTM5), ++ PINMUX_GPIO(PTM4), ++ PINMUX_GPIO(PTM3), ++ PINMUX_GPIO(PTM2), ++ PINMUX_GPIO(PTM1), ++ PINMUX_GPIO(PTM0), + + /* PTN */ +- PINMUX_GPIO(GPIO_PTN7, PTN7_DATA), +- PINMUX_GPIO(GPIO_PTN6, PTN6_DATA), +- PINMUX_GPIO(GPIO_PTN5, PTN5_DATA), +- PINMUX_GPIO(GPIO_PTN4, PTN4_DATA), +- PINMUX_GPIO(GPIO_PTN3, PTN3_DATA), +- PINMUX_GPIO(GPIO_PTN2, PTN2_DATA), +- PINMUX_GPIO(GPIO_PTN1, PTN1_DATA), +- PINMUX_GPIO(GPIO_PTN0, PTN0_DATA), ++ PINMUX_GPIO(PTN7), ++ PINMUX_GPIO(PTN6), ++ PINMUX_GPIO(PTN5), ++ PINMUX_GPIO(PTN4), ++ PINMUX_GPIO(PTN3), ++ PINMUX_GPIO(PTN2), ++ PINMUX_GPIO(PTN1), ++ PINMUX_GPIO(PTN0), + + /* PTQ */ +- PINMUX_GPIO(GPIO_PTQ7, PTQ7_DATA), +- PINMUX_GPIO(GPIO_PTQ6, PTQ6_DATA), +- PINMUX_GPIO(GPIO_PTQ5, PTQ5_DATA), +- PINMUX_GPIO(GPIO_PTQ4, PTQ4_DATA), +- PINMUX_GPIO(GPIO_PTQ3, PTQ3_DATA), +- PINMUX_GPIO(GPIO_PTQ2, PTQ2_DATA), +- PINMUX_GPIO(GPIO_PTQ1, PTQ1_DATA), +- PINMUX_GPIO(GPIO_PTQ0, PTQ0_DATA), ++ PINMUX_GPIO(PTQ7), ++ PINMUX_GPIO(PTQ6), ++ PINMUX_GPIO(PTQ5), ++ PINMUX_GPIO(PTQ4), ++ PINMUX_GPIO(PTQ3), ++ PINMUX_GPIO(PTQ2), ++ PINMUX_GPIO(PTQ1), ++ PINMUX_GPIO(PTQ0), + + /* PTR */ +- PINMUX_GPIO(GPIO_PTR7, PTR7_DATA), +- PINMUX_GPIO(GPIO_PTR6, PTR6_DATA), +- PINMUX_GPIO(GPIO_PTR5, PTR5_DATA), +- PINMUX_GPIO(GPIO_PTR4, PTR4_DATA), +- PINMUX_GPIO(GPIO_PTR3, PTR3_DATA), +- PINMUX_GPIO(GPIO_PTR2, PTR2_DATA), +- PINMUX_GPIO(GPIO_PTR1, PTR1_DATA), +- PINMUX_GPIO(GPIO_PTR0, PTR0_DATA), ++ PINMUX_GPIO(PTR7), ++ PINMUX_GPIO(PTR6), ++ PINMUX_GPIO(PTR5), ++ PINMUX_GPIO(PTR4), ++ PINMUX_GPIO(PTR3), ++ PINMUX_GPIO(PTR2), ++ PINMUX_GPIO(PTR1), ++ PINMUX_GPIO(PTR0), + + /* PTS */ +- PINMUX_GPIO(GPIO_PTS6, PTS6_DATA), +- PINMUX_GPIO(GPIO_PTS5, PTS5_DATA), +- PINMUX_GPIO(GPIO_PTS4, PTS4_DATA), +- PINMUX_GPIO(GPIO_PTS3, PTS3_DATA), +- PINMUX_GPIO(GPIO_PTS2, PTS2_DATA), +- PINMUX_GPIO(GPIO_PTS1, PTS1_DATA), +- PINMUX_GPIO(GPIO_PTS0, PTS0_DATA), ++ PINMUX_GPIO(PTS6), ++ PINMUX_GPIO(PTS5), ++ PINMUX_GPIO(PTS4), ++ PINMUX_GPIO(PTS3), ++ PINMUX_GPIO(PTS2), ++ PINMUX_GPIO(PTS1), ++ PINMUX_GPIO(PTS0), + + /* PTT */ +- PINMUX_GPIO(GPIO_PTT7, PTT7_DATA), +- PINMUX_GPIO(GPIO_PTT6, PTT6_DATA), +- PINMUX_GPIO(GPIO_PTT5, PTT5_DATA), +- PINMUX_GPIO(GPIO_PTT4, PTT4_DATA), +- PINMUX_GPIO(GPIO_PTT3, PTT3_DATA), +- PINMUX_GPIO(GPIO_PTT2, PTT2_DATA), +- PINMUX_GPIO(GPIO_PTT1, PTT1_DATA), +- PINMUX_GPIO(GPIO_PTT0, PTT0_DATA), ++ PINMUX_GPIO(PTT7), ++ PINMUX_GPIO(PTT6), ++ PINMUX_GPIO(PTT5), ++ PINMUX_GPIO(PTT4), ++ PINMUX_GPIO(PTT3), ++ PINMUX_GPIO(PTT2), ++ PINMUX_GPIO(PTT1), ++ PINMUX_GPIO(PTT0), + + /* PTU */ +- PINMUX_GPIO(GPIO_PTU7, PTU7_DATA), +- PINMUX_GPIO(GPIO_PTU6, PTU6_DATA), +- PINMUX_GPIO(GPIO_PTU5, PTU5_DATA), +- PINMUX_GPIO(GPIO_PTU4, PTU4_DATA), +- PINMUX_GPIO(GPIO_PTU3, PTU3_DATA), +- PINMUX_GPIO(GPIO_PTU2, PTU2_DATA), +- PINMUX_GPIO(GPIO_PTU1, PTU1_DATA), +- PINMUX_GPIO(GPIO_PTU0, PTU0_DATA), ++ PINMUX_GPIO(PTU7), ++ PINMUX_GPIO(PTU6), ++ PINMUX_GPIO(PTU5), ++ PINMUX_GPIO(PTU4), ++ PINMUX_GPIO(PTU3), ++ PINMUX_GPIO(PTU2), ++ PINMUX_GPIO(PTU1), ++ PINMUX_GPIO(PTU0), + + /* PTV */ +- PINMUX_GPIO(GPIO_PTV7, PTV7_DATA), +- PINMUX_GPIO(GPIO_PTV6, PTV6_DATA), +- PINMUX_GPIO(GPIO_PTV5, PTV5_DATA), +- PINMUX_GPIO(GPIO_PTV4, PTV4_DATA), +- PINMUX_GPIO(GPIO_PTV3, PTV3_DATA), +- PINMUX_GPIO(GPIO_PTV2, PTV2_DATA), +- PINMUX_GPIO(GPIO_PTV1, PTV1_DATA), +- PINMUX_GPIO(GPIO_PTV0, PTV0_DATA), ++ PINMUX_GPIO(PTV7), ++ PINMUX_GPIO(PTV6), ++ PINMUX_GPIO(PTV5), ++ PINMUX_GPIO(PTV4), ++ PINMUX_GPIO(PTV3), ++ PINMUX_GPIO(PTV2), ++ PINMUX_GPIO(PTV1), ++ PINMUX_GPIO(PTV0), + + /* PTW */ +- PINMUX_GPIO(GPIO_PTW7, PTW7_DATA), +- PINMUX_GPIO(GPIO_PTW6, PTW6_DATA), +- PINMUX_GPIO(GPIO_PTW5, PTW5_DATA), +- PINMUX_GPIO(GPIO_PTW4, PTW4_DATA), +- PINMUX_GPIO(GPIO_PTW3, PTW3_DATA), +- PINMUX_GPIO(GPIO_PTW2, PTW2_DATA), +- PINMUX_GPIO(GPIO_PTW1, PTW1_DATA), +- PINMUX_GPIO(GPIO_PTW0, PTW0_DATA), ++ PINMUX_GPIO(PTW7), ++ PINMUX_GPIO(PTW6), ++ PINMUX_GPIO(PTW5), ++ PINMUX_GPIO(PTW4), ++ PINMUX_GPIO(PTW3), ++ PINMUX_GPIO(PTW2), ++ PINMUX_GPIO(PTW1), ++ PINMUX_GPIO(PTW0), + + /* PTX */ +- PINMUX_GPIO(GPIO_PTX7, PTX7_DATA), +- PINMUX_GPIO(GPIO_PTX6, PTX6_DATA), +- PINMUX_GPIO(GPIO_PTX5, PTX5_DATA), +- PINMUX_GPIO(GPIO_PTX4, PTX4_DATA), +- PINMUX_GPIO(GPIO_PTX3, PTX3_DATA), +- PINMUX_GPIO(GPIO_PTX2, PTX2_DATA), +- PINMUX_GPIO(GPIO_PTX1, PTX1_DATA), +- PINMUX_GPIO(GPIO_PTX0, PTX0_DATA), ++ PINMUX_GPIO(PTX7), ++ PINMUX_GPIO(PTX6), ++ PINMUX_GPIO(PTX5), ++ PINMUX_GPIO(PTX4), ++ PINMUX_GPIO(PTX3), ++ PINMUX_GPIO(PTX2), ++ PINMUX_GPIO(PTX1), ++ PINMUX_GPIO(PTX0), + + /* PTY */ +- PINMUX_GPIO(GPIO_PTY7, PTY7_DATA), +- PINMUX_GPIO(GPIO_PTY6, PTY6_DATA), +- PINMUX_GPIO(GPIO_PTY5, PTY5_DATA), +- PINMUX_GPIO(GPIO_PTY4, PTY4_DATA), +- PINMUX_GPIO(GPIO_PTY3, PTY3_DATA), +- PINMUX_GPIO(GPIO_PTY2, PTY2_DATA), +- PINMUX_GPIO(GPIO_PTY1, PTY1_DATA), +- PINMUX_GPIO(GPIO_PTY0, PTY0_DATA), ++ PINMUX_GPIO(PTY7), ++ PINMUX_GPIO(PTY6), ++ PINMUX_GPIO(PTY5), ++ PINMUX_GPIO(PTY4), ++ PINMUX_GPIO(PTY3), ++ PINMUX_GPIO(PTY2), ++ PINMUX_GPIO(PTY1), ++ PINMUX_GPIO(PTY0), + + /* PTZ */ +- PINMUX_GPIO(GPIO_PTZ7, PTZ7_DATA), +- PINMUX_GPIO(GPIO_PTZ6, PTZ6_DATA), +- PINMUX_GPIO(GPIO_PTZ5, PTZ5_DATA), +- PINMUX_GPIO(GPIO_PTZ4, PTZ4_DATA), +- PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA), +- PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA), +- PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), +- PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA), ++ PINMUX_GPIO(PTZ7), ++ PINMUX_GPIO(PTZ6), ++ PINMUX_GPIO(PTZ5), ++ PINMUX_GPIO(PTZ4), ++ PINMUX_GPIO(PTZ3), ++ PINMUX_GPIO(PTZ2), ++ PINMUX_GPIO(PTZ1), ++ PINMUX_GPIO(PTZ0), + }; + + #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7757.c b/drivers/pinctrl/sh-pfc/pfc-sh7757.c +index f4271167..33d75e51 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7757.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7757.c +@@ -1076,260 +1076,260 @@ static const u16 pinmux_data[] = { + + static struct sh_pfc_pin pinmux_pins[] = { + /* PTA */ +- PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), +- PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), +- PINMUX_GPIO(GPIO_PTA5, PTA5_DATA), +- PINMUX_GPIO(GPIO_PTA4, PTA4_DATA), +- PINMUX_GPIO(GPIO_PTA3, PTA3_DATA), +- PINMUX_GPIO(GPIO_PTA2, PTA2_DATA), +- PINMUX_GPIO(GPIO_PTA1, PTA1_DATA), +- PINMUX_GPIO(GPIO_PTA0, PTA0_DATA), ++ PINMUX_GPIO(PTA7), ++ PINMUX_GPIO(PTA6), ++ PINMUX_GPIO(PTA5), ++ PINMUX_GPIO(PTA4), ++ PINMUX_GPIO(PTA3), ++ PINMUX_GPIO(PTA2), ++ PINMUX_GPIO(PTA1), ++ PINMUX_GPIO(PTA0), + + /* PTB */ +- PINMUX_GPIO(GPIO_PTB7, PTB7_DATA), +- PINMUX_GPIO(GPIO_PTB6, PTB6_DATA), +- PINMUX_GPIO(GPIO_PTB5, PTB5_DATA), +- PINMUX_GPIO(GPIO_PTB4, PTB4_DATA), +- PINMUX_GPIO(GPIO_PTB3, PTB3_DATA), +- PINMUX_GPIO(GPIO_PTB2, PTB2_DATA), +- PINMUX_GPIO(GPIO_PTB1, PTB1_DATA), +- PINMUX_GPIO(GPIO_PTB0, PTB0_DATA), ++ PINMUX_GPIO(PTB7), ++ PINMUX_GPIO(PTB6), ++ PINMUX_GPIO(PTB5), ++ PINMUX_GPIO(PTB4), ++ PINMUX_GPIO(PTB3), ++ PINMUX_GPIO(PTB2), ++ PINMUX_GPIO(PTB1), ++ PINMUX_GPIO(PTB0), + + /* PTC */ +- PINMUX_GPIO(GPIO_PTC7, PTC7_DATA), +- PINMUX_GPIO(GPIO_PTC6, PTC6_DATA), +- PINMUX_GPIO(GPIO_PTC5, PTC5_DATA), +- PINMUX_GPIO(GPIO_PTC4, PTC4_DATA), +- PINMUX_GPIO(GPIO_PTC3, PTC3_DATA), +- PINMUX_GPIO(GPIO_PTC2, PTC2_DATA), +- PINMUX_GPIO(GPIO_PTC1, PTC1_DATA), +- PINMUX_GPIO(GPIO_PTC0, PTC0_DATA), ++ PINMUX_GPIO(PTC7), ++ PINMUX_GPIO(PTC6), ++ PINMUX_GPIO(PTC5), ++ PINMUX_GPIO(PTC4), ++ PINMUX_GPIO(PTC3), ++ PINMUX_GPIO(PTC2), ++ PINMUX_GPIO(PTC1), ++ PINMUX_GPIO(PTC0), + + /* PTD */ +- PINMUX_GPIO(GPIO_PTD7, PTD7_DATA), +- PINMUX_GPIO(GPIO_PTD6, PTD6_DATA), +- PINMUX_GPIO(GPIO_PTD5, PTD5_DATA), +- PINMUX_GPIO(GPIO_PTD4, PTD4_DATA), +- PINMUX_GPIO(GPIO_PTD3, PTD3_DATA), +- PINMUX_GPIO(GPIO_PTD2, PTD2_DATA), +- PINMUX_GPIO(GPIO_PTD1, PTD1_DATA), +- PINMUX_GPIO(GPIO_PTD0, PTD0_DATA), ++ PINMUX_GPIO(PTD7), ++ PINMUX_GPIO(PTD6), ++ PINMUX_GPIO(PTD5), ++ PINMUX_GPIO(PTD4), ++ PINMUX_GPIO(PTD3), ++ PINMUX_GPIO(PTD2), ++ PINMUX_GPIO(PTD1), ++ PINMUX_GPIO(PTD0), + + /* PTE */ +- PINMUX_GPIO(GPIO_PTE7, PTE7_DATA), +- PINMUX_GPIO(GPIO_PTE6, PTE6_DATA), +- PINMUX_GPIO(GPIO_PTE5, PTE5_DATA), +- PINMUX_GPIO(GPIO_PTE4, PTE4_DATA), +- PINMUX_GPIO(GPIO_PTE3, PTE3_DATA), +- PINMUX_GPIO(GPIO_PTE2, PTE2_DATA), +- PINMUX_GPIO(GPIO_PTE1, PTE1_DATA), +- PINMUX_GPIO(GPIO_PTE0, PTE0_DATA), ++ PINMUX_GPIO(PTE7), ++ PINMUX_GPIO(PTE6), ++ PINMUX_GPIO(PTE5), ++ PINMUX_GPIO(PTE4), ++ PINMUX_GPIO(PTE3), ++ PINMUX_GPIO(PTE2), ++ PINMUX_GPIO(PTE1), ++ PINMUX_GPIO(PTE0), + + /* PTF */ +- PINMUX_GPIO(GPIO_PTF7, PTF7_DATA), +- PINMUX_GPIO(GPIO_PTF6, PTF6_DATA), +- PINMUX_GPIO(GPIO_PTF5, PTF5_DATA), +- PINMUX_GPIO(GPIO_PTF4, PTF4_DATA), +- PINMUX_GPIO(GPIO_PTF3, PTF3_DATA), +- PINMUX_GPIO(GPIO_PTF2, PTF2_DATA), +- PINMUX_GPIO(GPIO_PTF1, PTF1_DATA), +- PINMUX_GPIO(GPIO_PTF0, PTF0_DATA), ++ PINMUX_GPIO(PTF7), ++ PINMUX_GPIO(PTF6), ++ PINMUX_GPIO(PTF5), ++ PINMUX_GPIO(PTF4), ++ PINMUX_GPIO(PTF3), ++ PINMUX_GPIO(PTF2), ++ PINMUX_GPIO(PTF1), ++ PINMUX_GPIO(PTF0), + + /* PTG */ +- PINMUX_GPIO(GPIO_PTG7, PTG7_DATA), +- PINMUX_GPIO(GPIO_PTG6, PTG6_DATA), +- PINMUX_GPIO(GPIO_PTG5, PTG5_DATA), +- PINMUX_GPIO(GPIO_PTG4, PTG4_DATA), +- PINMUX_GPIO(GPIO_PTG3, PTG3_DATA), +- PINMUX_GPIO(GPIO_PTG2, PTG2_DATA), +- PINMUX_GPIO(GPIO_PTG1, PTG1_DATA), +- PINMUX_GPIO(GPIO_PTG0, PTG0_DATA), ++ PINMUX_GPIO(PTG7), ++ PINMUX_GPIO(PTG6), ++ PINMUX_GPIO(PTG5), ++ PINMUX_GPIO(PTG4), ++ PINMUX_GPIO(PTG3), ++ PINMUX_GPIO(PTG2), ++ PINMUX_GPIO(PTG1), ++ PINMUX_GPIO(PTG0), + + /* PTH */ +- PINMUX_GPIO(GPIO_PTH7, PTH7_DATA), +- PINMUX_GPIO(GPIO_PTH6, PTH6_DATA), +- PINMUX_GPIO(GPIO_PTH5, PTH5_DATA), +- PINMUX_GPIO(GPIO_PTH4, PTH4_DATA), +- PINMUX_GPIO(GPIO_PTH3, PTH3_DATA), +- PINMUX_GPIO(GPIO_PTH2, PTH2_DATA), +- PINMUX_GPIO(GPIO_PTH1, PTH1_DATA), +- PINMUX_GPIO(GPIO_PTH0, PTH0_DATA), ++ PINMUX_GPIO(PTH7), ++ PINMUX_GPIO(PTH6), ++ PINMUX_GPIO(PTH5), ++ PINMUX_GPIO(PTH4), ++ PINMUX_GPIO(PTH3), ++ PINMUX_GPIO(PTH2), ++ PINMUX_GPIO(PTH1), ++ PINMUX_GPIO(PTH0), + + /* PTI */ +- PINMUX_GPIO(GPIO_PTI7, PTI7_DATA), +- PINMUX_GPIO(GPIO_PTI6, PTI6_DATA), +- PINMUX_GPIO(GPIO_PTI5, PTI5_DATA), +- PINMUX_GPIO(GPIO_PTI4, PTI4_DATA), +- PINMUX_GPIO(GPIO_PTI3, PTI3_DATA), +- PINMUX_GPIO(GPIO_PTI2, PTI2_DATA), +- PINMUX_GPIO(GPIO_PTI1, PTI1_DATA), +- PINMUX_GPIO(GPIO_PTI0, PTI0_DATA), ++ PINMUX_GPIO(PTI7), ++ PINMUX_GPIO(PTI6), ++ PINMUX_GPIO(PTI5), ++ PINMUX_GPIO(PTI4), ++ PINMUX_GPIO(PTI3), ++ PINMUX_GPIO(PTI2), ++ PINMUX_GPIO(PTI1), ++ PINMUX_GPIO(PTI0), + + /* PTJ */ +- PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA), +- PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA), +- PINMUX_GPIO(GPIO_PTJ4, PTJ4_DATA), +- PINMUX_GPIO(GPIO_PTJ3, PTJ3_DATA), +- PINMUX_GPIO(GPIO_PTJ2, PTJ2_DATA), +- PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA), +- PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA), ++ PINMUX_GPIO(PTJ6), ++ PINMUX_GPIO(PTJ5), ++ PINMUX_GPIO(PTJ4), ++ PINMUX_GPIO(PTJ3), ++ PINMUX_GPIO(PTJ2), ++ PINMUX_GPIO(PTJ1), ++ PINMUX_GPIO(PTJ0), + + /* PTK */ +- PINMUX_GPIO(GPIO_PTK7, PTK7_DATA), +- PINMUX_GPIO(GPIO_PTK6, PTK6_DATA), +- PINMUX_GPIO(GPIO_PTK5, PTK5_DATA), +- PINMUX_GPIO(GPIO_PTK4, PTK4_DATA), +- PINMUX_GPIO(GPIO_PTK3, PTK3_DATA), +- PINMUX_GPIO(GPIO_PTK2, PTK2_DATA), +- PINMUX_GPIO(GPIO_PTK1, PTK1_DATA), +- PINMUX_GPIO(GPIO_PTK0, PTK0_DATA), ++ PINMUX_GPIO(PTK7), ++ PINMUX_GPIO(PTK6), ++ PINMUX_GPIO(PTK5), ++ PINMUX_GPIO(PTK4), ++ PINMUX_GPIO(PTK3), ++ PINMUX_GPIO(PTK2), ++ PINMUX_GPIO(PTK1), ++ PINMUX_GPIO(PTK0), + + /* PTL */ +- PINMUX_GPIO(GPIO_PTL6, PTL6_DATA), +- PINMUX_GPIO(GPIO_PTL5, PTL5_DATA), +- PINMUX_GPIO(GPIO_PTL4, PTL4_DATA), +- PINMUX_GPIO(GPIO_PTL3, PTL3_DATA), +- PINMUX_GPIO(GPIO_PTL2, PTL2_DATA), +- PINMUX_GPIO(GPIO_PTL1, PTL1_DATA), +- PINMUX_GPIO(GPIO_PTL0, PTL0_DATA), ++ PINMUX_GPIO(PTL6), ++ PINMUX_GPIO(PTL5), ++ PINMUX_GPIO(PTL4), ++ PINMUX_GPIO(PTL3), ++ PINMUX_GPIO(PTL2), ++ PINMUX_GPIO(PTL1), ++ PINMUX_GPIO(PTL0), + + /* PTM */ +- PINMUX_GPIO(GPIO_PTM7, PTM7_DATA), +- PINMUX_GPIO(GPIO_PTM6, PTM6_DATA), +- PINMUX_GPIO(GPIO_PTM5, PTM5_DATA), +- PINMUX_GPIO(GPIO_PTM4, PTM4_DATA), +- PINMUX_GPIO(GPIO_PTM3, PTM3_DATA), +- PINMUX_GPIO(GPIO_PTM2, PTM2_DATA), +- PINMUX_GPIO(GPIO_PTM1, PTM1_DATA), +- PINMUX_GPIO(GPIO_PTM0, PTM0_DATA), ++ PINMUX_GPIO(PTM7), ++ PINMUX_GPIO(PTM6), ++ PINMUX_GPIO(PTM5), ++ PINMUX_GPIO(PTM4), ++ PINMUX_GPIO(PTM3), ++ PINMUX_GPIO(PTM2), ++ PINMUX_GPIO(PTM1), ++ PINMUX_GPIO(PTM0), + + /* PTN */ +- PINMUX_GPIO(GPIO_PTN6, PTN6_DATA), +- PINMUX_GPIO(GPIO_PTN5, PTN5_DATA), +- PINMUX_GPIO(GPIO_PTN4, PTN4_DATA), +- PINMUX_GPIO(GPIO_PTN3, PTN3_DATA), +- PINMUX_GPIO(GPIO_PTN2, PTN2_DATA), +- PINMUX_GPIO(GPIO_PTN1, PTN1_DATA), +- PINMUX_GPIO(GPIO_PTN0, PTN0_DATA), ++ PINMUX_GPIO(PTN6), ++ PINMUX_GPIO(PTN5), ++ PINMUX_GPIO(PTN4), ++ PINMUX_GPIO(PTN3), ++ PINMUX_GPIO(PTN2), ++ PINMUX_GPIO(PTN1), ++ PINMUX_GPIO(PTN0), + + /* PTO */ +- PINMUX_GPIO(GPIO_PTO7, PTO7_DATA), +- PINMUX_GPIO(GPIO_PTO6, PTO6_DATA), +- PINMUX_GPIO(GPIO_PTO5, PTO5_DATA), +- PINMUX_GPIO(GPIO_PTO4, PTO4_DATA), +- PINMUX_GPIO(GPIO_PTO3, PTO3_DATA), +- PINMUX_GPIO(GPIO_PTO2, PTO2_DATA), +- PINMUX_GPIO(GPIO_PTO1, PTO1_DATA), +- PINMUX_GPIO(GPIO_PTO0, PTO0_DATA), ++ PINMUX_GPIO(PTO7), ++ PINMUX_GPIO(PTO6), ++ PINMUX_GPIO(PTO5), ++ PINMUX_GPIO(PTO4), ++ PINMUX_GPIO(PTO3), ++ PINMUX_GPIO(PTO2), ++ PINMUX_GPIO(PTO1), ++ PINMUX_GPIO(PTO0), + + /* PTP */ +- PINMUX_GPIO(GPIO_PTP7, PTP7_DATA), +- PINMUX_GPIO(GPIO_PTP6, PTP6_DATA), +- PINMUX_GPIO(GPIO_PTP5, PTP5_DATA), +- PINMUX_GPIO(GPIO_PTP4, PTP4_DATA), +- PINMUX_GPIO(GPIO_PTP3, PTP3_DATA), +- PINMUX_GPIO(GPIO_PTP2, PTP2_DATA), +- PINMUX_GPIO(GPIO_PTP1, PTP1_DATA), +- PINMUX_GPIO(GPIO_PTP0, PTP0_DATA), ++ PINMUX_GPIO(PTP7), ++ PINMUX_GPIO(PTP6), ++ PINMUX_GPIO(PTP5), ++ PINMUX_GPIO(PTP4), ++ PINMUX_GPIO(PTP3), ++ PINMUX_GPIO(PTP2), ++ PINMUX_GPIO(PTP1), ++ PINMUX_GPIO(PTP0), + + /* PTQ */ +- PINMUX_GPIO(GPIO_PTQ6, PTQ6_DATA), +- PINMUX_GPIO(GPIO_PTQ5, PTQ5_DATA), +- PINMUX_GPIO(GPIO_PTQ4, PTQ4_DATA), +- PINMUX_GPIO(GPIO_PTQ3, PTQ3_DATA), +- PINMUX_GPIO(GPIO_PTQ2, PTQ2_DATA), +- PINMUX_GPIO(GPIO_PTQ1, PTQ1_DATA), +- PINMUX_GPIO(GPIO_PTQ0, PTQ0_DATA), ++ PINMUX_GPIO(PTQ6), ++ PINMUX_GPIO(PTQ5), ++ PINMUX_GPIO(PTQ4), ++ PINMUX_GPIO(PTQ3), ++ PINMUX_GPIO(PTQ2), ++ PINMUX_GPIO(PTQ1), ++ PINMUX_GPIO(PTQ0), + + /* PTR */ +- PINMUX_GPIO(GPIO_PTR7, PTR7_DATA), +- PINMUX_GPIO(GPIO_PTR6, PTR6_DATA), +- PINMUX_GPIO(GPIO_PTR5, PTR5_DATA), +- PINMUX_GPIO(GPIO_PTR4, PTR4_DATA), +- PINMUX_GPIO(GPIO_PTR3, PTR3_DATA), +- PINMUX_GPIO(GPIO_PTR2, PTR2_DATA), +- PINMUX_GPIO(GPIO_PTR1, PTR1_DATA), +- PINMUX_GPIO(GPIO_PTR0, PTR0_DATA), ++ PINMUX_GPIO(PTR7), ++ PINMUX_GPIO(PTR6), ++ PINMUX_GPIO(PTR5), ++ PINMUX_GPIO(PTR4), ++ PINMUX_GPIO(PTR3), ++ PINMUX_GPIO(PTR2), ++ PINMUX_GPIO(PTR1), ++ PINMUX_GPIO(PTR0), + + /* PTS */ +- PINMUX_GPIO(GPIO_PTS7, PTS7_DATA), +- PINMUX_GPIO(GPIO_PTS6, PTS6_DATA), +- PINMUX_GPIO(GPIO_PTS5, PTS5_DATA), +- PINMUX_GPIO(GPIO_PTS4, PTS4_DATA), +- PINMUX_GPIO(GPIO_PTS3, PTS3_DATA), +- PINMUX_GPIO(GPIO_PTS2, PTS2_DATA), +- PINMUX_GPIO(GPIO_PTS1, PTS1_DATA), +- PINMUX_GPIO(GPIO_PTS0, PTS0_DATA), ++ PINMUX_GPIO(PTS7), ++ PINMUX_GPIO(PTS6), ++ PINMUX_GPIO(PTS5), ++ PINMUX_GPIO(PTS4), ++ PINMUX_GPIO(PTS3), ++ PINMUX_GPIO(PTS2), ++ PINMUX_GPIO(PTS1), ++ PINMUX_GPIO(PTS0), + + /* PTT */ +- PINMUX_GPIO(GPIO_PTT7, PTT7_DATA), +- PINMUX_GPIO(GPIO_PTT6, PTT6_DATA), +- PINMUX_GPIO(GPIO_PTT5, PTT5_DATA), +- PINMUX_GPIO(GPIO_PTT4, PTT4_DATA), +- PINMUX_GPIO(GPIO_PTT3, PTT3_DATA), +- PINMUX_GPIO(GPIO_PTT2, PTT2_DATA), +- PINMUX_GPIO(GPIO_PTT1, PTT1_DATA), +- PINMUX_GPIO(GPIO_PTT0, PTT0_DATA), ++ PINMUX_GPIO(PTT7), ++ PINMUX_GPIO(PTT6), ++ PINMUX_GPIO(PTT5), ++ PINMUX_GPIO(PTT4), ++ PINMUX_GPIO(PTT3), ++ PINMUX_GPIO(PTT2), ++ PINMUX_GPIO(PTT1), ++ PINMUX_GPIO(PTT0), + + /* PTU */ +- PINMUX_GPIO(GPIO_PTU7, PTU7_DATA), +- PINMUX_GPIO(GPIO_PTU6, PTU6_DATA), +- PINMUX_GPIO(GPIO_PTU5, PTU5_DATA), +- PINMUX_GPIO(GPIO_PTU4, PTU4_DATA), +- PINMUX_GPIO(GPIO_PTU3, PTU3_DATA), +- PINMUX_GPIO(GPIO_PTU2, PTU2_DATA), +- PINMUX_GPIO(GPIO_PTU1, PTU1_DATA), +- PINMUX_GPIO(GPIO_PTU0, PTU0_DATA), ++ PINMUX_GPIO(PTU7), ++ PINMUX_GPIO(PTU6), ++ PINMUX_GPIO(PTU5), ++ PINMUX_GPIO(PTU4), ++ PINMUX_GPIO(PTU3), ++ PINMUX_GPIO(PTU2), ++ PINMUX_GPIO(PTU1), ++ PINMUX_GPIO(PTU0), + + /* PTV */ +- PINMUX_GPIO(GPIO_PTV7, PTV7_DATA), +- PINMUX_GPIO(GPIO_PTV6, PTV6_DATA), +- PINMUX_GPIO(GPIO_PTV5, PTV5_DATA), +- PINMUX_GPIO(GPIO_PTV4, PTV4_DATA), +- PINMUX_GPIO(GPIO_PTV3, PTV3_DATA), +- PINMUX_GPIO(GPIO_PTV2, PTV2_DATA), +- PINMUX_GPIO(GPIO_PTV1, PTV1_DATA), +- PINMUX_GPIO(GPIO_PTV0, PTV0_DATA), ++ PINMUX_GPIO(PTV7), ++ PINMUX_GPIO(PTV6), ++ PINMUX_GPIO(PTV5), ++ PINMUX_GPIO(PTV4), ++ PINMUX_GPIO(PTV3), ++ PINMUX_GPIO(PTV2), ++ PINMUX_GPIO(PTV1), ++ PINMUX_GPIO(PTV0), + + /* PTW */ +- PINMUX_GPIO(GPIO_PTW7, PTW7_DATA), +- PINMUX_GPIO(GPIO_PTW6, PTW6_DATA), +- PINMUX_GPIO(GPIO_PTW5, PTW5_DATA), +- PINMUX_GPIO(GPIO_PTW4, PTW4_DATA), +- PINMUX_GPIO(GPIO_PTW3, PTW3_DATA), +- PINMUX_GPIO(GPIO_PTW2, PTW2_DATA), +- PINMUX_GPIO(GPIO_PTW1, PTW1_DATA), +- PINMUX_GPIO(GPIO_PTW0, PTW0_DATA), ++ PINMUX_GPIO(PTW7), ++ PINMUX_GPIO(PTW6), ++ PINMUX_GPIO(PTW5), ++ PINMUX_GPIO(PTW4), ++ PINMUX_GPIO(PTW3), ++ PINMUX_GPIO(PTW2), ++ PINMUX_GPIO(PTW1), ++ PINMUX_GPIO(PTW0), + + /* PTX */ +- PINMUX_GPIO(GPIO_PTX7, PTX7_DATA), +- PINMUX_GPIO(GPIO_PTX6, PTX6_DATA), +- PINMUX_GPIO(GPIO_PTX5, PTX5_DATA), +- PINMUX_GPIO(GPIO_PTX4, PTX4_DATA), +- PINMUX_GPIO(GPIO_PTX3, PTX3_DATA), +- PINMUX_GPIO(GPIO_PTX2, PTX2_DATA), +- PINMUX_GPIO(GPIO_PTX1, PTX1_DATA), +- PINMUX_GPIO(GPIO_PTX0, PTX0_DATA), ++ PINMUX_GPIO(PTX7), ++ PINMUX_GPIO(PTX6), ++ PINMUX_GPIO(PTX5), ++ PINMUX_GPIO(PTX4), ++ PINMUX_GPIO(PTX3), ++ PINMUX_GPIO(PTX2), ++ PINMUX_GPIO(PTX1), ++ PINMUX_GPIO(PTX0), + + /* PTY */ +- PINMUX_GPIO(GPIO_PTY7, PTY7_DATA), +- PINMUX_GPIO(GPIO_PTY6, PTY6_DATA), +- PINMUX_GPIO(GPIO_PTY5, PTY5_DATA), +- PINMUX_GPIO(GPIO_PTY4, PTY4_DATA), +- PINMUX_GPIO(GPIO_PTY3, PTY3_DATA), +- PINMUX_GPIO(GPIO_PTY2, PTY2_DATA), +- PINMUX_GPIO(GPIO_PTY1, PTY1_DATA), +- PINMUX_GPIO(GPIO_PTY0, PTY0_DATA), ++ PINMUX_GPIO(PTY7), ++ PINMUX_GPIO(PTY6), ++ PINMUX_GPIO(PTY5), ++ PINMUX_GPIO(PTY4), ++ PINMUX_GPIO(PTY3), ++ PINMUX_GPIO(PTY2), ++ PINMUX_GPIO(PTY1), ++ PINMUX_GPIO(PTY0), + + /* PTZ */ +- PINMUX_GPIO(GPIO_PTZ7, PTZ7_DATA), +- PINMUX_GPIO(GPIO_PTZ6, PTZ6_DATA), +- PINMUX_GPIO(GPIO_PTZ5, PTZ5_DATA), +- PINMUX_GPIO(GPIO_PTZ4, PTZ4_DATA), +- PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA), +- PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA), +- PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), +- PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA), ++ PINMUX_GPIO(PTZ7), ++ PINMUX_GPIO(PTZ6), ++ PINMUX_GPIO(PTZ5), ++ PINMUX_GPIO(PTZ4), ++ PINMUX_GPIO(PTZ3), ++ PINMUX_GPIO(PTZ2), ++ PINMUX_GPIO(PTZ1), ++ PINMUX_GPIO(PTZ0), + }; + + #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7785.c b/drivers/pinctrl/sh-pfc/pfc-sh7785.c +index 209289c8..517eb49d 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7785.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7785.c +@@ -673,147 +673,147 @@ static const u16 pinmux_data[] = { + + static struct sh_pfc_pin pinmux_pins[] = { + /* PA */ +- PINMUX_GPIO(GPIO_PA7, PA7_DATA), +- PINMUX_GPIO(GPIO_PA6, PA6_DATA), +- PINMUX_GPIO(GPIO_PA5, PA5_DATA), +- PINMUX_GPIO(GPIO_PA4, PA4_DATA), +- PINMUX_GPIO(GPIO_PA3, PA3_DATA), +- PINMUX_GPIO(GPIO_PA2, PA2_DATA), +- PINMUX_GPIO(GPIO_PA1, PA1_DATA), +- PINMUX_GPIO(GPIO_PA0, PA0_DATA), ++ PINMUX_GPIO(PA7), ++ PINMUX_GPIO(PA6), ++ PINMUX_GPIO(PA5), ++ PINMUX_GPIO(PA4), ++ PINMUX_GPIO(PA3), ++ PINMUX_GPIO(PA2), ++ PINMUX_GPIO(PA1), ++ PINMUX_GPIO(PA0), + + /* PB */ +- PINMUX_GPIO(GPIO_PB7, PB7_DATA), +- PINMUX_GPIO(GPIO_PB6, PB6_DATA), +- PINMUX_GPIO(GPIO_PB5, PB5_DATA), +- PINMUX_GPIO(GPIO_PB4, PB4_DATA), +- PINMUX_GPIO(GPIO_PB3, PB3_DATA), +- PINMUX_GPIO(GPIO_PB2, PB2_DATA), +- PINMUX_GPIO(GPIO_PB1, PB1_DATA), +- PINMUX_GPIO(GPIO_PB0, PB0_DATA), ++ PINMUX_GPIO(PB7), ++ PINMUX_GPIO(PB6), ++ PINMUX_GPIO(PB5), ++ PINMUX_GPIO(PB4), ++ PINMUX_GPIO(PB3), ++ PINMUX_GPIO(PB2), ++ PINMUX_GPIO(PB1), ++ PINMUX_GPIO(PB0), + + /* PC */ +- PINMUX_GPIO(GPIO_PC7, PC7_DATA), +- PINMUX_GPIO(GPIO_PC6, PC6_DATA), +- PINMUX_GPIO(GPIO_PC5, PC5_DATA), +- PINMUX_GPIO(GPIO_PC4, PC4_DATA), +- PINMUX_GPIO(GPIO_PC3, PC3_DATA), +- PINMUX_GPIO(GPIO_PC2, PC2_DATA), +- PINMUX_GPIO(GPIO_PC1, PC1_DATA), +- PINMUX_GPIO(GPIO_PC0, PC0_DATA), ++ PINMUX_GPIO(PC7), ++ PINMUX_GPIO(PC6), ++ PINMUX_GPIO(PC5), ++ PINMUX_GPIO(PC4), ++ PINMUX_GPIO(PC3), ++ PINMUX_GPIO(PC2), ++ PINMUX_GPIO(PC1), ++ PINMUX_GPIO(PC0), + + /* PD */ +- PINMUX_GPIO(GPIO_PD7, PD7_DATA), +- PINMUX_GPIO(GPIO_PD6, PD6_DATA), +- PINMUX_GPIO(GPIO_PD5, PD5_DATA), +- PINMUX_GPIO(GPIO_PD4, PD4_DATA), +- PINMUX_GPIO(GPIO_PD3, PD3_DATA), +- PINMUX_GPIO(GPIO_PD2, PD2_DATA), +- PINMUX_GPIO(GPIO_PD1, PD1_DATA), +- PINMUX_GPIO(GPIO_PD0, PD0_DATA), ++ PINMUX_GPIO(PD7), ++ PINMUX_GPIO(PD6), ++ PINMUX_GPIO(PD5), ++ PINMUX_GPIO(PD4), ++ PINMUX_GPIO(PD3), ++ PINMUX_GPIO(PD2), ++ PINMUX_GPIO(PD1), ++ PINMUX_GPIO(PD0), + + /* PE */ +- PINMUX_GPIO(GPIO_PE5, PE5_DATA), +- PINMUX_GPIO(GPIO_PE4, PE4_DATA), +- PINMUX_GPIO(GPIO_PE3, PE3_DATA), +- PINMUX_GPIO(GPIO_PE2, PE2_DATA), +- PINMUX_GPIO(GPIO_PE1, PE1_DATA), +- PINMUX_GPIO(GPIO_PE0, PE0_DATA), ++ PINMUX_GPIO(PE5), ++ PINMUX_GPIO(PE4), ++ PINMUX_GPIO(PE3), ++ PINMUX_GPIO(PE2), ++ PINMUX_GPIO(PE1), ++ PINMUX_GPIO(PE0), + + /* PF */ +- PINMUX_GPIO(GPIO_PF7, PF7_DATA), +- PINMUX_GPIO(GPIO_PF6, PF6_DATA), +- PINMUX_GPIO(GPIO_PF5, PF5_DATA), +- PINMUX_GPIO(GPIO_PF4, PF4_DATA), +- PINMUX_GPIO(GPIO_PF3, PF3_DATA), +- PINMUX_GPIO(GPIO_PF2, PF2_DATA), +- PINMUX_GPIO(GPIO_PF1, PF1_DATA), +- PINMUX_GPIO(GPIO_PF0, PF0_DATA), ++ PINMUX_GPIO(PF7), ++ PINMUX_GPIO(PF6), ++ PINMUX_GPIO(PF5), ++ PINMUX_GPIO(PF4), ++ PINMUX_GPIO(PF3), ++ PINMUX_GPIO(PF2), ++ PINMUX_GPIO(PF1), ++ PINMUX_GPIO(PF0), + + /* PG */ +- PINMUX_GPIO(GPIO_PG7, PG7_DATA), +- PINMUX_GPIO(GPIO_PG6, PG6_DATA), +- PINMUX_GPIO(GPIO_PG5, PG5_DATA), +- PINMUX_GPIO(GPIO_PG4, PG4_DATA), +- PINMUX_GPIO(GPIO_PG3, PG3_DATA), +- PINMUX_GPIO(GPIO_PG2, PG2_DATA), +- PINMUX_GPIO(GPIO_PG1, PG1_DATA), +- PINMUX_GPIO(GPIO_PG0, PG0_DATA), ++ PINMUX_GPIO(PG7), ++ PINMUX_GPIO(PG6), ++ PINMUX_GPIO(PG5), ++ PINMUX_GPIO(PG4), ++ PINMUX_GPIO(PG3), ++ PINMUX_GPIO(PG2), ++ PINMUX_GPIO(PG1), ++ PINMUX_GPIO(PG0), + + /* PH */ +- PINMUX_GPIO(GPIO_PH7, PH7_DATA), +- PINMUX_GPIO(GPIO_PH6, PH6_DATA), +- PINMUX_GPIO(GPIO_PH5, PH5_DATA), +- PINMUX_GPIO(GPIO_PH4, PH4_DATA), +- PINMUX_GPIO(GPIO_PH3, PH3_DATA), +- PINMUX_GPIO(GPIO_PH2, PH2_DATA), +- PINMUX_GPIO(GPIO_PH1, PH1_DATA), +- PINMUX_GPIO(GPIO_PH0, PH0_DATA), ++ PINMUX_GPIO(PH7), ++ PINMUX_GPIO(PH6), ++ PINMUX_GPIO(PH5), ++ PINMUX_GPIO(PH4), ++ PINMUX_GPIO(PH3), ++ PINMUX_GPIO(PH2), ++ PINMUX_GPIO(PH1), ++ PINMUX_GPIO(PH0), + + /* PJ */ +- PINMUX_GPIO(GPIO_PJ7, PJ7_DATA), +- PINMUX_GPIO(GPIO_PJ6, PJ6_DATA), +- PINMUX_GPIO(GPIO_PJ5, PJ5_DATA), +- PINMUX_GPIO(GPIO_PJ4, PJ4_DATA), +- PINMUX_GPIO(GPIO_PJ3, PJ3_DATA), +- PINMUX_GPIO(GPIO_PJ2, PJ2_DATA), +- PINMUX_GPIO(GPIO_PJ1, PJ1_DATA), +- PINMUX_GPIO(GPIO_PJ0, PJ0_DATA), ++ PINMUX_GPIO(PJ7), ++ PINMUX_GPIO(PJ6), ++ PINMUX_GPIO(PJ5), ++ PINMUX_GPIO(PJ4), ++ PINMUX_GPIO(PJ3), ++ PINMUX_GPIO(PJ2), ++ PINMUX_GPIO(PJ1), ++ PINMUX_GPIO(PJ0), + + /* PK */ +- PINMUX_GPIO(GPIO_PK7, PK7_DATA), +- PINMUX_GPIO(GPIO_PK6, PK6_DATA), +- PINMUX_GPIO(GPIO_PK5, PK5_DATA), +- PINMUX_GPIO(GPIO_PK4, PK4_DATA), +- PINMUX_GPIO(GPIO_PK3, PK3_DATA), +- PINMUX_GPIO(GPIO_PK2, PK2_DATA), +- PINMUX_GPIO(GPIO_PK1, PK1_DATA), +- PINMUX_GPIO(GPIO_PK0, PK0_DATA), ++ PINMUX_GPIO(PK7), ++ PINMUX_GPIO(PK6), ++ PINMUX_GPIO(PK5), ++ PINMUX_GPIO(PK4), ++ PINMUX_GPIO(PK3), ++ PINMUX_GPIO(PK2), ++ PINMUX_GPIO(PK1), ++ PINMUX_GPIO(PK0), + + /* PL */ +- PINMUX_GPIO(GPIO_PL7, PL7_DATA), +- PINMUX_GPIO(GPIO_PL6, PL6_DATA), +- PINMUX_GPIO(GPIO_PL5, PL5_DATA), +- PINMUX_GPIO(GPIO_PL4, PL4_DATA), +- PINMUX_GPIO(GPIO_PL3, PL3_DATA), +- PINMUX_GPIO(GPIO_PL2, PL2_DATA), +- PINMUX_GPIO(GPIO_PL1, PL1_DATA), +- PINMUX_GPIO(GPIO_PL0, PL0_DATA), ++ PINMUX_GPIO(PL7), ++ PINMUX_GPIO(PL6), ++ PINMUX_GPIO(PL5), ++ PINMUX_GPIO(PL4), ++ PINMUX_GPIO(PL3), ++ PINMUX_GPIO(PL2), ++ PINMUX_GPIO(PL1), ++ PINMUX_GPIO(PL0), + + /* PM */ +- PINMUX_GPIO(GPIO_PM1, PM1_DATA), +- PINMUX_GPIO(GPIO_PM0, PM0_DATA), ++ PINMUX_GPIO(PM1), ++ PINMUX_GPIO(PM0), + + /* PN */ +- PINMUX_GPIO(GPIO_PN7, PN7_DATA), +- PINMUX_GPIO(GPIO_PN6, PN6_DATA), +- PINMUX_GPIO(GPIO_PN5, PN5_DATA), +- PINMUX_GPIO(GPIO_PN4, PN4_DATA), +- PINMUX_GPIO(GPIO_PN3, PN3_DATA), +- PINMUX_GPIO(GPIO_PN2, PN2_DATA), +- PINMUX_GPIO(GPIO_PN1, PN1_DATA), +- PINMUX_GPIO(GPIO_PN0, PN0_DATA), ++ PINMUX_GPIO(PN7), ++ PINMUX_GPIO(PN6), ++ PINMUX_GPIO(PN5), ++ PINMUX_GPIO(PN4), ++ PINMUX_GPIO(PN3), ++ PINMUX_GPIO(PN2), ++ PINMUX_GPIO(PN1), ++ PINMUX_GPIO(PN0), + + /* PP */ +- PINMUX_GPIO(GPIO_PP5, PP5_DATA), +- PINMUX_GPIO(GPIO_PP4, PP4_DATA), +- PINMUX_GPIO(GPIO_PP3, PP3_DATA), +- PINMUX_GPIO(GPIO_PP2, PP2_DATA), +- PINMUX_GPIO(GPIO_PP1, PP1_DATA), +- PINMUX_GPIO(GPIO_PP0, PP0_DATA), ++ PINMUX_GPIO(PP5), ++ PINMUX_GPIO(PP4), ++ PINMUX_GPIO(PP3), ++ PINMUX_GPIO(PP2), ++ PINMUX_GPIO(PP1), ++ PINMUX_GPIO(PP0), + + /* PQ */ +- PINMUX_GPIO(GPIO_PQ4, PQ4_DATA), +- PINMUX_GPIO(GPIO_PQ3, PQ3_DATA), +- PINMUX_GPIO(GPIO_PQ2, PQ2_DATA), +- PINMUX_GPIO(GPIO_PQ1, PQ1_DATA), +- PINMUX_GPIO(GPIO_PQ0, PQ0_DATA), ++ PINMUX_GPIO(PQ4), ++ PINMUX_GPIO(PQ3), ++ PINMUX_GPIO(PQ2), ++ PINMUX_GPIO(PQ1), ++ PINMUX_GPIO(PQ0), + + /* PR */ +- PINMUX_GPIO(GPIO_PR3, PR3_DATA), +- PINMUX_GPIO(GPIO_PR2, PR2_DATA), +- PINMUX_GPIO(GPIO_PR1, PR1_DATA), +- PINMUX_GPIO(GPIO_PR0, PR0_DATA), ++ PINMUX_GPIO(PR3), ++ PINMUX_GPIO(PR2), ++ PINMUX_GPIO(PR1), ++ PINMUX_GPIO(PR0), + }; + + #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7786.c b/drivers/pinctrl/sh-pfc/pfc-sh7786.c +index 353fde1f..623345fa 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7786.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7786.c +@@ -409,82 +409,82 @@ static const u16 pinmux_data[] = { + + static struct sh_pfc_pin pinmux_pins[] = { + /* PA */ +- PINMUX_GPIO(GPIO_PA7, PA7_DATA), +- PINMUX_GPIO(GPIO_PA6, PA6_DATA), +- PINMUX_GPIO(GPIO_PA5, PA5_DATA), +- PINMUX_GPIO(GPIO_PA4, PA4_DATA), +- PINMUX_GPIO(GPIO_PA3, PA3_DATA), +- PINMUX_GPIO(GPIO_PA2, PA2_DATA), +- PINMUX_GPIO(GPIO_PA1, PA1_DATA), +- PINMUX_GPIO(GPIO_PA0, PA0_DATA), ++ PINMUX_GPIO(PA7), ++ PINMUX_GPIO(PA6), ++ PINMUX_GPIO(PA5), ++ PINMUX_GPIO(PA4), ++ PINMUX_GPIO(PA3), ++ PINMUX_GPIO(PA2), ++ PINMUX_GPIO(PA1), ++ PINMUX_GPIO(PA0), + + /* PB */ +- PINMUX_GPIO(GPIO_PB7, PB7_DATA), +- PINMUX_GPIO(GPIO_PB6, PB6_DATA), +- PINMUX_GPIO(GPIO_PB5, PB5_DATA), +- PINMUX_GPIO(GPIO_PB4, PB4_DATA), +- PINMUX_GPIO(GPIO_PB3, PB3_DATA), +- PINMUX_GPIO(GPIO_PB2, PB2_DATA), +- PINMUX_GPIO(GPIO_PB1, PB1_DATA), +- PINMUX_GPIO(GPIO_PB0, PB0_DATA), ++ PINMUX_GPIO(PB7), ++ PINMUX_GPIO(PB6), ++ PINMUX_GPIO(PB5), ++ PINMUX_GPIO(PB4), ++ PINMUX_GPIO(PB3), ++ PINMUX_GPIO(PB2), ++ PINMUX_GPIO(PB1), ++ PINMUX_GPIO(PB0), + + /* PC */ +- PINMUX_GPIO(GPIO_PC7, PC7_DATA), +- PINMUX_GPIO(GPIO_PC6, PC6_DATA), +- PINMUX_GPIO(GPIO_PC5, PC5_DATA), +- PINMUX_GPIO(GPIO_PC4, PC4_DATA), +- PINMUX_GPIO(GPIO_PC3, PC3_DATA), +- PINMUX_GPIO(GPIO_PC2, PC2_DATA), +- PINMUX_GPIO(GPIO_PC1, PC1_DATA), +- PINMUX_GPIO(GPIO_PC0, PC0_DATA), ++ PINMUX_GPIO(PC7), ++ PINMUX_GPIO(PC6), ++ PINMUX_GPIO(PC5), ++ PINMUX_GPIO(PC4), ++ PINMUX_GPIO(PC3), ++ PINMUX_GPIO(PC2), ++ PINMUX_GPIO(PC1), ++ PINMUX_GPIO(PC0), + + /* PD */ +- PINMUX_GPIO(GPIO_PD7, PD7_DATA), +- PINMUX_GPIO(GPIO_PD6, PD6_DATA), +- PINMUX_GPIO(GPIO_PD5, PD5_DATA), +- PINMUX_GPIO(GPIO_PD4, PD4_DATA), +- PINMUX_GPIO(GPIO_PD3, PD3_DATA), +- PINMUX_GPIO(GPIO_PD2, PD2_DATA), +- PINMUX_GPIO(GPIO_PD1, PD1_DATA), +- PINMUX_GPIO(GPIO_PD0, PD0_DATA), ++ PINMUX_GPIO(PD7), ++ PINMUX_GPIO(PD6), ++ PINMUX_GPIO(PD5), ++ PINMUX_GPIO(PD4), ++ PINMUX_GPIO(PD3), ++ PINMUX_GPIO(PD2), ++ PINMUX_GPIO(PD1), ++ PINMUX_GPIO(PD0), + + /* PE */ +- PINMUX_GPIO(GPIO_PE7, PE7_DATA), +- PINMUX_GPIO(GPIO_PE6, PE6_DATA), ++ PINMUX_GPIO(PE7), ++ PINMUX_GPIO(PE6), + + /* PF */ +- PINMUX_GPIO(GPIO_PF7, PF7_DATA), +- PINMUX_GPIO(GPIO_PF6, PF6_DATA), +- PINMUX_GPIO(GPIO_PF5, PF5_DATA), +- PINMUX_GPIO(GPIO_PF4, PF4_DATA), +- PINMUX_GPIO(GPIO_PF3, PF3_DATA), +- PINMUX_GPIO(GPIO_PF2, PF2_DATA), +- PINMUX_GPIO(GPIO_PF1, PF1_DATA), +- PINMUX_GPIO(GPIO_PF0, PF0_DATA), ++ PINMUX_GPIO(PF7), ++ PINMUX_GPIO(PF6), ++ PINMUX_GPIO(PF5), ++ PINMUX_GPIO(PF4), ++ PINMUX_GPIO(PF3), ++ PINMUX_GPIO(PF2), ++ PINMUX_GPIO(PF1), ++ PINMUX_GPIO(PF0), + + /* PG */ +- PINMUX_GPIO(GPIO_PG7, PG7_DATA), +- PINMUX_GPIO(GPIO_PG6, PG6_DATA), +- PINMUX_GPIO(GPIO_PG5, PG5_DATA), ++ PINMUX_GPIO(PG7), ++ PINMUX_GPIO(PG6), ++ PINMUX_GPIO(PG5), + + /* PH */ +- PINMUX_GPIO(GPIO_PH7, PH7_DATA), +- PINMUX_GPIO(GPIO_PH6, PH6_DATA), +- PINMUX_GPIO(GPIO_PH5, PH5_DATA), +- PINMUX_GPIO(GPIO_PH4, PH4_DATA), +- PINMUX_GPIO(GPIO_PH3, PH3_DATA), +- PINMUX_GPIO(GPIO_PH2, PH2_DATA), +- PINMUX_GPIO(GPIO_PH1, PH1_DATA), +- PINMUX_GPIO(GPIO_PH0, PH0_DATA), ++ PINMUX_GPIO(PH7), ++ PINMUX_GPIO(PH6), ++ PINMUX_GPIO(PH5), ++ PINMUX_GPIO(PH4), ++ PINMUX_GPIO(PH3), ++ PINMUX_GPIO(PH2), ++ PINMUX_GPIO(PH1), ++ PINMUX_GPIO(PH0), + + /* PJ */ +- PINMUX_GPIO(GPIO_PJ7, PJ7_DATA), +- PINMUX_GPIO(GPIO_PJ6, PJ6_DATA), +- PINMUX_GPIO(GPIO_PJ5, PJ5_DATA), +- PINMUX_GPIO(GPIO_PJ4, PJ4_DATA), +- PINMUX_GPIO(GPIO_PJ3, PJ3_DATA), +- PINMUX_GPIO(GPIO_PJ2, PJ2_DATA), +- PINMUX_GPIO(GPIO_PJ1, PJ1_DATA), ++ PINMUX_GPIO(PJ7), ++ PINMUX_GPIO(PJ6), ++ PINMUX_GPIO(PJ5), ++ PINMUX_GPIO(PJ4), ++ PINMUX_GPIO(PJ3), ++ PINMUX_GPIO(PJ2), ++ PINMUX_GPIO(PJ1), + }; + + #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) +diff --git a/drivers/pinctrl/sh-pfc/pfc-shx3.c b/drivers/pinctrl/sh-pfc/pfc-shx3.c +index 775a622b..55262bd8 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-shx3.c ++++ b/drivers/pinctrl/sh-pfc/pfc-shx3.c +@@ -287,82 +287,82 @@ static const u16 pinmux_data[] = { + + static struct sh_pfc_pin pinmux_pins[] = { + /* PA */ +- PINMUX_GPIO(GPIO_PA7, PA7_DATA), +- PINMUX_GPIO(GPIO_PA6, PA6_DATA), +- PINMUX_GPIO(GPIO_PA5, PA5_DATA), +- PINMUX_GPIO(GPIO_PA4, PA4_DATA), +- PINMUX_GPIO(GPIO_PA3, PA3_DATA), +- PINMUX_GPIO(GPIO_PA2, PA2_DATA), +- PINMUX_GPIO(GPIO_PA1, PA1_DATA), +- PINMUX_GPIO(GPIO_PA0, PA0_DATA), ++ PINMUX_GPIO(PA7), ++ PINMUX_GPIO(PA6), ++ PINMUX_GPIO(PA5), ++ PINMUX_GPIO(PA4), ++ PINMUX_GPIO(PA3), ++ PINMUX_GPIO(PA2), ++ PINMUX_GPIO(PA1), ++ PINMUX_GPIO(PA0), + + /* PB */ +- PINMUX_GPIO(GPIO_PB7, PB7_DATA), +- PINMUX_GPIO(GPIO_PB6, PB6_DATA), +- PINMUX_GPIO(GPIO_PB5, PB5_DATA), +- PINMUX_GPIO(GPIO_PB4, PB4_DATA), +- PINMUX_GPIO(GPIO_PB3, PB3_DATA), +- PINMUX_GPIO(GPIO_PB2, PB2_DATA), +- PINMUX_GPIO(GPIO_PB1, PB1_DATA), +- PINMUX_GPIO(GPIO_PB0, PB0_DATA), ++ PINMUX_GPIO(PB7), ++ PINMUX_GPIO(PB6), ++ PINMUX_GPIO(PB5), ++ PINMUX_GPIO(PB4), ++ PINMUX_GPIO(PB3), ++ PINMUX_GPIO(PB2), ++ PINMUX_GPIO(PB1), ++ PINMUX_GPIO(PB0), + + /* PC */ +- PINMUX_GPIO(GPIO_PC7, PC7_DATA), +- PINMUX_GPIO(GPIO_PC6, PC6_DATA), +- PINMUX_GPIO(GPIO_PC5, PC5_DATA), +- PINMUX_GPIO(GPIO_PC4, PC4_DATA), +- PINMUX_GPIO(GPIO_PC3, PC3_DATA), +- PINMUX_GPIO(GPIO_PC2, PC2_DATA), +- PINMUX_GPIO(GPIO_PC1, PC1_DATA), +- PINMUX_GPIO(GPIO_PC0, PC0_DATA), ++ PINMUX_GPIO(PC7), ++ PINMUX_GPIO(PC6), ++ PINMUX_GPIO(PC5), ++ PINMUX_GPIO(PC4), ++ PINMUX_GPIO(PC3), ++ PINMUX_GPIO(PC2), ++ PINMUX_GPIO(PC1), ++ PINMUX_GPIO(PC0), + + /* PD */ +- PINMUX_GPIO(GPIO_PD7, PD7_DATA), +- PINMUX_GPIO(GPIO_PD6, PD6_DATA), +- PINMUX_GPIO(GPIO_PD5, PD5_DATA), +- PINMUX_GPIO(GPIO_PD4, PD4_DATA), +- PINMUX_GPIO(GPIO_PD3, PD3_DATA), +- PINMUX_GPIO(GPIO_PD2, PD2_DATA), +- PINMUX_GPIO(GPIO_PD1, PD1_DATA), +- PINMUX_GPIO(GPIO_PD0, PD0_DATA), ++ PINMUX_GPIO(PD7), ++ PINMUX_GPIO(PD6), ++ PINMUX_GPIO(PD5), ++ PINMUX_GPIO(PD4), ++ PINMUX_GPIO(PD3), ++ PINMUX_GPIO(PD2), ++ PINMUX_GPIO(PD1), ++ PINMUX_GPIO(PD0), + + /* PE */ +- PINMUX_GPIO(GPIO_PE7, PE7_DATA), +- PINMUX_GPIO(GPIO_PE6, PE6_DATA), +- PINMUX_GPIO(GPIO_PE5, PE5_DATA), +- PINMUX_GPIO(GPIO_PE4, PE4_DATA), +- PINMUX_GPIO(GPIO_PE3, PE3_DATA), +- PINMUX_GPIO(GPIO_PE2, PE2_DATA), +- PINMUX_GPIO(GPIO_PE1, PE1_DATA), +- PINMUX_GPIO(GPIO_PE0, PE0_DATA), ++ PINMUX_GPIO(PE7), ++ PINMUX_GPIO(PE6), ++ PINMUX_GPIO(PE5), ++ PINMUX_GPIO(PE4), ++ PINMUX_GPIO(PE3), ++ PINMUX_GPIO(PE2), ++ PINMUX_GPIO(PE1), ++ PINMUX_GPIO(PE0), + + /* PF */ +- PINMUX_GPIO(GPIO_PF7, PF7_DATA), +- PINMUX_GPIO(GPIO_PF6, PF6_DATA), +- PINMUX_GPIO(GPIO_PF5, PF5_DATA), +- PINMUX_GPIO(GPIO_PF4, PF4_DATA), +- PINMUX_GPIO(GPIO_PF3, PF3_DATA), +- PINMUX_GPIO(GPIO_PF2, PF2_DATA), +- PINMUX_GPIO(GPIO_PF1, PF1_DATA), +- PINMUX_GPIO(GPIO_PF0, PF0_DATA), ++ PINMUX_GPIO(PF7), ++ PINMUX_GPIO(PF6), ++ PINMUX_GPIO(PF5), ++ PINMUX_GPIO(PF4), ++ PINMUX_GPIO(PF3), ++ PINMUX_GPIO(PF2), ++ PINMUX_GPIO(PF1), ++ PINMUX_GPIO(PF0), + + /* PG */ +- PINMUX_GPIO(GPIO_PG7, PG7_DATA), +- PINMUX_GPIO(GPIO_PG6, PG6_DATA), +- PINMUX_GPIO(GPIO_PG5, PG5_DATA), +- PINMUX_GPIO(GPIO_PG4, PG4_DATA), +- PINMUX_GPIO(GPIO_PG3, PG3_DATA), +- PINMUX_GPIO(GPIO_PG2, PG2_DATA), +- PINMUX_GPIO(GPIO_PG1, PG1_DATA), +- PINMUX_GPIO(GPIO_PG0, PG0_DATA), ++ PINMUX_GPIO(PG7), ++ PINMUX_GPIO(PG6), ++ PINMUX_GPIO(PG5), ++ PINMUX_GPIO(PG4), ++ PINMUX_GPIO(PG3), ++ PINMUX_GPIO(PG2), ++ PINMUX_GPIO(PG1), ++ PINMUX_GPIO(PG0), + + /* PH */ +- PINMUX_GPIO(GPIO_PH5, PH5_DATA), +- PINMUX_GPIO(GPIO_PH4, PH4_DATA), +- PINMUX_GPIO(GPIO_PH3, PH3_DATA), +- PINMUX_GPIO(GPIO_PH2, PH2_DATA), +- PINMUX_GPIO(GPIO_PH1, PH1_DATA), +- PINMUX_GPIO(GPIO_PH0, PH0_DATA), ++ PINMUX_GPIO(PH5), ++ PINMUX_GPIO(PH4), ++ PINMUX_GPIO(PH3), ++ PINMUX_GPIO(PH2), ++ PINMUX_GPIO(PH1), ++ PINMUX_GPIO(PH0), + }; + + #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) +diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h +index 05b905fa..61205fbf 100644 +--- a/drivers/pinctrl/sh-pfc/sh_pfc.h ++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h +@@ -250,10 +250,10 @@ struct sh_pfc_soc_info { + #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str) + + /* PINMUX_GPIO - Expand to a sh_pfc_pin entry */ +-#define PINMUX_GPIO(gpio, data_or_mark) \ +- [gpio] = { \ +- .name = __stringify(gpio), \ +- .enum_id = data_or_mark, \ ++#define PINMUX_GPIO(pin) \ ++ [GPIO_##pin] = { \ ++ .name = __stringify(name), \ ++ .enum_id = pin##_DATA, \ + } + + /* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0549-sh-pfc-Add-port-numbers-to-the-CPU_ALL_PORT-macro.patch b/patches.renesas/0549-sh-pfc-Add-port-numbers-to-the-CPU_ALL_PORT-macro.patch new file mode 100644 index 00000000000..5eb312ae222 --- /dev/null +++ b/patches.renesas/0549-sh-pfc-Add-port-numbers-to-the-CPU_ALL_PORT-macro.patch @@ -0,0 +1,316 @@ +From 393b888bd96635f5309c1e5d414986ffd4056b5f Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 14 Feb 2013 00:24:32 +0100 +Subject: sh-pfc: Add port numbers to the CPU_ALL_PORT macro + +Pass down the port number down to the PORT_1 macro. The port number will +be used to compute the pin ranges automatically. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com> +(cherry picked from commit 16b915e4389ba8f55df31b03d9de973a3d014cf7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a73a4.c | 124 +++++++++++++++++------------------ + drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 8 +-- + drivers/pinctrl/sh-pfc/pfc-sh7372.c | 14 ++-- + drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 52 +++++++-------- + drivers/pinctrl/sh-pfc/sh_pfc.h | 30 ++++----- + 5 files changed, 114 insertions(+), 114 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +index 288821b6..04ecb5e9 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +@@ -28,78 +28,78 @@ + + #define CPU_ALL_PORT(fn, pfx, sfx) \ + /* Port0 - Port30 */ \ +- PORT_10(fn, pfx, sfx), \ +- PORT_10(fn, pfx##1, sfx), \ +- PORT_10(fn, pfx##2, sfx), \ +- PORT_1(fn, pfx##30, sfx), \ ++ PORT_10(0, fn, pfx, sfx), \ ++ PORT_10(10, fn, pfx##1, sfx), \ ++ PORT_10(20, fn, pfx##2, sfx), \ ++ PORT_1(30, fn, pfx##30, sfx), \ + /* Port32 - Port40 */ \ +- PORT_1(fn, pfx##32, sfx), PORT_1(fn, pfx##33, sfx), \ +- PORT_1(fn, pfx##34, sfx), PORT_1(fn, pfx##35, sfx), \ +- PORT_1(fn, pfx##36, sfx), PORT_1(fn, pfx##37, sfx), \ +- PORT_1(fn, pfx##38, sfx), PORT_1(fn, pfx##39, sfx), \ +- PORT_1(fn, pfx##40, sfx), \ ++ PORT_1(32, fn, pfx##32, sfx), PORT_1(33, fn, pfx##33, sfx), \ ++ PORT_1(34, fn, pfx##34, sfx), PORT_1(35, fn, pfx##35, sfx), \ ++ PORT_1(36, fn, pfx##36, sfx), PORT_1(37, fn, pfx##37, sfx), \ ++ PORT_1(38, fn, pfx##38, sfx), PORT_1(39, fn, pfx##39, sfx), \ ++ PORT_1(40, fn, pfx##40, sfx), \ + /* Port64 - Port85 */ \ +- PORT_1(fn, pfx##64, sfx), PORT_1(fn, pfx##65, sfx), \ +- PORT_1(fn, pfx##66, sfx), PORT_1(fn, pfx##67, sfx), \ +- PORT_1(fn, pfx##68, sfx), PORT_1(fn, pfx##69, sfx), \ +- PORT_10(fn, pfx##7, sfx), \ +- PORT_1(fn, pfx##80, sfx), PORT_1(fn, pfx##81, sfx), \ +- PORT_1(fn, pfx##82, sfx), PORT_1(fn, pfx##83, sfx), \ +- PORT_1(fn, pfx##84, sfx), PORT_1(fn, pfx##85, sfx), \ ++ PORT_1(64, fn, pfx##64, sfx), PORT_1(65, fn, pfx##65, sfx), \ ++ PORT_1(66, fn, pfx##66, sfx), PORT_1(67, fn, pfx##67, sfx), \ ++ PORT_1(68, fn, pfx##68, sfx), PORT_1(69, fn, pfx##69, sfx), \ ++ PORT_10(70, fn, pfx##7, sfx), \ ++ PORT_1(80, fn, pfx##80, sfx), PORT_1(81, fn, pfx##81, sfx), \ ++ PORT_1(82, fn, pfx##82, sfx), PORT_1(83, fn, pfx##83, sfx), \ ++ PORT_1(84, fn, pfx##84, sfx), PORT_1(85, fn, pfx##85, sfx), \ + /* Port96 - Port126 */ \ +- PORT_1(fn, pfx##96, sfx), PORT_1(fn, pfx##97, sfx), \ +- PORT_1(fn, pfx##98, sfx), PORT_1(fn, pfx##99, sfx), \ +- PORT_10(fn, pfx##10, sfx), \ +- PORT_10(fn, pfx##11, sfx), \ +- PORT_1(fn, pfx##120, sfx), PORT_1(fn, pfx##121, sfx), \ +- PORT_1(fn, pfx##122, sfx), PORT_1(fn, pfx##123, sfx), \ +- PORT_1(fn, pfx##124, sfx), PORT_1(fn, pfx##125, sfx), \ +- PORT_1(fn, pfx##126, sfx), \ ++ PORT_1(96, fn, pfx##96, sfx), PORT_1(97, fn, pfx##97, sfx), \ ++ PORT_1(98, fn, pfx##98, sfx), PORT_1(99, fn, pfx##99, sfx), \ ++ PORT_10(100, fn, pfx##10, sfx), \ ++ PORT_10(110, fn, pfx##11, sfx), \ ++ PORT_1(120, fn, pfx##120, sfx), PORT_1(121, fn, pfx##121, sfx), \ ++ PORT_1(122, fn, pfx##122, sfx), PORT_1(123, fn, pfx##123, sfx), \ ++ PORT_1(124, fn, pfx##124, sfx), PORT_1(125, fn, pfx##125, sfx), \ ++ PORT_1(126, fn, pfx##126, sfx), \ + /* Port128 - Port134 */ \ +- PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \ +- PORT_1(fn, pfx##130, sfx), PORT_1(fn, pfx##131, sfx), \ +- PORT_1(fn, pfx##132, sfx), PORT_1(fn, pfx##133, sfx), \ +- PORT_1(fn, pfx##134, sfx), \ ++ PORT_1(128, fn, pfx##128, sfx), PORT_1(129, fn, pfx##129, sfx), \ ++ PORT_1(130, fn, pfx##130, sfx), PORT_1(131, fn, pfx##131, sfx), \ ++ PORT_1(132, fn, pfx##132, sfx), PORT_1(133, fn, pfx##133, sfx), \ ++ PORT_1(134, fn, pfx##134, sfx), \ + /* Port160 - Port178 */ \ +- PORT_10(fn, pfx##16, sfx), \ +- PORT_1(fn, pfx##170, sfx), PORT_1(fn, pfx##171, sfx), \ +- PORT_1(fn, pfx##172, sfx), PORT_1(fn, pfx##173, sfx), \ +- PORT_1(fn, pfx##174, sfx), PORT_1(fn, pfx##175, sfx), \ +- PORT_1(fn, pfx##176, sfx), PORT_1(fn, pfx##177, sfx), \ +- PORT_1(fn, pfx##178, sfx), \ ++ PORT_10(160, fn, pfx##16, sfx), \ ++ PORT_1(170, fn, pfx##170, sfx), PORT_1(171, fn, pfx##171, sfx), \ ++ PORT_1(172, fn, pfx##172, sfx), PORT_1(173, fn, pfx##173, sfx), \ ++ PORT_1(174, fn, pfx##174, sfx), PORT_1(175, fn, pfx##175, sfx), \ ++ PORT_1(176, fn, pfx##176, sfx), PORT_1(177, fn, pfx##177, sfx), \ ++ PORT_1(178, fn, pfx##178, sfx), \ + /* Port192 - Port222 */ \ +- PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \ +- PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \ +- PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \ +- PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \ +- PORT_10(fn, pfx##20, sfx), \ +- PORT_10(fn, pfx##21, sfx), \ +- PORT_1(fn, pfx##220, sfx), PORT_1(fn, pfx##221, sfx), \ +- PORT_1(fn, pfx##222, sfx), \ ++ PORT_1(192, fn, pfx##192, sfx), PORT_1(193, fn, pfx##193, sfx), \ ++ PORT_1(194, fn, pfx##194, sfx), PORT_1(195, fn, pfx##195, sfx), \ ++ PORT_1(196, fn, pfx##196, sfx), PORT_1(197, fn, pfx##197, sfx), \ ++ PORT_1(198, fn, pfx##198, sfx), PORT_1(199, fn, pfx##199, sfx), \ ++ PORT_10(200, fn, pfx##20, sfx), \ ++ PORT_10(210, fn, pfx##21, sfx), \ ++ PORT_1(220, fn, pfx##220, sfx), PORT_1(221, fn, pfx##221, sfx), \ ++ PORT_1(222, fn, pfx##222, sfx), \ + /* Port224 - Port250 */ \ +- PORT_1(fn, pfx##224, sfx), PORT_1(fn, pfx##225, sfx), \ +- PORT_1(fn, pfx##226, sfx), PORT_1(fn, pfx##227, sfx), \ +- PORT_1(fn, pfx##228, sfx), PORT_1(fn, pfx##229, sfx), \ +- PORT_10(fn, pfx##23, sfx), \ +- PORT_10(fn, pfx##24, sfx), \ +- PORT_1(fn, pfx##250, sfx), \ ++ PORT_1(224, fn, pfx##224, sfx), PORT_1(225, fn, pfx##225, sfx), \ ++ PORT_1(226, fn, pfx##226, sfx), PORT_1(227, fn, pfx##227, sfx), \ ++ PORT_1(228, fn, pfx##228, sfx), PORT_1(229, fn, pfx##229, sfx), \ ++ PORT_10(230, fn, pfx##23, sfx), \ ++ PORT_10(240, fn, pfx##24, sfx), \ ++ PORT_1(250, fn, pfx##250, sfx), \ + /* Port256 - Port283 */ \ +- PORT_1(fn, pfx##256, sfx), PORT_1(fn, pfx##257, sfx), \ +- PORT_1(fn, pfx##258, sfx), PORT_1(fn, pfx##259, sfx), \ +- PORT_10(fn, pfx##26, sfx), \ +- PORT_10(fn, pfx##27, sfx), \ +- PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx), \ +- PORT_1(fn, pfx##282, sfx), PORT_1(fn, pfx##283, sfx), \ ++ PORT_1(256, fn, pfx##256, sfx), PORT_1(257, fn, pfx##257, sfx), \ ++ PORT_1(258, fn, pfx##258, sfx), PORT_1(259, fn, pfx##259, sfx), \ ++ PORT_10(260, fn, pfx##26, sfx), \ ++ PORT_10(270, fn, pfx##27, sfx), \ ++ PORT_1(280, fn, pfx##280, sfx), PORT_1(281, fn, pfx##281, sfx), \ ++ PORT_1(282, fn, pfx##282, sfx), PORT_1(283, fn, pfx##283, sfx), \ + /* Port288 - Port308 */ \ +- PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx), \ +- PORT_10(fn, pfx##29, sfx), \ +- PORT_1(fn, pfx##300, sfx), PORT_1(fn, pfx##301, sfx), \ +- PORT_1(fn, pfx##302, sfx), PORT_1(fn, pfx##303, sfx), \ +- PORT_1(fn, pfx##304, sfx), PORT_1(fn, pfx##305, sfx), \ +- PORT_1(fn, pfx##306, sfx), PORT_1(fn, pfx##307, sfx), \ +- PORT_1(fn, pfx##308, sfx), \ ++ PORT_1(288, fn, pfx##288, sfx), PORT_1(289, fn, pfx##289, sfx), \ ++ PORT_10(290, fn, pfx##29, sfx), \ ++ PORT_1(300, fn, pfx##300, sfx), PORT_1(301, fn, pfx##301, sfx), \ ++ PORT_1(302, fn, pfx##302, sfx), PORT_1(303, fn, pfx##303, sfx), \ ++ PORT_1(304, fn, pfx##304, sfx), PORT_1(305, fn, pfx##305, sfx), \ ++ PORT_1(306, fn, pfx##306, sfx), PORT_1(307, fn, pfx##307, sfx), \ ++ PORT_1(308, fn, pfx##308, sfx), \ + /* Port320 - Port329 */ \ +- PORT_10(fn, pfx##32, sfx) ++ PORT_10(320, fn, pfx##32, sfx) + + + enum { +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +index b5bc1d09..2c745368 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +@@ -29,10 +29,10 @@ + #include "sh_pfc.h" + + #define CPU_ALL_PORT(fn, pfx, sfx) \ +- PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \ +- PORT_10(fn, pfx##10, sfx), PORT_90(fn, pfx##1, sfx), \ +- PORT_10(fn, pfx##20, sfx), \ +- PORT_1(fn, pfx##210, sfx), PORT_1(fn, pfx##211, sfx) ++ PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \ ++ PORT_10(100, fn, pfx##10, sfx), PORT_90(100, fn, pfx##1, sfx), \ ++ PORT_10(200, fn, pfx##20, sfx), \ ++ PORT_1(210, fn, pfx##210, sfx), PORT_1(211, fn, pfx##211, sfx) + + #define IRQC_PIN_MUX(irq, pin) \ + static const unsigned int intc_irq##irq##_pins[] = { \ +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +index 17f1c179..02526df3 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +@@ -30,13 +30,13 @@ + #include "core.h" + #include "sh_pfc.h" + +-#define CPU_ALL_PORT(fn, pfx, sfx) \ +- PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \ +- PORT_10(fn, pfx##10, sfx), PORT_10(fn, pfx##11, sfx), \ +- PORT_10(fn, pfx##12, sfx), PORT_10(fn, pfx##13, sfx), \ +- PORT_10(fn, pfx##14, sfx), PORT_10(fn, pfx##15, sfx), \ +- PORT_10(fn, pfx##16, sfx), PORT_10(fn, pfx##17, sfx), \ +- PORT_10(fn, pfx##18, sfx), PORT_1(fn, pfx##190, sfx) ++#define CPU_ALL_PORT(fn, pfx, sfx) \ ++ PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \ ++ PORT_10(100, fn, pfx##10, sfx), PORT_10(110, fn, pfx##11, sfx), \ ++ PORT_10(120, fn, pfx##12, sfx), PORT_10(130, fn, pfx##13, sfx), \ ++ PORT_10(140, fn, pfx##14, sfx), PORT_10(150, fn, pfx##15, sfx), \ ++ PORT_10(160, fn, pfx##16, sfx), PORT_10(170, fn, pfx##17, sfx), \ ++ PORT_10(180, fn, pfx##18, sfx), PORT_1(190, fn, pfx##190, sfx) + + #define IRQC_PIN_MUX(irq, pin) \ + static const unsigned int intc_irq##irq##_pins[] = { \ +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +index 21d2726c..918bad5f 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +@@ -31,32 +31,32 @@ + #include "core.h" + #include "sh_pfc.h" + +-#define CPU_ALL_PORT(fn, pfx, sfx) \ +- PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \ +- PORT_10(fn, pfx##10, sfx), \ +- PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx), \ +- PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx), \ +- PORT_1(fn, pfx##114, sfx), PORT_1(fn, pfx##115, sfx), \ +- PORT_1(fn, pfx##116, sfx), PORT_1(fn, pfx##117, sfx), \ +- PORT_1(fn, pfx##118, sfx), \ +- PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \ +- PORT_10(fn, pfx##13, sfx), PORT_10(fn, pfx##14, sfx), \ +- PORT_10(fn, pfx##15, sfx), \ +- PORT_1(fn, pfx##160, sfx), PORT_1(fn, pfx##161, sfx), \ +- PORT_1(fn, pfx##162, sfx), PORT_1(fn, pfx##163, sfx), \ +- PORT_1(fn, pfx##164, sfx), \ +- PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \ +- PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \ +- PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \ +- PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \ +- PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx), \ +- PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx), \ +- PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx), \ +- PORT_10(fn, pfx##26, sfx), PORT_10(fn, pfx##27, sfx), \ +- PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx), \ +- PORT_1(fn, pfx##282, sfx), \ +- PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx), \ +- PORT_10(fn, pfx##29, sfx), PORT_10(fn, pfx##30, sfx) ++#define CPU_ALL_PORT(fn, pfx, sfx) \ ++ PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \ ++ PORT_10(100, fn, pfx##10, sfx), \ ++ PORT_1(110, fn, pfx##110, sfx), PORT_1(111, fn, pfx##111, sfx), \ ++ PORT_1(112, fn, pfx##112, sfx), PORT_1(113, fn, pfx##113, sfx), \ ++ PORT_1(114, fn, pfx##114, sfx), PORT_1(115, fn, pfx##115, sfx), \ ++ PORT_1(116, fn, pfx##116, sfx), PORT_1(117, fn, pfx##117, sfx), \ ++ PORT_1(118, fn, pfx##118, sfx), \ ++ PORT_1(128, fn, pfx##128, sfx), PORT_1(129, fn, pfx##129, sfx), \ ++ PORT_10(130, fn, pfx##13, sfx), PORT_10(140, fn, pfx##14, sfx), \ ++ PORT_10(150, fn, pfx##15, sfx), \ ++ PORT_1(160, fn, pfx##160, sfx), PORT_1(161, fn, pfx##161, sfx), \ ++ PORT_1(162, fn, pfx##162, sfx), PORT_1(163, fn, pfx##163, sfx), \ ++ PORT_1(164, fn, pfx##164, sfx), \ ++ PORT_1(192, fn, pfx##192, sfx), PORT_1(193, fn, pfx##193, sfx), \ ++ PORT_1(194, fn, pfx##194, sfx), PORT_1(195, fn, pfx##195, sfx), \ ++ PORT_1(196, fn, pfx##196, sfx), PORT_1(197, fn, pfx##197, sfx), \ ++ PORT_1(198, fn, pfx##198, sfx), PORT_1(199, fn, pfx##199, sfx), \ ++ PORT_10(200, fn, pfx##20, sfx), PORT_10(210, fn, pfx##21, sfx), \ ++ PORT_10(220, fn, pfx##22, sfx), PORT_10(230, fn, pfx##23, sfx), \ ++ PORT_10(240, fn, pfx##24, sfx), PORT_10(250, fn, pfx##25, sfx), \ ++ PORT_10(260, fn, pfx##26, sfx), PORT_10(270, fn, pfx##27, sfx), \ ++ PORT_1(280, fn, pfx##280, sfx), PORT_1(281, fn, pfx##281, sfx), \ ++ PORT_1(282, fn, pfx##282, sfx), \ ++ PORT_1(288, fn, pfx##288, sfx), PORT_1(289, fn, pfx##289, sfx), \ ++ PORT_10(290, fn, pfx##29, sfx), PORT_10(300, fn, pfx##30, sfx) + + enum { + PINMUX_RESERVED = 0, +diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h +index 61205fbf..005b4822 100644 +--- a/drivers/pinctrl/sh-pfc/sh_pfc.h ++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h +@@ -229,21 +229,21 @@ struct sh_pfc_soc_info { + * PORT style (linear pin space) + */ + +-#define PORT_1(fn, pfx, sfx) fn(pfx, sfx) +- +-#define PORT_10(fn, pfx, sfx) \ +- PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \ +- PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \ +- PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \ +- PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \ +- PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx) +- +-#define PORT_90(fn, pfx, sfx) \ +- PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx), \ +- PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx), \ +- PORT_10(fn, pfx##5, sfx), PORT_10(fn, pfx##6, sfx), \ +- PORT_10(fn, pfx##7, sfx), PORT_10(fn, pfx##8, sfx), \ +- PORT_10(fn, pfx##9, sfx) ++#define PORT_1(pn, fn, pfx, sfx) fn(pfx, sfx) ++ ++#define PORT_10(pn, fn, pfx, sfx) \ ++ PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \ ++ PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \ ++ PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \ ++ PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \ ++ PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx) ++ ++#define PORT_90(pn, fn, pfx, sfx) \ ++ PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \ ++ PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \ ++ PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \ ++ PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \ ++ PORT_10(pn+90, fn, pfx##9, sfx) + + /* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */ + #define _PORT_ALL(pfx, sfx) pfx##_##sfx +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0550-sh-pfc-Pass-the-pin-number-down-to-the-port-function.patch b/patches.renesas/0550-sh-pfc-Pass-the-pin-number-down-to-the-port-function.patch new file mode 100644 index 00000000000..772dca5ac80 --- /dev/null +++ b/patches.renesas/0550-sh-pfc-Pass-the-pin-number-down-to-the-port-function.patch @@ -0,0 +1,51 @@ +From 79d84c1a1e7b1f5b66cc2e7edb394b8e3db2fac3 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 14 Feb 2013 00:41:57 +0100 +Subject: sh-pfc: Pass the pin number down to the port function macro + +The PORT_1 macro invokes a macro passed as a parameter. Pass the pin +number down to that macro at the bottom of the call stack. This will be +used to compute the pin ranges automatically. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com> +(cherry picked from commit 3ce0d7eba042b186cdf9e50f53320240ae36cf6b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/sh_pfc.h | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h +index 005b4822..596ceb7f 100644 +--- a/drivers/pinctrl/sh-pfc/sh_pfc.h ++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h +@@ -229,7 +229,7 @@ struct sh_pfc_soc_info { + * PORT style (linear pin space) + */ + +-#define PORT_1(pn, fn, pfx, sfx) fn(pfx, sfx) ++#define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx) + + #define PORT_10(pn, fn, pfx, sfx) \ + PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \ +@@ -246,7 +246,7 @@ struct sh_pfc_soc_info { + PORT_10(pn+90, fn, pfx##9, sfx) + + /* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */ +-#define _PORT_ALL(pfx, sfx) pfx##_##sfx ++#define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx + #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str) + + /* PINMUX_GPIO - Expand to a sh_pfc_pin entry */ +@@ -267,7 +267,7 @@ struct sh_pfc_soc_info { + /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0, + * PORT_name_OUT, PORT_name_IN marks + */ +-#define _PORT_DATA(pfx, sfx) \ ++#define _PORT_DATA(pn, pfx, sfx) \ + PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \ + PORT##pfx##_OUT, PORT##pfx##_IN) + #define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0551-sh-pfc-Add-pin-number-to-struct-sh_pfc_pin.patch b/patches.renesas/0551-sh-pfc-Add-pin-number-to-struct-sh_pfc_pin.patch new file mode 100644 index 00000000000..cbc4eb8911b --- /dev/null +++ b/patches.renesas/0551-sh-pfc-Add-pin-number-to-struct-sh_pfc_pin.patch @@ -0,0 +1,69 @@ +From f3067c4516c2bb946af95508be928b0fadb5b676 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 14 Feb 2013 00:59:49 +0100 +Subject: sh-pfc: Add pin number to struct sh_pfc_pin + +The pin number is usually equal to the GPIO number but can differ when +GPIO numbering is sparse. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com> +(cherry picked from commit 9689896cb106bf756ec3616beaeb57da6e39a6a0) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/sh_pfc.h | 20 ++++++++++++-------- + 1 file changed, 12 insertions(+), 8 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h +index 596ceb7f..839e6954 100644 +--- a/drivers/pinctrl/sh-pfc/sh_pfc.h ++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h +@@ -28,6 +28,7 @@ enum { + #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3) + + struct sh_pfc_pin { ++ u16 pin; + u16 enum_id; + const char *name; + unsigned int configs; +@@ -214,8 +215,9 @@ struct sh_pfc_soc_info { + #define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str) + + /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */ +-#define _GP_GPIO(bank, pin, _name, sfx) \ +- [(bank * 32) + pin] = { \ ++#define _GP_GPIO(bank, _pin, _name, sfx) \ ++ [(bank * 32) + _pin] = { \ ++ .pin = (bank * 32) + _pin, \ + .name = __stringify(_name), \ + .enum_id = _name##_DATA, \ + } +@@ -250,17 +252,19 @@ struct sh_pfc_soc_info { + #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str) + + /* PINMUX_GPIO - Expand to a sh_pfc_pin entry */ +-#define PINMUX_GPIO(pin) \ +- [GPIO_##pin] = { \ ++#define PINMUX_GPIO(_pin) \ ++ [GPIO_##_pin] = { \ ++ .pin = (u16)-1, \ + .name = __stringify(name), \ +- .enum_id = pin##_DATA, \ ++ .enum_id = _pin##_DATA, \ + } + + /* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */ +-#define SH_PFC_PIN_CFG(pin, cfgs) \ ++#define SH_PFC_PIN_CFG(_pin, cfgs) \ + { \ +- .name = __stringify(PORT##pin), \ +- .enum_id = PORT##pin##_DATA, \ ++ .pin = _pin, \ ++ .name = __stringify(PORT##_pin), \ ++ .enum_id = PORT##_pin##_DATA, \ + .configs = cfgs, \ + } + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0552-sh-pfc-Rename-struct-sh_pfc-nr_pins-field-to-nr_gpio.patch b/patches.renesas/0552-sh-pfc-Rename-struct-sh_pfc-nr_pins-field-to-nr_gpio.patch new file mode 100644 index 00000000000..9d33d0feb5e --- /dev/null +++ b/patches.renesas/0552-sh-pfc-Rename-struct-sh_pfc-nr_pins-field-to-nr_gpio.patch @@ -0,0 +1,71 @@ +From 05219fc0af04f8f2874eaa3f1343230a4b9c27aa Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 15 Jul 2013 13:48:56 +0200 +Subject: sh-pfc: Rename struct sh_pfc nr_pins field to nr_gpio_pins + +The field contains the number of pins with an associated GPIO port. This +is currently equal to the total number of pins but will be modified when +adding support for pins without a GPIO port. Rename the field +accordingly. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com> +(cherry picked from commit 28818fa5dadfd458fa7e17c8be26b2d7edffa8bf) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/core.h | 2 +- + drivers/pinctrl/sh-pfc/gpio.c | 4 ++-- + drivers/pinctrl/sh-pfc/pinctrl.c | 2 +- + 3 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h +index f02ba1dd..93963a19 100644 +--- a/drivers/pinctrl/sh-pfc/core.h ++++ b/drivers/pinctrl/sh-pfc/core.h +@@ -34,7 +34,7 @@ struct sh_pfc { + unsigned int num_windows; + struct sh_pfc_window *window; + +- unsigned int nr_pins; ++ unsigned int nr_gpio_pins; + + struct sh_pfc_chip *gpio; + struct sh_pfc_chip *func; +diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c +index 87ae38b9..7661be50 100644 +--- a/drivers/pinctrl/sh-pfc/gpio.c ++++ b/drivers/pinctrl/sh-pfc/gpio.c +@@ -245,7 +245,7 @@ static int gpio_pin_setup(struct sh_pfc_chip *chip) + gc->dev = pfc->dev; + gc->owner = THIS_MODULE; + gc->base = 0; +- gc->ngpio = pfc->nr_pins; ++ gc->ngpio = pfc->nr_gpio_pins; + + return 0; + } +@@ -293,7 +293,7 @@ static int gpio_function_setup(struct sh_pfc_chip *chip) + + gc->label = pfc->info->name; + gc->owner = THIS_MODULE; +- gc->base = pfc->nr_pins; ++ gc->base = pfc->nr_gpio_pins; + gc->ngpio = pfc->info->nr_func_gpios; + + return 0; +diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c +index bc8b028b..314255d7 100644 +--- a/drivers/pinctrl/sh-pfc/pinctrl.c ++++ b/drivers/pinctrl/sh-pfc/pinctrl.c +@@ -632,7 +632,7 @@ static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) + } + } + +- pfc->nr_pins = ranges[nr_ranges-1].end + 1; ++ pfc->nr_gpio_pins = ranges[nr_ranges-1].end + 1; + + return nr_ranges; + } +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0553-sh-pfc-Compute-pin-ranges-automatically.patch b/patches.renesas/0553-sh-pfc-Compute-pin-ranges-automatically.patch new file mode 100644 index 00000000000..fdb7d49a57c --- /dev/null +++ b/patches.renesas/0553-sh-pfc-Compute-pin-ranges-automatically.patch @@ -0,0 +1,352 @@ +From 76f65da95b5d72b75cd55d4d8f5d0638a793aadf Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 15 Jul 2013 18:38:30 +0200 +Subject: sh-pfc: Compute pin ranges automatically + +Remove the manually specified ranges from PFC SoC data and compute the +ranges automatically. This prevents ranges from being out-of-sync with +pins definitions. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com> +(cherry picked from commit acac8ed5e2aa2c0d364d06f364fd9ed0dc27d28a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/core.c | 70 +++++++++++++++++++++++++++++++----- + drivers/pinctrl/sh-pfc/core.h | 8 +++++ + drivers/pinctrl/sh-pfc/gpio.c | 21 +++-------- + drivers/pinctrl/sh-pfc/pfc-r8a73a4.c | 17 --------- + drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 9 ----- + drivers/pinctrl/sh-pfc/pinctrl.c | 49 ++++++++----------------- + drivers/pinctrl/sh-pfc/sh_pfc.h | 2 -- + 7 files changed, 88 insertions(+), 88 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c +index 96b02246..cb47bcee 100644 +--- a/drivers/pinctrl/sh-pfc/core.c ++++ b/drivers/pinctrl/sh-pfc/core.c +@@ -82,17 +82,14 @@ int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin) + unsigned int offset; + unsigned int i; + +- if (pfc->info->ranges == NULL) +- return pin; +- +- for (i = 0, offset = 0; i < pfc->info->nr_ranges; ++i) { +- const struct pinmux_range *range = &pfc->info->ranges[i]; ++ for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) { ++ const struct sh_pfc_pin_range *range = &pfc->ranges[i]; + + if (pin <= range->end) +- return pin >= range->begin +- ? offset + pin - range->begin : -1; ++ return pin >= range->start ++ ? offset + pin - range->start : -1; + +- offset += range->end - range->begin + 1; ++ offset += range->end - range->start + 1; + } + + return -EINVAL; +@@ -341,6 +338,59 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) + return 0; + } + ++static int sh_pfc_init_ranges(struct sh_pfc *pfc) ++{ ++ struct sh_pfc_pin_range *range; ++ unsigned int nr_ranges; ++ unsigned int i; ++ ++ if (pfc->info->pins[0].pin == (u16)-1) { ++ /* Pin number -1 denotes that the SoC doesn't report pin numbers ++ * in its pin arrays yet. Consider the pin numbers range as ++ * continuous and allocate a single range. ++ */ ++ pfc->nr_ranges = 1; ++ pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges), ++ GFP_KERNEL); ++ if (pfc->ranges == NULL) ++ return -ENOMEM; ++ ++ pfc->ranges->start = 0; ++ pfc->ranges->end = pfc->info->nr_pins - 1; ++ pfc->nr_gpio_pins = pfc->info->nr_pins; ++ ++ return 0; ++ } ++ ++ /* Count, allocate and fill the ranges. */ ++ for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) { ++ if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1) ++ nr_ranges++; ++ } ++ ++ pfc->nr_ranges = nr_ranges; ++ pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges) * nr_ranges, ++ GFP_KERNEL); ++ if (pfc->ranges == NULL) ++ return -ENOMEM; ++ ++ range = pfc->ranges; ++ range->start = pfc->info->pins[0].pin; ++ ++ for (i = 1; i < pfc->info->nr_pins; ++i) { ++ if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1) { ++ range->end = pfc->info->pins[i-1].pin; ++ range++; ++ range->start = pfc->info->pins[i].pin; ++ } ++ } ++ ++ range->end = pfc->info->pins[i-1].pin; ++ pfc->nr_gpio_pins = range->end + 1; ++ ++ return 0; ++} ++ + #ifdef CONFIG_OF + static const struct of_device_id sh_pfc_of_table[] = { + #ifdef CONFIG_PINCTRL_PFC_R8A73A4 +@@ -431,6 +481,10 @@ static int sh_pfc_probe(struct platform_device *pdev) + + pinctrl_provide_dummies(); + ++ ret = sh_pfc_init_ranges(pfc); ++ if (ret < 0) ++ return ret; ++ + /* + * Initialize pinctrl bindings first + */ +diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h +index 93963a19..a1b23762 100644 +--- a/drivers/pinctrl/sh-pfc/core.h ++++ b/drivers/pinctrl/sh-pfc/core.h +@@ -25,6 +25,11 @@ struct sh_pfc_window { + struct sh_pfc_chip; + struct sh_pfc_pinctrl; + ++struct sh_pfc_pin_range { ++ u16 start; ++ u16 end; ++}; ++ + struct sh_pfc { + struct device *dev; + const struct sh_pfc_soc_info *info; +@@ -34,6 +39,9 @@ struct sh_pfc { + unsigned int num_windows; + struct sh_pfc_window *window; + ++ struct sh_pfc_pin_range *ranges; ++ unsigned int nr_ranges; ++ + unsigned int nr_gpio_pins; + + struct sh_pfc_chip *gpio; +diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c +index 7661be50..78fcb802 100644 +--- a/drivers/pinctrl/sh-pfc/gpio.c ++++ b/drivers/pinctrl/sh-pfc/gpio.c +@@ -334,10 +334,7 @@ sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *), + + int sh_pfc_register_gpiochip(struct sh_pfc *pfc) + { +- const struct pinmux_range *ranges; +- struct pinmux_range def_range; + struct sh_pfc_chip *chip; +- unsigned int nr_ranges; + unsigned int i; + int ret; + +@@ -368,23 +365,13 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc) + pfc->gpio = chip; + + /* Register the GPIO to pin mappings. */ +- if (pfc->info->ranges == NULL) { +- def_range.begin = 0; +- def_range.end = pfc->info->nr_pins - 1; +- ranges = &def_range; +- nr_ranges = 1; +- } else { +- ranges = pfc->info->ranges; +- nr_ranges = pfc->info->nr_ranges; +- } +- +- for (i = 0; i < nr_ranges; ++i) { +- const struct pinmux_range *range = &ranges[i]; ++ for (i = 0; i < pfc->nr_ranges; ++i) { ++ const struct sh_pfc_pin_range *range = &pfc->ranges[i]; + + ret = gpiochip_add_pin_range(&chip->gpio_chip, + dev_name(pfc->dev), +- range->begin, range->begin, +- range->end - range->begin + 1); ++ range->start, range->start, ++ range->end - range->start + 1); + if (ret < 0) + return ret; + } +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +index 04ecb5e9..05d96ae3 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +@@ -1398,20 +1398,6 @@ static struct sh_pfc_pin pinmux_pins[] = { + R8A73A4_PIN_IO_PU_PD(328), R8A73A4_PIN_IO_PU_PD(329), + }; + +-static const struct pinmux_range pinmux_ranges[] = { +- {.begin = 0, .end = 30,}, +- {.begin = 32, .end = 40,}, +- {.begin = 64, .end = 85,}, +- {.begin = 96, .end = 126,}, +- {.begin = 128, .end = 134,}, +- {.begin = 160, .end = 178,}, +- {.begin = 192, .end = 222,}, +- {.begin = 224, .end = 250,}, +- {.begin = 256, .end = 283,}, +- {.begin = 288, .end = 308,}, +- {.begin = 320, .end = 329,}, +-}; +- + /* - IRQC ------------------------------------------------------------------- */ + #define IRQC_PINS_MUX(pin, irq_mark) \ + static const unsigned int irqc_irq##irq_mark##_pins[] = { \ +@@ -2756,9 +2742,6 @@ const struct sh_pfc_soc_info r8a73a4_pinmux_info = { + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + +- .ranges = pinmux_ranges, +- .nr_ranges = ARRAY_SIZE(pinmux_ranges), +- + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +index 918bad5f..6a26946d 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +@@ -1446,13 +1446,6 @@ static struct sh_pfc_pin pinmux_pins[] = { + SH73A0_PIN_O(309), + }; + +-static const struct pinmux_range pinmux_ranges[] = { +- {.begin = 0, .end = 118,}, +- {.begin = 128, .end = 164,}, +- {.begin = 192, .end = 282,}, +- {.begin = 288, .end = 309,}, +-}; +- + /* Pin numbers for pins without a corresponding GPIO port number are computed + * from the row and column numbers with a 1000 offset to avoid collisions with + * GPIO port numbers. +@@ -3895,8 +3888,6 @@ const struct sh_pfc_soc_info sh73a0_pinmux_info = { + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), +- .ranges = pinmux_ranges, +- .nr_ranges = ARRAY_SIZE(pinmux_ranges), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, +diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c +index 314255d7..8649ec39 100644 +--- a/drivers/pinctrl/sh-pfc/pinctrl.c ++++ b/drivers/pinctrl/sh-pfc/pinctrl.c +@@ -587,22 +587,9 @@ static const struct pinconf_ops sh_pfc_pinconf_ops = { + /* PFC ranges -> pinctrl pin descs */ + static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) + { +- const struct pinmux_range *ranges; +- struct pinmux_range def_range; +- unsigned int nr_ranges; +- unsigned int nr_pins; + unsigned int i; + +- if (pfc->info->ranges == NULL) { +- def_range.begin = 0; +- def_range.end = pfc->info->nr_pins - 1; +- ranges = &def_range; +- nr_ranges = 1; +- } else { +- ranges = pfc->info->ranges; +- nr_ranges = pfc->info->nr_ranges; +- } +- ++ /* Allocate and initialize the pins and configs arrays. */ + pmx->pins = devm_kzalloc(pfc->dev, + sizeof(*pmx->pins) * pfc->info->nr_pins, + GFP_KERNEL); +@@ -615,32 +602,24 @@ static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) + if (unlikely(!pmx->configs)) + return -ENOMEM; + +- for (i = 0, nr_pins = 0; i < nr_ranges; ++i) { +- const struct pinmux_range *range = &ranges[i]; +- unsigned int number; ++ for (i = 0; i < pfc->info->nr_pins; ++i) { ++ const struct sh_pfc_pin *info = &pfc->info->pins[i]; ++ struct sh_pfc_pin_config *cfg = &pmx->configs[i]; ++ struct pinctrl_pin_desc *pin = &pmx->pins[i]; + +- for (number = range->begin; number <= range->end; +- number++, nr_pins++) { +- struct sh_pfc_pin_config *cfg = &pmx->configs[nr_pins]; +- struct pinctrl_pin_desc *pin = &pmx->pins[nr_pins]; +- const struct sh_pfc_pin *info = +- &pfc->info->pins[nr_pins]; +- +- pin->number = number; +- pin->name = info->name; +- cfg->type = PINMUX_TYPE_NONE; +- } ++ /* If the pin number is equal to -1 all pins are considered */ ++ pin->number = info->pin != (u16)-1 ? info->pin : i; ++ pin->name = info->name; ++ cfg->type = PINMUX_TYPE_NONE; + } + +- pfc->nr_gpio_pins = ranges[nr_ranges-1].end + 1; +- +- return nr_ranges; ++ return 0; + } + + int sh_pfc_register_pinctrl(struct sh_pfc *pfc) + { + struct sh_pfc_pinctrl *pmx; +- int nr_ranges; ++ int ret; + + pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL); + if (unlikely(!pmx)) +@@ -649,9 +628,9 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc) + pmx->pfc = pfc; + pfc->pinctrl = pmx; + +- nr_ranges = sh_pfc_map_pins(pfc, pmx); +- if (unlikely(nr_ranges < 0)) +- return nr_ranges; ++ ret = sh_pfc_map_pins(pfc, pmx); ++ if (ret < 0) ++ return ret; + + pmx->pctl_desc.name = DRV_NAME; + pmx->pctl_desc.owner = THIS_MODULE; +diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h +index 839e6954..2469b35c 100644 +--- a/drivers/pinctrl/sh-pfc/sh_pfc.h ++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h +@@ -125,8 +125,6 @@ struct sh_pfc_soc_info { + + const struct sh_pfc_pin *pins; + unsigned int nr_pins; +- const struct pinmux_range *ranges; +- unsigned int nr_ranges; + const struct sh_pfc_pin_group *groups; + unsigned int nr_groups; + const struct sh_pfc_function *functions; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0554-sh-pfc-Support-pins-not-associated-with-a-GPIO-port.patch b/patches.renesas/0554-sh-pfc-Support-pins-not-associated-with-a-GPIO-port.patch new file mode 100644 index 00000000000..0d6fd168463 --- /dev/null +++ b/patches.renesas/0554-sh-pfc-Support-pins-not-associated-with-a-GPIO-port.patch @@ -0,0 +1,184 @@ +From 16933164311228f10beb90ba453461e9c292a112 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 15 Jul 2013 21:10:54 +0200 +Subject: sh-pfc: Support pins not associated with a GPIO port + +Pins with selectable functions but without a GPIO port can't be named +PORT_# or GP_#_#. Add a SH_PFC_PIN_NAMED macro to declare such pins in +the pinmux pins array, naming them with the PIN_ prefix followed by the +pin physical position. + +In order to make sure not to register those pins as GPIOs, add a +SH_PFC_PIN_CFG_NO_GPIO pin flag to denote pins without a GPIO port. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com> +(cherry picked from commit 4f82e3ee724f1712f9e84b8802e24ea096a6089f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/core.c | 22 +++++++++++++++------- + drivers/pinctrl/sh-pfc/gpio.c | 8 +++++++- + drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 13 +++++++++---- + drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 15 +++++++++------ + drivers/pinctrl/sh-pfc/sh_pfc.h | 9 +++++++++ + 5 files changed, 49 insertions(+), 18 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c +index cb47bcee..9e66614b 100644 +--- a/drivers/pinctrl/sh-pfc/core.c ++++ b/drivers/pinctrl/sh-pfc/core.c +@@ -362,7 +362,10 @@ static int sh_pfc_init_ranges(struct sh_pfc *pfc) + return 0; + } + +- /* Count, allocate and fill the ranges. */ ++ /* Count, allocate and fill the ranges. The PFC SoC data pins array must ++ * be sorted by pin numbers, and pins without a GPIO port must come ++ * last. ++ */ + for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) { + if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1) + nr_ranges++; +@@ -378,15 +381,20 @@ static int sh_pfc_init_ranges(struct sh_pfc *pfc) + range->start = pfc->info->pins[0].pin; + + for (i = 1; i < pfc->info->nr_pins; ++i) { +- if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1) { +- range->end = pfc->info->pins[i-1].pin; +- range++; +- range->start = pfc->info->pins[i].pin; +- } ++ if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1) ++ continue; ++ ++ range->end = pfc->info->pins[i-1].pin; ++ if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO)) ++ pfc->nr_gpio_pins = range->end + 1; ++ ++ range++; ++ range->start = pfc->info->pins[i].pin; + } + + range->end = pfc->info->pins[i-1].pin; +- pfc->nr_gpio_pins = range->end + 1; ++ if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO)) ++ pfc->nr_gpio_pins = range->end + 1; + + return 0; + } +diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c +index 78fcb802..04bf52b6 100644 +--- a/drivers/pinctrl/sh-pfc/gpio.c ++++ b/drivers/pinctrl/sh-pfc/gpio.c +@@ -364,10 +364,16 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc) + + pfc->gpio = chip; + +- /* Register the GPIO to pin mappings. */ ++ /* Register the GPIO to pin mappings. As pins with GPIO ports must come ++ * first in the ranges, skip the pins without GPIO ports by stopping at ++ * the first range that contains such a pin. ++ */ + for (i = 0; i < pfc->nr_ranges; ++i) { + const struct sh_pfc_pin_range *range = &pfc->ranges[i]; + ++ if (range->start >= pfc->nr_gpio_pins) ++ break; ++ + ret = gpiochip_add_pin_range(&chip->gpio_chip, + dev_name(pfc->dev), + range->start, range->start, +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +index 40aecfee..428d2a68 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +@@ -1254,16 +1254,21 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MSEL(IP10_24_22, CAN_CLK_C, SEL_CANCLK_C), + }; + +-static struct sh_pfc_pin pinmux_pins[] = { +- PINMUX_GPIO_GP_ALL(), +-}; +- + /* Pin numbers for pins without a corresponding GPIO port number are computed + * from the row and column numbers with a 1000 offset to avoid collisions with + * GPIO port numbers. + */ + #define PIN_NUMBER(row, col) (1000+((row)-1)*25+(col)-1) + ++static struct sh_pfc_pin pinmux_pins[] = { ++ PINMUX_GPIO_GP_ALL(), ++ ++ /* Pins not associated with a GPIO port */ ++ SH_PFC_PIN_NAMED(3, 20, C20), ++ SH_PFC_PIN_NAMED(20, 1, T1), ++ SH_PFC_PIN_NAMED(25, 2, Y2), ++}; ++ + /* - macro */ + #define SH_PFC_PINS(name, args...) \ + static const unsigned int name ##_pins[] = { args } +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +index 6a26946d..9a42c52b 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +@@ -1173,6 +1173,12 @@ static const u16 pinmux_data[] = { + #define SH73A0_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD) + #define SH73A0_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O) + ++/* Pin numbers for pins without a corresponding GPIO port number are computed ++ * from the row and column numbers with a 1000 offset to avoid collisions with ++ * GPIO port numbers. ++ */ ++#define PIN_NUMBER(row, col) (1000+((row)-1)*34+(col)-1) ++ + static struct sh_pfc_pin pinmux_pins[] = { + /* Table 25-1 (I/O and Pull U/D) */ + SH73A0_PIN_I_PD(0), +@@ -1444,13 +1450,10 @@ static struct sh_pfc_pin pinmux_pins[] = { + SH73A0_PIN_O(307), + SH73A0_PIN_I_PU(308), + SH73A0_PIN_O(309), +-}; + +-/* Pin numbers for pins without a corresponding GPIO port number are computed +- * from the row and column numbers with a 1000 offset to avoid collisions with +- * GPIO port numbers. +- */ +-#define PIN_NUMBER(row, col) (1000+((row)-1)*34+(col)-1) ++ /* Pins not associated with a GPIO port */ ++ SH_PFC_PIN_NAMED(6, 26, F26), ++}; + + /* - BSC -------------------------------------------------------------------- */ + static const unsigned int bsc_data_0_7_pins[] = { +diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h +index 2469b35c..11bd0d97 100644 +--- a/drivers/pinctrl/sh-pfc/sh_pfc.h ++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h +@@ -26,6 +26,7 @@ enum { + #define SH_PFC_PIN_CFG_OUTPUT (1 << 1) + #define SH_PFC_PIN_CFG_PULL_UP (1 << 2) + #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3) ++#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31) + + struct sh_pfc_pin { + u16 pin; +@@ -266,6 +267,14 @@ struct sh_pfc_soc_info { + .configs = cfgs, \ + } + ++/* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */ ++#define SH_PFC_PIN_NAMED(row, col, _name) \ ++ { \ ++ .pin = PIN_NUMBER(row, col), \ ++ .name = __stringify(PIN_##_name), \ ++ .configs = SH_PFC_PIN_CFG_NO_GPIO, \ ++ } ++ + /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0, + * PORT_name_OUT, PORT_name_IN marks + */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0555-sh-pfc-Remove-unneeded-mach-soc-.h-includes.patch b/patches.renesas/0555-sh-pfc-Remove-unneeded-mach-soc-.h-includes.patch new file mode 100644 index 00000000000..6ab52f23e4a --- /dev/null +++ b/patches.renesas/0555-sh-pfc-Remove-unneeded-mach-soc-.h-includes.patch @@ -0,0 +1,57 @@ +From 75814d9432685c805f60b915fb7bde2fd45e0e1d Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 23 Jul 2013 23:08:10 +0200 +Subject: sh-pfc: Remove unneeded mach/<soc>.h includes + +The SoC-specific mach/<soc>.h headers are included needlesly. Don't +include them. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Acked-by: Magnus Damm <damm@opensource.se> +(cherry picked from commit e7004440907cc4c6130f23920a694fce2625acc9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a73a4.c | 1 - + drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 1 - + drivers/pinctrl/sh-pfc/pfc-sh7372.c | 1 - + 3 files changed, 3 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +index 05d96ae3..d25fd4ea 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +@@ -21,7 +21,6 @@ + #include <linux/kernel.h> + #include <linux/pinctrl/pinconf-generic.h> + #include <mach/irqs.h> +-#include <mach/r8a73a4.h> + + #include "core.h" + #include "sh_pfc.h" +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +index 2c745368..009174d0 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +@@ -22,7 +22,6 @@ + #include <linux/kernel.h> + #include <linux/pinctrl/pinconf-generic.h> + +-#include <mach/r8a7740.h> + #include <mach/irqs.h> + + #include "core.h" +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +index 02526df3..d546c478 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +@@ -25,7 +25,6 @@ + #include <linux/pinctrl/pinconf-generic.h> + + #include <mach/irqs.h> +-#include <mach/sh7372.h> + + #include "core.h" + #include "sh_pfc.h" +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0556-sh-pfc-sh7372-Replace-mach-irqs.h-with-linux-sh_intc.patch b/patches.renesas/0556-sh-pfc-sh7372-Replace-mach-irqs.h-with-linux-sh_intc.patch new file mode 100644 index 00000000000..95ebd27775e --- /dev/null +++ b/patches.renesas/0556-sh-pfc-sh7372-Replace-mach-irqs.h-with-linux-sh_intc.patch @@ -0,0 +1,34 @@ +From 9fa283265f0c45f5c99253e9698ac77fef3bd403 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Wed, 24 Jul 2013 00:25:16 +0200 +Subject: sh-pfc: sh7372: Replace <mach/irqs.h> with <linux/sh_intc.h> + +The mach/irqs.h header is included only to get the evt2irq macro +definition. The macro is defined in linux/sh_intc.h, include it directly +instead of the mach-specific header. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Acked-by: Magnus Damm <damm@opensource.se> +(cherry picked from commit f3dcc9ffadea53e355e7d94cf9930898fc6a4b67) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-sh7372.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +index d546c478..70b522d3 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c +@@ -23,8 +23,7 @@ + #include <linux/io.h> + #include <linux/kernel.h> + #include <linux/pinctrl/pinconf-generic.h> +- +-#include <mach/irqs.h> ++#include <linux/sh_intc.h> + + #include "core.h" + #include "sh_pfc.h" +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0557-sh-pfc-sh73a0-Remove-EXT_IRQ16L-and-EXT_IRQ16H-macro.patch b/patches.renesas/0557-sh-pfc-sh73a0-Remove-EXT_IRQ16L-and-EXT_IRQ16H-macro.patch new file mode 100644 index 00000000000..4ee576e069a --- /dev/null +++ b/patches.renesas/0557-sh-pfc-sh73a0-Remove-EXT_IRQ16L-and-EXT_IRQ16H-macro.patch @@ -0,0 +1,99 @@ +From 500c6fc974eb3f9521f00fc67f45f93609548445 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Wed, 24 Jul 2013 01:24:15 +0200 +Subject: sh-pfc: sh73a0: Remove EXT_IRQ16L and EXT_IRQ16H macros + +The macros expand to irq_pin() calls and where most probably introduced +from a copy&paste of the sh7372 PFC data. Replace them with irq_pin(). + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Acked-by: Magnus Damm <damm@opensource.se> +(cherry picked from commit deeb6d3f1fce7e2269462eaa7cfe1ea426857d89) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 68 +++++++++++++++++-------------------- + 1 file changed, 32 insertions(+), 36 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +index 9a42c52b..7e278a97 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c ++++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +@@ -3660,43 +3660,39 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { + { }, + }; + +-/* External IRQ pins mapped at IRQPIN_BASE */ +-#define EXT_IRQ16L(n) irq_pin(n) +-#define EXT_IRQ16H(n) irq_pin(n) +- + static const struct pinmux_irq pinmux_irqs[] = { +- PINMUX_IRQ(EXT_IRQ16H(19), 9), +- PINMUX_IRQ(EXT_IRQ16L(1), 10), +- PINMUX_IRQ(EXT_IRQ16L(0), 11), +- PINMUX_IRQ(EXT_IRQ16H(18), 13), +- PINMUX_IRQ(EXT_IRQ16H(20), 14), +- PINMUX_IRQ(EXT_IRQ16H(21), 15), +- PINMUX_IRQ(EXT_IRQ16H(31), 26), +- PINMUX_IRQ(EXT_IRQ16H(30), 27), +- PINMUX_IRQ(EXT_IRQ16H(29), 28), +- PINMUX_IRQ(EXT_IRQ16H(22), 40), +- PINMUX_IRQ(EXT_IRQ16H(23), 53), +- PINMUX_IRQ(EXT_IRQ16L(10), 54), +- PINMUX_IRQ(EXT_IRQ16L(9), 56), +- PINMUX_IRQ(EXT_IRQ16H(26), 115), +- PINMUX_IRQ(EXT_IRQ16H(27), 116), +- PINMUX_IRQ(EXT_IRQ16H(28), 117), +- PINMUX_IRQ(EXT_IRQ16H(24), 118), +- PINMUX_IRQ(EXT_IRQ16L(6), 147), +- PINMUX_IRQ(EXT_IRQ16L(2), 149), +- PINMUX_IRQ(EXT_IRQ16L(7), 150), +- PINMUX_IRQ(EXT_IRQ16L(12), 156), +- PINMUX_IRQ(EXT_IRQ16L(4), 159), +- PINMUX_IRQ(EXT_IRQ16H(25), 164), +- PINMUX_IRQ(EXT_IRQ16L(8), 223), +- PINMUX_IRQ(EXT_IRQ16L(3), 224), +- PINMUX_IRQ(EXT_IRQ16L(5), 227), +- PINMUX_IRQ(EXT_IRQ16H(17), 234), +- PINMUX_IRQ(EXT_IRQ16L(11), 238), +- PINMUX_IRQ(EXT_IRQ16L(13), 239), +- PINMUX_IRQ(EXT_IRQ16H(16), 249), +- PINMUX_IRQ(EXT_IRQ16L(14), 251), +- PINMUX_IRQ(EXT_IRQ16L(9), 308), ++ PINMUX_IRQ(irq_pin(19), 9), ++ PINMUX_IRQ(irq_pin(1), 10), ++ PINMUX_IRQ(irq_pin(0), 11), ++ PINMUX_IRQ(irq_pin(18), 13), ++ PINMUX_IRQ(irq_pin(20), 14), ++ PINMUX_IRQ(irq_pin(21), 15), ++ PINMUX_IRQ(irq_pin(31), 26), ++ PINMUX_IRQ(irq_pin(30), 27), ++ PINMUX_IRQ(irq_pin(29), 28), ++ PINMUX_IRQ(irq_pin(22), 40), ++ PINMUX_IRQ(irq_pin(23), 53), ++ PINMUX_IRQ(irq_pin(10), 54), ++ PINMUX_IRQ(irq_pin(9), 56), ++ PINMUX_IRQ(irq_pin(26), 115), ++ PINMUX_IRQ(irq_pin(27), 116), ++ PINMUX_IRQ(irq_pin(28), 117), ++ PINMUX_IRQ(irq_pin(24), 118), ++ PINMUX_IRQ(irq_pin(6), 147), ++ PINMUX_IRQ(irq_pin(2), 149), ++ PINMUX_IRQ(irq_pin(7), 150), ++ PINMUX_IRQ(irq_pin(12), 156), ++ PINMUX_IRQ(irq_pin(4), 159), ++ PINMUX_IRQ(irq_pin(25), 164), ++ PINMUX_IRQ(irq_pin(8), 223), ++ PINMUX_IRQ(irq_pin(3), 224), ++ PINMUX_IRQ(irq_pin(5), 227), ++ PINMUX_IRQ(irq_pin(17), 234), ++ PINMUX_IRQ(irq_pin(11), 238), ++ PINMUX_IRQ(irq_pin(13), 239), ++ PINMUX_IRQ(irq_pin(16), 249), ++ PINMUX_IRQ(irq_pin(14), 251), ++ PINMUX_IRQ(irq_pin(9), 308), + }; + + /* ----------------------------------------------------------------------------- +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0558-sh-pfc-r8a7779-Add-I2C-pin-groups.patch b/patches.renesas/0558-sh-pfc-r8a7779-Add-I2C-pin-groups.patch new file mode 100644 index 00000000000..817dd5cbbc8 --- /dev/null +++ b/patches.renesas/0558-sh-pfc-r8a7779-Add-I2C-pin-groups.patch @@ -0,0 +1,155 @@ +From 3c60160b7123ea36e676a12f49deda44566f8632 Mon Sep 17 00:00:00 2001 +From: Phil Edworthy <phil.edworthy@renesas.com> +Date: Wed, 17 Jul 2013 12:00:48 +0100 +Subject: sh-pfc: r8a7779: Add I2C pin groups + +Add all I2C pin groups to R8A7779 PFC driver. + +Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit 528e94773907b86adfd778019a9b7d35a7ab431e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 105 +++++++++++++++++++++++++++++++++++ + 1 file changed, 105 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +index be832dcd..d3e94e30 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +@@ -1674,6 +1674,79 @@ static const unsigned int hspi2_b_pins[] = { + static const unsigned int hspi2_b_mux[] = { + HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK, + }; ++/* - I2C1 ------------------------------------------------------------------ */ ++static const unsigned int i2c1_pins[] = { ++ /* SCL, SDA, */ ++ RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), ++}; ++static const unsigned int i2c1_mux[] = { ++ SCL1_MARK, SDA1_MARK, ++}; ++static const unsigned int i2c1_b_pins[] = { ++ /* SCL, SDA, */ ++ RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11), ++}; ++static const unsigned int i2c1_b_mux[] = { ++ SCL1_B_MARK, SDA1_B_MARK, ++}; ++static const unsigned int i2c1_c_pins[] = { ++ /* SCL, SDA, */ ++ RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), ++}; ++static const unsigned int i2c1_c_mux[] = { ++ SCL1_C_MARK, SDA1_C_MARK, ++}; ++static const unsigned int i2c1_d_pins[] = { ++ /* SCL, SDA, */ ++ RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27), ++}; ++static const unsigned int i2c1_d_mux[] = { ++ SCL1_D_MARK, SDA1_D_MARK, ++}; ++/* - I2C2 ------------------------------------------------------------------ */ ++static const unsigned int i2c2_pins[] = { ++ /* SCL, SDA, */ ++ RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 26), ++}; ++static const unsigned int i2c2_mux[] = { ++ SCL2_MARK, SDA2_MARK, ++}; ++static const unsigned int i2c2_b_pins[] = { ++ /* SCL, SDA, */ ++ RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), ++}; ++static const unsigned int i2c2_b_mux[] = { ++ SCL2_B_MARK, SDA2_B_MARK, ++}; ++static const unsigned int i2c2_c_pins[] = { ++ /* SCL, SDA */ ++ RCAR_GP_PIN(0, 31), RCAR_GP_PIN(0, 30), ++}; ++static const unsigned int i2c2_c_mux[] = { ++ SCL2_C_MARK, SDA2_C_MARK, ++}; ++static const unsigned int i2c2_d_pins[] = { ++ /* SCL, SDA */ ++ RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25), ++}; ++static const unsigned int i2c2_d_mux[] = { ++ SCL2_D_MARK, SDA2_D_MARK, ++}; ++/* - I2C3 ------------------------------------------------------------------ */ ++static const unsigned int i2c3_pins[] = { ++ /* SCL, SDA, */ ++ RCAR_GP_PIN(3, 0), RCAR_GP_PIN(2, 30), ++}; ++static const unsigned int i2c3_mux[] = { ++ SCL3_MARK, SDA3_MARK, ++}; ++static const unsigned int i2c3_b_pins[] = { ++ /* SCL, SDA, */ ++ RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 30), ++}; ++static const unsigned int i2c3_b_mux[] = { ++ SCL3_B_MARK, SDA3_B_MARK, ++}; + /* - INTC ------------------------------------------------------------------- */ + static const unsigned int intc_irq0_pins[] = { + /* IRQ */ +@@ -2543,6 +2616,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(hspi1_d), + SH_PFC_PIN_GROUP(hspi2), + SH_PFC_PIN_GROUP(hspi2_b), ++ SH_PFC_PIN_GROUP(i2c1), ++ SH_PFC_PIN_GROUP(i2c1_b), ++ SH_PFC_PIN_GROUP(i2c1_c), ++ SH_PFC_PIN_GROUP(i2c1_d), ++ SH_PFC_PIN_GROUP(i2c2), ++ SH_PFC_PIN_GROUP(i2c2_b), ++ SH_PFC_PIN_GROUP(i2c2_c), ++ SH_PFC_PIN_GROUP(i2c2_d), ++ SH_PFC_PIN_GROUP(i2c3), ++ SH_PFC_PIN_GROUP(i2c3_b), + SH_PFC_PIN_GROUP(intc_irq0), + SH_PFC_PIN_GROUP(intc_irq0_b), + SH_PFC_PIN_GROUP(intc_irq1), +@@ -2703,6 +2786,25 @@ static const char * const hspi2_groups[] = { + "hspi2_b", + }; + ++static const char * const i2c1_groups[] = { ++ "i2c1", ++ "i2c1_b", ++ "i2c1_c", ++ "i2c1_d", ++}; ++ ++static const char * const i2c2_groups[] = { ++ "i2c2", ++ "i2c2_b", ++ "i2c2_c", ++ "i2c2_d", ++}; ++ ++static const char * const i2c3_groups[] = { ++ "i2c3", ++ "i2c3_b", ++}; ++ + static const char * const intc_groups[] = { + "intc_irq0", + "intc_irq0_b", +@@ -2886,6 +2988,9 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(hspi0), + SH_PFC_FUNCTION(hspi1), + SH_PFC_FUNCTION(hspi2), ++ SH_PFC_FUNCTION(i2c1), ++ SH_PFC_FUNCTION(i2c2), ++ SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(lbsc), + SH_PFC_FUNCTION(mmc0), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0559-sh-pfc-r8a7790-Rename-I2C-SDA-SCL-pins.patch b/patches.renesas/0559-sh-pfc-r8a7790-Rename-I2C-SDA-SCL-pins.patch new file mode 100644 index 00000000000..e5a1872047d --- /dev/null +++ b/patches.renesas/0559-sh-pfc-r8a7790-Rename-I2C-SDA-SCL-pins.patch @@ -0,0 +1,558 @@ +From a3b3f6c7149a441940602b15e3b7ccf0ffb02d72 Mon Sep 17 00:00:00 2001 +From: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> +Date: Wed, 22 May 2013 19:46:16 +0900 +Subject: sh-pfc: r8a7790: Rename I2C SDA/SCL pins + +The I2C pins have been renamed in the datasheet, rename them here as +well. + +Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit c4721249dd15684d97af76b2b10073baff90959e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 208 +++++++++++++++++------------------ + 1 file changed, 104 insertions(+), 104 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +index 95b38faf..3ddebc6b 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -111,9 +111,9 @@ enum { + FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5, + FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5, + FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6, +- FN_SCL2_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, +- FN_SCL2_CIS_C, FN_D7, FN_AD_DI_B, FN_SDA2_C, +- FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_SDA2_CIS_C, ++ FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, ++ FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C, ++ FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, + FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, FN_MII_TXD0, + FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, + +@@ -182,11 +182,11 @@ enum { + /* IPSR5 */ + FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, + FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N, +- FN_VI2_HSYNC_N, FN_SCL1, FN_VI2_HSYNC_N_B, +- FN_INTC_EN0_N, FN_SCL1_CIS, FN_EX_CS5_N, FN_CAN0_RX, ++ FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B, ++ FN_INTC_EN0_N, FN_I2C1_SCL, FN_EX_CS5_N, FN_CAN0_RX, + FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2, +- FN_VI1_G2_B, FN_VI2_R4, FN_SDA1, FN_INTC_EN1_N, +- FN_SDA1_CIS, FN_BS_N, FN_IETX, FN_HTX1_B, ++ FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N, ++ FN_I2C1_SDA, FN_BS_N, FN_IETX, FN_HTX1_B, + FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N, + FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3, + FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, +@@ -210,10 +210,10 @@ enum { + FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, + FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, + FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B, +- FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E, +- FN_SCL2_CIS_E, FN_ETH_RX_ER, FN_RMII_RX_ER, ++ FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, ++ FN_I2C2_SCL_E, FN_ETH_RX_ER, FN_RMII_RX_ER, + FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C, +- FN_SDA2_E, FN_SDA2_CIS_E, FN_ETH_RXD0, FN_RMII_RXD0, ++ FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0, FN_RMII_RXD0, + FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C, + FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1, + FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B, +@@ -269,11 +269,11 @@ enum { + FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, + FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, + FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP, +- FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B, +- FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP, ++ FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B, ++ FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP, + FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, +- FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B, +- FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK, ++ FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B, ++ FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK, + FN_AVB_TX_EN, FN_MII_TX_EN, FN_SD1_CMD, + FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B, + FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK, +@@ -283,12 +283,12 @@ enum { + FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0, + FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6, + FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B, +- FN_SCL2_D, FN_SCL2_CIS_D, FN_SIM0_CLK_B, ++ FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B, + FN_VI3_CLK_B, + + /* IPSR10 */ + FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, +- FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D, ++ FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D, + FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK, + FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B, + FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D, +@@ -322,9 +322,9 @@ enum { + FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP, + FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, + FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F, +- FN_RDS_DATA_E, FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B, +- FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B, +- FN_SDA2_CIS_B, FN_MLB_DAT, FN_SPV_EVEN, ++ FN_RDS_DATA_E, FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, ++ FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, ++ FN_I2C2_SDA_B, FN_MLB_DAT, FN_SPV_EVEN, + FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, + FN_RDS_CLK_B, FN_SSI_SCK0129, FN_CAN_CLK_B, + FN_MOUT0, +@@ -378,12 +378,12 @@ enum { + FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, + FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, + FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, +- FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_SDA1_C, +- FN_SDA1_CIS_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0, ++ FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_IIC1_SDA_C, ++ FN_I2C1_SDA_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0, + FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1, + FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N, + FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3, +- FN_LCDOUT11, FN_PWM0_B, FN_SCL1_C, FN_SCL1_CIS_C, ++ FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C, + FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N_TANS, + FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, + FN_SCIFA1_RXD, FN_AD_DI, FN_RX1, +@@ -398,9 +398,9 @@ enum { + /* IPSR15 */ + FN_SCIFA2_SCK, FN_FMCLK, FN_MSIOF3_SCK, FN_DU2_DG7, + FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN, +- FN_DU2_DB0, FN_LCDOUT16, FN_SCL2, FN_SCL2_CIS, ++ FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL, + FN_SCIFA2_TXD, FN_BPFCLK, FN_DU2_DB1, FN_LCDOUT17, +- FN_SDA2, FN_SDA2_CIS, FN_HSCK0, FN_TS_SDEN0, ++ FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0, + FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0, + FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3, + FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, +@@ -491,9 +491,9 @@ enum { + VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK, + SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK, + VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK, +- SCL2_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK, +- SCL2_CIS_C_MARK, D7_MARK, AD_DI_B_MARK, SDA2_C_MARK, +- VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, SDA2_CIS_C_MARK, ++ IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK, ++ I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK, ++ VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, + D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK, MII_TXD0_MARK, + VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK, + +@@ -558,11 +558,11 @@ enum { + EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK, + VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK, + EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK, +- VI2_HSYNC_N_MARK, SCL1_MARK, VI2_HSYNC_N_B_MARK, +- INTC_EN0_N_MARK, SCL1_CIS_MARK, EX_CS5_N_MARK, CAN0_RX_MARK, ++ VI2_HSYNC_N_MARK, IIC1_SCL_MARK, VI2_HSYNC_N_B_MARK, ++ INTC_EN0_N_MARK, I2C1_SCL_MARK, EX_CS5_N_MARK, CAN0_RX_MARK, + MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK, +- VI1_G2_B_MARK, VI2_R4_MARK, SDA1_MARK, INTC_EN1_N_MARK, +- SDA1_CIS_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK, ++ VI1_G2_B_MARK, VI2_R4_MARK, IIC1_SDA_MARK, INTC_EN1_N_MARK, ++ I2C1_SDA_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK, + CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK, + CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK, + VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK, +@@ -585,10 +585,10 @@ enum { + MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK, + SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK, + ETH_CRS_DV_MARK, RMII_CRS_DV_MARK, STP_ISCLK_0_B_MARK, +- TS_SDEN0_D_MARK, GLO_Q0_C_MARK, SCL2_E_MARK, +- SCL2_CIS_E_MARK, ETH_RX_ER_MARK, RMII_RX_ER_MARK, ++ TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK, ++ I2C2_SCL_E_MARK, ETH_RX_ER_MARK, RMII_RX_ER_MARK, + STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK, +- SDA2_E_MARK, SDA2_CIS_E_MARK, ETH_RXD0_MARK, RMII_RXD0_MARK, ++ IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK, RMII_RXD0_MARK, + STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK, + SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK, + RMII_RXD1_MARK, HRX0_E_MARK, STP_ISSYNC_0_B_MARK, +@@ -641,11 +641,11 @@ enum { + SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK, + SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK, + SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK, +- GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, SCL1_B_MARK, +- SCL1_CIS_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK, ++ GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, IIC1_SCL_B_MARK, ++ I2C1_SCL_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK, + MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK, +- GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, SDA1_B_MARK, +- SDA1_CIS_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK, ++ GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK, ++ I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK, + AVB_TX_EN_MARK, MII_TX_EN_MARK, SD1_CMD_MARK, + AVB_TX_ER_MARK, MII_TX_ER_MARK, SCIFB0_SCK_B_MARK, + SD1_DAT0_MARK, AVB_TX_CLK_MARK, MII_TX_CLK_MARK, +@@ -655,11 +655,11 @@ enum { + SD1_DAT3_MARK, AVB_RXD0_MARK, MII_RXD0_MARK, + SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK, + TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK, +- SCL2_D_MARK, SCL2_CIS_D_MARK, SIM0_CLK_B_MARK, ++ IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK, + VI3_CLK_B_MARK, + + SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK, +- GLO_RFON_MARK, VI1_CLK_B_MARK, SDA2_D_MARK, SDA2_CIS_D_MARK, ++ GLO_RFON_MARK, VI1_CLK_B_MARK, IIC2_SDA_D_MARK, I2C2_SDA_D_MARK, + SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK, + VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK, + VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK, +@@ -692,9 +692,9 @@ enum { + VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK, + MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK, + RDS_DATA_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK, FMIN_F_MARK, +- RDS_DATA_E_MARK, MLB_CLK_MARK, SCL2_B_MARK, SCL2_CIS_B_MARK, +- MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, SDA2_B_MARK, +- SDA2_CIS_B_MARK, MLB_DAT_MARK, SPV_EVEN_MARK, ++ RDS_DATA_E_MARK, MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK, ++ MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK, ++ I2C2_SDA_B_MARK, MLB_DAT_MARK, SPV_EVEN_MARK, + SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK, + RDS_CLK_B_MARK, SSI_SCK0129_MARK, CAN_CLK_B_MARK, + MOUT0_MARK, +@@ -745,12 +745,12 @@ enum { + AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK, + DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK, + REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK, +- MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, SDA1_C_MARK, +- SDA1_CIS_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK, ++ MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, IIC1_SDA_C_MARK, ++ I2C1_SDA_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK, + DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK, + TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK, + HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK, +- LCDOUT11_MARK, PWM0_B_MARK, SCL1_C_MARK, SCL1_CIS_C_MARK, ++ LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK, + SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_TANS_MARK, + MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK, + SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK, +@@ -764,9 +764,9 @@ enum { + + SCIFA2_SCK_MARK, FMCLK_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK, + LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK, +- DU2_DB0_MARK, LCDOUT16_MARK, SCL2_MARK, SCL2_CIS_MARK, ++ DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK, + SCIFA2_TXD_MARK, BPFCLK_MARK, DU2_DB1_MARK, LCDOUT17_MARK, +- SDA2_MARK, SDA2_CIS_MARK, HSCK0_MARK, TS_SDEN0_MARK, ++ IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK, + DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK, + DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK, + LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK, +@@ -835,18 +835,18 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP0_19_16, TX0_B, SEL_SCIF0_1), + PINMUX_IPSR_DATA(IP0_22_20, D6), +- PINMUX_IPSR_MODSEL_DATA(IP0_22_20, SCL2_C, SEL_IIC2_2), ++ PINMUX_IPSR_MODSEL_DATA(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2), + PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI3_DATA6, SEL_VI3_0), + PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2_B, SEL_VI0_1), +- PINMUX_IPSR_MODSEL_DATA(IP0_22_20, SCL2_CIS_C, SEL_I2C2_2), ++ PINMUX_IPSR_MODSEL_DATA(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2), + PINMUX_IPSR_DATA(IP0_26_23, D7), + PINMUX_IPSR_MODSEL_DATA(IP0_26_23, AD_DI_B, SEL_ADI_1), +- PINMUX_IPSR_MODSEL_DATA(IP0_26_23, SDA2_C, SEL_IIC2_2), ++ PINMUX_IPSR_MODSEL_DATA(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2), + PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI3_DATA7, SEL_VI3_0), + PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3_B, SEL_VI0_1), +- PINMUX_IPSR_MODSEL_DATA(IP0_26_23, SDA2_CIS_C, SEL_I2C2_2), ++ PINMUX_IPSR_MODSEL_DATA(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2), + PINMUX_IPSR_DATA(IP0_30_27, D8), + PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2), + PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0), +@@ -1063,10 +1063,10 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1), + PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N), + PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0), +- PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SCL1, SEL_IIC1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP5_5_3, IIC1_SCL, SEL_IIC1_0), + PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP5_5_3, INTC_EN0_N), +- PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SCL1_CIS, SEL_I2C1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP5_5_3, I2C1_SCL, SEL_I2C1_0), + PINMUX_IPSR_DATA(IP5_9_6, EX_CS5_N), + PINMUX_IPSR_MODSEL_DATA(IP5_9_6, CAN0_RX, SEL_CAN0_0), + PINMUX_IPSR_MODSEL_DATA(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1), +@@ -1074,9 +1074,9 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP5_9_6, VI2_R4), +- PINMUX_IPSR_MODSEL_DATA(IP5_9_6, SDA1, SEL_IIC1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP5_9_6, IIC1_SDA, SEL_IIC1_0), + PINMUX_IPSR_DATA(IP5_9_6, INTC_EN1_N), +- PINMUX_IPSR_MODSEL_DATA(IP5_9_6, SDA1_CIS, SEL_I2C1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP5_9_6, I2C1_SDA, SEL_I2C1_0), + PINMUX_IPSR_DATA(IP5_12_10, BS_N), + PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX, SEL_IEB_0), + PINMUX_IPSR_MODSEL_DATA(IP5_12_10, HTX1_B, SEL_HSCIF1_1), +@@ -1152,15 +1152,15 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2), +- PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_E, SEL_IIC2_4), +- PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_CIS_E, SEL_I2C2_4), ++ PINMUX_IPSR_MODSEL_DATA(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4), ++ PINMUX_IPSR_MODSEL_DATA(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4), + PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER), + PINMUX_IPSR_DATA(IP6_19_17, RMII_RX_ER), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2), +- PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_E, SEL_IIC2_4), +- PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_CIS_E, SEL_I2C2_4), ++ PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4), ++ PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4), + PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0), + PINMUX_IPSR_DATA(IP6_22_20, RMII_RXD0), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1), +@@ -1315,8 +1315,8 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP), + PINMUX_IPSR_MODSEL_DATA(IP9_11_8, GLO_SCLK, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1), +- PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_B, SEL_IIC1_1), +- PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_CIS_B, SEL_I2C1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP9_15_12, SD0_WP), + PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7), +@@ -1324,8 +1324,8 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN), + PINMUX_IPSR_MODSEL_DATA(IP9_15_12, GLO_SDATA, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1), +- PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_B, SEL_IIC1_1), +- PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_CIS_B, SEL_I2C1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK), + PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN), +@@ -1356,8 +1356,8 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP), + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, GLO_SS, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI0_CLK_B, SEL_VI0_1), +- PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_D, SEL_IIC2_3), +- PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_CIS_D, SEL_I2C2_3), ++ PINMUX_IPSR_MODSEL_DATA(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3), ++ PINMUX_IPSR_MODSEL_DATA(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3), + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SIM0_CLK_B, SEL_SIM_1), + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI3_CLK_B, SEL_VI3_1), + +@@ -1367,8 +1367,8 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN), + PINMUX_IPSR_MODSEL_DATA(IP10_3_0, GLO_RFON, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP10_3_0, VI1_CLK_B, SEL_VI1_1), +- PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_D, SEL_IIC2_3), +- PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_CIS_D, SEL_I2C2_3), ++ PINMUX_IPSR_MODSEL_DATA(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3), ++ PINMUX_IPSR_MODSEL_DATA(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3), + PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SIM0_D_B, SEL_SIM_1), + PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK), + PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK), +@@ -1477,13 +1477,13 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_E, SEL_RDS_4), + PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK), +- PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_B, SEL_IIC2_1), +- PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_CIS_B, SEL_I2C2_1), ++ PINMUX_IPSR_MODSEL_DATA(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1), ++ PINMUX_IPSR_MODSEL_DATA(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1), + PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, RX1_C, SEL_SCIF1_2), +- PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_B, SEL_IIC2_1), +- PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_CIS_B, SEL_I2C2_1), ++ PINMUX_IPSR_MODSEL_DATA(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1), ++ PINMUX_IPSR_MODSEL_DATA(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1), + PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT), + PINMUX_IPSR_DATA(IP11_29_27, SPV_EVEN), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3), +@@ -1633,8 +1633,8 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_DATA(IP14_5_3, MSIOF3_SS2), + PINMUX_IPSR_DATA(IP14_5_3, DU2_DG2), + PINMUX_IPSR_DATA(IP14_5_3, LCDOUT10), +- PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SDA1_C, SEL_IIC1_2), +- PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SDA1_CIS_C, SEL_I2C1_2), ++ PINMUX_IPSR_MODSEL_DATA(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2), ++ PINMUX_IPSR_MODSEL_DATA(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2), + PINMUX_IPSR_MODSEL_DATA(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0), + PINMUX_IPSR_MODSEL_DATA(IP14_8_6, HRX1, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP14_8_6, RX0, SEL_SCIF0_0), +@@ -1652,8 +1652,8 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3), + PINMUX_IPSR_MODSEL_DATA(IP14_15_12, LCDOUT11, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP14_15_12, PWM0_B, SEL_SCIF0_0), +- PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCL1_C, SEL_IIC1_2), +- PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCL1_CIS_C, SEL_I2C1_2), ++ PINMUX_IPSR_MODSEL_DATA(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2), ++ PINMUX_IPSR_MODSEL_DATA(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2), + PINMUX_IPSR_MODSEL_DATA(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0), + PINMUX_IPSR_MODSEL_DATA(IP14_18_16, HRTS1_N, SEL_HSCIF1_0), + PINMUX_IPSR_DATA(IP14_18_16, RTS0_N_TANS), +@@ -1695,20 +1695,20 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MODSEL_DATA(IP15_5_3, FMIN, SEL_FM_0), + PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0), + PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16), +- PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCL2, SEL_IIC2_0), +- PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCL2_CIS, SEL_I2C2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP15_5_3, IIC2_SCL, SEL_IIC2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP15_5_3, I2C2_SCL, SEL_I2C2_0), + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0), + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, BPFCLK, SEL_FM_0), + PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1), + PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17), +- PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SDA2, SEL_IIC2_0), +- PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SDA2_CIS, SEL_I2C2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP15_8_6, IIC2_SDA, SEL_IIC2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP15_8_6, I2C2_SDA, SEL_I2C2_0), + PINMUX_IPSR_DATA(IP15_11_9, HSCK0), + PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TS_SDEN0, SEL_TSIF0_0), + PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4), + PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12), + PINMUX_IPSR_MODSEL_DATA(IP15_11_9, HCTS0_N_C, SEL_IIC2_0), +- PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SDA2_CIS, SEL_I2C2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP15_11_9, I2C2_SDA, SEL_I2C2_0), + PINMUX_IPSR_MODSEL_DATA(IP15_13_12, HRX0, SEL_HSCIF0_0), + PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2), + PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18), +@@ -3204,12 +3204,12 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP0_26_23 [4] */ +- FN_D7, FN_AD_DI_B, FN_SDA2_C, +- FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_SDA2_CIS_C, ++ FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C, ++ FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP0_22_20 [3] */ +- FN_D6, FN_SCL2_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, +- FN_SCL2_CIS_C, 0, 0, ++ FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, ++ FN_I2C2_SCL_C, 0, 0, + /* IP0_19_16 [4] */ + FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5, + FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, +@@ -3391,12 +3391,12 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + 0, 0, + /* IP5_9_6 [4] */ + FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, +- FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_SDA1, FN_INTC_EN1_N, +- FN_SDA1_CIS, 0, 0, 0, 0, 0, 0, ++ FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N, ++ FN_I2C1_SDA, 0, 0, 0, 0, 0, 0, + /* IP5_5_3 [3] */ + FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N, +- FN_VI2_HSYNC_N, FN_SCL1, FN_VI2_HSYNC_N_B, +- FN_INTC_EN0_N, FN_SCL1_CIS, ++ FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B, ++ FN_INTC_EN0_N, FN_I2C1_SCL, + /* IP5_2_0 [3] */ + FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, + FN_VI2_R3, 0, 0, } +@@ -3417,11 +3417,11 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0, + /* IP6_19_17 [3] */ + FN_ETH_RX_ER, FN_RMII_RX_ER, FN_STP_ISD_0_B, +- FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_SDA2_E, FN_SDA2_CIS_E, 0, ++ FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0, + /* IP6_16_14 [3] */ + FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B, +- FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E, +- FN_SCL2_CIS_E, 0, ++ FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, ++ FN_I2C2_SCL_E, 0, + /* IP6_13_11 [3] */ + FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, + FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0, +@@ -3520,7 +3520,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) { + /* IP9_31_28 [4] */ + FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP, +- FN_GLO_SS, FN_VI0_CLK_B, FN_SCL2_D, FN_SCL2_CIS_D, ++ FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D, + FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0, + /* IP9_27_26 [2] */ + FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0, FN_SCIFB0_RTS_N_B, +@@ -3536,12 +3536,12 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + FN_SD1_CLK, FN_AVB_TX_EN, FN_MII_TX_EN, 0, + /* IP9_15_12 [4] */ + FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, +- FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B, +- FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0, ++ FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B, ++ FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0, + /* IP9_11_8 [4] */ + FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP, +- FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B, +- FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0, ++ FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B, ++ FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0, + /* IP9_7_6 [2] */ + FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0, + /* IP9_5_4 [2] */ +@@ -3587,7 +3587,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + FN_VI3_DATA0_B, 0, + /* IP10_3_0 [4] */ + FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, +- FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D, ++ FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D, + FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, +@@ -3598,10 +3598,10 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + FN_MLB_DAT, FN_SPV_EVEN, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, + FN_RDS_CLK_B, 0, 0, + /* IP11_26_24 [3] */ +- FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B, FN_SDA2_CIS_B, ++ FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B, + 0, 0, 0, + /* IP11_23_22 [2] */ +- FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B, 0, ++ FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0, + /* IP11_21_18 [4] */ + FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, + FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F, +@@ -3724,7 +3724,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0, + /* IP14_15_12 [4] */ + FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, +- FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_SCL1_C, FN_SCL1_CIS_C, ++ FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C, + 0, 0, 0, 0, 0, 0, 0, + /* IP14_11_9 [3] */ + FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1, +@@ -3734,7 +3734,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + 0, 0, 0, + /* IP14_5_3 [3] */ + FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2, +- FN_LCDOUT10, FN_SDA1_C, FN_SDA1_CIS_C, ++ FN_LCDOUT10, FN_IIC1_SDA_C, FN_I2C1_SDA_C, + /* IP14_2_0 [3] */ + FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, + FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, +@@ -3767,10 +3767,10 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + 0, 0, 0, + /* IP15_8_6 [3] */ + FN_SCIFA2_TXD, FN_BPFCLK, 0, FN_DU2_DB1, FN_LCDOUT17, +- FN_SDA2, FN_SDA2_CIS, 0, ++ FN_IIC2_SDA, FN_I2C2_SDA, 0, + /* IP15_5_3 [3] */ + FN_SCIFA2_RXD, FN_FMIN, 0, FN_DU2_DB0, FN_LCDOUT16, +- FN_SCL2, FN_SCL2_CIS, 0, ++ FN_IIC2_SCL, FN_I2C2_SCL, 0, + /* IP15_2_0 [3] */ + FN_SCIFA2_SCK, FN_FMCLK, 0, FN_MSIOF3_SCK, FN_DU2_DG7, + FN_LCDOUT15, FN_SCIF_CLK_B, 0, } +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0560-sh-pfc-r8a7790-Remove-trailing-_TANS-string-from-RTS.patch b/patches.renesas/0560-sh-pfc-r8a7790-Remove-trailing-_TANS-string-from-RTS.patch new file mode 100644 index 00000000000..83e3cc66c91 --- /dev/null +++ b/patches.renesas/0560-sh-pfc-r8a7790-Remove-trailing-_TANS-string-from-RTS.patch @@ -0,0 +1,111 @@ +From 5c71f2209ad503afc2c822c9d99b2a1168171afc Mon Sep 17 00:00:00 2001 +From: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> +Date: Fri, 24 May 2013 17:28:17 +0900 +Subject: sh-pfc: r8a7790: Remove trailing '_TANS' string from RTS/CTS pins + +The RTS/CTS pins have been renamed in the datasheet, rename them here as +well. + +Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit bcec7475d84c16c62d5310da96d1e34b9edc750a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 20 ++++++++++---------- + 1 file changed, 10 insertions(+), 10 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +index 3ddebc6b..55827243 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -384,14 +384,14 @@ enum { + FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N, + FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3, + FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C, +- FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N_TANS, ++ FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N, + FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, + FN_SCIFA1_RXD, FN_AD_DI, FN_RX1, + FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, + FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1, + FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK, + FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK, +- FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N_TANS, ++ FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N, + FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE, + FN_HRTS0_N_C, + +@@ -751,14 +751,14 @@ enum { + TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK, + HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK, + LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK, +- SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_TANS_MARK, ++ SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_MARK, + MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK, + SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK, + DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, + SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK, + LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK, + CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK, +- SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_TANS_MARK, ++ SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_MARK, + MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK, + HRTS0_N_C_MARK, + +@@ -1656,7 +1656,7 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MODSEL_DATA(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2), + PINMUX_IPSR_MODSEL_DATA(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0), + PINMUX_IPSR_MODSEL_DATA(IP14_18_16, HRTS1_N, SEL_HSCIF1_0), +- PINMUX_IPSR_DATA(IP14_18_16, RTS0_N_TANS), ++ PINMUX_IPSR_DATA(IP14_18_16, RTS0_N), + PINMUX_IPSR_DATA(IP14_18_16, MSIOF3_SS1), + PINMUX_IPSR_DATA(IP14_18_16, DU2_DG0), + PINMUX_IPSR_DATA(IP14_18_16, LCDOUT8), +@@ -1679,7 +1679,7 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_DATA(IP14_27_25, QCLK), + PINMUX_IPSR_MODSEL_DATA(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0), + PINMUX_IPSR_MODSEL_DATA(IP14_30_28, AD_NCS_N, SEL_ADI_0), +- PINMUX_IPSR_DATA(IP14_30_28, RTS1_N_TANS), ++ PINMUX_IPSR_DATA(IP14_30_28, RTS1_N), + PINMUX_IPSR_MODSEL_DATA(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0), + PINMUX_IPSR_DATA(IP14_30_28, DU1_DOTCLKOUT), + PINMUX_IPSR_DATA(IP14_30_28, QSTVB_QVE), +@@ -1849,7 +1849,7 @@ static const unsigned int scif0_ctrl_pins[] = { + RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), + }; + static const unsigned int scif0_ctrl_mux[] = { +- RTS0_N_TANS_MARK, CTS0_N_MARK, ++ RTS0_N_MARK, CTS0_N_MARK, + }; + static const unsigned int scif0_data_b_pins[] = { + /* RX, TX */ +@@ -1878,7 +1878,7 @@ static const unsigned int scif1_ctrl_pins[] = { + RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2), + }; + static const unsigned int scif1_ctrl_mux[] = { +- RTS1_N_TANS_MARK, CTS1_N_MARK, ++ RTS1_N_MARK, CTS1_N_MARK, + }; + static const unsigned int scif1_data_b_pins[] = { + /* RX, TX */ +@@ -3707,7 +3707,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + /* IP14_30 [1] */ + 0, 0, + /* IP14_30_28 [3] */ +- FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N_TANS, ++ FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N, + FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE, + FN_HRTS0_N_C, 0, + /* IP14_27_25 [3] */ +@@ -3720,7 +3720,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + FN_SCIFA1_RXD, FN_AD_DI, FN_RX1, + FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0, + /* IP14_18_16 [3] */ +- FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N_TANS, ++ FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N, + FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0, + /* IP14_15_12 [4] */ + FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0561-sh-pfc-r8a7790-Remove-deprecated-Ethernet-MII-RMII-p.patch b/patches.renesas/0561-sh-pfc-r8a7790-Remove-deprecated-Ethernet-MII-RMII-p.patch new file mode 100644 index 00000000000..023f47e228c --- /dev/null +++ b/patches.renesas/0561-sh-pfc-r8a7790-Remove-deprecated-Ethernet-MII-RMII-p.patch @@ -0,0 +1,593 @@ +From 32402952533b2049e44420c70d31ba8dfbcceee0 Mon Sep 17 00:00:00 2001 +From: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> +Date: Wed, 22 May 2013 19:55:08 +0900 +Subject: sh-pfc: r8a7790: Remove deprecated Ethernet MII/RMII pins + +The pins have been removed from the datasheet, remove them here as well. + +Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit 9f2edd4113daefb5280fb5f06085fa2069ba0d2b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 224 +++++++++++++++-------------------- + 1 file changed, 94 insertions(+), 130 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +index 55827243..5ddc19a3 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -114,15 +114,15 @@ enum { + FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, + FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C, + FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, +- FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, FN_MII_TXD0, ++ FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, + FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, + + /* IPSR1 */ +- FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, FN_MII_TXD1, ++ FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, + FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10, +- FN_SCIFA1_TXD_C, FN_AVB_TXD2, FN_MII_TXD2, ++ FN_SCIFA1_TXD_C, FN_AVB_TXD2, + FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11, +- FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, FN_MII_TXD3, ++ FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, + FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3, + FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4, + FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4, +@@ -209,29 +209,29 @@ enum { + FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, + FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, + FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, +- FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B, ++ FN_ETH_CRS_DV, FN_STP_ISCLK_0_B, + FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, +- FN_I2C2_SCL_E, FN_ETH_RX_ER, FN_RMII_RX_ER, ++ FN_I2C2_SCL_E, FN_ETH_RX_ER, + FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C, +- FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0, FN_RMII_RXD0, ++ FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0, + FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C, + FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1, +- FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B, ++ FN_HRX0_E, FN_STP_ISSYNC_0_B, + FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, +- FN_RX1_E, FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E, ++ FN_RX1_E, FN_ETH_LINK, FN_HTX0_E, + FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, +- FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E, ++ FN_ETH_REF_CLK, FN_HCTS0_N_E, + FN_STP_IVCXO27_1_B, FN_HRX0_F, + + /* IPSR7 */ +- FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E, ++ FN_ETH_MDIO, FN_HRTS0_N_E, + FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1, +- FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F, +- FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, +- FN_HRTS0_N_F, FN_ETH_MAGIC, FN_RMII_MAGIC, +- FN_SIM0_RST_C, FN_ETH_TXD0, FN_RMII_TXD0, ++ FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F, ++ FN_ETH_TX_EN, FN_SIM0_CLK_C, ++ FN_HRTS0_N_F, FN_ETH_MAGIC, ++ FN_SIM0_RST_C, FN_ETH_TXD0, + FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C, +- FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B, ++ FN_ETH_MDC, FN_STP_ISD_1_B, + FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0, + FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, + FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C, +@@ -239,26 +239,25 @@ enum { + FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, + FN_PCMWE_N, FN_IECLK_C, FN_DU1_DOTCLKIN, + FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK, +- FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1, ++ FN_ATACS00_N, FN_AVB_RXD1, + FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, +- FN_MII_RXD2, + + /* IPSR8 */ + FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, +- FN_MII_RXD3, FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, ++ FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, + FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, + FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, + FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, + FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, +- FN_MII_RX_ER, FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, +- FN_MII_RX_CLK, FN_VI1_CLK, FN_AVB_RX_DV, +- FN_MII_RX_DV, FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, +- FN_AVB_CRS, FN_MII_CRS, FN_VI1_DATA1_VI1_B1, +- FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC, ++ FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, ++ FN_VI1_CLK, FN_AVB_RX_DV, ++ FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, ++ FN_AVB_CRS, FN_VI1_DATA1_VI1_B1, ++ FN_SCIFA1_RXD_D, FN_AVB_MDC, + FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, +- FN_MII_MDIO, FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, ++ FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, + FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, +- FN_AVB_MAGIC, FN_MII_MAGIC, FN_VI1_DATA5_VI1_B5, ++ FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5, + FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK, + FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD, + FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, +@@ -274,13 +273,13 @@ enum { + FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, + FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B, + FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK, +- FN_AVB_TX_EN, FN_MII_TX_EN, FN_SD1_CMD, +- FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B, +- FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK, ++ FN_AVB_TX_EN, FN_SD1_CMD, ++ FN_AVB_TX_ER, FN_SCIFB0_SCK_B, ++ FN_SD1_DAT0, FN_AVB_TX_CLK, + FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK, +- FN_MII_LINK, FN_SCIFB0_TXD_B, FN_SD1_DAT2, +- FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B, +- FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0, ++ FN_SCIFB0_TXD_B, FN_SD1_DAT2, ++ FN_AVB_COL, FN_SCIFB0_CTS_N_B, ++ FN_SD1_DAT3, FN_AVB_RXD0, + FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6, + FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B, + FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B, +@@ -494,14 +493,14 @@ enum { + IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK, + I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK, + VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, +- D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK, MII_TXD0_MARK, ++ D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK, + VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK, + +- D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK, MII_TXD1_MARK, ++ D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK, + VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK, +- SCIFA1_TXD_C_MARK, AVB_TXD2_MARK, MII_TXD2_MARK, ++ SCIFA1_TXD_C_MARK, AVB_TXD2_MARK, + VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK, +- SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK, MII_TXD3_MARK, ++ SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK, + VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK, + D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK, + VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK, +@@ -584,28 +583,28 @@ enum { + DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK, + MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK, + SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK, +- ETH_CRS_DV_MARK, RMII_CRS_DV_MARK, STP_ISCLK_0_B_MARK, ++ ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK, + TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK, +- I2C2_SCL_E_MARK, ETH_RX_ER_MARK, RMII_RX_ER_MARK, ++ I2C2_SCL_E_MARK, ETH_RX_ER_MARK, + STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK, +- IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK, RMII_RXD0_MARK, ++ IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK, + STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK, + SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK, +- RMII_RXD1_MARK, HRX0_E_MARK, STP_ISSYNC_0_B_MARK, ++ HRX0_E_MARK, STP_ISSYNC_0_B_MARK, + TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK, +- RX1_E_MARK, ETH_LINK_MARK, RMII_LINK_MARK, HTX0_E_MARK, ++ RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK, + STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK, +- ETH_REF_CLK_MARK, RMII_REF_CLK_MARK, HCTS0_N_E_MARK, ++ ETH_REF_CLK_MARK, HCTS0_N_E_MARK, + STP_IVCXO27_1_B_MARK, HRX0_F_MARK, + +- ETH_MDIO_MARK, RMII_MDIO_MARK, HRTS0_N_E_MARK, ++ ETH_MDIO_MARK, HRTS0_N_E_MARK, + SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK, +- RMII_TXD1_MARK, HTX0_F_MARK, BPFCLK_G_MARK, RDS_CLK_F_MARK, +- ETH_TX_EN_MARK, RMII_TX_EN_MARK, SIM0_CLK_C_MARK, +- HRTS0_N_F_MARK, ETH_MAGIC_MARK, RMII_MAGIC_MARK, +- SIM0_RST_C_MARK, ETH_TXD0_MARK, RMII_TXD0_MARK, ++ HTX0_F_MARK, BPFCLK_G_MARK, RDS_CLK_F_MARK, ++ ETH_TX_EN_MARK, SIM0_CLK_C_MARK, ++ HRTS0_N_F_MARK, ETH_MAGIC_MARK, ++ SIM0_RST_C_MARK, ETH_TXD0_MARK, + STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK, +- ETH_MDC_MARK, RMII_MDC_MARK, STP_ISD_1_B_MARK, ++ ETH_MDC_MARK, STP_ISD_1_B_MARK, + TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK, + SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK, + GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK, +@@ -613,25 +612,24 @@ enum { + PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK, + PCMWE_N_MARK, IECLK_C_MARK, DU1_DOTCLKIN_MARK, + AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK, +- ATACS00_N_MARK, AVB_RXD1_MARK, MII_RXD1_MARK, ++ ATACS00_N_MARK, AVB_RXD1_MARK, + VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK, +- MII_RXD2_MARK, + + VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK, +- MII_RXD3_MARK, VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK, ++ VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK, + AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK, + AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK, + AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK, + AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK, +- MII_RX_ER_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK, +- MII_RX_CLK_MARK, VI1_CLK_MARK, AVB_RX_DV_MARK, +- MII_RX_DV_MARK, VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK, +- AVB_CRS_MARK, MII_CRS_MARK, VI1_DATA1_VI1_B1_MARK, +- SCIFA1_RXD_D_MARK, AVB_MDC_MARK, MII_MDC_MARK, ++ VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK, ++ VI1_CLK_MARK, AVB_RX_DV_MARK, ++ VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK, ++ AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK, ++ SCIFA1_RXD_D_MARK, AVB_MDC_MARK, + VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK, +- MII_MDIO_MARK, VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK, ++ VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK, + AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK, +- AVB_MAGIC_MARK, MII_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK, ++ AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK, + AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK, + SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK, + SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK, +@@ -646,13 +644,13 @@ enum { + MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK, + GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK, + I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK, +- AVB_TX_EN_MARK, MII_TX_EN_MARK, SD1_CMD_MARK, +- AVB_TX_ER_MARK, MII_TX_ER_MARK, SCIFB0_SCK_B_MARK, +- SD1_DAT0_MARK, AVB_TX_CLK_MARK, MII_TX_CLK_MARK, ++ AVB_TX_EN_MARK, SD1_CMD_MARK, ++ AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK, ++ SD1_DAT0_MARK, AVB_TX_CLK_MARK, + SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK, +- MII_LINK_MARK, SCIFB0_TXD_B_MARK, SD1_DAT2_MARK, +- AVB_COL_MARK, MII_COL_MARK, SCIFB0_CTS_N_B_MARK, +- SD1_DAT3_MARK, AVB_RXD0_MARK, MII_RXD0_MARK, ++ SCIFB0_TXD_B_MARK, SD1_DAT2_MARK, ++ AVB_COL_MARK, SCIFB0_CTS_N_B_MARK, ++ SD1_DAT3_MARK, AVB_RXD0_MARK, + SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK, + TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK, + IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK, +@@ -850,7 +848,6 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_DATA(IP0_30_27, D8), + PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2), + PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0), +- PINMUX_IPSR_DATA(IP0_30_27, MII_TXD0), + PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0), +@@ -858,21 +855,18 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_DATA(IP1_3_0, D9), + PINMUX_IPSR_MODSEL_DATA(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2), + PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1), +- PINMUX_IPSR_DATA(IP1_3_0, MII_TXD1), + PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0), + PINMUX_IPSR_DATA(IP1_7_4, D10), + PINMUX_IPSR_MODSEL_DATA(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2), + PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2), +- PINMUX_IPSR_DATA(IP1_7_4, MII_TXD2), + PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0), + PINMUX_IPSR_DATA(IP1_11_8, D11), + PINMUX_IPSR_MODSEL_DATA(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2), + PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3), +- PINMUX_IPSR_DATA(IP1_11_8, MII_TXD3), + PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0), +@@ -1148,28 +1142,24 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1), + PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV), +- PINMUX_IPSR_DATA(IP6_16_14, RMII_CRS_DV), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4), + PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER), +- PINMUX_IPSR_DATA(IP6_19_17, RMII_RX_ER), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4), + PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0), +- PINMUX_IPSR_DATA(IP6_22_20, RMII_RXD0), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4), + PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1), +- PINMUX_IPSR_DATA(IP6_25_23, RMII_RXD1), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3), +@@ -1177,41 +1167,33 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4), + PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK), +- PINMUX_IPSR_DATA(IP6_28_26, RMII_LINK), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4), + PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK), +- PINMUX_IPSR_DATA(IP6_31_29, RMII_REF_CLK), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5), + + PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO), +- PINMUX_IPSR_DATA(IP7_2_0, RMII_MDIO), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5), + PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1), +- PINMUX_IPSR_DATA(IP7_5_3, RMII_TXD1), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_SIM_2), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RDS_CLK_F, SEL_HSCIF0_5), + PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN), +- PINMUX_IPSR_DATA(IP7_7_6, RMII_TX_EN), + PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2), + PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5), + PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC), +- PINMUX_IPSR_DATA(IP7_9_8, RMII_MAGIC), + PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2), + PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0), +- PINMUX_IPSR_DATA(IP7_12_10, RMII_TXD0), + PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2), + PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC), +- PINMUX_IPSR_DATA(IP7_15_13, RMII_MDC), + PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2), +@@ -1237,16 +1219,13 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0), + PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N), + PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1), +- PINMUX_IPSR_DATA(IP7_28_27, MII_RXD1), + PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0), + PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N), + PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2), +- PINMUX_IPSR_DATA(IP7_30_29, MII_RXD2), + + PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0), + PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N), + PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3), +- PINMUX_IPSR_DATA(IP8_1_0, MII_RXD3), + PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0), + PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N), + PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4), +@@ -1261,32 +1240,25 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7), + PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0), + PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER), +- PINMUX_IPSR_DATA(IP8_11_10, MII_RX_ER), + PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0), + PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK), +- PINMUX_IPSR_DATA(IP8_13_12, MII_RX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0), + PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV), +- PINMUX_IPSR_DATA(IP8_15_14, MII_RX_DV), + PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3), + PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS), +- PINMUX_IPSR_DATA(IP8_17_16, MII_CRS), + PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3), + PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC), +- PINMUX_IPSR_DATA(IP8_19_18, MII_MDC), + PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3), + PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO), +- PINMUX_IPSR_DATA(IP8_21_20, MII_MDIO), + PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3), + PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3), + PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC), +- PINMUX_IPSR_DATA(IP8_25_24, MII_MAGIC), + PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP8_26, AVB_PHY_INT, SEL_SCIFA1_3), + PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0), +@@ -1329,26 +1301,20 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK), + PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN), +- PINMUX_IPSR_DATA(IP9_17_16, MII_TX_EN), + PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD), + PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER), +- PINMUX_IPSR_DATA(IP9_19_18, MII_TX_ER), + PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1), + PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0), + PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK), +- PINMUX_IPSR_DATA(IP9_21_20, MII_TX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1), + PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1), + PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK), +- PINMUX_IPSR_DATA(IP9_23_22, MII_LINK), + PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1), + PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2), + PINMUX_IPSR_DATA(IP9_25_24, AVB_COL), +- PINMUX_IPSR_DATA(IP9_25_24, MII_COL), + PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1), + PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3), + PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0), +- PINMUX_IPSR_DATA(IP9_27_26, MII_RXD0), + PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1), + PINMUX_IPSR_DATA(IP9_31_28, SD1_CD), + PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6), +@@ -3200,7 +3166,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + /* IP0_31 [1] */ + 0, 0, + /* IP0_30_27 [4] */ +- FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, FN_MII_TXD0, ++ FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0, + FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP0_26_23 [4] */ +@@ -3256,15 +3222,15 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4, + 0, 0, + /* IP1_11_8 [4] */ +- FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, FN_MII_TXD3, ++ FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0, + FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP1_7_4 [4] */ +- FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, FN_MII_TXD2, ++ FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0, + FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP1_3_0 [4] */ +- FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, FN_MII_TXD1, ++ FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0, + FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, } + }, +@@ -3404,22 +3370,22 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, + 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) { + /* IP6_31_29 [3] */ +- FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E, ++ FN_ETH_REF_CLK, 0, FN_HCTS0_N_E, + FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0, + /* IP6_28_26 [3] */ +- FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E, ++ FN_ETH_LINK, 0, FN_HTX0_E, + FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0, + /* IP6_25_23 [3] */ +- FN_ETH_RXD1, FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B, ++ FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B, + FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E, + /* IP6_22_20 [3] */ +- FN_ETH_RXD0, FN_RMII_RXD0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D, ++ FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D, + FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0, + /* IP6_19_17 [3] */ +- FN_ETH_RX_ER, FN_RMII_RX_ER, FN_STP_ISD_0_B, ++ FN_ETH_RX_ER, 0, FN_STP_ISD_0_B, + FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0, + /* IP6_16_14 [3] */ +- FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B, ++ FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B, + FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, + FN_I2C2_SCL_E, 0, + /* IP6_13_11 [3] */ +@@ -3442,10 +3408,9 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + /* IP7_31 [1] */ + 0, 0, + /* IP7_30_29 [2] */ +- FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, +- FN_MII_RXD2, ++ FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0, + /* IP7_28_27 [2] */ +- FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1, ++ FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0, + /* IP7_26_25 [2] */ + FN_DU1_DOTCLKIN, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0, + /* IP7_24_22 [3] */ +@@ -3458,20 +3423,20 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, + FN_GLO_SS_C, 0, 0, 0, + /* IP7_15_13 [3] */ +- FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B, ++ FN_ETH_MDC, 0, FN_STP_ISD_1_B, + FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0, + /* IP7_12_10 [3] */ +- FN_ETH_TXD0, FN_RMII_TXD0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, ++ FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, + FN_GLO_SCLK_C, 0, 0, 0, + /* IP7_9_8 [2] */ +- FN_ETH_MAGIC, FN_RMII_MAGIC, FN_SIM0_RST_C, 0, ++ FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0, + /* IP7_7_6 [2] */ +- FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, FN_HRTS0_N_F, ++ FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F, + /* IP7_5_3 [3] */ +- FN_ETH_TXD1, FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F, ++ FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F, + 0, 0, 0, + /* IP7_2_0 [3] */ +- FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E, ++ FN_ETH_MDIO, 0, FN_HRTS0_N_E, + FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, +@@ -3489,22 +3454,21 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT, + /* IP8_25_24 [2] */ + FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, +- FN_AVB_MAGIC, FN_MII_MAGIC, ++ FN_AVB_MAGIC, 0, + /* IP8_23_22 [2] */ + FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0, + /* IP8_21_20 [2] */ +- FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, +- FN_MII_MDIO, ++ FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0, + /* IP8_19_18 [2] */ +- FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC, ++ FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0, + /* IP8_17_16 [2] */ +- FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, FN_MII_CRS, ++ FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0, + /* IP8_15_14 [2] */ +- FN_VI1_CLK, FN_AVB_RX_DV, FN_MII_RX_DV, 0, ++ FN_VI1_CLK, FN_AVB_RX_DV, 0, 0, + /* IP8_13_12 [2] */ +- FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, FN_MII_RX_CLK, 0, ++ FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0, + /* IP8_11_10 [2] */ +- FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, FN_MII_RX_ER, 0, ++ FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0, + /* IP8_9_8 [2] */ + FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0, + /* IP8_7_6 [2] */ +@@ -3514,7 +3478,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + /* IP8_3_2 [2] */ + FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0, + /* IP8_1_0 [2] */ +- FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, FN_MII_RXD3, } ++ FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, + 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) { +@@ -3523,17 +3487,17 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D, + FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0, + /* IP9_27_26 [2] */ +- FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0, FN_SCIFB0_RTS_N_B, ++ FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B, + /* IP9_25_24 [2] */ +- FN_SD1_DAT2, FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B, ++ FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B, + /* IP9_23_22 [2] */ +- FN_SD1_DAT1, FN_AVB_LINK, FN_MII_LINK, FN_SCIFB0_TXD_B, ++ FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B, + /* IP9_21_20 [2] */ +- FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK, FN_SCIFB0_RXD_B, ++ FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B, + /* IP9_19_18 [2] */ +- FN_SD1_CMD, FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B, ++ FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B, + /* IP9_17_16 [2] */ +- FN_SD1_CLK, FN_AVB_TX_EN, FN_MII_TX_EN, 0, ++ FN_SD1_CLK, FN_AVB_TX_EN, 0, 0, + /* IP9_15_12 [4] */ + FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, + FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0562-sh-pfc-r8a7790-Remove-deprecated-RDS-pins.patch b/patches.renesas/0562-sh-pfc-r8a7790-Remove-deprecated-RDS-pins.patch new file mode 100644 index 00000000000..020f506e5e3 --- /dev/null +++ b/patches.renesas/0562-sh-pfc-r8a7790-Remove-deprecated-RDS-pins.patch @@ -0,0 +1,321 @@ +From b27d6f120c36b6dd8a79b1b2ff30105a2ede371f Mon Sep 17 00:00:00 2001 +From: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> +Date: Fri, 24 May 2013 16:14:24 +0900 +Subject: sh-pfc: r8a7790: Remove deprecated RDS pins + +The pins have been removed from the datasheet, remove them here as well. + +Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit 14da999bd69c3bc1f4b1066306d5b268d3dcb57c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 84 ++++++++++++++---------------------- + 1 file changed, 33 insertions(+), 51 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +index 5ddc19a3..ba6ea425 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -226,7 +226,7 @@ enum { + /* IPSR7 */ + FN_ETH_MDIO, FN_HRTS0_N_E, + FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1, +- FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F, ++ FN_HTX0_F, FN_BPFCLK_G, + FN_ETH_TX_EN, FN_SIM0_CLK_C, + FN_HRTS0_N_F, FN_ETH_MAGIC, + FN_SIM0_RST_C, FN_ETH_TXD0, +@@ -296,10 +296,10 @@ enum { + FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B, + FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D, + FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B, +- FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA, ++ FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, + FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D, + FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B, +- FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK, ++ FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, + FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B, + FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3, + FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B, +@@ -320,12 +320,12 @@ enum { + FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1, + FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP, + FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, +- FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F, +- FN_RDS_DATA_E, FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, ++ FN_FMIN_E, FN_FMIN_F, ++ FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, + FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, + FN_I2C2_SDA_B, FN_MLB_DAT, FN_SPV_EVEN, + FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, +- FN_RDS_CLK_B, FN_SSI_SCK0129, FN_CAN_CLK_B, ++ FN_SSI_SCK0129, FN_CAN_CLK_B, + FN_MOUT0, + + /* IPSR12 */ +@@ -352,12 +352,12 @@ enum { + /* IPSR13 */ + FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2, + FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6, +- FN_SCIFB1_CTS_N, FN_BPFCLK_D, FN_RDS_CLK_C, ++ FN_SCIFB1_CTS_N, FN_BPFCLK_D, + FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6, +- FN_BPFCLK_F, FN_RDS_CLK_E, FN_SSI_WS6, ++ FN_BPFCLK_F, FN_SSI_WS6, + FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4, + FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6, +- FN_FMIN_D, FN_RDS_DATA_C, FN_DU2_DR5, FN_LCDOUT5, ++ FN_FMIN_D, FN_DU2_DR5, FN_LCDOUT5, + FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1, + FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6, + FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1, +@@ -365,8 +365,8 @@ enum { + FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7, + FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N, + FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, +- FN_BPFCLK_E, FN_RDS_CLK_D, FN_SSI_SDATA7_B, +- FN_FMIN_G, FN_RDS_DATA_F, FN_SSI_SDATA8, ++ FN_BPFCLK_E, FN_SSI_SDATA7_B, ++ FN_FMIN_G, FN_SSI_SDATA8, + FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C, + FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9, + FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1, +@@ -457,8 +457,6 @@ enum { + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3, + FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, + FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, +- FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, +- FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5, + FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, + FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, + +@@ -599,7 +597,7 @@ enum { + + ETH_MDIO_MARK, HRTS0_N_E_MARK, + SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK, +- HTX0_F_MARK, BPFCLK_G_MARK, RDS_CLK_F_MARK, ++ HTX0_F_MARK, BPFCLK_G_MARK, + ETH_TX_EN_MARK, SIM0_CLK_C_MARK, + HRTS0_N_F_MARK, ETH_MAGIC_MARK, + SIM0_RST_C_MARK, ETH_TXD0_MARK, +@@ -666,10 +664,10 @@ enum { + SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK, + VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK, + TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK, +- SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK, RDS_DATA_MARK, ++ SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK, + VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK, + TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK, +- SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK, RDS_CLK_MARK, ++ SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK, + VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK, + GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK, + MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK, +@@ -689,12 +687,12 @@ enum { + SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK, + VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK, + MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK, +- RDS_DATA_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK, FMIN_F_MARK, +- RDS_DATA_E_MARK, MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK, ++ FMIN_E_MARK, FMIN_F_MARK, ++ MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK, + MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK, + I2C2_SDA_B_MARK, MLB_DAT_MARK, SPV_EVEN_MARK, + SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK, +- RDS_CLK_B_MARK, SSI_SCK0129_MARK, CAN_CLK_B_MARK, ++ SSI_SCK0129_MARK, CAN_CLK_B_MARK, + MOUT0_MARK, + + SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK, +@@ -719,12 +717,12 @@ enum { + + SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK, + LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK, +- SCIFB1_CTS_N_MARK, BPFCLK_D_MARK, RDS_CLK_C_MARK, ++ SCIFB1_CTS_N_MARK, BPFCLK_D_MARK, + DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK, +- BPFCLK_F_MARK, RDS_CLK_E_MARK, SSI_WS6_MARK, ++ BPFCLK_F_MARK, SSI_WS6_MARK, + SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK, + LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK, +- FMIN_D_MARK, RDS_DATA_C_MARK, DU2_DR5_MARK, LCDOUT5_MARK, ++ FMIN_D_MARK, DU2_DR5_MARK, LCDOUT5_MARK, + CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK, + SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK, + CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK, +@@ -732,8 +730,8 @@ enum { + LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK, + STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK, + TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK, +- BPFCLK_E_MARK, RDS_CLK_D_MARK, SSI_SDATA7_B_MARK, +- FMIN_G_MARK, RDS_DATA_F_MARK, SSI_SDATA8_MARK, ++ BPFCLK_E_MARK, SSI_SDATA7_B_MARK, ++ FMIN_G_MARK, SSI_SDATA8_MARK, + STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK, + CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK, + STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK, +@@ -1183,7 +1181,6 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_SIM_2), +- PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RDS_CLK_F, SEL_HSCIF0_5), + PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN), + PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2), + PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5), +@@ -1364,7 +1361,6 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1), + PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, FMIN_B, SEL_FM_1), +- PINMUX_IPSR_MODSEL_DATA(IP10_18_15, RDS_DATA, SEL_RDS_0), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TX1_D, SEL_SCIF1_3), +@@ -1374,7 +1370,6 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2), + PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2), + PINMUX_IPSR_MODSEL_DATA(IP10_22_19, BPFCLK_B, SEL_FM_1), +- PINMUX_IPSR_MODSEL_DATA(IP10_22_19, RDS_CLK, SEL_RDS_0), + PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP10_22_19, HRX0_D, SEL_HSCIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1), +@@ -1437,11 +1432,8 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, TS_SCK1, SEL_TSIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, GLO_Q1, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_C, SEL_FM_2), +- PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_B, SEL_RDS_1), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_E, SEL_FM_4), +- PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_D, SEL_RDS_3), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5), +- PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_E, SEL_RDS_4), + PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK), + PINMUX_IPSR_MODSEL_DATA(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1), + PINMUX_IPSR_MODSEL_DATA(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1), +@@ -1455,7 +1447,6 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2), +- PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RDS_CLK_B, SEL_RDS_1), + PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129), + PINMUX_IPSR_MODSEL_DATA(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1), + PINMUX_IPSR_DATA(IP11_31_30, MOUT0), +@@ -1526,12 +1517,10 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SSI_SCK6, SEL_SSI6_0), + PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0), + PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_D, SEL_FM_3), +- PINMUX_IPSR_MODSEL_DATA(IP13_6_3, RDS_CLK_C, SEL_RDS_2), + PINMUX_IPSR_DATA(IP13_6_3, DU2_DR3), + PINMUX_IPSR_DATA(IP13_6_3, LCDOUT3), + PINMUX_IPSR_DATA(IP13_6_3, CAN_DEBUGOUT6), + PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_F, SEL_FM_5), +- PINMUX_IPSR_MODSEL_DATA(IP13_6_3, RDS_CLK_E, SEL_RDS_4), + PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SSI_WS6, SEL_SSI6_0), + PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0), + PINMUX_IPSR_MODSEL_DATA(IP13_9_7, CAN0_TX_D, SEL_CAN0_3), +@@ -1540,7 +1529,6 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_DATA(IP13_9_7, CAN_DEBUGOUT7), + PINMUX_IPSR_MODSEL_DATA(IP13_12_10, SSI_SDATA6, SEL_SSI6_0), + PINMUX_IPSR_MODSEL_DATA(IP13_12_10, FMIN_D, SEL_FM_3), +- PINMUX_IPSR_MODSEL_DATA(IP13_12_10, RDS_DATA_C, SEL_RDS_2), + PINMUX_IPSR_DATA(IP13_12_10, DU2_DR5), + PINMUX_IPSR_DATA(IP13_12_10, LCDOUT5), + PINMUX_IPSR_DATA(IP13_12_10, CAN_DEBUGOUT8), +@@ -1566,10 +1554,8 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_DATA(IP13_22_19, QSTVA_QVS), + PINMUX_IPSR_DATA(IP13_22_19, CAN_DEBUGOUT11), + PINMUX_IPSR_MODSEL_DATA(IP13_22_19, BPFCLK_E, SEL_FM_4), +- PINMUX_IPSR_MODSEL_DATA(IP13_22_19, RDS_CLK_D, SEL_RDS_3), + PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1), + PINMUX_IPSR_MODSEL_DATA(IP13_22_19, FMIN_G, SEL_FM_6), +- PINMUX_IPSR_MODSEL_DATA(IP13_22_19, RDS_DATA_F, SEL_RDS_5), + PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8, SEL_SSI8_0), + PINMUX_IPSR_MODSEL_DATA(IP13_25_23, STP_ISEN_1, SEL_SSP_0), + PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0), +@@ -3433,8 +3419,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + /* IP7_7_6 [2] */ + FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F, + /* IP7_5_3 [3] */ +- FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F, +- 0, 0, 0, ++ FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0, + /* IP7_2_0 [3] */ + FN_ETH_MDIO, 0, FN_HRTS0_N_E, + FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, } +@@ -3527,11 +3512,11 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B, + FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B, + /* IP10_22_19 [4] */ +- FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK, ++ FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0, + FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B, + FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0, + /* IP10_18_15 [4] */ +- FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA, ++ FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0, + FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D, + FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B, + 0, 0, 0, 0, 0, 0, +@@ -3560,7 +3545,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0, + /* IP11_29_27 [3] */ + FN_MLB_DAT, FN_SPV_EVEN, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, +- FN_RDS_CLK_B, 0, 0, ++ 0, 0, 0, + /* IP11_26_24 [3] */ + FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B, + 0, 0, 0, +@@ -3568,8 +3553,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0, + /* IP11_21_18 [4] */ + FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, +- FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F, +- FN_RDS_DATA_E, 0, 0, 0, 0, 0, 0, ++ 0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0, + /* IP11_17_15 [3] */ + FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1, + FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0, +@@ -3644,8 +3628,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + /* IP13_22_19 [4] */ + FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N, + FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E, +- FN_RDS_CLK_D, FN_SSI_SDATA7_B, FN_FMIN_G, FN_RDS_DATA_F, +- 0, 0, 0, 0, ++ 0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0, + /* IP13_18_16 [3] */ + FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, + FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0, +@@ -3653,15 +3636,15 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK, + FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0, + /* IP13_12_10 [3] */ +- FN_SSI_SDATA6, FN_FMIN_D, FN_RDS_DATA_C, FN_DU2_DR5, FN_LCDOUT5, ++ FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5, + FN_CAN_DEBUGOUT8, 0, 0, + /* IP13_9_7 [3] */ + FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4, + FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0, + /* IP13_6_3 [4] */ +- FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, FN_RDS_CLK_C, ++ FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0, + FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6, +- FN_BPFCLK_F, FN_RDS_CLK_E, 0, 0, 0, 0, 0, 0, 0, ++ FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP13_2_0 [3] */ + FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2, + FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, } +@@ -3855,9 +3838,8 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0, + /* SEL_GPS [2] */ + FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0, +- /* SEL_RDS [3] */ +- FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, +- FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5, 0, 0, ++ /* RESERVED [3] */ ++ 0, 0, 0, 0, 0, 0, 0, 0, + /* SEL_SIM [2] */ + FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0, + /* SEL_SSI8 [2] */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0563-sh-pfc-r8a7790-Remove-deprecated-SPV_EVEN-pin.patch b/patches.renesas/0563-sh-pfc-r8a7790-Remove-deprecated-SPV_EVEN-pin.patch new file mode 100644 index 00000000000..aca78964da2 --- /dev/null +++ b/patches.renesas/0563-sh-pfc-r8a7790-Remove-deprecated-SPV_EVEN-pin.patch @@ -0,0 +1,57 @@ +From 6a252a5e5ba6465dfb6fba5ec607438a0d2a6a61 Mon Sep 17 00:00:00 2001 +From: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> +Date: Fri, 24 May 2013 17:26:08 +0900 +Subject: sh-pfc: r8a7790: Remove deprecated SPV_EVEN pin + +The pins have been removed from the datasheet, remove them here as well. + +Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit 7d2b2854c665ff1bcbf0e740c30bf3fc4dc760bf) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 7 +++---- + 1 file changed, 3 insertions(+), 4 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +index ba6ea425..be19b25e 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -323,7 +323,7 @@ enum { + FN_FMIN_E, FN_FMIN_F, + FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, + FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, +- FN_I2C2_SDA_B, FN_MLB_DAT, FN_SPV_EVEN, ++ FN_I2C2_SDA_B, FN_MLB_DAT, + FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, + FN_SSI_SCK0129, FN_CAN_CLK_B, + FN_MOUT0, +@@ -690,7 +690,7 @@ enum { + FMIN_E_MARK, FMIN_F_MARK, + MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK, + MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK, +- I2C2_SDA_B_MARK, MLB_DAT_MARK, SPV_EVEN_MARK, ++ I2C2_SDA_B_MARK, MLB_DAT_MARK, + SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK, + SSI_SCK0129_MARK, CAN_CLK_B_MARK, + MOUT0_MARK, +@@ -1443,7 +1443,6 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1), + PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT), +- PINMUX_IPSR_DATA(IP11_29_27, SPV_EVEN), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2), +@@ -3544,7 +3543,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + /* IP11_31_30 [2] */ + FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0, + /* IP11_29_27 [3] */ +- FN_MLB_DAT, FN_SPV_EVEN, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, ++ FN_MLB_DAT, 0, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, + 0, 0, 0, + /* IP11_26_24 [3] */ + FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0564-sh-pfc-r8a7790-Swap-SCIFA2_RXD_B-and-HRX0_C-configur.patch b/patches.renesas/0564-sh-pfc-r8a7790-Swap-SCIFA2_RXD_B-and-HRX0_C-configur.patch new file mode 100644 index 00000000000..2e61103a08d --- /dev/null +++ b/patches.renesas/0564-sh-pfc-r8a7790-Swap-SCIFA2_RXD_B-and-HRX0_C-configur.patch @@ -0,0 +1,94 @@ +From a37c7e191c20ef11a2981f93e97fdc373abca1aa Mon Sep 17 00:00:00 2001 +From: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> +Date: Fri, 24 May 2013 17:50:44 +0900 +Subject: sh-pfc: r8a7790: Swap SCIFA2_RXD_B and HRX0_C configurations + +The SCIFA2 RXD_B and HRX0_C pins have their pinmux configuration data +swapped, fix it. + +Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit 5de880dd953ebb5b5d7852ce568608e828a7217e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +index be19b25e..1507d3e6 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -407,7 +407,7 @@ enum { + FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK, + FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0, + FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23, +- FN_SCIFA2_RXD_B, FN_MSIOF0_SS1, FN_ADICHS0, ++ FN_HRX0_C, FN_MSIOF0_SS1, FN_ADICHS0, + FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1, + FN_DU2_DG6, FN_LCDOUT14, + +@@ -415,7 +415,7 @@ enum { + FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2, + FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, + FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2, +- FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_HRX0_C, ++ FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, + FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC, + FN_TCLK1_B, + +@@ -770,14 +770,14 @@ enum { + LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK, + DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK, + SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK, +- SCIFA2_RXD_B_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK, ++ HRX0_C_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK, + DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK, + DU2_DG6_MARK, LCDOUT14_MARK, + + MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK, + DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK, + MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK, +- ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, HRX0_C_MARK, ++ ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK, + USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK, + TCLK1_B_MARK, + PINMUX_MARK_END, +@@ -1685,7 +1685,7 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_DATA(IP15_25_23, ADIDATA), + PINMUX_IPSR_DATA(IP15_25_23, DU2_DB7), + PINMUX_IPSR_DATA(IP15_25_23, LCDOUT23), +- PINMUX_IPSR_MODSEL_DATA(IP15_25_23, SCIFA2_RXD_B, SEL_SCIFA2_1), ++ PINMUX_IPSR_MODSEL_DATA(IP15_25_23, HRX0_C, SEL_SCIFA2_1), + PINMUX_IPSR_MODSEL_DATA(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0), + PINMUX_IPSR_DATA(IP15_27_26, ADICHS0), + PINMUX_IPSR_DATA(IP15_27_26, DU2_DG5), +@@ -1708,7 +1708,7 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_DATA(IP16_5_3, ADICS_SAMP), + PINMUX_IPSR_DATA(IP16_5_3, DU2_CDE), + PINMUX_IPSR_DATA(IP16_5_3, QPOLB), +- PINMUX_IPSR_MODSEL_DATA(IP16_5_3, HRX0_C, SEL_HSCIF0_2), ++ PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2), + PINMUX_IPSR_DATA(IP16_6, USB1_PWEN), + PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D), + PINMUX_IPSR_DATA(IP16_7, USB1_OVC), +@@ -3696,7 +3696,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13, + /* IP15_25_23 [3] */ + FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA, +- FN_DU2_DB7, FN_LCDOUT23, FN_SCIFA2_RXD_B, 0, ++ FN_DU2_DB7, FN_LCDOUT23, FN_HRX0_C, 0, + /* IP15_22_20 [3] */ + FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK, + FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0, +@@ -3747,7 +3747,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, + /* IP16_5_3 [3] */ + FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2, +- FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_HRX0_C, 0, ++ FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0, + /* IP16_2_0 [3] */ + FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2, + FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, } +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0565-sh-pfc-r8a7790-Add-TCLK1-pin-configuration-support.patch b/patches.renesas/0565-sh-pfc-r8a7790-Add-TCLK1-pin-configuration-support.patch new file mode 100644 index 00000000000..8615ef1ecd7 --- /dev/null +++ b/patches.renesas/0565-sh-pfc-r8a7790-Add-TCLK1-pin-configuration-support.patch @@ -0,0 +1,57 @@ +From 562d63b0a26c69d27adc7a93f6970c828f0e1fbb Mon Sep 17 00:00:00 2001 +From: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> +Date: Fri, 24 May 2013 16:31:32 +0900 +Subject: sh-pfc: r8a7790: Add TCLK1 pin configuration support + +Update the pinmux configuration tables to support the TCLK1 pin. + +Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit 05bcb07bc8dd5f185e9f6568866e7b1abdc60e82) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +index 1507d3e6..1ae1dc75 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -113,7 +113,7 @@ enum { + FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6, + FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, + FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C, +- FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, ++ FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, FN_TCLK1, + FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, + FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, + +@@ -490,7 +490,7 @@ enum { + VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK, + IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK, + I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK, +- VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, ++ VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, TCLK1_MARK, + D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK, + VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK, + +@@ -843,6 +843,7 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2), ++ PINMUX_IPSR_MODSEL_DATA(IP0_26_23, TCLK1, SEL_TMU1_0), + PINMUX_IPSR_DATA(IP0_30_27, D8), + PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2), + PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0), +@@ -3157,7 +3158,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + /* IP0_26_23 [4] */ + FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C, + FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, +- 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ FN_TCLK1, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP0_22_20 [3] */ + FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, + FN_I2C2_SCL_C, 0, 0, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0566-sh-pfc-r8a7790-Add-SCIF2-pins-configuration-support.patch b/patches.renesas/0566-sh-pfc-r8a7790-Add-SCIF2-pins-configuration-support.patch new file mode 100644 index 00000000000..efc895b76ec --- /dev/null +++ b/patches.renesas/0566-sh-pfc-r8a7790-Add-SCIF2-pins-configuration-support.patch @@ -0,0 +1,163 @@ +From 56d947d068e57efc226bdaf981e6e1909cf1c90b Mon Sep 17 00:00:00 2001 +From: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> +Date: Fri, 24 May 2013 16:56:54 +0900 +Subject: sh-pfc: r8a7790: Add SCIF2 pins configuration support + +Update the pinmux configuration tables to support the SCIF2 pins +(TX2/TX2_B, RX2/RX2_B, SCK2). + +Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit 1ddb66cd6f337e3df5d51d0d3cdfd4507d9199c3) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 40 +++++++++++++++++++++--------------- + 1 file changed, 23 insertions(+), 17 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +index 1ae1dc75..344be5e3 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -141,9 +141,9 @@ enum { + FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7, + FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3, + FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4, +- FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_VI2_DATA0_VI2_B0_B, ++ FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B, + FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5, +- FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_VI2_DATA1_VI2_B1_B, ++ FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B, + FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6, + FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, + +@@ -395,10 +395,10 @@ enum { + FN_HRTS0_N_C, + + /* IPSR15 */ +- FN_SCIFA2_SCK, FN_FMCLK, FN_MSIOF3_SCK, FN_DU2_DG7, ++ FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7, + FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN, +- FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL, +- FN_SCIFA2_TXD, FN_BPFCLK, FN_DU2_DB1, FN_LCDOUT17, ++ FN_TX2, FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL, ++ FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17, + FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0, + FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0, + FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3, +@@ -450,6 +450,7 @@ enum { + FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, + FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, + FN_SEL_CAN1_0, FN_SEL_CAN1_1, ++ FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, + FN_SEL_ADI_0, FN_SEL_ADI_1, + FN_SEL_SSP_0, FN_SEL_SSP_1, + FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, +@@ -516,9 +517,9 @@ enum { + A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK, + SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK, + A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK, +- VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, VI2_DATA0_VI2_B0_B_MARK, ++ VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, RX2_B_MARK, VI2_DATA0_VI2_B0_B_MARK, + A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK, +- VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, VI2_DATA1_VI2_B1_B_MARK, ++ VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, TX2_B_MARK, VI2_DATA1_VI2_B1_B_MARK, + A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK, + VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK, + +@@ -758,10 +759,10 @@ enum { + MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK, + HRTS0_N_C_MARK, + +- SCIFA2_SCK_MARK, FMCLK_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK, ++ SCIFA2_SCK_MARK, FMCLK_MARK, SCK2_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK, + LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK, +- DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK, +- SCIFA2_TXD_MARK, BPFCLK_MARK, DU2_DB1_MARK, LCDOUT17_MARK, ++ TX2_MARK, DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK, ++ SCIFA2_TXD_MARK, BPFCLK_MARK, RX2_MARK, DU2_DB1_MARK, LCDOUT17_MARK, + IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK, + DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK, + DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK, +@@ -924,6 +925,7 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2), ++ PINMUX_IPSR_MODSEL_DATA(IP2_21_18, RX2_B, SEL_SCIF2_1), + PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP2_25_22, A9), + PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1), +@@ -931,6 +933,7 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2), ++ PINMUX_IPSR_MODSEL_DATA(IP2_25_22, TX2_B, SEL_SCIF2_1), + PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP2_28_26, A10), + PINMUX_IPSR_MODSEL_DATA(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1), +@@ -1639,18 +1642,21 @@ static const u16 pinmux_data[] = { + + PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0), + PINMUX_IPSR_MODSEL_DATA(IP15_2_0, FMCLK, SEL_FM_0), ++ PINMUX_IPSR_DATA(IP15_2_0, SCK2), + PINMUX_IPSR_MODSEL_DATA(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0), + PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7), + PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15), + PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_0), + PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0), + PINMUX_IPSR_MODSEL_DATA(IP15_5_3, FMIN, SEL_FM_0), ++ PINMUX_IPSR_MODSEL_DATA(IP15_5_3, TX2, SEL_SCIF2_0), + PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0), + PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16), + PINMUX_IPSR_MODSEL_DATA(IP15_5_3, IIC2_SCL, SEL_IIC2_0), + PINMUX_IPSR_MODSEL_DATA(IP15_5_3, I2C2_SCL, SEL_I2C2_0), + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0), + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, BPFCLK, SEL_FM_0), ++ PINMUX_IPSR_MODSEL_DATA(IP15_8_6, RX2, SEL_SCIF2_0), + PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1), + PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17), + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, IIC2_SDA, SEL_IIC2_0), +@@ -3229,11 +3235,11 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0, + /* IP2_25_22 [4] */ + FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5, +- FN_VI0_R5_B, FN_SCIFB2_TXD_C, 0, FN_VI2_DATA1_VI2_B1_B, ++ FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP2_21_18 [4] */ + FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4, +- FN_VI0_R4_B, FN_SCIFB2_RXD_C, 0, FN_VI2_DATA0_VI2_B0_B, ++ FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP2_17_15 [3] */ + FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3, +@@ -3713,13 +3719,13 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, + 0, 0, 0, + /* IP15_8_6 [3] */ +- FN_SCIFA2_TXD, FN_BPFCLK, 0, FN_DU2_DB1, FN_LCDOUT17, ++ FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17, + FN_IIC2_SDA, FN_I2C2_SDA, 0, + /* IP15_5_3 [3] */ +- FN_SCIFA2_RXD, FN_FMIN, 0, FN_DU2_DB0, FN_LCDOUT16, ++ FN_SCIFA2_RXD, FN_FMIN, FN_TX2, FN_DU2_DB0, FN_LCDOUT16, + FN_IIC2_SCL, FN_I2C2_SCL, 0, + /* IP15_2_0 [3] */ +- FN_SCIFA2_SCK, FN_FMCLK, 0, FN_MSIOF3_SCK, FN_DU2_DG7, ++ FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7, + FN_LCDOUT15, FN_SCIF_CLK_B, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32, +@@ -3824,8 +3830,8 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + FN_SEL_CAN1_0, FN_SEL_CAN1_1, + /* RESERVED [2] */ + 0, 0, 0, 0, +- /* RESERVED [1] (actually TX2, RX2 vs. TX2_B, RX2_B of SCIF2) */ +- 0, 0, ++ /* SEL_SCIF2 [1] */ ++ FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, + /* SEL_ADI [1] */ + FN_SEL_ADI_0, FN_SEL_ADI_1, + /* SEL_SSP [1] */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0567-sh-pfc-r8a7790-Fix-miscellaneous-pinmux-configuratio.patch b/patches.renesas/0567-sh-pfc-r8a7790-Fix-miscellaneous-pinmux-configuratio.patch new file mode 100644 index 00000000000..f3370ca1840 --- /dev/null +++ b/patches.renesas/0567-sh-pfc-r8a7790-Fix-miscellaneous-pinmux-configuratio.patch @@ -0,0 +1,140 @@ +From 46ca753fea157c3bfe024cd040d3e1556a29adea Mon Sep 17 00:00:00 2001 +From: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> +Date: Mon, 27 May 2013 17:10:11 +0900 +Subject: sh-pfc: r8a7790: Fix miscellaneous pinmux configuration tables + mistakes + +Fix erroneous entries in the pinmux configuration tables that affect +HSCIF, I2C, LBSC, SCIF, SSI and VIN operation. + +Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit 0a664e3d7978f54af72277a969245ac5e6418cd9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 31 +++++++++++++++---------------- + 1 file changed, 15 insertions(+), 16 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +index 344be5e3..93d4f788 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -877,7 +877,7 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0), + PINMUX_IPSR_DATA(IP1_17_15, D13), +- PINMUX_IPSR_MODSEL_DATA(IP1_17_15, AVB_TXD5, SEL_SCIFA1_2), ++ PINMUX_IPSR_DATA(IP1_17_15, AVB_TXD5), + PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0), +@@ -948,14 +948,14 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP3_3_0, VI2_G0), +- PINMUX_IPSR_DATA(IP3_3_0, VI2_DATA3_VI2_B3_B), ++ PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP3_7_4, A12), + PINMUX_IPSR_MODSEL_DATA(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1), + PINMUX_IPSR_DATA(IP3_7_4, MSIOF2_TXD), + PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP3_7_4, VI2_G1), +- PINMUX_IPSR_DATA(IP3_7_4, VI2_DATA4_VI2_B4_B), ++ PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP3_11_8, A13), + PINMUX_IPSR_MODSEL_DATA(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1), + PINMUX_IPSR_DATA(IP3_11_8, EX_WAIT2), +@@ -963,7 +963,7 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP3_11_8, VI2_G2), +- PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP3_14_12, A14), + PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1), + PINMUX_IPSR_DATA(IP3_14_12, ATACS11_N), +@@ -1055,7 +1055,7 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP5_2_0, VI2_R3), +- PINMUX_IPSR_MODSEL_DATA(IP5_5_3, EX_CS4_N, SEL_I2C1_0), ++ PINMUX_IPSR_DATA(IP5_5_3, EX_CS4_N), + PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1), + PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N), + PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0), +@@ -1102,7 +1102,7 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_DATA(IP5_23_21, VI2_R6), + PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1), + PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX_C, SEL_IEB_2), +- PINMUX_IPSR_DATA(IP5_26_24, EX_WAIT0), ++ PINMUX_IPSR_MODSEL_DATA(IP5_26_24, EX_WAIT0, SEL_LBS_0), + PINMUX_IPSR_DATA(IP5_26_24, IRQ3), + PINMUX_IPSR_DATA(IP5_26_24, INTC_IRQ3_N), + PINMUX_IPSR_MODSEL_DATA(IP5_26_24, VI3_CLK, SEL_VI3_0), +@@ -1183,8 +1183,8 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5), + PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1), +- PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_4), +- PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_SIM_2), ++ PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_5), ++ PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_FM_6), + PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN), + PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2), + PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5), +@@ -1261,7 +1261,7 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3), + PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC), + PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0), +- PINMUX_IPSR_MODSEL_DATA(IP8_26, AVB_PHY_INT, SEL_SCIFA1_3), ++ PINMUX_IPSR_DATA(IP8_26, AVB_PHY_INT), + PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0), + PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK), + PINMUX_IPSR_DATA(IP8_28, SD0_CLK), +@@ -1465,7 +1465,7 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_DATA(IP12_5_4, MOUT5), + PINMUX_IPSR_DATA(IP12_7_6, SSI_SDATA2), + PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_RX_B, SEL_CAN1_1), +- PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_TX_B, SEL_CAN1_1), ++ PINMUX_IPSR_DATA(IP12_7_6, SSI_SCK1), + PINMUX_IPSR_DATA(IP12_7_6, MOUT6), + PINMUX_IPSR_DATA(IP12_10_8, SSI_SCK34), + PINMUX_IPSR_DATA(IP12_10_8, STP_OPWM_0), +@@ -1602,11 +1602,11 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_DATA(IP14_11_9, LCDOUT1), + PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0), + PINMUX_IPSR_MODSEL_DATA(IP14_15_12, HCTS1_N, SEL_HSCIF1_0), +- PINMUX_IPSR_MODSEL_DATA(IP14_15_12, CTS0_N, SEL_SCIF0_0), ++ PINMUX_IPSR_DATA(IP14_15_12, CTS0_N), + PINMUX_IPSR_MODSEL_DATA(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0), + PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3), +- PINMUX_IPSR_MODSEL_DATA(IP14_15_12, LCDOUT11, SEL_HSCIF1_0), +- PINMUX_IPSR_MODSEL_DATA(IP14_15_12, PWM0_B, SEL_SCIF0_0), ++ PINMUX_IPSR_DATA(IP14_15_12, LCDOUT11), ++ PINMUX_IPSR_DATA(IP14_15_12, PWM0_B), + PINMUX_IPSR_MODSEL_DATA(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2), + PINMUX_IPSR_MODSEL_DATA(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2), + PINMUX_IPSR_MODSEL_DATA(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0), +@@ -1646,7 +1646,7 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MODSEL_DATA(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0), + PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7), + PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15), +- PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_0), ++ PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1), + PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0), + PINMUX_IPSR_MODSEL_DATA(IP15_5_3, FMIN, SEL_FM_0), + PINMUX_IPSR_MODSEL_DATA(IP15_5_3, TX2, SEL_SCIF2_0), +@@ -1665,8 +1665,7 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TS_SDEN0, SEL_TSIF0_0), + PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4), + PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12), +- PINMUX_IPSR_MODSEL_DATA(IP15_11_9, HCTS0_N_C, SEL_IIC2_0), +- PINMUX_IPSR_MODSEL_DATA(IP15_11_9, I2C2_SDA, SEL_I2C2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP15_13_12, HRX0, SEL_HSCIF0_0), + PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2), + PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0568-sh-pfc-r8a7790-Sort-pin-groups-and-functions-alphabe.patch b/patches.renesas/0568-sh-pfc-r8a7790-Sort-pin-groups-and-functions-alphabe.patch new file mode 100644 index 00000000000..be3a8f9b110 --- /dev/null +++ b/patches.renesas/0568-sh-pfc-r8a7790-Sort-pin-groups-and-functions-alphabe.patch @@ -0,0 +1,653 @@ +From 96045f7ed964adc331e3850dc56190a930a2bd81 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Wed, 24 Jul 2013 01:47:29 +0200 +Subject: sh-pfc: r8a7790: Sort pin groups and functions alphabetically + +Navigating through the source code is hard enough without having to +manually search for groups and functions. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit 457c11d3e89f7c874d793b05a1c808f64d5f896f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 560 +++++++++++++++++------------------ + 1 file changed, 280 insertions(+), 280 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +index 93d4f788..e0337832 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -1757,128 +1757,6 @@ static const unsigned int eth_rmii_mux[] = { + ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, + ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK, + }; +-/* - INTC ------------------------------------------------------------------- */ +-static const unsigned int intc_irq0_pins[] = { +- /* IRQ */ +- RCAR_GP_PIN(1, 25), +-}; +-static const unsigned int intc_irq0_mux[] = { +- IRQ0_MARK, +-}; +-static const unsigned int intc_irq1_pins[] = { +- /* IRQ */ +- RCAR_GP_PIN(1, 27), +-}; +-static const unsigned int intc_irq1_mux[] = { +- IRQ1_MARK, +-}; +-static const unsigned int intc_irq2_pins[] = { +- /* IRQ */ +- RCAR_GP_PIN(1, 29), +-}; +-static const unsigned int intc_irq2_mux[] = { +- IRQ2_MARK, +-}; +-static const unsigned int intc_irq3_pins[] = { +- /* IRQ */ +- RCAR_GP_PIN(1, 23), +-}; +-static const unsigned int intc_irq3_mux[] = { +- IRQ3_MARK, +-}; +-/* - SCIF0 ----------------------------------------------------------------- */ +-static const unsigned int scif0_data_pins[] = { +- /* RX, TX */ +- RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), +-}; +-static const unsigned int scif0_data_mux[] = { +- RX0_MARK, TX0_MARK, +-}; +-static const unsigned int scif0_clk_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(4, 27), +-}; +-static const unsigned int scif0_clk_mux[] = { +- SCK0_MARK, +-}; +-static const unsigned int scif0_ctrl_pins[] = { +- /* RTS, CTS */ +- RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), +-}; +-static const unsigned int scif0_ctrl_mux[] = { +- RTS0_N_MARK, CTS0_N_MARK, +-}; +-static const unsigned int scif0_data_b_pins[] = { +- /* RX, TX */ +- RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), +-}; +-static const unsigned int scif0_data_b_mux[] = { +- RX0_B_MARK, TX0_B_MARK, +-}; +-/* - SCIF1 ----------------------------------------------------------------- */ +-static const unsigned int scif1_data_pins[] = { +- /* RX, TX */ +- RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), +-}; +-static const unsigned int scif1_data_mux[] = { +- RX1_MARK, TX1_MARK, +-}; +-static const unsigned int scif1_clk_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(4, 20), +-}; +-static const unsigned int scif1_clk_mux[] = { +- SCK1_MARK, +-}; +-static const unsigned int scif1_ctrl_pins[] = { +- /* RTS, CTS */ +- RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2), +-}; +-static const unsigned int scif1_ctrl_mux[] = { +- RTS1_N_MARK, CTS1_N_MARK, +-}; +-static const unsigned int scif1_data_b_pins[] = { +- /* RX, TX */ +- RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), +-}; +-static const unsigned int scif1_data_b_mux[] = { +- RX1_B_MARK, TX1_B_MARK, +-}; +-static const unsigned int scif1_data_c_pins[] = { +- /* RX, TX */ +- RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), +-}; +-static const unsigned int scif1_data_c_mux[] = { +- RX1_C_MARK, TX1_C_MARK, +-}; +-static const unsigned int scif1_data_d_pins[] = { +- /* RX, TX */ +- RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), +-}; +-static const unsigned int scif1_data_d_mux[] = { +- RX1_D_MARK, TX1_D_MARK, +-}; +-static const unsigned int scif1_clk_d_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(3, 17), +-}; +-static const unsigned int scif1_clk_d_mux[] = { +- SCK1_D_MARK, +-}; +-static const unsigned int scif1_data_e_pins[] = { +- /* RX, TX */ +- RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), +-}; +-static const unsigned int scif1_data_e_mux[] = { +- RX1_E_MARK, TX1_E_MARK, +-}; +-static const unsigned int scif1_clk_e_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(2, 20), +-}; +-static const unsigned int scif1_clk_e_mux[] = { +- SCK1_E_MARK, +-}; + /* - HSCIF0 ----------------------------------------------------------------- */ + static const unsigned int hscif0_data_pins[] = { + /* RX, TX */ +@@ -1990,29 +1868,219 @@ static const unsigned int hscif1_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), + }; +-static const unsigned int hscif1_ctrl_mux[] = { +- HRTS1_N_MARK, HCTS1_N_MARK, ++static const unsigned int hscif1_ctrl_mux[] = { ++ HRTS1_N_MARK, HCTS1_N_MARK, ++}; ++static const unsigned int hscif1_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18), ++}; ++static const unsigned int hscif1_data_b_mux[] = { ++ HRX1_B_MARK, HTX1_B_MARK, ++}; ++static const unsigned int hscif1_clk_b_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(1, 28), ++}; ++static const unsigned int hscif1_clk_b_mux[] = { ++ HSCK1_B_MARK, ++}; ++static const unsigned int hscif1_ctrl_b_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), ++}; ++static const unsigned int hscif1_ctrl_b_mux[] = { ++ HRTS1_N_B_MARK, HCTS1_N_B_MARK, ++}; ++/* - INTC ------------------------------------------------------------------- */ ++static const unsigned int intc_irq0_pins[] = { ++ /* IRQ */ ++ RCAR_GP_PIN(1, 25), ++}; ++static const unsigned int intc_irq0_mux[] = { ++ IRQ0_MARK, ++}; ++static const unsigned int intc_irq1_pins[] = { ++ /* IRQ */ ++ RCAR_GP_PIN(1, 27), ++}; ++static const unsigned int intc_irq1_mux[] = { ++ IRQ1_MARK, ++}; ++static const unsigned int intc_irq2_pins[] = { ++ /* IRQ */ ++ RCAR_GP_PIN(1, 29), ++}; ++static const unsigned int intc_irq2_mux[] = { ++ IRQ2_MARK, ++}; ++static const unsigned int intc_irq3_pins[] = { ++ /* IRQ */ ++ RCAR_GP_PIN(1, 23), ++}; ++static const unsigned int intc_irq3_mux[] = { ++ IRQ3_MARK, ++}; ++/* - MMCIF0 ----------------------------------------------------------------- */ ++static const unsigned int mmc0_data1_pins[] = { ++ /* D[0] */ ++ RCAR_GP_PIN(3, 18), ++}; ++static const unsigned int mmc0_data1_mux[] = { ++ MMC0_D0_MARK, ++}; ++static const unsigned int mmc0_data4_pins[] = { ++ /* D[0:3] */ ++ RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), ++ RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), ++}; ++static const unsigned int mmc0_data4_mux[] = { ++ MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, ++}; ++static const unsigned int mmc0_data8_pins[] = { ++ /* D[0:7] */ ++ RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), ++ RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), ++ RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), ++ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), ++}; ++static const unsigned int mmc0_data8_mux[] = { ++ MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, ++ MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK, ++}; ++static const unsigned int mmc0_ctrl_pins[] = { ++ /* CLK, CMD */ ++ RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), ++}; ++static const unsigned int mmc0_ctrl_mux[] = { ++ MMC0_CLK_MARK, MMC0_CMD_MARK, ++}; ++/* - MMCIF1 ----------------------------------------------------------------- */ ++static const unsigned int mmc1_data1_pins[] = { ++ /* D[0] */ ++ RCAR_GP_PIN(3, 26), ++}; ++static const unsigned int mmc1_data1_mux[] = { ++ MMC1_D0_MARK, ++}; ++static const unsigned int mmc1_data4_pins[] = { ++ /* D[0:3] */ ++ RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), ++ RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), ++}; ++static const unsigned int mmc1_data4_mux[] = { ++ MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, ++}; ++static const unsigned int mmc1_data8_pins[] = { ++ /* D[0:7] */ ++ RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), ++ RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), ++ RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), ++ RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), ++}; ++static const unsigned int mmc1_data8_mux[] = { ++ MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, ++ MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK, ++}; ++static const unsigned int mmc1_ctrl_pins[] = { ++ /* CLK, CMD */ ++ RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25), ++}; ++static const unsigned int mmc1_ctrl_mux[] = { ++ MMC1_CLK_MARK, MMC1_CMD_MARK, ++}; ++/* - SCIF0 ------------------------------------------------------------------ */ ++static const unsigned int scif0_data_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), ++}; ++static const unsigned int scif0_data_mux[] = { ++ RX0_MARK, TX0_MARK, ++}; ++static const unsigned int scif0_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(4, 27), ++}; ++static const unsigned int scif0_clk_mux[] = { ++ SCK0_MARK, ++}; ++static const unsigned int scif0_ctrl_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), ++}; ++static const unsigned int scif0_ctrl_mux[] = { ++ RTS0_N_MARK, CTS0_N_MARK, ++}; ++static const unsigned int scif0_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), ++}; ++static const unsigned int scif0_data_b_mux[] = { ++ RX0_B_MARK, TX0_B_MARK, ++}; ++/* - SCIF1 ------------------------------------------------------------------ */ ++static const unsigned int scif1_data_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), ++}; ++static const unsigned int scif1_data_mux[] = { ++ RX1_MARK, TX1_MARK, ++}; ++static const unsigned int scif1_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(4, 20), ++}; ++static const unsigned int scif1_clk_mux[] = { ++ SCK1_MARK, ++}; ++static const unsigned int scif1_ctrl_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2), ++}; ++static const unsigned int scif1_ctrl_mux[] = { ++ RTS1_N_MARK, CTS1_N_MARK, ++}; ++static const unsigned int scif1_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), ++}; ++static const unsigned int scif1_data_b_mux[] = { ++ RX1_B_MARK, TX1_B_MARK, ++}; ++static const unsigned int scif1_data_c_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), ++}; ++static const unsigned int scif1_data_c_mux[] = { ++ RX1_C_MARK, TX1_C_MARK, + }; +-static const unsigned int hscif1_data_b_pins[] = { ++static const unsigned int scif1_data_d_pins[] = { + /* RX, TX */ +- RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18), ++ RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), + }; +-static const unsigned int hscif1_data_b_mux[] = { +- HRX1_B_MARK, HTX1_B_MARK, ++static const unsigned int scif1_data_d_mux[] = { ++ RX1_D_MARK, TX1_D_MARK, + }; +-static const unsigned int hscif1_clk_b_pins[] = { ++static const unsigned int scif1_clk_d_pins[] = { + /* SCK */ +- RCAR_GP_PIN(1, 28), ++ RCAR_GP_PIN(3, 17), + }; +-static const unsigned int hscif1_clk_b_mux[] = { +- HSCK1_B_MARK, ++static const unsigned int scif1_clk_d_mux[] = { ++ SCK1_D_MARK, + }; +-static const unsigned int hscif1_ctrl_b_pins[] = { +- /* RTS, CTS */ +- RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), ++static const unsigned int scif1_data_e_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), + }; +-static const unsigned int hscif1_ctrl_b_mux[] = { +- HRTS1_N_B_MARK, HCTS1_N_B_MARK, ++static const unsigned int scif1_data_e_mux[] = { ++ RX1_E_MARK, TX1_E_MARK, ++}; ++static const unsigned int scif1_clk_e_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(2, 20), ++}; ++static const unsigned int scif1_clk_e_mux[] = { ++ SCK1_E_MARK, + }; + /* - SCIFA0 ----------------------------------------------------------------- */ + static const unsigned int scifa0_data_pins[] = { +@@ -2377,103 +2445,6 @@ static const unsigned int scifb2_data_c_pins[] = { + static const unsigned int scifb2_data_c_mux[] = { + SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK, + }; +-/* - TPU0 ------------------------------------------------------------------- */ +-static const unsigned int tpu0_to0_pins[] = { +- /* TO */ +- RCAR_GP_PIN(0, 20), +-}; +-static const unsigned int tpu0_to0_mux[] = { +- TPU0TO0_MARK, +-}; +-static const unsigned int tpu0_to1_pins[] = { +- /* TO */ +- RCAR_GP_PIN(0, 21), +-}; +-static const unsigned int tpu0_to1_mux[] = { +- TPU0TO1_MARK, +-}; +-static const unsigned int tpu0_to2_pins[] = { +- /* TO */ +- RCAR_GP_PIN(0, 22), +-}; +-static const unsigned int tpu0_to2_mux[] = { +- TPU0TO2_MARK, +-}; +-static const unsigned int tpu0_to3_pins[] = { +- /* TO */ +- RCAR_GP_PIN(0, 23), +-}; +-static const unsigned int tpu0_to3_mux[] = { +- TPU0TO3_MARK, +-}; +-/* - MMCIF0 ----------------------------------------------------------------- */ +-static const unsigned int mmc0_data1_pins[] = { +- /* D[0] */ +- RCAR_GP_PIN(3, 18), +-}; +-static const unsigned int mmc0_data1_mux[] = { +- MMC0_D0_MARK, +-}; +-static const unsigned int mmc0_data4_pins[] = { +- /* D[0:3] */ +- RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), +- RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), +-}; +-static const unsigned int mmc0_data4_mux[] = { +- MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, +-}; +-static const unsigned int mmc0_data8_pins[] = { +- /* D[0:7] */ +- RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), +- RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), +- RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), +- RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), +-}; +-static const unsigned int mmc0_data8_mux[] = { +- MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, +- MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK, +-}; +-static const unsigned int mmc0_ctrl_pins[] = { +- /* CLK, CMD */ +- RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), +-}; +-static const unsigned int mmc0_ctrl_mux[] = { +- MMC0_CLK_MARK, MMC0_CMD_MARK, +-}; +-/* - MMCIF1 ----------------------------------------------------------------- */ +-static const unsigned int mmc1_data1_pins[] = { +- /* D[0] */ +- RCAR_GP_PIN(3, 26), +-}; +-static const unsigned int mmc1_data1_mux[] = { +- MMC1_D0_MARK, +-}; +-static const unsigned int mmc1_data4_pins[] = { +- /* D[0:3] */ +- RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), +- RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), +-}; +-static const unsigned int mmc1_data4_mux[] = { +- MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, +-}; +-static const unsigned int mmc1_data8_pins[] = { +- /* D[0:7] */ +- RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), +- RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), +- RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), +- RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), +-}; +-static const unsigned int mmc1_data8_mux[] = { +- MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, +- MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK, +-}; +-static const unsigned int mmc1_ctrl_pins[] = { +- /* CLK, CMD */ +- RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25), +-}; +-static const unsigned int mmc1_ctrl_mux[] = { +- MMC1_CLK_MARK, MMC1_CMD_MARK, +-}; + /* - SDHI0 ------------------------------------------------------------------ */ + static const unsigned int sdhi0_data1_pins[] = { + /* D0 */ +@@ -2618,6 +2589,35 @@ static const unsigned int sdhi3_wp_pins[] = { + static const unsigned int sdhi3_wp_mux[] = { + SD3_WP_MARK, + }; ++/* - TPU0 ------------------------------------------------------------------- */ ++static const unsigned int tpu0_to0_pins[] = { ++ /* TO */ ++ RCAR_GP_PIN(0, 20), ++}; ++static const unsigned int tpu0_to0_mux[] = { ++ TPU0TO0_MARK, ++}; ++static const unsigned int tpu0_to1_pins[] = { ++ /* TO */ ++ RCAR_GP_PIN(0, 21), ++}; ++static const unsigned int tpu0_to1_mux[] = { ++ TPU0TO1_MARK, ++}; ++static const unsigned int tpu0_to2_pins[] = { ++ /* TO */ ++ RCAR_GP_PIN(0, 22), ++}; ++static const unsigned int tpu0_to2_mux[] = { ++ TPU0TO2_MARK, ++}; ++static const unsigned int tpu0_to3_pins[] = { ++ /* TO */ ++ RCAR_GP_PIN(0, 23), ++}; ++static const unsigned int tpu0_to3_mux[] = { ++ TPU0TO3_MARK, ++}; + + static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(eth_link), +@@ -2752,6 +2752,31 @@ static const char * const eth_groups[] = { + "eth_rmii", + }; + ++static const char * const hscif0_groups[] = { ++ "hscif0_data", ++ "hscif0_clk", ++ "hscif0_ctrl", ++ "hscif0_data_b", ++ "hscif0_ctrl_b", ++ "hscif0_data_c", ++ "hscif0_ctrl_c", ++ "hscif0_data_d", ++ "hscif0_ctrl_d", ++ "hscif0_data_e", ++ "hscif0_ctrl_e", ++ "hscif0_data_f", ++ "hscif0_ctrl_f", ++}; ++ ++static const char * const hscif1_groups[] = { ++ "hscif1_data", ++ "hscif1_clk", ++ "hscif1_ctrl", ++ "hscif1_data_b", ++ "hscif1_clk_b", ++ "hscif1_ctrl_b", ++}; ++ + static const char * const intc_groups[] = { + "intc_irq0", + "intc_irq1", +@@ -2759,6 +2784,20 @@ static const char * const intc_groups[] = { + "intc_irq3", + }; + ++static const char * const mmc0_groups[] = { ++ "mmc0_data1", ++ "mmc0_data4", ++ "mmc0_data8", ++ "mmc0_ctrl", ++}; ++ ++static const char * const mmc1_groups[] = { ++ "mmc1_data1", ++ "mmc1_data4", ++ "mmc1_data8", ++ "mmc1_ctrl", ++}; ++ + static const char * const scif0_groups[] = { + "scif0_data", + "scif0_clk", +@@ -2778,31 +2817,6 @@ static const char * const scif1_groups[] = { + "scif1_clk_e", + }; + +-static const char * const hscif0_groups[] = { +- "hscif0_data", +- "hscif0_clk", +- "hscif0_ctrl", +- "hscif0_data_b", +- "hscif0_ctrl_b", +- "hscif0_data_c", +- "hscif0_ctrl_c", +- "hscif0_data_d", +- "hscif0_ctrl_d", +- "hscif0_data_e", +- "hscif0_ctrl_e", +- "hscif0_data_f", +- "hscif0_ctrl_f", +-}; +- +-static const char * const hscif1_groups[] = { +- "hscif1_data", +- "hscif1_clk", +- "hscif1_ctrl", +- "hscif1_data_b", +- "hscif1_clk_b", +- "hscif1_ctrl_b", +-}; +- + static const char * const scifa0_groups[] = { + "scifa0_data", + "scifa0_clk", +@@ -2872,27 +2886,6 @@ static const char * const scifb2_groups[] = { + "scifb2_data_c", + }; + +-static const char * const tpu0_groups[] = { +- "tpu0_to0", +- "tpu0_to1", +- "tpu0_to2", +- "tpu0_to3", +-}; +- +-static const char * const mmc0_groups[] = { +- "mmc0_data1", +- "mmc0_data4", +- "mmc0_data8", +- "mmc0_ctrl", +-}; +- +-static const char * const mmc1_groups[] = { +- "mmc1_data1", +- "mmc1_data4", +- "mmc1_data8", +- "mmc1_ctrl", +-}; +- + static const char * const sdhi0_groups[] = { + "sdhi0_data1", + "sdhi0_data4", +@@ -2925,6 +2918,13 @@ static const char * const sdhi3_groups[] = { + "sdhi3_wp", + }; + ++static const char * const tpu0_groups[] = { ++ "tpu0_to0", ++ "tpu0_to1", ++ "tpu0_to2", ++ "tpu0_to3", ++}; ++ + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(eth), + SH_PFC_FUNCTION(hscif0), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0569-sh-pfc-r8a7790-Add-MSIOF-pin-groups-and-functions.patch b/patches.renesas/0569-sh-pfc-r8a7790-Add-MSIOF-pin-groups-and-functions.patch new file mode 100644 index 00000000000..e1b84ffac85 --- /dev/null +++ b/patches.renesas/0569-sh-pfc-r8a7790-Add-MSIOF-pin-groups-and-functions.patch @@ -0,0 +1,285 @@ +From 58b9dde799cd3f3c6ccecb901611efdc50566ab0 Mon Sep 17 00:00:00 2001 +From: Kunihito Higashiyama <kunihito.higashiyama.ur@renesas.com> +Date: Fri, 28 Jun 2013 09:36:09 +0900 +Subject: sh-pfc: r8a7790: Add MSIOF pin groups and functions + +Signed-off-by: Kunihito Higashiyama <kunihito.higashiyama.ur@renesas.com> +Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit 4f47cc5e307db4b7219012878cb3f7a65eaa2f7c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 236 +++++++++++++++++++++++++++++++++++ + 1 file changed, 236 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +index e0337832..8e61ba0c 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -1989,6 +1989,178 @@ static const unsigned int mmc1_ctrl_pins[] = { + static const unsigned int mmc1_ctrl_mux[] = { + MMC1_CLK_MARK, MMC1_CMD_MARK, + }; ++/* - MSIOF0 ----------------------------------------------------------------- */ ++static const unsigned int msiof0_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(5, 12), ++}; ++static const unsigned int msiof0_clk_mux[] = { ++ MSIOF0_SCK_MARK, ++}; ++static const unsigned int msiof0_sync_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(5, 13), ++}; ++static const unsigned int msiof0_sync_mux[] = { ++ MSIOF0_SYNC_MARK, ++}; ++static const unsigned int msiof0_ss1_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(5, 14), ++}; ++static const unsigned int msiof0_ss1_mux[] = { ++ MSIOF0_SS1_MARK, ++}; ++static const unsigned int msiof0_ss2_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(5, 16), ++}; ++static const unsigned int msiof0_ss2_mux[] = { ++ MSIOF0_SS2_MARK, ++}; ++static const unsigned int msiof0_rx_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(5, 17), ++}; ++static const unsigned int msiof0_rx_mux[] = { ++ MSIOF0_RXD_MARK, ++}; ++static const unsigned int msiof0_tx_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(5, 15), ++}; ++static const unsigned int msiof0_tx_mux[] = { ++ MSIOF0_TXD_MARK, ++}; ++/* - MSIOF1 ----------------------------------------------------------------- */ ++static const unsigned int msiof1_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(4, 8), ++}; ++static const unsigned int msiof1_clk_mux[] = { ++ MSIOF1_SCK_MARK, ++}; ++static const unsigned int msiof1_sync_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(4, 9), ++}; ++static const unsigned int msiof1_sync_mux[] = { ++ MSIOF1_SYNC_MARK, ++}; ++static const unsigned int msiof1_ss1_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(4, 10), ++}; ++static const unsigned int msiof1_ss1_mux[] = { ++ MSIOF1_SS1_MARK, ++}; ++static const unsigned int msiof1_ss2_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(4, 11), ++}; ++static const unsigned int msiof1_ss2_mux[] = { ++ MSIOF1_SS2_MARK, ++}; ++static const unsigned int msiof1_rx_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(4, 13), ++}; ++static const unsigned int msiof1_rx_mux[] = { ++ MSIOF1_RXD_MARK, ++}; ++static const unsigned int msiof1_tx_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(4, 12), ++}; ++static const unsigned int msiof1_tx_mux[] = { ++ MSIOF1_TXD_MARK, ++}; ++/* - MSIOF2 ----------------------------------------------------------------- */ ++static const unsigned int msiof2_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(0, 27), ++}; ++static const unsigned int msiof2_clk_mux[] = { ++ MSIOF2_SCK_MARK, ++}; ++static const unsigned int msiof2_sync_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(0, 26), ++}; ++static const unsigned int msiof2_sync_mux[] = { ++ MSIOF2_SYNC_MARK, ++}; ++static const unsigned int msiof2_ss1_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(0, 30), ++}; ++static const unsigned int msiof2_ss1_mux[] = { ++ MSIOF2_SS1_MARK, ++}; ++static const unsigned int msiof2_ss2_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(0, 31), ++}; ++static const unsigned int msiof2_ss2_mux[] = { ++ MSIOF2_SS2_MARK, ++}; ++static const unsigned int msiof2_rx_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(0, 29), ++}; ++static const unsigned int msiof2_rx_mux[] = { ++ MSIOF2_RXD_MARK, ++}; ++static const unsigned int msiof2_tx_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(0, 28), ++}; ++static const unsigned int msiof2_tx_mux[] = { ++ MSIOF2_TXD_MARK, ++}; ++/* - MSIOF3 ----------------------------------------------------------------- */ ++static const unsigned int msiof3_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(5, 4), ++}; ++static const unsigned int msiof3_clk_mux[] = { ++ MSIOF3_SCK_MARK, ++}; ++static const unsigned int msiof3_sync_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(4, 30), ++}; ++static const unsigned int msiof3_sync_mux[] = { ++ MSIOF3_SYNC_MARK, ++}; ++static const unsigned int msiof3_ss1_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(4, 31), ++}; ++static const unsigned int msiof3_ss1_mux[] = { ++ MSIOF3_SS1_MARK, ++}; ++static const unsigned int msiof3_ss2_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(4, 27), ++}; ++static const unsigned int msiof3_ss2_mux[] = { ++ MSIOF3_SS2_MARK, ++}; ++static const unsigned int msiof3_rx_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(5, 2), ++}; ++static const unsigned int msiof3_rx_mux[] = { ++ MSIOF3_RXD_MARK, ++}; ++static const unsigned int msiof3_tx_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(5, 3), ++}; ++static const unsigned int msiof3_tx_mux[] = { ++ MSIOF3_TXD_MARK, ++}; + /* - SCIF0 ------------------------------------------------------------------ */ + static const unsigned int scif0_data_pins[] = { + /* RX, TX */ +@@ -2655,6 +2827,30 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(mmc1_data4), + SH_PFC_PIN_GROUP(mmc1_data8), + SH_PFC_PIN_GROUP(mmc1_ctrl), ++ SH_PFC_PIN_GROUP(msiof0_clk), ++ SH_PFC_PIN_GROUP(msiof0_sync), ++ SH_PFC_PIN_GROUP(msiof0_ss1), ++ SH_PFC_PIN_GROUP(msiof0_ss2), ++ SH_PFC_PIN_GROUP(msiof0_rx), ++ SH_PFC_PIN_GROUP(msiof0_tx), ++ SH_PFC_PIN_GROUP(msiof1_clk), ++ SH_PFC_PIN_GROUP(msiof1_sync), ++ SH_PFC_PIN_GROUP(msiof1_ss1), ++ SH_PFC_PIN_GROUP(msiof1_ss2), ++ SH_PFC_PIN_GROUP(msiof1_rx), ++ SH_PFC_PIN_GROUP(msiof1_tx), ++ SH_PFC_PIN_GROUP(msiof2_clk), ++ SH_PFC_PIN_GROUP(msiof2_sync), ++ SH_PFC_PIN_GROUP(msiof2_ss1), ++ SH_PFC_PIN_GROUP(msiof2_ss2), ++ SH_PFC_PIN_GROUP(msiof2_rx), ++ SH_PFC_PIN_GROUP(msiof2_tx), ++ SH_PFC_PIN_GROUP(msiof3_clk), ++ SH_PFC_PIN_GROUP(msiof3_sync), ++ SH_PFC_PIN_GROUP(msiof3_ss1), ++ SH_PFC_PIN_GROUP(msiof3_ss2), ++ SH_PFC_PIN_GROUP(msiof3_rx), ++ SH_PFC_PIN_GROUP(msiof3_tx), + SH_PFC_PIN_GROUP(scif0_data), + SH_PFC_PIN_GROUP(scif0_clk), + SH_PFC_PIN_GROUP(scif0_ctrl), +@@ -2798,6 +2994,42 @@ static const char * const mmc1_groups[] = { + "mmc1_ctrl", + }; + ++static const char * const msiof0_groups[] = { ++ "msiof0_clk", ++ "msiof0_sync", ++ "msiof0_ss1", ++ "msiof0_ss2", ++ "msiof0_rx", ++ "msiof0_tx", ++}; ++ ++static const char * const msiof1_groups[] = { ++ "msiof1_clk", ++ "msiof1_sync", ++ "msiof1_ss1", ++ "msiof1_ss2", ++ "msiof1_rx", ++ "msiof1_tx", ++}; ++ ++static const char * const msiof2_groups[] = { ++ "msiof2_clk", ++ "msiof2_sync", ++ "msiof2_ss1", ++ "msiof2_ss2", ++ "msiof2_rx", ++ "msiof2_tx", ++}; ++ ++static const char * const msiof3_groups[] = { ++ "msiof3_clk", ++ "msiof3_sync", ++ "msiof3_ss1", ++ "msiof3_ss2", ++ "msiof3_rx", ++ "msiof3_tx", ++}; ++ + static const char * const scif0_groups[] = { + "scif0_data", + "scif0_clk", +@@ -2932,6 +3164,10 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(mmc0), + SH_PFC_FUNCTION(mmc1), ++ SH_PFC_FUNCTION(msiof0), ++ SH_PFC_FUNCTION(msiof1), ++ SH_PFC_FUNCTION(msiof2), ++ SH_PFC_FUNCTION(msiof3), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scifa0), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0570-sh-pfc-r8a7790-Add-SCIF2-pin-groups-and-functions.patch b/patches.renesas/0570-sh-pfc-r8a7790-Add-SCIF2-pin-groups-and-functions.patch new file mode 100644 index 00000000000..b37e5f5e20e --- /dev/null +++ b/patches.renesas/0570-sh-pfc-r8a7790-Add-SCIF2-pin-groups-and-functions.patch @@ -0,0 +1,79 @@ +From 9ca134ca36d1bb919aeb3b36bc47090973776b94 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Wed, 24 Jul 2013 02:02:58 +0200 +Subject: sh-pfc: r8a7790: Add SCIF2 pin groups and functions + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit 2dbe7f2cc91d679cdf6290b53f76f763802224cd) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 32 ++++++++++++++++++++++++++++++++ + 1 file changed, 32 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +index 8e61ba0c..6fc99fcb 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -2254,6 +2254,28 @@ static const unsigned int scif1_clk_e_pins[] = { + static const unsigned int scif1_clk_e_mux[] = { + SCK1_E_MARK, + }; ++/* - SCIF2 ------------------------------------------------------------------ */ ++static const unsigned int scif2_data_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5), ++}; ++static const unsigned int scif2_data_mux[] = { ++ RX2_MARK, TX2_MARK, ++}; ++static const unsigned int scif2_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(5, 4), ++}; ++static const unsigned int scif2_clk_mux[] = { ++ SCK2_MARK, ++}; ++static const unsigned int scif2_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), ++}; ++static const unsigned int scif2_data_b_mux[] = { ++ RX2_B_MARK, TX2_B_MARK, ++}; + /* - SCIFA0 ----------------------------------------------------------------- */ + static const unsigned int scifa0_data_pins[] = { + /* RXD, TXD */ +@@ -2864,6 +2886,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(scif1_clk_d), + SH_PFC_PIN_GROUP(scif1_data_e), + SH_PFC_PIN_GROUP(scif1_clk_e), ++ SH_PFC_PIN_GROUP(scif2_data), ++ SH_PFC_PIN_GROUP(scif2_clk), ++ SH_PFC_PIN_GROUP(scif2_data_b), + SH_PFC_PIN_GROUP(scifa0_data), + SH_PFC_PIN_GROUP(scifa0_clk), + SH_PFC_PIN_GROUP(scifa0_ctrl), +@@ -3049,6 +3074,12 @@ static const char * const scif1_groups[] = { + "scif1_clk_e", + }; + ++static const char * const scif2_groups[] = { ++ "scif2_data", ++ "scif2_clk", ++ "scif2_data_b", ++}; ++ + static const char * const scifa0_groups[] = { + "scifa0_data", + "scifa0_clk", +@@ -3170,6 +3201,7 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(msiof3), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), ++ SH_PFC_FUNCTION(scif2), + SH_PFC_FUNCTION(scifa0), + SH_PFC_FUNCTION(scifa1), + SH_PFC_FUNCTION(scifa2), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0571-sh-pfc-r8a7790-Add-USB-pin-groups-and-functions.patch b/patches.renesas/0571-sh-pfc-r8a7790-Add-USB-pin-groups-and-functions.patch new file mode 100644 index 00000000000..a33f3b611f0 --- /dev/null +++ b/patches.renesas/0571-sh-pfc-r8a7790-Add-USB-pin-groups-and-functions.patch @@ -0,0 +1,91 @@ +From c68bac96b78409beb08dcaf2c3769ea5805d0f4f Mon Sep 17 00:00:00 2001 +From: Shinobu Uehara <shinobu.uehara.xc@renesas.com> +Date: Wed, 26 Jun 2013 09:39:34 +0900 +Subject: sh-pfc: r8a7790: Add USB pin groups and functions + +Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com> +Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit dac896e221d42316059fb87eb4b7bee226e7da5d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 42 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 42 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +index 6fc99fcb..f789dbd7 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -2812,6 +2812,30 @@ static const unsigned int tpu0_to3_pins[] = { + static const unsigned int tpu0_to3_mux[] = { + TPU0TO3_MARK, + }; ++/* - USB0 ------------------------------------------------------------------- */ ++static const unsigned int usb0_pins[] = { ++ /* PWEN, OVC/VBUS */ ++ RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), ++}; ++static const unsigned int usb0_mux[] = { ++ USB0_PWEN_MARK, USB0_OVC_VBUS_MARK, ++}; ++/* - USB1 ------------------------------------------------------------------- */ ++static const unsigned int usb1_pins[] = { ++ /* PWEN, OVC */ ++ RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21), ++}; ++static const unsigned int usb1_mux[] = { ++ USB1_PWEN_MARK, USB1_OVC_MARK, ++}; ++/* - USB2 ------------------------------------------------------------------- */ ++static const unsigned int usb2_pins[] = { ++ /* PWEN, OVC */ ++ RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), ++}; ++static const unsigned int usb2_mux[] = { ++ USB2_PWEN_MARK, USB2_OVC_MARK, ++}; + + static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(eth_link), +@@ -2964,6 +2988,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(tpu0_to1), + SH_PFC_PIN_GROUP(tpu0_to2), + SH_PFC_PIN_GROUP(tpu0_to3), ++ SH_PFC_PIN_GROUP(usb0), ++ SH_PFC_PIN_GROUP(usb1), ++ SH_PFC_PIN_GROUP(usb2), + }; + + static const char * const eth_groups[] = { +@@ -3188,6 +3215,18 @@ static const char * const tpu0_groups[] = { + "tpu0_to3", + }; + ++static const char * const usb0_groups[] = { ++ "usb0", ++}; ++ ++static const char * const usb1_groups[] = { ++ "usb1", ++}; ++ ++static const char * const usb2_groups[] = { ++ "usb2", ++}; ++ + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(eth), + SH_PFC_FUNCTION(hscif0), +@@ -3213,6 +3252,9 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(sdhi3), + SH_PFC_FUNCTION(tpu0), ++ SH_PFC_FUNCTION(usb0), ++ SH_PFC_FUNCTION(usb1), ++ SH_PFC_FUNCTION(usb2), + }; + + static struct pinmux_cfg_reg pinmux_config_regs[] = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0572-sh-pfc-r8a7790-Add-VIN-pin-groups-and-functions.patch b/patches.renesas/0572-sh-pfc-r8a7790-Add-VIN-pin-groups-and-functions.patch new file mode 100644 index 00000000000..dafa4388b4b --- /dev/null +++ b/patches.renesas/0572-sh-pfc-r8a7790-Add-VIN-pin-groups-and-functions.patch @@ -0,0 +1,155 @@ +From 3156bc0250eb2b27fd1ddfe2b4f404067d3c40db Mon Sep 17 00:00:00 2001 +From: Shinobu Uehara <shinobu.uehara.xc@renesas.com> +Date: Thu, 27 Jun 2013 19:38:02 +0900 +Subject: sh-pfc: r8a7790: Add VIN pin groups and functions + +Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com> +Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit e120cacfaac24d4de31b181371daaef6a5773ee3) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 106 +++++++++++++++++++++++++++++++++++ + 1 file changed, 106 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +index f789dbd7..763c031e 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -2836,6 +2836,84 @@ static const unsigned int usb2_pins[] = { + static const unsigned int usb2_mux[] = { + USB2_PWEN_MARK, USB2_OVC_MARK, + }; ++/* - VIN0 ------------------------------------------------------------------- */ ++static const unsigned int vin0_data_g_pins[] = { ++ RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), ++ RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), ++ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), ++}; ++static const unsigned int vin0_data_g_mux[] = { ++ VI0_G0_MARK, VI0_G1_MARK, VI0_G2_MARK, ++ VI0_G3_MARK, VI0_G4_MARK, VI0_G5_MARK, ++ VI0_G6_MARK, VI0_G7_MARK, ++}; ++static const unsigned int vin0_data_r_pins[] = { ++ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), ++ RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), ++ RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11), ++}; ++static const unsigned int vin0_data_r_mux[] = { ++ VI0_R0_MARK, VI0_R1_MARK, VI0_R2_MARK, ++ VI0_R3_MARK, VI0_R4_MARK, VI0_R5_MARK, ++ VI0_R6_MARK, VI0_R7_MARK, ++}; ++static const unsigned int vin0_data_b_pins[] = { ++ RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), ++ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), ++ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), ++}; ++static const unsigned int vin0_data_b_mux[] = { ++ VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, VI0_DATA2_VI0_B2_MARK, ++ VI0_DATA3_VI0_B3_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, ++ VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, ++}; ++static const unsigned int vin0_hsync_signal_pins[] = { ++ RCAR_GP_PIN(0, 12), ++}; ++static const unsigned int vin0_hsync_signal_mux[] = { ++ VI0_HSYNC_N_MARK, ++}; ++static const unsigned int vin0_vsync_signal_pins[] = { ++ RCAR_GP_PIN(0, 13), ++}; ++static const unsigned int vin0_vsync_signal_mux[] = { ++ VI0_VSYNC_N_MARK, ++}; ++static const unsigned int vin0_field_signal_pins[] = { ++ RCAR_GP_PIN(0, 15), ++}; ++static const unsigned int vin0_field_signal_mux[] = { ++ VI0_FIELD_MARK, ++}; ++static const unsigned int vin0_data_enable_pins[] = { ++ RCAR_GP_PIN(0, 14), ++}; ++static const unsigned int vin0_data_enable_mux[] = { ++ VI0_CLKENB_MARK, ++}; ++static const unsigned int vin0_clk_pins[] = { ++ RCAR_GP_PIN(2, 0), ++}; ++static const unsigned int vin0_clk_mux[] = { ++ VI0_CLK_MARK, ++}; ++/* - VIN1 ------------------------------------------------------------------- */ ++static const unsigned int vin1_data_pins[] = { ++ RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), ++ RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), ++ RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), ++}; ++static const unsigned int vin1_data_mux[] = { ++ VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, VI1_DATA2_VI1_B2_MARK, ++ VI1_DATA3_VI1_B3_MARK, VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, ++ VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK, ++}; ++static const unsigned int vin1_clk_pins[] = { ++ RCAR_GP_PIN(2, 9), ++}; ++static const unsigned int vin1_clk_mux[] = { ++ VI1_CLK_MARK, ++}; + + static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(eth_link), +@@ -2991,6 +3069,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(usb0), + SH_PFC_PIN_GROUP(usb1), + SH_PFC_PIN_GROUP(usb2), ++ SH_PFC_PIN_GROUP(vin0_data_g), ++ SH_PFC_PIN_GROUP(vin0_data_r), ++ SH_PFC_PIN_GROUP(vin0_data_b), ++ SH_PFC_PIN_GROUP(vin0_hsync_signal), ++ SH_PFC_PIN_GROUP(vin0_vsync_signal), ++ SH_PFC_PIN_GROUP(vin0_field_signal), ++ SH_PFC_PIN_GROUP(vin0_data_enable), ++ SH_PFC_PIN_GROUP(vin0_clk), ++ SH_PFC_PIN_GROUP(vin1_data), ++ SH_PFC_PIN_GROUP(vin1_clk), + }; + + static const char * const eth_groups[] = { +@@ -3227,6 +3315,22 @@ static const char * const usb2_groups[] = { + "usb2", + }; + ++static const char * const vin0_groups[] = { ++ "vin0_data_g", ++ "vin0_data_r", ++ "vin0_data_b", ++ "vin0_hsync_signal", ++ "vin0_vsync_signal", ++ "vin0_field_signal", ++ "vin0_data_enable", ++ "vin0_clk", ++}; ++ ++static const char * const vin1_groups[] = { ++ "vin1_data", ++ "vin1_clk", ++}; ++ + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(eth), + SH_PFC_FUNCTION(hscif0), +@@ -3255,6 +3359,8 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(usb0), + SH_PFC_FUNCTION(usb1), + SH_PFC_FUNCTION(usb2), ++ SH_PFC_FUNCTION(vin0), ++ SH_PFC_FUNCTION(vin1), + }; + + static struct pinmux_cfg_reg pinmux_config_regs[] = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0573-sh-pfc-r8a7790-Rename-DU1_DOTCLKIN-to-DU_DOTCLKIN1.patch b/patches.renesas/0573-sh-pfc-r8a7790-Rename-DU1_DOTCLKIN-to-DU_DOTCLKIN1.patch new file mode 100644 index 00000000000..d706adefe73 --- /dev/null +++ b/patches.renesas/0573-sh-pfc-r8a7790-Rename-DU1_DOTCLKIN-to-DU_DOTCLKIN1.patch @@ -0,0 +1,58 @@ +From c741fe4a50708738a1a235bd7cac43c134c5c62e Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Wed, 7 Aug 2013 14:02:22 +0200 +Subject: sh-pfc: r8a7790: Rename DU1_DOTCLKIN to DU_DOTCLKIN1 + +Name the DU clock input 1 consistently with clock inputs 0 and 2. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit f06812095e97af956c9fe8e0f82a5f6d5a26e5d2) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +index 763c031e..da3aaeb5 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -237,7 +237,7 @@ enum { + FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C, + FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C, + FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, +- FN_PCMWE_N, FN_IECLK_C, FN_DU1_DOTCLKIN, ++ FN_PCMWE_N, FN_IECLK_C, FN_DU_DOTCLKIN1, + FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK, + FN_ATACS00_N, FN_AVB_RXD1, + FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, +@@ -609,7 +609,7 @@ enum { + GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK, + STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK, + PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK, +- PCMWE_N_MARK, IECLK_C_MARK, DU1_DOTCLKIN_MARK, ++ PCMWE_N_MARK, IECLK_C_MARK, DU_DOTCLKIN1_MARK, + AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK, + ATACS00_N_MARK, AVB_RXD1_MARK, + VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK, +@@ -1214,7 +1214,7 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2), + PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N), + PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2), +- PINMUX_IPSR_DATA(IP7_26_25, DU1_DOTCLKIN), ++ PINMUX_IPSR_DATA(IP7_26_25, DU_DOTCLKIN1), + PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC), + PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C), + PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0), +@@ -3819,7 +3819,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { + /* IP7_28_27 [2] */ + FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0, + /* IP7_26_25 [2] */ +- FN_DU1_DOTCLKIN, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0, ++ FN_DU_DOTCLKIN1, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0, + /* IP7_24_22 [3] */ + FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C, + 0, 0, 0, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0574-sh-pfc-r8a7790-Add-DU-pin-groups-and-functions.patch b/patches.renesas/0574-sh-pfc-r8a7790-Add-DU-pin-groups-and-functions.patch new file mode 100644 index 00000000000..4d749346f84 --- /dev/null +++ b/patches.renesas/0574-sh-pfc-r8a7790-Add-DU-pin-groups-and-functions.patch @@ -0,0 +1,182 @@ +From a91129c353a70be41082050aad7a8c468c5924f9 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Wed, 7 Aug 2013 14:02:23 +0200 +Subject: sh-pfc: r8a7790: Add DU pin groups and functions + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit 62783b714f21a08b20acfaab1c13679e887ab66c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 134 +++++++++++++++++++++++++++++++++++ + 1 file changed, 134 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +index da3aaeb5..64fcc006 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -1725,6 +1725,104 @@ static struct sh_pfc_pin pinmux_pins[] = { + PINMUX_GPIO_GP_ALL(), + }; + ++/* - DU RGB ----------------------------------------------------------------- */ ++static const unsigned int du_rgb666_pins[] = { ++ /* R[7:2], G[7:2], B[7:2] */ ++ RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), ++ RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), ++ RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), ++ RCAR_GP_PIN(5, 7), RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), ++ RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11), ++ RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8), ++}; ++static const unsigned int du_rgb666_mux[] = { ++ DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK, ++ DU2_DR3_MARK, DU2_DR2_MARK, ++ DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK, ++ DU2_DG3_MARK, DU2_DG2_MARK, ++ DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK, ++ DU2_DB3_MARK, DU2_DB2_MARK, ++}; ++static const unsigned int du_rgb888_pins[] = { ++ /* R[7:0], G[7:0], B[7:0] */ ++ RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), ++ RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), ++ RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 28), RCAR_GP_PIN(5, 4), ++ RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 7), ++ RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), RCAR_GP_PIN(5, 1), ++ RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), ++ RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9), ++ RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5), ++}; ++static const unsigned int du_rgb888_mux[] = { ++ DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK, ++ DU2_DR3_MARK, DU2_DR2_MARK, DU2_DR1_MARK, DU2_DR0_MARK, ++ DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK, ++ DU2_DG3_MARK, DU2_DG2_MARK, DU2_DG1_MARK, DU2_DG0_MARK, ++ DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK, ++ DU2_DB3_MARK, DU2_DB2_MARK, DU2_DB1_MARK, DU2_DB0_MARK, ++}; ++static const unsigned int du_clk_out_0_pins[] = { ++ /* CLKOUT */ ++ RCAR_GP_PIN(5, 2), ++}; ++static const unsigned int du_clk_out_0_mux[] = { ++ DU0_DOTCLKOUT_MARK ++}; ++static const unsigned int du_clk_out_1_pins[] = { ++ /* CLKOUT */ ++ RCAR_GP_PIN(5, 3), ++}; ++static const unsigned int du_clk_out_1_mux[] = { ++ DU1_DOTCLKOUT_MARK ++}; ++static const unsigned int du_sync_0_pins[] = { ++ /* VSYNC, HSYNC, DISP */ ++ RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 0), ++}; ++static const unsigned int du_sync_0_mux[] = { ++ DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, ++ DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK ++}; ++static const unsigned int du_sync_1_pins[] = { ++ /* VSYNC, HSYNC, DISP */ ++ RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 16), ++}; ++static const unsigned int du_sync_1_mux[] = { ++ DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, ++ DU2_DISP_MARK ++}; ++static const unsigned int du_cde_pins[] = { ++ /* CDE */ ++ RCAR_GP_PIN(5, 17), ++}; ++static const unsigned int du_cde_mux[] = { ++ DU2_CDE_MARK, ++}; ++/* - DU0 -------------------------------------------------------------------- */ ++static const unsigned int du0_clk_in_pins[] = { ++ /* CLKIN */ ++ RCAR_GP_PIN(5, 26), ++}; ++static const unsigned int du0_clk_in_mux[] = { ++ DU_DOTCLKIN0_MARK ++}; ++/* - DU1 -------------------------------------------------------------------- */ ++static const unsigned int du1_clk_in_pins[] = { ++ /* CLKIN */ ++ RCAR_GP_PIN(5, 27), ++}; ++static const unsigned int du1_clk_in_mux[] = { ++ DU_DOTCLKIN1_MARK, ++}; ++/* - DU2 -------------------------------------------------------------------- */ ++static const unsigned int du2_clk_in_pins[] = { ++ /* CLKIN */ ++ RCAR_GP_PIN(5, 28), ++}; ++static const unsigned int du2_clk_in_mux[] = { ++ DU_DOTCLKIN2_MARK, ++}; + /* - ETH -------------------------------------------------------------------- */ + static const unsigned int eth_link_pins[] = { + /* LINK */ +@@ -2916,6 +3014,16 @@ static const unsigned int vin1_clk_mux[] = { + }; + + static const struct sh_pfc_pin_group pinmux_groups[] = { ++ SH_PFC_PIN_GROUP(du_rgb666), ++ SH_PFC_PIN_GROUP(du_rgb888), ++ SH_PFC_PIN_GROUP(du_clk_out_0), ++ SH_PFC_PIN_GROUP(du_clk_out_1), ++ SH_PFC_PIN_GROUP(du_sync_0), ++ SH_PFC_PIN_GROUP(du_sync_1), ++ SH_PFC_PIN_GROUP(du_cde), ++ SH_PFC_PIN_GROUP(du0_clk_in), ++ SH_PFC_PIN_GROUP(du1_clk_in), ++ SH_PFC_PIN_GROUP(du2_clk_in), + SH_PFC_PIN_GROUP(eth_link), + SH_PFC_PIN_GROUP(eth_magic), + SH_PFC_PIN_GROUP(eth_mdio), +@@ -3081,6 +3189,28 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(vin1_clk), + }; + ++static const char * const du_groups[] = { ++ "du_rgb666", ++ "du_rgb888", ++ "du_clk_out_0", ++ "du_clk_out_1", ++ "du_sync_0", ++ "du_sync_1", ++ "du_cde", ++}; ++ ++static const char * const du0_groups[] = { ++ "du0_clk_in", ++}; ++ ++static const char * const du1_groups[] = { ++ "du1_clk_in", ++}; ++ ++static const char * const du2_groups[] = { ++ "du2_clk_in", ++}; ++ + static const char * const eth_groups[] = { + "eth_link", + "eth_magic", +@@ -3332,6 +3462,10 @@ static const char * const vin1_groups[] = { + }; + + static const struct sh_pfc_function pinmux_functions[] = { ++ SH_PFC_FUNCTION(du), ++ SH_PFC_FUNCTION(du0), ++ SH_PFC_FUNCTION(du1), ++ SH_PFC_FUNCTION(du2), + SH_PFC_FUNCTION(eth), + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0575-pinctrl-sh-pfc-remove-unnecessary-platform_set_drvda.patch b/patches.renesas/0575-pinctrl-sh-pfc-remove-unnecessary-platform_set_drvda.patch new file mode 100644 index 00000000000..9f951b8c034 --- /dev/null +++ b/patches.renesas/0575-pinctrl-sh-pfc-remove-unnecessary-platform_set_drvda.patch @@ -0,0 +1,34 @@ +From 8ef5c5eca6e3ea29f45d86605d6b9ecd1795bc3f Mon Sep 17 00:00:00 2001 +From: Jingoo Han <jg1.han@samsung.com> +Date: Thu, 22 Aug 2013 11:00:55 +0900 +Subject: pinctrl: sh-pfc: remove unnecessary platform_set_drvdata() + +The driver core clears the driver data to NULL after device_release +or on probe failure. Thus, it is not needed to manually clear the +device driver data to NULL. + +Signed-off-by: Jingoo Han <jg1.han@samsung.com> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit db8ed174295f33e7c3441557a0caf296399ddea5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/core.c | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c +index 9e66614b..738f14f6 100644 +--- a/drivers/pinctrl/sh-pfc/core.c ++++ b/drivers/pinctrl/sh-pfc/core.c +@@ -539,8 +539,6 @@ static int sh_pfc_remove(struct platform_device *pdev) + if (pfc->info->ops && pfc->info->ops->exit) + pfc->info->ops->exit(pfc); + +- platform_set_drvdata(pdev, NULL); +- + return 0; + } + +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0576-mmc-sdhi-tmio-make-DMA-filter-implementation-specifi.patch b/patches.renesas/0576-mmc-sdhi-tmio-make-DMA-filter-implementation-specifi.patch new file mode 100644 index 00000000000..de979a53dba --- /dev/null +++ b/patches.renesas/0576-mmc-sdhi-tmio-make-DMA-filter-implementation-specifi.patch @@ -0,0 +1,114 @@ +From 857b84b21a9cc7e80ce10849bcbf565faa0e6098 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Fri, 26 Apr 2013 17:47:17 +0200 +Subject: mmc: sdhi/tmio: make DMA filter implementation specific + +So far only the SDHI implementation uses TMIO MMC with DMA. That way a DMA +channel filter function, defined in the TMIO driver wasn't a problem. +However, such a filter function is DMA controller specific. Since the SDHI +glue is only running on systems with the SHDMA DMA controller, the filter +function can safely be provided by it. Move it into SDHI. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Acked-by: Samuel Ortiz <sameo@linux.intel.com> +Signed-off-by: Chris Ball <cjb@laptop.org> +(cherry picked from commit 03a0675b2a112038a8a5078d8815e3f7356c7064) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/sh_mobile_sdhi.c | 9 +++++++++ + drivers/mmc/host/tmio_mmc_dma.c | 12 ++---------- + include/linux/mfd/tmio.h | 3 +++ + 3 files changed, 14 insertions(+), 10 deletions(-) + +diff --git a/drivers/mmc/host/sh_mobile_sdhi.c b/drivers/mmc/host/sh_mobile_sdhi.c +index fe908539..e0088d7f 100644 +--- a/drivers/mmc/host/sh_mobile_sdhi.c ++++ b/drivers/mmc/host/sh_mobile_sdhi.c +@@ -20,6 +20,7 @@ + + #include <linux/kernel.h> + #include <linux/clk.h> ++#include <linux/dmaengine.h> + #include <linux/slab.h> + #include <linux/mod_devicetable.h> + #include <linux/module.h> +@@ -124,6 +125,13 @@ static void sh_mobile_sdhi_cd_wakeup(const struct platform_device *pdev) + mmc_detect_change(dev_get_drvdata(&pdev->dev), msecs_to_jiffies(100)); + } + ++static bool sh_mobile_sdhi_filter(struct dma_chan *chan, void *arg) ++{ ++ dev_dbg(chan->device->dev, "%s: slave data %p\n", __func__, arg); ++ chan->private = arg; ++ return true; ++} ++ + static const struct sh_mobile_sdhi_ops sdhi_ops = { + .cd_wakeup = sh_mobile_sdhi_cd_wakeup, + }; +@@ -191,6 +199,7 @@ static int sh_mobile_sdhi_probe(struct platform_device *pdev) + priv->dma_priv.chan_priv_tx = &priv->param_tx.shdma_slave; + priv->dma_priv.chan_priv_rx = &priv->param_rx.shdma_slave; + priv->dma_priv.alignment_shift = 1; /* 2-byte alignment */ ++ priv->dma_priv.filter = sh_mobile_sdhi_filter; + mmc_data->dma = &priv->dma_priv; + } + } +diff --git a/drivers/mmc/host/tmio_mmc_dma.c b/drivers/mmc/host/tmio_mmc_dma.c +index 491e9ecc..de1264da 100644 +--- a/drivers/mmc/host/tmio_mmc_dma.c ++++ b/drivers/mmc/host/tmio_mmc_dma.c +@@ -261,14 +261,6 @@ out: + spin_unlock_irq(&host->lock); + } + +-/* It might be necessary to make filter MFD specific */ +-static bool tmio_mmc_filter(struct dma_chan *chan, void *arg) +-{ +- dev_dbg(chan->device->dev, "%s: slave data %p\n", __func__, arg); +- chan->private = arg; +- return true; +-} +- + void tmio_mmc_request_dma(struct tmio_mmc_host *host, struct tmio_mmc_data *pdata) + { + /* We can only either use DMA for both Tx and Rx or not use it at all */ +@@ -281,7 +273,7 @@ void tmio_mmc_request_dma(struct tmio_mmc_host *host, struct tmio_mmc_data *pdat + dma_cap_zero(mask); + dma_cap_set(DMA_SLAVE, mask); + +- host->chan_tx = dma_request_channel(mask, tmio_mmc_filter, ++ host->chan_tx = dma_request_channel(mask, pdata->dma->filter, + pdata->dma->chan_priv_tx); + dev_dbg(&host->pdev->dev, "%s: TX: got channel %p\n", __func__, + host->chan_tx); +@@ -289,7 +281,7 @@ void tmio_mmc_request_dma(struct tmio_mmc_host *host, struct tmio_mmc_data *pdat + if (!host->chan_tx) + return; + +- host->chan_rx = dma_request_channel(mask, tmio_mmc_filter, ++ host->chan_rx = dma_request_channel(mask, pdata->dma->filter, + pdata->dma->chan_priv_rx); + dev_dbg(&host->pdev->dev, "%s: RX: got channel %p\n", __func__, + host->chan_rx); +diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h +index 99bf3e66..0990d8a2 100644 +--- a/include/linux/mfd/tmio.h ++++ b/include/linux/mfd/tmio.h +@@ -81,10 +81,13 @@ int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base); + void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state); + void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state); + ++struct dma_chan; ++ + struct tmio_mmc_dma { + void *chan_priv_tx; + void *chan_priv_rx; + int alignment_shift; ++ bool (*filter)(struct dma_chan *chan, void *arg); + }; + + struct tmio_mmc_host; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0577-DMA-shdma-shdma_chan_filter-has-to-be-in-shdma-base..patch b/patches.renesas/0577-DMA-shdma-shdma_chan_filter-has-to-be-in-shdma-base..patch new file mode 100644 index 00000000000..422bf957ef6 --- /dev/null +++ b/patches.renesas/0577-DMA-shdma-shdma_chan_filter-has-to-be-in-shdma-base..patch @@ -0,0 +1,42 @@ +From 4f0502400a61a53dc0fb0bb73a15a45eb6eb2605 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Thu, 6 Jun 2013 17:37:14 +0200 +Subject: DMA: shdma: shdma_chan_filter() has to be in shdma-base.h + +shdma_chan_filter() is a function, provided by the shdma-base.c module, +move its declaration to the appropriate header. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Signed-off-by: Vinod Koul <vinod.koul@intel.com> +(cherry picked from commit d0951a23383d09276f7976ed34d8f1cede629b48) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + include/linux/sh_dma.h | 2 -- + include/linux/shdma-base.h | 1 + + 2 files changed, 1 insertion(+), 2 deletions(-) + +diff --git a/include/linux/sh_dma.h b/include/linux/sh_dma.h +index b64d6bec..4e83f3e0 100644 +--- a/include/linux/sh_dma.h ++++ b/include/linux/sh_dma.h +@@ -99,6 +99,4 @@ struct sh_dmae_pdata { + #define CHCR_TE 0x00000002 + #define CHCR_IE 0x00000004 + +-bool shdma_chan_filter(struct dma_chan *chan, void *arg); +- + #endif +diff --git a/include/linux/shdma-base.h b/include/linux/shdma-base.h +index a3728bf6..9a938971 100644 +--- a/include/linux/shdma-base.h ++++ b/include/linux/shdma-base.h +@@ -122,5 +122,6 @@ void shdma_chan_remove(struct shdma_chan *schan); + int shdma_init(struct device *dev, struct shdma_dev *sdev, + int chan_num); + void shdma_cleanup(struct shdma_dev *sdev); ++bool shdma_chan_filter(struct dma_chan *chan, void *arg); + + #endif +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0578-dmaengine-shdma-fix-a-build-failure-on-platforms-wit.patch b/patches.renesas/0578-dmaengine-shdma-fix-a-build-failure-on-platforms-wit.patch new file mode 100644 index 00000000000..fd9d502b7b5 --- /dev/null +++ b/patches.renesas/0578-dmaengine-shdma-fix-a-build-failure-on-platforms-wit.patch @@ -0,0 +1,44 @@ +From f9a419ae072591d1b554fe98134d4e11b20b1f4b Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Wed, 10 Jul 2013 11:09:12 +0900 +Subject: dmaengine: shdma: fix a build failure on platforms with no DMA + support + +On platforms with no support for the shdma dmaengine driver build is +currently failing with + +drivers/built-in.o: In function `sh_mobile_sdhi_probe': +drivers/mmc/host/sh_mobile_sdhi.c:170: undefined reference to`shdma_chan_filter' + +Fix the breakage by defining shdma_chan_filter to NULL in such +configurations. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +[horms+renesas@verge.net.au: Apply change to shdma-base.h instead of sh_dma.h] +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: Olof Johansson <olof@lixom.net> + +(cherry picked from commit ab116a4df4942c78c189d9b0744dd940ab9e00b9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + include/linux/shdma-base.h | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/include/linux/shdma-base.h b/include/linux/shdma-base.h +index 9a938971..e2127205 100644 +--- a/include/linux/shdma-base.h ++++ b/include/linux/shdma-base.h +@@ -122,6 +122,10 @@ void shdma_chan_remove(struct shdma_chan *schan); + int shdma_init(struct device *dev, struct shdma_dev *sdev, + int chan_num); + void shdma_cleanup(struct shdma_dev *sdev); ++#if IS_ENABLED(CONFIG_SH_DMAE_BASE) + bool shdma_chan_filter(struct dma_chan *chan, void *arg); ++#else ++#define shdma_chan_filter NULL ++#endif + + #endif +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0579-mmc-sdhi-tmio-switch-to-using-dmaengine_slave_config.patch b/patches.renesas/0579-mmc-sdhi-tmio-switch-to-using-dmaengine_slave_config.patch new file mode 100644 index 00000000000..426ae0465cd --- /dev/null +++ b/patches.renesas/0579-mmc-sdhi-tmio-switch-to-using-dmaengine_slave_config.patch @@ -0,0 +1,162 @@ +From 336d66a028afeefd95bfc12e7408d1daa489f618 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Fri, 26 Apr 2013 17:47:18 +0200 +Subject: mmc: sdhi/tmio: switch to using dmaengine_slave_config() + +This removes the deprecated use of the .private member of struct dma_chan +and switches the sdhi / tmio mmc driver to using the +dmaengine_slave_config() channel configuration method. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Acked-by: Samuel Ortiz <sameo@linux.intel.com> +Signed-off-by: Chris Ball <cjb@laptop.org> +(cherry picked from commit eec95ee22611f2207bd991d63a07884de28e6f56) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/sh_mobile_sdhi.c | 33 ++++++++++++++++----------------- + drivers/mmc/host/tmio_mmc_dma.c | 25 +++++++++++++++++++++++++ + include/linux/mfd/tmio.h | 2 ++ + 3 files changed, 43 insertions(+), 17 deletions(-) + +diff --git a/drivers/mmc/host/sh_mobile_sdhi.c b/drivers/mmc/host/sh_mobile_sdhi.c +index e0088d7f..7f45f628 100644 +--- a/drivers/mmc/host/sh_mobile_sdhi.c ++++ b/drivers/mmc/host/sh_mobile_sdhi.c +@@ -20,7 +20,6 @@ + + #include <linux/kernel.h> + #include <linux/clk.h> +-#include <linux/dmaengine.h> + #include <linux/slab.h> + #include <linux/mod_devicetable.h> + #include <linux/module.h> +@@ -47,8 +46,6 @@ static const struct sh_mobile_sdhi_of_data sh_mobile_sdhi_of_cfg[] = { + struct sh_mobile_sdhi { + struct clk *clk; + struct tmio_mmc_data mmc_data; +- struct sh_dmae_slave param_tx; +- struct sh_dmae_slave param_rx; + struct tmio_mmc_dma dma_priv; + }; + +@@ -125,13 +122,6 @@ static void sh_mobile_sdhi_cd_wakeup(const struct platform_device *pdev) + mmc_detect_change(dev_get_drvdata(&pdev->dev), msecs_to_jiffies(100)); + } + +-static bool sh_mobile_sdhi_filter(struct dma_chan *chan, void *arg) +-{ +- dev_dbg(chan->device->dev, "%s: slave data %p\n", __func__, arg); +- chan->private = arg; +- return true; +-} +- + static const struct sh_mobile_sdhi_ops sdhi_ops = { + .cd_wakeup = sh_mobile_sdhi_cd_wakeup, + }; +@@ -194,13 +184,22 @@ static int sh_mobile_sdhi_probe(struct platform_device *pdev) + mmc_data->get_cd = sh_mobile_sdhi_get_cd; + + if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0) { +- priv->param_tx.shdma_slave.slave_id = p->dma_slave_tx; +- priv->param_rx.shdma_slave.slave_id = p->dma_slave_rx; +- priv->dma_priv.chan_priv_tx = &priv->param_tx.shdma_slave; +- priv->dma_priv.chan_priv_rx = &priv->param_rx.shdma_slave; +- priv->dma_priv.alignment_shift = 1; /* 2-byte alignment */ +- priv->dma_priv.filter = sh_mobile_sdhi_filter; +- mmc_data->dma = &priv->dma_priv; ++ struct tmio_mmc_dma *dma_priv = &priv->dma_priv; ++ ++ /* ++ * Yes, we have to provide slave IDs twice to TMIO: ++ * once as a filter parameter and once for channel ++ * configuration as an explicit slave ID ++ */ ++ dma_priv->chan_priv_tx = (void *)p->dma_slave_tx; ++ dma_priv->chan_priv_rx = (void *)p->dma_slave_rx; ++ dma_priv->slave_id_tx = p->dma_slave_tx; ++ dma_priv->slave_id_rx = p->dma_slave_rx; ++ ++ dma_priv->alignment_shift = 1; /* 2-byte alignment */ ++ dma_priv->filter = shdma_chan_filter; ++ ++ mmc_data->dma = dma_priv; + } + } + +diff --git a/drivers/mmc/host/tmio_mmc_dma.c b/drivers/mmc/host/tmio_mmc_dma.c +index de1264da..a8aaa787 100644 +--- a/drivers/mmc/host/tmio_mmc_dma.c ++++ b/drivers/mmc/host/tmio_mmc_dma.c +@@ -268,7 +268,14 @@ void tmio_mmc_request_dma(struct tmio_mmc_host *host, struct tmio_mmc_data *pdat + return; + + if (!host->chan_tx && !host->chan_rx) { ++ struct resource *res = platform_get_resource(host->pdev, ++ IORESOURCE_MEM, 0); ++ struct dma_slave_config cfg = {}; + dma_cap_mask_t mask; ++ int ret; ++ ++ if (!res) ++ return; + + dma_cap_zero(mask); + dma_cap_set(DMA_SLAVE, mask); +@@ -281,6 +288,14 @@ void tmio_mmc_request_dma(struct tmio_mmc_host *host, struct tmio_mmc_data *pdat + if (!host->chan_tx) + return; + ++ cfg.slave_id = pdata->dma->slave_id_tx; ++ cfg.direction = DMA_MEM_TO_DEV; ++ cfg.dst_addr = res->start + (CTL_SD_DATA_PORT << host->bus_shift); ++ cfg.src_addr = 0; ++ ret = dmaengine_slave_config(host->chan_tx, &cfg); ++ if (ret < 0) ++ goto ecfgtx; ++ + host->chan_rx = dma_request_channel(mask, pdata->dma->filter, + pdata->dma->chan_priv_rx); + dev_dbg(&host->pdev->dev, "%s: RX: got channel %p\n", __func__, +@@ -289,6 +304,14 @@ void tmio_mmc_request_dma(struct tmio_mmc_host *host, struct tmio_mmc_data *pdat + if (!host->chan_rx) + goto ereqrx; + ++ cfg.slave_id = pdata->dma->slave_id_rx; ++ cfg.direction = DMA_DEV_TO_MEM; ++ cfg.src_addr = cfg.dst_addr; ++ cfg.dst_addr = 0; ++ ret = dmaengine_slave_config(host->chan_rx, &cfg); ++ if (ret < 0) ++ goto ecfgrx; ++ + host->bounce_buf = (u8 *)__get_free_page(GFP_KERNEL | GFP_DMA); + if (!host->bounce_buf) + goto ebouncebuf; +@@ -302,9 +325,11 @@ void tmio_mmc_request_dma(struct tmio_mmc_host *host, struct tmio_mmc_data *pdat + return; + + ebouncebuf: ++ecfgrx: + dma_release_channel(host->chan_rx); + host->chan_rx = NULL; + ereqrx: ++ecfgtx: + dma_release_channel(host->chan_tx); + host->chan_tx = NULL; + } +diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h +index 0990d8a2..ce351132 100644 +--- a/include/linux/mfd/tmio.h ++++ b/include/linux/mfd/tmio.h +@@ -86,6 +86,8 @@ struct dma_chan; + struct tmio_mmc_dma { + void *chan_priv_tx; + void *chan_priv_rx; ++ int slave_id_tx; ++ int slave_id_rx; + int alignment_shift; + bool (*filter)(struct dma_chan *chan, void *arg); + }; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0580-mmc-sdhi-tmio-add-DT-DMA-support.patch b/patches.renesas/0580-mmc-sdhi-tmio-add-DT-DMA-support.patch new file mode 100644 index 00000000000..83d76bb748e --- /dev/null +++ b/patches.renesas/0580-mmc-sdhi-tmio-add-DT-DMA-support.patch @@ -0,0 +1,124 @@ +From 54f5a1e20c0a7f6aa135dee201fe13a3e3eb508e Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Fri, 26 Apr 2013 17:47:19 +0200 +Subject: mmc: sdhi/tmio: add DT DMA support + +Add support for initialising DMA from the Device Tree. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Signed-off-by: Chris Ball <cjb@laptop.org> +(cherry picked from commit 87ae7bbebd9c9b32ad49dde1742aa68b5a86caf8) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/sh_mobile_sdhi.c | 14 +++++++------- + drivers/mmc/host/tmio_mmc_dma.c | 19 ++++++++++++------- + 2 files changed, 19 insertions(+), 14 deletions(-) + +diff --git a/drivers/mmc/host/sh_mobile_sdhi.c b/drivers/mmc/host/sh_mobile_sdhi.c +index 7f45f628..cc4c872c 100644 +--- a/drivers/mmc/host/sh_mobile_sdhi.c ++++ b/drivers/mmc/host/sh_mobile_sdhi.c +@@ -144,6 +144,7 @@ static int sh_mobile_sdhi_probe(struct platform_device *pdev) + struct tmio_mmc_host *host; + int irq, ret, i = 0; + bool multiplexed_isr = true; ++ struct tmio_mmc_dma *dma_priv; + + priv = devm_kzalloc(&pdev->dev, sizeof(struct sh_mobile_sdhi), GFP_KERNEL); + if (priv == NULL) { +@@ -152,6 +153,7 @@ static int sh_mobile_sdhi_probe(struct platform_device *pdev) + } + + mmc_data = &priv->mmc_data; ++ dma_priv = &priv->dma_priv; + + if (p) { + if (p->init) { +@@ -184,8 +186,6 @@ static int sh_mobile_sdhi_probe(struct platform_device *pdev) + mmc_data->get_cd = sh_mobile_sdhi_get_cd; + + if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0) { +- struct tmio_mmc_dma *dma_priv = &priv->dma_priv; +- + /* + * Yes, we have to provide slave IDs twice to TMIO: + * once as a filter parameter and once for channel +@@ -195,14 +195,14 @@ static int sh_mobile_sdhi_probe(struct platform_device *pdev) + dma_priv->chan_priv_rx = (void *)p->dma_slave_rx; + dma_priv->slave_id_tx = p->dma_slave_tx; + dma_priv->slave_id_rx = p->dma_slave_rx; +- +- dma_priv->alignment_shift = 1; /* 2-byte alignment */ +- dma_priv->filter = shdma_chan_filter; +- +- mmc_data->dma = dma_priv; + } + } + ++ dma_priv->alignment_shift = 1; /* 2-byte alignment */ ++ dma_priv->filter = shdma_chan_filter; ++ ++ mmc_data->dma = dma_priv; ++ + /* + * All SDHI blocks support 2-byte and larger block sizes in 4-bit + * bus width mode. +diff --git a/drivers/mmc/host/tmio_mmc_dma.c b/drivers/mmc/host/tmio_mmc_dma.c +index a8aaa787..65edb4a6 100644 +--- a/drivers/mmc/host/tmio_mmc_dma.c ++++ b/drivers/mmc/host/tmio_mmc_dma.c +@@ -264,7 +264,8 @@ out: + void tmio_mmc_request_dma(struct tmio_mmc_host *host, struct tmio_mmc_data *pdata) + { + /* We can only either use DMA for both Tx and Rx or not use it at all */ +- if (!pdata->dma) ++ if (!pdata->dma || (!host->pdev->dev.of_node && ++ (!pdata->dma->chan_priv_tx || !pdata->dma->chan_priv_rx))) + return; + + if (!host->chan_tx && !host->chan_rx) { +@@ -280,15 +281,17 @@ void tmio_mmc_request_dma(struct tmio_mmc_host *host, struct tmio_mmc_data *pdat + dma_cap_zero(mask); + dma_cap_set(DMA_SLAVE, mask); + +- host->chan_tx = dma_request_channel(mask, pdata->dma->filter, +- pdata->dma->chan_priv_tx); ++ host->chan_tx = dma_request_slave_channel_compat(mask, ++ pdata->dma->filter, pdata->dma->chan_priv_tx, ++ &host->pdev->dev, "tx"); + dev_dbg(&host->pdev->dev, "%s: TX: got channel %p\n", __func__, + host->chan_tx); + + if (!host->chan_tx) + return; + +- cfg.slave_id = pdata->dma->slave_id_tx; ++ if (pdata->dma->chan_priv_tx) ++ cfg.slave_id = pdata->dma->slave_id_tx; + cfg.direction = DMA_MEM_TO_DEV; + cfg.dst_addr = res->start + (CTL_SD_DATA_PORT << host->bus_shift); + cfg.src_addr = 0; +@@ -296,15 +299,17 @@ void tmio_mmc_request_dma(struct tmio_mmc_host *host, struct tmio_mmc_data *pdat + if (ret < 0) + goto ecfgtx; + +- host->chan_rx = dma_request_channel(mask, pdata->dma->filter, +- pdata->dma->chan_priv_rx); ++ host->chan_rx = dma_request_slave_channel_compat(mask, ++ pdata->dma->filter, pdata->dma->chan_priv_rx, ++ &host->pdev->dev, "rx"); + dev_dbg(&host->pdev->dev, "%s: RX: got channel %p\n", __func__, + host->chan_rx); + + if (!host->chan_rx) + goto ereqrx; + +- cfg.slave_id = pdata->dma->slave_id_rx; ++ if (pdata->dma->chan_priv_rx) ++ cfg.slave_id = pdata->dma->slave_id_rx; + cfg.direction = DMA_DEV_TO_MEM; + cfg.src_addr = cfg.dst_addr; + cfg.dst_addr = 0; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0581-mmc-remove-unnecessary-platform_set_drvdata.patch b/patches.renesas/0581-mmc-remove-unnecessary-platform_set_drvdata.patch new file mode 100644 index 00000000000..513bd1e676e --- /dev/null +++ b/patches.renesas/0581-mmc-remove-unnecessary-platform_set_drvdata.patch @@ -0,0 +1,372 @@ +From 43bbfa109a44c217889a72041060f570a2f92ffe Mon Sep 17 00:00:00 2001 +From: Jingoo Han <jg1.han@samsung.com> +Date: Mon, 6 May 2013 15:05:21 +0900 +Subject: mmc: remove unnecessary platform_set_drvdata() + +The driver core clears the driver data to NULL after device_release +or on probe failure, since commit 0998d0631001288a5974afc0b2a5f568bcdecb4d +(device-core: Ensure drvdata = NULL when no driver is bound). +Thus, it is not needed to manually clear the device driver data to NULL. + +Signed-off-by: Jingoo Han <jg1.han@samsung.com> +Acked-by: Sonic Zhang <sonic.zhang@analog.com> +Acked-by: Seungwon Jeon <tgih.jun@samsung.com> +Acked-by: Shawn Guo <shawn.guo@linaro.org> +Acked-by: Adrian Hunter <adrian.hunter@intel.com> +Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> +Acked-by: Jaehoon Chung <jh80.chung@samsung.com> +Acked-by: Viresh Kumar <viresh.kumar@linaro.org> +Acked-by: Tony Prisk <linux@prisktech.co.nz> +Signed-off-by: Chris Ball <cjb@laptop.org> +(cherry picked from commit 113a87f868b2f2e086790a68e8b9e41d8f0c3295) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/android-goldfish.c | 2 -- + drivers/mmc/host/atmel-mci.c | 2 -- + drivers/mmc/host/au1xmmc.c | 1 - + drivers/mmc/host/bfin_sdh.c | 2 -- + drivers/mmc/host/davinci_mmc.c | 1 - + drivers/mmc/host/dw_mmc-pltfm.c | 1 - + drivers/mmc/host/jz4740_mmc.c | 2 -- + drivers/mmc/host/mvsdio.c | 1 - + drivers/mmc/host/mxcmmc.c | 2 -- + drivers/mmc/host/mxs-mmc.c | 2 -- + drivers/mmc/host/omap.c | 2 -- + drivers/mmc/host/omap_hsmmc.c | 2 -- + drivers/mmc/host/pxamci.c | 2 -- + drivers/mmc/host/rtsx_pci_sdmmc.c | 2 -- + drivers/mmc/host/sdhci-acpi.c | 2 -- + drivers/mmc/host/sdhci-pltfm.c | 1 - + drivers/mmc/host/sdhci-pxav2.c | 2 -- + drivers/mmc/host/sdhci-pxav3.c | 2 -- + drivers/mmc/host/sdhci-s3c.c | 1 - + drivers/mmc/host/sdhci-spear.c | 2 -- + drivers/mmc/host/sh_mmcif.c | 2 -- + drivers/mmc/host/tmio_mmc.c | 2 -- + drivers/mmc/host/wmt-sdmmc.c | 2 -- + 23 files changed, 40 deletions(-) + +diff --git a/drivers/mmc/host/android-goldfish.c b/drivers/mmc/host/android-goldfish.c +index 7780c147..8b4e20a3 100644 +--- a/drivers/mmc/host/android-goldfish.c ++++ b/drivers/mmc/host/android-goldfish.c +@@ -546,8 +546,6 @@ static int goldfish_mmc_remove(struct platform_device *pdev) + { + struct goldfish_mmc_host *host = platform_get_drvdata(pdev); + +- platform_set_drvdata(pdev, NULL); +- + BUG_ON(host == NULL); + + mmc_remove_host(host->mmc); +diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c +index aca59d93..699c56b6 100644 +--- a/drivers/mmc/host/atmel-mci.c ++++ b/drivers/mmc/host/atmel-mci.c +@@ -2475,8 +2475,6 @@ static int __exit atmci_remove(struct platform_device *pdev) + struct atmel_mci *host = platform_get_drvdata(pdev); + unsigned int i; + +- platform_set_drvdata(pdev, NULL); +- + if (host->buffer) + dma_free_coherent(&pdev->dev, host->buf_size, + host->buffer, host->buf_phys_addr); +diff --git a/drivers/mmc/host/au1xmmc.c b/drivers/mmc/host/au1xmmc.c +index 127a8fad..df9becdd 100644 +--- a/drivers/mmc/host/au1xmmc.c ++++ b/drivers/mmc/host/au1xmmc.c +@@ -1149,7 +1149,6 @@ static int au1xmmc_remove(struct platform_device *pdev) + kfree(host->ioarea); + + mmc_free_host(host->mmc); +- platform_set_drvdata(pdev, NULL); + } + return 0; + } +diff --git a/drivers/mmc/host/bfin_sdh.c b/drivers/mmc/host/bfin_sdh.c +index fb4348c5..94fae2f1 100644 +--- a/drivers/mmc/host/bfin_sdh.c ++++ b/drivers/mmc/host/bfin_sdh.c +@@ -621,8 +621,6 @@ static int sdh_remove(struct platform_device *pdev) + { + struct mmc_host *mmc = platform_get_drvdata(pdev); + +- platform_set_drvdata(pdev, NULL); +- + if (mmc) { + struct sdh_host *host = mmc_priv(mmc); + +diff --git a/drivers/mmc/host/davinci_mmc.c b/drivers/mmc/host/davinci_mmc.c +index 3946a0eb..b1b82022 100644 +--- a/drivers/mmc/host/davinci_mmc.c ++++ b/drivers/mmc/host/davinci_mmc.c +@@ -1406,7 +1406,6 @@ static int __exit davinci_mmcsd_remove(struct platform_device *pdev) + { + struct mmc_davinci_host *host = platform_get_drvdata(pdev); + +- platform_set_drvdata(pdev, NULL); + if (host) { + mmc_davinci_cpufreq_deregister(host); + +diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c +index 41c27b74..37873f10 100644 +--- a/drivers/mmc/host/dw_mmc-pltfm.c ++++ b/drivers/mmc/host/dw_mmc-pltfm.c +@@ -72,7 +72,6 @@ static int dw_mci_pltfm_remove(struct platform_device *pdev) + { + struct dw_mci *host = platform_get_drvdata(pdev); + +- platform_set_drvdata(pdev, NULL); + dw_mci_remove(host); + return 0; + } +diff --git a/drivers/mmc/host/jz4740_mmc.c b/drivers/mmc/host/jz4740_mmc.c +index 2391c6b7..1c47b347 100644 +--- a/drivers/mmc/host/jz4740_mmc.c ++++ b/drivers/mmc/host/jz4740_mmc.c +@@ -932,7 +932,6 @@ err_release_mem_region: + err_clk_put: + clk_put(host->clk); + err_free_host: +- platform_set_drvdata(pdev, NULL); + mmc_free_host(mmc); + + return ret; +@@ -960,7 +959,6 @@ static int jz4740_mmc_remove(struct platform_device *pdev) + + clk_put(host->clk); + +- platform_set_drvdata(pdev, NULL); + mmc_free_host(host->mmc); + + return 0; +diff --git a/drivers/mmc/host/mvsdio.c b/drivers/mmc/host/mvsdio.c +index a1fcc1f9..3f26428d 100644 +--- a/drivers/mmc/host/mvsdio.c ++++ b/drivers/mmc/host/mvsdio.c +@@ -827,7 +827,6 @@ static int __exit mvsd_remove(struct platform_device *pdev) + clk_disable_unprepare(host->clk); + mmc_free_host(mmc); + +- platform_set_drvdata(pdev, NULL); + return 0; + } + +diff --git a/drivers/mmc/host/mxcmmc.c b/drivers/mmc/host/mxcmmc.c +index d5036353..786448a1 100644 +--- a/drivers/mmc/host/mxcmmc.c ++++ b/drivers/mmc/host/mxcmmc.c +@@ -1219,8 +1219,6 @@ static int mxcmci_remove(struct platform_device *pdev) + struct mmc_host *mmc = platform_get_drvdata(pdev); + struct mxcmci_host *host = mmc_priv(mmc); + +- platform_set_drvdata(pdev, NULL); +- + mmc_remove_host(mmc); + + if (host->vcc) +diff --git a/drivers/mmc/host/mxs-mmc.c b/drivers/mmc/host/mxs-mmc.c +index 4278a178..d38f0dae 100644 +--- a/drivers/mmc/host/mxs-mmc.c ++++ b/drivers/mmc/host/mxs-mmc.c +@@ -708,8 +708,6 @@ static int mxs_mmc_remove(struct platform_device *pdev) + + mmc_remove_host(mmc); + +- platform_set_drvdata(pdev, NULL); +- + if (ssp->dmach) + dma_release_channel(ssp->dmach); + +diff --git a/drivers/mmc/host/omap.c b/drivers/mmc/host/omap.c +index 4254975f..4b3e0eb7 100644 +--- a/drivers/mmc/host/omap.c ++++ b/drivers/mmc/host/omap.c +@@ -1500,8 +1500,6 @@ static int mmc_omap_remove(struct platform_device *pdev) + struct mmc_omap_host *host = platform_get_drvdata(pdev); + int i; + +- platform_set_drvdata(pdev, NULL); +- + BUG_ON(host == NULL); + + for (i = 0; i < host->nr_slots; i++) +diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c +index eccedc7d..18653214 100644 +--- a/drivers/mmc/host/omap_hsmmc.c ++++ b/drivers/mmc/host/omap_hsmmc.c +@@ -2047,7 +2047,6 @@ err_irq: + } + err1: + iounmap(host->base); +- platform_set_drvdata(pdev, NULL); + mmc_free_host(mmc); + err_alloc: + omap_hsmmc_gpio_free(pdata); +@@ -2093,7 +2092,6 @@ static int omap_hsmmc_remove(struct platform_device *pdev) + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res) + release_mem_region(res->start, resource_size(res)); +- platform_set_drvdata(pdev, NULL); + + return 0; + } +diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c +index 2b2f65ad..847b1996 100644 +--- a/drivers/mmc/host/pxamci.c ++++ b/drivers/mmc/host/pxamci.c +@@ -834,8 +834,6 @@ static int pxamci_remove(struct platform_device *pdev) + struct mmc_host *mmc = platform_get_drvdata(pdev); + int gpio_cd = -1, gpio_ro = -1, gpio_power = -1; + +- platform_set_drvdata(pdev, NULL); +- + if (mmc) { + struct pxamci_host *host = mmc_priv(mmc); + +diff --git a/drivers/mmc/host/rtsx_pci_sdmmc.c b/drivers/mmc/host/rtsx_pci_sdmmc.c +index ad13f424..82a35b91 100644 +--- a/drivers/mmc/host/rtsx_pci_sdmmc.c ++++ b/drivers/mmc/host/rtsx_pci_sdmmc.c +@@ -1316,8 +1316,6 @@ static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev) + mmc_remove_host(mmc); + mmc_free_host(mmc); + +- platform_set_drvdata(pdev, NULL); +- + dev_dbg(&(pdev->dev), + ": Realtek PCI-E SDMMC controller has been removed\n"); + +diff --git a/drivers/mmc/host/sdhci-acpi.c b/drivers/mmc/host/sdhci-acpi.c +index 706d9cb1..b1a6588b 100644 +--- a/drivers/mmc/host/sdhci-acpi.c ++++ b/drivers/mmc/host/sdhci-acpi.c +@@ -262,7 +262,6 @@ static int sdhci_acpi_probe(struct platform_device *pdev) + return 0; + + err_free: +- platform_set_drvdata(pdev, NULL); + sdhci_free_host(c->host); + return err; + } +@@ -281,7 +280,6 @@ static int sdhci_acpi_remove(struct platform_device *pdev) + + dead = (sdhci_readl(c->host, SDHCI_INT_STATUS) == ~0); + sdhci_remove_host(c->host, dead); +- platform_set_drvdata(pdev, NULL); + sdhci_free_host(c->host); + + return 0; +diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c +index cd0f1f68..252d1cea 100644 +--- a/drivers/mmc/host/sdhci-pltfm.c ++++ b/drivers/mmc/host/sdhci-pltfm.c +@@ -197,7 +197,6 @@ void sdhci_pltfm_free(struct platform_device *pdev) + iounmap(host->ioaddr); + release_mem_region(iomem->start, resource_size(iomem)); + sdhci_free_host(host); +- platform_set_drvdata(pdev, NULL); + } + EXPORT_SYMBOL_GPL(sdhci_pltfm_free); + +diff --git a/drivers/mmc/host/sdhci-pxav2.c b/drivers/mmc/host/sdhci-pxav2.c +index 6a3f702a..98b5145c 100644 +--- a/drivers/mmc/host/sdhci-pxav2.c ++++ b/drivers/mmc/host/sdhci-pxav2.c +@@ -253,8 +253,6 @@ static int sdhci_pxav2_remove(struct platform_device *pdev) + sdhci_pltfm_free(pdev); + kfree(pxa); + +- platform_set_drvdata(pdev, NULL); +- + return 0; + } + +diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c +index ce84208d..4b3f5e14 100644 +--- a/drivers/mmc/host/sdhci-pxav3.c ++++ b/drivers/mmc/host/sdhci-pxav3.c +@@ -340,8 +340,6 @@ static int sdhci_pxav3_remove(struct platform_device *pdev) + sdhci_pltfm_free(pdev); + kfree(pxa); + +- platform_set_drvdata(pdev, NULL); +- + return 0; + } + +diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c +index c6f6246a..926aaf6a 100644 +--- a/drivers/mmc/host/sdhci-s3c.c ++++ b/drivers/mmc/host/sdhci-s3c.c +@@ -745,7 +745,6 @@ static int sdhci_s3c_remove(struct platform_device *pdev) + clk_disable_unprepare(sc->clk_io); + + sdhci_free_host(host); +- platform_set_drvdata(pdev, NULL); + + return 0; + } +diff --git a/drivers/mmc/host/sdhci-spear.c b/drivers/mmc/host/sdhci-spear.c +index 7ae5b3ae..2dba9f8d 100644 +--- a/drivers/mmc/host/sdhci-spear.c ++++ b/drivers/mmc/host/sdhci-spear.c +@@ -258,7 +258,6 @@ static int sdhci_probe(struct platform_device *pdev) + return 0; + + set_drvdata: +- platform_set_drvdata(pdev, NULL); + sdhci_remove_host(host, 1); + free_host: + sdhci_free_host(host); +@@ -278,7 +277,6 @@ static int sdhci_remove(struct platform_device *pdev) + int dead = 0; + u32 scratch; + +- platform_set_drvdata(pdev, NULL); + scratch = readl(host->ioaddr + SDHCI_INT_STATUS); + if (scratch == (u32)-1) + dead = 1; +diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c +index e979d2db..36629a02 100644 +--- a/drivers/mmc/host/sh_mmcif.c ++++ b/drivers/mmc/host/sh_mmcif.c +@@ -1530,8 +1530,6 @@ static int sh_mmcif_remove(struct platform_device *pdev) + if (irq[1] >= 0) + free_irq(irq[1], host); + +- platform_set_drvdata(pdev, NULL); +- + clk_disable(host->hclk); + mmc_free_host(host->mmc); + pm_runtime_put_sync(&pdev->dev); +diff --git a/drivers/mmc/host/tmio_mmc.c b/drivers/mmc/host/tmio_mmc.c +index 139212e7..8860d4d2 100644 +--- a/drivers/mmc/host/tmio_mmc.c ++++ b/drivers/mmc/host/tmio_mmc.c +@@ -112,8 +112,6 @@ static int tmio_mmc_remove(struct platform_device *pdev) + const struct mfd_cell *cell = mfd_get_cell(pdev); + struct mmc_host *mmc = platform_get_drvdata(pdev); + +- platform_set_drvdata(pdev, NULL); +- + if (mmc) { + struct tmio_mmc_host *host = mmc_priv(mmc); + free_irq(platform_get_irq(pdev, 0), host); +diff --git a/drivers/mmc/host/wmt-sdmmc.c b/drivers/mmc/host/wmt-sdmmc.c +index 442f5766..34231d51 100644 +--- a/drivers/mmc/host/wmt-sdmmc.c ++++ b/drivers/mmc/host/wmt-sdmmc.c +@@ -927,8 +927,6 @@ static int wmt_mci_remove(struct platform_device *pdev) + + mmc_free_host(mmc); + +- platform_set_drvdata(pdev, NULL); +- + dev_info(&pdev->dev, "WMT MCI device removed\n"); + + return 0; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0582-mmc-tmio-postpone-controller-reset-during-resume.patch b/patches.renesas/0582-mmc-tmio-postpone-controller-reset-during-resume.patch new file mode 100644 index 00000000000..eb41e25cac8 --- /dev/null +++ b/patches.renesas/0582-mmc-tmio-postpone-controller-reset-during-resume.patch @@ -0,0 +1,62 @@ +From 6fa5c9807b85480145cbdcd4eb14844181a09117 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Mon, 22 Apr 2013 10:29:26 +0200 +Subject: mmc: tmio: postpone controller reset during resume + +When resuming, the tmio_mmc_host_resume() function is run when the +controller might still be powered down. Issuing a reset command to it at +that time has no effect. This patch postpones resetting the controller +until the first powering-up .set_ios() call. + +Reported-by: Nguyen Viet Dung <nv-dung@jinso.co.jp> +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Signed-off-by: Chris Ball <cjb@laptop.org> +(cherry picked from commit b22ffdcd25d67a07f2b5a75a7805826bfe8597f1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/tmio_mmc.h | 1 + + drivers/mmc/host/tmio_mmc_pio.c | 6 +++++- + 2 files changed, 6 insertions(+), 1 deletion(-) + +diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h +index d857f5c6..759d8f4f 100644 +--- a/drivers/mmc/host/tmio_mmc.h ++++ b/drivers/mmc/host/tmio_mmc.h +@@ -85,6 +85,7 @@ struct tmio_mmc_host { + unsigned long last_req_ts; + struct mutex ios_lock; /* protect set_ios() context */ + bool native_hotplug; ++ bool resuming; + }; + + int tmio_mmc_host_probe(struct tmio_mmc_host **host, +diff --git a/drivers/mmc/host/tmio_mmc_pio.c b/drivers/mmc/host/tmio_mmc_pio.c +index 5a1bc3b4..7e644da0 100644 +--- a/drivers/mmc/host/tmio_mmc_pio.c ++++ b/drivers/mmc/host/tmio_mmc_pio.c +@@ -862,6 +862,10 @@ static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) + if (!host->power) { + tmio_mmc_clk_update(mmc); + pm_runtime_get_sync(dev); ++ if (host->resuming) { ++ tmio_mmc_reset(host); ++ host->resuming = false; ++ } + } + tmio_mmc_set_clock(host, ios->clock); + if (!host->power) { +@@ -1154,10 +1158,10 @@ int tmio_mmc_host_resume(struct device *dev) + struct mmc_host *mmc = dev_get_drvdata(dev); + struct tmio_mmc_host *host = mmc_priv(mmc); + +- tmio_mmc_reset(host); + tmio_mmc_enable_dma(host, true); + + /* The MMC core will perform the complete set up */ ++ host->resuming = true; + return mmc_resume_host(mmc); + } + EXPORT_SYMBOL(tmio_mmc_host_resume); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0583-mmc-tmio-fix-unbalanced-power-on-calls-with-clock-ga.patch b/patches.renesas/0583-mmc-tmio-fix-unbalanced-power-on-calls-with-clock-ga.patch new file mode 100644 index 00000000000..7e9bf492118 --- /dev/null +++ b/patches.renesas/0583-mmc-tmio-fix-unbalanced-power-on-calls-with-clock-ga.patch @@ -0,0 +1,128 @@ +From 77b18fbebc4caf64698f6eea433f2e57f384441d Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Thu, 6 Jun 2013 16:35:44 +0200 +Subject: mmc: tmio: fix unbalanced power-on calls with clock-gating enabled + +With MMC clock gating enabled the MMC core currently calls MMC host driver's +.set_ios() method with .power_mode == MMC_POWER_ON and the clock value set +either to 0 or to the target rate. The tmio MMC driver then wrongly +translates the latter calls to card slot power-on requests, even when the +slot already was on. This patch fixes the driver to avoid needlessly +incrementing power-supplying regulator's use count. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Chris Ball <cjb@laptop.org> +(cherry picked from commit e83b7a8acc420923cbe8a30901d9eb60677f54fb) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/tmio_mmc.h | 20 ++++++++++++++++++-- + drivers/mmc/host/tmio_mmc_pio.c | 27 +++++++++++++++++---------- + 2 files changed, 35 insertions(+), 12 deletions(-) + +diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h +index 759d8f4f..86fd21e0 100644 +--- a/drivers/mmc/host/tmio_mmc.h ++++ b/drivers/mmc/host/tmio_mmc.h +@@ -40,6 +40,22 @@ + + struct tmio_mmc_data; + ++/* ++ * We differentiate between the following 3 power states: ++ * 1. card slot powered off, controller stopped. This is used, when either there ++ * is no card in the slot, or the card really has to be powered down. ++ * 2. card slot powered on, controller stopped. This is used, when a card is in ++ * the slot, but no activity is currently taking place. This is a power- ++ * saving mode with card-state preserved. This state can be entered, e.g. ++ * when MMC clock-gating is used. ++ * 3. card slot powered on, controller running. This is the actual active state. ++ */ ++enum tmio_mmc_power { ++ TMIO_MMC_OFF_STOP, /* card power off, controller stopped */ ++ TMIO_MMC_ON_STOP, /* card power on, controller stopped */ ++ TMIO_MMC_ON_RUN, /* card power on, controller running */ ++}; ++ + struct tmio_mmc_host { + void __iomem *ctl; + unsigned long bus_shift; +@@ -48,8 +64,8 @@ struct tmio_mmc_host { + struct mmc_data *data; + struct mmc_host *mmc; + +- /* Controller power state */ +- bool power; ++ /* Controller and card power state */ ++ enum tmio_mmc_power power; + + /* Callbacks for clock / power control */ + void (*set_pwr)(struct platform_device *host, int state); +diff --git a/drivers/mmc/host/tmio_mmc_pio.c b/drivers/mmc/host/tmio_mmc_pio.c +index 7e644da0..8e955ce2 100644 +--- a/drivers/mmc/host/tmio_mmc_pio.c ++++ b/drivers/mmc/host/tmio_mmc_pio.c +@@ -859,7 +859,7 @@ static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) + * is kept positive, so no suspending actually takes place. + */ + if (ios->power_mode == MMC_POWER_ON && ios->clock) { +- if (!host->power) { ++ if (host->power != TMIO_MMC_ON_RUN) { + tmio_mmc_clk_update(mmc); + pm_runtime_get_sync(dev); + if (host->resuming) { +@@ -868,27 +868,34 @@ static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) + } + } + tmio_mmc_set_clock(host, ios->clock); +- if (!host->power) { ++ if (host->power == TMIO_MMC_OFF_STOP) + /* power up SD card and the bus */ + tmio_mmc_power_on(host, ios->vdd); +- host->power = true; +- } ++ host->power = TMIO_MMC_ON_RUN; + /* start bus clock */ + tmio_mmc_clk_start(host); + } else if (ios->power_mode != MMC_POWER_UP) { +- if (host->power) { +- struct tmio_mmc_data *pdata = host->pdata; +- if (ios->power_mode == MMC_POWER_OFF) ++ struct tmio_mmc_data *pdata = host->pdata; ++ unsigned int old_power = host->power; ++ ++ if (old_power != TMIO_MMC_OFF_STOP) { ++ if (ios->power_mode == MMC_POWER_OFF) { + tmio_mmc_power_off(host); ++ host->power = TMIO_MMC_OFF_STOP; ++ } else { ++ host->power = TMIO_MMC_ON_STOP; ++ } ++ } ++ ++ if (old_power == TMIO_MMC_ON_RUN) { + tmio_mmc_clk_stop(host); +- host->power = false; + pm_runtime_put(dev); + if (pdata->clk_disable) + pdata->clk_disable(host->pdev); + } + } + +- if (host->power) { ++ if (host->power != TMIO_MMC_OFF_STOP) { + switch (ios->bus_width) { + case MMC_BUS_WIDTH_1: + sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x80e0); +@@ -1029,7 +1036,7 @@ int tmio_mmc_host_probe(struct tmio_mmc_host **host, + mmc->caps & MMC_CAP_NONREMOVABLE || + mmc->slot.cd_irq >= 0); + +- _host->power = false; ++ _host->power = TMIO_MMC_OFF_STOP; + pm_runtime_enable(&pdev->dev); + ret = pm_runtime_resume(&pdev->dev); + if (ret < 0) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0584-mmc-tmio-reset-the-controller-after-power-up.patch b/patches.renesas/0584-mmc-tmio-reset-the-controller-after-power-up.patch new file mode 100644 index 00000000000..bc51fef9ed4 --- /dev/null +++ b/patches.renesas/0584-mmc-tmio-reset-the-controller-after-power-up.patch @@ -0,0 +1,47 @@ +From d85ca2c63ef14f0af1ff528911fedc74bf22b0c6 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Thu, 6 Jun 2013 16:35:48 +0200 +Subject: mmc: tmio: reset the controller after power-up + +This fixes two reported problems: +1. after a system resume the controller isn't functioning until a command + runs on a timeout and a controller reset is performed. +2. if a card is ejected during a running write operation, its re-insertion + isn't detected. + +Reported-by: Nguyen Viet Dung <nv-dung@jinso.co.jp> +Reported-by: Nguyen Hong Ky <nh-ky@jinso.co.jp> +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Tested-by: Nguyen Viet Dung <nv-dung@jinso.co.jp> +Tested-by: Nguyen Hong Ky <nh-ky@jinso.co.jp> +Signed-off-by: Chris Ball <cjb@laptop.org> +(cherry picked from commit b9ec2744128d0940342b236e9018614ba8848118) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/tmio_mmc_pio.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/mmc/host/tmio_mmc_pio.c b/drivers/mmc/host/tmio_mmc_pio.c +index 8e955ce2..1912d6f4 100644 +--- a/drivers/mmc/host/tmio_mmc_pio.c ++++ b/drivers/mmc/host/tmio_mmc_pio.c +@@ -867,6 +867,8 @@ static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) + host->resuming = false; + } + } ++ if (host->power == TMIO_MMC_OFF_STOP) ++ tmio_mmc_reset(host); + tmio_mmc_set_clock(host, ios->clock); + if (host->power == TMIO_MMC_OFF_STOP) + /* power up SD card and the bus */ +@@ -1186,7 +1188,6 @@ int tmio_mmc_host_runtime_resume(struct device *dev) + struct mmc_host *mmc = dev_get_drvdata(dev); + struct tmio_mmc_host *host = mmc_priv(mmc); + +- tmio_mmc_reset(host); + tmio_mmc_enable_dma(host, true); + + return 0; +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0585-mmc-tmio-mmc-handle-mmc_of_parse-errors-during-probe.patch b/patches.renesas/0585-mmc-tmio-mmc-handle-mmc_of_parse-errors-during-probe.patch new file mode 100644 index 00000000000..8d571c7c92b --- /dev/null +++ b/patches.renesas/0585-mmc-tmio-mmc-handle-mmc_of_parse-errors-during-probe.patch @@ -0,0 +1,32 @@ +From e6115a664d26ca3e5a7935712d8a1de54aca4c74 Mon Sep 17 00:00:00 2001 +From: Simon Baatz <gmbnomis@gmail.com> +Date: Sun, 9 Jun 2013 22:14:13 +0200 +Subject: mmc: tmio-mmc: handle mmc_of_parse() errors during probe + +Signed-off-by: Simon Baatz <gmbnomis@gmail.com> +Acked-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Signed-off-by: Chris Ball <cjb@laptop.org> +(cherry picked from commit 274a752b1adc7e756acb283edc188f27fb3be6f8) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/tmio_mmc_pio.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/mmc/host/tmio_mmc_pio.c b/drivers/mmc/host/tmio_mmc_pio.c +index 1912d6f4..8486a22a 100644 +--- a/drivers/mmc/host/tmio_mmc_pio.c ++++ b/drivers/mmc/host/tmio_mmc_pio.c +@@ -1001,7 +1001,9 @@ int tmio_mmc_host_probe(struct tmio_mmc_host **host, + if (!mmc) + return -ENOMEM; + +- mmc_of_parse(mmc); ++ ret = mmc_of_parse(mmc); ++ if (ret < 0) ++ goto host_free; + + pdata->dev = &pdev->dev; + _host = mmc_priv(mmc); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0586-mmc-sh_mobile_sdhi-fix-error-return-code-in-sh_mobil.patch b/patches.renesas/0586-mmc-sh_mobile_sdhi-fix-error-return-code-in-sh_mobil.patch new file mode 100644 index 00000000000..0def3c35d19 --- /dev/null +++ b/patches.renesas/0586-mmc-sh_mobile_sdhi-fix-error-return-code-in-sh_mobil.patch @@ -0,0 +1,36 @@ +From 7de148776354cc4f743f5d999db427169f7d0d60 Mon Sep 17 00:00:00 2001 +From: Wei Yongjun <yongjun_wei@trendmicro.com.cn> +Date: Tue, 28 May 2013 13:26:50 +0800 +Subject: mmc: sh_mobile_sdhi: fix error return code in sh_mobile_sdhi_probe() + +Fix to return a negative error code instead of 0 when we cannot get +IRQ source by platform_get_irq(), as done elsewhere in this function. + +Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> +Acked-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Signed-off-by: Chris Ball <cjb@laptop.org> +(cherry picked from commit 7913ae7d10d82bf9d9af6be6c20281fceb695ec0) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/sh_mobile_sdhi.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/mmc/host/sh_mobile_sdhi.c b/drivers/mmc/host/sh_mobile_sdhi.c +index cc4c872c..a4316b34 100644 +--- a/drivers/mmc/host/sh_mobile_sdhi.c ++++ b/drivers/mmc/host/sh_mobile_sdhi.c +@@ -273,8 +273,10 @@ static int sh_mobile_sdhi_probe(struct platform_device *pdev) + } + + /* There must be at least one IRQ source */ +- if (!i) ++ if (!i) { ++ ret = irq; + goto eirq; ++ } + } + + dev_info(&pdev->dev, "%s base at 0x%08lx clock rate %u MHz\n", +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0587-mmc-host-use-platform_-get-set-_drvdata.patch b/patches.renesas/0587-mmc-host-use-platform_-get-set-_drvdata.patch new file mode 100644 index 00000000000..6d64c037a3c --- /dev/null +++ b/patches.renesas/0587-mmc-host-use-platform_-get-set-_drvdata.patch @@ -0,0 +1,83 @@ +From 520ac2583bb4f2690dc1c30ffdbd67e9a72afd7a Mon Sep 17 00:00:00 2001 +From: Jingoo Han <jg1.han@samsung.com> +Date: Mon, 3 Jun 2013 13:41:03 +0900 +Subject: mmc: host: use platform_{get,set}_drvdata() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Use the wrapper functions for getting and setting the driver data using +platform_device instead of using dev_{get,set}_drvdata() with &pdev->dev, +so we can directly pass a struct platform_device. + +Signed-off-by: Jingoo Han <jg1.han@samsung.com> +Acked-by: MichaÅ‚ MirosÅ‚aw <mirq-linux@rere.qmqm.pl> +Signed-off-by: Chris Ball <cjb@laptop.org> +(cherry picked from commit 6e2c0f3ffbb54547edcf1dd92a120ff37988a4d8) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/cb710-mmc.c | 2 +- + drivers/mmc/host/cb710-mmc.h | 2 +- + drivers/mmc/host/sh_mobile_sdhi.c | 6 +++--- + 3 files changed, 5 insertions(+), 5 deletions(-) + +diff --git a/drivers/mmc/host/cb710-mmc.c b/drivers/mmc/host/cb710-mmc.c +index 777ca204..9d6e2b84 100644 +--- a/drivers/mmc/host/cb710-mmc.c ++++ b/drivers/mmc/host/cb710-mmc.c +@@ -703,7 +703,7 @@ static int cb710_mmc_init(struct platform_device *pdev) + if (!mmc) + return -ENOMEM; + +- dev_set_drvdata(&pdev->dev, mmc); ++ platform_set_drvdata(pdev, mmc); + + /* harmless (maybe) magic */ + pci_read_config_dword(chip->pdev, 0x48, &val); +diff --git a/drivers/mmc/host/cb710-mmc.h b/drivers/mmc/host/cb710-mmc.h +index e845c776..8984ec87 100644 +--- a/drivers/mmc/host/cb710-mmc.h ++++ b/drivers/mmc/host/cb710-mmc.h +@@ -24,7 +24,7 @@ struct cb710_mmc_reader { + + static inline struct mmc_host *cb710_slot_to_mmc(struct cb710_slot *slot) + { +- return dev_get_drvdata(&slot->pdev.dev); ++ return platform_get_drvdata(&slot->pdev); + } + + static inline struct cb710_slot *cb710_mmc_to_slot(struct mmc_host *mmc) +diff --git a/drivers/mmc/host/sh_mobile_sdhi.c b/drivers/mmc/host/sh_mobile_sdhi.c +index a4316b34..ebea7492 100644 +--- a/drivers/mmc/host/sh_mobile_sdhi.c ++++ b/drivers/mmc/host/sh_mobile_sdhi.c +@@ -51,7 +51,7 @@ struct sh_mobile_sdhi { + + static int sh_mobile_sdhi_clk_enable(struct platform_device *pdev, unsigned int *f) + { +- struct mmc_host *mmc = dev_get_drvdata(&pdev->dev); ++ struct mmc_host *mmc = platform_get_drvdata(pdev); + struct tmio_mmc_host *host = mmc_priv(mmc); + struct sh_mobile_sdhi *priv = container_of(host->pdata, struct sh_mobile_sdhi, mmc_data); + int ret = clk_enable(priv->clk); +@@ -64,7 +64,7 @@ static int sh_mobile_sdhi_clk_enable(struct platform_device *pdev, unsigned int + + static void sh_mobile_sdhi_clk_disable(struct platform_device *pdev) + { +- struct mmc_host *mmc = dev_get_drvdata(&pdev->dev); ++ struct mmc_host *mmc = platform_get_drvdata(pdev); + struct tmio_mmc_host *host = mmc_priv(mmc); + struct sh_mobile_sdhi *priv = container_of(host->pdata, struct sh_mobile_sdhi, mmc_data); + clk_disable(priv->clk); +@@ -119,7 +119,7 @@ static int sh_mobile_sdhi_write16_hook(struct tmio_mmc_host *host, int addr) + + static void sh_mobile_sdhi_cd_wakeup(const struct platform_device *pdev) + { +- mmc_detect_change(dev_get_drvdata(&pdev->dev), msecs_to_jiffies(100)); ++ mmc_detect_change(platform_get_drvdata(pdev), msecs_to_jiffies(100)); + } + + static const struct sh_mobile_sdhi_ops sdhi_ops = { +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0588-mmc-tmio-fix-compiler-warning.patch b/patches.renesas/0588-mmc-tmio-fix-compiler-warning.patch new file mode 100644 index 00000000000..51a5fc391d6 --- /dev/null +++ b/patches.renesas/0588-mmc-tmio-fix-compiler-warning.patch @@ -0,0 +1,41 @@ +From 93c91e46ee06be1c10699765409debf224b90bf8 Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Mon, 8 Jul 2013 11:38:09 +0200 +Subject: mmc: tmio: fix compiler warning + +This patch fixes a compiler warning: + +drivers/mmc/host/tmio_mmc_pio.c: In function 'tmio_mmc_power_on': +drivers/mmc/host/tmio_mmc_pio.c:798:19: warning: ignoring return value of +'regulator_enable', declared with attribute warn_unused_result [-Wunused-result] + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Signed-off-by: Chris Ball <cjb@laptop.org> +(cherry picked from commit 6d1d6b4759112acf4c079eb3a0dd296bdbf61cf5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/tmio_mmc_pio.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/drivers/mmc/host/tmio_mmc_pio.c b/drivers/mmc/host/tmio_mmc_pio.c +index 8486a22a..17f7fa99 100644 +--- a/drivers/mmc/host/tmio_mmc_pio.c ++++ b/drivers/mmc/host/tmio_mmc_pio.c +@@ -795,9 +795,13 @@ static void tmio_mmc_power_on(struct tmio_mmc_host *host, unsigned short vdd) + * omap_hsmmc.c driver does. + */ + if (!IS_ERR(mmc->supply.vqmmc) && !ret) { +- regulator_enable(mmc->supply.vqmmc); ++ ret = regulator_enable(mmc->supply.vqmmc); + udelay(200); + } ++ ++ if (ret < 0) ++ dev_dbg(&host->pdev->dev, "Regulators failed to power up: %d\n", ++ ret); + } + + static void tmio_mmc_power_off(struct tmio_mmc_host *host) +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0589-mmc-sh_mobile_sdhi-Remove-.get_cd-callback-from-plat.patch b/patches.renesas/0589-mmc-sh_mobile_sdhi-Remove-.get_cd-callback-from-plat.patch new file mode 100644 index 00000000000..011b6489917 --- /dev/null +++ b/patches.renesas/0589-mmc-sh_mobile_sdhi-Remove-.get_cd-callback-from-plat.patch @@ -0,0 +1,60 @@ +From f26deeb9727c142a5fd85ce4baa4ca6d127a4842 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 8 Aug 2013 12:38:41 +0200 +Subject: mmc: sh_mobile_sdhi: Remove .get_cd() callback from platform data + +All platforms pass the CD GPIO number to the driver in the .cd_gpio +field. The .get_cd() callback isn't used anymore, remove it. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Acked-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Signed-off-by: Chris Ball <cjb@laptop.org> +(cherry picked from commit 57fcb523e5fce1c24e9c28b64f6e6dc3edf55073) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/sh_mobile_sdhi.c | 9 --------- + include/linux/mmc/sh_mobile_sdhi.h | 1 - + 2 files changed, 10 deletions(-) + +diff --git a/drivers/mmc/host/sh_mobile_sdhi.c b/drivers/mmc/host/sh_mobile_sdhi.c +index ebea7492..663a6727 100644 +--- a/drivers/mmc/host/sh_mobile_sdhi.c ++++ b/drivers/mmc/host/sh_mobile_sdhi.c +@@ -77,13 +77,6 @@ static void sh_mobile_sdhi_set_pwr(struct platform_device *pdev, int state) + p->set_pwr(pdev, state); + } + +-static int sh_mobile_sdhi_get_cd(struct platform_device *pdev) +-{ +- struct sh_mobile_sdhi_info *p = pdev->dev.platform_data; +- +- return p->get_cd(pdev); +-} +- + static int sh_mobile_sdhi_wait_idle(struct tmio_mmc_host *host) + { + int timeout = 1000; +@@ -182,8 +175,6 @@ static int sh_mobile_sdhi_probe(struct platform_device *pdev) + mmc_data->cd_gpio = p->cd_gpio; + if (p->set_pwr) + mmc_data->set_pwr = sh_mobile_sdhi_set_pwr; +- if (p->get_cd) +- mmc_data->get_cd = sh_mobile_sdhi_get_cd; + + if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0) { + /* +diff --git a/include/linux/mmc/sh_mobile_sdhi.h b/include/linux/mmc/sh_mobile_sdhi.h +index b76bcf06..f31c6926 100644 +--- a/include/linux/mmc/sh_mobile_sdhi.h ++++ b/include/linux/mmc/sh_mobile_sdhi.h +@@ -26,7 +26,6 @@ struct sh_mobile_sdhi_info { + u32 tmio_ocr_mask; /* available MMC voltages */ + unsigned int cd_gpio; + void (*set_pwr)(struct platform_device *pdev, int state); +- int (*get_cd)(struct platform_device *pdev); + + /* callbacks for board specific setup code */ + int (*init)(struct platform_device *pdev, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0590-mmc-sh_mobile_sdhi-Remove-.set_pwr-callback-from-pla.patch b/patches.renesas/0590-mmc-sh_mobile_sdhi-Remove-.set_pwr-callback-from-pla.patch new file mode 100644 index 00000000000..ba2e797d9f5 --- /dev/null +++ b/patches.renesas/0590-mmc-sh_mobile_sdhi-Remove-.set_pwr-callback-from-pla.patch @@ -0,0 +1,60 @@ +From 49d88ee21980f7ea5fde142e0585226d25d227d1 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 8 Aug 2013 12:38:42 +0200 +Subject: mmc: sh_mobile_sdhi: Remove .set_pwr() callback from platform data + +The .set_pwr() callback isn't used anymore as all platforms register +GPIO-controlled regulators. Remove it. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Acked-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Signed-off-by: Chris Ball <cjb@laptop.org> +(cherry picked from commit 1036563e1417c050993bbd48f20a84ff7c7cef99) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/sh_mobile_sdhi.c | 9 --------- + include/linux/mmc/sh_mobile_sdhi.h | 1 - + 2 files changed, 10 deletions(-) + +diff --git a/drivers/mmc/host/sh_mobile_sdhi.c b/drivers/mmc/host/sh_mobile_sdhi.c +index 663a6727..b3fd2c36 100644 +--- a/drivers/mmc/host/sh_mobile_sdhi.c ++++ b/drivers/mmc/host/sh_mobile_sdhi.c +@@ -70,13 +70,6 @@ static void sh_mobile_sdhi_clk_disable(struct platform_device *pdev) + clk_disable(priv->clk); + } + +-static void sh_mobile_sdhi_set_pwr(struct platform_device *pdev, int state) +-{ +- struct sh_mobile_sdhi_info *p = pdev->dev.platform_data; +- +- p->set_pwr(pdev, state); +-} +- + static int sh_mobile_sdhi_wait_idle(struct tmio_mmc_host *host) + { + int timeout = 1000; +@@ -173,8 +166,6 @@ static int sh_mobile_sdhi_probe(struct platform_device *pdev) + mmc_data->capabilities |= p->tmio_caps; + mmc_data->capabilities2 |= p->tmio_caps2; + mmc_data->cd_gpio = p->cd_gpio; +- if (p->set_pwr) +- mmc_data->set_pwr = sh_mobile_sdhi_set_pwr; + + if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0) { + /* +diff --git a/include/linux/mmc/sh_mobile_sdhi.h b/include/linux/mmc/sh_mobile_sdhi.h +index f31c6926..68927ae5 100644 +--- a/include/linux/mmc/sh_mobile_sdhi.h ++++ b/include/linux/mmc/sh_mobile_sdhi.h +@@ -25,7 +25,6 @@ struct sh_mobile_sdhi_info { + unsigned long tmio_caps2; + u32 tmio_ocr_mask; /* available MMC voltages */ + unsigned int cd_gpio; +- void (*set_pwr)(struct platform_device *pdev, int state); + + /* callbacks for board specific setup code */ + int (*init)(struct platform_device *pdev, +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0591-mmc-tmio-mmc-Remove-.get_cd-callback-from-platform-d.patch b/patches.renesas/0591-mmc-tmio-mmc-Remove-.get_cd-callback-from-platform-d.patch new file mode 100644 index 00000000000..937199061b8 --- /dev/null +++ b/patches.renesas/0591-mmc-tmio-mmc-Remove-.get_cd-callback-from-platform-d.patch @@ -0,0 +1,64 @@ +From 64d8f15c333fd6f609770cccce9bbc7b2e7b472a Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 8 Aug 2013 12:38:43 +0200 +Subject: mmc: tmio-mmc: Remove .get_cd() callback from platform data + +All platforms pass the CD GPIO number to the driver in the .cd_gpio +field. The .get_cd() callback isn't used anymore, remove it + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Acked-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Signed-off-by: Chris Ball <cjb@laptop.org> +(cherry picked from commit 2b63b341d42cd64ff40062447320d46cf3e7f0bb) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/tmio_mmc_pio.c | 16 +--------------- + include/linux/mfd/tmio.h | 1 - + 2 files changed, 1 insertion(+), 16 deletions(-) + +diff --git a/drivers/mmc/host/tmio_mmc_pio.c b/drivers/mmc/host/tmio_mmc_pio.c +index 17f7fa99..b3802256 100644 +--- a/drivers/mmc/host/tmio_mmc_pio.c ++++ b/drivers/mmc/host/tmio_mmc_pio.c +@@ -936,25 +936,11 @@ static int tmio_mmc_get_ro(struct mmc_host *mmc) + (sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_WRPROTECT)); + } + +-static int tmio_mmc_get_cd(struct mmc_host *mmc) +-{ +- struct tmio_mmc_host *host = mmc_priv(mmc); +- struct tmio_mmc_data *pdata = host->pdata; +- int ret = mmc_gpio_get_cd(mmc); +- if (ret >= 0) +- return ret; +- +- if (!pdata->get_cd) +- return -ENOSYS; +- else +- return pdata->get_cd(host->pdev); +-} +- + static const struct mmc_host_ops tmio_mmc_ops = { + .request = tmio_mmc_request, + .set_ios = tmio_mmc_set_ios, + .get_ro = tmio_mmc_get_ro, +- .get_cd = tmio_mmc_get_cd, ++ .get_cd = mmc_gpio_get_cd, + .enable_sdio_irq = tmio_mmc_enable_sdio_irq, + }; + +diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h +index ce351132..b22883d6 100644 +--- a/include/linux/mfd/tmio.h ++++ b/include/linux/mfd/tmio.h +@@ -108,7 +108,6 @@ struct tmio_mmc_data { + unsigned int cd_gpio; + void (*set_pwr)(struct platform_device *host, int state); + void (*set_clk_div)(struct platform_device *host, int state); +- int (*get_cd)(struct platform_device *host); + int (*write16_hook)(struct tmio_mmc_host *host, int addr); + /* clock management callbacks */ + int (*clk_enable)(struct platform_device *pdev, unsigned int *f); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0592-mmc-tmio-mmc-Remove-.set_pwr-callback-from-platform-.patch b/patches.renesas/0592-mmc-tmio-mmc-Remove-.set_pwr-callback-from-platform-.patch new file mode 100644 index 00000000000..229f70ce4ac --- /dev/null +++ b/patches.renesas/0592-mmc-tmio-mmc-Remove-.set_pwr-callback-from-platform-.patch @@ -0,0 +1,78 @@ +From 7e4e70d40fedf15556f00e0274114bec69d51f2a Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 8 Aug 2013 12:38:44 +0200 +Subject: mmc: tmio-mmc: Remove .set_pwr() callback from platform data + +The .set_pwr() callback isn't used anymore as all platforms register +GPIO-controlled regulators. Remove it. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Acked-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Signed-off-by: Chris Ball <cjb@laptop.org> +(cherry picked from commit 3af9d15c719017feb63fa99f89ac6009a5a3d467) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/tmio_mmc.h | 1 - + drivers/mmc/host/tmio_mmc_pio.c | 7 ------- + include/linux/mfd/tmio.h | 1 - + 3 files changed, 9 deletions(-) + +diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h +index 86fd21e0..39c2f451 100644 +--- a/drivers/mmc/host/tmio_mmc.h ++++ b/drivers/mmc/host/tmio_mmc.h +@@ -68,7 +68,6 @@ struct tmio_mmc_host { + enum tmio_mmc_power power; + + /* Callbacks for clock / power control */ +- void (*set_pwr)(struct platform_device *host, int state); + void (*set_clk_div)(struct platform_device *host, int state); + + /* pio related stuff */ +diff --git a/drivers/mmc/host/tmio_mmc_pio.c b/drivers/mmc/host/tmio_mmc_pio.c +index b3802256..67a3bf12 100644 +--- a/drivers/mmc/host/tmio_mmc_pio.c ++++ b/drivers/mmc/host/tmio_mmc_pio.c +@@ -777,9 +777,6 @@ static void tmio_mmc_power_on(struct tmio_mmc_host *host, unsigned short vdd) + + /* .set_ios() is returning void, so, no chance to report an error */ + +- if (host->set_pwr) +- host->set_pwr(host->pdev, 1); +- + if (!IS_ERR(mmc->supply.vmmc)) { + ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); + /* +@@ -813,9 +810,6 @@ static void tmio_mmc_power_off(struct tmio_mmc_host *host) + + if (!IS_ERR(mmc->supply.vmmc)) + mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); +- +- if (host->set_pwr) +- host->set_pwr(host->pdev, 0); + } + + /* Set MMC clock / power. +@@ -1002,7 +996,6 @@ int tmio_mmc_host_probe(struct tmio_mmc_host **host, + _host->pdev = pdev; + platform_set_drvdata(pdev, mmc); + +- _host->set_pwr = pdata->set_pwr; + _host->set_clk_div = pdata->set_clk_div; + + /* SD control register space size is 0x200, 0x400 for bus_shift=1 */ +diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h +index b22883d6..baa23464 100644 +--- a/include/linux/mfd/tmio.h ++++ b/include/linux/mfd/tmio.h +@@ -106,7 +106,6 @@ struct tmio_mmc_data { + struct tmio_mmc_dma *dma; + struct device *dev; + unsigned int cd_gpio; +- void (*set_pwr)(struct platform_device *host, int state); + void (*set_clk_div)(struct platform_device *host, int state); + int (*write16_hook)(struct tmio_mmc_host *host, int addr); + /* clock management callbacks */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0593-mmc-SDHI-add-DT-compatibility-strings-for-further-So.patch b/patches.renesas/0593-mmc-SDHI-add-DT-compatibility-strings-for-further-So.patch new file mode 100644 index 00000000000..baecb6c28b2 --- /dev/null +++ b/patches.renesas/0593-mmc-SDHI-add-DT-compatibility-strings-for-further-So.patch @@ -0,0 +1,38 @@ +From 86ff130cadc66806ab681cf6b122ae6ec58de81f Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Wed, 17 Jul 2013 10:22:50 +0900 +Subject: mmc: SDHI: add DT compatibility strings for further SoCs + +Add further OF compatibility strings to the SDHI driver to be able to +precisely control driver's behaviour on each of them. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Acked-by: Magnus Damm <damm@opensource.se> +Acked-by: Simon Horman <horms@verge.net.au> +Signed-off-by: Chris Ball <cjb@laptop.org> +(cherry picked from commit af99106ee9231b5382ee8c9a38899c5758bd6298) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/sh_mobile_sdhi.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/drivers/mmc/host/sh_mobile_sdhi.c b/drivers/mmc/host/sh_mobile_sdhi.c +index b3fd2c36..87ed3fb5 100644 +--- a/drivers/mmc/host/sh_mobile_sdhi.c ++++ b/drivers/mmc/host/sh_mobile_sdhi.c +@@ -115,7 +115,12 @@ static const struct sh_mobile_sdhi_ops sdhi_ops = { + static const struct of_device_id sh_mobile_sdhi_of_match[] = { + { .compatible = "renesas,shmobile-sdhi" }, + { .compatible = "renesas,sh7372-sdhi" }, ++ { .compatible = "renesas,sh73a0-sdhi", .data = &sh_mobile_sdhi_of_cfg[0], }, ++ { .compatible = "renesas,r8a73a4-sdhi", .data = &sh_mobile_sdhi_of_cfg[0], }, + { .compatible = "renesas,r8a7740-sdhi", .data = &sh_mobile_sdhi_of_cfg[0], }, ++ { .compatible = "renesas,r8a7778-sdhi", .data = &sh_mobile_sdhi_of_cfg[0], }, ++ { .compatible = "renesas,r8a7779-sdhi", .data = &sh_mobile_sdhi_of_cfg[0], }, ++ { .compatible = "renesas,r8a7790-sdhi", .data = &sh_mobile_sdhi_of_cfg[0], }, + {}, + }; + MODULE_DEVICE_TABLE(of, sh_mobile_sdhi_of_match); +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0594-Revert-mmc-tmio-mmc-Remove-.set_pwr-callback-from-pl.patch b/patches.renesas/0594-Revert-mmc-tmio-mmc-Remove-.set_pwr-callback-from-pl.patch new file mode 100644 index 00000000000..6150791ad14 --- /dev/null +++ b/patches.renesas/0594-Revert-mmc-tmio-mmc-Remove-.set_pwr-callback-from-pl.patch @@ -0,0 +1,77 @@ +From 4b27b3333d50a9a453ed10b60847e9d4f488ea22 Mon Sep 17 00:00:00 2001 +From: Chris Ball <cjb@laptop.org> +Date: Fri, 6 Sep 2013 07:29:05 -0400 +Subject: Revert "mmc: tmio-mmc: Remove .set_pwr() callback from platform data" + +This reverts commit 3af9d15c719017feb63fa99f89ac6009a5a3d467, which +causes a build failure: + +drivers/mfd/asic3.c:724:2: error: unknown field 'set_pwr' specified in initializer + +(cherry picked from commit 9d731e7539713acc0ec7b67a5a91357c455d2334) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/tmio_mmc.h | 1 + + drivers/mmc/host/tmio_mmc_pio.c | 7 +++++++ + include/linux/mfd/tmio.h | 1 + + 3 files changed, 9 insertions(+) + +diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h +index 39c2f451..86fd21e0 100644 +--- a/drivers/mmc/host/tmio_mmc.h ++++ b/drivers/mmc/host/tmio_mmc.h +@@ -68,6 +68,7 @@ struct tmio_mmc_host { + enum tmio_mmc_power power; + + /* Callbacks for clock / power control */ ++ void (*set_pwr)(struct platform_device *host, int state); + void (*set_clk_div)(struct platform_device *host, int state); + + /* pio related stuff */ +diff --git a/drivers/mmc/host/tmio_mmc_pio.c b/drivers/mmc/host/tmio_mmc_pio.c +index 67a3bf12..b3802256 100644 +--- a/drivers/mmc/host/tmio_mmc_pio.c ++++ b/drivers/mmc/host/tmio_mmc_pio.c +@@ -777,6 +777,9 @@ static void tmio_mmc_power_on(struct tmio_mmc_host *host, unsigned short vdd) + + /* .set_ios() is returning void, so, no chance to report an error */ + ++ if (host->set_pwr) ++ host->set_pwr(host->pdev, 1); ++ + if (!IS_ERR(mmc->supply.vmmc)) { + ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); + /* +@@ -810,6 +813,9 @@ static void tmio_mmc_power_off(struct tmio_mmc_host *host) + + if (!IS_ERR(mmc->supply.vmmc)) + mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); ++ ++ if (host->set_pwr) ++ host->set_pwr(host->pdev, 0); + } + + /* Set MMC clock / power. +@@ -996,6 +1002,7 @@ int tmio_mmc_host_probe(struct tmio_mmc_host **host, + _host->pdev = pdev; + platform_set_drvdata(pdev, mmc); + ++ _host->set_pwr = pdata->set_pwr; + _host->set_clk_div = pdata->set_clk_div; + + /* SD control register space size is 0x200, 0x400 for bus_shift=1 */ +diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h +index baa23464..b22883d6 100644 +--- a/include/linux/mfd/tmio.h ++++ b/include/linux/mfd/tmio.h +@@ -106,6 +106,7 @@ struct tmio_mmc_data { + struct tmio_mmc_dma *dma; + struct device *dev; + unsigned int cd_gpio; ++ void (*set_pwr)(struct platform_device *host, int state); + void (*set_clk_div)(struct platform_device *host, int state); + int (*write16_hook)(struct tmio_mmc_host *host, int addr); + /* clock management callbacks */ +-- +1.8.4.3.gca3854a + diff --git a/patches.renesas/0595-ARM-shmobile-update-SDHI-DT-compatibility-string-to-.patch b/patches.renesas/0595-ARM-shmobile-update-SDHI-DT-compatibility-string-to-.patch new file mode 100644 index 00000000000..f13d52518ce --- /dev/null +++ b/patches.renesas/0595-ARM-shmobile-update-SDHI-DT-compatibility-string-to-.patch @@ -0,0 +1,186 @@ +From 9a0abd69551523478851347de9c18a038357241e Mon Sep 17 00:00:00 2001 +From: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Thu, 29 Aug 2013 17:14:49 +0200 +Subject: ARM: shmobile: update SDHI DT compatibility string to the + <unit>-<soc> format + +Currently DT compatibility strings of both types can be found in the kernel +sources: <unit>-<soc> and <soc>-<unit>, whereas a unique format should be +followed and the former one is preferred. This patch converts the SDHI +MMC driver and its users to the common standard. This is safe for now, since +ATM no real products are using this driver with DT. + +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> +Acked-by: Chris Ball <cjb@laptop.org> +[Removed r8a7740.dtsi portion as it is not applicable] +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit df1d0584b2292df5b9d576d7e5246e94616220a1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 17 ++++++++++------- + arch/arm/boot/dts/r8a73a4.dtsi | 6 +++--- + arch/arm/boot/dts/r8a7790.dtsi | 8 ++++---- + arch/arm/boot/dts/sh73a0.dtsi | 6 +++--- + drivers/mmc/host/sh_mobile_sdhi.c | 16 ++++++++-------- + 5 files changed, 28 insertions(+), 25 deletions(-) + +diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt +index df204e18..6a2a1160 100644 +--- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt ++++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt +@@ -9,12 +9,15 @@ compulsory and any optional properties, common to all SD/MMC drivers, as + described in mmc.txt, can be used. Additionally the following tmio_mmc-specific + optional bindings can be used. + ++Required properties: ++- compatible: "renesas,sdhi-shmobile" - a generic sh-mobile SDHI unit ++ "renesas,sdhi-sh7372" - SDHI IP on SH7372 SoC ++ "renesas,sdhi-sh73a0" - SDHI IP on SH73A0 SoC ++ "renesas,sdhi-r8a73a4" - SDHI IP on R8A73A4 SoC ++ "renesas,sdhi-r8a7740" - SDHI IP on R8A7740 SoC ++ "renesas,sdhi-r8a7778" - SDHI IP on R8A7778 SoC ++ "renesas,sdhi-r8a7779" - SDHI IP on R8A7779 SoC ++ "renesas,sdhi-r8a7790" - SDHI IP on R8A7790 SoC ++ + Optional properties: + - toshiba,mmc-wrprotect-disable: write-protect detection is unavailable +- +-When used with Renesas SDHI hardware, the following compatibility strings +-configure various model-specific properties: +- +-"renesas,sh7372-sdhi": (default) compatible with SH7372 +-"renesas,r8a7740-sdhi": compatible with R8A7740: certain MMC/SD commands have to +- wait for the interface to become idle. +diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi +index 6c26caa8..658fcc53 100644 +--- a/arch/arm/boot/dts/r8a73a4.dtsi ++++ b/arch/arm/boot/dts/r8a73a4.dtsi +@@ -193,7 +193,7 @@ + }; + + sdhi0: sdhi@ee100000 { +- compatible = "renesas,r8a73a4-sdhi"; ++ compatible = "renesas,sdhi-r8a73a4"; + reg = <0 0xee100000 0 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 165 4>; +@@ -202,7 +202,7 @@ + }; + + sdhi1: sdhi@ee120000 { +- compatible = "renesas,r8a73a4-sdhi"; ++ compatible = "renesas,sdhi-r8a73a4"; + reg = <0 0xee120000 0 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 166 4>; +@@ -211,7 +211,7 @@ + }; + + sdhi2: sdhi@ee140000 { +- compatible = "renesas,r8a73a4-sdhi"; ++ compatible = "renesas,sdhi-r8a73a4"; + reg = <0 0xee140000 0 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 167 4>; +diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi +index 98513984..413b4c29 100644 +--- a/arch/arm/boot/dts/r8a7790.dtsi ++++ b/arch/arm/boot/dts/r8a7790.dtsi +@@ -151,7 +151,7 @@ + }; + + sdhi0: sdhi@ee100000 { +- compatible = "renesas,r8a7790-sdhi"; ++ compatible = "renesas,sdhi-r8a7790"; + reg = <0 0xee100000 0 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 165 4>; +@@ -160,7 +160,7 @@ + }; + + sdhi1: sdhi@ee120000 { +- compatible = "renesas,r8a7790-sdhi"; ++ compatible = "renesas,sdhi-r8a7790"; + reg = <0 0xee120000 0 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 166 4>; +@@ -169,7 +169,7 @@ + }; + + sdhi2: sdhi@ee140000 { +- compatible = "renesas,r8a7790-sdhi"; ++ compatible = "renesas,sdhi-r8a7790"; + reg = <0 0xee140000 0 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 167 4>; +@@ -178,7 +178,7 @@ + }; + + sdhi3: sdhi@ee160000 { +- compatible = "renesas,r8a7790-sdhi"; ++ compatible = "renesas,sdhi-r8a7790"; + reg = <0 0xee160000 0 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 168 4>; +diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi +index ba59a587..3955c760 100644 +--- a/arch/arm/boot/dts/sh73a0.dtsi ++++ b/arch/arm/boot/dts/sh73a0.dtsi +@@ -196,7 +196,7 @@ + }; + + sdhi0: sdhi@ee100000 { +- compatible = "renesas,r8a7740-sdhi"; ++ compatible = "renesas,sdhi-r8a7740"; + reg = <0xee100000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 83 4 +@@ -208,7 +208,7 @@ + + /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */ + sdhi1: sdhi@ee120000 { +- compatible = "renesas,r8a7740-sdhi"; ++ compatible = "renesas,sdhi-r8a7740"; + reg = <0xee120000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 88 4 +@@ -219,7 +219,7 @@ + }; + + sdhi2: sdhi@ee140000 { +- compatible = "renesas,r8a7740-sdhi"; ++ compatible = "renesas,sdhi-r8a7740"; + reg = <0xee140000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 104 4 +diff --git a/drivers/mmc/host/sh_mobile_sdhi.c b/drivers/mmc/host/sh_mobile_sdhi.c +index 87ed3fb5..f344659d 100644 +--- a/drivers/mmc/host/sh_mobile_sdhi.c ++++ b/drivers/mmc/host/sh_mobile_sdhi.c +@@ -113,14 +113,14 @@ static const struct sh_mobile_sdhi_ops sdhi_ops = { + }; + + static const struct of_device_id sh_mobile_sdhi_of_match[] = { +- { .compatible = "renesas,shmobile-sdhi" }, +- { .compatible = "renesas,sh7372-sdhi" }, +- { .compatible = "renesas,sh73a0-sdhi", .data = &sh_mobile_sdhi_of_cfg[0], }, +- { .compatible = "renesas,r8a73a4-sdhi", .data = &sh_mobile_sdhi_of_cfg[0], }, +- { .compatible = "renesas,r8a7740-sdhi", .data = &sh_mobile_sdhi_of_cfg[0], }, +- { .compatible = "renesas,r8a7778-sdhi", .data = &sh_mobile_sdhi_of_cfg[0], }, +- { .compatible = "renesas,r8a7779-sdhi", .data = &sh_mobile_sdhi_of_cfg[0], }, +- { .compatible = "renesas,r8a7790-sdhi", .data = &sh_mobile_sdhi_of_cfg[0], }, ++ { .compatible = "renesas,sdhi-shmobile" }, ++ { .compatible = "renesas,sdhi-sh7372" }, ++ { .compatible = "renesas,sdhi-sh73a0", .data = &sh_mobile_sdhi_of_cfg[0], }, ++ { .compatible = "renesas,sdhi-r8a73a4", .data = &sh_mobile_sdhi_of_cfg[0], }, ++ { .compatible = "renesas,sdhi-r8a7740", .data = &sh_mobile_sdhi_of_cfg[0], }, ++ { .compatible = "renesas,sdhi-r8a7778", .data = &sh_mobile_sdhi_of_cfg[0], }, ++ { .compatible = "renesas,sdhi-r8a7779", .data = &sh_mobile_sdhi_of_cfg[0], }, ++ { .compatible = "renesas,sdhi-r8a7790", .data = &sh_mobile_sdhi_of_cfg[0], }, + {}, + }; + MODULE_DEVICE_TABLE(of, sh_mobile_sdhi_of_match); +-- +1.8.4.3.gca3854a + @@ -17,11 +17,6 @@ patches.ltsi/ltsi-makefile-addition.patch # -############################################################################# -# Android patches. -# -# Upstream patches -# 3.2.0 through 3.3-rc3 ############################################################################# @@ -66,5 +61,606 @@ patches.lttng/lttng-fix-reference-to-obsolete-rt-kconfig-variable.patch ############################################################################# +# Renesas SOC patches +# +patches.renesas/0001-serial-sh-sci-HSCIF-support.patch +patches.renesas/0002-serial-sh-sci-Initialise-variables-before-access-in-.patch +patches.renesas/0003-serial-sh-sci-use-dev_get_platdata.patch +patches.renesas/0004-ata-use-platform_-get-set-_drvdata.patch +patches.renesas/0005-sata_rcar-kill-superfluous-code-in-sata_rcar_bmdma_f.patch +patches.renesas/0006-sata_rcar-correct-sata_rcar_sht.patch +patches.renesas/0007-sata_rcar-add-base-local-variable-to-some-functions.patch +patches.renesas/0008-sata_rcar-fix-compilation-warning-in-sata_rcar_thaw.patch +patches.renesas/0009-drivers-ata-sata_rcar.c-simplify-use-of-devm_ioremap.patch +patches.renesas/0010-drivers-irq-chip-irq-gic-introduce-gic_cpu_if_down.patch +patches.renesas/0011-irqchip-renesas-intc-irqpin-DT-binding-for-sense-bit.patch +patches.renesas/0012-ARM-shmobile-irqpin-add-a-DT-property-to-enable-mask.patch +patches.renesas/0013-irqchip-renesas-irqc-Fix-irqc_probe-error-handling.patch +patches.renesas/0014-clocksource-arch_timer-use-virtual-counters.patch +patches.renesas/0015-clocksource-arch_timer-Make-register-accessors-less-.patch +patches.renesas/0016-clocksource-arch_timer-Push-the-read-write-wrappers-.patch +patches.renesas/0017-clocksource-em_sti-Convert-to-devm_-managed-helpers.patch +patches.renesas/0018-clocksource-em_sti-Set-cpu_possible_mask-to-fix-SMP-.patch +patches.renesas/0019-gpio-rcar-R-Car-GPIO-IRQ-share-interrupt.patch +patches.renesas/0020-gpio-rcar-Make-the-platform-data-gpio_base-field-sig.patch +patches.renesas/0021-gpio-rcar-Add-support-for-IRQ_TYPE_EDGE_BOTH.patch +patches.renesas/0022-gpio-rcar-Add-RCAR_GP_PIN-macro.patch +patches.renesas/0023-gpio-rcar-Add-DT-support.patch +patches.renesas/0024-gpio-rcar-Use-OUTDT-when-reading-GPIOs-configured-as.patch +patches.renesas/0025-gpio-rcar-Reference-core-gpio-documentation-in-the-D.patch +patches.renesas/0026-gpio-rcar-Remove-ifdef-CONFIG_OF-around-OF-specific-.patch +patches.renesas/0027-gpio-rcar-fix-gpio_rcar_of_table.patch +patches.renesas/0028-gpio-rcar-Add-interrupt-controller-support-to-the-DT.patch +patches.renesas/0029-i2c-rcar-add-rcar-H2-support.patch +patches.renesas/0030-thermal-rcar-Fix-typo-in-probe-information-message.patch +patches.renesas/0031-Thermal-rcar-Remove-redundant-platform_set_drvdata.patch +patches.renesas/0032-ASoC-fsi-fixup-sparse-errors.patch +patches.renesas/0033-ASoC-add-Renesas-R-Car-core-feature.patch +patches.renesas/0034-ASoC-fsi-reserve-prefetch-period-on-DMA-transferring.patch +patches.renesas/0035-backlight-Add-GPIO-based-backlight-driver.patch +patches.renesas/0036-pwm-Add-Renesas-TPU-PWM-driver.patch +patches.renesas/0037-pwm-renesas-tpu-fix-return-value-check-in-tpu_probe.patch +patches.renesas/0038-pwm-renesas-tpu-Add-MODULE_ALIAS-to-make-module-auto.patch +patches.renesas/0039-pwm-renesas-tpu-Add-DT-support.patch +patches.renesas/0040-pwm-simplify-use-of-devm_ioremap_resource.patch +patches.renesas/0041-phy-rcar-usb-remove-EHCI-internal-buffer-setup.patch +patches.renesas/0042-phy-rcar-usb-correct-base-address.patch +patches.renesas/0043-phy-rcar-usb-add-platform-data.patch +patches.renesas/0044-phy-rcar-usb-handle-platform-data.patch +patches.renesas/0045-phy-rcar-usb-add-R8A7778-support.patch +patches.renesas/0046-usb-phy-don-t-check-resource-with-devm_ioremap_resou.patch +patches.renesas/0047-of-introduce-of_parse_phandle_with_fixed_args.patch +patches.renesas/0048-gpio-implement-gpio-ranges-binding-document-fix.patch +patches.renesas/0049-gpio-rcar-Remove-gpio-range-cells-DT-property-usage.patch +patches.renesas/0050-media-soc-camera-move-common-code-to-soc_camera.c.patch +patches.renesas/0051-mmc-return-mmc_of_parse-errors-to-caller.patch +patches.renesas/0052-mmc-slot-gpio-Add-debouncing-capability-to-mmc_gpio_.patch +patches.renesas/0053-mmc-sh_mmcif-don-t-clear-masked-interrupts.patch +patches.renesas/0054-mmc-sh_mmcif-handle-mmc_of_parse-errors-during-probe.patch +patches.renesas/0055-mmc-sh_mmcif-Remove-.down_pwr-callback-from-platform.patch +patches.renesas/0056-mmc-sh_mmcif-Remove-.set_pwr-callback-from-platform-.patch +patches.renesas/0057-mmc-sh_mmcif-move-header-include-from-header-into-.c.patch +patches.renesas/0058-mmc-sh_mmcif-add-support-for-Device-Tree-DMA-binding.patch +patches.renesas/0059-mmc-sh_mmcif-revision-specific-Command-Completion-Si.patch +patches.renesas/0060-mmc-sh_mmcif-revision-specific-CLK_CTRL2-handling.patch +patches.renesas/0061-media-soc-camera-add-host-clock-callbacks-to-start-a.patch +patches.renesas/0062-media-sh-mobile-ceu-camera-move-interface-activation.patch +patches.renesas/0063-media-sh-mobile-ceu-camera-add-primitive-OF-support.patch +patches.renesas/0064-media-sh-mobile-ceu-driver-support-max-width-and-hei.patch +patches.renesas/0065-media-V4L2-sh_mobile_ceu_camera-remove-CEU-specific-.patch +patches.renesas/0066-media-V4L2-soc-camera-move-generic-functions-into-a-.patch +patches.renesas/0067-sh_mobile_ceu_camera-Fix-a-compilation-warning.patch +patches.renesas/0068-media-V4L2-soc_camera-Renesas-R-Car-VIN-driver.patch +patches.renesas/0069-ARM-dts-r8a7740-cpus-cpu-nodes-dts-updates.patch +patches.renesas/0070-ARM-dts-sh7372-cpus-cpu-nodes-dts-updates.patch +patches.renesas/0071-ARM-shmobile-r8a7740-Add-OF-support-to-initialze-the.patch +patches.renesas/0072-ARM-shmobile-r8a7740-Prepare-for-reference-DT-setup.patch +patches.renesas/0073-ARM-shmobile-Remove-unused-r8a73a4-GIC-CPU-interface.patch +patches.renesas/0074-ARM-shmobile-Remove-unused-r8a7790-GIC-CPU-interface.patch +patches.renesas/0075-ARM-shmobile-armadillo800eva-Reference-DT-implementa.patch +patches.renesas/0076-ARM-shmobile-kzm9g-reference-add-AS3711-and-CPUFreq-.patch +patches.renesas/0077-ARM-shmobile-marzen-reference-add-irqpin-support-in-.patch +patches.renesas/0078-ARM-shmobile-armadillo800eva-Fix-maximum-number-of-S.patch +patches.renesas/0079-ARM-shmobile-bockw-enable-SDHI-on-defconfig.patch +patches.renesas/0080-ARM-shmobile-add-GPIO-IRQ-macro.patch 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+patches.renesas/0545-sh-pfc-Consolidate-pin-definition-macros.patch +patches.renesas/0546-sh-pfc-sh7734-Use-the-common-GP-port-style-macros.patch +patches.renesas/0547-sh-pfc-shx3-Remove-shx3_-prefix-from-static-symbols.patch +patches.renesas/0548-sh-pfc-Don-t-duplicate-argument-to-PINMUX_GPIO-macro.patch +patches.renesas/0549-sh-pfc-Add-port-numbers-to-the-CPU_ALL_PORT-macro.patch +patches.renesas/0550-sh-pfc-Pass-the-pin-number-down-to-the-port-function.patch +patches.renesas/0551-sh-pfc-Add-pin-number-to-struct-sh_pfc_pin.patch +patches.renesas/0552-sh-pfc-Rename-struct-sh_pfc-nr_pins-field-to-nr_gpio.patch +patches.renesas/0553-sh-pfc-Compute-pin-ranges-automatically.patch +patches.renesas/0554-sh-pfc-Support-pins-not-associated-with-a-GPIO-port.patch +patches.renesas/0555-sh-pfc-Remove-unneeded-mach-soc-.h-includes.patch +patches.renesas/0556-sh-pfc-sh7372-Replace-mach-irqs.h-with-linux-sh_intc.patch +patches.renesas/0557-sh-pfc-sh73a0-Remove-EXT_IRQ16L-and-EXT_IRQ16H-macro.patch +patches.renesas/0558-sh-pfc-r8a7779-Add-I2C-pin-groups.patch +patches.renesas/0559-sh-pfc-r8a7790-Rename-I2C-SDA-SCL-pins.patch +patches.renesas/0560-sh-pfc-r8a7790-Remove-trailing-_TANS-string-from-RTS.patch +patches.renesas/0561-sh-pfc-r8a7790-Remove-deprecated-Ethernet-MII-RMII-p.patch +patches.renesas/0562-sh-pfc-r8a7790-Remove-deprecated-RDS-pins.patch +patches.renesas/0563-sh-pfc-r8a7790-Remove-deprecated-SPV_EVEN-pin.patch +patches.renesas/0564-sh-pfc-r8a7790-Swap-SCIFA2_RXD_B-and-HRX0_C-configur.patch +patches.renesas/0565-sh-pfc-r8a7790-Add-TCLK1-pin-configuration-support.patch +patches.renesas/0566-sh-pfc-r8a7790-Add-SCIF2-pins-configuration-support.patch +patches.renesas/0567-sh-pfc-r8a7790-Fix-miscellaneous-pinmux-configuratio.patch +patches.renesas/0568-sh-pfc-r8a7790-Sort-pin-groups-and-functions-alphabe.patch +patches.renesas/0569-sh-pfc-r8a7790-Add-MSIOF-pin-groups-and-functions.patch +patches.renesas/0570-sh-pfc-r8a7790-Add-SCIF2-pin-groups-and-functions.patch +patches.renesas/0571-sh-pfc-r8a7790-Add-USB-pin-groups-and-functions.patch +patches.renesas/0572-sh-pfc-r8a7790-Add-VIN-pin-groups-and-functions.patch +patches.renesas/0573-sh-pfc-r8a7790-Rename-DU1_DOTCLKIN-to-DU_DOTCLKIN1.patch +patches.renesas/0574-sh-pfc-r8a7790-Add-DU-pin-groups-and-functions.patch +patches.renesas/0575-pinctrl-sh-pfc-remove-unnecessary-platform_set_drvda.patch +patches.renesas/0576-mmc-sdhi-tmio-make-DMA-filter-implementation-specifi.patch +patches.renesas/0577-DMA-shdma-shdma_chan_filter-has-to-be-in-shdma-base..patch +patches.renesas/0578-dmaengine-shdma-fix-a-build-failure-on-platforms-wit.patch +patches.renesas/0579-mmc-sdhi-tmio-switch-to-using-dmaengine_slave_config.patch +patches.renesas/0580-mmc-sdhi-tmio-add-DT-DMA-support.patch +patches.renesas/0581-mmc-remove-unnecessary-platform_set_drvdata.patch +patches.renesas/0582-mmc-tmio-postpone-controller-reset-during-resume.patch +patches.renesas/0583-mmc-tmio-fix-unbalanced-power-on-calls-with-clock-ga.patch +patches.renesas/0584-mmc-tmio-reset-the-controller-after-power-up.patch +patches.renesas/0585-mmc-tmio-mmc-handle-mmc_of_parse-errors-during-probe.patch +patches.renesas/0586-mmc-sh_mobile_sdhi-fix-error-return-code-in-sh_mobil.patch +patches.renesas/0587-mmc-host-use-platform_-get-set-_drvdata.patch +patches.renesas/0588-mmc-tmio-fix-compiler-warning.patch +patches.renesas/0589-mmc-sh_mobile_sdhi-Remove-.get_cd-callback-from-plat.patch +patches.renesas/0590-mmc-sh_mobile_sdhi-Remove-.set_pwr-callback-from-pla.patch +patches.renesas/0591-mmc-tmio-mmc-Remove-.get_cd-callback-from-platform-d.patch +patches.renesas/0592-mmc-tmio-mmc-Remove-.set_pwr-callback-from-platform-.patch +patches.renesas/0593-mmc-SDHI-add-DT-compatibility-strings-for-further-So.patch +patches.renesas/0594-Revert-mmc-tmio-mmc-Remove-.set_pwr-callback-from-pl.patch +patches.renesas/0595-ARM-shmobile-update-SDHI-DT-compatibility-string-to-.patch + + +############################################################################# # fixes that go after all of the above # + |