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| author | Lorenzo Pieralisi <Lorenzo.Pieralisi@arm.com> | 2014-01-24 10:56:19 +0000 |
|---|---|---|
| committer | Chanho Park <chanho61.park@samsung.com> | 2014-04-16 21:36:44 +0900 |
| commit | 823b1e1d556cdf2b5b9a2a82ba8f5f283ac197b7 (patch) | |
| tree | 9a1e9516a44ad758f2e9b700f2df451a97717489 | |
| parent | ec3b5a7e2314bf04464a99598d09b8f5ba31f267 (diff) | |
| download | linux-3.10-823b1e1d556cdf2b5b9a2a82ba8f5f283ac197b7.tar.gz linux-3.10-823b1e1d556cdf2b5b9a2a82ba8f5f283ac197b7.tar.bz2 linux-3.10-823b1e1d556cdf2b5b9a2a82ba8f5f283ac197b7.zip | |
arm64: kernel: fix per-cpu offset restore on resume
The introduction of percpu offset optimisation through tpidr_el1 in:
Commit id :7158627686f02319c50c8d9d78f75d4c8
"arm64: percpu: implement optimised pcpu access using tpidr_el1"
requires cpu_{suspend/resume} to restore the tpidr_el1 register upon resume
so that percpu variables can be addressed correctly when a CPU comes out
of reset from warm-boot.
This patch fixes cpu_{suspend}/{resume} tpidr_el1 restoration on resume, by
calling the set_my_cpu_offset C API, as it is done on primary and secondary
CPUs on cold boot, so that, even if the register used to store the percpu
offset is changed, the save and restore of general purpose registers does not
have to be updated.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| -rw-r--r-- | arch/arm64/kernel/suspend.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/kernel/suspend.c b/arch/arm64/kernel/suspend.c index 430344e2c98..1fa9ce4afd8 100644 --- a/arch/arm64/kernel/suspend.c +++ b/arch/arm64/kernel/suspend.c @@ -1,3 +1,4 @@ +#include <linux/percpu.h> #include <linux/slab.h> #include <asm/cacheflush.h> #include <asm/cpu_ops.h> @@ -89,6 +90,13 @@ int cpu_suspend(unsigned long arg) if (ret == 0) { cpu_switch_mm(mm->pgd, mm); flush_tlb_all(); + + /* + * Restore per-cpu offset before any kernel + * subsystem relying on it has a chance to run. + */ + set_my_cpu_offset(per_cpu_offset(cpu)); + /* * Restore HW breakpoint registers to sane values * before debug exceptions are possibly reenabled |