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authorChirantan Ekbote <chirantan@chromium.org>2014-06-11 15:18:48 (GMT)
committerChanho Park <chanho61.park@samsung.com>2014-10-16 06:36:51 (GMT)
commit3a1acbc2ac949a5b53a413ea1256407b8f5f09f3 (patch)
tree131374c42331df8b54e27a820697e7ab7e225b3e
parentc900a1ab108c9b24d80bfe8fd9aa5162d30b30c3 (diff)
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clocksource: exynos_mct: Don't reset the counter during boot and resumesubmit/tizen_common/20141016.103111accepted/tizen/common/20141020.075855refs/changes/78/28778/4
Unfortunately on some exynos systems, resetting the mct counter also resets the architected timer counter. This can cause problems if the architected timer driver has already been initialized because the kernel will think that the counter has wrapped around, causing a big jump in printk timestamps and delaying any scheduled clock events until the counter reaches the value it had before it was reset. The kernel code makes no assumptions about the initial value of the mct counter so there is no reason from a software perspective to clear the counter before starting it. This also fixes the problems described in the previous paragraph. Change-Id: I35f6bcd1e0ef46d5c19183dc526078a6b8b4ca64 Cc: Olof Johansson <olof@lixom.net> Cc: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Chirantan Ekbote <chirantan@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
-rw-r--r--drivers/clocksource/exynos_mct.c9
1 files changed, 3 insertions, 6 deletions
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index a74e49a..3857718 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -151,13 +151,10 @@ static void exynos4_mct_write(unsigned int value, unsigned long offset)
}
/* Clocksource handling */
-static void exynos4_mct_frc_start(u32 hi, u32 lo)
+static void exynos4_mct_frc_start(void)
{
u32 reg;
- exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
- exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
-
reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
reg |= MCT_G_TCON_START;
exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
@@ -179,7 +176,7 @@ static cycle_t exynos4_frc_read(struct clocksource *cs)
static void exynos4_frc_resume(struct clocksource *cs)
{
- exynos4_mct_frc_start(0, 0);
+ exynos4_mct_frc_start();
}
struct clocksource mct_frc = {
@@ -198,7 +195,7 @@ static u32 notrace exynos4_mct_read_sched_clock(void)
static void __init exynos4_clocksource_init(void)
{
- exynos4_mct_frc_start(0, 0);
+ exynos4_mct_frc_start();
setup_sched_clock(exynos4_mct_read_sched_clock, 32, clk_rate);