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/*
* Copyright (c) 2016, Wind River Systems.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Entry points for the A9 inits, A9 revision specific or not.
* It is assume no stack is available when these routines are called.
* It is assume each routine is called with return address in LR
* and with ARM registers R0, R1, R2, R3 being scratchable.
*/
#include <arm32.h>
#include <arm32_macros.S>
#include <asm.S>
#include <kernel/unwind.h>
#include <platform_config.h>
.section .text
.balign 4
.code 32
/*
* platform early configuration
*
* Use scratables registers R0-R3.
* No stack usage.
* LR store return address.
* Trap CPU in case of error.
*/
FUNC plat_cpu_reset_early , :
UNWIND( .fnstart)
/*
* Disallow NSec to mask FIQ [bit4: FW=0]
* Allow NSec to manage Imprecise Abort [bit5: AW=1]
* Imprecise Abort trapped to Abort Mode [bit3: EA=0]
* In Sec world, FIQ trapped to FIQ Mode [bit2: FIQ=0]
* IRQ always trapped to IRQ Mode [bit1: IRQ=0]
* Secure World [bit0: NS=0]
*/
mov r0, #SCR_AW
write_scr r0 /* write Secure Configuration Register */
/*
* Mandated HW config loaded
*
* SCTLR = 0x00000000
*
* ACTRL = 0x00000040
* - core NOT booted in full SMP (FW bit0=0)
*
* NSACR = 0x00000C00
* - NSec cannot change ACTRL.SMP (NS_SMP bit18=0)
* - NSec can use SIMD/VFP (CP10/CP11) (bit15:14=2b00, bit11:10=2b11)
*/
mov_imm r0, 0x00000000
write_sctlr r0
mov_imm r0, 0x00000040
write_actlr r0
mov_imm r0, 0x00000C00
write_nsacr r0
mov pc, lr
UNWIND( .fnend)
END_FUNC plat_cpu_reset_early
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