diff options
Diffstat (limited to 'core/arch/arm/plat-zynq7k')
| -rw-r--r-- | core/arch/arm/plat-zynq7k/conf.mk | 24 | ||||
| -rw-r--r-- | core/arch/arm/plat-zynq7k/kern.ld.S | 1 | ||||
| -rw-r--r-- | core/arch/arm/plat-zynq7k/link.mk | 1 | ||||
| -rw-r--r-- | core/arch/arm/plat-zynq7k/main.c | 276 | ||||
| -rw-r--r-- | core/arch/arm/plat-zynq7k/plat_init.S | 111 | ||||
| -rw-r--r-- | core/arch/arm/plat-zynq7k/platform_config.h | 276 | ||||
| -rw-r--r-- | core/arch/arm/plat-zynq7k/platform_smc.h | 81 | ||||
| -rw-r--r-- | core/arch/arm/plat-zynq7k/sub.mk | 3 |
8 files changed, 773 insertions, 0 deletions
diff --git a/core/arch/arm/plat-zynq7k/conf.mk b/core/arch/arm/plat-zynq7k/conf.mk new file mode 100644 index 0000000..f457d8d --- /dev/null +++ b/core/arch/arm/plat-zynq7k/conf.mk @@ -0,0 +1,24 @@ +PLATFORM_FLAVOR ?= zc702 + +arm32-platform-cpuarch := cortex-a9 + +arm32-platform-cflags += -mcpu=$(arm32-platform-cpuarch) +arm32-platform-aflags += -mcpu=$(arm32-platform-cpuarch) +core_arm32-platform-aflags += -mfpu=neon + +$(call force,CFG_ARM32_core,y) +$(call force,CFG_GENERIC_BOOT,y) +$(call force,CFG_GIC,y) +$(call force,CFG_CDNS_UART,y) +$(call force,CFG_PM_STUBS,y) +$(call force,CFG_WITH_SOFTWARE_PRNG,y) +$(call force,CFG_PL310,y) +$(call force,CFG_PL310_LOCKED,y) +$(call force,CFG_SECURE_TIME_SOURCE_REE,y) + +ta-targets = ta_arm32 + +CFG_BOOT_SYNC_CPU ?= y +CFG_BOOT_SECONDARY_REQUEST ?= y +CFG_CRYPTO_SIZE_OPTIMIZATION ?= n +CFG_WITH_STACK_CANARIES ?= y diff --git a/core/arch/arm/plat-zynq7k/kern.ld.S b/core/arch/arm/plat-zynq7k/kern.ld.S new file mode 100644 index 0000000..8d794ee --- /dev/null +++ b/core/arch/arm/plat-zynq7k/kern.ld.S @@ -0,0 +1 @@ +#include "../kernel/kern.ld.S" diff --git a/core/arch/arm/plat-zynq7k/link.mk b/core/arch/arm/plat-zynq7k/link.mk new file mode 100644 index 0000000..448ab89 --- /dev/null +++ b/core/arch/arm/plat-zynq7k/link.mk @@ -0,0 +1 @@ +include core/arch/arm/kernel/link.mk diff --git a/core/arch/arm/plat-zynq7k/main.c b/core/arch/arm/plat-zynq7k/main.c new file mode 100644 index 0000000..74bc1ce --- /dev/null +++ b/core/arch/arm/plat-zynq7k/main.c @@ -0,0 +1,276 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * All rights reserved. + * Copyright (c) 2016, Wind River Systems. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <arm32.h> +#include <console.h> +#include <drivers/cdns_uart.h> +#include <drivers/gic.h> +#include <io.h> +#include <kernel/generic_boot.h> +#include <kernel/misc.h> +#include <kernel/panic.h> +#include <kernel/pm_stubs.h> +#include <kernel/tz_ssvce_pl310.h> +#include <mm/core_mmu.h> +#include <mm/core_memprot.h> +#include <platform_config.h> +#include <platform_smc.h> +#include <stdint.h> +#include <tee/entry_fast.h> +#include <tee/entry_std.h> + +static void main_fiq(void); +static void platform_tee_entry_fast(struct thread_smc_args *args); + +static const struct thread_handlers handlers = { + .std_smc = tee_entry_std, + .fast_smc = platform_tee_entry_fast, + .fiq = main_fiq, + .cpu_on = pm_panic, + .cpu_off = pm_panic, + .cpu_suspend = pm_panic, + .cpu_resume = pm_panic, + .system_off = pm_panic, + .system_reset = pm_panic, +}; + +static struct gic_data gic_data; + +register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, CORE_MMU_DEVICE_SIZE); +register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_DEVICE_SIZE); +register_phys_mem(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_DEVICE_SIZE); +register_phys_mem(MEM_AREA_IO_SEC, SLCR_BASE, CORE_MMU_DEVICE_SIZE); + +const struct thread_handlers *generic_boot_get_handlers(void) +{ + return &handlers; +} + +static void main_fiq(void) +{ + panic(); +} + +void plat_cpu_reset_late(void) +{ + if (!get_core_pos()) { + /* primary core */ +#if defined(CFG_BOOT_SECONDARY_REQUEST) + /* set secondary entry address and release core */ + write32(CFG_TEE_LOAD_ADDR, SECONDARY_ENTRY_DROP); + dsb(); + sev(); +#endif + + /* SCU config */ + write32(SCU_INV_CTRL_INIT, SCU_BASE + SCU_INV_SEC); + write32(SCU_SAC_CTRL_INIT, SCU_BASE + SCU_SAC); + write32(SCU_NSAC_CTRL_INIT, SCU_BASE + SCU_NSAC); + + /* SCU enable */ + write32(read32(SCU_BASE + SCU_CTRL) | 0x1, + SCU_BASE + SCU_CTRL); + + /* NS Access control */ + write32(ACCESS_BITS_ALL, SECURITY2_SDIO0); + write32(ACCESS_BITS_ALL, SECURITY3_SDIO1); + write32(ACCESS_BITS_ALL, SECURITY4_QSPI); + write32(ACCESS_BITS_ALL, SECURITY6_APB_SLAVES); + + write32(SLCR_UNLOCK_MAGIC, SLCR_UNLOCK); + + write32(ACCESS_BITS_ALL, SLCR_TZ_DDR_RAM); + write32(ACCESS_BITS_ALL, SLCR_TZ_DMA_NS); + write32(ACCESS_BITS_ALL, SLCR_TZ_DMA_IRQ_NS); + write32(ACCESS_BITS_ALL, SLCR_TZ_DMA_PERIPH_NS); + write32(ACCESS_BITS_ALL, SLCR_TZ_GEM); + write32(ACCESS_BITS_ALL, SLCR_TZ_SDIO); + write32(ACCESS_BITS_ALL, SLCR_TZ_USB); + + write32(SLCR_LOCK_MAGIC, SLCR_LOCK); + } +} + +static vaddr_t console_base(void) +{ + static void *va __early_bss; + + if (cpu_mmu_enabled()) { + if (!va) + va = phys_to_virt(CONSOLE_UART_BASE, + MEM_AREA_IO_NSEC); + return (vaddr_t)va; + } + return CONSOLE_UART_BASE; +} + +void console_init(void) +{ +} + +void console_putc(int ch) +{ + if (ch == '\n') + cdns_uart_putc('\r', console_base()); + cdns_uart_putc(ch, console_base()); +} + +void console_flush(void) +{ + cdns_uart_flush(console_base()); +} + +vaddr_t pl310_base(void) +{ + static void *va __early_bss; + + if (cpu_mmu_enabled()) { + if (!va) + va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC); + return (vaddr_t)va; + } + return PL310_BASE; +} + +void arm_cl2_config(vaddr_t pl310_base) +{ + /* Disable PL310 */ + write32(0, pl310_base + PL310_CTRL); + + /* + * Xilinx AR#54190 recommends setting L2C RAM in SLCR + * to 0x00020202 for proper cache operations. + */ + write32(SLCR_L2C_RAM_VALUE, SLCR_L2C_RAM); + + write32(PL310_TAG_RAM_CTRL_INIT, pl310_base + PL310_TAG_RAM_CTRL); + write32(PL310_DATA_RAM_CTRL_INIT, pl310_base + PL310_DATA_RAM_CTRL); + write32(PL310_AUX_CTRL_INIT, pl310_base + PL310_AUX_CTRL); + write32(PL310_PREFETCH_CTRL_INIT, pl310_base + PL310_PREFETCH_CTRL); + write32(PL310_POWER_CTRL_INIT, pl310_base + PL310_POWER_CTRL); + + /* invalidate all cache ways */ + arm_cl2_invbyway(pl310_base); +} + +void arm_cl2_enable(vaddr_t pl310_base) +{ + uint32_t val; + + /* Enable PL310 ctrl -> only set lsb bit */ + write32(1, pl310_base + PL310_CTRL); + + /* if L2 FLZW enable, enable in L1 */ + val = read32(pl310_base + PL310_AUX_CTRL); + if (val & 1) + write_actlr(read_actlr() | (1 << 3)); +} + +void main_init_gic(void) +{ + vaddr_t gicc_base; + vaddr_t gicd_base; + + gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, + MEM_AREA_IO_SEC); + gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, + MEM_AREA_IO_SEC); + + if (!gicc_base || !gicd_base) + panic(); + + /* Initialize GIC */ + gic_init(&gic_data, gicc_base, gicd_base); + itr_init(&gic_data.chip); +} + +void main_secondary_init_gic(void) +{ + gic_cpu_init(&gic_data); +} + +static vaddr_t slcr_access_range[] = { + 0x004, 0x008, /* lock, unlock */ + 0x100, 0x1FF, /* PLL */ + 0x200, 0x2FF, /* Reset */ + 0xA00, 0xAFF /* L2C */ +}; + +static uint32_t write_slcr(uint32_t addr, uint32_t val) +{ + uint32_t i; + + for (i = 0; i < ARRAY_SIZE(slcr_access_range); i += 2) { + if (addr >= slcr_access_range[i] && + addr <= slcr_access_range[i+1]) { + static vaddr_t va __early_bss; + + if (!va) + va = (vaddr_t)phys_to_virt(SLCR_BASE, + MEM_AREA_IO_SEC); + write32(val, va + addr); + return OPTEE_SMC_RETURN_OK; + } + } + return OPTEE_SMC_RETURN_EBADADDR; +} + +static uint32_t read_slcr(uint32_t addr, uint32_t *val) +{ + uint32_t i; + + for (i = 0; i < ARRAY_SIZE(slcr_access_range); i += 2) { + if (addr >= slcr_access_range[i] && + addr <= slcr_access_range[i+1]) { + static vaddr_t va __early_bss; + + if (!va) + va = (vaddr_t)phys_to_virt(SLCR_BASE, + MEM_AREA_IO_SEC); + *val = read32(va + addr); + return OPTEE_SMC_RETURN_OK; + } + } + return OPTEE_SMC_RETURN_EBADADDR; +} + +static void platform_tee_entry_fast(struct thread_smc_args *args) +{ + switch (args->a0) { + case ZYNQ7K_SMC_SLCR_WRITE: + args->a0 = write_slcr(args->a1, args->a2); + break; + case ZYNQ7K_SMC_SLCR_READ: + args->a0 = read_slcr(args->a1, &args->a2); + break; + default: + tee_entry_fast(args); + break; + } +} diff --git a/core/arch/arm/plat-zynq7k/plat_init.S b/core/arch/arm/plat-zynq7k/plat_init.S new file mode 100644 index 0000000..6d99a30 --- /dev/null +++ b/core/arch/arm/plat-zynq7k/plat_init.S @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2014, STMicroelectronics International N.V. + * All rights reserved. + * Copyright (c) 2016, Wind River Systems. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Entry points for the A9 inits, A9 revision specific or not. + * It is assume no stack is available when these routines are called. + * It is assume each routine is called with return address in LR + * and with ARM registers R0, R1, R2, R3 being scratchable. + */ + +#include <arm32.h> +#include <arm32_macros.S> +#include <arm32_macros_cortex_a9.S> +#include <asm.S> +#include <kernel/tz_ssvce_def.h> +#include <kernel/unwind.h> +#include <platform_config.h> + +#define ZYNQ_SLCR_L2C_RAM 0xF8000A1C + +.section .text +.balign 4 +.code 32 + +/* + * Cortex A9 early configuration + * + * Use registers R0-R3. + * No stack usage. + * LR store return address. + * Trap CPU in case of error. + */ +FUNC plat_cpu_reset_early , : +UNWIND( .fnstart) + + /* + * Disallow NSec to mask FIQ [bit4: FW=0] + * Allow NSec to manage Imprecise Abort [bit5: AW=1] + * Imprecise Abort trapped to Abort Mode [bit3: EA=0] + * In Sec world, FIQ trapped to FIQ Mode [bit2: FIQ=0] + * IRQ always trapped to IRQ Mode [bit1: IRQ=0] + * Secure World [bit0: NS=0] + */ + mov r0, #SCR_AW + write_scr r0 /* write Secure Configuration Register */ + + /* + * Mandated HW config loaded + * + * SCTLR = 0x00004000 + * - Round-Robin replac. for icache, btac, i/duTLB (bit14: RoundRobin) + * + * ACTRL = 0x00000041 + * - core always in full SMP (FW bit0=1, SMP bit6=1) + * - L2 write full line of zero disabled (bit3=0) + * (keep WFLZ low. Will be set once outer L2 is ready) + * + * NSACR = 0x00020C00 + * - NSec cannot change ACTRL.SMP (NS_SMP bit18=0) + * - Nsec can lockdown TLB (TL bit17=1) + * - NSec cannot access PLE (PLE bit16=0) + * - NSec can use SIMD/VFP (CP10/CP11) (bit15:14=2b00, bit11:10=2b11) + * + * PCR = 0x00000001 + * - no change latency, enable clk gating + */ + movw r0, #0x4000 + movt r0, #0x0000 + write_sctlr r0 + + movw r0, #0x0041 + movt r0, #0x0000 + write_actlr r0 + + movw r0, #0x0FFF + movt r0, #0x0002 + write_nsacr r0 + + movw r0, #0x0000 + movt r0, #0x0001 + write_pcr r0 + + mov pc, lr +UNWIND( .fnend) +END_FUNC plat_cpu_reset_early diff --git a/core/arch/arm/plat-zynq7k/platform_config.h b/core/arch/arm/plat-zynq7k/platform_config.h new file mode 100644 index 0000000..c970048 --- /dev/null +++ b/core/arch/arm/plat-zynq7k/platform_config.h @@ -0,0 +1,276 @@ +/* + * Copyright (c) 2016, Wind River Systems. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef PLATFORM_CONFIG_H +#define PLATFORM_CONFIG_H + +#define STACK_ALIGNMENT 64 + +/* For Zynq7000 board */ + +#define SCU_BASE 0xF8F00000 +#define PL310_BASE 0xF8F02000 +#define GIC_BASE 0xF8F00000 +#define GICC_OFFSET 0x100 +#define GICD_OFFSET 0x1000 +#define GIC_CPU_BASE (GIC_BASE + GICC_OFFSET) +#define GIC_DIST_BASE (GIC_BASE + GICD_OFFSET) + +#define SLCR_BASE 0xF8000000 +#define SLCR_LOCK 0xF8000004 +#define SLCR_UNLOCK 0xF8000008 +#define SLCR_TZ_DDR_RAM 0xF8000430 +#define SLCR_TZ_DMA_NS 0xF8000440 +#define SLCR_TZ_DMA_IRQ_NS 0xF8000444 +#define SLCR_TZ_DMA_PERIPH_NS 0xF8000448 +#define SLCR_TZ_GEM 0xF8000450 +#define SLCR_TZ_SDIO 0xF8000454 +#define SLCR_TZ_USB 0xF8000458 +#define SLCR_L2C_RAM 0xF8000A1C + +#define SLCR_LOCK_MAGIC 0x0000767B +#define SLCR_UNLOCK_MAGIC 0x0000DF0D + +#define SECURITY2_SDIO0 0xE0200008 +#define SECURITY3_SDIO1 0xE020000C +#define SECURITY4_QSPI 0xE0200010 +#define SECURITY6_APB_SLAVES 0xE0200018 + +#define UART0_BASE 0xE0000000 +#define UART1_BASE 0xE0001000 + +#define CONSOLE_UART_BASE UART1_BASE + +#define DRAM0_BASE 0x00100000 +#define DRAM0_SIZE 0x3FF00000 + +#define CFG_TEE_RAM_VA_SIZE (1024 * 1024) + +#define CFG_TEE_CORE_NB_CORE 2 + +#define DDR_PHYS_START DRAM0_BASE +#define DDR_SIZE DRAM0_SIZE + +#define CFG_DDR_START DDR_PHYS_START +#define CFG_DDR_SIZE DDR_SIZE + +/* + * PL310 TAG RAM Control Register + * + * bit[10:8]:1 - 2 cycle of write accesses latency + * bit[6:4]:1 - 2 cycle of read accesses latency + * bit[2:0]:1 - 2 cycle of setup latency + */ +#ifndef PL310_TAG_RAM_CTRL_INIT +#define PL310_TAG_RAM_CTRL_INIT 0x00000111 +#endif + +/* + * PL310 DATA RAM Control Register + * + * bit[10:8]:2 - 3 cycle of write accesses latency + * bit[6:4]:2 - 3 cycle of read accesses latency + * bit[2:0]:2 - 3 cycle of setup latency + */ +#ifndef PL310_DATA_RAM_CTRL_INIT +#define PL310_DATA_RAM_CTRL_INIT 0x00000222 +#endif + +/* + * PL310 Auxiliary Control Register + * + * I/Dcache prefetch enabled (bit29:28=2b11) + * NS can access interrupts (bit27=1) + * NS can lockown cache lines (bit26=1) + * Pseudo-random replacement policy (bit25=0) + * Force write allocated (default) + * Shared attribute internally ignored (bit22=1, bit13=0) + * Parity disabled (bit21=0) + * Event monitor disabled (bit20=0) + * Platform fmavor specific way config: + * - 64kb way size (bit19:17=3b011) + * - 8-way associciativity (bit16=0) + * Store buffer device limitation enabled (bit11=1) + * Cacheable accesses have high prio (bit10=0) + * Full Line Zero (FLZ) disabled (bit0=0) + */ +#ifndef PL310_AUX_CTRL_INIT +#define PL310_AUX_CTRL_INIT 0x3C460800 +#endif + +/* + * PL310 Prefetch Control Register + * + * Double linefill disabled (bit30=0) + * I/D prefetch enabled (bit29:28=2b11) + * Prefetch drop enabled (bit24=1) + * Incr double linefill disable (bit23=0) + * Prefetch offset = 7 (bit4:0) + */ +#define PL310_PREFETCH_CTRL_INIT 0x31000007 + +/* + * PL310 Power Register + * + * Dynamic clock gating enabled + * Standby mode enabled + */ +#define PL310_POWER_CTRL_INIT 0x00000003 + +/* + * SCU Invalidate Register + * + * Invalidate all registers + */ +#define SCU_INV_CTRL_INIT 0xFFFFFFFF + +/* + * SCU Access Register + * - both secure CPU access SCU + */ +#define SCU_SAC_CTRL_INIT 0x0000000F + +/* + * SCU NonSecure Access Register + * - both nonsec cpu access SCU, private and global timer + */ +#define SCU_NSAC_CTRL_INIT 0x00000FFF + +/* all bit enabled in access control register */ +#define ACCESS_BITS_ALL 0xFFFFFFFF + +/* recommended value for setting the L2C_RAM register */ +#define SLCR_L2C_RAM_VALUE 0x00020202 + +/* place in OCRAM to write secondary entry to */ +#define SECONDARY_ENTRY_DROP 0xFFFFFFF0 + +/* define the memory areas */ + +#ifdef CFG_WITH_PAGER + +/* + * TEE/TZ RAM layout: + * + * +---------------------------------------+ <- CFG_CORE_TZSRAM_EMUL_START + * | TEE private highly | TEE_RAM | ^ + * | secure memory | | | CFG_CORE_TZSRAM_EMUL_SIZE + * +---------------------------------------+ v + * + * +---------------------------------------+ <- CFG_DDR_TEETZ_RESERVED_START + * | TEE private secure | TA_RAM | ^ + * | external memory | | | + * +---------------------------------------+ | CFG_DDR_TEETZ_RESERVED_SIZE + * | Non secure | SHM | | + * | shared memory | | | + * +---------------------------------------+ v + * + * TEE_RAM : default 256kByte + * TA_RAM : all what is left in DDR TEE reserved area + * PUB_RAM : default 2MByte + */ + +/* emulated SRAM, 256K at start of secure DDR */ + +#define CFG_CORE_TZSRAM_EMUL_START 0x3E000000 + +#define TZSRAM_BASE CFG_CORE_TZSRAM_EMUL_START +#define TZSRAM_SIZE CFG_CORE_TZSRAM_EMUL_SIZE + +/* Location of trusted dram */ + +#define CFG_DDR_TEETZ_RESERVED_START 0x3E100000 +#define CFG_DDR_TEETZ_RESERVED_SIZE 0x01F00000 + +#define CFG_PUB_RAM_SIZE (1 * 1024 * 1024) +#define CFG_TEE_RAM_PH_SIZE TZSRAM_SIZE + +#define TZDRAM_BASE (CFG_DDR_TEETZ_RESERVED_START) +#define TZDRAM_SIZE (CFG_DDR_TEETZ_RESERVED_SIZE - \ + CFG_PUB_RAM_SIZE) + +#define CFG_SHMEM_START (CFG_DDR_TEETZ_RESERVED_START + \ + TZDRAM_SIZE) +#define CFG_SHMEM_SIZE CFG_PUB_RAM_SIZE + +#define CFG_TA_RAM_START TZDRAM_BASE +#define CFG_TA_RAM_SIZE TZDRAM_SIZE + +#define CFG_TEE_RAM_START TZSRAM_BASE + +#ifndef CFG_TEE_LOAD_ADDR +#define CFG_TEE_LOAD_ADDR TZSRAM_BASE +#endif + +#else /* CFG_WITH_PAGER */ + +/* + * TEE/TZ RAM layout: + * + * +---------------------------------------+ <- CFG_DDR_TEETZ_RESERVED_START + * | TEE private secure | TEE_RAM | ^ + * | external memory +------------------+ | + * | | TA_RAM | | + * +---------------------------------------+ | CFG_DDR_TEETZ_RESERVED_SIZE + * | Non secure | SHM | | + * | shared memory | | | + * +---------------------------------------+ v + * + * TEE_RAM : 1MByte + * PUB_RAM : 1MByte + * TA_RAM : all what is left (at least 2MByte !) + */ + +#define CFG_DDR_TEETZ_RESERVED_START 0x3E000000 +#define CFG_DDR_TEETZ_RESERVED_SIZE 0x02000000 + +#define CFG_PUB_RAM_SIZE (1 * 1024 * 1024) +#define CFG_TEE_RAM_PH_SIZE (1 * 1024 * 1024) + +#define TZDRAM_BASE (CFG_DDR_TEETZ_RESERVED_START) +#define TZDRAM_SIZE (CFG_DDR_TEETZ_RESERVED_SIZE - \ + CFG_PUB_RAM_SIZE) + +#define CFG_TA_RAM_START (CFG_DDR_TEETZ_RESERVED_START + \ + CFG_TEE_RAM_PH_SIZE) +#define CFG_TA_RAM_SIZE (CFG_DDR_TEETZ_RESERVED_SIZE - \ + CFG_TEE_RAM_PH_SIZE - \ + CFG_PUB_RAM_SIZE) + +#define CFG_SHMEM_START (CFG_DDR_TEETZ_RESERVED_START + \ + TZDRAM_SIZE) +#define CFG_SHMEM_SIZE CFG_PUB_RAM_SIZE + +#define CFG_TEE_RAM_START TZDRAM_BASE + +#ifndef CFG_TEE_LOAD_ADDR +#define CFG_TEE_LOAD_ADDR TZDRAM_BASE +#endif + +#endif /* CFG_WITH_PAGER */ + +#endif /*PLATFORM_CONFIG_H*/ diff --git a/core/arch/arm/plat-zynq7k/platform_smc.h b/core/arch/arm/plat-zynq7k/platform_smc.h new file mode 100644 index 0000000..ac6bc33 --- /dev/null +++ b/core/arch/arm/plat-zynq7k/platform_smc.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2016, Wind River System + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef PLATFORM_SMC_H +#define PLATFORM_SMC_H + +#include <sm/optee_smc.h> + +/* + * Read SLCR (System Level Control Register) + * + * Call register usage: + * a0 SMC Function ID, ZYNQ7K_SMC_SLCR_READ + * a1 Register offset + * a2-7 Not used + * + * Normal return register usage: + * a0 OPTEE_SMC_RETURN_OK + * a1 Value read back + * a2-3 Not used + * a4-7 Preserved + * + * OPTEE_SMC_RETURN_EBADCMD on Invalid input offset: + * a0 OPTEE_SMC_RETURN_EBADCMD + * a1 Undefined value + * a2-3 Not used + * a4-7 Preserved + */ +#define ZYNQ7K_SMC_FUNCID_SLCR_READ 0x100 +#define ZYNQ7K_SMC_SLCR_READ \ + OPTEE_SMC_CALL_VAL(OPTEE_SMC_32, OPTEE_SMC_FAST_CALL, \ + OPTEE_SMC_OWNER_OEM, ZYNQ7K_SMC_FUNCID_SLCR_READ) + +/* + * Write SLCR (System Level Control Register) + * + * Call register usage: + * a0 SMC Function ID, ZYNQ7K_SMC_SLCR_READ + * a1 Register offset + * a2 Value to write + * a3-7 Not used + * + * Normal return register usage: + * a0 OPTEE_SMC_RETURN_OK + * a1-3 Not used + * a4-7 Preserved + * + * OPTEE_SMC_RETURN_EBADCMD on Invalid input offset: + * a0 OPTEE_SMC_RETURN_EBADCMD + * a1-3 Not used + * a4-7 Preserved + */ +#define ZYNQ7K_SMC_FUNCID_SLCR_WRITE 0x101 +#define ZYNQ7K_SMC_SLCR_WRITE \ + OPTEE_SMC_CALL_VAL(OPTEE_SMC_32, OPTEE_SMC_FAST_CALL, \ + OPTEE_SMC_OWNER_OEM, ZYNQ7K_SMC_FUNCID_SLCR_WRITE) + +#endif /* PLATFORM_SMC_H */ diff --git a/core/arch/arm/plat-zynq7k/sub.mk b/core/arch/arm/plat-zynq7k/sub.mk new file mode 100644 index 0000000..652c084 --- /dev/null +++ b/core/arch/arm/plat-zynq7k/sub.mk @@ -0,0 +1,3 @@ +global-incdirs-y += . +srcs-y += main.c +srcs-y += plat_init.S |