diff options
Diffstat (limited to 'core/arch/arm/plat-vexpress/main.c')
| -rw-r--r-- | core/arch/arm/plat-vexpress/main.c | 201 |
1 files changed, 201 insertions, 0 deletions
diff --git a/core/arch/arm/plat-vexpress/main.c b/core/arch/arm/plat-vexpress/main.c new file mode 100644 index 0000000..85ed9ee --- /dev/null +++ b/core/arch/arm/plat-vexpress/main.c @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2016, Linaro Limited + * Copyright (c) 2014, STMicroelectronics International N.V. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <platform_config.h> + +#include <stdint.h> +#include <string.h> + +#include <drivers/gic.h> +#include <drivers/pl011.h> +#include <drivers/tzc400.h> + +#include <arm.h> +#include <kernel/generic_boot.h> +#include <kernel/pm_stubs.h> +#include <trace.h> +#include <kernel/misc.h> +#include <kernel/panic.h> +#include <kernel/tee_time.h> +#include <tee/entry_fast.h> +#include <tee/entry_std.h> +#include <mm/core_memprot.h> +#include <mm/core_mmu.h> +#include <console.h> +#include <keep.h> +#include <initcall.h> + +static void main_fiq(void); + +static const struct thread_handlers handlers = { + .std_smc = tee_entry_std, + .fast_smc = tee_entry_fast, + .fiq = main_fiq, +#if defined(CFG_WITH_ARM_TRUSTED_FW) + .cpu_on = cpu_on_handler, + .cpu_off = pm_do_nothing, + .cpu_suspend = pm_do_nothing, + .cpu_resume = pm_do_nothing, + .system_off = pm_do_nothing, + .system_reset = pm_do_nothing, +#else + .cpu_on = pm_panic, + .cpu_off = pm_panic, + .cpu_suspend = pm_panic, + .cpu_resume = pm_panic, + .system_off = pm_panic, + .system_reset = pm_panic, +#endif +}; + +static struct gic_data gic_data; + +register_phys_mem(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); + +const struct thread_handlers *generic_boot_get_handlers(void) +{ + return &handlers; +} + +#ifdef GIC_BASE + +register_phys_mem(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); +register_phys_mem(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE); + +void main_init_gic(void) +{ + vaddr_t gicc_base; + vaddr_t gicd_base; + + gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, + MEM_AREA_IO_SEC); + gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, + MEM_AREA_IO_SEC); + if (!gicc_base || !gicd_base) + panic(); + +#if defined(PLATFORM_FLAVOR_fvp) || defined(PLATFORM_FLAVOR_juno) || \ + defined(PLATFORM_FLAVOR_qemu_armv8a) + /* On ARMv8, GIC configuration is initialized in ARM-TF */ + gic_init_base_addr(&gic_data, gicc_base, gicd_base); +#else + /* Initialize GIC */ + gic_init(&gic_data, gicc_base, gicd_base); +#endif + itr_init(&gic_data.chip); +} +#endif + +static void main_fiq(void) +{ + gic_it_handle(&gic_data); +} + +static vaddr_t console_base(void) +{ + static void *va; + + if (cpu_mmu_enabled()) { + if (!va) + va = phys_to_virt(CONSOLE_UART_BASE, MEM_AREA_IO_SEC); + return (vaddr_t)va; + } + return CONSOLE_UART_BASE; +} + +void console_init(void) +{ + pl011_init(console_base(), CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE); +} + +void console_putc(int ch) +{ + vaddr_t base = console_base(); + + if (ch == '\n') + pl011_putc('\r', base); + pl011_putc(ch, base); +} + +void console_flush(void) +{ + pl011_flush(console_base()); +} + +#ifdef IT_CONSOLE_UART +static enum itr_return console_itr_cb(struct itr_handler *h __unused) +{ + paddr_t uart_base = console_base(); + + while (pl011_have_rx_data(uart_base)) { + int ch __maybe_unused = pl011_getchar(uart_base); + + DMSG("cpu %zu: got 0x%x", get_core_pos(), ch); + } + return ITRR_HANDLED; +} + +static struct itr_handler console_itr = { + .it = IT_CONSOLE_UART, + .flags = ITRF_TRIGGER_LEVEL, + .handler = console_itr_cb, +}; +KEEP_PAGER(console_itr); + +static TEE_Result init_console_itr(void) +{ + itr_add(&console_itr); + itr_enable(IT_CONSOLE_UART); + return TEE_SUCCESS; +} +driver_init(init_console_itr); +#endif + +#ifdef CFG_TZC400 +register_phys_mem(MEM_AREA_IO_SEC, TZC400_BASE, TZC400_REG_SIZE); + +static TEE_Result init_tzc400(void) +{ + void *va; + + DMSG("Initializing TZC400"); + + va = phys_to_virt(TZC400_BASE, MEM_AREA_IO_SEC); + if (!va) { + EMSG("TZC400 not mapped"); + panic(); + } + + tzc_init((vaddr_t)va); + tzc_dump_state(); + + return TEE_SUCCESS; +} + +service_init(init_tzc400); +#endif /*CFG_TZC400*/ |