diff options
Diffstat (limited to 'core/arch/arm/plat-stm')
| -rw-r--r-- | core/arch/arm/plat-stm/.gitignore | 1 | ||||
| -rw-r--r-- | core/arch/arm/plat-stm/asc.S | 108 | ||||
| -rw-r--r-- | core/arch/arm/plat-stm/asc.h | 35 | ||||
| -rw-r--r-- | core/arch/arm/plat-stm/conf.mk | 30 | ||||
| -rw-r--r-- | core/arch/arm/plat-stm/kern.ld.S | 1 | ||||
| -rw-r--r-- | core/arch/arm/plat-stm/link.mk | 1 | ||||
| -rw-r--r-- | core/arch/arm/plat-stm/main.c | 201 | ||||
| -rw-r--r-- | core/arch/arm/plat-stm/platform_config.h | 340 | ||||
| -rw-r--r-- | core/arch/arm/plat-stm/rng_support.c | 147 | ||||
| -rw-r--r-- | core/arch/arm/plat-stm/sub.mk | 6 | ||||
| -rw-r--r-- | core/arch/arm/plat-stm/tz_a9init.S | 101 |
11 files changed, 971 insertions, 0 deletions
diff --git a/core/arch/arm/plat-stm/.gitignore b/core/arch/arm/plat-stm/.gitignore new file mode 100644 index 0000000..49b7bb9 --- /dev/null +++ b/core/arch/arm/plat-stm/.gitignore @@ -0,0 +1 @@ +System.map diff --git a/core/arch/arm/plat-stm/asc.S b/core/arch/arm/plat-stm/asc.S new file mode 100644 index 0000000..3f2b6aa --- /dev/null +++ b/core/arch/arm/plat-stm/asc.S @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2014, STMicroelectronics International N.V. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include <platform_config.h> +#include <asm.S> +#include <kernel/unwind.h> + +#define ASC_BAUDRATE 0x00 +#define ASC_TXBUFFER 0x04 +#define ASC_RXBUFFER 0x08 +#define ASC_CONTROL 0x0c +#define ASC_INTENABLE 0x10 +#define ASC_STATUS 0x14 +#define ASC_GUARDTIME 0x18 +#define ASC_TIMEOUT 0x1c +#define ASC_TXRESET 0x20 +#define ASC_RXRESET 0x24 +#define ASC_RETRIES 0x28 + +.section .text.asc + + +/* + * void __asc_flush(vaddr_t base) + * + * Clobbers r0-r3 + */ +FUNC __asc_flush , : +UNWIND( .fnstart) + + ADD r3, r0, #ASC_STATUS + +flush_wait: + LDR r1, [r3] + ANDS r1, r1, #0x02 /* AND TX FIFO EMPTY flag */ + BEQ flush_wait /* ANDS should have set Z bit if zero */ + + LDR r0, =0 + BX lr +UNWIND( .fnend) +END_FUNC __asc_flush + +/* + * int __asc_xmit_char(char p, vaddr_t base) - Transmit a single character. + * + * R0 is the 1-byte character to be transmited + * R1 is the base address of the uart + * Clobbers r0-r3 + */ +FUNC __asc_xmit_char , : +UNWIND( .fnstart) + + ADD r2, r1, #ASC_TXBUFFER + ADD r3, r1, #ASC_STATUS + + /* Output byte */ + + /* Spin until TX FIFO ready */ +__asc_char_crwait: + LDR r1, [r3] + ANDS r1, r1, #0x04 /* AND TX FIFO HALF EMPTY flag */ + BEQ __asc_char_crwait /* ANDS should have set Z bit if zero */ + + MOVS r1, r0 + LDR r0, =0xFF + AND r1, r1, r0 + BEQ __asc_char_exit + CMP r1, #0xa /* r1 == \n (line feed) ? */ + BNE __asc_char_notlf + + /* Transmit character extra carriage return for each line feed */ + LDR r1, =0x0d + STR r1, [r2] + + LDR r1, =0x0a /* replace line feed */ + +__asc_char_notlf: + /* Transmit character */ + STR r1, [r2] + +__asc_char_exit: + LDR r0, =0 + BX lr +UNWIND( .fnend) +END_FUNC __asc_xmit_char diff --git a/core/arch/arm/plat-stm/asc.h b/core/arch/arm/plat-stm/asc.h new file mode 100644 index 0000000..bbf574c --- /dev/null +++ b/core/arch/arm/plat-stm/asc.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2014, STMicroelectronics International N.V. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef ASC_H +#define ASC_H + +#include <types_ext.h> + +extern int __asc_xmit_char(const char p, vaddr_t base); +extern void __asc_flush(vaddr_t base); + +#endif diff --git a/core/arch/arm/plat-stm/conf.mk b/core/arch/arm/plat-stm/conf.mk new file mode 100644 index 0000000..4afe256 --- /dev/null +++ b/core/arch/arm/plat-stm/conf.mk @@ -0,0 +1,30 @@ +PLATFORM_FLAVOR ?= b2260 + +arm32-platform-cpuarch := cortex-a9 +arm32-platform-cflags += -mcpu=$(arm32-platform-cpuarch) +arm32-platform-aflags += -mcpu=$(arm32-platform-cpuarch) +core_arm32-platform-aflags += -mfpu=neon + +$(call force,CFG_ARM32_core,y) +$(call force,CFG_SECURE_TIME_SOURCE_REE,y) +$(call force,CFG_PL310,y) +$(call force,CFG_CACHE_API,y) +$(call force,CFG_PM_STUBS,y) +$(call force,CFG_GENERIC_BOOT,y) +$(call force,CFG_WITH_LPAE,n) +$(call force,CFG_GIC,y) + +ta-targets = ta_arm32 + +CFG_WITH_PAGER ?= n +CFG_BOOT_SYNC_CPU ?= y +CFG_TEE_CORE_EMBED_INTERNAL_TESTS ?= y +CFG_WITH_STACK_CANARIES ?= y +CFG_WITH_STATS ?= y +CFG_WITH_SOFTWARE_PRNG ?= n + +ifeq ($(PLATFORM_FLAVOR),b2260) +CFG_PL310_LOCKED ?= y +else +CFG_PL310_LOCKED ?= n +endif diff --git a/core/arch/arm/plat-stm/kern.ld.S b/core/arch/arm/plat-stm/kern.ld.S new file mode 100644 index 0000000..8d794ee --- /dev/null +++ b/core/arch/arm/plat-stm/kern.ld.S @@ -0,0 +1 @@ +#include "../kernel/kern.ld.S" diff --git a/core/arch/arm/plat-stm/link.mk b/core/arch/arm/plat-stm/link.mk new file mode 100644 index 0000000..448ab89 --- /dev/null +++ b/core/arch/arm/plat-stm/link.mk @@ -0,0 +1 @@ +include core/arch/arm/kernel/link.mk diff --git a/core/arch/arm/plat-stm/main.c b/core/arch/arm/plat-stm/main.c new file mode 100644 index 0000000..e569e07 --- /dev/null +++ b/core/arch/arm/plat-stm/main.c @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2014-2016, STMicroelectronics International N.V. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <arm32.h> +#include <asc.h> +#include <console.h> +#include <drivers/gic.h> +#include <drivers/pl011.h> +#include <io.h> +#include <kernel/generic_boot.h> +#include <kernel/misc.h> +#include <kernel/panic.h> +#include <kernel/pm_stubs.h> +#include <kernel/tz_ssvce_pl310.h> +#include <mm/core_mmu.h> +#include <mm/core_memprot.h> +#include <platform_config.h> +#include <stdint.h> +#include <tee/entry_std.h> +#include <tee/entry_fast.h> +#include <trace.h> +#include <util.h> + +register_phys_mem(MEM_AREA_IO_SEC, CPU_IOMEM_BASE, CORE_MMU_DEVICE_SIZE); +register_phys_mem(MEM_AREA_IO_SEC, RNG_BASE, CORE_MMU_DEVICE_SIZE); +register_phys_mem(MEM_AREA_IO_NSEC, UART_CONSOLE_BASE, CORE_MMU_DEVICE_SIZE); + +static struct gic_data gic_data; +static void main_fiq(void); + +#if defined(PLATFORM_FLAVOR_b2260) +#define stm_tee_entry_std tee_entry_std +static bool ns_resources_ready(void) +{ + return true; +} +#else +/* some nonsecure resource might not be ready (uart) */ +static int boot_is_completed __early_bss; +static bool ns_resources_ready(void) +{ + return !!boot_is_completed; +} +static void stm_tee_entry_std(struct thread_smc_args *smc_args) +{ + boot_is_completed = 1; + tee_entry_std(smc_args); +} +#endif + +static const struct thread_handlers handlers = { + .std_smc = stm_tee_entry_std, + .fast_smc = tee_entry_fast, + .fiq = main_fiq, + .cpu_on = pm_panic, + .cpu_off = pm_panic, + .cpu_suspend = pm_panic, + .cpu_resume = pm_panic, + .system_off = pm_panic, + .system_reset = pm_panic, +}; + +const struct thread_handlers *generic_boot_get_handlers(void) +{ + return &handlers; +} + +static vaddr_t console_base(void) +{ + static void *va __early_bss; + + if (cpu_mmu_enabled()) { + if (!va) + va = phys_to_virt(UART_CONSOLE_BASE, MEM_AREA_IO_NSEC); + return (vaddr_t)va; + } + return UART_CONSOLE_BASE; +} + +void console_init(void) +{ +} + +void console_putc(int ch) +{ + if (ns_resources_ready()) { + if (ch == '\n') + __asc_xmit_char('\r', console_base()); + __asc_xmit_char((char)ch, console_base()); + } +} + +void console_flush(void) +{ + if (ns_resources_ready()) + __asc_flush(console_base()); +} + +vaddr_t pl310_base(void) +{ + static void *va __early_bss; + + if (cpu_mmu_enabled()) { + if (!va) + va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC); + return (vaddr_t)va; + } + return PL310_BASE; +} + +void arm_cl2_config(vaddr_t pl310) +{ + /* pl310 off */ + write32(0, pl310 + PL310_CTRL); + + /* config PL310 */ + write32(PL310_TAG_RAM_CTRL_INIT, pl310 + PL310_TAG_RAM_CTRL); + write32(PL310_DATA_RAM_CTRL_INIT, pl310 + PL310_DATA_RAM_CTRL); + write32(PL310_AUX_CTRL_INIT, pl310 + PL310_AUX_CTRL); + write32(PL310_PREFETCH_CTRL_INIT, pl310 + PL310_PREFETCH_CTRL); + write32(PL310_POWER_CTRL_INIT, pl310 + PL310_POWER_CTRL); + + /* invalidate all pl310 cache ways */ + arm_cl2_invbyway(pl310); +} + +void plat_cpu_reset_late(void) +{ + int i; + + assert(!cpu_mmu_enabled()); + + /* Allow NSec to Imprecise abort */ + write_scr(SCR_AW); + + if (get_core_pos()) + return; + + write32(SCU_SAC_INIT, SCU_BASE + SCU_SAC); + write32(SCU_NSAC_INIT, SCU_BASE + SCU_NSAC); + write32(CPU_PORT_FILT_END, SCU_BASE + SCU_FILT_EA); + write32(CPU_PORT_FILT_START, SCU_BASE + SCU_FILT_SA); + write32(SCU_CTRL_INIT, SCU_BASE + SCU_CTRL); + + write32(CPU_PORT_FILT_END, pl310_base() + PL310_ADDR_FILT_END); + write32(CPU_PORT_FILT_START | PL310_CTRL_ENABLE_BIT, + pl310_base() + PL310_ADDR_FILT_START); + + /* TODO: gic_init scan fails, pre-init all SPIs are nonsecure */ + for (i = 0; i < (31 * 4); i += 4) + write32(0xFFFFFFFF, GIC_DIST_BASE + GIC_DIST_ISR1 + i); +} + +void main_init_gic(void) +{ + vaddr_t gicc_base; + vaddr_t gicd_base; + + gicc_base = (vaddr_t)phys_to_virt(GIC_CPU_BASE, MEM_AREA_IO_SEC); + gicd_base = (vaddr_t)phys_to_virt(GIC_DIST_BASE, MEM_AREA_IO_SEC); + + if (!gicc_base || !gicd_base) + panic(); + + gic_init(&gic_data, gicc_base, gicd_base); + itr_init(&gic_data.chip); +} + +void main_secondary_init_gic(void) +{ + gic_cpu_init(&gic_data); +} + +static void main_fiq(void) +{ + gic_it_handle(&gic_data); +} diff --git a/core/arch/arm/plat-stm/platform_config.h b/core/arch/arm/plat-stm/platform_config.h new file mode 100644 index 0000000..407a412 --- /dev/null +++ b/core/arch/arm/plat-stm/platform_config.h @@ -0,0 +1,340 @@ +/* + * Copyright (c) 2014-2016, Linaro Limited + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef PLATFORM_CONFIG_H +#define PLATFORM_CONFIG_H + +/* Below are platform/SoC settings specific to stm platform flavors */ + +#if defined(PLATFORM_FLAVOR_b2260) + +#define CFG_TEE_CORE_NB_CORE 2 + +#ifndef CFG_DDR_START +#define CFG_DDR_START 0x40000000 +#define CFG_DDR_SIZE 0x40000000 +#endif +#ifndef CFG_DDR_TEETZ_RESERVED_START +#define CFG_DDR_TEETZ_RESERVED_START 0x7E000000 +#define CFG_DDR_TEETZ_RESERVED_SIZE 0x01E00000 +#endif +#ifndef CFG_CORE_TZSRAM_EMUL_START +#define CFG_CORE_TZSRAM_EMUL_START 0x7FE00000 +#endif + +#define CPU_IOMEM_BASE 0x08760000 +#define CPU_PORT_FILT_START 0x40000000 +#define CPU_PORT_FILT_END 0xC0000000 +#define STXHxxx_LPM_PERIPH_BASE 0x09700000 +#define RNG_BASE 0x08A89000 + +#define ASC_NUM 21 +#define UART_CONSOLE_BASE ST_ASC21_REGS_BASE + +#elif defined(PLATFORM_FLAVOR_cannes) + +#define CFG_TEE_CORE_NB_CORE 2 + +#ifndef CFG_DDR_START +#define CFG_DDR_START 0x40000000 +#define CFG_DDR_SIZE 0x80000000 +#endif +#ifndef CFG_DDR_TEETZ_RESERVED_START +#define CFG_DDR_TEETZ_RESERVED_START 0x93a00000 +#define CFG_DDR_TEETZ_RESERVED_SIZE 0x01000000 +#endif +#ifndef CFG_CORE_TZSRAM_EMUL_START +#define CFG_CORE_TZSRAM_EMUL_START 0x94a00000 +#endif + +#define CPU_IOMEM_BASE 0x08760000 +#define CPU_PORT_FILT_START 0x40000000 +#define CPU_PORT_FILT_END 0xC0000000 +#define STXHxxx_LPM_PERIPH_BASE 0x09400000 +#define RNG_BASE 0x08A89000 + +#define ASC_NUM 20 +#define UART_CONSOLE_BASE ST_ASC20_REGS_BASE + +#elif defined(PLATFORM_FLAVOR_orly2) + +#define CFG_TEE_CORE_NB_CORE 2 + +#ifndef CFG_DDR_START +#define CFG_DDR_START 0x40000000 +#define CFG_DDR_SIZE 0x40000000 +#define CFG_DDR1_START 0x80000000 +#define CFG_DDR1_SIZE 0x40000000 +#endif +#ifndef CFG_DDR_TEETZ_RESERVED_START +#define CFG_DDR_TEETZ_RESERVED_START 0x8F000000 +#define CFG_DDR_TEETZ_RESERVED_SIZE 0x00800000 +#endif + +#define CPU_IOMEM_BASE 0xFFFE0000 +#define CPU_PORT_FILT_START 0x40000000 +#define CPU_PORT_FILT_END 0x80000000 +#define STXHxxx_LPM_PERIPH_BASE 0xFE400000 +#define RNG_BASE 0xFEE80000 + +#define ASC_NUM 21 +#define UART_CONSOLE_BASE ST_ASC21_REGS_BASE + +#else /* defined(PLATFORM_FLAVOR_xxx) */ + +#error "Unknown platform flavor" + +#endif /* defined(PLATFORM_FLAVOR_xxx) */ + +/* Below are settings common to stm platform flavors */ + +/* + * CP15 Secure ConTroL Register (SCTLR + * + * - Round-Robin replac. for icache, btac, i/duTLB (bit14: RoundRobin) + */ +#define CPU_SCTLR_INIT 0x00004000 + +/* + * CP15 Auxiliary ConTroL Register (ACTRL) + * + * - core always in full SMP (FW bit0=1, SMP bit6=1) + * - L2 write full line of zero disabled (bit3=0) + * (keep WFLZ low. Will be set once outer L2 is ready) + */ + +#define CPU_ACTLR_INIT 0x00000041 + +/* + * CP15 NonSecure Access Control Register (NSACR) + * + * - NSec cannot change ACTRL.SMP (NS_SMP bit18=0) + * - Nsec can lockdown TLB (TL bit17=1) + * - NSec cannot access PLE (PLE bit16=0) + * - NSec can use SIMD/VFP (CP10/CP11) (bit15:14=2b00, bit11:10=2b11) + */ +#define CPU_NSACR_INIT 0x00020C00 + +/* + * CP15 Power Control Register (PCR) + * + * - no change latency, enable clk gating + */ +#define CPU_PCR_INIT 0x00000001 + + +/* + * SCU Secure Access Control / NonSecure Access Control + * + * SAC: Both secure CPU access SCU (bit[3:0]). + * NSAC: Both nonsec cpu access SCU (bit[3:0]), private timers (bit[7:4]) + * and global timers (bit[11:8]). + */ +#if !defined(SCU_SAC_INIT) || !defined(SCU_NSAC_INIT) +#define SCU_CPUS_MASK (SHIFT_U32(1, CFG_TEE_CORE_NB_CORE) - 1) + +#define SCU_SAC_INIT SCU_CPUS_MASK +#define SCU_NSAC_INIT (SHIFT_U32(SCU_CPUS_MASK, SCU_NSAC_SCU_SHIFT) | \ + SHIFT_U32(SCU_CPUS_MASK, SCU_NSAC_PTIMER_SHIFT) | \ + SHIFT_U32(SCU_CPUS_MASK, SCU_NSAC_GTIMER_SHIFT)) +#endif + +/* + * PL310 TAG RAM Control Register + * + * bit[10:8]:1 - 2 cycle of write accesses latency + * bit[6:4]:1 - 2 cycle of read accesses latency + * bit[2:0]:1 - 2 cycle of setup latency + */ +#ifndef PL310_TAG_RAM_CTRL_INIT +#define PL310_TAG_RAM_CTRL_INIT 0x00000111 +#endif + +/* + * PL310 DATA RAM Control Register + * + * bit[10:8]:2 - 3 cycle of write accesses latency + * bit[6:4]:2 - 3 cycle of read accesses latency + * bit[2:0]:2 - 3 cycle of setup latency + */ +#ifndef PL310_DATA_RAM_CTRL_INIT +#define PL310_DATA_RAM_CTRL_INIT 0x00000222 +#endif + +/* + * PL310 Auxiliary Control Register + * + * I/Dcache prefetch enabled (bit29:28=2b11) + * NS can access interrupts (bit27=1) + * NS can lockown cache lines (bit26=1) + * Pseudo-random replacement policy (bit25=0) + * Force write allocated (default) + * Shared attribute internally ignored (bit22=1, bit13=0) + * Parity disabled (bit21=0) + * Event monitor disabled (bit20=0) + * Platform fmavor specific way config: + * - way size (bit19:17) + * - way associciativity (bit16) + * Store buffer device limitation enabled (bit11=1) + * Cacheable accesses have high prio (bit10=0) + * Full Line Zero (FLZ) disabled (bit0=0) + */ +#ifndef PL310_AUX_CTRL_INIT +#define PL310_AUX_CTRL_INIT 0x3C480800 +#endif + +/* + * PL310 Prefetch Control Register + * + * Double linefill disabled (bit30=0) + * I/D prefetch enabled (bit29:28=2b11) + * Prefetch drop enabled (bit24=1) + * Incr double linefill disable (bit23=0) + * Prefetch offset = 7 (bit4:0) + */ +#define PL310_PREFETCH_CTRL_INIT 0x31000007 + +/* + * PL310 Power Register + * + * Dynamic clock gating enabled + * Standby mode enabled + */ +#define PL310_POWER_CTRL_INIT 0x00000003 + +/* + * SCU Control Register : CTRL = 0x00000065 + * - ic stanby enable=1 + * - scu standby enable=1 + * - scu enable=1 + */ +#define SCU_CTRL_INIT 0x00000065 + +/* + * TEE RAM layout without CFG_WITH_PAGER: + * + * +---------------------------------------+ <- CFG_DDR_TEETZ_RESERVED_START + * | TEE private secure | TEE_RAM | ^ + * | external memory +------------------+ | + * | | TA_RAM | | + * +---------------------------------------+ | CFG_DDR_TEETZ_RESERVED_SIZE + * | Non secure | SHM | | + * | shared memory | | | + * +---------------------------------------+ v + * + * TEE_RAM : default 1MByte + * PUB_RAM : default 2MByte + * TA_RAM : all what is left + * + * ---------------------------------------------------------------------------- + * TEE RAM layout with CFG_WITH_PAGER=y: + * + * +---------------------------------------+ <- CFG_CORE_TZSRAM_EMUL_START + * | TEE private highly | TEE_RAM | ^ + * | secure memory | | | CFG_CORE_TZSRAM_EMUL_SIZE + * +---------------------------------------+ v + * + * +---------------------------------------+ <- CFG_DDR_TEETZ_RESERVED_START + * | TEE private secure | TA_RAM | ^ + * | external memory | | | + * +---------------------------------------+ | CFG_DDR_TEETZ_RESERVED_SIZE + * | Non secure | SHM | | + * | shared memory | | | + * +---------------------------------------+ v + * + * TEE_RAM : default 256kByte + * TA_RAM : all what is left in DDR TEE reserved area + * PUB_RAM : default 2MByte + */ + +/* default locate shared memory at the end of the TEE reserved DDR */ +#ifndef CFG_SHMEM_SIZE +#define CFG_SHMEM_SIZE (2 * 1024 * 1024) +#endif + +#ifndef CFG_SHMEM_START +#define CFG_SHMEM_START (CFG_DDR_TEETZ_RESERVED_START + \ + CFG_DDR_TEETZ_RESERVED_SIZE - \ + CFG_SHMEM_SIZE) +#endif + +#if defined(CFG_WITH_PAGER) + +#define TZSRAM_BASE CFG_CORE_TZSRAM_EMUL_START +#define TZSRAM_SIZE CFG_CORE_TZSRAM_EMUL_SIZE + +#define TZDRAM_BASE CFG_DDR_TEETZ_RESERVED_START +#define TZDRAM_SIZE (CFG_DDR_TEETZ_RESERVED_SIZE - CFG_SHMEM_SIZE) + +#define CFG_TEE_RAM_START TZSRAM_BASE +#define CFG_TEE_RAM_PH_SIZE TZSRAM_SIZE + +#define CFG_TA_RAM_START TZDRAM_BASE +#define CFG_TA_RAM_SIZE TZDRAM_SIZE + +#else /* CFG_WITH_PAGER */ + +#define TZDRAM_BASE CFG_DDR_TEETZ_RESERVED_START +#define TZDRAM_SIZE (CFG_DDR_TEETZ_RESERVED_SIZE - CFG_SHMEM_SIZE) + +#define CFG_TEE_RAM_START TZDRAM_BASE +#ifndef CFG_TEE_RAM_PH_SIZE +#define CFG_TEE_RAM_PH_SIZE (1 * 1024 * 1024) +#endif + +#define CFG_TA_RAM_START (TZDRAM_BASE + CFG_TEE_RAM_PH_SIZE) +#define CFG_TA_RAM_SIZE (TZDRAM_SIZE - CFG_TEE_RAM_PH_SIZE) + +#endif /* !CFG_WITH_PAGER */ + +/* External DDR dies */ +#define DRAM0_BASE CFG_DDR_START +#define DRAM0_SIZE CFG_DDR_SIZE +#ifdef CFG_DDR1_START +#define DRAM1_BASE CFG_DDR1_START +#define DRAM1_SIZE CFG_DDR1_SIZE +#endif + +#ifndef CFG_TEE_RAM_VA_SIZE +#define CFG_TEE_RAM_VA_SIZE (1024 * 1024) +#endif + +#ifndef CFG_TEE_LOAD_ADDR +#define CFG_TEE_LOAD_ADDR CFG_TEE_RAM_START +#endif + +#define PL310_BASE (CPU_IOMEM_BASE + 0x2000) +#define GIC_DIST_BASE (CPU_IOMEM_BASE + 0x1000) +#define SCU_BASE (CPU_IOMEM_BASE + 0x0000) +#define GIC_CPU_BASE (CPU_IOMEM_BASE + 0x0100) +#define ST_ASC20_REGS_BASE (STXHxxx_LPM_PERIPH_BASE + 0x00130000) +#define ST_ASC21_REGS_BASE (STXHxxx_LPM_PERIPH_BASE + 0x00131000) + +/* Make stacks aligned to data cache line length */ +#define STACK_ALIGNMENT 32 + +#endif /* PLATFORM_CONFIG_H */ diff --git a/core/arch/arm/plat-stm/rng_support.c b/core/arch/arm/plat-stm/rng_support.c new file mode 100644 index 0000000..25b3893 --- /dev/null +++ b/core/arch/arm/plat-stm/rng_support.c @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2014-2016, STMicroelectronics International N.V. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <io.h> +#include <kernel/panic.h> +#include <mm/core_mmu.h> +#include <mm/core_memprot.h> +#include <platform_config.h> +#include <trace.h> + +#include "rng_support.h" + +/* Address of the register to read in the RNG IP */ +#define RNG_VAL_OFFSET 0x24 +#define RNG_STATUS_OFFSET 0x20 + +#define RNG_STATUS_ERR0 BIT32(0) +#define RNG_STATUS_ERR1 BIT32(1) +#define RNG_STATUS_FULL BIT32(5) + +static vaddr_t rng_base(void) +{ + static void *va __early_bss; + + if (cpu_mmu_enabled()) { + if (!va) + va = phys_to_virt(RNG_BASE, MEM_AREA_IO_SEC); + return (vaddr_t)va; + } + return RNG_BASE; +} + +static inline int hwrng_waithost_fifo_full(void) +{ + uint32_t status; + + do { + status = read32(rng_base() + RNG_STATUS_OFFSET); + } while (!(status & RNG_STATUS_FULL)); + + if (status & (RNG_STATUS_ERR0 | RNG_STATUS_ERR1)) + return 1; + + return 0; +} + +uint8_t hw_get_random_byte(void) +{ + /* + * Only the HW RNG IP is used to generate the value through the + * HOST interface. + * + * @see the document rng_fspec_revG_120720.pdf for details + * + * - HOST FIFO size = 8x8b (64b) + * - LSB (16b) of the RNG_VAL register allows to read 16b + * - bit5 of the RNG_STATUS register allows to known if the HOST + * FIFO is full or not. + * - bit1,0 of the RNG_STATUS register allows to known if the + * data are valid. + * + * Main principle: + * For performance reason, a local SW fifo is used to store the + * content of the HOST FIFO (max size = 8bytes). When a random + * value is expected, this SW fifo is used to return a stored value. + * When the local SW fifo is empty, it is filled with the HOST FIFO + * according the following sequence: + * + * - wait HOST FIFO full + * o Indicates that max 8-bytes (64b) are available + * o This is mandatory to guarantee that a valid data is + * available. No STATUS bit to indicate that the HOST FIFO + * is empty is provided. + * - check STATUS bits + * - update the local SW fifo with the HOST FIFO + * + * This avoid to wait at each iteration that a valid random value is + * available. _LOCAL_FIFO_SIZE indicates the size of the local SW fifo. + * + */ + + +#define _LOCAL_FIFO_SIZE 8 /* min 2, 4, 6, max 8 */ + + static uint8_t lfifo[_LOCAL_FIFO_SIZE]; /* local fifo */ + static int pos = -1; + + static int nbcall; /* debug purpose - 0 is the initial value*/ + + volatile uint32_t tmpval[_LOCAL_FIFO_SIZE/2]; + uint8_t value; + int i; + + nbcall++; + + /* Retrieve data from local fifo */ + if (pos >= 0) { + pos++; + value = lfifo[pos]; + if (pos == (_LOCAL_FIFO_SIZE - 1)) + pos = -1; + return value; + } + + if (hwrng_waithost_fifo_full()) + return 0; + + /* Read the FIFO according the number of expected element */ + for (i = 0; i < _LOCAL_FIFO_SIZE / 2; i++) + tmpval[i] = read32(rng_base() + RNG_VAL_OFFSET) & 0xFFFF; + + /* Update the local SW fifo for next request */ + pos = 0; + for (i = 0; i < _LOCAL_FIFO_SIZE / 2; i++) { + lfifo[pos] = tmpval[i] & 0xFF; + pos++; + lfifo[pos] = (tmpval[i] >> 8) & 0xFF; + pos++; + }; + + pos = 0; + return lfifo[pos]; +} diff --git a/core/arch/arm/plat-stm/sub.mk b/core/arch/arm/plat-stm/sub.mk new file mode 100644 index 0000000..d16bb72 --- /dev/null +++ b/core/arch/arm/plat-stm/sub.mk @@ -0,0 +1,6 @@ +global-incdirs-y += . + +srcs-y += rng_support.c +srcs-y += asc.S +srcs-y += tz_a9init.S +srcs-y += main.c diff --git a/core/arch/arm/plat-stm/tz_a9init.S b/core/arch/arm/plat-stm/tz_a9init.S new file mode 100644 index 0000000..aee7dbe --- /dev/null +++ b/core/arch/arm/plat-stm/tz_a9init.S @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2014-2016, STMicroelectronics International N.V. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <arm32.h> +#include <arm32_macros.S> +#include <arm32_macros_cortex_a9.S> +#include <asm.S> +#include <kernel/tz_ssvce_def.h> +#include <kernel/unwind.h> +#include <platform_config.h> + +.section .text +.balign 4 +.code 32 + +/* + * void arm_cl2_enable(vaddr_t pl310_base) - Memory Cache Level2 Enable Function + * + * If PL310 supports FZLW, enable also FZL in A9 core + * + * Use scratables registers R0-R3. + * No stack usage. + * LR store return address. + * Trap CPU in case of error. + * TODO: to be moved to PL310 code (tz_svce_pl310.S ?) + */ +FUNC arm_cl2_enable , : +UNWIND( .fnstart) + + /* Enable PL310 ctrl -> only set lsb bit */ + mov r1, #0x1 + str r1, [r0, #PL310_CTRL] + + /* if L2 FLZW enable, enable in L1 */ + ldr r1, [r0, #PL310_AUX_CTRL] + tst r1, #(1 << 0) /* test AUX_CTRL[FLZ] */ + read_actlr r0 + orrne r0, r0, #(1 << 3) /* enable ACTLR[FLZW] */ + write_actlr r0 + + mov pc, lr + +UNWIND( .fnend) +END_FUNC arm_cl2_enable + +/* + * Cortex A9 configuration early configuration + * + * Use scratables registers R0-R3. + * No stack usage. + * LR store return address. + * Trap CPU in case of error. + */ +FUNC plat_cpu_reset_early , : +UNWIND( .fnstart) + + movw r0, #(CPU_SCTLR_INIT & 0xFFFF) + movt r0, #((CPU_SCTLR_INIT >> 16) & 0xFFFF) + write_sctlr r0 + + movw r0, #(CPU_ACTLR_INIT & 0xFFFF) + movt r0, #((CPU_ACTLR_INIT >> 16) & 0xFFFF) + write_actlr r0 + + movw r0, #(CPU_NSACR_INIT & 0xFFFF) + movt r0, #((CPU_NSACR_INIT >> 16) & 0xFFFF) + write_nsacr r0 + + movw r0, #(CPU_PCR_INIT & 0xFFFF) + movt r0, #((CPU_PCR_INIT >> 16) & 0xFFFF) + write_pcr r0 + + mov pc, lr + +UNWIND( .fnend) +END_FUNC plat_cpu_reset_early + |