path: root/documentation/
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authorr.tyminski <>2017-06-05 10:44:25 (GMT)
committerr.tyminski <>2017-06-05 10:44:25 (GMT)
commit146aec115cd05a164a88e6d7b07435c57a33817f (patch)
treed8099075c92576b1928069af274f9b833aca996e /documentation/
parentf9a43781767007462965b21f3f518c4cfc0744c7 (diff)
Update from upstream to 2.4.0 versionupstream/2.4.0upstreamrefs/changes/68/132468/1
Change-Id: I2b3a30f20684d6629fe379d9cd7895aff759c301
Diffstat (limited to 'documentation/')
1 files changed, 12 insertions, 2 deletions
diff --git a/documentation/ b/documentation/
index 7ca8121..8063357 100644
--- a/documentation/
+++ b/documentation/
@@ -19,8 +19,18 @@ The processor is configured to use:
* Monitor vector for SMC exceptions
* State vector for IRQ exceptions
-Interrupts handled by secure world are sent as FIQs and interrupts handled
-by normal world are sent as IRQs.
+Two types of interrupt are defined in optee_os:
+* Native interrupt - The interrupt handled by optee_os
+ (for example: secure interrupt)
+* Foreign interrupt - The interrupt not handled by optee_os
+ (for example: non-secure interrupt which is handled by normal world)
+For ARM GICv2 mode, native interrupt is sent as FIQ and foreign interrupt is
+sent as IRQ.
+For ARM GICv3 mode, foreign interrupt is sent as FIQ which could be handled
+by either secure world (EL3 in AArch64) or normal world. This mode is not
+supported yet.
Since IRQs are received using the state vector the actual vector used
depends on the current state of the CPU. If the NS (non-secure) bit in SCR