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authorr.tyminski <r.tyminski@partner.samsung.com>2017-06-05 10:44:25 (GMT)
committerr.tyminski <r.tyminski@partner.samsung.com>2017-06-05 10:44:25 (GMT)
commit146aec115cd05a164a88e6d7b07435c57a33817f (patch)
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Update from upstream to 2.4.0 versionupstream/2.4.0upstreamrefs/changes/68/132468/1
Change-Id: I2b3a30f20684d6629fe379d9cd7895aff759c301
Diffstat (limited to 'documentation/interrupt_handling.md')
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1 files changed, 12 insertions, 2 deletions
diff --git a/documentation/interrupt_handling.md b/documentation/interrupt_handling.md
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--- a/documentation/interrupt_handling.md
+++ b/documentation/interrupt_handling.md
@@ -19,8 +19,18 @@ The processor is configured to use:
* Monitor vector for SMC exceptions
* State vector for IRQ exceptions
-Interrupts handled by secure world are sent as FIQs and interrupts handled
-by normal world are sent as IRQs.
+Two types of interrupt are defined in optee_os:
+* Native interrupt - The interrupt handled by optee_os
+ (for example: secure interrupt)
+* Foreign interrupt - The interrupt not handled by optee_os
+ (for example: non-secure interrupt which is handled by normal world)
+
+For ARM GICv2 mode, native interrupt is sent as FIQ and foreign interrupt is
+sent as IRQ.
+
+For ARM GICv3 mode, foreign interrupt is sent as FIQ which could be handled
+by either secure world (EL3 in AArch64) or normal world. This mode is not
+supported yet.
Since IRQs are received using the state vector the actual vector used
depends on the current state of the CPU. If the NS (non-secure) bit in SCR