Update from upstream to 2.4.0 versionupstream/2.4.0upstream

Change-Id: I2b3a30f20684d6629fe379d9cd7895aff759c301

1 files changed, 38 insertions, 11 deletions

diff --git a/core/arch/arm/plat-vexpress/platform_config.h b/core/arch/arm/plat-vexpress/platform_config.h
index bd006ca..45d9993 100644
--- a/core/arch/arm/plat-vexpress/platform_config.h
+++ b/core/arch/arm/plat-vexpress/platform_config.h
@@ -39,6 +39,13 @@
 #endif
 #endif /*ARM64*/
 
+/* SDP enable but no pool defined: reserve 4MB for SDP tests */
+#if defined(CFG_SECURE_DATA_PATH) && !defined(CFG_TEE_SDP_MEM_BASE)
+#define CFG_TEE_SDP_MEM_TEST_SIZE	0x00400000
+#else
+#define CFG_TEE_SDP_MEM_TEST_SIZE	0
+#endif
+
 #if defined(PLATFORM_FLAVOR_fvp)
 
 #define GIC_BASE		0x2c000000
@@ -187,23 +194,25 @@
 #define DRAM0_TEERES_BASE	(DRAM0_BASE + DRAM0_SIZE)
 #define DRAM0_TEERES_SIZE	CFG_SHMEM_SIZE
 
+#define SECRAM_BASE		0x0e000000
+#define SECRAM_SIZE		0x01000000
+
 #ifdef CFG_WITH_PAGER
 
 /* Emulated SRAM */
-#define TZSRAM_BASE		0x0e000000
+#define TZSRAM_BASE		SECRAM_BASE
 #define TZSRAM_SIZE		CFG_CORE_TZSRAM_EMUL_SIZE
 
 #define TZDRAM_BASE		(TZSRAM_BASE + TZSRAM_SIZE)
-#define TZDRAM_SIZE		(0x01000000 - TZSRAM_SIZE)
+#define TZDRAM_SIZE		(SECRAM_SIZE - TZSRAM_SIZE)
 
 #else /* CFG_WITH_PAGER */
 
-#define TZDRAM_BASE		0x0e000000
-#define TZDRAM_SIZE		0x01000000
+#define TZDRAM_BASE		SECRAM_BASE
+#define TZDRAM_SIZE		SECRAM_SIZE
 
 #endif /* CFG_WITH_PAGER */
 
-
 #define CFG_TEE_CORE_NB_CORE	2
 
 #define CFG_SHMEM_START		(DRAM0_TEERES_BASE + \
@@ -226,8 +235,12 @@
 #define DRAM0_TEERES_BASE	(DRAM0_BASE + DRAM0_SIZE)
 #define DRAM0_TEERES_SIZE	CFG_SHMEM_SIZE
 
-#define TZDRAM_BASE		0x0e100000
-#define TZDRAM_SIZE		0x00f00000
+#define SECRAM_BASE		0x0e000000
+#define SECRAM_SIZE		0x01000000
+
+/* First 1MByte of the secure RAM is reserved to ARM-TF runtime services */
+#define TZDRAM_BASE		(SECRAM_BASE + 0x00100000)
+#define TZDRAM_SIZE		(SECRAM_SIZE - 0x00100000)
 
 #define CFG_TEE_CORE_NB_CORE	2
 
@@ -254,28 +267,42 @@
  * | TZSRAM | TEE_RAM |
  * +--------+---------+
  * | TZDRAM | TA_RAM  |
+ * |        +---------+
+ * |        | SDP RAM | (SDP test pool, optional)
  * +--------+---------+
  */
 #define CFG_TEE_RAM_PH_SIZE	TZSRAM_SIZE
 #define CFG_TEE_RAM_START	TZSRAM_BASE
 #define CFG_TA_RAM_START	ROUNDUP(TZDRAM_BASE, CORE_MMU_DEVICE_SIZE)
-#define CFG_TA_RAM_SIZE		ROUNDDOWN(TZDRAM_SIZE, CORE_MMU_DEVICE_SIZE)
+
 #else
 /*
  * Assumes that either TZSRAM isn't large enough or TZSRAM doesn't exist,
  * everything is in TZDRAM.
  * +------------------+
  * |        | TEE_RAM |
- * + TZDRAM +---------+
+ * | TZDRAM +---------+
  * |        | TA_RAM  |
+ * |        +---------+
+ * |        | SDP RAM | (test pool, optional)
  * +--------+---------+
  */
 #define CFG_TEE_RAM_PH_SIZE	CFG_TEE_RAM_VA_SIZE
 #define CFG_TEE_RAM_START	TZDRAM_BASE
-#define CFG_TA_RAM_START	ROUNDUP((TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE), \
+#define CFG_TA_RAM_START	ROUNDUP(TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE, \
 					CORE_MMU_DEVICE_SIZE)
-#define CFG_TA_RAM_SIZE		ROUNDDOWN((TZDRAM_SIZE - CFG_TEE_RAM_VA_SIZE), \
+#endif
+
+#define CFG_TA_RAM_SIZE		ROUNDDOWN(TZDRAM_SIZE - \
+					  (CFG_TA_RAM_START - TZDRAM_BASE) - \
+					  CFG_TEE_SDP_MEM_TEST_SIZE, \
 					  CORE_MMU_DEVICE_SIZE)
+
+/* Secure data path test memory pool: located at end of TA RAM */
+#if CFG_TEE_SDP_MEM_TEST_SIZE
+#define CFG_TEE_SDP_MEM_SIZE		CFG_TEE_SDP_MEM_TEST_SIZE
+#define CFG_TEE_SDP_MEM_BASE		(TZDRAM_BASE + TZDRAM_SIZE - \
+						CFG_TEE_SDP_MEM_SIZE)
 #endif
 
 #ifdef GIC_BASE