Initial commit with upstream sources

Change-Id: Ie9460111f21fc955102fd8732a0173b2d0499a4a

1 files changed, 101 insertions, 0 deletions

diff --git a/core/arch/arm/plat-stm/tz_a9init.S b/core/arch/arm/plat-stm/tz_a9init.S
new file mode 100644
index 0000000..aee7dbe
--- /dev/null
+++ b/core/arch/arm/plat-stm/tz_a9init.S
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2014-2016, STMicroelectronics International N.V.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arm32.h>
+#include <arm32_macros.S>
+#include <arm32_macros_cortex_a9.S>
+#include <asm.S>
+#include <kernel/tz_ssvce_def.h>
+#include <kernel/unwind.h>
+#include <platform_config.h>
+
+.section .text
+.balign 4
+.code 32
+
+/*
+ * void arm_cl2_enable(vaddr_t pl310_base) - Memory Cache Level2 Enable Function
+ *
+ * If PL310 supports FZLW, enable also FZL in A9 core
+ *
+ * Use scratables registers R0-R3.
+ * No stack usage.
+ * LR store return address.
+ * Trap CPU in case of error.
+ * TODO: to be moved to PL310 code (tz_svce_pl310.S ?)
+ */
+FUNC arm_cl2_enable , :
+UNWIND(	.fnstart)
+
+	/* Enable PL310 ctrl -> only set lsb bit */
+	mov  r1, #0x1
+	str  r1, [r0, #PL310_CTRL]
+
+	/* if L2 FLZW enable, enable in L1 */
+	ldr  r1, [r0, #PL310_AUX_CTRL]
+	tst  r1, #(1 << 0) /* test AUX_CTRL[FLZ] */
+	read_actlr r0
+	orrne r0, r0, #(1 << 3) /* enable ACTLR[FLZW] */
+	write_actlr r0
+
+	mov pc, lr
+
+UNWIND(	.fnend)
+END_FUNC arm_cl2_enable
+
+/*
+ * Cortex A9 configuration early configuration
+ *
+ * Use scratables registers R0-R3.
+ * No stack usage.
+ * LR store return address.
+ * Trap CPU in case of error.
+ */
+FUNC plat_cpu_reset_early , :
+UNWIND(	.fnstart)
+
+	movw r0, #(CPU_SCTLR_INIT & 0xFFFF)
+	movt r0, #((CPU_SCTLR_INIT >> 16) & 0xFFFF)
+	write_sctlr r0
+
+	movw r0, #(CPU_ACTLR_INIT & 0xFFFF)
+	movt r0, #((CPU_ACTLR_INIT >> 16) & 0xFFFF)
+	write_actlr r0
+
+	movw r0, #(CPU_NSACR_INIT & 0xFFFF)
+	movt r0, #((CPU_NSACR_INIT >> 16) & 0xFFFF)
+	write_nsacr r0
+
+	movw r0, #(CPU_PCR_INIT & 0xFFFF)
+	movt r0, #((CPU_PCR_INIT >> 16) & 0xFFFF)
+	write_pcr r0
+
+	mov pc, lr
+
+UNWIND(	.fnend)
+END_FUNC plat_cpu_reset_early
+