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authorr.tyminski <r.tyminski@partner.samsung.com>2017-05-29 09:42:10 (GMT)
committerr.tyminski <r.tyminski@partner.samsung.com>2017-05-29 09:49:50 (GMT)
commitf9a43781767007462965b21f3f518c4cfc0744c7 (patch)
tree201509439b1d9798256227794dae6774345adf43 /core/arch/arm/plat-imx
parent1fed20f5471aa0dad5e4b4f79d1f2843ac88734f (diff)
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Initial commit with upstream sourcesrefs/changes/71/131471/1
Change-Id: Ie9460111f21fc955102fd8732a0173b2d0499a4a
Diffstat (limited to 'core/arch/arm/plat-imx')
-rw-r--r--core/arch/arm/plat-imx/a9_plat_init.S109
-rw-r--r--core/arch/arm/plat-imx/conf.mk34
-rw-r--r--core/arch/arm/plat-imx/imx6ul.c57
-rw-r--r--core/arch/arm/plat-imx/imx_pl310.c63
-rw-r--r--core/arch/arm/plat-imx/kern.ld.S1
-rw-r--r--core/arch/arm/plat-imx/link.mk1
-rw-r--r--core/arch/arm/plat-imx/main.c202
-rw-r--r--core/arch/arm/plat-imx/platform_config.h410
-rw-r--r--core/arch/arm/plat-imx/psci.c78
-rw-r--r--core/arch/arm/plat-imx/sub.mk9
10 files changed, 964 insertions, 0 deletions
diff --git a/core/arch/arm/plat-imx/a9_plat_init.S b/core/arch/arm/plat-imx/a9_plat_init.S
new file mode 100644
index 0000000..64d03f5
--- /dev/null
+++ b/core/arch/arm/plat-imx/a9_plat_init.S
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2014, STMicroelectronics International N.V.
+ * All rights reserved.
+ * Copyright (c) 2016, Wind River Systems.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Entry points for the A9 inits, A9 revision specific or not.
+ * It is assume no stack is available when these routines are called.
+ * It is assume each routine is called with return address in LR
+ * and with ARM registers R0, R1, R2, R3 being scratchable.
+ */
+
+#include <arm32.h>
+#include <arm32_macros.S>
+#include <arm32_macros_cortex_a9.S>
+#include <asm.S>
+#include <kernel/tz_ssvce_def.h>
+#include <kernel/unwind.h>
+#include <platform_config.h>
+
+.section .text
+.balign 4
+.code 32
+
+/*
+ * Cortex A9 early configuration
+ *
+ * Use registers R0-R3.
+ * No stack usage.
+ * LR store return address.
+ * Trap CPU in case of error.
+ */
+FUNC plat_cpu_reset_early , :
+UNWIND( .fnstart)
+
+ /*
+ * Disallow NSec to mask FIQ [bit4: FW=0]
+ * Allow NSec to manage Imprecise Abort [bit5: AW=1]
+ * Imprecise Abort trapped to Abort Mode [bit3: EA=0]
+ * In Sec world, FIQ trapped to FIQ Mode [bit2: FIQ=0]
+ * IRQ always trapped to IRQ Mode [bit1: IRQ=0]
+ * Secure World [bit0: NS=0]
+ */
+ mov r0, #SCR_AW
+ write_scr r0
+
+ /*
+ * Mandated HW config loaded
+ *
+ * SCTLR = 0x00004000
+ * - Round-Robin replac. for icache, btac, i/duTLB (bit14: RoundRobin)
+ *
+ * ACTRL = 0x00000041
+ * - core always in full SMP (FW bit0=1, SMP bit6=1)
+ * - L2 write full line of zero disabled (bit3=0)
+ * (keep WFLZ low. Will be set once outer L2 is ready)
+ *
+ * NSACR = 0x00020C00
+ * - NSec cannot change ACTRL.SMP (NS_SMP bit18=0)
+ * - Nsec can lockdown TLB (TL bit17=1)
+ * - NSec cannot access PLE (PLE bit16=0)
+ * - NSec can use SIMD/VFP (CP10/CP11) (bit15:14=2b00, bit11:10=2b11)
+ *
+ * PCR = 0x00000001
+ * - no change latency, enable clk gating
+ */
+ movw r0, #0x4000
+ movt r0, #0x0000
+ write_sctlr r0
+
+ movw r0, #0x0041
+ movt r0, #0x0000
+ write_actlr r0
+
+ movw r0, #0x0C00
+ movt r0, #0x0002
+ write_nsacr r0
+
+ movw r0, #0x0000
+ movt r0, #0x0001
+ write_pcr r0
+
+ mov pc, lr
+UNWIND( .fnend)
+END_FUNC plat_cpu_reset_early
diff --git a/core/arch/arm/plat-imx/conf.mk b/core/arch/arm/plat-imx/conf.mk
new file mode 100644
index 0000000..785736a
--- /dev/null
+++ b/core/arch/arm/plat-imx/conf.mk
@@ -0,0 +1,34 @@
+PLATFORM_FLAVOR ?= mx6ulevk
+
+ifeq ($(PLATFORM_FLAVOR),mx6ulevk)
+arm32-platform-cpuarch := cortex-a7
+endif
+ifeq ($(PLATFORM_FLAVOR),$(filter $(PLATFORM_FLAVOR),mx6qsabrelite mx6qsabresd))
+arm32-platform-cpuarch := cortex-a9
+endif
+arm32-platform-cflags += -mcpu=$(arm32-platform-cpuarch)
+arm32-platform-aflags += -mcpu=$(arm32-platform-cpuarch)
+core_arm32-platform-aflags += -mfpu=neon
+
+$(call force,CFG_ARM32_core,y)
+$(call force,CFG_GENERIC_BOOT,y)
+$(call force,CFG_GIC,y)
+$(call force,CFG_IMX_UART,y)
+$(call force,CFG_PM_STUBS,y)
+$(call force,CFG_WITH_SOFTWARE_PRNG,y)
+ifeq ($(PLATFORM_FLAVOR),mx6ulevk)
+$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
+endif
+ifeq ($(PLATFORM_FLAVOR),$(filter $(PLATFORM_FLAVOR),mx6qsabrelite mx6qsabresd))
+$(call force,CFG_PL310,y)
+$(call force,CFG_PL310_LOCKED,y)
+$(call force,CFG_SECURE_TIME_SOURCE_REE,y)
+
+CFG_BOOT_SYNC_CPU ?= y
+CFG_BOOT_SECONDARY_REQUEST ?= y
+endif
+
+ta-targets = ta_arm32
+
+CFG_CRYPTO_SIZE_OPTIMIZATION ?= n
+CFG_WITH_STACK_CANARIES ?= y
diff --git a/core/arch/arm/plat-imx/imx6ul.c b/core/arch/arm/plat-imx/imx6ul.c
new file mode 100644
index 0000000..795c750
--- /dev/null
+++ b/core/arch/arm/plat-imx/imx6ul.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arm32.h>
+#include <io.h>
+#include <kernel/generic_boot.h>
+#include <platform_config.h>
+#include <stdint.h>
+
+static void init_csu(void)
+{
+ uintptr_t addr;
+
+ /* first grant all peripherals */
+ for (addr = CSU_BASE + CSU_CSL_START;
+ addr != CSU_BASE + CSU_CSL_END;
+ addr += 4)
+ write32(CSU_ACCESS_ALL, addr);
+
+ /* lock the settings */
+ for (addr = CSU_BASE + CSU_CSL_START;
+ addr != CSU_BASE + CSU_CSL_END;
+ addr += 4)
+ write32(read32(addr) | CSU_SETTING_LOCK, addr);
+}
+
+/* MMU not enabled now */
+void plat_cpu_reset_late(void)
+{
+ init_csu();
+}
diff --git a/core/arch/arm/plat-imx/imx_pl310.c b/core/arch/arm/plat-imx/imx_pl310.c
new file mode 100644
index 0000000..fcad225
--- /dev/null
+++ b/core/arch/arm/plat-imx/imx_pl310.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <arm32.h>
+#include <io.h>
+#include <kernel/generic_boot.h>
+#include <kernel/tz_ssvce_def.h>
+#include <kernel/tz_ssvce_pl310.h>
+#include <platform_config.h>
+#include <stdint.h>
+
+void arm_cl2_config(vaddr_t pl310_base)
+{
+ /* Disable PL310 */
+ write32(0, pl310_base + PL310_CTRL);
+
+ write32(PL310_TAG_RAM_CTRL_INIT, pl310_base + PL310_TAG_RAM_CTRL);
+ write32(PL310_DATA_RAM_CTRL_INIT, pl310_base + PL310_DATA_RAM_CTRL);
+ write32(PL310_AUX_CTRL_INIT, pl310_base + PL310_AUX_CTRL);
+ write32(PL310_PREFETCH_CTRL_INIT, pl310_base + PL310_PREFETCH_CTRL);
+ write32(PL310_POWER_CTRL_INIT, pl310_base + PL310_POWER_CTRL);
+
+ /* invalidate all cache ways */
+ arm_cl2_invbyway(pl310_base);
+}
+
+void arm_cl2_enable(vaddr_t pl310_base)
+{
+ uint32_t val;
+
+ /* Enable PL310 ctrl -> only set lsb bit */
+ write32(1, pl310_base + PL310_CTRL);
+
+ /* if L2 FLZW enable, enable in L1 */
+ val = read32(pl310_base + PL310_AUX_CTRL);
+ if (val & 1)
+ write_actlr(read_actlr() | (1 << 3));
+}
diff --git a/core/arch/arm/plat-imx/kern.ld.S b/core/arch/arm/plat-imx/kern.ld.S
new file mode 100644
index 0000000..8d794ee
--- /dev/null
+++ b/core/arch/arm/plat-imx/kern.ld.S
@@ -0,0 +1 @@
+#include "../kernel/kern.ld.S"
diff --git a/core/arch/arm/plat-imx/link.mk b/core/arch/arm/plat-imx/link.mk
new file mode 100644
index 0000000..448ab89
--- /dev/null
+++ b/core/arch/arm/plat-imx/link.mk
@@ -0,0 +1 @@
+include core/arch/arm/kernel/link.mk
diff --git a/core/arch/arm/plat-imx/main.c b/core/arch/arm/plat-imx/main.c
new file mode 100644
index 0000000..edfbc37
--- /dev/null
+++ b/core/arch/arm/plat-imx/main.c
@@ -0,0 +1,202 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * All rights reserved.
+ * Copyright (c) 2016, Wind River Systems.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arm32.h>
+#include <console.h>
+#include <drivers/gic.h>
+#include <drivers/imx_uart.h>
+#include <io.h>
+#include <kernel/generic_boot.h>
+#include <kernel/misc.h>
+#include <kernel/panic.h>
+#include <kernel/pm_stubs.h>
+#include <mm/core_mmu.h>
+#include <mm/core_memprot.h>
+#include <platform_config.h>
+#include <stdint.h>
+#include <sm/optee_smc.h>
+#include <tee/entry_fast.h>
+#include <tee/entry_std.h>
+
+#if defined(PLATFORM_FLAVOR_mx6qsabrelite) || \
+ defined(PLATFORM_FLAVOR_mx6qsabresd)
+#include <kernel/tz_ssvce_pl310.h>
+#endif
+
+static void main_fiq(void);
+static struct gic_data gic_data;
+
+static const struct thread_handlers handlers = {
+ .std_smc = tee_entry_std,
+ .fast_smc = tee_entry_fast,
+ .fiq = main_fiq,
+ .cpu_on = pm_panic,
+ .cpu_off = pm_panic,
+ .cpu_suspend = pm_panic,
+ .cpu_resume = pm_panic,
+ .system_off = pm_panic,
+ .system_reset = pm_panic,
+};
+
+register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, CORE_MMU_DEVICE_SIZE);
+register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_DEVICE_SIZE);
+
+#if defined(PLATFORM_FLAVOR_mx6qsabrelite) || \
+ defined(PLATFORM_FLAVOR_mx6qsabresd)
+register_phys_mem(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_DEVICE_SIZE);
+register_phys_mem(MEM_AREA_IO_SEC, SRC_BASE, CORE_MMU_DEVICE_SIZE);
+#endif
+
+const struct thread_handlers *generic_boot_get_handlers(void)
+{
+ return &handlers;
+}
+
+static void main_fiq(void)
+{
+ panic();
+}
+
+#if defined(PLATFORM_FLAVOR_mx6qsabrelite) || \
+ defined(PLATFORM_FLAVOR_mx6qsabresd)
+void plat_cpu_reset_late(void)
+{
+ uintptr_t addr;
+
+ if (!get_core_pos()) {
+ /* primary core */
+#if defined(CFG_BOOT_SYNC_CPU)
+ /* set secondary entry address and release core */
+ write32(CFG_TEE_LOAD_ADDR, SRC_BASE + SRC_GPR1 + 8);
+ write32(CFG_TEE_LOAD_ADDR, SRC_BASE + SRC_GPR1 + 16);
+ write32(CFG_TEE_LOAD_ADDR, SRC_BASE + SRC_GPR1 + 24);
+
+ write32(SRC_SCR_CPU_ENABLE_ALL, SRC_BASE + SRC_SCR);
+#endif
+
+ /* SCU config */
+ write32(SCU_INV_CTRL_INIT, SCU_BASE + SCU_INV_SEC);
+ write32(SCU_SAC_CTRL_INIT, SCU_BASE + SCU_SAC);
+ write32(SCU_NSAC_CTRL_INIT, SCU_BASE + SCU_NSAC);
+
+ /* SCU enable */
+ write32(read32(SCU_BASE + SCU_CTRL) | 0x1,
+ SCU_BASE + SCU_CTRL);
+
+ /* configure imx6 CSU */
+
+ /* first grant all peripherals */
+ for (addr = CSU_BASE + CSU_CSL_START;
+ addr != CSU_BASE + CSU_CSL_END;
+ addr += 4)
+ write32(CSU_ACCESS_ALL, addr);
+
+ /* lock the settings */
+ for (addr = CSU_BASE + CSU_CSL_START;
+ addr != CSU_BASE + CSU_CSL_END;
+ addr += 4)
+ write32(read32(addr) | CSU_SETTING_LOCK, addr);
+ }
+}
+#endif
+
+static vaddr_t console_base(void)
+{
+ static void *va;
+
+ if (cpu_mmu_enabled()) {
+ if (!va)
+ va = phys_to_virt(CONSOLE_UART_BASE,
+ MEM_AREA_IO_NSEC);
+ return (vaddr_t)va;
+ }
+ return CONSOLE_UART_BASE;
+}
+
+void console_init(void)
+{
+ vaddr_t base = console_base();
+
+ imx_uart_init(base);
+}
+
+void console_putc(int ch)
+{
+ vaddr_t base = console_base();
+
+ /* If \n, also do \r */
+ if (ch == '\n')
+ imx_uart_putc('\r', base);
+ imx_uart_putc(ch, base);
+}
+
+void console_flush(void)
+{
+ vaddr_t base = console_base();
+
+ imx_uart_flush_tx_fifo(base);
+}
+
+void main_init_gic(void)
+{
+ vaddr_t gicc_base;
+ vaddr_t gicd_base;
+
+ gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET,
+ MEM_AREA_IO_SEC);
+ gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET,
+ MEM_AREA_IO_SEC);
+
+ if (!gicc_base || !gicd_base)
+ panic();
+
+ /* Initialize GIC */
+ gic_init(&gic_data, gicc_base, gicd_base);
+ itr_init(&gic_data.chip);
+}
+
+#if defined(PLATFORM_FLAVOR_mx6qsabrelite) || \
+ defined(PLATFORM_FLAVOR_mx6qsabresd)
+vaddr_t pl310_base(void)
+{
+ static void *va __early_bss;
+
+ if (cpu_mmu_enabled()) {
+ if (!va)
+ va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC);
+ return (vaddr_t)va;
+ }
+ return PL310_BASE;
+}
+
+void main_secondary_init_gic(void)
+{
+ gic_cpu_init(&gic_data);
+}
+#endif
diff --git a/core/arch/arm/plat-imx/platform_config.h b/core/arch/arm/plat-imx/platform_config.h
new file mode 100644
index 0000000..8e55ee8
--- /dev/null
+++ b/core/arch/arm/plat-imx/platform_config.h
@@ -0,0 +1,410 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * All rights reserved.
+ * Copyright (c) 2016, Wind River Systems.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef PLATFORM_CONFIG_H
+#define PLATFORM_CONFIG_H
+
+#define STACK_ALIGNMENT 64
+
+/* For i.MX 6UltraLite EVK board */
+
+#if defined(PLATFORM_FLAVOR_mx6ulevk)
+
+#ifdef CFG_WITH_PAGER
+#error "Pager not supported for platform mx6ulevk"
+#endif
+#ifdef CFG_WITH_LPAE
+#error "LPAE not supported for now"
+#endif
+
+#define GIC_BASE 0xA00000
+#define GIC_SIZE 0x8000
+#define GICC_OFFSET 0x2000
+#define GICD_OFFSET 0x1000
+#define UART0_BASE 0x2020000
+#define UART1_BASE 0x21E8000
+#define UART2_BASE 0x21EC000
+
+#define AHB1_BASE 0x02000000
+#define AHB1_SIZE 0x100000
+#define AHB2_BASE 0x02100000
+#define AHB2_SIZE 0x100000
+#define AHB3_BASE 0x02200000
+#define AHB3_SIZE 0x100000
+
+#define AIPS_TZ1_BASE_ADDR 0x02000000
+#define AIPS1_OFF_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x80000)
+
+#define DRAM0_BASE 0x80000000
+#define DRAM0_SIZE 0x20000000
+
+#define CFG_TEE_CORE_NB_CORE 1
+
+#define DDR_PHYS_START DRAM0_BASE
+#define DDR_SIZE DRAM0_SIZE
+
+#define CFG_DDR_START DDR_PHYS_START
+#define CFG_DDR_SIZE DDR_SIZE
+
+/* Full GlobalPlatform test suite requires CFG_SHMEM_SIZE to be at least 2MB */
+#define CFG_SHMEM_START (TZDRAM_BASE - 0x100000)
+#define CFG_SHMEM_SIZE 0x100000
+
+/* Location of trusted dram on imx */
+#define TZDRAM_BASE (0x9c100000)
+#define TZDRAM_SIZE (0x03000000)
+
+#define CFG_TEE_RAM_VA_SIZE (1024 * 1024)
+
+#ifndef CFG_TEE_LOAD_ADDR
+#define CFG_TEE_LOAD_ADDR CFG_TEE_RAM_START
+#endif
+
+/*
+ * Everything is in TZDRAM.
+ * +------------------+
+ * | | TEE_RAM |
+ * + TZDRAM +---------+
+ * | | TA_RAM |
+ * +--------+---------+
+ */
+#define CFG_TEE_RAM_PH_SIZE CFG_TEE_RAM_VA_SIZE
+#define CFG_TEE_RAM_START TZDRAM_BASE
+#define CFG_TA_RAM_START ROUNDUP((TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE), \
+ CORE_MMU_DEVICE_SIZE)
+#define CFG_TA_RAM_SIZE ROUNDDOWN((TZDRAM_SIZE - CFG_TEE_RAM_VA_SIZE), \
+ CORE_MMU_DEVICE_SIZE)
+
+#define CONSOLE_UART_BASE (UART0_BASE)
+
+/* Central Security Unit register values */
+#define CSU_BASE 0x021C0000
+#define CSU_CSL_START 0x0
+#define CSU_CSL_END 0xA0
+#define CSU_ACCESS_ALL 0x00FF00FF
+#define CSU_SETTING_LOCK 0x01000100
+
+/* For i.MX6 Quad SABRE Lite and Smart Device board */
+
+#elif defined(PLATFORM_FLAVOR_mx6qsabrelite) || \
+ defined(PLATFORM_FLAVOR_mx6qsabresd)
+
+#define SCU_BASE 0x00A00000
+#define PL310_BASE 0x00A02000
+#define SRC_BASE 0x020D8000
+#define SRC_SCR 0x000
+#define SRC_GPR1 0x020
+#define SRC_SCR_CPU_ENABLE_ALL SHIFT_U32(0x7, 22)
+#define SRC_SCR_CORE1_RST_OFFSET 14
+#define SRC_SCR_CORE1_ENABLE_OFFSET 22
+#define GIC_BASE 0x00A00000
+#define GICC_OFFSET 0x100
+#define GICD_OFFSET 0x1000
+#define GIC_CPU_BASE (GIC_BASE + GICC_OFFSET)
+#define GIC_DIST_BASE (GIC_BASE + GICD_OFFSET)
+#define UART1_BASE 0x02020000
+#define UART2_BASE 0x021E8000
+
+/* Central Security Unit register values */
+#define CSU_BASE 0x021C0000
+#define CSU_CSL_START 0x0
+#define CSU_CSL_END 0xA0
+#define CSU_CSL5 0x14
+#define CSU_CSL16 0x40
+#define CSU_ACCESS_ALL 0x00FF00FF
+#define CSU_SETTING_LOCK 0x01000100
+
+#if defined(PLATFORM_FLAVOR_mx6qsabrelite)
+#define CONSOLE_UART_BASE UART2_BASE
+#endif
+#if defined(PLATFORM_FLAVOR_mx6qsabresd)
+#define CONSOLE_UART_BASE UART1_BASE
+#endif
+#define DRAM0_BASE 0x10000000
+#define DRAM0_SIZE 0x40000000
+
+#define CFG_TEE_RAM_VA_SIZE (1024 * 1024)
+
+#define CFG_TEE_CORE_NB_CORE 4
+
+#define DDR_PHYS_START DRAM0_BASE
+#define DDR_SIZE DRAM0_SIZE
+
+#define CFG_DDR_START DDR_PHYS_START
+#define CFG_DDR_SIZE DDR_SIZE
+
+/*
+ * PL310 TAG RAM Control Register
+ *
+ * bit[10:8]:1 - 2 cycle of write accesses latency
+ * bit[6:4]:1 - 2 cycle of read accesses latency
+ * bit[2:0]:1 - 2 cycle of setup latency
+ */
+#ifndef PL310_TAG_RAM_CTRL_INIT
+#define PL310_TAG_RAM_CTRL_INIT 0x00000111
+#endif
+
+/*
+ * PL310 DATA RAM Control Register
+ *
+ * bit[10:8]:2 - 3 cycle of write accesses latency
+ * bit[6:4]:2 - 3 cycle of read accesses latency
+ * bit[2:0]:2 - 3 cycle of setup latency
+ */
+#ifndef PL310_DATA_RAM_CTRL_INIT
+#define PL310_DATA_RAM_CTRL_INIT 0x00000222
+#endif
+
+/*
+ * PL310 Auxiliary Control Register
+ *
+ * I/Dcache prefetch enabled (bit29:28=2b11)
+ * NS can access interrupts (bit27=1)
+ * NS can lockown cache lines (bit26=1)
+ * Pseudo-random replacement policy (bit25=0)
+ * Force write allocated (default)
+ * Shared attribute internally ignored (bit22=1, bit13=0)
+ * Parity disabled (bit21=0)
+ * Event monitor disabled (bit20=0)
+ * Platform fmavor specific way config:
+ * - 64kb way size (bit19:17=3b011)
+ * - 16-way associciativity (bit16=1)
+ * Store buffer device limitation enabled (bit11=1)
+ * Cacheable accesses have high prio (bit10=0)
+ * Full Line Zero (FLZ) disabled (bit0=0)
+ */
+#ifndef PL310_AUX_CTRL_INIT
+#define PL310_AUX_CTRL_INIT 0x3C470800
+#endif
+
+/*
+ * PL310 Prefetch Control Register
+ *
+ * Double linefill disabled (bit30=0)
+ * I/D prefetch enabled (bit29:28=2b11)
+ * Prefetch drop enabled (bit24=1)
+ * Incr double linefill disable (bit23=0)
+ * Prefetch offset = 7 (bit4:0)
+ */
+#define PL310_PREFETCH_CTRL_INIT 0x31000007
+
+/*
+ * PL310 Power Register
+ *
+ * Dynamic clock gating enabled
+ * Standby mode enabled
+ */
+#define PL310_POWER_CTRL_INIT 0x00000003
+
+/*
+ * SCU Invalidate Register
+ *
+ * Invalidate all registers
+ */
+#define SCU_INV_CTRL_INIT 0xFFFFFFFF
+
+/*
+ * SCU Access Register
+ * - both secure CPU access SCU
+ */
+#define SCU_SAC_CTRL_INIT 0x0000000F
+
+/*
+ * SCU NonSecure Access Register
+ * - both nonsec cpu access SCU, private and global timer
+ */
+#define SCU_NSAC_CTRL_INIT 0x00000FFF
+
+/* define the memory areas */
+
+#ifdef CFG_WITH_PAGER
+
+/*
+ * TEE/TZ RAM layout:
+ *
+ * +---------------------------------------+ <- CFG_CORE_TZSRAM_EMUL_START
+ * | TEE private highly | TEE_RAM | ^
+ * | secure memory | | | CFG_CORE_TZSRAM_EMUL_SIZE
+ * +---------------------------------------+ v
+ *
+ * +---------------------------------------+ <- CFG_DDR_TEETZ_RESERVED_START
+ * | TEE private secure | TA_RAM | ^
+ * | external memory | | |
+ * +---------------------------------------+ | CFG_DDR_TEETZ_RESERVED_SIZE
+ * | Non secure | SHM | |
+ * | shared memory | | |
+ * +---------------------------------------+ v
+ *
+ * TEE_RAM : default 256kByte
+ * TA_RAM : all what is left in DDR TEE reserved area
+ * PUB_RAM : default 2MByte
+ */
+
+/* emulated SRAM, at start of secure DDR */
+
+#define CFG_CORE_TZSRAM_EMUL_START 0x4E000000
+
+#define TZSRAM_BASE CFG_CORE_TZSRAM_EMUL_START
+#define TZSRAM_SIZE CFG_CORE_TZSRAM_EMUL_SIZE
+
+/* Location of trusted dram */
+
+#define CFG_DDR_TEETZ_RESERVED_START 0x4E100000
+#define CFG_DDR_TEETZ_RESERVED_SIZE 0x01F00000
+
+#define CFG_PUB_RAM_SIZE (1 * 1024 * 1024)
+#define CFG_TEE_RAM_PH_SIZE TZSRAM_SIZE
+
+#define TZDRAM_BASE (CFG_DDR_TEETZ_RESERVED_START)
+#define TZDRAM_SIZE (CFG_DDR_TEETZ_RESERVED_SIZE - \
+ CFG_PUB_RAM_SIZE)
+
+#define CFG_TA_RAM_START TZDRAM_BASE
+#define CFG_TA_RAM_SIZE TZDRAM_SIZE
+
+#define CFG_SHMEM_START (CFG_DDR_TEETZ_RESERVED_START + \
+ TZDRAM_SIZE)
+#define CFG_SHMEM_SIZE CFG_PUB_RAM_SIZE
+
+#define CFG_TEE_RAM_START TZSRAM_BASE
+
+#ifndef CFG_TEE_LOAD_ADDR
+#define CFG_TEE_LOAD_ADDR TZSRAM_BASE
+#endif
+
+#else /* CFG_WITH_PAGER */
+
+/*
+ * TEE/TZ RAM layout:
+ *
+ * +---------------------------------------+ <- CFG_DDR_TEETZ_RESERVED_START
+ * | TEE private secure | TEE_RAM | ^
+ * | external memory +------------------+ |
+ * | | TA_RAM | |
+ * +---------------------------------------+ | CFG_DDR_TEETZ_RESERVED_SIZE
+ * | Non secure | SHM | |
+ * | shared memory | | |
+ * +---------------------------------------+ v
+ *
+ * TEE_RAM : default 1MByte
+ * PUB_RAM : default 2MByte
+ * TA_RAM : all what is left
+ */
+
+#define CFG_DDR_TEETZ_RESERVED_START 0x4E000000
+#define CFG_DDR_TEETZ_RESERVED_SIZE 0x02000000
+
+#define CFG_PUB_RAM_SIZE (1 * 1024 * 1024)
+#define CFG_TEE_RAM_PH_SIZE (1 * 1024 * 1024)
+
+#define TZDRAM_BASE (CFG_DDR_TEETZ_RESERVED_START)
+#define TZDRAM_SIZE (CFG_DDR_TEETZ_RESERVED_SIZE - \
+ CFG_PUB_RAM_SIZE)
+
+#define CFG_TA_RAM_START (CFG_DDR_TEETZ_RESERVED_START + \
+ CFG_TEE_RAM_PH_SIZE)
+#define CFG_TA_RAM_SIZE (CFG_DDR_TEETZ_RESERVED_SIZE - \
+ CFG_TEE_RAM_PH_SIZE - \
+ CFG_PUB_RAM_SIZE)
+
+#define CFG_SHMEM_START (CFG_DDR_TEETZ_RESERVED_START + \
+ TZDRAM_SIZE)
+#define CFG_SHMEM_SIZE CFG_PUB_RAM_SIZE
+
+#define CFG_TEE_RAM_START TZDRAM_BASE
+
+#ifndef CFG_TEE_LOAD_ADDR
+#define CFG_TEE_LOAD_ADDR TZDRAM_BASE
+#endif
+
+#endif /* CFG_WITH_PAGER */
+
+#else
+#error "Unknown platform flavor"
+#endif /* defined(PLATFORM_FLAVOR_mx6ulevk) */
+
+#ifdef CFG_PL310
+/*
+ * PL310 TAG RAM Control Register
+ *
+ * bit[10:8]:1 - 2 cycle of write accesses latency
+ * bit[6:4]:1 - 2 cycle of read accesses latency
+ * bit[2:0]:1 - 2 cycle of setup latency
+ */
+#define PL310_TAG_RAM_CTRL_INIT 0x00000111
+
+/*
+ * DATA RAM Control Register
+ *
+ * bit[10:8]:2 - 3 cycle of write accesses latency
+ * bit[6:4]:2 - 3 cycle of read accesses latency
+ * bit[2:0]:2 - 3 cycle of setup latency
+ */
+#define PL310_DATA_RAM_CTRL_INIT 0x00000222
+
+/*
+ * Auxiliary Control Register
+ *
+ * I/Dcache prefetch enabled (bit29:28=2b11)
+ * NS can access interrupts (bit27=1)
+ * NS can lockown cache lines (bit26=1)
+ * Pseudo-random replacement policy (bit25=0)
+ * Force write allocated (default)
+ * Shared attribute internally ignored (bit22=1, bit13=0)
+ * Parity disabled (bit21=0)
+ * Event monitor disabled (bit20=0)
+ * 64kB ways, 16-way associativity (bit19:17=3b011 bit16=1)
+ * Store buffer device limitation enabled (bit11=1)
+ * Cacheable accesses have high prio (bit10=0)
+ * Full Line Zero (FLZ) disabled (bit0=0)
+ */
+#define PL310_AUX_CTRL_INIT 0x3C470800
+
+/*
+ * Prefetch Control Register
+ *
+ * Double linefill disabled (bit30=0)
+ * I/D prefetch enabled (bit29:28=2b11)
+ * Prefetch drop enabled (bit24=1)
+ * Incr double linefill disable (bit23=0)
+ * Prefetch offset = 7 (bit4:0)
+ */
+#define PL310_PREFETCH_CTRL_INIT 0x31000007
+
+/*
+ * Power Register = 0x00000003
+ *
+ * Dynamic clock gating enabled
+ * Standby mode enabled
+ */
+#define PL310_POWER_CTRL_INIT 0x00000003
+
+#endif
+
+#endif /*PLATFORM_CONFIG_H*/
diff --git a/core/arch/arm/plat-imx/psci.c b/core/arch/arm/plat-imx/psci.c
new file mode 100644
index 0000000..065555b
--- /dev/null
+++ b/core/arch/arm/plat-imx/psci.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <console.h>
+#include <drivers/imx_uart.h>
+#include <io.h>
+#include <kernel/generic_boot.h>
+#include <kernel/panic.h>
+#include <kernel/pm_stubs.h>
+#include <mm/core_mmu.h>
+#include <mm/core_memprot.h>
+#include <platform_config.h>
+#include <stdint.h>
+#include <sm/optee_smc.h>
+#include <sm/psci.h>
+#include <tee/entry_std.h>
+#include <tee/entry_fast.h>
+
+static vaddr_t src_base(void)
+{
+ static void *va __data; /* in case it's used before .bss is cleared */
+
+ if (cpu_mmu_enabled()) {
+ if (!va)
+ va = phys_to_virt(SRC_BASE, MEM_AREA_IO_SEC);
+ return (vaddr_t)va;
+ }
+ return SRC_BASE;
+}
+
+int psci_cpu_on(uint32_t core_idx, uint32_t entry,
+ uint32_t context_id __attribute__((unused)))
+{
+ uint32_t val;
+ vaddr_t va = src_base();
+
+ if ((core_idx == 0) || (core_idx >= CFG_TEE_CORE_NB_CORE))
+ return PSCI_RET_INVALID_PARAMETERS;
+
+ /* set secondary cores' NS entry addresses */
+ ns_entry_addrs[core_idx] = entry;
+
+ /* boot secondary cores from OP-TEE load address */
+ write32((uint32_t)CFG_TEE_LOAD_ADDR, va + SRC_GPR1 + core_idx * 8);
+
+ /* release secondary core */
+ val = read32(va + SRC_SCR);
+ val |= BIT32(SRC_SCR_CORE1_ENABLE_OFFSET + (core_idx - 1));
+ val |= BIT32(SRC_SCR_CORE1_RST_OFFSET + (core_idx - 1));
+ write32(val, va + SRC_SCR);
+
+ return PSCI_RET_SUCCESS;
+}
diff --git a/core/arch/arm/plat-imx/sub.mk b/core/arch/arm/plat-imx/sub.mk
new file mode 100644
index 0000000..d0a2f51
--- /dev/null
+++ b/core/arch/arm/plat-imx/sub.mk
@@ -0,0 +1,9 @@
+global-incdirs-y += .
+srcs-y += main.c
+
+srcs-$(CFG_PL310) += imx_pl310.c
+srcs-$(CFG_PSCI_ARM32) += psci.c
+
+srcs-$(PLATFORM_FLAVOR_mx6qsabrelite) += a9_plat_init.S
+srcs-$(PLATFORM_FLAVOR_mx6qsabresd) += a9_plat_init.S
+srcs-$(PLATFORM_FLAVOR_mx6ulevk) += imx6ul.c