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author | r.tyminski <r.tyminski@partner.samsung.com> | 2017-11-23 08:27:00 +0100 |
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committer | Rafa? Tymi?ski <r.tyminski@partner.samsung.com> | 2017-11-23 07:40:31 +0000 |
commit | 468debea90fbed7a364a157baefda869267f8e3c (patch) | |
tree | a6a4e70e50d979bb8af91168f47b4b8ee13c6937 | |
parent | 493442391fcebb623711f41789b2346902aa6ce9 (diff) | |
parent | ae15aefe6d17d470045b8ef59861c9f63103f68b (diff) | |
download | tef-optee_os-468debea90fbed7a364a157baefda869267f8e3c.tar.gz tef-optee_os-468debea90fbed7a364a157baefda869267f8e3c.tar.bz2 tef-optee_os-468debea90fbed7a364a157baefda869267f8e3c.zip |
Merge remote-tracking branch 'origin/tizen_4.0' into 'origin/tizen'submit/tizen/20171123.081046accepted/tizen/unified/20171124.064555
Change-Id: Ic78fa653d759783441b75aff4d332b383d711163
-rw-r--r-- | core/arch/arm/plat-s5p6818/conf.mk | 37 | ||||
-rw-r--r-- | core/arch/arm/plat-s5p6818/kern.ld.S | 1 | ||||
-rw-r--r-- | core/arch/arm/plat-s5p6818/link.mk | 1 | ||||
-rw-r--r-- | core/arch/arm/plat-s5p6818/main.c | 86 | ||||
-rw-r--r-- | core/arch/arm/plat-s5p6818/platform_config.h | 148 | ||||
-rw-r--r-- | core/arch/arm/plat-s5p6818/platform_flags.mk | 28 | ||||
-rw-r--r-- | core/arch/arm/plat-s5p6818/sub.mk | 2 | ||||
-rw-r--r-- | core/drivers/s5p6818_tieoff.c | 115 | ||||
-rw-r--r-- | core/drivers/s5p6818_uart.c | 285 | ||||
-rw-r--r-- | core/drivers/sub.mk | 2 | ||||
-rw-r--r-- | core/include/drivers/s5p6818_tieoff.h | 406 | ||||
-rw-r--r-- | core/include/drivers/s5p6818_uart.h | 44 | ||||
-rw-r--r-- | packaging/optee-os-artik710.spec | 43 |
13 files changed, 1198 insertions, 0 deletions
diff --git a/core/arch/arm/plat-s5p6818/conf.mk b/core/arch/arm/plat-s5p6818/conf.mk new file mode 100644 index 0000000..54a5b06 --- /dev/null +++ b/core/arch/arm/plat-s5p6818/conf.mk @@ -0,0 +1,37 @@ +include core/arch/$(ARCH)/plat-$(PLATFORM)/platform_flags.mk + +#$(call force,CFG_TEE_CORE_DEBUG,1) + +core-platform-cppflags += -I$(arch-dir)/include + +$(call force,CFG_GENERIC_BOOT,y) +$(call force,CFG_HWSUPP_MEM_PERM_PXN,y) +$(call force,CFG_S5P6818_UART,y) +#$(call force,CFG_S5P6818_TIEOFF,y) +#$(call force,CFG_GIC,y) +$(call force,CFG_PM_STUBS,y) +#$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) +$(call force,CFG_SECURE_TIME_SOURCE_REE,y) +$(call force,CFG_WITH_ARM_TRUSTED_FW,y) +#$(call force,CFG_NO_TA_HASH_SIGN,y) + +ifeq ($(CFG_ARM64_core),y) +$(call force,CFG_WITH_LPAE,y) +ta-targets += ta_arm64 +else +$(call force,CFG_ARM32_core,y) +$(call force,CFG_MMU_V7_TTB,y) +ta-targets += ta_arm32 +endif + +libtomcrypt_with_optimize_size ?= y +CFG_WITH_STACK_CANARIES ?= y +CFG_CORE_HEAP_SIZE ?= 24576 +# Number of threads +CFG_NUM_THREADS ?= 8 + +$(call force,CFG_CRYPTO_SHA256_ARM32_CE,n) +$(call force,CFG_CRYPTO_SHA256_ARM64_CE,n) +$(call force,CFG_CRYPTO_SHA1_ARM32_CE,n) +$(call force,CFG_CRYPTO_SHA1_ARM64_CE,n) +$(call force,CFG_CRYPTO_AES_ARM64_CE,n) diff --git a/core/arch/arm/plat-s5p6818/kern.ld.S b/core/arch/arm/plat-s5p6818/kern.ld.S new file mode 100644 index 0000000..8d794ee --- /dev/null +++ b/core/arch/arm/plat-s5p6818/kern.ld.S @@ -0,0 +1 @@ +#include "../kernel/kern.ld.S" diff --git a/core/arch/arm/plat-s5p6818/link.mk b/core/arch/arm/plat-s5p6818/link.mk new file mode 100644 index 0000000..448ab89 --- /dev/null +++ b/core/arch/arm/plat-s5p6818/link.mk @@ -0,0 +1 @@ +include core/arch/arm/kernel/link.mk diff --git a/core/arch/arm/plat-s5p6818/main.c b/core/arch/arm/plat-s5p6818/main.c new file mode 100644 index 0000000..45e45ba --- /dev/null +++ b/core/arch/arm/plat-s5p6818/main.c @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2016 Nexell Co., Ltd. + * Author: Bon-gyu, KOO <freestyle@nexell.co.kr> + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <console.h> +#include <drivers/gic.h> +#include <drivers/s5p6818_uart.h> +#include <kernel/generic_boot.h> +#include <kernel/panic.h> +#include <kernel/pm_stubs.h> +#include <mm/tee_pager.h> +#include <platform_config.h> +#include <stdint.h> +#include <tee/arch_svc.h> +#include <tee/entry_std.h> +#include <tee/entry_fast.h> + + +static void main_fiq(void); + +static const struct thread_handlers handlers = { + .std_smc = tee_entry_std, + .fast_smc = tee_entry_fast, + .nintr = main_fiq, + .cpu_on = cpu_on_handler, + .cpu_off = pm_do_nothing, + .cpu_suspend = pm_do_nothing, + .cpu_resume = pm_do_nothing, + .system_off = pm_do_nothing, + .system_reset = pm_do_nothing, +}; + +static struct s5p6818_uart_data console_data __early_bss; + +const struct thread_handlers *generic_boot_get_handlers(void) +{ + return &handlers; +} + +#ifdef CFG_GIC +void main_init_gic(void) +{ + /* Initialize GIC */ + gic_init_base_addr(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); + /* gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); */ +} +#endif + +static void main_fiq(void) +{ + panic(); +} + +void console_init(void) +{ + s5p6818_uart_init(&console_data, CONSOLE_UART_BASE, + CONSOLE_UART_CLK_IN_HZ, + CONSOLE_BAUDRATE); + register_serial_console(&console_data.chip); +} + diff --git a/core/arch/arm/plat-s5p6818/platform_config.h b/core/arch/arm/plat-s5p6818/platform_config.h new file mode 100644 index 0000000..e21ea2a --- /dev/null +++ b/core/arch/arm/plat-s5p6818/platform_config.h @@ -0,0 +1,148 @@ +/* + * Copyright (C) 2016 Nexell Co., Ltd. + * Author: Bon-gyu, KOO <freestyle@nexell.co.kr> + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef PLATFORM_CONFIG_H +#define PLATFORM_CONFIG_H + +/* Make stacks aligned to data cache line length */ +#define STACK_ALIGNMENT 64 + +#ifdef ARM64 +#ifdef CFG_WITH_PAGER +#error "Pager not supported for ARM64" +#endif +#endif /* ARM64 */ + +#define GIC_BASE 0xC0009000 +#define GICD_OFFSET 0x0 +#define GICC_OFFSET 0x1000 + +#define UART0_BASE 0xC00A1000 +#define UART1_BASE 0xC00A0000 +#define UART2_BASE 0xC00A2000 +#define UART3_BASE 0xC00A3000 +#define UART4_BASE 0xC006D000 +#define UART5_BASE 0xC006F000 + +/* S5P6818 UART */ +#ifdef PLAT_UART_BASE +#define CONSOLE_UART_BASE (PLAT_UART_BASE) +#else +#define CONSOLE_UART_BASE (UART3_BASE) +#endif +#define CONSOLE_BAUDRATE 115200 +#define CONSOLE_UART_CLK_IN_HZ 19200000 + +/* + * nexell memory map + * + * We use only non-secure DRAM (TZDRAM and TZSRAM are emulated). + */ +#if defined(PLAT_DRAM_SIZE) && PLAT_DRAM_SIZE == 2048 +#define DRAM_SIZE 0x80000000 +#define DRAM0_SIZE 0x7DB00000 +#ifdef CFG_WITH_PAGER +#define TZSRAM_BASE 0xBDB00000 +#define TZDRAM_BASE 0xBDC00000 +#else /* CFG_WITH_PAGER */ +#define TZDRAM_BASE 0xBEA00000 +#endif /* CFG_WITH_PAGER */ +#define CFG_SHMEM_START 0xBDE00000 +#define CFG_TEE_LOAD_ADDR 0xBEA00000 + +#elif defined(PLAT_DRAM_SIZE) && PLAT_DRAM_SIZE == 512 +#define DRAM_SIZE 0x20000000 +#define DRAM0_SIZE 0x1DB00000 +#ifdef CFG_WITH_PAGER +#define TZSRAM_BASE 0x5DB00000 +#define TZDRAM_BASE 0x5DC00000 +#else /* CFG_WITH_PAGER */ +#define TZDRAM_BASE 0x5EA00000 +#endif /* CFG_WITH_PAGER */ +#define CFG_SHMEM_START 0x5DE00000 +#define CFG_TEE_LOAD_ADDR 0x5EA00000 + +#else /* PLAT_DRAM_SIZE */ +/* default: DRAM size is 1GB. */ +#define DRAM_SIZE 0x40000000 +#define DRAM0_SIZE 0x3DB00000 +#ifdef CFG_WITH_PAGER +#define TZSRAM_BASE 0x7DB00000 +#define TZDRAM_BASE 0x7DC00000 +#else /* CFG_WITH_PAGER */ +#define TZDRAM_BASE 0x7EA00000 +#endif /* CFG_WITH_PAGER */ +#define CFG_SHMEM_START 0x7DE00000 +#define CFG_TEE_LOAD_ADDR 0x7EA00000 + +#endif /* PLAT_DRAM_SIZE */ + + +#define DRAM_BASE 0x40000000 +#define DRAM0_BASE DRAM_BASE + +#ifdef CFG_WITH_PAGER +#define TZSRAM_SIZE (200 * 1024) +#define TZDRAM_SIZE (15 * 1024 * 1024) +#else /* CFG_WITH_PAGER */ +#define TZDRAM_SIZE (16 * 1024 * 1024) +#endif /* CFG_WITH_PAGER */ + +#define CFG_SHMEM_SIZE (1024 * 1024) + +#define CFG_TEE_CORE_NB_CORE 8 + +#define CFG_TEE_RAM_VA_SIZE (1024 * 1024) + +#ifdef CFG_WITH_PAGER + +#define CFG_TEE_RAM_START TZSRAM_BASE +#define CFG_TEE_RAM_PH_SIZE TZSRAM_SIZE +#define CFG_TA_RAM_START ROUNDUP(TZDRAM_BASE, CORE_MMU_DEVICE_SIZE) +#define CFG_TA_RAM_SIZE ROUNDDOWN(TZDRAM_SIZE, CORE_MMU_DEVICE_SIZE) + +#else /* CFG_WITH_PAGER */ + +#define CFG_TEE_RAM_PH_SIZE CFG_TEE_RAM_VA_SIZE +#define CFG_TEE_RAM_START TZDRAM_BASE +#define CFG_TA_RAM_START ROUNDUP((TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE), \ + CORE_MMU_DEVICE_SIZE) + +#define CFG_TA_RAM_SIZE ROUNDDOWN((TZDRAM_SIZE - CFG_TEE_RAM_VA_SIZE),\ + CORE_MMU_DEVICE_SIZE) + +#endif /* CFG_WITH_PAGER */ + +#define DEVICE0_BASE ROUNDDOWN(CONSOLE_UART_BASE, \ + CORE_MMU_DEVICE_SIZE) +#define DEVICE0_PA_BASE DEVICE0_BASE +#define DEVICE0_SIZE CORE_MMU_DEVICE_SIZE +#define DEVICE0_TYPE MEM_AREA_IO_NSEC + +#endif /* PLATFORM_CONFIG_H */ diff --git a/core/arch/arm/plat-s5p6818/platform_flags.mk b/core/arch/arm/plat-s5p6818/platform_flags.mk new file mode 100644 index 0000000..60fb576 --- /dev/null +++ b/core/arch/arm/plat-s5p6818/platform_flags.mk @@ -0,0 +1,28 @@ +# 32-bit flags +arm32-platform-cpuarch := cortex-a53 +arm32-platform-cflags += -mcpu=$(arm32-platform-cpuarch) +arm32-platform-cflags += -pipe +arm32-platform-cflags += -fno-short-enums -fno-common +arm32-platform-aflags += -mcpu=$(arm32-platform-cpuarch) +arm32-platform-aflags += -mfpu=neon + +# 64-bit flags +arm64-platform-cflags += -mstrict-align + +platform-cflags += -ffunction-sections -fdata-sections + +DEBUG ?= 1 +ifeq ($(DEBUG),1) +platform-cflags += -O0 +else +platform-cflags += -Os +endif + +platform-cflags += -g +platform-aflags += -g + +CFG_ARM32_user_ta := y +user_ta-platform-cflags += $(arm32-platform-cflags) +user_ta-platform-cflags += -fpie +user_ta-platform-cppflags += $(arm32-platform-cppflags) +user_ta-platform-aflags += $(arm32-platform-aflags) diff --git a/core/arch/arm/plat-s5p6818/sub.mk b/core/arch/arm/plat-s5p6818/sub.mk new file mode 100644 index 0000000..8ddc2fd --- /dev/null +++ b/core/arch/arm/plat-s5p6818/sub.mk @@ -0,0 +1,2 @@ +global-incdirs-y += . +srcs-y += main.c diff --git a/core/drivers/s5p6818_tieoff.c b/core/drivers/s5p6818_tieoff.c new file mode 100644 index 0000000..d415e3e --- /dev/null +++ b/core/drivers/s5p6818_tieoff.c @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2016 Nexell Co., Ltd. + * Author: Youngbok, Park <ybparkle@nexell.co.kr> + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include <drivers/s5p6818_tieoff.h> +#include <io.h> + +#define NX_PIN_FN_SIZE 4 +#define TIEOFF_REG_NUM 33 + +struct nx_tieoff_registerset { + uint32_t tieoffreg[TIEOFF_REG_NUM]; +}; + +static struct nx_tieoff_registerset *nx_tieoff = (void *)0xC0011000; + + +void nx_tieoff_set(uint32_t tieoff_index, uint32_t tieoff_value) +{ + uint32_t regindex, mask; + uint32_t lsb, msb; + uint32_t regval; + + uint32_t position; + uint32_t bitwidth; + + position = tieoff_index & 0xffff; + bitwidth = (tieoff_index>>16) & 0xffff; + + regindex = position>>5; + + lsb = position & 0x1F; + msb = lsb+bitwidth; + + if (msb > 32) { + msb &= 0x1F; + mask = ~(0xffffffff<<lsb); + regval = read32((vaddr_t)&nx_tieoff->tieoffreg[regindex]) + & mask; + regval |= ((tieoff_value & ((1UL<<bitwidth)-1))<<lsb); + write32(regval, (vaddr_t)&nx_tieoff->tieoffreg[regindex]); + + mask = (0xffffffff<<msb); + regval = read32((vaddr_t)&nx_tieoff->tieoffreg[regindex+1]) + & mask; + regval |= ((tieoff_value & ((1UL<<bitwidth)-1))>>msb); + write32(regval, (vaddr_t)&nx_tieoff->tieoffreg[regindex+1]); + } else { + mask = (0xffffffff<<msb) | (~(0xffffffff<<lsb)); + regval = read32((vaddr_t)&nx_tieoff->tieoffreg[regindex]) + & mask; + regval |= ((tieoff_value & ((1UL<<bitwidth)-1))<<lsb); + write32(regval, (vaddr_t)&nx_tieoff->tieoffreg[regindex]); + } +} + +uint32_t nx_tieoff_get(uint32_t tieoff_index) +{ + uint32_t regindex, mask; + uint32_t lsb, msb; + uint32_t regval; + + uint32_t position; + uint32_t bitwidth; + + position = tieoff_index & 0xffff; + bitwidth = (tieoff_index>>16) & 0xffff; + + regindex = position/32; + lsb = position % 32; + msb = lsb+bitwidth; + + if (msb > 32) { + msb &= 0x1F; + mask = 0xffffffff<<lsb; + regval = read32((vaddr_t)&nx_tieoff->tieoffreg[regindex]) + & mask; + regval >>= lsb; + + mask = ~(0xffffffff<<msb); + regval |= ((read32((vaddr_t)&nx_tieoff->tieoffreg[regindex+1]) + & mask) + << (32-lsb)); + } else { + mask = ~(0xffffffff<<msb) & (0xffffffff<<lsb); + regval = read32((vaddr_t)&nx_tieoff->tieoffreg[regindex]) + & mask; + regval >>= lsb; + } + return regval; +} diff --git a/core/drivers/s5p6818_uart.c b/core/drivers/s5p6818_uart.c new file mode 100644 index 0000000..659831f --- /dev/null +++ b/core/drivers/s5p6818_uart.c @@ -0,0 +1,285 @@ +/* + * Copyright (C) 2016 Nexell Co., Ltd. + * Author: Bon-gyu, KOO <freestyle@nexell.co.kr> + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include <compiler.h> +#include <console.h> +#include <drivers/s5p6818_uart.h> +#include <io.h> +#include <keep.h> +#include <util.h> +#include <platform_config.h> + +/* NX_UART Registers */ +#define UARTDLCON 0x00 /* Line Control */ +#define UARTRUCON 0x04 /* Control */ +#define UARTEFCON 0x08 /* FIFO Control */ +#define UARTFMCON 0x0C /* Modem Control */ +#define UARTTRSTAT 0x10 /* Tx/Rx Status */ +#define UARTERSTAT 0x14 /* Rx Error Status */ +#define UARTFSTAT 0x18 /* FIFO Status */ +#define UARTMSTAT 0x1C /* Modem Status */ +#define UARTTXH 0x20 /* Transmit Buffer */ +#define UARTRXH 0x24 /* Receive Buffer */ +#define UARTBRDR 0x28 /* Baud Rate Driver */ +#define UARTFRACVAL 0x2C /* Driver Fractional Value */ +#define UARTINTP 0x30 /* Instrrupt Pending */ +#define UARTINTSP 0x34 /* Instrrupt Source */ +#define UARTINTM 0x38 /* Instrrupt Mask */ + +#define NUMBER_OF_RESET_MODULE_PIN 69 +#define UART_RST_BASE 50 + +#define NX_UARTFSTAT_TXFF_BIT (1 << 24) + /* Transmit FIFO full bit in UARTFSTAT register */ +#define NX_UARTFSTAT_RXFE_BIT (1 << 2) + /* Receive FIFO empty bit in UARTFR register */ + +#define NX_UARTTRSTAT_TX_EMPTY_BIT (1 << 2) + /* Transmit empty bit in UARTTRSTAT register */ +#define NX_UARTTRSTAT_TXBE_BIT (1 << 1) + /* Transmit BUFFER empty bit in UARTTRSTAT register */ + +/* FIXME - Modify and use it after confirming the operation. */ +#ifdef CFG_S5P6818_TIEOFF +static int s5p6818_uart_get_ch_num(vaddr_t base) +{ + int ch = 0; + + switch (base) { + case UART0_BASE: + ch = 0; + break; + case UART1_BASE: + ch = 1; + break; + case UART2_BASE: + ch = 2; + break; + case UART3_BASE: + ch = 3; + break; + case UART4_BASE: + ch = 4; + break; + case UART5_BASE: + ch = 5; + break; + default: + break; + }; + return ch; +} + +/* + * FIXME modify after clock control interface. + */ +static vaddr_t get_clock_base(uint32_t ch) +{ + vaddr_t base = 0; + + switch (ch) { + case 0: + base = 0xc00A9000; + break; + case 1: + base = 0xc00A8000; + break; + case 2: + base = 0xc00AA000; + break; + case 3: + base = 0xc00AB000; + break; + case 4: + base = 0xc00E0000; + break; + case 5: + base = 0xc00B1000; + break; + default: + break; + }; + return base; +} + +static void uart_clk_enb(uint32_t ch) +{ + vaddr_t base = get_clock_base(ch); + + write32(0x4, base); + write32(0x68, base+0x4); +} + +/* For Reset control */ + +struct nx_rstcon_registerset { + uint32_t regrst[(NUMBER_OF_RESET_MODULE_PIN+31)>>5]; +}; + +static struct nx_rstcon_registerset *nx_rstcon += (struct nx_rstcon_registerset *)0xC0012000; + +static void nx_rstcon_setrst(uint32_t rstindex, uint32_t status) +{ + uint32_t regnum, bitpos, curstat; + + regnum = rstindex >> 5; + curstat = (uint32_t)read32((vaddr_t)(&nx_rstcon->regrst[regnum])); + bitpos = rstindex & 0x1f; + curstat &= ~(1UL << bitpos); + curstat |= (status & 0x01) << bitpos; + write32(curstat, (vaddr_t)(&nx_rstcon->regrst[regnum])); +} + +/* tieoff setting */ +static void uart_tieoff_set(uint32_t ch) +{ + switch (ch) { + case 0: + nx_tieoff_set(NX_TIEOFF_UART0_USESMC, 0); + nx_tieoff_set(NX_TIEOFF_UART0_SMCTXENB, 0); + nx_tieoff_set(NX_TIEOFF_UART0_SMCRXENB, 0); + break; + case 1: + nx_tieoff_set(NX_TIEOFF_UART1_USESMC, 0); + nx_tieoff_set(NX_TIEOFF_UART1_SMCTXENB, 0); + nx_tieoff_set(NX_TIEOFF_UART1_SMCRXENB, 0); + break; + case 2: + nx_tieoff_set(NX_TIEOFF_UART2_USESMC, 0); + nx_tieoff_set(NX_TIEOFF_UART2_SMCTXENB, 0); + nx_tieoff_set(NX_TIEOFF_UART2_SMCRXENB, 0); + break; + case 3: + nx_tieoff_set(NX_TIEOFF_UART3_USESMC, 0); + nx_tieoff_set(NX_TIEOFF_UART3_SMCTXENB, 0); + nx_tieoff_set(NX_TIEOFF_UART3_SMCRXENB, 0); + break; + case 4: + nx_tieoff_set(NX_TIEOFF_UART4_USESMC, 0); + nx_tieoff_set(NX_TIEOFF_UART4_SMCTXENB, 0); + nx_tieoff_set(NX_TIEOFF_UART4_SMCRXENB, 0); + break; + case 5: + nx_tieoff_set(NX_TIEOFF_UART5_USESMC, 0); + nx_tieoff_set(NX_TIEOFF_UART5_SMCTXENB, 0); + nx_tieoff_set(NX_TIEOFF_UART5_SMCRXENB, 0); + break; + default: + break; + + }; +} + +void s5p6818_uart_tieoff_init(paddr_t base, uint32_t uart_clk, uint32_t baud_rate) +{ + int ch = s5p6818_uart_get_ch_num(base); + + nx_rstcon_setrst(UART_RST_BASE+ch, 1); /* reset */ + uart_tieoff_set(ch); + uart_clk_enb(ch); + + write32(0x3, base + UARTEFCON); + write32(0, base + UARTFMCON); + /* 8N1 */ + write32(0x3, base + UARTDLCON); + /* No interrupts, no DMA, pure polling */ + write32(0x245, base + UARTRUCON); + + if (baud_rate) { + int divisor = uart_clk / baud_rate; + + write32(divisor / 16 - 1, base + UARTBRDR); + write32(divisor % 16, base + UARTFRACVAL); + } +} +#endif + +static vaddr_t chip_to_base(struct serial_chip *chip) +{ + struct s5p6818_uart_data *pd = + container_of(chip, struct s5p6818_uart_data, chip); + + return io_pa_or_va(&pd->base); +} + +static void s5p6818_uart_flush(struct serial_chip *chip) +{ + vaddr_t base = chip_to_base(chip); + + while (!(read32(base + UARTTRSTAT) & NX_UARTTRSTAT_TX_EMPTY_BIT)) + ; +} + +static bool s5p6818_uart_have_rx_data(struct serial_chip *chip) +{ + vaddr_t base = chip_to_base(chip); + + return !(read32(base + UARTFSTAT) & NX_UARTFSTAT_RXFE_BIT); +} + +static int s5p6818_uart_getchar(struct serial_chip *chip) +{ + vaddr_t base = chip_to_base(chip); + + while (!s5p6818_uart_have_rx_data(chip)) + ; + return read32(base + UARTRXH) & 0xff; +} + +static void s5p6818_uart_putc(struct serial_chip *chip, int ch) +{ + vaddr_t base = chip_to_base(chip); + + s5p6818_uart_flush(chip); + + /* Send the character */ + write32(ch, base + UARTTXH); +} + +static const struct serial_ops s5p6818_uart_ops = { + .flush = s5p6818_uart_flush, + .getchar = s5p6818_uart_getchar, + .have_rx_data = s5p6818_uart_have_rx_data, + .putc = s5p6818_uart_putc, +}; +KEEP_PAGER(s5p6818_uart_ops); + +void s5p6818_uart_init(struct s5p6818_uart_data *pd, paddr_t base, + uint32_t __unused uart_clk, + uint32_t __unused baud_rate) +{ + pd->base.pa = base; + pd->chip.ops = &s5p6818_uart_ops; + +#ifdef CFG_S5P6818_TIEOFF + s5p6818_uart_tieoff_init(base, uart_clk, baud_rate); +#endif + return; +} + diff --git a/core/drivers/sub.mk b/core/drivers/sub.mk index 015f5c3..a1d8584 100644 --- a/core/drivers/sub.mk +++ b/core/drivers/sub.mk @@ -18,3 +18,5 @@ srcs-$(CFG_HI16XX_RNG) += hi16xx_rng.c srcs-$(CFG_SCIF) += scif.c srcs-$(CFG_DRA7_RNG) += dra7_rng.c srcs-$(CFG_STIH_UART) += stih_asc.c +srcs-$(CFG_S5P6818_UART) += s5p6818_uart.c +srcs-$(CFG_S5P6818_TIEOFF) += s5p6818_tieoff.c diff --git a/core/include/drivers/s5p6818_tieoff.h b/core/include/drivers/s5p6818_tieoff.h new file mode 100644 index 0000000..e2a6a24 --- /dev/null +++ b/core/include/drivers/s5p6818_tieoff.h @@ -0,0 +1,406 @@ +/* + * Copyright (C) 2016 Nexell Co., Ltd. + * Author: Youngbok, Park <ybparkle@nexell.co.kr> + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _S5P6818_TIEOFF_H +#define _S5P6818_TIEOFF_H + +#include <types_ext.h> + +#define NX_TIEOFF_MMC_8BIT ((1<<16) | 5) +#define NX_TIEOFF_AXISRAM0_i_TIE_ra2w_EMAA ((3<<16) | 47) +#define NX_TIEOFF_AXISRAM0_i_TIE_ra2w_EMAB ((3<<16) | 50) +#define NX_TIEOFF_AXISRAM0_i_TIE_ra2w_EMAWA ((2<<16) | 53) +#define NX_TIEOFF_AXISRAM0_i_TIE_ra2w_EMAWB ((2<<16) | 55) +#define NX_TIEOFF_AXISRAM0_i_nPowerDown ((1<<16) | 57) +#define NX_TIEOFF_AXISRAM0_i_nSleep ((1<<16) | 58) +#define NX_TIEOFF_CAN0_i_TIE_rf1_EMA ((3<<16) | 59) +#define NX_TIEOFF_CAN0_i_TIE_rf1_EMAW ((2<<16) | 62) +#define NX_TIEOFF_CAN0_i_nPowerDown ((1<<16) | 64) +#define NX_TIEOFF_CAN0_i_nSleep ((1<<16) | 65) +#define NX_TIEOFF_CAN1_i_TIE_rf1_EMA ((3<<16) | 66) +#define NX_TIEOFF_CAN1_i_TIE_rf1_EMAW ((2<<16) | 69) +#define NX_TIEOFF_CAN1_i_nPowerDown ((1<<16) | 71) +#define NX_TIEOFF_CAN1_i_nSleep ((1<<16) | 72) +#define NX_TIEOFF_DEINTERLACE0_i_NX_RF1_EMA ((3<<16) | 73) +#define NX_TIEOFF_DEINTERLACE0_i_NX_RF1_EMAW ((2<<16) | 76) +#define NX_TIEOFF_DEINTERLACE0_i_NX_RF2_EMAA ((3<<16) | 78) +#define NX_TIEOFF_DEINTERLACE0_i_NX_RF2_EMAB ((3<<16) | 81) +#define NX_TIEOFF_DEINTERLACE0_i_NX_RF2W_EMAA ((3<<16) | 84) +#define NX_TIEOFF_DEINTERLACE0_i_NX_RF2W_EMAB ((3<<16) | 87) +#define NX_TIEOFF_DISPLAYTOP0_i_ResConv_nPowerDown ((1<<16) | 90) +#define NX_TIEOFF_DISPLAYTOP0_i_ResConv_nSleep ((1<<16) | 91) +#define NX_TIEOFF_DISPLAYTOP0_i_HDMI_nPowerDown ((2<<16) | 92) +#define NX_TIEOFF_DISPLAYTOP0_i_HDMI_nSleep ((2<<16) | 94) +#define NX_TIEOFF_DISPLAYTOP0_i_HDMI_PHY_REFCLK_SEL ((1<<16) | 96) +#define NX_TIEOFF_DISPLAYTOP0_i_TIEOFF_SPSRAM_EMA ((3<<16) | 97) +#define NX_TIEOFF_DISPLAYTOP0_i_TIEOFF_SPSRAM_EMAW ((2<<16) | 100) +#define NX_TIEOFF_DISPLAYTOP0_i_TIEOFF_DPSRAM_1R1W_EMAA ((3<<16) | 102) +#define NX_TIEOFF_DISPLAYTOP0_i_TIEOFF_DPSRAM_1R1W_EMAB ((3<<16) | 105) +#define NX_TIEOFF_DISPLAYTOP0_i_TIEOFF_DPSRAM_EMAA ((3<<16) | 108) +#define NX_TIEOFF_DISPLAYTOP0_i_TIEOFF_DPSRAM_EMAB ((3<<16) | 111) +#define NX_TIEOFF_DISPLAYTOP0_i_TIEOFF_DPSRAM_EMAWA ((2<<16) | 114) +#define NX_TIEOFF_DISPLAYTOP0_i_TIEOFF_DPSRAM_EMAWB ((2<<16) | 116) +#define NX_TIEOFF_MCUSTOP0_i_vrom_EMA ((3<<16) | 118) +#define NX_TIEOFF_DREX0_CKE_INIT ((1<<16) | 121) +#define NX_TIEOFF_DREX0_CA_SWAP ((1<<16) | 122) +#define NX_TIEOFF_DREX0_CSYSREQ ((1<<16) | 123) +#define NX_TIEOFF_DREX0_PAUSE_REQ ((1<<16) | 124) +#define NX_TIEOFF_DREX0_PEREV_TRIGGER ((1<<16) | 125) +#define NX_TIEOFF_DREX0_CTRL_HCKE ((1<<16) | 126) +#define NX_TIEOFF_DREX0_DFI_RESET_N_P0 ((1<<16) | 127) +#define NX_TIEOFF_DREX0_DFI_RESET_N_P1 ((1<<16) | 128) +#define NX_TIEOFF_MIPI0_NX_DPSRAM_1R1W_EMAA ((3<<16) | 129) +#define NX_TIEOFF_MIPI0_NX_DPSRAM_1R1W_EMAB ((3<<16) | 132) +#define NX_TIEOFF_MIPI0_i_NX_NPOWERDOWN ((4<<16) | 135) +#define NX_TIEOFF_MIPI0_i_NX_NSLEEP ((4<<16) | 139) +#define NX_TIEOFF_SCALER0_i_NX_EMA ((3<<16) | 143) +#define NX_TIEOFF_SCALER0_i_NX_EMAW ((2<<16) | 146) +#define NX_TIEOFF_UART0_USESMC ((1<<16) | 148) +#define NX_TIEOFF_UART0_SMCTXENB ((1<<16) | 149) +#define NX_TIEOFF_UART0_SMCRXENB ((1<<16) | 150) +#define NX_TIEOFF_UART1_USESMC ((1<<16) | 151) +#define NX_TIEOFF_UART1_SMCTXENB ((1<<16) | 152) +#define NX_TIEOFF_UART1_SMCRXENB ((1<<16) | 153) +#define NX_TIEOFF_UART2_USESMC ((1<<16) | 154) +#define NX_TIEOFF_UART2_SMCTXENB ((1<<16) | 155) +#define NX_TIEOFF_UART2_SMCRXENB ((1<<16) | 156) +#define NX_TIEOFF_UART3_USESMC ((1<<16) | 157) +#define NX_TIEOFF_UART3_SMCTXENB ((1<<16) | 158) +#define NX_TIEOFF_UART3_SMCRXENB ((1<<16) | 159) +#define NX_TIEOFF_UART4_USESMC ((1<<16) | 160) +#define NX_TIEOFF_UART4_SMCTXENB ((1<<16) | 161) +#define NX_TIEOFF_UART4_SMCRXENB ((1<<16) | 162) +#define NX_TIEOFF_UART5_USESMC ((1<<16) | 163) +#define NX_TIEOFF_UART5_SMCTXENB ((1<<16) | 164) +#define NX_TIEOFF_UART5_SMCRXENB ((1<<16) | 165) +#define NX_TIEOFF_USB20HOST0_i_nPowerDown ((1<<16) | 166) +#define NX_TIEOFF_USB20HOST0_i_nSleep ((1<<16) | 167) +#define NX_TIEOFF_USB20HOST0_i_NX_RF1_EMA ((3<<16) | 168) +#define NX_TIEOFF_USB20HOST0_i_NX_RF1_EMAW ((2<<16) | 171) +#define NX_TIEOFF_USB20HOST0_sys_interrupt_i ((1<<16) | 173) +#define NX_TIEOFF_USB20HOST0_i_hsic_en ((3<<16) | 174) +#define NX_TIEOFF_USB20HOST0_ss_word_if_enb_i ((1<<16) | 185) +#define NX_TIEOFF_USB20HOST0_ss_word_if_i ((1<<16) | 186) +#define NX_TIEOFF_USB20HOST0_ss_utmi_backward_enb_i ((1<<16) | 187) +#define NX_TIEOFF_USB20HOST0_ss_resume_utmi_pls_dis_i ((1<<16) | 188) +#define NX_TIEOFF_USB20HOST0_phy_vstatus_0_i ((3<<16) | 189) +#define NX_TIEOFF_USB20HOST0_phy_vstatus_1_i ((3<<16) | 192) +#define NX_TIEOFF_USB20HOST0_phy_vstatus_2_i ((3<<16) | 195) +#define NX_TIEOFF_USB20HOST0_phy_vstatus_3_i ((3<<16) | 198) +#define NX_TIEOFF_USB20HOST0_phy_vstatus_4_i ((3<<16) | 201) +#define NX_TIEOFF_USB20HOST0_phy_vstatus_5_i ((3<<16) | 204) +#define NX_TIEOFF_USB20HOST0_phy_vstatus_6_i ((3<<16) | 207) +#define NX_TIEOFF_USB20HOST0_phy_vstatus_7_i ((3<<16) | 210) +#define NX_TIEOFF_USB20HOST0_ss_power_state_valid_i ((1<<16) | 213) +#define NX_TIEOFF_USB20HOST0_ss_nxt_power_state_valid_i ((1<<16) | 214) +#define NX_TIEOFF_USB20HOST0_ss_power_state_i ((2<<16) | 215) +#define NX_TIEOFF_USB20HOST0_ss_next_power_state_i ((2<<16) | 217) +#define NX_TIEOFF_USB20HOST0_app_prt_ovrcur_i ((3<<16) | 219) +#define NX_TIEOFF_USB20HOST0_ss_simulation_mode_i ((1<<16) | 222) +#define NX_TIEOFF_USB20HOST0_ss_fladj_val_host_i ((6<<16) | 224) +#define NX_TIEOFF_USB20HOST0_ss_fladj_val_5_i ((3<<16) | 230) +#define NX_TIEOFF_USB20HOST0_ss_fladj_val_4_i ((3<<16) | 233) +#define NX_TIEOFF_USB20HOST0_ss_fladj_val_3_i ((3<<16) | 236) +#define NX_TIEOFF_USB20HOST0_ss_fladj_val_2_i ((3<<16) | 239) +#define NX_TIEOFF_USB20HOST0_ss_fladj_val_1_i ((3<<16) | 242) +#define NX_TIEOFF_USB20HOST0_ss_fladj_val_0_i ((3<<16) | 245) +#define NX_TIEOFF_USB20HOST0_ss_autoppd_on_overcur_en_i ((1<<16) | 248) +#define NX_TIEOFF_USB20HOST0_ss_ena_incr16_i ((1<<16) | 249) +#define NX_TIEOFF_USB20HOST0_ss_ena_incr8_i ((1<<16) | 250) +#define NX_TIEOFF_USB20HOST0_ss_ena_incr4_i ((1<<16) | 251) +#define NX_TIEOFF_USB20HOST0_ss_ena_incrx_align_i ((1<<16) | 252) +#define NX_TIEOFF_USB20HOST0_i_ohci_0_cntsel_n ((1<<16) | 253) +#define NX_TIEOFF_USB20HOST0_ohci_0_app_irq1_i ((1<<16) | 254) +#define NX_TIEOFF_USB20HOST0_ohci_0_app_irq12_i ((1<<16) | 255) +#define NX_TIEOFF_USB20HOST0_ohci_0_app_io_hit_i ((1<<16) | 256) +#define NX_TIEOFF_USB20HOST0_ss_hubsetup_min_i ((1<<16) | 257) +#define NX_TIEOFF_USB20HOST0_app_start_clk_i ((1<<16) | 258) +#define NX_TIEOFF_USB20HOST0_ohci_susp_lgcy_i ((1<<16) | 259) +#define NX_TIEOFF_USB20HOST0_i_SIDDQ ((1<<16) | 260) +#define NX_TIEOFF_USB20HOST0_i_VATESTENB ((2<<16) | 261) +#define NX_TIEOFF_USB20HOST0_i_POR_ENB ((1<<16) | 263) +#define NX_TIEOFF_USB20HOST0_i_POR ((1<<16) | 264) +#define NX_TIEOFF_USB20HOST0_i_REFCLKSEL ((2<<16) | 265) +#define NX_TIEOFF_USB20HOST0_i_FSEL ((3<<16) | 267) +#define NX_TIEOFF_USB20HOST0_i_COMMONONN ((1<<16) | 270) +#define NX_TIEOFF_USB20HOST0_i_RESREQIN ((1<<16) | 271) +#define NX_TIEOFF_USB20HOST0_i_PORTRESET ((1<<16) | 272) +#define NX_TIEOFF_USB20HOST0_i_OTGDISABLE ((1<<16) | 273) +#define NX_TIEOFF_USB20HOST0_i_LOOPBACKENB ((1<<16) | 274) +#define NX_TIEOFF_USB20HOST0_i_IDPULLUPi ((1<<16) | 275) +#define NX_TIEOFF_USB20HOST0_i_DRVVBUS ((1<<16) | 276) +#define NX_TIEOFF_USB20HOST0_i_ADPCHRG ((1<<16) | 277) +#define NX_TIEOFF_USB20HOST0_i_ADPDISCHRG ((1<<16) | 278) +#define NX_TIEOFF_USB20HOST0_i_ADPPRBENB ((1<<16) | 279) +#define NX_TIEOFF_USB20HOST0_i_VBUSVLDEXT ((1<<16) | 280) +#define NX_TIEOFF_USB20HOST0_i_VBUSVLDEXTSEL ((1<<16) | 281) +#define NX_TIEOFF_USB20HOST0_i_DPPULLDOWN ((1<<16) | 282) +#define NX_TIEOFF_USB20HOST0_i_DMPULLDOWN ((1<<16) | 283) +#define NX_TIEOFF_USB20HOST0_i_SUSPENDM_ENB ((1<<16) | 284) +#define NX_TIEOFF_USB20HOST0_i_SUSPENDM ((1<<16) | 285) +#define NX_TIEOFF_USB20HOST0_i_SLEEPM_ENB ((1<<16) | 286) +#define NX_TIEOFF_USB20HOST0_i_SLEEPM ((1<<16) | 287) +#define NX_TIEOFF_USB20HOST0_i_OPMODE_ENB ((1<<16) | 288) +#define NX_TIEOFF_USB20HOST0_i_OPMODE ((2<<16) | 289) +#define NX_TIEOFF_USB20HOST0_i_TERMSEL_ENB ((1<<16) | 291) +#define NX_TIEOFF_USB20HOST0_i_TERMSEL ((1<<16) | 292) +#define NX_TIEOFF_USB20HOST0_i_XCVRSEL_ENB ((1<<16) | 293) +#define NX_TIEOFF_USB20HOST0_i_XCVRSEL ((2<<16) | 294) +#define NX_TIEOFF_USB20HOST0_i_WORDINTERFACE_ENB ((1<<16) | 296) +#define NX_TIEOFF_USB20HOST0_i_WORDINTERFACE ((1<<16) | 297) +#define NX_TIEOFF_USB20HOST0_i_TXBITSTUFFEN ((1<<16) | 298) +#define NX_TIEOFF_USB20HOST0_i_TXBITSTUFFENH ((1<<16) | 299) +#define NX_TIEOFF_USB20HOST0_i_BYPASSDPDATA ((1<<16) | 300) +#define NX_TIEOFF_USB20HOST0_i_BYPASSDMDATA ((1<<16) | 301) +#define NX_TIEOFF_USB20HOST0_i_BYPASSDPEN ((1<<16) | 302) +#define NX_TIEOFF_USB20HOST0_i_BYPASSDMEN ((1<<16) | 303) +#define NX_TIEOFF_USB20HOST0_i_BYPASSSEL ((1<<16) | 304) +#define NX_TIEOFF_USB20HOST0_i_COMPDISTUNE ((3<<16) | 305) +#define NX_TIEOFF_USB20HOST0_i_SQRXTUNE ((3<<16) | 308) +#define NX_TIEOFF_USB20HOST0_i_OTGTUNE ((3<<16) | 311) +#define NX_TIEOFF_USB20HOST0_i_TXHSXVTUNE ((2<<16) | 314) +#define NX_TIEOFF_USB20HOST0_i_TXFSLSTUNE ((4<<16) | 316) +#define NX_TIEOFF_USB20HOST0_i_TXVREFTUNE ((4<<16) | 320) +#define NX_TIEOFF_USB20HOST0_i_TXRISETUNE ((2<<16) | 324) +#define NX_TIEOFF_USB20HOST0_i_TXRESTUNE ((2<<16) | 326) +#define NX_TIEOFF_USB20HOST0_i_TXPREEMPAMPTUNE ((2<<16) | 328) +#define NX_TIEOFF_USB20HOST0_i_TXPREEMPPULSETUNE ((1<<16) | 330) +#define NX_TIEOFF_USB20HOST0_i_CHRGSEL ((1<<16) | 331) +#define NX_TIEOFF_USB20HOST0_i_VDATDETENB ((1<<16) | 332) +#define NX_TIEOFF_USB20HOST0_i_VDATSRCENB ((1<<16) | 333) +#define NX_TIEOFF_USB20HOST0_i_DCDENB ((1<<16) | 334) +#define NX_TIEOFF_USB20HOST0_i_ACAENB ((1<<16) | 335) +#define NX_TIEOFF_USB20HOST0_i_HSIC_MSTRXCVR ((1<<16) | 336) +#define NX_TIEOFF_USB20HOST0_i_HSIC_SIDDQ ((1<<16) | 337) +#define NX_TIEOFF_USB20HOST0_i_HSIC_POR_ENB ((1<<16) | 338) +#define NX_TIEOFF_USB20HOST0_i_HSIC_POR ((1<<16) | 339) +#define NX_TIEOFF_USB20HOST0_i_HSIC_REFCLKDIV ((7<<16) | 340) +#define NX_TIEOFF_USB20HOST0_i_HSIC_REFCLKSEL ((2<<16) | 347) +#define NX_TIEOFF_USB20HOST0_i_HSIC_COMMONONN ((1<<16) | 349) +#define NX_TIEOFF_USB20HOST0_i_HSIC_PORTRESET ((1<<16) | 350) +#define NX_TIEOFF_USB20HOST0_i_HSIC_LOOPBACKENB ((1<<16) | 351) +#define NX_TIEOFF_USB20HOST0_i_HSIC_DPPULLDOWN ((1<<16) | 352) +#define NX_TIEOFF_USB20HOST0_i_HSIC_DMPULLDOWN ((1<<16) | 353) +#define NX_TIEOFF_USB20HOST0_i_HSIC_SUSPENDM_ENB ((1<<16) | 354) +#define NX_TIEOFF_USB20HOST0_i_HSIC_SUSPENDM ((1<<16) | 355) +#define NX_TIEOFF_USB20HOST0_i_HSIC_SLEEPM_ENB ((1<<16) | 356) +#define NX_TIEOFF_USB20HOST0_i_HSIC_SLEEPM ((1<<16) | 357) +#define NX_TIEOFF_USB20HOST0_i_HSIC_MSTRXOPU ((1<<16) | 358) +#define NX_TIEOFF_USB20HOST0_i_HSIC_OPMODE_ENB ((1<<16) | 359) +#define NX_TIEOFF_USB20HOST0_i_HSIC_OPMODE ((2<<16) | 360) +#define NX_TIEOFF_USB20HOST0_i_HSIC_XCVRSELECT_ENB ((1<<16) | 362) +#define NX_TIEOFF_USB20HOST0_i_HSIC_XCVRSELECT ((1<<16) | 363) +#define NX_TIEOFF_USB20HOST0_i_HSIC_WORDINTERFACE_ENB ((1<<16) | 364) +#define NX_TIEOFF_USB20HOST0_i_HSIC_WORDINTERFACE ((1<<16) | 365) +#define NX_TIEOFF_USB20HOST0_i_HSIC_TXBITSTUFFEN ((1<<16) | 366) +#define NX_TIEOFF_USB20HOST0_i_HSIC_TXBITSTUFFENH ((1<<16) | 367) +#define NX_TIEOFF_USB20HOST0_i_HSIC_TXRPUTUNE ((2<<16) | 368) +#define NX_TIEOFF_USB20HOST0_i_HSIC_TXRPDTUNE ((2<<16) | 370) +#define NX_TIEOFF_USB20HOST0_i_HSIC_TXSRTUNE ((4<<16) | 372) +#define NX_TIEOFF_USB20OTG0_i_nPowerDown ((1<<16) | 376) +#define NX_TIEOFF_USB20OTG0_i_nSleep ((1<<16) | 377) +#define NX_TIEOFF_USB20OTG0_i_NX_RF1_EMA ((3<<16) | 378) +#define NX_TIEOFF_USB20OTG0_i_NX_RF1_EMAW ((2<<16) | 381) +#define NX_TIEOFF_USB20OTG0_i_ss_scaledown_mode ((2<<16) | 384) +#define NX_TIEOFF_USB20OTG0_i_gp_in ((16<<16) | 386) +#define NX_TIEOFF_USB20OTG0_i_sof_count ((14<<16) | 402) +#define NX_TIEOFF_USB20OTG0_i_sys_dma_done ((1<<16) | 416) +#define NX_TIEOFF_USB20OTG0_i_if_select_hsic ((1<<16) | 417) +#define NX_TIEOFF_USB20OTG0_i_nResetSync ((1<<16) | 418) +#define NX_TIEOFF_USB20OTG0_i_nUtmiResetSync ((1<<16) | 419) +#define NX_TIEOFF_USB20OTG0_i_SIDDQ ((1<<16) | 420) +#define NX_TIEOFF_USB20OTG0_i_VATESTENB ((2<<16) | 421) +#define NX_TIEOFF_USB20OTG0_i_POR_ENB ((1<<16) | 423) +#define NX_TIEOFF_USB20OTG0_i_POR ((1<<16) | 424) +#define NX_TIEOFF_USB20OTG0_i_REFCLKSEL ((2<<16) | 425) +#define NX_TIEOFF_USB20OTG0_i_FSEL ((3<<16) | 427) +#define NX_TIEOFF_USB20OTG0_i_COMMONONN ((1<<16) | 430) +#define NX_TIEOFF_USB20OTG0_i_RESREQIN ((1<<16) | 431) +#define NX_TIEOFF_USB20OTG0_i_PORTRESET ((1<<16) | 432) +#define NX_TIEOFF_USB20OTG0_i_OTGDISABLE ((1<<16) | 433) +#define NX_TIEOFF_USB20OTG0_i_LOOPBACKENB ((1<<16) | 434) +#define NX_TIEOFF_USB20OTG0_i_IDPULLUP ((1<<16) | 435) +#define NX_TIEOFF_USB20OTG0_i_DRVVBUS ((1<<16) | 436) +#define NX_TIEOFF_USB20OTG0_i_ADPCHRG ((1<<16) | 437) +#define NX_TIEOFF_USB20OTG0_i_ADPDISCHRG ((1<<16) | 438) +#define NX_TIEOFF_USB20OTG0_i_ADPPRBENB ((1<<16) | 439) +#define NX_TIEOFF_USB20OTG0_i_VBUSVLDEXT ((1<<16) | 440) +#define NX_TIEOFF_USB20OTG0_i_VBUSVLDEXTSEL ((1<<16) | 441) +#define NX_TIEOFF_USB20OTG0_i_DPPULLDOWN ((1<<16) | 442) +#define NX_TIEOFF_USB20OTG0_i_DMPULLDOWN ((1<<16) | 443) +#define NX_TIEOFF_USB20OTG0_i_SUSPENDM_ENB ((1<<16) | 444) +#define NX_TIEOFF_USB20OTG0_i_SUSPENDM ((1<<16) | 445) +#define NX_TIEOFF_USB20OTG0_i_SLEEPM_ENB ((1<<16) | 446) +#define NX_TIEOFF_USB20OTG0_i_SLEEPM ((1<<16) | 447) +#define NX_TIEOFF_USB20OTG0_i_OPMODE_ENB ((1<<16) | 448) +#define NX_TIEOFF_USB20OTG0_i_OPMODE ((2<<16) | 449) +#define NX_TIEOFF_USB20OTG0_i_TERMSEL_ENB ((1<<16) | 451) +#define NX_TIEOFF_USB20OTG0_i_TERMSEL ((1<<16) | 452) +#define NX_TIEOFF_USB20OTG0_i_XCVRSEL_ENB ((1<<16) | 453) +#define NX_TIEOFF_USB20OTG0_i_XCVRSEL ((2<<16) | 454) +#define NX_TIEOFF_USB20OTG0_i_WORDINTERFACE_ENB ((1<<16) | 456) +#define NX_TIEOFF_USB20OTG0_i_WORDINTERFACE ((1<<16) | 457) +#define NX_TIEOFF_USB20OTG0_i_TXBITSTUFFEN ((1<<16) | 458) +#define NX_TIEOFF_USB20OTG0_i_TXBITSTUFFENH ((1<<16) | 459) +#define NX_TIEOFF_USB20OTG0_i_BYPASSDPDATA ((1<<16) | 460) +#define NX_TIEOFF_USB20OTG0_i_BYPASSDMDATA ((1<<16) | 461) +#define NX_TIEOFF_USB20OTG0_i_BYPASSDPEN ((1<<16) | 462) +#define NX_TIEOFF_USB20OTG0_i_BYPASSDMEN ((1<<16) | 463) +#define NX_TIEOFF_USB20OTG0_i_BYPASSSEL ((1<<16) | 464) +#define NX_TIEOFF_USB20OTG0_i_COMPDISTUNE ((3<<16) | 465) +#define NX_TIEOFF_USB20OTG0_i_SQRXTUNE ((3<<16) | 468) +#define NX_TIEOFF_USB20OTG0_i_OTGTUNE ((3<<16) | 471) +#define NX_TIEOFF_USB20OTG0_i_TXHSXVTUNE ((2<<16) | 474) +#define NX_TIEOFF_USB20OTG0_i_TXFSLSTUNE ((4<<16) | 476) +#define NX_TIEOFF_USB20OTG0_i_TXVREFTUNE ((4<<16) | 480) +#define NX_TIEOFF_USB20OTG0_i_TXRISETUNE ((2<<16) | 484) +#define NX_TIEOFF_USB20OTG0_i_TXRESTUNE ((2<<16) | 486) +#define NX_TIEOFF_USB20OTG0_i_TXPREEMPAMPTUNE ((2<<16) | 488) +#define NX_TIEOFF_USB20OTG0_i_TXPREEMPPULSETUNE ((1<<16) | 490) +#define NX_TIEOFF_USB20OTG0_i_CHRGSEL ((1<<16) | 491) +#define NX_TIEOFF_USB20OTG0_i_VDATDETENB ((1<<16) | 492) +#define NX_TIEOFF_USB20OTG0_i_VDATSRCENB ((1<<16) | 493) +#define NX_TIEOFF_USB20OTG0_i_DCDENB ((1<<16) | 494) +#define NX_TIEOFF_USB20OTG0_i_ACAENB ((1<<16) | 495) +#define NX_TIEOFF_USB20OTG0_i_IDPULLUP_ENB ((1<<16) | 496) +#define NX_TIEOFF_USB20OTG0_i_DPPULLDOWN_ENB ((1<<16) | 497) +#define NX_TIEOFF_USB20OTG0_i_DMPULLDOWN_ENB ((1<<16) | 498) +#define NX_TIEOFF_USB20OTG0_i_DRVVBUS_ENB ((1<<16) | 499) +#define NX_TIEOFF_USB20OTG0_i_LPMClkMuxCntrl ((1<<16) | 500) +#define NX_TIEOFF_USB20OTG0_i_GLITCHLESSMUXCntrl ((1<<16) | 501) +#define NX_TIEOFF_CODA9600_i_nPWRDN00 ((4<<16) | 502) +#define NX_TIEOFF_CODA9600_i_nSLEEP00 ((4<<16) | 506) +#define NX_TIEOFF_CODA9600_i_nPWRDN01 ((8<<16) | 512) +#define NX_TIEOFF_CODA9600_i_nSLEEP01 ((8<<16) | 520) +#define NX_TIEOFF_CODA9600_i_nPWRDN02 ((10<<16) | 528) +#define NX_TIEOFF_CODA9600_i_nSLEEP02 ((10<<16) | 544) +#define NX_TIEOFF_CODA9600_i_nPWRDN03 ((2<<16) | 554) +#define NX_TIEOFF_CODA9600_i_nSLEEP03 ((2<<16) | 556) +#define NX_TIEOFF_CODA9600_i_nPWRDN04 ((8<<16) | 558) +#define NX_TIEOFF_CODA9600_i_nSLEEP04 ((8<<16) | 566) +#define NX_TIEOFF_CODA9600_i_nPWRDN05 ((3<<16) | 576) +#define NX_TIEOFF_CODA9600_i_nSLEEP05 ((3<<16) | 579) +#define NX_TIEOFF_CODA9600_i_nPWRDN06 ((7<<16) | 582) +#define NX_TIEOFF_CODA9600_i_nSLEEP06 ((7<<16) | 589) +#define NX_TIEOFF_CODA9600_i_nPWRDN07 ((12<<16) | 596) +#define NX_TIEOFF_CODA9600_i_nSLEEP07 ((12<<16) | 608) +#define NX_TIEOFF_CODA9600_i_nPWRDN08 ((1<<16) | 620) +#define NX_TIEOFF_CODA9600_i_nSLEEP08 ((1<<16) | 621) +#define NX_TIEOFF_CODA9600_i_nPWRDN09 ((2<<16) | 622) +#define NX_TIEOFF_CODA9600_i_nSLEEP09 ((2<<16) | 624) +#define NX_TIEOFF_CODA9600_i_nPWRDN10 ((10<<16) | 626) +#define NX_TIEOFF_CODA9600_i_nSLEEP10 ((10<<16) | 640) +#define NX_TIEOFF_CODA9600_i_nPWRDN11 ((1<<16) | 650) +#define NX_TIEOFF_CODA9600_i_nSLEEP11 ((1<<16) | 651) +#define NX_TIEOFF_CODA9600_i_TIE_rf2_EMAA ((3<<16) | 652) +#define NX_TIEOFF_CODA9600_i_TIE_rf2_EMAB ((3<<16) | 655) +#define NX_TIEOFF_CODA9600_i_TIE_rf2w_EMAA ((3<<16) | 658) +#define NX_TIEOFF_CODA9600_i_TIE_rf2w_EMAB ((3<<16) | 661) +#define NX_TIEOFF_CODA9600_i_TIE_ra2_EMAA ((3<<16) | 664) +#define NX_TIEOFF_CODA9600_i_TIE_ra2_EMAB ((3<<16) | 667) +#define NX_TIEOFF_CODA9600_i_TIE_ra2_EMAWA ((2<<16) | 670) +#define NX_TIEOFF_CODA9600_i_TIE_ra2_EMAWB ((2<<16) | 672) +#define NX_TIEOFF_CODA9600_i_TIE_ra2w_EMAA ((3<<16) | 674) +#define NX_TIEOFF_CODA9600_i_TIE_ra2w_EMAB ((3<<16) | 677) +#define NX_TIEOFF_CODA9600_i_TIE_ra2w_EMAWA ((2<<16) | 680) +#define NX_TIEOFF_CODA9600_i_TIE_ra2w_EMAWB ((2<<16) | 682) +#define NX_TIEOFF_CODA9600_i_TIE_rf1_EMA ((3<<16) | 684) +#define NX_TIEOFF_CODA9600_i_TIE_rf1_EMAW ((2<<16) | 687) +#define NX_TIEOFF_CODA9600_i_TIE_rf1w_EMA ((3<<16) | 689) +#define NX_TIEOFF_CODA9600_i_TIE_rf1w_EMAW ((2<<16) | 692) +#define NX_TIEOFF_DWC_GMAC0_sbd_flowctrl_i ((1<<16) | 694) +#define NX_TIEOFF_DWC_GMAC0_phy_intf_sel_i ((3<<16) | 695) +#define NX_TIEOFF_DWC_GMAC0_i_NX_RF2_EMAA ((3<<16) | 698) +#define NX_TIEOFF_DWC_GMAC0_i_NX_RF2_EMAB ((3<<16) | 701) +#define NX_TIEOFF_MALI4000_NX_DPSRAM_1R1W_EMAA ((3<<16) | 704) +#define NX_TIEOFF_MALI4000_NX_DPSRAM_1R1W_EMAB ((3<<16) | 707) +#define NX_TIEOFF_MALI4000_NX_SPSRAM_EMA ((3<<16) | 710) +#define NX_TIEOFF_MALI4000_NX_SPSRAM_EMAW ((2<<16) | 713) +#define NX_TIEOFF_MALI4000_NX_SPSRAM_BW_EMA ((3<<16) | 715) +#define NX_TIEOFF_MALI4000_NX_SPSRAM_BW_EMAW ((2<<16) | 718) +#define NX_TIEOFF_MALI4000_PWRDNBYPASS ((1<<16) | 720) +#define NX_TIEOFF_MALI4000_GP_NX_NPOWERDOWN ((15<<16) | 721) +#define NX_TIEOFF_MALI4000_GP_NX_NSLEEP ((15<<16) | 736) +#define NX_TIEOFF_MALI4000_L2_NX_NPOWERDOWN ((3<<16) | 751) +#define NX_TIEOFF_MALI4000_L2_NX_NSLEEP ((3<<16) | 754) +#define NX_TIEOFF_MALI4000_PP0_NX_NPOWERDOWN ((32<<16) | 768) +#define NX_TIEOFF_MALI4000_PP0_NX_NSLEEP ((32<<16) | 800) +#define NX_TIEOFF_MALI4000_PP1_NX_NPOWERDOWN ((32<<16) | 832) +#define NX_TIEOFF_MALI4000_PP1_NX_NSLEEP ((32<<16) | 864) +#define NX_TIEOFF_MALI4000_PP2_NX_NPOWERDOWN ((32<<16) | 896) +#define NX_TIEOFF_MALI4000_PP2_NX_NSLEEP ((32<<16) | 928) +#define NX_TIEOFF_MALI4000_PP3_NX_NPOWERDOWN ((32<<16) | 960) +#define NX_TIEOFF_MALI4000_PP3_NX_NSLEEP ((32<<16) | 992) +#define NX_TIEOFF_A3BM_AXI_PERI_BUS0_SYNCMODEREQm9 ((1<<16) | 1024) +#define NX_TIEOFF_A3BM_AXI_PERI_BUS0_SYNCMODEREQm10 ((1<<16) | 1025) +#define NX_TIEOFF_A3BM_AXI_PERI_BUS0_SYNCMODEREQm16 ((1<<16) | 1026) +#define NX_TIEOFF_A3BM_AXI_TOP_MASTER_BUS0_REMAP ((2<<16) | 1027) +#define NX_TIEOFF_Inst_ARMTOP_SMPEN ((4<<16) | 2816) +#define NX_TIEOFF_Inst_ARMTOP_STANBYWFI ((4<<16) | 2880) +#define NX_TIEOFF_Inst_ARMTOP_STANBYWFIL2 ((1<<16) | 2884) +#define NX_TIEOFF_Inst_ARMTOP_DBGNOPWRDWN ((4<<16) | 2889) +#define NX_TIEOFF_Inst_ARMTOP_DBGPWRUPREQ ((4<<16) | 2893) +#define NX_TIEOFF_Inst_ARMTOP_COREPWRDOWNPRE ((1<<16) | 2901) +#define NX_TIEOFF_Inst_ARMTOP_CPU0PWRDOWNPRE ((1<<16) | 2902) +#define NX_TIEOFF_Inst_ARMTOP_CPU1PWRDOWNPRE ((1<<16) | 2903) +#define NX_TIEOFF_Inst_ARMTOP_CPU2PWRDOWNPRE ((1<<16) | 2904) +#define NX_TIEOFF_Inst_ARMTOP_CPU3PWRDOWNPRE ((1<<16) | 2905) +#define NX_TIEOFF_Inst_ARMTOP_COREPWRDOWNALL ((1<<16) | 2906) +#define NX_TIEOFF_Inst_ARMTOP_CPU0PWRDOWNALL ((1<<16) | 2907) +#define NX_TIEOFF_Inst_ARMTOP_CPU1PWRDOWNALL ((1<<16) | 2908) +#define NX_TIEOFF_Inst_ARMTOP_CPU2PWRDOWNALL ((1<<16) | 2909) +#define NX_TIEOFF_Inst_ARMTOP_CPU3PWRDOWNALL ((1<<16) | 2910) +#define NX_TIEOFF_Inst_ARMTOP_CLAMPL2 ((1<<16) | 2920) +#define NX_TIEOFF_Inst_ARMTOP_L2FLUSHREQ ((1<<16) | 3018) +#define NX_TIEOFF_Inst_ARMTOP_L2FLUSHDONE ((1<<16) | 3019) +#define NX_TIEOFF_Inst_ARMTOP_ACINACTM ((1<<16) | 3023) +#define NX_TIEOFF_Inst_ARMTOP_P1_SMPEN ((4<<16) | 3360) +#define NX_TIEOFF_Inst_ARMTOP_P1_STANBYWFI ((4<<16) | 3424) +#define NX_TIEOFF_Inst_ARMTOP_P1_STANBYWFIL2 ((1<<16) | 3428) +#define NX_TIEOFF_Inst_ARMTOP_P1_DBGNOPWRDWN ((4<<16) | 3442) +#define NX_TIEOFF_Inst_ARMTOP_P1_DBGPWRUPREQ ((4<<16) | 3443) +#define NX_TIEOFF_Inst_ARMTOP_P1_DBGPWRDUP ((4<<16) | 3444) +#define NX_TIEOFF_Inst_ARMTOP_P1_COREPWRDOWNPRE ((1<<16) | 3445) +#define NX_TIEOFF_Inst_ARMTOP_P1_CPU0PWRDOWNPRE ((1<<16) | 3446) +#define NX_TIEOFF_Inst_ARMTOP_P1_CPU1PWRDOWNPRE ((1<<16) | 3447) +#define NX_TIEOFF_Inst_ARMTOP_P1_CPU2PWRDOWNPRE ((1<<16) | 3448) +#define NX_TIEOFF_Inst_ARMTOP_P1_CPU3PWRDOWNPRE ((1<<16) | 3449) +#define NX_TIEOFF_Inst_ARMTOP_P1_COREPWRDOWNALL ((1<<16) | 3450) +#define NX_TIEOFF_Inst_ARMTOP_P1_CPU0PWRDOWNALL ((1<<16) | 3451) +#define NX_TIEOFF_Inst_ARMTOP_P1_CPU1PWRDOWNALL ((1<<16) | 3452) +#define NX_TIEOFF_Inst_ARMTOP_P1_CPU2PWRDOWNALL ((1<<16) | 3453) +#define NX_TIEOFF_Inst_ARMTOP_P1_CPU3PWRDOWNALL ((1<<16) | 3454) +#define NX_TIEOFF_Inst_ARMTOP_P1_CLAMPL2 ((1<<16) | 3464) +#define NX_TIEOFF_Inst_ARMTOP_P1_L2FLUSHREQ ((1<<16) | 3562) +#define NX_TIEOFF_Inst_ARMTOP_P1_L2FLUSHDONE ((1<<16) | 3563) +#define NX_TIEOFF_Inst_ARMTOP_P1_ACINACTM ((1<<16) | 3567) + +void nx_tieoff_set(uint32_t tieoff_index, uint32_t tieoff_value); +uint32_t nx_tieoff_get(uint32_t tieoff_index); + +#endif /* _S5P6818_TIEOFF_H */ diff --git a/core/include/drivers/s5p6818_uart.h b/core/include/drivers/s5p6818_uart.h new file mode 100644 index 0000000..e4a4442 --- /dev/null +++ b/core/include/drivers/s5p6818_uart.h @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2016 Nexell Co., Ltd. + * Author: Bon-gyu, KOO <freestyle@nexell.co.kr> + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __S5P6818_UART_H__ +#define __S5P6818_UART_H__ + +#include <types_ext.h> +#include <drivers/serial.h> + +struct s5p6818_uart_data { + struct io_pa_va base; + struct serial_chip chip; +}; + +void s5p6818_uart_init(struct s5p6818_uart_data *pd, paddr_t base, + uint32_t uart_clk, uint32_t baud_rate); + +#endif /* __S5P6818_UART_H__ */ + diff --git a/packaging/optee-os-artik710.spec b/packaging/optee-os-artik710.spec new file mode 100644 index 0000000..5cc1bc8 --- /dev/null +++ b/packaging/optee-os-artik710.spec @@ -0,0 +1,43 @@ +%define buildplat s5p6818 +%define compile_flags CROSS_COMPILE="" CROSS_COMPILE64="" PLATFORM=%{buildplat} CFLAGS=-lgcc_eh CFG_LIBUTEE_TUI=n CFG_TEE_CORE_LOG_LEVEL=3 DEBUG=0 +%if %{__isa_bits} == 64 +%define compile_arch %{compile_flags} CFG_ARM64_core=y +%else +%define compile_arch %{compile_flags} CFG_WITH_VFP=n +%endif +%define out_dir out/arm-plat-%{buildplat} + +Name: optee-os-artik710 +Summary: OPTEE trusted operation system. +Version: 2.4.0 +Release: 1%{?dist} +Group: Security/Testing +License: BSD-2-Clause +URL: https://github.com/OP-TEE/optee_os +Source0: %{name}-%{version}-%{buildplat}.tar.gz +ExclusiveArch: armv6l armv7hl armv7l aarch64 + +Provides: tee.bin + +BuildRequires: make +BuildRequires: python +BuildRequires: openssl + +%description +Trusted execution enviroment in Linux using the ARMĀ® TrustZoneĀ® technology. + +%prep +%setup -q + +%build +make %{compile_arch} %{out_dir}/core/tee.bin + +%install +mkdir -p %{buildroot}/boot/ + +cp -p %{_builddir}/%{name}-%{version}/%{out_dir}/core/tee.bin %{buildroot}/boot/ + +%clean + +%files +/boot/tee.bin |