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/*
* Copyright (c) 2023 Samsung Electronics Co., Ltd. All Rights Reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <cassert>
#include <string>
#include "nnfw.h"
namespace onert_train
{
uint64_t num_elems(const nnfw_tensorinfo *ti)
{
uint64_t n = 1;
for (uint32_t i = 0; i < ti->rank; ++i)
{
assert(ti->dims[i] >= 0);
n *= ti->dims[i];
}
return n;
}
uint64_t bufsize_for(const nnfw_tensorinfo *ti)
{
static int elmsize[] = {
sizeof(float), /* NNFW_TYPE_TENSOR_FLOAT32 */
sizeof(int), /* NNFW_TYPE_TENSOR_INT32 */
sizeof(uint8_t), /* NNFW_TYPE_TENSOR_QUANT8_ASYMM */
sizeof(bool), /* NNFW_TYPE_TENSOR_BOOL = 3 */
sizeof(uint8_t), /* NNFW_TYPE_TENSOR_UINT8 = 4 */
sizeof(int64_t), /* NNFW_TYPE_TENSOR_INT64 = 5 */
sizeof(int8_t), /* NNFW_TYPE_TENSOR_QUANT8_ASYMM_SIGNED = 6 */
sizeof(int16_t), /* NNFW_TYPE_TENSOR_QUANT16_SYMM_SIGNED = 7 */
};
return elmsize[ti->dtype] * num_elems(ti);
}
} // namespace onert_train
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