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/*
* Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
* Copyright (c) 2017-2018 ARM Limited.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "arm_compute/runtime/CL/functions/CLReduceOperation.h"
#include "arm_compute/core/CL/kernels/CLReduceOperationKernel.h"
#include "arm_compute/runtime/CL/CLScheduler.h"
using namespace arm_compute;
CLReduceOperation::CLReduceOperation()
: _input(nullptr), _output(nullptr), _axis(), _interm_tensors(), _reduce_kernels()
{
}
Status CLReduceOperation::validate(const ITensorInfo *input, const ITensorInfo *output,
const std::set<uint32_t> &axis, const ReduceOperation &op)
{
const size_t num_of_kernels = axis.size();
const size_t num_of_interm_tensors = num_of_kernels - 1;
// Create temporary tensor infos
auto interm_tensors =
arm_compute::support::cpp14::make_unique<TensorInfo[]>(num_of_interm_tensors);
// Create intermediate tensor info
TensorShape shape{input->tensor_shape()};
auto it = axis.begin();
for (size_t i = 0; i < num_of_interm_tensors; ++i, ++it)
{
shape.set(*it, 1);
interm_tensors[i].set_data_type(input->data_type());
interm_tensors[i].set_tensor_shape(shape);
interm_tensors[i].set_num_channels(input->num_channels());
interm_tensors[i].set_data_layout(input->data_layout());
}
// Set a vector that is ordered ITensorInfo sequentially.
std::vector<const ITensorInfo *> tensors;
tensors.emplace_back(input);
for (size_t i = 0; i < num_of_interm_tensors; ++i)
{
tensors.emplace_back(interm_tensors.get() + i);
}
tensors.emplace_back(output);
// Validate ReduceOperation only on all kernels
it = axis.begin();
for (size_t i = 0; i < num_of_kernels; ++i, ++it)
{
ARM_COMPUTE_RETURN_ON_ERROR(
CLReduceOperationKernel::validate(tensors[i], tensors[i + 1], *it, op));
}
return Status{};
}
void CLReduceOperation::configure(ICLTensor *input, ICLTensor *output,
const std::set<uint32_t> &axis, ReduceOperation op)
{
ARM_COMPUTE_ERROR_THROW_ON(validate(input->info(), output->info(), axis, op));
_axis = axis;
_input = input;
_output = output;
// NOTE The axis must have no duplication.
const size_t num_of_kernels = axis.size();
const size_t num_of_interm_tensors = num_of_kernels - 1;
_interm_tensors = arm_compute::support::cpp14::make_unique<CLTensor[]>(num_of_interm_tensors);
_reduce_kernels =
arm_compute::support::cpp14::make_unique<CLReduceOperationKernel[]>(num_of_kernels);
TensorShape shape{input->info()->tensor_shape()};
auto it = axis.begin();
for (size_t i = 0; i < num_of_interm_tensors; ++i, ++it)
{
shape.set(*it, 1);
_interm_tensors[i].allocator()->init(
TensorInfo(shape, input->info()->num_channels(), input->info()->data_type())
.set_data_layout(input->info()->data_layout()));
_interm_tensors[i].allocator()->allocate();
}
// Set a vector that is ordered ICLTensors sequentially.
std::vector<ICLTensor *> tensors;
tensors.emplace_back(input);
for (size_t i = 0; i < num_of_interm_tensors; ++i)
{
tensors.emplace_back(_interm_tensors.get() + i);
}
tensors.emplace_back(output);
// Apply ReduceOperation on all kernels
it = axis.begin();
for (size_t i = 0; i < num_of_kernels; ++i, ++it)
{
_reduce_kernels[i].configure(tensors[i], tensors[i + 1], *it, op);
}
}
void CLReduceOperation::run()
{
const size_t num_of_kernels = _axis.size();
for (size_t i = 0; i < num_of_kernels; ++i)
{
CLScheduler::get().enqueue(_reduce_kernels[i]);
}
}
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