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/*
* Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __NEURUN_BACKEND_ITENSOR_REGISTER_H__
#define __NEURUN_BACKEND_ITENSOR_REGISTER_H__
#include "compiler/SubTensorInfo.h"
#include "ir/LowerInfoMap.h"
#include "ir/operand/ParentInfo.h"
#include "ITensorBuilder.h"
#include "ir/Layout.h"
#include "ir/OperandIndexSequence.h"
#include "ir/OperandInfo.h"
#include "ir/Operands.h"
#include "ir/OperationVisitor.h"
namespace
{
neurun::ir::Shape permuteTensorShape(const neurun::ir::Shape &shape,
neurun::ir::Layout frontend_layout,
neurun::ir::Layout backend_layout)
{
assert(shape.rank() <= 4);
neurun::ir::Shape backend_shape{shape};
if (shape.rank() == 4 && frontend_layout == neurun::ir::Layout::NHWC &&
backend_layout == neurun::ir::Layout::NCHW)
{
backend_shape.dim(1) = shape.dim(3);
backend_shape.dim(2) = shape.dim(1);
backend_shape.dim(3) = shape.dim(2);
}
else if (shape.rank() == 4 && frontend_layout == neurun::ir::Layout::NCHW &&
backend_layout == neurun::ir::Layout::NHWC)
{
backend_shape.dim(1) = shape.dim(2);
backend_shape.dim(2) = shape.dim(3);
backend_shape.dim(3) = shape.dim(1);
}
return backend_shape;
}
} // namespace
namespace neurun
{
namespace backend
{
class ITensorRegister : public ir::OperationVisitor
{
public:
virtual ~ITensorRegister() = default;
public:
void registerTensors(const ir::OpSequence &subg, const ir::LowerInfoMap *lower_info_map)
{
_current_subg_layout = subg.getLayout();
_lower_info_map = lower_info_map;
assert(_lower_info_map != nullptr);
assert(tensor_builder().get() != nullptr);
subg.accept(*this);
}
protected:
virtual const ir::Operands &operands() const = 0;
virtual std::shared_ptr<ITensorBuilder> tensor_builder() const = 0;
virtual bool supportSubTensor() const = 0;
protected:
#define OP(InternalName) \
void visit(const ir::operation::InternalName &node) override \
{ \
ir::OperandIndexSequence indices{node.getInputs()}; \
indices.append(node.getOutputs()); \
for (const auto &index : indices) \
{ \
defaultRegisterTensorInfo(index); \
} \
}
#include "ir/Operations.lst"
#undef OP
protected:
void defaultRegisterTensorInfo(const ir::OperandIndex &index) const
{
if (tensor_builder()->isRegistered(index))
{
return;
}
const auto &obj = operands().at(index);
const auto frontend_layout = frontendLayout();
const auto backend_layout = backendLayout(index);
if (supportSubTensor() && obj.parent_info() != nullptr)
{
tensor_builder()->registerSubTensorInfo(
index, generateSubTensorInfo(obj, frontend_layout, backend_layout));
}
else
{
ir::OperandInfo backend_info{permuteTensorShape(obj.shape(), frontend_layout, backend_layout),
obj.typeInfo()};
tensor_builder()->registerTensorInfo(index, backend_info, backend_layout, obj.isConstant());
}
}
protected:
ir::Layout frontendLayout() const { return _current_subg_layout; }
ir::Layout backendLayout(const ir::OperandIndex &index) const
{
assert(_lower_info_map != nullptr);
const auto lower_info = _lower_info_map->operand.at(index).get();
return lower_info->def_factors().getOnlyElement().layout();
}
private:
compiler::SubTensorInfo generateSubTensorInfo(const ir::Operand &obj, ir::Layout frontend_layout,
ir::Layout backend_layout) const
{
assert(obj.shape().rank() <= 4);
const auto parent_index = obj.parent_info()->parent();
auto shape = obj.shape();
auto offset = obj.parent_info()->offset();
if (operands().at(parent_index).shape().rank() == 4 && frontend_layout == ir::Layout::NHWC &&
backend_layout == ir::Layout::NCHW)
{
shape.extendRank(4);
offset = {offset[0], offset[3], offset[1], offset[2]};
}
else if (operands().at(parent_index).shape().rank() == 4 &&
frontend_layout == ir::Layout::NHWC && backend_layout == ir::Layout::NCHW)
{
shape.extendRank(4);
offset = {offset[0], offset[2], offset[3], offset[1]};
}
ir::Operand subtensor_obj{permuteTensorShape(shape, frontend_layout, backend_layout),
obj.typeInfo()};
subtensor_obj.parent_info(
nnfw::cpp14::make_unique<ir::operand::ParentInfo>(parent_index, offset));
return compiler::SubTensorInfo{subtensor_obj};
}
private:
ir::Layout _current_subg_layout;
const ir::LowerInfoMap *_lower_info_map{nullptr};
};
} // namespace backend
} // namespace neurun
#endif // __NEURUN_BACKEND_ITENSOR_REGISTER_H__
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