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/*
* Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __NEURUN_BACKEND_CPU_TENSOR_BUILDER_H__
#define __NEURUN_BACKEND_CPU_TENSOR_BUILDER_H__
#include <unordered_map>
#include <backend/ITensorBuilder.h>
#include "operand/Tensor.h"
#include "ir/OperandIndexMap.h"
#include "TensorManager.h"
namespace neurun
{
namespace backend
{
namespace cpu
{
class TensorBuilder : public ITensorBuilder
{
public:
TensorBuilder();
/**
* @brief Register tensor information to allocate on CPU backend
* @param[in] ind Operand index
* @param[in] info Operand information
* @param[in] layout Operand data layout
*/
void registerTensorInfo(const ir::OperandIndex &ind, const ir::OperandInfo &info,
ir::Layout backend_layout, bool as_const) override;
/**
* @brief Register subtensor information to allocate on CPU backend
* @param[in] ind Operand index
* @param[in] info Tensor information
*/
void registerSubTensorInfo(const ir::OperandIndex &ind,
const compiler::SubTensorInfo &info) override;
void notifyFirstUse(const ir::OperandIndex &) override;
void notifyLastUse(const ir::OperandIndex &) override;
bool isRegistered(const ir::OperandIndex &) const override;
void prepare(void) override;
void allocateConsts() override;
void allocateNonconsts() override;
void postFunctionPrepare() override { /* DO NOTHING */}
void finalize() override { /* DO NOTHING */}
std::shared_ptr<::neurun::backend::operand::ITensor>
tensorAt(const ir::OperandIndex &ind) override;
void iterate(const IterateFunction &fn) override;
void preVisit(const ir::Operation &) override { /* DO NOTHING */}
void postVisit(const ir::Operation &) override { /* DO NOTHING */}
std::unique_ptr<ITensorManager> releaseTensorManager(void) override;
std::shared_ptr<operand::Tensor> at(const ir::OperandIndex &ind);
private:
std::unique_ptr<TensorManager> _tensor_mgr;
ir::OperandIndexMap<ir::OperandInfo> _tensor_info_map;
ir::OperandIndexSequence _constants;
};
} // namespace cpu
} // namespace backend
} // namespace neurun
#endif // __NEURUN_BACKEND_CPU_TENSOR_BUILDER_H__
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