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/*
* Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
* Copyright (c) 2016-2018 ARM Limited.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __ARM_COMPUTE_CLSPACE_TO_BATCH_ND_H__
#define __ARM_COMPUTE_CLSPACE_TO_BATCH_ND_H__
#include "arm_compute/runtime/CL/ICLSimpleFunction.h"
namespace arm_compute
{
class ICLTensor;
/** Basic function to run @ref CLSpaceToBatchNDKernel
*
* @note The tensor data type for the inputs must be U8/QASYMM8/S16/F16/S32/F32.
* @note The function divides "spatial" dimensions of the input into a grid of blocks of shape
* block_shape, and interleaves these blocks with the "batch" dimension such that in the output.
*/
class CLSpaceToBatchND : public ICLSimpleFunction
{
public:
/** Initialise the kernel's input and output.
*
* @note The data layout of input and output must be the same.
* @note The number of dimensions of input and output must be 4, and `spatial` dimensions
* are height and width.
* @param[in] input Input tensor. Data types supported: U8/QASYMM8/S16/F16/S32/F32.
* Data layout supported: NCHW/NHWC
* @param[in] block_size Tensor of integer values specifying block sizes for spatial
* dimension.
* Data types supported: S32
* @param[in] padding_size Tensor of integer values specifying padding sizes for spatial
* dimension.
* Data types supported: S32
* @param[out] output Output tensor. Data types supported: same as @p input.
* Data layout supported: NCHW/NHWC
*/
void configure(const ICLTensor *input, const ICLTensor *block_size, const ICLTensor *padding_size,
ICLTensor *output);
};
} // namespace arm_compute
#endif /* __ARM_COMPUTE_CLSPACE_TO_BATCH_ND_H__ */
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