1 files changed, 0 insertions, 118 deletions
diff --git a/runtime/neurun/backend/srcn/TensorRegister.cc b/runtime/neurun/backend/srcn/TensorRegister.cc
deleted file mode 100644
index 8c2f59aef..000000000
--- a/runtime/neurun/backend/srcn/TensorRegister.cc
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *      http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "TensorRegister.h"
-
-#include "Convert.h"
-#include "kernel/OperationUtils.h"
-
-namespace neurun
-{
-namespace backend
-{
-namespace srcn
-{
-
-TensorRegister::TensorRegister(const ir::Operands &operands,
-                               const std::shared_ptr<TensorBuilder> &tensor_builder)
-    : _operands{operands}, _tensor_builder{tensor_builder}
-{
-  assert(tensor_builder != nullptr);
-}
-
-void TensorRegister::visit(const ir::operation::Conv2D &node)
-{
-  // General cases
-  defaultRegisterTensorInfo(node.getInputs().at(ir::operation::Conv2D::INPUT));
-  defaultRegisterTensorInfo(node.getInputs().at(ir::operation::Conv2D::BIAS));
-  defaultRegisterTensorInfo(node.getOutputs().at(0));
-
-  // Special case
-  const auto &kernel_index = node.getInputs().at(ir::operation::Conv2D::KERNEL);
-  const auto &kernel_obj = _operands.at(kernel_index);
-
-  const auto frontend_layout = frontendLayout();
-  assert(frontend_layout == ir::Layout::NCHW || frontend_layout == ir::Layout::NHWC);
-  const auto frontend_filter_layout =
-      frontend_layout == ir::Layout::NHWC ? kernel::FilterLayout::OHWI : kernel::FilterLayout::OIHW;
-  const auto backend_layout = backendLayout(kernel_index);
-  assert(backend_layout == ir::Layout::NCHW || backend_layout == ir::Layout::NHWC);
-  const auto backend_filter_layout =
-      backend_layout == ir::Layout::NHWC ? kernel::FilterLayout::HWIO : kernel::FilterLayout::OIHW;
-
-  ir::OperandInfo backend_info{
-      asKernelShape(kernel_obj.shape(), frontend_filter_layout, backend_filter_layout),
-      kernel_obj.info().typeInfo()};
-  _tensor_builder->registerTensorInfo(kernel_index, backend_info, backend_layout,
-                                      kernel_obj.isConstant());
-}
-
-void TensorRegister::visit(const ir::operation::DepthwiseConv2D &node)
-{
-  // General cases
-  defaultRegisterTensorInfo(node.getInputs().at(ir::operation::DepthwiseConv2D::INPUT));
-  defaultRegisterTensorInfo(node.getInputs().at(ir::operation::DepthwiseConv2D::BIAS));
-  defaultRegisterTensorInfo(node.getOutputs().at(0));
-
-  // Special case
-  const auto &kernel_index = node.getInputs().at(ir::operation::DepthwiseConv2D::KERNEL);
-  const auto &kernel_obj = _operands.at(kernel_index);
-
-  const auto frontend_layout = frontendLayout();
-  assert(frontend_layout == ir::Layout::NCHW || frontend_layout == ir::Layout::NHWC);
-  const auto frontend_filter_layout =
-      frontend_layout == ir::Layout::NHWC ? kernel::FilterLayout::OHWI : kernel::FilterLayout::OIHW;
-  const auto backend_layout = backendLayout(kernel_index);
-  assert(backend_layout == ir::Layout::NCHW || backend_layout == ir::Layout::NHWC);
-  const auto backend_filter_layout =
-      backend_layout == ir::Layout::NHWC ? kernel::FilterLayout::HWIO : kernel::FilterLayout::OIHW;
-
-  ir::OperandInfo backend_info{
-      asKernelShape(kernel_obj.shape(), frontend_filter_layout, backend_filter_layout),
-      kernel_obj.info().typeInfo()};
-  _tensor_builder->registerTensorInfo(kernel_index, backend_info, backend_layout,
-                                      kernel_obj.isConstant());
-}
-
-void TensorRegister::visit(const ir::operation::TransposeConv &node)
-{
-  // General cases
-  defaultRegisterTensorInfo(node.getInputs().at(ir::operation::TransposeConv::INPUT));
-  defaultRegisterTensorInfo(node.getOutputs().at(0));
-
-  // Special case
-  const auto &kernel_index = node.getInputs().at(ir::operation::TransposeConv::KERNEL);
-  const auto &kernel_obj = _operands.at(kernel_index);
-
-  const auto frontend_layout = frontendLayout();
-  assert(frontend_layout == ir::Layout::NCHW || frontend_layout == ir::Layout::NHWC);
-  const auto frontend_filter_layout =
-      frontend_layout == ir::Layout::NHWC ? kernel::FilterLayout::OHWI : kernel::FilterLayout::OIHW;
-  const auto backend_layout = backendLayout(kernel_index);
-  assert(backend_layout == ir::Layout::NCHW || backend_layout == ir::Layout::NHWC);
-  const auto backend_filter_layout =
-      backend_layout == ir::Layout::NHWC ? kernel::FilterLayout::HWOI : kernel::FilterLayout::IOHW;
-
-  ir::OperandInfo backend_info{
-      asKernelShape(kernel_obj.shape(), frontend_filter_layout, backend_filter_layout),
-      kernel_obj.info().typeInfo()};
-  _tensor_builder->registerTensorInfo(kernel_index, backend_info, backend_layout,
-                                      kernel_obj.isConstant());
-}
-
-} // namespace srcn
-} // namespace backend
-} // namespace neurun