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Diffstat (limited to 'runtime/neurun/backend/cpu/TensorBuilder.cc')
-rw-r--r-- | runtime/neurun/backend/cpu/TensorBuilder.cc | 104 |
1 files changed, 0 insertions, 104 deletions
diff --git a/runtime/neurun/backend/cpu/TensorBuilder.cc b/runtime/neurun/backend/cpu/TensorBuilder.cc deleted file mode 100644 index 2c654c256..000000000 --- a/runtime/neurun/backend/cpu/TensorBuilder.cc +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "TensorBuilder.h" - -#include <cassert> - -#include "util/logging.h" - -namespace neurun -{ -namespace backend -{ -namespace cpu -{ - -TensorBuilder::TensorBuilder() : _tensor_mgr{new TensorManager()} -{ - // DO NOTHING -} - -void TensorBuilder::registerTensorInfo(const ir::OperandIndex &ind, const ir::OperandInfo &info, - ir::Layout, bool as_const) -{ - _tensor_info_map.emplace(ind, info); - - if (as_const) - _constants.append(ind); -} - -void TensorBuilder::registerSubTensorInfo(const ir::OperandIndex &, const compiler::SubTensorInfo &) -{ - // Not supported yet - assert(false); -} - -void TensorBuilder::notifyFirstUse(const ir::OperandIndex &ind) -{ - assert(_tensor_info_map.find(ind) != _tensor_info_map.end()); - const auto tensor_info = _tensor_info_map.at(ind); - const auto size = tensor_info.total_size(); - _tensor_mgr->buildTensor(ind, tensor_info, _constants.contains(ind)); - _tensor_mgr->claimPlan(ind, size); -} - -void TensorBuilder::notifyLastUse(const ir::OperandIndex &ind) { _tensor_mgr->releasePlan(ind); } - -bool TensorBuilder::isRegistered(const ir::OperandIndex &ind) const -{ - return _tensor_info_map.find(ind) != _tensor_info_map.end(); -} - -void TensorBuilder::prepare(void) -{ - _tensor_mgr->allocateConsts(); - _tensor_mgr->allocateNonconsts(); -} - -void TensorBuilder::allocateConsts() -{ - // NOTE For now nothing to do. Allocation is done in prepare stage, which is not appropriate - // This is because CPU kernels require `ITensor`s to be allocated before Kernel Generation. -} - -void TensorBuilder::allocateNonconsts() -{ - // NOTE For now nothing to do. Allocation is done in prepare stage, which is not appropriate - // This is because CPU kernels require `ITensor`s to be allocated before Kernel Generation. -} - -std::shared_ptr<::neurun::backend::operand::ITensor> -TensorBuilder::tensorAt(const ir::OperandIndex &ind) -{ - return _tensor_mgr->at(ind); -} - -void TensorBuilder::iterate(const IterateFunction &fn) { _tensor_mgr->iterate(fn); } - -std::shared_ptr<operand::Tensor> TensorBuilder::at(const ir::OperandIndex &ind) -{ - return _tensor_mgr->at(ind); -} - -std::unique_ptr<ITensorManager> TensorBuilder::releaseTensorManager(void) -{ - return std::move(_tensor_mgr); -} - -} // namespace cpu -} // namespace backend -} // namespace neurun |