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Diffstat (limited to 'runtime/neurun/backend/cpu/KernelGenerator.cc')
| -rw-r--r-- | runtime/neurun/backend/cpu/KernelGenerator.cc | 624 |
1 files changed, 0 insertions, 624 deletions
diff --git a/runtime/neurun/backend/cpu/KernelGenerator.cc b/runtime/neurun/backend/cpu/KernelGenerator.cc deleted file mode 100644 index 09bd1367d..000000000 --- a/runtime/neurun/backend/cpu/KernelGenerator.cc +++ /dev/null @@ -1,624 +0,0 @@ -/* - * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "KernelGenerator.h" - -#include <stdexcept> - -#include "cpp14/memory.h" -#include "util/Padding.h" -#include "kernel/OperationUtils.h" -#include "kernel/ConvolutionLayer.h" -#include "kernel/AvgPoolLayer.h" -#include "kernel/MaxPoolLayer.h" -#include "kernel/ConcatLayer.h" -#include "kernel/FullyConnectedLayer.h" -#include "kernel/ReshapeLayer.h" -#include "kernel/SoftMaxLayer.h" -#include "kernel/PermuteLayer.h" -#include "kernel/DepthwiseConvolutionLayer.h" -#include "kernel/AddLayer.h" -#include "kernel/SubLayer.h" -#include "kernel/MulLayer.h" -#include "kernel/GatherLayer.h" -#include "kernel/LogisticLayer.h" -#include "kernel/PadLayer.h" - -#include <backend/Backend.h> -#include <backend/IConfig.h> - -#include "util/logging.h" - -#include "util/Utils.h" - -namespace neurun -{ -namespace backend -{ -namespace cpu -{ - -KernelGenerator::KernelGenerator( - const ir::Operands &operand_ctx, const std::shared_ptr<TensorBuilder> &tensor_builder, - const std::shared_ptr<backend::custom::IKernelBuilder> &kernel_builer) - : _ctx(operand_ctx), _tensor_builder(tensor_builder), _kernel_builder(kernel_builer), - _current_subg_layout(ir::Layout::UNKNOWN) -{ - // DO NOTHING -} - -void KernelGenerator::visit(const ir::OpSequence &op_seq) -{ - _current_subg_layout = op_seq.getLayout(); - for (const auto &e : op_seq.operations()) - { - const auto &node = *(e.node); - _tensor_builder->preVisit(node); - node.accept(*this); - _tensor_builder->postVisit(node); - } -} - -void KernelGenerator::visit(const ir::operation::Conv2D &node) -{ - using ir::operation::Conv2D; - - const auto ofm_index{node.getOutputs().at(0)}; - const auto ifm_index{node.getInputs().at(Conv2D::Input::INPUT)}; - const auto ker_index{node.getInputs().at(Conv2D::Input::KERNEL)}; - const auto bias_index{node.getInputs().at(Conv2D::Input::BIAS)}; - - const auto stride = node.param().stride; - const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature(_current_subg_layout); - const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature(_current_subg_layout); - // Kernel format is [depth_out, kernel_height, kernel_width, depth_in]. - const auto &ker_shape = _ctx.at(ker_index).shape(); - const auto ker_height = ker_shape.dim(1); - const auto ker_width = ker_shape.dim(2); - const auto padding = neurun::util::calculatePadding(node.param().padding, ifm_shape, ofm_shape, - stride, ker_width, ker_height); - const auto activation = node.param().activation; - - const auto ofm_backend_descr = - ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(ofm_index), _current_subg_layout); - const auto ifm_backend_descr = - ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(ifm_index), _current_subg_layout); - const auto ker_backend_descr = - ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(ker_index), ir::Layout::UNKNOWN); - const auto bias_backend_descr = - ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(bias_index), ir::Layout::UNKNOWN); - - auto ofm_alloc = _tensor_builder->at(ofm_index); - auto ifm_alloc = _tensor_builder->at(ifm_index); - auto ker_alloc = _tensor_builder->at(ker_index); - auto bias_alloc = _tensor_builder->at(bias_index); - - auto fn = nnfw::cpp14::make_unique<::neurun::backend::cpu::kernel::ConvolutionLayer>(); - - fn->configure(ifm_alloc->buffer(), ifm_backend_descr, ker_alloc->buffer(), ker_backend_descr, - bias_alloc->buffer(), bias_backend_descr, padding.left, padding.right, padding.top, - padding.bottom, stride.horizontal, stride.vertical, activation, ofm_alloc->buffer(), - ofm_backend_descr); - - _execution_builder->append(std::move(fn)); -} - -void KernelGenerator::visit(const ir::operation::DepthwiseConv2D &node) -{ - using ir::operation::DepthwiseConv2D; - - const auto ofm_index{node.getOutputs().at(0)}; - const auto ifm_index{node.getInputs().at(DepthwiseConv2D::Input::INPUT)}; - const auto ker_index{node.getInputs().at(DepthwiseConv2D::Input::KERNEL)}; - const auto bias_index{node.getInputs().at(DepthwiseConv2D::Input::BIAS)}; - - const auto stride = node.param().stride; - const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature(_current_subg_layout); - const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature(_current_subg_layout); - // Kernel format is [1, kernel_height, kernel_width, depth_out]. - const auto &ker_shape = _ctx.at(ker_index).shape(); - const auto ker_height = ker_shape.dim(1); - const auto ker_width = ker_shape.dim(2); - const auto padding = neurun::util::calculatePadding(node.param().padding, ifm_shape, ofm_shape, - stride, ker_width, ker_height); - - const auto ofm_backend_descr = - ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(ofm_index), _current_subg_layout); - const auto ifm_backend_descr = - ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(ifm_index), _current_subg_layout); - const auto ker_backend_descr = - ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(ker_index), ir::Layout::UNKNOWN); - const auto bias_backend_descr = - ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(bias_index), ir::Layout::UNKNOWN); - - const auto multiplier = node.param().multiplier; - const auto activation = node.param().activation; - - auto ofm_alloc = _tensor_builder->at(ofm_index); - auto ifm_alloc = _tensor_builder->at(ifm_index); - auto ker_alloc = _tensor_builder->at(ker_index); - auto bias_alloc = _tensor_builder->at(bias_index); - - auto fn = nnfw::cpp14::make_unique<::neurun::backend::cpu::kernel::DepthwiseConvolutionLayer>(); - - fn->configure(ifm_alloc->buffer(), ifm_backend_descr, ker_alloc->buffer(), ker_backend_descr, - bias_alloc->buffer(), bias_backend_descr, padding.left, padding.right, padding.top, - padding.bottom, stride.horizontal, stride.vertical, multiplier, activation, - ofm_alloc->buffer(), ofm_backend_descr); - - _execution_builder->append(std::move(fn)); -} - -void KernelGenerator::visit(const ir::operation::MaxPool2D &node) -{ - const auto ofm_index{node.getOutputs().at(0)}; - const auto ifm_index{node.getInputs().at(ir::operation::MaxPool2D::Input::INPUT)}; - - const auto kh = node.param().kh; - const auto kw = node.param().kw; - - const auto stride = node.param().stride; - const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature(_current_subg_layout); - const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature(_current_subg_layout); - const auto padding = - neurun::util::calculatePadding(node.param().padding, ifm_shape, ofm_shape, stride, kw, kh); - const auto activation = node.param().activation; - - const auto ofm_backend_descr = - ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(ofm_index), _current_subg_layout); - const auto ifm_backend_descr = - ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(ifm_index), _current_subg_layout); - - auto ofm_alloc = _tensor_builder->at(ofm_index).get(); - auto ifm_alloc = _tensor_builder->at(ifm_index).get(); - - auto fn = nnfw::cpp14::make_unique<::neurun::backend::cpu::kernel::MaxPoolLayer>(); - - fn->configure(ifm_alloc->buffer(), ifm_backend_descr, padding.left, padding.right, padding.top, - padding.bottom, stride.horizontal, stride.vertical, kw, kh, activation, - ofm_alloc->buffer(), ofm_backend_descr); - - _execution_builder->append(std::move(fn)); -} - -void KernelGenerator::visit(const ir::operation::AvgPool2D &node) -{ - const auto ofm_index{node.getOutputs().at(0)}; - const auto ifm_index{node.getInputs().at(ir::operation::AvgPool2D::Input::INPUT)}; - - const auto kh = node.param().kh; - const auto kw = node.param().kw; - const auto stride = node.param().stride; - const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature(_current_subg_layout); - const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature(_current_subg_layout); - const auto padding = - neurun::util::calculatePadding(node.param().padding, ifm_shape, ofm_shape, stride, kw, kh); - const auto activation = node.param().activation; - - const auto ofm_backend_descr = - ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(ofm_index), _current_subg_layout); - const auto ifm_backend_descr = - ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(ifm_index), _current_subg_layout); - - auto ofm_alloc = _tensor_builder->at(ofm_index).get(); - auto ifm_alloc = _tensor_builder->at(ifm_index).get(); - - auto fn = nnfw::cpp14::make_unique<::neurun::backend::cpu::kernel::AvgPoolLayer>(); - - fn->configure(ifm_alloc->buffer(), ifm_backend_descr, padding.left, padding.right, padding.top, - padding.bottom, stride.horizontal, stride.vertical, kw, kh, activation, - ofm_alloc->buffer(), ofm_backend_descr); - - _execution_builder->append(std::move(fn)); -} - -void KernelGenerator::visit(const ir::operation::Concat &node) -{ - const auto ofm_index{node.getOutputs().at(0)}; - - const auto rank = _ctx.at(ofm_index).shape().rank(); - const auto axis = - ::neurun::backend::cpu::kernel::getAxis(rank, node.param().axis, _current_subg_layout); - - const auto ofm_backend_descr = - ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(ofm_index), _current_subg_layout); - std::vector<::neurun::backend::cpu::kernel::TensorDescriptor> ifm_backend_descrs; - for (auto &in_idx : node.getInputs()) - ifm_backend_descrs.emplace_back( - ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(in_idx), _current_subg_layout)); - - auto output_alloc = _tensor_builder->at(ofm_index).get(); - - std::vector<const uint8_t *> input_buffers; - for (auto &ifm_idx : node.getInputs()) - input_buffers.emplace_back(_tensor_builder->at(ifm_idx).get()->buffer()); - - auto fn = nnfw::cpp14::make_unique<::neurun::backend::cpu::kernel::ConcatLayer>(); - - fn->configure(input_buffers, ifm_backend_descrs, axis, output_alloc->buffer(), ofm_backend_descr); - - _execution_builder->append(std::move(fn)); -} - -void KernelGenerator::visit(const ir::operation::FullyConnected &node) -{ - using ir::operation::FullyConnected; - - const auto output_index{node.getOutputs().at(0)}; - const auto input_index{node.getInputs().at(FullyConnected::Input::INPUT)}; - const auto weight_index{node.getInputs().at(FullyConnected::Input::WEIGHT)}; - const auto bias_index{node.getInputs().at(FullyConnected::Input::BIAS)}; - - const auto ofm_backend_descr = ::neurun::backend::cpu::kernel::getTensorDescriptor( - _ctx.at(output_index), _current_subg_layout); - const auto ifm_backend_descr = ::neurun::backend::cpu::kernel::getTensorDescriptor( - _ctx.at(input_index), _current_subg_layout); - const auto weight_backend_descr = ::neurun::backend::cpu::kernel::getTensorDescriptor( - _ctx.at(weight_index), ir::Layout::UNKNOWN); - const auto bias_backend_descr = - ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(bias_index), ir::Layout::UNKNOWN); - - const auto activation = node.param().activation; - - auto output_alloc = _tensor_builder->at(output_index).get(); - auto input_alloc = _tensor_builder->at(input_index).get(); - auto weight_alloc = _tensor_builder->at(weight_index).get(); - auto bias_alloc = _tensor_builder->at(bias_index).get(); - - auto fn = nnfw::cpp14::make_unique<::neurun::backend::cpu::kernel::FullyConnectedLayer>(); - - fn->configure(input_alloc->buffer(), ifm_backend_descr, weight_alloc->buffer(), - weight_backend_descr, bias_alloc->buffer(), bias_backend_descr, activation, - output_alloc->buffer(), ofm_backend_descr); - - _execution_builder->append(std::move(fn)); -} - -void KernelGenerator::visit(const ir::operation::Reshape &node) -{ - const auto output_index{node.getOutputs().at(0)}; - const auto input_index{node.getInputs().at(ir::operation::Reshape::Input::INPUT)}; - - const auto ofm_backend_descr = ::neurun::backend::cpu::kernel::getTensorDescriptor( - _ctx.at(output_index), _current_subg_layout); - const auto ifm_backend_descr = ::neurun::backend::cpu::kernel::getTensorDescriptor( - _ctx.at(input_index), _current_subg_layout); - - auto output_alloc = _tensor_builder->at(output_index).get(); - auto input_alloc = _tensor_builder->at(input_index).get(); - - auto fn = nnfw::cpp14::make_unique<::neurun::backend::cpu::kernel::ReshapeLayer>(); - - fn->configure(input_alloc->buffer(), ifm_backend_descr, output_alloc->buffer(), - ofm_backend_descr); - - _execution_builder->append(std::move(fn)); -} - -void KernelGenerator::visit(const ir::operation::Squeeze &node) -{ - const auto output_index{node.getOutputs().at(0)}; - const auto input_index{node.getInputs().at(ir::operation::Squeeze::Input::INPUT)}; - - const auto ofm_backend_descr = ::neurun::backend::cpu::kernel::getTensorDescriptor( - _ctx.at(output_index), _current_subg_layout); - const auto ifm_backend_descr = ::neurun::backend::cpu::kernel::getTensorDescriptor( - _ctx.at(input_index), _current_subg_layout); - - auto output_alloc = _tensor_builder->at(output_index).get(); - auto input_alloc = _tensor_builder->at(input_index).get(); - - // Squeeze can share same kernel with reshape - auto fn = nnfw::cpp14::make_unique<::neurun::backend::cpu::kernel::ReshapeLayer>(); - - fn->configure(input_alloc->buffer(), ifm_backend_descr, output_alloc->buffer(), - ofm_backend_descr); - - _execution_builder->append(std::move(fn)); -} - -void KernelGenerator::visit(const ir::operation::Softmax &node) -{ - const auto output_index{node.getOutputs().at(0)}; - const auto input_index{node.getInputs().at(ir::operation::Softmax::Input::INPUT)}; - - const auto ofm_backend_descr = ::neurun::backend::cpu::kernel::getTensorDescriptor( - _ctx.at(output_index), _current_subg_layout); - const auto ifm_backend_descr = ::neurun::backend::cpu::kernel::getTensorDescriptor( - _ctx.at(input_index), _current_subg_layout); - - const auto beta = node.param().beta; - - auto output_alloc = _tensor_builder->at(output_index).get(); - auto input_alloc = _tensor_builder->at(input_index).get(); - - auto fn = nnfw::cpp14::make_unique<::neurun::backend::cpu::kernel::SoftMaxLayer>(); - - fn->configure(input_alloc->buffer(), ifm_backend_descr, beta, output_alloc->buffer(), - ofm_backend_descr); - - _execution_builder->append(std::move(fn)); -} - -void KernelGenerator::visit(const ir::operation::Add &node) -{ - const auto ofm_index{node.getOutputs().at(0)}; - const auto lhs_index{node.getInputs().at(ir::operation::Add::Input::LHS)}; - const auto rhs_index{node.getInputs().at(ir::operation::Add::Input::RHS)}; - - const auto ofm_backend_descr = - ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(ofm_index), _current_subg_layout); - const auto lhs_backend_descr = - ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(lhs_index), _current_subg_layout); - const auto rhs_backend_descr = - ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(rhs_index), _current_subg_layout); - - const auto activation = node.param().activation; - - auto ofm_alloc = _tensor_builder->at(ofm_index).get(); - auto lhs_alloc = _tensor_builder->at(lhs_index).get(); - auto rhs_alloc = _tensor_builder->at(rhs_index).get(); - - auto fn = nnfw::cpp14::make_unique<::neurun::backend::cpu::kernel::AddLayer>(); - - fn->configure(lhs_alloc->buffer(), lhs_backend_descr, rhs_alloc->buffer(), rhs_backend_descr, - activation, ofm_alloc->buffer(), ofm_backend_descr); - - _execution_builder->append(std::move(fn)); -} - -void KernelGenerator::visit(const ir::operation::Gather &node) -{ - const auto output_index{node.getOutputs().at(0)}; - const auto input_index{node.getInputs().at(ir::operation::Gather::Input::INPUT)}; - const auto indices_index{node.getInputs().at(ir::operation::Gather::Input::INDICES)}; - - const auto output_backend_descr = ::neurun::backend::cpu::kernel::getTensorDescriptor( - _ctx.at(output_index), _current_subg_layout); - const auto input_backend_descr = ::neurun::backend::cpu::kernel::getTensorDescriptor( - _ctx.at(input_index), _current_subg_layout); - const auto indices_backend_descr = ::neurun::backend::cpu::kernel::getTensorDescriptor( - _ctx.at(indices_index), _current_subg_layout); - - auto output_alloc = _tensor_builder->at(output_index).get(); - auto input_alloc = _tensor_builder->at(input_index).get(); - auto indices_alloc = _tensor_builder->at(indices_index).get(); - - const auto backend_layout = output_alloc->layout(); - UNUSED_RELEASE(backend_layout); - - // NOTE The frontend layout and backend layout must be the same for this operation. - // If not the same, we have to add a stage(?) to perform permutation of output tensor. It - // is not not efficient even if it works well. If so, it would be better to set the - // layout of these backend tensors to the same layout. - // There is also one thing we have to think about. This operation depends on the layout of - // a model. For example, if a model in NHWC has this operation as output rank == 4, indices - // rank == 2 and axis == 2, this operation should work as the axis W and C, but the axis W - // and C are not sequential in NCHW. So the backend in NCHW cannot handle this case. - assert(backend_layout == input_alloc->layout()); - assert(backend_layout == indices_alloc->layout()); - const auto &input_shape = _ctx.at(input_index).shape(); - UNUSED_RELEASE(input_shape); - assert(input_shape.rank() < 4 || _current_subg_layout == backend_layout); - - const auto axis_raw = node.param().axis; - const auto axis_value = (axis_raw < 0 ? (input_shape.rank() + axis_raw) : axis_raw); - - auto fn = nnfw::cpp14::make_unique<::neurun::backend::cpu::kernel::GatherLayer>(); - - fn->configure(input_alloc->buffer(), input_backend_descr, indices_alloc->buffer(), - indices_backend_descr, output_alloc->buffer(), output_backend_descr, axis_value); - - _execution_builder->append(std::move(fn)); -} - -void KernelGenerator::visit(const ir::operation::Sub &node) -{ - // The same as Add - const auto ofm_index{node.getOutputs().at(0)}; - const auto lhs_index{node.getInputs().at(ir::operation::Sub::Input::LHS)}; - const auto rhs_index{node.getInputs().at(ir::operation::Sub::Input::RHS)}; - - const auto ofm_backend_descr = - ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(ofm_index), _current_subg_layout); - const auto lhs_backend_descr = - ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(lhs_index), _current_subg_layout); - const auto rhs_backend_descr = - ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(rhs_index), _current_subg_layout); - - const auto activation = node.param().activation; - - auto ofm_alloc = _tensor_builder->at(ofm_index).get(); - auto lhs_alloc = _tensor_builder->at(lhs_index).get(); - auto rhs_alloc = _tensor_builder->at(rhs_index).get(); - - auto fn = nnfw::cpp14::make_unique<::neurun::backend::cpu::kernel::SubLayer>(); - - fn->configure(lhs_alloc->buffer(), lhs_backend_descr, rhs_alloc->buffer(), rhs_backend_descr, - activation, ofm_alloc->buffer(), ofm_backend_descr); - - _execution_builder->append(std::move(fn)); -} - -void KernelGenerator::visit(const ir::operation::Mul &node) -{ - // The same as Add - const auto ofm_index{node.getOutputs().at(0)}; - const auto lhs_index{node.getInputs().at(ir::operation::Sub::Input::LHS)}; - const auto rhs_index{node.getInputs().at(ir::operation::Sub::Input::RHS)}; - - const auto ofm_backend_descr = - ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(ofm_index), _current_subg_layout); - const auto lhs_backend_descr = - ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(lhs_index), _current_subg_layout); - const auto rhs_backend_descr = - ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(rhs_index), _current_subg_layout); - - const auto activation = node.param().activation; - - auto ofm_alloc = _tensor_builder->at(ofm_index).get(); - auto lhs_alloc = _tensor_builder->at(lhs_index).get(); - auto rhs_alloc = _tensor_builder->at(rhs_index).get(); - - auto fn = nnfw::cpp14::make_unique<::neurun::backend::cpu::kernel::MulLayer>(); - - fn->configure(lhs_alloc->buffer(), lhs_backend_descr, rhs_alloc->buffer(), rhs_backend_descr, - activation, ofm_alloc->buffer(), ofm_backend_descr); - - _execution_builder->append(std::move(fn)); -} - -void KernelGenerator::visit(const ir::operation::Permute &node) -{ - const auto output_index{node.getOutputs().at(0)}; - const auto input_index{node.getInputs().at(0)}; - - const auto &shape = _ctx.at(output_index).shape(); - const auto input_backend_ctx = node.param().input_backend_ctx; - const auto output_backend_ctx = node.param().output_backend_ctx; - const auto data_type = node.getDataType(); - - output_backend_ctx->tensor_builder->preVisit(node); - - auto output_object = output_backend_ctx->tensor_builder->tensorAt(output_index); - auto input_object = input_backend_ctx->tensor_builder->tensorAt(input_index); - - auto fn = nnfw::cpp14::make_unique<::neurun::backend::cpu::kernel::PermuteLayer>(); - - // TODO Support NCHW frontend - auto out_shape = shape; - if (shape.rank() == 4 && output_object->layout() == ir::Layout::NCHW) - { - out_shape.dim(1) = shape.dim(3); - out_shape.dim(2) = shape.dim(1); - out_shape.dim(3) = shape.dim(2); - } - - const auto permute_type = node.getPermuteType(); - // Check Permutation Type - const auto inferPermuteType = [&]() { - if (input_object->layout() == ir::Layout::NHWC && output_object->layout() == ir::Layout::NCHW) - { - return ir::operation::Permute::Type::NHWC_TO_NCHW; - } - else if (input_object->layout() == ir::Layout::NCHW && - output_object->layout() == ir::Layout::NHWC) - { - return ir::operation::Permute::Type::NCHW_TO_NHWC; - } - else - { - return ir::operation::Permute::Type::COPY; - } - }(); - UNUSED_RELEASE(inferPermuteType); - assert(permute_type == inferPermuteType); - - fn->configure(input_object, output_object, out_shape, permute_type, data_type); - - input_backend_ctx->tensor_builder->postVisit(node); - - _execution_builder->append(std::move(fn)); -} - -void KernelGenerator::visit(const ir::operation::Custom &node) -{ - auto get_type_info = [this](const ir::Operand &operand) -> custom::TypeInfo { - auto backendDescr = - ::neurun::backend::cpu::kernel::getTensorDescriptor(operand, _current_subg_layout); - - custom::Shape shape(backendDescr.dimensions.size()); - for (size_t d = 0; d < backendDescr.dimensions.size(); ++d) - { - shape.dim(d) = backendDescr.dimensions[d]; - } - - return {shape, backendDescr.type}; - }; - - auto fill_op_info = [&](const ir::OperandIndexSequence &opSeq, - std::vector<custom::TypeInfo> &types, std::vector<void *> &allocs) { - for (auto &idx : opSeq) - { - const auto &operand = _ctx.at(idx); - // TODO make sure using `_current_subg_layout` is correct for custom operations - types.emplace_back(get_type_info(operand)); - auto in_alloc = _tensor_builder->at(idx)->buffer(); - allocs.emplace_back(in_alloc); - } - }; - - backend::custom::CustomKernelConfigParams params{}; - - fill_op_info(node.getInputs(), params.input_types, params.input_allocations); - fill_op_info(node.getOutputs(), params.output_types, params.output_allocations); - - params.userdata = node.userdata().data; - params.userdata_size = node.userdata().size; - - auto fn = _kernel_builder->buildKernel(node.id(), std::move(params)); - - _execution_builder->append(std::move(fn)); -} - -void KernelGenerator::visit(const ir::operation::Logistic &node) -{ - const auto output_index{node.getOutputs().at(0)}; - const auto input_index{node.getInputs().at(ir::operation::Logistic::Input::INPUT)}; - - const auto ofm_backend_descr = ::neurun::backend::cpu::kernel::getTensorDescriptor( - _ctx.at(output_index), _current_subg_layout); - const auto ifm_backend_descr = ::neurun::backend::cpu::kernel::getTensorDescriptor( - _ctx.at(input_index), _current_subg_layout); - - auto output_alloc = _tensor_builder->at(output_index).get(); - auto input_alloc = _tensor_builder->at(input_index).get(); - - auto fn = nnfw::cpp14::make_unique<::neurun::backend::cpu::kernel::LogisticLayer>(); - - fn->configure(input_alloc->buffer(), ifm_backend_descr, output_alloc->buffer(), - ofm_backend_descr); - - _execution_builder->append(std::move(fn)); -} - -void KernelGenerator::visit(const ir::operation::Pad &node) -{ - const auto input_index{node.getInputs().at(ir::operation::Pad::Input::INPUT)}; - const auto pad_index{node.getInputs().at(ir::operation::Pad::Input::PAD)}; - const auto output_index{node.getOutputs().at(0)}; - assert(_ctx.at(pad_index).isConstant()); - - auto input = _tensor_builder->at(input_index).get(); - auto output = _tensor_builder->at(output_index).get(); - auto pad_rank = _ctx.at(pad_index).shape().dim(0); - auto pad_base = reinterpret_cast<const int32_t *>(_ctx.at(pad_index).data().base()); - const auto ofm_backend_descr = ::neurun::backend::cpu::kernel::getTensorDescriptor( - _ctx.at(output_index), _current_subg_layout); - const auto ifm_backend_descr = ::neurun::backend::cpu::kernel::getTensorDescriptor( - _ctx.at(input_index), _current_subg_layout); - - auto fn = nnfw::cpp14::make_unique<::neurun::backend::cpu::kernel::PadLayer>(); - - fn->configure(input->buffer(), ifm_backend_descr, output->buffer(), ofm_backend_descr, pad_base, - pad_rank); - - _execution_builder->append(std::move(fn)); -} - -} // namespace cpu -} // namespace backend -} // namespace neurun |