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author | Chunseok Lee <chunseok.lee@samsung.com> | 2020-03-05 15:10:09 +0900 |
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committer | Chunseok Lee <chunseok.lee@samsung.com> | 2020-03-05 15:22:53 +0900 |
commit | d91a039e0eda6fd70dcd22672b8ce1817c1ca50e (patch) | |
tree | 62668ec548cf31fadbbf4e99522999ad13434a25 /runtimes/neurun/backend/acl_common/IACLTensor.h | |
parent | bd11b24234d7d43dfe05a81c520aa01ffad06e42 (diff) | |
download | nnfw-d91a039e0eda6fd70dcd22672b8ce1817c1ca50e.tar.gz nnfw-d91a039e0eda6fd70dcd22672b8ce1817c1ca50e.tar.bz2 nnfw-d91a039e0eda6fd70dcd22672b8ce1817c1ca50e.zip |
catch up to tizen_5.5 and remove unness dir
- update to tizen_5.5
- remove dirs
Diffstat (limited to 'runtimes/neurun/backend/acl_common/IACLTensor.h')
-rw-r--r-- | runtimes/neurun/backend/acl_common/IACLTensor.h | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/runtimes/neurun/backend/acl_common/IACLTensor.h b/runtimes/neurun/backend/acl_common/IACLTensor.h new file mode 100644 index 000000000..1dc79f480 --- /dev/null +++ b/runtimes/neurun/backend/acl_common/IACLTensor.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __NEURUN_BACKEND_ACL_COMMON_I_ACL_TENSOR_H__ +#define __NEURUN_BACKEND_ACL_COMMON_I_ACL_TENSOR_H__ + +#include <backend/operand/ITensor.h> +#include <arm_compute/core/ITensor.h> + +namespace neurun +{ +namespace backend +{ +namespace acl_common +{ + +class IACLTensor : public operand::ITensor +{ +public: + IACLTensor() = default; + IACLTensor(const IACLTensor &) = delete; + IACLTensor &operator=(const IACLTensor &) = delete; + IACLTensor(IACLTensor &&) = default; + IACLTensor &operator=(IACLTensor &&) = default; + +public: + uint8_t *buffer() const final { return handle()->buffer(); } + size_t total_size() const final { return info()->total_size(); } + size_t dimension(size_t index) const final; + size_t num_dimensions() const override; + size_t calcOffset(const neurun::util::Coordinates &coords) const final; + model::Layout layout() const final; + bool has_padding() const override { return info()->has_padding(); } + +public: + virtual const arm_compute::ITensor *handle() const = 0; + virtual arm_compute::ITensor *handle() = 0; + + const arm_compute::ITensorInfo *info() const { return handle()->info(); } + arm_compute::ITensorInfo *info() { return handle()->info(); } + + arm_compute::DataType data_type() const { return info()->data_type(); } +}; + +} // namespace acl_common +} // namespace backend +} // namespace neurun + +#endif //__NEURUN_BACKEND_ACL_COMMON_I_ACL_TENSOR_H__ |