Imported Upstream version 1.1.0upstream/1.1.0submit/tizen/20200304.094649submit/tizen/20200304.093946submit/tizen/20200304.092919accepted/tizen/unified/20200305.051107

997 files changed, 134295 insertions, 0 deletions

diff --git a/runtime/CMakeLists.txt b/runtime/CMakeLists.txt
new file mode 100644
index 000000000..5ea6cdadd
--- /dev/null
+++ b/runtime/CMakeLists.txt
@@ -0,0 +1 @@
+add_subdirectories()
diff --git a/runtime/contrib/CMakeLists.txt b/runtime/contrib/CMakeLists.txt
new file mode 100644
index 000000000..5ea6cdadd
--- /dev/null
+++ b/runtime/contrib/CMakeLists.txt
@@ -0,0 +1 @@
+add_subdirectories()
diff --git a/runtime/contrib/README.md b/runtime/contrib/README.md
new file mode 100644
index 000000000..2f8b709eb
--- /dev/null
+++ b/runtime/contrib/README.md
@@ -0,0 +1,10 @@
+# nnfw contrib
+
+The `contrib` directory is basically a contribution channel where contributors can create a project
+and start the code development.  The projects in the `contrib` directory may not be directly related
+to `nnfw` but should have its own purpose that could augment the nnfw project.
+
+If you are interested in proposing a new project, please create a pull request (PR) with a new
+project directory under `contrib` including the description of proposing project.  The PR will be
+reviewed by reviewers in `nnfw`, and the acceptance of new project will be determined based on the
+PR reviews.
diff --git a/runtime/contrib/TFLiteSharp/README.md b/runtime/contrib/TFLiteSharp/README.md
new file mode 100644
index 000000000..8e43be618
--- /dev/null
+++ b/runtime/contrib/TFLiteSharp/README.md
@@ -0,0 +1,92 @@
+# C-Sharp TFLite API Directory structure
+```
+.
+├── packaging
+│   ├── TFLiteSharp.manifest
+│   └── TFLiteSharp.spec
+├── README.md
+├── TFLiteNative
+│   ├── CMakeLists.txt
+│   ├── include
+│   │   ├── tflite_log.h
+│   │   └── tflite_nativewrapper.h
+│   ├── src
+│   │   └── tflite_nativewrapper.cpp
+│   └── tflite-native.pc.in
+├── TFLiteSharp
+│   ├── TFLiteSharp
+│   │   ├── src
+│   │   │   └── Interpreter.cs
+│   │   └── TFLiteSharp.csproj
+│   └── TFLiteSharp.sln
+└── TFLiteSharpTest
+    ├── TFLiteSharpTest
+    │   ├── Program.cs
+    │   └── TFLiteSharpTest.csproj
+    └── TFLiteSharpTest.sln
+```
+
+# Build C-Sharp TFLite
+gbs should be used to build TFLiteSharp package. nnfw is also built by gbs. As in most cases when building nnfw we won't intend to build TFLiteSharp hence we have separated its build process, so in order to build TFLiteSharp below command is needed:
+```
+nnfw$ gbs build --packaging-dir=contrib/TFLiteSharp/packaging/ --spec=TFLiteSharp.spec -A armv7l
+```
+This will first build the TFLiteNative package containing native c++ bindings between c# api and tflite api
+and then it will build TFLiteSharp(c# api package).
+
+Please use gbs.conf file corresponding to tizen image version. In most cases gbs.conf file should be same as the one which is used to build nnfw.
+# C-Sharp TFLite API list
+
+## Interpreter Class
+
+### Constructor
+
+The `Interpreter.cs` class drives model inference with TensorFlow Lite.
+
+#### Initializing an `Interpreter` With a Model File
+
+The `Interpreter` can be initialized with a model file using the constructor:
+
+```c#
+public Interpreter(string modelFile);
+```
+
+Number of threads available to the interpereter can be set by using the following function:
+```c#
+public void SetNumThreads(int num_threads)
+```
+
+### Running a model
+
+If a model takes only one input and returns only one output, the following will trigger an inference run:
+
+```c#
+interpreter.Run(input, output);
+```
+
+For models with multiple inputs, or multiple outputs, use:
+
+```c#
+interpreter.RunForMultipleInputsOutputs(inputs, map_of_indices_to_outputs);
+```
+
+The C# api also provides functions for getting the model's input and output indices given the name of tensors as input:
+
+```c#
+public int GetInputIndex(String tensorName)
+public int GetOutputIndex(String tensorName)
+```
+
+Developer can also enable or disable the use of NN API based on hardware capabilites:
+```c#
+public void SetUseNNAPI(boolean useNNAPI)
+```
+
+### Releasing Resources After Use
+
+An `Interpreter` owns resources. To avoid memory leak, the resources must be
+released after use by:
+
+```c#
+interpreter.Dispose();
+```
diff --git a/runtime/contrib/TFLiteSharp/TFLiteNative/CMakeLists.txt b/runtime/contrib/TFLiteSharp/TFLiteNative/CMakeLists.txt
new file mode 100644
index 000000000..8b58aac9c
--- /dev/null
+++ b/runtime/contrib/TFLiteSharp/TFLiteNative/CMakeLists.txt
@@ -0,0 +1,67 @@
+CMAKE_MINIMUM_REQUIRED(VERSION 2.6)
+SET(fw_name "tflite-native")
+
+PROJECT(${fw_name})
+SET(PREFIX ${CMAKE_INSTALL_PREFIX})
+SET(LIB ${LIB_PATH})
+SET(LIBDIR ${PREFIX}/${LIB_PATH})
+
+SET(INC_DIR include)
+INCLUDE_DIRECTORIES(${INC_DIR})
+
+INCLUDE(FindPkgConfig)
+
+SET(COMMON_DEPS "tensorflow-lite")
+SET(PC_DEPS "capi-base-common")
+
+IF (TIZEN)
+	MESSAGE("Building for Tizen")
+	SET(TIZEN_DEPS "dlog")
+	PKG_CHECK_MODULES(${fw_name} REQUIRED ${COMMON_DEPS} ${TIZEN_DEPS})
+	ADD_DEFINITIONS("-D__TIZEN__")
+ELSE ()
+	MESSAGE("Building for Linux")
+	PKG_CHECK_MODULES(${fw_name} REQUIRED ${COMMON_DEPS})
+ENDIF ()
+
+FOREACH(flag ${${fw_name}_CFLAGS})
+    SET(EXTRA_CFLAGS "${EXTRA_CFLAGS} ${flag}")
+ENDFOREACH(flag)
+
+SET(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${EXTRA_CXXFLAGS} -fPIC -Wall -Werror")
+SET(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${EXTRA_CFLAGS} -fPIC -Wall")
+SET(CMAKE_C_FLAGS_DEBUG "-O0 -g")
+
+ADD_DEFINITIONS("-DPREFIX=\"${CMAKE_INSTALL_PREFIX}\"")
+
+SET(CMAKE_EXE_LINKER_FLAGS "-Wl,--as-needed -Wl,--rpath=${LIBDIR}")
+
+aux_source_directory(src SOURCES)
+ADD_LIBRARY(${fw_name} SHARED ${SOURCES})
+
+TARGET_LINK_LIBRARIES(${fw_name} ${${fw_name}_LDFLAGS})
+
+SET_TARGET_PROPERTIES(${fw_name}
+     PROPERTIES
+     VERSION ${FULLVER}
+     SOVERSION ${MAJORVER}
+     CLEAN_DIRECT_OUTPUT 1
+)
+
+INSTALL(TARGETS ${fw_name} DESTINATION ${LIB})
+INSTALL(
+        DIRECTORY ${INC_DIR}/ DESTINATION include/
+        FILES_MATCHING
+        PATTERN "${INC_DIR}/*.h"
+        )
+
+SET(PC_NAME ${fw_name})
+SET(PC_REQUIRED ${pc_dependents})
+SET(PC_LDFLAGS -l${fw_name})
+
+CONFIGURE_FILE(
+    ${fw_name}.pc.in
+    ${CMAKE_CURRENT_SOURCE_DIR}/${fw_name}.pc
+    @ONLY
+)
+INSTALL(FILES ${CMAKE_CURRENT_SOURCE_DIR}/${fw_name}.pc DESTINATION ${LIB}/pkgconfig)
diff --git a/runtime/contrib/TFLiteSharp/TFLiteNative/include/tflite_log.h b/runtime/contrib/TFLiteSharp/TFLiteNative/include/tflite_log.h
new file mode 100644
index 000000000..405ca9879
--- /dev/null
+++ b/runtime/contrib/TFLiteSharp/TFLiteNative/include/tflite_log.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the License);
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _TFLITE_LOG_H_
+#define _TFLITE_LOG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /*__cplusplus*/
+
+#define ERROR 1
+#define WARNING 2
+#define INFO 3
+#define DEBUG 4
+
+#ifdef __TIZEN__
+#include <dlog/dlog.h>
+#ifdef LOG_TAG
+#undef LOG_TAG
+#endif // LOG_TAG
+#define LOG_TAG "TFLITE_NATIVE"
+
+#define TFLITE_NATIVE_LOG(log_level, format, args...) \
+  do                                                  \
+  {                                                   \
+    switch (log_level)                                \
+    {                                                 \
+      case ERROR:                                     \
+        LOGE(format, ##args);                         \
+      case WARNING:                                   \
+        LOGE(format, ##args);                         \
+      default:                                        \
+        LOGI(format, ##args);                         \
+    }                                                 \
+  } while (0)
+#else // __TIZEN__
+#define LEVEL_TO_STR(level)   \
+  (((level) == ERROR)         \
+       ? "ERROR"              \
+       : ((level) == WARNING) \
+             ? "WARNING"      \
+             : ((level) == INFO) ? "INFO" : ((level) == DEBUG) ? "DEBUG" : "DEFAULT")
+#define TFLITE_NATIVE_LOG(log_level, format, args...)      \
+  do                                                       \
+  {                                                        \
+    printf("%s: %s: ", LEVEL_TO_STR(log_level), __FILE__); \
+    printf(format, ##args);                                \
+    printf("\n");                                          \
+  } while (0)
+#endif // __TIZEN__
+
+#ifdef __cplusplus
+}
+#endif /*__cplusplus*/
+
+#endif /*_TFLITE_LOG_H*/
diff --git a/runtime/contrib/TFLiteSharp/TFLiteNative/include/tflite_nativewrapper.h b/runtime/contrib/TFLiteSharp/TFLiteNative/include/tflite_nativewrapper.h
new file mode 100644
index 000000000..af1947ff0
--- /dev/null
+++ b/runtime/contrib/TFLiteSharp/TFLiteNative/include/tflite_nativewrapper.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the License);
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _TFLITE_NATIVEWRAPPER_H_
+#define _TFLITE_NATIVEWRAPPER_H_
+
+#include "tensorflow/lite/kernels/register.h"
+#include "tensorflow/lite/model.h"
+#include "tensorflow/lite/string_util.h"
+#include "tensorflow/lite/tools/mutable_op_resolver.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /*__cplusplus*/
+
+typedef enum {
+  /** 32-bit signed integer. */
+  INT32 = 1,
+
+  /** 32-bit single precision floating point. */
+  FLOAT32 = 2,
+
+  /** 8-bit unsigned integer. */
+  UINT8 = 3,
+
+  /** 64-bit signed integer. */
+  INT64 = 4
+} TFLiteNativeType;
+
+void tflite_interpreter_setNumThreads(long *interpreterHandle, int numThreads);
+
+long long tflite_flatbuffermodel_BuildFromFile(char *modelPath);
+
+long long tflite_builder_interpreterBuilder(long *modelHandle);
+
+void *tflite_interpreter_run(long *interpreterHandle, void *values, int inputLength, int dataType);
+
+#ifdef __cplusplus
+}
+#endif /*__cplusplus*/
+
+#endif /*_TFLITE_NATIVEWRAPPER_H_*/
diff --git a/runtime/contrib/TFLiteSharp/TFLiteNative/src/tflite_nativewrapper.cpp b/runtime/contrib/TFLiteSharp/TFLiteNative/src/tflite_nativewrapper.cpp
new file mode 100644
index 000000000..0304720f7
--- /dev/null
+++ b/runtime/contrib/TFLiteSharp/TFLiteNative/src/tflite_nativewrapper.cpp
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the License);
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <iostream>
+#include "tflite_nativewrapper.h"
+#include "tflite_log.h"
+#include <string.h>
+#include <unistd.h>
+#include <errno.h>
+#include <assert.h>
+
+int getNumBytes(TFLiteNativeType dataType)
+{
+  switch (dataType)
+  {
+    case INT32:
+      return 4;
+    case FLOAT32:
+      return 4;
+    case UINT8:
+      return 1;
+    case INT64:
+      return 8;
+    default:
+      return 1;
+  }
+}
+
+/// <summary>
+/// Set the number of threads available to the interpreter.
+/// </summary>
+/// <param name="interpreterHandle">Handle of the interpreter instance.</param>
+/// <param name="numThreads">Number of threads.</param>
+void tflite_interpreter_setNumThreads(long *interpreterHandle, int numThreads)
+{
+  assert(interpreterHandle != nullptr);
+  tflite::Interpreter *interpreter = reinterpret_cast<tflite::Interpreter *>(*interpreterHandle);
+
+  interpreter->SetNumThreads(numThreads);
+
+  TFLITE_NATIVE_LOG(DEBUG, "Number of threads: %d", numThreads);
+  return;
+}
+
+/// <summary>
+/// Creates a Flat Buffer Model from the given .tflite model.
+/// </summary>
+/// <param name="modelPath">Path of the model.</param>
+long long tflite_flatbuffermodel_BuildFromFile(char *modelPath)
+{
+  if (modelPath == nullptr)
+  {
+    TFLITE_NATIVE_LOG(ERROR, "Invalid parameter");
+    return 0;
+  }
+  TFLITE_NATIVE_LOG(ERROR, "Model Path: %s", modelPath);
+
+  if (access(modelPath, F_OK) == -1)
+  {
+    TFLITE_NATIVE_LOG(ERROR, "Failed to access model [%s]", strerror(errno));
+    return 0;
+  }
+
+  auto model = tflite::FlatBufferModel::BuildFromFile(modelPath);
+
+  TFLITE_NATIVE_LOG(DEBUG, "Successfully loaded model");
+  return reinterpret_cast<long>(model.release());
+}
+
+/// <summary>
+/// Creates an interpreter instance taking the flatbuffer model as input.
+/// </summary>
+/// <param name="modelHandle">Address of the flatbuffer model.</param>
+long long tflite_builder_interpreterBuilder(long *modelHandle)
+{
+  assert(modelHandle != nullptr);
+  tflite::FlatBufferModel *model = reinterpret_cast<tflite::FlatBufferModel *>(*modelHandle);
+
+  tflite::ops::builtin::BuiltinOpResolver resolver;
+  std::unique_ptr<tflite::Interpreter> interpreter;
+
+  TfLiteStatus status = tflite::InterpreterBuilder(*model, resolver)(&interpreter);
+
+  if (status != kTfLiteOk)
+  {
+    TFLITE_NATIVE_LOG(DEBUG, "Cannot create interpreter");
+    return 0;
+  }
+  TFLITE_NATIVE_LOG(DEBUG, "CheckPoint interpreter");
+  return reinterpret_cast<long>(interpreter.release());
+}
+
+/// <summary>
+/// Runs the inference given the inputs.
+/// </summary>
+/// <param name="interpreterHandle">Address of the interpreter instance.</param>
+/// <param name="values">Input values for the model.</param>
+/// <param name="inpLength">Length of the input.</param>
+/// <param name="dataType">Data type key of the input.</param>
+void *tflite_interpreter_run(long *interpreterHandle, void *values, int inputLength, int dataType)
+{
+  assert(interpreterHandle != nullptr);
+  tflite::Interpreter *interpreter = reinterpret_cast<tflite::Interpreter *>(*interpreterHandle);
+
+  int inputTensorIndex = interpreter->inputs()[0];
+
+  // TODO:: input tensor size will be passed as a parameter. It is hardcoded for now.
+  interpreter->ResizeInputTensor(inputTensorIndex, {1, 224, 224, 3});
+
+  if (interpreter->AllocateTensors() != kTfLiteOk)
+  {
+    TFLITE_NATIVE_LOG(ERROR, "Failed to allocate tensors!");
+    return nullptr;
+  }
+
+  float *inputTensorPointer = interpreter->typed_tensor<float>(inputTensorIndex);
+
+  int numBytes = getNumBytes((TFLiteNativeType)dataType);
+
+  memcpy(inputTensorPointer, values, inputLength * numBytes);
+
+  if (interpreter->Invoke() != kTfLiteOk)
+  {
+    TFLITE_NATIVE_LOG(ERROR, "Failed to invoke");
+  }
+
+  float *output = interpreter->typed_output_tensor<float>(0);
+  return output;
+}
diff --git a/runtime/contrib/TFLiteSharp/TFLiteNative/tflite-native.pc.in b/runtime/contrib/TFLiteSharp/TFLiteNative/tflite-native.pc.in
new file mode 100644
index 000000000..eec103acc
--- /dev/null
+++ b/runtime/contrib/TFLiteSharp/TFLiteNative/tflite-native.pc.in
@@ -0,0 +1,13 @@
+# Package Information for pkg-config
+
+prefix=@PREFIX@
+exec_prefix=/usr
+libdir=@LIB_INSTALL_DIR@
+includedir=@INCLUDE_INSTALL_DIR@/
+
+Name: @PC_NAME@
+Description: @PACKAGE_DESCRIPTION@
+Version: @VERSION@
+Requires: @PC_REQUIRED@ tensorflow-lite
+Libs: -L${libdir} @PC_LDFLAGS@
+Cflags: -I${includedir}
diff --git a/runtime/contrib/TFLiteSharp/TFLiteSharp/TFLiteSharp.sln b/runtime/contrib/TFLiteSharp/TFLiteSharp/TFLiteSharp.sln
new file mode 100644
index 000000000..985466cef
--- /dev/null
+++ b/runtime/contrib/TFLiteSharp/TFLiteSharp/TFLiteSharp.sln
@@ -0,0 +1,25 @@
+
+Microsoft Visual Studio Solution File, Format Version 12.00
+# Visual Studio 15
+VisualStudioVersion = 15.0.26730.16
+MinimumVisualStudioVersion = 10.0.40219.1
+Project("{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC}") = "TFLiteSharp", "TFLiteSharp\TFLiteSharp.csproj", "{22D47176-D5AD-4AD4-8867-8788139DF71C}"
+EndProject
+Global
+	GlobalSection(SolutionConfigurationPlatforms) = preSolution
+		Debug|Any CPU = Debug|Any CPU
+		Release|Any CPU = Release|Any CPU
+	EndGlobalSection
+	GlobalSection(ProjectConfigurationPlatforms) = postSolution
+		{22D47176-D5AD-4AD4-8867-8788139DF71C}.Debug|Any CPU.ActiveCfg = Debug|Any CPU
+		{22D47176-D5AD-4AD4-8867-8788139DF71C}.Debug|Any CPU.Build.0 = Debug|Any CPU
+		{22D47176-D5AD-4AD4-8867-8788139DF71C}.Release|Any CPU.ActiveCfg = Release|Any CPU
+		{22D47176-D5AD-4AD4-8867-8788139DF71C}.Release|Any CPU.Build.0 = Release|Any CPU
+	EndGlobalSection
+	GlobalSection(SolutionProperties) = preSolution
+		HideSolutionNode = FALSE
+	EndGlobalSection
+	GlobalSection(ExtensibilityGlobals) = postSolution
+		SolutionGuid = {1B276F69-8E79-4501-AF04-6D340690762B}
+	EndGlobalSection
+EndGlobal
diff --git a/runtime/contrib/TFLiteSharp/TFLiteSharp/TFLiteSharp/Interop/Interop.Libraries.cs b/runtime/contrib/TFLiteSharp/TFLiteSharp/TFLiteSharp/Interop/Interop.Libraries.cs
new file mode 100644
index 000000000..db8d9f612
--- /dev/null
+++ b/runtime/contrib/TFLiteSharp/TFLiteSharp/TFLiteSharp/Interop/Interop.Libraries.cs
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the License);
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+internal static partial class Interop
+{
+    internal static partial class Libraries
+    {
+        public const string TFLite = "libtflite-native.so";
+    }
+}
diff --git a/runtime/contrib/TFLiteSharp/TFLiteSharp/TFLiteSharp/Interop/Interop.TFLite.cs b/runtime/contrib/TFLiteSharp/TFLiteSharp/TFLiteSharp/Interop/Interop.TFLite.cs
new file mode 100644
index 000000000..c7c7b24aa
--- /dev/null
+++ b/runtime/contrib/TFLiteSharp/TFLiteSharp/TFLiteSharp/Interop/Interop.TFLite.cs
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the License);
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+using System;
+using System.Runtime.InteropServices;
+
+internal static partial class Interop
+{
+    internal static partial class TFLite
+    {
+        [DllImport(Libraries.TFLite, EntryPoint = "tflite_flatbuffermodel_BuildFromFile")]
+        internal static extern IntPtr TFLiteFlatBufferModelBuildFromFile(string path);
+
+        [DllImport(Libraries.TFLite, EntryPoint = "tflite_builder_interpreterBuilder")]
+        internal static extern IntPtr TFLiteBuilderInterpreterBuilder(ref IntPtr modelHandle);
+
+        [DllImport(Libraries.TFLite, EntryPoint = "tflite_interpreter_setNumThreads")]
+        internal static extern void TFLiteInterpreterSetNumThreads(int numThreads);
+
+        [DllImport(Libraries.TFLite, EntryPoint = "tflite_interpreter_run")]
+        internal static extern IntPtr TFLiteInterpreterRun(ref IntPtr interpreterHandle, IntPtr values, int inpLen, int dataType);
+
+    }
+}
diff --git a/runtime/contrib/TFLiteSharp/TFLiteSharp/TFLiteSharp/TFLiteSharp.csproj b/runtime/contrib/TFLiteSharp/TFLiteSharp/TFLiteSharp/TFLiteSharp.csproj
new file mode 100644
index 000000000..e0490bfb8
--- /dev/null
+++ b/runtime/contrib/TFLiteSharp/TFLiteSharp/TFLiteSharp/TFLiteSharp.csproj
@@ -0,0 +1,52 @@
+<Project>
+  <Import Project="Sdk.props" Sdk="Microsoft.NET.Sdk" />
+
+  <PropertyGroup Label="Globals">
+    <TizenProjectExtensionsPath>$(MSBuildExtensionsPath)\Tizen\VisualStudio\</TizenProjectExtensionsPath>
+  </PropertyGroup>
+
+  <Import Project="$(TizenProjectExtensionsPath)Tizen.NET.ProjectType.props" Condition="Exists('$(TizenProjectExtensionsPath)Tizen.NET.ProjectType.props')" />
+
+  <PropertyGroup>
+    <OutputType>Library</OutputType>
+    <TargetFramework>netstandard2.0</TargetFramework>
+  </PropertyGroup>
+
+  <!--
+  This Property Group for msbuild command line.
+  If project build on Visual Studio, it would be set automatically through the certificate manager.
+  <PropertyGroup>
+    <AuthorPath>author_test.p12</AuthorPath>
+    <AuthorPass>author_test</AuthorPass>
+    <DistributorPath>tizen-distributor-signer.p12</DistributorPath>
+    <DistributorPass>tizenpkcs12passfordsigner</DistributorPass>
+  </PropertyGroup>
+  -->
+
+  <PropertyGroup Condition=" '$(Configuration)|$(Platform)' == 'Debug|AnyCPU' ">
+    <DebugType>portable</DebugType>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)|$(Platform)' == 'Release|AnyCPU' ">
+    <DebugType>None</DebugType>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Remove="res\**" />
+    <EmbeddedResource Remove="res\**" />
+    <None Remove="res\**" />
+  </ItemGroup>
+
+  <ItemGroup>
+    <Folder Include="Interop\" />
+    <Folder Include="lib\" />
+  </ItemGroup>
+
+  <Import Project="Sdk.targets" Sdk="Microsoft.NET.Sdk" />
+  <Import Project="$(TizenProjectExtensionsPath)Tizen.NET.ProjectType.targets" Condition="Exists('$(TizenProjectExtensionsPath)Tizen.NET.ProjectType.targets')" />
+
+  <!-- Install Check 'Visual Studio for Tizen' for developing on Visual Studio -->
+  <Target Name="TizenVsixInstallCheck" BeforeTargets="CompileDesignTime">
+    <Warning Condition="!Exists('$(TizenProjectExtensionsPath)Tizen.NET.ProjectType.props')" Text="$(TizenProjectExtensionsPath)Tizen.NET.ProjectType.props is not exist.&#xA; you need to check if 'Visual Studio for Tizen' is installed" />
+    <Warning Condition="!Exists('$(TizenProjectExtensionsPath)Tizen.NET.ProjectType.targets')" Text="$(TizenProjectExtensionsPath)Tizen.NET.ProjectType.targets is not exist.\&#xA; you need to check if 'Visual Studio for Tizen' is installed" />
+  </Target>
+</Project>
+
diff --git a/runtime/contrib/TFLiteSharp/TFLiteSharp/TFLiteSharp/src/Datatype.cs b/runtime/contrib/TFLiteSharp/TFLiteSharp/TFLiteSharp/src/Datatype.cs
new file mode 100644
index 000000000..404d1663e
--- /dev/null
+++ b/runtime/contrib/TFLiteSharp/TFLiteSharp/TFLiteSharp/src/Datatype.cs
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the License);
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/** Type of elements in a {@link TfLiteTensor}. */
+enum DataType
+{
+    /** 32-bit signed integer. */
+    INT32 = 1,
+
+    /** 32-bit single precision floating point. */
+    FLOAT32 = 2,
+
+    /** 8-bit unsigned integer. */
+    UINT8 = 3,
+
+    /** 64-bit signed integer. */
+    INT64 = 4
+}
diff --git a/runtime/contrib/TFLiteSharp/TFLiteSharp/TFLiteSharp/src/Interpreter.cs b/runtime/contrib/TFLiteSharp/TFLiteSharp/TFLiteSharp/src/Interpreter.cs
new file mode 100644
index 000000000..f1b4a8e07
--- /dev/null
+++ b/runtime/contrib/TFLiteSharp/TFLiteSharp/TFLiteSharp/src/Interpreter.cs
@@ -0,0 +1,263 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the License);
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+using System;
+using System.Collections.Generic;
+using System.Runtime.InteropServices;
+
+namespace TFLite
+{
+
+    /// <summary>
+    /// Driver class to drive model inference with TensorFlow Lite. Interpreter
+    /// encapsulates a pre-trained model file in whihc the operations are performed
+    /// @class	Interpreter
+    /// </summary>
+    public class Interpreter : IDisposable
+    {
+        // Handle to hold the model instance
+        private IntPtr m_modelHandle;
+        // Handle to hold the interpreter instance
+        private IntPtr m_interpreterHandle;
+
+        /// <summary>
+        /// Interpreter Constructor. Inititalizes an interpreter.     
+        /// </summary>
+        ///<param name="modelPath">a File of a pre-trained TF Lite model. </param>        
+        public Interpreter(string modelPath)
+        {
+            //Constructor to initialize the interpreter with a model file
+            m_modelHandle = Interop.TFLite.TFLiteFlatBufferModelBuildFromFile(modelPath);
+            if(m_modelHandle == IntPtr.Zero)
+            {
+                //TODO: routine for handling null pointer.
+            }
+            m_interpreterHandle = Interop.TFLite.TFLiteBuilderInterpreterBuilder(ref m_modelHandle);
+            if (m_interpreterHandle == IntPtr.Zero)
+            {
+                //TODO: routine for handling null pointer.
+            }
+        }
+
+        /// <summary>
+        /// Set the number of threads available to the interpreter.
+        /// </summary>
+        /// <param name="numThreads">Number of threads.</param>
+        public void SetNumThreads(int numThreads)
+        {
+            Interop.TFLite.TFLiteInterpreterSetNumThreads(numThreads);
+            return;
+        }
+
+        /// <summary>
+        /// Runs model inference if the model takes only one input, and provides only
+        /// one output.
+        /// </summary>
+        /// <param name="input">input an array or multidimensional array.</param>
+        /// <param name="output">outputs a multidimensional array of output data.</param>
+        public void Run(Array input, ref Array output)
+        {
+            Array[] inputs = { input };
+            Dictionary<int, Array> outputs = new Dictionary<int, Array>();
+
+            RunForMultipleInputsOutputs(inputs, ref outputs);
+            output = outputs[0];
+
+            return;
+        }
+
+        /// <summary>
+        /// Runs model inference if the model takes multiple inputs, or returns multiple
+        /// outputs.
+        /// </summary>
+        /// <param name="inputs">input an array of input data.</param>
+        /// <param name="outputs">outputs a map mapping output indices to multidimensional
+        /// arrays of output data.</param>
+        public void RunForMultipleInputsOutputs(Array[] inputs, ref Dictionary<int, Array> outputs)
+        {
+            if(m_interpreterHandle == IntPtr.Zero)
+            {
+                //TODO:: exception handling
+            }
+
+            if (inputs == null || inputs.Length == 0)
+            {
+                //TODO::throw new IllegalArgumentException("Input error: Inputs should not be null or empty.");
+            }
+
+            DataType[] dataTypes = new DataType[inputs.Length];//To be used in multi-dimensional case
+
+            for (int i = 0; i < inputs.Length; ++i)
+            {
+                dataTypes[i] = DataTypeOf(inputs[i]);
+            }
+
+            //TODO:: Support for multi dimesional array to be added.
+            IntPtr pnt = Marshal.AllocHGlobal(inputs[0].Length);
+
+            switch (dataTypes[0])
+            {
+                case DataType.INT32:
+                    Marshal.Copy((int[])inputs[0], 0, pnt, inputs[0].Length);
+                    break;
+                case DataType.FLOAT32:
+                    Marshal.Copy((float[])inputs[0], 0, pnt, inputs[0].Length);
+                    break;
+                case DataType.UINT8:
+                    Marshal.Copy((byte[])inputs[0], 0, pnt, inputs[0].Length);
+                    break;
+                case DataType.INT64:
+                    Marshal.Copy((long[])inputs[0], 0, pnt, inputs[0].Length);
+                    break;
+                default:
+                    Marshal.Copy((byte[])inputs[0], 0, pnt, inputs[0].Length);
+                    break;
+            }
+
+            //Currently this handles only single input with single dimension.
+            IntPtr outputsHandles = Interop.TFLite.TFLiteInterpreterRun(ref m_interpreterHandle, pnt, inputs[0].Length, (int)dataTypes[0]);
+
+            if (outputsHandles == null)
+            {
+                //throw new IllegalStateException("Internal error: Interpreter has no outputs.");
+            }
+
+            switch (dataTypes[0])
+            {
+                case DataType.INT32:
+                    int[] managedArrayInt = new int[inputs[0].Length];
+                    Marshal.Copy(outputsHandles, managedArrayInt, 0, inputs[0].Length);
+                    outputs.Add(0, managedArrayInt);
+                    break;
+                case DataType.FLOAT32:
+                    float[] managedArrayFloat = new float[inputs[0].Length];
+                    Marshal.Copy(outputsHandles, managedArrayFloat, 0, inputs[0].Length);
+                    outputs.Add(0, managedArrayFloat);
+                    break;
+                case DataType.UINT8:
+                    byte[] managedArrayByte = new byte[inputs[0].Length];
+                    Marshal.Copy(outputsHandles, managedArrayByte, 0, inputs[0].Length);
+                    outputs.Add(0, managedArrayByte);
+                    break;
+                case DataType.INT64:
+                    long[] managedArrayLong = new long[inputs[0].Length];
+                    Marshal.Copy(outputsHandles, managedArrayLong, 0, inputs[0].Length);
+                    outputs.Add(0, managedArrayLong);
+                    break;
+                default:
+                    byte[] managedArrayDefault = new byte[inputs[0].Length];
+                    Marshal.Copy(outputsHandles, managedArrayDefault, 0, inputs[0].Length);
+                    outputs.Add(0, managedArrayDefault);
+                    break;
+            }
+            return;
+        }
+
+        static DataType DataTypeOf(Array a)
+        {
+            if (a.GetValue(0).GetType()==typeof(int))
+            {
+                return DataType.INT32;
+            }
+            else if (a.GetValue(0).GetType() == typeof(float))
+            {
+                return DataType.FLOAT32;
+            }
+            else if (a.GetValue(0).GetType() == typeof(byte))
+            {
+                return DataType.UINT8;
+            }
+            else if(a.GetValue(0).GetType() == typeof(long))
+            {
+                return DataType.INT64;
+            }
+            else
+            {
+                return DataType.UINT8;
+                //TODO: throw exception
+            }
+
+        }
+
+        /// <summary>
+        /// Resizes idx-th input of the native model to the given dims.
+        /// </summary>
+        /// <param name="idx">index of the input.</param>
+        /// <param name="dims">Dimensions to which input needs to be resized.</param>
+        public void ResizeInput(int idx, int[] dims)
+        {
+            return;
+        }
+
+        /// <summary>
+        /// Gets index of an input given the tensor name of the input.
+        /// </summary>
+        /// <param name="tensorName">Name of the tensor.</param>
+        public int GetInputIndex(string tensorName)
+        {
+            return 0;
+        }
+
+        /// <summary>
+        /// Gets index of output given the tensor name of the input.
+        /// </summary>
+        /// <param name="tensorName">Name of the tensor.</param>
+        public int GetOutputIndex(string tensorName)
+        {
+            return 0;
+        }
+
+        /// <summary>
+        /// Turns on/off Android NNAPI for hardware acceleration when it is available.
+        /// </summary>
+        /// <param name="useNNAPI">set the boolean value to turn on/off nnapi.</param>
+        public void SetUseNNAPI(bool useNNAPI)
+        {
+            return;
+        }
+
+        /// <summary>
+        /// Release resources associated with the Interpreter.
+        /// </summary>
+        public void Dispose()
+        {
+            Dispose(true);
+        }
+
+        protected virtual void Dispose(bool bDisposing)
+        {
+            if (m_interpreterHandle != IntPtr.Zero)
+            {
+                // Call the function to dispose this class
+                m_interpreterHandle = IntPtr.Zero;
+            }
+
+            if (bDisposing)
+            {
+                // No need to call the finalizer since we've now cleaned
+                // up the unmanaged memory
+                GC.SuppressFinalize(this);
+            }
+        }
+
+        // This finalizer is called when Garbage collection occurs, but only if
+        // the IDisposable.Dispose method wasn't already called.
+        ~Interpreter()
+        {
+            Dispose(false);
+        }
+    }
+}
diff --git a/runtime/contrib/TFLiteSharp/TFLiteSharpTest/TFLiteSharpTest.sln b/runtime/contrib/TFLiteSharp/TFLiteSharpTest/TFLiteSharpTest.sln
new file mode 100644
index 000000000..e260a72c7
--- /dev/null
+++ b/runtime/contrib/TFLiteSharp/TFLiteSharpTest/TFLiteSharpTest.sln
@@ -0,0 +1,31 @@
+
+Microsoft Visual Studio Solution File, Format Version 12.00
+# Visual Studio 15
+VisualStudioVersion = 15.0.26730.16
+MinimumVisualStudioVersion = 10.0.40219.1
+Project("{9A19103F-16F7-4668-BE54-9A1E7A4F7556}") = "TFLiteSharpTest", "TFLiteSharpTest\TFLiteSharpTest.csproj", "{D35A178F-9EF3-4B07-9E53-A91AA7A030B3}"
+EndProject
+Project("{9A19103F-16F7-4668-BE54-9A1E7A4F7556}") = "TFLiteSharp", "..\TFLiteSharp\TFLiteSharp\TFLiteSharp.csproj", "{C06BC425-9BC3-43C7-A9D3-E12849E0C129}"
+EndProject
+Global
+	GlobalSection(SolutionConfigurationPlatforms) = preSolution
+		Debug|Any CPU = Debug|Any CPU
+		Release|Any CPU = Release|Any CPU
+	EndGlobalSection
+	GlobalSection(ProjectConfigurationPlatforms) = postSolution
+		{D35A178F-9EF3-4B07-9E53-A91AA7A030B3}.Debug|Any CPU.ActiveCfg = Debug|Any CPU
+		{D35A178F-9EF3-4B07-9E53-A91AA7A030B3}.Debug|Any CPU.Build.0 = Debug|Any CPU
+		{D35A178F-9EF3-4B07-9E53-A91AA7A030B3}.Release|Any CPU.ActiveCfg = Release|Any CPU
+		{D35A178F-9EF3-4B07-9E53-A91AA7A030B3}.Release|Any CPU.Build.0 = Release|Any CPU
+		{C06BC425-9BC3-43C7-A9D3-E12849E0C129}.Debug|Any CPU.ActiveCfg = Debug|Any CPU
+		{C06BC425-9BC3-43C7-A9D3-E12849E0C129}.Debug|Any CPU.Build.0 = Debug|Any CPU
+		{C06BC425-9BC3-43C7-A9D3-E12849E0C129}.Release|Any CPU.ActiveCfg = Release|Any CPU
+		{C06BC425-9BC3-43C7-A9D3-E12849E0C129}.Release|Any CPU.Build.0 = Release|Any CPU
+	EndGlobalSection
+	GlobalSection(SolutionProperties) = preSolution
+		HideSolutionNode = FALSE
+	EndGlobalSection
+	GlobalSection(ExtensibilityGlobals) = postSolution
+		SolutionGuid = {8F946511-2BE4-40A5-A48C-A5684C62755D}
+	EndGlobalSection
+EndGlobal
diff --git a/runtime/contrib/TFLiteSharp/TFLiteSharpTest/TFLiteSharpTest/Program.cs b/runtime/contrib/TFLiteSharp/TFLiteSharpTest/TFLiteSharpTest/Program.cs
new file mode 100644
index 000000000..e559bec36
--- /dev/null
+++ b/runtime/contrib/TFLiteSharp/TFLiteSharpTest/TFLiteSharpTest/Program.cs
@@ -0,0 +1,38 @@
+using System;
+
+namespace TFLiteSharpTest
+{
+    class Program
+    {
+        static void Main(string[] args)
+        {
+            //Constructing a new interpreter instance from the modelfile
+            TFLite.Interpreter interpreter = new TFLite.Interpreter("modelpath/modelfile.tflite");
+            Console.WriteLine("Interpreter Built Successfully");
+
+            //Setting the number of threads of the interpreter
+            interpreter.SetNumThreads(1);
+
+            //Declaring input and output variables;
+            Array input = new int[5] { 1, 2, 3, 4, 5 };
+            Array output = new int[5];
+
+            //Call to invoke the interpreter and run the inference to populate output
+            interpreter.Run(input, out output);
+            Console.WriteLine("Output generated Successfully");
+
+            //get input, output indices
+            Console.WriteLine("Input index for tensorname: " + interpreter.GetInputIndex("tensorname"));
+            Console.WriteLine("Output index for tensorname: " + interpreter.GetOutputIndex("tensorname"));
+
+            //Resizing the dimensions
+            int[] dims = new int[3] { 1, 2, 3 };
+            interpreter.ResizeInput(1, dims);
+
+            //Disposing the interpreter to free resources at the end
+            interpreter.Dispose();
+
+            Console.WriteLine("Run Complete");
+        }
+    }
+}
diff --git a/runtime/contrib/TFLiteSharp/TFLiteSharpTest/TFLiteSharpTest/TFLiteSharpTest.csproj b/runtime/contrib/TFLiteSharp/TFLiteSharpTest/TFLiteSharpTest/TFLiteSharpTest.csproj
new file mode 100644
index 000000000..b143ee598
--- /dev/null
+++ b/runtime/contrib/TFLiteSharp/TFLiteSharpTest/TFLiteSharpTest/TFLiteSharpTest.csproj
@@ -0,0 +1,12 @@
+<Project Sdk="Microsoft.NET.Sdk">
+
+  <PropertyGroup>
+    <OutputType>Exe</OutputType>
+    <TargetFramework>netcoreapp2.0</TargetFramework>
+  </PropertyGroup>
+
+  <ItemGroup>
+    <ProjectReference Include="..\..\TFLiteSharp\TFLiteSharp\TFLiteSharp.csproj" />
+  </ItemGroup>
+
+</Project>
diff --git a/runtime/contrib/TFLiteSharp/TFLiteTestApp/TFLiteTestApp.csproj b/runtime/contrib/TFLiteSharp/TFLiteTestApp/TFLiteTestApp.csproj
new file mode 100644
index 000000000..1c9ed6037
--- /dev/null
+++ b/runtime/contrib/TFLiteSharp/TFLiteTestApp/TFLiteTestApp.csproj
@@ -0,0 +1,54 @@
+<Project>
+  <Import Project="Sdk.props" Sdk="Microsoft.NET.Sdk" />
+
+  <!-- Setting Tizen Extension Path -->
+  <PropertyGroup Label="Globals">
+    <TizenProjectExtensionsPath>$(MSBuildExtensionsPath)\Tizen\VisualStudio\</TizenProjectExtensionsPath>
+  </PropertyGroup>
+
+  <!-- Import Tizen property in Tizen.NET SDK -->
+  <Import Project="$(TizenProjectExtensionsPath)Tizen.NET.ProjectType.props" Condition="Exists('$(TizenProjectExtensionsPath)Tizen.NET.ProjectType.props')" />
+
+  <!-- Property Group for .NET Core Project -->
+  <PropertyGroup>
+    <OutputType>Exe</OutputType>
+    <TargetFramework>netstandard2.0</TargetFramework>
+  </PropertyGroup>
+
+  <!-- Property Group for Tizen Project -->
+  <PropertyGroup>
+    <TizenCreateTpkOnBuild>true</TizenCreateTpkOnBuild>
+    <PackageTargetFallback>$(PackageTargetFallback);portable-net45+wp80+win81+wpa81</PackageTargetFallback>
+  </PropertyGroup>
+  
+  <PropertyGroup Condition=" '$(Configuration)|$(Platform)' == 'Debug|AnyCPU' ">
+    <DebugType>portable</DebugType>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)|$(Platform)' == 'Release|AnyCPU' ">
+    <DebugType>None</DebugType>
+  </PropertyGroup>
+
+  <ItemGroup>
+	<Folder Include="lib\" />
+	<Folder Include="res\" />
+  </ItemGroup>
+
+  <!-- Include Nuget Package for Tizen Project building -->
+  <ItemGroup>
+    <PackageReference Include="Tizen.NET" Version="3.0.0" />
+    <PackageReference Include="Tizen.NET.Sdk" Version="1.0.1" />
+    <PackageReference Include="Xamarin.Forms.Platform.Tizen" Version="2.3.5-r256-001" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\TFLiteSharp\TFLiteSharp\TFLiteSharp.csproj" />
+  </ItemGroup>
+
+  <Import Project="Sdk.targets" Sdk="Microsoft.NET.Sdk" />
+  <Import Project="$(TizenProjectExtensionsPath)Tizen.NET.ProjectType.targets" Condition="Exists('$(TizenProjectExtensionsPath)Tizen.NET.ProjectType.targets')" />
+
+  <!-- Install Check 'Visual Studio for Tizen' for developing on Visual Studio -->
+  <Target Name="TizenVsixInstallCheck" BeforeTargets="CompileDesignTime">
+    <Warning Condition="!Exists('$(TizenProjectExtensionsPath)Tizen.NET.ProjectType.props')" Text="$(TizenProjectExtensionsPath)Tizen.NET.ProjectType.props is not exist.&#xA; you need to check if 'Visual Studio for Tizen' is installed" />
+    <Warning Condition="!Exists('$(TizenProjectExtensionsPath)Tizen.NET.ProjectType.targets')" Text="$(TizenProjectExtensionsPath)Tizen.NET.ProjectType.targets is not exist.\&#xA; you need to check if 'Visual Studio for Tizen' is installed" />
+  </Target>
+</Project>
diff --git a/runtime/contrib/TFLiteSharp/TFLiteTestApp/TFLiteTestApp_App.cs b/runtime/contrib/TFLiteSharp/TFLiteTestApp/TFLiteTestApp_App.cs
new file mode 100644
index 000000000..49a08604d
--- /dev/null
+++ b/runtime/contrib/TFLiteSharp/TFLiteTestApp/TFLiteTestApp_App.cs
@@ -0,0 +1,65 @@
+using System;
+using System.IO;
+using System.Collections.Generic;
+using System.Linq;
+using System.Text;
+
+using Xamarin.Forms;
+
+namespace TFLiteTestApp
+{
+    public class App : Application
+    {
+        public App()
+        {
+            TFLite.Interpreter interpreter = null;
+            try
+            {
+                interpreter = new TFLite.Interpreter(Tizen.Applications.Application.Current.DirectoryInfo.Resource + "mobilenet_v1_1.0_224.tflite");
+            }
+            catch(Exception e)
+            {
+                Tizen.Log.Debug("tflite", "Error: " + e);
+            }
+
+            Tizen.Log.Debug("tflite", "Interpreter Initialised");
+            Array Output = new byte[1000];
+
+            Array input = new byte[150582];
+            input = File.ReadAllBytes(Tizen.Applications.Application.Current.DirectoryInfo.Resource + "mouse_224.bmp");
+
+            interpreter.Run(input, ref Output);
+            //val variable to check if the Output array is being populated or not.
+            byte val = ((byte[])Output)[0];
+            // The root page of your application
+            MainPage = new ContentPage
+            {
+                Content = new StackLayout
+                {
+                    VerticalOptions = LayoutOptions.Center,
+                    Children = {
+                        new Label {
+                            HorizontalTextAlignment = TextAlignment.Center,
+                            Text = "Welcome to Xamarin Forms!"
+                        }
+                    }
+                }
+            };
+        }
+
+        protected override void OnStart()
+        {
+            // Handle when your app starts
+        }
+
+        protected override void OnSleep()
+        {
+            // Handle when your app sleeps
+        }
+
+        protected override void OnResume()
+        {
+            // Handle when your app resumes
+        }
+    }
+}
diff --git a/runtime/contrib/TFLiteSharp/TFLiteTestApp/TFLiteTestApp_Main.cs b/runtime/contrib/TFLiteSharp/TFLiteTestApp/TFLiteTestApp_Main.cs
new file mode 100644
index 000000000..2a8f747a4
--- /dev/null
+++ b/runtime/contrib/TFLiteSharp/TFLiteTestApp/TFLiteTestApp_Main.cs
@@ -0,0 +1,20 @@
+using System;
+
+namespace TFLiteTestApp
+{
+    class Program : global::Xamarin.Forms.Platform.Tizen.FormsApplication
+    {
+        protected override void OnCreate()
+        {
+            base.OnCreate();
+            LoadApplication(new App());
+        }
+
+        static void Main(string[] args)
+        {
+            var app = new Program();
+            global::Xamarin.Forms.Platform.Tizen.Forms.Init(app);
+            app.Run(args);
+        }
+    }
+}
diff --git a/runtime/contrib/TFLiteSharp/TFLiteTestApp/res/mobilenet_v1_1.0_224.tflite b/runtime/contrib/TFLiteSharp/TFLiteTestApp/res/mobilenet_v1_1.0_224.tflite
new file mode 100644
index 000000000..d34691eb6
--- /dev/null
+++ b/runtime/contrib/TFLiteSharp/TFLiteTestApp/res/mobilenet_v1_1.0_224.tflite
diff --git a/runtime/contrib/TFLiteSharp/TFLiteTestApp/res/mouse1.bmp b/runtime/contrib/TFLiteSharp/TFLiteTestApp/res/mouse1.bmp
new file mode 100644
index 000000000..1734ca318
--- /dev/null
+++ b/runtime/contrib/TFLiteSharp/TFLiteTestApp/res/mouse1.bmp
diff --git a/runtime/contrib/TFLiteSharp/TFLiteTestApp/res/mouse_224.bmp b/runtime/contrib/TFLiteSharp/TFLiteTestApp/res/mouse_224.bmp
new file mode 100644
index 000000000..ccfed6ad3
--- /dev/null
+++ b/runtime/contrib/TFLiteSharp/TFLiteTestApp/res/mouse_224.bmp
diff --git a/runtime/contrib/TFLiteSharp/TFLiteTestApp/shared/res/TFLiteTestApp.png b/runtime/contrib/TFLiteSharp/TFLiteTestApp/shared/res/TFLiteTestApp.png
new file mode 100644
index 000000000..9f3cb9860
--- /dev/null
+++ b/runtime/contrib/TFLiteSharp/TFLiteTestApp/shared/res/TFLiteTestApp.png
diff --git a/runtime/contrib/TFLiteSharp/TFLiteTestApp/tizen-manifest.xml b/runtime/contrib/TFLiteSharp/TFLiteTestApp/tizen-manifest.xml
new file mode 100644
index 000000000..62a8d4c7c
--- /dev/null
+++ b/runtime/contrib/TFLiteSharp/TFLiteTestApp/tizen-manifest.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="utf-8"?>
+<manifest xmlns="http://tizen.org/ns/packages" api-version="4" package="org.tizen.example.TFLiteTestApp" version="1.0.0">
+  <profile name="common" />
+  <ui-application appid="org.tizen.example.TFLiteTestApp"
+					exec="TFLiteTestApp.dll"
+					type="dotnet"
+					multiple="false"
+					taskmanage="true"
+					nodisplay="false"
+					launch_mode="single">
+    <label>TFLiteTestApp</label>
+    <icon>TFLiteTestApp.png</icon>
+  </ui-application>
+</manifest>
diff --git a/runtime/contrib/TFLiteSharp/packaging/TFLiteSharp.manifest b/runtime/contrib/TFLiteSharp/packaging/TFLiteSharp.manifest
new file mode 100644
index 000000000..75b0fa5e3
--- /dev/null
+++ b/runtime/contrib/TFLiteSharp/packaging/TFLiteSharp.manifest
@@ -0,0 +1,5 @@
+<manifest>
+    <request>
+        <domain name="_"/>
+    </request>
+</manifest>
diff --git a/runtime/contrib/TFLiteSharp/packaging/TFLiteSharp.spec b/runtime/contrib/TFLiteSharp/packaging/TFLiteSharp.spec
new file mode 100644
index 000000000..dcb65a864
--- /dev/null
+++ b/runtime/contrib/TFLiteSharp/packaging/TFLiteSharp.spec
@@ -0,0 +1,103 @@
+Name:    TFLiteSharp
+Summary: Tensorflow lite native cpp wrapper and C# API
+Version: 1.0.0
+Release: 1
+Group:   Development/Libraries
+License: Apache-2.0
+Source0: %{name}-%{version}.tar.gz
+Source1: %{name}.manifest
+Source2: tflite-native.manifest
+
+%description
+%{summary}
+
+%package TFLiteNative
+Summary:          Tensorflow lite native cpp wrapper
+Group:            Development/Libraries
+BuildRequires:    cmake
+BuildRequires:    pkgconfig(dlog)
+BuildRequires:    pkgconfig(tensorflow-lite)
+Requires(post):   /sbin/ldconfig
+Requires(postun): /sbin/ldconfig
+
+%description TFLiteNative
+Native CPP Wrapper for Tensorflow lite
+
+%package TFLiteNative-devel
+Summary:  Tensorflow lite native cpp wrapper (Development)
+Requires: %{name} = %{version}-%{release}
+
+%description TFLiteNative-devel
+Tensorflow lite native cpp wrapper (Development)
+
+%package TFLiteSharp
+Summary:       Tensorflow lite API for C#
+Group:         Development/Libraries
+AutoReqProv:   no
+ExcludeArch:   aarch64
+
+BuildRequires: dotnet-build-tools
+
+%define Assemblies TFLiteSharp
+
+%description TFLiteSharp
+Tensorflow lite API for C#
+
+%dotnet_import_sub_packages
+
+%prep
+%setup -q
+cp %{SOURCE1} .
+cp %{SOURCE2} .
+%if 0%{?tizen:1}
+%define TARGET_OS tizen
+%else
+%define TARGET_OS linux
+%endif
+
+%build
+MAJORVER=`echo %{version} | awk 'BEGIN {FS="."}{print $1}'`
+%if "%{TARGET_OS}" == "tizen"
+cmake VERBOSE=1 -DCMAKE_INSTALL_PREFIX=/usr -DFULLVER=%{version} -DMAJORVER=${MAJORVER} \
+      -DLIB_INSTALL_DIR=%{_libdir} -DINCLUDE_INSTALL_DIR=%{_includedir} \
+      -DLIB_PATH=%{_lib} -DTIZEN=1 contrib/TFLiteSharp/TFLiteNative
+%else
+cmake VERBOSE=1 -DCMAKE_INSTALL_PREFIX=/usr -DFULLVER=%{version} -DMAJORVER=${MAJORVER} \
+      -DLIB_INSTALL_DIR=%{_libdir} -DINCLUDE_INSTALL_DIR=%{_includedir} \
+      -DLIB_PATH=%{_lib} contrib/TFLiteSharp/TFLiteNative
+%endif
+
+make %{?_smp_mflags}
+
+cd contrib/TFLiteSharp/
+for ASM in %{Assemblies}; do
+%dotnet_build $ASM
+%dotnet_pack $ASM
+done
+
+%install
+%make_install
+cd contrib/TFLiteSharp/TFLiteSharp
+for ASM in %{Assemblies}; do
+%dotnet_install $ASM
+done
+
+%post -p /sbin/ldconfig
+
+%postun -p /sbin/ldconfig
+
+%files
+%manifest %{name}.manifest
+%license LICENSE
+
+%files TFLiteNative
+%manifest tflite-native.manifest
+%{_libdir}/libtflite-native.so*
+
+%files TFLiteNative-devel
+%{_includedir}/*
+%{_libdir}/pkgconfig/tflite-native.pc
+%{_libdir}/libtflite-native.so*
+
+%files TFLiteSharp
+%attr(644,root,root) %{dotnet_assembly_files}
diff --git a/runtime/contrib/TFLiteSharp/packaging/tflite-native.manifest b/runtime/contrib/TFLiteSharp/packaging/tflite-native.manifest
new file mode 100644
index 000000000..75b0fa5e3
--- /dev/null
+++ b/runtime/contrib/TFLiteSharp/packaging/tflite-native.manifest
@@ -0,0 +1,5 @@
+<manifest>
+    <request>
+        <domain name="_"/>
+    </request>
+</manifest>
diff --git a/runtime/contrib/android_benchmark_app/AndroidManifest.xml b/runtime/contrib/android_benchmark_app/AndroidManifest.xml
new file mode 100644
index 000000000..f0b967cfa
--- /dev/null
+++ b/runtime/contrib/android_benchmark_app/AndroidManifest.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<manifest xmlns:android="http://schemas.android.com/apk/res/android"
+    package="com.ndk.tflbench" >
+
+    <application
+        android:allowBackup="true"
+        android:icon="@drawable/ic_launcher"
+        android:label="@string/app_name"
+        android:theme="@style/AppTheme" >
+        <activity
+            android:name="com.ndk.tflbench.MainActivity"
+            android:label="@string/app_name" >
+            <intent-filter>
+                <action android:name="android.intent.action.MAIN" />
+
+                <category android:name="android.intent.category.LAUNCHER" />
+            </intent-filter>
+        </activity>
+    </application>
+
+</manifest>
diff --git a/runtime/contrib/android_benchmark_app/CMakeLists.txt b/runtime/contrib/android_benchmark_app/CMakeLists.txt
new file mode 100644
index 000000000..8e9d3c7a1
--- /dev/null
+++ b/runtime/contrib/android_benchmark_app/CMakeLists.txt
@@ -0,0 +1,97 @@
+if(NOT BUILD_ANDROID_BENCHMARK_APP)
+  return()
+endif(NOT BUILD_ANDROID_BENCHMARK_APP)
+
+if(NOT ANDROID)
+  message(STATUS "Sample app is disabled as non-Android build")
+  return()
+endif()
+
+if(NOT DEFINED ANDROID_BUILD_TOOLS_DIR)
+  message(STATUS "Sample app is disabled as ANDROID_BUILD_TOOLS_DIR is not defined")
+  return()
+endif()
+
+if(NOT DEFINED ANDROID_SDK_DIR)
+  message(STATUS "Sample app is disabled as ANDROID_SDK_DIR is not defined")
+  return()
+endif()
+
+if(NOT DEFINED TFLITE_MODEL_PATH)
+  message(STATUS "Sample app is disabled as TFLITE_MODEL_PATH is not defined")
+  return()
+endif()
+
+nnas_find_package(ARMCompute REQUIRED)
+
+if(NOT CORE_LIBRARY OR NOT RUNTIME_LIBRARY)
+  message(STATUS "Sample app is disabled as ARM Compute Library is missing")
+  return()
+endif()
+
+get_filename_component(TFLITE_MODEL_FILENAME ${TFLITE_MODEL_PATH} NAME)
+
+set(ANDROID_API_VERSION 27)
+set(ANDROID_PLATFORM_DIR ${ANDROID_SDK_DIR}/platforms/android-${ANDROID_API_VERSION})
+
+set(GEN_DIR ${CMAKE_CURRENT_BINARY_DIR}/gen)
+set(OBJ_DIR ${CMAKE_CURRENT_BINARY_DIR}/obj)
+set(PKG_DIR ${CMAKE_CURRENT_BINARY_DIR}/pkg)
+set(LIB_DIR ${PKG_DIR}/lib/arm64-v8a)
+set(ASSETS_DIR ${PKG_DIR}/assets)
+set(SRC_LIST ${CMAKE_CURRENT_BINARY_DIR}/src.list)
+
+if (ANDROID_BOOST_ROOT)
+  set(BOOST_ROOT ${ANDROID_BOOST_ROOT})
+endif (ANDROID_BOOST_ROOT)
+
+nnas_find_package(Boost REQUIRED)
+
+add_library(android_benchmark_native SHARED cpp/ndk_main.cpp)
+target_compile_definitions(android_benchmark_native PRIVATE MODEL_NAME="${TFLITE_MODEL_FILENAME}")
+target_include_directories(android_benchmark_native PRIVATE ${NNAS_EXTERNALS_DIR}/tensorflow)
+target_include_directories(android_benchmark_native PRIVATE ${Boost_INCLUDE_DIRS})
+target_link_libraries(android_benchmark_native nnfw_lib_tflite)
+target_link_libraries(android_benchmark_native nnfw_lib_misc)
+target_link_libraries(android_benchmark_native log)
+
+nnfw_find_package(FlatBuffersSource REQUIRED)
+target_include_directories(android_benchmark_native PUBLIC ${FlatBuffersSource_DIR}/include .)
+
+add_custom_target(android-benchmark-apk ALL
+  COMMAND ${CMAKE_COMMAND} -E remove_directory ${GEN_DIR}
+  COMMAND ${CMAKE_COMMAND} -E make_directory ${GEN_DIR}
+  COMMAND ${ANDROID_BUILD_TOOLS_DIR}/aapt package -m -J ${GEN_DIR}
+                                                  -M ${CMAKE_CURRENT_SOURCE_DIR}/AndroidManifest.xml
+                                                  -S ${CMAKE_CURRENT_SOURCE_DIR}/res
+                                                  -I ${ANDROID_PLATFORM_DIR}/android.jar
+  COMMAND ${CMAKE_COMMAND} -E remove_directory ${OBJ_DIR}
+  COMMAND ${CMAKE_COMMAND} -E make_directory ${OBJ_DIR}
+  COMMAND ${CMAKE_COMMAND} -E remove -f ${SRC_LIST}
+  COMMAND find ${CMAKE_CURRENT_SOURCE_DIR}/java -name '*.java' >> ${SRC_LIST}
+  COMMAND find ${GEN_DIR} -name '*.java' >> ${SRC_LIST}
+  COMMAND javac -d ${OBJ_DIR} -source 1.7 -target 1.7 -bootclasspath "${JAVA_HOME}/jre/lib/rt.jar"
+                -classpath ${ANDROID_PLATFORM_DIR}/android.jar @${SRC_LIST}
+  COMMAND ${CMAKE_COMMAND} -E remove_directory ${PKG_DIR}
+  COMMAND ${CMAKE_COMMAND} -E make_directory ${PKG_DIR}
+  COMMAND ${CMAKE_COMMAND} -E make_directory ${ASSETS_DIR}
+  COMMAND ${CMAKE_COMMAND} -E copy ${TFLITE_MODEL_PATH} ${ASSETS_DIR}/model.tflite
+  COMMAND ${ANDROID_BUILD_TOOLS_DIR}/dx --dex --output=${PKG_DIR}/classes.dex ${OBJ_DIR}
+  COMMAND ${CMAKE_COMMAND} -E make_directory ${LIB_DIR}
+  COMMAND ${CMAKE_COMMAND} -E copy ${CORE_LIBRARY} ${LIB_DIR}
+  COMMAND ${CMAKE_COMMAND} -E copy ${RUNTIME_LIBRARY} ${LIB_DIR}
+  COMMAND ${CMAKE_COMMAND} -E copy $<TARGET_FILE:android_benchmark_native> ${LIB_DIR}
+  COMMAND ${CMAKE_COMMAND} -E copy $<TARGET_FILE:neurun> ${LIB_DIR}
+  COMMAND ${CMAKE_COMMAND} -E copy $<TARGET_FILE:neurun_backend_acl_cl> ${LIB_DIR}
+  COMMAND ${CMAKE_COMMAND} -E copy $<TARGET_FILE:arm_compute_ex> ${LIB_DIR}
+  COMMAND ${CMAKE_COMMAND} -E copy $<TARGET_FILE:neurun_backend_acl_neon> ${LIB_DIR}
+  COMMAND ${CMAKE_COMMAND} -E copy $<TARGET_FILE:neurun_backend_cpu> ${LIB_DIR}
+  COMMAND ${CMAKE_COMMAND} -E echo ${ANDROID_BUILD_TOOLS_DIR}/aapt package -f -0 tflite -M ${CMAKE_CURRENT_SOURCE_DIR}/AndroidManifest.xml -S ${CMAKE_CURRENT_SOURCE_DIR}/res/ -I ${ANDROID_PLATFORM_DIR}/android.jar -F ${CMAKE_CURRENT_BINARY_DIR}/android-benchmark.unsigned.pkg ${PKG_DIR}
+  COMMAND ${ANDROID_BUILD_TOOLS_DIR}/aapt package -f
+                                                  -0 tflite
+                                                  -M ${CMAKE_CURRENT_SOURCE_DIR}/AndroidManifest.xml
+                                                  -S ${CMAKE_CURRENT_SOURCE_DIR}/res/
+                                                  -I ${ANDROID_PLATFORM_DIR}/android.jar
+                                                  -F ${CMAKE_CURRENT_BINARY_DIR}/android-benchmark.unsigned.pkg
+                                                  ${PKG_DIR}
+  DEPENDS android_benchmark_native neurun neurun_backend_acl_cl neurun_backend_acl_neon neurun_backend_cpu)
diff --git a/runtime/contrib/android_benchmark_app/README.md b/runtime/contrib/android_benchmark_app/README.md
new file mode 100644
index 000000000..2868e0ada
--- /dev/null
+++ b/runtime/contrib/android_benchmark_app/README.md
@@ -0,0 +1,58 @@
+# Android Benchmark App
+
+An Android sample app that run `.tflite` and measure performance.
+
+You can run with two engines.
+
+- Tensorflow Lite Interpreter
+- NN API Delegate (neurun)
+
+## Build
+
+In addition to aarch64-Android build, you need to specify more parameters.
+
+- `ANDROID_BUILD_TOOLS_DIR` : Android `build-tools` directory (You may find it in Android SDK directory)
+- `ANDROID_SDK_DIR` : Android SDK directory
+- `TFLITE_MODEL_PATH` : A model to run (Only one model can be packed)
+- `ANDROID_BOOST_ROOT` : Boost library root path
+    - This repo should contain `lib` and `include` directory
+    - How to build Boost for Android - Build with [this repo](https://github.com/moritz-wundke/Boost-for-Android)
+
+Example:
+
+```bash
+make TARGET_OS=android \
+    CROSS_BUILD=1 \
+    BUILD_TYPE=RELEASE \
+    NDK_DIR=/home/hanjoung/ws/android-tools/r20/ndk \
+    EXT_ACL_FOLDER=/home/hanjoung/ws/temp/arm_compute-v19.05-bin-android/lib/android-arm64-v8a-neon-cl \
+    ANDROID_BUILD_TOOLS_DIR=/home/hanjoung/ws/android-tools/sdk/build-tools/27.0.3/ \
+    ANDROID_SDK_DIR=/home/hanjoung/ws/android-tools/sdk \
+    TFLITE_MODEL_PATH=/Users/hanjoung/ws/ghent/STAR/nnfw/tests/framework/cache/MODELS/mobilenet/mobilenet_v1_0.25_128.tflite \
+    ANDROID_BOOST_ROOT=/home/hanjoung/ws/gh/moritz-wundke/Boost-for-Android/build/out/arm64-v8a
+```
+
+And you will get `obj/contrib/android_benchmark_app/android-benchmark.unsigned.pkg`. This is an unsigned Android app package.
+
+## Sign APK
+
+Before installing the package you probably need to sign the package.
+
+- `apksigner` : This is in `build-tools` directory
+- Your keystore : How-to is TBD
+
+```bash
+apksigner sign \
+    --ks ~/.android/debug.keystore \
+    --in Product/aarch64-android.release/obj/contrib/android_benchmark_app/android-benchmark.unsigned.pkg \
+    --out tflbench.apk
+```
+
+You should enter the keystore password. Then you will get `tflbench.apk`.
+
+## Install APK
+
+```bash
+adb install tflbench.apk
+adb uninstall com.ndk.tflbench # To uninstall
+```
diff --git a/runtime/contrib/android_benchmark_app/cpp/ndk_main.cpp b/runtime/contrib/android_benchmark_app/cpp/ndk_main.cpp
new file mode 100644
index 000000000..f2ca1312c
--- /dev/null
+++ b/runtime/contrib/android_benchmark_app/cpp/ndk_main.cpp
@@ -0,0 +1,228 @@
+#include "ndk_main.h"
+
+#include "tensorflow/lite/kernels/register.h"
+#include "tensorflow/lite/model.h"
+
+#include "tflite/Assert.h"
+#include "tflite/Session.h"
+#include "tflite/InterpreterSession.h"
+#include "tflite/NNAPISession.h"
+#include "tflite/ext/kernels/register.h"
+
+#include "misc/benchmark.h"
+
+#include <boost/accumulators/accumulators.hpp>
+#include <boost/accumulators/statistics/stats.hpp>
+#include <boost/accumulators/statistics/mean.hpp>
+#include <boost/accumulators/statistics/min.hpp>
+#include <boost/accumulators/statistics/max.hpp>
+
+#include <cassert>
+#include <chrono>
+#include <sstream>
+
+#include <android/log.h>
+
+using namespace tflite;
+using namespace tflite::ops::builtin;
+
+static StderrReporter error_reporter;
+
+static std::unique_ptr<FlatBufferModel> model;
+
+inline void setText(JNIEnv *env, jobject thisObj, const std::string &message)
+{
+  jclass thisClass = env->GetObjectClass(thisObj);
+  jmethodID setTextMethod = env->GetMethodID(thisClass, "setText", "(Ljava/lang/String;)V");
+
+  assert(setTextMethod != nullptr);
+
+  env->CallVoidMethod(thisObj, setTextMethod, env->NewStringUTF(message.c_str()));
+}
+
+inline void setTitle(JNIEnv *env, jobject thisObj, const std::string &message)
+{
+  jclass thisClass = env->GetObjectClass(thisObj);
+  jmethodID setTextMethod = env->GetMethodID(thisClass, "setTitle", "(Ljava/lang/String;)V");
+
+  assert(setTextMethod != nullptr);
+
+  env->CallVoidMethod(thisObj, setTextMethod, env->NewStringUTF(message.c_str()));
+
+  // Clear message
+  setText(env, thisObj, "");
+}
+
+inline void setText(JNIEnv *env, jobject thisObj, const std::stringstream &ss)
+{
+  setText(env, thisObj, ss.str());
+}
+
+inline std::unique_ptr<FlatBufferModel> loadModel(JNIEnv *env, jobject thisObj,
+                                                  jobject model_buffer)
+{
+  const char *model_base = static_cast<char *>(env->GetDirectBufferAddress(model_buffer));
+  jlong model_size = env->GetDirectBufferCapacity(model_buffer);
+
+  return FlatBufferModel::BuildFromBuffer(model_base, static_cast<size_t>(model_size),
+                                          &error_reporter);
+}
+
+struct Activity
+{
+  virtual ~Activity() = default;
+
+  virtual void prepare(void) const = 0;
+  virtual void run(void) const = 0;
+  virtual void teardown(void) const = 0;
+};
+
+struct LiteActivity final : public Activity
+{
+public:
+  LiteActivity(nnfw::tflite::Session &sess) : _sess(sess)
+  {
+    // DO NOTHING
+  }
+
+public:
+  void prepare(void) const override { _sess.prepare(); }
+  void run(void) const override { _sess.run(); }
+  void teardown(void) const override { _sess.teardown(); }
+
+private:
+  nnfw::tflite::Session &_sess;
+};
+
+struct SimpleActivity final : public Activity
+{
+public:
+  SimpleActivity(const std::function<void(void)> &fn) : _fn{fn}
+  {
+    // DO NOTHING
+  }
+
+public:
+  void prepare(void) const override {}
+  void run(void) const override { _fn(); }
+  void teardown(void) const override {}
+
+private:
+  std::function<void(void)> _fn;
+};
+
+inline void runBenchmark(JNIEnv *env, jobject thisObj, Activity &act)
+{
+  auto runTrial = [&](void) {
+    std::chrono::milliseconds elapsed(0);
+
+    act.prepare();
+    nnfw::misc::benchmark::measure(elapsed) << [&](void) { act.run(); };
+    act.teardown();
+
+    return elapsed;
+  };
+
+  // Warm-up
+  for (uint32_t n = 0; n < 3; ++n)
+  {
+    auto elapsed = runTrial();
+
+    std::stringstream ss;
+    ss << "Warm-up #" << n << "  takes " << elapsed.count() << "ms" << std::endl;
+    setText(env, thisObj, ss);
+  }
+
+  // Measure
+  using namespace boost::accumulators;
+
+  accumulator_set<double, stats<tag::mean, tag::min, tag::max>> acc;
+
+  for (uint32_t n = 0; n < 100; ++n)
+  {
+    auto elapsed = runTrial();
+
+    std::stringstream ss;
+    ss << "Iteration #" << n << " takes " << elapsed.count() << "ms" << std::endl;
+    setText(env, thisObj, ss);
+
+    acc(elapsed.count());
+  }
+
+  std::stringstream ss;
+  ss << "Average is " << mean(acc) << "ms" << std::endl;
+  ss << "Min is " << min(acc) << "ms" << std::endl;
+  ss << "Max is " << max(acc) << "ms" << std::endl;
+  setText(env, thisObj, ss);
+}
+
+JNIEXPORT void JNICALL Java_com_ndk_tflbench_MainActivity_runInterpreterBenchmark(
+    JNIEnv *env, jobject thisObj, jobject model_buffer)
+{
+  setTitle(env, thisObj, "Running Interpreter Benchmark");
+
+  auto model = loadModel(env, thisObj, model_buffer);
+  assert(model != nullptr);
+
+  nnfw::tflite::BuiltinOpResolver resolver;
+  InterpreterBuilder builder(*model, resolver);
+
+  std::unique_ptr<Interpreter> interpreter;
+
+  TFLITE_ENSURE(builder(&interpreter));
+
+  interpreter->SetNumThreads(-1);
+
+  nnfw::tflite::InterpreterSession sess(interpreter.get());
+  LiteActivity act{sess};
+  runBenchmark(env, thisObj, act);
+}
+
+static void runNNAPIBenchmark(JNIEnv *env, jobject thisObj, jobject model_buffer)
+{
+  auto model = loadModel(env, thisObj, model_buffer);
+  assert(model != nullptr);
+
+  nnfw::tflite::BuiltinOpResolver resolver;
+  InterpreterBuilder builder(*model, resolver);
+
+  std::unique_ptr<Interpreter> interpreter;
+
+  TFLITE_ENSURE(builder(&interpreter));
+
+  nnfw::tflite::NNAPISession sess(interpreter.get());
+  LiteActivity act{sess};
+  runBenchmark(env, thisObj, act);
+}
+
+JNIEXPORT void JNICALL Java_com_ndk_tflbench_MainActivity_runNNAPIBenchmark(JNIEnv *env,
+                                                                            jobject thisObj,
+                                                                            jobject model_buffer)
+{
+  setTitle(env, thisObj, "Running NNAPI Benchmark");
+
+  try
+  {
+    runNNAPIBenchmark(env, thisObj, model_buffer);
+  }
+  catch (const std::exception &ex)
+  {
+    std::stringstream ss;
+    ss << "Caught an exception " << ex.what();
+    setText(env, thisObj, ss);
+  }
+}
+
+JNIEXPORT jstring JNICALL Java_com_ndk_tflbench_MainActivity_getModelName(JNIEnv *env,
+                                                                          jobject thisObj)
+{
+  return env->NewStringUTF(MODEL_NAME);
+}
+
+#define TF_ENSURE(e)                               \
+  {                                                \
+    if (!(e).ok())                                 \
+    {                                              \
+      throw std::runtime_error{"'" #e "' FAILED"}; \
+    }                                              \
+  }
diff --git a/runtime/contrib/android_benchmark_app/cpp/ndk_main.h b/runtime/contrib/android_benchmark_app/cpp/ndk_main.h
new file mode 100644
index 000000000..8de39ce9f
--- /dev/null
+++ b/runtime/contrib/android_benchmark_app/cpp/ndk_main.h
@@ -0,0 +1,92 @@
+/* DO NOT EDIT THIS FILE - it is machine generated */
+#include <jni.h>
+/* Header for class com_ndk_tflbench_MainActivity */
+
+#ifndef _Included_com_ndk_tflbench_MainActivity
+#define _Included_com_ndk_tflbench_MainActivity
+#ifdef __cplusplus
+extern "C" {
+#endif
+#undef com_ndk_tflbench_MainActivity_BIND_ABOVE_CLIENT
+#define com_ndk_tflbench_MainActivity_BIND_ABOVE_CLIENT 8L
+#undef com_ndk_tflbench_MainActivity_BIND_ADJUST_WITH_ACTIVITY
+#define com_ndk_tflbench_MainActivity_BIND_ADJUST_WITH_ACTIVITY 128L
+#undef com_ndk_tflbench_MainActivity_BIND_ALLOW_OOM_MANAGEMENT
+#define com_ndk_tflbench_MainActivity_BIND_ALLOW_OOM_MANAGEMENT 16L
+#undef com_ndk_tflbench_MainActivity_BIND_AUTO_CREATE
+#define com_ndk_tflbench_MainActivity_BIND_AUTO_CREATE 1L
+#undef com_ndk_tflbench_MainActivity_BIND_DEBUG_UNBIND
+#define com_ndk_tflbench_MainActivity_BIND_DEBUG_UNBIND 2L
+#undef com_ndk_tflbench_MainActivity_BIND_EXTERNAL_SERVICE
+#define com_ndk_tflbench_MainActivity_BIND_EXTERNAL_SERVICE -2147483648L
+#undef com_ndk_tflbench_MainActivity_BIND_IMPORTANT
+#define com_ndk_tflbench_MainActivity_BIND_IMPORTANT 64L
+#undef com_ndk_tflbench_MainActivity_BIND_NOT_FOREGROUND
+#define com_ndk_tflbench_MainActivity_BIND_NOT_FOREGROUND 4L
+#undef com_ndk_tflbench_MainActivity_BIND_WAIVE_PRIORITY
+#define com_ndk_tflbench_MainActivity_BIND_WAIVE_PRIORITY 32L
+#undef com_ndk_tflbench_MainActivity_CONTEXT_IGNORE_SECURITY
+#define com_ndk_tflbench_MainActivity_CONTEXT_IGNORE_SECURITY 2L
+#undef com_ndk_tflbench_MainActivity_CONTEXT_INCLUDE_CODE
+#define com_ndk_tflbench_MainActivity_CONTEXT_INCLUDE_CODE 1L
+#undef com_ndk_tflbench_MainActivity_CONTEXT_RESTRICTED
+#define com_ndk_tflbench_MainActivity_CONTEXT_RESTRICTED 4L
+#undef com_ndk_tflbench_MainActivity_MODE_APPEND
+#define com_ndk_tflbench_MainActivity_MODE_APPEND 32768L
+#undef com_ndk_tflbench_MainActivity_MODE_ENABLE_WRITE_AHEAD_LOGGING
+#define com_ndk_tflbench_MainActivity_MODE_ENABLE_WRITE_AHEAD_LOGGING 8L
+#undef com_ndk_tflbench_MainActivity_MODE_MULTI_PROCESS
+#define com_ndk_tflbench_MainActivity_MODE_MULTI_PROCESS 4L
+#undef com_ndk_tflbench_MainActivity_MODE_NO_LOCALIZED_COLLATORS
+#define com_ndk_tflbench_MainActivity_MODE_NO_LOCALIZED_COLLATORS 16L
+#undef com_ndk_tflbench_MainActivity_MODE_PRIVATE
+#define com_ndk_tflbench_MainActivity_MODE_PRIVATE 0L
+#undef com_ndk_tflbench_MainActivity_MODE_WORLD_READABLE
+#define com_ndk_tflbench_MainActivity_MODE_WORLD_READABLE 1L
+#undef com_ndk_tflbench_MainActivity_MODE_WORLD_WRITEABLE
+#define com_ndk_tflbench_MainActivity_MODE_WORLD_WRITEABLE 2L
+#undef com_ndk_tflbench_MainActivity_RECEIVER_VISIBLE_TO_INSTANT_APPS
+#define com_ndk_tflbench_MainActivity_RECEIVER_VISIBLE_TO_INSTANT_APPS 1L
+#undef com_ndk_tflbench_MainActivity_DEFAULT_KEYS_DIALER
+#define com_ndk_tflbench_MainActivity_DEFAULT_KEYS_DIALER 1L
+#undef com_ndk_tflbench_MainActivity_DEFAULT_KEYS_DISABLE
+#define com_ndk_tflbench_MainActivity_DEFAULT_KEYS_DISABLE 0L
+#undef com_ndk_tflbench_MainActivity_DEFAULT_KEYS_SEARCH_GLOBAL
+#define com_ndk_tflbench_MainActivity_DEFAULT_KEYS_SEARCH_GLOBAL 4L
+#undef com_ndk_tflbench_MainActivity_DEFAULT_KEYS_SEARCH_LOCAL
+#define com_ndk_tflbench_MainActivity_DEFAULT_KEYS_SEARCH_LOCAL 3L
+#undef com_ndk_tflbench_MainActivity_DEFAULT_KEYS_SHORTCUT
+#define com_ndk_tflbench_MainActivity_DEFAULT_KEYS_SHORTCUT 2L
+#undef com_ndk_tflbench_MainActivity_RESULT_CANCELED
+#define com_ndk_tflbench_MainActivity_RESULT_CANCELED 0L
+#undef com_ndk_tflbench_MainActivity_RESULT_FIRST_USER
+#define com_ndk_tflbench_MainActivity_RESULT_FIRST_USER 1L
+#undef com_ndk_tflbench_MainActivity_RESULT_OK
+#define com_ndk_tflbench_MainActivity_RESULT_OK -1L
+/*
+ * Class:     com_ndk_tflbench_MainActivity
+ * Method:    getModelName
+ * Signature: ()Ljava/lang/String;
+ */
+JNIEXPORT jstring JNICALL Java_com_ndk_tflbench_MainActivity_getModelName(JNIEnv *, jobject);
+
+/*
+ * Class:     com_ndk_tflbench_MainActivity
+ * Method:    runInterpreterBenchmark
+ * Signature: (Ljava/nio/MappedByteBuffer;)V
+ */
+JNIEXPORT void JNICALL Java_com_ndk_tflbench_MainActivity_runInterpreterBenchmark(JNIEnv *, jobject,
+                                                                                  jobject);
+
+/*
+ * Class:     com_ndk_tflbench_MainActivity
+ * Method:    runNNAPIBenchmark
+ * Signature: (Ljava/nio/MappedByteBuffer;)V
+ */
+JNIEXPORT void JNICALL Java_com_ndk_tflbench_MainActivity_runNNAPIBenchmark(JNIEnv *, jobject,
+                                                                            jobject);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/runtime/contrib/android_benchmark_app/java/com/ndk/tflbench/MainActivity.java b/runtime/contrib/android_benchmark_app/java/com/ndk/tflbench/MainActivity.java
new file mode 100644
index 000000000..14bf239a6
--- /dev/null
+++ b/runtime/contrib/android_benchmark_app/java/com/ndk/tflbench/MainActivity.java
@@ -0,0 +1,110 @@
+package com.ndk.tflbench;
+
+import android.app.Activity;
+import android.os.Bundle;
+import android.content.Intent;
+import android.view.View;
+import android.view.Menu;
+import android.view.MenuItem;
+import android.widget.TextView;
+import android.widget.Button;
+import android.net.Uri;
+import android.content.res.AssetFileDescriptor;
+import android.content.res.AssetManager;
+import android.graphics.Bitmap;
+import android.os.SystemClock;
+import android.os.Trace;
+import android.util.Log;
+import java.io.BufferedReader;
+import java.io.FileInputStream;
+import java.io.IOException;
+import java.io.InputStreamReader;
+import java.nio.ByteBuffer;
+import java.nio.ByteOrder;
+import java.nio.MappedByteBuffer;
+import java.nio.channels.FileChannel;
+import java.util.ArrayList;
+import java.util.Comparator;
+import java.util.List;
+import java.util.PriorityQueue;
+import java.util.Vector;
+
+public class MainActivity extends Activity {
+
+  static {
+    System.loadLibrary("android_benchmark_native");
+  }
+
+  private void setModel(final String message) {
+    final TextView textView = (TextView)findViewById(R.id.model_label);
+    runOnUiThread(new Runnable() {
+      @Override
+      public void run() { textView.setText(message); }
+    });
+  }
+
+  private void setTitle(final String message) {
+    final TextView textView = (TextView)findViewById(R.id.title_label);
+    runOnUiThread(new Runnable() {
+      @Override
+      public void run() { textView.setText(message); }
+    });
+  }
+
+  private void setText(final String message) {
+    final TextView textView = (TextView)findViewById(R.id.message_label);
+    runOnUiThread(new Runnable() {
+      @Override
+      public void run() { textView.setText(message); }
+    });
+  }
+
+  private MappedByteBuffer buffer;
+
+  @Override
+  protected void onCreate(Bundle savedInstanceState) {
+    super.onCreate(savedInstanceState);
+    setContentView(R.layout.activity_main);
+
+    setModel(getModelName());
+
+    // Load Tensorflow Lite model
+    try
+    {
+      AssetManager assets = getAssets();
+      AssetFileDescriptor fileDescriptor = assets.openFd("model.tflite");
+      FileInputStream inputStream = new FileInputStream(fileDescriptor.getFileDescriptor());
+      FileChannel fileChannel = inputStream.getChannel();
+      final long startOffset = fileDescriptor.getStartOffset();
+      final long declaredLength = fileDescriptor.getDeclaredLength();
+
+      buffer = fileChannel.map(FileChannel.MapMode.READ_ONLY, startOffset, declaredLength);
+    } catch (IOException e) {
+      Log.e("MYAPP", "exception", e);
+    }
+
+    Button btn_interp = (Button)findViewById(R.id.button_interp);
+    btn_interp.setOnClickListener(new Button.OnClickListener() {
+      @Override public void onClick(View view) {
+        new Thread(new Runnable() {
+          @Override
+          public void run() { runInterpreterBenchmark(buffer); }
+        }).start();
+      }
+    });
+
+    Button btn_nnapi = (Button)findViewById(R.id.button_nnapi);
+    btn_nnapi.setOnClickListener(new Button.OnClickListener() {
+      @Override public void onClick(View view) {
+        new Thread(new Runnable() {
+          @Override
+          public void run() { runNNAPIBenchmark(buffer); }
+        }).start();
+      }
+    });
+  }
+
+  public native String getModelName();
+  public native void runInterpreterBenchmark(MappedByteBuffer buffer);
+  public native void runNNAPIBenchmark(MappedByteBuffer buffer);
+}
diff --git a/runtime/contrib/android_benchmark_app/res/drawable-hdpi/ic_launcher.png b/runtime/contrib/android_benchmark_app/res/drawable-hdpi/ic_launcher.png
new file mode 100644
index 000000000..96a442e5b
--- /dev/null
+++ b/runtime/contrib/android_benchmark_app/res/drawable-hdpi/ic_launcher.png
diff --git a/runtime/contrib/android_benchmark_app/res/drawable-mdpi/ic_launcher.png b/runtime/contrib/android_benchmark_app/res/drawable-mdpi/ic_launcher.png
new file mode 100644
index 000000000..359047dfa
--- /dev/null
+++ b/runtime/contrib/android_benchmark_app/res/drawable-mdpi/ic_launcher.png
diff --git a/runtime/contrib/android_benchmark_app/res/drawable-xhdpi/ic_launcher.png b/runtime/contrib/android_benchmark_app/res/drawable-xhdpi/ic_launcher.png
new file mode 100644
index 000000000..71c6d760f
--- /dev/null
+++ b/runtime/contrib/android_benchmark_app/res/drawable-xhdpi/ic_launcher.png
diff --git a/runtime/contrib/android_benchmark_app/res/drawable-xxhdpi/ic_launcher.png b/runtime/contrib/android_benchmark_app/res/drawable-xxhdpi/ic_launcher.png
new file mode 100644
index 000000000..4df189464
--- /dev/null
+++ b/runtime/contrib/android_benchmark_app/res/drawable-xxhdpi/ic_launcher.png
diff --git a/runtime/contrib/android_benchmark_app/res/layout/activity_main.xml b/runtime/contrib/android_benchmark_app/res/layout/activity_main.xml
new file mode 100644
index 000000000..551952582
--- /dev/null
+++ b/runtime/contrib/android_benchmark_app/res/layout/activity_main.xml
@@ -0,0 +1,38 @@
+<LinearLayout xmlns:android="http://schemas.android.com/apk/res/android"
+  xmlns:tools="http://schemas.android.com/tools"
+  android:layout_width="match_parent"
+  android:layout_height="match_parent"
+  android:orientation="vertical">
+
+  <Button android:layout_width="match_parent"
+          android:layout_height="wrap_content"
+          android:id="@+id/button_interp"
+          android:text="Run Interp benchmark"/>
+
+  <Button android:layout_width="match_parent"
+          android:layout_height="wrap_content"
+          android:id="@+id/button_nnapi"
+          android:text="Run NNAPI benchmark"/>
+
+  <TextView android:text=""
+            android:layout_width="match_parent"
+            android:layout_height="wrap_content"
+            android:id="@+id/model_label"
+            android:layout_centerHorizontal="true"
+            android:textSize="16dp"/>
+
+  <TextView android:text=""
+            android:layout_width="match_parent"
+            android:layout_height="wrap_content"
+            android:id="@+id/title_label"
+            android:layout_centerHorizontal="true"
+            android:textSize="16dp"/>
+
+  <TextView android:text=""
+            android:layout_width="match_parent"
+            android:layout_height="wrap_content"
+            android:id="@+id/message_label"
+            android:layout_centerHorizontal="true"
+            android:textSize="16dp"/>
+
+</LinearLayout>
diff --git a/runtime/contrib/android_benchmark_app/res/values-v21/styles.xml b/runtime/contrib/android_benchmark_app/res/values-v21/styles.xml
new file mode 100644
index 000000000..dba3c417b
--- /dev/null
+++ b/runtime/contrib/android_benchmark_app/res/values-v21/styles.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" encoding="utf-8"?>
+<resources>
+    <style name="AppTheme" parent="android:Theme.Material.Light">
+    </style>
+</resources>
diff --git a/runtime/contrib/android_benchmark_app/res/values/strings.xml b/runtime/contrib/android_benchmark_app/res/values/strings.xml
new file mode 100644
index 000000000..3c6c4aaa4
--- /dev/null
+++ b/runtime/contrib/android_benchmark_app/res/values/strings.xml
@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="utf-8"?>
+<resources>
+
+  <string name="app_name">T/F Lite Benchmark</string>
+
+</resources>
diff --git a/runtime/contrib/android_tflite/CMakeLists.txt b/runtime/contrib/android_tflite/CMakeLists.txt
new file mode 100644
index 000000000..b65a7c525
--- /dev/null
+++ b/runtime/contrib/android_tflite/CMakeLists.txt
@@ -0,0 +1,31 @@
+if(NOT BUILD_ANDROID_TFLITE)
+  return()
+endif(NOT BUILD_ANDROID_TFLITE)
+
+nnfw_find_package(TensorFlowLite REQUIRED)
+
+if(NOT DEFINED NDK_DIR)
+  message(FATAL_ERROR "NDK_DIR should be specified via environment variable")
+endif()
+message(STATUS "Found NDK: ${NDK_DIR}")
+
+#
+# Tensorflow Lite JNI library
+#
+set(TENSORFLOW_LITE_BASE "${TensorFlowSource_DIR}/tensorflow/lite")
+set(TFLITE_JNI_BASE ${TENSORFLOW_LITE_BASE}/java/src/main/native)
+set(TFLITE_JNI_SRCS ${TFLITE_JNI_BASE}/exception_jni.cc
+                    ${TFLITE_JNI_BASE}/nativeinterpreterwrapper_jni.cc
+                    ${TFLITE_JNI_BASE}/tensor_jni.cc
+                    ${TFLITE_JNI_BASE}/tensorflow_lite_jni.cc
+                    ${CMAKE_CURRENT_SOURCE_DIR}/builtin_ops_jni.cc # Use nnfw's OpResolver
+                    )
+set(TFLITE_JNI_INCLUDES ${TENSORFLOW_LITE_BASE}/java/src/native)
+
+# TODO use tensorflow-lite static library instead of compiling all the sources again
+add_library(tensorflowlite_jni SHARED ${TFLITE_JNI_SRCS} ${TFLITE_SRCS})
+target_include_directories(tensorflowlite_jni PUBLIC ${TFLITE_JNI_INCLUDES} ${TFLITE_INCLUDES})
+target_link_libraries(tensorflowlite_jni eigen ${LIB_PTHREAD} dl)
+target_link_libraries(tensorflowlite_jni log)
+target_link_libraries(tensorflowlite_jni nnfw_lib_tflite)
+install(TARGETS tensorflowlite_jni DESTINATION lib)
diff --git a/runtime/contrib/android_tflite/builtin_ops_jni.cc b/runtime/contrib/android_tflite/builtin_ops_jni.cc
new file mode 100644
index 000000000..af9d3325d
--- /dev/null
+++ b/runtime/contrib/android_tflite/builtin_ops_jni.cc
@@ -0,0 +1,29 @@
+/* Copyright 2017 The TensorFlow Authors. All Rights Reserved.
+   Copyright 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+==============================================================================*/
+
+#include "tensorflow/lite/kernels/register.h"
+#include "tflite/ext/kernels/register.h"
+
+namespace tflite
+{
+
+std::unique_ptr<OpResolver> CreateOpResolver()
+{
+  return std::unique_ptr<::nnfw::tflite::BuiltinOpResolver>(
+      new ::nnfw::tflite::BuiltinOpResolver());
+}
+
+} // namespace tflite
diff --git a/runtime/contrib/benchmark_acl/.FORMATDENY b/runtime/contrib/benchmark_acl/.FORMATDENY
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/runtime/contrib/benchmark_acl/.FORMATDENY
diff --git a/runtime/contrib/benchmark_acl/CMakeLists.txt b/runtime/contrib/benchmark_acl/CMakeLists.txt
new file mode 100644
index 000000000..528db4142
--- /dev/null
+++ b/runtime/contrib/benchmark_acl/CMakeLists.txt
@@ -0,0 +1,24 @@
+if(NOT BUILD_BENCHMARK_ACL)
+  return()
+endif(NOT BUILD_BENCHMARK_ACL)
+
+nnas_find_package(ARMCompute REQUIRED)
+
+add_library(arm_compute_benchmark SHARED "src/Benchmark.cpp")
+target_include_directories(arm_compute_benchmark PUBLIC ${CMAKE_CURRENT_SOURCE_DIR})
+target_link_libraries(arm_compute_benchmark arm_compute_graph)
+install(TARGETS arm_compute_benchmark DESTINATION lib)
+
+# GoogLeNet benchmark
+add_executable(benchmark_googlenet "src/benchmark_googlenet.cpp")
+target_link_libraries(benchmark_googlenet arm_compute_benchmark)
+
+# GoogLeNet benchmark
+add_executable(benchmark_inception_v3 "src/benchmark_inception_v3.cpp")
+target_link_libraries(benchmark_inception_v3 arm_compute_benchmark)
+
+# MobileNet benchmark
+add_executable(benchmark_mobilenet "src/benchmark_mobilenet.cpp")
+target_link_libraries(benchmark_mobilenet arm_compute_benchmark)
+
+install(TARGETS benchmark_googlenet benchmark_inception_v3 benchmark_mobilenet DESTINATION bin)
diff --git a/runtime/contrib/benchmark_acl/src/Benchmark.cpp b/runtime/contrib/benchmark_acl/src/Benchmark.cpp
new file mode 100644
index 000000000..4a761ec76
--- /dev/null
+++ b/runtime/contrib/benchmark_acl/src/Benchmark.cpp
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "Benchmark.h"
+
+#include <cstdlib>
+
+Count::Count() : _value(1)
+{
+  auto env = std::getenv("COUNT");
+
+  if (env)
+  {
+    _value = std::strtol(env, NULL, 0);
+  }
+}
+
+uint32_t Count::value(void) const { return _value; }
+
+#include <boost/accumulators/accumulators.hpp>
+#include <boost/accumulators/statistics/stats.hpp>
+#include <boost/accumulators/statistics/mean.hpp>
+
+#include <iostream>
+#include <chrono>
+
+using namespace boost::accumulators;
+
+void run_benchmark(arm_compute::graph::frontend::Stream &graph)
+{
+  // NOTE Here the number of warming-up iterations is hardcoded
+  // TODO Decide the number of warming-up iterations appropriately
+  for (uint32_t n = 0; n < 3; ++n)
+  {
+    auto beg = std::chrono::steady_clock::now();
+    graph.run();
+    auto end = std::chrono::steady_clock::now();
+    auto elapsed = std::chrono::duration_cast<std::chrono::milliseconds>(end - beg);
+
+    std::cout << "Warming-up " << n << ": " << elapsed.count() << "ms" << std::endl;
+  }
+
+  accumulator_set<double, stats<tag::mean>> acc;
+
+  const Count count;
+
+  for (uint32_t n = 0; n < count.value(); ++n)
+  {
+    auto beg = std::chrono::steady_clock::now();
+    graph.run();
+    auto end = std::chrono::steady_clock::now();
+    auto elapsed = std::chrono::duration_cast<std::chrono::milliseconds>(end - beg);
+
+    std::cout << "Iteration " << n << ": " << elapsed.count() << "ms" << std::endl;
+
+    acc(elapsed.count());
+  }
+
+  std::cout << "--------" << std::endl;
+  std::cout << "Mean: " << mean(acc) << "ms" << std::endl;
+}
diff --git a/runtime/contrib/benchmark_acl/src/Benchmark.h b/runtime/contrib/benchmark_acl/src/Benchmark.h
new file mode 100644
index 000000000..200f40952
--- /dev/null
+++ b/runtime/contrib/benchmark_acl/src/Benchmark.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __ACL_BENCHMARK_H__
+#define __ACL_BENCHMARK_H__
+
+#include "arm_compute/graph/ITensorAccessor.h"
+#include "arm_compute/graph.h"
+#include "arm_compute/core/CL/OpenCL.h"
+
+struct InputAccessor final : public arm_compute::graph::ITensorAccessor
+{
+    InputAccessor() = default;
+    /** Allows instances to move constructed */
+    InputAccessor(InputAccessor &&) = default;
+
+    // Inherited methods overriden:
+    bool access_tensor(arm_compute::ITensor &tensor) override
+    {
+      return true;
+    }
+};
+
+struct OutputAccessor final : public arm_compute::graph::ITensorAccessor
+{
+    OutputAccessor() = default;
+    /** Allows instances to move constructed */
+    OutputAccessor(OutputAccessor &&) = default;
+
+    // Inherited methods overriden:
+    bool access_tensor(arm_compute::ITensor &tensor) override
+    {
+      return false;
+    }
+};
+
+template <typename T> std::unique_ptr<arm_compute::graph::ITensorAccessor> get_accessor()
+{
+  return std::unique_ptr<T>(new T());
+}
+
+class Count
+{
+public:
+  Count();
+
+public:
+  uint32_t value(void) const;
+
+private:
+  uint32_t _value;
+};
+
+inline arm_compute::graph::Target set_target_hint(int target)
+{
+    if(target == 1 && arm_compute::opencl_is_available())
+    {
+        // If type of target is OpenCL, check if OpenCL is available and initialize the scheduler
+        return arm_compute::graph::Target::CL;
+    }
+    else
+    {
+        return arm_compute::graph::Target::NEON;
+    }
+}
+
+void run_benchmark(arm_compute::graph::frontend::Stream &graph);
+
+#endif
diff --git a/runtime/contrib/benchmark_acl/src/benchmark_googlenet.cpp b/runtime/contrib/benchmark_acl/src/benchmark_googlenet.cpp
new file mode 100644
index 000000000..8b0fbfdac
--- /dev/null
+++ b/runtime/contrib/benchmark_acl/src/benchmark_googlenet.cpp
@@ -0,0 +1,242 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ * Copyright (c) 2017 ARM Limited.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "arm_compute/graph.h"
+
+#include "Benchmark.h"
+
+#include <cstdlib>
+#include <tuple>
+
+using namespace arm_compute::graph::frontend;
+
+inline std::unique_ptr<arm_compute::graph::ITensorAccessor> get_input_accessor(void)
+{
+    return get_accessor<InputAccessor>();
+}
+
+inline std::unique_ptr<arm_compute::graph::ITensorAccessor> get_random_accessor(float lower, float upper)
+{
+    return get_accessor<InputAccessor>();
+}
+
+inline std::unique_ptr<arm_compute::graph::ITensorAccessor> get_weights_accessor(const std::string &path, const std::string &data_file, DataLayout file_layout = DataLayout::NCHW)
+{
+    return get_accessor<InputAccessor>();
+}
+
+inline std::unique_ptr<arm_compute::graph::ITensorAccessor> get_output_accessor(void)
+{
+    return get_accessor<OutputAccessor>();
+}
+
+/** Example demonstrating how to implement Googlenet's network using the Compute Library's graph API
+ *
+ * @param[in] argc Number of arguments
+ * @param[in] argv Arguments ( [optional] Target (0 = NEON, 1 = OpenCL, 2 = OpenCL with Tuner), [optional] Path to the weights folder, [optional] image, [optional] labels, [optional] Fast math for convolution layer (0 = DISABLED, 1 = ENABLED) )
+ */
+class GraphGooglenetExample
+{
+public:
+    void do_setup(int argc, char **argv)
+    {
+        std::string data_path; /* Path to the trainable data */
+        std::string image;     /* Image data */
+        std::string label;     /* Label data */
+
+        const std::array<float, 3> mean_rgb{ { 122.68f, 116.67f, 104.01f } };
+        // Set target. 0 (NEON), 1 (OpenCL), 2 (OpenCL with Tuner). By default it is NEON
+        const int    target         = argc > 1 ? std::strtol(argv[1], nullptr, 10) : 0;
+        Target       target_hint    = set_target_hint(target);
+        FastMathHint fast_math_hint = FastMathHint::Disabled;
+
+        // Parse arguments
+        if(argc < 2)
+        {
+            // Print help
+            std::cout << "Usage: " << argv[0] << " [target] [path_to_data] [image] [labels] [fast_math_hint]\n\n";
+            std::cout << "No data folder provided: using random values\n\n";
+        }
+        else if(argc == 2)
+        {
+            std::cout << "Usage: " << argv[0] << " " << argv[1] << " [path_to_data] [image] [labels] [fast_math_hint]\n\n";
+            std::cout << "No data folder provided: using random values\n\n";
+        }
+        else if(argc == 3)
+        {
+            data_path = argv[2];
+            std::cout << "Usage: " << argv[0] << " " << argv[1] << " " << argv[2] << " [image] [labels] [fast_math_hint]\n\n";
+            std::cout << "No image provided: using random values\n\n";
+        }
+        else if(argc == 4)
+        {
+            data_path = argv[2];
+            image     = argv[3];
+            std::cout << "Usage: " << argv[0] << " " << argv[1] << " " << argv[2] << " " << argv[3] << " [labels] [fast_math_hint]\n\n";
+            std::cout << "No text file with labels provided: skipping output accessor\n\n";
+        }
+        else if(argc == 5)
+        {
+            data_path = argv[2];
+            image     = argv[3];
+            label     = argv[4];
+            std::cout << "Usage: " << argv[0] << " " << argv[1] << " " << argv[2] << " " << argv[3] << " " << argv[4] << " [fast_math_hint]\n\n";
+            std::cout << "No fast math info provided: disabling fast math\n\n";
+        }
+        else
+        {
+            data_path      = argv[2];
+            image          = argv[3];
+            label          = argv[4];
+            fast_math_hint = (std::strtol(argv[5], nullptr, 1) == 0) ? FastMathHint::Disabled : FastMathHint::Enabled;
+        }
+
+        graph << target_hint
+              << fast_math_hint
+              << InputLayer(TensorDescriptor(TensorShape(224U, 224U, 3U, 1U), DataType::F32),
+                             get_input_accessor())
+              << ConvolutionLayer(
+                  7U, 7U, 64U,
+                  get_weights_accessor(data_path, "/cnn_data/googlenet_model/conv1/conv1_7x7_s2_w.npy"),
+                  get_weights_accessor(data_path, "/cnn_data/googlenet_model/conv1/conv1_7x7_s2_b.npy"),
+                  PadStrideInfo(2, 2, 3, 3))
+              << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU))
+              << PoolingLayer(PoolingLayerInfo(PoolingType::MAX, 3, PadStrideInfo(2, 2, 0, 0, DimensionRoundingType::CEIL)))
+              << NormalizationLayer(NormalizationLayerInfo(NormType::CROSS_MAP, 5, 0.0001f, 0.75f))
+              << ConvolutionLayer(
+                  1U, 1U, 64U,
+                  get_weights_accessor(data_path, "/cnn_data/googlenet_model/conv2/conv2_3x3_reduce_w.npy"),
+                  get_weights_accessor(data_path, "/cnn_data/googlenet_model/conv2/conv2_3x3_reduce_b.npy"),
+                  PadStrideInfo(1, 1, 0, 0))
+              << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU))
+              << ConvolutionLayer(
+                  3U, 3U, 192U,
+                  get_weights_accessor(data_path, "/cnn_data/googlenet_model/conv2/conv2_3x3_w.npy"),
+                  get_weights_accessor(data_path, "/cnn_data/googlenet_model/conv2/conv2_3x3_b.npy"),
+                  PadStrideInfo(1, 1, 1, 1))
+              << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU))
+              << NormalizationLayer(NormalizationLayerInfo(NormType::CROSS_MAP, 5, 0.0001f, 0.75f))
+              << PoolingLayer(PoolingLayerInfo(PoolingType::MAX, 3, PadStrideInfo(2, 2, 0, 0, DimensionRoundingType::CEIL)));
+        graph << get_inception_node(data_path, "inception_3a", 64, std::make_tuple(96U, 128U), std::make_tuple(16U, 32U), 32U);
+        graph << get_inception_node(data_path, "inception_3b", 128, std::make_tuple(128U, 192U), std::make_tuple(32U, 96U), 64U);
+        graph << PoolingLayer(PoolingLayerInfo(PoolingType::MAX, 3, PadStrideInfo(2, 2, 0, 0, DimensionRoundingType::CEIL)));
+        graph << get_inception_node(data_path, "inception_4a", 192, std::make_tuple(96U, 208U), std::make_tuple(16U, 48U), 64U);
+        graph << get_inception_node(data_path, "inception_4b", 160, std::make_tuple(112U, 224U), std::make_tuple(24U, 64U), 64U);
+        graph << get_inception_node(data_path, "inception_4c", 128, std::make_tuple(128U, 256U), std::make_tuple(24U, 64U), 64U);
+        graph << get_inception_node(data_path, "inception_4d", 112, std::make_tuple(144U, 288U), std::make_tuple(32U, 64U), 64U);
+        graph << get_inception_node(data_path, "inception_4e", 256, std::make_tuple(160U, 320U), std::make_tuple(32U, 128U), 128U);
+        graph << PoolingLayer(PoolingLayerInfo(PoolingType::MAX, 3, PadStrideInfo(2, 2, 0, 0, DimensionRoundingType::CEIL)));
+        graph << get_inception_node(data_path, "inception_5a", 256, std::make_tuple(160U, 320U), std::make_tuple(32U, 128U), 128U);
+        graph << get_inception_node(data_path, "inception_5b", 384, std::make_tuple(192U, 384U), std::make_tuple(48U, 128U), 128U);
+        graph << PoolingLayer(PoolingLayerInfo(PoolingType::AVG, 7, PadStrideInfo(1, 1, 0, 0, DimensionRoundingType::CEIL)))
+              << FullyConnectedLayer(
+                  1000U,
+                  get_weights_accessor(data_path, "/cnn_data/googlenet_model/loss3/loss3_classifier_w.npy"),
+                  get_weights_accessor(data_path, "/cnn_data/googlenet_model/loss3/loss3_classifier_b.npy"))
+              << SoftmaxLayer()
+              << OutputLayer(get_output_accessor());
+
+        // Finalize graph
+        GraphConfig config;
+        config.use_tuner = (target == 2);
+        graph.finalize(target_hint, config);
+    }
+    void do_run()
+    {
+        run_benchmark(graph);
+    }
+
+private:
+    Stream graph{ 0, "GoogleNet" };
+
+    ConcatLayer get_inception_node(const std::string &data_path, std::string &&param_path,
+                                   unsigned int a_filt,
+                                   std::tuple<unsigned int, unsigned int> b_filters,
+                                   std::tuple<unsigned int, unsigned int> c_filters,
+                                   unsigned int d_filt)
+    {
+        std::string total_path = "/cnn_data/googlenet_model/" + param_path + "/" + param_path + "_";
+        SubStream   i_a(graph);
+        i_a << ConvolutionLayer(
+                1U, 1U, a_filt,
+                get_weights_accessor(data_path, total_path + "1x1_w.npy"),
+                get_weights_accessor(data_path, total_path + "1x1_b.npy"),
+                PadStrideInfo(1, 1, 0, 0))
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU));
+
+        SubStream i_b(graph);
+        i_b << ConvolutionLayer(
+                1U, 1U, std::get<0>(b_filters),
+                get_weights_accessor(data_path, total_path + "3x3_reduce_w.npy"),
+                get_weights_accessor(data_path, total_path + "3x3_reduce_b.npy"),
+                PadStrideInfo(1, 1, 0, 0))
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU))
+            << ConvolutionLayer(
+                3U, 3U, std::get<1>(b_filters),
+                get_weights_accessor(data_path, total_path + "3x3_w.npy"),
+                get_weights_accessor(data_path, total_path + "3x3_b.npy"),
+                PadStrideInfo(1, 1, 1, 1))
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU));
+
+        SubStream i_c(graph);
+        i_c << ConvolutionLayer(
+                1U, 1U, std::get<0>(c_filters),
+                get_weights_accessor(data_path, total_path + "5x5_reduce_w.npy"),
+                get_weights_accessor(data_path, total_path + "5x5_reduce_b.npy"),
+                PadStrideInfo(1, 1, 0, 0))
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU))
+            << ConvolutionLayer(
+                5U, 5U, std::get<1>(c_filters),
+                get_weights_accessor(data_path, total_path + "5x5_w.npy"),
+                get_weights_accessor(data_path, total_path + "5x5_b.npy"),
+                PadStrideInfo(1, 1, 2, 2))
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU));
+
+        SubStream i_d(graph);
+        i_d << PoolingLayer(PoolingLayerInfo(PoolingType::MAX, 3, PadStrideInfo(1, 1, 1, 1, DimensionRoundingType::CEIL)))
+            << ConvolutionLayer(
+                1U, 1U, d_filt,
+                get_weights_accessor(data_path, total_path + "pool_proj_w.npy"),
+                get_weights_accessor(data_path, total_path + "pool_proj_b.npy"),
+                PadStrideInfo(1, 1, 0, 0))
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU));
+
+        return ConcatLayer(std::move(i_a), std::move(i_b), std::move(i_c), std::move(i_d));
+    }
+};
+
+/** Main program for Googlenet
+ *
+ * @param[in] argc Number of arguments
+ * @param[in] argv Arguments ( [optional] Target (0 = NEON, 1 = OpenCL, 2 = OpenCL with Tuner), [optional] Path to the weights folder, [optional] image, [optional] labels, [optional] Fast math for convolution layer (0 = DISABLED, 1 = ENABLED) )
+ */
+int main(int argc, char **argv)
+{
+    GraphGooglenetExample example;
+
+    example.do_setup(argc, argv);
+    example.do_run();
+
+    return 0;
+}
diff --git a/runtime/contrib/benchmark_acl/src/benchmark_inception_v3.cpp b/runtime/contrib/benchmark_acl/src/benchmark_inception_v3.cpp
new file mode 100644
index 000000000..382851f50
--- /dev/null
+++ b/runtime/contrib/benchmark_acl/src/benchmark_inception_v3.cpp
@@ -0,0 +1,891 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ * Copyright (c) 2017-2018 ARM Limited.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "arm_compute/graph.h"
+
+#include "Benchmark.h"
+
+#include <cstdlib>
+#include <tuple>
+
+using namespace arm_compute::graph::frontend;
+
+inline std::unique_ptr<arm_compute::graph::ITensorAccessor> get_input_accessor(void)
+{
+    return get_accessor<InputAccessor>();
+}
+
+inline std::unique_ptr<arm_compute::graph::ITensorAccessor> get_random_accessor(float lower, float upper)
+{
+    return get_accessor<InputAccessor>();
+}
+
+inline std::unique_ptr<arm_compute::graph::ITensorAccessor> get_weights_accessor(const std::string &path, const std::string &data_file, DataLayout file_layout = DataLayout::NCHW)
+{
+    return get_accessor<InputAccessor>();
+}
+
+inline std::unique_ptr<arm_compute::graph::ITensorAccessor> get_output_accessor(void)
+{
+    return get_accessor<OutputAccessor>();
+}
+
+/** Example demonstrating how to implement InceptionV3's network using the Compute Library's graph API
+ *
+ * @param[in] argc Number of arguments
+ * @param[in] argv Arguments ( [optional] Target (0 = NEON, 1 = OpenCL, 2 = OpenCL with Tuner), [optional] Path to the weights folder, [optional] image, [optional] labels )
+ */
+class InceptionV3Example
+{
+public:
+    void do_setup(int argc, char **argv)
+    {
+        std::string data_path; /* Path to the trainable data */
+        std::string image;     /* Image data */
+        std::string label;     /* Label data */
+
+        // Set target. 0 (NEON), 1 (OpenCL), 2 (OpenCL with Tuner). By default it is NEON
+        const int    target         = argc > 1 ? std::strtol(argv[1], nullptr, 10) : 0;
+        Target       target_hint    = set_target_hint(target);
+        FastMathHint fast_math_hint = FastMathHint::Disabled;
+
+        // Parse arguments
+        if(argc < 2)
+        {
+            // Print help
+            std::cout << "Usage: " << argv[0] << " [target] [path_to_data] [image] [labels] [fast_math_hint]\n\n";
+            std::cout << "No data folder provided: using random values\n\n";
+        }
+        else if(argc == 2)
+        {
+            std::cout << "Usage: " << argv[0] << " " << argv[1] << " [path_to_data] [image] [labels] [fast_math_hint]\n\n";
+            std::cout << "No data folder provided: using random values\n\n";
+        }
+        else if(argc == 3)
+        {
+            data_path = argv[2];
+            std::cout << "Usage: " << argv[0] << " " << argv[1] << " " << argv[2] << " [image] [labels] [fast_math_hint]\n\n";
+            std::cout << "No image provided: using random values\n\n";
+        }
+        else if(argc == 4)
+        {
+            data_path = argv[2];
+            image     = argv[3];
+            std::cout << "Usage: " << argv[0] << " " << argv[1] << " " << argv[2] << " " << argv[3] << " [labels] [fast_math_hint]\n\n";
+            std::cout << "No text file with labels provided: skipping output accessor\n\n";
+        }
+        else if(argc == 5)
+        {
+            data_path = argv[2];
+            image     = argv[3];
+            label     = argv[4];
+            std::cout << "Usage: " << argv[0] << " " << argv[1] << " " << argv[2] << " " << argv[3] << " " << argv[4] << " [fast_math_hint]\n\n";
+            std::cout << "No fast math info provided: disabling fast math\n\n";
+        }
+        else
+        {
+            data_path      = argv[2];
+            image          = argv[3];
+            label          = argv[4];
+            fast_math_hint = (std::strtol(argv[5], nullptr, 1) == 0) ? FastMathHint::Disabled : FastMathHint::Enabled;
+        }
+
+        graph << target_hint
+              << fast_math_hint
+              << InputLayer(TensorDescriptor(TensorShape(299U, 299U, 3U, 1U), DataType::F32),
+                                       get_input_accessor())
+              << ConvolutionLayer(3U, 3U, 32U,
+                                  get_weights_accessor(data_path, "/cnn_data/inceptionv3_model/Conv2d_1a_3x3_weights.npy"),
+                                  std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr), PadStrideInfo(2, 2, 0, 0))
+              .set_name("Conv2d_1a_3x3/convolution")
+              << BatchNormalizationLayer(get_weights_accessor(data_path,
+                                                              "/cnn_data/inceptionv3_model/Conv2d_1a_3x3_BatchNorm_moving_mean.npy"),
+                                         get_weights_accessor(data_path,
+                                                              "/cnn_data/inceptionv3_model/Conv2d_1a_3x3_BatchNorm_moving_variance.npy"),
+                                         get_random_accessor(1.f, 1.f), get_weights_accessor(data_path,
+                                                                                             "/cnn_data/inceptionv3_model/Conv2d_1a_3x3_BatchNorm_beta.npy"),
+                                         0.001f)
+              .set_name("Conv2d_1a_3x3/BatchNorm/batchnorm")
+              << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name("Conv2d_1a_3x3/Relu")
+              << ConvolutionLayer(3U, 3U, 32U,
+                                  get_weights_accessor(data_path, "/cnn_data/inceptionv3_model/Conv2d_2a_3x3_weights.npy"),
+                                  std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr), PadStrideInfo(1, 1, 0, 0))
+              .set_name("Conv2d_2a_3x3/convolution")
+              << BatchNormalizationLayer(get_weights_accessor(data_path,
+                                                              "/cnn_data/inceptionv3_model/Conv2d_2a_3x3_BatchNorm_moving_mean.npy"),
+                                         get_weights_accessor(data_path,
+                                                              "/cnn_data/inceptionv3_model/Conv2d_2a_3x3_BatchNorm_moving_variance.npy"),
+                                         get_random_accessor(1.f, 1.f), get_weights_accessor(data_path,
+                                                                                             "/cnn_data/inceptionv3_model/Conv2d_2a_3x3_BatchNorm_beta.npy"),
+                                         0.001f)
+              .set_name("Conv2d_2a_3x3/BatchNorm/batchnorm")
+              << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name("Conv2d_2a_3x3/Relu")
+
+              << ConvolutionLayer(3U, 3U, 64U,
+                                  get_weights_accessor(data_path, "/cnn_data/inceptionv3_model/Conv2d_2b_3x3_weights.npy"),
+                                  std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr), PadStrideInfo(1, 1, 1, 1))
+              .set_name("Conv2d_2b_3x3/convolution")
+              << BatchNormalizationLayer(get_weights_accessor(data_path,
+                                                              "/cnn_data/inceptionv3_model/Conv2d_2b_3x3_BatchNorm_moving_mean.npy"),
+                                         get_weights_accessor(data_path,
+                                                              "/cnn_data/inceptionv3_model/Conv2d_2b_3x3_BatchNorm_moving_variance.npy"),
+                                         get_random_accessor(1.f, 1.f), get_weights_accessor(data_path,
+                                                                                             "/cnn_data/inceptionv3_model/Conv2d_2b_3x3_BatchNorm_beta.npy"),
+                                         0.001f)
+              .set_name("Conv2d_2b_3x3/BatchNorm/batchnorm")
+              << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name("Conv2d_2b_3x3/Relu")
+
+              << PoolingLayer(PoolingLayerInfo(PoolingType::MAX, 3, PadStrideInfo(2, 2, 0, 0, DimensionRoundingType::CEIL))).set_name("MaxPool_3a_3x3/MaxPool")
+
+              << ConvolutionLayer(1U, 1U, 80U,
+                                  get_weights_accessor(data_path, "/cnn_data/inceptionv3_model/Conv2d_3b_1x1_weights.npy"),
+                                  std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr), PadStrideInfo(1, 1, 0, 0))
+              .set_name("Conv2d_3b_1x1/convolution")
+              << BatchNormalizationLayer(get_weights_accessor(data_path,
+                                                              "/cnn_data/inceptionv3_model/Conv2d_3b_1x1_BatchNorm_moving_mean.npy"),
+                                         get_weights_accessor(data_path,
+                                                              "/cnn_data/inceptionv3_model/Conv2d_3b_1x1_BatchNorm_moving_variance.npy"),
+                                         get_random_accessor(1.f, 1.f), get_weights_accessor(data_path,
+                                                                                             "/cnn_data/inceptionv3_model/Conv2d_3b_1x1_BatchNorm_beta.npy"),
+                                         0.001f)
+              .set_name("Conv2d_3b_1x1/BatchNorm/batchnorm")
+              << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name("Conv2d_3b_1x1/Relu")
+
+              << ConvolutionLayer(3U, 3U, 192U,
+                                  get_weights_accessor(data_path, "/cnn_data/inceptionv3_model/Conv2d_4a_3x3_weights.npy"),
+                                  std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr), PadStrideInfo(1, 1, 0, 0))
+              .set_name("Conv2d_4a_3x3/convolution")
+              << BatchNormalizationLayer(get_weights_accessor(data_path,
+                                                              "/cnn_data/inceptionv3_model/Conv2d_4a_3x3_BatchNorm_moving_mean.npy"),
+                                         get_weights_accessor(data_path,
+                                                              "/cnn_data/inceptionv3_model/Conv2d_4a_3x3_BatchNorm_moving_variance.npy"),
+                                         get_random_accessor(1.f, 1.f), get_weights_accessor(data_path,
+                                                                                             "/cnn_data/inceptionv3_model/Conv2d_4a_3x3_BatchNorm_beta.npy"),
+                                         0.001f)
+              .set_name("Conv2d_4a_3x3/BatchNorm/batchnorm")
+              << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name("Conv2d_4a_3x3/Relu")
+
+              << PoolingLayer(PoolingLayerInfo(PoolingType::MAX, 3, PadStrideInfo(2, 2, 0, 0, DimensionRoundingType::CEIL))).set_name("MaxPool_5a_3x3/MaxPool");
+
+        graph << get_inception_node_A(data_path, "Mixed_5b", 64U, std::make_tuple(48U, 64U), std::make_tuple(64U, 96U, 96U),
+                                      32U)
+              .set_name("Mixed_5b/concat");
+        graph << get_inception_node_A(data_path, "Mixed_5c", 64U, std::make_tuple(48U, 64U), std::make_tuple(64U, 96U, 96U),
+                                      64U, true)
+              .set_name("Mixed_5c/concat");
+        graph << get_inception_node_A(data_path, "Mixed_5d", 64U, std::make_tuple(48U, 64U), std::make_tuple(64U, 96U, 96U),
+                                      64U)
+              .set_name("Mixed_5d/concat");
+
+        graph << get_inception_node_B(data_path, "Mixed_6a", 384U, std::make_tuple(64U, 96U, 96U)).set_name("Mixed_6a/concat");
+
+        graph << get_inception_node_C(data_path, "Mixed_6b", 192U, std::make_tuple(128U, 128U, 192U),
+                                      std::make_tuple(128U, 128U, 128U, 128U, 192U), 192U)
+              .set_name("Mixed_6b/concat");
+        graph << get_inception_node_C(data_path, "Mixed_6c", 192U, std::make_tuple(160U, 160U, 192U),
+                                      std::make_tuple(160U, 160U, 160U, 160U, 192U), 192U)
+              .set_name("Mixed_6c/concat");
+        graph << get_inception_node_C(data_path, "Mixed_6d", 192U, std::make_tuple(160U, 160U, 192U),
+                                      std::make_tuple(160U, 160U, 160U, 160U, 192U), 192U)
+              .set_name("Mixed_6d/concat");
+        graph << get_inception_node_C(data_path, "Mixed_6e", 192U, std::make_tuple(192U, 192U, 192U),
+                                      std::make_tuple(192U, 192U, 192U, 192U, 192U), 192U)
+              .set_name("Mixed_6e/concat");
+
+        graph << get_inception_node_D(data_path, "Mixed_7a", std::make_tuple(192U, 320U),
+                                      std::make_tuple(192U, 192U, 192U, 192U))
+              .set_name("Mixed_7a/concat");
+
+        graph << get_inception_node_E(data_path, "Mixed_7b", 320U, std::make_tuple(384U, 384U, 384U),
+                                      std::make_tuple(448U, 384U, 384U, 384U), 192U)
+              .set_name("Mixed_7b/concat");
+        graph << get_inception_node_E(data_path, "Mixed_7c", 320U, std::make_tuple(384U, 384U, 384U),
+                                      std::make_tuple(448U, 384U, 384U, 384U), 192U, true)
+              .set_name("Mixed_7c/concat");
+
+        graph << PoolingLayer(PoolingLayerInfo(PoolingType::AVG, 8, PadStrideInfo(1, 1, 0, 0, DimensionRoundingType::CEIL))).set_name("Logits/AvgPool_1a_8x8/AvgPool")
+              << ConvolutionLayer(1U, 1U, 1001U, get_weights_accessor(data_path,
+                                                                      "/cnn_data/inceptionv3_model/Logits_Conv2d_1c_1x1_weights.npy"),
+                                  get_weights_accessor(data_path,
+                                                       "/cnn_data/inceptionv3_model/Logits_Conv2d_1c_1x1_biases.npy"),
+                                  PadStrideInfo(1, 1, 0, 0))
+              .set_name("Logits/Conv2d_1c_1x1/convolution")
+              << ReshapeLayer(TensorShape(1001U)).set_name("Predictions/Reshape")
+              << SoftmaxLayer().set_name("Predictions/Softmax")
+              << OutputLayer(get_output_accessor());
+
+        // Finalize graph
+        GraphConfig config;
+        config.use_tuner = (target == 2);
+        graph.finalize(target_hint, config);
+    }
+
+    void do_run()
+    {
+        run_benchmark(graph);
+    }
+
+private:
+    Stream graph{ 0, "InceptionV3" };
+
+private:
+    ConcatLayer get_inception_node_A(const std::string &data_path, std::string &&param_path,
+                                     unsigned int a_filt,
+                                     std::tuple<unsigned int, unsigned int> b_filters,
+                                     std::tuple<unsigned int, unsigned int, unsigned int> c_filters,
+                                     unsigned int d_filt,
+                                     bool         is_name_different = false)
+    {
+        std::string total_path = "/cnn_data/inceptionv3_model/" + param_path + "_";
+
+        // This is due to a naming issue in the tf model
+        std::string conv_id0 = "_0a_";
+        std::string conv_id1 = "2d_0b_";
+        if(is_name_different)
+        {
+            conv_id0 = "_0b_";
+            conv_id1 = "_1_0c_";
+        }
+
+        SubStream i_a(graph);
+        i_a << ConvolutionLayer(
+                1U, 1U, a_filt,
+                get_weights_accessor(data_path, total_path + "Branch_0_Conv2d_0a_1x1_weights.npy"),
+                std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                PadStrideInfo(1, 1, 0, 0))
+            .set_name(param_path + "/Branch_0/Conv2d_0a_1x1/convolution")
+            << BatchNormalizationLayer(
+                get_weights_accessor(data_path, total_path + "Branch_0_Conv2d_0a_1x1_BatchNorm_moving_mean.npy"),
+                get_weights_accessor(data_path, total_path + "Branch_0_Conv2d_0a_1x1_BatchNorm_moving_variance.npy"),
+                get_random_accessor(1.f, 1.f),
+                get_weights_accessor(data_path, total_path + "Branch_0_Conv2d_0a_1x1_BatchNorm_beta.npy"),
+                0.001f)
+            .set_name(param_path + "/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm")
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_0/Conv2d_0a_1x1/Relu");
+
+        SubStream i_b(graph);
+        i_b << ConvolutionLayer(
+                1U, 1U, std::get<0>(b_filters),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d" + conv_id0 + "1x1_weights.npy"),
+                std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                PadStrideInfo(1, 1, 0, 0))
+            .set_name(param_path + "/Branch_1/Conv2d" + conv_id0 + "1x1/convolution")
+            << BatchNormalizationLayer(
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d" + conv_id0 + "1x1_BatchNorm_moving_mean.npy"),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d" + conv_id0 + "1x1_BatchNorm_moving_variance.npy"),
+                get_random_accessor(1.f, 1.f),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d" + conv_id0 + "1x1_BatchNorm_beta.npy"),
+                0.001f)
+            .set_name(param_path + "/Branch_1/Conv2d" + conv_id0 + "1x1/BatchNorm/batchnorm")
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_1/Conv2d" + conv_id0 + "1x1/Relu")
+            << ConvolutionLayer(
+                5U, 5U, std::get<1>(b_filters),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv" + conv_id1 + "5x5_weights.npy"),
+                std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                PadStrideInfo(1, 1, 2, 2))
+            .set_name(param_path + "/Branch_1/Conv2d" + conv_id1 + "5x5/convolution")
+            << BatchNormalizationLayer(
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv" + conv_id1 + "5x5_BatchNorm_moving_mean.npy"),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv" + conv_id1 + "5x5_BatchNorm_moving_variance.npy"),
+                get_random_accessor(1.f, 1.f),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv" + conv_id1 + "5x5_BatchNorm_beta.npy"),
+                0.001f)
+            .set_name(param_path + "/Branch_1/Conv2d" + conv_id1 + "5x5/BatchNorm/batchnorm")
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_1/Conv2d" + conv_id1 + "5x5/Relu");
+
+        SubStream i_c(graph);
+        i_c << ConvolutionLayer(
+                1U, 1U, std::get<0>(c_filters),
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0a_1x1_weights.npy"),
+                std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                PadStrideInfo(1, 1, 0, 0))
+            .set_name(param_path + "/Branch_2/Conv2d_0a_1x1/convolution")
+            << BatchNormalizationLayer(
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0a_1x1_BatchNorm_moving_mean.npy"),
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0a_1x1_BatchNorm_moving_variance.npy"),
+                get_random_accessor(1.f, 1.f),
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0a_1x1_BatchNorm_beta.npy"),
+                0.001f)
+            .set_name(param_path + "/Branch_2/Conv2d_0a_1x1/BatchNorm/batchnorm")
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_2/Conv2d_0a_1x1/Relu")
+            << ConvolutionLayer(
+                3U, 3U, std::get<1>(c_filters),
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0b_3x3_weights.npy"),
+                std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                PadStrideInfo(1, 1, 1, 1))
+            .set_name(param_path + "/Branch_2/Conv2d_0b_3x3/convolution")
+            << BatchNormalizationLayer(
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0b_3x3_BatchNorm_moving_mean.npy"),
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0b_3x3_BatchNorm_moving_variance.npy"),
+                get_random_accessor(1.f, 1.f),
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0b_3x3_BatchNorm_beta.npy"),
+                0.001f)
+            .set_name(param_path + "/Branch_2/Conv2d_0b_3x3/BatchNorm/batchnorm")
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_2/Conv2d_0b_3x3/Relu")
+            << ConvolutionLayer(
+                3U, 3U, std::get<2>(c_filters),
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0c_3x3_weights.npy"),
+                std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                PadStrideInfo(1, 1, 1, 1))
+            .set_name(param_path + "/Branch_2/Conv2d_0c_3x3/convolution")
+            << BatchNormalizationLayer(
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0c_3x3_BatchNorm_moving_mean.npy"),
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0c_3x3_BatchNorm_moving_variance.npy"),
+                get_random_accessor(1.f, 1.f),
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0c_3x3_BatchNorm_beta.npy"),
+                0.001f)
+            .set_name(param_path + "/Branch_2/Conv2d_0c_3x3/BatchNorm/batcnorm")
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_2/Conv2d_0c_3x3/Relu");
+
+        SubStream i_d(graph);
+        i_d << PoolingLayer(PoolingLayerInfo(PoolingType::AVG, 3, PadStrideInfo(1, 1, 1, 1, DimensionRoundingType::CEIL), true)).set_name(param_path + "/Branch_3/AvgPool_0a_3x3/AvgPool")
+            << ConvolutionLayer(
+                1U, 1U, d_filt,
+                get_weights_accessor(data_path, total_path + "Branch_3_Conv2d_0b_1x1_weights.npy"),
+                std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                PadStrideInfo(1, 1, 0, 0))
+            .set_name(param_path + "/Branch_3/Conv2d_0b_1x1/convolution")
+            << BatchNormalizationLayer(
+                get_weights_accessor(data_path, total_path + "Branch_3_Conv2d_0b_1x1_BatchNorm_moving_mean.npy"),
+                get_weights_accessor(data_path, total_path + "Branch_3_Conv2d_0b_1x1_BatchNorm_moving_variance.npy"),
+                get_random_accessor(1.f, 1.f),
+                get_weights_accessor(data_path, total_path + "Branch_3_Conv2d_0b_1x1_BatchNorm_beta.npy"),
+                0.001f)
+            .set_name(param_path + "/Branch_3/Conv2d_0b_1x1/BatchNorm/batchnorm")
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_3/Conv2d_0b_1x1/Relu");
+
+        return ConcatLayer(std::move(i_a), std::move(i_b), std::move(i_c), std::move(i_d));
+    }
+
+    ConcatLayer get_inception_node_B(const std::string &data_path, std::string &&param_path,
+                                     unsigned int a_filt,
+                                     std::tuple<unsigned int, unsigned int, unsigned int> b_filters)
+    {
+        std::string total_path = "/cnn_data/inceptionv3_model/" + param_path + "_";
+        SubStream   i_a(graph);
+        i_a << ConvolutionLayer(
+                3U, 3U, a_filt,
+                get_weights_accessor(data_path, total_path + "Branch_0_Conv2d_1a_1x1_weights.npy"),
+                std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                PadStrideInfo(2, 2, 0, 0))
+            .set_name(param_path + "/Branch_0/Conv2d_1a_1x1/convolution")
+            << BatchNormalizationLayer(
+                get_weights_accessor(data_path, total_path + "Branch_0_Conv2d_1a_1x1_BatchNorm_moving_mean.npy"),
+                get_weights_accessor(data_path, total_path + "Branch_0_Conv2d_1a_1x1_BatchNorm_moving_variance.npy"),
+                get_random_accessor(1.f, 1.f),
+                get_weights_accessor(data_path, total_path + "Branch_0_Conv2d_1a_1x1_BatchNorm_beta.npy"),
+                0.001f)
+            .set_name(param_path + "/Branch_0/Conv2d_1a_1x1/BatchNorm/batchnorm")
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_0/Conv2d_1a_1x1/Relu");
+
+        SubStream i_b(graph);
+        i_b << ConvolutionLayer(
+                1U, 1U, std::get<0>(b_filters),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0a_1x1_weights.npy"),
+                std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                PadStrideInfo(1, 1, 0, 0))
+            .set_name(param_path + "/Branch_1/Conv2d_0a_1x1/convolution")
+            << BatchNormalizationLayer(
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0a_1x1_BatchNorm_moving_mean.npy"),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0a_1x1_BatchNorm_moving_variance.npy"),
+                get_random_accessor(1.f, 1.f),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0a_1x1_BatchNorm_beta.npy"),
+                0.001f)
+            .set_name(param_path + "/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm")
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_1/Conv2d_0a_1x1/Relu")
+            << ConvolutionLayer(
+                3U, 3U, std::get<1>(b_filters),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0b_3x3_weights.npy"),
+                std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                PadStrideInfo(1, 1, 1, 1))
+            .set_name(param_path + "/Branch_1/Conv2d_0b_3x3/convolution")
+            << BatchNormalizationLayer(
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0b_3x3_BatchNorm_moving_mean.npy"),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0b_3x3_BatchNorm_moving_variance.npy"),
+                get_random_accessor(1.f, 1.f),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0b_3x3_BatchNorm_beta.npy"),
+                0.001f)
+            .set_name(param_path + "/Branch_1/Conv2d_0b_3x3/BatchNorm/batchnorm")
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_1/Conv2d_0b_3x3/Relu")
+            << ConvolutionLayer(
+                3U, 3U, std::get<2>(b_filters),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_1a_1x1_weights.npy"),
+                std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                PadStrideInfo(2, 2, 0, 0))
+            .set_name(param_path + "/Branch_1/Conv2d_1a_1x1/convolution")
+            << BatchNormalizationLayer(
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_1a_1x1_BatchNorm_moving_mean.npy"),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_1a_1x1_BatchNorm_moving_variance.npy"),
+                get_random_accessor(1.f, 1.f),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_1a_1x1_BatchNorm_beta.npy"),
+                0.001f)
+            .set_name(param_path + "/Branch_1/Conv2d_1a_1x1/BatchNorm/batchnorm")
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_1/Conv2d_1a_1x1/Relu");
+
+        SubStream i_c(graph);
+        i_c << PoolingLayer(PoolingLayerInfo(PoolingType::MAX, 3, PadStrideInfo(2, 2, 0, 0, DimensionRoundingType::CEIL))).set_name(param_path + "/Branch_2/MaxPool_1a_3x3/MaxPool");
+
+        return ConcatLayer(std::move(i_a), std::move(i_b), std::move(i_c));
+    }
+
+    ConcatLayer get_inception_node_C(const std::string &data_path, std::string &&param_path,
+                                     unsigned int a_filt,
+                                     std::tuple<unsigned int, unsigned int, unsigned int> b_filters,
+                                     std::tuple<unsigned int, unsigned int, unsigned int, unsigned int, unsigned int> c_filters,
+                                     unsigned int d_filt)
+    {
+        std::string total_path = "/cnn_data/inceptionv3_model/" + param_path + "_";
+        SubStream   i_a(graph);
+        i_a << ConvolutionLayer(
+                1U, 1U, a_filt,
+                get_weights_accessor(data_path, total_path + "Branch_0_Conv2d_0a_1x1_weights.npy"),
+                std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                PadStrideInfo(1, 1, 0, 0))
+            .set_name(param_path + "/Branch_0/Conv2d_0a_1x1/convolution")
+            << BatchNormalizationLayer(
+                get_weights_accessor(data_path, total_path + "Branch_0_Conv2d_0a_1x1_BatchNorm_moving_mean.npy"),
+                get_weights_accessor(data_path, total_path + "Branch_0_Conv2d_0a_1x1_BatchNorm_moving_variance.npy"),
+                get_random_accessor(1.f, 1.f),
+                get_weights_accessor(data_path, total_path + "Branch_0_Conv2d_0a_1x1_BatchNorm_beta.npy"),
+                0.001f)
+            .set_name(param_path + "/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm")
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_0/Conv2d_0a_1x1/Relu");
+
+        SubStream i_b(graph);
+        i_b << ConvolutionLayer(
+                1U, 1U, std::get<0>(b_filters),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0a_1x1_weights.npy"),
+                std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                PadStrideInfo(1, 1, 0, 0))
+            .set_name(param_path + "/Branch_1/Conv2d_0a_1x1/convolution")
+            << BatchNormalizationLayer(
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0a_1x1_BatchNorm_moving_mean.npy"),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0a_1x1_BatchNorm_moving_variance.npy"),
+                get_random_accessor(1.f, 1.f),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0a_1x1_BatchNorm_beta.npy"),
+                0.001f)
+            .set_name(param_path + "/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm")
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_1/Conv2d_0a_1x1/Relu")
+            << ConvolutionLayer(
+                7U, 1U, std::get<1>(b_filters),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0b_1x7_weights.npy"),
+                std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                PadStrideInfo(1, 1, 3, 0))
+            .set_name(param_path + "/Branch_1/Conv2d_0b_1x7/convolution")
+            << BatchNormalizationLayer(
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0b_1x7_BatchNorm_moving_mean.npy"),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0b_1x7_BatchNorm_moving_variance.npy"),
+                get_random_accessor(1.f, 1.f),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0b_1x7_BatchNorm_beta.npy"),
+                0.001f)
+            .set_name(param_path + "/Branch_1/Conv2d_0b_1x7/BatchNorm/batchnorm")
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_1/Conv2d_0b_1x7/Relu")
+            << ConvolutionLayer(
+                1U, 7U, std::get<2>(b_filters),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0c_7x1_weights.npy"),
+                std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                PadStrideInfo(1, 1, 0, 3))
+            .set_name(param_path + "/Branch_1/Conv2d_0c_7x1/convolution")
+            << BatchNormalizationLayer(
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0c_7x1_BatchNorm_moving_mean.npy"),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0c_7x1_BatchNorm_moving_variance.npy"),
+                get_random_accessor(1.f, 1.f),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0c_7x1_BatchNorm_beta.npy"),
+                0.001f)
+            .set_name(param_path + "/Branch_1/Conv2d_0c_7x1/BatchNorm/batchnorm")
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_0/Conv2d_0c_7x1/Relu");
+
+        SubStream i_c(graph);
+        i_c << ConvolutionLayer(
+                1U, 1U, std::get<0>(c_filters),
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0a_1x1_weights.npy"),
+                std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                PadStrideInfo(1, 1, 0, 0))
+            .set_name(param_path + "/Branch_2/Conv2d_0a_1x1/convolution")
+            << BatchNormalizationLayer(
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0a_1x1_BatchNorm_moving_mean.npy"),
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0a_1x1_BatchNorm_moving_variance.npy"),
+                get_random_accessor(1.f, 1.f),
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0a_1x1_BatchNorm_beta.npy"),
+                0.001f)
+            .set_name(param_path + "/Branch_2/Conv2d_0a_1x1/BatchNorm/batchnorm")
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_2/Conv2d_0a_1x1/Relu")
+            << ConvolutionLayer(
+                1U, 7U, std::get<1>(c_filters),
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0b_7x1_weights.npy"),
+                std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                PadStrideInfo(1, 1, 0, 3))
+            .set_name(param_path + "/Branch_2/Conv2d_0b_7x1/convolution")
+            << BatchNormalizationLayer(
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0b_7x1_BatchNorm_moving_mean.npy"),
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0b_7x1_BatchNorm_moving_variance.npy"),
+                get_random_accessor(1.f, 1.f),
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0b_7x1_BatchNorm_beta.npy"),
+                0.001f)
+            .set_name(param_path + "/Branch_2/Conv2d_0b_7x1/BatchNorm/batchnorm")
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_2/Conv2d_0b_7x1/Relu")
+            << ConvolutionLayer(
+                7U, 1U, std::get<2>(c_filters),
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0c_1x7_weights.npy"),
+                std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                PadStrideInfo(1, 1, 3, 0))
+            .set_name(param_path + "/Branch_2/Conv2d_0c_1x7/convolution")
+            << BatchNormalizationLayer(
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0c_1x7_BatchNorm_moving_mean.npy"),
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0c_1x7_BatchNorm_moving_variance.npy"),
+                get_random_accessor(1.f, 1.f),
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0c_1x7_BatchNorm_beta.npy"),
+                0.001f)
+            .set_name(param_path + "/Branch_2/Conv2d_0c_1x7/BatchNorm/batchnorm")
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_2/Conv2d_0c_1x7/Relu")
+            << ConvolutionLayer(
+                1U, 7U, std::get<3>(c_filters),
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0d_7x1_weights.npy"),
+                std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                PadStrideInfo(1, 1, 0, 3))
+            .set_name(param_path + "/Branch_2/Conv2d_0d_7x1/convolution")
+            << BatchNormalizationLayer(
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0d_7x1_BatchNorm_moving_mean.npy"),
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0d_7x1_BatchNorm_moving_variance.npy"),
+                get_random_accessor(1.f, 1.f),
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0d_7x1_BatchNorm_beta.npy"),
+                0.001f)
+            .set_name(param_path + "/Branch_2/Conv2d_0d_7x1/BatchNorm/batchnorm")
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_2/Conv2d_0d_7x1/Relu")
+            << ConvolutionLayer(
+                7U, 1U, std::get<4>(c_filters),
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0e_1x7_weights.npy"),
+                std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                PadStrideInfo(1, 1, 3, 0))
+            .set_name(param_path + "/Branch_2/Conv2d_0e_1x7/convolution")
+            << BatchNormalizationLayer(
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0e_1x7_BatchNorm_moving_mean.npy"),
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0e_1x7_BatchNorm_moving_variance.npy"),
+                get_random_accessor(1.f, 1.f),
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0e_1x7_BatchNorm_beta.npy"),
+                0.001f)
+            .set_name(param_path + "/Branch_2/Conv2d_0e_1x7/BatchNorm/batchnorm")
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_2/Conv2d_0e_1x7/Relu");
+
+        SubStream i_d(graph);
+        i_d << PoolingLayer(PoolingLayerInfo(PoolingType::AVG, 3, PadStrideInfo(1, 1, 1, 1, DimensionRoundingType::CEIL), true)).set_name(param_path + "/Branch_3/AvgPool_0a_3x3/AvgPool")
+            << ConvolutionLayer(
+                1U, 1U, d_filt,
+                get_weights_accessor(data_path, total_path + "Branch_3_Conv2d_0b_1x1_weights.npy"),
+                std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                PadStrideInfo(1, 1, 0, 0))
+            .set_name(param_path + "/Branch_3/Conv2d_0b_1x1/convolution")
+            << BatchNormalizationLayer(
+                get_weights_accessor(data_path, total_path + "Branch_3_Conv2d_0b_1x1_BatchNorm_moving_mean.npy"),
+                get_weights_accessor(data_path, total_path + "Branch_3_Conv2d_0b_1x1_BatchNorm_moving_variance.npy"),
+                get_random_accessor(1.f, 1.f),
+                get_weights_accessor(data_path, total_path + "Branch_3_Conv2d_0b_1x1_BatchNorm_beta.npy"),
+                0.001f)
+            .set_name(param_path + "/Branch_3/Conv2d_0b_1x1/BatchNorm/batchnorm")
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_3/Conv2d_0b_1x1/Relu");
+
+        return ConcatLayer(std::move(i_a), std::move(i_b), std::move(i_c), std::move(i_d));
+    }
+
+    ConcatLayer get_inception_node_D(const std::string &data_path, std::string &&param_path,
+                                     std::tuple<unsigned int, unsigned int>      a_filters,
+                                     std::tuple<unsigned int, unsigned int, unsigned int, unsigned int> b_filters)
+    {
+        std::string total_path = "/cnn_data/inceptionv3_model/" + param_path + "_";
+        SubStream   i_a(graph);
+        i_a << ConvolutionLayer(
+                1U, 1U, std::get<0>(a_filters),
+                get_weights_accessor(data_path, total_path + "Branch_0_Conv2d_0a_1x1_weights.npy"),
+                std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                PadStrideInfo(1, 1, 0, 0))
+            .set_name(param_path + "/Branch_0/Conv2d_0a_1x1/convolution")
+            << BatchNormalizationLayer(
+                get_weights_accessor(data_path, total_path + "Branch_0_Conv2d_0a_1x1_BatchNorm_moving_mean.npy"),
+                get_weights_accessor(data_path, total_path + "Branch_0_Conv2d_0a_1x1_BatchNorm_moving_variance.npy"),
+                get_random_accessor(1.f, 1.f),
+                get_weights_accessor(data_path, total_path + "Branch_0_Conv2d_0a_1x1_BatchNorm_beta.npy"),
+                0.001f)
+            .set_name(param_path + "/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm")
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_0/Conv2d_0a_1x1/Relu")
+            << ConvolutionLayer(
+                3U, 3U, std::get<1>(a_filters),
+                get_weights_accessor(data_path, total_path + "Branch_0_Conv2d_1a_3x3_weights.npy"),
+                std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                PadStrideInfo(2, 2, 0, 0))
+            .set_name(param_path + "/Branch_0/Conv2d_1a_3x3/convolution")
+            << BatchNormalizationLayer(
+                get_weights_accessor(data_path, total_path + "Branch_0_Conv2d_1a_3x3_BatchNorm_moving_mean.npy"),
+                get_weights_accessor(data_path, total_path + "Branch_0_Conv2d_1a_3x3_BatchNorm_moving_variance.npy"),
+                get_random_accessor(1.f, 1.f),
+                get_weights_accessor(data_path, total_path + "Branch_0_Conv2d_1a_3x3_BatchNorm_beta.npy"),
+                0.001f)
+            .set_name(param_path + "/Branch_0/Conv2d_1a_3x3/BatchNorm/batchnorm")
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_0/Conv2d_1a_3x3/Relu");
+
+        SubStream i_b(graph);
+        i_b << ConvolutionLayer(
+                1U, 1U, std::get<0>(b_filters),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0a_1x1_weights.npy"),
+                std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                PadStrideInfo(1, 1, 0, 0))
+            .set_name(param_path + "/Branch_1/Conv2d_0a_1x1/convolution")
+            << BatchNormalizationLayer(
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0a_1x1_BatchNorm_moving_mean.npy"),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0a_1x1_BatchNorm_moving_variance.npy"),
+                get_random_accessor(1.f, 1.f),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0a_1x1_BatchNorm_beta.npy"),
+                0.001f)
+            .set_name(param_path + "/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm")
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_1/Conv2d_0a_1x1/Relu")
+            << ConvolutionLayer(
+                7U, 1U, std::get<1>(b_filters),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0b_1x7_weights.npy"),
+                std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                PadStrideInfo(1, 1, 3, 0))
+            .set_name(param_path + "/Branch_1/Conv2d_0b_1x7/convolution")
+            << BatchNormalizationLayer(
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0b_1x7_BatchNorm_moving_mean.npy"),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0b_1x7_BatchNorm_moving_variance.npy"),
+                get_random_accessor(1.f, 1.f),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0b_1x7_BatchNorm_beta.npy"),
+                0.001f)
+            .set_name(param_path + "/Branch_1/Conv2d_0b_1x7/BatchNorm/batchnorm")
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_1/Conv2d_0b_1x7/Relu")
+            << ConvolutionLayer(
+                1U, 7U, std::get<2>(b_filters),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0c_7x1_weights.npy"),
+                std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                PadStrideInfo(1, 1, 0, 3))
+            .set_name(param_path + "/Branch_1/Conv2d_0c_7x1/convolution")
+            << BatchNormalizationLayer(
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0c_7x1_BatchNorm_moving_mean.npy"),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0c_7x1_BatchNorm_moving_variance.npy"),
+                get_random_accessor(1.f, 1.f),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0c_7x1_BatchNorm_beta.npy"),
+                0.001f)
+            .set_name(param_path + "/Branch_1/Conv2d_0c_7x1/BatchNorm/batchnorm")
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_1/Conv2d_0c_7x1/Relu")
+            << ConvolutionLayer(
+                3U, 3U, std::get<3>(b_filters),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_1a_3x3_weights.npy"),
+                std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                PadStrideInfo(2, 2, 0, 0))
+            .set_name(param_path + "/Branch_1/Conv2d_1a_3x3/convolution")
+            << BatchNormalizationLayer(
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_1a_3x3_BatchNorm_moving_mean.npy"),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_1a_3x3_BatchNorm_moving_variance.npy"),
+                get_random_accessor(1.f, 1.f),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_1a_3x3_BatchNorm_beta.npy"),
+                0.001f)
+            .set_name(param_path + "/Branch_1/Conv2d_1a_3x3/BatchNorm/batchnorm")
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_1/Conv2d_1a_3x3/Relu");
+
+        SubStream i_c(graph);
+        i_c << PoolingLayer(PoolingLayerInfo(PoolingType::MAX, 3, PadStrideInfo(2, 2, 0, 0, DimensionRoundingType::CEIL))).set_name(param_path + "/Branch_2/MaxPool_1a_3x3/MaxPool");
+
+        return ConcatLayer(std::move(i_a), std::move(i_b), std::move(i_c));
+    }
+
+    ConcatLayer get_inception_node_E(const std::string &data_path, std::string &&param_path,
+                                     unsigned int a_filt,
+                                     std::tuple<unsigned int, unsigned int, unsigned int> b_filters,
+                                     std::tuple<unsigned int, unsigned int, unsigned int, unsigned int> c_filters,
+                                     unsigned int d_filt,
+                                     bool         is_name_different = false)
+    {
+        // This is due to a naming issue in the tf model
+        std::string conv_id = "_0b_";
+        if(is_name_different)
+        {
+            conv_id = "_0c_";
+        }
+
+        std::string total_path = "/cnn_data/inceptionv3_model/" + param_path + "_";
+        SubStream   i_a(graph);
+        i_a << ConvolutionLayer(
+                1U, 1U, a_filt,
+                get_weights_accessor(data_path, total_path + "Branch_0_Conv2d_0a_1x1_weights.npy"),
+                std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                PadStrideInfo(1, 1, 0, 0))
+            .set_name(param_path + "/Branch_0/Conv2d_0a_1x1/convolution")
+            << BatchNormalizationLayer(
+                get_weights_accessor(data_path, total_path + "Branch_0_Conv2d_0a_1x1_BatchNorm_moving_mean.npy"),
+                get_weights_accessor(data_path, total_path + "Branch_0_Conv2d_0a_1x1_BatchNorm_moving_variance.npy"),
+                get_random_accessor(1.f, 1.f),
+                get_weights_accessor(data_path, total_path + "Branch_0_Conv2d_0a_1x1_BatchNorm_beta.npy"),
+                0.001f)
+            .set_name(param_path + "/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm")
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_0/Conv2d_0a_1x1/Relu");
+
+        SubStream i_b(graph);
+        i_b << ConvolutionLayer(
+                1U, 1U, std::get<0>(b_filters),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0a_1x1_weights.npy"),
+                std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                PadStrideInfo(1, 1, 0, 0))
+            .set_name(param_path + "/Branch_1/Conv2d_0a_1x1/convolution")
+            << BatchNormalizationLayer(
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0a_1x1_BatchNorm_moving_mean.npy"),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0a_1x1_BatchNorm_moving_variance.npy"),
+                get_random_accessor(1.f, 1.f),
+                get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0a_1x1_BatchNorm_beta.npy"),
+                0.001f)
+            .set_name(param_path + "/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm")
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_1/Conv2d_0a_1x1/Relu");
+
+        SubStream i_b1(static_cast<IStream &>(i_b));
+        i_b1 << ConvolutionLayer(
+                 3U, 1U, std::get<1>(b_filters),
+                 get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0b_1x3_weights.npy"),
+                 std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                 PadStrideInfo(1, 1, 1, 0))
+             .set_name(param_path + "/Branch_1/Conv2d_0b_1x3/convolution")
+             << BatchNormalizationLayer(
+                 get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0b_1x3_BatchNorm_moving_mean.npy"),
+                 get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0b_1x3_BatchNorm_moving_variance.npy"),
+                 get_random_accessor(1.f, 1.f),
+                 get_weights_accessor(data_path, total_path + "Branch_1_Conv2d_0b_1x3_BatchNorm_beta.npy"),
+                 0.001f)
+             .set_name(param_path + "/Branch_1/Conv2d_0b_1x3/BatchNorm/batchnorm")
+             << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_1/Conv2d_0b_1x3/Relu");
+
+        SubStream i_b2(static_cast<IStream &>(i_b));
+        i_b2 << ConvolutionLayer(
+                 1U, 3U, std::get<2>(b_filters),
+                 get_weights_accessor(data_path, total_path + "Branch_1_Conv2d" + conv_id + "3x1_weights.npy"),
+                 std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                 PadStrideInfo(1, 1, 0, 1))
+             .set_name(param_path + "/Branch_1/Conv2d" + conv_id + "3x1/convolution")
+             << BatchNormalizationLayer(
+                 get_weights_accessor(data_path, total_path + "Branch_1_Conv2d" + conv_id + "3x1_BatchNorm_moving_mean.npy"),
+                 get_weights_accessor(data_path, total_path + "Branch_1_Conv2d" + conv_id + "3x1_BatchNorm_moving_variance.npy"),
+                 get_random_accessor(1.f, 1.f),
+                 get_weights_accessor(data_path, total_path + "Branch_1_Conv2d" + conv_id + "3x1_BatchNorm_beta.npy"),
+                 0.001f)
+             .set_name(param_path + "/Branch_1/Conv2d" + conv_id + "3x1/BatchNorm/batchnorm")
+             << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_1/Conv2d" + conv_id + "3x1/Relu");
+
+        // Merge b1 and b2
+        i_b << ConcatLayer(std::move(i_b1), std::move(i_b2)).set_name(param_path + "/Branch_1/concat");
+
+        SubStream i_c(graph);
+        i_c << ConvolutionLayer(
+                1U, 1U, std::get<0>(c_filters),
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0a_1x1_weights.npy"),
+                std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                PadStrideInfo(1, 1, 0, 0))
+            .set_name(param_path + "/Branch_2/Conv2d_0a_1x1/convolution")
+            << BatchNormalizationLayer(
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0a_1x1_BatchNorm_moving_mean.npy"),
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0a_1x1_BatchNorm_moving_variance.npy"),
+                get_random_accessor(1.f, 1.f),
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0a_1x1_BatchNorm_beta.npy"),
+                0.001f)
+            .set_name(param_path + "/Branch_2/Conv2d_0a_1x1/BatchNorm/batchnorm")
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_2/Conv2d_0a_1x1/Relu")
+            << ConvolutionLayer(
+                3U, 3U, std::get<1>(c_filters),
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0b_3x3_weights.npy"),
+                std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                PadStrideInfo(1, 1, 1, 1))
+            .set_name(param_path + "/Branch_2/Conv2d_0b_3x3/convolution")
+            << BatchNormalizationLayer(
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0b_3x3_BatchNorm_moving_mean.npy"),
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0b_3x3_BatchNorm_moving_variance.npy"),
+                get_random_accessor(1.f, 1.f),
+                get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0b_3x3_BatchNorm_beta.npy"),
+                0.001f)
+            .set_name(param_path + "/Branch_2/Conv2d_0b_3x3/BatchNorm/batchnorm")
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_2/Conv2d_0b_3x3/Relu");
+
+        SubStream i_c1(static_cast<IStream &>(i_c));
+        i_c1 << ConvolutionLayer(
+                 3U, 1U, std::get<2>(c_filters),
+                 get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0c_1x3_weights.npy"),
+                 std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                 PadStrideInfo(1, 1, 1, 0))
+             .set_name(param_path + "/Branch_2/Conv2d_0c_1x3/convolution")
+             << BatchNormalizationLayer(
+                 get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0c_1x3_BatchNorm_moving_mean.npy"),
+                 get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0c_1x3_BatchNorm_moving_variance.npy"),
+                 get_random_accessor(1.f, 1.f),
+                 get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0c_1x3_BatchNorm_beta.npy"),
+                 0.001f)
+             .set_name(param_path + "/Branch_2/Conv2d_0c_1x3/BatchNorm/batchnorm")
+             << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_2/Conv2d_0c_1x3/Relu");
+
+        SubStream i_c2(static_cast<IStream &>(i_c));
+        i_c2 << ConvolutionLayer(
+                 1U, 3U, std::get<3>(c_filters),
+                 get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0d_3x1_weights.npy"),
+                 std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                 PadStrideInfo(1, 1, 0, 1))
+             .set_name(param_path + "/Branch_2/Conv2d_0d_3x1/convolution")
+             << BatchNormalizationLayer(
+                 get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0d_3x1_BatchNorm_moving_mean.npy"),
+                 get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0d_3x1_BatchNorm_moving_variance.npy"),
+                 get_random_accessor(1.f, 1.f),
+                 get_weights_accessor(data_path, total_path + "Branch_2_Conv2d_0d_3x1_BatchNorm_beta.npy"),
+                 0.001f)
+             .set_name(param_path + "/Branch_2/Conv2d_0d_3x1/BatchNorm/batchnorm")
+             << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_2/Conv2d_0d_3x1/Relu");
+
+        // Merge i_c1 and i_c2
+        i_c << ConcatLayer(std::move(i_c1), std::move(i_c2)).set_name(param_path + "/Branch_2/concat");
+
+        SubStream i_d(graph);
+        i_d << PoolingLayer(PoolingLayerInfo(PoolingType::AVG, 3, PadStrideInfo(1, 1, 1, 1, DimensionRoundingType::CEIL), true)).set_name(param_path + "/Branch_3/AvgPool_0a_3x3/AvgPool")
+            << ConvolutionLayer(
+                1U, 1U, d_filt,
+                get_weights_accessor(data_path, total_path + "Branch_3_Conv2d_0b_1x1_weights.npy"),
+                std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                PadStrideInfo(1, 1, 0, 0))
+            .set_name(param_path + "/Branch_3/Conv2d_0b_1x1/convolution")
+            << BatchNormalizationLayer(
+                get_weights_accessor(data_path, total_path + "Branch_3_Conv2d_0b_1x1_BatchNorm_moving_mean.npy"),
+                get_weights_accessor(data_path, total_path + "Branch_3_Conv2d_0b_1x1_BatchNorm_moving_variance.npy"),
+                get_random_accessor(1.f, 1.f),
+                get_weights_accessor(data_path, total_path + "Branch_3_Conv2d_0b_1x1_BatchNorm_beta.npy"),
+                0.001f)
+            .set_name(param_path + "/Branch_3/Conv2d_0b_1x1/BatchNorm/batchnorm")
+            << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::RELU)).set_name(param_path + "/Branch_3/Conv2d_0b_1x1/Relu");
+
+        return ConcatLayer(std::move(i_a), std::move(i_b), std::move(i_c), std::move(i_d));
+    }
+};
+
+/** Main program for Inception V3
+ *
+ * @param[in] argc Number of arguments
+ * @param[in] argv Arguments ( [optional] Target (0 = NEON, 1 = OpenCL, 2 = OpenCL with Tuner), [optional] Path to the weights folder, [optional] image, [optional] labels, [optional] Fast math for convolution layer (0 = DISABLED, 1 = ENABLED) )
+ */
+int main(int argc, char **argv)
+{
+    InceptionV3Example example;
+
+    example.do_setup(argc, argv);
+    example.do_run();
+
+    return 0;
+}
diff --git a/runtime/contrib/benchmark_acl/src/benchmark_mobilenet.cpp b/runtime/contrib/benchmark_acl/src/benchmark_mobilenet.cpp
new file mode 100644
index 000000000..085be184e
--- /dev/null
+++ b/runtime/contrib/benchmark_acl/src/benchmark_mobilenet.cpp
@@ -0,0 +1,265 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ * Copyright (c) 2017 ARM Limited.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "arm_compute/graph.h"
+
+#include "Benchmark.h"
+
+#include <cstdlib>
+
+using namespace arm_compute::graph::frontend;
+
+inline std::unique_ptr<arm_compute::graph::ITensorAccessor> get_input_accessor(void)
+{
+    return get_accessor<InputAccessor>();
+}
+
+inline std::unique_ptr<arm_compute::graph::ITensorAccessor> get_random_accessor(float lower, float upper)
+{
+    return get_accessor<InputAccessor>();
+}
+
+inline std::unique_ptr<arm_compute::graph::ITensorAccessor> get_weights_accessor(const std::string &path, const std::string &data_file, DataLayout file_layout = DataLayout::NCHW)
+{
+    return get_accessor<InputAccessor>();
+}
+
+inline std::unique_ptr<arm_compute::graph::ITensorAccessor> get_output_accessor(void)
+{
+    return get_accessor<OutputAccessor>();
+}
+
+/** Example demonstrating how to implement MobileNet's network using the Compute Library's graph API
+ *
+ * @param[in] argc Number of arguments
+ * @param[in] argv Arguments ( [optional] Target (0 = NEON, 1 = OpenCL), [optional] Path to the weights folder, [optional] image, [optional] labels )
+ */
+class GraphMobilenetExample
+{
+public:
+    void do_setup(int argc, char **argv)
+    {
+        std::string data_path; /* Path to the trainable data */
+        std::string image;     /* Image data */
+        std::string label;     /* Label data */
+
+        // Set target. 0 (NEON), 1 (OpenCL), 2 (OpenCL with Tuner). By default it is NEON
+        const int                  target                     = argc > 1 ? std::strtol(argv[1], nullptr, 10) : 0;
+        Target                     target_hint                = set_target_hint(target);
+        ConvolutionMethod          convolution_hint           = ConvolutionMethod::GEMM;
+        DepthwiseConvolutionMethod depthwise_convolution_hint = DepthwiseConvolutionMethod::Optimized3x3;
+        FastMathHint               fast_math_hint             = FastMathHint::Disabled;
+
+        // Set model to execute. 0 (MobileNetV1_1.0_224), 1 (MobileNetV1_0.75_160)
+        int model_id = (argc > 2) ? std::strtol(argv[2], nullptr, 10) : 0;
+        ARM_COMPUTE_ERROR_ON_MSG(model_id > 1, "Invalid model ID. Model must be 0 (MobileNetV1_1.0_224) or 1 (MobileNetV1_0.75_160)");
+        int layout_id = (argc > 3) ? std::strtol(argv[3], nullptr, 10) : 0;
+        ARM_COMPUTE_ERROR_ON_MSG(layout_id > 1, "Invalid layout ID. Layout must be 0 (NCHW) or 1 (NHWC)");
+
+        float            depth_scale           = (model_id == 0) ? 1.f : 0.75;
+        unsigned int     spatial_size          = (model_id == 0) ? 224 : 160;
+        std::string      model_path            = (model_id == 0) ? "/cnn_data/mobilenet_v1_1_224_model/" : "/cnn_data/mobilenet_v1_075_160_model/";
+        TensorDescriptor input_descriptor_nchw = TensorDescriptor(TensorShape(spatial_size, spatial_size, 3U, 1U), DataType::F32);
+        TensorDescriptor input_descriptor_nhwc = TensorDescriptor(TensorShape(3U, spatial_size, spatial_size, 1U), DataType::F32).set_layout(DataLayout::NHWC);
+        TensorDescriptor input_descriptor      = (layout_id == 0) ? input_descriptor_nchw : input_descriptor_nhwc;
+
+        // Parse arguments
+        if(argc < 2)
+        {
+            // Print help
+            std::cout << "Usage: " << argv[0] << " [target] [model] [layout] [path_to_data] [image] [labels] [fast_math_hint]\n\n";
+            std::cout << "No model ID provided: using MobileNetV1_1.0_224\n\n";
+            std::cout << "No data layout provided: using NCHW\n\n";
+            std::cout << "No data folder provided: using random values\n\n";
+        }
+        else if(argc == 2)
+        {
+            std::cout << "Usage: " << argv[0] << " " << argv[1] << " [model] [layout] [path_to_data] [image] [labels] [fast_math_hint]\n\n";
+            std::cout << "No model ID provided: using MobileNetV1_1.0_224\n\n";
+            std::cout << "No data layout provided: using NCHW\n\n";
+            std::cout << "No data folder provided: using random values\n\n";
+        }
+        else if(argc == 3)
+        {
+            std::cout << "Usage: " << argv[0] << " " << argv[1] << " " << argv[2] << " [layout] [path_to_data] [image] [labels] [fast_math_hint]\n\n";
+            std::cout << "No data layout provided: using NCHW\n\n";
+            std::cout << "No data folder provided: using random values\n\n";
+        }
+        else if(argc == 4)
+        {
+            std::cout << "Usage: " << argv[0] << " " << argv[1] << " " << argv[2] << " " << argv[3] << " [path_to_data] [image] [labels] [fast_math_hint]\n\n";
+            std::cout << "No data folder provided: using random values\n\n";
+        }
+        else if(argc == 5)
+        {
+            data_path = argv[4];
+            std::cout << "Usage: " << argv[0] << " " << argv[1] << " " << argv[2] << " " << argv[3] << " " << argv[4] << " [image] [labels] [fast_math_hint]\n\n";
+            std::cout << "No image provided: using random values\n\n";
+            std::cout << "No text file with labels provided: skipping output accessor\n\n";
+        }
+        else if(argc == 6)
+        {
+            data_path = argv[4];
+            image     = argv[5];
+            std::cout << "Usage: " << argv[0] << " " << argv[1] << " " << argv[2] << " " << argv[3] << " [labels] [fast_math_hint]\n\n";
+            std::cout << "No text file with labels provided: skipping output accessor\n\n";
+        }
+        else if(argc == 7)
+        {
+            data_path = argv[4];
+            image     = argv[5];
+            label     = argv[6];
+            std::cout << "Usage: " << argv[0] << " " << argv[1] << " " << argv[2] << " " << argv[3] << " " << argv[4] << " [fast_math_hint]\n\n";
+            std::cout << "No fast math info provided: disabling fast math\n\n";
+        }
+        else
+        {
+            data_path      = argv[4];
+            image          = argv[5];
+            label          = argv[6];
+            fast_math_hint = (std::strtol(argv[7], nullptr, 1) == 0) ? FastMathHint::Disabled : FastMathHint::Enabled;
+        }
+
+        // Add model path to data path
+        if(!data_path.empty())
+        {
+            data_path += model_path;
+        }
+
+        graph << target_hint
+              << convolution_hint
+              << depthwise_convolution_hint
+              << fast_math_hint
+              << InputLayer(input_descriptor,
+                            get_input_accessor())
+              << ConvolutionLayer(
+                  3U, 3U, 32U * depth_scale,
+                  get_weights_accessor(data_path, "Conv2d_0_weights.npy", DataLayout::NCHW),
+                  std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+                  PadStrideInfo(2, 2, 0, 1, 0, 1, DimensionRoundingType::FLOOR))
+              .set_name("Conv2d_0")
+              << BatchNormalizationLayer(
+                  get_weights_accessor(data_path, "Conv2d_0_BatchNorm_moving_mean.npy"),
+                  get_weights_accessor(data_path, "Conv2d_0_BatchNorm_moving_variance.npy"),
+                  get_weights_accessor(data_path, "Conv2d_0_BatchNorm_gamma.npy"),
+                  get_weights_accessor(data_path, "Conv2d_0_BatchNorm_beta.npy"),
+                  0.001f)
+              .set_name("Conv2d_0/BatchNorm")
+              << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::BOUNDED_RELU, 6.f)).set_name("Conv2d_0/Relu6");
+        graph << get_dwsc_node(data_path, "Conv2d_1", 64 * depth_scale, PadStrideInfo(1, 1, 1, 1), PadStrideInfo(1, 1, 0, 0));
+        graph << get_dwsc_node(data_path, "Conv2d_2", 128 * depth_scale, PadStrideInfo(2, 2, 0, 1, 0, 1, DimensionRoundingType::CEIL), PadStrideInfo(1, 1, 0, 0));
+        graph << get_dwsc_node(data_path, "Conv2d_3", 128 * depth_scale, PadStrideInfo(1, 1, 1, 1, 1, 1, DimensionRoundingType::CEIL), PadStrideInfo(1, 1, 0, 0));
+        graph << get_dwsc_node(data_path, "Conv2d_4", 256 * depth_scale, PadStrideInfo(2, 2, 0, 1, 0, 1, DimensionRoundingType::CEIL), PadStrideInfo(1, 1, 0, 0));
+        graph << get_dwsc_node(data_path, "Conv2d_5", 256 * depth_scale, PadStrideInfo(1, 1, 1, 1, 1, 1, DimensionRoundingType::CEIL), PadStrideInfo(1, 1, 0, 0));
+        graph << get_dwsc_node(data_path, "Conv2d_6", 512 * depth_scale, PadStrideInfo(2, 2, 0, 1, 0, 1, DimensionRoundingType::CEIL), PadStrideInfo(1, 1, 0, 0));
+        graph << get_dwsc_node(data_path, "Conv2d_7", 512 * depth_scale, PadStrideInfo(1, 1, 1, 1, 1, 1, DimensionRoundingType::CEIL), PadStrideInfo(1, 1, 0, 0));
+        graph << get_dwsc_node(data_path, "Conv2d_8", 512 * depth_scale, PadStrideInfo(1, 1, 1, 1, 1, 1, DimensionRoundingType::CEIL), PadStrideInfo(1, 1, 0, 0));
+        graph << get_dwsc_node(data_path, "Conv2d_9", 512 * depth_scale, PadStrideInfo(1, 1, 1, 1, 1, 1, DimensionRoundingType::CEIL), PadStrideInfo(1, 1, 0, 0));
+        graph << get_dwsc_node(data_path, "Conv2d_10", 512 * depth_scale, PadStrideInfo(1, 1, 1, 1, 1, 1, DimensionRoundingType::CEIL), PadStrideInfo(1, 1, 0, 0));
+        graph << get_dwsc_node(data_path, "Conv2d_11", 512 * depth_scale, PadStrideInfo(1, 1, 1, 1, 1, 1, DimensionRoundingType::CEIL), PadStrideInfo(1, 1, 0, 0));
+        graph << get_dwsc_node(data_path, "Conv2d_12", 1024 * depth_scale, PadStrideInfo(2, 2, 0, 1, 0, 1, DimensionRoundingType::CEIL), PadStrideInfo(1, 1, 0, 0));
+        graph << get_dwsc_node(data_path, "Conv2d_13", 1024 * depth_scale, PadStrideInfo(1, 1, 1, 1, 1, 1, DimensionRoundingType::CEIL), PadStrideInfo(1, 1, 0, 0));
+        graph << PoolingLayer(PoolingLayerInfo(PoolingType::AVG)).set_name("Logits/AvgPool_1a")
+              << ConvolutionLayer(
+                  1U, 1U, 1001U,
+                  get_weights_accessor(data_path, "Logits_Conv2d_1c_1x1_weights.npy", DataLayout::NCHW),
+                  get_weights_accessor(data_path, "Logits_Conv2d_1c_1x1_biases.npy"),
+                  PadStrideInfo(1, 1, 0, 0))
+              .set_name("Logits/Conv2d_1c_1x1")
+              << ReshapeLayer(TensorShape(1001U)).set_name("Reshape")
+              << SoftmaxLayer().set_name("Softmax")
+              << OutputLayer(get_output_accessor());
+
+        // Finalize graph
+        GraphConfig config;
+        config.use_tuner = (target == 2);
+        graph.finalize(target_hint, config);
+    }
+    void do_run()
+    {
+        run_benchmark(graph);
+    }
+
+private:
+    Stream graph{ 0, "MobileNetV1" };
+
+    ConcatLayer get_dwsc_node(const std::string &data_path, std::string &&param_path,
+                              unsigned int  conv_filt,
+                              PadStrideInfo dwc_pad_stride_info, PadStrideInfo conv_pad_stride_info)
+    {
+        std::string total_path = param_path + "_";
+        SubStream   sg(graph);
+        sg << DepthwiseConvolutionLayer(
+               3U, 3U,
+               get_weights_accessor(data_path, total_path + "depthwise_depthwise_weights.npy", DataLayout::NCHW),
+               std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+               dwc_pad_stride_info)
+           .set_name(total_path + "depthwise/depthwise")
+           << BatchNormalizationLayer(
+               get_weights_accessor(data_path, total_path + "depthwise_BatchNorm_moving_mean.npy"),
+               get_weights_accessor(data_path, total_path + "depthwise_BatchNorm_moving_variance.npy"),
+               get_weights_accessor(data_path, total_path + "depthwise_BatchNorm_gamma.npy"),
+               get_weights_accessor(data_path, total_path + "depthwise_BatchNorm_beta.npy"),
+               0.001f)
+           .set_name(total_path + "depthwise/BatchNorm")
+           << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::BOUNDED_RELU, 6.f)).set_name(total_path + "depthwise/Relu6")
+           << ConvolutionLayer(
+               1U, 1U, conv_filt,
+               get_weights_accessor(data_path, total_path + "pointwise_weights.npy", DataLayout::NCHW),
+               std::unique_ptr<arm_compute::graph::ITensorAccessor>(nullptr),
+               conv_pad_stride_info)
+           .set_name(total_path + "pointwise/Conv2D")
+           << BatchNormalizationLayer(
+               get_weights_accessor(data_path, total_path + "pointwise_BatchNorm_moving_mean.npy"),
+               get_weights_accessor(data_path, total_path + "pointwise_BatchNorm_moving_variance.npy"),
+               get_weights_accessor(data_path, total_path + "pointwise_BatchNorm_gamma.npy"),
+               get_weights_accessor(data_path, total_path + "pointwise_BatchNorm_beta.npy"),
+               0.001f)
+           .set_name(total_path + "pointwise/BatchNorm")
+           << ActivationLayer(ActivationLayerInfo(ActivationLayerInfo::ActivationFunction::BOUNDED_RELU, 6.f)).set_name(total_path + "pointwise/Relu6");
+
+        return ConcatLayer(std::move(sg));
+    }
+};
+
+/** Main program for MobileNetV1
+ *
+ * @param[in] argc Number of arguments
+ * @param[in] argv Arguments ( [optional] Target (0 = NEON, 1 = OpenCL, 2 = OpenCL with Tuner),
+ *                             [optional] Model ID (0 = MobileNetV1_1.0_224, 1 = MobileNetV1_0.75_160),
+ *                             [optional] Path to the weights folder,
+ *                             [optional] image,
+ *                             [optional] labels,
+ *                             [optional] data layout,
+ *                             [optional] Fast math for convolution layer (0 = DISABLED, 1 = ENABLED) )
+ */
+int main(int argc, char **argv)
+{
+    GraphMobilenetExample example;
+
+    example.do_setup(argc, argv);
+    example.do_run();
+
+    return 0;
+}
diff --git a/runtime/contrib/custom_op/README.md b/runtime/contrib/custom_op/README.md
new file mode 100644
index 000000000..7815ce9d5
--- /dev/null
+++ b/runtime/contrib/custom_op/README.md
@@ -0,0 +1,25 @@
+This document is about custom operators.
+
+# Introduction
+
+# Requirements
+
+- [ ] Support tizen in-house custom op developer
+- [ ] Minimiz exposed headers (structures and functions)
+- [ ] Provide acceptable performance
+
+# Design
+
+## Design
+
+### Workflow
+
+![](customOp-workflow.png)
+
+## Candidate Architecture 1
+
+## Candidate Architecture 2
+
+## Discussion
+
+# Conclusion
diff --git a/runtime/contrib/custom_op/customOp-workflow.png b/runtime/contrib/custom_op/customOp-workflow.png
new file mode 100644
index 000000000..0487f5b63
--- /dev/null
+++ b/runtime/contrib/custom_op/customOp-workflow.png
diff --git a/runtime/contrib/detection/CMakeLists.txt b/runtime/contrib/detection/CMakeLists.txt
new file mode 100644
index 000000000..37d91b527
--- /dev/null
+++ b/runtime/contrib/detection/CMakeLists.txt
@@ -0,0 +1,11 @@
+if(NOT BUILD_DETECTION_APP)
+  return()
+endif(NOT BUILD_DETECTION_APP)
+
+nnfw_find_package(Tensorflow REQUIRED)
+
+list(APPEND SOURCES detection.cpp)
+
+add_executable(detection ${SOURCES})
+target_link_libraries(detection nnfw_lib_misc)
+target_link_libraries(detection tensorflow-core)
diff --git a/runtime/contrib/detection/detection.cpp b/runtime/contrib/detection/detection.cpp
new file mode 100644
index 000000000..8fe78ca57
--- /dev/null
+++ b/runtime/contrib/detection/detection.cpp
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <tensorflow/core/public/session.h>
+
+#include <iostream>
+#include <stdexcept>
+
+#include <cassert>
+#include <cstring>
+
+#include "misc/benchmark.h"
+
+#define CHECK_TF(e)                                \
+  {                                                \
+    if (!(e).ok())                                 \
+    {                                              \
+      throw std::runtime_error{"'" #e "' FAILED"}; \
+    }                                              \
+  }
+
+int main(int argc, char **argv)
+{
+  if (argc < 2)
+  {
+    std::cerr << "USAGE: " << argv[0] << " [T/F model path] [output 0] [output 1] ..." << std::endl;
+    return 255;
+  }
+
+  std::vector<std::string> output_nodes;
+
+  for (int argn = 2; argn < argc; ++argn)
+  {
+    output_nodes.emplace_back(argv[argn]);
+  }
+
+  tensorflow::Session *sess;
+
+  CHECK_TF(tensorflow::NewSession(tensorflow::SessionOptions(), &sess));
+
+  tensorflow::GraphDef graph_def;
+
+  CHECK_TF(ReadBinaryProto(tensorflow::Env::Default(), argv[1], &graph_def));
+  CHECK_TF(sess->Create(graph_def));
+
+  tensorflow::Tensor input(tensorflow::DT_FLOAT, tensorflow::TensorShape({1, 320, 320, 3}));
+  std::vector<tensorflow::Tensor> outputs;
+
+  for (uint32_t n = 0; n < 5; ++n)
+  {
+    std::chrono::milliseconds elapsed(0);
+
+    nnfw::misc::benchmark::measure(elapsed) << [&](void) {
+      CHECK_TF(sess->Run({{"input_node", input}}, output_nodes, {}, &outputs));
+    };
+
+    std::cout << "Takes " << elapsed.count() << "ms" << std::endl;
+  }
+
+  return 0;
+}
diff --git a/runtime/contrib/heap_trace/CMakeLists.txt b/runtime/contrib/heap_trace/CMakeLists.txt
new file mode 100644
index 000000000..1f18152d8
--- /dev/null
+++ b/runtime/contrib/heap_trace/CMakeLists.txt
@@ -0,0 +1,18 @@
+if(NOT BUILD_HEAP_TRACE)
+  return()
+endif(NOT BUILD_HEAP_TRACE)
+
+add_library(heap_trace SHARED src/cl_create_buffer_stub.cc
+                              src/cl_release_mem_object.cc
+                              src/free_stub.cc
+                              src/malloc_stub.cc
+                              src/realloc_stub.cc
+                              src/valloc_stub.cc
+                              src/symbol_searcher.cc
+                              src/trace.cc
+)
+target_link_libraries(heap_trace PRIVATE ${CMAKE_DL_LIBS})
+
+add_subdirectory(tests)
+
+install(TARGETS heap_trace DESTINATION lib)
diff --git a/runtime/contrib/heap_trace/src/cl_create_buffer_stub.cc b/runtime/contrib/heap_trace/src/cl_create_buffer_stub.cc
new file mode 100644
index 000000000..d9d2700ee
--- /dev/null
+++ b/runtime/contrib/heap_trace/src/cl_create_buffer_stub.cc
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "trace.h"
+#include "function_resolver.h"
+
+#include <CL/cl.h>
+
+#include <memory>
+
+extern std::unique_ptr<Trace> GlobalTrace;
+
+extern "C" {
+
+cl_mem clCreateBuffer(cl_context context, cl_mem_flags flags, size_t size, void *host_ptr,
+                      cl_int *errcode_ret)
+{
+  static auto isOriginalFunctionCallSuccessful = [](cl_mem result) -> bool { return result; };
+
+  static auto originalFunction =
+      findFunctionByName<cl_mem, cl_context, cl_mem_flags, size_t, void *, cl_int *>(
+          "clCreateBuffer");
+  cl_mem result = originalFunction(context, flags, size, host_ptr, errcode_ret);
+  if (isOriginalFunctionCallSuccessful(result) && !Trace::Guard{}.isActive())
+  {
+    GlobalTrace->logAllocationEvent(result, size);
+  }
+
+  return result;
+}
+}
diff --git a/runtime/contrib/heap_trace/src/cl_release_mem_object.cc b/runtime/contrib/heap_trace/src/cl_release_mem_object.cc
new file mode 100644
index 000000000..f2f249e0b
--- /dev/null
+++ b/runtime/contrib/heap_trace/src/cl_release_mem_object.cc
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "trace.h"
+#include "function_resolver.h"
+
+#include <CL/cl.h>
+
+#include <memory>
+
+extern std::unique_ptr<Trace> GlobalTrace;
+
+extern "C" {
+
+cl_int clReleaseMemObject(cl_mem mem)
+{
+  static auto isOriginalFunctionCallSuccessful = [](cl_int result) -> bool {
+    return result == CL_SUCCESS;
+  };
+
+  auto originalFunction = findFunctionByName<cl_int, cl_mem>("clReleaseMemObject");
+  cl_int result = originalFunction(mem);
+  if (isOriginalFunctionCallSuccessful(result) && !Trace::Guard{}.isActive())
+  {
+    GlobalTrace->logDeallocationEvent(mem);
+  }
+
+  return result;
+}
+}
diff --git a/runtime/contrib/heap_trace/src/free_stub.cc b/runtime/contrib/heap_trace/src/free_stub.cc
new file mode 100644
index 000000000..31af63c8a
--- /dev/null
+++ b/runtime/contrib/heap_trace/src/free_stub.cc
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "trace.h"
+#include "function_resolver.h"
+
+#include <memory>
+
+extern std::unique_ptr<Trace> GlobalTrace;
+
+extern "C" {
+
+void free(void *p) noexcept
+{
+  static auto originalFunction = findFunctionByName<void, void *>("free");
+  originalFunction(p);
+  if (!Trace::Guard{}.isActive())
+  {
+    GlobalTrace->logDeallocationEvent(p);
+  }
+}
+}
diff --git a/runtime/contrib/heap_trace/src/function_resolver.h b/runtime/contrib/heap_trace/src/function_resolver.h
new file mode 100644
index 000000000..9b6879539
--- /dev/null
+++ b/runtime/contrib/heap_trace/src/function_resolver.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef FUNCTION_RESOLVER_H
+#define FUNCTION_RESOLVER_H
+
+#include "symbol_searcher.h"
+
+template <typename ReturnType, typename... ArgTypes>
+ReturnType (*findFunctionByName(const char *function_name))(ArgTypes...)
+{
+  auto found_symbol = findSymbol(function_name);
+  return reinterpret_cast<ReturnType (*)(ArgTypes...)>(found_symbol);
+}
+
+#endif // ! FUNCTION_RESOLVER_H
diff --git a/runtime/contrib/heap_trace/src/malloc_stub.cc b/runtime/contrib/heap_trace/src/malloc_stub.cc
new file mode 100644
index 000000000..50124d164
--- /dev/null
+++ b/runtime/contrib/heap_trace/src/malloc_stub.cc
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "trace.h"
+#include "function_resolver.h"
+
+#include <memory>
+
+extern std::unique_ptr<Trace> GlobalTrace;
+
+extern "C" {
+
+void *malloc(size_t sz) noexcept
+{
+  static auto isOriginalFunctionCallSuccessful = [](void *result) -> bool { return result; };
+
+  static auto originalFunction = findFunctionByName<void *, size_t>("malloc");
+  void *result = originalFunction(sz);
+  if (isOriginalFunctionCallSuccessful(result) && !Trace::Guard{}.isActive())
+  {
+    GlobalTrace->logAllocationEvent(result, sz);
+  }
+
+  return result;
+}
+}
diff --git a/runtime/contrib/heap_trace/src/realloc_stub.cc b/runtime/contrib/heap_trace/src/realloc_stub.cc
new file mode 100644
index 000000000..ce4569b0e
--- /dev/null
+++ b/runtime/contrib/heap_trace/src/realloc_stub.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "trace.h"
+#include "function_resolver.h"
+
+#include <memory>
+
+extern std::unique_ptr<Trace> GlobalTrace;
+
+extern "C" {
+
+void *realloc(void *ptr, size_t sz) noexcept
+{
+  static auto isOriginalFunctionCallSuccessful = [](void *result) -> bool { return result; };
+
+  static auto originalFunction = findFunctionByName<void *, void *, size_t>("realloc");
+  void *result = originalFunction(ptr, sz);
+  if (isOriginalFunctionCallSuccessful(result) && !Trace::Guard{}.isActive())
+  {
+    GlobalTrace->logDeallocationEvent(ptr);
+    GlobalTrace->logAllocationEvent(result, sz);
+  }
+
+  return result;
+}
+}
diff --git a/runtime/contrib/heap_trace/src/symbol_searcher.cc b/runtime/contrib/heap_trace/src/symbol_searcher.cc
new file mode 100644
index 000000000..cf83f2f7b
--- /dev/null
+++ b/runtime/contrib/heap_trace/src/symbol_searcher.cc
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "symbol_searcher.h"
+
+#include <dlfcn.h>
+#include <link.h>
+
+struct SymbolDescription
+{
+  const char *name;
+  void *address = nullptr; // address in memory where this symbol can be found
+
+  SymbolDescription(const char *name) : name(name) {}
+};
+
+using InfoAboutLoadedLib = struct dl_phdr_info *;
+
+static void tryToFindSymbolInLinkedLibraries(SymbolDescription &symbol);
+static void tryToFindSymbolInAllLoadedLibraries(SymbolDescription &symbol);
+static int checkIfLibraryContainsSymbol(InfoAboutLoadedLib library_description, size_t /* size */,
+                                        void *data);
+static bool isSymbolAddressNotInTheSameTranslationUnit(SymbolDescription *symbol);
+void *findSymbol(const char *name)
+{
+  SymbolDescription symbol(name);
+  tryToFindSymbolInLinkedLibraries(symbol);
+  if (!symbol.address)
+  {
+    tryToFindSymbolInAllLoadedLibraries(symbol);
+  }
+
+  return symbol.address;
+}
+
+static void tryToFindSymbolInLinkedLibraries(SymbolDescription &symbol)
+{
+  symbol.address = dlsym(RTLD_NEXT, symbol.name);
+}
+
+static void tryToFindSymbolInAllLoadedLibraries(SymbolDescription &symbol)
+{
+  dl_iterate_phdr(checkIfLibraryContainsSymbol, &symbol);
+}
+
+static int checkIfLibraryContainsSymbol(InfoAboutLoadedLib library_description, size_t /* size */,
+                                        void *data)
+{
+  SymbolDescription *symbol = (SymbolDescription *)data;
+
+  void *handle = dlopen(library_description->dlpi_name, RTLD_NOW);
+  symbol->address = dlsym(handle, symbol->name);
+  dlclose(handle);
+  if (symbol->address && isSymbolAddressNotInTheSameTranslationUnit(symbol))
+  {
+    return 1;
+  }
+  return 0;
+}
+
+static bool isSymbolAddressNotInTheSameTranslationUnit(SymbolDescription *symbol)
+{
+  void *handle = dlopen("", RTLD_NOW);
+  void *addressInTheSameTranslationUnit = dlsym(handle, symbol->name);
+  dlclose(handle);
+
+  return addressInTheSameTranslationUnit == nullptr ||
+         addressInTheSameTranslationUnit != symbol->address;
+}
diff --git a/runtime/contrib/heap_trace/src/symbol_searcher.h b/runtime/contrib/heap_trace/src/symbol_searcher.h
new file mode 100644
index 000000000..f70a4e46f
--- /dev/null
+++ b/runtime/contrib/heap_trace/src/symbol_searcher.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef SYMBOL_SEARCHER_H
+#define SYMBOL_SEARCHER_H
+
+void *findSymbol(const char *name);
+
+#endif // ! SYMBOL_SEARCHER_H
diff --git a/runtime/contrib/heap_trace/src/trace.cc b/runtime/contrib/heap_trace/src/trace.cc
new file mode 100644
index 000000000..82f2915cb
--- /dev/null
+++ b/runtime/contrib/heap_trace/src/trace.cc
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "trace.h"
+
+#include <memory>
+
+std::unique_ptr<Trace> GlobalTrace(new Trace);
+
+bool Trace::Guard::_is_trace_not_available = true;
+thread_local bool Trace::Guard::_is_recursion_detected = false;
+
+Trace::Trace()
+{
+  if (!_out.is_open())
+  {
+    _out.open(getLogFileNameFromEnvVariable("HEAP_TRACE_LOG"));
+  }
+
+  Guard{}.markTraceAsReady();
+}
+
+const char *Trace::getLogFileNameFromEnvVariable(const char *env_variable_name)
+{
+  return getenv(env_variable_name);
+}
+
+void Trace::logAllocationEvent(void *memory_ptr, size_t size_of_allocated_space_in_bytes)
+{
+  Guard{}.signalizeAboutPossibleRecursion();
+  std::lock_guard<std::mutex> guard(_lock);
+  _total_allocated_bytes_on_cpu += size_of_allocated_space_in_bytes;
+  if (_peak_heap_usage_on_cpu < _total_allocated_bytes_on_cpu - _total_deallocated_bytes_on_cpu)
+  {
+    _peak_heap_usage_on_cpu = _total_allocated_bytes_on_cpu - _total_deallocated_bytes_on_cpu;
+  }
+  _memory_in_use_on_cpu[memory_ptr] = size_of_allocated_space_in_bytes;
+  Guard{}.signalizeThatDangerOfRecursionHAsPassed();
+}
+
+void Trace::logDeallocationEvent(void *memory_ptr)
+{
+  Guard{}.signalizeAboutPossibleRecursion();
+  std::lock_guard<std::mutex> guard(_lock);
+  auto found_memory_space_description = _memory_in_use_on_cpu.find(memory_ptr);
+  if (found_memory_space_description != _memory_in_use_on_cpu.end())
+  {
+    _total_deallocated_bytes_on_cpu += found_memory_space_description->second;
+    _memory_in_use_on_cpu.erase(found_memory_space_description);
+  }
+  Guard{}.signalizeThatDangerOfRecursionHAsPassed();
+}
+
+void Trace::logAllocationEvent(cl_mem memory_ptr, size_t size_of_allocated_space_in_bytes)
+{
+  Guard{}.signalizeAboutPossibleRecursion();
+  std::lock_guard<std::mutex> guard(_lock);
+  _total_allocated_bytes_on_gpu += size_of_allocated_space_in_bytes;
+  if (_peak_heap_usage_on_gpu < _total_allocated_bytes_on_gpu - _total_deallocated_bytes_on_gpu)
+  {
+    _peak_heap_usage_on_gpu = _total_allocated_bytes_on_gpu - _total_deallocated_bytes_on_gpu;
+  }
+  _memory_in_use_on_gpu[memory_ptr] = size_of_allocated_space_in_bytes;
+  Guard{}.signalizeThatDangerOfRecursionHAsPassed();
+}
+
+void Trace::logDeallocationEvent(cl_mem memory_ptr)
+{
+  Guard{}.signalizeAboutPossibleRecursion();
+  std::lock_guard<std::mutex> guard(_lock);
+  auto found_memory_space_description = _memory_in_use_on_gpu.find(memory_ptr);
+  if (found_memory_space_description != _memory_in_use_on_gpu.end())
+  {
+    _total_deallocated_bytes_on_gpu += found_memory_space_description->second;
+    _memory_in_use_on_gpu.erase(found_memory_space_description);
+  }
+  Guard{}.signalizeThatDangerOfRecursionHAsPassed();
+}
+
+Trace::~Trace()
+{
+  Guard{}.markTraceAsNotReady();
+
+  _out << "On CPU - Peak heap usage: " << _peak_heap_usage_on_cpu
+       << " B, Total allocated: " << _total_allocated_bytes_on_cpu
+       << " B, Total deallocated: " << _total_deallocated_bytes_on_cpu << " B\n";
+  _out << "On GPU - Peak mem usage: " << _peak_heap_usage_on_gpu
+       << " B, Total allocated: " << _total_allocated_bytes_on_gpu
+       << " B, Total deallocated: " << _total_deallocated_bytes_on_gpu << " B\n";
+}
diff --git a/runtime/contrib/heap_trace/src/trace.h b/runtime/contrib/heap_trace/src/trace.h
new file mode 100644
index 000000000..f03a65a58
--- /dev/null
+++ b/runtime/contrib/heap_trace/src/trace.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef TRACE_H_
+#define TRACE_H_
+
+#include <CL/cl.h>
+
+#include <unordered_map>
+#include <fstream>
+#include <mutex>
+
+class Trace
+{
+public:
+  class Guard
+  {
+    friend class Trace;
+
+  public:
+    bool isActive() { return _is_trace_not_available || _is_recursion_detected; }
+
+  private:
+    void markTraceAsReady() { _is_trace_not_available = false; }
+    void markTraceAsNotReady() { _is_trace_not_available = true; }
+    void signalizeAboutPossibleRecursion() { _is_recursion_detected = true; }
+    void signalizeThatDangerOfRecursionHAsPassed() { _is_recursion_detected = false; }
+
+  private:
+    static bool _is_trace_not_available;
+    static thread_local bool _is_recursion_detected;
+  };
+
+public:
+  Trace();
+  Trace(const Trace &) = delete;
+  const Trace &operator=(const Trace &) = delete;
+
+  void logAllocationEvent(void *memory_ptr, size_t size_of_allocated_space_in_bytes);
+  void logAllocationEvent(cl_mem memory_ptr, size_t size_of_allocated_space_in_bytes);
+  void logDeallocationEvent(void *memory_ptr);
+  void logDeallocationEvent(cl_mem memory_ptr);
+
+  ~Trace();
+
+private:
+  const char *getLogFileNameFromEnvVariable(const char *env_variable_name);
+
+private:
+  std::mutex _lock;
+  std::ofstream _out;
+  size_t _total_allocated_bytes_on_cpu = 0;
+  size_t _total_deallocated_bytes_on_cpu = 0;
+  size_t _peak_heap_usage_on_cpu = 0;
+  size_t _total_allocated_bytes_on_gpu = 0;
+  size_t _total_deallocated_bytes_on_gpu = 0;
+  size_t _peak_heap_usage_on_gpu = 0;
+  std::unordered_map<void *, size_t> _memory_in_use_on_cpu;
+  std::unordered_map<cl_mem, size_t> _memory_in_use_on_gpu;
+};
+
+#endif // !TRACE_H
diff --git a/runtime/contrib/heap_trace/src/valloc_stub.cc b/runtime/contrib/heap_trace/src/valloc_stub.cc
new file mode 100644
index 000000000..24e91bd11
--- /dev/null
+++ b/runtime/contrib/heap_trace/src/valloc_stub.cc
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "trace.h"
+#include "function_resolver.h"
+
+#include <memory>
+
+extern std::unique_ptr<Trace> GlobalTrace;
+
+extern "C" {
+
+void *valloc(size_t sz) noexcept
+{
+  static auto isOriginalFunctionCallSuccessful = [](void *result) -> bool { return result; };
+
+  static auto originalFunction = findFunctionByName<void *, size_t>("valloc");
+  void *result = originalFunction(sz);
+  if (isOriginalFunctionCallSuccessful(result) && !Trace::Guard{}.isActive())
+  {
+    GlobalTrace->logAllocationEvent(result, sz);
+  }
+
+  return result;
+}
+}
diff --git a/runtime/contrib/heap_trace/tests/CMakeLists.txt b/runtime/contrib/heap_trace/tests/CMakeLists.txt
new file mode 100644
index 000000000..8fbe5dec1
--- /dev/null
+++ b/runtime/contrib/heap_trace/tests/CMakeLists.txt
@@ -0,0 +1,43 @@
+set(HEAP_TRACE_TESTS heap_trace_test)
+
+find_package(OpenCL REQUIRED)
+
+add_library(test_sample1 SHARED src/test_sample1/test_sample1.cc)
+
+add_library(test_sample2 SHARED src/test_sample2/test_sample2.cc)
+target_link_libraries(test_sample2 test_sample3)
+
+add_library(test_sample3 SHARED src/test_sample3/test_sample3.cc)
+
+add_library(test_sample4 SHARED src/test_sample4/test_sample4.cc)
+
+add_executable(${HEAP_TRACE_TESTS} src/cl_release_mem_object_interception_test.cc
+        src/symbol_searcher_test.cc
+        src/cl_create_buffer_interception_test.cc
+        src/free_interception_test.cc
+        src/main.cc
+        src/common_test_environment.cc
+        src/trace_test.cc
+        src/malloc_interception_test.cc
+        src/realloc_interception_test.cc
+        src/valloc_interception_test.cc
+        src/file_content_manipulations.cc
+        )
+target_include_directories(${HEAP_TRACE_TESTS} PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/../src)
+target_link_libraries(${HEAP_TRACE_TESTS} test_sample1)
+target_link_libraries(${HEAP_TRACE_TESTS} heap_trace)
+target_link_libraries(${HEAP_TRACE_TESTS} test_sample4)
+target_link_libraries(${HEAP_TRACE_TESTS} gtest)
+target_link_libraries(${HEAP_TRACE_TESTS} gtest_main)
+target_link_libraries(${HEAP_TRACE_TESTS} ${LIB_PTHREAD})
+target_link_libraries(${HEAP_TRACE_TESTS} ${CMAKE_DL_LIBS})
+target_link_libraries(${HEAP_TRACE_TESTS} ${OpenCL_LIBRARY})
+target_link_libraries(${HEAP_TRACE_TESTS} stdc++fs)
+
+add_test(${HEAP_TRACE_TESTS} ${HEAP_TRACE_TESTS})
+
+install(TARGETS test_sample1 DESTINATION unittest)
+install(TARGETS test_sample2 DESTINATION unittest)
+install(TARGETS test_sample3 DESTINATION unittest)
+install(TARGETS test_sample4 DESTINATION unittest)
+install(TARGETS ${HEAP_TRACE_TESTS} DESTINATION unittest)
diff --git a/runtime/contrib/heap_trace/tests/src/cl_create_buffer_interception_test.cc b/runtime/contrib/heap_trace/tests/src/cl_create_buffer_interception_test.cc
new file mode 100644
index 000000000..33d01868e
--- /dev/null
+++ b/runtime/contrib/heap_trace/tests/src/cl_create_buffer_interception_test.cc
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "common_test_environment.h"
+#include "file_content_manipulations.h"
+
+#include "trace.h"
+
+#include <CL/cl.h>
+
+extern std::unique_ptr<Trace> GlobalTrace;
+
+namespace backstage
+{
+
+struct ClCreateBufferStub : public TestEnv
+{
+  cl_context context;
+
+  ClCreateBufferStub() : TestEnv("./cl_create_buffer_interception_test.log") {}
+
+  void SetUp() final
+  {
+    cl_device_id device_id;
+    int err = clGetDeviceIDs(NULL, CL_DEVICE_TYPE_GPU, 1, &device_id, NULL);
+    context = clCreateContext(0, 1, &device_id, NULL, NULL, &err);
+
+    TestEnv::SetUp();
+  }
+
+  void TearDown() final
+  {
+    TestEnv::TearDown();
+
+    clReleaseContext(context);
+  }
+};
+
+TEST_F(ClCreateBufferStub, must_allocate_space_as_standard_ocl_function)
+{
+  cl_mem mem = clCreateBuffer(context, CL_MEM_READ_WRITE, 1024 * 1024, NULL, NULL);
+
+  ASSERT_TRUE(mem);
+
+  clReleaseMemObject(mem);
+}
+
+TEST_F(ClCreateBufferStub, must_log_allocation_events_if_trace_is_ready_for_it)
+{
+  GlobalTrace.reset();
+  clReleaseMemObject(clCreateBuffer(context, CL_MEM_READ_WRITE, 1024, NULL, NULL));
+
+  GlobalTrace.reset(new Trace);
+  clReleaseMemObject(clCreateBuffer(context, CL_MEM_READ_WRITE, 128, NULL, NULL));
+  clReleaseMemObject(clCreateBuffer(context, CL_MEM_READ_WRITE, 64, NULL, NULL));
+  GlobalTrace.reset();
+
+  ASSERT_STREQ(getContentOfFile("./cl_create_buffer_interception_test.log").c_str(),
+               "On CPU - Peak heap usage: 0 B, Total allocated: 0 B, Total deallocated: 0 B\nOn "
+               "GPU - Peak mem usage: 128 B, Total allocated: 192 B, Total deallocated: 192 B\n");
+}
+
+TEST_F(ClCreateBufferStub,
+       must_not_do_the_record_about_allocation_event_if_original_function_failed)
+{
+  cl_context badContext = nullptr;
+  cl_mem p = clCreateBuffer(badContext, CL_MEM_READ_WRITE, 1024, nullptr, nullptr);
+  GlobalTrace.reset();
+
+  ASSERT_FALSE(p);
+  ASSERT_STREQ(getContentOfFile("./cl_create_buffer_interception_test.log").c_str(),
+               "On CPU - Peak heap usage: 0 B, Total allocated: 0 B, Total deallocated: 0 B\nOn "
+               "GPU - Peak mem usage: 0 B, Total allocated: 0 B, Total deallocated: 0 B\n");
+}
+
+} // namespace backstage
diff --git a/runtime/contrib/heap_trace/tests/src/cl_release_mem_object_interception_test.cc b/runtime/contrib/heap_trace/tests/src/cl_release_mem_object_interception_test.cc
new file mode 100644
index 000000000..ddd1a0d5c
--- /dev/null
+++ b/runtime/contrib/heap_trace/tests/src/cl_release_mem_object_interception_test.cc
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "common_test_environment.h"
+#include "file_content_manipulations.h"
+
+#include "trace.h"
+
+#include <CL/cl.h>
+
+extern std::unique_ptr<Trace> GlobalTrace;
+
+namespace backstage
+{
+
+struct ClReleaseMemObjectStub : public TestEnv
+{
+  cl_context context;
+
+  ClReleaseMemObjectStub() : TestEnv("./cl_release_mem_object_interception_test.log") {}
+
+  void SetUp() final
+  {
+    cl_device_id device_id;
+    int err = clGetDeviceIDs(NULL, CL_DEVICE_TYPE_GPU, 1, &device_id, NULL);
+    context = clCreateContext(0, 1, &device_id, NULL, NULL, &err);
+
+    TestEnv::SetUp();
+  }
+
+  void TearDown() final
+  {
+    TestEnv::TearDown();
+
+    clReleaseContext(context);
+  }
+};
+
+TEST_F(ClReleaseMemObjectStub, should_work_as_standard_version)
+{
+  cl_mem mem = clCreateBuffer(context, CL_MEM_READ_WRITE, 1024, NULL, NULL);
+  clReleaseMemObject(mem);
+  ASSERT_TRUE(mem);
+}
+
+TEST_F(ClReleaseMemObjectStub, must_log_deallocation_events_if_trace_is_ready_for_it)
+{
+  GlobalTrace.reset();
+  cl_mem mem1 = clCreateBuffer(context, CL_MEM_READ_WRITE, 1024, NULL, NULL);
+  ASSERT_TRUE(mem1);
+  clReleaseMemObject(mem1);
+
+  GlobalTrace.reset(new Trace);
+  cl_mem mem2 = clCreateBuffer(context, CL_MEM_READ_WRITE, 128, NULL, NULL);
+  cl_mem mem3 = clCreateBuffer(context, CL_MEM_READ_WRITE, 64, NULL, NULL);
+  ASSERT_TRUE(mem2 && mem3);
+  clReleaseMemObject(mem2);
+  clReleaseMemObject(mem3);
+  GlobalTrace.reset();
+
+  ASSERT_STREQ(getContentOfFile("./cl_release_mem_object_interception_test.log").c_str(),
+               "On CPU - Peak heap usage: 0 B, Total allocated: 0 B, Total deallocated: 0 B\nOn "
+               "GPU - Peak mem usage: 192 B, Total allocated: 192 B, Total deallocated: 192 B\n");
+}
+
+TEST_F(ClReleaseMemObjectStub, must_not_log_deallocation_event_if_original_function_failed)
+{
+  cl_mem mem;
+  ASSERT_NE(clReleaseMemObject(mem), CL_SUCCESS);
+
+  GlobalTrace.reset();
+
+  ASSERT_STREQ(getContentOfFile("./cl_release_mem_object_interception_test.log").c_str(),
+               "On CPU - Peak heap usage: 0 B, Total allocated: 0 B, Total deallocated: 0 B\nOn "
+               "GPU - Peak mem usage: 0 B, Total allocated: 0 B, Total deallocated: 0 B\n");
+}
+
+} // namespace backstage
diff --git a/runtime/contrib/heap_trace/tests/src/common_test_environment.cc b/runtime/contrib/heap_trace/tests/src/common_test_environment.cc
new file mode 100644
index 000000000..e5c4dc121
--- /dev/null
+++ b/runtime/contrib/heap_trace/tests/src/common_test_environment.cc
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "common_test_environment.h"
+
+#include "trace.h"
+
+#include <experimental/filesystem>
+
+namespace fs = std::experimental::filesystem;
+
+extern std::unique_ptr<Trace> GlobalTrace;
+
+void TestEnv::SetUp() { configureTraceToMakeLogInFile(); }
+
+void TestEnv::TearDown() { removeOldTraceLogIfNeed(); }
+
+void TestEnv::configureTraceToMakeLogInFile()
+{
+  removeOldTraceLogIfNeed();
+  setNewNameOfTraceLog();
+}
+
+void TestEnv::removeOldTraceLogIfNeed()
+{
+  GlobalTrace.reset();
+  const char *trace_log_name = getenv("HEAP_TRACE_LOG");
+  if (trace_log_name)
+  {
+    fs::remove(trace_log_name);
+  }
+}
+
+void TestEnv::setNewNameOfTraceLog()
+{
+  setenv("HEAP_TRACE_LOG", test_log_file.c_str(), 1);
+  GlobalTrace.reset(new ::Trace);
+}
diff --git a/runtime/contrib/heap_trace/tests/src/common_test_environment.h b/runtime/contrib/heap_trace/tests/src/common_test_environment.h
new file mode 100644
index 000000000..8c4c9e396
--- /dev/null
+++ b/runtime/contrib/heap_trace/tests/src/common_test_environment.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef COMMON_TEST_ENVIRONMENT_H
+#define COMMON_TEST_ENVIRONMENT_H
+
+#include "gtest/gtest.h"
+
+struct TestEnv : public ::testing::Test
+{
+  TestEnv(const char *log_file) : test_log_file(log_file) {}
+
+  void SetUp() override;
+  void TearDown() override;
+
+private:
+  void configureTraceToMakeLogInFile();
+  void removeOldTraceLogIfNeed();
+  void setNewNameOfTraceLog();
+
+private:
+  std::string test_log_file;
+};
+
+#endif // ! COMMON_TEST_ENVIRONMENT_H
diff --git a/runtime/contrib/heap_trace/tests/src/file_content_manipulations.cc b/runtime/contrib/heap_trace/tests/src/file_content_manipulations.cc
new file mode 100644
index 000000000..0c968ab4b
--- /dev/null
+++ b/runtime/contrib/heap_trace/tests/src/file_content_manipulations.cc
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "file_content_manipulations.h"
+
+#include <fstream>
+
+std::string getContentOfFile(const char *file_name)
+{
+  std::ifstream in(file_name);
+  return std::string((std::istreambuf_iterator<char>(in)), std::istreambuf_iterator<char>());
+}
diff --git a/runtime/contrib/heap_trace/tests/src/file_content_manipulations.h b/runtime/contrib/heap_trace/tests/src/file_content_manipulations.h
new file mode 100644
index 000000000..ba938931c
--- /dev/null
+++ b/runtime/contrib/heap_trace/tests/src/file_content_manipulations.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef TEST_SUPPORT_H
+#define TEST_SUPPORT_H
+
+#include <string>
+
+std::string getContentOfFile(const char *file_name);
+
+#endif //! TEST_SUPPORT_H
diff --git a/runtime/contrib/heap_trace/tests/src/free_interception_test.cc b/runtime/contrib/heap_trace/tests/src/free_interception_test.cc
new file mode 100644
index 000000000..e690718d0
--- /dev/null
+++ b/runtime/contrib/heap_trace/tests/src/free_interception_test.cc
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "common_test_environment.h"
+#include "file_content_manipulations.h"
+
+#include "trace.h"
+
+extern std::unique_ptr<Trace> GlobalTrace;
+
+namespace backstage
+{
+
+struct FreeStub : public TestEnv
+{
+  FreeStub() : TestEnv("./free_interception_test.log") {}
+};
+
+TEST_F(FreeStub, should_work_as_standard_version)
+{
+  void *p = malloc(1024);
+  free(p);
+  ASSERT_TRUE(p);
+  // TODO Bad test. Need use death test from Google test framework
+}
+
+TEST_F(FreeStub, must_log_deallocation_events_if_trace_is_ready_for_it)
+{
+  GlobalTrace.reset();
+  void *p1 = malloc(1024);
+  ASSERT_TRUE(p1);
+  free(p1);
+
+  GlobalTrace.reset(new Trace);
+  void *p2 = malloc(128);
+  void *p3 = malloc(64);
+  ASSERT_TRUE(p2 && p3);
+  free(p2);
+  free(p3);
+  GlobalTrace.reset();
+
+  ASSERT_STREQ(getContentOfFile("./free_interception_test.log").c_str(),
+               "On CPU - Peak heap usage: 192 B, Total allocated: 192 B, Total deallocated: 192 "
+               "B\nOn GPU - Peak mem usage: 0 B, Total allocated: 0 B, Total deallocated: 0 B\n");
+}
+
+} // namespace backstage
diff --git a/runtime/contrib/heap_trace/tests/src/main.cc b/runtime/contrib/heap_trace/tests/src/main.cc
new file mode 100644
index 000000000..b53b2030b
--- /dev/null
+++ b/runtime/contrib/heap_trace/tests/src/main.cc
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "gtest/gtest.h"
+
+int main(int argc, char *argv[])
+{
+  ::testing::InitGoogleTest(&argc, argv);
+  return RUN_ALL_TESTS();
+}
diff --git a/runtime/contrib/heap_trace/tests/src/malloc_interception_test.cc b/runtime/contrib/heap_trace/tests/src/malloc_interception_test.cc
new file mode 100644
index 000000000..7a2f5a915
--- /dev/null
+++ b/runtime/contrib/heap_trace/tests/src/malloc_interception_test.cc
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "common_test_environment.h"
+#include "file_content_manipulations.h"
+
+#include "trace.h"
+
+#include <experimental/filesystem>
+#include <limits>
+
+extern std::unique_ptr<Trace> GlobalTrace;
+
+namespace backstage
+{
+
+struct MallocStub : public TestEnv
+{
+  MallocStub() : TestEnv("./malloc_interception_test.log") {}
+};
+
+TEST_F(MallocStub, must_allocate_space_as_standard_malloc)
+{
+  void *p = malloc(128);
+
+  ASSERT_TRUE(p);
+  free(p);
+}
+
+TEST_F(MallocStub, must_log_allocation_events_if_trace_is_ready_for_it)
+{
+  GlobalTrace.reset();
+  void *p1 = malloc(1024);
+
+  GlobalTrace.reset(new Trace);
+  void *p2 = malloc(128);
+  void *p3 = malloc(64);
+  GlobalTrace.reset();
+
+  ASSERT_TRUE(p1 && p2 && p3);
+  ASSERT_STREQ(getContentOfFile("./malloc_interception_test.log").c_str(),
+               "On CPU - Peak heap usage: 192 B, Total allocated: 192 B, Total deallocated: 0 "
+               "B\nOn GPU - Peak mem usage: 0 B, Total allocated: 0 B, Total deallocated: 0 B\n");
+  free(p1);
+  free(p2);
+  free(p3);
+}
+
+TEST_F(MallocStub, must_not_do_the_record_about_allocation_event_if_original_function_failed)
+{
+  void *p = malloc(std::numeric_limits<size_t>::max());
+  GlobalTrace.reset();
+
+  ASSERT_FALSE(p);
+  ASSERT_STREQ(getContentOfFile("./malloc_interception_test.log").c_str(),
+               "On CPU - Peak heap usage: 0 B, Total allocated: 0 B, Total deallocated: 0 B\nOn "
+               "GPU - Peak mem usage: 0 B, Total allocated: 0 B, Total deallocated: 0 B\n");
+}
+
+TEST_F(
+    MallocStub,
+    should_not_influence_on_trace_results_even_if_orignal_function_return_any_not_null_ptr_when_incoming_size_is_zero)
+{
+  void *p = malloc(0);
+  free(p);
+  GlobalTrace.reset();
+
+  ASSERT_TRUE(p);
+  ASSERT_STREQ(getContentOfFile("./malloc_interception_test.log").c_str(),
+               "On CPU - Peak heap usage: 0 B, Total allocated: 0 B, Total deallocated: 0 B\nOn "
+               "GPU - Peak mem usage: 0 B, Total allocated: 0 B, Total deallocated: 0 B\n");
+}
+
+} // namespace backstage
diff --git a/runtime/contrib/heap_trace/tests/src/realloc_interception_test.cc b/runtime/contrib/heap_trace/tests/src/realloc_interception_test.cc
new file mode 100644
index 000000000..160a19beb
--- /dev/null
+++ b/runtime/contrib/heap_trace/tests/src/realloc_interception_test.cc
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "common_test_environment.h"
+#include "file_content_manipulations.h"
+
+#include "trace.h"
+
+#include <experimental/filesystem>
+#include <limits>
+#include <cstring>
+
+extern std::unique_ptr<Trace> GlobalTrace;
+
+namespace backstage
+{
+
+struct ReallocStub : public TestEnv
+{
+  ReallocStub() : TestEnv("./realloc_interception_test.log") {}
+};
+
+TEST_F(ReallocStub, must_allocate_space_as_standard_realloc)
+{
+  void *p = malloc(128);
+  p = realloc(p, 1024);
+
+  ASSERT_TRUE(p);
+  free(p);
+}
+
+TEST_F(ReallocStub, must_log_allocation_deallocation_events_if_trace_is_ready_for_it)
+{
+  std::array<char, 1024> reference_data;
+  reference_data.fill('a');
+  void *p1 = malloc(1024);
+  memcpy(p1, reference_data.data(), reference_data.size());
+  void *p2 = realloc(p1, 64);
+  void *p3 = realloc(p2, 128);
+  GlobalTrace.reset();
+
+  ASSERT_TRUE(p3);
+  ASSERT_TRUE(memcmp(p3, reference_data.data(), 64) == 0);
+  ASSERT_STREQ(getContentOfFile("./realloc_interception_test.log").c_str(),
+               "On CPU - Peak heap usage: 1024 B, Total allocated: 1216 B, Total deallocated: 1088 "
+               "B\nOn GPU - Peak mem usage: 0 B, Total allocated: 0 B, Total deallocated: 0 B\n");
+  free(p3);
+}
+
+TEST_F(ReallocStub,
+       must_not_do_the_record_about_allocation_deallocation_events_if_original_function_failed)
+{
+  GlobalTrace.reset();
+  void *p = malloc(128);
+  GlobalTrace.reset(new Trace);
+
+  void *ptr_after_realloc = realloc(p, std::numeric_limits<size_t>::max());
+  ptr_after_realloc = realloc(p, 0);
+  GlobalTrace.reset();
+
+  ASSERT_FALSE(ptr_after_realloc);
+  ASSERT_STREQ(getContentOfFile("./realloc_interception_test.log").c_str(),
+               "On CPU - Peak heap usage: 0 B, Total allocated: 0 B, Total deallocated: 0 B\nOn "
+               "GPU - Peak mem usage: 0 B, Total allocated: 0 B, Total deallocated: 0 B\n");
+
+  free(p);
+}
+
+TEST_F(ReallocStub, should_work_as_malloc_when_incoming_ptr_is_equal_to_nullptr)
+{
+  void *p = realloc(nullptr, 1024);
+  GlobalTrace.reset();
+
+  ASSERT_TRUE(p);
+  ASSERT_STREQ(
+      getContentOfFile("./realloc_interception_test.log").c_str(),
+      "On CPU - Peak heap usage: 1024 B, Total allocated: 1024 B, Total deallocated: 0 B\nOn "
+      "GPU - Peak mem usage: 0 B, Total allocated: 0 B, Total deallocated: 0 B\n");
+
+  free(p);
+}
+
+TEST_F(
+    ReallocStub,
+    should_not_influence_on_trace_results_even_if_orignal_function_return_any_not_null_ptr_when_incoming_size_is_zero_and_ptr_is_null)
+{
+  void *p = realloc(nullptr, 0);
+  free(p);
+  GlobalTrace.reset();
+
+  ASSERT_TRUE(p);
+  ASSERT_STREQ(getContentOfFile("./realloc_interception_test.log").c_str(),
+               "On CPU - Peak heap usage: 0 B, Total allocated: 0 B, Total deallocated: 0 B\nOn "
+               "GPU - Peak mem usage: 0 B, Total allocated: 0 B, Total deallocated: 0 B\n");
+}
+
+} // namespace backstage
diff --git a/runtime/contrib/heap_trace/tests/src/symbol_searcher_test.cc b/runtime/contrib/heap_trace/tests/src/symbol_searcher_test.cc
new file mode 100644
index 000000000..d615cc928
--- /dev/null
+++ b/runtime/contrib/heap_trace/tests/src/symbol_searcher_test.cc
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "gtest/gtest.h"
+#include "test_sample1.h"
+#include "test_sample2.h"
+#include "test_sample4.h"
+
+#include "symbol_searcher.h"
+
+#include <dlfcn.h>
+#include <linux/limits.h>
+#include <unistd.h>
+
+#include <cstdlib>
+
+#include <experimental/filesystem>
+
+namespace fs = std::experimental::filesystem;
+
+fs::path exePath()
+{
+  char result[PATH_MAX] = {0};
+  ssize_t count = readlink("/proc/self/exe", result, PATH_MAX);
+  return fs::path(result).parent_path();
+}
+
+namespace backstage
+{
+
+struct SymbolSearcher : public ::testing::Test
+{
+};
+
+TEST_F(SymbolSearcher, should_find_symbol_in_linked_library)
+{
+  ASSERT_TRUE((void *)funcDefinedOnlyInTestSample4 == findSymbol("funcDefinedOnlyInTestSample4"));
+}
+
+TEST_F(SymbolSearcher, should_find_symbol_in_library_which_have_been_loaded_in_runtime)
+{
+  fs::path pathToTestLib = exePath() / "libtest_sample2.so";
+  void *handle = dlopen(pathToTestLib.c_str(), RTLD_NOW);
+
+  ASSERT_TRUE(handle);
+  ASSERT_TRUE(dlsym(handle, "funcDefinedOnlyInTestSample2") ==
+              findSymbol("funcDefinedOnlyInTestSample2"));
+  dlclose(handle);
+}
+
+TEST_F(SymbolSearcher,
+       should_ignore_symbols_found_in_current_translation_unit_if_there_is_another_alternative)
+{
+  fs::path pathToTestSample2 = exePath() / "libtest_sample2.so";
+  void *test_sample2_handle = dlopen(pathToTestSample2.c_str(), RTLD_NOW);
+  void *func_addr_in_test_sample2 =
+      dlsym(test_sample2_handle, "funcWhichCallFuncDefinedInTestSample3");
+
+  ASSERT_TRUE(test_sample2_handle);
+  ASSERT_TRUE((void *)funcDefinedInTestSample3_ButWrappedInTestSample1 !=
+              reinterpret_cast<void *(*)()>(func_addr_in_test_sample2)());
+
+  dlclose(test_sample2_handle);
+}
+
+} // namespace backstage
diff --git a/runtime/contrib/heap_trace/tests/src/test_sample1.h b/runtime/contrib/heap_trace/tests/src/test_sample1.h
new file mode 100644
index 000000000..3abea56a3
--- /dev/null
+++ b/runtime/contrib/heap_trace/tests/src/test_sample1.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef TEST_SAMPLE1_H
+#define TEST_SAMPLE1_H
+
+extern "C" {
+
+void *funcDefinedInTestSample3_ButWrappedInTestSample1();
+}
+
+#endif // ! TEST_SAMPLE1_H
diff --git a/runtime/contrib/heap_trace/tests/src/test_sample1/test_sample1.cc b/runtime/contrib/heap_trace/tests/src/test_sample1/test_sample1.cc
new file mode 100644
index 000000000..1d2843707
--- /dev/null
+++ b/runtime/contrib/heap_trace/tests/src/test_sample1/test_sample1.cc
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "../test_sample1.h"
+
+#include "../../../src/symbol_searcher.h"
+
+extern "C" {
+
+void *funcDefinedInTestSample3_ButWrappedInTestSample1()
+{
+  return findSymbol("funcDefinedInTestSample3_ButWrappedInTestSample1");
+}
+}
diff --git a/runtime/contrib/heap_trace/tests/src/test_sample2.h b/runtime/contrib/heap_trace/tests/src/test_sample2.h
new file mode 100644
index 000000000..785fc252d
--- /dev/null
+++ b/runtime/contrib/heap_trace/tests/src/test_sample2.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef TEST_SAMPLE2_H
+#define TEST_SAMPLE2_H
+
+extern "C" {
+
+void funcDefinedOnlyInTestSample2();
+void funcWhichCallFuncDefinedInTestSample3();
+}
+
+#endif // ! TEST_SAMPLE2_H
diff --git a/runtime/contrib/heap_trace/tests/src/test_sample2/test_sample2.cc b/runtime/contrib/heap_trace/tests/src/test_sample2/test_sample2.cc
new file mode 100644
index 000000000..792dba665
--- /dev/null
+++ b/runtime/contrib/heap_trace/tests/src/test_sample2/test_sample2.cc
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "../test_sample2.h"
+#include "../test_sample3.h"
+
+extern "C" {
+
+void funcDefinedOnlyInTestSample2() {}
+void funcWhichCallFuncDefinedInTestSample3() { funcDefinedInTestSample3_ButWrappedInTestSample1(); }
+}
diff --git a/runtime/contrib/heap_trace/tests/src/test_sample3.h b/runtime/contrib/heap_trace/tests/src/test_sample3.h
new file mode 100644
index 000000000..8f85b8bd6
--- /dev/null
+++ b/runtime/contrib/heap_trace/tests/src/test_sample3.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef TEST_SAMPLE3_H
+#define TEST_SAMPLE3_H
+
+extern "C" {
+
+void funcDefinedInTestSample3_ButWrappedInTestSample1();
+}
+
+#endif // ! TEST_SAMPLE3_H
diff --git a/runtime/contrib/heap_trace/tests/src/test_sample3/test_sample3.cc b/runtime/contrib/heap_trace/tests/src/test_sample3/test_sample3.cc
new file mode 100644
index 000000000..ded78db85
--- /dev/null
+++ b/runtime/contrib/heap_trace/tests/src/test_sample3/test_sample3.cc
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+extern "C" {
+
+void funcDefinedInTestSample3_ButWrappedInTestSample1() {}
+}
diff --git a/runtime/contrib/heap_trace/tests/src/test_sample4.h b/runtime/contrib/heap_trace/tests/src/test_sample4.h
new file mode 100644
index 000000000..47c9e8c92
--- /dev/null
+++ b/runtime/contrib/heap_trace/tests/src/test_sample4.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef TEST_SAMPLE4_H
+#define TEST_SAMPLE4_H
+
+extern "C" {
+
+void funcDefinedOnlyInTestSample4();
+}
+
+#endif // ! TEST_SAMPLE4_H
diff --git a/runtime/contrib/heap_trace/tests/src/test_sample4/test_sample4.cc b/runtime/contrib/heap_trace/tests/src/test_sample4/test_sample4.cc
new file mode 100644
index 000000000..55c96cb0e
--- /dev/null
+++ b/runtime/contrib/heap_trace/tests/src/test_sample4/test_sample4.cc
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "../test_sample4.h"
+
+extern "C" {
+void funcDefinedOnlyInTestSample4() {}
+}
diff --git a/runtime/contrib/heap_trace/tests/src/trace_test.cc b/runtime/contrib/heap_trace/tests/src/trace_test.cc
new file mode 100644
index 000000000..1cf4c530b
--- /dev/null
+++ b/runtime/contrib/heap_trace/tests/src/trace_test.cc
@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "common_test_environment.h"
+#include "file_content_manipulations.h"
+
+#include "trace.h"
+
+#include <CL/cl.h>
+
+#include <experimental/filesystem>
+#include <thread>
+#include <atomic>
+
+using namespace std;
+namespace fs = experimental::filesystem;
+
+extern unique_ptr<::Trace> GlobalTrace;
+
+namespace backstage
+{
+
+struct Trace : TestEnv
+{
+  Trace() : TestEnv("./trace_test.log") {}
+
+  void generateGarbageInTestLogFile();
+  template <typename MemType>
+  static void emulateAllocationEvent(size_t eventsPoolId, size_t numberOfEmulation,
+                                     size_t numberOfBytesPerOneEmulation, atomic_bool &isPauseNeed);
+};
+
+TEST_F(Trace,
+       must_create_log_file_with_name_defined_in_env_var_HEAP_TRACE_LOG_during_initialization)
+{
+  ASSERT_TRUE(fs::exists("./trace_test.log"));
+}
+
+TEST_F(Trace, must_truncate_log_file_if_it_exists_during_initialization)
+{
+  GlobalTrace.reset();
+  generateGarbageInTestLogFile();
+  GlobalTrace.reset(new ::Trace);
+  GlobalTrace.reset();
+
+  ASSERT_STREQ(getContentOfFile("./trace_test.log").c_str(),
+               "On CPU - Peak heap usage: 0 B, Total allocated: 0 B, Total deallocated: 0 B\nOn "
+               "GPU - Peak mem usage: 0 B, Total allocated: 0 B, Total deallocated: 0 B\n");
+}
+
+void Trace::generateGarbageInTestLogFile()
+{
+  ofstream log("./trace_test.log");
+  log << string(256, 'a');
+}
+
+TEST_F(Trace, should_not_generate_any_records_in_log_during_creation)
+{
+  GlobalTrace.reset();
+
+  ASSERT_STREQ(getContentOfFile("./trace_test.log").c_str(),
+               "On CPU - Peak heap usage: 0 B, Total allocated: 0 B, Total deallocated: 0 B\nOn "
+               "GPU - Peak mem usage: 0 B, Total allocated: 0 B, Total deallocated: 0 B\n");
+}
+
+TEST_F(Trace, can_signalize_to_users_if_it_is_ready_for_using)
+{
+  ASSERT_FALSE(::Trace::Guard().isActive());
+}
+
+TEST_F(Trace, must_signalize_that_it_is_not_ready_for_using_until_it_is_not_created)
+{
+  GlobalTrace.reset();
+  ASSERT_TRUE(::Trace::Guard().isActive());
+}
+
+TEST_F(Trace, should_work_correctly_in_multithreaded_environment)
+{
+  constexpr size_t numberOfThreads = 10, numberOfEmulations = 100,
+                   numberOfBytesPerOneEmulation = 1024;
+  atomic_bool isPauseNeed{true};
+  array<thread, numberOfThreads> threads;
+  for (size_t i = 0; i < numberOfThreads / 2; ++i)
+  {
+    threads[i] = thread(emulateAllocationEvent<void *>, i, numberOfEmulations,
+                        numberOfBytesPerOneEmulation, ref(isPauseNeed));
+  }
+  for (size_t i = numberOfThreads / 2; i < numberOfThreads; ++i)
+  {
+    threads[i] = thread(emulateAllocationEvent<cl_mem>, i, numberOfEmulations,
+                        numberOfBytesPerOneEmulation, ref(isPauseNeed));
+  }
+
+  GlobalTrace.reset(new ::Trace);
+  isPauseNeed = false;
+
+  for (size_t i = 0; i < numberOfThreads; ++i)
+  {
+    threads[i].join();
+  }
+  GlobalTrace.reset();
+
+  string thisShouldBeInLogFile =
+      "Total allocated: " +
+      to_string(numberOfThreads / 2 * numberOfEmulations * numberOfBytesPerOneEmulation) +
+      " B, Total deallocated: " +
+      to_string(numberOfThreads / 2 * numberOfEmulations * numberOfBytesPerOneEmulation) + " B\n";
+  string andThisToo =
+      "Total allocated: " +
+      to_string(numberOfThreads / 2 * numberOfEmulations * numberOfBytesPerOneEmulation) +
+      " B, Total deallocated: " +
+      to_string(numberOfThreads / 2 * numberOfEmulations * numberOfBytesPerOneEmulation) + " B\n";
+  ASSERT_TRUE(getContentOfFile("./trace_test.log").find(thisShouldBeInLogFile) != string::npos);
+  ASSERT_TRUE(getContentOfFile("./trace_test.log").find(andThisToo) != string::npos);
+}
+
+template <typename MemType>
+void Trace::emulateAllocationEvent(size_t eventsPoolId, size_t numberOfEmulation,
+                                   size_t numberOfBytesPerOneEmulation, atomic_bool &isPauseNeed)
+{
+  while (isPauseNeed)
+  {
+    continue;
+  }
+
+  for (size_t i = 1; i <= numberOfEmulation; ++i)
+  {
+    GlobalTrace->logAllocationEvent((MemType)(i + numberOfEmulation * eventsPoolId),
+                                    numberOfBytesPerOneEmulation);
+  }
+
+  for (size_t i = 1; i <= numberOfEmulation; ++i)
+  {
+    GlobalTrace->logDeallocationEvent((MemType)(i + numberOfEmulation * eventsPoolId));
+  }
+}
+
+TEST_F(Trace, must_log_allocation_and_deallocation_events)
+{
+  void *memOnCPU1 = (void *)1, *memOnCPU2 = (void *)3;
+  cl_mem memOnGPU1 = (cl_mem)2, memOnGPU2 = (cl_mem)4;
+  GlobalTrace->logAllocationEvent(memOnCPU1, 347);
+  GlobalTrace->logDeallocationEvent(memOnCPU1);
+  GlobalTrace->logAllocationEvent(memOnGPU2, 592);
+  GlobalTrace->logDeallocationEvent(memOnGPU2);
+  GlobalTrace->logAllocationEvent(memOnGPU1, 349);
+  GlobalTrace->logDeallocationEvent(memOnGPU1);
+  GlobalTrace->logAllocationEvent(memOnCPU2, 568);
+  GlobalTrace->logDeallocationEvent(memOnCPU2);
+  GlobalTrace.reset();
+
+  string shouldBeInLogFile = "On CPU - Peak heap usage: " + to_string(568) +
+                             " B, Total allocated: " + to_string(347 + 568) +
+                             " B, Total deallocated: " + to_string(347 + 568) +
+                             " B\n"
+                             "On GPU - Peak mem usage: " +
+                             to_string(592) + " B, Total allocated: " + to_string(592 + 349) +
+                             " B, Total deallocated: " + to_string(592 + 349) + " B\n";
+  ASSERT_STREQ(getContentOfFile("./trace_test.log").c_str(), shouldBeInLogFile.c_str());
+}
+
+} // namespace backstage
diff --git a/runtime/contrib/heap_trace/tests/src/valloc_interception_test.cc b/runtime/contrib/heap_trace/tests/src/valloc_interception_test.cc
new file mode 100644
index 000000000..6b3d6df82
--- /dev/null
+++ b/runtime/contrib/heap_trace/tests/src/valloc_interception_test.cc
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "common_test_environment.h"
+#include "file_content_manipulations.h"
+
+#include "trace.h"
+
+#include <experimental/filesystem>
+#include <limits>
+
+extern std::unique_ptr<Trace> GlobalTrace;
+
+namespace backstage
+{
+
+struct VallocStub : public TestEnv
+{
+  VallocStub() : TestEnv("./valloc_interception_test.log") {}
+};
+
+TEST_F(VallocStub, must_allocate_space_as_standard_valloc)
+{
+  void *p = valloc(128);
+
+  ASSERT_TRUE(p);
+  free(p);
+}
+
+TEST_F(VallocStub, must_log_allocation_events_if_trace_is_ready_for_it)
+{
+  GlobalTrace.reset();
+  void *p1 = valloc(1024);
+
+  GlobalTrace.reset(new Trace);
+  void *p2 = valloc(128);
+  void *p3 = valloc(64);
+  GlobalTrace.reset();
+
+  ASSERT_TRUE(p1 && p2 && p3);
+  ASSERT_STREQ(getContentOfFile("./valloc_interception_test.log").c_str(),
+               "On CPU - Peak heap usage: 192 B, Total allocated: 192 B, Total deallocated: 0 "
+               "B\nOn GPU - Peak mem usage: 0 B, Total allocated: 0 B, Total deallocated: 0 B\n");
+  free(p1);
+  free(p2);
+  free(p3);
+}
+
+TEST_F(VallocStub, must_not_do_the_record_about_allocation_event_if_original_function_failed)
+{
+  void *p = valloc(std::numeric_limits<size_t>::max());
+  GlobalTrace.reset();
+
+  ASSERT_FALSE(p);
+  ASSERT_STREQ(getContentOfFile("./valloc_interception_test.log").c_str(),
+               "On CPU - Peak heap usage: 0 B, Total allocated: 0 B, Total deallocated: 0 B\nOn "
+               "GPU - Peak mem usage: 0 B, Total allocated: 0 B, Total deallocated: 0 B\n");
+}
+
+} // namespace backstage
diff --git a/runtime/contrib/labs/CMakeLists.txt b/runtime/contrib/labs/CMakeLists.txt
new file mode 100644
index 000000000..57e28c11a
--- /dev/null
+++ b/runtime/contrib/labs/CMakeLists.txt
@@ -0,0 +1,5 @@
+if(NOT BUILD_LABS)
+  return()
+endif(NOT BUILD_LABS)
+
+add_subdirectories()
diff --git a/runtime/contrib/labs/jniacl/CMakeLists.txt b/runtime/contrib/labs/jniacl/CMakeLists.txt
new file mode 100644
index 000000000..6d05122a0
--- /dev/null
+++ b/runtime/contrib/labs/jniacl/CMakeLists.txt
@@ -0,0 +1,18 @@
+#
+# Simple Android JNI execution test of ACL
+#
+
+if(NOT ANDROID)
+  return()
+endif(NOT ANDROID)
+
+nnas_find_package(ARMCompute REQUIRED)
+
+link_directories(${CMAKE_INSTALL_PREFIX}/lib)
+
+set(JNIACL_SRCS src/jniacl_main.cc
+                src/io_accessor.cc)
+
+add_library(jniacl_jni SHARED ${JNIACL_SRCS})
+target_include_directories(jniacl_jni PUBLIC ${TFLITE_JNI_INCLUDES} src)
+target_link_libraries(jniacl_jni arm_compute_graph log)
diff --git a/runtime/contrib/labs/jniacl/src/io_accessor.cc b/runtime/contrib/labs/jniacl/src/io_accessor.cc
new file mode 100644
index 000000000..076c93f3d
--- /dev/null
+++ b/runtime/contrib/labs/jniacl/src/io_accessor.cc
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * Copyright (c) 2018 ARM Limited.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "io_accessor.h"
+#include <ostream>
+#include <android/log.h>
+
+bool InputAccessor::access_tensor(arm_compute::ITensor &tensor)
+{
+  // Subtract the mean value from each channel
+  arm_compute::Window window;
+  window.use_tensor_dimensions(tensor.info()->tensor_shape());
+
+  execute_window_loop(window, [&](const arm_compute::Coordinates &id) {
+    *reinterpret_cast<float *>(tensor.ptr_to_element(id)) = _test_input;
+    _test_input += _inc ? 1.0 : 0.0;
+
+    __android_log_print(ANDROID_LOG_DEBUG, "LOG_TAG", "Input %d, %d = %lf\r\n", id.y(), id.x(),
+                        *reinterpret_cast<float *>(tensor.ptr_to_element(id)));
+  });
+  return true;
+}
+
+bool OutputAccessor::access_tensor(arm_compute::ITensor &tensor)
+{
+  // Subtract the mean value from each channel
+  arm_compute::Window window;
+  window.use_tensor_dimensions(tensor.info()->tensor_shape());
+
+  execute_window_loop(window, [&](const arm_compute::Coordinates &id) {
+    __android_log_print(ANDROID_LOG_DEBUG, "Output", "Input %d, %d = %lf\r\n", id.y(), id.x(),
+                        *reinterpret_cast<float *>(tensor.ptr_to_element(id)));
+  });
+  return false; // end the network
+}
+
+bool WeightAccessor::access_tensor(arm_compute::ITensor &tensor)
+{
+  // Subtract the mean value from each channel
+  arm_compute::Window window;
+  window.use_tensor_dimensions(tensor.info()->tensor_shape());
+
+  execute_window_loop(window, [&](const arm_compute::Coordinates &id) {
+    *reinterpret_cast<float *>(tensor.ptr_to_element(id)) = _test_weight;
+    _test_weight += _inc ? 1.0 : 0.0;
+  });
+  return true;
+}
+
+bool BiasAccessor::access_tensor(arm_compute::ITensor &tensor)
+{
+  // Subtract the mean value from each channel
+  arm_compute::Window window;
+  window.use_tensor_dimensions(tensor.info()->tensor_shape());
+
+  execute_window_loop(window, [&](const arm_compute::Coordinates &id) {
+    *reinterpret_cast<float *>(tensor.ptr_to_element(id)) = 0.0;
+  });
+  return true;
+}
diff --git a/runtime/contrib/labs/jniacl/src/io_accessor.h b/runtime/contrib/labs/jniacl/src/io_accessor.h
new file mode 100644
index 000000000..bc4376644
--- /dev/null
+++ b/runtime/contrib/labs/jniacl/src/io_accessor.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * Copyright (c) 2018 ARM Limited.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef __IO_ACCESSOR_H__
+#define __IO_ACCESSOR_H__
+
+#include <arm_compute/graph/ITensorAccessor.h>
+
+class InputAccessor : public arm_compute::graph::ITensorAccessor
+{
+public:
+  InputAccessor(bool inc) : _inc(inc) { _test_input = 1.0; }
+  InputAccessor(InputAccessor &&) = default;
+
+  // Inherited methods overriden:
+  bool access_tensor(arm_compute::ITensor &tensor) override;
+
+private:
+  bool _inc;
+  float _test_input;
+};
+
+class OutputAccessor : public arm_compute::graph::ITensorAccessor
+{
+public:
+  OutputAccessor() = default;
+  OutputAccessor(OutputAccessor &&) = default;
+
+  // Inherited methods overriden:
+  bool access_tensor(arm_compute::ITensor &tensor) override;
+};
+
+class WeightAccessor : public arm_compute::graph::ITensorAccessor
+{
+public:
+  WeightAccessor(bool inc) : _inc(inc) { _test_weight = 1.0; }
+  WeightAccessor(WeightAccessor &&) = default;
+
+  // Inherited methods overriden:
+  bool access_tensor(arm_compute::ITensor &tensor) override;
+
+private:
+  bool _inc;
+  float _test_weight;
+};
+
+class BiasAccessor : public arm_compute::graph::ITensorAccessor
+{
+public:
+  BiasAccessor() = default;
+  BiasAccessor(BiasAccessor &&) = default;
+
+  // Inherited methods overriden:
+  bool access_tensor(arm_compute::ITensor &tensor) override;
+};
+
+#endif // __IO_ACCESSOR_H__
diff --git a/runtime/contrib/labs/jniacl/src/jniacl_main.cc b/runtime/contrib/labs/jniacl/src/jniacl_main.cc
new file mode 100644
index 000000000..4e5f10d1f
--- /dev/null
+++ b/runtime/contrib/labs/jniacl/src/jniacl_main.cc
@@ -0,0 +1,37 @@
+#include <jni.h>
+#include <string>
+
+#include <arm_compute/graph/Graph.h>
+#include <arm_compute/graph/Nodes.h>
+
+#include "io_accessor.h"
+
+extern "C" JNIEXPORT jstring JNICALL
+Java_com_samsung_testaclexec_ActivityMain_RunACLJNI(JNIEnv *env, jobject)
+{
+  using arm_compute::DataType;
+  using arm_compute::graph::Tensor;
+  using arm_compute::graph::TargetHint;
+  using arm_compute::graph::Graph;
+  using arm_compute::TensorInfo;
+  using arm_compute::TensorShape;
+
+  arm_compute::graph::Graph graph;
+  TargetHint target_hint = TargetHint::OPENCL;
+  bool autoinc = true;
+
+  graph << target_hint << Tensor(TensorInfo(TensorShape(3U, 3U, 1U, 1U), 1, DataType::F32),
+                                 std::unique_ptr<InputAccessor>(new InputAccessor(autoinc)))
+        << arm_compute::graph::ConvolutionLayer(
+               3U, 3U, 1U, std::unique_ptr<WeightAccessor>(new WeightAccessor(autoinc)),
+               std::unique_ptr<BiasAccessor>(new BiasAccessor()),
+               arm_compute::PadStrideInfo(1, 1, 0, 0))
+        << Tensor(std::unique_ptr<OutputAccessor>(new OutputAccessor()));
+  ;
+
+  graph.run();
+
+  std::string hello = "SoftMax Run OK";
+
+  return env->NewStringUTF(hello.c_str());
+}
diff --git a/runtime/contrib/labs/opencl_test/CMakeLists.txt b/runtime/contrib/labs/opencl_test/CMakeLists.txt
new file mode 100644
index 000000000..40cb30bb9
--- /dev/null
+++ b/runtime/contrib/labs/opencl_test/CMakeLists.txt
@@ -0,0 +1,11 @@
+if(NOT ${TARGET_ARCH_BASE} STREQUAL "arm")
+  return()
+endif(NOT ${TARGET_ARCH_BASE} STREQUAL "arm")
+
+list(APPEND OPENCL_INFO_SOURCE "src/opencl_test.cc")
+
+nnas_find_package(ARMCompute REQUIRED)
+
+add_executable(opencl_test ${OPENCL_INFO_SOURCE})
+target_link_libraries(opencl_test arm_compute)
+target_link_libraries(opencl_test arm_compute_ex)
diff --git a/runtime/contrib/labs/opencl_test/README.md b/runtime/contrib/labs/opencl_test/README.md
new file mode 100644
index 000000000..950528f81
--- /dev/null
+++ b/runtime/contrib/labs/opencl_test/README.md
@@ -0,0 +1,8 @@
+This directory contains experients of OpenCL code.
+
+How to run:
+```
+LD_LIBRARY_PATH=Product/out/lib Product/obj/contrib/opencl_test/opencl_test [option]
+```
+   - `[option]`
+      - `-g`: prints devices inside GPU and check if they use same memory address
diff --git a/runtime/contrib/labs/opencl_test/src/opencl_test.cc b/runtime/contrib/labs/opencl_test/src/opencl_test.cc
new file mode 100644
index 000000000..1faa91478
--- /dev/null
+++ b/runtime/contrib/labs/opencl_test/src/opencl_test.cc
@@ -0,0 +1,386 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*******************************************************************************
+ * Copyright (c) 2008-2015 The Khronos Group Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and/or associated documentation files (the
+ * "Materials"), to deal in the Materials without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Materials, and to
+ * permit persons to whom the Materials are furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Materials.
+ *
+ * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
+ ******************************************************************************/
+
+#include "arm_compute/core/CL/OpenCL.h"
+
+#include <iostream>
+#include <vector>
+
+void printDeviceInfo(int n, cl::Device &device, cl::Device &default_device)
+{
+  bool is_default = (device() == default_device());
+  std::cout << "\t\t\t#" << n << " Device: (id: " << device() << ") "
+            << (is_default ? " -> default" : "") << "\n";
+
+  const auto name = device.getInfo<CL_DEVICE_NAME>();
+  std::cout << "\t\t\t\tName: " << name << "\n";
+
+  const auto compute_unit = device.getInfo<CL_DEVICE_MAX_COMPUTE_UNITS>();
+  std::cout << "\t\t\t\tMax Compute Unit: " << compute_unit << "\n";
+
+  const auto max_work_item_size = device.getInfo<CL_DEVICE_MAX_WORK_ITEM_SIZES>();
+  std::cout << "\t\t\t\tMax Work Item Size: [";
+  for (auto size : max_work_item_size)
+    std::cout << size << ",";
+  std::cout << "]\n";
+
+  const auto max_work_group_size = device.getInfo<CL_DEVICE_MAX_WORK_GROUP_SIZE>();
+  std::cout << "\t\t\t\tMax Work Grpup Size: " << max_work_group_size << "\n";
+
+  const auto max_clock_frequency = device.getInfo<CL_DEVICE_MAX_CLOCK_FREQUENCY>();
+  std::cout << "\t\t\t\tMax Clock Frequency: " << max_clock_frequency << "\n";
+
+  std::cout << "\n";
+}
+
+class OpenCLGpu
+{
+public:
+  cl::Platform platform_;
+  cl::Context context_;
+  cl::vector<cl::Device> devices_;
+  std::vector<cl::CommandQueue *> q_;
+  cl::Program program_;
+
+  OpenCLGpu()
+  {
+    cl_int cl_error;
+
+    platform_ = cl::Platform::getDefault();
+
+    try
+    {
+      cl_context_properties properties[3] = {CL_CONTEXT_PLATFORM,
+                                             (cl_context_properties)platform_(), 0};
+
+      context_ = cl::Context(CL_DEVICE_TYPE_GPU, properties, NULL, NULL, &cl_error);
+    }
+    catch (cl::Error &err) // thrown when there is no Context for this platform
+    {
+      std::cout << "\t\t No Context Found\n";
+      return;
+    }
+
+    devices_ = context_.getInfo<CL_CONTEXT_DEVICES>();
+
+    for (int dev_id = 0; dev_id < devices_.size(); dev_id++)
+    {
+      cl::CommandQueue *que = new cl::CommandQueue(context_, devices_[dev_id]);
+      q_.emplace_back(que);
+    }
+  }
+
+  ~OpenCLGpu()
+  {
+    for (auto each_q : q_)
+      delete each_q;
+  }
+
+  void buildProgram(std::string &kernel_source_code)
+  {
+    std::vector<std::string> programStrings{kernel_source_code};
+
+    program_ = cl::Program(context_, programStrings);
+
+    try
+    {
+      program_.build("-cl-std=CL1.2");
+    }
+    catch (cl::Error &err)
+    {
+      cl_int buildErr = CL_SUCCESS;
+      auto buildInfo = program_.getBuildInfo<CL_PROGRAM_BUILD_LOG>(&buildErr);
+      for (auto &pair : buildInfo)
+      {
+        std::cerr << pair.second << std::endl << std::endl;
+      }
+    }
+  }
+};
+
+void checkContextMem()
+{
+  cl_int cl_error;
+
+  // get context, devices
+  //
+  std::cout << "\nChecking if devices in GPU shares the same memory address:\n\n";
+
+  OpenCLGpu gpu;
+
+  std::cout << "\nDevices in GPU:\n\n";
+
+  auto &devices = gpu.devices_;
+  auto default_device = cl::Device::getDefault();
+
+  int d = 0;
+  for (auto device : devices)
+    printDeviceInfo(++d, device, default_device);
+
+  if (d < 2)
+  {
+    std::cout << "\t\t This options works when there are n (>= 2) devices.\n";
+    return;
+  }
+
+  // allocate and map memory
+
+  typedef cl_int T;
+  const int items_per_device = 128;
+  const int length = items_per_device * devices.size();
+
+  std::vector<T> input(length);
+  std::vector<T> output(length, 0);
+
+  for (int i = 0; i < length; i++)
+    input[i] = i;
+
+  cl::Buffer input_buf(gpu.context_, (cl_mem_flags)CL_MEM_USE_HOST_PTR, length * sizeof(T),
+                       input.data(), &cl_error);
+  cl::Buffer output_buf(gpu.context_, (cl_mem_flags)CL_MEM_USE_HOST_PTR, length * sizeof(T),
+                        output.data(), &cl_error);
+
+  // compile test cl code
+
+  std::string kernel_source{"typedef int T;                                                 \n"
+                            "kernel void memory_test(                                       \n"
+                            "   const int dev_id,                                           \n"
+                            "   global T* input,                                            \n"
+                            "   global T* output,                                           \n"
+                            "   const int start_idx,                                        \n"
+                            "   const int count)                                            \n"
+                            "{                                                              \n"
+                            "   int input_idx = get_global_id(0);                           \n"
+                            "   if(input_idx < count)                                       \n"
+                            "   {                                                           \n"
+                            "       int output_idx = start_idx + input_idx;                 \n"
+                            "       output[output_idx] = input[input_idx] + dev_id;         \n"
+                            "   }                                                           \n"
+                            "}                                                              \n"};
+
+  gpu.buildProgram(kernel_source);
+
+  try
+  {
+    auto kernel_functor = cl::KernelFunctor<cl_int, cl::Buffer, cl::Buffer, cl_int, cl_int>(
+        gpu.program_, "memory_test"); // name should be same as cl function name
+
+    // create a queue per device and queue a kernel job
+
+    for (int dev_id = 0; dev_id < devices.size(); dev_id++)
+    {
+      kernel_functor(cl::EnqueueArgs(*(gpu.q_[dev_id]), cl::NDRange(items_per_device)),
+                     (cl_int)dev_id, // dev id
+                     input_buf, output_buf,
+                     (cl_int)(items_per_device * dev_id), // start index
+                     (cl_int)(items_per_device),          // count
+                     cl_error);
+    }
+
+    // sync
+
+    for (d = 0; d < devices.size(); d++)
+      (gpu.q_[d])->finish();
+
+    // check if memory state changed by all devices
+
+    cl::copy(*(gpu.q_[0]), output_buf, begin(output), end(output));
+
+    bool use_same_memory = true;
+
+    for (int dev_id = 0; dev_id < devices.size(); dev_id++)
+    {
+      for (int i = 0; i < items_per_device; ++i)
+      {
+        int output_idx = items_per_device * dev_id + i;
+        if (output[output_idx] != input[i] + dev_id)
+        {
+          std::cout << "Output[" << output_idx << "] : "
+                    << "expected = " << input[i] + dev_id << "; actual = " << output[output_idx]
+                    << "\n";
+          use_same_memory = false;
+          break;
+        }
+      }
+    }
+
+    if (use_same_memory)
+      std::cout << "\n=> Mapped memory addresses used by devices in GPU are same.\n\n";
+    else
+      std::cout << "\n=> Mapped memory addresses used by devices in GPU are different.\n\n";
+  }
+  catch (cl::Error &err)
+  {
+    std::cerr << "error: code: " << err.err() << ", what: " << err.what() << std::endl;
+  }
+}
+
+void printHelp()
+{
+  std::cout << "opencl information: \n\n";
+  std::cout << "\t -h : help\n";
+  std::cout
+      << "\t -g : print if memory map is shared among devices in GPU (in default platform)\n\n";
+  std::cout << "\t -s : test for synchronized work by two devices in a GPU\n\n";
+}
+
+#include <mutex>
+#include <chrono>
+#include <thread>
+#include <condition_variable>
+
+#define MAX_DEVICE_NUM 8 // just for testing
+
+int kernel_idx[MAX_DEVICE_NUM];
+unsigned char kernel_completed = 0x00; // bit 0 = 1 means kernel by device[0] was completed.
+unsigned char
+    kernel_completed_flag; // if comparing kernel_completed with this var, all kernels are completed
+int device_num;
+std::mutex kernel_complete_handler_mutex;
+
+std::condition_variable wakeup_main;
+std::mutex wakeup_main_mutex;
+
+void notifyKernelFinished(cl_event ev, cl_int ev_info, void *device_idx)
+{
+  std::cout << "callback from device[" << *((int *)device_idx) << "] : ==> completed.\n";
+
+  std::unique_lock<std::mutex> lock(kernel_complete_handler_mutex);
+
+  kernel_completed |= 0x01 << *((int *)device_idx);
+  if (kernel_completed == kernel_completed_flag)
+    wakeup_main.notify_one();
+}
+
+void testSync()
+{
+  OpenCLGpu gpu;
+
+  cl_int cl_error;
+  typedef cl_int T;
+  const int items_per_device = 1024 * 768;
+  const int length = items_per_device * gpu.devices_.size();
+
+  std::vector<T> output(length, 0);
+
+  cl::Buffer output_buf(gpu.context_, (cl_mem_flags)CL_MEM_USE_HOST_PTR, length * sizeof(T),
+                        output.data(), &cl_error);
+
+  std::string kernel_source{"kernel void test(global float* output, const int count)  \n"
+                            "{                                                        \n"
+                            "   int idx = get_global_id(0);                           \n"
+                            "   if(idx < count)                                       \n"
+                            "   {                                                     \n"
+                            "       float x = hypot(idx/1.111, idx*1.111);            \n"
+                            "       for (int y = 0; y < 200; y++)                     \n"
+                            "         x = rootn(log(pown(rootn(log(pown(x, 20)), 5), 20)), 5);  \n"
+                            "       output[idx] = x;                                  \n"
+                            "   }                                                     \n"
+                            "}                                                        \n"};
+
+  gpu.buildProgram(kernel_source);
+
+  try
+  {
+    auto kernel_functor = cl::KernelFunctor<cl::Buffer, cl_int>(
+        gpu.program_, "test"); // name should be same as cl function name
+
+    // variable init
+    cl::Event ev[MAX_DEVICE_NUM];
+
+    device_num = gpu.devices_.size();
+
+    kernel_completed = 0;
+    kernel_completed_flag = 0;
+    for (int i = 0; i < device_num; i++)
+    {
+      kernel_idx[i] = i;
+      kernel_completed_flag |= 0x01 << i;
+    }
+
+    // create a queue per device and queue a kernel job
+    // queueing with callback function
+    for (int dev_id = 0; dev_id < gpu.devices_.size(); dev_id++)
+    {
+      ev[dev_id] = kernel_functor(cl::EnqueueArgs(*(gpu.q_[dev_id]), cl::NDRange(items_per_device)),
+                                  output_buf,
+                                  (cl_int)(items_per_device), // count
+                                  cl_error);
+      ev[dev_id].setCallback(CL_COMPLETE, notifyKernelFinished, (void *)(kernel_idx + dev_id));
+
+      // how to check kernel execution status
+      //
+      // auto status  = ev[dev_id].getInfo<CL_EVENT_COMMAND_EXECUTION_STATUS>();
+      // std::cout << "Event status = " << (status == CL_QUEUED ? "CL_QUEUED" : status ==
+      // CL_SUBMITTED ? "CL_SUBMITTED" : status == CL_COMPLETE ? "CL_COMPLETE" : "unknown")
+      //           << std::endl;
+      // std::cout << "Event status code = " << status << std::endl;
+    }
+
+    // long wait until kernels are over
+    {
+      std::unique_lock<std::mutex> lk(wakeup_main_mutex);
+      wakeup_main.wait(lk, [] { return (kernel_completed == kernel_completed_flag); });
+
+      std::cout << "all devices were completed.\n";
+    }
+  }
+  catch (cl::Error &err)
+  {
+    std::cerr << "error: code: " << err.err() << ", what: " << err.what() << std::endl;
+  }
+}
+
+int main(const int argc, char **argv)
+{
+  if (argc < 2)
+    printHelp();
+  else
+  {
+    std::string option = argv[1];
+
+    if (option == "-h") // help
+      printHelp();
+    else if (option == "-g") // check if devices in GPU uses same memory address
+      checkContextMem();
+    else if (option == "-s") // check synchronization between devices in GPU
+      testSync();
+  }
+  return 0;
+}
diff --git a/runtime/contrib/labs/tflite_examples/CMakeLists.txt b/runtime/contrib/labs/tflite_examples/CMakeLists.txt
new file mode 100644
index 000000000..463bc5531
--- /dev/null
+++ b/runtime/contrib/labs/tflite_examples/CMakeLists.txt
@@ -0,0 +1,2 @@
+add_executable(tflite_conv_example "src/conv.cpp")
+target_link_libraries(tflite_conv_example tensorflow-lite ${LIB_PTHREAD} dl nnfw_lib_tflite)
diff --git a/runtime/contrib/labs/tflite_examples/src/conv.cpp b/runtime/contrib/labs/tflite_examples/src/conv.cpp
new file mode 100644
index 000000000..3117c316c
--- /dev/null
+++ b/runtime/contrib/labs/tflite_examples/src/conv.cpp
@@ -0,0 +1,330 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "tflite/ext/kernels/register.h"
+#include "tensorflow/lite/model.h"
+#include "tensorflow/lite/builtin_op_data.h"
+
+#include <iostream>
+
+using namespace tflite;
+using namespace nnfw::tflite;
+
+namespace vector
+{
+
+template <typename T> struct View
+{
+  virtual ~View() = default;
+
+  virtual int32_t size(void) const = 0;
+  virtual T at(uint32_t off) const = 0;
+};
+}
+
+namespace feature
+{
+
+struct Shape
+{
+  int32_t C;
+  int32_t H;
+  int32_t W;
+};
+
+template <typename T> struct View
+{
+  virtual ~View() = default;
+
+  virtual const Shape &shape(void) const = 0;
+  virtual T at(uint32_t ch, uint32_t row, uint32_t col) const = 0;
+};
+}
+
+namespace kernel
+{
+
+struct Shape
+{
+  int32_t N;
+  int32_t C;
+  int32_t H;
+  int32_t W;
+};
+
+template <typename T> struct View
+{
+  virtual ~View() = default;
+
+  virtual const Shape &shape(void) const = 0;
+  virtual T at(uint32_t nth, uint32_t ch, uint32_t row, uint32_t col) const = 0;
+};
+}
+
+const int32_t N = 1;
+const int32_t C = 2;
+
+class SampleBiasObject final : public vector::View<float>
+{
+public:
+  SampleBiasObject() : _size(N)
+  {
+    // DO NOTHING
+  }
+
+public:
+  int32_t size(void) const override { return _size; }
+
+  float at(uint32_t off) const override { return 0.0f; }
+
+private:
+  int32_t _size;
+};
+
+class SampleFeatureObject final : public feature::View<float>
+{
+public:
+  SampleFeatureObject()
+  {
+    _shape.C = C;
+    _shape.H = 3;
+    _shape.W = 4;
+
+    const uint32_t size = _shape.C * _shape.H * _shape.W;
+
+    for (uint32_t off = 0; off < size; ++off)
+    {
+      _value.emplace_back(off);
+    }
+
+    assert(_value.size() == size);
+  }
+
+public:
+  const feature::Shape &shape(void) const override { return _shape; };
+
+  float at(uint32_t ch, uint32_t row, uint32_t col) const override
+  {
+    return _value.at(ch * _shape.H * _shape.W + row * _shape.W + col);
+  }
+
+public:
+  float &at(uint32_t ch, uint32_t row, uint32_t col)
+  {
+    return _value.at(ch * _shape.H * _shape.W + row * _shape.W + col);
+  }
+
+private:
+  feature::Shape _shape;
+  std::vector<float> _value;
+};
+
+class SampleKernelObject final : public kernel::View<float>
+{
+public:
+  SampleKernelObject()
+  {
+    _shape.N = N;
+    _shape.C = C;
+    _shape.H = 3;
+    _shape.W = 4;
+
+    const uint32_t size = _shape.N * _shape.C * _shape.H * _shape.W;
+
+    for (uint32_t off = 0; off < size; ++off)
+    {
+      _value.emplace_back(off);
+    }
+
+    assert(_value.size() == size);
+  }
+
+public:
+  const kernel::Shape &shape(void) const override { return _shape; };
+
+  float at(uint32_t nth, uint32_t ch, uint32_t row, uint32_t col) const override
+  {
+    return _value.at(nth * _shape.C * _shape.H * _shape.W + ch * _shape.H * _shape.W +
+                     row * _shape.W + col);
+  }
+
+private:
+  kernel::Shape _shape;
+  std::vector<float> _value;
+};
+
+int main(int argc, char **argv)
+{
+  const SampleFeatureObject ifm;
+  const SampleKernelObject kernel;
+  const SampleBiasObject bias;
+
+  const int32_t IFM_C = ifm.shape().C;
+  const int32_t IFM_H = ifm.shape().H;
+  const int32_t IFM_W = ifm.shape().W;
+
+  const int32_t KER_N = kernel.shape().N;
+  const int32_t KER_C = kernel.shape().C;
+  const int32_t KER_H = kernel.shape().H;
+  const int32_t KER_W = kernel.shape().W;
+
+  const int32_t OFM_C = kernel.shape().N;
+  const int32_t OFM_H = (IFM_H - KER_H) + 1;
+  const int32_t OFM_W = (IFM_W - KER_W) + 1;
+
+  // Assumption on this example
+  assert(IFM_C == KER_C);
+  assert(KER_N == bias.size());
+
+  // Comment from 'context.h'
+  //
+  // Parameters for asymmetric quantization. Quantized values can be converted
+  // back to float using:
+  //    real_value = scale * (quantized_value - zero_point);
+  //
+  // Q: Is this necessary?
+  TfLiteQuantizationParams quantization;
+
+  quantization.scale = 1;
+  quantization.zero_point = 0;
+
+  Interpreter interp;
+
+  // On AddTensors(N) call, T/F Lite interpreter creates N tensors whose index is [0 ~ N)
+  interp.AddTensors(5);
+
+  // Configure OFM
+  interp.SetTensorParametersReadWrite(0, kTfLiteFloat32 /* type */, "output" /* name */,
+                                      {1 /*N*/, OFM_H, OFM_W, OFM_C} /* dims */, quantization);
+
+  // Configure IFM
+  interp.SetTensorParametersReadWrite(1, kTfLiteFloat32 /* type */, "input" /* name */,
+                                      {1 /*N*/, IFM_H, IFM_W, IFM_C} /* dims */, quantization);
+
+  // Configure Filter
+  const uint32_t kernel_size = KER_N * KER_C * KER_H * KER_W;
+  float kernel_data[kernel_size] = {
+      0.0f,
+  };
+
+  // Fill kernel data in NHWC order
+  {
+    uint32_t off = 0;
+
+    for (uint32_t nth = 0; nth < KER_N; ++nth)
+    {
+      for (uint32_t row = 0; row < KER_H; ++row)
+      {
+        for (uint32_t col = 0; col < KER_W; ++col)
+        {
+          for (uint32_t ch = 0; ch < KER_C; ++ch)
+          {
+            const auto value = kernel.at(nth, ch, row, col);
+            kernel_data[off++] = value;
+          }
+        }
+      }
+    }
+
+    assert(kernel_size == off);
+  }
+
+  interp.SetTensorParametersReadOnly(
+      2, kTfLiteFloat32 /* type */, "filter" /* name */, {KER_N, KER_H, KER_W, KER_C} /* dims */,
+      quantization, reinterpret_cast<const char *>(kernel_data), sizeof(kernel_data));
+
+  // Configure Bias
+  const uint32_t bias_size = bias.size();
+  float bias_data[bias_size] = {
+      0.0f,
+  };
+
+  // Fill bias data
+  for (uint32_t off = 0; off < bias.size(); ++off)
+  {
+    bias_data[off] = bias.at(off);
+  }
+
+  interp.SetTensorParametersReadOnly(3, kTfLiteFloat32 /* type */, "bias" /* name */,
+                                     {bias.size()} /* dims */, quantization,
+                                     reinterpret_cast<const char *>(bias_data), sizeof(bias_data));
+
+  // Add Convolution Node
+  //
+  // NOTE AddNodeWithParameters take the ownership of param, and deallocate it with free
+  //      So, param should be allocated with malloc
+  TfLiteConvParams *param = reinterpret_cast<TfLiteConvParams *>(malloc(sizeof(TfLiteConvParams)));
+
+  param->padding = kTfLitePaddingValid;
+  param->stride_width = 1;
+  param->stride_height = 1;
+  param->activation = kTfLiteActRelu;
+
+  // Run Convolution and store its result into Tensor #0
+  //  - Read IFM from Tensor #1
+  //  - Read Filter from Tensor #2,
+  //  - Read Bias from Tensor #3
+  interp.AddNodeWithParameters({1, 2, 3}, {0}, nullptr, 0, reinterpret_cast<void *>(param),
+                               BuiltinOpResolver().FindOp(BuiltinOperator_CONV_2D, 1));
+
+  // Set Tensor #1 as Input #0, and Tensor #0 as Output #0
+  interp.SetInputs({1});
+  interp.SetOutputs({0});
+
+  // Let's use NNAPI (if possible)
+  interp.UseNNAPI(true);
+
+  // Allocate Tensor
+  interp.AllocateTensors();
+
+  // Fill IFM data in HWC order
+  {
+    uint32_t off = 0;
+
+    for (uint32_t row = 0; row < ifm.shape().H; ++row)
+    {
+      for (uint32_t col = 0; col < ifm.shape().W; ++col)
+      {
+        for (uint32_t ch = 0; ch < ifm.shape().C; ++ch)
+        {
+          const auto value = ifm.at(ch, row, col);
+          interp.typed_input_tensor<float>(0)[off++] = value;
+        }
+      }
+    }
+  }
+
+  // Let's Rock-n-Roll!
+  interp.Invoke();
+
+  // Print OFM
+  {
+    uint32_t off = 0;
+
+    for (uint32_t row = 0; row < OFM_H; ++row)
+    {
+      for (uint32_t col = 0; col < OFM_W; ++col)
+      {
+        for (uint32_t ch = 0; ch < kernel.shape().N; ++ch)
+        {
+          std::cout << interp.typed_output_tensor<float>(0)[off++] << std::endl;
+        }
+      }
+    }
+  }
+
+  return 0;
+}
diff --git a/runtime/contrib/logging/CMakeLists.txt b/runtime/contrib/logging/CMakeLists.txt
new file mode 100644
index 000000000..b200bf89a
--- /dev/null
+++ b/runtime/contrib/logging/CMakeLists.txt
@@ -0,0 +1,12 @@
+if(NOT BUILD_LOGGING)
+  return()
+endif(NOT BUILD_LOGGING)
+
+file(GLOB_RECURSE NNAPI_LOGGING_SRCS "src/*.cc")
+
+nnas_find_package(Boost REQUIRED)
+
+add_library(neuralnetworks SHARED ${NNAPI_LOGGING_SRCS})
+target_include_directories(neuralnetworks PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/include)
+target_include_directories(neuralnetworks PRIVATE ${Boost_INCLUDE_DIRS})
+target_link_libraries(neuralnetworks PUBLIC nnfw-nnapi-header)
diff --git a/runtime/contrib/logging/include/operand.def b/runtime/contrib/logging/include/operand.def
new file mode 100644
index 000000000..c570cf026
--- /dev/null
+++ b/runtime/contrib/logging/include/operand.def
@@ -0,0 +1,12 @@
+// Extracted from tensorflow/contrib/lite/nnapi/NeuralNetworksShim.h
+//
+// NNAPI_OPERAND(NAME, CODE)
+#ifndef NNAPI_OPERAND
+#error NNAPI_OPERAND should be defined
+#endif
+NNAPI_OPERAND(ANEURALNETWORKS_FLOAT32, 0)
+NNAPI_OPERAND(ANEURALNETWORKS_INT32, 1)
+NNAPI_OPERAND(ANEURALNETWORKS_UINT32, 2)
+NNAPI_OPERAND(ANEURALNETWORKS_TENSOR_FLOAT32, 3)
+NNAPI_OPERAND(ANEURALNETWORKS_TENSOR_INT32, 4)
+NNAPI_OPERAND(ANEURALNETWORKS_TENSOR_QUANT8_ASYMM, 5)
diff --git a/runtime/contrib/logging/include/operation.def b/runtime/contrib/logging/include/operation.def
new file mode 100644
index 000000000..cace360d7
--- /dev/null
+++ b/runtime/contrib/logging/include/operation.def
@@ -0,0 +1,15 @@
+// Extracted from tensorflow/contrib/lite/nnapi/NeuralNetworksShim.h
+//
+// NNAPI_OPERATION(NAME, CODE)
+#ifndef NNAPI_OPERATION
+#error NNAPI_OPERATION should be defined
+#endif
+NNAPI_OPERATION(ANEURALNETWORKS_AVERAGE_POOL_2D, 1)
+NNAPI_OPERATION(ANEURALNETWORKS_CONCATENATION, 2)
+NNAPI_OPERATION(ANEURALNETWORKS_CONV_2D, 3)
+NNAPI_OPERATION(ANEURALNETWORKS_DEPTHWISE_CONV_2D, 4)
+NNAPI_OPERATION(ANEURALNETWORKS_FULLY_CONNECTED, 9)
+NNAPI_OPERATION(ANEURALNETWORKS_MAX_POOL_2D, 17)
+NNAPI_OPERATION(ANEURALNETWORKS_RESHAPE, 22)
+NNAPI_OPERATION(ANEURALNETWORKS_RESIZE_BILINEAR, 23)
+NNAPI_OPERATION(ANEURALNETWORKS_SOFTMAX, 25)
diff --git a/runtime/contrib/logging/src/nnapi_logging.cc b/runtime/contrib/logging/src/nnapi_logging.cc
new file mode 100644
index 000000000..14f2369ec
--- /dev/null
+++ b/runtime/contrib/logging/src/nnapi_logging.cc
@@ -0,0 +1,399 @@
+#include <NeuralNetworks.h>
+#include <NeuralNetworksEx.h>
+
+#include <stdexcept>
+#include <iostream>
+
+#include <string>
+#include <map>
+
+#include <cassert>
+
+#include <boost/format.hpp>
+
+namespace
+{
+
+class OperationCodeResolver
+{
+public:
+  OperationCodeResolver();
+
+public:
+  std::string resolve(int code) const;
+
+private:
+  void setName(int code, const std::string &name);
+
+private:
+  std::map<int, std::string> _table;
+
+public:
+  static const OperationCodeResolver &access()
+  {
+    static const OperationCodeResolver resolver;
+
+    return resolver;
+  }
+};
+
+OperationCodeResolver::OperationCodeResolver()
+{
+#define NNAPI_OPERATION(NAME, CODE) setName(CODE, #NAME);
+#include "operation.def"
+#undef NNAPI_OPERATION
+}
+
+void OperationCodeResolver::setName(int code, const std::string &name)
+{
+  assert(_table.find(code) == _table.end());
+  _table[code] = name;
+}
+
+std::string OperationCodeResolver::resolve(int code) const
+{
+  auto it = _table.find(code);
+
+  if (it == _table.end())
+  {
+    return boost::str(boost::format("unknown(%d)") % code);
+  }
+
+  return it->second;
+}
+
+class OperandCodeResolver
+{
+public:
+  OperandCodeResolver();
+
+public:
+  std::string resolve(int code) const;
+
+private:
+  void setName(int code, const std::string &name);
+
+private:
+  std::map<int, std::string> _table;
+
+public:
+  static const OperandCodeResolver &access()
+  {
+    static const OperandCodeResolver resolver;
+
+    return resolver;
+  }
+};
+
+OperandCodeResolver::OperandCodeResolver()
+{
+#define NNAPI_OPERAND(NAME, CODE) setName(CODE, #NAME);
+#include "operand.def"
+#undef NNAPI_OPERAND
+}
+
+void OperandCodeResolver::setName(int code, const std::string &name)
+{
+  assert(_table.find(code) == _table.end());
+  _table[code] = name;
+}
+
+std::string OperandCodeResolver::resolve(int code) const
+{
+  auto it = _table.find(code);
+
+  if (it == _table.end())
+  {
+    return boost::str(boost::format("unknown(%d)") % code);
+  }
+
+  return it->second;
+}
+}
+
+//
+// Asynchronous Event
+//
+struct ANeuralNetworksEvent
+{
+};
+
+int ANeuralNetworksEvent_wait(ANeuralNetworksEvent *event) { return ANEURALNETWORKS_NO_ERROR; }
+
+void ANeuralNetworksEvent_free(ANeuralNetworksEvent *event) { delete event; }
+
+//
+// Memory
+//
+struct ANeuralNetworksMemory
+{
+  // 1st approach - Store all the data inside ANeuralNetworksMemory object
+  // 2nd approach - Store metadata only, and defer data loading as much as possible
+};
+
+int ANeuralNetworksMemory_createFromFd(size_t size, int protect, int fd, size_t offset,
+                                       ANeuralNetworksMemory **memory)
+{
+  *memory = new ANeuralNetworksMemory;
+
+  std::cout << __FUNCTION__ << "() --> (memory: " << *memory << ")" << std::endl;
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+void ANeuralNetworksMemory_free(ANeuralNetworksMemory *memory)
+{
+  std::cout << __FUNCTION__ << "(" << memory << ")" << std::endl;
+  delete memory;
+}
+
+//
+// Model
+//
+struct ANeuralNetworksModel
+{
+  // ANeuralNetworksModel should be a factory for Graph IR (a.k.a ISA Frontend)
+  // TODO Record # of operands
+  uint32_t numOperands;
+
+  ANeuralNetworksModel() : numOperands(0)
+  {
+    // DO NOTHING
+  }
+};
+
+int ANeuralNetworksModel_create(ANeuralNetworksModel **model)
+{
+  *model = new ANeuralNetworksModel;
+
+  std::cout << __FUNCTION__ << "(" << model << ") --> (model: " << *model << ")" << std::endl;
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+void ANeuralNetworksModel_free(ANeuralNetworksModel *model)
+{
+  std::cout << __FUNCTION__ << "(" << model << ")" << std::endl;
+
+  delete model;
+}
+
+int ANeuralNetworksModel_addOperand(ANeuralNetworksModel *model,
+                                    const ANeuralNetworksOperandType *type)
+{
+  std::cout << __FUNCTION__ << "(model: " << model
+            << ", type: " << ::OperandCodeResolver::access().resolve(type->type) << ")"
+            << std::endl;
+
+  auto id = model->numOperands;
+
+  std::cout << "  id: " << id << std::endl;
+  std::cout << "  rank: " << type->dimensionCount << std::endl;
+  for (uint32_t dim = 0; dim < type->dimensionCount; ++dim)
+  {
+    std::cout << "    dim(" << dim << "): " << type->dimensions[dim] << std::endl;
+  }
+
+  model->numOperands += 1;
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksModel_setOperandValue(ANeuralNetworksModel *model, int32_t index,
+                                         const void *buffer, size_t length)
+{
+  std::cout << __FUNCTION__ << "(model: " << model << ", index: " << index << ")" << std::endl;
+
+  // TODO Implement this!
+  // NOTE buffer becomes invalid after ANeuralNetworksModel_setOperandValue returns
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksModel_setOperandValueFromMemory(ANeuralNetworksModel *model, int32_t index,
+                                                   const ANeuralNetworksMemory *memory,
+                                                   size_t offset, size_t length)
+{
+  std::cout << __FUNCTION__ << "(model: " << model << ", index: " << index << ")" << std::endl;
+
+  // TODO Implement this!
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksModel_addOperation(ANeuralNetworksModel *model,
+                                      ANeuralNetworksOperationType type, uint32_t inputCount,
+                                      const uint32_t *inputs, uint32_t outputCount,
+                                      const uint32_t *outputs)
+{
+  std::cout << __FUNCTION__ << "(model: " << model
+            << ", type: " << ::OperationCodeResolver::access().resolve(type)
+            << ", inputCount: " << inputCount << ", outputCount: " << outputCount << ")"
+            << std::endl;
+
+  for (uint32_t input = 0; input < inputCount; ++input)
+  {
+    std::cout << "  input(" << input << "): " << inputs[input] << std::endl;
+  }
+  for (uint32_t output = 0; output < outputCount; ++output)
+  {
+    std::cout << "  output(" << output << "): " << outputs[output] << std::endl;
+  }
+
+  // TODO Implement this!
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksModel_addOperationEx(ANeuralNetworksModel *model,
+                                        ANeuralNetworksOperationTypeEx type, uint32_t inputCount,
+                                        const uint32_t *inputs, uint32_t outputCount,
+                                        const uint32_t *outputs)
+{
+  std::cout << __FUNCTION__ << "(model: " << model << ", type: " << type
+            << ", inputCount: " << inputCount << ", outputCount: " << outputCount << ")"
+            << std::endl;
+
+  for (uint32_t input = 0; input < inputCount; ++input)
+  {
+    std::cout << "  input(" << input << "): " << inputs[input] << std::endl;
+  }
+  for (uint32_t output = 0; output < outputCount; ++output)
+  {
+    std::cout << "  output(" << output << "): " << outputs[output] << std::endl;
+  }
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksModel_identifyInputsAndOutputs(ANeuralNetworksModel *model, uint32_t inputCount,
+                                                  const uint32_t *inputs, uint32_t outputCount,
+                                                  const uint32_t *outputs)
+{
+  std::cout << __FUNCTION__ << "(model: " << model << ")" << std::endl;
+
+  for (uint32_t input = 0; input < inputCount; ++input)
+  {
+    std::cout << "  input(" << input << "): " << inputs[input] << std::endl;
+  }
+  for (uint32_t output = 0; output < outputCount; ++output)
+  {
+    std::cout << "  output(" << output << "): " << outputs[output] << std::endl;
+  }
+
+  // TODO Implement this!
+  // NOTE It seems that this function identifies the input and output of the whole model
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksModel_finish(ANeuralNetworksModel *model)
+{
+  std::cout << __FUNCTION__ << "(model: " << model << ")" << std::endl;
+
+  // TODO Implement this!
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+//
+// Compilation
+//
+struct ANeuralNetworksCompilation
+{
+  // ANeuralNetworksCompilation should hold a compiled IR
+};
+
+int ANeuralNetworksCompilation_create(ANeuralNetworksModel *model,
+                                      ANeuralNetworksCompilation **compilation)
+{
+  *compilation = new ANeuralNetworksCompilation;
+
+  std::cout << __FUNCTION__ << "(model: " << model << ") --> (compilation: " << *compilation << ")"
+            << std::endl;
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksCompilation_finish(ANeuralNetworksCompilation *compilation)
+{
+  std::cout << __FUNCTION__ << "(compilation: " << compilation << ")" << std::endl;
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+//
+// Execution
+//
+struct ANeuralNetworksExecution
+{
+  // ANeuralNetworksExecution corresponds to NPU::Interp::Session
+};
+
+int ANeuralNetworksExecution_create(ANeuralNetworksCompilation *compilation,
+                                    ANeuralNetworksExecution **execution)
+{
+  *execution = new ANeuralNetworksExecution;
+
+  std::cout << __FUNCTION__ << "(compilation: " << compilation << ") --> (execution: " << *execution
+            << ")" << std::endl;
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+// ANeuralNetworksExecution_setInput and ANeuralNetworksExecution_setOutput specify HOST buffer for
+// input/output
+int ANeuralNetworksExecution_setInput(ANeuralNetworksExecution *execution, int32_t index,
+                                      const ANeuralNetworksOperandType *type, const void *buffer,
+                                      size_t length)
+{
+  std::cout << __FUNCTION__ << "(execution: " << execution << ", type: ";
+
+  if (type == nullptr)
+    std::cout << "nullptr)" << std::endl;
+  else
+    std::cout << ::OperandCodeResolver::access().resolve(type->type) << ")" << std::endl;
+
+  // Q: Should we transfer input from HOST to DEVICE here, or in
+  // ANeuralNetworksExecution_startCompute?
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksExecution_setOutput(ANeuralNetworksExecution *execution, int32_t index,
+                                       const ANeuralNetworksOperandType *type, void *buffer,
+                                       size_t length)
+{
+  std::cout << __FUNCTION__ << "(execution: " << execution << ", type: ";
+
+  if (type == nullptr)
+    std::cout << "nullptr)" << std::endl;
+  else
+    std::cout << ::OperandCodeResolver::access().resolve(type->type) << ")" << std::endl;
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksExecution_startCompute(ANeuralNetworksExecution *execution,
+                                          ANeuralNetworksEvent **event)
+{
+  *event = new ANeuralNetworksEvent;
+
+  std::cout << __FUNCTION__ << "(execution: " << execution << ") --> (event: " << *event << ")"
+            << std::endl;
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+void ANeuralNetworksExecution_free(ANeuralNetworksExecution *execution)
+{
+  std::cout << __FUNCTION__ << "(execution: " << execution << ")" << std::endl;
+
+  delete execution;
+}
+
+void ANeuralNetworksCompilation_free(ANeuralNetworksCompilation *compilation)
+{
+  std::cout << __FUNCTION__ << "(compilation: " << compilation << ")" << std::endl;
+  delete compilation;
+}
diff --git a/runtime/contrib/mlapse/CMakeLists.txt b/runtime/contrib/mlapse/CMakeLists.txt
new file mode 100644
index 000000000..bba79971a
--- /dev/null
+++ b/runtime/contrib/mlapse/CMakeLists.txt
@@ -0,0 +1,8 @@
+if(NOT BUILD_MLAPSE)
+  return()
+endif(NOT BUILD_MLAPSE)
+
+message(STATUS "Build mlapse: TRUE")
+
+# TODO Add "core"
+add_subdirectory(tfl)
diff --git a/runtime/contrib/mlapse/README.md b/runtime/contrib/mlapse/README.md
new file mode 100644
index 000000000..36f14ac39
--- /dev/null
+++ b/runtime/contrib/mlapse/README.md
@@ -0,0 +1,3 @@
+# mlapse
+
+_mlapse_ is a toolkit for model inference latency benchmark.
diff --git a/runtime/contrib/mlapse/tfl/CMakeLists.txt b/runtime/contrib/mlapse/tfl/CMakeLists.txt
new file mode 100644
index 000000000..36f32d7ef
--- /dev/null
+++ b/runtime/contrib/mlapse/tfl/CMakeLists.txt
@@ -0,0 +1,12 @@
+message(STATUS "Build mlapse-tfl: TRUE")
+
+file(GLOB_RECURSE SOURCES "*.cc")
+
+add_executable(mlapse-tfl ${SOURCES})
+target_include_directories(mlapse-tfl PRIVATE ${CMAKE_CURRENT_SOURCE_DIR})
+target_link_libraries(mlapse-tfl nnfw_lib_tflite)
+target_link_libraries(mlapse-tfl nnfw_lib_misc)
+target_link_libraries(mlapse-tfl nnfw_lib_cpp14)
+target_link_libraries(mlapse-tfl tensorflow-lite)
+
+install(TARGETS mlapse-tfl DESTINATION bin)
diff --git a/runtime/contrib/mlapse/tfl/driver.cc b/runtime/contrib/mlapse/tfl/driver.cc
new file mode 100644
index 000000000..867a6051a
--- /dev/null
+++ b/runtime/contrib/mlapse/tfl/driver.cc
@@ -0,0 +1,280 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mlapse/benchmark_runner.h"
+#include "mlapse/multicast_observer.h"
+#include "mlapse/CSV_report_generator.h"
+
+#include "mlapse/tfl/load.h"
+
+// From 'nnfw_lib_tflite'
+#include <tflite/InterpreterSession.h>
+#include <tflite/NNAPISession.h>
+
+// From 'nnfw_lib_cpp14'
+#include <cpp14/memory.h>
+
+// From C++ Standard Library
+#include <cassert>
+#include <fstream>
+#include <iostream>
+#include <vector>
+
+namespace
+{
+
+using namespace mlapse;
+
+class ConsoleReporter final : public mlapse::BenchmarkObserver
+{
+public:
+  ConsoleReporter() = default;
+
+public:
+  void notify(const NotificationArg<PhaseBegin> &arg) final
+  {
+    _phase = arg.phase;
+    _count = arg.count;
+
+    std::cout << tag() << " BEGIN" << std::endl;
+  }
+
+  void notify(const NotificationArg<PhaseEnd> &arg) final
+  {
+    std::cout << tag() << " END" << std::endl;
+
+    _phase = mlapse::uninitialized_phase();
+    _count = 0;
+  }
+
+  void notify(const NotificationArg<IterationBegin> &arg) final { _index = arg.index; }
+
+  void notify(const NotificationArg<IterationEnd> &arg) final
+  {
+    std::cout << tag() << " " << progress() << " - " << arg.latency.count() << "ms" << std::endl;
+  }
+
+private:
+  std::string progress(void) const
+  {
+    return "[" + std::to_string(_index + 1) + "/" + std::to_string(_count) + "]";
+  }
+
+  std::string tag(void) const
+  {
+    switch (_phase)
+    {
+      case Phase::Warmup:
+        return "WARMUP";
+      case Phase::Record:
+        return "RECORD";
+      default:
+        break;
+    }
+
+    return "unknown";
+  }
+
+  Phase _phase = mlapse::uninitialized_phase();
+  uint32_t _count = 0;
+  uint32_t _index = 0;
+};
+
+} // namespace
+
+// Q. Is is worth to make a library for these routines?
+namespace
+{
+
+enum class SessionType
+{
+  Interp,
+  NNAPI,
+};
+
+class SessionBuilder
+{
+public:
+  SessionBuilder(const SessionType &type) : _type{type}
+  {
+    // DO NOTHING
+  }
+
+public:
+  std::unique_ptr<nnfw::tflite::Session> with(tflite::Interpreter *interp) const
+  {
+    switch (_type)
+    {
+      case SessionType::Interp:
+        return nnfw::cpp14::make_unique<nnfw::tflite::InterpreterSession>(interp);
+      case SessionType::NNAPI:
+        return nnfw::cpp14::make_unique<nnfw::tflite::NNAPISession>(interp);
+      default:
+        break;
+    }
+
+    return nullptr;
+  }
+
+  std::unique_ptr<nnfw::tflite::Session>
+  with(const std::unique_ptr<tflite::Interpreter> &interp) const
+  {
+    return with(interp.get());
+  }
+
+private:
+  SessionType _type;
+};
+
+SessionBuilder make_session(const SessionType &type) { return SessionBuilder{type}; }
+
+} // namespace
+
+namespace
+{
+
+// mlapse-tfl
+//  [REQUIRED] --model <path/to/tflite>
+//  [OPTIONAL] --warmup-count N (default = 3)
+//  [OPTIONAL] --record-count N (default = 10)
+//  [OPTIONAL] --thread N or auto (default = auto)
+//  [OPTIOANL] --nnapi (default = off)
+//  [OPTIONAL] --pause N (default = 0)
+//  [OPTIONAL] --csv-report <path/to/csv>
+int entry(const int argc, char **argv)
+{
+  // Create an observer
+  mlapse::MulticastObserver observer;
+
+  observer.append(nnfw::cpp14::make_unique<ConsoleReporter>());
+
+  // Set default parameters
+  std::string model_path;
+  bool model_path_initialized = false;
+
+  SessionType session_type = SessionType::Interp;
+  uint32_t warmup_count = 3;
+  uint32_t record_count = 10;
+  int num_thread = -1; // -1 means "auto"
+
+  // Read command-line arguments
+  std::map<std::string, std::function<uint32_t(const char *const *)>> opts;
+
+  opts["--model"] = [&model_path, &model_path_initialized](const char *const *tok) {
+    model_path = std::string{tok[0]};
+    model_path_initialized = true;
+    return 1; // # of arguments
+  };
+
+  opts["--record-count"] = [&record_count](const char *const *tok) {
+    record_count = std::stoi(tok[0]);
+    return 1; // # of arguments
+  };
+
+  opts["--thread"] = [](const char *const *tok) {
+    assert(std::string{tok[0]} == "auto");
+    return 1;
+  };
+
+  opts["--nnapi"] = [&session_type](const char *const *) {
+    session_type = SessionType::NNAPI;
+    return 0;
+  };
+
+  opts["--csv-report"] = [&observer](const char *const *tok) {
+    observer.append(nnfw::cpp14::make_unique<mlapse::CSVReportGenerator>(tok[0]));
+    return 1;
+  };
+
+  {
+    uint32_t offset = 1;
+
+    while (offset < argc)
+    {
+      auto opt = argv[offset];
+
+      auto it = opts.find(opt);
+
+      if (it == opts.end())
+      {
+        std::cout << "INVALID OPTION: " << opt << std::endl;
+        return 255;
+      }
+
+      auto func = it->second;
+
+      auto num_skip = func(argv + offset + 1);
+
+      offset += 1;
+      offset += num_skip;
+    }
+  }
+
+  // Check arguments
+  if (!model_path_initialized)
+  {
+    std::cerr << "ERROR: --model is missing" << std::endl;
+    return 255;
+  }
+
+  // Load T/F Lite model
+  auto model = mlapse::tfl::load_model(model_path);
+
+  if (model == nullptr)
+  {
+    std::cerr << "ERROR: Failed to load '" << model_path << "'" << std::endl;
+    return 255;
+  }
+
+  auto interp = mlapse::tfl::make_interpreter(model.get());
+
+  if (interp == nullptr)
+  {
+    std::cerr << "ERROR: Failed to create a T/F Lite interpreter" << std::endl;
+    return 255;
+  }
+
+  auto sess = make_session(session_type).with(interp);
+
+  if (sess == nullptr)
+  {
+    std::cerr << "ERROR: Failed to create a session" << std::endl;
+  }
+
+  // Run benchmark
+  mlapse::BenchmarkRunner benchmark_runner{warmup_count, record_count};
+
+  benchmark_runner.attach(&observer);
+  benchmark_runner.run(sess);
+
+  return 0;
+}
+
+} // namespace
+
+int main(int argc, char **argv)
+{
+  try
+  {
+    return entry(argc, argv);
+  }
+  catch (const std::exception &e)
+  {
+    std::cerr << e.what() << std::endl;
+  }
+
+  return 255;
+}
diff --git a/runtime/contrib/mlapse/tfl/mlapse/CSV_report_generator.cc b/runtime/contrib/mlapse/tfl/mlapse/CSV_report_generator.cc
new file mode 100644
index 000000000..c6237a04f
--- /dev/null
+++ b/runtime/contrib/mlapse/tfl/mlapse/CSV_report_generator.cc
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mlapse/CSV_report_generator.h"
+
+#include <cassert>
+#include <stdexcept>
+
+namespace
+{
+
+std::string tag(const mlapse::Phase &phase)
+{
+  switch (phase)
+  {
+    case mlapse::Phase::Warmup:
+      return "WARMUP";
+    case mlapse::Phase::Record:
+      return "STEADY";
+    default:
+      break;
+  }
+
+  throw std::invalid_argument{"phase"};
+}
+
+} // namespace
+
+namespace mlapse
+{
+
+void CSVReportGenerator::notify(const NotificationArg<PhaseBegin> &arg)
+{
+  assert(_phase == uninitialized_phase());
+  _phase = arg.phase;
+}
+
+void CSVReportGenerator::notify(const NotificationArg<PhaseEnd> &arg)
+{
+  assert(_phase != uninitialized_phase());
+  _phase = uninitialized_phase();
+}
+
+void CSVReportGenerator::notify(const NotificationArg<IterationBegin> &arg)
+{
+  // DO NOTHING
+}
+
+void CSVReportGenerator::notify(const NotificationArg<IterationEnd> &arg)
+{
+  _ofs << tag(_phase) << "," << arg.latency.count() << std::endl;
+}
+
+} // namespace mlapse
diff --git a/runtime/contrib/mlapse/tfl/mlapse/CSV_report_generator.h b/runtime/contrib/mlapse/tfl/mlapse/CSV_report_generator.h
new file mode 100644
index 000000000..8842baf8e
--- /dev/null
+++ b/runtime/contrib/mlapse/tfl/mlapse/CSV_report_generator.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MLAPSE_CSV_REPORT_GENERATOR_H__
+#define __MLAPSE_CSV_REPORT_GENERATOR_H__
+
+#include "mlapse/benchmark_observer.h"
+
+#include <fstream>
+#include <string>
+
+namespace mlapse
+{
+
+class CSVReportGenerator final : public BenchmarkObserver
+{
+public:
+  CSVReportGenerator(const std::string &path) : _ofs{path, std::ofstream::out}
+  {
+    // DO NOTHING
+  }
+
+public:
+  void notify(const NotificationArg<PhaseBegin> &arg) final;
+  void notify(const NotificationArg<PhaseEnd> &arg) final;
+  void notify(const NotificationArg<IterationBegin> &arg) final;
+  void notify(const NotificationArg<IterationEnd> &arg);
+
+private:
+  std::ofstream _ofs;
+
+  Phase _phase = uninitialized_phase();
+};
+
+} // namespace mlapse
+
+#endif // __MLAPSE_MULTICAST_OBSERER_H__
diff --git a/runtime/contrib/mlapse/tfl/mlapse/benchmark_observer.cc b/runtime/contrib/mlapse/tfl/mlapse/benchmark_observer.cc
new file mode 100644
index 000000000..f6d596a7b
--- /dev/null
+++ b/runtime/contrib/mlapse/tfl/mlapse/benchmark_observer.cc
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mlapse/benchmark_observer.h"
+
+namespace mlapse
+{
+
+Phase uninitialized_phase(void) { return static_cast<Phase>(0); }
+
+} // namespace mlapse
diff --git a/runtime/contrib/mlapse/tfl/mlapse/benchmark_observer.h b/runtime/contrib/mlapse/tfl/mlapse/benchmark_observer.h
new file mode 100644
index 000000000..8fc570d24
--- /dev/null
+++ b/runtime/contrib/mlapse/tfl/mlapse/benchmark_observer.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MLAPSE_BENCHMARK_OBSERVER_H__
+#define __MLAPSE_BENCHMARK_OBSERVER_H__
+
+#include <cstdint>
+#include <chrono>
+
+namespace mlapse
+{
+
+enum Phase : int32_t
+{
+  // 0 denotes "uninitialized value"
+  Warmup = 1,
+  Record = 2,
+};
+
+Phase uninitialized_phase(void);
+
+enum Notification
+{
+  PhaseBegin,
+  PhaseEnd,
+  IterationBegin,
+  IterationEnd,
+};
+
+template <Notification N> struct NotificationArg;
+
+template <> struct NotificationArg<PhaseBegin>
+{
+  Phase phase;
+  uint32_t count;
+};
+
+template <> struct NotificationArg<PhaseEnd>
+{
+};
+
+template <> struct NotificationArg<IterationBegin>
+{
+  uint32_t index;
+};
+
+template <> struct NotificationArg<IterationEnd>
+{
+  std::chrono::milliseconds latency;
+};
+
+struct BenchmarkObserver
+{
+  virtual ~BenchmarkObserver() = default;
+
+  virtual void notify(const NotificationArg<PhaseBegin> &arg) = 0;
+  virtual void notify(const NotificationArg<PhaseEnd> &arg) = 0;
+  virtual void notify(const NotificationArg<IterationBegin> &arg) = 0;
+  virtual void notify(const NotificationArg<IterationEnd> &arg) = 0;
+};
+
+} // namespace mlpase
+
+#endif // __MLAPSE_BENCHMARK_OBSERVER_H__
diff --git a/runtime/contrib/mlapse/tfl/mlapse/benchmark_runner.cc b/runtime/contrib/mlapse/tfl/mlapse/benchmark_runner.cc
new file mode 100644
index 000000000..f5fc7302d
--- /dev/null
+++ b/runtime/contrib/mlapse/tfl/mlapse/benchmark_runner.cc
@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mlapse/benchmark_runner.h"
+
+// From 'nnfw_lib_misc'
+#include <misc/benchmark.h>
+
+// From C++ Standard Library
+#include <cassert>
+
+namespace mlapse
+{
+void BenchmarkRunner::attach(BenchmarkObserver *observer)
+{
+  assert(_observer == nullptr);
+  _observer = observer;
+}
+
+void BenchmarkRunner::run(nnfw::tflite::Session *sess) const
+{
+  for (auto phase : {Warmup, Record})
+  {
+    uint32_t const count = _count.at(phase);
+
+    // Notify when each phase begins
+    {
+      NotificationArg<PhaseBegin> arg;
+
+      arg.phase = phase;
+      arg.count = count;
+
+      notify(arg);
+    }
+
+    for (uint32_t n = 0; n < count; ++n)
+    {
+      std::chrono::milliseconds elapsed(0);
+
+      sess->prepare();
+
+      // Notify when each iteration begins
+      {
+        NotificationArg<IterationBegin> arg;
+
+        arg.index = n;
+
+        notify(arg);
+      };
+
+      nnfw::misc::benchmark::measure(elapsed) << [&](void) {
+        if (!sess->run())
+        {
+          throw std::runtime_error{"run failed"};
+        }
+      };
+
+      // Notify when each iteration ends
+      {
+        NotificationArg<IterationEnd> arg;
+
+        arg.latency = elapsed;
+
+        notify(arg);
+      };
+
+      sess->teardown();
+    }
+
+    // Notify when each phase ends
+    {
+      NotificationArg<PhaseEnd> arg;
+
+      notify(arg);
+    }
+  }
+}
+
+void BenchmarkRunner::notify(const NotificationArg<PhaseBegin> &arg) const
+{
+  if (_observer)
+  {
+    _observer->notify(arg);
+  }
+}
+
+void BenchmarkRunner::notify(const NotificationArg<PhaseEnd> &arg) const
+{
+  if (_observer)
+  {
+    _observer->notify(arg);
+  }
+}
+
+void BenchmarkRunner::notify(const NotificationArg<IterationBegin> &arg) const
+{
+  if (_observer)
+  {
+    _observer->notify(arg);
+  }
+}
+
+void BenchmarkRunner::notify(const NotificationArg<IterationEnd> &arg) const
+{
+  if (_observer)
+  {
+    _observer->notify(arg);
+  }
+}
+
+} // namespace mlapse
diff --git a/runtime/contrib/mlapse/tfl/mlapse/benchmark_runner.h b/runtime/contrib/mlapse/tfl/mlapse/benchmark_runner.h
new file mode 100644
index 000000000..fcbb41d1b
--- /dev/null
+++ b/runtime/contrib/mlapse/tfl/mlapse/benchmark_runner.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MLAPSE_BENCHMARK_RUNNER_H__
+#define __MLAPSE_BENCHMARK_RUNNER_H__
+
+#include "mlapse/benchmark_observer.h"
+
+#include <tflite/Session.h>
+
+#include <chrono>
+#include <map>
+
+namespace mlapse
+{
+
+class BenchmarkRunner final
+{
+public:
+  BenchmarkRunner(uint32_t warmup_count, uint32_t record_count)
+  {
+    _count[Warmup] = warmup_count;
+    _count[Record] = record_count;
+  }
+
+public:
+  void attach(BenchmarkObserver *observer);
+
+public:
+  void run(nnfw::tflite::Session *sess) const;
+
+public:
+  void run(const std::unique_ptr<nnfw::tflite::Session> &sess) const { run(sess.get()); }
+
+private:
+  void notify(const NotificationArg<PhaseBegin> &arg) const;
+  void notify(const NotificationArg<PhaseEnd> &arg) const;
+  void notify(const NotificationArg<IterationBegin> &arg) const;
+  void notify(const NotificationArg<IterationEnd> &arg) const;
+
+private:
+  std::map<Phase, uint32_t> _count;
+
+private:
+  BenchmarkObserver *_observer = nullptr;
+};
+
+} // namespace mlpase
+
+#endif // __MLAPSE_BENCHMARK_RUNNER_H__
diff --git a/runtime/contrib/mlapse/tfl/mlapse/multicast_observer.cc b/runtime/contrib/mlapse/tfl/mlapse/multicast_observer.cc
new file mode 100644
index 000000000..639acfe45
--- /dev/null
+++ b/runtime/contrib/mlapse/tfl/mlapse/multicast_observer.cc
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mlapse/multicast_observer.h"
diff --git a/runtime/contrib/mlapse/tfl/mlapse/multicast_observer.h b/runtime/contrib/mlapse/tfl/mlapse/multicast_observer.h
new file mode 100644
index 000000000..e4aac50a9
--- /dev/null
+++ b/runtime/contrib/mlapse/tfl/mlapse/multicast_observer.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MLAPSE_MULTICAST_OBSERER_H__
+#define __MLAPSE_MULTICAST_OBSERER_H__
+
+#include "mlapse/benchmark_observer.h"
+
+#include <memory>
+#include <vector>
+
+namespace mlapse
+{
+
+class MulticastObserver final : public BenchmarkObserver
+{
+public:
+  MulticastObserver() = default;
+
+public:
+  void append(std::unique_ptr<BenchmarkObserver> &&o) { _observers.emplace_back(std::move(o)); }
+
+public:
+  void notify(const NotificationArg<PhaseBegin> &arg) final
+  {
+    for (const auto &o : _observers)
+    {
+      o->notify(arg);
+    }
+  }
+
+  void notify(const NotificationArg<PhaseEnd> &arg) final
+  {
+    for (const auto &o : _observers)
+    {
+      o->notify(arg);
+    }
+  }
+
+  void notify(const NotificationArg<IterationBegin> &arg) final
+  {
+    for (const auto &o : _observers)
+    {
+      o->notify(arg);
+    }
+  }
+
+  void notify(const NotificationArg<IterationEnd> &arg) final
+  {
+    for (const auto &o : _observers)
+    {
+      o->notify(arg);
+    }
+  }
+
+private:
+  std::vector<std::unique_ptr<BenchmarkObserver>> _observers;
+};
+
+} // namespace mlapse
+
+#endif // __MLAPSE_MULTICAST_OBSERER_H__
diff --git a/runtime/contrib/mlapse/tfl/mlapse/tfl/load.cc b/runtime/contrib/mlapse/tfl/mlapse/tfl/load.cc
new file mode 100644
index 000000000..9e770aecf
--- /dev/null
+++ b/runtime/contrib/mlapse/tfl/mlapse/tfl/load.cc
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mlapse/tfl/load.h"
+
+#include <tflite/ext/kernels/register.h>
+
+namespace
+{
+
+tflite::StderrReporter error_reporter;
+
+} // namespace
+
+namespace mlapse
+{
+namespace tfl
+{
+
+std::unique_ptr<tflite::FlatBufferModel> load_model(const std::string &path)
+{
+  return tflite::FlatBufferModel::BuildFromFile(path.c_str(), &error_reporter);
+}
+
+std::unique_ptr<tflite::Interpreter> make_interpreter(const tflite::FlatBufferModel *model)
+{
+  // Let's use extended resolver!
+  nnfw::tflite::BuiltinOpResolver resolver;
+  tflite::InterpreterBuilder builder(*model, resolver);
+
+  std::unique_ptr<tflite::Interpreter> interpreter;
+
+  if (builder(&interpreter) != kTfLiteOk)
+  {
+    return nullptr;
+  }
+
+  return std::move(interpreter);
+}
+
+} // namespace tfl
+} // namespace mlapse
diff --git a/runtime/contrib/mlapse/tfl/mlapse/tfl/load.h b/runtime/contrib/mlapse/tfl/mlapse/tfl/load.h
new file mode 100644
index 000000000..6f5a8f1ea
--- /dev/null
+++ b/runtime/contrib/mlapse/tfl/mlapse/tfl/load.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MLAPSE_TFL_LOAD_H__
+#define __MLAPSE_TFL_LOAD_H__
+
+#include <tensorflow/lite/interpreter.h>
+#include <tensorflow/lite/model.h>
+
+#include <memory>
+
+namespace mlapse
+{
+namespace tfl
+{
+
+std::unique_ptr<tflite::FlatBufferModel> load_model(const std::string &path);
+
+// WARNING
+//
+//  model SHOULD outlive Interpreter
+std::unique_ptr<tflite::Interpreter> make_interpreter(const tflite::FlatBufferModel *model);
+
+} // namespace tfl
+} // namespace mlapse
+
+#endif // __MLAPSE_TFL_LOAD_H__
diff --git a/runtime/contrib/pure_arm_compute/CMakeLists.txt b/runtime/contrib/pure_arm_compute/CMakeLists.txt
new file mode 100644
index 000000000..f9cdfcba9
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/CMakeLists.txt
@@ -0,0 +1,29 @@
+if(NOT BUILD_PURE_ARM_COMPUTE)
+  return()
+endif(NOT BUILD_PURE_ARM_COMPUTE)
+
+nnas_find_package(ARMCompute REQUIRED)
+
+file(GLOB_RECURSE SOURCES "src/*.cc")
+
+add_library(nnapi_pure_arm_compute SHARED ${SOURCES})
+# To ignore compiler warnings from ARM Compute Library
+target_compile_options(nnapi_pure_arm_compute PRIVATE -Wno-ignored-attributes)
+target_include_directories(nnapi_pure_arm_compute PUBLIC src)
+if(BUILD_TFLITE_BENCHMARK_MODEL)
+  target_compile_definitions(nnapi_pure_arm_compute PUBLIC "TFLITE_PROFILING_ENABLED")
+endif()
+target_link_libraries(nnapi_pure_arm_compute nnfw-nnapi-header)
+target_link_libraries(nnapi_pure_arm_compute arm_compute arm_compute_ex)
+target_link_libraries(nnapi_pure_arm_compute nnfw_lib_cpp14 nnfw_lib_misc nnfw_lib_profiling)
+
+if(ANDROID)
+  target_link_libraries(nnapi_pure_arm_compute log)
+endif()
+
+set_target_properties(nnapi_pure_arm_compute PROPERTIES OUTPUT_NAME neuralnetworks)
+install(TARGETS nnapi_pure_arm_compute DESTINATION lib/pureacl RENAME neuralnetworks)
+
+# To prevent undefined references
+add_executable(pure_arm_compute_symbolcheck symbolcheck.cpp)
+target_link_libraries(pure_arm_compute_symbolcheck nnapi_pure_arm_compute)
diff --git a/runtime/contrib/pure_arm_compute/src/compilation.cc b/runtime/contrib/pure_arm_compute/src/compilation.cc
new file mode 100644
index 000000000..8cc86ebae
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/compilation.cc
@@ -0,0 +1,6434 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     compilation.cc
+ * @brief    This file contains ANeuralNetworksCompilation APIs and related classes
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#include <NeuralNetworks.h>
+
+// For CLKernelLibraryEx initialization
+#include "arm_compute/core/CL/CLHelpers.h"
+#include "arm_compute/core/CL/CLKernelLibrary.h"
+#include "arm_compute/core/CL/CLKernelLibraryEx.h"
+
+#include <arm_compute/runtime/IFunction.h>
+#include <arm_compute/runtime/CL/CLScheduler.h>
+#include <arm_compute/runtime/CL/CLSubTensor.h>
+#include <arm_compute/runtime/CL/CLFunctions.h>   // Include all ARM Compute CL functions
+#include <arm_compute/runtime/CL/CLFunctionsEx.h> // Include all ARM Compute EX CL functions
+
+#include <arm_compute/runtime/SubTensor.h>
+#include <arm_compute/runtime/NEON/NEFunctions.h>   // Include all ARM Compute NEON functions
+#include <arm_compute/runtime/NEON/NEFunctionsEx.h> // Include all ARM Compute EX NEON functions
+
+#include "internal/arm_compute.h"
+#include "internal/arm_compute/Cast.h"
+#include "internal/arm_compute/matrix/View.h"
+#include "internal/arm_compute/kernel/View.h"
+#include "internal/nnapi/matrix/Reader.h"
+#include "internal/nnapi/kernel/Reader.h"
+#include "internal/nnapi/feature/Reader.h"
+#include "internal/nnapi/feature/View.h"
+#include "internal/nnapi/tensor/Reader.h"
+#include "internal/arm_compute/feature/View.h"
+#include "internal/arm_compute/tensor/View.h"
+
+#include <arm_compute/runtime/misc/functions/GenericReshapeLayer.h>
+#include <arm_compute/runtime/misc/functions/GenericGather.h>
+
+#include "misc/matrix/IndexIterator.h"
+#include "misc/kernel/IndexIterator.h"
+#include "misc/feature/IndexIterator.h"
+#include "misc/tensor/IndexIterator.h"
+
+#include <cpp14/memory.h>
+
+#include "compilation.h"
+#include "model.h"
+#include "logging.h"
+
+using namespace arm_compute::misc;
+
+template <typename T> T from_env(const char *);
+
+template <> bool from_env(const char *s)
+{
+  if (s == nullptr)
+  {
+    return false;
+  }
+
+  return std::stoi(s) != 0;
+}
+
+const char *to_string(const PaddingCode &code)
+{
+  assert((ANEURALNETWORKS_PADDING_SAME == code) || (ANEURALNETWORKS_PADDING_VALID == code));
+
+  switch (code)
+  {
+    case ANEURALNETWORKS_PADDING_SAME:
+      return "ANEURALNETWORKS_PADDING_SAME";
+    case ANEURALNETWORKS_PADDING_VALID:
+      return "ANEURALNETWORKS_PADDING_VALID";
+  }
+
+  return nullptr;
+}
+
+struct Padding
+{
+  uint32_t top;
+  uint32_t bottom;
+  uint32_t left;
+  uint32_t right;
+};
+
+struct Stride
+{
+  uint32_t vertical;
+  uint32_t horizontal;
+};
+
+Padding valid_padding(void)
+{
+  //
+  // ANEURALNETWORKS_PADDING_VALID
+  //
+  // VALID padding. No padding.
+  //
+  // When the input size is not evenly divisible by the filter size,
+  // the input at the end that could not fill the whole filter tile
+  // will simply be ignored.
+  //
+  Padding padding;
+
+  padding.top = 0;
+  padding.bottom = 0;
+  padding.left = 0;
+  padding.right = 0;
+
+  return padding;
+}
+
+Padding same_padding(const nnfw::misc::feature::Shape &ifm_shape,
+                     const nnfw::misc::feature::Shape &ofm_shape, const Stride &stride, uint32_t kw,
+                     uint32_t kh)
+{
+  Padding padding;
+
+  // ANEURALNETWORKS_PADDING_SAME (from NNAPI spec)
+  //
+  // SAME padding. Padding on both ends are the "same":
+  //
+  // padding_to_beginning = total_padding / 2
+  // padding_to_end = (total_padding + 1)/2.
+  //
+  const int32_t vertical_needed_input = (ofm_shape.H - 1) * stride.vertical + kh;
+  const int32_t vertical_total_padding = std::max(0, vertical_needed_input - ifm_shape.H);
+
+  const int32_t horizontal_needed_input = (ofm_shape.W - 1) * stride.horizontal + kw;
+  const int32_t horizontal_total_padding = std::max(0, horizontal_needed_input - ifm_shape.W);
+
+  padding.top = vertical_total_padding / 2;
+  padding.bottom = (vertical_total_padding + 1) / 2;
+  padding.left = horizontal_total_padding / 2;
+  padding.right = (horizontal_total_padding + 1) / 2;
+
+  return padding;
+}
+
+::arm_compute::PadStrideInfo asPadStrideInfo(const Padding &padding, const Stride &stride)
+{
+  return ::arm_compute::PadStrideInfo{stride.horizontal,
+                                      stride.vertical,
+                                      padding.left,
+                                      padding.right,
+                                      padding.top,
+                                      padding.bottom,
+                                      ::arm_compute::DimensionRoundingType::FLOOR};
+}
+
+::arm_compute::ActivationLayerInfo asActInfo(FuseCode act)
+{
+  if (act == ANEURALNETWORKS_FUSED_NONE)
+  {
+    return ::arm_compute::ActivationLayerInfo();
+  }
+  else if (act == ANEURALNETWORKS_FUSED_RELU)
+  {
+    return ::arm_compute::ActivationLayerInfo(
+        ::arm_compute::ActivationLayerInfo::ActivationFunction::RELU);
+  }
+  else if (act == ANEURALNETWORKS_FUSED_RELU1)
+  {
+    return ::arm_compute::ActivationLayerInfo(
+        ::arm_compute::ActivationLayerInfo::ActivationFunction::LU_BOUNDED_RELU, 1.0f, -1.0f);
+  }
+  else if (act == ANEURALNETWORKS_FUSED_RELU6)
+  {
+    return ::arm_compute::ActivationLayerInfo(
+        ::arm_compute::ActivationLayerInfo::ActivationFunction::LU_BOUNDED_RELU, 6.0f, 0.0f);
+  }
+  else
+  {
+    throw std::runtime_error("Not supported, yet");
+  }
+}
+
+struct IAllocationContext
+{
+  virtual ~IAllocationContext() = default;
+
+  virtual ::arm_compute::ITensor *at(const ::internal::tflite::operand::Index &ind) const = 0;
+};
+
+#include "internal/IExecutionBuilder.h"
+
+using Initializer = std::function<void(::arm_compute::ITensor &)>;
+using Stage = std::function<void(const IAllocationContext &, IExecutionBuilder &)>;
+
+using namespace std::placeholders;
+
+template <typename T>
+static void initFeatureTensor(::arm_compute::ITensor &tensor,
+                              const nnfw::misc::feature::Shape &feature_shape,
+                              const uint8_t *feature_base, const size_t feature_size)
+{
+  const ::internal::nnapi::feature::Reader<T> from{
+      feature_shape, reinterpret_cast<const T *>(feature_base), feature_size};
+  ::internal::arm_compute::feature::View<T> into{&tensor};
+
+  ::nnfw::misc::feature::iterate(feature_shape)
+      << [&](uint32_t batch, uint32_t ch, uint32_t row, uint32_t col) {
+           const auto value = from.at(batch, ch, row, col);
+           into.at(batch, ch, row, col) = value;
+         };
+}
+
+template <typename T>
+static void initVectorTensor(::arm_compute::ITensor &tensor, const uint8_t *vec_base,
+                             const size_t vec_size)
+{
+  for (uint32_t n = 0; n < vec_size; ++n)
+  {
+    const ::arm_compute::Coordinates coordinate{n};
+
+    T *into = reinterpret_cast<T *>(tensor.ptr_to_element(coordinate));
+
+    const T *from = reinterpret_cast<const T *>(vec_base) + n;
+    const auto value = *from;
+
+    *into = value;
+  }
+}
+
+template <typename T>
+static void initTensor3D(::arm_compute::ITensor &tensor,
+                         const nnfw::misc::tensor::Shape &tensor_shape, const uint8_t *tensor_base,
+                         const size_t tensor_size)
+{
+  const ::internal::nnapi::tensor::Reader<T> from{
+      tensor_shape, reinterpret_cast<const T *>(tensor_base), tensor_size};
+  ::internal::arm_compute::tensor::View<T> into{&tensor};
+
+  ::nnfw::misc::tensor::iterate(tensor_shape) << [&](const nnfw::misc::tensor::Index &index_nnapi) {
+    ::nnfw::misc::tensor::Index index_ACL = ::nnfw::misc::tensor::copy_reverse(index_nnapi);
+    into.at(index_ACL) = from.at(index_nnapi);
+  };
+}
+
+template <typename T>
+static void initMatrixTensor(::arm_compute::ITensor &tensor,
+                             const nnfw::misc::matrix::Shape &matrix_shape,
+                             const uint8_t *matrix_base, const size_t matrix_size)
+{
+  const ::internal::nnapi::matrix::Reader<T> from{
+      matrix_shape, reinterpret_cast<const T *>(matrix_base), matrix_size};
+  ::internal::arm_compute::matrix::View<T> into{&tensor};
+
+  ::nnfw::misc::matrix::iterate(matrix_shape) << [&](uint32_t row, uint32_t col) {
+    const auto value = from.at(row, col);
+    into.at(row, col) = value;
+  };
+}
+
+template <typename T>
+static void initReorderVectorTensor(::arm_compute::ITensor &tensor, const uint8_t *vec_base,
+                                    const size_t vec_size)
+{
+  for (uint32_t n = 0; n < vec_size; ++n)
+  {
+    const ::arm_compute::Coordinates coordinate{ToARMComputeAxis(vec_size, n).value()};
+
+    T *into = reinterpret_cast<T *>(tensor.ptr_to_element(coordinate));
+
+    const T *from = reinterpret_cast<const T *>(vec_base) + n;
+    const auto value = *from;
+
+    *into = value;
+  }
+}
+
+template <typename T>
+static void initKernelTensor(::arm_compute::ITensor &tensor,
+                             const nnfw::misc::kernel::Shape &kernel_shape,
+                             const uint8_t *kernel_base, const size_t kernel_size)
+{
+  const ::internal::nnapi::kernel::Reader<T> from{
+      kernel_shape, reinterpret_cast<const T *>(kernel_base), kernel_size};
+  ::internal::arm_compute::kernel::View<T> into{&tensor};
+
+  ::nnfw::misc::kernel::iterate(kernel_shape)
+      << [&](uint32_t nth, uint32_t ch, uint32_t row, uint32_t col) {
+           const auto value = from.at(nth, ch, row, col);
+           into.at(nth, ch, row, col) = value;
+         };
+}
+
+/**
+ * @brief Structure to provide interface methods of compilation plan builder
+ */
+struct IPlanBuilder
+{
+  /**
+   * @brief  Destruct IPlanBuilder object using default destructor
+   */
+  virtual ~IPlanBuilder() = default;
+
+  /**
+   * @brief  Add TensorInfo with Shape Constraints
+   * @param [in] ind   Index of operand
+   * @param [in] info  TensorInfo value to set to index of operand
+   * @return  N/A
+   */
+  virtual void addShapeConstr(const ::internal::tflite::operand::Index &ind,
+                              const ::arm_compute::TensorInfo &info) = 0;
+  /**
+   * @brief  Add Subsumption constraints
+   * @param [in] ind  Index of operand
+   * @param [in] base  Index of base operand of Subsumption
+   * @param [in] offset  Offset of Subsumption
+   * @param [in] shape  Shape of Subsumption
+   * @param [in] extend_parent  extend_parent value of Subsumption
+   * @return  N/A
+   */
+  virtual void addSubsumptionConstr(const ::internal::tflite::operand::Index &ind,
+                                    const ::internal::tflite::operand::Index &base,
+                                    const ::arm_compute::Coordinates &offset,
+                                    const ::arm_compute::TensorShape &shape,
+                                    bool extend_parent = false) = 0;
+  /**
+   * @brief  Add Initializer lambda with ITensor param
+   * @param [in] ind  Index of operand
+   * @param [in] initializer  Initializer to add
+   * @return  N/A
+   */
+  virtual void addInitializer(const ::internal::tflite::operand::Index &ind,
+                              const Initializer &initializer) = 0;
+  /**
+   * @brief  Add Stage lambda with IAllocationContext and IExecutionBuilder params
+   * @param [in] stage Stage to add
+   * @return  N/A
+   */
+  virtual void addStage(const Stage &stage) = 0;
+};
+
+//
+// ActivationBuilder
+//
+class ActivationBuilder
+{
+public:
+  ActivationBuilder(IExecutionBuilder &builder) : _builder(builder)
+  {
+    // DO NOTHING
+  }
+
+private:
+  void appendReLU(::arm_compute::ITensor *tensor);
+  void appendReLU6(::arm_compute::ITensor *tensor);
+  void appendReLU1(::arm_compute::ITensor *tensor);
+
+public:
+  void append(FuseCode code, ::arm_compute::ITensor *tensor);
+
+private:
+  IExecutionBuilder &_builder;
+};
+
+void ActivationBuilder::appendReLU(::arm_compute::ITensor *ifm_alloc)
+{
+  const ::arm_compute::ActivationLayerInfo act_info{
+      ::arm_compute::ActivationLayerInfo::ActivationFunction::RELU};
+
+  if (::internal::arm_compute::isGpuMode())
+  {
+    auto fn = nnfw::cpp14::make_unique<::arm_compute::CLActivationLayer>();
+
+    fn->configure(CAST_CL(ifm_alloc), nullptr, act_info);
+
+    _builder.append("ReLU", std::move(fn));
+  }
+  else
+  {
+    auto fn = nnfw::cpp14::make_unique<::arm_compute::NEActivationLayer>();
+
+    fn->configure(ifm_alloc, nullptr, act_info);
+
+    _builder.append("ReLU", std::move(fn));
+  }
+}
+
+void ActivationBuilder::appendReLU1(::arm_compute::ITensor *ifm_alloc)
+{
+  const ::arm_compute::ActivationLayerInfo act_info{
+      ::arm_compute::ActivationLayerInfo::ActivationFunction::LU_BOUNDED_RELU, 1.0f, -1.0f};
+
+  if (::internal::arm_compute::isGpuMode())
+  {
+    auto fn = nnfw::cpp14::make_unique<::arm_compute::CLActivationLayer>();
+
+    fn->configure(CAST_CL(ifm_alloc), nullptr, act_info);
+
+    _builder.append("ReLU1", std::move(fn));
+  }
+  else
+  {
+    auto fn = nnfw::cpp14::make_unique<::arm_compute::NEActivationLayer>();
+
+    fn->configure(ifm_alloc, nullptr, act_info);
+
+    _builder.append("ReLU1", std::move(fn));
+  }
+}
+
+void ActivationBuilder::appendReLU6(::arm_compute::ITensor *ifm_alloc)
+{
+  const ::arm_compute::ActivationLayerInfo act_info{
+      ::arm_compute::ActivationLayerInfo::ActivationFunction::LU_BOUNDED_RELU, 6.0f, 0.0f};
+
+  if (::internal::arm_compute::isGpuMode())
+  {
+    auto fn = nnfw::cpp14::make_unique<::arm_compute::CLActivationLayer>();
+
+    fn->configure(CAST_CL(ifm_alloc), nullptr, act_info);
+
+    _builder.append("ReLU6", std::move(fn));
+  }
+  else
+  {
+    auto fn = nnfw::cpp14::make_unique<::arm_compute::NEActivationLayer>();
+
+    fn->configure(ifm_alloc, nullptr, act_info);
+
+    _builder.append("ReLU6", std::move(fn));
+  }
+}
+
+void ActivationBuilder::append(FuseCode code, ::arm_compute::ITensor *ifm_alloc)
+{
+  switch (code)
+  {
+    case ANEURALNETWORKS_FUSED_NONE:
+    {
+      // DO NOTHING
+      break;
+    }
+    case ANEURALNETWORKS_FUSED_RELU:
+    {
+      appendReLU(ifm_alloc);
+      break;
+    }
+    case ANEURALNETWORKS_FUSED_RELU1:
+    {
+      appendReLU1(ifm_alloc);
+      break;
+    }
+    case ANEURALNETWORKS_FUSED_RELU6:
+    {
+      appendReLU6(ifm_alloc);
+      break;
+    }
+    default:
+    {
+      throw std::runtime_error("Not supported, yet");
+    }
+  }
+}
+
+class Planner : public ::internal::tflite::op::NodeVisitor
+{
+public:
+  Planner(const ::internal::tflite::operand::Set &ctx, IPlanBuilder &builder)
+      : _ctx{ctx}, _builder{builder}
+  {
+    // DO NOTHING
+  }
+
+public:
+  void visit(const ::internal::tflite::op::Add::Node &node) override;
+  void visit(const ::internal::tflite::op::Sub::Node &node) override;
+  void visit(const ::internal::tflite::op::Mul::Node &node) override;
+  void visit(const ::internal::tflite::op::Div::Node &node) override;
+  void visit(const ::internal::tflite::op::Conv2D::Implicit::Node &node) override;
+  void visit(const ::internal::tflite::op::Conv2D::Explicit::Node &node) override;
+  void visit(const ::internal::tflite::op::DepthwiseConv2D::Implicit::Node &node) override;
+  void visit(const ::internal::tflite::op::DepthwiseConv2D::Explicit::Node &node) override;
+  void visit(const ::internal::tflite::op::Dequantize::Node &node) override;
+  void visit(const ::internal::tflite::op::MaxPool2D::Implicit::Node &node) override;
+  void visit(const ::internal::tflite::op::MaxPool2D::Explicit::Node &node) override;
+  void visit(const ::internal::tflite::op::AvgPool2D::Implicit::Node &node) override;
+  void visit(const ::internal::tflite::op::AvgPool2D::Explicit::Node &node) override;
+  void visit(const ::internal::tflite::op::Concat::Node &node) override;
+  void visit(const ::internal::tflite::op::FullyConnected::Node &node) override;
+  void visit(const ::internal::tflite::op::ResizeBilinear::Node &node) override;
+  void visit(const ::internal::tflite::op::Reshape::Node &node) override;
+  void visit(const ::internal::tflite::op::Squeeze::Node &node) override;
+  void visit(const ::internal::tflite::op::Softmax::Node &node) override;
+  void visit(const ::internal::tflite::op::StridedSlice::Node &node) override;
+  void visit(const ::internal::tflite::op::ReduceMax::Node &node) override;
+  void visit(const ::internal::tflite::op::ReduceMin::Node &node) override;
+  void visit(const ::internal::tflite::op::Cast::Node &node) override;
+  void visit(const ::internal::tflite::op::TopKV2::Node &node) override;
+  void visit(const ::internal::tflite::op::Gather::Node &node) override;
+  void visit(const ::internal::tflite::op::PReLU::Node &node) override;
+  void visit(const ::internal::tflite::op::ReLU::Node &node) override;
+  void visit(const ::internal::tflite::op::ReLU1::Node &node) override;
+  void visit(const ::internal::tflite::op::ReLU6::Node &node) override;
+  void visit(const ::internal::tflite::op::Tanh::Node &node) override;
+  void visit(const ::internal::tflite::op::Logistic::Node &node) override;
+  void visit(const ::internal::tflite::op::Mean::Node &node) override;
+  void visit(const ::internal::tflite::op::RNN::Node &node) override;
+  void visit(const ::internal::tflite::op::Transpose::Node &node) override;
+  void visit(const ::internal::tflite::op::LSTM::Node &node) override;
+  void visit(const ::internal::tflite::op::Floor::Node &node) override;
+  void visit(const ::internal::tflite::op::Split::Node &node) override;
+  void visit(const ::internal::tflite::op::ArgMax::Node &node) override;
+  void visit(const ::internal::tflite::op::RSQRT::Node &node) override;
+  void visit(const ::internal::tflite::op::SQRT::Node &node) override;
+  void visit(const ::internal::tflite::op::Pad::Node &node) override;
+  void visit(const ::internal::tflite::op::SpaceToDepth::Node &node) override;
+  void visit(const ::internal::tflite::op::SpaceToBatchND::Node &node) override;
+  void visit(const ::internal::tflite::op::BatchToSpaceNd::Node &node) override;
+  void visit(const ::internal::tflite::op::L2Pool2D::Implicit::Node &node) override;
+  void visit(const ::internal::tflite::op::L2Pool2D::Explicit::Node &node) override;
+  void visit(const ::internal::tflite::op::EmbeddingLookup::Node &node) override;
+  void visit(const ::internal::tflite::op::HashtableLookup::Node &node) override;
+  void visit(const ::internal::tflite::op::L2Normalization::Node &node) override;
+  void visit(const ::internal::tflite::op::SquaredDifference::Node &node) override;
+  void visit(const ::internal::tflite::op::LocalResponseNormalization::Node &node) override;
+  void visit(const ::internal::tflite::op::DepthToSpace::Node &node) override;
+  void visit(const ::internal::tflite::op::Unpack::Node &node) override;
+  void visit(const ::internal::tflite::op::Neg::Node &node) override;
+  void visit(const ::internal::tflite::op::Exp::Node &node) override;
+  void visit(const ::internal::tflite::op::ReduceSum::Node &node) override;
+  void visit(const ::internal::tflite::op::Equal::Node &node) override;
+  void visit(const ::internal::tflite::op::TransposeConv::Node &node) override;
+  void visit(const ::internal::tflite::op::Pack::Node &node) override;
+  void visit(const ::internal::tflite::op::Abs::Node &node) override;
+  void visit(const ::internal::tflite::op::NotEqual::Node &node) override;
+  void visit(const ::internal::tflite::op::LogicalAnd::Node &node) override;
+  void visit(const ::internal::tflite::op::LogicalNot::Node &node) override;
+  void visit(const ::internal::tflite::op::LogicalOr::Node &node) override;
+
+private:
+  const ::internal::tflite::operand::Set &_ctx;
+  IPlanBuilder &_builder;
+};
+
+void Planner::visit(const ::internal::tflite::op::Add::Node &node)
+{
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+  const ::internal::tflite::operand::Index lhs_index{node.param().lhs_index};
+  const ::internal::tflite::operand::Index rhs_index{node.param().rhs_index};
+  const ::internal::tflite::operand::Index activation_index{node.param().activation_index};
+
+  // TODO Should move to the place where the operand is handled, if it is possible.
+  // Set Shape Constraints and TensorInfo
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+
+  if (!(_ctx.at(lhs_index).shape() == _ctx.at(rhs_index).shape()))
+  {
+    const auto broadcast_rank =
+        std::max(_ctx.at(lhs_index).shape().rank(), _ctx.at(rhs_index).shape().rank());
+    const_cast<::internal::tflite::operand::Shape &>(_ctx.at(lhs_index).shape())
+        .extendRank(broadcast_rank);
+    const_cast<::internal::tflite::operand::Shape &>(_ctx.at(rhs_index).shape())
+        .extendRank(broadcast_rank);
+  }
+  _builder.addShapeConstr(
+      lhs_index, asTensorInfo(asTensorShape(_ctx.at(lhs_index).shape()), _ctx.at(lhs_index).type(),
+                              _ctx.at(lhs_index).scale(), _ctx.at(lhs_index).zeroPoint()));
+  _builder.addShapeConstr(
+      rhs_index, asTensorInfo(asTensorShape(_ctx.at(rhs_index).shape()), _ctx.at(rhs_index).type(),
+                              _ctx.at(rhs_index).scale(), _ctx.at(rhs_index).zeroPoint()));
+
+  // Construct operation parameters
+  struct Param
+  {
+    int ofm_index;
+    int lhs_index;
+    int rhs_index;
+
+    FuseCode activation;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.lhs_index = lhs_index.asInt();
+  param.rhs_index = rhs_index.asInt();
+
+  param.activation = static_cast<FuseCode>(_ctx.at(activation_index).asScalar<int32_t>());
+
+  const auto lhs_shape = _ctx.at(lhs_index).shape();
+  const auto rhs_shape = _ctx.at(rhs_index).shape();
+  auto stage = [param, lhs_shape, rhs_shape](const IAllocationContext &ctx,
+                                             IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto lhs_alloc = ctx.at(::internal::tflite::operand::Index{param.lhs_index});
+    auto rhs_alloc = ctx.at(::internal::tflite::operand::Index{param.rhs_index});
+
+    std::unique_ptr<::arm_compute::IFunction> fn;
+
+    {
+      if (::internal::arm_compute::isGpuMode())
+      {
+        auto l = nnfw::cpp14::make_unique<::arm_compute::CLArithmeticAddition>();
+
+        // TODO Decide ConvertPolicy (WARP? SATURATE?) according to NN API specification
+        l->configure(CAST_CL(lhs_alloc), CAST_CL(rhs_alloc), CAST_CL(ofm_alloc),
+                     ::arm_compute::ConvertPolicy::SATURATE);
+
+        fn = std::move(l);
+      }
+      else // NEON
+      {
+        auto l = nnfw::cpp14::make_unique<::arm_compute::NEArithmeticAddition>();
+
+        // TODO Decide ConvertPolicy (WARP? SATURATE?) according to NN API specification
+        l->configure(lhs_alloc, rhs_alloc, ofm_alloc, ::arm_compute::ConvertPolicy::SATURATE);
+
+        fn = std::move(l);
+      }
+    }
+
+    builder.append("Add", std::move(fn));
+
+    ActivationBuilder{builder}.append(param.activation, ofm_alloc);
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::Sub::Node &node)
+{
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+  const ::internal::tflite::operand::Index lhs_index{node.param().lhs_index};
+  const ::internal::tflite::operand::Index rhs_index{node.param().rhs_index};
+  const ::internal::tflite::operand::Index activation_index{node.param().activation_index};
+
+  // Set Shape Constraints and TensorInfo
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+
+  if (!(_ctx.at(lhs_index).shape() == _ctx.at(rhs_index).shape()))
+  {
+    const auto broadcast_rank =
+        std::max(_ctx.at(lhs_index).shape().rank(), _ctx.at(rhs_index).shape().rank());
+    const_cast<::internal::tflite::operand::Shape &>(_ctx.at(lhs_index).shape())
+        .extendRank(broadcast_rank);
+    const_cast<::internal::tflite::operand::Shape &>(_ctx.at(rhs_index).shape())
+        .extendRank(broadcast_rank);
+  }
+  _builder.addShapeConstr(
+      lhs_index, asTensorInfo(asTensorShape(_ctx.at(lhs_index).shape()), _ctx.at(lhs_index).type(),
+                              _ctx.at(lhs_index).scale(), _ctx.at(lhs_index).zeroPoint()));
+  _builder.addShapeConstr(
+      rhs_index, asTensorInfo(asTensorShape(_ctx.at(rhs_index).shape()), _ctx.at(rhs_index).type(),
+                              _ctx.at(rhs_index).scale(), _ctx.at(rhs_index).zeroPoint()));
+
+  // Construct operation parameters
+  struct Param
+  {
+    int ofm_index;
+    int lhs_index;
+    int rhs_index;
+
+    FuseCode activation;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.lhs_index = lhs_index.asInt();
+  param.rhs_index = rhs_index.asInt();
+
+  param.activation = static_cast<FuseCode>(_ctx.at(activation_index).asScalar<int32_t>());
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto lhs_alloc = ctx.at(::internal::tflite::operand::Index{param.lhs_index});
+    auto rhs_alloc = ctx.at(::internal::tflite::operand::Index{param.rhs_index});
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLArithmeticSubtraction>();
+
+      // TODO Decide ConvertPolicy (WARP? SATURATE?) according to NN API specification
+      fn->configure(CAST_CL(lhs_alloc), CAST_CL(rhs_alloc), CAST_CL(ofm_alloc),
+                    ::arm_compute::ConvertPolicy::SATURATE);
+
+      builder.append("Sub", std::move(fn));
+    }
+    else // NEON
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::NEArithmeticSubtraction>();
+
+      // TODO Decide ConvertPolicy (WARP? SATURATE?) according to NN API specification
+      fn->configure(lhs_alloc, rhs_alloc, ofm_alloc, ::arm_compute::ConvertPolicy::SATURATE);
+
+      builder.append("Sub", std::move(fn));
+    }
+
+    ActivationBuilder{builder}.append(param.activation, ofm_alloc);
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::Mul::Node &node)
+{
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+  const ::internal::tflite::operand::Index lhs_index{node.param().lhs_index};
+  const ::internal::tflite::operand::Index rhs_index{node.param().rhs_index};
+  const ::internal::tflite::operand::Index activation_index{node.param().activation_index};
+
+  if (_ctx.at(ofm_index).scale() > 0)
+  {
+    assert(_ctx.at(ofm_index).scale() > _ctx.at(lhs_index).scale() * _ctx.at(rhs_index).scale());
+  }
+  // Set Shape Constraints and TensorInfo
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+
+  if (!(_ctx.at(lhs_index).shape() == _ctx.at(rhs_index).shape()))
+  {
+    const auto broadcast_rank =
+        std::max(_ctx.at(lhs_index).shape().rank(), _ctx.at(rhs_index).shape().rank());
+    const_cast<::internal::tflite::operand::Shape &>(_ctx.at(lhs_index).shape())
+        .extendRank(broadcast_rank);
+    const_cast<::internal::tflite::operand::Shape &>(_ctx.at(rhs_index).shape())
+        .extendRank(broadcast_rank);
+  }
+  _builder.addShapeConstr(
+      lhs_index, asTensorInfo(asTensorShape(_ctx.at(lhs_index).shape()), _ctx.at(lhs_index).type(),
+                              _ctx.at(lhs_index).scale(), _ctx.at(lhs_index).zeroPoint()));
+  _builder.addShapeConstr(
+      rhs_index, asTensorInfo(asTensorShape(_ctx.at(rhs_index).shape()), _ctx.at(rhs_index).type(),
+                              _ctx.at(rhs_index).scale(), _ctx.at(rhs_index).zeroPoint()));
+
+  struct Param
+  {
+    int ofm_index;
+    int lhs_index;
+    int rhs_index;
+
+    FuseCode activation;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.lhs_index = lhs_index.asInt();
+  param.rhs_index = rhs_index.asInt();
+
+  param.activation = static_cast<FuseCode>(_ctx.at(activation_index).asScalar<int32_t>());
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+
+    auto output_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto lhs_input_alloc = ctx.at(::internal::tflite::operand::Index{param.lhs_index});
+    auto rhs_input_alloc = ctx.at(::internal::tflite::operand::Index{param.rhs_index});
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLPixelWiseMultiplication>();
+
+      fn->configure(CAST_CL(lhs_input_alloc), CAST_CL(rhs_input_alloc), CAST_CL(output_alloc),
+                    1.0, // scale
+                    arm_compute::ConvertPolicy::SATURATE,
+                    arm_compute::RoundingPolicy::TO_NEAREST_EVEN);
+
+      builder.append("Mul", std::move(fn));
+    }
+    else // NEON
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::NEPixelWiseMultiplication>();
+
+      fn->configure(lhs_input_alloc, rhs_input_alloc, output_alloc,
+                    1.0, // scale
+                    arm_compute::ConvertPolicy::SATURATE, arm_compute::RoundingPolicy::TO_ZERO);
+
+      builder.append("Mul", std::move(fn));
+    }
+
+    ActivationBuilder{builder}.append(param.activation, output_alloc);
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::Div::Node &node)
+{
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+
+  const ::internal::tflite::operand::Index lhs_index{node.param().lhs_index};
+  const ::internal::tflite::operand::Index rhs_index{node.param().rhs_index};
+
+  const ::internal::tflite::operand::Index activation_index{node.param().activation_index};
+
+  // Set Shape Constraints and TensorInfo
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+
+  if (!(_ctx.at(lhs_index).shape() == _ctx.at(rhs_index).shape()))
+  {
+    const auto broadcast_rank =
+        std::max(_ctx.at(lhs_index).shape().rank(), _ctx.at(rhs_index).shape().rank());
+    const_cast<::internal::tflite::operand::Shape &>(_ctx.at(lhs_index).shape())
+        .extendRank(broadcast_rank);
+    const_cast<::internal::tflite::operand::Shape &>(_ctx.at(rhs_index).shape())
+        .extendRank(broadcast_rank);
+  }
+
+  _builder.addShapeConstr(
+      lhs_index, asTensorInfo(asTensorShape(_ctx.at(lhs_index).shape()), _ctx.at(lhs_index).type(),
+                              _ctx.at(lhs_index).scale(), _ctx.at(lhs_index).zeroPoint()));
+  _builder.addShapeConstr(
+      rhs_index, asTensorInfo(asTensorShape(_ctx.at(rhs_index).shape()), _ctx.at(rhs_index).type(),
+                              _ctx.at(rhs_index).scale(), _ctx.at(rhs_index).zeroPoint()));
+
+  // Construct operation parameters
+  struct Param
+  {
+    int ofm_index;
+    int lhs_index;
+    int rhs_index;
+
+    FuseCode activation;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.lhs_index = lhs_index.asInt();
+  param.rhs_index = rhs_index.asInt();
+
+  param.activation = static_cast<FuseCode>(_ctx.at(activation_index).asScalar<int32_t>());
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto lhs_alloc = ctx.at(::internal::tflite::operand::Index{param.lhs_index});
+    auto rhs_alloc = ctx.at(::internal::tflite::operand::Index{param.rhs_index});
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLArithmeticDivision>();
+
+      fn->configure(CAST_CL(lhs_alloc), CAST_CL(rhs_alloc), CAST_CL(ofm_alloc));
+
+      builder.append("Div", std::move(fn));
+    }
+    else
+      throw std::runtime_error("Not supported, yet");
+
+    ActivationBuilder{builder}.append(param.activation, ofm_alloc);
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::Conv2D::Implicit::Node &node)
+{
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+
+  const ::internal::tflite::operand::Index ifm_index{node.param().ifm_index};
+  const ::internal::tflite::operand::Index ker_index{node.param().ker_index};
+  const ::internal::tflite::operand::Index bias_index{node.param().bias_index};
+
+  const ::internal::tflite::operand::Index vstride_index{node.param().vstride_index};
+  const ::internal::tflite::operand::Index hstride_index{node.param().hstride_index};
+
+  const ::internal::tflite::operand::Index padding_index{node.param().padding_index};
+  const ::internal::tflite::operand::Index activation_index{node.param().activation_index};
+
+  const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature();
+  const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature();
+  const auto ker_shape = _ctx.at(ker_index).shape().asKernel();
+  const auto bias_size = _ctx.at(bias_index).shape().asVector();
+
+  const PaddingCode padding_type =
+      static_cast<PaddingCode>(_ctx.at(padding_index).asScalar<int32_t>());
+
+  Stride stride;
+
+  stride.vertical = _ctx.at(vstride_index).asScalar<int32_t>();
+  stride.horizontal = _ctx.at(hstride_index).asScalar<int32_t>();
+
+  assert((ANEURALNETWORKS_PADDING_SAME == padding_type) ||
+         (ANEURALNETWORKS_PADDING_VALID == padding_type));
+
+  // TODO Should move to the place where the operand is handled, if it is possible.
+  // Set Shape Constraints and TensorInfo
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+  _builder.addShapeConstr(
+      ifm_index, asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape()), _ctx.at(ifm_index).type(),
+                              _ctx.at(ifm_index).scale(), _ctx.at(ifm_index).zeroPoint()));
+  _builder.addShapeConstr(
+      ker_index, asTensorInfo(asTensorShape(_ctx.at(ker_index).shape()), _ctx.at(ker_index).type(),
+                              _ctx.at(ker_index).scale(), _ctx.at(ker_index).zeroPoint()));
+  _builder.addShapeConstr(bias_index,
+                          asTensorInfo(asTensorShape(_ctx.at(bias_index).shape()),
+                                       _ctx.at(bias_index).type(), _ctx.at(bias_index).scale(),
+                                       _ctx.at(bias_index).zeroPoint()));
+
+  // Set initializer for kernel
+  {
+    auto ker_base = _ctx.at(ker_index).data().base();
+    auto ker_size = _ctx.at(ker_index).data().size();
+    auto ker_type = _ctx.at(ker_index).type();
+
+    switch (ker_type)
+    {
+      case ANEURALNETWORKS_TENSOR_FLOAT32:
+      {
+        auto initializer = std::bind(initKernelTensor<float>, _1, ker_shape, ker_base, ker_size);
+        _builder.addInitializer(ker_index, initializer);
+        break;
+      }
+      case ANEURALNETWORKS_TENSOR_QUANT8_ASYMM:
+      {
+        auto initializer = std::bind(initKernelTensor<uint8_t>, _1, ker_shape, ker_base, ker_size);
+        _builder.addInitializer(ker_index, initializer);
+        break;
+      }
+      default:
+      {
+        throw std::runtime_error("Not supported");
+      }
+    }
+  }
+
+  // Set initializer for bias
+  {
+    auto bias_base = _ctx.at(bias_index).data().base();
+    auto bias_type = _ctx.at(bias_index).type();
+
+    switch (bias_type)
+    {
+      case ANEURALNETWORKS_TENSOR_FLOAT32:
+      {
+        auto initializer = std::bind(initVectorTensor<float>, _1, bias_base, bias_size);
+        _builder.addInitializer(bias_index, initializer);
+        break;
+      }
+      case ANEURALNETWORKS_TENSOR_INT32:
+      {
+        auto initializer = std::bind(initVectorTensor<int32_t>, _1, bias_base, bias_size);
+        _builder.addInitializer(bias_index, initializer);
+        break;
+      }
+      default:
+      {
+        throw std::runtime_error("Not supported");
+      }
+    }
+  }
+
+  // Construct operation parameters
+  struct Param
+  {
+    int ofm_index;
+    int ifm_index;
+    int ker_index;
+    int bias_index;
+
+    Padding padding;
+    Stride stride;
+
+    FuseCode activation;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.ifm_index = ifm_index.asInt();
+  param.ker_index = ker_index.asInt();
+  param.bias_index = bias_index.asInt();
+
+  param.stride = stride;
+  param.padding = (padding_type == ANEURALNETWORKS_PADDING_SAME)
+                      ? same_padding(ifm_shape, ofm_shape, stride, ker_shape.W, ker_shape.H)
+                      : valid_padding();
+
+  param.activation = static_cast<FuseCode>(_ctx.at(activation_index).asScalar<int32_t>());
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto ifm_alloc = ctx.at(::internal::tflite::operand::Index{param.ifm_index});
+    auto ker_alloc = ctx.at(::internal::tflite::operand::Index{param.ker_index});
+    auto bias_alloc = ctx.at(::internal::tflite::operand::Index{param.bias_index});
+
+    const auto conv_info = asPadStrideInfo(param.padding, param.stride);
+    const auto fused_act = asActInfo(param.activation);
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      std::unique_ptr<::arm_compute::CLConvolutionLayer> fn{new ::arm_compute::CLConvolutionLayer};
+
+      // To pass the fused_act parameter, it calls the WeightsInfo() and Size2D(1U, 1U) (dilation)
+      // functions like the default parameter.
+      fn->configure(CAST_CL(ifm_alloc), CAST_CL(ker_alloc), CAST_CL(bias_alloc), CAST_CL(ofm_alloc),
+                    conv_info, ::arm_compute::WeightsInfo(), ::arm_compute::Size2D(1U, 1U),
+                    fused_act);
+
+      builder.append("Conv2D", std::move(fn));
+    }
+    else
+    {
+      std::unique_ptr<::arm_compute::NEConvolutionLayer> fn{new ::arm_compute::NEConvolutionLayer};
+
+      // To pass the fused_act parameter, it calls the WeightsInfo() and Size2D(1U, 1U) (dilation)
+      // functions like the default parameter.
+      fn->configure(ifm_alloc, ker_alloc, bias_alloc, ofm_alloc, conv_info,
+                    ::arm_compute::WeightsInfo(), ::arm_compute::Size2D(1U, 1U), fused_act);
+
+      builder.append("Conv2D", std::move(fn));
+    }
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::Conv2D::Explicit::Node &node)
+{
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+
+  const ::internal::tflite::operand::Index ifm_index{node.param().ifm_index};
+  const ::internal::tflite::operand::Index ker_index{node.param().ker_index};
+  const ::internal::tflite::operand::Index bias_index{node.param().bias_index};
+
+  const ::internal::tflite::operand::Index vstride_index{node.param().vstride_index};
+  const ::internal::tflite::operand::Index hstride_index{node.param().hstride_index};
+
+  const ::internal::tflite::operand::Index padding_left_index{node.param().padding_left_index};
+  const ::internal::tflite::operand::Index padding_right_index{node.param().padding_right_index};
+  const ::internal::tflite::operand::Index padding_top_index{node.param().padding_top_index};
+  const ::internal::tflite::operand::Index padding_bottom_index{node.param().padding_bottom_index};
+
+  const ::internal::tflite::operand::Index activation_index{node.param().activation_index};
+
+  const int32_t padding_left = _ctx.at(padding_left_index).asScalar<int32_t>();
+  const int32_t padding_right = _ctx.at(padding_right_index).asScalar<int32_t>();
+  const int32_t padding_top = _ctx.at(padding_top_index).asScalar<int32_t>();
+  const int32_t padding_bottom = _ctx.at(padding_bottom_index).asScalar<int32_t>();
+
+  Stride stride;
+
+  stride.vertical = _ctx.at(vstride_index).asScalar<int32_t>();
+  stride.horizontal = _ctx.at(hstride_index).asScalar<int32_t>();
+
+  // TODO Should move to the place where the operand is handled, if it is possible.
+  // Set Shape Constraints and TensorInfo
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+  _builder.addShapeConstr(
+      ifm_index, asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape()), _ctx.at(ifm_index).type(),
+                              _ctx.at(ifm_index).scale(), _ctx.at(ifm_index).zeroPoint()));
+  _builder.addShapeConstr(
+      ker_index, asTensorInfo(asTensorShape(_ctx.at(ker_index).shape()), _ctx.at(ker_index).type(),
+                              _ctx.at(ker_index).scale(), _ctx.at(ker_index).zeroPoint()));
+  _builder.addShapeConstr(bias_index,
+                          asTensorInfo(asTensorShape(_ctx.at(bias_index).shape()),
+                                       _ctx.at(bias_index).type(), _ctx.at(bias_index).scale(),
+                                       _ctx.at(bias_index).zeroPoint()));
+
+  // Set initializer for kernel
+  // Workaround for https://github.sec.samsung.net/STAR/nnfw/issues/2319
+  if (_ctx.at(ker_index).hasData())
+  {
+    const auto ker_shape = _ctx.at(ker_index).shape().asKernel();
+    auto ker_base = _ctx.at(ker_index).data().base();
+    auto ker_size = _ctx.at(ker_index).data().size();
+    auto ker_type = _ctx.at(ker_index).type();
+
+    switch (ker_type)
+    {
+      case ANEURALNETWORKS_TENSOR_FLOAT32:
+      {
+        auto initializer = std::bind(initKernelTensor<float>, _1, ker_shape, ker_base, ker_size);
+        _builder.addInitializer(ker_index, initializer);
+        break;
+      }
+      case ANEURALNETWORKS_TENSOR_QUANT8_ASYMM:
+      {
+        auto initializer = std::bind(initKernelTensor<uint8_t>, _1, ker_shape, ker_base, ker_size);
+        _builder.addInitializer(ker_index, initializer);
+        break;
+      }
+      default:
+      {
+        throw std::runtime_error("Not supported");
+      }
+    }
+  }
+
+  // Set initializer for bias
+  // See above comment.
+  if (_ctx.at(bias_index).hasData())
+  {
+    const auto bias_size = _ctx.at(bias_index).shape().asVector();
+    auto bias_base = _ctx.at(bias_index).data().base();
+    auto bias_type = _ctx.at(bias_index).type();
+
+    switch (bias_type)
+    {
+      case ANEURALNETWORKS_TENSOR_FLOAT32:
+      {
+        auto initializer = std::bind(initVectorTensor<float>, _1, bias_base, bias_size);
+        _builder.addInitializer(bias_index, initializer);
+        break;
+      }
+      case ANEURALNETWORKS_TENSOR_INT32:
+      {
+        auto initializer = std::bind(initVectorTensor<int32_t>, _1, bias_base, bias_size);
+        _builder.addInitializer(bias_index, initializer);
+        break;
+      }
+      default:
+      {
+        throw std::runtime_error("Not supported");
+      }
+    }
+  }
+
+  // Construct operation parameters
+  struct Param
+  {
+    int ofm_index;
+    int ifm_index;
+    int ker_index;
+    int bias_index;
+
+    Padding padding;
+    Stride stride;
+
+    FuseCode activation;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.ifm_index = ifm_index.asInt();
+  param.ker_index = ker_index.asInt();
+  param.bias_index = bias_index.asInt();
+
+  param.stride = stride;
+
+  param.padding.left = padding_left;
+  param.padding.right = padding_right;
+  param.padding.top = padding_top;
+  param.padding.bottom = padding_bottom;
+
+  param.activation = static_cast<FuseCode>(_ctx.at(activation_index).asScalar<int32_t>());
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto ifm_alloc = ctx.at(::internal::tflite::operand::Index{param.ifm_index});
+    auto ker_alloc = ctx.at(::internal::tflite::operand::Index{param.ker_index});
+    auto bias_alloc = ctx.at(::internal::tflite::operand::Index{param.bias_index});
+
+    const auto conv_info = asPadStrideInfo(param.padding, param.stride);
+    const auto fused_act = asActInfo(param.activation);
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      std::unique_ptr<::arm_compute::CLConvolutionLayer> fn{new ::arm_compute::CLConvolutionLayer};
+
+      // To pass the fused_act parameter, it calls the WeightsInfo() and Size2D(1U, 1U) (dilation)
+      // functions like the default parameter.
+      fn->configure(CAST_CL(ifm_alloc), CAST_CL(ker_alloc), CAST_CL(bias_alloc), CAST_CL(ofm_alloc),
+                    conv_info, ::arm_compute::WeightsInfo(), ::arm_compute::Size2D(1U, 1U),
+                    fused_act);
+
+      builder.append("Conv2D", std::move(fn));
+    }
+    else
+    {
+      std::unique_ptr<::arm_compute::NEConvolutionLayer> fn{new ::arm_compute::NEConvolutionLayer};
+
+      // To pass the fused_act parameter, it calls the WeightsInfo() and Size2D(1U, 1U) (dilation)
+      // functions like the default parameter.
+      fn->configure(ifm_alloc, ker_alloc, bias_alloc, ofm_alloc, conv_info,
+                    ::arm_compute::WeightsInfo(), ::arm_compute::Size2D(1U, 1U), fused_act);
+
+      builder.append("Conv2D", std::move(fn));
+    }
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::DepthwiseConv2D::Implicit::Node &node)
+{
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+
+  const ::internal::tflite::operand::Index ifm_index{node.param().ifm_index};
+  const ::internal::tflite::operand::Index ker_index{node.param().ker_index};
+  const ::internal::tflite::operand::Index bias_index{node.param().bias_index};
+
+  const ::internal::tflite::operand::Index vstride_index{node.param().vstride_index};
+  const ::internal::tflite::operand::Index hstride_index{node.param().hstride_index};
+
+  const ::internal::tflite::operand::Index padding_index{node.param().padding_index};
+  const ::internal::tflite::operand::Index multiplier_index{node.param().multiplier_index};
+  const ::internal::tflite::operand::Index activation_index{node.param().activation_index};
+
+  const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature();
+
+  const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature();
+  const auto ker_shape = _ctx.at(ker_index).shape().asFeature();
+  const auto bias_size = _ctx.at(bias_index).shape().asVector();
+
+  auto multiplier = _ctx.at(multiplier_index).asScalar<int>();
+
+  assert(ker_shape.C == bias_size);
+  assert(ker_shape.C == ifm_shape.C * multiplier);
+
+  const PaddingCode padding_type =
+      static_cast<PaddingCode>(_ctx.at(padding_index).asScalar<int32_t>());
+
+  Stride stride;
+
+  stride.vertical = _ctx.at(vstride_index).asScalar<int32_t>();
+  stride.horizontal = _ctx.at(hstride_index).asScalar<int32_t>();
+
+  assert((ANEURALNETWORKS_PADDING_SAME == padding_type) ||
+         (ANEURALNETWORKS_PADDING_VALID == padding_type));
+
+  // TODO Should move to the place where the operand is handled, if it is possible.
+  // Set Shape Constraints and TensorInfo
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+  _builder.addShapeConstr(
+      ifm_index, asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape()), _ctx.at(ifm_index).type(),
+                              _ctx.at(ifm_index).scale(), _ctx.at(ifm_index).zeroPoint()));
+  // NOTE DepthwiseConv2D kernel is of shape [1, KER_W, KER_H, IFM_C * MULTIPLIER]
+  _builder.addShapeConstr(
+      ker_index, asTensorInfo(asTensorShape(_ctx.at(ker_index).shape()), _ctx.at(ker_index).type(),
+                              _ctx.at(ker_index).scale(), _ctx.at(ker_index).zeroPoint()));
+  _builder.addShapeConstr(bias_index,
+                          asTensorInfo(asTensorShape(_ctx.at(bias_index).shape()),
+                                       _ctx.at(bias_index).type(), _ctx.at(bias_index).scale(),
+                                       _ctx.at(bias_index).zeroPoint()));
+
+  // Construct operation parameters
+  struct Param
+  {
+    int ofm_index;
+    int ifm_index;
+    int ker_index;
+    int bias_index;
+
+    Padding padding;
+    Stride stride;
+
+    int multipler;
+    FuseCode activation;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.ifm_index = ifm_index.asInt();
+  param.ker_index = ker_index.asInt();
+  param.bias_index = bias_index.asInt();
+
+  param.stride = stride;
+  param.padding = (padding_type == ANEURALNETWORKS_PADDING_SAME)
+                      ? same_padding(ifm_shape, ofm_shape, stride, ker_shape.W, ker_shape.H)
+                      : valid_padding();
+
+  param.multipler = multiplier;
+  param.activation = static_cast<FuseCode>(_ctx.at(activation_index).asScalar<int32_t>());
+
+  VERBOSE(DepthwiseConv2D) << "OFM_C: " << ofm_shape.C << std::endl;
+  VERBOSE(DepthwiseConv2D) << "OFM_H: " << ofm_shape.H << std::endl;
+  VERBOSE(DepthwiseConv2D) << "OFM_W: " << ofm_shape.W << std::endl;
+
+  VERBOSE(DepthwiseConv2D) << "IFM_C: " << ifm_shape.C << std::endl;
+  VERBOSE(DepthwiseConv2D) << "IFM_H: " << ifm_shape.H << std::endl;
+  VERBOSE(DepthwiseConv2D) << "IFM_W: " << ifm_shape.W << std::endl;
+
+  VERBOSE(DepthwiseConv2D) << "KER_C: " << ker_shape.C << std::endl;
+  VERBOSE(DepthwiseConv2D) << "KER_H: " << ker_shape.H << std::endl;
+  VERBOSE(DepthwiseConv2D) << "KER_W: " << ker_shape.W << std::endl;
+
+  VERBOSE(DepthwiseConv2D) << "STRIDE_H: " << param.stride.vertical << std::endl;
+  VERBOSE(DepthwiseConv2D) << "STRIDE_W: " << param.stride.horizontal << std::endl;
+
+  VERBOSE(DepthwiseConv2D) << "ACTIVATION: " << param.activation << std::endl;
+
+  VERBOSE(DepthwiseConv2D) << "PAD(T): " << param.padding.top << std::endl;
+  VERBOSE(DepthwiseConv2D) << "PAD(B): " << param.padding.bottom << std::endl;
+  VERBOSE(DepthwiseConv2D) << "PAD(L): " << param.padding.left << std::endl;
+  VERBOSE(DepthwiseConv2D) << "PAD(R): " << param.padding.right << std::endl;
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto ifm_alloc = ctx.at(::internal::tflite::operand::Index{param.ifm_index});
+    auto ker_alloc = ctx.at(::internal::tflite::operand::Index{param.ker_index});
+    auto bias_alloc = ctx.at(::internal::tflite::operand::Index{param.bias_index});
+
+    const auto conv_info = asPadStrideInfo(param.padding, param.stride);
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLDepthwiseConvolutionLayer>();
+
+      fn->configure(CAST_CL(ifm_alloc), CAST_CL(ker_alloc), CAST_CL(bias_alloc), CAST_CL(ofm_alloc),
+                    conv_info, param.multipler);
+
+      builder.append("DepthwiseConv2D", std::move(fn));
+    }
+    else
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::NEDepthwiseConvolutionLayer>();
+
+      fn->configure(ifm_alloc, ker_alloc, bias_alloc, ofm_alloc, conv_info, param.multipler);
+
+      builder.append("DepthwiseConv2D", std::move(fn));
+    }
+
+    ActivationBuilder{builder}.append(param.activation, ofm_alloc);
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::DepthwiseConv2D::Explicit::Node &node)
+{
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+
+  const ::internal::tflite::operand::Index ifm_index{node.param().ifm_index};
+  const ::internal::tflite::operand::Index ker_index{node.param().ker_index};
+  const ::internal::tflite::operand::Index bias_index{node.param().bias_index};
+
+  const ::internal::tflite::operand::Index vstride_index{node.param().vstride_index};
+  const ::internal::tflite::operand::Index hstride_index{node.param().hstride_index};
+
+  const ::internal::tflite::operand::Index padding_left_index{node.param().padding_left_index};
+  const ::internal::tflite::operand::Index padding_right_index{node.param().padding_right_index};
+  const ::internal::tflite::operand::Index padding_top_index{node.param().padding_top_index};
+  const ::internal::tflite::operand::Index padding_bottom_index{node.param().padding_bottom_index};
+
+  const ::internal::tflite::operand::Index multiplier_index{node.param().multiplier_index};
+  const ::internal::tflite::operand::Index activation_index{node.param().activation_index};
+
+  const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature();
+
+  const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature();
+  const auto ker_shape = _ctx.at(ker_index).shape().asFeature();
+  const auto bias_size = _ctx.at(bias_index).shape().asVector();
+
+  auto multiplier = _ctx.at(multiplier_index).asScalar<int>();
+
+  assert(ker_shape.C == bias_size);
+  assert(ker_shape.C == ifm_shape.C * multiplier);
+
+  const int32_t padding_left = _ctx.at(padding_left_index).asScalar<int32_t>();
+  const int32_t padding_right = _ctx.at(padding_right_index).asScalar<int32_t>();
+  const int32_t padding_top = _ctx.at(padding_top_index).asScalar<int32_t>();
+  const int32_t padding_bottom = _ctx.at(padding_bottom_index).asScalar<int32_t>();
+
+  Stride stride;
+
+  stride.vertical = _ctx.at(vstride_index).asScalar<int32_t>();
+  stride.horizontal = _ctx.at(hstride_index).asScalar<int32_t>();
+
+  // TODO Should move to the place where the operand is handled, if it is possible.
+  // Set Shape Constraints and TensorInfo
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+  _builder.addShapeConstr(
+      ifm_index, asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape()), _ctx.at(ifm_index).type(),
+                              _ctx.at(ifm_index).scale(), _ctx.at(ifm_index).zeroPoint()));
+  // NOTE DepthwiseConv2D kernel is of shape [1, KER_W, KER_H, IFM_C * MULTIPLIER]
+  _builder.addShapeConstr(
+      ker_index, asTensorInfo(asTensorShape(_ctx.at(ker_index).shape()), _ctx.at(ker_index).type(),
+                              _ctx.at(ker_index).scale(), _ctx.at(ker_index).zeroPoint()));
+  _builder.addShapeConstr(bias_index,
+                          asTensorInfo(asTensorShape(_ctx.at(bias_index).shape()),
+                                       _ctx.at(bias_index).type(), _ctx.at(bias_index).scale(),
+                                       _ctx.at(bias_index).zeroPoint()));
+
+  // Construct operation parameters
+  struct Param
+  {
+    int ofm_index;
+    int ifm_index;
+    int ker_index;
+    int bias_index;
+
+    Padding padding;
+    Stride stride;
+
+    int multipler;
+    FuseCode activation;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.ifm_index = ifm_index.asInt();
+  param.ker_index = ker_index.asInt();
+  param.bias_index = bias_index.asInt();
+
+  param.stride = stride;
+
+  param.padding.left = padding_left;
+  param.padding.right = padding_right;
+  param.padding.top = padding_top;
+  param.padding.bottom = padding_bottom;
+
+  param.multipler = multiplier;
+  param.activation = static_cast<FuseCode>(_ctx.at(activation_index).asScalar<int32_t>());
+
+  VERBOSE(DepthwiseConv2D) << "OFM_C: " << ofm_shape.C << std::endl;
+  VERBOSE(DepthwiseConv2D) << "OFM_H: " << ofm_shape.H << std::endl;
+  VERBOSE(DepthwiseConv2D) << "OFM_W: " << ofm_shape.W << std::endl;
+
+  VERBOSE(DepthwiseConv2D) << "IFM_C: " << ifm_shape.C << std::endl;
+  VERBOSE(DepthwiseConv2D) << "IFM_H: " << ifm_shape.H << std::endl;
+  VERBOSE(DepthwiseConv2D) << "IFM_W: " << ifm_shape.W << std::endl;
+
+  VERBOSE(DepthwiseConv2D) << "KER_C: " << ker_shape.C << std::endl;
+  VERBOSE(DepthwiseConv2D) << "KER_H: " << ker_shape.H << std::endl;
+  VERBOSE(DepthwiseConv2D) << "KER_W: " << ker_shape.W << std::endl;
+
+  VERBOSE(DepthwiseConv2D) << "STRIDE_H: " << param.stride.vertical << std::endl;
+  VERBOSE(DepthwiseConv2D) << "STRIDE_W: " << param.stride.horizontal << std::endl;
+
+  VERBOSE(DepthwiseConv2D) << "ACTIVATION: " << param.activation << std::endl;
+
+  VERBOSE(DepthwiseConv2D) << "PAD(T): " << param.padding.top << std::endl;
+  VERBOSE(DepthwiseConv2D) << "PAD(B): " << param.padding.bottom << std::endl;
+  VERBOSE(DepthwiseConv2D) << "PAD(L): " << param.padding.left << std::endl;
+  VERBOSE(DepthwiseConv2D) << "PAD(R): " << param.padding.right << std::endl;
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto ifm_alloc = ctx.at(::internal::tflite::operand::Index{param.ifm_index});
+    auto ker_alloc = ctx.at(::internal::tflite::operand::Index{param.ker_index});
+    auto bias_alloc = ctx.at(::internal::tflite::operand::Index{param.bias_index});
+
+    const auto conv_info = asPadStrideInfo(param.padding, param.stride);
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLDepthwiseConvolutionLayer>();
+
+      fn->configure(CAST_CL(ifm_alloc), CAST_CL(ker_alloc), CAST_CL(bias_alloc), CAST_CL(ofm_alloc),
+                    conv_info, param.multipler);
+
+      builder.append("DepthwiseConv2D", std::move(fn));
+    }
+    else
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::NEDepthwiseConvolutionLayer>();
+
+      fn->configure(ifm_alloc, ker_alloc, bias_alloc, ofm_alloc, conv_info, param.multipler);
+
+      builder.append("DepthwiseConv2D", std::move(fn));
+    }
+
+    ActivationBuilder{builder}.append(param.activation, ofm_alloc);
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::Dequantize::Node &node)
+{
+  const ::internal::tflite::operand::Index output_index{node.param().output_index};
+  const ::internal::tflite::operand::Index input_index{node.param().input_index};
+
+  assert(_ctx.at(input_index).shape().rank() >= 0 && _ctx.at(input_index).shape().rank() <= 4);
+  assert(_ctx.at(input_index).shape() == _ctx.at(output_index).shape());
+  assert(_ctx.at(input_index).type() == ANEURALNETWORKS_TENSOR_QUANT8_ASYMM);
+  assert(_ctx.at(output_index).type() == ANEURALNETWORKS_TENSOR_FLOAT32);
+
+  // Set Shape Constraints
+  _builder.addShapeConstr(output_index,
+                          asTensorInfo(asTensorShape(_ctx.at(output_index).shape()),
+                                       _ctx.at(output_index).type(), _ctx.at(output_index).scale(),
+                                       _ctx.at(output_index).zeroPoint()));
+  _builder.addShapeConstr(input_index,
+                          asTensorInfo(asTensorShape(_ctx.at(input_index).shape()),
+                                       _ctx.at(input_index).type(), _ctx.at(input_index).scale(),
+                                       _ctx.at(input_index).zeroPoint()));
+
+  // Construct operation parameters
+  struct Param
+  {
+    int output_index;
+    int input_index;
+  };
+
+  Param param;
+
+  param.output_index = output_index.asInt();
+  param.input_index = input_index.asInt();
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto output_alloc = ctx.at(::internal::tflite::operand::Index{param.output_index});
+    auto input_alloc = ctx.at(::internal::tflite::operand::Index{param.input_index});
+
+    std::unique_ptr<::arm_compute::IFunction> fn;
+
+    {
+      if (::internal::arm_compute::isGpuMode())
+      {
+        auto l = nnfw::cpp14::make_unique<::arm_compute::CLCast>();
+
+        l->configure(CAST_CL(input_alloc), CAST_CL(output_alloc));
+        fn = std::move(l);
+      }
+      else
+        throw std::runtime_error("Not supported, yet");
+    }
+
+    builder.append("Dequantize", std::move(fn));
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::MaxPool2D::Implicit::Node &node)
+{
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+  const ::internal::tflite::operand::Index ifm_index{node.param().ifm_index};
+
+  const ::internal::tflite::operand::Index kh_index{node.param().kh_index};
+  const ::internal::tflite::operand::Index kw_index{node.param().kw_index};
+
+  const ::internal::tflite::operand::Index vstride_index{node.param().vstride_index};
+  const ::internal::tflite::operand::Index hstride_index{node.param().hstride_index};
+
+  const ::internal::tflite::operand::Index padding_index{node.param().padding_index};
+  const ::internal::tflite::operand::Index activation_index{node.param().activation_index};
+
+  const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature();
+  const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature();
+
+  const int32_t kh = _ctx.at(kh_index).asScalar<int32_t>();
+  const int32_t kw = _ctx.at(kw_index).asScalar<int32_t>();
+
+  const int32_t vstride = _ctx.at(vstride_index).asScalar<int32_t>();
+  const int32_t hstride = _ctx.at(hstride_index).asScalar<int32_t>();
+
+  const PaddingCode padding_type =
+      static_cast<PaddingCode>(_ctx.at(padding_index).asScalar<int32_t>());
+
+  assert((ANEURALNETWORKS_PADDING_SAME == padding_type) ||
+         (ANEURALNETWORKS_PADDING_VALID == padding_type));
+
+  // TODO Should move to the place where the operand is handled, if it is possible.
+  // Set Shape Constraints and TensorInfo
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+  _builder.addShapeConstr(
+      ifm_index, asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape()), _ctx.at(ifm_index).type(),
+                              _ctx.at(ifm_index).scale(), _ctx.at(ifm_index).zeroPoint()));
+
+  // Construct operation parameters
+  struct Param
+  {
+    int ofm_index;
+    int ifm_index;
+
+    uint32_t kw;
+    uint32_t kh;
+
+    Padding padding;
+    Stride stride;
+
+    FuseCode activation;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.ifm_index = ifm_index.asInt();
+
+  param.kh = kh;
+  param.kw = kw;
+
+  param.stride.vertical = vstride;
+  param.stride.horizontal = hstride;
+
+  param.padding = (padding_type == ANEURALNETWORKS_PADDING_SAME)
+                      ? same_padding(ifm_shape, ofm_shape, param.stride, kw, kh)
+                      : valid_padding();
+  param.activation = static_cast<FuseCode>(_ctx.at(activation_index).asScalar<int32_t>());
+
+  VERBOSE(MaxPool2D) << "IFM_H: " << ifm_shape.H << std::endl;
+  VERBOSE(MaxPool2D) << "IFM_W: " << ifm_shape.W << std::endl;
+  VERBOSE(MaxPool2D) << "OFM_H: " << ofm_shape.H << std::endl;
+  VERBOSE(MaxPool2D) << "OFM_W: " << ofm_shape.W << std::endl;
+  VERBOSE(MaxPool2D) << "KER_H: " << kh << std::endl;
+  VERBOSE(MaxPool2D) << "KER_W: " << kw << std::endl;
+  VERBOSE(MaxPool2D) << "STRIDE_H: " << vstride << std::endl;
+  VERBOSE(MaxPool2D) << "STRIDE_W: " << hstride << std::endl;
+  VERBOSE(MaxPool2D) << "PAD(T): " << param.padding.top << std::endl;
+  VERBOSE(MaxPool2D) << "PAD(B): " << param.padding.bottom << std::endl;
+  VERBOSE(MaxPool2D) << "PAD(L): " << param.padding.left << std::endl;
+  VERBOSE(MaxPool2D) << "PAD(R): " << param.padding.right << std::endl;
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto ifm_alloc = ctx.at(::internal::tflite::operand::Index{param.ifm_index});
+
+    ::arm_compute::PoolingLayerInfo info{::arm_compute::PoolingType::MAX,
+                                         ::arm_compute::Size2D{param.kw, param.kh},
+                                         asPadStrideInfo(param.padding, param.stride)};
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      std::unique_ptr<::arm_compute::CLPoolingLayer> fn{new ::arm_compute::CLPoolingLayer};
+
+      fn->configure(CAST_CL(ifm_alloc), CAST_CL(ofm_alloc), info);
+
+      builder.append("MaxPool2D", std::move(fn));
+    }
+    else
+    {
+      std::unique_ptr<::arm_compute::NEPoolingLayer> fn{new ::arm_compute::NEPoolingLayer};
+
+      fn->configure(ifm_alloc, ofm_alloc, info);
+
+      builder.append("MaxPool2D", std::move(fn));
+    }
+
+    ActivationBuilder{builder}.append(param.activation, ofm_alloc);
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::MaxPool2D::Explicit::Node &node)
+{
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+  const ::internal::tflite::operand::Index ifm_index{node.param().ifm_index};
+
+  const ::internal::tflite::operand::Index kh_index{node.param().kh_index};
+  const ::internal::tflite::operand::Index kw_index{node.param().kw_index};
+
+  const ::internal::tflite::operand::Index vstride_index{node.param().vstride_index};
+  const ::internal::tflite::operand::Index hstride_index{node.param().hstride_index};
+
+  const ::internal::tflite::operand::Index padding_left_index{node.param().padding_left_index};
+  const ::internal::tflite::operand::Index padding_right_index{node.param().padding_right_index};
+  const ::internal::tflite::operand::Index padding_top_index{node.param().padding_top_index};
+  const ::internal::tflite::operand::Index padding_bottom_index{node.param().padding_bottom_index};
+
+  const ::internal::tflite::operand::Index activation_index{node.param().activation_index};
+
+  const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature();
+  const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature();
+
+  const int32_t kh = _ctx.at(kh_index).asScalar<int32_t>();
+  const int32_t kw = _ctx.at(kw_index).asScalar<int32_t>();
+
+  const int32_t vstride = _ctx.at(vstride_index).asScalar<int32_t>();
+  const int32_t hstride = _ctx.at(hstride_index).asScalar<int32_t>();
+
+  const int32_t padding_left = _ctx.at(padding_left_index).asScalar<int32_t>();
+  const int32_t padding_right = _ctx.at(padding_right_index).asScalar<int32_t>();
+  const int32_t padding_top = _ctx.at(padding_top_index).asScalar<int32_t>();
+  const int32_t padding_bottom = _ctx.at(padding_bottom_index).asScalar<int32_t>();
+
+  // TODO Should move to the place where the operand is handled, if it is possible.
+  // Set Shape Constraints and TensorInfo
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+  _builder.addShapeConstr(
+      ifm_index, asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape()), _ctx.at(ifm_index).type(),
+                              _ctx.at(ifm_index).scale(), _ctx.at(ifm_index).zeroPoint()));
+
+  // Construct operation parameters
+  struct Param
+  {
+    int ofm_index;
+    int ifm_index;
+
+    uint32_t kw;
+    uint32_t kh;
+
+    Padding padding;
+    Stride stride;
+
+    FuseCode activation;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.ifm_index = ifm_index.asInt();
+
+  param.kh = kh;
+  param.kw = kw;
+
+  param.stride.vertical = vstride;
+  param.stride.horizontal = hstride;
+
+  param.padding.left = padding_left;
+  param.padding.right = padding_right;
+  param.padding.top = padding_top;
+  param.padding.bottom = padding_bottom;
+
+  param.activation = static_cast<FuseCode>(_ctx.at(activation_index).asScalar<int32_t>());
+
+  VERBOSE(MaxPool2D) << "IFM_H: " << ifm_shape.H << std::endl;
+  VERBOSE(MaxPool2D) << "IFM_W: " << ifm_shape.W << std::endl;
+  VERBOSE(MaxPool2D) << "OFM_H: " << ofm_shape.H << std::endl;
+  VERBOSE(MaxPool2D) << "OFM_W: " << ofm_shape.W << std::endl;
+  VERBOSE(MaxPool2D) << "KER_H: " << kh << std::endl;
+  VERBOSE(MaxPool2D) << "KER_W: " << kw << std::endl;
+  VERBOSE(MaxPool2D) << "STRIDE_H: " << vstride << std::endl;
+  VERBOSE(MaxPool2D) << "STRIDE_W: " << hstride << std::endl;
+  VERBOSE(MaxPool2D) << "PAD(T): " << param.padding.top << std::endl;
+  VERBOSE(MaxPool2D) << "PAD(B): " << param.padding.bottom << std::endl;
+  VERBOSE(MaxPool2D) << "PAD(L): " << param.padding.left << std::endl;
+  VERBOSE(MaxPool2D) << "PAD(R): " << param.padding.right << std::endl;
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto ifm_alloc = ctx.at(::internal::tflite::operand::Index{param.ifm_index});
+
+    ::arm_compute::PoolingLayerInfo info{::arm_compute::PoolingType::MAX,
+                                         ::arm_compute::Size2D{param.kw, param.kh},
+                                         asPadStrideInfo(param.padding, param.stride)};
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      std::unique_ptr<::arm_compute::CLPoolingLayer> fn{new ::arm_compute::CLPoolingLayer};
+
+      fn->configure(CAST_CL(ifm_alloc), CAST_CL(ofm_alloc), info);
+
+      builder.append("MaxPool2D", std::move(fn));
+    }
+    else
+    {
+      std::unique_ptr<::arm_compute::NEPoolingLayer> fn{new ::arm_compute::NEPoolingLayer};
+
+      fn->configure(ifm_alloc, ofm_alloc, info);
+
+      builder.append("MaxPool2D", std::move(fn));
+    }
+
+    ActivationBuilder{builder}.append(param.activation, ofm_alloc);
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::AvgPool2D::Implicit::Node &node)
+{
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+  const ::internal::tflite::operand::Index ifm_index{node.param().ifm_index};
+
+  const ::internal::tflite::operand::Index kh_index{node.param().kh_index};
+  const ::internal::tflite::operand::Index kw_index{node.param().kw_index};
+
+  const ::internal::tflite::operand::Index vstride_index{node.param().vstride_index};
+  const ::internal::tflite::operand::Index hstride_index{node.param().hstride_index};
+
+  const ::internal::tflite::operand::Index padding_index{node.param().padding_index};
+  const ::internal::tflite::operand::Index activation_index{node.param().activation_index};
+
+  const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature();
+  const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature();
+
+  const int32_t kh = _ctx.at(kh_index).asScalar<int32_t>();
+  const int32_t kw = _ctx.at(kw_index).asScalar<int32_t>();
+
+  const int32_t vstride = _ctx.at(vstride_index).asScalar<int32_t>();
+  const int32_t hstride = _ctx.at(hstride_index).asScalar<int32_t>();
+
+  const PaddingCode padding_type =
+      static_cast<PaddingCode>(_ctx.at(padding_index).asScalar<int32_t>());
+
+  assert((ANEURALNETWORKS_PADDING_SAME == padding_type) ||
+         (ANEURALNETWORKS_PADDING_VALID == padding_type));
+
+  // TODO Should move to the place where the operand is handled, if it is possible.
+  // Set Shape Constraints and TensorInfo
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+  _builder.addShapeConstr(
+      ifm_index, asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape()), _ctx.at(ifm_index).type(),
+                              _ctx.at(ifm_index).scale(), _ctx.at(ifm_index).zeroPoint()));
+
+  // Construct operation parameters
+  struct Param
+  {
+    int ofm_index;
+    int ifm_index;
+
+    uint32_t kw;
+    uint32_t kh;
+
+    Padding padding;
+    Stride stride;
+
+    FuseCode activation;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.ifm_index = ifm_index.asInt();
+
+  param.kh = kh;
+  param.kw = kw;
+
+  param.stride.vertical = vstride;
+  param.stride.horizontal = hstride;
+
+  param.padding = (padding_type == ANEURALNETWORKS_PADDING_SAME)
+                      ? same_padding(ifm_shape, ofm_shape, param.stride, kw, kh)
+                      : valid_padding();
+
+  param.activation = static_cast<FuseCode>(_ctx.at(activation_index).asScalar<int32_t>());
+
+  VERBOSE(AvgPool2D) << "IFM_H: " << ifm_shape.H << std::endl;
+  VERBOSE(AvgPool2D) << "IFM_W: " << ifm_shape.W << std::endl;
+  VERBOSE(AvgPool2D) << "OFM_H: " << ofm_shape.H << std::endl;
+  VERBOSE(AvgPool2D) << "OFM_W: " << ofm_shape.W << std::endl;
+  VERBOSE(AvgPool2D) << "KER_H: " << kh << std::endl;
+  VERBOSE(AvgPool2D) << "KER_W: " << kw << std::endl;
+  VERBOSE(AvgPool2D) << "STRIDE_H: " << vstride << std::endl;
+  VERBOSE(AvgPool2D) << "STRIDE_W: " << hstride << std::endl;
+  VERBOSE(AvgPool2D) << "PAD: " << to_string(padding_type) << std::endl;
+  VERBOSE(AvgPool2D) << "PAD(T): " << param.padding.top << std::endl;
+  VERBOSE(AvgPool2D) << "PAD(B): " << param.padding.bottom << std::endl;
+  VERBOSE(AvgPool2D) << "PAD(L): " << param.padding.left << std::endl;
+  VERBOSE(AvgPool2D) << "PAD(R): " << param.padding.right << std::endl;
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto ifm_alloc = ctx.at(::internal::tflite::operand::Index{param.ifm_index});
+
+    ::arm_compute::PoolingLayerInfo info{
+        ::arm_compute::PoolingType::AVG, ::arm_compute::Size2D{param.kw, param.kh},
+        asPadStrideInfo(param.padding, param.stride), true /* exclude_padding */};
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      std::unique_ptr<::arm_compute::CLPoolingLayer> fn{new ::arm_compute::CLPoolingLayer};
+
+      fn->configure(CAST_CL(ifm_alloc), CAST_CL(ofm_alloc), info);
+
+      builder.append("AvgPool2D", std::move(fn));
+    }
+    else
+    {
+      std::unique_ptr<::arm_compute::NEPoolingLayer> fn{new ::arm_compute::NEPoolingLayer};
+
+      fn->configure(ifm_alloc, ofm_alloc, info);
+
+      builder.append("AvgPool2D", std::move(fn));
+    }
+
+    ActivationBuilder{builder}.append(param.activation, ofm_alloc);
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::AvgPool2D::Explicit::Node &node)
+{
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+  const ::internal::tflite::operand::Index ifm_index{node.param().ifm_index};
+
+  const ::internal::tflite::operand::Index kh_index{node.param().kh_index};
+  const ::internal::tflite::operand::Index kw_index{node.param().kw_index};
+
+  const ::internal::tflite::operand::Index vstride_index{node.param().vstride_index};
+  const ::internal::tflite::operand::Index hstride_index{node.param().hstride_index};
+
+  const ::internal::tflite::operand::Index padding_left_index{node.param().padding_left_index};
+  const ::internal::tflite::operand::Index padding_right_index{node.param().padding_right_index};
+  const ::internal::tflite::operand::Index padding_top_index{node.param().padding_top_index};
+  const ::internal::tflite::operand::Index padding_bottom_index{node.param().padding_bottom_index};
+
+  const ::internal::tflite::operand::Index activation_index{node.param().activation_index};
+
+  const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature();
+  const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature();
+
+  const int32_t kh = _ctx.at(kh_index).asScalar<int32_t>();
+  const int32_t kw = _ctx.at(kw_index).asScalar<int32_t>();
+
+  const int32_t vstride = _ctx.at(vstride_index).asScalar<int32_t>();
+  const int32_t hstride = _ctx.at(hstride_index).asScalar<int32_t>();
+
+  const int32_t padding_left = _ctx.at(padding_left_index).asScalar<int32_t>();
+  const int32_t padding_right = _ctx.at(padding_right_index).asScalar<int32_t>();
+  const int32_t padding_top = _ctx.at(padding_top_index).asScalar<int32_t>();
+  const int32_t padding_bottom = _ctx.at(padding_bottom_index).asScalar<int32_t>();
+
+  // TODO Should move to the place where the operand is handled, if it is possible.
+  // Set Shape Constraints and TensorInfo
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+  _builder.addShapeConstr(
+      ifm_index, asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape()), _ctx.at(ifm_index).type(),
+                              _ctx.at(ifm_index).scale(), _ctx.at(ifm_index).zeroPoint()));
+
+  // Construct operation parameters
+  struct Param
+  {
+    int ofm_index;
+    int ifm_index;
+
+    uint32_t kw;
+    uint32_t kh;
+
+    Padding padding;
+    Stride stride;
+
+    FuseCode activation;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.ifm_index = ifm_index.asInt();
+
+  param.kh = kh;
+  param.kw = kw;
+
+  param.stride.vertical = vstride;
+  param.stride.horizontal = hstride;
+
+  param.padding.left = padding_left;
+  param.padding.right = padding_right;
+  param.padding.top = padding_top;
+  param.padding.bottom = padding_bottom;
+
+  param.activation = static_cast<FuseCode>(_ctx.at(activation_index).asScalar<int32_t>());
+
+  VERBOSE(AvgPool2D) << "IFM_H: " << ifm_shape.H << std::endl;
+  VERBOSE(AvgPool2D) << "IFM_W: " << ifm_shape.W << std::endl;
+  VERBOSE(AvgPool2D) << "OFM_H: " << ofm_shape.H << std::endl;
+  VERBOSE(AvgPool2D) << "OFM_W: " << ofm_shape.W << std::endl;
+  VERBOSE(AvgPool2D) << "KER_H: " << kh << std::endl;
+  VERBOSE(AvgPool2D) << "KER_W: " << kw << std::endl;
+  VERBOSE(AvgPool2D) << "STRIDE_H: " << vstride << std::endl;
+  VERBOSE(AvgPool2D) << "STRIDE_W: " << hstride << std::endl;
+  VERBOSE(AvgPool2D) << "PAD(T): " << param.padding.top << std::endl;
+  VERBOSE(AvgPool2D) << "PAD(B): " << param.padding.bottom << std::endl;
+  VERBOSE(AvgPool2D) << "PAD(L): " << param.padding.left << std::endl;
+  VERBOSE(AvgPool2D) << "PAD(R): " << param.padding.right << std::endl;
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto ifm_alloc = ctx.at(::internal::tflite::operand::Index{param.ifm_index});
+
+    ::arm_compute::PoolingLayerInfo info{
+        ::arm_compute::PoolingType::AVG, ::arm_compute::Size2D{param.kw, param.kh},
+        asPadStrideInfo(param.padding, param.stride), true /* exclude_padding */};
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      std::unique_ptr<::arm_compute::CLPoolingLayer> fn{new ::arm_compute::CLPoolingLayer};
+
+      fn->configure(CAST_CL(ifm_alloc), CAST_CL(ofm_alloc), info);
+
+      builder.append("AvgPool2D", std::move(fn));
+    }
+    else
+    {
+      std::unique_ptr<::arm_compute::NEPoolingLayer> fn{new ::arm_compute::NEPoolingLayer};
+
+      fn->configure(ifm_alloc, ofm_alloc, info);
+
+      builder.append("AvgPool2D", std::move(fn));
+    }
+
+    ActivationBuilder{builder}.append(param.activation, ofm_alloc);
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::Concat::Node &node)
+{
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+  const ::internal::tflite::operand::Index axis_index{node.param().axis_index};
+
+  // NOTE This implementation assumes that inputs and output are a feature
+  const auto ofm_shape = _ctx.at(ofm_index).shape();
+  uint32_t input_rank = ofm_shape.rank();
+  int32_t axis = _ctx.at(axis_index).asScalar<int32_t>();
+
+  // Handle negative axis
+  if (axis < 0)
+  {
+    axis += input_rank;
+  }
+
+  // Set Shape Constraints and TensorInfo (for output)
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+
+  // Set Shape Constraints and TensorInfo (for input)
+  const uint32_t coord_index = ToARMComputeAxis(input_rank, axis).value();
+  uint32_t depth = 0;
+
+  ::arm_compute::Coordinates coordinates;
+  coordinates.set_num_dimensions(input_rank);
+
+  for (const auto &index : node.param().ifm_indexes)
+  {
+    const ::internal::tflite::operand::Index ifm_index{index};
+    const auto ifm_shape = _ctx.at(ifm_index).shape();
+
+    coordinates[coord_index] = depth;
+
+    _builder.addSubsumptionConstr(ifm_index, ofm_index, coordinates,
+                                  asTensorShape(_ctx.at(ifm_index).shape()), true);
+
+    depth += ifm_shape.dim(axis);
+  }
+
+  // NOTE Concat has no actual operation!
+  // However, dummy stage is added because profiler assumes every operation make a stage.
+  auto stage = [](const IAllocationContext &ctx, IExecutionBuilder &builder) {};
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::FullyConnected::Node &node)
+{
+  VERBOSE(FullyConnected) << "Configure FULLY_CONNECTED operation" << std::endl;
+
+  const ::internal::tflite::operand::Index output_index{node.param().output_index};
+
+  const ::internal::tflite::operand::Index input_index{node.param().input_index};
+  const ::internal::tflite::operand::Index weight_index{node.param().weight_index};
+  const ::internal::tflite::operand::Index bias_index{node.param().bias_index};
+
+  const ::internal::tflite::operand::Index activation_index{node.param().activation_index};
+
+  assert(_ctx.at(input_index).shape().rank() >= 2);
+  assert(_ctx.at(output_index).shape().rank() == 2);
+  assert(_ctx.at(weight_index).shape().rank() == 2);
+  assert(_ctx.at(bias_index).shape().rank() == 1);
+
+  const auto input_rank = _ctx.at(input_index).shape().rank();
+  // TODO Currently we are not handling where the case is that the input's rank is 3.
+  // The handling should be added in the future.
+  assert(input_rank != 3);
+
+  const auto output_size = _ctx.at(output_index).shape().dim(1);
+  assert(_ctx.at(bias_index).shape().dim(0) == output_size);
+  assert(_ctx.at(weight_index).shape().dim(0) == output_size);
+  const auto batch_size = _ctx.at(output_index).shape().dim(0);
+  const auto input_size = _ctx.at(weight_index).shape().dim(1);
+
+  // Check for reshaping input's shape into rank-2
+  bool needs_reshape = false;
+  internal::tflite::operand::Shape reshape(2);
+  if (input_rank == 4)
+  {
+    nnfw::misc::feature::Shape ifm_shape_feature = _ctx.at(input_index).shape().asFeature();
+    auto feature_size =
+        ifm_shape_feature.N * ifm_shape_feature.C * ifm_shape_feature.H * ifm_shape_feature.W;
+    assert(feature_size == batch_size * input_size);
+
+    _builder.addShapeConstr(input_index,
+                            asTensorInfo(asTensorShape(_ctx.at(input_index).shape(), false),
+                                         _ctx.at(input_index).type(), _ctx.at(input_index).scale(),
+                                         _ctx.at(input_index).zeroPoint()));
+
+    // for reshaping
+    needs_reshape = true;
+    reshape.dim(0) = batch_size; /* H */
+    reshape.dim(1) = input_size; /* W */
+  }
+  else if (input_rank == 2)
+  {
+    auto ifm_shape = _ctx.at(input_index).shape();
+    nnfw::misc::matrix::Shape ifm_shape_matrix = ifm_shape.asMatrix();
+    assert(ifm_shape.dim(0) == batch_size);
+    assert(ifm_shape.dim(1) == input_size);
+
+    _builder.addShapeConstr(input_index,
+                            asTensorInfo(asTensorShape(_ctx.at(input_index).shape()),
+                                         _ctx.at(input_index).type(), _ctx.at(input_index).scale(),
+                                         _ctx.at(input_index).zeroPoint()));
+  }
+
+  // TODO Should move to the place where the operand is handled, if it is possible.
+  // Set Shape Constraints
+  _builder.addShapeConstr(output_index,
+                          asTensorInfo(asTensorShape(_ctx.at(output_index).shape()),
+                                       _ctx.at(output_index).type(), _ctx.at(output_index).scale(),
+                                       _ctx.at(output_index).zeroPoint()));
+  _builder.addShapeConstr(weight_index,
+                          asTensorInfo(asTensorShape(_ctx.at(weight_index).shape()),
+                                       _ctx.at(weight_index).type(), _ctx.at(weight_index).scale(),
+                                       _ctx.at(weight_index).zeroPoint()));
+  _builder.addShapeConstr(bias_index,
+                          asTensorInfo(asTensorShape(_ctx.at(bias_index).shape()),
+                                       _ctx.at(bias_index).type(), _ctx.at(bias_index).scale(),
+                                       _ctx.at(bias_index).zeroPoint()));
+
+  // Construct operation parameters
+  struct Param
+  {
+    int output_index;
+
+    int input_index;
+    int weight_index;
+    int bias_index;
+
+    FuseCode activation;
+  };
+
+  Param param;
+
+  param.output_index = output_index.asInt();
+  param.input_index = input_index.asInt();
+  param.weight_index = weight_index.asInt();
+  param.bias_index = bias_index.asInt();
+
+  param.activation = static_cast<FuseCode>(_ctx.at(activation_index).asScalar<int32_t>());
+
+  auto stage = [param, needs_reshape, reshape](const IAllocationContext &ctx,
+                                               IExecutionBuilder &builder) {
+    auto output_alloc = ctx.at(::internal::tflite::operand::Index{param.output_index});
+    auto input_alloc = ctx.at(::internal::tflite::operand::Index{param.input_index});
+    auto weight_alloc = ctx.at(::internal::tflite::operand::Index{param.weight_index});
+    auto bias_alloc = ctx.at(::internal::tflite::operand::Index{param.bias_index});
+
+    auto fn = nnfw::cpp14::make_unique<arm_compute::CLFullyConnectedReshapingLayer>();
+
+    fn->configure(CAST_CL(input_alloc), CAST_CL(weight_alloc), CAST_CL(bias_alloc),
+                  CAST_CL(output_alloc), needs_reshape, asTensorShape(reshape));
+
+    builder.append("FullyConnected", std::move(fn));
+
+    ActivationBuilder{builder}.append(param.activation, output_alloc);
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::ResizeBilinear::Node &node)
+{
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+
+  const ::internal::tflite::operand::Index ifm_index{node.param().ifm_index};
+  const ::internal::tflite::operand::Index height_index{node.param().height_index};
+  const ::internal::tflite::operand::Index width_index{node.param().width_index};
+
+  // TODO Should move to the place where the operand is handled, if it is possible.
+  // Set Shape Constraints
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+  _builder.addShapeConstr(
+      ifm_index, asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape()), _ctx.at(ifm_index).type(),
+                              _ctx.at(ifm_index).scale(), _ctx.at(ifm_index).zeroPoint()));
+
+  struct Param
+  {
+    int ofm_index;
+    int ifm_index;
+
+    int new_height;
+    int new_width;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.ifm_index = ifm_index.asInt();
+  param.new_height = _ctx.at(height_index).asScalar<int32_t>();
+  param.new_width = _ctx.at(width_index).asScalar<int32_t>();
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto ifm_alloc = ctx.at(::internal::tflite::operand::Index{param.ifm_index});
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLScale>();
+
+      fn->configure(CAST_CL(ifm_alloc), CAST_CL(ofm_alloc),
+                    ::arm_compute::InterpolationPolicy::BILINEAR,
+                    ::arm_compute::BorderMode::REPLICATE, ::arm_compute::PixelValue(0.f),
+                    ::arm_compute::SamplingPolicy::TOP_LEFT);
+
+      builder.append("ResizeBilinear", std::move(fn));
+    }
+    else
+      throw std::runtime_error("Not supported, yet");
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::Reshape::Node &node)
+{
+  const ::internal::tflite::operand::Index output_index{node.param().output_index};
+  const ::internal::tflite::operand::Index input_index{node.param().input_index};
+
+  auto input_shape = asTensorShape(_ctx.at(input_index).shape(), false);
+  auto output_shape = asTensorShape(_ctx.at(output_index).shape(), false);
+
+  assert(input_shape[0] * input_shape[1] * input_shape[2] * input_shape[3] ==
+         output_shape[0] * output_shape[1] * output_shape[2] * output_shape[3]);
+
+  // TODO Should move to the place where the operand is handled, if it is possible.
+  _builder.addShapeConstr(output_index, asTensorInfo(output_shape, _ctx.at(output_index).type(),
+                                                     _ctx.at(output_index).scale(),
+                                                     _ctx.at(output_index).zeroPoint()));
+  _builder.addShapeConstr(input_index, asTensorInfo(input_shape, _ctx.at(input_index).type(),
+                                                    _ctx.at(input_index).scale(),
+                                                    _ctx.at(input_index).zeroPoint()));
+
+  struct Param
+  {
+    int output_index;
+    int input_index;
+  };
+
+  Param param;
+
+  param.output_index = output_index.asInt();
+  param.input_index = input_index.asInt();
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto output_alloc = ctx.at(::internal::tflite::operand::Index{param.output_index});
+    auto input_alloc = ctx.at(::internal::tflite::operand::Index{param.input_index});
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      // GenericReshape first apply NCHW->NHWC permutation, and apply reshape
+      auto fn = nnfw::cpp14::make_unique<GenericReshapeLayer>();
+
+      fn->configure(CAST_CL(input_alloc), CAST_CL(output_alloc));
+
+      builder.append("Reshape", std::move(fn));
+    }
+    else
+    {
+      auto fn = nnfw::cpp14::make_unique<GenericReshapeLayer>();
+
+      fn->configure(input_alloc, output_alloc);
+
+      builder.append("Reshape", std::move(fn));
+    }
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::Squeeze::Node &node)
+{
+  // node.param().dims_index_optional is ignored since output tensor already has squeezed shape
+  // by freezer and toco
+  const ::internal::tflite::operand::Index output_index{node.param().output_index};
+  const ::internal::tflite::operand::Index input_index{node.param().input_index};
+
+  // Set Shape Constraints
+  _builder.addShapeConstr(output_index,
+                          asTensorInfo(asTensorShape(_ctx.at(output_index).shape()),
+                                       _ctx.at(output_index).type(), _ctx.at(output_index).scale(),
+                                       _ctx.at(output_index).zeroPoint()));
+  _builder.addShapeConstr(input_index,
+                          asTensorInfo(asTensorShape(_ctx.at(input_index).shape()),
+                                       _ctx.at(input_index).type(), _ctx.at(input_index).scale(),
+                                       _ctx.at(input_index).zeroPoint()));
+
+  // Construct operation parameters
+  struct Param
+  {
+    int output_index;
+    int input_index;
+  };
+
+  Param param;
+
+  param.output_index = output_index.asInt();
+  param.input_index = input_index.asInt();
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto output_alloc = ctx.at(::internal::tflite::operand::Index{param.output_index});
+    auto input_alloc = ctx.at(::internal::tflite::operand::Index{param.input_index});
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLReshapeLayer>();
+
+      fn->configure(CAST_CL(input_alloc), CAST_CL(output_alloc));
+
+      builder.append("Squeeze", std::move(fn));
+    }
+    else
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::NEReshapeLayer>();
+
+      fn->configure(input_alloc, output_alloc);
+
+      builder.append("Squeeze", std::move(fn));
+    }
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::Softmax::Node &node)
+{
+  VERBOSE(Softmax) << "Configure SOFTMAX operation" << std::endl;
+
+  const ::internal::tflite::operand::Index output_index{node.param().output_index};
+  const ::internal::tflite::operand::Index input_index{node.param().input_index};
+  const ::internal::tflite::operand::Index scale_index{node.param().scale_index};
+
+  assert(_ctx.at(output_index).shape().rank() == _ctx.at(input_index).shape().rank());
+  assert(_ctx.at(scale_index).shape().rank() == 0);
+
+  // TODO Should move to the place where the operand is handled, if it is possible.
+  _builder.addShapeConstr(output_index,
+                          asTensorInfo(asTensorShape(_ctx.at(output_index).shape()),
+                                       _ctx.at(output_index).type(), _ctx.at(output_index).scale(),
+                                       _ctx.at(output_index).zeroPoint()));
+  _builder.addShapeConstr(input_index,
+                          asTensorInfo(asTensorShape(_ctx.at(input_index).shape()),
+                                       _ctx.at(input_index).type(), _ctx.at(input_index).scale(),
+                                       _ctx.at(input_index).zeroPoint()));
+
+  struct Param
+  {
+    int output_index;
+    int input_index;
+    float scale;
+  };
+
+  Param param;
+
+  param.output_index = output_index.asInt();
+  param.input_index = input_index.asInt();
+  param.scale = _ctx.at(scale_index).asScalar<float>();
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto output_alloc = ctx.at(::internal::tflite::operand::Index{param.output_index});
+    auto input_alloc = ctx.at(::internal::tflite::operand::Index{param.input_index});
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLSoftmaxLayer>();
+
+      fn->configure(CAST_CL(input_alloc), CAST_CL(output_alloc), param.scale);
+
+      builder.append("Softmax", std::move(fn));
+    }
+    else
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::NESoftmaxLayer>();
+
+      fn->configure(input_alloc, output_alloc, param.scale);
+
+      builder.append("Softmax", std::move(fn));
+    }
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::StridedSlice::Node &node)
+{
+  VERBOSE(StridedSlice) << "Configure STRIDED_SLICE operation" << std::endl;
+
+  const ::internal::tflite::operand::Index outputData_index{node.param().outputData_index};
+
+  const ::internal::tflite::operand::Index inputData_index{node.param().inputData_index};
+  const ::internal::tflite::operand::Index startData_index{node.param().startData_index};
+  const ::internal::tflite::operand::Index endData_index{node.param().endData_index};
+  const ::internal::tflite::operand::Index stridesData_index{node.param().stridesData_index};
+  const ::internal::tflite::operand::Index beginMask_index{node.param().beginMask_index};
+  const ::internal::tflite::operand::Index endMask_index{node.param().endMask_index};
+  const ::internal::tflite::operand::Index shrinkAxisMask_index{node.param().shrinkAxisMask_index};
+
+  // Set Shape Constraints
+  _builder.addShapeConstr(outputData_index,
+                          asTensorInfo(asTensorShape(_ctx.at(outputData_index).shape()),
+                                       _ctx.at(outputData_index).type(),
+                                       _ctx.at(outputData_index).scale(),
+                                       _ctx.at(outputData_index).zeroPoint()));
+  _builder.addShapeConstr(
+      inputData_index,
+      asTensorInfo(asTensorShape(_ctx.at(inputData_index).shape()), _ctx.at(inputData_index).type(),
+                   _ctx.at(inputData_index).scale(), _ctx.at(inputData_index).zeroPoint()));
+
+  assert(_ctx.at(startData_index).shape().rank() == 1);
+  assert(_ctx.at(endData_index).shape().rank() == 1);
+  assert(_ctx.at(stridesData_index).shape().rank() == 1);
+  _builder.addShapeConstr(
+      startData_index,
+      asTensorInfo(asTensorShape(_ctx.at(startData_index).shape()), _ctx.at(startData_index).type(),
+                   _ctx.at(startData_index).scale(), _ctx.at(startData_index).zeroPoint()));
+  _builder.addShapeConstr(endData_index, asTensorInfo(asTensorShape(_ctx.at(endData_index).shape()),
+                                                      _ctx.at(endData_index).type(),
+                                                      _ctx.at(endData_index).scale(),
+                                                      _ctx.at(endData_index).zeroPoint()));
+  _builder.addShapeConstr(
+      stridesData_index,
+      asTensorInfo(asTensorShape(_ctx.at(endData_index).shape()), _ctx.at(stridesData_index).type(),
+                   _ctx.at(stridesData_index).scale(), _ctx.at(stridesData_index).zeroPoint()));
+
+  // Set initializers for indices data such as order of inputData
+  int input_rank = _ctx.at(inputData_index).shape().rank();
+  std::vector<int32_t> starts;
+  std::vector<int32_t> ends;
+  std::vector<int32_t> strides;
+  starts.resize(input_rank, 0);
+  ends.resize(input_rank, 0);
+  strides.resize(input_rank, 0);
+  {
+    auto input_shape = _ctx.at(inputData_index).shape();
+    auto startData_base = _ctx.at(startData_index).data().base();
+    auto endData_base = _ctx.at(endData_index).data().base();
+    auto stridesData_base = _ctx.at(stridesData_index).data().base();
+    const auto startData_size = _ctx.at(startData_index).shape().asVector();
+    const auto endData_size = _ctx.at(endData_index).shape().asVector();
+    const auto stridesData_size = _ctx.at(stridesData_index).shape().asVector();
+
+    assert(_ctx.at(startData_index).type() == ANEURALNETWORKS_TENSOR_INT32);
+    assert(_ctx.at(endData_index).type() == ANEURALNETWORKS_TENSOR_INT32);
+    assert(_ctx.at(stridesData_index).type() == ANEURALNETWORKS_TENSOR_INT32);
+    assert(startData_size == input_rank);
+    assert(endData_size == input_rank);
+    assert(stridesData_size == input_rank);
+
+    assert(startData_base != nullptr);
+    for (uint32_t n = 0; n < input_rank; ++n)
+    {
+      auto axis = ToARMComputeAxis(input_rank, n).value();
+
+      int32_t start_value = *(reinterpret_cast<const int32_t *>(startData_base) + n);
+      starts[axis] = start_value;
+
+      int32_t end_value = *(reinterpret_cast<const int32_t *>(endData_base) + n);
+      ends[axis] = end_value;
+
+      int32_t strides_value = *(reinterpret_cast<const int32_t *>(stridesData_base) + n);
+      strides[axis] = strides_value;
+    }
+  }
+
+  struct Param
+  {
+    int32_t outputData_index;
+    int32_t inputData_index;
+
+    std::vector<int32_t> starts;
+    std::vector<int32_t> ends;
+    std::vector<int32_t> strides;
+
+    int32_t beginMask;
+    int32_t endMask;
+    int32_t shrinkAxisMask;
+  };
+
+  Param param;
+  param.outputData_index = outputData_index.asInt();
+  param.inputData_index = inputData_index.asInt();
+
+  param.starts = starts;
+  param.ends = ends;
+  param.strides = strides;
+
+  // Set mask bits such as order of inputData
+  param.beginMask = _ctx.at(beginMask_index).asReorderBits<int32_t>(input_rank);
+  param.endMask = _ctx.at(endMask_index).asReorderBits<int32_t>(input_rank);
+  param.shrinkAxisMask = _ctx.at(shrinkAxisMask_index).asReorderBits<int32_t>(input_rank);
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto outputData_alloc = ctx.at(::internal::tflite::operand::Index{param.outputData_index});
+    auto inputData_alloc = ctx.at(::internal::tflite::operand::Index{param.inputData_index});
+
+    ::arm_compute::Coordinates starts;
+    ::arm_compute::Coordinates ends;
+    ::arm_compute::BiStrides strides;
+    for (int i = 0; i < param.starts.size(); ++i)
+    {
+      starts.set(i, param.starts[i]);
+      ends.set(i, param.ends[i]);
+      strides.set(i, param.strides[i]);
+    }
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLStridedSlice>();
+
+      fn->configure(CAST_CL(inputData_alloc), CAST_CL(outputData_alloc), starts, ends, strides,
+                    param.beginMask, param.endMask, param.shrinkAxisMask);
+
+      builder.append("StridedSlice", std::move(fn));
+    }
+    else
+      throw std::runtime_error("Not supported, yet");
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::ReduceMin::Node &node)
+{
+  VERBOSE(ReduceMin) << "Configure REDUCEMIN operation" << std::endl;
+
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+  const ::internal::tflite::operand::Index ifm_index{node.param().ifm_index};
+  const ::internal::tflite::operand::Index axis_index{node.param().axis_index};
+
+  auto ifm_shape = _ctx.at(ifm_index).shape();
+  auto ofm_shape = _ctx.at(ofm_index).shape();
+  auto axis_shape = _ctx.at(axis_index).shape();
+  assert(ifm_shape.rank() <= 4);
+  assert(ofm_shape.rank() <= ifm_shape.rank());
+  assert(_ctx.at(axis_index).hasData());
+  assert(axis_shape.rank() == 0 || axis_shape.rank() == 1);
+
+  // NOTE For the 4-dimensions, if the rank of input and output are different, this runtime only
+  // supports cases reducing height and width or reducing depth.
+  // TODO We have to support all cases of dimensions up to 4.
+  // For correct permuting, we have to set output's shape to be equal in dimension position of the
+  // input. But the positions of the same dimensions in the input and output may be set differently.
+  // For example {2,3,4,5}(input's shape) can be reduced to {3,5}(output's shape). The original
+  // output shape should be {1,3,1,5}, but real output shape may be {3,5}. If you simply try to
+  // extend it in 4 dimensions, it should be {1,1,3,5}.
+  // Even if output shape is changed to {1,3,1,5}, there is another problem. It is that shape of
+  // output tensor used at next operation is changed to {1,3,1,5} after this operation even if the
+  // next operation is not desired.
+  if (ifm_shape.rank() == 4 && ifm_shape.rank() != ofm_shape.rank())
+  {
+    if (ofm_shape.rank() == 2)
+    {
+      // Reducing HW
+      assert(ifm_shape.dim(0) == ofm_shape.dim(0) && ifm_shape.dim(3) == ofm_shape.dim(1));
+    }
+    else if (ofm_shape.rank() == 3)
+    {
+      // Reducing C or
+      // (Reducing H and C(ifm and ofm) == 1) or (Reducing W and C(ifm and ofm) == 1)
+      assert(ifm_shape.dim(0) == ofm_shape.dim(0) && ifm_shape.dim(1) == ofm_shape.dim(1) &&
+                 ifm_shape.dim(2) == ofm_shape.dim(2) ||
+             (ifm_shape.dim(0) == ofm_shape.dim(0) &&
+              (ifm_shape.dim(1) == ofm_shape.dim(1) || ifm_shape.dim(2) == ofm_shape.dim(1)) &&
+              ifm_shape.dim(3) == 1 && ofm_shape.dim(2) == 1));
+    }
+  }
+
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+  _builder.addShapeConstr(
+      ifm_index, asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape()), _ctx.at(ifm_index).type(),
+                              _ctx.at(ifm_index).scale(), _ctx.at(ifm_index).zeroPoint()));
+
+  std::set<uint32_t> axis;
+  {
+    const auto ifm_rank = ifm_shape.rank();
+    switch (axis_shape.rank())
+    {
+      case 0: // scalar
+      {
+        int32_t axis_value = _ctx.at(axis_index).asScalar<int32_t>();
+        if (axis_value < 0)
+        {
+          axis_value += ifm_rank;
+        }
+        axis.insert(ToARMComputeAxis(ifm_rank, axis_value).value());
+        break;
+      }
+      case 1: // vector
+      {
+        const auto axis_base = _ctx.at(axis_index).data().base();
+        const auto axis_size = _ctx.at(axis_index).shape().asVector();
+
+        // If axis's data does not exist as constant values and can be gotten as input data, we have
+        // to find a way to infer output shape when sinking output.
+        assert(axis_base != nullptr);
+        for (uint32_t n = 0; n < axis_size; ++n)
+        {
+          int32_t axis_value = *(reinterpret_cast<const int32_t *>(axis_base) + n);
+          if (axis_value < 0)
+          {
+            axis_value += ifm_rank;
+          }
+          axis.insert(ToARMComputeAxis(ifm_rank, axis_value).value());
+        }
+        break;
+      }
+      default:
+        throw std::runtime_error("Not supported");
+        break;
+    }
+  }
+
+  // Construct operation parameters
+  struct Param
+  {
+    int ofm_index;
+    int ifm_index;
+    std::set<uint32_t> axis;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.ifm_index = ifm_index.asInt();
+  param.axis = axis;
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto ifm_alloc = ctx.at(::internal::tflite::operand::Index{param.ifm_index});
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLReduceOperation>();
+
+      fn->configure(CAST_CL(ifm_alloc), CAST_CL(ofm_alloc), param.axis,
+                    ::arm_compute::ReduceOperation::MIN);
+
+      builder.append("ReduceMin", std::move(fn));
+    }
+    else
+      throw std::runtime_error("Not supported, yet");
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::ReduceMax::Node &node)
+{
+  VERBOSE(ReduceMax) << "Configure REDUCEMAX operation" << std::endl;
+
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+  const ::internal::tflite::operand::Index ifm_index{node.param().ifm_index};
+  const ::internal::tflite::operand::Index axis_index{node.param().axis_index};
+
+  auto ifm_shape = _ctx.at(ifm_index).shape();
+  auto ofm_shape = _ctx.at(ofm_index).shape();
+  auto axis_shape = _ctx.at(axis_index).shape();
+  assert(ifm_shape.rank() <= 4);
+  assert(ofm_shape.rank() <= ifm_shape.rank());
+  assert(_ctx.at(axis_index).hasData());
+  assert(axis_shape.rank() == 0 || axis_shape.rank() == 1);
+
+  // NOTE For the 4-dimensions, if the rank of input and output are different, this runtime only
+  // supports cases reducing height and width or reducing depth.
+  // TODO We have to support all cases of dimensions up to 4.
+  // For correct permuting, we have to set output's shape to be equal in dimension position of the
+  // input. But the positions of the same dimensions in the input and output may be set differently.
+  // For example {2,3,4,5}(input's shape) can be reduced to {3,5}(output's shape). The original
+  // output shape should be {1,3,1,5}, but real output shape may be {3,5}. If you simply try to
+  // extend it in 4 dimensions, it should be {1,1,3,5}.
+  // Even if output shape is changed to {1,3,1,5}, there is another problem. It is that shape of
+  // output tensor used at next operation is changed to {1,3,1,5} after this operation even if the
+  // next operation is not desired.
+  if (ifm_shape.rank() == 4 && ifm_shape.rank() != ofm_shape.rank())
+  {
+    if (ofm_shape.rank() == 2)
+    {
+      // Reducing HW
+      assert(ifm_shape.dim(0) == ofm_shape.dim(0) && ifm_shape.dim(3) == ofm_shape.dim(1));
+    }
+    else if (ofm_shape.rank() == 3)
+    {
+      // Reducing C or
+      // (Reducing H and C(ifm and ofm) == 1) or (Reducing W and C(ifm and ofm) == 1)
+      assert(ifm_shape.dim(0) == ofm_shape.dim(0) && ifm_shape.dim(1) == ofm_shape.dim(1) &&
+                 ifm_shape.dim(2) == ofm_shape.dim(2) ||
+             (ifm_shape.dim(0) == ofm_shape.dim(0) &&
+              (ifm_shape.dim(1) == ofm_shape.dim(1) || ifm_shape.dim(2) == ofm_shape.dim(1)) &&
+              ifm_shape.dim(3) == 1 && ofm_shape.dim(2) == 1));
+    }
+  }
+
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+  _builder.addShapeConstr(
+      ifm_index, asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape()), _ctx.at(ifm_index).type(),
+                              _ctx.at(ifm_index).scale(), _ctx.at(ifm_index).zeroPoint()));
+
+  std::set<uint32_t> axis;
+  {
+    const auto ifm_rank = ifm_shape.rank();
+    switch (axis_shape.rank())
+    {
+      case 0: // scalar
+      {
+        int32_t axis_value = _ctx.at(axis_index).asScalar<int32_t>();
+        if (axis_value < 0)
+        {
+          axis_value += ifm_rank;
+        }
+        axis.insert(ToARMComputeAxis(ifm_rank, axis_value).value());
+        break;
+      }
+      case 1: // vector
+      {
+        const auto axis_base = _ctx.at(axis_index).data().base();
+        const auto axis_size = _ctx.at(axis_index).shape().asVector();
+
+        // If axis's data does not exist as constant values and can be gotten as input data, we have
+        // to find a way to infer output shape when sinking output.
+        assert(axis_base != nullptr);
+        for (uint32_t n = 0; n < axis_size; ++n)
+        {
+          int32_t axis_value = *(reinterpret_cast<const int32_t *>(axis_base) + n);
+          if (axis_value < 0)
+          {
+            axis_value += ifm_rank;
+          }
+          axis.insert(ToARMComputeAxis(ifm_rank, axis_value).value());
+        }
+        break;
+      }
+      default:
+        throw std::runtime_error("Not supported");
+        break;
+    }
+  }
+
+  // Construct operation parameters
+  struct Param
+  {
+    int ofm_index;
+    int ifm_index;
+    std::set<uint32_t> axis;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.ifm_index = ifm_index.asInt();
+  param.axis = axis;
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto ifm_alloc = ctx.at(::internal::tflite::operand::Index{param.ifm_index});
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLReduceOperation>();
+
+      fn->configure(CAST_CL(ifm_alloc), CAST_CL(ofm_alloc), param.axis,
+                    ::arm_compute::ReduceOperation::MAX);
+
+      builder.append("ReduceMax", std::move(fn));
+    }
+    else
+      throw std::runtime_error("Not supported, yet");
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::Cast::Node &node)
+{
+  const ::internal::tflite::operand::Index output_index{node.param().output_index};
+  const ::internal::tflite::operand::Index input_index{node.param().input_index};
+
+  assert(_ctx.at(output_index).shape() == _ctx.at(input_index).shape());
+
+  _builder.addShapeConstr(output_index,
+                          asTensorInfo(asTensorShape(_ctx.at(output_index).shape()),
+                                       _ctx.at(output_index).type(), _ctx.at(output_index).scale(),
+                                       _ctx.at(output_index).zeroPoint()));
+  _builder.addShapeConstr(input_index,
+                          asTensorInfo(asTensorShape(_ctx.at(input_index).shape()),
+                                       _ctx.at(input_index).type(), _ctx.at(input_index).scale(),
+                                       _ctx.at(input_index).zeroPoint()));
+
+  // Construct operation parameters
+  struct Param
+  {
+    int input_index;
+    int output_index;
+  };
+
+  Param param;
+
+  param.output_index = output_index.asInt();
+  param.input_index = input_index.asInt();
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto output_alloc = ctx.at(::internal::tflite::operand::Index{param.output_index});
+    auto input_alloc = ctx.at(::internal::tflite::operand::Index{param.input_index});
+
+    std::unique_ptr<::arm_compute::IFunction> fn;
+
+    {
+      if (::internal::arm_compute::isGpuMode())
+      {
+        auto l = nnfw::cpp14::make_unique<::arm_compute::CLCast>();
+
+        l->configure(CAST_CL(input_alloc), CAST_CL(output_alloc));
+        fn = std::move(l);
+      }
+      else
+        throw std::runtime_error("Not supported, yet");
+    }
+
+    builder.append("Cast", std::move(fn));
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::TopKV2::Node &node)
+{
+  const ::internal::tflite::operand::Index outputValues_index{node.param().outputValues_index};
+  const ::internal::tflite::operand::Index outputIndices_index{node.param().outputIndices_index};
+
+  const ::internal::tflite::operand::Index inputData_index{node.param().inputData_index};
+  const ::internal::tflite::operand::Index k_index{node.param().k_index};
+
+  // Currently, we only support the vector input.
+  assert(_ctx.at(inputData_index).shape().rank() == 1 ||
+         _ctx.at(inputData_index).shape().rank() == 2);
+
+  const int32_t k = _ctx.at(k_index).asScalar<int32_t>();
+
+  // Set shape constraints
+  _builder.addShapeConstr(outputValues_index,
+                          asTensorInfo(asTensorShape(_ctx.at(outputValues_index).shape()),
+                                       _ctx.at(outputValues_index).type(),
+                                       _ctx.at(outputValues_index).scale(),
+                                       _ctx.at(outputValues_index).zeroPoint()));
+  _builder.addShapeConstr(outputIndices_index,
+                          asTensorInfo(asTensorShape(_ctx.at(outputIndices_index).shape()),
+                                       _ctx.at(outputIndices_index).type(),
+                                       _ctx.at(outputIndices_index).scale(),
+                                       _ctx.at(outputIndices_index).zeroPoint()));
+  _builder.addShapeConstr(
+      inputData_index,
+      asTensorInfo(asTensorShape(_ctx.at(inputData_index).shape()), _ctx.at(inputData_index).type(),
+                   _ctx.at(inputData_index).scale(), _ctx.at(inputData_index).zeroPoint()));
+
+  // Construct operation parameters
+  struct Param
+  {
+    int32_t outputValues_index;
+    int32_t outputIndices_index;
+
+    int32_t inputData_index;
+    int32_t k;
+  };
+
+  Param param;
+
+  param.outputValues_index = outputValues_index.asInt();
+  param.outputIndices_index = outputIndices_index.asInt();
+  param.inputData_index = inputData_index.asInt();
+  param.k = k;
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto values_alloc = ctx.at(::internal::tflite::operand::Index{param.outputValues_index});
+    auto indices_alloc = ctx.at(::internal::tflite::operand::Index{param.outputIndices_index});
+    auto input_alloc = ctx.at(::internal::tflite::operand::Index{param.inputData_index});
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLTopKV2>();
+
+      fn->configure(CAST_CL(input_alloc), param.k, CAST_CL(values_alloc), CAST_CL(indices_alloc));
+
+      builder.append("TopKV2", std::move(fn));
+    }
+    else
+      throw std::runtime_error("Not supported, yet");
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::Gather::Node &node)
+{
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+
+  const ::internal::tflite::operand::Index ifm_index{node.param().ifm_index};
+  const ::internal::tflite::operand::Index indices_index{node.param().indices_index};
+
+  const ::internal::tflite::operand::Index axis_index{node.param().axis_index};
+
+  const auto ifm_shape = _ctx.at(ifm_index).shape();
+  const auto indices_shape = _ctx.at(indices_index).shape();
+  const auto axis_shape = _ctx.at(axis_index).shape();
+  const auto ofm_shape = _ctx.at(ofm_index).shape();
+
+  assert(ifm_shape.rank() <= 4);
+  assert(indices_shape.rank() <= 3);
+  assert(ofm_shape.rank() <= 4);
+  assert(_ctx.at(axis_index).hasData());
+  assert(axis_shape.rank() == 0);
+
+  // Set Shape Constraints
+  _builder.addShapeConstr(ofm_index,
+                          asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape(), false),
+                                       _ctx.at(ofm_index).type(), _ctx.at(ofm_index).scale(),
+                                       _ctx.at(ofm_index).zeroPoint()));
+  _builder.addShapeConstr(ifm_index,
+                          asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape(), false),
+                                       _ctx.at(ifm_index).type(), _ctx.at(ifm_index).scale(),
+                                       _ctx.at(ifm_index).zeroPoint()));
+  _builder.addShapeConstr(
+      indices_index, asTensorInfo(asTensorShape(_ctx.at(indices_index).shape(), false),
+                                  _ctx.at(indices_index).type(), _ctx.at(indices_index).scale(),
+                                  _ctx.at(indices_index).zeroPoint()));
+
+  const int32_t axis_value = static_cast<int>(_ctx.at(axis_index).asScalar<int32_t>());
+  const int axis = ToARMComputeAxis(ifm_shape.rank(), axis_value).value();
+
+  // Construct operation parameters
+  struct Param
+  {
+    int ofm_index;
+    int ifm_index;
+    int indices_index;
+
+    int axis;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.ifm_index = ifm_index.asInt();
+  param.indices_index = indices_index.asInt();
+
+  param.axis = axis;
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto ifm_alloc = ctx.at(::internal::tflite::operand::Index{param.ifm_index});
+    auto indices_alloc = ctx.at(::internal::tflite::operand::Index{param.indices_index});
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      std::unique_ptr<::arm_compute::IFunction> fn;
+
+      auto l = nnfw::cpp14::make_unique<GenericGather>();
+      l->configure(CAST_CL(ifm_alloc), CAST_CL(indices_alloc), CAST_CL(ofm_alloc), param.axis);
+      fn = std::move(l);
+      builder.append("Gather", std::move(fn));
+    }
+    else
+      throw std::runtime_error("Not supported, yet");
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::PReLU::Node &node)
+{
+  VERBOSE(PReLU) << "Configure PReLU operation" << std::endl;
+
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+  const ::internal::tflite::operand::Index ifm_index{node.param().ifm_index};
+  const ::internal::tflite::operand::Index alpha_index{node.param().alpha_index};
+
+  // Set Shape Constraints and TensorInfo
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+
+  if (!(_ctx.at(ifm_index).shape() == _ctx.at(alpha_index).shape()))
+  {
+    const auto broadcast_rank =
+        std::max(_ctx.at(ifm_index).shape().rank(), _ctx.at(alpha_index).shape().rank());
+    const_cast<::internal::tflite::operand::Shape &>(_ctx.at(ifm_index).shape())
+        .extendRank(broadcast_rank);
+    const_cast<::internal::tflite::operand::Shape &>(_ctx.at(alpha_index).shape())
+        .extendRank(broadcast_rank);
+  }
+  _builder.addShapeConstr(
+      ifm_index, asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape()), _ctx.at(ifm_index).type(),
+                              _ctx.at(ifm_index).scale(), _ctx.at(ifm_index).zeroPoint()));
+
+  _builder.addShapeConstr(alpha_index,
+                          asTensorInfo(asTensorShape(_ctx.at(alpha_index).shape()),
+                                       _ctx.at(alpha_index).type(), _ctx.at(alpha_index).scale(),
+                                       _ctx.at(alpha_index).zeroPoint()));
+
+  struct Param
+  {
+    int ofm_index;
+    int ifm_index;
+    int alpha_index;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.ifm_index = ifm_index.asInt();
+  param.alpha_index = alpha_index.asInt();
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto ifm_alloc = ctx.at(::internal::tflite::operand::Index{param.ifm_index});
+    auto alpha_alloc = ctx.at(::internal::tflite::operand::Index{param.alpha_index});
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLPReLU>();
+      fn->configure(CAST_CL(ifm_alloc), CAST_CL(alpha_alloc), CAST_CL(ofm_alloc));
+      builder.append("PReLU", std::move(fn));
+    }
+    else
+    {
+      // TODO Add NEON support
+
+      throw std::runtime_error("Not supported, yet");
+    }
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::ReLU::Node &node)
+{
+  VERBOSE(ReLU) << "Configure ReLU operation" << std::endl;
+
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+  const ::internal::tflite::operand::Index ifm_index{node.param().ifm_index};
+
+  // Set shape constraints
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+  _builder.addShapeConstr(
+      ifm_index, asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape()), _ctx.at(ifm_index).type(),
+                              _ctx.at(ifm_index).scale(), _ctx.at(ifm_index).zeroPoint()));
+
+  struct Param
+  {
+    int ofm_index;
+    int ifm_index;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.ifm_index = ifm_index.asInt();
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto ifm_alloc = ctx.at(::internal::tflite::operand::Index{param.ifm_index});
+
+    const ::arm_compute::ActivationLayerInfo act_info{
+        ::arm_compute::ActivationLayerInfo::ActivationFunction::RELU};
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLActivationLayer>();
+
+      fn->configure(CAST_CL(ifm_alloc), CAST_CL(ofm_alloc), act_info);
+
+      builder.append("ReLU", std::move(fn));
+    }
+    else
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::NEActivationLayer>();
+
+      fn->configure(ifm_alloc, ofm_alloc, act_info);
+
+      builder.append("ReLU", std::move(fn));
+    }
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::ReLU1::Node &node)
+{
+  VERBOSE(ReLU1) << "Configure ReLU1 operation" << std::endl;
+
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+  const ::internal::tflite::operand::Index ifm_index{node.param().ifm_index};
+
+  // Set shape constraints
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+  _builder.addShapeConstr(
+      ifm_index, asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape()), _ctx.at(ifm_index).type(),
+                              _ctx.at(ifm_index).scale(), _ctx.at(ifm_index).zeroPoint()));
+
+  struct Param
+  {
+    int ofm_index;
+    int ifm_index;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.ifm_index = ifm_index.asInt();
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto ifm_alloc = ctx.at(::internal::tflite::operand::Index{param.ifm_index});
+
+    const ::arm_compute::ActivationLayerInfo act_info{
+        ::arm_compute::ActivationLayerInfo::ActivationFunction::LU_BOUNDED_RELU, 1.0f, -1.0f};
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLActivationLayer>();
+
+      fn->configure(CAST_CL(ifm_alloc), CAST_CL(ofm_alloc), act_info);
+
+      builder.append("ReLU1", std::move(fn));
+    }
+    else
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::NEActivationLayer>();
+
+      fn->configure(ifm_alloc, ofm_alloc, act_info);
+
+      builder.append("ReLU1", std::move(fn));
+    }
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::ReLU6::Node &node)
+{
+  VERBOSE(ReLU6) << "Configure ReLU6 operation" << std::endl;
+
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+  const ::internal::tflite::operand::Index ifm_index{node.param().ifm_index};
+
+  // Set shape constraints
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+  _builder.addShapeConstr(
+      ifm_index, asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape()), _ctx.at(ifm_index).type(),
+                              _ctx.at(ifm_index).scale(), _ctx.at(ifm_index).zeroPoint()));
+
+  struct Param
+  {
+    int ofm_index;
+    int ifm_index;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.ifm_index = ifm_index.asInt();
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto ifm_alloc = ctx.at(::internal::tflite::operand::Index{param.ifm_index});
+
+    const ::arm_compute::ActivationLayerInfo act_info{
+        ::arm_compute::ActivationLayerInfo::ActivationFunction::BOUNDED_RELU, 6.0f};
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLActivationLayer>();
+
+      fn->configure(CAST_CL(ifm_alloc), CAST_CL(ofm_alloc), act_info);
+
+      builder.append("ReLU6", std::move(fn));
+    }
+    else
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::NEActivationLayer>();
+
+      fn->configure(ifm_alloc, ofm_alloc, act_info);
+
+      builder.append("ReLU6", std::move(fn));
+    }
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::Tanh::Node &node)
+{
+  VERBOSE(Tanh) << "Configure Tanh operation" << std::endl;
+
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+  const ::internal::tflite::operand::Index ifm_index{node.param().ifm_index};
+
+  // Set shape constraints
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+  _builder.addShapeConstr(
+      ifm_index, asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape()), _ctx.at(ifm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+
+  struct Param
+  {
+    int ofm_index;
+    int ifm_index;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.ifm_index = ifm_index.asInt();
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto ifm_alloc = ctx.at(::internal::tflite::operand::Index{param.ifm_index});
+
+    const ::arm_compute::ActivationLayerInfo act_info{
+        ::arm_compute::ActivationLayerInfo::ActivationFunction::TANH, 1.0f, 1.0f};
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLActivationLayer>();
+
+      fn->configure(CAST_CL(ifm_alloc), CAST_CL(ofm_alloc), act_info);
+
+      builder.append("Tanh", std::move(fn));
+    }
+    else
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::NEActivationLayer>();
+
+      fn->configure(ifm_alloc, ofm_alloc, act_info);
+
+      builder.append("Tanh", std::move(fn));
+    }
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::Logistic::Node &node)
+{
+  VERBOSE(Logistic) << "Configure Logistic operation" << std::endl;
+
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+  const ::internal::tflite::operand::Index ifm_index{node.param().ifm_index};
+
+  // Set shape constraints
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+  _builder.addShapeConstr(
+      ifm_index, asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape()), _ctx.at(ifm_index).type(),
+                              _ctx.at(ifm_index).scale(), _ctx.at(ifm_index).zeroPoint()));
+
+  struct Param
+  {
+    int ofm_index;
+    int ifm_index;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.ifm_index = ifm_index.asInt();
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto ifm_alloc = ctx.at(::internal::tflite::operand::Index{param.ifm_index});
+
+    const ::arm_compute::ActivationLayerInfo act_info{
+        ::arm_compute::ActivationLayerInfo::ActivationFunction::LOGISTIC};
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLActivationLayer>();
+
+      fn->configure(CAST_CL(ifm_alloc), CAST_CL(ofm_alloc), act_info);
+
+      builder.append("Logistic", std::move(fn));
+    }
+    else
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::NEActivationLayer>();
+
+      fn->configure(ifm_alloc, ofm_alloc, act_info);
+
+      builder.append("Logistic", std::move(fn));
+    }
+  };
+
+  _builder.addStage(stage);
+}
+
+// Reduce Mean
+void Planner::visit(const ::internal::tflite::op::Mean::Node &node)
+{
+  VERBOSE(Mean) << "Configure Mean operation" << std::endl;
+
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+  const ::internal::tflite::operand::Index ifm_index{node.param().ifm_index};
+  const ::internal::tflite::operand::Index axis_index{node.param().axis_index};
+  const ::internal::tflite::operand::Index keep_dims_index{node.param().keep_dims_index};
+  const int keep_dims = _ctx.at(keep_dims_index).asScalar<int>();
+
+  const auto ifm_shape = _ctx.at(ifm_index).shape();
+  const auto ofm_shape = _ctx.at(ofm_index).shape();
+
+  // NOTE For the 4-dimensions, if the rank of input and output are different, this runtime only
+  // supports cases reducing height and width or reducing depth.
+  // TODO We have to support all cases of dimensions up to 4.
+  // For correct permuting, we have to set output's shape to be equal in dimension position of the
+  // input. But the positions of the same dimensions in the input and output may be set differently.
+  // For example {2,3,4,5}(input's shape) can be reduced to {3,5}(output's shape). The original
+  // output shape should be {1,3,1,5}, but real output shape may be {3,5}. If you simply try to
+  // extend it in 4 dimensions, it should be {1,1,3,5}.
+  // Even if output shape is changed to {1,3,1,5}, there is another problem. It is that shape of
+  // output tensor used at next operation is changed to {1,3,1,5} after this operation even if the
+  // next operation is not desired.
+  if (ifm_shape.rank() == 4 && ifm_shape.rank() != ofm_shape.rank())
+  {
+    if (ofm_shape.rank() == 2)
+    {
+      // Reducing HW
+      assert(ifm_shape.dim(0) == ofm_shape.dim(0) && ifm_shape.dim(3) == ofm_shape.dim(1));
+    }
+    else if (ofm_shape.rank() == 3)
+    {
+      // Reducing C or
+      // (Reducing H and C(ifm and ofm) == 1) or (Reducing W and C(ifm and ofm) == 1)
+      assert(ifm_shape.dim(0) == ofm_shape.dim(0) && ifm_shape.dim(1) == ofm_shape.dim(1) &&
+                 ifm_shape.dim(2) == ofm_shape.dim(2) ||
+             (ifm_shape.dim(0) == ofm_shape.dim(0) &&
+              (ifm_shape.dim(1) == ofm_shape.dim(1) || ifm_shape.dim(2) == ofm_shape.dim(1)) &&
+              ifm_shape.dim(3) == 1 && ofm_shape.dim(2) == 1));
+    }
+  }
+
+  // Set shape constraints
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+  _builder.addShapeConstr(
+      ifm_index, asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape()), _ctx.at(ifm_index).type(),
+                              _ctx.at(ifm_index).scale(), _ctx.at(ifm_index).zeroPoint()));
+  _builder.addShapeConstr(axis_index,
+                          asTensorInfo(asTensorShape(_ctx.at(axis_index).shape()),
+                                       _ctx.at(axis_index).type(), _ctx.at(axis_index).scale(),
+                                       _ctx.at(axis_index).zeroPoint()));
+
+  std::set<uint32_t> axis;
+  {
+    const auto ifm_rank = ifm_shape.rank();
+    const auto axis_shape = _ctx.at(axis_index).shape();
+    switch (axis_shape.rank())
+    {
+      case 0: // scalar
+      {
+        int32_t axis_value = _ctx.at(axis_index).asScalar<int32_t>();
+        if (axis_value < 0)
+        {
+          axis_value += ifm_rank;
+        }
+        axis.insert(ToARMComputeAxis(ifm_rank, axis_value).value());
+        break;
+      }
+      case 1: // vector
+      {
+        const auto axis_base = _ctx.at(axis_index).data().base();
+        const auto axis_size = _ctx.at(axis_index).shape().asVector();
+
+        // If axis's data does not exist as constant values and can be gotten as input data, we have
+        // to find a way to infer output shape when sinking output.
+        assert(axis_base != nullptr);
+        for (uint32_t n = 0; n < axis_size; ++n)
+        {
+          int32_t axis_value = *(reinterpret_cast<const int32_t *>(axis_base) + n);
+          if (axis_value < 0)
+          {
+            axis_value += ifm_rank;
+          }
+          axis.insert(ToARMComputeAxis(ifm_rank, axis_value).value());
+        }
+        break;
+      }
+      default:
+        throw std::runtime_error("Not supported");
+        break;
+    }
+  }
+
+  struct Param
+  {
+    int ofm_index;
+    int ifm_index;
+    bool keep_dims;
+    std::set<uint32_t> axis;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.ifm_index = ifm_index.asInt();
+  param.keep_dims = keep_dims > 0 ? true : false;
+  param.axis = axis;
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto ifm_alloc = ctx.at(::internal::tflite::operand::Index{param.ifm_index});
+
+    ::arm_compute::Coordinates reduction_axis;
+    size_t i = 0;
+    for (auto index : param.axis)
+    {
+      reduction_axis.set(i++, index);
+    }
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLReduceMean>();
+
+      fn->configure(CAST_CL(ifm_alloc), reduction_axis, param.keep_dims, CAST_CL(ofm_alloc));
+
+      builder.append("Mean", std::move(fn));
+    }
+    else
+      throw std::runtime_error("Not supported, yet");
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::RNN::Node &node)
+{
+  const ::internal::tflite::operand::Index output_index{node.param().output_index};
+  const ::internal::tflite::operand::Index hidden_state_out_index{
+      node.param().hidden_state_out_index};
+
+  const ::internal::tflite::operand::Index input_index{node.param().input_index};
+  const ::internal::tflite::operand::Index weights_index{node.param().weights_index};
+  const ::internal::tflite::operand::Index recurrent_weights_index{
+      node.param().recurrent_weights_index};
+  const ::internal::tflite::operand::Index bias_index{node.param().bias_index};
+  const ::internal::tflite::operand::Index hidden_state_in_index{
+      node.param().hidden_state_in_index};
+  const ::internal::tflite::operand::Index fused_activation_index{
+      node.param().fused_activation_index};
+
+  assert(_ctx.at(output_index).shape().rank() == 2 &&
+         _ctx.at(hidden_state_out_index).shape().rank() == 2 &&
+         _ctx.at(input_index).shape().rank() == 2 && _ctx.at(weights_index).shape().rank() == 2 &&
+         _ctx.at(recurrent_weights_index).shape().rank() == 2 &&
+         _ctx.at(hidden_state_in_index).shape().rank() == 2);
+  assert(_ctx.at(bias_index).shape().rank() == 1);
+
+  const auto batch_size = _ctx.at(output_index).shape().dim(0);
+  assert(batch_size == _ctx.at(input_index).shape().dim(0) &&
+         batch_size == _ctx.at(hidden_state_in_index).shape().dim(0) &&
+         batch_size == _ctx.at(hidden_state_out_index).shape().dim(0));
+  assert(_ctx.at(input_index).shape().dim(1) == _ctx.at(weights_index).shape().dim(1));
+
+  const auto num_units = _ctx.at(output_index).shape().dim(1);
+  assert(num_units == _ctx.at(weights_index).shape().dim(0) &&
+         num_units == _ctx.at(recurrent_weights_index).shape().dim(0) &&
+         num_units == _ctx.at(bias_index).shape().dim(0));
+  assert(num_units == _ctx.at(output_index).shape().dim(1) &&
+         num_units == _ctx.at(recurrent_weights_index).shape().dim(1) &&
+         num_units == _ctx.at(hidden_state_in_index).shape().dim(1) &&
+         num_units == _ctx.at(hidden_state_out_index).shape().dim(1));
+
+  // Set Shape Constraints and TensorInfo
+  _builder.addShapeConstr(output_index,
+                          asTensorInfo(asTensorShape(_ctx.at(output_index).shape()),
+                                       _ctx.at(output_index).type(), _ctx.at(output_index).scale(),
+                                       _ctx.at(output_index).zeroPoint()));
+  _builder.addShapeConstr(hidden_state_out_index,
+                          asTensorInfo(asTensorShape(_ctx.at(hidden_state_out_index).shape()),
+                                       _ctx.at(hidden_state_out_index).type(),
+                                       _ctx.at(hidden_state_out_index).scale(),
+                                       _ctx.at(hidden_state_out_index).zeroPoint()));
+  _builder.addShapeConstr(input_index,
+                          asTensorInfo(asTensorShape(_ctx.at(input_index).shape()),
+                                       _ctx.at(input_index).type(), _ctx.at(input_index).scale(),
+                                       _ctx.at(input_index).zeroPoint()));
+  _builder.addShapeConstr(weights_index, asTensorInfo(asTensorShape(_ctx.at(weights_index).shape()),
+                                                      _ctx.at(weights_index).type(),
+                                                      _ctx.at(weights_index).scale(),
+                                                      _ctx.at(weights_index).zeroPoint()));
+  _builder.addShapeConstr(recurrent_weights_index,
+                          asTensorInfo(asTensorShape(_ctx.at(recurrent_weights_index).shape()),
+                                       _ctx.at(recurrent_weights_index).type(),
+                                       _ctx.at(recurrent_weights_index).scale(),
+                                       _ctx.at(recurrent_weights_index).zeroPoint()));
+  _builder.addShapeConstr(bias_index,
+                          asTensorInfo(asTensorShape(_ctx.at(bias_index).shape()),
+                                       _ctx.at(bias_index).type(), _ctx.at(bias_index).scale(),
+                                       _ctx.at(bias_index).zeroPoint()));
+  _builder.addShapeConstr(hidden_state_in_index,
+                          asTensorInfo(asTensorShape(_ctx.at(hidden_state_in_index).shape()),
+                                       _ctx.at(hidden_state_in_index).type(),
+                                       _ctx.at(hidden_state_in_index).scale(),
+                                       _ctx.at(hidden_state_in_index).zeroPoint()));
+
+  // Construct operation parameters
+  struct Param
+  {
+    int output_index;
+    int hidden_state_out_index;
+
+    int input_index;
+    int weights_index;
+    int recurrent_weights_index;
+    int bias_index;
+    int hidden_state_in_index;
+
+    FuseCode activation;
+  };
+
+  Param param;
+
+  param.output_index = output_index.asInt();
+  param.hidden_state_out_index = hidden_state_out_index.asInt();
+
+  param.input_index = input_index.asInt();
+  param.weights_index = weights_index.asInt();
+  param.recurrent_weights_index = recurrent_weights_index.asInt();
+  param.bias_index = bias_index.asInt();
+  param.hidden_state_in_index = hidden_state_in_index.asInt();
+  param.activation = static_cast<FuseCode>(_ctx.at(fused_activation_index).asScalar<int32_t>());
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto output_alloc = ctx.at(::internal::tflite::operand::Index{param.output_index});
+    auto hidden_state_out_alloc =
+        ctx.at(::internal::tflite::operand::Index{param.hidden_state_out_index});
+    auto input_alloc = ctx.at(::internal::tflite::operand::Index{param.input_index});
+    auto weights_alloc = ctx.at(::internal::tflite::operand::Index{param.weights_index});
+    auto recurrent_weights_alloc =
+        ctx.at(::internal::tflite::operand::Index{param.recurrent_weights_index});
+    auto bias_alloc = ctx.at(::internal::tflite::operand::Index{param.bias_index});
+    auto hidden_state_in_alloc =
+        ctx.at(::internal::tflite::operand::Index{param.hidden_state_in_index});
+    auto act_info = asActivationInfo(param.activation);
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      std::unique_ptr<::arm_compute::CLCopy> copy_fn{new ::arm_compute::CLCopy};
+      copy_fn->configure(CAST_CL(hidden_state_in_alloc), CAST_CL(hidden_state_out_alloc));
+      builder.append("COPY", std::move(copy_fn));
+
+      std::unique_ptr<::arm_compute::CLRNNLayer> rnn_fn{new ::arm_compute::CLRNNLayer};
+
+      // The hidden_state_in's data must be copied to hidden_state_out_alloc before fn->run() is
+      // performed.
+      rnn_fn->configure(CAST_CL(input_alloc), CAST_CL(weights_alloc),
+                        CAST_CL(recurrent_weights_alloc), CAST_CL(bias_alloc),
+                        CAST_CL(hidden_state_out_alloc), CAST_CL(output_alloc), act_info);
+
+      builder.append("RNN", std::move(rnn_fn));
+    }
+    else
+      throw std::runtime_error("Not supported, yet");
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::LSTM::Node &node)
+{
+  // TODO Implement LSTM op
+  throw std::runtime_error("Not supported, yet");
+}
+
+void Planner::visit(const ::internal::tflite::op::Transpose::Node &node)
+{
+  VERBOSE(Transpose) << "Configure Transpose operation" << std::endl;
+
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+  const ::internal::tflite::operand::Index ifm_index{node.param().ifm_index};
+  const ::internal::tflite::operand::Index permu_index{node.param().permu_index};
+
+  assert(_ctx.at(ifm_index).shape().rank() == _ctx.at(ofm_index).shape().rank());
+  assert(_ctx.at(permu_index).hasData() == true);
+
+  // Set shape constraints
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+  _builder.addShapeConstr(
+      ifm_index, asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape()), _ctx.at(ifm_index).type(),
+                              _ctx.at(ifm_index).scale(), _ctx.at(ifm_index).zeroPoint()));
+
+  struct Param
+  {
+    int ofm_index;
+    int ifm_index;
+    const int32_t *pv;
+    int rank;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.ifm_index = ifm_index.asInt();
+  param.pv = reinterpret_cast<const int32_t *>(_ctx.at(permu_index).data().base());
+  param.rank = _ctx.at(ifm_index).shape().rank();
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    const auto ifm_alloc = ctx.at(::internal::tflite::operand::Index{param.ifm_index});
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLPermute>();
+
+      fn->configure(CAST_CL(ifm_alloc), CAST_CL(ofm_alloc),
+                    getARMComputePermutationVector(param.rank, param.pv));
+
+      builder.append("Transpose", std::move(fn));
+    }
+    else
+    {
+      throw std::runtime_error("Not supported, yet");
+    }
+
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::Floor::Node &node)
+{
+  VERBOSE(Floor) << "Configure Floor operation" << std::endl;
+
+  const ::internal::tflite::operand::Index ofm_index{node.param().output_index};
+  const ::internal::tflite::operand::Index ifm_index{node.param().input_index};
+
+  // Set shape constraints
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+  _builder.addShapeConstr(
+      ifm_index, asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape()), _ctx.at(ifm_index).type(),
+                              _ctx.at(ifm_index).scale(), _ctx.at(ifm_index).zeroPoint()));
+
+  struct Param
+  {
+    int ofm_index;
+    int ifm_index;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.ifm_index = ifm_index.asInt();
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto ifm_alloc = ctx.at(::internal::tflite::operand::Index{param.ifm_index});
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLFloor>();
+
+      fn->configure(CAST_CL(ifm_alloc), CAST_CL(ofm_alloc));
+
+      builder.append("Floor", std::move(fn));
+    }
+    else
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::NEFloor>();
+
+      fn->configure(ifm_alloc, ofm_alloc);
+
+      builder.append("Floor", std::move(fn));
+    }
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::ArgMax::Node &node)
+{
+  VERBOSE(ArgMax) << "Configure ARGMAX operation" << std::endl;
+
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+  const ::internal::tflite::operand::Index ifm_index{node.param().ifm_index};
+  const ::internal::tflite::operand::Index axis_index{node.param().axis_index};
+
+  auto ifm_shape = _ctx.at(ifm_index).shape();
+  auto ofm_shape = _ctx.at(ofm_index).shape();
+  auto axis_shape = _ctx.at(axis_index).shape();
+
+  assert(_ctx.at(axis_index).hasData());
+  // Axis dimension is always 1.
+  assert(axis_shape.rank() == 1);
+  assert((ifm_shape.rank() - 1) == ofm_shape.rank());
+
+  _builder.addShapeConstr(ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape(), false),
+                                                  _ctx.at(ofm_index).type()));
+  _builder.addShapeConstr(ifm_index, asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape(), false),
+                                                  _ctx.at(ifm_index).type()));
+
+  std::vector<uint32_t> l_axis;
+  const auto axis_size = _ctx.at(axis_index).shape().asVector();
+  auto axis_base = _ctx.at(axis_index).data().base();
+  auto axis_type = _ctx.at(axis_index).type();
+  // TODO Should support axis size > 1.
+  assert(axis_size == 1);
+  // axis is tensor with 1 dimension - always a vector.
+  assert(axis_base != nullptr);
+  for (uint32_t n = 0; n < axis_size; ++n)
+  {
+    int32_t axis_value = *(reinterpret_cast<const int32_t *>(axis_base) + n);
+    if (axis_value < 0)
+    {
+      axis_value += ifm_shape.rank();
+    }
+    l_axis.push_back(ToARMComputeAxis(ifm_shape.rank(), axis_value).value());
+  }
+
+  // Construct operation parameters
+  struct Param
+  {
+    int ofm_index;
+    int ifm_index;
+    std::vector<uint32_t> axis;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.ifm_index = ifm_index.asInt();
+  param.axis = l_axis;
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto ifm_alloc = ctx.at(::internal::tflite::operand::Index{param.ifm_index});
+
+    {
+
+      if (::internal::arm_compute::isGpuMode())
+      {
+        auto fn = nnfw::cpp14::make_unique<::arm_compute::CLArgOperation>();
+
+        fn->configure(CAST_CL(ifm_alloc), CAST_CL(ofm_alloc), param.axis,
+                      ::arm_compute::ArgOperation::MAX);
+
+        builder.append("ArgMax", std::move(fn));
+      }
+      else
+        throw std::runtime_error("Not supported, yet");
+    }
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::SQRT::Node &node)
+{
+  VERBOSE(SQRT) << "Configure SQRT operation" << std::endl;
+
+  const ::internal::tflite::operand::Index output_index{node.param().output_index};
+  const ::internal::tflite::operand::Index input_index{node.param().input_index};
+
+  // Set shape constraints
+  _builder.addShapeConstr(output_index,
+                          asTensorInfo(asTensorShape(_ctx.at(output_index).shape()),
+                                       _ctx.at(output_index).type(), _ctx.at(output_index).scale(),
+                                       _ctx.at(output_index).zeroPoint()));
+  _builder.addShapeConstr(input_index,
+                          asTensorInfo(asTensorShape(_ctx.at(input_index).shape()),
+                                       _ctx.at(input_index).type(), _ctx.at(input_index).scale(),
+                                       _ctx.at(input_index).zeroPoint()));
+
+  struct Param
+  {
+    int output_index;
+    int input_index;
+  };
+
+  Param param;
+
+  param.output_index = output_index.asInt();
+  param.input_index = input_index.asInt();
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto output_alloc = ctx.at(::internal::tflite::operand::Index{param.output_index});
+    auto input_alloc = ctx.at(::internal::tflite::operand::Index{param.input_index});
+
+    const ::arm_compute::ActivationLayerInfo act_info{
+        ::arm_compute::ActivationLayerInfo::ActivationFunction::SQRT};
+
+    {
+      if (::internal::arm_compute::isGpuMode())
+      {
+        auto fn = nnfw::cpp14::make_unique<::arm_compute::CLActivationLayer>();
+
+        fn->configure(CAST_CL(input_alloc), CAST_CL(output_alloc), act_info);
+
+        builder.append("SQRT", std::move(fn));
+      }
+      else
+      {
+        auto fn = nnfw::cpp14::make_unique<::arm_compute::NEActivationLayer>();
+
+        fn->configure(input_alloc, output_alloc, act_info);
+
+        builder.append("SQRT", std::move(fn));
+      }
+    }
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::RSQRT::Node &node)
+{
+  VERBOSE(RSQRT) << "Configure Rsqrt operation" << std::endl;
+
+  const ::internal::tflite::operand::Index output_index{node.param().output_index};
+  const ::internal::tflite::operand::Index input_index{node.param().input_index};
+
+  // Set shape constraints
+  _builder.addShapeConstr(output_index,
+                          asTensorInfo(asTensorShape(_ctx.at(output_index).shape()),
+                                       _ctx.at(output_index).type(), _ctx.at(output_index).scale(),
+                                       _ctx.at(output_index).zeroPoint()));
+  _builder.addShapeConstr(input_index,
+                          asTensorInfo(asTensorShape(_ctx.at(input_index).shape()),
+                                       _ctx.at(input_index).type(), _ctx.at(input_index).scale(),
+                                       _ctx.at(input_index).zeroPoint()));
+
+  struct Param
+  {
+    int output_index;
+    int input_index;
+  };
+
+  Param param;
+
+  param.output_index = output_index.asInt();
+  param.input_index = input_index.asInt();
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto output_alloc = ctx.at(::internal::tflite::operand::Index{param.output_index});
+    auto input_alloc = ctx.at(::internal::tflite::operand::Index{param.input_index});
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLRsqrtLayer>();
+
+      fn->configure(CAST_CL(input_alloc), CAST_CL(output_alloc));
+
+      builder.append("RSQRT", std::move(fn));
+    }
+    else
+      throw std::runtime_error("Not supported, yet");
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::Equal::Node &node)
+{
+  const ::internal::tflite::operand::Index output_index{node.param().output_index};
+  const ::internal::tflite::operand::Index input1_index{node.param().input1_index};
+  const ::internal::tflite::operand::Index input2_index{node.param().input2_index};
+
+  // Set Shape Constraints and TensorInfo
+  _builder.addShapeConstr(output_index,
+                          asTensorInfo(asTensorShape(_ctx.at(output_index).shape()),
+                                       _ctx.at(output_index).type(), _ctx.at(output_index).scale(),
+                                       _ctx.at(output_index).zeroPoint()));
+
+  if (!(_ctx.at(input1_index).shape() == _ctx.at(input2_index).shape()))
+  {
+    const auto broadcast_rank =
+        std::max(_ctx.at(input1_index).shape().rank(), _ctx.at(input2_index).shape().rank());
+    const_cast<::internal::tflite::operand::Shape &>(_ctx.at(input1_index).shape())
+        .extendRank(broadcast_rank);
+    const_cast<::internal::tflite::operand::Shape &>(_ctx.at(input2_index).shape())
+        .extendRank(broadcast_rank);
+  }
+  _builder.addShapeConstr(input1_index,
+                          asTensorInfo(asTensorShape(_ctx.at(input1_index).shape()),
+                                       _ctx.at(input1_index).type(), _ctx.at(input1_index).scale(),
+                                       _ctx.at(input1_index).zeroPoint()));
+  _builder.addShapeConstr(input2_index,
+                          asTensorInfo(asTensorShape(_ctx.at(input2_index).shape()),
+                                       _ctx.at(input2_index).type(), _ctx.at(input2_index).scale(),
+                                       _ctx.at(input2_index).zeroPoint()));
+
+  // Construct operation parameters
+  struct Param
+  {
+    int output_index;
+    int input1_index;
+    int input2_index;
+  };
+
+  Param param;
+
+  param.output_index = output_index.asInt();
+  param.input1_index = input1_index.asInt();
+  param.input2_index = input2_index.asInt();
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto output_alloc = ctx.at(::internal::tflite::operand::Index{param.output_index});
+    auto input1_alloc = ctx.at(::internal::tflite::operand::Index{param.input1_index});
+    auto input2_alloc = ctx.at(::internal::tflite::operand::Index{param.input2_index});
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLComparison>();
+
+      fn->configure(CAST_CL(input1_alloc), CAST_CL(input2_alloc), CAST_CL(output_alloc),
+                    ::arm_compute::ComparisonOperation::Equal);
+
+      builder.append("Equal", std::move(fn));
+    }
+    else
+    {
+      // TODO Add NEON support
+
+      throw std::runtime_error("Not supported, yet");
+    }
+  };
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::TransposeConv::Node &node)
+{
+  VERBOSE(TransposeConv) << "Configure TransposeConv operation" << std::endl;
+
+  const ::internal::tflite::operand::Index op_shape_index{node.param().op_shape_index};
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+  const ::internal::tflite::operand::Index ifm_index{node.param().ifm_index};
+  const ::internal::tflite::operand::Index ker_index{node.param().ker_index};
+
+  const ::internal::tflite::operand::Index padding_index{node.param().padding_index};
+  const ::internal::tflite::operand::Index hstride_index{node.param().hstride_index};
+  const ::internal::tflite::operand::Index vstride_index{node.param().vstride_index};
+
+  // Only 4D tensors are supported
+  assert(_ctx.at(ofm_index).shape().rank() == 4);
+  assert(_ctx.at(ofm_index).shape().rank() == _ctx.at(ifm_index).shape().rank());
+  assert(_ctx.at(ofm_index).shape().rank() == _ctx.at(ker_index).shape().rank());
+
+  const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature();
+  const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature();
+  const auto ker_shape = _ctx.at(ker_index).shape().asFeature();
+
+  assert(_ctx.at(padding_index).hasData() == true);
+
+  const int32_t vstride = _ctx.at(vstride_index).asScalar<int32_t>();
+  const int32_t hstride = _ctx.at(hstride_index).asScalar<int32_t>();
+
+  const PaddingCode padding_type =
+      static_cast<PaddingCode>(_ctx.at(padding_index).asScalar<int32_t>());
+
+  assert(vstride > 0);
+  assert(hstride > 0);
+  assert((ANEURALNETWORKS_PADDING_SAME == padding_type) ||
+         (ANEURALNETWORKS_PADDING_VALID == padding_type));
+  assert(ifm_shape.N == ofm_shape.N);
+  assert(ifm_shape.C == ker_shape.C);
+  assert(ker_shape.N == ofm_shape.C);
+
+  // Set Shape Constraints and TensorInfo
+  _builder.addShapeConstr(
+      ifm_index, asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape()), _ctx.at(ifm_index).type(),
+                              _ctx.at(ifm_index).scale(), _ctx.at(ifm_index).zeroPoint()));
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+  _builder.addShapeConstr(
+      ker_index, asTensorInfo(asTensorShape(_ctx.at(ker_index).shape()), _ctx.at(ker_index).type(),
+                              _ctx.at(ker_index).scale(), _ctx.at(ker_index).zeroPoint()));
+
+  // Construct operation parameters
+  struct Param
+  {
+    int ofm_index;
+    int ifm_index;
+    int ker_index;
+    Padding padding;
+    Stride stride;
+    uint32_t invalid_horizontal;
+    uint32_t invalid_vertical;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.ifm_index = ifm_index.asInt();
+  param.ker_index = ker_index.asInt();
+
+  param.stride.horizontal = hstride;
+  param.stride.vertical = vstride;
+
+  param.padding = (padding_type == ANEURALNETWORKS_PADDING_SAME)
+                      ? same_padding(ofm_shape, ifm_shape, param.stride, ker_shape.W, ker_shape.H)
+                      : valid_padding();
+
+  param.invalid_horizontal =
+      (padding_type == ANEURALNETWORKS_PADDING_SAME)
+          ? 0
+          : ofm_shape.W - (1 + (ifm_shape.W - 1) * hstride) - (ker_shape.W - 1);
+  param.invalid_vertical =
+      (padding_type == ANEURALNETWORKS_PADDING_SAME)
+          ? 0
+          : ofm_shape.H - (1 + (ifm_shape.H - 1) * param.stride.vertical) - (ker_shape.H - 1);
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto ifm_alloc = ctx.at(::internal::tflite::operand::Index{param.ifm_index});
+    auto ker_alloc = ctx.at(::internal::tflite::operand::Index{param.ker_index});
+
+    // Only rank 4 is supported
+    const int rank = 4;
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLTransposeConvLayer>();
+
+      auto symmetric_tconv_info = asPadStrideInfo(param.padding, param.stride);
+
+      // TODO Support WeightInfo in some cases in order to performance improvement
+      fn->configure(CAST_CL(ifm_alloc), CAST_CL(ker_alloc), nullptr, CAST_CL(ofm_alloc),
+                    symmetric_tconv_info, param.invalid_horizontal, param.invalid_vertical);
+      builder.append("TransposeConv", std::move(fn));
+    }
+    else
+    {
+      throw std::runtime_error("Not supported, yet");
+    }
+  };
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::SquaredDifference::Node &node)
+{
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+  const ::internal::tflite::operand::Index lhs_index{node.param().lhs_index};
+  const ::internal::tflite::operand::Index rhs_index{node.param().rhs_index};
+
+  // Set Shape Constraints and TensorInfo
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+
+  if (!(_ctx.at(lhs_index).shape() == _ctx.at(rhs_index).shape()))
+  {
+    const auto broadcast_rank =
+        std::max(_ctx.at(lhs_index).shape().rank(), _ctx.at(rhs_index).shape().rank());
+    const_cast<::internal::tflite::operand::Shape &>(_ctx.at(lhs_index).shape())
+        .extendRank(broadcast_rank);
+    const_cast<::internal::tflite::operand::Shape &>(_ctx.at(rhs_index).shape())
+        .extendRank(broadcast_rank);
+  }
+  _builder.addShapeConstr(
+      lhs_index, asTensorInfo(asTensorShape(_ctx.at(lhs_index).shape()), _ctx.at(lhs_index).type(),
+                              _ctx.at(lhs_index).scale(), _ctx.at(lhs_index).zeroPoint()));
+  _builder.addShapeConstr(
+      rhs_index, asTensorInfo(asTensorShape(_ctx.at(rhs_index).shape()), _ctx.at(rhs_index).type(),
+                              _ctx.at(rhs_index).scale(), _ctx.at(rhs_index).zeroPoint()));
+
+  // Construct operation parameters
+  struct Param
+  {
+    int ofm_index;
+    int lhs_index;
+    int rhs_index;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.lhs_index = lhs_index.asInt();
+  param.rhs_index = rhs_index.asInt();
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto lhs_alloc = ctx.at(::internal::tflite::operand::Index{param.lhs_index});
+    auto rhs_alloc = ctx.at(::internal::tflite::operand::Index{param.rhs_index});
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLElementwiseSquaredDiff>();
+
+      fn->configure(CAST_CL(lhs_alloc), CAST_CL(rhs_alloc), CAST_CL(ofm_alloc));
+      builder.append("SquaredDifference", std::move(fn));
+    }
+    else
+    {
+      // TODO Enable NEON Support
+      throw std::runtime_error("Not supported, yet");
+    }
+
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::Split::Node &node)
+{
+  VERBOSE(Split) << "Configure Split operation" << std::endl;
+
+  const ::internal::tflite::operand::Index axis_index{node.param().axis_index};
+  const ::internal::tflite::operand::Index ifm_index{node.param().ifm_index};
+
+  const auto ifm_shape = _ctx.at(ifm_index).shape();
+  int32_t axis = _ctx.at(axis_index).asScalar<int32_t>();
+
+  // Handle negative axis
+  if (axis < 0)
+  {
+    axis += ifm_shape.rank();
+  }
+
+  const int32_t num_split = node.param().ofm_indexes.size();
+  const auto input_size = ifm_shape.dim(axis);
+  assert(input_size % num_split == 0);
+  const int32_t slice_size = input_size / num_split;
+
+  // Set Shape Constraints and TensorInfo (for input)
+  _builder.addShapeConstr(ifm_index, asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape()),
+                                                  _ctx.at(ifm_index).type()));
+
+  // Set Shape Constraints and TensorInfo (for output)
+  const auto rank = ifm_shape.rank();
+  const uint32_t coord_index = ToARMComputeAxis(rank, axis).value();
+  uint32_t depth = 0;
+
+  ::arm_compute::Coordinates coordinates;
+  coordinates.set_num_dimensions(rank);
+
+  for (const auto &index : node.param().ofm_indexes)
+  {
+    const ::internal::tflite::operand::Index ofm_index{index};
+
+    coordinates[coord_index] = depth;
+
+    _builder.addSubsumptionConstr(ofm_index, ifm_index, coordinates,
+                                  asTensorShape(_ctx.at(ofm_index).shape()), true);
+    depth += slice_size;
+  }
+
+  // NOTE Split has no actual operation!
+}
+
+void Planner::visit(const ::internal::tflite::op::Pad::Node &node)
+{
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+  const ::internal::tflite::operand::Index ifm_index{node.param().ifm_index};
+  const ::internal::tflite::operand::Index paddings_index{node.param().paddings_index};
+
+  assert(_ctx.at(paddings_index).hasData() == true);
+
+  // Set Shape Constraints and TensorInfo
+  _builder.addShapeConstr(ifm_index,
+                          asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape(), false),
+                                       _ctx.at(ifm_index).type(), _ctx.at(ifm_index).scale(),
+                                       _ctx.at(ifm_index).zeroPoint()));
+  _builder.addShapeConstr(ofm_index,
+                          asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape(), false),
+                                       _ctx.at(ofm_index).type(), _ctx.at(ofm_index).scale(),
+                                       _ctx.at(ofm_index).zeroPoint()));
+  _builder.addShapeConstr(
+      paddings_index, asTensorInfo(asTensorShape(_ctx.at(paddings_index).shape(), false),
+                                   _ctx.at(paddings_index).type(), _ctx.at(paddings_index).scale(),
+                                   _ctx.at(paddings_index).zeroPoint()));
+
+  // Construct operation parameters
+  struct Param
+  {
+    int ofm_index;
+    int ifm_index;
+    ::arm_compute::PixelValue pixel_value;
+    ::arm_compute::PaddingList padding_list;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.ifm_index = ifm_index.asInt();
+
+  // initializer for padding
+  auto rank = _ctx.at(ifm_index).shape().rank();
+  auto pad_type = _ctx.at(paddings_index).type();
+
+  if (pad_type == ANEURALNETWORKS_TENSOR_INT32)
+  {
+    auto pad_base = _ctx.at(paddings_index).data().base();
+    auto pad_shape = _ctx.at(paddings_index).shape();
+
+    param.padding_list.resize(rank);
+    for (int32_t n = 0; n < rank; ++n)
+    {
+      const int32_t *from = reinterpret_cast<const int32_t *>(pad_base) + (n * pad_shape.dim(1));
+      auto axis = ToARMComputeAxis(rank, n).value();
+
+      param.padding_list[axis] = ::arm_compute::PaddingInfo{from[0], from[1]};
+    }
+    auto data_type = asDataType(_ctx.at(ifm_index).type());
+    auto quant_info =
+        asQuantizationInfo(_ctx.at(ifm_index).scale(), _ctx.at(ifm_index).zeroPoint());
+    param.pixel_value = ::arm_compute::PixelValue{0, data_type, quant_info};
+  }
+  else
+  {
+    throw std::runtime_error("Only Int32 datatype is supported for Pad values");
+  }
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto ifm_alloc = ctx.at(::internal::tflite::operand::Index{param.ifm_index});
+
+    {
+      if (::internal::arm_compute::isGpuMode()) // GPU
+      {
+        auto fn = nnfw::cpp14::make_unique<::arm_compute::CLPadLayer>();
+
+        fn->configure(CAST_CL(ifm_alloc), CAST_CL(ofm_alloc), param.padding_list,
+                      param.pixel_value);
+
+        builder.append("PAD", std::move(fn));
+      }
+      else // NEON
+      {
+        // TODO Enable NEON Support
+        throw std::runtime_error("Not supported, yet");
+      }
+    }
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::SpaceToDepth::Node &node)
+{
+  const ::internal::tflite::operand::Index output_index{node.param().output_index};
+  const ::internal::tflite::operand::Index input_index{node.param().input_index};
+  const ::internal::tflite::operand::Index block_size_index{node.param().block_size_index};
+
+  const auto input_batch = _ctx.at(input_index).shape().dim(0);
+  const auto output_batch = _ctx.at(output_index).shape().dim(0);
+  const auto input_depth = _ctx.at(input_index).shape().dim(3);
+  const auto output_depth = _ctx.at(output_index).shape().dim(3);
+  const auto block_size = _ctx.at(block_size_index).asScalar<int32_t>();
+  const auto input_height = _ctx.at(input_index).shape().dim(1);
+  const auto input_width = _ctx.at(input_index).shape().dim(2);
+
+  // All assertions as per NNAPI specification.
+  assert(_ctx.at(input_index).shape().rank() == 4);
+  assert(_ctx.at(output_index).shape().rank() == 4);
+  assert((block_size >= 1) && (input_height % block_size == 0) && (input_width % block_size == 0));
+  assert(input_batch == output_batch);
+  assert(input_depth * block_size * block_size == output_depth);
+
+  // Set Shape Constraints and TensorInfo
+  _builder.addShapeConstr(output_index,
+                          asTensorInfo(asTensorShape(_ctx.at(output_index).shape(), false),
+                                       _ctx.at(output_index).type(), _ctx.at(output_index).scale(),
+                                       _ctx.at(output_index).zeroPoint()));
+  _builder.addShapeConstr(input_index,
+                          asTensorInfo(asTensorShape(_ctx.at(input_index).shape(), false),
+                                       _ctx.at(input_index).type(), _ctx.at(input_index).scale(),
+                                       _ctx.at(input_index).zeroPoint()));
+
+  // Construct operation parameters
+  struct Param
+  {
+    int output_index;
+    int input_index;
+    int32_t block_size;
+  };
+
+  Param param;
+
+  param.output_index = output_index.asInt();
+  param.input_index = input_index.asInt();
+  param.block_size = block_size;
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto output_alloc = ctx.at(::internal::tflite::operand::Index{param.output_index});
+    auto input_alloc = ctx.at(::internal::tflite::operand::Index{param.input_index});
+
+    {
+      if (::internal::arm_compute::isGpuMode()) // GPU
+      {
+        auto fn = nnfw::cpp14::make_unique<::arm_compute::CLSpaceToDepth>();
+
+        fn->configure(CAST_CL(input_alloc), CAST_CL(output_alloc), param.block_size);
+
+        builder.append("SpaceToDepth", std::move(fn));
+      }
+      else // NEON
+      {
+        // TODO Enable NEON Support
+        throw std::runtime_error("Not supported, yet");
+      }
+    }
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::SpaceToBatchND::Node &node)
+{
+  const ::internal::tflite::operand::Index output_index{node.param().output_index};
+  const ::internal::tflite::operand::Index input_index{node.param().input_index};
+  const ::internal::tflite::operand::Index block_size_index{node.param().block_size_index};
+  const ::internal::tflite::operand::Index padding_size_index{node.param().padding_size_index};
+
+  const auto &output_shape = _ctx.at(output_index).shape();
+  const auto &input_shape = _ctx.at(input_index).shape();
+  const auto &padding_size_shape = _ctx.at(padding_size_index).shape();
+  auto block_size_base = reinterpret_cast<const int32_t *>(_ctx.at(block_size_index).data().base());
+  auto padding_size_base =
+      reinterpret_cast<const int32_t *>(_ctx.at(padding_size_index).data().base());
+
+  { // New block for assertions
+    const auto &block_size_shape = _ctx.at(block_size_index).shape();
+
+    // Currently, only 4D NHWC input/output op_context are supported.
+    // The 4D array need to have exactly 2 spatial dimensions.
+    // TODO: Support arbitrary dimension in SpaceToBatchND.
+    assert(input_shape.rank() == 4);
+    assert(output_shape.rank() == 4);
+    assert(block_size_shape.rank() == 1);
+    assert(padding_size_shape.rank() == 2);
+
+    assert(output_shape.dim(3) == input_shape.dim(3));
+    assert(block_size_shape.dim(0) == 2);
+    assert(padding_size_shape.dim(0) == 2);
+    assert(padding_size_shape.dim(1) == 2);
+
+    assert(_ctx.at(block_size_index).hasData() && _ctx.at(padding_size_index).hasData());
+    assert(_ctx.at(block_size_index).type() == ANEURALNETWORKS_TENSOR_INT32);
+    assert(_ctx.at(padding_size_index).type() == ANEURALNETWORKS_TENSOR_INT32);
+
+    assert(block_size_base[0] > 0 && block_size_base[1] > 0);
+    assert(output_shape.dim(0) == input_shape.dim(0) * block_size_base[0] * block_size_base[1]);
+    assert(output_shape.dim(1) ==
+           (input_shape.dim(1) + padding_size_base[0] + padding_size_base[1]) / block_size_base[0]);
+    assert(output_shape.dim(2) ==
+           (input_shape.dim(2) + padding_size_base[2] + padding_size_base[3]) / block_size_base[1]);
+  }
+
+  // Set Shape Constraints and TensorInfo
+  _builder.addShapeConstr(output_index,
+                          asTensorInfo(asTensorShape(_ctx.at(output_index).shape(), false),
+                                       _ctx.at(output_index).type(), _ctx.at(output_index).scale(),
+                                       _ctx.at(output_index).zeroPoint()));
+  _builder.addShapeConstr(input_index,
+                          asTensorInfo(asTensorShape(_ctx.at(input_index).shape(), false),
+                                       _ctx.at(input_index).type(), _ctx.at(input_index).scale(),
+                                       _ctx.at(input_index).zeroPoint()));
+
+  _builder.addShapeConstr(block_size_index,
+                          asTensorInfo(asTensorShape(_ctx.at(block_size_index).shape()),
+                                       _ctx.at(block_size_index).type(),
+                                       _ctx.at(block_size_index).scale(),
+                                       _ctx.at(block_size_index).zeroPoint()));
+
+  _builder.addShapeConstr(padding_size_index,
+                          asTensorInfo(asTensorShape(_ctx.at(padding_size_index).shape()),
+                                       _ctx.at(padding_size_index).type(),
+                                       _ctx.at(padding_size_index).scale(),
+                                       _ctx.at(padding_size_index).zeroPoint()));
+
+  { // Append block_size initializer
+    auto initializer = [block_size_base](::arm_compute::ITensor &tensor) {
+      const auto block_size_y = block_size_base[0];
+      const auto block_size_x = block_size_base[1];
+
+      auto into = reinterpret_cast<int32_t *>(tensor.ptr_to_element({0}));
+      into[0] = block_size_x;
+      into[1] = block_size_y;
+    };
+    _builder.addInitializer(block_size_index, initializer);
+  }
+
+  { // Append padding_size initializer
+    auto initializer = [padding_size_base, padding_size_shape](::arm_compute::ITensor &tensor) {
+      // If n == 0, then the axis is the height
+      // If n == 1, then the axis is the width
+      for (size_t n = 0; n < padding_size_shape.dim(0); ++n)
+      {
+        const auto from = padding_size_base + (n * padding_size_shape.dim(1));
+        auto into = reinterpret_cast<int32_t *>(tensor.ptr_to_element({0, 1 - n}));
+        into[0] = from[0];
+        into[1] = from[1];
+      }
+    };
+    _builder.addInitializer(padding_size_index, initializer);
+  }
+
+  // Construct operation parameters
+  struct Param
+  {
+    int output_index;
+    int input_index;
+    int block_size_index;
+    int padding_size_index;
+    int32_t rank;
+  };
+
+  Param param;
+
+  param.output_index = output_index.asInt();
+  param.input_index = input_index.asInt();
+  param.block_size_index = block_size_index.asInt();
+  param.padding_size_index = padding_size_index.asInt();
+  param.rank = _ctx.at(input_index).shape().rank();
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto output_alloc = ctx.at(::internal::tflite::operand::Index{param.output_index});
+    auto input_alloc = ctx.at(::internal::tflite::operand::Index{param.input_index});
+    auto block_size_alloc = ctx.at(::internal::tflite::operand::Index{param.block_size_index});
+    auto padding_size_alloc = ctx.at(::internal::tflite::operand::Index{param.padding_size_index});
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLSpaceToBatchND>();
+
+      fn->configure(CAST_CL(input_alloc), CAST_CL(block_size_alloc), CAST_CL(padding_size_alloc),
+                    CAST_CL(output_alloc));
+      builder.append("SpaceToBatchND", std::move(fn));
+    }
+    else
+    {
+      // TODO Enable NEON Support
+      throw std::runtime_error("Not supported, yet");
+    }
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::BatchToSpaceNd::Node &node)
+{
+  const ::internal::tflite::operand::Index output_index{node.param().output_index};
+  const ::internal::tflite::operand::Index input_index{node.param().input_index};
+  const ::internal::tflite::operand::Index block_size_index{node.param().block_size_index};
+
+  assert(_ctx.at(input_index).shape().rank() == 4);
+  assert(_ctx.at(output_index).shape().rank() == 4);
+  assert(_ctx.at(block_size_index).shape().rank() == 1);
+  assert(_ctx.at(block_size_index).hasData() == true);
+
+  const int32_t *block_size =
+      reinterpret_cast<const int32_t *>(_ctx.at(block_size_index).data().base());
+
+  const auto &output_shape = _ctx.at(output_index).shape();
+  const auto &input_shape = _ctx.at(input_index).shape();
+  const auto &block_size_shape = _ctx.at(block_size_index).shape();
+
+  // Set Shape Constraints and TensorInfo
+  _builder.addShapeConstr(
+      output_index, asTensorInfo(asTensorShape(output_shape, false), _ctx.at(output_index).type(),
+                                 _ctx.at(output_index).scale(), _ctx.at(output_index).zeroPoint()));
+  _builder.addShapeConstr(
+      input_index, asTensorInfo(asTensorShape(input_shape, false), _ctx.at(input_index).type(),
+                                _ctx.at(input_index).scale(), _ctx.at(input_index).zeroPoint()));
+
+  _builder.addShapeConstr(block_size_index, asTensorInfo(asTensorShape(block_size_shape),
+                                                         _ctx.at(block_size_index).type(),
+                                                         _ctx.at(block_size_index).scale(),
+                                                         _ctx.at(block_size_index).zeroPoint()));
+
+  // initializer for block_size
+  {
+    const auto block_size_base =
+        reinterpret_cast<const int32_t *>(_ctx.at(block_size_index).data().base());
+
+    assert(output_shape.dim(3) == input_shape.dim(3));
+    assert(output_shape.dim(1) == input_shape.dim(1) * block_size_base[0]);
+    assert(output_shape.dim(2) == input_shape.dim(2) * block_size_base[1]);
+    assert(output_shape.dim(0) == input_shape.dim(0) / (block_size_base[0] * block_size_base[1]));
+    assert(_ctx.at(block_size_index).type() == ANEURALNETWORKS_TENSOR_INT32);
+
+    assert((_ctx.at(block_size_index).data().size() / sizeof(int32_t)) == 2 &&
+           block_size_base[0] > 0 && block_size_base[1] > 0);
+
+    auto initializer = [block_size_base](::arm_compute::ITensor &tensor) {
+      const int32_t *from = reinterpret_cast<const int32_t *>(block_size_base);
+      int32_t *into = reinterpret_cast<int32_t *>(tensor.ptr_to_element({0}));
+      into[0] = from[1];
+      into[1] = from[0];
+    };
+    _builder.addInitializer(block_size_index, initializer);
+  }
+
+  // Construct operation parameters
+  struct Param
+  {
+    int output_index;
+    int input_index;
+    int block_size_index;
+    const int32_t *block_size;
+    int32_t rank;
+  };
+
+  Param param;
+
+  param.output_index = output_index.asInt();
+  param.input_index = input_index.asInt();
+  param.block_size_index = block_size_index.asInt();
+  param.block_size = block_size;
+  param.rank = _ctx.at(input_index).shape().rank();
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto output_alloc = ctx.at(::internal::tflite::operand::Index{param.output_index});
+    auto input_alloc = ctx.at(::internal::tflite::operand::Index{param.input_index});
+    auto block_size_alloc = ctx.at(::internal::tflite::operand::Index{param.block_size_index});
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLBatchToSpaceLayer>();
+
+      fn->configure(CAST_CL(input_alloc), CAST_CL(block_size_alloc), CAST_CL(output_alloc));
+      builder.append("BatchToSpaceND", std::move(fn));
+    }
+    else
+    {
+      // TODO Enable NEON Support
+      throw std::runtime_error("Not supported, yet");
+    }
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::L2Normalization::Node &node)
+{
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+  const ::internal::tflite::operand::Index ifm_index{node.param().ifm_index};
+
+  // Set Shape Constraints and TensorInfo
+  _builder.addShapeConstr(
+      ifm_index, asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape()), _ctx.at(ifm_index).type(),
+                              _ctx.at(ifm_index).scale(), _ctx.at(ifm_index).zeroPoint()));
+
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+
+  // {CL|Neon}L2Normalization performs the reduction only along dimension 0
+  // L2 Normalization always performs the reduction along the depth axis
+  // Thus, we repurpose {CL|Neon}NormalizationLayers to act as depthwise L2 normalizations by
+  // choosing normalization parameters as below
+
+  // Construct operation parameters
+  struct Param
+  {
+    int ofm_index;
+    int ifm_index;
+    int32_t radius;
+    float alpha;
+    float beta;
+    float bias;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.ifm_index = ifm_index.asInt();
+
+  param.radius = 2 * _ctx.at(ifm_index).shape().dim(3) + 1; // normSize = depth * 2 + 1
+  param.alpha = 1.0f; // In the implementation to make alpha_ become 1
+  param.beta = 0.5f;  // pow(reduction, -0.5) = 1 / sqrt(reduction)
+  param.bias = 0.0f;  // Don't offset the reduction.
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto ifm_alloc = ctx.at(::internal::tflite::operand::Index{param.ifm_index});
+
+    const auto norm_info =
+        ::arm_compute::NormalizationLayerInfo(::arm_compute::NormType::CROSS_MAP, param.radius,
+                                              param.alpha, param.beta, param.bias, false);
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLNormalizationLayer>();
+
+      fn->configure(CAST_CL(ifm_alloc), CAST_CL(ofm_alloc), norm_info);
+
+      builder.append("L2Normalize", std::move(fn));
+    }
+    else
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::NENormalizationLayer>();
+
+      fn->configure(ifm_alloc, ofm_alloc, norm_info);
+
+      builder.append("L2Normalize", std::move(fn));
+    }
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::L2Pool2D::Implicit::Node &node)
+
+{
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+  const ::internal::tflite::operand::Index ifm_index{node.param().ifm_index};
+
+  const ::internal::tflite::operand::Index kh_index{node.param().kh_index};
+  const ::internal::tflite::operand::Index kw_index{node.param().kw_index};
+
+  const ::internal::tflite::operand::Index vstride_index{node.param().vstride_index};
+  const ::internal::tflite::operand::Index hstride_index{node.param().hstride_index};
+
+  const ::internal::tflite::operand::Index padding_index{node.param().padding_index};
+  const ::internal::tflite::operand::Index activation_index{node.param().activation_index};
+
+  const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature();
+  const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature();
+
+  const int32_t kh = _ctx.at(kh_index).asScalar<int32_t>();
+  const int32_t kw = _ctx.at(kw_index).asScalar<int32_t>();
+
+  const int32_t vstride = _ctx.at(vstride_index).asScalar<int32_t>();
+  const int32_t hstride = _ctx.at(hstride_index).asScalar<int32_t>();
+
+  const PaddingCode padding_type =
+      static_cast<PaddingCode>(_ctx.at(padding_index).asScalar<int32_t>());
+
+  assert((ANEURALNETWORKS_PADDING_SAME == padding_type) ||
+         (ANEURALNETWORKS_PADDING_VALID == padding_type));
+
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+  _builder.addShapeConstr(
+      ifm_index, asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape()), _ctx.at(ifm_index).type(),
+                              _ctx.at(ifm_index).scale(), _ctx.at(ifm_index).zeroPoint()));
+
+  struct Param
+  {
+    int ofm_index;
+    int ifm_index;
+
+    uint32_t kw;
+    uint32_t kh;
+
+    Padding padding;
+    Stride stride;
+
+    FuseCode activation;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.ifm_index = ifm_index.asInt();
+
+  param.kh = kh;
+  param.kw = kw;
+
+  param.stride.vertical = vstride;
+  param.stride.horizontal = hstride;
+
+  param.padding = (padding_type == ANEURALNETWORKS_PADDING_SAME)
+                      ? same_padding(ifm_shape, ofm_shape, param.stride, kw, kh)
+                      : valid_padding();
+  param.activation = static_cast<FuseCode>(_ctx.at(activation_index).asScalar<int32_t>());
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto ifm_alloc = ctx.at(::internal::tflite::operand::Index{param.ifm_index});
+
+    ::arm_compute::PoolingLayerInfo info{::arm_compute::PoolingType::L2,
+                                         ::arm_compute::Size2D{param.kw, param.kh},
+                                         asPadStrideInfo(param.padding, param.stride)};
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      std::unique_ptr<::arm_compute::CLPoolingLayer> fn{new ::arm_compute::CLPoolingLayer};
+
+      fn->configure(CAST_CL(ifm_alloc), CAST_CL(ofm_alloc), info);
+
+      builder.append("L2Pool2D", std::move(fn));
+    }
+    else
+    {
+      std::unique_ptr<::arm_compute::NEPoolingLayer> fn{new ::arm_compute::NEPoolingLayer};
+
+      fn->configure(ifm_alloc, ofm_alloc, info);
+
+      builder.append("L2Pool2D", std::move(fn));
+    }
+
+    ActivationBuilder{builder}.append(param.activation, ofm_alloc);
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::L2Pool2D::Explicit::Node &node)
+{
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+  const ::internal::tflite::operand::Index ifm_index{node.param().ifm_index};
+
+  const ::internal::tflite::operand::Index kh_index{node.param().kh_index};
+  const ::internal::tflite::operand::Index kw_index{node.param().kw_index};
+
+  const ::internal::tflite::operand::Index vstride_index{node.param().vstride_index};
+  const ::internal::tflite::operand::Index hstride_index{node.param().hstride_index};
+
+  const ::internal::tflite::operand::Index padding_left_index{node.param().padding_left_index};
+  const ::internal::tflite::operand::Index padding_right_index{node.param().padding_right_index};
+  const ::internal::tflite::operand::Index padding_top_index{node.param().padding_top_index};
+  const ::internal::tflite::operand::Index padding_bottom_index{node.param().padding_bottom_index};
+
+  const ::internal::tflite::operand::Index activation_index{node.param().activation_index};
+
+  const int32_t kh = _ctx.at(kh_index).asScalar<int32_t>();
+  const int32_t kw = _ctx.at(kw_index).asScalar<int32_t>();
+
+  const int32_t vstride = _ctx.at(vstride_index).asScalar<int32_t>();
+  const int32_t hstride = _ctx.at(hstride_index).asScalar<int32_t>();
+
+  const int32_t padding_left = _ctx.at(padding_left_index).asScalar<int32_t>();
+  const int32_t padding_right = _ctx.at(padding_right_index).asScalar<int32_t>();
+  const int32_t padding_top = _ctx.at(padding_top_index).asScalar<int32_t>();
+  const int32_t padding_bottom = _ctx.at(padding_bottom_index).asScalar<int32_t>();
+
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+  _builder.addShapeConstr(
+      ifm_index, asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape()), _ctx.at(ifm_index).type(),
+                              _ctx.at(ifm_index).scale(), _ctx.at(ifm_index).zeroPoint()));
+
+  // Construct operation parameters
+  struct Param
+  {
+    int ofm_index;
+    int ifm_index;
+
+    uint32_t kw;
+    uint32_t kh;
+
+    Padding padding;
+    Stride stride;
+
+    FuseCode activation;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.ifm_index = ifm_index.asInt();
+
+  param.kh = kh;
+  param.kw = kw;
+
+  param.stride.vertical = vstride;
+  param.stride.horizontal = hstride;
+
+  param.padding.left = padding_left;
+  param.padding.right = padding_right;
+  param.padding.top = padding_top;
+  param.padding.bottom = padding_bottom;
+
+  param.activation = static_cast<FuseCode>(_ctx.at(activation_index).asScalar<int32_t>());
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto ifm_alloc = ctx.at(::internal::tflite::operand::Index{param.ifm_index});
+
+    ::arm_compute::PoolingLayerInfo info{::arm_compute::PoolingType::L2,
+                                         ::arm_compute::Size2D{param.kw, param.kh},
+                                         asPadStrideInfo(param.padding, param.stride)};
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      std::unique_ptr<::arm_compute::CLPoolingLayer> fn{new ::arm_compute::CLPoolingLayer};
+
+      fn->configure(CAST_CL(ifm_alloc), CAST_CL(ofm_alloc), info);
+
+      builder.append("L2Pool2D", std::move(fn));
+    }
+    else
+    {
+      std::unique_ptr<::arm_compute::NEPoolingLayer> fn{new ::arm_compute::NEPoolingLayer};
+
+      fn->configure(ifm_alloc, ofm_alloc, info);
+
+      builder.append("L2Pool2D", std::move(fn));
+    }
+
+    ActivationBuilder{builder}.append(param.activation, ofm_alloc);
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::EmbeddingLookup::Node &node)
+{
+  const ::internal::tflite::operand::Index output_index{node.param().output_index};
+  const ::internal::tflite::operand::Index lookups_index{node.param().lookups_index};
+  const ::internal::tflite::operand::Index values_index{node.param().values_index};
+
+  const auto &output_obj = _ctx.at(output_index);
+  const auto &lookups_obj = _ctx.at(lookups_index);
+  const auto &values_obj = _ctx.at(values_index);
+
+  // Verify operand here, not at configure() to avoid acl's modifying
+  // TensorShape sometimes(Issue: https://github.sec.samsung.net/STAR/nnfw/issues/729)
+  {
+    assert(lookups_obj.type() == ANEURALNETWORKS_TENSOR_INT32);
+
+    const auto &output_shape = output_obj.shape();
+    const auto &lookups_shape = lookups_obj.shape();
+    const auto &values_shape = values_obj.shape();
+
+    assert(lookups_shape.rank() == 1);
+    assert(values_shape.rank() >= 2);
+
+    // output should be a n-D tensor with the same rank and shape as the values tensor, except for
+    // the first dimension which has the same size as lookups' only dimension.
+    assert(output_shape.rank() == values_shape.rank());
+    assert(output_shape.dim(0) == lookups_shape.dim(0));
+    for (size_t n = 1; n < output_shape.rank(); ++n)
+    {
+      assert(output_shape.dim(n) == values_shape.dim(n));
+    }
+  }
+
+  // Set Shape Constraints and TensorInfo
+  _builder.addShapeConstr(output_index,
+                          asTensorInfo(asTensorShape(output_obj.shape(), false), output_obj.type(),
+                                       output_obj.scale(), output_obj.zeroPoint()));
+  _builder.addShapeConstr(lookups_index,
+                          asTensorInfo(asTensorShape(lookups_obj.shape()), lookups_obj.type(),
+                                       lookups_obj.scale(), lookups_obj.zeroPoint()));
+  _builder.addShapeConstr(values_index,
+                          asTensorInfo(asTensorShape(values_obj.shape(), false), values_obj.type(),
+                                       values_obj.scale(), values_obj.zeroPoint()));
+
+  // Construct operation parameters
+  struct Param
+  {
+    int32_t output_index;
+    int32_t lookups_index;
+    int32_t values_index;
+  };
+
+  Param param;
+
+  param.output_index = output_index.asInt();
+  param.lookups_index = lookups_index.asInt();
+  param.values_index = values_index.asInt();
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto output_alloc = ctx.at(::internal::tflite::operand::Index{param.output_index});
+    auto lookups_alloc = ctx.at(::internal::tflite::operand::Index{param.lookups_index});
+    auto values_alloc = ctx.at(::internal::tflite::operand::Index{param.values_index});
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLEmbeddingLookup>();
+
+      fn->configure(CAST_CL(values_alloc), CAST_CL(output_alloc), CAST_CL(lookups_alloc));
+
+      builder.append("EmbeddingLookup", std::move(fn));
+    }
+    else
+    {
+      // TODO Enable NEON Support
+      throw std::runtime_error("Not supported, yet");
+    }
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::HashtableLookup::Node &node)
+{
+  const ::internal::tflite::operand::Index output_index{node.param().output_index};
+  const ::internal::tflite::operand::Index hits_index{node.param().hits_index};
+  const ::internal::tflite::operand::Index lookups_index{node.param().lookups_index};
+  const ::internal::tflite::operand::Index values_index{node.param().values_index};
+  const ::internal::tflite::operand::Index keys_index{node.param().keys_index};
+
+  const auto &lookups_obj = _ctx.at(lookups_index);
+  const auto &keys_obj = _ctx.at(keys_index);
+  const auto &hits_obj = _ctx.at(hits_index);
+  const auto &values_obj = _ctx.at(values_index);
+  const auto &output_obj = _ctx.at(output_index);
+
+  assert(lookups_obj.type() == ANEURALNETWORKS_TENSOR_INT32);
+  assert(keys_obj.type() == ANEURALNETWORKS_TENSOR_INT32);
+  assert(hits_obj.type() == ANEURALNETWORKS_TENSOR_QUANT8_ASYMM);
+
+  const auto &lookups_shape = lookups_obj.shape();
+  const auto &keys_shape = keys_obj.shape();
+  const auto &hits_shape = hits_obj.shape();
+  const auto &values_shape = values_obj.shape();
+  const auto &output_shape = output_obj.shape();
+
+  assert(values_shape.rank() == output_shape.rank());
+
+  assert(lookups_shape.rank() == 1);
+  assert(keys_shape.rank() == 1);
+  assert(values_shape.dim(0) == keys_shape.dim(0));
+  assert(lookups_shape.dim(0) == output_shape.dim(0));
+
+  _builder.addShapeConstr(output_index,
+                          asTensorInfo(asTensorShape(_ctx.at(output_index).shape()),
+                                       _ctx.at(output_index).type(), _ctx.at(output_index).scale(),
+                                       _ctx.at(output_index).zeroPoint()));
+  _builder.addShapeConstr(hits_index,
+                          asTensorInfo(asTensorShape(_ctx.at(hits_index).shape()),
+                                       _ctx.at(hits_index).type(), _ctx.at(hits_index).type(),
+                                       _ctx.at(hits_index).zeroPoint()));
+
+  _builder.addShapeConstr(lookups_index, asTensorInfo(asTensorShape(_ctx.at(lookups_index).shape()),
+                                                      _ctx.at(lookups_index).type(),
+                                                      _ctx.at(lookups_index).scale(),
+                                                      _ctx.at(lookups_index).zeroPoint()));
+  _builder.addShapeConstr(values_index,
+                          asTensorInfo(asTensorShape(_ctx.at(values_index).shape()),
+                                       _ctx.at(values_index).type(), _ctx.at(values_index).scale(),
+                                       _ctx.at(values_index).zeroPoint()));
+  _builder.addShapeConstr(keys_index,
+                          asTensorInfo(asTensorShape(_ctx.at(keys_index).shape()),
+                                       _ctx.at(keys_index).type(), _ctx.at(keys_index).scale(),
+                                       _ctx.at(keys_index).zeroPoint()));
+
+  // Construct operation parameters
+  struct Param
+  {
+    int32_t output_index;
+    int32_t hits_index;
+    int32_t lookups_index;
+    int32_t values_index;
+    int32_t keys_index;
+  };
+
+  Param param;
+
+  param.output_index = output_index.asInt();
+  param.hits_index = hits_index.asInt();
+  param.lookups_index = lookups_index.asInt();
+  param.values_index = values_index.asInt();
+  param.keys_index = keys_index.asInt();
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto output_alloc = ctx.at(::internal::tflite::operand::Index{param.output_index});
+    auto hits_alloc = ctx.at(::internal::tflite::operand::Index{param.hits_index});
+    auto lookups_alloc = ctx.at(::internal::tflite::operand::Index{param.lookups_index});
+    auto values_alloc = ctx.at(::internal::tflite::operand::Index{param.values_index});
+    auto keys_alloc = ctx.at(::internal::tflite::operand::Index{param.keys_index});
+
+    if (::internal::arm_compute::isGpuMode()) // GPU
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLHashtableLookup>();
+
+      fn->configure(CAST_CL(lookups_alloc), CAST_CL(keys_alloc), CAST_CL(values_alloc),
+                    CAST_CL(output_alloc), CAST_CL(hits_alloc));
+
+      builder.append("HashtableLookup", std::move(fn));
+    }
+    else // NEON
+    {
+      // TODO Enable NEON Support
+      throw std::runtime_error("Not supported, yet");
+    }
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::LocalResponseNormalization::Node &node)
+{
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+  const ::internal::tflite::operand::Index ifm_index{node.param().ifm_index};
+  const ::internal::tflite::operand::Index radius_index{node.param().radius_index};
+  const ::internal::tflite::operand::Index bias_index{node.param().bias_index};
+  const ::internal::tflite::operand::Index alpha_index{node.param().alpha_index};
+  const ::internal::tflite::operand::Index beta_index{node.param().beta_index};
+
+  // Set Shape Constraints and TensorInfo
+  _builder.addShapeConstr(
+      ifm_index, asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape()), _ctx.at(ifm_index).type(),
+                              _ctx.at(ifm_index).scale(), _ctx.at(ifm_index).zeroPoint()));
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+
+  // Construct operation parameters
+  struct Param
+  {
+    int ofm_index;
+    int ifm_index;
+    int32_t radius;
+    float bias;
+    float alpha;
+    float beta;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.ifm_index = ifm_index.asInt();
+
+  param.radius = _ctx.at(radius_index).asScalar<int32_t>();
+  param.alpha = _ctx.at(alpha_index).asScalar<float>();
+  param.beta = _ctx.at(beta_index).asScalar<float>();
+  param.bias = _ctx.at(bias_index).asScalar<float>();
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto ifm_alloc = ctx.at(::internal::tflite::operand::Index{param.ifm_index});
+
+    const auto norm_info = ::arm_compute::NormalizationLayerInfo(::arm_compute::NormType::CROSS_MAP,
+                                                                 param.radius * 2 + 1, param.alpha,
+                                                                 param.beta, param.bias, false);
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLNormalizationLayer>();
+
+      fn->configure(CAST_CL(ifm_alloc), CAST_CL(ofm_alloc), norm_info);
+
+      builder.append("LocalResponseNormalization", std::move(fn));
+    }
+    else
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::NENormalizationLayer>();
+
+      fn->configure(ifm_alloc, ofm_alloc, norm_info);
+
+      builder.append("LocalResponseNormalization", std::move(fn));
+    }
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::DepthToSpace::Node &node)
+{
+  const ::internal::tflite::operand::Index output_index{node.param().output_index};
+  const ::internal::tflite::operand::Index input_index{node.param().input_index};
+  const ::internal::tflite::operand::Index block_size_index{node.param().block_size_index};
+
+  assert(_ctx.at(input_index).shape().rank() == 4);
+  assert(_ctx.at(output_index).shape().rank() == 4);
+
+  int32_t block_size = _ctx.at(block_size_index).asScalar<int32_t>();
+  assert(block_size > 0);
+
+  { // assertions block
+    const auto output_shape = _ctx.at(output_index).shape();
+    const auto input_shape = _ctx.at(input_index).shape();
+    assert(output_shape.dim(0) == input_shape.dim(0));
+    assert(output_shape.dim(1) == input_shape.dim(1) * block_size);
+    assert(output_shape.dim(2) == input_shape.dim(2) * block_size);
+    assert(input_shape.dim(3) % (block_size * block_size) == 0);
+    assert(output_shape.dim(3) == input_shape.dim(3) / (block_size * block_size));
+  }
+
+  // Set Shape Constraints and TensorInfo
+  _builder.addShapeConstr(output_index,
+                          asTensorInfo(asTensorShape(_ctx.at(output_index).shape(), false),
+                                       _ctx.at(output_index).type(), _ctx.at(output_index).scale(),
+                                       _ctx.at(output_index).zeroPoint()));
+  _builder.addShapeConstr(input_index,
+                          asTensorInfo(asTensorShape(_ctx.at(input_index).shape(), false),
+                                       _ctx.at(input_index).type(), _ctx.at(input_index).scale(),
+                                       _ctx.at(input_index).zeroPoint()));
+
+  // Construct operation parameters
+  struct Param
+  {
+    int output_index;
+    int input_index;
+    int32_t block_size;
+  };
+
+  Param param;
+
+  param.output_index = output_index.asInt();
+  param.input_index = input_index.asInt();
+  param.block_size = block_size;
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto output_alloc = ctx.at(::internal::tflite::operand::Index{param.output_index});
+    auto input_alloc = ctx.at(::internal::tflite::operand::Index{param.input_index});
+
+    {
+      if (::internal::arm_compute::isGpuMode()) // GPU
+      {
+        auto fn = nnfw::cpp14::make_unique<::arm_compute::CLDepthToSpace>();
+
+        fn->configure(CAST_CL(input_alloc), CAST_CL(output_alloc), param.block_size);
+
+        builder.append("DepthToSpace", std::move(fn));
+      }
+      else // NEON
+      {
+        // TODO Enable NEON Support
+        throw std::runtime_error("Not supported, yet");
+      }
+    }
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::Unpack::Node &node)
+{
+  VERBOSE(Unpack) << "Configure Unpack operation" << std::endl;
+  const ::internal::tflite::operand::Index ifm_index{node.param().ifm_index};
+  uint32_t input_rank = _ctx.at(ifm_index).shape().rank();
+
+  assert(input_rank == 4 || input_rank == 3 || input_rank == 2);
+  _builder.addShapeConstr(ifm_index, asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape()),
+                                                  _ctx.at(ifm_index).type()));
+
+  int32_t axis =
+      _ctx.at(::internal::tflite::operand::Index{node.param().axis_index}).asScalar<int32_t>();
+  // Negatige axis is supported, -1 implies R-1 axis where R is input rank
+  if (axis < 0)
+  {
+    axis += input_rank;
+    assert(axis >= 0);
+  }
+  uint32_t axis_uint = ToARMComputeAxis(input_rank, axis).value();
+  // int32_t num_split =
+  // _ctx.at(::internal::tflite::operand::Index{node.param().num_split_index}).asScalar<int32_t>();
+
+  for (const auto &index : node.param().ofm_indexes)
+  {
+    const ::internal::tflite::operand::Index ofm_index{index};
+    _builder.addShapeConstr(ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()),
+                                                    _ctx.at(ofm_index).type()));
+  }
+
+  struct Param
+  {
+    std::vector<int32_t> ofm_indexes;
+    int ifm_index;
+    uint32_t axis;
+  };
+
+  if (input_rank == 4)
+  {
+    // TODO: generate test case for this and generalize 4D method all cases.
+    throw std::runtime_error("UNPACK_4D not implemented");
+  }
+  else if (input_rank == 3)
+  {
+    Param param;
+    param.ifm_index = ifm_index.asInt();
+    param.axis = axis_uint;
+    for (const auto &index : node.param().ofm_indexes)
+    {
+      param.ofm_indexes.push_back(index);
+    }
+
+    auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+      auto input_alloc = ctx.at(::internal::tflite::operand::Index{param.ifm_index});
+
+      if (::internal::arm_compute::isGpuMode())
+      {
+        auto fn = nnfw::cpp14::make_unique<::arm_compute::CLUnstack>();
+        std::vector<::arm_compute::ICLTensor *> outputs;
+        for (const auto &index : param.ofm_indexes)
+        {
+          auto output_alloc = ctx.at(::internal::tflite::operand::Index{index});
+          outputs.push_back(CAST_CL(output_alloc));
+        }
+        fn->configure(CAST_CL(input_alloc), outputs, param.axis);
+
+        builder.append("Unpack", std::move(fn));
+      }
+      else
+        throw std::runtime_error("Not supported, yet");
+    };
+
+    _builder.addStage(stage);
+  }
+  else if (input_rank == 2)
+  {
+    throw std::runtime_error("UNPACK_2D not implemented");
+  }
+  else
+  {
+    throw std::runtime_error("UNPACK axis is not valid");
+  }
+}
+
+void Planner::visit(const ::internal::tflite::op::Pack::Node &node)
+{
+  VERBOSE(Pack) << "Configure Pack operation" << std::endl;
+
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+  const uint32_t output_rank = _ctx.at(ofm_index).shape().rank();
+  const uint32_t input_rank = output_rank - 1;
+
+  assert(output_rank == 4 || output_rank == 3 || output_rank == 2);
+
+  for (const auto &index : node.param().ifm_indexes)
+  {
+    const ::internal::tflite::operand::Index ifm_index{index};
+    assert(_ctx.at(ifm_index).shape().rank() == input_rank);
+    _builder.addShapeConstr(ifm_index, asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape()),
+                                                    _ctx.at(ifm_index).type()));
+  }
+
+  _builder.addShapeConstr(ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()),
+                                                  _ctx.at(ofm_index).type()));
+
+  int32_t axis =
+      _ctx.at(::internal::tflite::operand::Index{node.param().axis_index}).asScalar<int32_t>();
+  // A negative axis implies axis from the end.
+  // For example, axis = -1 implies the first axis from the end, i.e. axis = Rank - 1.
+  // Similarly, axis = -2 imples second axis from the end, i.e. axis = Rank - 2.
+  if (axis < 0)
+  {
+    axis += output_rank;
+    assert(axis >= 0);
+  }
+  uint32_t axis_uint = ToARMComputeAxis(output_rank, axis).value();
+
+  struct Param
+  {
+    std::vector<int32_t> ifm_indexes;
+    int ofm_index;
+    uint32_t axis;
+  };
+
+  if (input_rank == 3)
+  {
+    // TODO: generate test case for this and generalize 4D method all cases.
+    throw std::runtime_error("PACK_3D not implemented");
+  }
+  else if (input_rank == 2)
+  {
+    Param param;
+    param.ofm_index = ofm_index.asInt();
+    param.axis = axis_uint;
+
+    for (const auto &index : node.param().ifm_indexes)
+    {
+      param.ifm_indexes.push_back(index);
+    }
+
+    auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+      auto output_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+
+      if (::internal::arm_compute::isGpuMode())
+      {
+        auto fn = nnfw::cpp14::make_unique<::arm_compute::CLStackLayer>();
+        std::vector<::arm_compute::ICLTensor *> inputs;
+        for (const auto &index : param.ifm_indexes)
+        {
+          auto input_alloc = ctx.at(::internal::tflite::operand::Index{index});
+          inputs.push_back(CAST_CL(input_alloc));
+        }
+        fn->configure(inputs, param.axis, CAST_CL(output_alloc));
+
+        builder.append("Pack", std::move(fn));
+      }
+      else
+        throw std::runtime_error("Not supported, yet");
+    };
+
+    _builder.addStage(stage);
+  }
+  else if (input_rank == 1)
+  {
+    throw std::runtime_error("PACK_1D not implemented");
+  }
+  else
+  {
+    throw std::runtime_error("PACK axis is not valid");
+  }
+}
+
+void Planner::visit(const ::internal::tflite::op::Neg::Node &node)
+{
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+  const ::internal::tflite::operand::Index ifm_index{node.param().ifm_index};
+
+  // Set Shape Constraints and TensorInfo
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+  _builder.addShapeConstr(
+      ifm_index, asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape()), _ctx.at(ifm_index).type(),
+                              _ctx.at(ifm_index).scale(), _ctx.at(ifm_index).zeroPoint()));
+
+  // Construct operation parameters
+  struct Param
+  {
+    int ofm_index;
+    int ifm_index;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.ifm_index = ifm_index.asInt();
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto ifm_alloc = ctx.at(::internal::tflite::operand::Index{param.ifm_index});
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLNeg>();
+
+      fn->configure(CAST_CL(ifm_alloc), CAST_CL(ofm_alloc));
+      builder.append("Neg", std::move(fn));
+    }
+    else
+    {
+      // TODO Enable NEON Support
+      throw std::runtime_error("Not supported, yet");
+    }
+
+  };
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::Exp::Node &node)
+{
+  VERBOSE(Exp) << "Configure Exp operation" << std::endl;
+
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+  const ::internal::tflite::operand::Index ifm_index{node.param().ifm_index};
+
+  // Set shape constraints
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+  _builder.addShapeConstr(
+      ifm_index, asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape()), _ctx.at(ifm_index).type(),
+                              _ctx.at(ifm_index).scale(), _ctx.at(ifm_index).zeroPoint()));
+
+  struct Param
+  {
+    int ofm_index;
+    int ifm_index;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.ifm_index = ifm_index.asInt();
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto ifm_alloc = ctx.at(::internal::tflite::operand::Index{param.ifm_index});
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLExpLayer>();
+
+      fn->configure(CAST_CL(ifm_alloc), CAST_CL(ofm_alloc));
+
+      builder.append("Exp", std::move(fn));
+    }
+    else
+    {
+      throw std::runtime_error("Not supported");
+    }
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::ReduceSum::Node &node)
+{
+  VERBOSE(ReduceSum) << "Configure ReduceSum operation" << std::endl;
+
+  const ::internal::tflite::operand::Index ofm_index{node.param().ofm_index};
+  const ::internal::tflite::operand::Index ifm_index{node.param().ifm_index};
+  const ::internal::tflite::operand::Index axis_index{node.param().axis_index};
+
+  const auto ifm_shape = _ctx.at(ifm_index).shape();
+  const auto ofm_shape = _ctx.at(ofm_index).shape();
+  const auto axis_shape = _ctx.at(axis_index).shape();
+
+  assert(ifm_shape.rank() <= 4);
+  assert(ofm_shape.rank() <= ifm_shape.rank());
+  assert(_ctx.at(axis_index).hasData());
+  assert(axis_shape.rank() == 0 || axis_shape.rank() == 1);
+
+  // NOTE For the 4-dimensions, if the rank of input and output are different, this runtime only
+  // supports cases reducing height and width or reducing depth.
+  // TODO We have to support all cases of dimensions up to 4.
+  // For correct permuting, we have to set output's shape to be equal in dimension position of the
+  // input. But the positions of the same dimensions in the input and output may be set differently.
+  // For example {2,3,4,5}(input's shape) can be reduced to {3,5}(output's shape). The original
+  // output shape should be {1,3,1,5}, but real output shape may be {3,5}. If you simply try to
+  // extend it in 4 dimensions, it should be {1,1,3,5}.
+  // Even if output shape is changed to {1,3,1,5}, there is another problem. It is that shape of
+  // output tensor used at next operation is changed to {1,3,1,5} after this operation even if the
+  // next operation is not desired.
+  if (ifm_shape.rank() == 4 && ifm_shape.rank() != ofm_shape.rank())
+  {
+    if (ofm_shape.rank() == 2)
+    {
+      // Reducing HW
+      assert(ifm_shape.dim(0) == ofm_shape.dim(0) && ifm_shape.dim(3) == ofm_shape.dim(1));
+    }
+    else if (ofm_shape.rank() == 3)
+    {
+      // Reducing C or
+      // (Reducing H and C(ifm and ofm) == 1) or (Reducing W and C(ifm and ofm) == 1)
+      assert(ifm_shape.dim(0) == ofm_shape.dim(0) && ifm_shape.dim(1) == ofm_shape.dim(1) &&
+                 ifm_shape.dim(2) == ofm_shape.dim(2) ||
+             (ifm_shape.dim(0) == ofm_shape.dim(0) &&
+              (ifm_shape.dim(1) == ofm_shape.dim(1) || ifm_shape.dim(2) == ofm_shape.dim(1)) &&
+              ifm_shape.dim(3) == 1 && ofm_shape.dim(2) == 1));
+    }
+  }
+
+  // Set shape constraints
+  _builder.addShapeConstr(
+      ofm_index, asTensorInfo(asTensorShape(_ctx.at(ofm_index).shape()), _ctx.at(ofm_index).type(),
+                              _ctx.at(ofm_index).scale(), _ctx.at(ofm_index).zeroPoint()));
+  _builder.addShapeConstr(
+      ifm_index, asTensorInfo(asTensorShape(_ctx.at(ifm_index).shape()), _ctx.at(ifm_index).type(),
+                              _ctx.at(ifm_index).scale(), _ctx.at(ifm_index).zeroPoint()));
+
+  uint32_t input_rank = ifm_shape.rank();
+  std::set<uint32_t> axis;
+  int32_t axis_rank = axis_shape.rank();
+
+  if (axis_rank == 0)
+  {
+    int32_t axis_value = _ctx.at(axis_index).asScalar<int32_t>();
+    if (axis_value < 0)
+    {
+      axis_value += input_rank;
+    }
+    axis.insert(ToARMComputeAxis(input_rank, axis_value).value());
+  }
+  else if (axis_rank == 1)
+  {
+    const auto axis_base = _ctx.at(axis_index).data().base();
+    const auto axis_size = _ctx.at(axis_index).shape().asVector();
+
+    // If axis's data does not exist as constant values and can be gotten as input data, we have to
+    // find a way to infer output shape when sinking output.
+    assert(axis_base != nullptr);
+    for (uint32_t n = 0; n < axis_size; ++n)
+    {
+      int32_t axis_value = *(reinterpret_cast<const int32_t *>(axis_base) + n);
+      if (axis_value < 0)
+      {
+        axis_value += input_rank;
+      }
+      axis.insert(ToARMComputeAxis(input_rank, axis_value).value());
+    }
+  }
+  else
+  {
+    throw std::runtime_error("Not supported axis");
+  }
+
+  struct Param
+  {
+    int ofm_index;
+    int ifm_index;
+    std::set<uint32_t> axis;
+  };
+
+  Param param;
+
+  param.ofm_index = ofm_index.asInt();
+  param.ifm_index = ifm_index.asInt();
+  param.axis = axis;
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto ofm_alloc = ctx.at(::internal::tflite::operand::Index{param.ofm_index});
+    auto ifm_alloc = ctx.at(::internal::tflite::operand::Index{param.ifm_index});
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLReduceOperation>();
+
+      fn->configure(CAST_CL(ifm_alloc), CAST_CL(ofm_alloc), param.axis,
+                    ::arm_compute::ReduceOperation::SUM);
+
+      builder.append("ReduceSum", std::move(fn));
+    }
+    else
+      throw std::runtime_error("Not supported, yet");
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::Abs::Node &node)
+{
+  VERBOSE(Tanh) << "Configure Abs operation" << std::endl;
+
+  const ::internal::tflite::operand::Index output_index{node.param().output_index};
+  const ::internal::tflite::operand::Index input_index{node.param().input_index};
+
+  // Set shape constraints
+  _builder.addShapeConstr(output_index,
+                          asTensorInfo(asTensorShape(_ctx.at(output_index).shape()),
+                                       _ctx.at(output_index).type(), _ctx.at(output_index).scale(),
+                                       _ctx.at(output_index).zeroPoint()));
+  _builder.addShapeConstr(input_index,
+                          asTensorInfo(asTensorShape(_ctx.at(input_index).shape()),
+                                       _ctx.at(input_index).type(), _ctx.at(output_index).scale(),
+                                       _ctx.at(output_index).zeroPoint()));
+
+  struct Param
+  {
+    int output_index;
+    int input_index;
+  };
+
+  Param param;
+
+  param.output_index = output_index.asInt();
+  param.input_index = input_index.asInt();
+
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto output_alloc = ctx.at(::internal::tflite::operand::Index{param.output_index});
+    auto input_alloc = ctx.at(::internal::tflite::operand::Index{param.input_index});
+
+    const ::arm_compute::ActivationLayerInfo act_info{
+        ::arm_compute::ActivationLayerInfo::ActivationFunction::ABS};
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLActivationLayer>();
+
+      fn->configure(CAST_CL(input_alloc), CAST_CL(output_alloc), act_info);
+
+      builder.append("Abs", std::move(fn));
+    }
+    else
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::NEActivationLayer>();
+
+      fn->configure(input_alloc, output_alloc, act_info);
+
+      builder.append("Abs", std::move(fn));
+    }
+  };
+
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::NotEqual::Node &node)
+{
+  const ::internal::tflite::operand::Index output_index{node.param().output_index};
+  const ::internal::tflite::operand::Index input1_index{node.param().input1_index};
+  const ::internal::tflite::operand::Index input2_index{node.param().input2_index};
+
+  // Set Shape Constraints and TensorInfo
+  _builder.addShapeConstr(output_index,
+                          asTensorInfo(asTensorShape(_ctx.at(output_index).shape()),
+                                       _ctx.at(output_index).type(), _ctx.at(output_index).scale(),
+                                       _ctx.at(output_index).zeroPoint()));
+
+  if (!(_ctx.at(input1_index).shape() == _ctx.at(input2_index).shape()))
+  {
+    const auto broadcast_rank =
+        std::max(_ctx.at(input1_index).shape().rank(), _ctx.at(input2_index).shape().rank());
+    const_cast<::internal::tflite::operand::Shape &>(_ctx.at(input1_index).shape())
+        .extendRank(broadcast_rank);
+    const_cast<::internal::tflite::operand::Shape &>(_ctx.at(input2_index).shape())
+        .extendRank(broadcast_rank);
+  }
+  _builder.addShapeConstr(input1_index,
+                          asTensorInfo(asTensorShape(_ctx.at(input1_index).shape()),
+                                       _ctx.at(input1_index).type(), _ctx.at(input1_index).scale(),
+                                       _ctx.at(input1_index).zeroPoint()));
+  _builder.addShapeConstr(input2_index,
+                          asTensorInfo(asTensorShape(_ctx.at(input2_index).shape()),
+                                       _ctx.at(input2_index).type(), _ctx.at(input2_index).scale(),
+                                       _ctx.at(input2_index).zeroPoint()));
+
+  // Construct operation parameters
+  struct Param
+  {
+    int output_index;
+    int input1_index;
+    int input2_index;
+  };
+
+  Param param;
+
+  param.output_index = output_index.asInt();
+  param.input1_index = input1_index.asInt();
+  param.input2_index = input2_index.asInt();
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto output_alloc = ctx.at(::internal::tflite::operand::Index{param.output_index});
+    auto input1_alloc = ctx.at(::internal::tflite::operand::Index{param.input1_index});
+    auto input2_alloc = ctx.at(::internal::tflite::operand::Index{param.input2_index});
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLComparison>();
+
+      fn->configure(CAST_CL(input1_alloc), CAST_CL(input2_alloc), CAST_CL(output_alloc),
+                    ::arm_compute::ComparisonOperation::NotEqual);
+
+      builder.append("NotEqual", std::move(fn));
+    }
+    else
+    {
+      // TODO Add NEON support
+
+      throw std::runtime_error("Not supported yet");
+    }
+  };
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::LogicalAnd::Node &node)
+{
+  VERBOSE(Logical_AND) << "Configure Logical_AND operation" << std::endl;
+
+  const ::internal::tflite::operand::Index output_index{node.param().output_index};
+  const ::internal::tflite::operand::Index input1_index{node.param().input1_index};
+  const ::internal::tflite::operand::Index input2_index{node.param().input2_index};
+
+  // Set Shape Constraints and TensorInfo
+  _builder.addShapeConstr(output_index,
+                          asTensorInfo(asTensorShape(_ctx.at(output_index).shape()),
+                                       _ctx.at(output_index).type(), _ctx.at(output_index).scale(),
+                                       _ctx.at(output_index).zeroPoint()));
+
+  if (!(_ctx.at(input1_index).shape() == _ctx.at(input2_index).shape()))
+  {
+    const auto broadcast_rank =
+        std::max(_ctx.at(input1_index).shape().rank(), _ctx.at(input2_index).shape().rank());
+    const_cast<::internal::tflite::operand::Shape &>(_ctx.at(input1_index).shape())
+        .extendRank(broadcast_rank);
+    const_cast<::internal::tflite::operand::Shape &>(_ctx.at(input2_index).shape())
+        .extendRank(broadcast_rank);
+  }
+  _builder.addShapeConstr(input1_index,
+                          asTensorInfo(asTensorShape(_ctx.at(input1_index).shape()),
+                                       _ctx.at(input1_index).type(), _ctx.at(input1_index).scale(),
+                                       _ctx.at(input1_index).zeroPoint()));
+  _builder.addShapeConstr(input2_index,
+                          asTensorInfo(asTensorShape(_ctx.at(input2_index).shape()),
+                                       _ctx.at(input2_index).type(), _ctx.at(input2_index).scale(),
+                                       _ctx.at(input2_index).zeroPoint()));
+
+  // Construct operation parameters
+  struct Param
+  {
+    int output_index;
+    int input1_index;
+    int input2_index;
+  };
+
+  Param param;
+
+  param.output_index = output_index.asInt();
+  param.input1_index = input1_index.asInt();
+  param.input2_index = input2_index.asInt();
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto output_alloc = ctx.at(::internal::tflite::operand::Index{param.output_index});
+    auto input1_alloc = ctx.at(::internal::tflite::operand::Index{param.input1_index});
+    auto input2_alloc = ctx.at(::internal::tflite::operand::Index{param.input2_index});
+
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLBinaryLogicalOp>();
+
+      fn->configure(CAST_CL(input1_alloc), CAST_CL(input2_alloc), CAST_CL(output_alloc),
+                    ::arm_compute::BinaryLogicalOperation::AND);
+
+      builder.append("LogicalAnd", std::move(fn));
+    }
+    else
+    {
+      // TODO Add NEON support
+
+      throw std::runtime_error("Not supported yet");
+    }
+  };
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::LogicalNot::Node &node)
+{
+  const ::internal::tflite::operand::Index output_index{node.param().output_index};
+  const ::internal::tflite::operand::Index input_index{node.param().input_index};
+
+  // Set Shape Constraints and TensorInfo
+  _builder.addShapeConstr(output_index,
+                          asTensorInfo(asTensorShape(_ctx.at(output_index).shape()),
+                                       ::arm_compute::DataType::U8, _ctx.at(output_index).scale(),
+                                       _ctx.at(output_index).zeroPoint()));
+
+  _builder.addShapeConstr(input_index,
+                          asTensorInfo(asTensorShape(_ctx.at(input_index).shape()),
+                                       ::arm_compute::DataType::U8, _ctx.at(input_index).scale(),
+                                       _ctx.at(input_index).zeroPoint()));
+
+  // Construct operation parameters
+  struct Param
+  {
+    int output_index;
+    int input_index;
+  };
+
+  Param param;
+
+  param.output_index = output_index.asInt();
+  param.input_index = input_index.asInt();
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto output_alloc = ctx.at(::internal::tflite::operand::Index{param.output_index});
+    auto input_alloc = ctx.at(::internal::tflite::operand::Index{param.input_index});
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLBitwiseNot>();
+
+      fn->configure(CAST_CL(input_alloc), CAST_CL(output_alloc));
+
+      builder.append("LogicalNot", std::move(fn));
+    }
+    else
+    {
+      // TODO Add NEON support
+
+      throw std::runtime_error("Not supported yet");
+    }
+  };
+  _builder.addStage(stage);
+}
+
+void Planner::visit(const ::internal::tflite::op::LogicalOr::Node &node)
+{
+  VERBOSE(LogicalOr) << "Configure LogicalOr operation" << std::endl;
+
+  const ::internal::tflite::operand::Index output_index{node.param().output_index};
+  const ::internal::tflite::operand::Index input1_index{node.param().input1_index};
+  const ::internal::tflite::operand::Index input2_index{node.param().input2_index};
+
+  // Set Shape Constraints and TensorInfo
+  _builder.addShapeConstr(output_index,
+                          asTensorInfo(asTensorShape(_ctx.at(output_index).shape()),
+                                       _ctx.at(output_index).type(), _ctx.at(output_index).scale(),
+                                       _ctx.at(output_index).zeroPoint()));
+
+  if (!(_ctx.at(input1_index).shape() == _ctx.at(input2_index).shape()))
+  {
+    const auto broadcast_rank =
+        std::max(_ctx.at(input1_index).shape().rank(), _ctx.at(input2_index).shape().rank());
+    const_cast<::internal::tflite::operand::Shape &>(_ctx.at(input1_index).shape())
+        .extendRank(broadcast_rank);
+    const_cast<::internal::tflite::operand::Shape &>(_ctx.at(input2_index).shape())
+        .extendRank(broadcast_rank);
+  }
+
+  _builder.addShapeConstr(input1_index,
+                          asTensorInfo(asTensorShape(_ctx.at(input1_index).shape()),
+                                       _ctx.at(input1_index).type(), _ctx.at(input1_index).scale(),
+                                       _ctx.at(input1_index).zeroPoint()));
+  _builder.addShapeConstr(input2_index,
+                          asTensorInfo(asTensorShape(_ctx.at(input2_index).shape()),
+                                       _ctx.at(input2_index).type(), _ctx.at(input2_index).scale(),
+                                       _ctx.at(input2_index).zeroPoint()));
+
+  // Construct operation parameters
+  struct Param
+  {
+    int output_index;
+    int input1_index;
+    int input2_index;
+  };
+
+  Param param;
+
+  param.output_index = output_index.asInt();
+  param.input1_index = input1_index.asInt();
+  param.input2_index = input2_index.asInt();
+  auto stage = [param](const IAllocationContext &ctx, IExecutionBuilder &builder) {
+    auto output_alloc = ctx.at(::internal::tflite::operand::Index{param.output_index});
+    auto input1_alloc = ctx.at(::internal::tflite::operand::Index{param.input1_index});
+    auto input2_alloc = ctx.at(::internal::tflite::operand::Index{param.input2_index});
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto fn = nnfw::cpp14::make_unique<::arm_compute::CLBinaryLogicalOp>();
+
+      fn->configure(CAST_CL(input1_alloc), CAST_CL(input2_alloc), CAST_CL(output_alloc),
+                    ::arm_compute::BinaryLogicalOperation::OR);
+
+      builder.append("LogicalOr", std::move(fn));
+    }
+    else
+    {
+      // TODO Add NEON support
+
+      throw std::runtime_error("Not supported yet");
+    }
+  };
+  _builder.addStage(stage);
+}
+
+class AllocationContext final : public IAllocationContext
+{
+public:
+  AllocationContext(::internal::arm_compute::Plan &plan) : _plan{plan}
+  {
+    // DO NOTHING
+  }
+
+public:
+  ::arm_compute::ITensor *at(const ::internal::tflite::operand::Index &ind) const override
+  {
+    return _plan.operands().at(ind).ptr();
+  }
+
+private:
+  ::internal::arm_compute::Plan &_plan;
+};
+
+class ExecutionBuilder final : public IExecutionBuilder
+{
+public:
+  ExecutionBuilder(::internal::arm_compute::Plan &plan) : _plan{plan}
+  {
+    // DO NOTHING
+  }
+
+public:
+  void append(const std::string &name, std::unique_ptr<::arm_compute::IFunction> &&f) override
+  {
+    _plan.operations().append(std::move(f));
+    _plan.operations().at(_plan.operations().size() - 1).name() = name;
+  }
+
+#ifdef TFLITE_PROFILING_ENABLED
+public:
+  int plan_op_size() const { return _plan.operations().size(); }
+  void addOpIndexToSteps(int from, int to, int op_idx)
+  {
+    for (int i = from; i < to; ++i)
+      _plan.operations().at(i).op_idx() = op_idx;
+  }
+#endif
+
+private:
+  ::internal::arm_compute::Plan &_plan;
+};
+
+/**
+ * @brief Class to provide methods of compilation plan builder
+ */
+class PlanBuilder final : public IPlanBuilder
+{
+public:
+  /**
+   * @brief Construct a new PlanBuilder object with Plan
+   * @param [in] plan  The Plan object
+   */
+  PlanBuilder(::internal::arm_compute::Plan &plan) : _plan{plan}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief  Add TensorInfo with Shape Constraints
+   * @param [in] ind   Index of operand
+   * @param [in] info  TensorInfo value to set to index of operand
+   * @return  N/A
+   */
+  void addShapeConstr(const ::internal::tflite::operand::Index &ind,
+                      const ::arm_compute::TensorInfo &info) override;
+
+public:
+  /**
+   * @brief  Add Subsumption constraints
+   * @param [in] ind  Index of operand
+   * @param [in] base  Index of base operand of Subsumption
+   * @param [in] offset  Offset of Subsumption
+   * @param [in] shape  Shape of Subsumption
+   * @param [in] extend_parent  extend_parent value of Subsumption
+   * @return  N/A
+   */
+  void addSubsumptionConstr(const ::internal::tflite::operand::Index &ind,
+                            const ::internal::tflite::operand::Index &base,
+                            const ::arm_compute::Coordinates &offset,
+                            const ::arm_compute::TensorShape &shape, bool extend_parent) override;
+
+public:
+  /**
+   * @brief  Add Initializer lambda with ITensor param
+   * @param [in] ind  Index of operand
+   * @param [in] initializer  Initializer to add
+   * @return  N/A
+   */
+  void addInitializer(const ::internal::tflite::operand::Index &ind,
+                      const Initializer &initializer) override;
+
+public:
+  /**
+   * @brief  Add Stage lambda with IAllocationContext and IExecutionBuilder params
+   * @param [in] stage  Stage to add
+   * @return  N/A
+   */
+  void addStage(const Stage &stage) override;
+
+public:
+  /**
+   * @brief  Finilize(build) the Plan
+   * @return  N/A
+   */
+  void finalize(void) const;
+
+private:
+  ::internal::arm_compute::Plan &_plan;
+
+private:
+  struct Subsumption
+  {
+  public:
+    Subsumption(const ::internal::tflite::operand::Index &base,
+                const ::arm_compute::Coordinates &offset, const ::arm_compute::TensorShape &shape,
+                bool extend_parent)
+        : _base{base}, _offset{offset}, _shape{shape}, _extend_parent{extend_parent}
+    {
+      // DO NOTHING
+    }
+
+  public:
+    const ::internal::tflite::operand::Index &base(void) const { return _base; }
+    const ::arm_compute::Coordinates &offset(void) const { return _offset; }
+    const ::arm_compute::TensorShape &shape(void) const { return _shape; }
+    const bool extend_parent(void) const { return _extend_parent; }
+
+  private:
+    const ::internal::tflite::operand::Index _base;
+    const ::arm_compute::Coordinates _offset;
+    const ::arm_compute::TensorShape _shape;
+    const bool _extend_parent;
+  };
+
+private:
+  std::map<int, ::arm_compute::TensorInfo> _tensor_info_ctx;
+  std::map<int, std::shared_ptr<Subsumption>> _subsumption_ctx;
+  std::map<int, Initializer> _initializer_ctx;
+  std::vector<Stage> _stages;
+};
+
+void PlanBuilder::addShapeConstr(const ::internal::tflite::operand::Index &ind,
+                                 const ::arm_compute::TensorInfo &info)
+{
+  _tensor_info_ctx[ind.asInt()] = info;
+}
+
+void PlanBuilder::addSubsumptionConstr(const ::internal::tflite::operand::Index &ind,
+                                       const ::internal::tflite::operand::Index &base,
+                                       const ::arm_compute::Coordinates &offset,
+                                       const ::arm_compute::TensorShape &shape, bool extend_parent)
+{
+  _subsumption_ctx[ind.asInt()] = std::make_shared<Subsumption>(base, offset, shape, extend_parent);
+}
+
+void PlanBuilder::addInitializer(const ::internal::tflite::operand::Index &ind,
+                                 const Initializer &initializer)
+{
+  _initializer_ctx[ind.asInt()] = initializer;
+}
+
+void PlanBuilder::addStage(const Stage &stage) { _stages.emplace_back(stage); }
+
+#include <stack>
+
+void PlanBuilder::finalize(void) const
+{
+  // ITensor objects to be initialized later
+  std::vector<std::shared_ptr<::arm_compute::ITensor>> tensors;
+
+  // Create Tensor & CLSubTensor
+  auto isAllocated = [this](int ind) {
+    const ::internal::tflite::operand::Index operand_index{ind};
+    return _plan.operands().exist(operand_index);
+  };
+
+  auto setCLTensor = [&](int ind) {
+    auto tensor = std::make_shared<::arm_compute::CLTensor>();
+
+    tensor->allocator()->init(_tensor_info_ctx.at(ind));
+
+    // NOTE Do NOT allocate here. allocate should be invoked after configure functions
+    _plan.operands().set(::internal::tflite::operand::Index{ind}, tensor);
+    tensors.emplace_back(tensor);
+  };
+
+  auto setCLSubTensor = [&](int curr) {
+    const auto &sub_info = *(_subsumption_ctx.find(curr)->second);
+
+    auto base_tensor = _plan.operands().at(sub_info.base()).ptr();
+
+    assert(base_tensor != nullptr);
+
+    auto curr_tensor = std::make_shared<::arm_compute::CLSubTensor>(
+        CAST_CL(base_tensor), sub_info.shape(), sub_info.offset(), sub_info.extend_parent());
+
+    _plan.operands().set(::internal::tflite::operand::Index{curr}, curr_tensor);
+  };
+
+  auto setNETensor = [&](int ind) {
+    auto tensor = std::make_shared<::arm_compute::Tensor>();
+
+    tensor->allocator()->init(_tensor_info_ctx.at(ind));
+
+    // NOTE Do NOT allocate here. allocate should be invoked after configure functions
+    _plan.operands().set(::internal::tflite::operand::Index{ind}, tensor);
+    tensors.emplace_back(tensor);
+  };
+
+  auto setNESubTensor = [&](int curr) {
+    const auto &sub_info = *(_subsumption_ctx.find(curr)->second);
+
+    auto base_tensor = _plan.operands().at(sub_info.base()).ptr();
+
+    assert(base_tensor != nullptr);
+
+    auto curr_tensor = std::make_shared<::arm_compute::SubTensor>(base_tensor, sub_info.shape(),
+                                                                  sub_info.offset());
+
+    _plan.operands().set(::internal::tflite::operand::Index{curr}, curr_tensor);
+  };
+
+  for (auto it = _subsumption_ctx.begin(); it != _subsumption_ctx.end(); ++it)
+  {
+    std::stack<int> stack;
+
+    stack.push(it->first);
+
+    while (!stack.empty())
+    {
+      const auto curr = stack.top();
+
+      if (isAllocated(curr))
+      {
+        // Skip if already allocated
+        stack.pop();
+        continue;
+      }
+
+      auto it_s = _subsumption_ctx.find(curr);
+
+      if (it_s == _subsumption_ctx.end())
+      {
+        if (::internal::arm_compute::isGpuMode())
+          setCLTensor(curr);
+        else
+          setNETensor(curr);
+        stack.pop();
+        continue;
+      }
+
+      const auto &sub_info = *(it_s->second);
+
+      if (isAllocated(sub_info.base().asInt()))
+      {
+        if (::internal::arm_compute::isGpuMode())
+          setCLSubTensor(curr);
+        else
+          setNESubTensor(curr);
+        stack.pop();
+      }
+      else
+      {
+        // Allocate base tensor first
+        stack.push(sub_info.base().asInt());
+      }
+    }
+  }
+
+  for (auto it = _tensor_info_ctx.begin(); it != _tensor_info_ctx.end(); ++it)
+  {
+    if (isAllocated(it->first))
+    {
+      // Skip if already allocated
+      continue;
+    }
+
+    if (::internal::arm_compute::isGpuMode())
+      setCLTensor(it->first);
+    else
+      setNETensor(it->first);
+  }
+
+  // Process Stage
+  AllocationContext allocation_context{_plan};
+  ExecutionBuilder execution_builder{_plan};
+
+  for (int idx = 0; idx < _stages.size(); idx++)
+  {
+    const auto &stage = _stages[idx];
+#ifdef TFLITE_PROFILING_ENABLED
+    int from = execution_builder.plan_op_size();
+#endif
+    stage(allocation_context, execution_builder);
+#ifdef TFLITE_PROFILING_ENABLED
+    int to = execution_builder.plan_op_size();
+    execution_builder.addOpIndexToSteps(from, to, idx);
+#endif
+  }
+
+  // Allocate Tensor Memory
+  for (const auto &tensor : tensors)
+  {
+    if (::internal::arm_compute::isGpuMode())
+    {
+      auto cl_tensor = CAST_CL(tensor.get());
+      cl_tensor->allocator()->allocate();
+    }
+    else
+    {
+      auto ne_tensor = CAST_NE(tensor.get());
+      ne_tensor->allocator()->allocate();
+    }
+  }
+
+  // Fill weight/bias
+  for (auto it = _initializer_ctx.begin(); it != _initializer_ctx.end(); ++it)
+  {
+    const ::internal::tflite::operand::Index operand_index{it->first};
+    _plan.operands().at(operand_index).access(it->second);
+  }
+
+  // Initialize CLTensors that have data in their corresponding NNAPI operand but are not
+  // initialized yet
+  const auto &operands = _plan.model().operands();
+  for (int idx = 0; idx < operands.size(); ++idx)
+  {
+    const ::internal::tflite::operand::Index operand_idx{idx};
+    if (isAllocated(idx) && operands.at(operand_idx).hasData() &&
+        _initializer_ctx.find(idx) == _initializer_ctx.end())
+    {
+      auto rank = operands.at(operand_idx).shape().rank();
+      auto base = operands.at(operand_idx).data().base();
+      auto type = operands.at(operand_idx).type();
+      auto shape = operands.at(operand_idx).shape();
+
+      // Need to support scalar types (ANEURALNETWORKS_FLOAT32 and ANEURALNETWORKS_INT32)
+      // for rank > 1 tensor, because it can be operand of broadcast operation
+      switch (rank)
+      {
+        case 0: // scalar
+        {
+          switch (type)
+          {
+            case ANEURALNETWORKS_FLOAT32:
+            case ANEURALNETWORKS_TENSOR_FLOAT32:
+            {
+              auto initializer = std::bind(initVectorTensor<float>, _1, base, 1);
+              _plan.operands().at(operand_idx).access(initializer);
+              break;
+            }
+            case ANEURALNETWORKS_INT32:
+            case ANEURALNETWORKS_TENSOR_INT32:
+            {
+              auto initializer = std::bind(initVectorTensor<int32_t>, _1, base, 1);
+              _plan.operands().at(operand_idx).access(initializer);
+              break;
+            }
+            case ANEURALNETWORKS_UINT32:
+            {
+              auto initializer = std::bind(initVectorTensor<uint32_t>, _1, base, 1);
+              _plan.operands().at(operand_idx).access(initializer);
+              break;
+            }
+            case ANEURALNETWORKS_TENSOR_QUANT8_ASYMM:
+            {
+              auto initializer = std::bind(initVectorTensor<uint8_t>, _1, base, 1);
+              _plan.operands().at(operand_idx).access(initializer);
+              break;
+            }
+            default:
+              throw std::runtime_error("Unknown scalar type, type : " + std::to_string(type));
+              break;
+          }
+          break;
+        }
+        case 1: // vector
+        {
+          auto size = shape.asVector();
+          switch (type)
+          {
+            case ANEURALNETWORKS_FLOAT32:
+            case ANEURALNETWORKS_TENSOR_FLOAT32:
+            {
+              auto initializer = std::bind(initVectorTensor<float>, _1, base, size);
+              _plan.operands().at(operand_idx).access(initializer);
+              break;
+            }
+            case ANEURALNETWORKS_INT32:
+            case ANEURALNETWORKS_TENSOR_INT32:
+            {
+              auto initializer = std::bind(initVectorTensor<int32_t>, _1, base, size);
+              _plan.operands().at(operand_idx).access(initializer);
+              break;
+            }
+            case ANEURALNETWORKS_TENSOR_QUANT8_ASYMM:
+            {
+              auto initializer = std::bind(initVectorTensor<uint8_t>, _1, base, size);
+              _plan.operands().at(operand_idx).access(initializer);
+              break;
+            }
+            default:
+              throw std::runtime_error("Unknown tensor type, type : " + std::to_string(type));
+              break;
+          }
+          break;
+        }
+        case 2: // matrix
+        {
+          const auto matrix_shape = shape.asMatrix();
+          auto size = operands.at(operand_idx).data().size();
+          switch (type)
+          {
+            case ANEURALNETWORKS_FLOAT32:
+            case ANEURALNETWORKS_TENSOR_FLOAT32:
+            {
+              auto initializer = std::bind(initMatrixTensor<float>, _1, matrix_shape, base, size);
+              _plan.operands().at(operand_idx).access(initializer);
+              break;
+            }
+            case ANEURALNETWORKS_INT32:
+            case ANEURALNETWORKS_TENSOR_INT32:
+            {
+              auto initializer = std::bind(initMatrixTensor<int32_t>, _1, matrix_shape, base, size);
+              _plan.operands().at(operand_idx).access(initializer);
+              break;
+            }
+            case ANEURALNETWORKS_TENSOR_QUANT8_ASYMM:
+            {
+              auto initializer = std::bind(initMatrixTensor<uint8_t>, _1, matrix_shape, base, size);
+              _plan.operands().at(operand_idx).access(initializer);
+              break;
+            }
+            default:
+              throw std::runtime_error("Unknown tensor type, type : " + std::to_string(type));
+              break;
+          }
+          break;
+        }
+        case 3: // 3D tensor
+        {
+          const auto tensor_shape = shape.asTensor();
+          auto size = operands.at(operand_idx).data().size();
+          switch (type)
+          {
+            case ANEURALNETWORKS_FLOAT32:
+            case ANEURALNETWORKS_TENSOR_FLOAT32:
+            {
+              auto initializer = std::bind(initTensor3D<float>, _1, tensor_shape, base, size);
+              _plan.operands().at(operand_idx).access(initializer);
+              break;
+            }
+            case ANEURALNETWORKS_INT32:
+            case ANEURALNETWORKS_TENSOR_INT32:
+            {
+              auto initializer = std::bind(initTensor3D<int32_t>, _1, tensor_shape, base, size);
+              _plan.operands().at(operand_idx).access(initializer);
+              break;
+            }
+            case ANEURALNETWORKS_TENSOR_QUANT8_ASYMM:
+            {
+              auto initializer = std::bind(initTensor3D<uint8_t>, _1, tensor_shape, base, size);
+              _plan.operands().at(operand_idx).access(initializer);
+              break;
+            }
+            default:
+              throw std::runtime_error("Unknown tensor type, type : " + std::to_string(type));
+              break;
+          }
+          break;
+        }
+        case 4: // feature
+        {
+          const auto feature_shape = shape.asFeature();
+          auto size = operands.at(operand_idx).data().size();
+          switch (type)
+          {
+            case ANEURALNETWORKS_FLOAT32:
+            case ANEURALNETWORKS_TENSOR_FLOAT32:
+            {
+              auto initializer = std::bind(initFeatureTensor<float>, _1, feature_shape, base, size);
+              _plan.operands().at(operand_idx).access(initializer);
+              break;
+            }
+            case ANEURALNETWORKS_INT32:
+            case ANEURALNETWORKS_TENSOR_INT32:
+            {
+              auto initializer =
+                  std::bind(initFeatureTensor<int32_t>, _1, feature_shape, base, size);
+              _plan.operands().at(operand_idx).access(initializer);
+              break;
+            }
+            case ANEURALNETWORKS_TENSOR_QUANT8_ASYMM:
+            {
+              auto initializer =
+                  std::bind(initFeatureTensor<uint8_t>, _1, feature_shape, base, size);
+              _plan.operands().at(operand_idx).access(initializer);
+              break;
+            }
+            default:
+              throw std::runtime_error("Unknown tensor type, type : " + std::to_string(type));
+              break;
+          }
+          break;
+        }
+        default:
+          throw std::runtime_error("Not supported, yet");
+          break;
+      }
+    }
+  }
+}
+
+//
+// NNAPI Implementation
+//
+int ANeuralNetworksCompilation_create(ANeuralNetworksModel *model,
+                                      ANeuralNetworksCompilation **compilation)
+{
+  if ((model == nullptr) || (compilation == nullptr))
+  {
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  if (!model->isFinished())
+  {
+    return ANEURALNETWORKS_BAD_STATE;
+  }
+
+  std::shared_ptr<const internal::tflite::Model> internal;
+
+  model->release(internal);
+
+  ANeuralNetworksCompilation *compilation_ptr = new ANeuralNetworksCompilation(internal);
+  if (compilation_ptr == nullptr)
+  {
+    return ANEURALNETWORKS_OUT_OF_MEMORY;
+  }
+  *compilation = compilation_ptr;
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksCompilation_setPreference(ANeuralNetworksCompilation *compilation,
+                                             int32_t preference)
+{
+  if (compilation == nullptr)
+  {
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  // NOTE Pure CL runimte currently ignores this API call
+  // TODO Use preference
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksCompilation_finish(ANeuralNetworksCompilation *compilation)
+{
+  if (compilation == nullptr)
+  {
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  if (::internal::arm_compute::isGpuMode())
+  {
+    arm_compute::CLScheduler::get().default_init();
+    // NOTE CLKernelLibraryEx must use the same context as CLScheduler
+    // It did not check whether another device is available.
+    arm_compute::CLKernelLibraryEx::get().init(
+        "./cl_kernels/", arm_compute::CLScheduler::get().context(), cl::Device::getDefault());
+  }
+
+  const auto &operands = compilation->plan().model().operands();
+  const auto &operations = compilation->plan().model().operations();
+
+  PlanBuilder plan_builder{compilation->plan()};
+
+  for (uint32_t n = 0; n < operations.size(); ++n)
+  {
+    operations.at(n).accept(Planner{operands, plan_builder});
+  }
+
+  plan_builder.finalize();
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+void ANeuralNetworksCompilation_free(ANeuralNetworksCompilation *compilation)
+{
+  delete compilation;
+}
diff --git a/runtime/contrib/pure_arm_compute/src/compilation.h b/runtime/contrib/pure_arm_compute/src/compilation.h
new file mode 100644
index 000000000..1a06d06b9
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/compilation.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file compilation.h
+ * @brief This file defines ANeuralNetworksCompilation class for handling Compilation NNAPI
+ * @ingroup COM_AI_RUNTIME
+ */
+
+#ifndef __COMPILATION_H__
+#define __COMPILATION_H__
+
+#include "internal/Model.h"
+#include "internal/arm_compute.h"
+
+/**
+ * @brief struct to define Compilation of NNAPI
+ */
+struct ANeuralNetworksCompilation
+{
+public:
+  /**
+   * @brief Construct with params
+   * @param [in] model Pointer of internal::tflite::Model to set internal::arm_compute::Plan
+   */
+  ANeuralNetworksCompilation(const std::shared_ptr<const internal::tflite::Model> &model)
+      : _plan{new internal::arm_compute::Plan{model}}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Get reference of internal::arm_compute::Plan
+   * @return Reference of internal::arm_compute::Plan
+   */
+  internal::arm_compute::Plan &plan(void) { return *_plan; }
+
+public:
+  /**
+   * @brief Publish internal Plan to param
+   * @param [out] plan Pointer of internal::arm_compute::Plan to be set
+   * @return N/A
+   */
+  void publish(std::shared_ptr<const internal::arm_compute::Plan> &plan) { plan = _plan; }
+  /**
+   * @brief Get @c true if ANeuralNetworksCompilation_finish has been called, otherwise @c false
+   * @return @c true if ANeuralNetworksCompilation_finish has been called, otherwise @c false
+   */
+  bool isFinished(void) { return _isFinished; }
+  /**
+   * @brief Mark compilation process finished
+   * @return N/A
+   */
+  void markAsFinished() { _isFinished = true; }
+
+private:
+  std::shared_ptr<internal::arm_compute::Plan> _plan;
+  bool _isFinished{false};
+};
+
+#endif
diff --git a/runtime/contrib/pure_arm_compute/src/event.cc b/runtime/contrib/pure_arm_compute/src/event.cc
new file mode 100644
index 000000000..247586cc3
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/event.cc
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <NeuralNetworks.h>
+
+#include "event.h"
+
+int ANeuralNetworksEvent_wait(ANeuralNetworksEvent *event)
+{
+  if (event == nullptr)
+  {
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+void ANeuralNetworksEvent_free(ANeuralNetworksEvent *event) { delete event; }
diff --git a/runtime/contrib/pure_arm_compute/src/event.h b/runtime/contrib/pure_arm_compute/src/event.h
new file mode 100644
index 000000000..b5595583c
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/event.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file event.h
+ * @brief This file defines ANeuralNetworksEvent struct for handling Event NNAPI
+ * @ingroup COM_AI_RUNTIME
+ */
+
+#ifndef __EVENT_H__
+#define __EVENT_H__
+
+/**
+ * @brief struct to define Event of NNAPI
+ */
+struct ANeuralNetworksEvent
+{
+};
+
+#endif
diff --git a/runtime/contrib/pure_arm_compute/src/execution.cc b/runtime/contrib/pure_arm_compute/src/execution.cc
new file mode 100644
index 000000000..657d25288
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/execution.cc
@@ -0,0 +1,628 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <NeuralNetworks.h>
+
+#include "compilation.h"
+#include "execution.h"
+#include "profiling/profiling.h"
+#include "profiling/profiler.h"
+#include "event.h"
+
+#include "internal/VectorSource.h"
+#include "internal/MatrixSource.h"
+#include "internal/Tensor3DSource.h"
+#include "internal/FeatureSource.h"
+#include "internal/TensorSource.h"
+
+#include "internal/Sinks.h"
+#include "internal/VectorSink.h"
+#include "internal/MatrixSink.h"
+#include "internal/Tensor3DSink.h"
+#include "internal/FeatureSink.h"
+
+#include "misc/feature/IndexIterator.h"
+
+#include <arm_compute/runtime/CL/CLScheduler.h>
+
+#include <cassert>
+
+static void asVectorSource(ANeuralNetworksExecution *execution, int32_t type, int32_t index,
+                           int32_t len, const void *buffer, size_t length)
+{
+  switch (type)
+  {
+    case ANEURALNETWORKS_FLOAT32:
+    case ANEURALNETWORKS_TENSOR_FLOAT32:
+      execution->source<VectorSource<float>>(index, len, reinterpret_cast<const float *>(buffer),
+                                             length);
+      break;
+    case ANEURALNETWORKS_INT32:
+    case ANEURALNETWORKS_TENSOR_INT32:
+      execution->source<VectorSource<int32_t>>(index, len,
+                                               reinterpret_cast<const int32_t *>(buffer), length);
+      break;
+    case ANEURALNETWORKS_UINT32:
+      execution->source<VectorSource<uint32_t>>(index, len,
+                                                reinterpret_cast<const uint32_t *>(buffer), length);
+      break;
+    case ANEURALNETWORKS_TENSOR_QUANT8_ASYMM:
+      execution->source<VectorSource<uint8_t>>(index, len,
+                                               reinterpret_cast<const uint8_t *>(buffer), length);
+      break;
+    default:
+      throw std::runtime_error("Not supported, yet");
+      break;
+  }
+}
+
+static void asMatrixSource(ANeuralNetworksExecution *execution, int32_t type, int32_t index,
+                           const nnfw::misc::matrix::Shape &shape, const void *buffer,
+                           size_t length)
+{
+  switch (type)
+  {
+    case ANEURALNETWORKS_FLOAT32:
+    case ANEURALNETWORKS_TENSOR_FLOAT32:
+      execution->source<MatrixSource<float>>(index, shape, reinterpret_cast<const float *>(buffer),
+                                             length);
+      break;
+    case ANEURALNETWORKS_INT32:
+    case ANEURALNETWORKS_TENSOR_INT32:
+      execution->source<MatrixSource<int32_t>>(index, shape,
+                                               reinterpret_cast<const int32_t *>(buffer), length);
+      break;
+    case ANEURALNETWORKS_UINT32:
+      execution->source<MatrixSource<uint32_t>>(index, shape,
+                                                reinterpret_cast<const uint32_t *>(buffer), length);
+      break;
+    case ANEURALNETWORKS_TENSOR_QUANT8_ASYMM:
+      execution->source<MatrixSource<uint8_t>>(index, shape,
+                                               reinterpret_cast<const uint8_t *>(buffer), length);
+      break;
+    default:
+      throw std::runtime_error("Not supported, yet");
+      break;
+  }
+}
+
+static void asTensor3DSource(ANeuralNetworksExecution *execution, int32_t type, int32_t index,
+                             const nnfw::misc::tensor::Shape &shape, const void *buffer,
+                             size_t length)
+{
+  switch (type)
+  {
+    case ANEURALNETWORKS_FLOAT32:
+    case ANEURALNETWORKS_TENSOR_FLOAT32:
+      execution->source<Tensor3DSource<float>>(index, shape,
+                                               reinterpret_cast<const float *>(buffer), length);
+      break;
+    case ANEURALNETWORKS_INT32:
+    case ANEURALNETWORKS_TENSOR_INT32:
+      execution->source<Tensor3DSource<int32_t>>(index, shape,
+                                                 reinterpret_cast<const int32_t *>(buffer), length);
+      break;
+    case ANEURALNETWORKS_UINT32:
+      execution->source<Tensor3DSource<uint32_t>>(
+          index, shape, reinterpret_cast<const uint32_t *>(buffer), length);
+      break;
+    case ANEURALNETWORKS_TENSOR_QUANT8_ASYMM:
+      execution->source<Tensor3DSource<uint8_t>>(index, shape,
+                                                 reinterpret_cast<const uint8_t *>(buffer), length);
+      break;
+    default:
+      throw std::runtime_error("Not supported, yet");
+      break;
+  }
+}
+
+static void asTensorSource(ANeuralNetworksExecution *execution, int32_t type, int32_t index,
+                           const nnfw::misc::tensor::Shape &shape, const void *buffer,
+                           size_t length)
+{
+  switch (type)
+  {
+    case ANEURALNETWORKS_FLOAT32:
+    case ANEURALNETWORKS_TENSOR_FLOAT32:
+      execution->source<TensorSource<float>>(index, shape, reinterpret_cast<const float *>(buffer),
+                                             length);
+      break;
+    case ANEURALNETWORKS_INT32:
+    case ANEURALNETWORKS_TENSOR_INT32:
+      execution->source<TensorSource<int32_t>>(index, shape,
+                                               reinterpret_cast<const int32_t *>(buffer), length);
+      break;
+    case ANEURALNETWORKS_UINT32:
+      execution->source<TensorSource<uint32_t>>(index, shape,
+                                                reinterpret_cast<const uint32_t *>(buffer), length);
+      break;
+    case ANEURALNETWORKS_TENSOR_QUANT8_ASYMM:
+      execution->source<TensorSource<uint8_t>>(index, shape,
+                                               reinterpret_cast<const uint8_t *>(buffer), length);
+      break;
+    default:
+      throw std::runtime_error("Not supported, yet");
+      break;
+  }
+}
+
+static void asFeatureSource(ANeuralNetworksExecution *execution, int32_t type, int32_t index,
+                            const nnfw::misc::feature::Shape &shape, const void *buffer,
+                            size_t length)
+{
+  switch (type)
+  {
+    case ANEURALNETWORKS_FLOAT32:
+    case ANEURALNETWORKS_TENSOR_FLOAT32:
+      execution->source<FeatureSource<float>>(index, shape, reinterpret_cast<const float *>(buffer),
+                                              length);
+      break;
+    case ANEURALNETWORKS_INT32:
+    case ANEURALNETWORKS_TENSOR_INT32:
+      execution->source<FeatureSource<int32_t>>(index, shape,
+                                                reinterpret_cast<const int32_t *>(buffer), length);
+      break;
+    case ANEURALNETWORKS_UINT32:
+      execution->source<FeatureSource<uint32_t>>(
+          index, shape, reinterpret_cast<const uint32_t *>(buffer), length);
+      break;
+    case ANEURALNETWORKS_TENSOR_QUANT8_ASYMM:
+      execution->source<FeatureSource<uint8_t>>(index, shape,
+                                                reinterpret_cast<const uint8_t *>(buffer), length);
+      break;
+    default:
+      throw std::runtime_error("Not supported, yet");
+      break;
+  }
+}
+
+static void asVectorSink(ANeuralNetworksExecution *execution, int32_t type, int32_t index,
+                         int32_t len, void *buffer, size_t length)
+{
+  switch (type)
+  {
+    case ANEURALNETWORKS_FLOAT32:
+    case ANEURALNETWORKS_TENSOR_FLOAT32:
+      execution->sink<VectorSink<float>>(index, len, reinterpret_cast<float *>(buffer), length);
+      break;
+    case ANEURALNETWORKS_INT32:
+    case ANEURALNETWORKS_TENSOR_INT32:
+      execution->sink<VectorSink<int32_t>>(index, len, reinterpret_cast<int32_t *>(buffer), length);
+      break;
+    case ANEURALNETWORKS_UINT32:
+      execution->sink<VectorSink<uint32_t>>(index, len, reinterpret_cast<uint32_t *>(buffer),
+                                            length);
+      break;
+    case ANEURALNETWORKS_TENSOR_QUANT8_ASYMM:
+      execution->sink<VectorSink<uint8_t>>(index, len, reinterpret_cast<uint8_t *>(buffer), length);
+      break;
+    default:
+      throw std::runtime_error("Not supported, yet");
+      break;
+  }
+}
+
+static void asMatrixSink(ANeuralNetworksExecution *execution, int32_t type, int32_t index,
+                         int32_t H, int32_t W, void *buffer, size_t length)
+{
+  switch (type)
+  {
+    case ANEURALNETWORKS_FLOAT32:
+    case ANEURALNETWORKS_TENSOR_FLOAT32:
+      execution->sink<MatrixSink<float>>(index, H, W, reinterpret_cast<float *>(buffer), length);
+      break;
+    case ANEURALNETWORKS_INT32:
+    case ANEURALNETWORKS_TENSOR_INT32:
+      execution->sink<MatrixSink<int32_t>>(index, H, W, reinterpret_cast<int32_t *>(buffer),
+                                           length);
+      break;
+    case ANEURALNETWORKS_UINT32:
+      execution->sink<MatrixSink<uint32_t>>(index, H, W, reinterpret_cast<uint32_t *>(buffer),
+                                            length);
+      break;
+    case ANEURALNETWORKS_TENSOR_QUANT8_ASYMM:
+      execution->sink<MatrixSink<uint8_t>>(index, H, W, reinterpret_cast<uint8_t *>(buffer),
+                                           length);
+      break;
+    default:
+      throw std::runtime_error("Not supported, yet");
+      break;
+  }
+}
+
+static void asFeatureSink(ANeuralNetworksExecution *execution, int32_t type, int32_t index,
+                          const nnfw::misc::feature::Shape &shape, void *buffer, size_t length)
+{
+  switch (type)
+  {
+    case ANEURALNETWORKS_FLOAT32:
+    case ANEURALNETWORKS_TENSOR_FLOAT32:
+      execution->sink<FeatureSink<float>>(index, shape, reinterpret_cast<float *>(buffer), length);
+      break;
+    case ANEURALNETWORKS_INT32:
+    case ANEURALNETWORKS_TENSOR_INT32:
+      execution->sink<FeatureSink<int32_t>>(index, shape, reinterpret_cast<int32_t *>(buffer),
+                                            length);
+      break;
+    case ANEURALNETWORKS_UINT32:
+      execution->sink<FeatureSink<uint32_t>>(index, shape, reinterpret_cast<uint32_t *>(buffer),
+                                             length);
+      break;
+    case ANEURALNETWORKS_TENSOR_QUANT8_ASYMM:
+      execution->sink<FeatureSink<uint8_t>>(index, shape, reinterpret_cast<uint8_t *>(buffer),
+                                            length);
+      break;
+    default:
+      throw std::runtime_error("Not supported, yet");
+      break;
+  }
+}
+
+static void asTensor3DSink(ANeuralNetworksExecution *execution, int32_t type, int32_t index,
+                           const nnfw::misc::tensor::Shape &shape, void *buffer, size_t length)
+{
+  assert(shape.rank() == 3);
+
+  switch (type)
+  {
+    case ANEURALNETWORKS_FLOAT32:
+    case ANEURALNETWORKS_TENSOR_FLOAT32:
+      execution->sink<Tensor3DSink<float>>(index, shape, reinterpret_cast<float *>(buffer), length);
+      break;
+    case ANEURALNETWORKS_INT32:
+    case ANEURALNETWORKS_TENSOR_INT32:
+      execution->sink<Tensor3DSink<int32_t>>(index, shape, reinterpret_cast<int32_t *>(buffer),
+                                             length);
+      break;
+    case ANEURALNETWORKS_UINT32:
+      execution->sink<Tensor3DSink<uint32_t>>(index, shape, reinterpret_cast<uint32_t *>(buffer),
+                                              length);
+      break;
+    case ANEURALNETWORKS_TENSOR_QUANT8_ASYMM:
+      execution->sink<Tensor3DSink<uint8_t>>(index, shape, reinterpret_cast<uint8_t *>(buffer),
+                                             length);
+      break;
+    default:
+      throw std::runtime_error("Not supported, yet");
+      break;
+  }
+}
+
+static void asTensorSink(ANeuralNetworksExecution *execution, int32_t type, int32_t index,
+                         const nnfw::misc::tensor::Shape &shape, void *buffer, size_t length)
+{
+  switch (type)
+  {
+    case ANEURALNETWORKS_FLOAT32:
+    case ANEURALNETWORKS_TENSOR_FLOAT32:
+      execution->sink<TensorSink<float>>(index, shape, reinterpret_cast<float *>(buffer), length);
+      break;
+    case ANEURALNETWORKS_INT32:
+    case ANEURALNETWORKS_TENSOR_INT32:
+      execution->sink<TensorSink<int32_t>>(index, shape, reinterpret_cast<int32_t *>(buffer),
+                                           length);
+      break;
+    case ANEURALNETWORKS_UINT32:
+      execution->sink<TensorSink<uint32_t>>(index, shape, reinterpret_cast<uint32_t *>(buffer),
+                                            length);
+      break;
+    case ANEURALNETWORKS_TENSOR_QUANT8_ASYMM:
+      execution->sink<TensorSink<uint8_t>>(index, shape, reinterpret_cast<uint8_t *>(buffer),
+                                           length);
+      break;
+    default:
+      throw std::runtime_error("Not supported, yet");
+      break;
+  }
+}
+
+//
+// NNAPI Implementation
+//
+int ANeuralNetworksExecution_create(ANeuralNetworksCompilation *compilation,
+                                    ANeuralNetworksExecution **execution)
+{
+  if ((compilation == nullptr) || (execution == nullptr))
+  {
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  std::shared_ptr<const ::internal::arm_compute::Plan> plan;
+  compilation->publish(plan);
+  ANeuralNetworksExecution *execution_ptr = new ANeuralNetworksExecution{plan};
+  if (execution_ptr == nullptr)
+  {
+    return ANEURALNETWORKS_OUT_OF_MEMORY;
+  }
+  *execution = execution_ptr;
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksExecution_setInput(ANeuralNetworksExecution *execution, int32_t index,
+                                      const ANeuralNetworksOperandType *type, const void *buffer,
+                                      size_t length)
+{
+  // Don't check type
+  // Comment about ANeuralNetworksOperandType in NeuralNetworks.h:
+  //  If the input or output is optional and omitted then it need not have a fully specified tensor
+  //  operand type
+  if ((execution == nullptr) || ((buffer == nullptr) && (length != 0)))
+  {
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  const auto &operands = execution->plan().model().operands();
+
+  // TODO Check type conflicts
+
+  // NOTE The current implemenation assumes that every input is a feature map.
+  // TODO Remove this assumption
+  const auto operand_index = execution->plan().model().inputs.at(index);
+  int32_t input_type = operands.at(operand_index).type();
+  // NOTE TFLite passes type parameter unconditionally as nullptr.
+  // Is it necessary to reget type value already set in model step?
+  if (type != nullptr)
+  {
+    input_type = type->type;
+  }
+
+  auto shape = operands.at(operand_index).shape();
+  auto rank = shape.rank();
+
+  if (rank == 1)
+  {
+    const auto len = shape.dim(0);
+
+    asVectorSource(execution, input_type, index, len, buffer, length);
+  }
+  else if (rank == 2)
+  {
+    const auto &operand_shape = shape.asMatrix();
+
+    asMatrixSource(execution, input_type, index, operand_shape, buffer, length);
+  }
+  else if (rank == 3)
+  {
+    const auto &operand_shape = shape.asTensor();
+
+    asTensor3DSource(execution, input_type, index, operand_shape, buffer, length);
+  }
+  else if (rank == 4)
+  {
+    const auto &operand_shape = shape.asFeature();
+
+    asFeatureSource(execution, input_type, index, operand_shape, buffer, length);
+  }
+  else
+  {
+    // NOTE TensorSource is much slower than specialized Source(s)
+    const auto &operand_shape = shape.asTensor();
+
+    asTensorSource(execution, input_type, index, operand_shape, buffer, length);
+  }
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+// squeeze(shape) eliminates all the dimensions whose dimensionality is 1
+// For example, squeeze([3, 1, 3]) returns [3, 3]
+static nnfw::misc::tensor::Shape squeeze(const nnfw::misc::tensor::Shape &shape)
+{
+  nnfw::misc::tensor::Shape res(0);
+
+  for (uint32_t axis = 0; axis < shape.rank(); ++axis)
+  {
+    if (shape.dim(axis) != 1)
+    {
+      res.append(shape.dim(axis));
+    }
+  }
+
+  return res;
+}
+
+int ANeuralNetworksExecution_setOutput(ANeuralNetworksExecution *execution, int32_t index,
+                                       const ANeuralNetworksOperandType *type, void *buffer,
+                                       size_t length)
+{
+  // Don't check type
+  // Comment about ANeuralNetworksOperandType in NeuralNetworks.h:
+  //  If the input or output is optional and omitted then it need not have a fully specified tensor
+  //  operand type
+  if ((execution == nullptr) || ((buffer == nullptr) && (length != 0)))
+  {
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  const auto &operands = execution->plan().model().operands();
+
+  // TODO Check type conflicts
+
+  const auto operand_index = execution->plan().model().outputs.at(index);
+  int32_t output_type = operands.at(operand_index).type();
+  const auto &output_shape = operands.at(operand_index).shape();
+
+  if (output_shape.rank() == 1)
+  {
+    const auto len = output_shape.dim(0);
+
+    asVectorSink(execution, output_type, index, len, buffer, length);
+  }
+  else if (output_shape.rank() == 2)
+  {
+    const auto H = output_shape.dim(0);
+    const auto W = output_shape.dim(1);
+
+    asMatrixSink(execution, output_type, index, H, W, buffer, length);
+  }
+  else if (output_shape.rank() == 3)
+  {
+    asTensor3DSink(execution, output_type, index, output_shape, buffer, length);
+  }
+  else if ((output_shape.rank() == 4))
+  {
+    const auto &operand_shape = operands.at(operand_index).shape().asFeature();
+
+    asFeatureSink(execution, output_type, index, operand_shape, buffer, length);
+  }
+  else
+  {
+    // NOTE TensorSink is much slower than specialized Sink(s)
+    const auto &shape = operands.at(operand_index).shape();
+    asTensorSink(execution, output_type, index, shape, buffer, length);
+  }
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksExecution_startCompute(ANeuralNetworksExecution *execution,
+                                          ANeuralNetworksEvent **event)
+{
+  if ((execution == nullptr) || (event == nullptr))
+  {
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  // TODO: Handle event
+  ANeuralNetworksEvent *event_ptr = new ANeuralNetworksEvent{};
+  if (event_ptr == nullptr)
+  {
+    return ANEURALNETWORKS_OUT_OF_MEMORY;
+  }
+  *event = event_ptr;
+
+  return ANeuralNetworksExecution_compute(execution);
+}
+
+int ANeuralNetworksExecution_compute(ANeuralNetworksExecution *execution)
+{
+  if (execution == nullptr)
+  {
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  const bool sync = profiling::Context::get().sync();
+  const auto &plan = execution->plan();
+  const auto &model = plan.model();
+
+  // Set input(s)
+  for (uint32_t n = 0; n < model.inputs.size(); ++n)
+  {
+    auto setter = [&](::arm_compute::ITensor &tensor) { execution->source(n).push(tensor); };
+
+    // Some operand may not be defined at plan. Because some operands
+    // may be useless at ACL (ex. shape tensor for Reshape operator)
+    // So added a sanity check.
+    if (plan.operands().exist(model.inputs.at(n)))
+    {
+      plan.operands().at(model.inputs.at(n)).access(setter);
+    }
+  }
+
+  const auto &operations = execution->plan().operations();
+
+  for (uint32_t n = 0; n < operations.size(); ++n)
+  {
+    auto prof = profiling::Context::get().getProfiler();
+    SCOPED_OPERATOR_PROFILE(prof, operations.at(n).op_idx());
+    operations.at(n).run();
+
+    if (sync)
+    {
+      arm_compute::CLScheduler::get().sync();
+    }
+  }
+
+  // Get output(s)
+  for (uint32_t n = 0; n < model.outputs.size(); ++n)
+  {
+    auto getter = [&](::arm_compute::ITensor &tensor) { execution->sink(n).pull(tensor); };
+
+    plan.operands().at(model.outputs.at(n)).access(getter);
+  }
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+void ANeuralNetworksExecution_free(ANeuralNetworksExecution *execution) {}
+
+// TODO: implement this. added to fix link error on test build.
+int ANeuralNetworksExecution_setInputFromMemory(ANeuralNetworksExecution *execution, int32_t index,
+                                                const ANeuralNetworksOperandType *type,
+                                                const ANeuralNetworksMemory *memory, size_t offset,
+                                                size_t length)
+{
+  if ((execution == nullptr) || (memory == nullptr))
+  {
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  assert(false);
+  return -1;
+}
+
+// TODO: implement this. added to fix link error on test build.
+int ANeuralNetworksExecution_setOutputFromMemory(ANeuralNetworksExecution *execution, int32_t index,
+                                                 const ANeuralNetworksOperandType *type,
+                                                 const ANeuralNetworksMemory *memory, size_t offset,
+                                                 size_t length)
+{
+  if ((execution == nullptr) || (memory == nullptr))
+  {
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  assert(false);
+  return -1;
+}
+
+int ANeuralNetworksExecution_getOutputOperandRank(ANeuralNetworksExecution *execution,
+                                                  int32_t index, uint32_t *rank)
+{
+  if ((execution == nullptr) || (rank == nullptr))
+  {
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  const auto &operands = execution->plan().model().operands();
+  const auto operand_index = execution->plan().model().outputs.at(index);
+  const auto &output_shape = operands.at(operand_index).shape();
+
+  *rank = output_shape.rank();
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksExecution_getOutputOperandDimensions(ANeuralNetworksExecution *execution,
+                                                        int32_t index, uint32_t *dimensions)
+{
+  if ((execution == nullptr) || (dimensions == nullptr))
+  {
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  const auto &operands = execution->plan().model().operands();
+  const auto operand_index = execution->plan().model().outputs.at(index);
+  const auto &output_shape = operands.at(operand_index).shape();
+
+  for (uint32_t axis = 0; axis < output_shape.rank(); ++axis)
+  {
+    dimensions[axis] = static_cast<uint32_t>(output_shape.dim(axis));
+  }
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
diff --git a/runtime/contrib/pure_arm_compute/src/execution.h b/runtime/contrib/pure_arm_compute/src/execution.h
new file mode 100644
index 000000000..f55ab3fbf
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/execution.h
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file execution.h
+ * @brief This file contains ANeuralNetworksExecution class for handling Execution NNAPI such as
+ * ANeuralNetworksExecution_create, ANeuralNetworksExecution_setInput
+ * @ingroup COM_AI_RUNTIME
+ */
+
+#ifndef __EXECUTION_H__
+#define __EXECUTION_H__
+
+#include "internal/arm_compute.h"
+#include "internal/Sink.h"
+#include "internal/Source.h"
+
+/**
+ * @brief struct to express Execution of NNAPI
+ */
+struct ANeuralNetworksExecution
+{
+public:
+  /**
+   * @brief Construct with params
+   * @param [in] plan Pointer to get internal::arm_compute::Plan
+   */
+  ANeuralNetworksExecution(const std::shared_ptr<const internal::arm_compute::Plan> &plan)
+      : _plan{plan}
+  {
+    _sources.resize(_plan->model().inputs.size());
+    _sinks.resize(_plan->model().outputs.size());
+  }
+
+public:
+  /**
+   * @brief Get reference of internal::arm_compute::Plan
+   * @return Const reference of internal::arm_compute::Plan
+   */
+  const internal::arm_compute::Plan &plan(void) const { return *_plan; }
+
+private:
+  std::shared_ptr<const internal::arm_compute::Plan> _plan;
+
+public:
+  /**
+   * @brief Set the nth source with param
+   * @param [in] n Index of the nth source
+   * @param [in] source Pointer to set the nth source from
+   * @return N/A
+   */
+  // TODO Use InputIndex instead of int
+  void source(int n, std::unique_ptr<Source> &&source) { _sources.at(n) = std::move(source); }
+  /**
+   * @brief Set the nth source with param
+   * @param [in] n Index of the nth source
+   * @param [in] args Arguments to set the nth source from
+   * @return N/A
+   */
+  template <typename T, typename... Args> void source(int n, Args &&... args)
+  {
+    source(n, std::unique_ptr<T>{new T{std::forward<Args>(args)...}});
+  }
+
+public:
+  /**
+   * @brief Get the nth source
+   * @param [in] n Index of the nth source
+   * @return Const reference of Source
+   */
+  const Source &source(int n) const { return *(_sources.at(n)); }
+
+public:
+  /**
+   * @brief Set the nth sink with param
+   * @param [in] n Index of the nth sink
+   * @param [in] sink Pointer to set the nth sink from
+   * @return N/A
+   */
+  // TODO Use OutputIndex instead of int
+  void sink(int n, std::unique_ptr<Sink> &&sink) { _sinks.at(n) = std::move(sink); }
+  /**
+   * @brief Set the nth sink with param
+   * @param [in] n Index of the nth sink
+   * @param [in] args Arguments to set the nth sink from
+   * @return N/A
+   */
+  template <typename T, typename... Args> void sink(int n, Args &&... args)
+  {
+    sink(n, std::unique_ptr<T>{new T{std::forward<Args>(args)...}});
+  }
+
+public:
+  /**
+   * @brief Get the nth sink
+   * @param [in] n Index of the nth sink
+   * @return Const reference of Sink
+   */
+  const Sink &sink(int n) const { return *(_sinks.at(n)); }
+
+private:
+  std::vector<std::unique_ptr<Source>> _sources;
+  std::vector<std::unique_ptr<Sink>> _sinks;
+};
+
+#endif
diff --git a/runtime/contrib/pure_arm_compute/src/internal/FeatureSink.h b/runtime/contrib/pure_arm_compute/src/internal/FeatureSink.h
new file mode 100644
index 000000000..7c6884141
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/FeatureSink.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file        FeatureSink.h
+ * @brief       This file contains FeatureSink class
+ * @ingroup     COM_AI_RUNTIME
+ */
+
+#ifndef __INTERNAL_FEATURE_SINK_H__
+#define __INTERNAL_FEATURE_SINK_H__
+
+#include "internal/Sink.h"
+#include "internal/nnapi/feature/View.h"
+#include "internal/arm_compute/feature/View.h"
+
+#include <misc/feature/Shape.h>
+#include "misc/feature/IndexIterator.h"
+
+/**
+ * @brief Class to store Feature(4D) output data.
+ * This is for pulling data to internal tensor from other tensor.
+ * @tparam T Type of the data elements
+ */
+template <typename T> class FeatureSink final : public Sink
+{
+public:
+  /**
+   * @brief Construct a FeatureSink object
+   *
+   * @param[in] shape 4D tensor dimensions for this feature
+   * @param[in] base Base pointer of the actual data
+   * @param[in] size Size of the data
+   */
+  FeatureSink(const nnfw::misc::feature::Shape &shape, T *base, const size_t size)
+      : _shape{shape}, _base{base}, _size{size}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Pull the data into the internal structure
+   * @param[in] tensor The tensor which contains source data
+   * @return N/A
+   */
+  void pull(::arm_compute::ITensor &tensor) const override
+  {
+    const ::internal::arm_compute::feature::View<T> from{&tensor};
+    // TODO Should remove casting.
+    // Inevitably casting must be done.
+    ::internal::nnapi::feature::View<T> into{_shape, _base, _size};
+
+    ::nnfw::misc::feature::iterate(_shape)
+        << [&](uint32_t batch, uint32_t ch, uint32_t row, uint32_t col) {
+             const auto value = from.at(batch, ch, row, col);
+             into.at(batch, ch, row, col) = value;
+           };
+  }
+
+private:
+  const nnfw::misc::feature::Shape _shape;
+  T *const _base;
+  const size_t _size;
+};
+
+#endif // __INTERNAL_FEATURE_SINK_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/FeatureSource.h b/runtime/contrib/pure_arm_compute/src/internal/FeatureSource.h
new file mode 100644
index 000000000..772beb701
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/FeatureSource.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file        FeatureSource.h
+ * @brief       This file contains FeatureSource class
+ * @ingroup     COM_AI_RUNTIME
+ */
+
+#ifndef __INTERNAL_FEATURE_SOURCE_H__
+#define __INTERNAL_FEATURE_SOURCE_H__
+
+#include <misc/feature/Shape.h>
+#include <misc/feature/IndexIterator.h>
+
+#include "internal/nnapi/feature/Reader.h"
+#include "internal/arm_compute/feature/View.h"
+
+/**
+ * @brief Class to store feature(4D) input data.
+ * This is for push out the data to another tensor.
+ * @tparam T Type of the data elements
+ */
+template <typename T> class FeatureSource final : public Source
+{
+public:
+  /**
+   * @brief Construct a FeatureSource object
+   *
+   * @param[in] shape 4D tensor dimensions for this feature
+   * @param[in] base Base pointer of the actual data
+   * @param[in] size Size of the data
+   */
+  FeatureSource(const nnfw::misc::feature::Shape &shape, const T *base, const size_t size)
+      : _shape{shape}, _base{base}, _size{size}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Push the data out to the another tensor
+   * @param[out] The tensor that output data will be stored
+   * @return N/A
+   */
+  void push(::arm_compute::ITensor &tensor) const override
+  {
+    const ::internal::nnapi::feature::Reader<T> from{_shape, _base, _size};
+    ::internal::arm_compute::feature::View<T> into{&tensor};
+
+    ::nnfw::misc::feature::iterate(_shape)
+        << [&](uint32_t batch, uint32_t ch, uint32_t row, uint32_t col) {
+             const auto value = from.at(batch, ch, row, col);
+             into.at(batch, ch, row, col) = value;
+           };
+  }
+
+private:
+  const nnfw::misc::feature::Shape _shape;
+  const T *const _base;
+  const size_t _size;
+};
+
+#endif // __INTERNAL_FEATURE_SOURCE_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/IExecutionBuilder.h b/runtime/contrib/pure_arm_compute/src/internal/IExecutionBuilder.h
new file mode 100644
index 000000000..2a6e2a743
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/IExecutionBuilder.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    IExecutionBuilder.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines interface of ExecutionBuilder
+ */
+#ifndef __INTERNAL_IEXECUTION_BUILDER_H__
+#define __INTERNAL_IEXECUTION_BUILDER_H__
+
+#include <arm_compute/runtime/IFunction.h>
+
+#include <memory>
+#include <string>
+
+/**
+ * @brief Struct to define interface of ExecutionBuilder
+ */
+struct IExecutionBuilder
+{
+  /**
+   * @brief Destroy the IExecutionBuilder object
+   */
+  virtual ~IExecutionBuilder() = default;
+
+  /**
+   * @brief     Append function to execute
+   * @param[in] name  Name of function
+   * @param[in] f     Function to append
+   * @return    N/A
+   */
+  virtual void append(const std::string &name, std::unique_ptr<::arm_compute::IFunction> &&f) = 0;
+};
+
+#endif // __INTERNAL_IEXECUTION_BUILDER_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/MatrixSink.h b/runtime/contrib/pure_arm_compute/src/internal/MatrixSink.h
new file mode 100644
index 000000000..23ecc112b
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/MatrixSink.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    MatrixSink.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines MatrixSink class
+ */
+#ifndef __INTERNAL_MATRIX_SINK_H__
+#define __INTERNAL_MATRIX_SINK_H__
+
+#include "internal/Sink.h"
+
+#include <arm_compute/core/ITensor.h>
+#include <arm_compute/core/Window.h>
+#include <arm_compute/core/Helpers.h>
+
+#include <cstdint>
+#include <cstring>
+#include <cassert>
+
+/**
+ * @brief Class to get matrix data from arm compute tensor
+ */
+template <typename T> class MatrixSink final : public Sink
+{
+public:
+  /**
+   * @brief Construct a new Matrix Sink object
+   * @param[in] H     Height of matrix
+   * @param[in] W     Width of matrix
+   * @param[in] base  Pointer to get data
+   * @param[in] size  Size of matrix
+   */
+  MatrixSink(const int32_t H, const int32_t W, T *base, const size_t size)
+      : _height{H}, _width{W}, _base{base}
+  {
+    assert(size >= _height * _width * sizeof(T));
+  }
+
+public:
+  /**
+   * @brief     Get matrix data from arm compute tensor to base
+   * @param[in] tensor  Tensor object of arm compute to get data
+   * @return    N/A
+   */
+  void pull(::arm_compute::ITensor &tensor) const override
+  {
+    assert(tensor.info()->dimension(0) == _width);
+    assert(tensor.info()->dimension(1) == _height);
+
+    using ::arm_compute::Window;
+    using ::arm_compute::Iterator;
+    using ::arm_compute::Coordinates;
+    using ::arm_compute::execute_window_loop;
+
+    Window window;
+
+    window.use_tensor_dimensions(tensor.info()->tensor_shape(), ::arm_compute::Window::DimY);
+
+    Iterator it(&tensor, window);
+    execute_window_loop(window,
+                        [&](const ::arm_compute::Coordinates &id) {
+                          const auto row = id.y();
+                          memcpy(_base + row * _width, it.ptr(), _width * sizeof(T));
+                        },
+                        it);
+  }
+
+private:
+  const int32_t _height;
+  const int32_t _width;
+
+private:
+  T *const _base;
+};
+
+#endif // __INTERNAL_MATRIX_SINK_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/MatrixSource.h b/runtime/contrib/pure_arm_compute/src/internal/MatrixSource.h
new file mode 100644
index 000000000..71d6a804f
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/MatrixSource.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    MatrixSource.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines MatrixSource class
+ */
+#ifndef __INTERNAL_MATRIX_SOURCE_H__
+#define __INTERNAL_MATRIX_SOURCE_H__
+
+#include <arm_compute/core/ITensor.h>
+#include <arm_compute/core/Window.h>
+#include <arm_compute/core/Helpers.h>
+
+#include "internal/Source.h"
+
+/**
+ * @brief Class to push matrix data to arm compute tensor
+ */
+template <typename T> class MatrixSource final : public Source
+{
+public:
+  /**
+   * @brief Construct a new MatrixSource object
+   * @param[in] shape Shape of matrix
+   * @param[in] base  Pointer of matrix data to push
+   * @param[in] size  Size of matrix
+   */
+  MatrixSource(const nnfw::misc::matrix::Shape &shape, const T *base, const size_t size)
+      : _shape{shape}, _base{base}, _size{size}
+  {
+    // do nothing
+  }
+
+public:
+  /**
+   * @brief       Push matrix data to arm compute tensor
+   * @param[out]  tensor  Tensor object of arm compute to push matrix data
+   * @return      N/A
+   */
+  void push(::arm_compute::ITensor &tensor) const override
+  {
+    using ::arm_compute::Window;
+    using ::arm_compute::Iterator;
+    using ::arm_compute::Coordinates;
+    using ::arm_compute::execute_window_loop;
+
+    Window window;
+    window.use_tensor_dimensions(tensor.info()->tensor_shape(), ::arm_compute::Window::DimY);
+
+    int32_t width = _shape.W;
+
+    Iterator it(&tensor, window);
+    execute_window_loop(window,
+                        [&](const ::arm_compute::Coordinates &id) {
+                          const auto height = id.y();
+                          memcpy(it.ptr(), _base + height * width, width * sizeof(T));
+                        },
+                        it);
+  }
+
+private:
+  const nnfw::misc::matrix::Shape _shape;
+  const T *const _base;
+  const size_t _size;
+};
+
+#endif // __INTERNAL_MATRIX_SOURCE_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/Model.cc b/runtime/contrib/pure_arm_compute/src/internal/Model.cc
new file mode 100644
index 000000000..03753fea2
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/Model.cc
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/Model.h"
+
+namespace internal
+{
+namespace tflite
+{
+namespace operand
+{
+
+Shape::Shape(uint32_t rank) : nnfw::misc::tensor::Shape(rank)
+{
+  // DO NOTHING
+}
+
+int32_t Shape::asVector(void) const
+{
+  assert(rank() == 1);
+
+  return dim(0);
+}
+
+nnfw::misc::matrix::Shape Shape::asMatrix(void) const
+{
+  assert(rank() == 2);
+
+  const auto height = dim(0);
+  const auto width = dim(1);
+
+  return nnfw::misc::matrix::Shape(height, width);
+}
+
+nnfw::misc::feature::Shape Shape::asFeature(void) const
+{
+  assert(rank() == 4);
+
+  // Feature Map in NNAPI
+  //  - Dimension(0) -> Batch
+  //  - Dimension(1) -> Height
+  //  - Dimension(2) -> Width
+  //  - Dimension(3) -> Depth
+
+  const auto batch = dim(0);
+  const auto depth = dim(3);
+  const auto height = dim(1);
+  const auto width = dim(2);
+
+  return nnfw::misc::feature::Shape(batch, depth, height, width);
+}
+
+nnfw::misc::tensor::Shape Shape::asTensor(void) const
+{
+  return nnfw::misc::tensor::Shape(*this); // this shape represents shape of NNAPI
+}
+
+nnfw::misc::kernel::Shape Shape::asKernel(void) const
+{
+  assert(rank() == 4);
+
+  // Convolution Kernel in NNAPI
+  //  - Dimension(0) -> Count
+  //  - Dimension(1) -> Height
+  //  - Dimension(2) -> Width
+  //  - Dimension(3) -> Depth
+  const auto count = dim(0);
+  const auto depth = dim(3);
+  const auto height = dim(1);
+  const auto width = dim(2);
+
+  return nnfw::misc::kernel::Shape(count, depth, height, width);
+}
+
+// Extended dimension is filled with 1.
+void Shape::extendRank(size_t to_rank)
+{
+  for (int i = rank() + 1; i <= to_rank; ++i)
+  {
+    prepend(1);
+  }
+}
+
+} // namespace operand
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace operand
+{
+
+Index Set::append(const Shape &shape, int32_t type, float scale, int32_t zeroPoint)
+{
+  int32_t index = _objects.size();
+
+  _objects.emplace_back(new Object{shape, type, scale, zeroPoint});
+
+  return Index{index};
+}
+
+const Object &Set::at(const Index &index) const { return *(_objects.at(index.asInt())); }
+
+Object &Set::at(const Index &index) { return *(_objects.at(index.asInt())); }
+
+bool Set::exist(const Index &index) const
+{
+  return index.asInt() >= 0 && index.asInt() < _objects.size();
+}
+
+} // namespace operand
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/Model.h b/runtime/contrib/pure_arm_compute/src/internal/Model.h
new file mode 100644
index 000000000..bdcf32f6f
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/Model.h
@@ -0,0 +1,538 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Model.h
+ * @brief This file contains classes for handle internal Model object
+ * @ingroup COM_AI_RUNTIME
+ */
+
+#ifndef __INTERNAL_MODEL_H__
+#define __INTERNAL_MODEL_H__
+
+namespace internal
+{
+namespace tflite
+{
+namespace operand
+{
+
+/**
+ * @brief Class to express index of operand.
+ */
+class Index
+{
+public:
+  /**
+   * @brief Construct a new Index object for operand with param.
+   * @param [in] value The number of index
+   */
+  explicit Index(int value) : _value{value}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Get index value as int
+   * @return Index value as int
+   */
+  int asInt(void) const { return _value; }
+
+private:
+  int _value;
+};
+
+} // namespace operand
+} // namespace tflite
+} // namespace internal
+
+#include <vector>
+#include <cstdint>
+
+#include "misc/feature/Shape.h"
+#include "misc/matrix/Shape.h"
+#include "misc/kernel/Shape.h"
+#include "misc/tensor/Shape.h"
+
+namespace internal
+{
+namespace tflite
+{
+namespace operand
+{
+
+/**
+ * @brief Class to express shape of operand.
+ */
+struct Shape : public nnfw::misc::tensor::Shape
+{
+public:
+  /**
+   * @brief Construct a new Shape object for operand with param.
+   * @param [in] rank The rank value of shape
+   */
+  Shape(uint32_t rank);
+
+public:
+  /**
+   * @brief Get dimension value of tensor as vector
+   * @return Dimension value(int32_t) of tensor as vector
+   */
+  int32_t asVector(void) const;
+  /**
+   * @brief Get dimension values of tensor as feature::Shape
+   * @return Dimension values of tensor as feature::Shape
+   */
+  nnfw::misc::feature::Shape asFeature(void) const;
+  /**
+   * @brief Get dimension values of tensor as matrix::Shape
+   * @return Dimension values of tensor as matrix::Shape
+   */
+  nnfw::misc::matrix::Shape asMatrix(void) const;
+  /**
+   * @brief Get dimension values of tensor as kernel::Shape
+   * @return Dimension values of tensor as kernel::Shape
+   */
+  nnfw::misc::kernel::Shape asKernel(void) const;
+  /**
+   * @brief Get dimension values of tensor::Shape
+   * @return Dimension values of tensor::Shape
+   */
+  nnfw::misc::tensor::Shape asTensor(void) const;
+
+public:
+  /**
+   * @brief Extend rank of Shape object for operand with param.
+   * @param [in] to_rank The rank value to be extended to
+   * @return N/A
+   */
+  void extendRank(size_t);
+};
+
+} // namespace operand
+} // namespace tflite
+} // namespace internal
+
+#include <algorithm>
+
+namespace internal
+{
+namespace tflite
+{
+namespace operand
+{
+
+/**
+ * @brief Class to have data of operand.
+ */
+struct Data
+{
+  /**
+   * @brief Destruct this object
+   */
+  virtual ~Data() = default;
+
+  /**
+   * @brief Get size of data
+   * @return size of data
+   */
+  virtual size_t size(void) const = 0;
+  /**
+   * @brief Get the base address of data
+   * @return the base address of data
+   */
+  virtual const uint8_t *base(void) const = 0;
+};
+
+/**
+ * @brief Class to have cached data of operand.
+ */
+class CachedData final : public Data
+{
+public:
+  /**
+   * @brief Construct a new CachedData object for operand with param.
+   * @param [in] base the base address of data
+   * @param [in] size the size of data
+   */
+  CachedData(const uint8_t *base, size_t size) : _base{new uint8_t[size]}, _size{size}
+  {
+    std::copy(base, base + size, _base);
+  }
+
+public:
+  /**
+   * @brief Destruct this object
+   */
+  ~CachedData() { delete[] _base; }
+
+public:
+  /**
+   * @brief Get size of data
+   * @return size of data
+   */
+  size_t size(void) const override { return _size; }
+  /**
+   * @brief Get the base address of data
+   * @return the base address of data
+   */
+  const uint8_t *base(void) const override { return _base; }
+
+private:
+  uint8_t *_base;
+  size_t _size;
+};
+
+/**
+ * @brief Class to have external data of operand.
+ */
+class ExternalData final : public Data
+{
+public:
+  /**
+   * @brief Construct a new ExternalData object for operand with param.
+   * @param [in] base the base address of data
+   * @param [in] size the size of data
+   */
+  ExternalData(const uint8_t *base, size_t size) : _base{base}, _size{size}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Get size of data
+   * @return size of data
+   */
+  size_t size(void) const override { return _size; }
+  /**
+   * @brief Get the base address of data
+   * @return the base address of data
+   */
+  const uint8_t *base(void) const override { return _base; }
+
+private:
+  const uint8_t *_base;
+  const size_t _size;
+};
+
+} // namespace operand
+} // namespace tflite
+} // namespace internal
+
+#include <memory>
+#include <cassert>
+#include <functional>
+#include "internal/Swizzle.h"
+
+namespace internal
+{
+namespace tflite
+{
+namespace operand
+{
+
+/**
+ * @brief Class to express operand as object.
+ */
+class Object
+{
+public:
+  /**
+   * @brief Construct a new Object object for operand with param.
+   * @param [in] shape shape of operand
+   * @param [in] type type of operand
+   * @param [in] scale scale of operand
+   * @param [in] zeroPoint zeroPoint of operand
+   */
+  explicit Object(const Shape &shape, const int32_t type, const float scale,
+                  const int32_t zeroPoint)
+      : _shape{shape}, _type{type}, _scale{scale}, _zeroPoint{zeroPoint}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Get shape of operand
+   * @return Reference of shape of operand
+   */
+  const Shape &shape(void) const { return _shape; }
+  /**
+   * @brief Get type of operand
+   * @return type of operand
+   */
+  const int32_t type(void) const { return _type; }
+  /**
+   * @brief Get scale of operand
+   * @return scale of operand
+   */
+  const float scale(void) const { return _scale; }
+  /**
+   * @brief Get zeroPoint of operand
+   * @return zeroPoint of operand
+   */
+  const int32_t zeroPoint(void) const { return _zeroPoint; }
+
+private:
+  void data(std::unique_ptr<Data> &&data) { _data = std::move(data); }
+
+public:
+  /**
+   * @brief Get data of operand
+   * @return Reference of data of operand
+   */
+  const Data &data(void) const { return *_data; }
+  /**
+   * @brief Get true if Object has data, otherwise @c false
+   * @return @c true if Object has data, otherwise @c false
+   */
+  bool hasData(void) const { return _data != nullptr; }
+
+public:
+  /**
+   * @brief Set data of operand with param
+   * @param [in] args arguments of data to be set
+   * @return N/A
+   */
+  template <typename T, typename... Args> void data(Args &&... args)
+  {
+    data(std::unique_ptr<T>(new T{std::forward<Args>(args)...}));
+  }
+
+public:
+  /**
+   * @brief Get value of data as scalar
+   * @return value of data as scalar
+   */
+  template <typename T> T asScalar(void) const
+  {
+    assert((_shape.rank() == 0) || ((_shape.rank() == 1) && (_shape.dim(0) == 1)));
+    assert(_data != nullptr);
+    assert((_data->base() != nullptr) && (_data->size() == sizeof(T)));
+
+    return *(reinterpret_cast<const T *>(_data->base()));
+  }
+
+public:
+  /**
+   * @brief Get value of data as ReorderBits
+   * @param [in] numOfBits The number of bits to be reordered to
+   * @return value of data as ReorderBits
+   */
+  template <typename T> T asReorderBits(size_t numOfBits) const
+  {
+    assert((_shape.rank() == 0) || ((_shape.rank() == 1) && (_shape.dim(0) == 1)));
+    assert(_data != nullptr);
+    assert((_data->base() != nullptr) && (_data->size() == sizeof(T)));
+
+    return ReorderBits<T>(asScalar<T>(), numOfBits);
+  }
+
+private:
+  const Shape _shape;
+  const int32_t _type;
+  const float _scale;
+  const int32_t _zeroPoint;
+  std::unique_ptr<Data> _data;
+};
+
+} // namespace operand
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace operand
+{
+
+/**
+ * @brief Class to have object instances in a kind of set
+ */
+class Set
+{
+public:
+  /**
+   * @brief Iterate objects with fn
+   * @param [in] fn function to be iterated
+   * @return N/A
+   */
+  void iterate(const std::function<void(const Index &)> &fn)
+  {
+    for (uint32_t n = 0; n < _objects.size(); ++n)
+    {
+      const Index operand_index{static_cast<int>(n)};
+      fn(operand_index);
+    }
+  }
+
+public:
+  /**
+   * @brief Append Object for operand with param
+   * @param [in] shape shape of operand
+   * @param [in] type type of operand
+   * @param [in] scale scale of operand
+   * @param [in] zeroPoint zeroPoint of operand
+   * @return Value of Index which has been appended to
+   */
+  Index append(const Shape &, int32_t type, float scale, int32_t zeroPoint);
+
+public:
+  /**
+   * @brief Get Object at Index
+   * @param [in] index Index to be at
+   * @return Const refernece of Object
+   */
+  const Object &at(const Index &) const;
+  /**
+   * @brief Get Object at Index
+   * @param [in] index Index to be at
+   * @return Refernece of Object
+   */
+  Object &at(const Index &);
+  /**
+   * @brief Get size of operands in Set
+   * @return Value of size
+   */
+  size_t size(void) const { return _objects.size(); }
+  bool exist(const Index &) const;
+
+private:
+  std::vector<std::unique_ptr<Object>> _objects;
+};
+
+} // namespace operand
+} // namespace tflite
+} // namespace internal
+
+#include "internal/op/NodeVisitor.h"
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+
+/**
+ * @brief Class to have sequence operators.
+ */
+class Sequence
+{
+public:
+  /**
+   * @brief Construct a new Sequence object for operator as default
+   */
+  Sequence() = default;
+
+public:
+  /**
+   * @brief Get size of operators in Sequence
+   * @return Value of size
+   */
+  uint32_t size(void) const { return _ops.size(); }
+
+public:
+  /**
+   * @brief Get op::Node at Index
+   * @param [in] nth index to be at
+   * @return Refernece of op::Node
+   */
+  op::Node &at(uint32_t nth) { return *(_ops.at(nth)); }
+  /**
+   * @brief Get op::Node at Index
+   * @param [in] nth index to be at
+   * @return Const refernece of op::Node
+   */
+  const op::Node &at(uint32_t nth) const { return *(_ops.at(nth)); }
+
+private:
+  Sequence &emplace_back(std::unique_ptr<op::Node> &&node)
+  {
+    _ops.emplace_back(std::move(node));
+    return (*this);
+  }
+
+public:
+  /**
+   * @brief Add op::Node with param
+   * @param [in] args arguments of op::Node to be set
+   * @return Reference of Sequence
+   */
+  template <typename T, typename... Args> Sequence &emplace_back(Args &&... args)
+  {
+    return emplace_back(std::unique_ptr<T>(new T{std::forward<Args>(args)...}));
+  }
+
+private:
+  std::vector<std::unique_ptr<op::Node>> _ops;
+};
+
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+
+/**
+ * @brief Class to have operand::Set as operands and op::Sequence as operators
+ */
+class Model
+{
+public:
+  /**
+   * @brief Get operand::Set
+   * @return Reference of operand::Set
+   */
+  operand::Set &operands(void) { return _operands; }
+  /**
+   * @brief Get operand::Set
+   * @return Const reference of operand::Set
+   */
+  const operand::Set &operands(void) const { return _operands; }
+
+public:
+  /**
+   * @brief Get op::Sequence
+   * @return Reference of op::Sequence
+   */
+  op::Sequence &operations(void) { return _operations; }
+  /**
+   * @brief Get op::Sequence
+   * @return Const reference of op::Sequence
+   */
+  const op::Sequence &operations(void) const { return _operations; }
+
+private:
+  operand::Set _operands;
+  op::Sequence _operations;
+
+public:
+  // TODO Hide these fields
+  std::vector<operand::Index> inputs;  /**< indexes of operand as input */
+  std::vector<operand::Index> outputs; /**< indexes of operand as output */
+};
+
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_MODEL_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/Sink.h b/runtime/contrib/pure_arm_compute/src/internal/Sink.h
new file mode 100644
index 000000000..6f44561ea
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/Sink.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    Sink.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines Sink struct
+ */
+#ifndef __INTERNAL_SINK_H__
+#define __INTERNAL_SINK_H__
+
+#include <arm_compute/core/ITensor.h>
+
+/**
+ * @brief Struct to get tensor data from arm compute tensor (abstract)
+ */
+struct Sink
+{
+  /**
+   * @brief Destroy the Sink object
+   */
+  virtual ~Sink() = default;
+
+  /**
+   * @brief     Get tensor data from arm compute tensor
+   * @param[in] tensor  Tensor object of arm compute to get data
+   * @return    N/A
+   */
+  virtual void pull(::arm_compute::ITensor &tensor) const = 0;
+};
+
+#endif // __INTERNAL_SINK_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/Sinks.h b/runtime/contrib/pure_arm_compute/src/internal/Sinks.h
new file mode 100644
index 000000000..7317c67c1
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/Sinks.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file        Sinks.h
+ * @brief       This file contains TensorSink class
+ * @ingroup     COM_AI_RUNTIME
+ */
+
+#ifndef __INTERNAL_SINKS_H__
+#define __INTERNAL_SINKS_H__
+
+#include "internal/Sink.h"
+
+// TODO Extract TensorSink into TensorSink.h
+//
+// TensorSink
+//
+#include "internal/Swizzle.h"
+
+#include "internal/nnapi/tensor/View.h"
+#include "internal/arm_compute/tensor/View.h"
+
+#include "misc/tensor/IndexIterator.h"
+
+/**
+ * @brief Class to store NN model output data for general-shaped tensors.
+ * This is for pulling data to internal tensor from other tensor.
+ * @tparam T Type of the data elements
+ */
+template <typename T> class TensorSink final : public Sink
+{
+public:
+  /**
+   * @brief Construct a TensorSink object
+   *
+   * @param[in] shape general-shaped tensor dimensions
+   * @param[in] base Base pointer of the actual data
+   * @param[in] size Size of the data
+   */
+  TensorSink(const nnfw::misc::tensor::Shape &shape, T *base, const size_t size)
+      : _shape{shape}, _base{base}, _size{size}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Pull the data into the internal structure
+   * @param[in] tensor The tensor which contains source data
+   * @return N/A
+   */
+  void pull(::arm_compute::ITensor &tensor) const override
+  {
+    const ::internal::arm_compute::tensor::View<T> from{&tensor};
+    ::internal::nnapi::tensor::View<T> into{_shape, _base, _size};
+
+    using ::nnfw::misc::tensor::iterate;
+    using ::nnfw::misc::tensor::Index;
+
+    const uint32_t rank = _shape.rank();
+
+    ::nnfw::misc::tensor::iterate(_shape) << [&](const Index &raw) {
+      Index permuted(raw.rank());
+
+      for (uint32_t axis = 0; axis < rank; ++axis)
+      {
+        permuted.at(ToARMComputeAxis(rank, axis).value()) = raw.at(axis);
+      }
+
+      const auto value = from.at(permuted);
+      into.at(raw) = value;
+    };
+  }
+
+private:
+  const nnfw::misc::tensor::Shape _shape;
+
+private:
+  T *const _base;
+  const size_t _size;
+};
+
+#endif // __INTERNAL_SINKS_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/Source.h b/runtime/contrib/pure_arm_compute/src/internal/Source.h
new file mode 100644
index 000000000..fa8f1e811
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/Source.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Source.h
+ * @brief This file contains Source struct for pushing ITensor
+ * @ingroup COM_AI_RUNTIME
+ */
+
+#ifndef __INTERNAL_SOURCE_H__
+#define __INTERNAL_SOURCE_H__
+
+#include <arm_compute/core/ITensor.h>
+
+/**
+ * @brief Struct to push inner source to ITensor.
+ */
+struct Source
+{
+  /**
+   * @brief Destructor as default
+   */
+  virtual ~Source() = default;
+
+  /**
+   * @brief Push inner source to ITensor
+   * @param [in] tensor ITensor to be pushed into
+   * @return N/A
+   */
+  virtual void push(::arm_compute::ITensor &tensor) const = 0;
+};
+
+#endif // __INTERNAL_SOURCE_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/Swizzle.h b/runtime/contrib/pure_arm_compute/src/internal/Swizzle.h
new file mode 100644
index 000000000..f127b8a3b
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/Swizzle.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    Swizzle.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines ARMComputeAxis class and utility functions to support mapping
+ *          between arm compute axis and NNAPI axis
+ */
+#ifndef __SWIZZLE_H__
+#define __SWIZZLE_H__
+
+/**
+ * @brief Class to represent arm compute axis
+ */
+class ARMComputeAxis
+{
+public:
+  /**
+   * @brief Construct a new ARMComputeAxis object
+   */
+  ARMComputeAxis() = default;
+
+public:
+  /**
+   * @brief Construct a new ARMComputeAxis object
+   * @param[in] value Raw axis number
+   */
+  explicit ARMComputeAxis(uint32_t value) : _value{value}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief   Get raw axis number
+   * @return  Raw axis number
+   */
+  uint32_t value(void) const { return _value; }
+
+private:
+  uint32_t _value;
+};
+
+/**
+ * @brief     Convert T/F Lite / NNAPI axis (based on ...NHWC) to arm compute axis (WHCN...)
+ * @param[in] rank  Rank of shape
+ * @param[in] axis  Axis to map
+ * @return    ARMComputeAxis including arm compute axis info
+ */
+inline ARMComputeAxis ToARMComputeAxis(uint32_t rank, uint32_t axis)
+{
+  assert(rank > axis);
+  const ARMComputeAxis reversed{(rank - axis) - 1};
+
+  if (rank < 4)
+  {
+    return reversed;
+  }
+
+  // DEPTH
+  if (0 == reversed.value())
+  {
+    return ARMComputeAxis{2};
+  }
+  // WIDTH
+  if (1 == reversed.value())
+  {
+    return ARMComputeAxis{0};
+  }
+  // HEIGHT
+  if (2 == reversed.value())
+  {
+    return ARMComputeAxis{1};
+  }
+
+  // ELSE
+  return reversed;
+}
+
+#include <cassert>
+
+/**
+ * @brief     Covert bitmask info from NNAPI axis to arm compute axis
+ * @param[in] in        Bitmask data
+ * @param[in] numOfBits Used bits (rank)
+ * @return    Coverted bitmask
+ */
+template <typename T> inline T ReorderBits(T in, size_t numOfBits)
+{
+  assert(numOfBits > 0);
+  T out = 0;
+  for (int32_t i = numOfBits - 1; i >= 0; --i)
+  {
+    const uint32_t toShift = numOfBits - ToARMComputeAxis(numOfBits, i).value() - 1;
+    out += ((in & 1) << toShift);
+    in >>= 1;
+  }
+  return out;
+}
+
+#endif // __SWIZZLE_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/Tensor3DSink.h b/runtime/contrib/pure_arm_compute/src/internal/Tensor3DSink.h
new file mode 100644
index 000000000..1e14e2d6c
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/Tensor3DSink.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    Tensor3DSink.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines Tensor3DSink class
+ */
+#ifndef __TENSOR3D_SINK_H__
+#define __TENSOR3D_SINK_H__
+
+#include "internal/Sink.h"
+
+//
+// This is mempcy() version of generic TensorSink for 3D tensor
+//
+#include <arm_compute/core/ITensor.h>
+#include <arm_compute/core/Window.h>
+#include <arm_compute/core/Helpers.h>
+
+/**
+ * @brief Class to get tensor data from arm compute tensor
+ */
+template <typename T> class Tensor3DSink final : public Sink
+{
+public:
+  /**
+   * @brief     Construct a new Tensor3DSink object
+   * @param[in] shape Shape of tensor
+   * @param[in] base  Pointer to get data
+   * @param[in] size  Size of tensor
+   */
+  Tensor3DSink(const nnfw::misc::tensor::Shape &shape, T *base, const size_t size)
+      : _shape{shape}, _base{base}, _size{size}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief     Get tensor data from arm compute tensor to base
+   * @param[in] tensor  Tensor object of arm compute to get data
+   * @return    N/A
+   */
+  void pull(::arm_compute::ITensor &tensor) const override
+  {
+    using ::arm_compute::Window;
+    using ::arm_compute::Iterator;
+    using ::arm_compute::Coordinates;
+    using ::arm_compute::execute_window_loop;
+
+    Window window;
+
+    window.use_tensor_dimensions(tensor.info()->tensor_shape(), ::arm_compute::Window::DimY);
+    int32_t height_width = _shape.dim(1) * _shape.dim(2);
+    int32_t width = _shape.dim(2);
+
+    Iterator it(&tensor, window);
+    execute_window_loop(window,
+                        [&](const ::arm_compute::Coordinates &id) {
+                          const auto z = id.z();
+                          const auto y = id.y();
+                          memcpy(_base + z * height_width + y * width, it.ptr(), width * sizeof(T));
+                        },
+                        it);
+  }
+
+private:
+  const nnfw::misc::tensor::Shape _shape;
+
+private:
+  T *const _base;
+  const size_t _size;
+};
+
+#endif // __TENSOR3D_SINK_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/Tensor3DSource.h b/runtime/contrib/pure_arm_compute/src/internal/Tensor3DSource.h
new file mode 100644
index 000000000..3d8d1b958
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/Tensor3DSource.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    Tensor3DSource.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines Tensor3DSource class
+ */
+#ifndef __TENSOR3D_SOURCE_H__
+#define __TENSOR3D_SOURCE_H__
+
+#include "internal/Source.h"
+
+//
+// This is memcpy() version of generic TensorSource for 3D tensor
+//
+#include <arm_compute/core/ITensor.h>
+#include <arm_compute/core/Window.h>
+#include <arm_compute/core/Helpers.h>
+
+/**
+ * @brief Class to push tensor data to arm compute tensor
+ */
+template <typename T> class Tensor3DSource final : public Source
+{
+public:
+  /**
+   * @brief     Construct a new Tensor3DSource object
+   * @param[in] shape Shape of tensor
+   * @param[in] base  Pointer of tensor data to push
+   * @param[in] size  Size of tensor
+   */
+  Tensor3DSource(const nnfw::misc::tensor::Shape &shape, const T *base, const size_t size)
+      : _shape{shape}, _base{base}, _size{size}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief       Push tensor data to arm compute tensor
+   * @param[out]  tensor  Tensor object of arm compute to push tensor data
+   * @return      N/A
+   */
+  void push(::arm_compute::ITensor &tensor) const override
+  {
+    using ::arm_compute::Window;
+    using ::arm_compute::Iterator;
+    using ::arm_compute::Coordinates;
+    using ::arm_compute::execute_window_loop;
+
+    Window window;
+
+    window.use_tensor_dimensions(tensor.info()->tensor_shape(), ::arm_compute::Window::DimY);
+    int32_t height_width = _shape.dim(1) * _shape.dim(2);
+    int32_t width = _shape.dim(2);
+
+    Iterator it(&tensor, window);
+    execute_window_loop(window,
+                        [&](const ::arm_compute::Coordinates &id) {
+                          const auto z = id.z();
+                          const auto y = id.y();
+                          memcpy(it.ptr(), _base + z * height_width + y * width, width * sizeof(T));
+                        },
+                        it);
+  }
+
+private:
+  const nnfw::misc::tensor::Shape _shape;
+
+private:
+  const T *const _base;
+  const size_t _size;
+};
+
+#endif // __TENSOR3D_SOURCE_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/TensorSource.h b/runtime/contrib/pure_arm_compute/src/internal/TensorSource.h
new file mode 100644
index 000000000..114d3588e
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/TensorSource.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file TensorSource.h
+ * @brief This file contains TensorSource class which is inherited from Source class
+ * @ingroup COM_AI_RUNTIME
+ */
+
+#ifndef __INTERNAL_TENSOR_SOURCE_H__
+#define __INTERNAL_TENSOR_SOURCE_H__
+
+#include <misc/tensor/Shape.h>
+#include <misc/tensor/IndexIterator.h>
+
+#include "internal/Source.h"
+#include "internal/Swizzle.h"
+#include "internal/nnapi/tensor/Reader.h"
+#include "internal/arm_compute/tensor/View.h"
+
+// NOTE TensorSource is much slower than specialized Source(s)
+/**
+ * @brief Class to define constructor and push function
+ */
+template <typename T> class TensorSource final : public Source
+{
+public:
+  /**
+   * @brief Construct a new TensorSource object with params
+   * @param [in] shape Shape of tensor
+   * @param [in] base Base address
+   * @param [in] size Size of tensor
+   */
+  TensorSource(const nnfw::misc::tensor::Shape &shape, const T *base, const size_t size)
+      : _shape{shape}, _base{base}, _size{size}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Function for pushing tensor
+   * @param [in] tensor Tensor to be pushed
+   * @return N/A
+   */
+  void push(::arm_compute::ITensor &tensor) const override
+  {
+    const ::internal::nnapi::tensor::Reader<T> from{_shape, _base, _size};
+    ::internal::arm_compute::tensor::View<T> into{&tensor};
+
+    ::nnfw::misc::tensor::iterate(_shape) << [&](const nnfw::misc::tensor::Index &index_nnapi) {
+      const auto rank = index_nnapi.rank();
+      nnfw::misc::tensor::Index index_ACL(rank);
+
+      for (uint32_t axis = 0; axis < rank; ++axis)
+      {
+        index_ACL.at(ToARMComputeAxis(rank, axis).value()) = index_nnapi.at(axis);
+      }
+
+      into.at(index_ACL) = from.at(index_nnapi);
+    };
+  }
+
+private:
+  const nnfw::misc::tensor::Shape _shape;
+  const T *const _base;
+  const size_t _size;
+};
+
+#endif // __INTERNAL_TENSOR_SOURCE_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/VectorSink.h b/runtime/contrib/pure_arm_compute/src/internal/VectorSink.h
new file mode 100644
index 000000000..a630ef1c1
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/VectorSink.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file        VectorSink.h
+ * @brief       This file contains VectorSink class
+ * @ingroup     COM_AI_RUNTIME
+ */
+
+#ifndef __INTERNAL_VECTOR_SINK_H__
+#define __INTERNAL_VECTOR_SINK_H__
+
+#include "internal/Sink.h"
+
+#include <arm_compute/core/ITensor.h>
+
+#include <cassert>
+
+/**
+ * @brief Class to store vector(2D) output data.
+ * This is for pulling out the data to another tensor.
+ * @tparam T Type of the data elements
+ */
+template <typename T> class VectorSink final : public Sink
+{
+public:
+  /**
+   * @brief Construct a VectorSink object
+   * @param[in] vlen Length of the vector
+   * @param[in] base Base pointer of the actual data
+   * @param[in] size Size of the data
+   */
+  VectorSink(const int32_t vlen, T *base, const size_t size) : _vlen{vlen}, _base{base}
+  {
+    assert(size >= _vlen * sizeof(T));
+  }
+
+public:
+  /**
+   * @brief Pull the data into the internal structure
+   * @param[in] tensor The tensor which contains source data
+   * @return N/A
+   */
+  void pull(::arm_compute::ITensor &tensor) const override
+  {
+    for (int32_t n = 0; n < _vlen; ++n)
+    {
+      auto from = reinterpret_cast<T *>(tensor.ptr_to_element(::arm_compute::Coordinates{n}));
+      auto into = _base + n;
+
+      *into = *from;
+    }
+  }
+
+private:
+  const int32_t _vlen;
+  T *const _base;
+};
+
+#endif // __INTERNAL_VECTOR_SINK_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/VectorSource.h b/runtime/contrib/pure_arm_compute/src/internal/VectorSource.h
new file mode 100644
index 000000000..48d3d3209
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/VectorSource.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file        VectorSource.h
+ * @brief       This file contains VectorSource class
+ * @ingroup     COM_AI_RUNTIME
+ */
+
+#ifndef __INTERNAL_VECTOR_SOURCE_H__
+#define __INTERNAL_VECTOR_SOURCE_H__
+
+#include "internal/Source.h"
+
+/**
+ * @brief Class to store vector(2D) input data.
+ * This is for push out the data to another tensor.
+ * @tparam T Type of the data elements
+ */
+template <typename T> class VectorSource final : public Source
+{
+public:
+  /**
+   * @brief Construct a VectorSource object
+   * @param[in] vlen Length of the vector
+   * @param[in] base Base pointer of the actual data
+   * @param[in] size Size of the data
+   */
+  VectorSource(const int32_t vlen, const T *base, const size_t size) : _vlen{vlen}, _base{base}
+  {
+    assert(size >= _vlen * sizeof(T));
+  }
+
+public:
+  /**
+   * @brief Push the data out to the another tensor
+   * @param[out] The tensor that output data will be stored
+   * @return N/A
+   */
+  void push(::arm_compute::ITensor &tensor) const override
+  {
+    for (int32_t n = 0; n < _vlen; ++n)
+    {
+      auto from = _base + n;
+      auto into = reinterpret_cast<T *>(tensor.ptr_to_element(::arm_compute::Coordinates{n}));
+
+      *into = *from;
+    }
+  }
+
+private:
+  const int32_t _vlen;
+  const T *const _base;
+};
+
+#endif // __INTERNAL_VECTOR_SOURCE_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/arm_compute.cc b/runtime/contrib/pure_arm_compute/src/internal/arm_compute.cc
new file mode 100644
index 000000000..a7be2068d
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/arm_compute.cc
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/arm_compute.h"
+
+#include <arm_compute/runtime/CL/CLScheduler.h>
+
+#include <cassert>
+
+namespace internal
+{
+namespace arm_compute
+{
+namespace operand
+{
+
+void Object::access(const std::function<void(::arm_compute::ITensor &tensor)> &fn) const
+{
+  if (::internal::arm_compute::isGpuMode())
+  {
+    auto &queue = ::arm_compute::CLScheduler::get().queue();
+
+    auto cl_tensor = _tensor.get();
+    CAST_CL(cl_tensor)->map(queue);
+    fn(*_tensor);
+    CAST_CL(cl_tensor)->unmap(queue);
+  }
+  else
+  {
+    fn(*_tensor);
+  }
+}
+
+} // namespace operand
+} // namepsace arm_compute
+} // namespace internal
+
+namespace internal
+{
+namespace arm_compute
+{
+namespace operand
+{
+
+Context &Context::set(const ::internal::tflite::operand::Index &id,
+                      const std::shared_ptr<::arm_compute::ITensor> &tensor)
+{
+  assert(_objects.find(id.asInt()) == _objects.end());
+
+  _objects[id.asInt()] = Object{tensor};
+  return (*this);
+}
+
+} // namespace operand
+} // namepsace arm_compute
+} // namespace internal
+
+namespace internal
+{
+namespace arm_compute
+{
+
+bool isGpuMode()
+{
+  char *neon = std::getenv("NEON");
+  if (neon == nullptr)
+    return true;
+  else if (neon[0] == '1')
+    return false;
+  return true;
+}
+
+} // namepsace arm_compute
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/arm_compute.h b/runtime/contrib/pure_arm_compute/src/internal/arm_compute.h
new file mode 100644
index 000000000..fb6acaf81
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/arm_compute.h
@@ -0,0 +1,337 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file        arm_compute.h
+ * @brief       This file contains arm_compute library related classes
+ * @ingroup     COM_AI_RUNTIME
+ */
+
+#ifndef __INTERNAL_ARM_COMPUTE_H__
+#define __INTERNAL_ARM_COMPUTE_H__
+
+#include <arm_compute/core/ITensor.h>
+#include <arm_compute/runtime/CL/CLTensor.h>
+#include <arm_compute/runtime/Tensor.h>
+
+namespace internal
+{
+namespace arm_compute
+{
+namespace operand
+{
+
+/**
+ * @brief Class to access the tensor object
+ */
+class Object
+{
+public:
+  Object() = default;
+
+public:
+  Object(const std::shared_ptr<::arm_compute::ITensor> &tensor) : _tensor{tensor}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Get the tensor pointer
+   * @return The tensor pointer
+   */
+  ::arm_compute::ITensor *ptr(void) const { return _tensor.get(); }
+
+private:
+  std::shared_ptr<::arm_compute::ITensor> _tensor;
+
+public:
+  /**
+   * @brief Access the tensor object and run the given function
+   : @param[in] fn The actual behavior when accessing the tensor object
+   * @return N/A
+   */
+  void access(const std::function<void(::arm_compute::ITensor &tensor)> &fn) const;
+};
+
+} // namespace operand
+} // namepsace arm_compute
+} // namespace internal
+
+#include "internal/Model.h"
+
+#include <map>
+
+namespace internal
+{
+namespace arm_compute
+{
+namespace operand
+{
+
+/**
+ * @brief Class to manage Object instances
+ */
+class Context
+{
+public:
+  /**
+   * @brief Set index and tensor pair
+   * @param[in] ind The operand index
+   * @param[in] tensor The tensor object
+   * @return This object reference
+   */
+  Context &set(const ::internal::tflite::operand::Index &ind,
+               const std::shared_ptr<::arm_compute::ITensor> &tensor);
+
+public:
+  /**
+   * @brief Check if the tensor for given index is exist
+   * @param[in] ind The operand Index
+   * @return @c true if the entry for ind is exist, otherwise @c false
+   */
+  bool exist(const ::internal::tflite::operand::Index &ind) const
+  {
+    return _objects.find(ind.asInt()) != _objects.end();
+  }
+
+public:
+  /**
+   * @brief Lookup the tensor with the given index
+   * @param[in] ind The index as the key
+   * @return The object const reference
+   */
+  const Object &at(const ::internal::tflite::operand::Index &ind) const
+  {
+    return _objects.at(ind.asInt());
+  }
+
+  /**
+   * @brief Lookup the tensor with the given index
+   * @param[in] ind The index as the key
+   * @return The object reference
+   */
+  Object &at(const ::internal::tflite::operand::Index &ind) { return _objects.at(ind.asInt()); }
+
+private:
+  std::map<int, Object> _objects;
+};
+
+} // namespace operand
+} // namepsace arm_compute
+} // namespace internal
+
+#include <arm_compute/runtime/IFunction.h>
+
+namespace internal
+{
+namespace arm_compute
+{
+namespace op
+{
+
+/**
+ * @brief Class to wrap IFunction
+ */
+class Step
+{
+public:
+  /**
+   * @brief Construct a Step object
+   * @param[in] func The compiled code to be executed
+   */
+  Step(std::unique_ptr<::arm_compute::IFunction> &&func) : _func{std::move(func)}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Run _func
+   * @return N/A
+   */
+  void run(void) const { _func->run(); }
+
+public:
+  /**
+   * @brief Get member @c _name
+   * @return The name as const reference
+   */
+  const std::string &name(void) const { return _name; }
+  /**
+   * @brief Get member @c _name
+   * @return The name as reference
+   */
+  std::string &name(void) { return _name; }
+
+private:
+  std::string _name;
+  std::unique_ptr<::arm_compute::IFunction> _func;
+#ifdef TFLITE_PROFILING_ENABLED
+public:
+  /**
+   * @brief Get member @c _op_index
+   * @return The operation index as value
+   */
+  int op_idx() const { return _op_idx; }
+  /**
+   * @brief Get member @c _op_index
+   * @return The operation index as reference
+   */
+  int &op_idx() { return _op_idx; }
+private:
+  int _op_idx;
+#endif
+};
+
+} // namespace op
+} // namepsace arm_compute
+} // namespace internal
+
+namespace internal
+{
+namespace arm_compute
+{
+namespace op
+{
+
+/**
+ * @brief Class managing compiled operation code Sequence
+ */
+class Sequence
+{
+public:
+  /**
+   * @brief Get size of sequence
+   * @return Number of sequence steps
+   */
+  uint32_t size(void) const { return _functions.size(); }
+
+public:
+  /**
+   * @brief Append a Function to the sequence
+   * @param[in] func Function to be appended
+   * @return This object reference
+   */
+  Sequence &append(std::unique_ptr<::arm_compute::IFunction> &&func)
+  {
+    _functions.emplace_back(std::move(func));
+    return (*this);
+  }
+
+public:
+  /**
+   * @brief Get the step entry on the index @c n
+   * @param[in] n The index
+   * @return The step object as reference
+   */
+  Step &at(uint32_t n) { return _functions.at(n); }
+  /**
+   * @brief Get the step entry on the index @c n
+   * @param[in] n The index
+   * @return The step object as const reference
+   */
+  const Step &at(uint32_t n) const { return _functions.at(n); }
+
+private:
+  // TODO Rename _functions as _steps
+  std::vector<Step> _functions;
+};
+
+} // namespace op
+} // namepsace arm_compute
+} // namespace internal
+
+namespace internal
+{
+namespace arm_compute
+{
+
+/**
+ * @brief Class to manage compiled operation sequence
+ */
+class Plan
+{
+public:
+  /**
+   * @brief Construct a Plan object
+   * @param[in] model Model that we want to compile
+   */
+  Plan(const std::shared_ptr<const ::internal::tflite::Model> &model) : _model(model)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Get the model object
+   * @return The model object as const reference
+   */
+  const ::internal::tflite::Model &model(void) const { return *_model; }
+
+public:
+  /**
+   * @brief Get operand context
+   * @return The operand context as reference
+   */
+  operand::Context &operands(void) { return _operands; }
+  /**
+   * @brief Get operand context
+   * @return The operand context as const reference
+   */
+  const operand::Context &operands(void) const { return _operands; }
+
+public:
+  /**
+   * @brief Get operation sequence
+   * @return The operation sequence as reference
+   */
+  op::Sequence &operations(void) { return _ops; }
+  /**
+   * @brief Get operation sequence
+   * @return The operation sequence as const reference
+   */
+  const op::Sequence &operations(void) const { return _ops; }
+
+private:
+  std::shared_ptr<const ::internal::tflite::Model> _model;
+  operand::Context _operands;
+  op::Sequence _ops;
+};
+
+} // namepsace arm_compute
+} // namespace internal
+
+#include <arm_compute/core/ITensor.h>
+
+namespace internal
+{
+namespace arm_compute
+{
+
+/**
+ * @brief Check if this runtime runs on GPU or NEON
+ * @return @c true if GPU mode, otherwise @c false
+ */
+bool isGpuMode();
+
+#define CAST_CL(tensor) static_cast<::arm_compute::CLTensor *>(tensor)
+#define CAST_NE(tensor) static_cast<::arm_compute::Tensor *>(tensor)
+
+} // namepsace arm_compute
+} // namespace internal
+
+#endif // __INTERNAL_ARM_COMPUTE_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/arm_compute/Cast.cc b/runtime/contrib/pure_arm_compute/src/internal/arm_compute/Cast.cc
new file mode 100644
index 000000000..1a5c735ee
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/arm_compute/Cast.cc
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/arm_compute/Cast.h"
+
+#include "internal/Swizzle.h"
+
+::arm_compute::Coordinates getARMComputeAxises(uint32_t rank)
+{
+  ::arm_compute::Coordinates res{};
+
+  res.set_num_dimensions(rank);
+
+  for (uint32_t axis = 0; axis < rank; ++axis)
+  {
+    res.set(axis, ToARMComputeAxis(rank, axis).value());
+  }
+
+  return res;
+}
+
+::arm_compute::Coordinates asARMComputeCoordinates(const ::arm_compute::Coordinates &runtime_coord,
+                                                   const ::arm_compute::Coordinates &axises)
+{
+  ::arm_compute::Coordinates id{};
+  assert(runtime_coord.num_dimensions() == axises.num_dimensions());
+  for (size_t i = 0; i < runtime_coord.num_dimensions(); ++i)
+  {
+    id.set(axises[i], runtime_coord[i]);
+  }
+  return id;
+}
+
+// Restructure runtime_permutationVector to ACL_permutationVector
+::arm_compute::PermutationVector getARMComputePermutationVector(uint32_t rank,
+                                                                const int32_t *runtime_pv)
+{
+  // rank upto 4 is supported
+  assert(rank <= 4);
+  assert(runtime_pv != nullptr);
+
+  int new_pv[4] = {0};
+  ::arm_compute::Coordinates axises = getARMComputeAxises(rank);
+
+  for (uint32_t i = 0; i < rank; ++i)
+  {
+    new_pv[axises[i]] = ToARMComputeAxis(rank, runtime_pv[i]).value();
+  }
+
+  ::arm_compute::PermutationVector ACL_PV =
+      ::arm_compute::PermutationVector{new_pv[0], new_pv[1], new_pv[2], new_pv[3]};
+  ACL_PV.set_num_dimensions(rank);
+
+  return ACL_PV;
+}
+
+::arm_compute::TensorShape asTensorShape(const internal::tflite::operand::Shape &shape,
+                                         bool apply_dim_correction)
+{
+  const uint32_t rank = shape.rank();
+
+  ::arm_compute::TensorShape res{};
+
+  res.set_num_dimensions(rank);
+
+  for (uint32_t axis = 0; axis < rank; ++axis)
+  {
+    // NOTE In some cases, in incorrect dimensions is required.
+    // For example, intput_size is 1 in LSTM. The input-to-input weights([num_units, input_size]) of
+    // LSTM is used as the weight of the FullyConnected.
+    // The FullyConnected's weight must be greater or equal than 2-dimensions.
+    // However, if the dimension correction is applied to input_to_input_weights with input_size
+    // equal to 1, it will be changed to 1-D.
+    // So input_to_input_weights is not used by the weight of FullyConnected.
+    res.set(ToARMComputeAxis(rank, axis).value(), shape.dim(axis), apply_dim_correction);
+  }
+
+  return res;
+}
+
+::arm_compute::DataType asDataType(const int32_t type)
+{
+  switch (type)
+  {
+    case ANEURALNETWORKS_FLOAT32:
+    case ANEURALNETWORKS_TENSOR_FLOAT32:
+      return ::arm_compute::DataType::F32;
+    case ANEURALNETWORKS_INT32:
+    case ANEURALNETWORKS_TENSOR_INT32:
+      return ::arm_compute::DataType::S32;
+    case ANEURALNETWORKS_UINT32:
+      return ::arm_compute::DataType::U32;
+    case ANEURALNETWORKS_TENSOR_QUANT8_ASYMM:
+      return ::arm_compute::DataType::QASYMM8;
+    default:
+      throw std::runtime_error("Not supported, yet");
+      break;
+  }
+}
+
+::arm_compute::ActivationLayerInfo asActivationInfo(FuseCode code)
+{
+  switch (code)
+  {
+    case ANEURALNETWORKS_FUSED_NONE:
+      return ::arm_compute::ActivationLayerInfo{};
+    case ANEURALNETWORKS_FUSED_RELU:
+      return ::arm_compute::ActivationLayerInfo{
+          ::arm_compute::ActivationLayerInfo::ActivationFunction::RELU};
+    case ANEURALNETWORKS_FUSED_RELU1:
+      return ::arm_compute::ActivationLayerInfo{
+          ::arm_compute::ActivationLayerInfo::ActivationFunction::LU_BOUNDED_RELU, 1.0f, -1.0f};
+    case ANEURALNETWORKS_FUSED_RELU6:
+      return ::arm_compute::ActivationLayerInfo{
+          ::arm_compute::ActivationLayerInfo::ActivationFunction::LU_BOUNDED_RELU, 6.0f, 0.0f};
+    default:
+      throw std::runtime_error("Not supported, yet");
+      break;
+  }
+}
+
+::arm_compute::QuantizationInfo asQuantizationInfo(const float scale, const int32_t offset)
+{
+  return ::arm_compute::QuantizationInfo(scale, offset);
+}
+
+::arm_compute::TensorInfo asTensorInfo(const ::arm_compute::TensorShape &shape, const int32_t type,
+                                       const float scale, const int32_t zeroPoint)
+{
+  return ::arm_compute::TensorInfo(shape, 1, asDataType(type),
+                                   asQuantizationInfo(scale, zeroPoint));
+}
+
+::arm_compute::TensorInfo asTensorInfo(const ::arm_compute::TensorShape &shape,
+                                       const ::arm_compute::DataType &type, const float scale,
+                                       const int32_t zeroPoint)
+{
+  return ::arm_compute::TensorInfo(shape, 1, type, asQuantizationInfo(scale, zeroPoint));
+}
diff --git a/runtime/contrib/pure_arm_compute/src/internal/arm_compute/Cast.h b/runtime/contrib/pure_arm_compute/src/internal/arm_compute/Cast.h
new file mode 100644
index 000000000..211a6ac87
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/arm_compute/Cast.h
@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    Cast.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines casting functions from internal object to arm compute object
+ */
+#ifndef __ARM_COMPUTE_CAST_H__
+#define __ARM_COMPUTE_CAST_H__
+
+#include <arm_compute/core/Coordinates.h>
+#include <arm_compute/core/TensorInfo.h>
+#include <arm_compute/core/TensorShape.h>
+#include <arm_compute/core/Types.h>
+
+#include <NeuralNetworks.h>
+
+#include "internal/Model.h"
+
+/**
+ * @brief     Generate arm compute coordinate object from rank
+ * @param[in] rank  Rank number
+ * @return    Coordinate object
+ */
+::arm_compute::Coordinates getARMComputeAxises(uint32_t rank);
+
+/**
+ * @brief     Generate arm compute coordinate object from runtime coordinate object
+ * @param[in] runtime_coord        Runtime coordinates object
+ * @param[in] axises               Coordinates for axises to map runtime-coordinates to
+ *                                 arm_compute-coordinates
+ * @return    Arm_compute coordinate object
+ */
+::arm_compute::Coordinates asARMComputeCoordinates(const ::arm_compute::Coordinates &runtime_coord,
+                                                   const ::arm_compute::Coordinates &axises);
+
+/**
+* @brief      Generate arm compute permutation vector from runtime permutation vector
+* @param[in]  rank                 Rank number supported upto 4
+* @param[in]  runtime_pv           Integer array for runtime permutation vector
+* @return     Permutation vector of arm compute
+*/
+::arm_compute::PermutationVector getARMComputePermutationVector(uint32_t rank,
+                                                                const int32_t *runtime_pv);
+/**
+ * @brief     Cast from shape of internal to arm compute
+ * @param[in] shape                 Internal shape object
+ * @param[in] apply_dim_correction  Flag to state whether apply dimension correction after setting
+ *                                  one dimension in arm compute
+ * @return    TensorShape object of arm compute
+ */
+::arm_compute::TensorShape asTensorShape(const internal::tflite::operand::Shape &shape,
+                                         bool apply_dim_correction = true);
+
+/**
+ * @brief     Cast from data type enum of NNAPI to arm compute
+ * @param[in] type  NNAPI data type
+ * @return    Data type of arm compute
+ */
+::arm_compute::DataType asDataType(const int32_t type);
+
+/**
+ * @brief     Cast from NNAPI activation type enum to activation object of arm compute
+ * @param[in] code  NNAPI activation type
+ * @return    ActivationLayerInfo object of arm compute
+ */
+::arm_compute::ActivationLayerInfo asActivationInfo(FuseCode code);
+
+/**
+ * @brief     Generate quantization info object of arm compute
+ * @param[in] scale   Scale of quantization
+ * @param[in] offset  Offset of quantization
+ * @return    QuantizationInfo object of arm compute
+ */
+::arm_compute::QuantizationInfo asQuantizationInfo(const float scale, const int32_t offset);
+
+/**
+ * @brief     Cast from internal tensor info to tensor info object of arm compute
+ * @param[in] shape     Tensor shape
+ * @param[in] type      Tensor type
+ * @param[in] scale     Scale of tensor quantization
+ * @param[in] zeroPoint Zeropoint of tensor quantization
+ * @return    TensorInfo object of arm compute
+ */
+::arm_compute::TensorInfo asTensorInfo(const ::arm_compute::TensorShape &shape, const int32_t type,
+                                       const float scale = 0.0f, const int32_t zeroPoint = 0);
+
+/**
+ * @brief     Cast from internal tensor info to tensor info object of arm compute
+ * @param[in] shape     Tensor shape
+ * @param[in] type      Tensor type of arm compute
+ * @param[in] scale     Scale of tensor quantization
+ * @param[in] zeroPoint Zeropoint of tensor quantization
+ * @return    TensorInfo object of arm compute
+ */
+::arm_compute::TensorInfo asTensorInfo(const ::arm_compute::TensorShape &shape,
+                                       const ::arm_compute::DataType &type, const float scale,
+                                       const int32_t zeroPoint);
+
+/**
+ * @brief       Set value to arm compute tensor with casting
+ * @param[in]   value Value to set
+ * @param[out]  to    Target tensor of arm compute
+ * @param[in]   id    Position of element
+ * @return      N/A
+ */
+template <typename FromT>
+void copyCast(const FromT value, ::arm_compute::ITensor *to, const ::arm_compute::Coordinates &id)
+{
+  switch (to->info()->data_type())
+  {
+    case ::arm_compute::DataType::F32:
+    {
+      *reinterpret_cast<float *>(to->ptr_to_element(id)) = static_cast<float>(value);
+      break;
+    }
+    case ::arm_compute::DataType::S32:
+    {
+      *reinterpret_cast<int32_t *>(to->ptr_to_element(id)) = static_cast<int32_t>(value);
+      break;
+    }
+    case ::arm_compute::DataType::U32:
+    {
+      *reinterpret_cast<uint32_t *>(to->ptr_to_element(id)) = static_cast<uint32_t>(value);
+      break;
+    }
+    case ::arm_compute::DataType::QASYMM8:
+    {
+      float realValue = static_cast<float>(value);
+      // NOTE We haven't known the policy of rounding for quantization.
+      //      So this is set to a temporary value.
+      *(to->ptr_to_element(id)) = to->info()->quantization_info().quantize(
+          realValue, ::arm_compute::RoundingPolicy::TO_ZERO);
+      break;
+    }
+    default:
+      throw std::runtime_error("Not supported, yet");
+      break;
+  }
+}
+
+#endif // __ARM_COMPUTE_CAST_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/arm_compute/feature/View.h b/runtime/contrib/pure_arm_compute/src/internal/arm_compute/feature/View.h
new file mode 100644
index 000000000..c989ef4c2
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/arm_compute/feature/View.h
@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    View.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines internal::arm_compute::feature::View class
+ */
+#ifndef __INTERNAL_ARM_COMPUTE_FEATURE_VIEW_H__
+#define __INTERNAL_ARM_COMPUTE_FEATURE_VIEW_H__
+
+#include "misc/feature/Reader.h"
+
+#include <arm_compute/core/ITensor.h>
+
+namespace internal
+{
+namespace arm_compute
+{
+namespace feature
+{
+
+/**
+ * @brief Class to access feature's element
+ */
+template <typename T> class View final : public nnfw::misc::feature::Reader<T>
+{
+public:
+  /**
+   * @brief     Construct a new View object
+   * @param[in] tensor  Feature to support access
+   */
+  View(::arm_compute::ITensor *tensor) : _tensor{tensor}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief     Get value of element in 3D feature using channel, row and column
+   * @param[in] ch  Channel index
+   * @param[in] row Row index
+   * @param[in] col Column index
+   * @return    Value of element
+   */
+  T at(uint32_t ch, uint32_t row, uint32_t col) const override
+  {
+    const auto offset = feature_index_to_byte_offset(ch, row, col);
+
+    T *ptr = reinterpret_cast<T *>(_tensor->buffer() + offset);
+
+    return *ptr;
+  }
+
+  /**
+   * @brief     Get value of element in 4D feature using batch, channel, row and column
+   * @param[in] batch Batch index
+   * @param[in] ch    Channel index
+   * @param[in] row   Row index
+   * @param[in] col   Column index
+   * @return    Value of element
+   */
+  T at(uint32_t batch, uint32_t ch, uint32_t row, uint32_t col) const override
+  {
+    const auto offset = feature_index_to_byte_offset(batch, ch, row, col);
+
+    T *ptr = reinterpret_cast<T *>(_tensor->buffer() + offset);
+
+    return *ptr;
+  }
+
+public:
+  /**
+   * @brief     Get reference of element in 3D feature using channel, row and column
+   * @param[in] ch  Channel index
+   * @param[in] row Row index
+   * @param[in] col Column index
+   * @return    Reference of element
+   */
+  T &at(uint32_t ch, uint32_t row, uint32_t col)
+  {
+    const auto offset = feature_index_to_byte_offset(ch, row, col);
+
+    T *ptr = reinterpret_cast<T *>(_tensor->buffer() + offset);
+
+    return *ptr;
+  }
+
+  /**
+   * @brief     Get reference of element in 4D feature using batch, channel, row and column
+   * @param[in] batch Batch index
+   * @param[in] ch    Channel index
+   * @param[in] row   Row index
+   * @param[in] col   Column index
+   * @return    Reference of element
+   */
+  T &at(uint32_t batch, uint32_t ch, uint32_t row, uint32_t col)
+  {
+    const auto offset = feature_index_to_byte_offset(batch, ch, row, col);
+
+    T *ptr = reinterpret_cast<T *>(_tensor->buffer() + offset);
+
+    return *ptr;
+  }
+
+private:
+  /**
+   * @brief     Get offset of element in 3D feature
+   * @param[in] ch  Channel index
+   * @param[in] row Row index
+   * @param[in] col Column index
+   * @return    Offset of element
+   */
+  size_t feature_index_to_byte_offset(uint32_t ch, uint32_t row, uint32_t col) const
+  {
+    // ARM Compute uses CHW ordering
+    return _tensor->info()->offset_element_in_bytes(::arm_compute::Coordinates{col, row, ch});
+  }
+
+  /**
+   * @brief     Get offset of element in 4D feature
+   * @param[in] batch Batch index
+   * @param[in] ch    Channel index
+   * @param[in] row   Row index
+   * @param[in] col   Column index
+   * @return    Offset of element
+   */
+  size_t feature_index_to_byte_offset(uint32_t batch, uint32_t ch, uint32_t row, uint32_t col) const
+  {
+    // ARM Compute uses CHW ordering
+    return _tensor->info()->offset_element_in_bytes(
+        ::arm_compute::Coordinates{col, row, ch, batch});
+  }
+
+private:
+  ::arm_compute::ITensor *_tensor;
+};
+
+} // namespace feature
+} // namespace arm_compute
+} // namespace internal
+
+#endif // __INTERNAL_ARM_COMPUTE_FEATURE_VIEW_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/arm_compute/kernel/View.h b/runtime/contrib/pure_arm_compute/src/internal/arm_compute/kernel/View.h
new file mode 100644
index 000000000..399cdf913
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/arm_compute/kernel/View.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    View.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines internel::arm_compute::kernel::View class
+ */
+#ifndef __INTERNAL_ARM_COMPUTE_KERNEL_VIEW_H__
+#define __INTERNAL_ARM_COMPUTE_KERNEL_VIEW_H__
+
+#include "misc/kernel/Shape.h"
+#include "misc/kernel/Reader.h"
+
+#include <arm_compute/core/ITensor.h>
+
+namespace internal
+{
+namespace arm_compute
+{
+namespace kernel
+{
+
+/**
+ * @brief Class to access kernel's element
+ */
+template <typename T> class View final : public nnfw::misc::kernel::Reader<T>
+{
+public:
+  /**
+   * @brief     Construct a new View object
+   * @param[in] tensor  Kernel to support access
+   */
+  View(::arm_compute::ITensor *tensor) : _tensor{tensor}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief     Get value of element in kernel
+   * @param[in] nth Kernel index
+   * @param[in] ch  Channel index
+   * @param[in] row Row index
+   * @param[in] col Column index
+   * @return    Value of element
+   */
+  T at(uint32_t nth, uint32_t ch, uint32_t row, uint32_t col) const override
+  {
+    const auto offset = kernel_index_to_byte_offset(nth, ch, row, col);
+
+    T *ptr = reinterpret_cast<T *>(_tensor->buffer() + offset);
+
+    return *ptr;
+  }
+
+public:
+  /**
+   * @brief     Get reference of element in kernel
+   * @param[in] nth Kernel index
+   * @param[in] ch  Channel index
+   * @param[in] row Row index
+   * @param[in] col Column index
+   * @return    Reference of element
+   */
+  T &at(uint32_t nth, uint32_t ch, uint32_t row, uint32_t col)
+  {
+    const auto offset = kernel_index_to_byte_offset(nth, ch, row, col);
+
+    T *ptr = reinterpret_cast<T *>(_tensor->buffer() + offset);
+
+    return *ptr;
+  }
+
+private:
+  /**
+   * @brief     Get offset of element in kernel
+   * @param[in] nth Kernel index
+   * @param[in] ch  Channel index
+   * @param[in] row Row index
+   * @param[in] col Column index
+   * @return    Offset of element
+   */
+  size_t kernel_index_to_byte_offset(uint32_t nth, uint32_t ch, uint32_t row, uint32_t col) const
+  {
+    return _tensor->info()->offset_element_in_bytes(::arm_compute::Coordinates{col, row, ch, nth});
+  }
+
+private:
+  ::arm_compute::ITensor *_tensor;
+};
+
+} // namespace kernel
+} // namespace arm_compute
+} // namespace internal
+
+#endif // __INTERNAL_ARM_COMPUTE_FEATURE_VIEW_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/arm_compute/matrix/View.h b/runtime/contrib/pure_arm_compute/src/internal/arm_compute/matrix/View.h
new file mode 100644
index 000000000..305fff729
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/arm_compute/matrix/View.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    View.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines internal::arm_compute::matrix::View class
+ */
+#ifndef __INTERNAL_ARM_COMPUTE_MATRIX_VIEW_H__
+#define __INTERNAL_ARM_COMPUTE_MATRIX_VIEW_H__
+
+#include "misc/matrix/Shape.h"
+#include "misc/matrix/Reader.h"
+
+#include <arm_compute/core/ITensor.h>
+
+namespace internal
+{
+namespace arm_compute
+{
+namespace matrix
+{
+
+/**
+ * @brief Class to access matrix's element
+ */
+template <typename T> class View final : public nnfw::misc::matrix::Reader<T>
+{
+public:
+  /**
+   * @brief     Construct a new View object
+   * @param[in] tensor  Matrix to support access
+   */
+  View(::arm_compute::ITensor *tensor) : _tensor{tensor}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief     Get value of element in matrix
+   * @param[in] row Row index
+   * @param[in] col Column index
+   * @return    Value of element
+   */
+  T at(uint32_t row, uint32_t col) const override
+  {
+    const auto offset = matrix_index_to_byte_offset(row, col);
+
+    T *ptr = reinterpret_cast<T *>(_tensor->buffer() + offset);
+
+    return *ptr;
+  }
+
+public:
+  /**
+   * @brief     Get reference of element in matrix
+   * @param[in] row Row index
+   * @param[in] col Column index
+   * @return    Refence of element
+   */
+  T &at(uint32_t row, uint32_t col)
+  {
+    const auto offset = matrix_index_to_byte_offset(row, col);
+
+    T *ptr = reinterpret_cast<T *>(_tensor->buffer() + offset);
+
+    return *ptr;
+  }
+
+private:
+  /**
+   * @brief     Get offset of element in matrix
+   * @param[in] row Row index
+   * @param[in] col Column index
+   * @return    Offset of element
+   */
+  size_t matrix_index_to_byte_offset(uint32_t row, uint32_t col) const
+  {
+    return _tensor->info()->offset_element_in_bytes(::arm_compute::Coordinates{col, row});
+  }
+
+private:
+  ::arm_compute::ITensor *_tensor;
+};
+
+} // namespace matrix
+} // namespace arm_compute
+} // namespace internal
+
+#endif // __INTERNAL_ARM_COMPUTE_MATRIX_VIEW_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/arm_compute/tensor/View.h b/runtime/contrib/pure_arm_compute/src/internal/arm_compute/tensor/View.h
new file mode 100644
index 000000000..372bd682d
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/arm_compute/tensor/View.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    View.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines internal::arm_compute::tensor::View class
+ */
+#ifndef __INTERNAL_ARM_COMPUTE_TENSOR_VIEW_H__
+#define __INTERNAL_ARM_COMPUTE_TENSOR_VIEW_H__
+
+#include "misc/tensor/Shape.h"
+#include "misc/tensor/Index.h"
+
+#include <arm_compute/core/ITensor.h>
+
+namespace internal
+{
+namespace arm_compute
+{
+namespace tensor
+{
+
+/**
+ * @brief Class to access tensor's element
+ */
+template <typename T> class View
+{
+public:
+  /**
+   * @brief     Construct a new View object
+   * @param[in] tensor  Tensor to support access
+   */
+  View(::arm_compute::ITensor *tensor) : _tensor{tensor}
+  {
+    // DO NOTHING
+  }
+
+private:
+  /**
+   * @brief     Get offset of element in tensor
+   * @param[in] index Index of element
+   * @return    Offset of element
+   */
+  uint32_t byte_offset_of(const nnfw::misc::tensor::Index &index) const
+  {
+    // NOTE index.rank() >= _tensor->info()->num_dimensions() should hold here
+    const uint32_t rank = index.rank();
+
+    ::arm_compute::Coordinates coordinates;
+
+    coordinates.set_num_dimensions(rank);
+
+    for (uint32_t axis = 0; axis < rank; ++axis)
+    {
+      coordinates[axis] = index.at(axis);
+    }
+
+    return _tensor->info()->offset_element_in_bytes(coordinates);
+  }
+
+public:
+  /**
+   * @brief     Get value of element in tensor
+   * @param[in] index Index of element
+   * @return    Value of element
+   */
+  T at(const nnfw::misc::tensor::Index &index) const
+  {
+    const auto offset = byte_offset_of(index);
+
+    T *ptr = reinterpret_cast<T *>(_tensor->buffer() + offset);
+
+    return *ptr;
+  }
+
+  /**
+   * @brief     Get reference of element in tensor
+   * @param[in] index Index of element
+   * @return    Reference of element
+   */
+  T &at(const nnfw::misc::tensor::Index &index)
+  {
+    const auto offset = byte_offset_of(index);
+
+    T *ptr = reinterpret_cast<T *>(_tensor->buffer() + offset);
+
+    return *ptr;
+  }
+
+private:
+  ::arm_compute::ITensor *_tensor;
+};
+
+} // namespace tensor
+} // namespace arm_compute
+} // namespace internal
+
+#endif // __INTERNAL_ARM_COMPUTE_TENSOR_VIEW_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/nnapi/feature/Reader.h b/runtime/contrib/pure_arm_compute/src/internal/nnapi/feature/Reader.h
new file mode 100644
index 000000000..ac25692a1
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/nnapi/feature/Reader.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    Reader.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines internal::nnapi::feature::Reader
+ */
+#ifndef __INTERNAL_NNAPI_FEATURE_READER_H__
+#define __INTERNAL_NNAPI_FEATURE_READER_H__
+
+#include "internal/nnapi/feature/Utils.h"
+
+#include "misc/feature/Reader.h"
+
+namespace internal
+{
+namespace nnapi
+{
+namespace feature
+{
+
+/**
+ * @brief Class to support reading element in feature(3D, 4D)
+ */
+template <typename T> class Reader final : public nnfw::misc::feature::Reader<T>
+{
+public:
+  /**
+   * @brief     Construct a new Reader object
+   * @param[in] shape Shape of feature
+   * @param[in] ptr   Pointer to feature data
+   * @param[in] len   Size of tensor (byte)
+   */
+  // NOTE The parameter len denotes the number of bytes.
+  Reader(const ::nnfw::misc::feature::Shape &shape, const T *ptr, size_t len)
+      : _shape{shape}, _ptr{ptr}
+  {
+    assert(shape.N * shape.C * shape.H * shape.W * sizeof(T) == len);
+  }
+
+public:
+  /**
+   * @brief   Get shape of feature
+   * @return  Shape of feature
+   */
+  const nnfw::misc::feature::Shape &shape(void) const { return _shape; }
+
+public:
+  /**
+   * @brief     Get value of element using channel, row, and column index for 3D feature
+   * @param[in] ch  Channel index
+   * @param[in] row Row index
+   * @param[in] col Column index
+   * @return    Value of element
+   */
+  T at(uint32_t ch, uint32_t row, uint32_t col) const override
+  {
+    uint32_t index = index_of(_shape, ch, row, col);
+
+    const auto arr = reinterpret_cast<const T *>(_ptr);
+
+    return arr[index];
+  }
+
+  /**
+   * @brief     Get value of element using batch, channel, row, and column index for 4D feature
+   * @param[in] batch Batch index
+   * @param[in] ch    Channel index
+   * @param[in] row   Row index
+   * @param[in] col   Column index
+   * @return    Value of element
+   */
+  T at(uint32_t batch, uint32_t ch, uint32_t row, uint32_t col) const override
+  {
+    uint32_t index = index_of(_shape, batch, ch, row, col);
+
+    return _ptr[index];
+  }
+
+private:
+  nnfw::misc::feature::Shape _shape;
+
+private:
+  const T *_ptr;
+};
+
+} // namespace feature
+} // namespace nnapi
+} // namespace internal
+
+#endif // __INTERNAL_NNAPI_FEATURE_READER_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/nnapi/feature/Utils.h b/runtime/contrib/pure_arm_compute/src/internal/nnapi/feature/Utils.h
new file mode 100644
index 000000000..ee59d217e
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/nnapi/feature/Utils.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Utils.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief This file defines utility functions used in internal::nnapi::feature namespace
+ */
+#ifndef __INTERNAL_NNAPI_FEATURE_UTILS_H__
+#define __INTERNAL_NNAPI_FEATURE_UTILS_H__
+
+#include "misc/feature/Shape.h"
+
+namespace internal
+{
+namespace nnapi
+{
+namespace feature
+{
+
+/**
+ * @brief     Get position of element using channel, row, and column for 3D feature
+ * @param[in] shape Shape of feature
+ * @param[in] ch    Channel index
+ * @param[in] row   Row index
+ * @param[in] col   Column index
+ * @return    Position of element
+ */
+inline uint32_t index_of(const ::nnfw::misc::feature::Shape &shape, uint32_t ch, uint32_t row,
+                         uint32_t col)
+{
+  uint32_t res = 0;
+
+  // NNAPI uses NHWC ordering
+  res += row * shape.W * shape.C;
+  res += col * shape.C;
+  res += ch;
+
+  return res;
+}
+
+/**
+ * @brief     Get position of element using batch, channel, row, and column for 4D feature
+ * @param[in] shape Shape of feature
+ * @param[in] batch Batch index
+ * @param[in] ch    Channel index
+ * @param[in] row   Row index
+ * @param[in] col   Column index
+ * @return    Position of element
+ */
+inline uint32_t index_of(const ::nnfw::misc::feature::Shape &shape, uint32_t batch, uint32_t ch,
+                         uint32_t row, uint32_t col)
+{
+  uint32_t res = 0;
+
+  // NNAPI uses NHWC ordering
+  res += batch * shape.H * shape.W * shape.C;
+  res += row * shape.W * shape.C;
+  res += col * shape.C;
+  res += ch;
+
+  return res;
+}
+
+} // namespace feature
+} // namespace nnapi
+} // namespace internal
+
+#endif // __INTERNAL_NNAPI_FEATURE_UTILS_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/nnapi/feature/View.h b/runtime/contrib/pure_arm_compute/src/internal/nnapi/feature/View.h
new file mode 100644
index 000000000..965e42f1c
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/nnapi/feature/View.h
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    View.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines internal::nnapi::feature::View class
+ */
+#ifndef __INTERNAL_NNAPI_FEATURE_VIEW_H__
+#define __INTERNAL_NNAPI_FEATURE_VIEW_H__
+
+#include "internal/nnapi/feature/Utils.h"
+
+#include "misc/feature/Reader.h"
+
+namespace internal
+{
+namespace nnapi
+{
+namespace feature
+{
+
+/**
+ * @brief   Class to access feature's element information using index
+ */
+template <typename T> class View final : public nnfw::misc::feature::Reader<T>
+{
+public:
+  /**
+   * @brief     Construct a new View object
+   * @param[in] shape Shape of feature
+   * @param[in] ptr   Pointer to feature data
+   * @param[in] len   Size of feature (byte)
+   * @return
+   */
+  // NOTE The parameter len denotes the number of bytes.
+  View(const ::nnfw::misc::feature::Shape &shape, T *ptr, size_t len) : _shape{shape}, _ptr{ptr}
+  {
+    assert(shape.N * shape.C * shape.H * shape.W * sizeof(T) == len);
+  }
+
+public:
+  /**
+   * @brief   Get shape of feature
+   * @return  Shape of feature
+   */
+  const nnfw::misc::feature::Shape &shape(void) const { return _shape; }
+
+public:
+  /**
+   * @brief     Get value of element in 3D feature using channel, row, and column index
+   * @param[in] ch  Channel index
+   * @param[in] row Row index
+   * @param[in] col Column index
+   * @return    Value of element
+   */
+  T at(uint32_t ch, uint32_t row, uint32_t col) const override
+  {
+    uint32_t index = index_of(_shape, ch, row, col);
+
+    return _ptr[index];
+  }
+
+  /**
+   * @brief     Get value of element in 4D feature using batch, channel, row and column index
+   * @param[in] batch Batch index
+   * @param[in] ch    Channel index
+   * @param[in] row   Row index
+   * @param[in] col   Column index
+   * @return    Value of element
+   */
+  T at(uint32_t batch, uint32_t ch, uint32_t row, uint32_t col) const override
+  {
+    uint32_t index = index_of(_shape, batch, ch, row, col);
+
+    return _ptr[index];
+  }
+
+  /**
+   * @brief     Get reference of element in 3D feature using channel, row, and column index
+   * @param[in] ch  Channel index
+   * @param[in] row Row index
+   * @param[in] col Column index
+   * @return    Reference of element
+   */
+  T &at(uint32_t ch, uint32_t row, uint32_t col)
+  {
+    uint32_t index = index_of(_shape, ch, row, col);
+
+    return _ptr[index];
+  }
+
+  /**
+   * @brief     Get reference of element in 4D feature using batch, channel, row and column index
+   * @param[in] batch Batch index
+   * @param[in] ch    Channel index
+   * @param[in] row   Row index
+   * @param[in] col   Column index
+   * @return    Reference of element
+   */
+  T &at(uint32_t batch, uint32_t ch, uint32_t row, uint32_t col)
+  {
+    uint32_t index = index_of(_shape, batch, ch, row, col);
+
+    return _ptr[index];
+  }
+
+private:
+  nnfw::misc::feature::Shape _shape;
+
+private:
+  T *_ptr;
+};
+
+} // namespace feature
+} // namespace nnapi
+} // namespace internal
+
+#endif // __INTERNAL_NNAPI_FEATURE_VIEW_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/nnapi/kernel/Reader.h b/runtime/contrib/pure_arm_compute/src/internal/nnapi/kernel/Reader.h
new file mode 100644
index 000000000..ae964f74c
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/nnapi/kernel/Reader.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    Reader.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines internal::nnapi::kernel::Reader class
+ */
+#ifndef __INTERNAL_NNAPI_KERNEL_READER_H__
+#define __INTERNAL_NNAPI_KERNEL_READER_H__
+
+#include "misc/kernel/Shape.h"
+#include "misc/kernel/Reader.h"
+
+namespace internal
+{
+namespace nnapi
+{
+namespace kernel
+{
+
+/**
+ * @brief Class to support reading element in kernel
+ */
+template <typename T> class Reader final : public nnfw::misc::kernel::Reader<T>
+{
+public:
+  /**
+   * @brief     Construct a new Reader object
+   * @param[in] shape Shape of kernel
+   * @param[in] ptr   Pointer to kernel data
+   * @param[in] len   Size of kernel (byte)
+   */
+  // NOTE The parameter len denotes the number of bytes.
+  Reader(const ::nnfw::misc::kernel::Shape &shape, const T *ptr, size_t len)
+      : _shape{shape}, _ptr{ptr}
+  {
+    assert(shape.N * shape.C * shape.H * shape.W * sizeof(T) == len);
+  }
+
+public:
+  /**
+   * @brief   Get shape of kernel
+   * @return  Shape of kernel
+   */
+  const nnfw::misc::kernel::Shape &shape(void) const { return _shape; }
+
+public:
+  /**
+   * @brief     Get value of element for kernel
+   * @param[in] nth Kernel index
+   * @param[in] ch  Channel index
+   * @param[in] row Row index
+   * @param[in] col Column index
+   * @return    Value of element
+   */
+  T at(uint32_t nth, uint32_t ch, uint32_t row, uint32_t col) const override
+  {
+    // NNAPI uses NHWC ordering
+    uint32_t index = 0;
+
+    index += nth * _shape.H * _shape.W * _shape.C;
+    index += row * _shape.W * _shape.C;
+    index += col * _shape.C;
+    index += ch;
+
+    return _ptr[index];
+  }
+
+private:
+  nnfw::misc::kernel::Shape _shape;
+
+private:
+  const T *_ptr;
+};
+
+} // namespace kernel
+} // namespace nnapi
+} // namespace internal
+
+#endif // __INTERNAL_NNAPI_KERNEL_READER_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/nnapi/matrix/Reader.h b/runtime/contrib/pure_arm_compute/src/internal/nnapi/matrix/Reader.h
new file mode 100644
index 000000000..f03a4be31
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/nnapi/matrix/Reader.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    Reader.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines internal::nnapi::matrix::Reader class
+ */
+#ifndef __INTERNAL_NNAPI_MATRIX_READER_H__
+#define __INTERNAL_NNAPI_MATRIX_READER_H__
+
+#include "misc/matrix/Shape.h"
+#include "misc/matrix/Reader.h"
+
+namespace internal
+{
+namespace nnapi
+{
+namespace matrix
+{
+
+/**
+ * @brief   Class to support reading element in matrix
+ */
+template <typename T> class Reader final : public nnfw::misc::matrix::Reader<T>
+{
+public:
+  /**
+   * @brief     Construct a new Reader object
+   * @param[in] shape Shape of matrix
+   * @param[in] ptr   Pointer to matrix data
+   * @param[in] len   Size of matrix (byte)
+   */
+  // NOTE The parameter len denotes the number of bytes.
+  Reader(const ::nnfw::misc::matrix::Shape &shape, const T *ptr, size_t len)
+      : _shape{shape}, _ptr{ptr}
+  {
+    assert(shape.H * shape.W * sizeof(T) == len);
+  }
+
+public:
+  /**
+   * @brief   Get shape of matrix
+   * @return  Shape of matrix
+   */
+  const nnfw::misc::matrix::Shape &shape(void) const { return _shape; }
+
+public:
+  /**
+   * @brief     Get value of element for matrix
+   * @param[in] row Row index
+   * @param[in] col Column index
+   * @return    Value of element
+   */
+  T at(uint32_t row, uint32_t col) const override
+  {
+    // NNAPI uses NHWC ordering
+    uint32_t index = 0;
+
+    index += row * _shape.W;
+    index += col;
+
+    return _ptr[index];
+  }
+
+private:
+  nnfw::misc::matrix::Shape _shape;
+
+private:
+  const T *_ptr;
+};
+
+} // namespace matrix
+} // namespace nnapi
+} // namespace internal
+
+#endif // __INTERNAL_NNAPI_MATRIX_READER_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/nnapi/tensor/ConstView.h b/runtime/contrib/pure_arm_compute/src/internal/nnapi/tensor/ConstView.h
new file mode 100644
index 000000000..6a3fff646
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/nnapi/tensor/ConstView.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file        ConstView.h
+ * @brief       This file contains ConstView class
+ * @ingroup     COM_AI_RUNTIME
+ */
+
+#ifndef __INTERNAL_NNAPI_TENSOR_CONST_VIEW_H__
+#define __INTERNAL_NNAPI_TENSOR_CONST_VIEW_H__
+
+#include "util/tensor/Shape.h"
+#include "util/tensor/Index.h"
+
+namespace internal
+{
+namespace nnapi
+{
+namespace tensor
+{
+
+/**
+ * @brief Wrapper class to read tensor values
+ * @tparam T The tensor element type
+ */
+template <typename T> class ConstView
+{
+public:
+  /**
+   * @brief Construct a ConstView class
+   * @param[in] shape Tensor shape
+   * @param[in] ptr The base pointer of actual data
+   * @param[in] len The number of bytes
+   */
+  ConstView(const ::nnfw::misc::tensor::Shape &shape, const uint8_t *ptr, size_t len)
+      : _shape{shape}, _ptr{ptr}, _len{len}
+  {
+    // DO NOTHING
+  }
+
+public:
+  const nnfw::misc::tensor::Shape &shape(void) const { return _shape; }
+
+private:
+  // TODO Make this as a helper function, and share it for both View<T> and ConstView<T>
+  /**
+   * @brief Calculate offset for the given tensor index
+   * @param[in] index Tensor index
+   * @return The calculated offset
+   */
+  uint32_t offset_of(const nnfw::misc::tensor::Index &index) const
+  {
+    if (_shape.rank() == 0)
+    {
+      return 0;
+    }
+
+    uint32_t offset = index.at(0);
+
+    // Stride decreases as axis increases in NNAPI
+    for (uint32_t axis = 1; axis < _shape.rank(); ++axis)
+    {
+      offset *= _shape.dim(axis);
+      offset += index.at(axis);
+    }
+
+    return offset;
+  }
+
+public:
+  /**
+   * @brief Get the value on the given index
+   * @param[in] index Flattened tensor index
+   * @return The value on the given index
+   */
+  T at(const nnfw::misc::tensor::Index &index) const
+  {
+    const auto offset = offset_of(index);
+
+    const T *arr = reinterpret_cast<const T *>(_ptr);
+
+    return arr[offset];
+  }
+
+private:
+  const nnfw::misc::tensor::Shape _shape;
+
+private:
+  const uint8_t *const _ptr;
+  const size_t _len;
+};
+
+} // namespace tensor
+} // namespace nnapi
+} // namespace internal
+
+#endif // __INTERNAL_NNAPI_TENSOR_CONST_VIEW_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/nnapi/tensor/Reader.h b/runtime/contrib/pure_arm_compute/src/internal/nnapi/tensor/Reader.h
new file mode 100644
index 000000000..fc6d490da
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/nnapi/tensor/Reader.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file        Reader.h
+ * @brief       This file contains Reader class
+ * @ingroup     COM_AI_RUNTIME
+ */
+
+#ifndef __INTERNAL_NNAPI_TENSOR_READER_H__
+#define __INTERNAL_NNAPI_TENSOR_READER_H__
+
+#include <vector>
+#include "misc/tensor/Reader.h"
+
+namespace internal
+{
+namespace nnapi
+{
+namespace tensor
+{
+
+/**
+ * @brief Wrapper class to read tensor values
+ * @tparam T The tensor element type
+ */
+template <typename T> class Reader final : public nnfw::misc::tensor::Reader<T>
+{
+public:
+  /**
+   * @brief Construct a Reader class
+   * @param[in] shape Tensor shape
+   * @param[in] ptr The base pointer of actual data
+   * @param[in] len The number of bytes
+   */
+  Reader(const ::nnfw::misc::tensor::Shape &shape, const T *ptr, size_t len)
+      : _shape{shape}, _ptr{ptr}
+  {
+    assert(shape.num_elements() * sizeof(T) == len);
+    initialize();
+  }
+
+public:
+  /**
+   * @brief Get shape object
+   * @return The shape as const reference
+   */
+  const nnfw::misc::tensor::Shape &shape(void) const { return _shape; }
+
+public:
+  /**
+   * @brief Get the value on the given index
+   * @param[in] index_nnapi Flattened tensor index
+   * @return The value on the given index
+   */
+  T at(const nnfw::misc::tensor::Index &index_nnapi) const override
+  {
+    uint32_t offset = 0;
+
+    for (int i = 0; i < _shape.rank(); i++)
+      offset += index_nnapi.at(i) * _stridess.at(i);
+
+    return _ptr[offset];
+  }
+
+private:
+  /**
+   * @brief Initializes @c _stridess
+   * @return N/A
+   * @note Assuming that shape is [d4, .. , d1] and data is stored at a pointer ptr,
+           we need to calculate the offset of index [i4, .. i1] as follows:
+           offset = i4 * (d3 * d2 * d1) +
+                    i3 * (d2 * d1) +
+                    i2 * (d1) +
+                    i1
+           So (d4 * d3 * d2 * d1) or (d3 * d2 * d1) or (d2 * d1) happens whenever offset is
+           calculate. To minimize this repetitive calculation,
+           _stridess[n] contains _spape[n-1]*_spape[n-2]*_spape[0]
+   */
+  void initialize(void)
+  {
+    for (int r = 0; r < _shape.rank(); r++)
+    {
+      int elem_count = 1;
+      for (int k = r + 1; k < _shape.rank(); k++)
+        elem_count *= _shape.dim(k);
+      _stridess.emplace_back(elem_count);
+    }
+  }
+
+private:
+  nnfw::misc::tensor::Shape _shape;
+
+private:
+  const T *_ptr;
+  std::vector<int32_t> _stridess;
+};
+
+} // namespace tensor
+} // namespace nnapi
+} // namespace internal
+
+#endif // __INTERNAL_NNAPI_TENSOR_READER_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/nnapi/tensor/View.h b/runtime/contrib/pure_arm_compute/src/internal/nnapi/tensor/View.h
new file mode 100644
index 000000000..4766851b9
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/nnapi/tensor/View.h
@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    View.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines internal::nnapi::tensor::View class
+ */
+#ifndef __INTERNAL_NNAPI_TENSOR_VIEW_H__
+#define __INTERNAL_NNAPI_TENSOR_VIEW_H__
+
+#include "misc/tensor/Shape.h"
+#include "misc/tensor/Index.h"
+
+namespace internal
+{
+namespace nnapi
+{
+namespace tensor
+{
+
+/**
+ * @brief Class to access tensor's element information using index
+ */
+template <typename T> class View
+{
+public:
+  /**
+   * @brief     Construct a new View object
+   * @param[in] shape Shape of tensor
+   * @param[in] ptr   Pointer to tensor data
+   * @param[in] len   Size of tensor (byte)
+   */
+  // NOTE The parameter len denotes the number of bytes.
+  View(const ::nnfw::misc::tensor::Shape &shape, T *ptr, size_t len) : _shape{shape}, _ptr{ptr}
+  {
+    assert(shape.num_elements() * sizeof(T) == len);
+  }
+
+public:
+  /**
+   * @brief   Get shape of tensor
+   * @return  Shape of tensor
+   */
+  const nnfw::misc::tensor::Shape &shape(void) const { return _shape; }
+
+private:
+  /**
+   * @brief     Get position of element using index in tensor
+   * @param[in] index Index of element
+   * @return    Position of element
+   */
+  uint32_t offset_of(const nnfw::misc::tensor::Index &index) const
+  {
+    if (_shape.rank() == 0)
+    {
+      return 0;
+    }
+
+    uint32_t offset = index.at(0);
+
+    // Stride decreases as axis increases in NNAPI
+    for (uint32_t axis = 1; axis < _shape.rank(); ++axis)
+    {
+      offset *= _shape.dim(axis);
+      offset += index.at(axis);
+    }
+
+    return offset;
+  }
+
+public:
+  /**
+   * @brief     Get value of element at index
+   * @param[in] index Index of element
+   * @return    Value of element at index
+   */
+  T at(const nnfw::misc::tensor::Index &index) const
+  {
+    const auto offset = offset_of(index);
+
+    return _ptr[offset];
+  }
+
+  /**
+   * @brief     Get reference of element at index
+   * @param[in] index Index of element
+   * @return    Reference of element at index
+   */
+  T &at(const nnfw::misc::tensor::Index &index)
+  {
+    const auto offset = offset_of(index);
+
+    return _ptr[offset];
+  }
+
+private:
+  nnfw::misc::tensor::Shape _shape;
+
+private:
+  T *_ptr;
+};
+
+} // namespace tensor
+} // namespace nnapi
+} // namespace internal
+
+#endif // __INTERNAL_NNAPI_TENSOR_VIEW_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Abs.cc b/runtime/contrib/pure_arm_compute/src/internal/op/Abs.cc
new file mode 100644
index 000000000..e23a9538c
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Abs.cc
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/Abs.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Abs
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Abs
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Abs
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 1 && outputCount == 1);
+
+  output_index = outputs[0];
+  input_index = inputs[0];
+}
+
+} // namespace Abs
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Abs.h b/runtime/contrib/pure_arm_compute/src/internal/op/Abs.h
new file mode 100644
index 000000000..0be8b0205
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Abs.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __INTERNAL_OP_ABS_H__
+#define __INTERNAL_OP_ABS_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Abs
+{
+
+struct Param
+{
+  int32_t output_index;
+  int32_t input_index;
+
+  Param() = default;
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+class Node final : public op::Node
+{
+public:
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  virtual ~Node() = default;
+
+public:
+  const Param &param(void) const { return _param; }
+
+public:
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace Abs
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_ABS_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Add.cc b/runtime/contrib/pure_arm_compute/src/internal/op/Add.cc
new file mode 100644
index 000000000..52803261f
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Add.cc
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/Add.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Add
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Add
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Add
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 3 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> LHS Tensor Index
+  //  1 -> RHS Tensor Index
+  //  2 -> Activation Index
+  lhs_index = inputs[0];
+  rhs_index = inputs[1];
+  activation_index = inputs[2];
+}
+
+} // namespace Add
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Add.h b/runtime/contrib/pure_arm_compute/src/internal/op/Add.h
new file mode 100644
index 000000000..a7804a569
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Add.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Add.h
+ * @brief This file contains accept function and params for Add operation
+ * @ingroup COM_AI_RUNTIME
+ */
+
+#ifndef __INTERNAL_OP_ADD_H__
+#define __INTERNAL_OP_ADD_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Add
+{
+
+/**
+ * @brief Struct of Add operation's param
+ */
+struct Param
+{
+  int32_t ofm_index; /**< Output format index */
+
+  int32_t lhs_index;        /**< Left hand side index */
+  int32_t rhs_index;        /**< Right hand side index */
+  int32_t activation_index; /**< Activation index */
+
+  /**
+   * @brief Construct a new Param object for Add as default
+   */
+  Param() = default;
+
+  /**
+   * @brief Construct a new Param object for Add with params
+   * @param [in] inputCount The number of input
+   * @param [in] inputs Array containing inputs
+   * @param [in] outputCount The number of output
+   * @param [in] outputs Array containing outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to define operation node for Add
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Node object for Add with param
+   * @param [in] param Parameters for Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destroy the Node object for Add
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief Get parameters for Add
+   * @return Parameters of Add
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Function for accepting node for Add
+   * @param [in] v Node visitor for invoking visit function of Add
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace Add
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_ADD_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/ArgMax.cc b/runtime/contrib/pure_arm_compute/src/internal/op/ArgMax.cc
new file mode 100644
index 000000000..485430377
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/ArgMax.cc
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "internal/op/ArgMax.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace ArgMax
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace ArgMax
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace ArgMax
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 2 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> Input Tensor Index
+  //  1 -> Axis Tensor Index
+  ifm_index = inputs[0];
+  axis_index = inputs[1];
+}
+
+} // namespace ArgMax
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/ArgMax.h b/runtime/contrib/pure_arm_compute/src/internal/op/ArgMax.h
new file mode 100644
index 000000000..780af2232
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/ArgMax.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __INTERNAL_OP_ARGMAX_H__
+#define __INTERNAL_OP_ARGMAX_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace ArgMax
+{
+
+struct Param
+{
+  int32_t ofm_index;
+
+  int32_t ifm_index;
+  int32_t axis_index;
+
+  Param() = default;
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+class Node final : public op::Node
+{
+public:
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  virtual ~Node() = default;
+
+public:
+  const Param &param(void) const { return _param; }
+
+public:
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace ArgMax
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_ARGMAX_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/AvgPool2D.cc b/runtime/contrib/pure_arm_compute/src/internal/op/AvgPool2D.cc
new file mode 100644
index 000000000..ae4c9411e
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/AvgPool2D.cc
@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/AvgPool2D.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace AvgPool2D
+{
+namespace Explicit
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Explicit
+
+namespace Implicit
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Implicit
+} // namespace AvgPool2D
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace AvgPool2D
+{
+namespace Explicit
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 10 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> IFM Tensor Index
+  //  1 -> Padding_left index
+  //  2 -> Padding_right index
+  //  3 -> Padding_top index
+  //  4 -> Padding_bottom index
+  //  5 -> Horizontal (over width) Stride Index
+  //  6 -> Vertial (over height) Stride Index
+  //  7 -> Filter Width Index
+  //  8 -> Filter Height Index
+  //  9 -> FuseCode (activation) Index
+  ifm_index = inputs[0];
+  padding_left_index = inputs[1];
+  padding_right_index = inputs[2];
+  padding_top_index = inputs[3];
+  padding_bottom_index = inputs[4];
+  hstride_index = inputs[5];
+  vstride_index = inputs[6];
+  kw_index = inputs[7];
+  kh_index = inputs[8];
+  activation_index = inputs[9];
+}
+
+} // namespace Explicit
+
+namespace Implicit
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 7 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> IFM Tensor Index
+  //  1 -> Padding Code (ANEURALNETWORKS_PADDING_SAME or ANEURALNETWORKS_PADDING_VALID) Index
+  //  2 -> Horizontal (over width) Stride Index
+  //  3 -> Vertial (over height) Stride Index
+  //  4 -> Filter Width Index
+  //  5 -> Filter Height Index
+  //  6 -> FuseCode (activation) Index
+  ifm_index = inputs[0];
+  padding_index = inputs[1];
+  hstride_index = inputs[2];
+  vstride_index = inputs[3];
+  kw_index = inputs[4];
+  kh_index = inputs[5];
+  activation_index = inputs[6];
+}
+
+} // namespace Implicit
+} // namespace AvgPool2D
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/AvgPool2D.h b/runtime/contrib/pure_arm_compute/src/internal/op/AvgPool2D.h
new file mode 100644
index 000000000..cf9061ca9
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/AvgPool2D.h
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    AvgPool2D.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines internal::tflite::op::AvgPool2D Param structs
+ *          and internal::tflite::op::AvgPool2D Node classes
+ */
+#ifndef __INTERNAL_OP_AVG_POOL_2D_H__
+#define __INTERNAL_OP_AVG_POOL_2D_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace AvgPool2D
+{
+namespace Explicit
+{
+
+/**
+ * @brief Struct to have indexes for operation parameter
+ */
+struct Param
+{
+  int32_t ofm_index; /**< Index of output feature map */
+
+  int32_t ifm_index; /**< Index of input feature map */
+
+  int32_t kw_index; /**< Index of kernel width */
+  int32_t kh_index; /**< Index of kernel height */
+
+  int32_t hstride_index; /**< Index of horizontal stride */
+  int32_t vstride_index; /**< Index of vertical stride */
+
+  int32_t padding_left_index;   /**< Index of padding left */
+  int32_t padding_right_index;  /**< Index of padding right */
+  int32_t padding_top_index;    /**< Index of padding top */
+  int32_t padding_bottom_index; /**< Index of padding bottom */
+
+  int32_t activation_index; /**< Index of activation */
+  /**
+   * @brief Construct as default
+   */
+  Param() = default;
+  /**
+   * @brief Construct a new Param object with params
+   * @param[in] inputCount  Count of inputs
+   * @param[in] inputs      Pointer of inputs
+   * @param[in] outputCount Count of outputs
+   * @param[in] outputs     Pointer of outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to represent an operation of data structure
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Node object with param
+   * @param[in] param Param object that makes up a Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destruct as default
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief  Get a reference of Param object
+   * @return Reference of Param object
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Visit this Node by NodeVisitor
+   * @param[in] v Visitor
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace Explicit
+
+namespace Implicit
+{
+
+/**
+ * @brief Struct to have indexes for operation parameter
+ */
+struct Param
+{
+  int32_t ofm_index; /**< Index of output feature map */
+
+  int32_t ifm_index; /**< Index of input feature map */
+
+  int32_t kw_index; /**< Index of kernel width */
+  int32_t kh_index; /**< Index of kernel height */
+
+  int32_t hstride_index; /**< Index of horizontal stride */
+  int32_t vstride_index; /**< Index of vertical stride */
+
+  int32_t padding_index;    /**< Index of padding */
+  int32_t activation_index; /**< Index of activation */
+  /**
+   * @brief Construct as default
+   */
+  Param() = default;
+  /**
+   * @brief Construct a new Param object with params
+   * @param[in] inputCount  Count of inputs
+   * @param[in] inputs      Pointer of inputs
+   * @param[in] outputCount Count of outputs
+   * @param[in] outputs     Pointer of outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to represent an operation of data structure
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Node object with param
+   * @param[in] param Param object that makes up a Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destruct as default
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief  Get a reference of Param object
+   * @return Reference of Param object
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Visit this Node by NodeVisitor
+   * @param[in] v Visitor
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace Implicit
+} // namespace AvgPool2D
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_MAX_POOL_2D_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/BatchToSpaceNd.cc b/runtime/contrib/pure_arm_compute/src/internal/op/BatchToSpaceNd.cc
new file mode 100644
index 000000000..0768039d0
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/BatchToSpaceNd.cc
@@ -0,0 +1,63 @@
+/*Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "internal/op/BatchToSpaceNd.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace BatchToSpaceNd
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace BatchToSpaceNd
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace BatchToSpaceNd
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 2 && outputCount == 1);
+
+  output_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> Input Tensor Index
+  //  1 -> Block size Index
+  input_index = inputs[0];
+  block_size_index = inputs[1];
+}
+
+} // namespace BatchToSpaceNd
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/BatchToSpaceNd.h b/runtime/contrib/pure_arm_compute/src/internal/op/BatchToSpaceNd.h
new file mode 100644
index 000000000..a514cb44c
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/BatchToSpaceNd.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __INTERNAL_OP_BATCHTOSPACE_ND_H__
+#define __INTERNAL_OP_BATCHTOSPACE_ND_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace BatchToSpaceNd
+{
+
+struct Param
+{
+  int32_t output_index;
+
+  int32_t input_index;
+  int32_t block_size_index;
+
+  Param() = default;
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+} // namespace BatchToSpaceNd
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace BatchToSpaceNd
+{
+class Node final : public op::Node
+{
+public:
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  virtual ~Node() = default;
+
+public:
+  const Param &param(void) const { return _param; }
+
+public:
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace BatchToSpaceNd
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_BATCHTOSPACE_Nd_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Cast.cc b/runtime/contrib/pure_arm_compute/src/internal/op/Cast.cc
new file mode 100644
index 000000000..13f58f137
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Cast.cc
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/Cast.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Cast
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Cast
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Cast
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 1 && outputCount == 1);
+
+  output_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //  0 -> input Tensor Index
+  input_index = inputs[0];
+}
+
+} // namespace Cast
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Cast.h b/runtime/contrib/pure_arm_compute/src/internal/op/Cast.h
new file mode 100644
index 000000000..8af741a16
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Cast.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Cast.h
+ * @brief This file contains accept function and params for Cast operation
+ * @ingroup COM_AI_RUNTIME
+ */
+
+#ifndef __INTERNAL_OP_CAST_H__
+#define __INTERNAL_OP_CAST_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Cast
+{
+
+/**
+ * @brief Struct of Cast operation's param
+ */
+struct Param
+{
+  int32_t output_index; /**< Output index */
+
+  int32_t input_index; /**< Input index */
+
+  /**
+   * @brief Construct a new Param object for Cast as default
+   */
+  Param() = default;
+
+  /**
+   * @brief Construct a new Param object for Cast with params
+   * @param [in] inputCount The number of input
+   * @param [in] inputs Array containing inputs
+   * @param [in] outputCount The number of output
+   * @param [in] outputs Array containing outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to define operation node for Cast
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Node object for Cast with param
+   * @param [in] param Parameters for Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destroy the Node object for Cast
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief Get parameters for Cast
+   * @return Parameters of Cast
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Function for accepting node for Cast
+   * @param [in] v Node visitor for invoking visit function of Cast
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace Cast
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_Cast_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Concat.cc b/runtime/contrib/pure_arm_compute/src/internal/op/Concat.cc
new file mode 100644
index 000000000..ee1730051
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Concat.cc
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/Concat.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Concat
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Concat
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Concat
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // When there are N + 1 inputs, each input should be interpreted as follows:
+  //
+  //  [0, N) -> Input tensors
+  //  N -> Axis
+  axis_index = inputs[inputCount - 1];
+
+  for (uint32_t n = 0; n < inputCount - 1; ++n)
+  {
+    ifm_indexes.emplace_back(inputs[n]);
+  }
+}
+
+} // namespace Concat
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Concat.h b/runtime/contrib/pure_arm_compute/src/internal/op/Concat.h
new file mode 100644
index 000000000..207f964fb
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Concat.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Concat.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief This file defines Concat node
+ */
+
+#ifndef __INTERNAL_OP_CONCAT_H__
+#define __INTERNAL_OP_CONCAT_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+#include <vector>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Concat
+{
+
+/**
+ * @brief Struct to manipulate parameter for Concat operation
+ */
+struct Param
+{
+  int32_t ofm_index; //!< index for output
+
+  std::vector<int32_t> ifm_indexes; //!< index for input
+  int32_t axis_index;               //!< index for axis
+
+  /**
+   * @brief Default Constructor
+   */
+  Param() = default;
+  /**
+   * @brief Construct a new Param object
+   * @param[in] inputCount the number of inputs
+   * @param[in] inputs pointer for input data
+   * @param[in] outputCount the number of outputs
+   * @param[in] outputs pointer for input data
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to define Concat Operation
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Concat Node object
+   * @param param Parameter for Concat Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Default Destructor
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief Get parameter
+   * @return Param reference
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Accept a NodeVisitor so that it can visit this node
+   * @param [in] v Visitor
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param; //!< parameter for Concat node
+};
+
+} // namespace Concat
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_CONCAT_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Conv2D.cc b/runtime/contrib/pure_arm_compute/src/internal/op/Conv2D.cc
new file mode 100644
index 000000000..a24d14632
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Conv2D.cc
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/Conv2D.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Conv2D
+{
+namespace Explicit
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Explicit
+
+namespace Implicit
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Implicit
+} // namespace Conv2D
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Conv2D
+{
+namespace Explicit
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 10 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //
+  //  0 -> IFM Tensor Index
+  //  1 -> Kernel Tensor Index
+  //  2 -> Bias Tensor Index
+  //  3 -> Padding_left index
+  //  4 -> Padding_right index
+  //  5 -> Padding_top index
+  //  6 -> Padding_bottom index
+  //  7 -> Stride (width) Index
+  //  8 -> Stride (height) INdex
+  //  9 -> Activation Index
+  ifm_index = inputs[0];
+  ker_index = inputs[1];
+  bias_index = inputs[2];
+  padding_left_index = inputs[3];
+  padding_right_index = inputs[4];
+  padding_top_index = inputs[5];
+  padding_bottom_index = inputs[6];
+  hstride_index = inputs[7];
+  vstride_index = inputs[8];
+  activation_index = inputs[9];
+}
+
+} // namespace Explicit
+
+namespace Implicit
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 7 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //
+  //  0 -> IFM Tensor Index
+  //  1 -> Kernel Tensor Index
+  //  2 -> Bias Tensor Index
+  //  3 -> Padding Code (ANEURALNETWORKS_PADDING_SAME or ANEURALNETWORKS_PADDING_VALID) Index
+  //  4 -> Stride (width) Index
+  //  5 -> Stride (height) INdex
+  //  6 -> Activation Index
+  ifm_index = inputs[0];
+  ker_index = inputs[1];
+  bias_index = inputs[2];
+  padding_index = inputs[3];
+  hstride_index = inputs[4];
+  vstride_index = inputs[5];
+  activation_index = inputs[6];
+}
+
+} // namespace Implicit
+} // namespace Conv2D
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Conv2D.h b/runtime/contrib/pure_arm_compute/src/internal/op/Conv2D.h
new file mode 100644
index 000000000..de46fbb9c
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Conv2D.h
@@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Conv2D.h
+ * @brief This file contains accept function and params for Conv2D operation
+ * @ingroup COM_AI_RUNTIME
+ */
+
+#ifndef __INTERNAL_OP_CONV_2D_H__
+#define __INTERNAL_OP_CONV_2D_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Conv2D
+{
+namespace Explicit
+{
+
+/**
+ * @brief Struct of Conv2D(explicit) operation's param
+ */
+struct Param
+{
+  int32_t ofm_index; /**< Output format index */
+
+  int32_t ifm_index;  /**< Input format index */
+  int32_t ker_index;  /**< Kernel index */
+  int32_t bias_index; /**< Bias index */
+
+  int32_t hstride_index; /**< Horizontal stride index */
+  int32_t vstride_index; /**< Vertical stride index */
+
+  int32_t padding_left_index;   /**< Left padding index */
+  int32_t padding_right_index;  /**< Right padding index */
+  int32_t padding_top_index;    /**< Top padding index */
+  int32_t padding_bottom_index; /**< Bottomd padding index */
+
+  int32_t activation_index; /**< Activation index */
+
+  /**
+   * @brief Construct a new Param object for Conv2D(explicit) as default
+   */
+  Param() = default;
+
+  /**
+   * @brief Construct a new Param object for Conv2D(explicit) with params
+   * @param [in] inputCount The number of input
+   * @param [in] inputs Array containing inputs
+   * @param [in] outputCount The number of output
+   * @param [in] outputs Array containing outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to define operation node for Conv2D(explicit)
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Node object for conv2D(explicit) with param
+   * @param [in] param Parameters for Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destroy the Node object for conv2D(explicit)
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief Get parameters for conv2D(explicit)
+   * @return Parameters of conv2D(explicit)
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Function for accepting node for conv2D(explicit)
+   * @param [in] v Node visitor for invoking visit function of conv2D(explicit)
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace Explicit
+
+namespace Implicit
+{
+
+/**
+ * @brief Struct of Conv2D(implicit) operation's param
+ */
+struct Param
+{
+  int32_t ofm_index; /**< Output format index */
+
+  int32_t ifm_index;  /**< Input format index */
+  int32_t ker_index;  /**< Kernel index */
+  int32_t bias_index; /**< Bias index */
+
+  int32_t hstride_index; /**< Horizontal stride index */
+  int32_t vstride_index; /**< Vertical stride index */
+
+  int32_t padding_index;    /**< Padding index */
+  int32_t activation_index; /**< Activation index */
+
+  /**
+   * @brief Construct a new Param object for Conv2D(implicit) as default
+   */
+  Param() = default;
+
+  /**
+   * @brief Construct a new Param object for Conv2D(implicit) with params
+   * @param [in] inputCount The number of input
+   * @param [in] inputs Array containing inputs
+   * @param [in] outputCount The number of output
+   * @param [in] outputs Array containing outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to define operation node for Conv2D(implicit)
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Node object for conv2D(implicit) with param
+   * @param [in] param Parameters for Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destroy the Node object for conv2D(implicit)
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief Get parameters for conv2D(implicit)
+   * @return Parameters of conv2D(implicit)
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Function for accepting node for conv2D(implicit)
+   * @param [in] v Node visitor for invoking visit function of conv2D(implicit)
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace Implicit
+} // namespace Conv2D
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_CONV_2D_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/DepthToSpace.cc b/runtime/contrib/pure_arm_compute/src/internal/op/DepthToSpace.cc
new file mode 100644
index 000000000..db164a148
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/DepthToSpace.cc
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/DepthToSpace.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace DepthToSpace
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace DepthToSpace
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace DepthToSpace
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 2 && outputCount == 1);
+
+  output_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> Input Tensor Index
+  //  1 -> Block size Index
+  input_index = inputs[0];
+  block_size_index = inputs[1];
+}
+
+} // namespace DepthToSpace
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/DepthToSpace.h b/runtime/contrib/pure_arm_compute/src/internal/op/DepthToSpace.h
new file mode 100644
index 000000000..dd4c5c914
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/DepthToSpace.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __INTERNAL_OP_DEPTHTOSPACE_H__
+#define __INTERNAL_OP_DEPTHTOSPACE_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace DepthToSpace
+{
+
+struct Param
+{
+  int32_t output_index;
+
+  int32_t input_index;
+  int32_t block_size_index;
+
+  Param() = default;
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+class Node final : public op::Node
+{
+public:
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  virtual ~Node() = default;
+
+public:
+  const Param &param(void) const { return _param; }
+
+public:
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace DepthToSpace
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_DEPTHTOSPACE_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/DepthwiseConv2D.cc b/runtime/contrib/pure_arm_compute/src/internal/op/DepthwiseConv2D.cc
new file mode 100644
index 000000000..f4d1ca3c5
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/DepthwiseConv2D.cc
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/DepthwiseConv2D.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace DepthwiseConv2D
+{
+namespace Explicit
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Explicit
+
+namespace Implicit
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Implicit
+} // namespace DepthwiseConv2D
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace DepthwiseConv2D
+{
+namespace Explicit
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 11 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> IFM Tensor Index
+  //  1 -> Kernel Tensor Index
+  //  2 -> Bias Tensor Index
+  //  3 -> Padding_left index
+  //  4 -> Padding_right index
+  //  5 -> Padding_top index
+  //  6 -> Padding_bottom index
+  //  7 -> Stride (width) Index
+  //  8 -> Stride (height) INdex
+  //  9 -> Depthwise Multiplier
+  //  10 -> Activation Index
+  ifm_index = inputs[0];
+  ker_index = inputs[1];
+  bias_index = inputs[2];
+  padding_left_index = inputs[3];
+  padding_right_index = inputs[4];
+  padding_top_index = inputs[5];
+  padding_bottom_index = inputs[6];
+  hstride_index = inputs[7];
+  vstride_index = inputs[8];
+  multiplier_index = inputs[9];
+  activation_index = inputs[10];
+}
+
+} // namespace Explicit
+
+namespace Implicit
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 8 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> IFM Tensor Index
+  //  1 -> Kernel Tensor Index
+  //  2 -> Bias Tensor Index
+  //  3 -> Padding Code (ANEURALNETWORKS_PADDING_SAME or ANEURALNETWORKS_PADDING_VALID) Index
+  //  4 -> Stride (width) Index
+  //  5 -> Stride (height) INdex
+  //  6 -> Depthwise Multiplier
+  //  7 -> Activation Index
+  ifm_index = inputs[0];
+  ker_index = inputs[1];
+  bias_index = inputs[2];
+  padding_index = inputs[3];
+  hstride_index = inputs[4];
+  vstride_index = inputs[5];
+  multiplier_index = inputs[6];
+  activation_index = inputs[7];
+}
+
+} // namespace Implicit
+} // namespace DepthwiseConv2D
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/DepthwiseConv2D.h b/runtime/contrib/pure_arm_compute/src/internal/op/DepthwiseConv2D.h
new file mode 100644
index 000000000..01a9e48be
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/DepthwiseConv2D.h
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    DepthwiseConv2D.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines internal::tflite::op::DepthwiseConv2D Param structs
+ *          and internal::tflite::op::DepthwiseConv2D Node classes
+ */
+#ifndef __INTERNAL_OP_DEPTHWISE_CONV_2D_H__
+#define __INTERNAL_OP_DEPTHWISE_CONV_2D_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace DepthwiseConv2D
+{
+namespace Explicit
+{
+
+/**
+ * @brief Struct to have indexes for explicit padding DepthwiseConv2D operation parameter
+ */
+struct Param
+{
+  int32_t ofm_index; /**< Index of output feature map */
+
+  int32_t ifm_index;  /**< Index of input feature map */
+  int32_t ker_index;  /**< Index of kernel */
+  int32_t bias_index; /**< Index of bias */
+
+  int32_t hstride_index; /**< Index of horizontal stride */
+  int32_t vstride_index; /**< Index of vertical stride */
+
+  int32_t padding_left_index;   /**< Index of padding left */
+  int32_t padding_right_index;  /**< Index of padding right */
+  int32_t padding_top_index;    /**< Index of padding top */
+  int32_t padding_bottom_index; /**< Index of padding bottom */
+
+  int32_t multiplier_index; /**< Index of multipler */
+  int32_t activation_index; /**< Index of activation */
+  /**
+   * @brief Construct as default
+   */
+  Param() = default;
+  /**
+   * @brief Construct a new Param object with params
+   * @param[in] inputCount  Count of inputs
+   * @param[in] inputs      Pointer of inputs
+   * @param[in] outputCount Count of outputs
+   * @param[in] outputs     Pointer of outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to represent an explicit padding DepthwiseConv2D operation of data structure
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Node object with param
+   * @param[in] param Param object that makes up a Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destruct as default
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief  Get a reference of Param object
+   * @return Reference of Param object
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Visit this Node by NodeVisitor
+   * @param[in] v Visitor
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace Explicit
+
+/**
+ * @brief Struct to have indexes for implicit padding DepthwiseConv2D operation parameter
+ */
+namespace Implicit
+{
+
+struct Param
+{
+  int32_t ofm_index; /**< Index of output feature map */
+
+  int32_t ifm_index;  /**< Index of input feature map */
+  int32_t ker_index;  /**< Index of kernel */
+  int32_t bias_index; /**< Index of bias */
+
+  int32_t hstride_index; /**< Index of horizontal stride */
+  int32_t vstride_index; /**< Index of vertical stride */
+
+  int32_t padding_index;    /**< Index of padding */
+  int32_t multiplier_index; /**< Index of multipler */
+  int32_t activation_index; /**< Index of activation */
+  /**
+   * @brief Construct as default
+   */
+  Param() = default;
+  /**
+   * @brief Construct a new Param object with params
+   * @param[in] inputCount  Count of inputs
+   * @param[in] inputs      Pointer of inputs
+   * @param[in] outputCount Count of outputs
+   * @param[in] outputs     Pointer of outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to represent an implicit padding DepthwiseConv2D operation of data structure
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Node object with param
+   * @param[in] param Param object that makes up a Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destruct as default
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief  Get a reference of Param object
+   * @return Reference of Param object
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Visit this Node by NodeVisitor
+   * @param[in] v Visitor
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace Implicit
+} // namespace DepthwiseConv2D
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_CONV_2D_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Dequantize.cc b/runtime/contrib/pure_arm_compute/src/internal/op/Dequantize.cc
new file mode 100644
index 000000000..7062463a2
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Dequantize.cc
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/Dequantize.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Dequantize
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Dequantize
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Dequantize
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 1 && outputCount == 1);
+
+  output_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //  0 -> input Tensor Index
+  input_index = inputs[0];
+}
+
+} // namespace Dequantize
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Dequantize.h b/runtime/contrib/pure_arm_compute/src/internal/op/Dequantize.h
new file mode 100644
index 000000000..f19898e9e
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Dequantize.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    Dequantize.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines internal::tflite::op::Dequantize::Param struct
+ *          and internal::tflite::op::Dequantize::Node class
+ */
+#ifndef __INTERNAL_OP_DEQUANTIZE_H__
+#define __INTERNAL_OP_DEQUANTIZE_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Dequantize
+{
+
+/**
+ * @brief Struct to have indexes for Dequantize operation parameter
+ */
+struct Param
+{
+  int32_t output_index; /**< Index of output feature map */
+
+  int32_t input_index; /**< Index of input feature map */
+  /**
+   * @brief Construct as default
+   */
+  Param() = default;
+  /**
+   * @brief Construct a new Param object with params
+   * @param[in] inputCount  Count of inputs
+   * @param[in] inputs      Pointer of inputs
+   * @param[in] outputCount Count of outputs
+   * @param[in] outputs     Pointer of outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to represent an Dequantize operation of data structure
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Node object with param
+   * @param[in] param Param object that makes up a Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destruct as default
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief  Get a reference of Param object
+   * @return Reference of Param object
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Visit this Node by NodeVisitor
+   * @param[in] v Visitor
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace Dequantize
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_DEQUANTIZE_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Div.cc b/runtime/contrib/pure_arm_compute/src/internal/op/Div.cc
new file mode 100644
index 000000000..649407eab
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Div.cc
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/Div.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Div
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Div
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Div
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 3 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> LHS Tensor Index
+  //  1 -> RHS Tensor Index
+  //  2 -> Activation Index
+  lhs_index = inputs[0];
+  rhs_index = inputs[1];
+  activation_index = inputs[2];
+}
+
+} // namespace Div
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Div.h b/runtime/contrib/pure_arm_compute/src/internal/op/Div.h
new file mode 100644
index 000000000..d5fc09d19
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Div.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    Div.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines internal::tflite::op::Div::Param struct
+ *          and internal::tflite::op::Div::Node class
+ */
+#ifndef __INTERNAL_OP_DIV_H__
+#define __INTERNAL_OP_DIV_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Div
+{
+
+/**
+ * @brief Struct to have indexes for operation parameter
+ */
+struct Param
+{
+  int32_t ofm_index; /**< Index of output feature map */
+
+  int32_t lhs_index;        /**< Index of lhs */
+  int32_t rhs_index;        /**< Index of rhs */
+  int32_t activation_index; /**< Index of activation */
+  /**
+   * @brief Construct as default
+   */
+  Param() = default;
+  /**
+   * @brief Construct a new Param object with params
+   * @param[in] inputCount  Count of inputs
+   * @param[in] inputs      Pointer of inputs
+   * @param[in] outputCount Count of outputs
+   * @param[in] outputs     Pointer of outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to represent an operation of data structure
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Node object with param
+   * @param[in] param Param object that makes up a Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destruct as default
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief  Get a reference of Param object
+   * @return Reference of Param object
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Visit this Node by NodeVisitor
+   * @param[in] v Visitor
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace Div
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_DIV_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/EmbeddingLookup.cc b/runtime/contrib/pure_arm_compute/src/internal/op/EmbeddingLookup.cc
new file mode 100644
index 000000000..a6eda3473
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/EmbeddingLookup.cc
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/EmbeddingLookup.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace EmbeddingLookup
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace EmbeddingLookup
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace EmbeddingLookup
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 2 && outputCount == 1);
+
+  output_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> Lookups Index
+  //  1 -> Values Index
+  lookups_index = inputs[0];
+  values_index = inputs[1];
+}
+
+} // namespace EmbeddingLookup
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/EmbeddingLookup.h b/runtime/contrib/pure_arm_compute/src/internal/op/EmbeddingLookup.h
new file mode 100644
index 000000000..17e8485f7
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/EmbeddingLookup.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file EmbeddingLookup.h
+ * @brief This file contains accept function and params for EmbeddingLookup operation
+ * @ingroup COM_AI_RUNTIME
+ */
+
+#ifndef __INTERNAL_OP_EMBEDDING_LOOKUP_H__
+#define __INTERNAL_OP_EMBEDDING_LOOKUP_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace EmbeddingLookup
+{
+
+/**
+ * @brief Struct of EmbeddingLookup operation's param
+ */
+struct Param
+{
+  int32_t output_index; /**< Output index */
+
+  int32_t lookups_index; /**< Lookups index */
+  int32_t values_index;  /**< Values index */
+
+  /**
+   * @brief Construct a new Param object for EmbeddingLookup as default
+   */
+  Param() = default;
+
+  /**
+   * @brief Construct a new Param object for EmbeddingLookup with params
+   * @param [in] inputCount The number of input
+   * @param [in] inputs Array containing inputs
+   * @param [in] outputCount The number of output
+   * @param [in] outputs Array containing outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to define operation node for EmbeddingLookup
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Node object for EmbeddingLookup with param
+   * @param [in] param Parameters for Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destroy the Node object for EmbeddingLookup
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief Get parameters for EmbeddingLookup
+   * @return Parameters of EmbeddingLookup
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Function for accepting node for EmbeddingLookup
+   * @param [in] v Node visitor for invoking visit function of EmbeddingLookup
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace EmbeddingLookup
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_EMBEDDING_LOOKUP_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Equal.cc b/runtime/contrib/pure_arm_compute/src/internal/op/Equal.cc
new file mode 100644
index 000000000..b9cccc6a9
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Equal.cc
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/Equal.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Equal
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Equal
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Equal
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 2 && outputCount == 1);
+
+  output_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> input1 Tensor Index
+  //  1 -> input2 Tensor Index
+  input1_index = inputs[0];
+  input2_index = inputs[1];
+}
+
+} // namespace Equal
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Equal.h b/runtime/contrib/pure_arm_compute/src/internal/op/Equal.h
new file mode 100644
index 000000000..78b9f846f
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Equal.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __INTERNAL_OP_EQUAL_H__
+#define __INTERNAL_OP_EQUAL_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Equal
+{
+
+struct Param
+{
+  int32_t output_index;
+
+  int32_t input1_index;
+  int32_t input2_index;
+
+  Param() = default;
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+} // namespace Equal
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Equal
+{
+class Node final : public op::Node
+{
+public:
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  virtual ~Node() = default;
+
+public:
+  const Param &param(void) const { return _param; }
+
+public:
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace Equal
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_EQUAL_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Exp.cc b/runtime/contrib/pure_arm_compute/src/internal/op/Exp.cc
new file mode 100644
index 000000000..6f1aa8f42
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Exp.cc
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/Exp.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Exp
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Exp
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Exp
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 1 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> Input Tensor Index
+  ifm_index = inputs[0];
+}
+
+} // namespace Exp
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Exp.h b/runtime/contrib/pure_arm_compute/src/internal/op/Exp.h
new file mode 100644
index 000000000..ac7f244b7
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Exp.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __INTERNAL_OP_EXP_H__
+#define __INTERNAL_OP_EXP_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Exp
+{
+
+struct Param
+{
+  int32_t ofm_index;
+
+  int32_t ifm_index;
+
+  Param() = default;
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+class Node final : public op::Node
+{
+public:
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  virtual ~Node() = default;
+
+public:
+  const Param &param(void) const { return _param; }
+
+public:
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace Exp
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_EXP_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Floor.cc b/runtime/contrib/pure_arm_compute/src/internal/op/Floor.cc
new file mode 100644
index 000000000..c04f0c8ab
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Floor.cc
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/Floor.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Floor
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Floor
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Floor
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 1 && outputCount == 1);
+
+  output_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //  0 -> input Tensor Index
+  input_index = inputs[0];
+}
+
+} // namespace Floor
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Floor.h b/runtime/contrib/pure_arm_compute/src/internal/op/Floor.h
new file mode 100644
index 000000000..5264ec10c
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Floor.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Floor.h
+ * @brief This file contains accept function and params for Floor operation
+ * @ingroup COM_AI_RUNTIME
+ */
+
+#ifndef __INTERNAL_OP_FLOOR_H__
+#define __INTERNAL_OP_FLOOR_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Floor
+{
+
+/**
+ * @brief Struct of Floor operation's param
+ */
+struct Param
+{
+  int32_t output_index; /**< Output index */
+
+  int32_t input_index; /**< Input index */
+
+  /**
+   * @brief Construct a new Param object for Floor as default
+   */
+  Param() = default;
+
+  /**
+   * @brief Construct a new Param object for Floor with params
+   * @param [in] inputCount The number of input
+   * @param [in] inputs Array containing inputs
+   * @param [in] outputCount The number of output
+   * @param [in] outputs Array containing outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to define operation node for Floor
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Node object for Floor with param
+   * @param [in] param Parameters for Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destroy the Node object for Floor
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief Get parameters for Floor
+   * @return Parameters of Floor
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Function for accepting node for Floor
+   * @param [in] v Node visitor for invoking visit function of Floor
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace Floor
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_FLOOR_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/FullyConnected.cc b/runtime/contrib/pure_arm_compute/src/internal/op/FullyConnected.cc
new file mode 100644
index 000000000..491fa5918
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/FullyConnected.cc
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/FullyConnected.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace FullyConnected
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace FullyConnected
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace FullyConnected
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 4 && outputCount == 1);
+
+  output_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> A tensor, specifying the input.
+  //  1 -> A 2-D tensor, specifying the weights
+  //  2 -> A 1-D tensor, specifying the bias
+  //  3 -> An INT32 value, and has to be one of the FuseCode values
+  input_index = inputs[0];
+  weight_index = inputs[1];
+  bias_index = inputs[2];
+  activation_index = inputs[3];
+}
+
+} // namespace FullyConnected
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/FullyConnected.h b/runtime/contrib/pure_arm_compute/src/internal/op/FullyConnected.h
new file mode 100644
index 000000000..434308435
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/FullyConnected.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file FullyConnected.h
+ * @brief This file contains accept function and params for FullyConnected operation
+ * @ingroup COM_AI_RUNTIME
+ */
+
+#ifndef __INTERNAL_OP_FULLY_CONNTECTED_H__
+#define __INTERNAL_OP_FULLY_CONNTECTED_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace FullyConnected
+{
+
+/**
+ * @brief Struct of FullyConnected operation's param
+ */
+struct Param
+{
+  int32_t output_index; /**< Output index */
+
+  int32_t input_index;      /**< Input index */
+  int32_t weight_index;     /**< Weight index */
+  int32_t bias_index;       /**< Bias index */
+  int32_t activation_index; /**< Activation index */
+
+  /**
+   * @brief Construct a new Param object for FullyConnected as default
+   */
+  Param() = default;
+
+  /**
+   * @brief Construct a new Param object for FullyConnected with params
+   * @param [in] inputCount The number of input
+   * @param [in] inputs Array containing inputs
+   * @param [in] outputCount The number of output
+   * @param [in] outputs Array containing outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to define operation node for FullyConnected
+ */
+class Node final : public op::Node
+{
+  /**
+   * @brief Construct a new Node object for FullyConnected with param
+   * @param [in] param Parameters for Node
+   */
+public:
+  /**
+   * @brief Destroy the Node object for FullyConnected
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destroy the Node object for FullyConnected
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief Parameter Get parameters for FullyConnected
+   * @return _param Parameters of FullyConnected
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Function for accepting node for FullyConnected
+   * @param [in] v Node visitor for invoking visit function of FullyConnected
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace FullyConnected
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_FULLY_CONNTECTED_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Gather.cc b/runtime/contrib/pure_arm_compute/src/internal/op/Gather.cc
new file mode 100644
index 000000000..bc517d28c
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Gather.cc
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/Gather.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Gather
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Gather
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Gather
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 3 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> input Tensor Index
+  //  1 -> indices Tensor Index
+  //  2 -> axis Index
+  ifm_index = inputs[0];
+  indices_index = inputs[1];
+  axis_index = inputs[2];
+}
+
+} // namespace Gather
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Gather.h b/runtime/contrib/pure_arm_compute/src/internal/op/Gather.h
new file mode 100644
index 000000000..d40794f99
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Gather.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Gather.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief This file defines Gather operation
+ */
+
+#ifndef __INTERNAL_OP_GATHER_H__
+#define __INTERNAL_OP_GATHER_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Gather
+{
+
+/**
+ * @brief Struct to manipulate parameter for Gather operation
+ */
+struct Param
+{
+  int32_t ofm_index; //!< index for output feature map
+
+  int32_t ifm_index;     //!< index for ifm tensor
+  int32_t indices_index; //!< index for indices tensor
+  int32_t axis_index;    //!< index for axis
+
+  /**
+   * @brief Default Constructor
+   */
+  Param() = default;
+  /**
+   * @brief Construct a new Param object
+   * @param[in] inputCount the number of inputs
+   * @param[in] inputs pointer for input data
+   * @param[in] outputCount the number of outputs
+   * @param[in] outputs pointer for input data
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to define Gather Operation
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Tanh Node object
+   * @param param Parameter for Tanh Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Default Destructor
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief Get parameter
+   * @return Param reference
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Accept a NodeVisitor so that it can visit this node
+   * @param [in] v Visitor
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param; //!< parameter for Gather node
+};
+
+} // namespace Gather
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_GATHER_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/HashtableLookup.cc b/runtime/contrib/pure_arm_compute/src/internal/op/HashtableLookup.cc
new file mode 100644
index 000000000..7e04ecf82
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/HashtableLookup.cc
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/HashtableLookup.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace HashtableLookup
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace HashtableLookup
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace HashtableLookup
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 3 && outputCount == 2);
+
+  output_index = outputs[0];
+  hits_index = outputs[1];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> Lookups Index
+  //  1 -> Keys Index
+  //  2 -> Values Index
+  lookups_index = inputs[0];
+  keys_index = inputs[1];
+  values_index = inputs[2];
+}
+
+} // namespace HashtableLookup
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/HashtableLookup.h b/runtime/contrib/pure_arm_compute/src/internal/op/HashtableLookup.h
new file mode 100644
index 000000000..a5b43d1c7
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/HashtableLookup.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    HashtableLookup.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines internal::tflite::op::HashtableLookup::Param struct
+ *          and internal::tflite::op::HashtableLookup::Node class
+ */
+#ifndef __INTERNAL_OP_HASHTABLE_LOOKUP_H__
+#define __INTERNAL_OP_HASHTABLE_LOOKUP_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace HashtableLookup
+{
+
+/**
+ * @brief Struct to have indexes for operation parameter
+ */
+struct Param
+{
+  int32_t output_index; /**< Index of output feature map */
+  int32_t hits_index;   /**< Index of hits */
+
+  int32_t lookups_index; /**< Index of lookups */
+  int32_t values_index;  /**< Index of values */
+  int32_t keys_index;    /**< Index of keys */
+  /**
+   * @brief Construct as default
+   */
+  Param() = default;
+  /**
+   * @brief Construct a new Param object with params
+   * @param[in] inputCount  Count of inputs
+   * @param[in] inputs      Pointer of inputs
+   * @param[in] outputCount Count of outputs
+   * @param[in] outputs     Pointer of outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to represent an operation of data structure
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Node object with param
+   * @param[in] param Param object that makes up a Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destruct as default
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief  Get a reference of Param object
+   * @return Reference of Param object
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Visit this Node by NodeVisitor
+   * @param[in] v Visitor
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace HashtableLookup
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_HASHTABLE_LOOKUP_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/L2Normalization.cc b/runtime/contrib/pure_arm_compute/src/internal/op/L2Normalization.cc
new file mode 100644
index 000000000..44a6ee63d
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/L2Normalization.cc
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/L2Normalization.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace L2Normalization
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace L2Normalization
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace L2Normalization
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 1 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  ifm_index = inputs[0];
+}
+
+} // namespace L2Normalization
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/L2Normalization.h b/runtime/contrib/pure_arm_compute/src/internal/op/L2Normalization.h
new file mode 100644
index 000000000..2e94fac11
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/L2Normalization.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    L2Normalization.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines internal::tflite::op::L2Normalization::Param struct
+ *          and internal::tflite::op::L2Normalization::Node class
+ */
+#ifndef __INTERNAL_OP_L2_NORMALIZATION_H__
+#define __INTERNAL_OP_L2_NORMALIZATION_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace L2Normalization
+{
+
+/**
+ * @brief Struct to have indexes for L2Normalization operation parameter
+ */
+struct Param
+{
+  int32_t ofm_index; /**< Index of output feature map */
+
+  int32_t ifm_index; /**< Index of input feature map */
+  /**
+   * @brief Construct as default
+   */
+  Param() = default;
+  /**
+   * @brief Construct a new Param object with params
+   * @param[in] inputCount  Count of inputs
+   * @param[in] inputs      Pointer of inputs
+   * @param[in] outputCount Count of outputs
+   * @param[in] outputs     Pointer of outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to represent an L2Normalization operation of data structure
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Node object with param
+   * @param[in] param Param object that makes up a Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destruct as default
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief  Get a reference of Param object
+   * @return Reference of Param object
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Visit this Node by NodeVisitor
+   * @param[in] v Visitor
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace L2Normalization
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_L2_NORMALIZATION_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/L2Pool2D.cc b/runtime/contrib/pure_arm_compute/src/internal/op/L2Pool2D.cc
new file mode 100644
index 000000000..64041ab49
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/L2Pool2D.cc
@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/L2Pool2D.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace L2Pool2D
+{
+namespace Explicit
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Explicit
+
+namespace Implicit
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Implicit
+} // namespace L2Pool2D
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace L2Pool2D
+{
+namespace Explicit
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 10 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> IFM Tensor Index
+  //  1 -> Padding_left index
+  //  2 -> Padding_right index
+  //  3 -> Padding_top index
+  //  4 -> Padding_bottom index
+  //  5 -> Horizontal (over width) Stride Index
+  //  6 -> Vertial (over height) Stride Index
+  //  7 -> Filter Width Index
+  //  8 -> Filter Height Index
+  //  9 -> FuseCode (activation) Index
+  ifm_index = inputs[0];
+  padding_left_index = inputs[1];
+  padding_right_index = inputs[2];
+  padding_top_index = inputs[3];
+  padding_bottom_index = inputs[4];
+  hstride_index = inputs[5];
+  vstride_index = inputs[6];
+  kw_index = inputs[7];
+  kh_index = inputs[8];
+  activation_index = inputs[9];
+}
+
+} // namespace Explicit
+
+namespace Implicit
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 7 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> IFM Tensor Index
+  //  1 -> Padding Code (ANEURALNETWORKS_PADDING_SAME or ANEURALNETWORKS_PADDING_VALID) Index
+  //  2 -> Horizontal (over width) Stride Index
+  //  3 -> Vertial (over height) Stride Index
+  //  4 -> Filter Width Index
+  //  5 -> Filter Height Index
+  //  6 -> FuseCode (activation) Index
+  ifm_index = inputs[0];
+  padding_index = inputs[1];
+  hstride_index = inputs[2];
+  vstride_index = inputs[3];
+  kw_index = inputs[4];
+  kh_index = inputs[5];
+  activation_index = inputs[6];
+}
+
+} // namespace Implicit
+} // namespace L2Pool2D
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/L2Pool2D.h b/runtime/contrib/pure_arm_compute/src/internal/op/L2Pool2D.h
new file mode 100644
index 000000000..facb223c7
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/L2Pool2D.h
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    L2Pool2D.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines internal::tflite::op::L2Pool2D Param structs
+ *          and internal::tflite::op::L2Pool2D Node classes
+ */
+#ifndef __INTERNAL_OP_L2_POOL_2D_H__
+#define __INTERNAL_OP_L2_POOL_2D_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace L2Pool2D
+{
+namespace Explicit
+{
+
+/**
+ * @brief Struct to have indexes for operation parameter
+ */
+struct Param
+{
+  int32_t ofm_index; /**< Index of output feature map */
+
+  int32_t ifm_index; /**< Index of input feature map */
+
+  int32_t kw_index; /**< Index of kernel width */
+  int32_t kh_index; /**< Index of kernel height */
+
+  int32_t hstride_index; /**< Index of horizontal stride */
+  int32_t vstride_index; /**< Index of vertical stride */
+
+  int32_t padding_left_index;   /**< Index of padding left */
+  int32_t padding_right_index;  /**< Index of padding right */
+  int32_t padding_top_index;    /**< Index of padding top */
+  int32_t padding_bottom_index; /**< Index of padding bottom */
+
+  int32_t activation_index; /**< Index of activation */
+  /**
+   * @brief Construct as default
+   */
+  Param() = default;
+  /**
+   * @brief Construct a new Param object with params
+   * @param[in] inputCount  Count of inputs
+   * @param[in] inputs      Pointer of inputs
+   * @param[in] outputCount Count of outputs
+   * @param[in] outputs     Pointer of outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to represent an operation of data structure
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Node object with param
+   * @param[in] param Param object that makes up a Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destruct as default
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief  Get a reference of Param object
+   * @return Reference of Param object
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Visit this Node by NodeVisitor
+   * @param[in] v Visitor
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace Explicit
+
+namespace Implicit
+{
+
+/**
+ * @brief Struct to have indexes for operation parameter
+ */
+struct Param
+{
+  int32_t ofm_index; /**< Index of output feature map */
+
+  int32_t ifm_index; /**< Index of input feature map */
+
+  int32_t kw_index; /**< Index of kernel width */
+  int32_t kh_index; /**< Index of kernel height */
+
+  int32_t hstride_index; /**< Index of horizontal stride */
+  int32_t vstride_index; /**< Index of vertical stride */
+
+  int32_t padding_index;    /**< Index of padding */
+  int32_t activation_index; /**< Index of activation */
+  /**
+   * @brief Construct as default
+   */
+  Param() = default;
+  /**
+   * @brief Construct a new Param object with params
+   * @param[in] inputCount  Count of inputs
+   * @param[in] inputs      Pointer of inputs
+   * @param[in] outputCount Count of outputs
+   * @param[in] outputs     Pointer of outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to represent an operation of data structure
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Node object with param
+   * @param[in] param Param object that makes up a Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destruct as default
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief  Get a reference of Param object
+   * @return Reference of Param object
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Visit this Node by NodeVisitor
+   * @param[in] v Visitor
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace Implicit
+} // namespace L2Pool2D
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_L2_POOL_2D_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/LocalResponseNormalization.cc b/runtime/contrib/pure_arm_compute/src/internal/op/LocalResponseNormalization.cc
new file mode 100644
index 000000000..b7419d923
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/LocalResponseNormalization.cc
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/LocalResponseNormalization.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace LocalResponseNormalization
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace LocalResponseNormalization
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace LocalResponseNormalization
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 5 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  ifm_index = inputs[0];
+  radius_index = inputs[1];
+  bias_index = inputs[2];
+  alpha_index = inputs[3];
+  beta_index = inputs[4];
+}
+
+} // namespace LocalResponseNormalization
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/LocalResponseNormalization.h b/runtime/contrib/pure_arm_compute/src/internal/op/LocalResponseNormalization.h
new file mode 100644
index 000000000..29e0699ad
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/LocalResponseNormalization.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __INTERNAL_OP_LOCAL_RESPONSE_NORMALIZATION_H__
+#define __INTERNAL_OP_LOCAL_RESPONSE_NORMALIZATION_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace LocalResponseNormalization
+{
+
+struct Param
+{
+  int32_t ofm_index;
+
+  int32_t ifm_index;
+  int32_t radius_index;
+  int32_t bias_index;
+  int32_t alpha_index;
+  int32_t beta_index;
+
+  Param() = default;
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+class Node final : public op::Node
+{
+public:
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  virtual ~Node() = default;
+
+public:
+  const Param &param(void) const { return _param; }
+
+public:
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace LocalResponseNormalization
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif //  __INTERNAL_OP_LOCAL_RESPONSE_NORMALIZATION_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/LogicalAnd.cc b/runtime/contrib/pure_arm_compute/src/internal/op/LogicalAnd.cc
new file mode 100644
index 000000000..5b7da4d3b
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/LogicalAnd.cc
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/LogicalAnd.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace LogicalAnd
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace LogicalAnd
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace LogicalAnd
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 2 && outputCount == 1);
+
+  output_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> input1 Tensor Index
+  //  1 -> input2 Tensor Index
+  input1_index = inputs[0];
+  input2_index = inputs[1];
+}
+
+} // namespace LogicalAnd
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/LogicalAnd.h b/runtime/contrib/pure_arm_compute/src/internal/op/LogicalAnd.h
new file mode 100644
index 000000000..2f53f756d
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/LogicalAnd.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __INTERNAL_OP_LOGICAL_AND_H__
+#define __INTERNAL_OP_LOGICAL_AND_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace LogicalAnd
+{
+
+struct Param
+{
+  int32_t output_index;
+
+  int32_t input1_index;
+  int32_t input2_index;
+
+  Param() = default;
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+} // namespace LogicalAnd
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace LogicalAnd
+{
+class Node final : public op::Node
+{
+public:
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  virtual ~Node() = default;
+
+public:
+  const Param &param(void) const { return _param; }
+
+public:
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace LogicalAnd
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_LOGICAL_AND_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/LogicalNot.cc b/runtime/contrib/pure_arm_compute/src/internal/op/LogicalNot.cc
new file mode 100644
index 000000000..4cb6a8e2a
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/LogicalNot.cc
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/LogicalNot.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace LogicalNot
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace LogicalNot
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace LogicalNot
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 1 && outputCount == 1);
+
+  output_index = outputs[0];
+
+  input_index = inputs[0];
+}
+
+} // namespace LogicalNot
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/LogicalNot.h b/runtime/contrib/pure_arm_compute/src/internal/op/LogicalNot.h
new file mode 100644
index 000000000..9593deafe
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/LogicalNot.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __INTERNAL_OP_LOGICAL_NOT_H__
+#define __INTERNAL_OP_LOGICAL_NOT_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace LogicalNot
+{
+
+struct Param
+{
+  int32_t output_index;
+
+  int32_t input_index;
+
+  Param() = default;
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+} // namespace LogicalNot
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace LogicalNot
+{
+class Node final : public op::Node
+{
+public:
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  virtual ~Node() = default;
+
+public:
+  const Param &param(void) const { return _param; }
+
+public:
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace LogicalNot
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_LOGICAL_NOT_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/LogicalOr.cc b/runtime/contrib/pure_arm_compute/src/internal/op/LogicalOr.cc
new file mode 100644
index 000000000..8295f6f0b
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/LogicalOr.cc
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/LogicalOr.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace LogicalOr
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace LogicalOr
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace LogicalOr
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 2 && outputCount == 1);
+
+  output_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> input1 Tensor Index
+  //  1 -> input2 Tensor Index
+  input1_index = inputs[0];
+  input2_index = inputs[1];
+}
+
+} // namespace LogicalOr
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/LogicalOr.h b/runtime/contrib/pure_arm_compute/src/internal/op/LogicalOr.h
new file mode 100644
index 000000000..6487fa720
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/LogicalOr.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __INTERNAL_OP_LOGICAL_OR_H__
+#define __INTERNAL_OP_LOGICAL_OR_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace LogicalOr
+{
+
+struct Param
+{
+  int32_t output_index;
+
+  int32_t input1_index;
+  int32_t input2_index;
+
+  Param() = default;
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+} // namespace LogicalOr
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace LogicalOr
+{
+class Node final : public op::Node
+{
+public:
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  virtual ~Node() = default;
+
+public:
+  const Param &param(void) const { return _param; }
+
+public:
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace LogicalOr
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_LOGICAL_OR_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Logistic.cc b/runtime/contrib/pure_arm_compute/src/internal/op/Logistic.cc
new file mode 100644
index 000000000..93ecd043c
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Logistic.cc
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/Logistic.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Logistic
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Logistic
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Logistic
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 1 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> Input Tensor Index
+  ifm_index = inputs[0];
+}
+
+} // namespace Logistic
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Logistic.h b/runtime/contrib/pure_arm_compute/src/internal/op/Logistic.h
new file mode 100644
index 000000000..a42fdc0d4
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Logistic.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    Logistic.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines internal::tflite::op::Logistic::Param struct
+ *          and internal::tflite::op::Logistic::Node class
+ */
+#ifndef __INTERNAL_OP_LOGISTIC_H__
+#define __INTERNAL_OP_LOGISTIC_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Logistic
+{
+
+/**
+ * @brief Struct to have indexes for operation parameter
+ */
+struct Param
+{
+  int32_t ofm_index; /**< Index of output feature map */
+
+  int32_t ifm_index; /**< Index of input feature map */
+  /**
+   * @brief Construct as default
+   */
+  Param() = default;
+  /**
+   * @brief Construct a new Param object with params
+   * @param[in] inputCount  Count of inputs
+   * @param[in] inputs      Pointer of inputs
+   * @param[in] outputCount Count of outputs
+   * @param[in] outputs     Pointer of outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to represent an operation of data structure
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Node object with param
+   * @param[in] param Param object that makes up a Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destruct as default
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief  Get a reference of Param object
+   * @return Reference of Param object
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Visit this Node by NodeVisitor
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace Logistic
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_LOGISTIC_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Lstm.cc b/runtime/contrib/pure_arm_compute/src/internal/op/Lstm.cc
new file mode 100644
index 000000000..3f5e9a490
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Lstm.cc
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/Lstm.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace LSTM
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace LSTM
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace LSTM
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 23 && outputCount == 4);
+
+  scratch_buffer_index = outputs[0];
+  output_state_out_index = outputs[1];
+  cell_state_out_index = outputs[2];
+  output_index = outputs[3];
+
+  input_index = inputs[0];
+  input_to_input_weights_index = inputs[1];
+  input_to_forget_weights_index = inputs[2];
+  input_to_cell_weights_index = inputs[3];
+  input_to_output_weights_index = inputs[4];
+  recurrent_to_input_weights_index = inputs[5];
+  recurrent_to_forget_weights_index = inputs[6];
+  recurrent_to_cell_weights_index = inputs[7];
+  recurrent_to_output_weights_index = inputs[8];
+  cell_to_input_weights_index = inputs[9];
+  cell_to_forget_weights_index = inputs[10];
+  cell_to_output_weights_index = inputs[11];
+  input_gate_bias_index = inputs[12];
+  forget_gate_bias_index = inputs[13];
+  cell_bias_index = inputs[14];
+  output_gate_bias_index = inputs[15];
+  projection_weights_index = inputs[16];
+  projection_bias_index = inputs[17];
+  output_state_in_index = inputs[18];
+  cell_state_in_index = inputs[19];
+  activation_index = inputs[20];
+  cell_threshold_index = inputs[21];
+  projection_threshold_index = inputs[22];
+}
+
+} // namespace LSTM
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Lstm.h b/runtime/contrib/pure_arm_compute/src/internal/op/Lstm.h
new file mode 100644
index 000000000..f51f0402a
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Lstm.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    Lstm.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines internal::tflite::op::LSTM::Param struct
+ *          and internal::tflite::op::LSTM::Node class
+ */
+#ifndef __INTERNAL_OP_LSTM_H__
+#define __INTERNAL_OP_LSTM_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace LSTM
+{
+
+/**
+ * @brief Struct to have indexes for operation parameter
+ */
+struct Param
+{
+  int32_t scratch_buffer_index;   /**< Index of scartch buffer */
+  int32_t output_state_out_index; /**< Index of output state out */
+  int32_t cell_state_out_index;   /**< Index of cell state out */
+  int32_t output_index;           /**< Index of output */
+
+  int32_t input_index;                       /**< Index of input */
+  int32_t input_to_input_weights_index;      /**< Index of input to input weights */
+  int32_t input_to_forget_weights_index;     /**< Index of input to forget weights */
+  int32_t input_to_cell_weights_index;       /**< Index of input to cell weights */
+  int32_t input_to_output_weights_index;     /**< Index of input to output weights */
+  int32_t recurrent_to_input_weights_index;  /**< Index of recurrent to input weights */
+  int32_t recurrent_to_forget_weights_index; /**< Index of recurrent to forget weights */
+  int32_t recurrent_to_cell_weights_index;   /**< Index of recurrent to cell weights */
+  int32_t recurrent_to_output_weights_index; /**< Index of recurrent to output weights */
+  int32_t cell_to_input_weights_index;       /**< Index of cell to input weights */
+  int32_t cell_to_forget_weights_index;      /**< Index of cell to forget weights */
+  int32_t cell_to_output_weights_index;      /**< Index of cell to output weights */
+  int32_t input_gate_bias_index;             /**< Index of input gate bias */
+  int32_t forget_gate_bias_index;            /**< Index of forget gate bias */
+  int32_t cell_bias_index;                   /**< Index of cell bias */
+  int32_t output_gate_bias_index;            /**< Index of output gate bias */
+  int32_t projection_weights_index;          /**< Index of projection weights */
+  int32_t projection_bias_index;             /**< Index of projection bias */
+  int32_t output_state_in_index;             /**< Index of output state in */
+  int32_t cell_state_in_index;               /**< Index of cell state in */
+  int32_t activation_index;                  /**< Index of activation */
+  int32_t cell_threshold_index;              /**< Index of cell threshold */
+  int32_t projection_threshold_index;        /**< Index of projection threshold */
+
+  /**
+   * @brief Construct as default
+   */
+  Param() = default;
+  /**
+   * @brief     Construct a new Param object with params
+   * @param[in] inputCount  Count of inputs
+   * @param[in] inputs      Pointer of inputs
+   * @param[in] outputCount Count of outputs
+   * @param[in] outputs     Pointer of outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to represent an operation of data structure
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief     Construct a new Node object with param
+   * @param[in] param Param object that makes up a Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destruct as default
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief  Get a reference of Param object
+   * @return Reference of Param object
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief  Visit this Node by NodeVisitor
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace LSTM
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_LSTM_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/MaxPool2D.cc b/runtime/contrib/pure_arm_compute/src/internal/op/MaxPool2D.cc
new file mode 100644
index 000000000..0c80f1f5c
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/MaxPool2D.cc
@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/MaxPool2D.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace MaxPool2D
+{
+namespace Explicit
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Explicit
+
+namespace Implicit
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Implicit
+} // namespace MaxPool2D
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace MaxPool2D
+{
+namespace Explicit
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 10 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> IFM Tensor Index
+  //  1 -> Padding_left index
+  //  2 -> Padding_right index
+  //  3 -> Padding_top index
+  //  4 -> Padding_bottom index
+  //  5 -> Horizontal (over width) Stride Index
+  //  6 -> Vertial (over height) Stride Index
+  //  7 -> Filter Width Index
+  //  8 -> Filter Height Index
+  //  9 -> FuseCode (activation) Index
+  ifm_index = inputs[0];
+  padding_left_index = inputs[1];
+  padding_right_index = inputs[2];
+  padding_top_index = inputs[3];
+  padding_bottom_index = inputs[4];
+  hstride_index = inputs[5];
+  vstride_index = inputs[6];
+  kw_index = inputs[7];
+  kh_index = inputs[8];
+  activation_index = inputs[9];
+}
+
+} // namespace Explicit
+
+namespace Implicit
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 7 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> IFM Tensor Index
+  //  1 -> Padding Code (ANEURALNETWORKS_PADDING_SAME or ANEURALNETWORKS_PADDING_VALID) Index
+  //  2 -> Horizontal (over width) Stride Index
+  //  3 -> Vertial (over height) Stride Index
+  //  4 -> Filter Width Index
+  //  5 -> Filter Height Index
+  //  6 -> FuseCode (activation) Index
+  ifm_index = inputs[0];
+  padding_index = inputs[1];
+  hstride_index = inputs[2];
+  vstride_index = inputs[3];
+  kw_index = inputs[4];
+  kh_index = inputs[5];
+  activation_index = inputs[6];
+}
+
+} // namespace Implicit
+} // namespace MaxPool2D
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/MaxPool2D.h b/runtime/contrib/pure_arm_compute/src/internal/op/MaxPool2D.h
new file mode 100644
index 000000000..329ccecb7
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/MaxPool2D.h
@@ -0,0 +1,202 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file MaxPool2D.h
+ * @brief This file contains accept function and params for MaxPool2D operation
+ * @ingroup COM_AI_RUNTIME
+ */
+
+#ifndef __INTERNAL_OP_MAX_POOL_2D_H__
+#define __INTERNAL_OP_MAX_POOL_2D_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace MaxPool2D
+{
+namespace Explicit
+{
+
+/**
+ * @brief Struct of MaxPool2D(Explicit) operation's param
+ */
+struct Param
+{
+  int32_t ofm_index; /**< Output format index */
+
+  int32_t ifm_index; /**< Input format index */
+
+  int32_t kw_index; /**< Kernel width index */
+  int32_t kh_index; /**< Kernel height index */
+
+  int32_t hstride_index; /**< Horizontal stride index */
+  int32_t vstride_index; /**< Vertical stride index */
+
+  int32_t padding_left_index;   /**< Left padding index */
+  int32_t padding_right_index;  /**< Right padding index */
+  int32_t padding_top_index;    /**< Top padding index */
+  int32_t padding_bottom_index; /**< Bottom padding index */
+
+  int32_t activation_index; /**< Activation index */
+
+  /**
+   * @brief Construct a new Param object for MaxPool2D(Explicit) as default
+   */
+  Param() = default;
+
+  /**
+   * @brief Construct a new Param object for MaxPool2D(Explicit) with params
+   * @param [in] inputCount The number of input
+   * @param [in] inputs Array containing inputs
+   * @param [in] outputCount The number of output
+   * @param [in] outputs Array containing outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to define operation node for MaxPool2D(Explicit)
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Node object for MaxPool2D(Explicit) with param
+   * @param [in] param Parameters for Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destroy the Node object for MaxPool2D(Explicit)
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief Get parameters for MaxPool2D(Explicit)
+   * @return Parameters of MaxPool2D(Explicit)
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Function for accepting node for MaxPool2D(Explicit)
+   * @param [in] v Node visitor for invoking visit function of MaxPool2D(Explicit)
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace Explicit
+
+namespace Implicit
+{
+
+/**
+ * @brief Struct of MaxPool2D(Implicit) operation's param
+ */
+struct Param
+{
+  int32_t ofm_index; /**< Output format index */
+
+  int32_t ifm_index; /**< Input format index */
+
+  int32_t kw_index; /**< Kernel width index */
+  int32_t kh_index; /**< Kernel height index */
+
+  int32_t hstride_index; /**< Horizontal stride index */
+  int32_t vstride_index; /**< Vertical stride index */
+
+  int32_t padding_index;    /**< Padding index */
+  int32_t activation_index; /**< Activation index */
+
+  /**
+   * @brief Construct a new Param object for MaxPool2D(Implicit) as default
+   */
+  Param() = default;
+
+  /**
+   * @brief Construct a new Param object for MaxPool2D(Implicit) with params
+   * @param [in] inputCount The number of input
+   * @param [in] inputs Array containing inputs
+   * @param [in] outputCount The number of output
+   * @param [in] outputs Array containing outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to define operation node for MaxPool2D(Implicit)
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Node object for MaxPool2D(Implicit) with param
+   * @param [in] param Parameters for Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destroy the Node object for MaxPool2D(Implicit)
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief Get parameters for MaxPool2D(Implicit)
+   * @return Parameters of MaxPool2D(Implicit)
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Function for accepting node for MaxPool2D(Implicit)
+   * @param [in] v Node visitor for invoking visit function of MaxPool2D(Implicit)
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace Implicit
+} // namespace MaxPool2D
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_MAX_POOL_2D_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Mean.cc b/runtime/contrib/pure_arm_compute/src/internal/op/Mean.cc
new file mode 100644
index 000000000..222a3ee4a
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Mean.cc
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/Mean.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Mean
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Mean
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Mean
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 3 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> ifm Tensor Index
+  //  1 -> axis Tensor Index
+  //  2 -> keep_dims Index
+  ifm_index = inputs[0];
+  axis_index = inputs[1];
+  keep_dims_index = inputs[2];
+}
+
+} // namespace Mean
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Mean.h b/runtime/contrib/pure_arm_compute/src/internal/op/Mean.h
new file mode 100644
index 000000000..f8e7ed308
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Mean.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    Mean.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines internal::tflite::op::Mean::Param struct
+ *          and internal::tflite::op::Mean::Node class
+ */
+#ifndef __INTERNAL_OP_MEAN_H__
+#define __INTERNAL_OP_MEAN_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Mean
+{
+
+/**
+ * @brief Struct to have indexes for operation parameter
+ */
+struct Param
+{
+  int32_t ofm_index; /**< Index of output feature map */ // output
+
+  int32_t ifm_index; /**< Index of input feature map */ // input
+  int32_t axis_index; /**< Index of axis */             // axis
+  int32_t keep_dims_index; /**< Index of keep dims */   // keep_dims
+  /**
+   * @brief Construct as default
+   */
+  Param() = default;
+  /**
+ * @brief Construct a new Param object with params
+ * @param[in] inputCount  Count of inputs
+ * @param[in] inputs      Pointer of inputs
+ * @param[in] outputCount Count of outputs
+ * @param[in] outputs     Pointer of outputs
+ */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to represent an operation of data structure
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Node object with param
+   * @param[in] param Param object that makes up a Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destruct as default
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief  Get a reference of Param object
+   * @return Reference of Param object
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Visit this Node by NodeVisitor
+   * @param[in] v Visitor
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace Mean
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_MEAN_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Mul.cc b/runtime/contrib/pure_arm_compute/src/internal/op/Mul.cc
new file mode 100644
index 000000000..2a2ae00ed
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Mul.cc
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/Mul.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Mul
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Mul
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Mul
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 3 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> LHS Tensor Index
+  //  1 -> RHS Tensor Index
+  //  2 -> Activation Index
+  lhs_index = inputs[0];
+  rhs_index = inputs[1];
+  activation_index = inputs[2];
+}
+
+} // namespace Mul
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Mul.h b/runtime/contrib/pure_arm_compute/src/internal/op/Mul.h
new file mode 100644
index 000000000..9710dd057
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Mul.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    Mul.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines internal::tflite::op::Mul class
+ */
+#ifndef __INTERNAL_OP_MUL_H__
+#define __INTERNAL_OP_MUL_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Mul
+{
+
+/**
+ * @brief Struct to have indexes for operation parameter
+ */
+struct Param
+{
+  int32_t ofm_index; /** Index of output feature map */
+
+  int32_t lhs_index;        /** Index of lhs */
+  int32_t rhs_index;        /** Index of rhs */
+  int32_t activation_index; /** Index of activation */
+  /**
+   * @brief Construct as default
+   */
+  Param() = default;
+  /**
+   * @brief     Construct a new Param object with params
+   * @param[in] inputCount  Count of inputs
+   * @param[in] inputs      Pointer of inputs
+   * @param[in] outputCount Count of outputs
+   * @param[in] outputs     Pointer of outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to represent an operation of data structure
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief     Construct a new Node object with param
+   * @param[in] param Param object that makes up a Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destruct as default
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief  Get a reference of Param object
+   * @return Reference of Param object
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief  Visit this Node by NodeVisitor
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace Mul
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_MUL_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Neg.cc b/runtime/contrib/pure_arm_compute/src/internal/op/Neg.cc
new file mode 100644
index 000000000..72fecf484
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Neg.cc
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/Neg.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Neg
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Neg
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Neg
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 1 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> Input Tensor Index
+  ifm_index = inputs[0];
+}
+
+} // namespace Neg
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Neg.h b/runtime/contrib/pure_arm_compute/src/internal/op/Neg.h
new file mode 100644
index 000000000..77507df3d
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Neg.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __INTERNAL_OP_NEG_H__
+#define __INTERNAL_OP_NEG_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Neg
+{
+
+struct Param
+{
+  int32_t ofm_index;
+
+  int32_t ifm_index;
+
+  Param() = default;
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+class Node final : public op::Node
+{
+public:
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  virtual ~Node() = default;
+
+public:
+  const Param &param(void) const { return _param; }
+
+public:
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace Neg
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_NEG_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Node.h b/runtime/contrib/pure_arm_compute/src/internal/op/Node.h
new file mode 100644
index 000000000..be1cbdb5b
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Node.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Node.h
+ * @brief This file contains struct of Node and NodeVisitor
+ * @ingroup COM_AI_RUNTIME
+ */
+
+#ifndef __INTERNAL_OP_NODE_H__
+#define __INTERNAL_OP_NODE_H__
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+
+/**
+ * @brief Struct of operation NodeVisitor
+ */
+struct NodeVisitor;
+
+/**
+ * @brief Struct of operation Node
+ */
+struct Node
+{
+  /**
+   * @brief Destroy the Node object for operation
+   */
+  virtual ~Node() = default;
+
+  /**
+   * @brief Function for accepting node for operation
+   * @param [in] v Node visitor for invoking visit function of operation
+   * @return N/A
+   */
+  virtual void accept(NodeVisitor &&) const = 0;
+};
+
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_NODE_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/NodeVisitor.h b/runtime/contrib/pure_arm_compute/src/internal/op/NodeVisitor.h
new file mode 100644
index 000000000..0c1a4001d
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/NodeVisitor.h
@@ -0,0 +1,493 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file NodeVisitor.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief This file defines NodeVisitor
+ */
+
+#ifndef __INTERNAL_OP_NODE_VISITOR_H__
+#define __INTERNAL_OP_NODE_VISITOR_H__
+
+#include "internal/op/Add.h"
+#include "internal/op/Sub.h"
+#include "internal/op/Mul.h"
+#include "internal/op/Div.h"
+#include "internal/op/Conv2D.h"
+#include "internal/op/DepthwiseConv2D.h"
+#include "internal/op/Dequantize.h"
+#include "internal/op/MaxPool2D.h"
+#include "internal/op/AvgPool2D.h"
+#include "internal/op/ArgMax.h"
+#include "internal/op/Concat.h"
+#include "internal/op/Reshape.h"
+#include "internal/op/ResizeBilinear.h"
+#include "internal/op/StridedSlice.h"
+#include "internal/op/FullyConnected.h"
+#include "internal/op/Softmax.h"
+#include "internal/op/ReduceMax.h"
+#include "internal/op/ReduceMin.h"
+#include "internal/op/Cast.h"
+#include "internal/op/TopKV2.h"
+#include "internal/op/Gather.h"
+#include "internal/op/PReLU.h"
+#include "internal/op/ReLU.h"
+#include "internal/op/ReLU1.h"
+#include "internal/op/ReLU6.h"
+#include "internal/op/Tanh.h"
+#include "internal/op/Squeeze.h"
+#include "internal/op/Logistic.h"
+#include "internal/op/Mean.h"
+#include "internal/op/Rnn.h"
+#include "internal/op/Transpose.h"
+#include "internal/op/Lstm.h"
+#include "internal/op/Floor.h"
+#include "internal/op/Split.h"
+#include "internal/op/RSQRT.h"
+#include "internal/op/SQRT.h"
+#include "internal/op/Pad.h"
+#include "internal/op/SpaceToDepth.h"
+#include "internal/op/SpaceToBatchND.h"
+#include "internal/op/L2Pool2D.h"
+#include "internal/op/EmbeddingLookup.h"
+#include "internal/op/HashtableLookup.h"
+#include "internal/op/L2Normalization.h"
+#include "internal/op/SquaredDifference.h"
+#include "internal/op/LocalResponseNormalization.h"
+#include "internal/op/DepthToSpace.h"
+#include "internal/op/Unpack.h"
+#include "internal/op/Neg.h"
+#include "internal/op/Exp.h"
+#include "internal/op/ReduceSum.h"
+#include "internal/op/Equal.h"
+#include "internal/op/BatchToSpaceNd.h"
+#include "internal/op/TransposeConv.h"
+#include "internal/op/Pack.h"
+#include "internal/op/Abs.h"
+#include "internal/op/NotEqual.h"
+#include "internal/op/LogicalAnd.h"
+#include "internal/op/LogicalNot.h"
+#include "internal/op/LogicalOr.h"
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+
+/**
+ * @brief Struct to define visitor for operation Nodes
+ */
+struct NodeVisitor
+{
+  /**
+   * @brief Destruct NodeVisitor object with default
+   */
+  virtual ~NodeVisitor() = default;
+
+  /**
+   * @brief Visit an Add node
+   * @param[in] node Add node to visit
+   * @return N/A
+   */
+  virtual void visit(const Add::Node &) = 0;
+  /**
+   * @brief Visit a Mul node
+   * @param[in] node Mul node to visit
+   * @return N/A
+   */
+  virtual void visit(const Sub::Node &) = 0;
+  /**
+   * @brief Visit a Mul node
+   * @param[in] node Mul node to visit
+   * @return N/A
+   */
+  virtual void visit(const Mul::Node &) = 0;
+  /**
+   * @brief Visit a Div node
+   * @param[in] node Div node to visit
+   * @return N/A
+   */
+  virtual void visit(const Div::Node &) = 0;
+  /**
+   * @brief Visit a Conv2D node with implicit padding
+   * @param[in] node Conv2D node to visit
+   * @return N/A
+   */
+  virtual void visit(const Conv2D::Implicit::Node &) = 0;
+  /**
+   * @brief Visit a Conv2D node with explicit padding
+   * @param[in] node Conv2D node to visit
+   * @return N/A
+   */
+  virtual void visit(const Conv2D::Explicit::Node &) = 0;
+  /**
+   * @brief Visit a DepthwiseConv2D node with implicit padding
+   * @param[in] node DepthwiseConv2D node to visit
+   * @return N/A
+   */
+  virtual void visit(const DepthwiseConv2D::Implicit::Node &) = 0;
+  /**
+   * @brief Visit a DepthwiseConv2D node with explicit padding
+   * @param[in] node DepthwiseConv2D node to visit
+   * @return N/A
+   */
+  virtual void visit(const DepthwiseConv2D::Explicit::Node &) = 0;
+  /**
+   * @brief Visit a Dequantize node
+   * @param[in] node Dequantize node to visit
+   * @return N/A
+   */
+  virtual void visit(const Dequantize::Node &) = 0;
+  /**
+   * @brief Visit a MaxPool2D node with implicit padding
+   * @param[in] node MaxPool2D node to visit
+   * @return N/A
+   */
+  virtual void visit(const MaxPool2D::Implicit::Node &) = 0;
+  /**
+   * @brief Visit a MaxPool2D node with explicit padding
+   * @param[in] node MaxPool2D node to visit
+   * @return N/A
+   */
+  virtual void visit(const MaxPool2D::Explicit::Node &) = 0;
+  /**
+   * @brief Visit an AvgPool2D node with implicit padding
+   * @param[in] node AvgPool2D node to visit
+   * @return N/A
+   */
+  virtual void visit(const AvgPool2D::Implicit::Node &) = 0;
+  /**
+   * @brief Visit an AvgPool2D node with explicit padding
+   * @param[in] node AvgPool2D node to visit
+   * @return N/A
+   */
+  virtual void visit(const AvgPool2D::Explicit::Node &) = 0;
+  /**
+   * @brief Visit a Concat node
+   * @param[in] node Concat node to visit
+   * @return N/A
+   */
+  virtual void visit(const Concat::Node &) = 0;
+  /**
+   * @brief Visit a ArgMax node
+   * @param[in] node ArgMax node to visit
+   * @return N/A
+   */
+  virtual void visit(const ArgMax::Node &) = 0;
+  /**
+   * @brief Visit an Reshape node
+   * @param[in] node Reshape node to visit
+   * @return N/A
+   */
+  virtual void visit(const Reshape::Node &) = 0;
+  /**
+   * @brief Visit an ResizeBilinear node
+   * @param[in] node ResizeBilinear node to visit
+   * @return N/A
+   */
+  virtual void visit(const ResizeBilinear::Node &) = 0;
+  /**
+   * @brief Visit a StridedSlice node
+   * @param[in] node StridedSlice node to visit
+   * @return N/A
+   */
+  virtual void visit(const StridedSlice::Node &) = 0;
+  /**
+   * @brief Visit a FullyConnected node
+   * @param[in] node FullyConnected node to visit
+   * @return N/A
+   */
+  virtual void visit(const FullyConnected::Node &) = 0;
+  /**
+   * @brief Visit a Softmax node
+   * @param[in] node Softmax node to visit
+   * @return N/A
+   */
+  virtual void visit(const Softmax::Node &) = 0;
+  /**
+   * @brief Visit a ReduceMax node
+   * @param[in] node ReduceMax node to visit
+   * @return N/A
+   */
+  virtual void visit(const ReduceMax::Node &) = 0;
+  /**
+   * @brief Visit a ReduceMin node
+   * @param[in] node ReduceMin node to visit
+   * @return N/A
+   */
+  virtual void visit(const ReduceMin::Node &) = 0;
+  /**
+   * @brief Visit a Cast node
+   * @param[in] node Cast node to visit
+   * @return N/A
+   */
+  virtual void visit(const Cast::Node &) = 0;
+  /**
+   * @brief Visit a TopKV2 node
+   * @param[in] node TopKV2 node to visit
+   * @return N/A
+   */
+  virtual void visit(const TopKV2::Node &) = 0;
+  /**
+   * @brief Visit a Gather node
+   * @param[in] node Gather node to visit
+   * @return N/A
+   */
+  virtual void visit(const Gather::Node &) = 0;
+  /**
+   * @brief Visit an PReLU node
+   * @param[in] node PReLU node to visit
+   * @return N/A
+   */
+  virtual void visit(const PReLU::Node &) = 0;
+  /**
+   * @brief Visit an ReLU node
+   * @param[in] node Relu node to visit
+   * @return N/A
+   */
+  virtual void visit(const ReLU::Node &) = 0;
+  /**
+   * @brief Visit a ReLU1 node
+   * @param[in] node ReLU1 node to visit
+   * @return N/A
+   */
+  virtual void visit(const ReLU1::Node &) = 0;
+  /**
+   * @brief Visit a ReLU6 node
+   * @param[in] node ReLU6 node to visit
+   * @return N/A
+   */
+  virtual void visit(const ReLU6::Node &) = 0;
+  /**
+   * @brief Visit a Tanh node
+   * @param[in] node Tanh node to visit
+   * @return N/A
+   */
+  virtual void visit(const Tanh::Node &) = 0;
+  /**
+   * @brief Visit a Squeeze node
+   * @param[in] node Squeeze node to visit
+   * @return N/A
+   */
+  virtual void visit(const Squeeze::Node &) = 0;
+  /**
+   * @brief Visit an Logistic node
+   * @param[in] node Logistic node to visit
+   * @return N/A
+   */
+  virtual void visit(const Logistic::Node &) = 0;
+  /**
+   * @brief Visit a Mean node
+   * @param[in] node Mean node to visit
+   * @return N/A
+   */
+  virtual void visit(const Mean::Node &) = 0;
+  /**
+   * @brief Visit an RNN node
+   * @param[in] node RNN node to visit
+   * @return N/A
+   */
+  virtual void visit(const RNN::Node &) = 0;
+  /**
+   * @brief Visit a Transpose node
+   * @param[in] node Transpose node to visit
+   * @return N/A
+   */
+  virtual void visit(const Transpose::Node &) = 0;
+  /**
+   * @brief Visit an LSTM node
+   * @param[in] node LSTM node to visit
+   * @return N/A
+   */
+  virtual void visit(const LSTM::Node &) = 0;
+  /**
+   * @brief Visit a Floor node
+   * @param[in] node Floor node to visit
+   * @return N/A
+   */
+  virtual void visit(const Floor::Node &) = 0;
+  /**
+   * @brief Visit a Split node
+   * @param[in] node Split node to visit
+   * @return N/A
+   */
+  virtual void visit(const Split::Node &) = 0;
+  /**
+   * @brief Visit an RSQRT node
+   * @param[in] node RSQRT node to visit
+   * @return N/A
+   */
+  virtual void visit(const RSQRT::Node &) = 0;
+  /**
+   * @brief Visit an SQRT node
+   * @param[in] node SQRT node to visit
+   * @return N/A
+   */
+  virtual void visit(const SQRT::Node &) = 0;
+  /**
+   * @brief Visit a Pad node
+   * @param[in] node Pad node to visit
+   * @return N/A
+   */
+  virtual void visit(const Pad::Node &) = 0;
+  /**
+   * @brief Visit a SpaceToDepth node
+   * @param[in] node SpaceToDepth node to visit
+   * @return N/A
+   */
+  virtual void visit(const SpaceToDepth::Node &) = 0;
+  /**
+   * @brief Visit a SpaceToBatchND node
+   * @param[in] node SpaceToBatchND node to visit
+   * @return N/A
+   */
+  virtual void visit(const SpaceToBatchND::Node &) = 0;
+  /**
+   * @brief Visit an L2Pool2D node with implicit padding
+   * @param[in] node L2Pool2D node to visit
+   * @return N/A
+   */
+  virtual void visit(const L2Pool2D::Implicit::Node &) = 0;
+  /**
+   * @brief Visit an L2Pool2D node with explicit padding
+   * @param[in] node L2Pool2D node to visit
+   * @return N/A
+   */
+  virtual void visit(const L2Pool2D::Explicit::Node &) = 0;
+  /**
+   * @brief Visit an EmbeddingLookup node
+   * @param[in] node EmbeddingLookup node to visit
+   * @return N/A
+   */
+  virtual void visit(const EmbeddingLookup::Node &) = 0;
+  /**
+   * @brief Visit a HashtableLookup node
+   * @param[in] node HashtableLookup node to visit
+   * @return N/A
+   */
+  virtual void visit(const HashtableLookup::Node &) = 0;
+  /**
+   * @brief Visit an L2Normalization node
+   * @param[in] node L2Normalization node to visit
+   * @return N/A
+   */
+  virtual void visit(const L2Normalization::Node &) = 0;
+  /**
+   * @brief Visit a SquaredDifference node
+   * @param[in] node SquaredDifference node to visit
+   * @return N/A
+   */
+  virtual void visit(const SquaredDifference::Node &) = 0;
+  /**
+   * @brief Visit a LocalResponseNormalization node
+   * @param[in] node LocalResponseNormalization node to visit
+   * @return N/A
+   */
+  virtual void visit(const LocalResponseNormalization::Node &) = 0;
+  /**
+   * @brief Visit a DepthToSpace node
+   * @param[in] node DepthToSpace node to visit
+   * @return N/A
+   */
+  virtual void visit(const DepthToSpace::Node &) = 0;
+  /**
+   * @brief Visit a Unpack node
+   * @param[in] node Unpack node to visit
+   * @return N/A
+   */
+  virtual void visit(const Unpack::Node &) = 0;
+  /**
+   * @brief Visit a Neg node
+   * @param[in] node Neg node to visit
+   * @return N/A
+   */
+  virtual void visit(const Neg::Node &) = 0;
+  /**
+   * @brief Visit a Exp node
+   * @param[in] node Exp node to visit
+   * @return N/A
+   */
+  virtual void visit(const Exp::Node &) = 0;
+  /**
+   * @brief Visit a ReduceSum node
+   * @param[in] node ReduceSum node to visit
+   * @return N/A
+   */
+  virtual void visit(const ReduceSum::Node &) = 0;
+  /**
+   * @brief Visit a Equal node
+   * @param[in] node Equal node to visit
+   * @return N/A
+   */
+  virtual void visit(const Equal::Node &) = 0;
+  /**
+   * @brief Visit a BatchToSpaceNd node
+   * @param[in] node BatchToSpaceNd node to visit
+   * @return N/A
+   */
+  virtual void visit(const BatchToSpaceNd::Node &) = 0;
+  /**
+   * @brief Visit a TransposeConv node
+   * @param[in] node TransposeConv node to visit
+   * @return N/A
+   */
+  virtual void visit(const TransposeConv::Node &) = 0;
+  /**
+   * @brief Visit a Pack node
+   * @param[in] node Pack node to visit
+   * @return N/A
+   */
+  virtual void visit(const Pack::Node &) = 0;
+  /**
+   * @brief Visit a Abs node
+   * @param[in] node Abs node to visit
+   * @return N/A
+   */
+  virtual void visit(const Abs::Node &) = 0;
+  /**
+   * @brief Visit a NotEqual node
+   * @param[in] node NotEqual node to visit
+   * @return N/A
+   */
+  virtual void visit(const NotEqual::Node &) = 0;
+  /**
+   * @brief Visit a LogicalAnd node
+   * @param[in] node LogicalAnd node to visit
+   * @return N/A
+   */
+  virtual void visit(const LogicalAnd::Node &) = 0;
+  /**
+   * @brief Visit a LogicalNot node
+   * @param[in] node LogicalNot node to visit
+   * @return N/A
+   */
+  virtual void visit(const LogicalNot::Node &) = 0;
+  /**
+   * @brief Visit a LogicalOr node
+   * @param[in] node LogicalOr node to visit
+   * @return N/A
+   */
+  virtual void visit(const LogicalOr::Node &) = 0;
+};
+
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_NODE_VISITOR_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/NotEqual.cc b/runtime/contrib/pure_arm_compute/src/internal/op/NotEqual.cc
new file mode 100644
index 000000000..2906e214b
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/NotEqual.cc
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/NotEqual.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace NotEqual
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace NotEqual
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace NotEqual
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 2 && outputCount == 1);
+
+  output_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> input1 Tensor Index
+  //  1 -> input2 Tensor Index
+  input1_index = inputs[0];
+  input2_index = inputs[1];
+}
+
+} // namespace NotEqual
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/NotEqual.h b/runtime/contrib/pure_arm_compute/src/internal/op/NotEqual.h
new file mode 100644
index 000000000..0d6130948
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/NotEqual.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __INTERNAL_OP_NOT_EQUAL_H__
+#define __INTERNAL_OP_NOT_EQUAL_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace NotEqual
+{
+
+struct Param
+{
+  int32_t output_index;
+
+  int32_t input1_index;
+  int32_t input2_index;
+
+  Param() = default;
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+} // namespace NotEqual
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace NotEqual
+{
+class Node final : public op::Node
+{
+public:
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  virtual ~Node() = default;
+
+public:
+  const Param &param(void) const { return _param; }
+
+public:
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace NotEqual
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_NOT_EQUAL_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/PReLU.cc b/runtime/contrib/pure_arm_compute/src/internal/op/PReLU.cc
new file mode 100644
index 000000000..25b06505b
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/PReLU.cc
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/PReLU.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace PReLU
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace PReLU
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace PReLU
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 2 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> input Tensor Index
+  //  1 -> alpha Tensor Index
+  ifm_index = inputs[0];
+  alpha_index = inputs[1];
+}
+
+} // namespace PReLU
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/PReLU.h b/runtime/contrib/pure_arm_compute/src/internal/op/PReLU.h
new file mode 100644
index 000000000..ae754abb4
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/PReLU.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file ReLU.h
+ * @brief This file contains accept function and params for ReLU operation
+ * @ingroup COM_AI_RUNTIME
+ */
+
+#ifndef __INTERNAL_OP_PRELU_H__
+#define __INTERNAL_OP_PRELU_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace PReLU
+{
+
+/**
+ * @brief Struct of PReLU operation's param
+ */
+struct Param
+{
+  int32_t ofm_index; /**< Output format index */
+
+  int32_t ifm_index;   /**< Input format index */
+  int32_t alpha_index; /**< Alpha input index */
+
+  /**
+   * @brief Construct a new Param object for ReLU as default
+   */
+  Param() = default;
+
+  /**
+   * @brief Construct a new Param object for PReLU with params
+   * @param [in] inputCount The number of input
+   * @param [in] inputs Array containing inputs
+   * @param [in] outputCount The number of output
+   * @param [in] outputs Array containing outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to define operation node for PReLU
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Node object for PReLU with param
+   * @param [in] param Parameters for Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destroy the Node object for PReLU
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief Get parameters for PReLU
+   * @return Parameters of PReLU
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Function for accepting node for PReLU
+   * @param [in] v Node visitor for invoking visit function of PReLU
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace PReLU
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_PRELU_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Pack.cc b/runtime/contrib/pure_arm_compute/src/internal/op/Pack.cc
new file mode 100644
index 000000000..73f89b840
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Pack.cc
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/Pack.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Pack
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Pack
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Pack
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(outputCount == 1);
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 .. n - 3 -> Input Tensor Index
+  //  n - 2      -> Input Tensor counts (will be ignored)
+  //  n - 1      -> Input Axis Index
+  ofm_index = outputs[0];
+  axis_index = inputs[inputCount - 1];
+  // last input is axis along which packing is required
+  for (uint32_t n = 0; n < inputCount - 2; ++n)
+  {
+    ifm_indexes.emplace_back(inputs[n]);
+  }
+}
+
+} // namespace Pack
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Pack.h b/runtime/contrib/pure_arm_compute/src/internal/op/Pack.h
new file mode 100644
index 000000000..c5de01bd8
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Pack.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __INTERNAL_OP_PACK_H__
+#define __INTERNAL_OP_PACK_H__
+
+#include "internal/op/Node.h"
+#include <vector>
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Pack
+{
+
+struct Param
+{
+  int32_t ofm_index;
+  //  There are N+1 inputs, 0 to N-1 are tensors of same shape
+  // Nth input is axis index along which stack is needed to be done.
+  std::vector<int32_t> ifm_indexes;
+  int32_t axis_index;
+
+  Param() = default;
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+class Node final : public op::Node
+{
+public:
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  virtual ~Node() = default;
+
+public:
+  const Param &param(void) const { return _param; }
+
+public:
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace Pack
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_PACK_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Pad.cc b/runtime/contrib/pure_arm_compute/src/internal/op/Pad.cc
new file mode 100644
index 000000000..00938242b
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Pad.cc
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/Pad.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Pad
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Pad
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Pad
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 2 && outputCount == 1);
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> input Tensor Index
+  //  1 -> paddings
+  ifm_index = inputs[0];
+  paddings_index = inputs[1];
+}
+} // namespace Pad
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Pad.h b/runtime/contrib/pure_arm_compute/src/internal/op/Pad.h
new file mode 100644
index 000000000..68752a10e
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Pad.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Pad.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief This file defines Pad node
+ */
+
+#ifndef __INTERNAL_OP_PAD_H__
+#define __INTERNAL_OP_PAD_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Pad
+{
+
+/**
+ * @brief Struct to manipulate parameter for Pad operation
+ */
+struct Param
+{
+  int32_t ifm_index;      //!< index for input
+  int32_t paddings_index; //!< index for padding
+  int32_t ofm_index;      //!< index for output
+
+  /**
+   * @brief Default Constructor
+   */
+  Param() = default;
+  /**
+   * @brief Construct a new Param object
+   * @param[in] inputCount the number of inputs
+   * @param[in] inputs pointer for input data
+   * @param[in] outputCount the number of outputs
+   * @param[in] outputs pointer for input data
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to define Pad Operation
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new RNN Node object
+   * @param param Parameter for RNN Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Default Destructor
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief Get parameter
+   * @return Param reference
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Accept a NodeVisitor so that it can visit this node
+   * @param [in] v Visitor
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param; //!< parameter for Pad node
+};
+
+} // namespace Pad
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_PAD_H_
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/RSQRT.cc b/runtime/contrib/pure_arm_compute/src/internal/op/RSQRT.cc
new file mode 100644
index 000000000..d79563d14
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/RSQRT.cc
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/RSQRT.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace RSQRT
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace RSQRT
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace RSQRT
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 1 && outputCount == 1);
+
+  output_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //  0 -> input Tensor Index
+  input_index = inputs[0];
+}
+
+} // namespace RSQRT
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/RSQRT.h b/runtime/contrib/pure_arm_compute/src/internal/op/RSQRT.h
new file mode 100644
index 000000000..e39d60241
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/RSQRT.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    RSQRT.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines internal::tflite::op::RSQRT::Param struct
+ *          and internal::tflite::op::RSQRT::Node class
+ */
+#ifndef __INTERNAL_OP_RSQRT_H__
+#define __INTERNAL_OP_RSQRT_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace RSQRT
+{
+
+/**
+ * @brief Struct to have indexes for operation parameter
+ */
+struct Param
+{
+  int32_t output_index; /**< Index of output feature map */
+
+  int32_t input_index; /**< Index of input feature map */
+  /**
+   * @brief Construct as default
+   */
+  Param() = default;
+  /**
+   * @brief     Construct a new Param object with params
+   * @param[in] inputCount  Count of inputs
+   * @param[in] inputs      Pointer of inputs
+   * @param[in] outputCount Count of outputs
+   * @param[in] outputs     Pointer of outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to represent an operation of data structure
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief     Construct a new Node object with param
+   * @param[in] param Param object that makes up a Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destruct as default
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief  Get a reference of Param object
+   * @return Reference of Param object
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief  Visit this Node by NodeVisitor
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace RSQRT
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_RSQRT_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/ReLU.cc b/runtime/contrib/pure_arm_compute/src/internal/op/ReLU.cc
new file mode 100644
index 000000000..2f48372af
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/ReLU.cc
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/ReLU.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace ReLU
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace ReLU
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace ReLU
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 1 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> input Tensor Index
+  ifm_index = inputs[0];
+}
+
+} // namespace ReLU
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/ReLU.h b/runtime/contrib/pure_arm_compute/src/internal/op/ReLU.h
new file mode 100644
index 000000000..aaa39b523
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/ReLU.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file ReLU.h
+ * @brief This file contains accept function and params for ReLU operation
+ * @ingroup COM_AI_RUNTIME
+ */
+
+#ifndef __INTERNAL_OP_RELU_H__
+#define __INTERNAL_OP_RELU_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace ReLU
+{
+
+/**
+ * @brief Struct of ReLU operation's param
+ */
+struct Param
+{
+  int32_t ofm_index; /**< Output format index */
+
+  int32_t ifm_index; /**< Input format index */
+
+  /**
+   * @brief Construct a new Param object for ReLU as default
+   */
+  Param() = default;
+
+  /**
+   * @brief Construct a new Param object for ReLU with params
+   * @param [in] inputCount The number of input
+   * @param [in] inputs Array containing inputs
+   * @param [in] outputCount The number of output
+   * @param [in] outputs Array containing outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to define operation node for ReLU
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Node object for ReLU with param
+   * @param [in] param Parameters for Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destroy the Node object for ReLU
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief Get parameters for ReLU
+   * @return Parameters of ReLU
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Function for accepting node for ReLU
+   * @param [in] v Node visitor for invoking visit function of ReLU
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace ReLU
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_RELU_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/ReLU1.cc b/runtime/contrib/pure_arm_compute/src/internal/op/ReLU1.cc
new file mode 100644
index 000000000..1925ac404
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/ReLU1.cc
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/ReLU1.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace ReLU1
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace ReLU1
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace ReLU1
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 1 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> input Tensor Index
+  ifm_index = inputs[0];
+}
+
+} // namespace ReLU1
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/ReLU1.h b/runtime/contrib/pure_arm_compute/src/internal/op/ReLU1.h
new file mode 100644
index 000000000..330445af8
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/ReLU1.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file ReLU1.h
+ * @brief This file contains accept function and params for ReLU1 operation
+ * @ingroup COM_AI_RUNTIME
+ */
+
+#ifndef __INTERNAL_OP_RELU1_H__
+#define __INTERNAL_OP_RELU1_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace ReLU1
+{
+
+/**
+ * @brief Struct of ReLU1 operation's param
+ */
+struct Param
+{
+  int32_t ofm_index; /**< Output format index */
+
+  int32_t ifm_index; /**< Input format index */
+
+  /**
+   * @brief Construct a new Param object for ReLU1 as default
+   */
+  Param() = default;
+
+  /**
+   * @brief Construct a new Param object for ReLU1 with params
+   * @param [in] inputCount The number of input
+   * @param [in] inputs Array containing inputs
+   * @param [in] outputCount The number of output
+   * @param [in] outputs Array containing outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to define operation node for ReLU1
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Node object for ReLU1 with param
+   * @param [in] param Parameters for Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destroy the Node object for ReLU1
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief Get parameters for ReLU1
+   * @return Parameters of ReLU1
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Function for accepting node for ReLU1
+   * @param [in] v Node visitor for invoking visit function of ReLU1
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace ReLU1
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_RELU1_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/ReLU6.cc b/runtime/contrib/pure_arm_compute/src/internal/op/ReLU6.cc
new file mode 100644
index 000000000..e94ddcf15
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/ReLU6.cc
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/ReLU6.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace ReLU6
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace ReLU6
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace ReLU6
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 1 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> input Tensor Index
+  ifm_index = inputs[0];
+}
+
+} // namespace ReLU6
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/ReLU6.h b/runtime/contrib/pure_arm_compute/src/internal/op/ReLU6.h
new file mode 100644
index 000000000..6fc2c24fe
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/ReLU6.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    ReLU6.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines internal::tflite::op::ReLU6 class
+ */
+#ifndef __INTERNAL_OP_RELU6_H__
+#define __INTERNAL_OP_RELU6_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace ReLU6
+{
+
+/**
+ * @brief Struct to have indexes for operation parameter
+ */
+struct Param
+{
+  int32_t ofm_index; /** Index of output feature map */
+
+  int32_t ifm_index; /** Index of input feature map */
+  /**
+   * @brief Construct as default
+   */
+  Param() = default;
+  /**
+   * @brief     Construct a new Param object with params
+   * @param[in] inputCount  Count of inputs
+   * @param[in] inputs      Pointer of inputs
+   * @param[in] outputCount Count of outputs
+   * @param[in] outputs     Pointer of outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to represent an operation of data structure
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief     Construct a new Node object with param
+   * @param[in] param Param object that makes up a Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destruct as default
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief  Get a reference of Param object
+   * @return Reference of Param object
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief  Visit this Node by NodeVisitor
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace ReLU6
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_RELU6_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/ReduceMax.cc b/runtime/contrib/pure_arm_compute/src/internal/op/ReduceMax.cc
new file mode 100644
index 000000000..7a337eabf
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/ReduceMax.cc
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/ReduceMax.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace ReduceMax
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace ReduceMax
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace ReduceMax
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 2 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> Input Tensor Index
+  //  1 -> Axis Tensor Index
+  ifm_index = inputs[0];
+  axis_index = inputs[1];
+}
+
+} // namespace ReduceMax
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/ReduceMax.h b/runtime/contrib/pure_arm_compute/src/internal/op/ReduceMax.h
new file mode 100644
index 000000000..77d8bd869
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/ReduceMax.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    ReduceMax.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines internal::tflite::op::ReduceMax::Param struct
+ *          and internal::tflite::op::ReduceMax::Node class
+ */
+#ifndef __INTERNAL_OP_REDUCEMAX_H__
+#define __INTERNAL_OP_REDUCEMAX_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace ReduceMax
+{
+
+/**
+ * @brief Struct to have indexes for operation parameter
+ */
+struct Param
+{
+  int32_t ofm_index; /**< Index of output feature map */
+
+  int32_t ifm_index;  /**< Index of input feature map */
+  int32_t axis_index; /**< Index of axis */
+  /**
+   * @brief Construct as default
+   */
+  Param() = default;
+  /**
+   * @brief Construct a new Param object with params
+   * @param[in] inputCount  Count of inputs
+   * @param[in] inputs      Pointer of inputs
+   * @param[in] outputCount Count of outputs
+   * @param[in] outputs     Pointer of outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to represent an operation of data structure
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Node object with param
+   * @param[in] param Param object that makes up a Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destruct as default
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief  Get a reference of Param object
+   * @return Reference of Param object
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Visit this Node by NodeVisitor
+   * @param[in] v Visitor
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace ReduceMax
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_REDUCEMAX_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/ReduceMin.cc b/runtime/contrib/pure_arm_compute/src/internal/op/ReduceMin.cc
new file mode 100644
index 000000000..72b6079d4
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/ReduceMin.cc
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/ReduceMin.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace ReduceMin
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace ReduceMin
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace ReduceMin
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 2 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> Input Tensor Index
+  //  1 -> Axis Tensor Index
+  ifm_index = inputs[0];
+  axis_index = inputs[1];
+}
+
+} // namespace ReduceMin
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/ReduceMin.h b/runtime/contrib/pure_arm_compute/src/internal/op/ReduceMin.h
new file mode 100644
index 000000000..5dd82ec43
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/ReduceMin.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    ReduceMin.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines internal::tflite::op::ReduceMin::Param struct
+ *          and internal::tflite::op::ReduceMin::Node class
+ */
+#ifndef __INTERNAL_OP_REDUCEMIN_H__
+#define __INTERNAL_OP_REDUCEMIN_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace ReduceMin
+{
+
+/**
+ * @brief Struct to have indexes for operation parameter
+ */
+struct Param
+{
+  int32_t ofm_index; /**< Index of output feature map */
+
+  int32_t ifm_index;  /**< Index of input feature map */
+  int32_t axis_index; /**< Index of axis */
+  /**
+   * @brief Construct as default
+   */
+  Param() = default;
+  /**
+   * @brief Construct a new Param object with params
+   * @param[in] inputCount  Count of inputs
+   * @param[in] inputs      Pointer of inputs
+   * @param[in] outputCount Count of outputs
+   * @param[in] outputs     Pointer of outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to represent an operation of data structure
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Node object with param
+   * @param[in] param Param object that makes up a Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destruct as default
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief  Get a reference of Param object
+   * @return Reference of Param object
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Visit this Node by NodeVisitor
+   * @param[in] v Visitor
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace ReduceMin
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_REDUCEMIN_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/ReduceSum.cc b/runtime/contrib/pure_arm_compute/src/internal/op/ReduceSum.cc
new file mode 100644
index 000000000..4d83c1734
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/ReduceSum.cc
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/ReduceSum.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace ReduceSum
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace ReduceSum
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace ReduceSum
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 2 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> Input Tensor Index
+  //  1 -> Axis Tensor Index
+  ifm_index = inputs[0];
+  axis_index = inputs[1];
+}
+
+} // namespace ReduceSum
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/ReduceSum.h b/runtime/contrib/pure_arm_compute/src/internal/op/ReduceSum.h
new file mode 100644
index 000000000..9c661f63a
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/ReduceSum.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __INTERNAL_OP_REDUCESUM_H__
+#define __INTERNAL_OP_REDUCESUM_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace ReduceSum
+{
+
+struct Param
+{
+  int32_t ofm_index;
+
+  int32_t ifm_index;
+  int32_t axis_index;
+
+  Param() = default;
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+class Node final : public op::Node
+{
+public:
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  virtual ~Node() = default;
+
+public:
+  const Param &param(void) const { return _param; }
+
+public:
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace ReduceSum
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_REDUCESUM_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Reshape.cc b/runtime/contrib/pure_arm_compute/src/internal/op/Reshape.cc
new file mode 100644
index 000000000..862ed30c7
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Reshape.cc
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/Reshape.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Reshape
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Reshape
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Reshape
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 2 && outputCount == 1);
+
+  output_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> A tensor, specifying the tensor to be reshaped.
+  //  1 -> A 1-D tensor of type ANEURALNETWORKS_TENSOR_INT32, defining the shape of the output
+  //  tensor
+  input_index = inputs[0];
+  shape_index = inputs[1];
+}
+
+} // namespace Reshape
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Reshape.h b/runtime/contrib/pure_arm_compute/src/internal/op/Reshape.h
new file mode 100644
index 000000000..7152eaece
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Reshape.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Reshape.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief This file defines Reshape node
+ */
+
+#ifndef __INTERNAL_OP_RESHAPE_H__
+#define __INTERNAL_OP_RESHAPE_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Reshape
+{
+
+/**
+ * @brief Struct to manipulate parameter for Reshape operation
+ */
+struct Param
+{
+  int32_t output_index; //!< index for output feature map
+
+  int32_t input_index; //!< index for input feature map
+  int32_t shape_index; //!< index for shape
+
+  /**
+   * @brief Default Constructor
+   */
+  Param() = default;
+  /**
+   * @brief Construct a new Param object
+   * @param[in] inputCount the number of inputs
+   * @param[in] inputs pointer for input data
+   * @param[in] outputCount the number of outputs
+   * @param[in] outputs pointer for input data
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to define Reshape Operation
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Reshape Node object
+   * @param param Parameter for Reshape Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Default Destructor
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief Get parameter
+   * @return Param reference
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Accept a NodeVisitor so that it can visit this node
+   * @param [in] v Visitor
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param; //!< parameter for Reshape node
+};
+
+} // namespace Reshape
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_RESHAPE_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/ResizeBilinear.cc b/runtime/contrib/pure_arm_compute/src/internal/op/ResizeBilinear.cc
new file mode 100644
index 000000000..02ec20cb1
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/ResizeBilinear.cc
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/ResizeBilinear.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace ResizeBilinear
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace ResizeBilinear
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace ResizeBilinear
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 3 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> IFM Index
+  //  1 -> Height Index
+  //  2 -> Width Index
+  ifm_index = inputs[0];
+  height_index = inputs[1];
+  width_index = inputs[2];
+}
+
+} // namespace ResizeBilinear
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/ResizeBilinear.h b/runtime/contrib/pure_arm_compute/src/internal/op/ResizeBilinear.h
new file mode 100644
index 000000000..f2eab4aaf
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/ResizeBilinear.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    ResizeBilinear.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines internal::tflite::op::ResizeBilinear::Param struct
+ *          and internal::tflite::op::ResizeBilinear::Node class
+ */
+#ifndef __INTERNAL_OP_RESIZE_BILINEAR_H__
+#define __INTERNAL_OP_RESIZE_BILINEAR_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace ResizeBilinear
+{
+
+/**
+ * @brief Struct to have indexes for ResizeBilinear operation parameter
+ */
+struct Param
+{
+  int32_t ofm_index; /**< Index of output feature map */
+
+  int32_t ifm_index;    /**< Index of input feature map */
+  int32_t height_index; /**< Index of height */
+  int32_t width_index;  /**< Index of width */
+  /**
+   * @brief Construct as default
+   */
+  Param() = default;
+  /**
+   * @brief Construct a new Param object with params
+   * @param[in] inputCount  Count of inputs
+   * @param[in] inputs      Pointer of inputs
+   * @param[in] outputCount Count of outputs
+   * @param[in] outputs     Pointer of outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to represent an ResizeBilinear operation of data structure
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Node object with param
+   * @param[in] param Param object that makes up a Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destruct as default
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief  Get a reference of Param object
+   * @return Reference of Param object
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Visit this Node by NodeVisitor
+   * @param[in] v Visitor
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace ResizeBilinear
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_RESIZE_BILINEAR_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Rnn.cc b/runtime/contrib/pure_arm_compute/src/internal/op/Rnn.cc
new file mode 100644
index 000000000..3f19fca3b
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Rnn.cc
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/Rnn.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace RNN
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace RNN
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace RNN
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 6 && outputCount == 2);
+
+  output_index = outputs[0];
+  hidden_state_out_index = outputs[1];
+
+  input_index = inputs[0];
+  weights_index = inputs[1];
+  recurrent_weights_index = inputs[2];
+  bias_index = inputs[3];
+  hidden_state_in_index = inputs[4];
+  fused_activation_index = inputs[5];
+}
+
+} // namespace RNN
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Rnn.h b/runtime/contrib/pure_arm_compute/src/internal/op/Rnn.h
new file mode 100644
index 000000000..7b2a10843
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Rnn.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Rnn.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief This file defines RNN node
+ */
+
+#ifndef __INTERNAL_OP_RNN_H__
+#define __INTERNAL_OP_RNN_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace RNN
+{
+
+/**
+ * @brief Struct to manipulate parameter for RNN operation
+ */
+struct Param
+{
+  int32_t output_index;           //!< index for ouuput
+  int32_t hidden_state_out_index; //!< index for hidden state output
+
+  int32_t input_index;             //!< index for input
+  int32_t weights_index;           //!< index for weight
+  int32_t recurrent_weights_index; //!< index for recurrent weights
+  int32_t bias_index;              //!< index for bias
+  int32_t hidden_state_in_index;   //!< index for hidden state input
+  int32_t fused_activation_index;  //!< index for fused activation
+
+  /**
+   * @brief Default Constructor
+   */
+  Param() = default;
+  /**
+   * @brief Construct a new Param object
+   * @param[in] inputCount the number of inputs
+   * @param[in] inputs pointer for input data
+   * @param[in] outputCount the number of outputs
+   * @param[in] outputs pointer for input data
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to define RNN Operation
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new RNN Node object
+   * @param param Parameter for RNN Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Default Destructor
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief Get parameter
+   * @return Param reference
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Accept a NodeVisitor so that it can visit this node
+   * @param [in] v Visitor
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param; //!< parameter for RNN node
+};
+
+} // namespace RNN
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_RNN_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/SQRT.cc b/runtime/contrib/pure_arm_compute/src/internal/op/SQRT.cc
new file mode 100644
index 000000000..70ce42e9c
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/SQRT.cc
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/SQRT.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace SQRT
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace SQRT
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace SQRT
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 1 && outputCount == 1);
+
+  output_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //  0 -> input Tensor Index
+  input_index = inputs[0];
+}
+
+} // namespace SQRT
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/SQRT.h b/runtime/contrib/pure_arm_compute/src/internal/op/SQRT.h
new file mode 100644
index 000000000..85dfb97a7
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/SQRT.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    SQRT.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines internal::tflite::op::SQRT::Param struct
+ *          and internal::tflite::op::SQRT::Node class
+ */
+#ifndef __INTERNAL_OP_SQRT_H__
+#define __INTERNAL_OP_SQRT_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace SQRT
+{
+
+/**
+ * @brief Struct to have indexes for operation parameter
+ */
+struct Param
+{
+  int32_t output_index; /**< Index of output feature map */
+
+  int32_t input_index; /**< Index of input feature map */
+  /**
+   * @brief Construct as default
+   */
+  Param() = default;
+  /**
+   * @brief     Construct a new Param object with params
+   * @param[in] inputCount  Count of inputs
+   * @param[in] inputs      Pointer of inputs
+   * @param[in] outputCount Count of outputs
+   * @param[in] outputs     Pointer of outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to represent an operation of data structure
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief     Construct a new Node object with param
+   * @param[in] param Param object that makes up a Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destruct as default
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief  Get a reference of Param object
+   * @return Reference of Param object
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief  Visit this Node by NodeVisitor
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace SQRT
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_SQRT_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Softmax.cc b/runtime/contrib/pure_arm_compute/src/internal/op/Softmax.cc
new file mode 100644
index 000000000..516a0fa04
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Softmax.cc
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/Softmax.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Softmax
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Softmax
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Softmax
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 2 && outputCount == 1);
+
+  output_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> A 2-D or 4-D tensor, specifying the tensor to be reshaped.
+  //  1 ->  FLOAT32 value, specifying the positive scaling factor for the exponent, beta.
+  input_index = inputs[0];
+  scale_index = inputs[1];
+}
+
+} // namespace Softmax
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Softmax.h b/runtime/contrib/pure_arm_compute/src/internal/op/Softmax.h
new file mode 100644
index 000000000..6e631af5f
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Softmax.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Softmax.h
+ * @brief This file contains accept function and params for Softmax operation
+ * @ingroup COM_AI_RUNTIME
+ */
+
+#ifndef __INTERNAL_OP_SOFTMAX_H__
+#define __INTERNAL_OP_SOFTMAX_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Softmax
+{
+
+/**
+ * @brief Struct of Softmax operation's param
+ */
+struct Param
+{
+  int32_t output_index; /**< Output index */
+
+  int32_t input_index; /**< Input index */
+  int32_t scale_index; /**< Scale index */
+
+  /**
+   * @brief Construct a new Param object for Softmax as default
+   */
+  Param() = default;
+
+  /**
+   * @brief Construct a new Param object for Softmax with params
+   * @param [in] inputCount The number of input
+   * @param [in] inputs Array containing inputs
+   * @param [in] outputCount The number of output
+   * @param [in] outputs Array containing outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to define operation node for Softmax
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Node object for Softmax with param
+   * @param [in] param Parameters for Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destroy the Node object for Softmax
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief Get parameters for Softmax
+   * @return Parameters of Softmax
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Function for accepting node for Softmax
+   * @param [in] v Node visitor for invoking visit function of Softmax
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace Softmax
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_SOFTMAX_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/SpaceToBatchND.cc b/runtime/contrib/pure_arm_compute/src/internal/op/SpaceToBatchND.cc
new file mode 100644
index 000000000..9ab026cf4
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/SpaceToBatchND.cc
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/SpaceToBatchND.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace SpaceToBatchND
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace SpaceToBatchND
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace SpaceToBatchND
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 3 && outputCount == 1);
+
+  output_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> Input Tensor Index
+  //  1 -> Block size Index
+  //  2 -> Padding size Index
+  input_index = inputs[0];
+  block_size_index = inputs[1];
+  padding_size_index = inputs[2];
+}
+
+} // namespace SpaceToBatchND
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/SpaceToBatchND.h b/runtime/contrib/pure_arm_compute/src/internal/op/SpaceToBatchND.h
new file mode 100644
index 000000000..650d068f4
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/SpaceToBatchND.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __INTERNAL_OP_SPACETOBATCHND_H__
+#define __INTERNAL_OP_SPACETOBATCHND_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace SpaceToBatchND
+{
+
+struct Param
+{
+  int32_t output_index;
+
+  int32_t input_index;
+  int32_t block_size_index;
+  int32_t padding_size_index;
+
+  Param() = default;
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+class Node final : public op::Node
+{
+public:
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  virtual ~Node() = default;
+
+public:
+  const Param &param(void) const { return _param; }
+
+public:
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace SpaceToBatchND
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_SPACETOBATCHND_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/SpaceToDepth.cc b/runtime/contrib/pure_arm_compute/src/internal/op/SpaceToDepth.cc
new file mode 100644
index 000000000..2fb587be0
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/SpaceToDepth.cc
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/SpaceToDepth.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace SpaceToDepth
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace SpaceToDepth
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace SpaceToDepth
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 2 && outputCount == 1);
+
+  output_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> Input Tensor Index
+  //  1 -> Block size Index
+  input_index = inputs[0];
+  block_size_index = inputs[1];
+}
+
+} // namespace SpaceToDepth
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/SpaceToDepth.h b/runtime/contrib/pure_arm_compute/src/internal/op/SpaceToDepth.h
new file mode 100644
index 000000000..2e624006a
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/SpaceToDepth.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file SpaceToDepth.h
+ * @brief This file contains accept function and params for SpaceToDepth operation
+ * @ingroup COM_AI_RUNTIME
+ */
+
+#ifndef __INTERNAL_OP_SPACETODEPTH_H__
+#define __INTERNAL_OP_SPACETODEPTH_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace SpaceToDepth
+{
+
+/**
+ * @brief Struct of SpaceToDepth operation's param
+ */
+struct Param
+{
+  int32_t output_index; /**< Output index */
+
+  int32_t input_index;      /**< Input index */
+  int32_t block_size_index; /**< Block size index */
+
+  /**
+   * @brief Construct a new Param object for SpaceToDepth as default
+   */
+  Param() = default;
+
+  /**
+   * @brief Construct a new Param object for SpaceToDepth with params
+   * @param [in] inputCount The number of input
+   * @param [in] inputs Array containing inputs
+   * @param [in] outputCount The number of output
+   * @param [in] outputs Array containing outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to define operation node for SpaceToDepth
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Node object for SpaceToDepth with param
+   * @param [in] param Parameters for Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destroy the Node object for SpaceToDepth
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief Get parameters for SpaceToDepth
+   * @return Parameters of SpaceToDepth
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Function for accepting node for SpaceToDepth
+   * @param [in] v Node visitor for invoking visit function of SpaceToDepth
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace SpaceToDepth
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_SPACETODEPTH_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Split.cc b/runtime/contrib/pure_arm_compute/src/internal/op/Split.cc
new file mode 100644
index 000000000..6457a106a
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Split.cc
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/Split.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Split
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Split
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Split
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 3);
+
+  // Each input should be interpreted as follows:
+  //  0 -> An n-D tensor, specifying the tensor to be split.
+  //  1 -> A 0-D int32 tensor, indicating the dimension along which to split.
+  //  2 -> A 0-D int32 tensor, indicating the number of outputs
+  //       (It can be ignored on pacl becasue pacl don't support dynamic tensor shape,
+  //        and can be used for verification only)
+  ifm_index = inputs[0];
+  axis_index = inputs[1];
+
+  // Each output should be interpreted as follow:
+  //  [0, outputCount) -> An n-D tensor.
+  for (uint32_t n = 0; n < outputCount; ++n)
+  {
+    ofm_indexes.emplace_back(outputs[n]);
+  }
+}
+
+} // namespace Split
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Split.h b/runtime/contrib/pure_arm_compute/src/internal/op/Split.h
new file mode 100644
index 000000000..cb5f3eb2d
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Split.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Split.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief This file defines Split node
+ */
+
+#ifndef __INTERNAL_OP_SPLIT_H__
+#define __INTERNAL_OP_SPLIT_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+#include <vector>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Split
+{
+
+/**
+ * @brief Struct to manipulate parameter for Split operation
+ */
+struct Param
+{
+  int32_t ifm_index;  //!< index for input feature map
+  int32_t axis_index; //!< index for axis
+
+  std::vector<int32_t> ofm_indexes; //!< index for output feature map
+
+  /**
+   * @brief Default Constructor
+   */
+  Param() = default;
+  /**
+   * @brief Construct a new Param object
+   * @param[in] inputCount the number of inputs
+   * @param[in] inputs pointer for input data
+   * @param[in] outputCount the number of outputs
+   * @param[in] outputs pointer for input data
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to define Split Operation
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Split Node object
+   * @param param Parameter for Split Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Default Destructor
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief Get parameter
+   * @return Param reference
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Accept a NodeVisitor so that it can visit this node
+   * @param [in] v Visitor
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param; //!< parameter for Split node
+};
+
+} // namespace Split
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_SPLIT_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/SquaredDifference.cc b/runtime/contrib/pure_arm_compute/src/internal/op/SquaredDifference.cc
new file mode 100644
index 000000000..f6c8bc5df
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/SquaredDifference.cc
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/SquaredDifference.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace SquaredDifference
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace SquaredDifference
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace SquaredDifference
+{
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 2 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> LHS Tensor Index
+  //  1 -> RHS Tensor Index
+  lhs_index = inputs[0];
+  rhs_index = inputs[1];
+}
+
+} // namespace SquaredDifference
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/SquaredDifference.h b/runtime/contrib/pure_arm_compute/src/internal/op/SquaredDifference.h
new file mode 100644
index 000000000..ecbb03209
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/SquaredDifference.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    SquaredDifference.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines internal::tflite::op::SquaredDifference::Param struct
+ *          and internal::tflite::op::SquaredDifference::Node class
+ */
+#ifndef __INTERNAL_OP_SQUAREDDIFFERENCE_H__
+#define __INTERNAL_OP_SQUAREDDIFFERENCE_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace SquaredDifference
+{
+
+/**
+ * @brief Struct to have indexes for operation parameter
+ */
+struct Param
+{
+  int32_t ofm_index; /**< Index of output feature map */
+
+  int32_t lhs_index; /**< Index of lhs */
+  int32_t rhs_index; /**< Index of rhs */
+  /**
+   * @brief Construct as default
+   */
+  Param() = default;
+  /**
+   * @brief Construct a new Param object with params
+   * @param[in] inputCount  Count of inputs
+   * @param[in] inputs      Pointer of inputs
+   * @param[in] outputCount Count of outputs
+   * @param[in] outputs     Pointer of outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to represent an operation of data structure
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Node object with param
+   * @param[in] param Param object that makes up a Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destruct as default
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief  Get a reference of Param object
+   * @return Reference of Param object
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Visit this Node by NodeVisitor
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace SquaredDifference
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_SQUAREDDIFFERENCE_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Squeeze.cc b/runtime/contrib/pure_arm_compute/src/internal/op/Squeeze.cc
new file mode 100644
index 000000000..6e89cd321
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Squeeze.cc
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/Squeeze.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Squeeze
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Squeeze
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Squeeze
+{
+// dims_index is optional input
+// if dims_index is not provided, dims_index is set to -1
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 1 || inputCount == 2);
+  assert(outputCount == 1);
+
+  output_index = outputs[0];
+
+  input_index = inputs[0];
+
+  // dims_index_optional = -1 by default
+  if (inputCount == 2)
+    dims_index_optional = inputs[1];
+}
+
+} // namespace Squeeze
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Squeeze.h b/runtime/contrib/pure_arm_compute/src/internal/op/Squeeze.h
new file mode 100644
index 000000000..d5f36f85f
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Squeeze.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    Squeeze.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief   This file defines internal::tflite::op::Squeeze::Param struct
+ *          and internal::tflite::op::Squeeze::Node class
+ */
+#ifndef __INTERNAL_OP_SQUEEZE_H__
+#define __INTERNAL_OP_SQUEEZE_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Squeeze
+{
+
+/**
+ * @brief Struct to have indexes for operation parameter
+ */
+struct Param
+{
+  int32_t output_index; /**< Index of output feature map */
+
+  int32_t input_index; /**< Index of input feature map */
+  // optional param. default is -1
+  int32_t dims_index_optional = -1; /**< Index of dims */
+  /**
+   * @brief Construct as default
+   */
+  Param() = default;
+  /**
+   * @brief Construct a new Param object with params
+   * @param[in] inputCount  Count of inputs
+   * @param[in] inputs      Pointer of inputs
+   * @param[in] outputCount Count of outputs
+   * @param[in] outputs     Pointer of outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to represent an operation of data structure
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Node object with param
+   * @param[in] param Param object that makes up a Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destruct as default
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief  Get a reference of Param object
+   * @return Reference of Param object
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Visit this Node by NodeVisitor
+   * @param[in] v Visitor
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace Squeeze
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_SQUEEZE_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/StridedSlice.cc b/runtime/contrib/pure_arm_compute/src/internal/op/StridedSlice.cc
new file mode 100644
index 000000000..6e7958954
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/StridedSlice.cc
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/StridedSlice.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace StridedSlice
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace StridedSlice
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace StridedSlice
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 7 && outputCount == 1);
+
+  outputData_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> An n-D tensor, specifying the tensor to be sliced.
+  //  1 -> A 1-D Tensor of {@link ANEURALNETWORKS_TENSOR_INT32}, the starts of
+  //       the dimensions of the input tensor to be sliced. The length must be
+  //       of rank(input0).
+  //  2 -> A 1-D Tensor of {@link ANEURALNETWORKS_TENSOR_INT32}, the ends of
+  //       the dimensions of the input tensor to be sliced. The length must be
+  //       of rank(input0).
+  //  3 -> A 1-D Tensor of {@link ANEURALNETWORKS_TENSOR_INT32}, the strides of
+  //       the dimensions of the input tensor to be sliced. The length must be
+  //       of rank(input0).
+  //  4 -> An {@link ANEURALNETWORKS_INT32} scalar, begin_mask. If the ith bit
+  //       of begin_mask is set, begin[i] is ignored and the fullest possible
+  //       range in that dimension is used instead.
+  //  5 -> An {@link ANEURALNETWORKS_INT32} scalar, end_mask. If the ith bit of
+  //       end_mask is set, end[i] is ignored and the fullest possible range in
+  //       that dimension is used instead.
+  //  6 -> An {@link ANEURALNETWORKS_INT32} scalar, shrink_axis_mask. An int32
+  //       mask. If the ith bit of shrink_axis_mask is set, it implies that the
+  //       ith specification shrinks the dimensionality by 1. A slice of size 1
+  //       starting from begin[i] in the dimension must be preserved.
+  inputData_index = inputs[0];
+  startData_index = inputs[1];
+  endData_index = inputs[2];
+  stridesData_index = inputs[3];
+  beginMask_index = inputs[4];
+  endMask_index = inputs[5];
+  shrinkAxisMask_index = inputs[6];
+}
+
+} // namespace StridedSlice
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/StridedSlice.h b/runtime/contrib/pure_arm_compute/src/internal/op/StridedSlice.h
new file mode 100644
index 000000000..21dbb9e68
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/StridedSlice.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file StridedSlice.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief This file defines StridedSlice node
+ */
+
+#ifndef __INTERNAL_OP_STRIDEDSLICE_H__
+#define __INTERNAL_OP_STRIDEDSLICE_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace StridedSlice
+{
+
+/**
+ * @brief Struct to manipulate parameter for StridedSlice operation
+ */
+struct Param
+{
+  int32_t outputData_index; //!< index for output data
+
+  int32_t inputData_index;      //!< index for input data
+  int32_t startData_index;      //!< index where slicing start from
+  int32_t endData_index;        //!< index where slicing ends to
+  int32_t stridesData_index;    //!< index for stride value
+  int32_t beginMask_index;      //!< index for beginmask
+  int32_t endMask_index;        //!< index for endmask
+  int32_t shrinkAxisMask_index; //!< index for shrink axis
+
+  /**
+   * @brief Default Constructor
+   */
+  Param() = default;
+  /**
+   * @brief Construct a new Param object
+   * @param[in] inputCount the number of inputs
+   * @param[in] inputs pointer for input data
+   * @param[in] outputCount the number of outputs
+   * @param[in] outputs pointer for input data
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to define StridedSlice Operation
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new StridedSlice Node object
+   * @param param Parameter for StridedSlice Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Default Destructor
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief Get parameter
+   * @return Param reference
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Accept a NodeVisitor so that it can visit this node
+   * @param [in] v Visitor
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param; //!< parameter for StridedSlice node
+};
+
+} // namespace StridedSlice
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_STRIDEDSLICE_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Sub.cc b/runtime/contrib/pure_arm_compute/src/internal/op/Sub.cc
new file mode 100644
index 000000000..74efe3c3a
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Sub.cc
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/Sub.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Sub
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Sub
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Sub
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 3 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> LHS Tensor Index
+  //  1 -> RHS Tensor Index
+  //  2 -> Activation Index
+  lhs_index = inputs[0];
+  rhs_index = inputs[1];
+  activation_index = inputs[2];
+}
+
+} // namespace Sub
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Sub.h b/runtime/contrib/pure_arm_compute/src/internal/op/Sub.h
new file mode 100644
index 000000000..864359d1e
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Sub.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Sub.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief This file defines SUB Node
+ */
+
+#ifndef __INTERNAL_OP_SUB_H__
+#define __INTERNAL_OP_SUB_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Sub
+{
+
+/**
+ * @brief Struct to manipulate parameters for SUB
+ */
+struct Param
+{
+  int32_t ofm_index; //!< index for output feature map
+
+  int32_t lhs_index;        //!< index for left-hand side
+  int32_t rhs_index;        //!< index for right-hand side
+  int32_t activation_index; //!< index for activation function
+
+  /**
+   * @brief Default Constructor
+   */
+  Param() = default;
+  /**
+   * @brief Construct a new Param object
+   * @param[in] inputCount the number of inputs
+   * @param[in] inputs pointer for input data
+   * @param[in] outputCount the number of outputs
+   * @param[in] outputs pointer for input data
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to define SUB Operation
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Sub Node object
+   * @param param Parameter for Sub Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Default Destructor
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief Get parameter
+   * @return Param reference
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Accept a NodeVisitor so that it can visit this node
+   * @param [in] v Visitor
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param; //!< parameter for SUB node
+};
+
+} // namespace Sub
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_SUB_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Tanh.cc b/runtime/contrib/pure_arm_compute/src/internal/op/Tanh.cc
new file mode 100644
index 000000000..fbd72abe4
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Tanh.cc
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/Tanh.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Tanh
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Tanh
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Tanh
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 1 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> Input Tensor Index
+  ifm_index = inputs[0];
+}
+
+} // namespace Tanh
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Tanh.h b/runtime/contrib/pure_arm_compute/src/internal/op/Tanh.h
new file mode 100644
index 000000000..fd87297f1
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Tanh.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Tanh.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief This file defines TANH node
+ */
+
+#ifndef __INTERNAL_OP_TANH_H__
+#define __INTERNAL_OP_TANH_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Tanh
+{
+
+/**
+ * @brief Struct to manipulate parameter for hyperbolic tangent operation
+ */
+struct Param
+{
+  int32_t ofm_index; //!< index for output feature map
+
+  int32_t ifm_index; //!< index for input feature map
+
+  /**
+   * @brief Default Constructor
+   */
+  Param() = default;
+  /**
+   * @brief Construct a new Param object
+   * @param[in] inputCount the number of inputs
+   * @param[in] inputs pointer for input data
+   * @param[in] outputCount the number of outputs
+   * @param[in] outputs pointer for input data
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to define Tanh Operation
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Tanh Node object
+   * @param param Parameter for Tanh Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Default Destructor
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief Get parameter
+   * @return Param reference
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Accept a NodeVisitor so that it can visit this node
+   * @param [in] v Visitor
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param; //!< parameter for Tanh node
+};
+
+} // namespace Tanh
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_TANH_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/TopKV2.cc b/runtime/contrib/pure_arm_compute/src/internal/op/TopKV2.cc
new file mode 100644
index 000000000..74d9a69d2
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/TopKV2.cc
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/TopKV2.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace TopKV2
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace TopKV2
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace TopKV2
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 2 && outputCount == 2);
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> Index for Output Values
+  //  1 -> Index for Output Indices
+  outputValues_index = outputs[0];
+  outputIndices_index = outputs[1];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> Index for Input Data
+  //  1 -> Index for K
+  inputData_index = inputs[0];
+  k_index = inputs[1];
+}
+
+} // namespace TopKV2
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/TopKV2.h b/runtime/contrib/pure_arm_compute/src/internal/op/TopKV2.h
new file mode 100644
index 000000000..02b7827e9
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/TopKV2.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file TopKV2.h
+ * @brief This file contains accept function and params for TopKV2 operation
+ * @ingroup COM_AI_RUNTIME
+ */
+
+#ifndef __INTERNAL_OP_TOPKV2_H__
+#define __INTERNAL_OP_TOPKV2_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace TopKV2
+{
+
+/**
+ * @brief Struct of TopKV2 operation's param
+ */
+struct Param
+{
+  int32_t outputValues_index;  /**< Output values index */
+  int32_t outputIndices_index; /**< Output indices index */
+
+  int32_t inputData_index; /**< Input data index */
+  int32_t k_index;         /**< K value index */
+
+  /**
+   * @brief Construct a new Param object for TopKV2 as default
+   */
+  Param() = default;
+
+  /**
+   * @brief Construct a new Param object for TopKV2 with params
+   * @param [in] inputCount The number of input
+   * @param [in] inputs Array containing inputs
+   * @param [in] outputCount The number of output
+   * @param [in] outputs Array containing outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to define operation node for TopKV2
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Node object for TopKV2 with param
+   * @param [in] param Parameters for Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destroy the Node object for TopKV2
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief Get parameters for TopKV2
+   * @return Parameters of TopKV2
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Function for accepting node for TopKV2
+   * @param [in] v Node visitor for invoking visit function of TopKV2
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace TopKV2
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_TOPKV2_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Transpose.cc b/runtime/contrib/pure_arm_compute/src/internal/op/Transpose.cc
new file mode 100644
index 000000000..0529e3790
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Transpose.cc
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/Transpose.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Transpose
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Transpose
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Transpose
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 2 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> Input Tensor Index
+  //  1 -> Permutation Tensor Index
+  ifm_index = inputs[0];
+  permu_index = inputs[1];
+}
+
+} // namespace Transpose
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Transpose.h b/runtime/contrib/pure_arm_compute/src/internal/op/Transpose.h
new file mode 100644
index 000000000..bb01bf322
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Transpose.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Transpose.h
+ * @brief This file contains accept function and params for Transpose operation
+ * @ingroup COM_AI_RUNTIME
+ */
+
+#ifndef __INTERNAL_OP_TRANSPOSE_H__
+#define __INTERNAL_OP_TRANSPOSE_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Transpose
+{
+
+/**
+ * @brief Struct of Transpose operation's param
+ */
+struct Param
+{
+  int32_t ofm_index; /**< Output format index */
+
+  int32_t ifm_index;   /**< Input format index */
+  int32_t permu_index; /**< Permutation index */
+
+  /**
+   * @brief Construct a new Param object for Transpose as default
+   */
+  Param() = default;
+
+  /**
+   * @brief Construct a new Param object for Transpose with params
+   * @param [in] inputCount The number of input
+   * @param [in] inputs Array containing inputs
+   * @param [in] outputCount The number of output
+   * @param [in] outputs Array containing outputs
+   */
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+/**
+ * @brief Class to define operation node for Transpose
+ */
+class Node final : public op::Node
+{
+public:
+  /**
+   * @brief Construct a new Node object for Transpose with param
+   * @param [in] param Parameters for Node
+   */
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Destroy the Node object for Transpose
+   */
+  virtual ~Node() = default;
+
+public:
+  /**
+   * @brief Get parameters for Transpose
+   * @return Parameters of Transpose
+   */
+  const Param &param(void) const { return _param; }
+
+public:
+  /**
+   * @brief Function for accepting node for Transpose
+   * @param [in] v Node visitor for invoking visit function of Transpose
+   * @return N/A
+   */
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace Transpose
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_TRANSPOSE_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/TransposeConv.cc b/runtime/contrib/pure_arm_compute/src/internal/op/TransposeConv.cc
new file mode 100644
index 000000000..502eff525
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/TransposeConv.cc
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/TransposeConv.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace TransposeConv
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace TransposeConv
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace TransposeConv
+{
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 6 && outputCount == 1);
+
+  ofm_index = outputs[0];
+
+  // Each input should be interpreted as follows:
+  //
+  //  0 -> Output Shape Index
+  //  1 -> Weights Index
+  //  2 -> Input Tensor Index
+  //  3 -> Padding Type
+  //  4 -> Stride width
+  //  5 -> Stride height
+
+  op_shape_index = inputs[0];
+  ker_index = inputs[1];
+  ifm_index = inputs[2];
+  padding_index = inputs[3];
+  hstride_index = inputs[4];
+  vstride_index = inputs[5];
+}
+
+} // namespace TransposeConv
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/TransposeConv.h b/runtime/contrib/pure_arm_compute/src/internal/op/TransposeConv.h
new file mode 100644
index 000000000..b0122f82d
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/TransposeConv.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __INTERNAL_OP_TRANSPOSECONV_H__
+#define __INTERNAL_OP_TRANSPOSECONV_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace TransposeConv
+{
+
+struct Param
+{
+  int32_t ofm_index;
+
+  int32_t op_shape_index;
+  int32_t ker_index;
+  int32_t ifm_index;
+  int32_t padding_index;
+  int32_t hstride_index;
+  int32_t vstride_index;
+
+  Param() = default;
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+class Node final : public op::Node
+{
+public:
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  virtual ~Node() = default;
+
+public:
+  const Param &param(void) const { return _param; }
+
+public:
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace TransposeConv
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_TRANSPOSECONV_H__
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Unpack.cc b/runtime/contrib/pure_arm_compute/src/internal/op/Unpack.cc
new file mode 100644
index 000000000..a1be0280c
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Unpack.cc
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "internal/op/Unpack.h"
+#include "internal/op/NodeVisitor.h"
+
+#include <cassert>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Unpack
+{
+
+void Node::accept(NodeVisitor &&v) const { v.visit(*this); }
+
+} // namespace Unpack
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Unpack
+{
+// There are three inputs: tensor which is to be unpacked,
+// axis along which tensor needs to be unpacked
+// and number of splits along the axis.
+
+Param::Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+             const uint32_t *outputs)
+{
+  assert(inputCount == 3);
+
+  ifm_index = inputs[0];
+
+  for (uint32_t n = 0; n < outputCount; ++n)
+  {
+    ofm_indexes.emplace_back(outputs[n]);
+  }
+  num_split_index = inputs[1];
+  axis_index = inputs[2];
+}
+
+} // namespace Unpack
+} // namespace op
+} // namespace tflite
+} // namespace internal
diff --git a/runtime/contrib/pure_arm_compute/src/internal/op/Unpack.h b/runtime/contrib/pure_arm_compute/src/internal/op/Unpack.h
new file mode 100644
index 000000000..575e3d024
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/internal/op/Unpack.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __INTERNAL_OP_UNPACK_H__
+#define __INTERNAL_OP_UNPACK_H__
+
+#include "internal/op/Node.h"
+
+#include <cstdint>
+#include <vector>
+
+namespace internal
+{
+namespace tflite
+{
+namespace op
+{
+namespace Unpack
+{
+
+struct Param
+{
+  int32_t ifm_index;
+  int32_t axis_index;
+  int32_t num_split_index;
+  // There are N outputs after Unpacking Input Tensor along axis
+  std::vector<int32_t> ofm_indexes;
+
+  Param() = default;
+  Param(uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount, const uint32_t *outputs);
+};
+
+class Node final : public op::Node
+{
+public:
+  Node(const Param &param) : _param(param)
+  {
+    // DO NOTHING
+  }
+
+public:
+  virtual ~Node() = default;
+
+public:
+  const Param &param(void) const { return _param; }
+
+public:
+  void accept(NodeVisitor &&) const override;
+
+private:
+  const Param _param;
+};
+
+} // namespace Unpack
+} // namespace op
+} // namespace tflite
+} // namespace internal
+
+#endif // __INTERNAL_OP_UNPACK_H__
diff --git a/runtime/contrib/pure_arm_compute/src/library_info.cc b/runtime/contrib/pure_arm_compute/src/library_info.cc
new file mode 100644
index 000000000..02a616094
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/library_info.cc
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+volatile static const char info[] = "library information : runtime=pure_arm_compute";
diff --git a/runtime/contrib/pure_arm_compute/src/logging.h b/runtime/contrib/pure_arm_compute/src/logging.h
new file mode 100644
index 000000000..447da03e2
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/logging.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file logging.h
+ * @brief This file contains Context class for logging.
+ * @ingroup COM_AI_RUNTIME
+ */
+
+#ifndef __PURE_ARM_COMPUTE_LOGGING_H__
+#define __PURE_ARM_COMPUTE_LOGGING_H__
+
+#include <iostream>
+
+namespace logging
+{
+
+/**
+ * @brief class to define Context for logging
+ */
+class Context
+{
+public:
+  /**
+   * @brief Construct default
+   */
+  Context() : _enabled{false}
+  {
+    auto env = std::getenv("PURE_ARM_COMPUTE_LOG_ENABLE");
+
+    if (env && std::strtol(env, NULL, 0) > 0)
+    {
+      _enabled = true;
+    }
+  }
+
+public:
+  /**
+   * @brief Get @c true if PURE_ARM_COMPUTE_LOG_ENABLE has been set as environment value, otherwise
+   * @c false
+   * @return @c true if PURE_ARM_COMPUTE_LOG_ENABLE has been set as environment value, otherwise @c
+   * false
+   */
+  bool enabled(void) const { return _enabled; }
+
+private:
+  bool _enabled;
+};
+
+/**
+ * @brief static Context class for logging
+ */
+static Context ctx;
+
+} // namespace logging
+
+#define VERBOSE(name)           \
+  if (::logging::ctx.enabled()) \
+  std::cout << "[" << #name << "] "
+
+#endif // __PURE_ARM_COMPUTE_LOGGING_H__
diff --git a/runtime/contrib/pure_arm_compute/src/memory.cc b/runtime/contrib/pure_arm_compute/src/memory.cc
new file mode 100644
index 000000000..9e999661a
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/memory.cc
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <NeuralNetworks.h>
+#include <sys/mman.h>
+#include <memory>
+
+#include "cpp14/memory.h"
+#include "memory.h"
+
+int ANeuralNetworksMemory_createFromFd(size_t size, int protect, int fd, size_t offset,
+                                       ANeuralNetworksMemory **memory)
+{
+  if (memory == nullptr)
+  {
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  // Use unique pointer to avoid memory leak
+  std::unique_ptr<ANeuralNetworksMemory> memory_ptr =
+      nnfw::cpp14::make_unique<ANeuralNetworksMemory>(size, protect, fd, offset);
+  if (memory_ptr == nullptr)
+  {
+    return ANEURALNETWORKS_OUT_OF_MEMORY;
+  }
+  *memory = memory_ptr.release();
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+void ANeuralNetworksMemory_free(ANeuralNetworksMemory *memory) { delete memory; }
+
+//
+// ANeuralNetworksMemory
+//
+ANeuralNetworksMemory::ANeuralNetworksMemory(size_t size, int protect, int fd, size_t offset)
+{
+  _base = reinterpret_cast<uint8_t *>(mmap(nullptr, size, protect, MAP_PRIVATE, fd, offset));
+  _size = size;
+}
+
+ANeuralNetworksMemory::~ANeuralNetworksMemory() { munmap(reinterpret_cast<void *>(_base), _size); }
diff --git a/runtime/contrib/pure_arm_compute/src/memory.h b/runtime/contrib/pure_arm_compute/src/memory.h
new file mode 100644
index 000000000..ffac26ef6
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/memory.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file execution.h
+ * @brief This file defines ANeuralNetworksMemory class for handling Memory NNAPI
+ * @ingroup COM_AI_RUNTIME
+ */
+
+#ifndef __MEMORY_H__
+#define __MEMORY_H__
+
+#include <cstdint>
+
+/**
+ * @brief struct to define Memory NNAPI
+ */
+struct ANeuralNetworksMemory
+{
+public:
+  /**
+   * @brief Constructor with params
+   * @param [in] size The requested size in bytes
+   * @param [in] protect The desired memory protection for the mapping
+   * @param [in] fd The requested file descriptor
+   * @param [in] offset The offset to the beginning of the file of the area to map
+   */
+  ANeuralNetworksMemory(size_t size, int protect, int fd, size_t offset);
+  /**
+   * @brief Destructor default
+   */
+  ~ANeuralNetworksMemory();
+
+public:
+  /**
+   * @brief Get size
+   * @return size
+   */
+  size_t size(void) const { return _size; }
+  /**
+   * @brief Get base pointer
+   * @return base pointer
+   */
+  uint8_t *base(void) { return _base; }
+  /**
+   * @brief Get base pointer
+   * @return const base pointer
+   */
+  const uint8_t *base(void) const { return _base; }
+
+private:
+  size_t _size;
+  uint8_t *_base;
+};
+
+#endif // __MEMORY_H__
diff --git a/runtime/contrib/pure_arm_compute/src/model.cc b/runtime/contrib/pure_arm_compute/src/model.cc
new file mode 100644
index 000000000..ddca589db
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/model.cc
@@ -0,0 +1,1082 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <NeuralNetworks.h>
+#include <NeuralNetworksEx.h>
+
+#include <cassert>
+#include <stdexcept>
+
+#include "model.h"
+#include "memory.h"
+
+int ANeuralNetworksModel_create(ANeuralNetworksModel **model)
+{
+  if (model == nullptr)
+  {
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  ANeuralNetworksModel *model_ptr = new ANeuralNetworksModel{};
+
+  if (model_ptr == nullptr)
+  {
+    return ANEURALNETWORKS_OUT_OF_MEMORY;
+  }
+
+  *model = model_ptr;
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+void ANeuralNetworksModel_free(ANeuralNetworksModel *model) { delete model; }
+
+int ANeuralNetworksModel_addOperand(ANeuralNetworksModel *model,
+                                    const ANeuralNetworksOperandType *type)
+{
+  if ((model == nullptr) || (type == nullptr))
+  {
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  if (model->isFinished())
+  {
+    return ANEURALNETWORKS_BAD_STATE;
+  }
+
+  if (type->type == ANEURALNETWORKS_TENSOR_QUANT8_ASYMM)
+  {
+    // Quantized:
+    //  scale: a 32 bit floating point value greater than zero
+    //  zeroPoint: a 32 bit integer, in range [0, 255]
+    if (type->scale <= 0.0f)
+    {
+      return ANEURALNETWORKS_BAD_DATA;
+    }
+
+    if (type->zeroPoint < 0 || type->zeroPoint > 255)
+    {
+      return ANEURALNETWORKS_BAD_DATA;
+    }
+  }
+  // NOTE Validation of scale and zeroPoint would be skipped for a while.
+  //      We do not know whether scalar type can have scale and zeroPoint.
+  //      To pass ValidationTest and GeneratedTest, this validation code
+  //      would not be implemented until we can define this issue clearly.
+  //
+  // scale and zeroPoint should be zero for scalars and non-fixed point tensors
+  // else if ((type->scale != 0.0f) || (type->zeroPoint != 0))
+  // {
+  //   return ANEURALNETWORKS_BAD_DATA;
+  // }
+
+  // scalar is ANEURALNETWORKS_FLOAT32, ANEURALNETWORKS_INT32 or ANEURALNETWORKS_UINT32.
+  // ANEURALNETWORKS_TENSOR_FLOAT32, ANEURALNETWORKS_TENSOR_INT32 and
+  // ANEURALNETWORKS_TENSOR_QUANT8_ASYMM are not scalar
+  //
+  // dimensionCount should be zero for scalars
+  if (type->dimensionCount != 0 &&
+      (type->type == ANEURALNETWORKS_FLOAT32 || type->type == ANEURALNETWORKS_INT32 ||
+       type->type == ANEURALNETWORKS_UINT32))
+  {
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  // ASSUME A tensor operand should consists of fp32 or int32 values.
+  // NOTE We do not care about scala operands.
+  assert((type->dimensionCount == 0) || (type->type == ANEURALNETWORKS_TENSOR_FLOAT32 ||
+                                         type->type == ANEURALNETWORKS_TENSOR_INT32 ||
+                                         type->type == ANEURALNETWORKS_TENSOR_QUANT8_ASYMM));
+
+  internal::tflite::operand::Shape shape(type->dimensionCount);
+
+  for (uint32_t axis = 0; axis < type->dimensionCount; ++axis)
+  {
+    shape.dim(axis) = type->dimensions[axis];
+  }
+
+  model->deref().operands().append(shape, type->type, type->scale, type->zeroPoint);
+
+  // NOTE We do NOT allocate CLTensor here as we do not how to interpret this one.
+  //      TensorFlow Lite may interpret a rank-4 tensor either as a feature map (with batch) or
+  //      a convolution kernel.
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksModel_setOperandValue(ANeuralNetworksModel *model, int32_t index,
+                                         const void *buffer, size_t length)
+{
+  if ((model == nullptr) || ((buffer == nullptr) && (length != 0)))
+  {
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  const internal::tflite::operand::Index ind{index};
+  auto &obj = model->deref().operands().at(ind);
+
+  if (buffer == nullptr)
+  {
+    using internal::tflite::operand::ExternalData;
+    obj.data<ExternalData>(reinterpret_cast<const uint8_t *>(buffer), length);
+  }
+  else
+  {
+    using internal::tflite::operand::CachedData;
+    obj.data<CachedData>(reinterpret_cast<const uint8_t *>(buffer), length);
+  }
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksModel_setOperandValueFromMemory(ANeuralNetworksModel *model, int32_t index,
+                                                   const ANeuralNetworksMemory *memory,
+                                                   size_t offset, size_t length)
+{
+  if ((model == nullptr) || (memory == nullptr))
+  {
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  const internal::tflite::operand::Index ind{index};
+  auto &obj = model->deref().operands().at(ind);
+
+  using internal::tflite::operand::ExternalData;
+
+  obj.data<ExternalData>(reinterpret_cast<const uint8_t *>(memory->base() + offset), length);
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksModel_addOperation(ANeuralNetworksModel *model,
+                                      ANeuralNetworksOperationType type, uint32_t inputCount,
+                                      const uint32_t *inputs, uint32_t outputCount,
+                                      const uint32_t *outputs)
+{
+  if (model == nullptr || inputs == nullptr || outputs == nullptr)
+  {
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  if (model->isFinished())
+  {
+    return ANEURALNETWORKS_BAD_STATE;
+  }
+
+  if (type < ANEURALNETWORKS_ADD || type > ANEURALNETWORKS_TRANSPOSE)
+  {
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  switch (type)
+  {
+    case ANEURALNETWORKS_ADD:
+    {
+      assert(inputCount == 3);
+      assert(outputCount == 1);
+
+      using internal::tflite::op::Add::Param;
+      using internal::tflite::op::Add::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_SUB:
+    {
+      assert(inputCount == 3);
+      assert(outputCount == 1);
+
+      using internal::tflite::op::Sub::Param;
+      using internal::tflite::op::Sub::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_MUL:
+    {
+      assert(inputCount == 3);
+      assert(outputCount == 1);
+
+      using internal::tflite::op::Mul::Param;
+      using internal::tflite::op::Mul::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_DIV:
+    {
+      assert(inputCount == 3);
+      assert(outputCount == 1);
+
+      using internal::tflite::op::Div::Param;
+      using internal::tflite::op::Div::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_CONV_2D:
+    {
+      // inputCount is either 7 or 10 acccording to NN API specification.
+      //  - Padding is implicit when inputCount is 7
+      //  - Padding is explicit when inputCount is 10
+      assert(inputCount == 7 || inputCount == 10);
+      assert(outputCount == 1);
+
+      if (inputCount == 7)
+      {
+        using internal::tflite::op::Conv2D::Implicit::Param;
+        using internal::tflite::op::Conv2D::Implicit::Node;
+
+        // Add 'operations'
+        auto &operations = model->deref().operations();
+
+        operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+      }
+      else
+      {
+        using internal::tflite::op::Conv2D::Explicit::Param;
+        using internal::tflite::op::Conv2D::Explicit::Node;
+
+        // Add 'operations'
+        auto &operations = model->deref().operations();
+
+        operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+      }
+
+      break;
+    }
+    case ANEURALNETWORKS_DEPTHWISE_CONV_2D:
+    {
+      // inputCount is either 8 or 11 acccording to NN API specification.
+      //  - Padding is implicit when inputCount is 8
+      //  - Padding is explicit when inputCount is 11
+      assert(inputCount == 8 || inputCount == 11);
+      assert(outputCount == 1);
+
+      if (inputCount == 8)
+      {
+        using internal::tflite::op::DepthwiseConv2D::Implicit::Param;
+        using internal::tflite::op::DepthwiseConv2D::Implicit::Node;
+
+        // Add 'operations'
+        auto &operations = model->deref().operations();
+
+        operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+      }
+      else
+      {
+        using internal::tflite::op::DepthwiseConv2D::Explicit::Param;
+        using internal::tflite::op::DepthwiseConv2D::Explicit::Node;
+
+        // Add 'operations'
+        auto &operations = model->deref().operations();
+
+        operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+      }
+
+      break;
+    }
+    case ANEURALNETWORKS_MAX_POOL_2D:
+    {
+      // inputCount is either 7 or 10 acccording to NN API specification.
+      //  - Padding is implicit when inputCount is 7
+      //  - Padding is explicit when inputCount is 10
+      assert(inputCount == 7 || inputCount == 10);
+      assert(outputCount == 1);
+
+      if (inputCount == 7)
+      {
+        using internal::tflite::op::MaxPool2D::Implicit::Param;
+        using internal::tflite::op::MaxPool2D::Implicit::Node;
+
+        // Add 'operations'
+        auto &operations = model->deref().operations();
+
+        operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+      }
+      else
+      {
+        using internal::tflite::op::MaxPool2D::Explicit::Param;
+        using internal::tflite::op::MaxPool2D::Explicit::Node;
+
+        // Add 'operations'
+        auto &operations = model->deref().operations();
+
+        operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+      }
+
+      break;
+    }
+    case ANEURALNETWORKS_DEQUANTIZE:
+    {
+      assert(outputCount == 1 && inputCount == 1);
+      using internal::tflite::op::Dequantize::Param;
+      using internal::tflite::op::Dequantize::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_AVERAGE_POOL_2D:
+    {
+      // inputCount is either 7 or 10 acccording to NN API specification.
+      //  - Padding is implicit when inputCount is 7
+      //  - Padding is explicit when inputCount is 10
+      assert(inputCount == 7 || inputCount == 10);
+      assert(outputCount == 1);
+
+      if (inputCount == 7)
+      {
+        using internal::tflite::op::AvgPool2D::Implicit::Param;
+        using internal::tflite::op::AvgPool2D::Implicit::Node;
+
+        // Add 'operations'
+        auto &operations = model->deref().operations();
+
+        operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+      }
+      else
+      {
+        using internal::tflite::op::AvgPool2D::Explicit::Param;
+        using internal::tflite::op::AvgPool2D::Explicit::Node;
+
+        // Add 'operations'
+        auto &operations = model->deref().operations();
+
+        operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+      }
+
+      break;
+    }
+    case ANEURALNETWORKS_CONCATENATION:
+    {
+      using internal::tflite::op::Concat::Param;
+      using internal::tflite::op::Concat::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_RESIZE_BILINEAR:
+    {
+      using internal::tflite::op::ResizeBilinear::Param;
+      using internal::tflite::op::ResizeBilinear::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_RESHAPE:
+    {
+      using internal::tflite::op::Reshape::Param;
+      using internal::tflite::op::Reshape::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_SQUEEZE:
+    {
+      using internal::tflite::op::Squeeze::Param;
+      using internal::tflite::op::Squeeze::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_FULLY_CONNECTED:
+    {
+      using internal::tflite::op::FullyConnected::Param;
+      using internal::tflite::op::FullyConnected::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_SOFTMAX:
+    {
+      using internal::tflite::op::Softmax::Param;
+      using internal::tflite::op::Softmax::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_RELU:
+    {
+      using internal::tflite::op::ReLU::Param;
+      using internal::tflite::op::ReLU::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_RELU1:
+    {
+      using internal::tflite::op::ReLU1::Param;
+      using internal::tflite::op::ReLU1::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_RELU6:
+    {
+      using internal::tflite::op::ReLU6::Param;
+      using internal::tflite::op::ReLU6::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_TANH:
+    {
+      using internal::tflite::op::Tanh::Param;
+      using internal::tflite::op::Tanh::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_STRIDED_SLICE:
+    {
+      using internal::tflite::op::StridedSlice::Param;
+      using internal::tflite::op::StridedSlice::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_LOGISTIC:
+    {
+      using internal::tflite::op::Logistic::Param;
+      using internal::tflite::op::Logistic::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_MEAN:
+    {
+      using internal::tflite::op::Mean::Param;
+      using internal::tflite::op::Mean::Node;
+
+      auto &operations = model->deref().operations();
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_RNN:
+    {
+      using internal::tflite::op::RNN::Param;
+      using internal::tflite::op::RNN::Node;
+
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_TRANSPOSE:
+    {
+      using internal::tflite::op::Transpose::Param;
+      using internal::tflite::op::Transpose::Node;
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_LSTM:
+    {
+      using internal::tflite::op::LSTM::Param;
+      using internal::tflite::op::LSTM::Node;
+
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_FLOOR:
+    {
+      using internal::tflite::op::Floor::Param;
+      using internal::tflite::op::Floor::Node;
+
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_PAD:
+    {
+      assert(inputCount == 2 && outputCount == 1);
+
+      using internal::tflite::op::Pad::Param;
+      using internal::tflite::op::Pad::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_SPACE_TO_DEPTH:
+    {
+      using internal::tflite::op::SpaceToDepth::Param;
+      using internal::tflite::op::SpaceToDepth::Node;
+
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_SPACE_TO_BATCH_ND:
+    {
+      using internal::tflite::op::SpaceToBatchND::Param;
+      using internal::tflite::op::SpaceToBatchND::Node;
+
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_BATCH_TO_SPACE_ND:
+    {
+      using internal::tflite::op::BatchToSpaceNd::Param;
+      using internal::tflite::op::BatchToSpaceNd::Node;
+
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_L2_POOL_2D:
+    {
+      // Input count is 7 for Implicit Padding
+      // Input count is 10 for Explicit Padding
+      assert(inputCount == 7 || inputCount == 10);
+      assert(outputCount == 1);
+
+      if (inputCount == 7)
+      {
+        using internal::tflite::op::L2Pool2D::Implicit::Param;
+        using internal::tflite::op::L2Pool2D::Implicit::Node;
+
+        // Add 'operations'
+        auto &operations = model->deref().operations();
+
+        operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+      }
+      else
+      {
+        using internal::tflite::op::L2Pool2D::Explicit::Param;
+        using internal::tflite::op::L2Pool2D::Explicit::Node;
+
+        // Add 'operations'
+        auto &operations = model->deref().operations();
+
+        operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+      }
+
+      break;
+    }
+    case ANEURALNETWORKS_EMBEDDING_LOOKUP:
+    {
+      assert(inputCount == 2);
+      assert(outputCount == 1);
+
+      using internal::tflite::op::EmbeddingLookup::Param;
+      using internal::tflite::op::EmbeddingLookup::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_L2_NORMALIZATION:
+    {
+      assert(inputCount == 1 && outputCount == 1);
+
+      using internal::tflite::op::L2Normalization::Param;
+      using internal::tflite::op::L2Normalization::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_HASHTABLE_LOOKUP:
+    {
+      assert(inputCount == 3);
+      assert(outputCount == 2);
+
+      using internal::tflite::op::HashtableLookup::Param;
+      using internal::tflite::op::HashtableLookup::Node;
+
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_LOCAL_RESPONSE_NORMALIZATION:
+    {
+
+      using internal::tflite::op::LocalResponseNormalization::Param;
+      using internal::tflite::op::LocalResponseNormalization::Node;
+
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_DEPTH_TO_SPACE:
+    {
+      using internal::tflite::op::DepthToSpace::Param;
+      using internal::tflite::op::DepthToSpace::Node;
+
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    default:
+      throw std::runtime_error{"Not supported operation"};
+  };
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksModel_addOperationEx(ANeuralNetworksModel *model,
+                                        ANeuralNetworksOperationTypeEx type, uint32_t inputCount,
+                                        const uint32_t *inputs, uint32_t outputCount,
+                                        const uint32_t *outputs)
+{
+  if ((model == nullptr) || (inputs == nullptr) || (outputs == nullptr))
+  {
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  switch (type)
+  {
+    case ANEURALNETWORKS_CAST_EX:
+    {
+      using internal::tflite::op::Cast::Param;
+      using internal::tflite::op::Cast::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_REDUCE_MIN_EX:
+    {
+      using internal::tflite::op::ReduceMin::Param;
+      using internal::tflite::op::ReduceMin::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_REDUCE_MAX_EX:
+    {
+      using internal::tflite::op::ReduceMax::Param;
+      using internal::tflite::op::ReduceMax::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_PRELU_EX:
+    {
+      using internal::tflite::op::PReLU::Param;
+      using internal::tflite::op::PReLU::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_TRANSPOSE_CONV_EX:
+    {
+      using internal::tflite::op::TransposeConv::Param;
+      using internal::tflite::op::TransposeConv::Node;
+
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_LOGICAL_AND_EX:
+    {
+      using internal::tflite::op::LogicalAnd::Param;
+      using internal::tflite::op::LogicalAnd::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_LOGICAL_OR_EX:
+    {
+      using internal::tflite::op::LogicalOr::Param;
+      using internal::tflite::op::LogicalOr::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_LOGICAL_NOT_EX:
+    {
+      using internal::tflite::op::LogicalNot::Param;
+      using internal::tflite::op::LogicalNot::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_RSQRT_EX:
+    {
+      using internal::tflite::op::RSQRT::Param;
+      using internal::tflite::op::RSQRT::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_SQRT_EX:
+    {
+      using internal::tflite::op::SQRT::Param;
+      using internal::tflite::op::SQRT::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_EQUAL_EX:
+    {
+      using internal::tflite::op::Equal::Param;
+      using internal::tflite::op::Equal::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_SQUARED_DIFFERENCE_EX:
+    {
+      using internal::tflite::op::SquaredDifference::Param;
+      using internal::tflite::op::SquaredDifference::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_TOPK_V2_EX:
+    {
+      using internal::tflite::op::TopKV2::Param;
+      using internal::tflite::op::TopKV2::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_GATHER_EX:
+    {
+      using internal::tflite::op::Gather::Param;
+      using internal::tflite::op::Gather::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_SPLIT_EX:
+    {
+      using internal::tflite::op::Split::Param;
+      using internal::tflite::op::Split::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_UNPACK_EX:
+    {
+      using internal::tflite::op::Unpack::Param;
+      using internal::tflite::op::Unpack::Node;
+
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_NEG_EX:
+    {
+      using internal::tflite::op::Neg::Param;
+      using internal::tflite::op::Neg::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_EXP_EX:
+    {
+      using internal::tflite::op::Exp::Param;
+      using internal::tflite::op::Exp::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_REDUCE_SUM_EX:
+    {
+      using internal::tflite::op::ReduceSum::Param;
+      using internal::tflite::op::ReduceSum::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_PACK_EX:
+    {
+      using internal::tflite::op::Pack::Param;
+      using internal::tflite::op::Pack::Node;
+
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_ABS_EX:
+    {
+      using internal::tflite::op::Abs::Param;
+      using internal::tflite::op::Abs::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_ARGMAX_EX:
+    {
+      using internal::tflite::op::ArgMax::Param;
+      using internal::tflite::op::ArgMax::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+    case ANEURALNETWORKS_NOT_EQUAL_EX:
+    {
+      using internal::tflite::op::NotEqual::Param;
+      using internal::tflite::op::NotEqual::Node;
+
+      // Add 'operations'
+      auto &operations = model->deref().operations();
+
+      operations.emplace_back<Node>(Param{inputCount, inputs, outputCount, outputs});
+
+      break;
+    }
+
+    default:
+      throw std::runtime_error{"Not supported operation"};
+  }
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksModel_identifyInputsAndOutputs(ANeuralNetworksModel *model, uint32_t inputCount,
+                                                  const uint32_t *inputs, uint32_t outputCount,
+                                                  const uint32_t *outputs)
+{
+  if ((model == nullptr) || (inputs == nullptr) || (outputs == nullptr))
+  {
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  if (model->isFinished())
+  {
+    return ANEURALNETWORKS_BAD_STATE;
+  }
+
+  // NOTE ::internal::tflite::operand::Index uses int as its underlying type as various NNAPI
+  //      functions such as ANeuralNetworksModel_setOperandValue use int to represent operand index
+  //
+  //      ANeuralNetworksModel_identifyInputsAndOutputs, however, uses uint32_t to represent operand
+  //      index.
+  //
+  //      Below, static_cast<int>(...) is introduced to eliminate compiler warning.
+  for (uint32_t n = 0; n < inputCount; ++n)
+  {
+    const ::internal::tflite::operand::Index ind{static_cast<int>(inputs[n])};
+    model->deref().inputs.emplace_back(ind);
+  }
+
+  for (uint32_t n = 0; n < outputCount; ++n)
+  {
+    const ::internal::tflite::operand::Index ind{static_cast<int>(outputs[n])};
+    model->deref().outputs.emplace_back(ind);
+  }
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksModel_finish(ANeuralNetworksModel *model)
+{
+  if (model == nullptr)
+  {
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  if (model->isFinished())
+  {
+    return ANEURALNETWORKS_BAD_STATE;
+  }
+
+  model->markAsFinished();
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+//
+// ANeuralNetworksModel
+//
+ANeuralNetworksModel::ANeuralNetworksModel() : _model{new internal::tflite::Model}
+{
+  // DO NOTHING
+}
diff --git a/runtime/contrib/pure_arm_compute/src/model.h b/runtime/contrib/pure_arm_compute/src/model.h
new file mode 100644
index 000000000..8acc894f4
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/src/model.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file model.h
+ * @brief This file contains ANeuralNetworksModel classe for handling Model NNAPI such as
+ * ANeuralNetworksModel_create, ANeuralNetworksModel_addOperand
+ * @ingroup COM_AI_RUNTIME
+ */
+
+#ifndef __MODEL_H__
+#define __MODEL_H__
+
+#include "internal/Model.h"
+
+/**
+ * @brief struct to express Model of NNAPI
+ */
+struct ANeuralNetworksModel
+{
+public:
+  /**
+   * @brief Construct without params
+   */
+  ANeuralNetworksModel();
+
+public:
+  /**
+   * @brief Get reference of internal::tflite::Model
+   * @return Reference of internal::tflite::Model
+   */
+  internal::tflite::Model &deref(void) { return *_model; }
+
+public:
+  /**
+   * @brief Release internal::tflite::Model pointer to param
+   * @param [in] model To get released internal::tflite::Model pointer
+   * @return N/A
+   */
+  void release(std::shared_ptr<const internal::tflite::Model> &model) { model = _model; }
+  /**
+   * @brief Get @c true if ANeuralNetworksModel_finish has been called, otherwise @c false
+   * @return @c true if ANeuralNetworksModel_finish has been called, otherwise @c false
+   */
+  bool isFinished() { return _isFinished == true; }
+  /**
+   * @brief Mark model process finished
+   * @return N/A
+   */
+  void markAsFinished() { _isFinished = true; }
+
+private:
+  std::shared_ptr<internal::tflite::Model> _model;
+  bool _isFinished{false};
+};
+
+#endif // __MODEL_H__
diff --git a/runtime/contrib/pure_arm_compute/symbolcheck.cpp b/runtime/contrib/pure_arm_compute/symbolcheck.cpp
new file mode 100644
index 000000000..d24943e10
--- /dev/null
+++ b/runtime/contrib/pure_arm_compute/symbolcheck.cpp
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <NeuralNetworks.h>
+
+#include <iostream>
+
+#define SHOW_FUNC_ENTRY(name)                                                       \
+  {                                                                                 \
+    std::cout << #name << " is at " << reinterpret_cast<void *>(name) << std::endl; \
+  }
+
+int main(int argc, char **argv)
+{
+  SHOW_FUNC_ENTRY(ANeuralNetworksMemory_createFromFd);
+  SHOW_FUNC_ENTRY(ANeuralNetworksMemory_free);
+
+  SHOW_FUNC_ENTRY(ANeuralNetworksModel_create);
+  SHOW_FUNC_ENTRY(ANeuralNetworksModel_addOperand);
+  SHOW_FUNC_ENTRY(ANeuralNetworksModel_setOperandValue);
+  SHOW_FUNC_ENTRY(ANeuralNetworksModel_setOperandValueFromMemory);
+  SHOW_FUNC_ENTRY(ANeuralNetworksModel_addOperation);
+  SHOW_FUNC_ENTRY(ANeuralNetworksModel_identifyInputsAndOutputs);
+  SHOW_FUNC_ENTRY(ANeuralNetworksModel_finish);
+  SHOW_FUNC_ENTRY(ANeuralNetworksModel_free);
+
+  SHOW_FUNC_ENTRY(ANeuralNetworksCompilation_create);
+  SHOW_FUNC_ENTRY(ANeuralNetworksCompilation_finish);
+  // ANeuralNetworksCompilation_setPreference and ANeuralNetworksCompilation_free
+  // are introduced to reuse NNAPI tests under runtimes/tests. Note that these APIs
+  // are not necessary for supporting Tensorflow Lite interperter
+  SHOW_FUNC_ENTRY(ANeuralNetworksCompilation_setPreference);
+  SHOW_FUNC_ENTRY(ANeuralNetworksCompilation_free);
+  SHOW_FUNC_ENTRY(ANeuralNetworksCompilation_create);
+
+  SHOW_FUNC_ENTRY(ANeuralNetworksExecution_create);
+  SHOW_FUNC_ENTRY(ANeuralNetworksExecution_setInput);
+  SHOW_FUNC_ENTRY(ANeuralNetworksExecution_setOutput);
+  SHOW_FUNC_ENTRY(ANeuralNetworksExecution_startCompute);
+  SHOW_FUNC_ENTRY(ANeuralNetworksExecution_free);
+
+  SHOW_FUNC_ENTRY(ANeuralNetworksEvent_wait);
+  SHOW_FUNC_ENTRY(ANeuralNetworksEvent_free);
+
+  // NOTE Pure CL runtime does not implement following NN API(s) as
+  //      Tensorflow Lite does not use these API(s)
+  // SHOW_FUNC_ENTRY(ANeuralNetworksExecution_setInputFromMemory);
+  // SHOW_FUNC_ENTRY(ANeuralNetworksExecution_setOutputFromMemory);
+
+  return 0;
+}
diff --git a/runtime/contrib/tflite_classify/CMakeLists.txt b/runtime/contrib/tflite_classify/CMakeLists.txt
new file mode 100644
index 000000000..c0bf62738
--- /dev/null
+++ b/runtime/contrib/tflite_classify/CMakeLists.txt
@@ -0,0 +1,22 @@
+if(NOT BUILD_TFLITE_CLASSIFY_APP)
+  return()
+endif(NOT BUILD_TFLITE_CLASSIFY_APP)
+
+list(APPEND SOURCES "src/tflite_classify.cc")
+list(APPEND SOURCES "src/ImageClassifier.cc")
+list(APPEND SOURCES "src/InferenceInterface.cc")
+
+## Required package
+find_package(OpenCV REQUIRED)
+find_package(Boost REQUIRED COMPONENTS system filesystem)
+
+# Without this line, this appliation couldn't search the opencv library that were already installed in ${ROOTFS_DIR}/usr/lib/arm-linux-gnueabihf directory
+set(CMAKE_EXE_LINKER_FLAGS "-Wl,--as-needed -Wl,--rpath=${ROOTFS_DIR}/usr/lib/arm-linux-gnueabihf -Wl,--rpath=${ROOTFS_DIR}/lib/arm-linux-gnueabihf")
+
+add_executable(tflite_classify ${SOURCES})
+target_include_directories(tflite_classify PRIVATE src)
+target_link_libraries(tflite_classify tensorflow-lite ${LIB_PTHREAD} dl nnfw_lib_tflite)
+target_link_libraries(tflite_classify ${Boost_LIBRARIES})
+target_link_libraries(tflite_classify ${OpenCV_LIBRARIES})
+
+install(TARGETS tflite_classify DESTINATION bin)
diff --git a/runtime/contrib/tflite_classify/src/ImageClassifier.cc b/runtime/contrib/tflite_classify/src/ImageClassifier.cc
new file mode 100644
index 000000000..fae4f066c
--- /dev/null
+++ b/runtime/contrib/tflite_classify/src/ImageClassifier.cc
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ImageClassifier.h"
+
+#include <fstream>
+#include <queue>
+#include <algorithm>
+
+ImageClassifier::ImageClassifier(const std::string &model_file, const std::string &label_file,
+                                 const int input_size, const int image_mean, const int image_std,
+                                 const std::string &input_name, const std::string &output_name,
+                                 const bool use_nnapi)
+    : _inference(new InferenceInterface(model_file, use_nnapi)), _input_size(input_size),
+      _image_mean(image_mean), _image_std(image_std), _input_name(input_name),
+      _output_name(output_name)
+{
+  // Load label
+  std::ifstream label_stream(label_file.c_str());
+  assert(label_stream);
+
+  std::string line;
+  while (std::getline(label_stream, line))
+  {
+    _labels.push_back(line);
+  }
+  _num_classes = _inference->getTensorSize(_output_name);
+  std::cout << "Output tensor size is " << _num_classes << ", label size is " << _labels.size()
+            << std::endl;
+
+  // Pre-allocate buffers
+  _fdata.reserve(_input_size * _input_size * 3);
+  _outputs.reserve(_num_classes);
+}
+
+std::vector<Recognition> ImageClassifier::recognizeImage(const cv::Mat &image)
+{
+  // Resize image
+  cv::Mat cropped;
+  cv::resize(image, cropped, cv::Size(_input_size, _input_size), 0, 0, cv::INTER_AREA);
+
+  // Preprocess the image data from 0~255 int to normalized float based
+  // on the provided parameters
+  _fdata.clear();
+  for (int y = 0; y < cropped.rows; ++y)
+  {
+    for (int x = 0; x < cropped.cols; ++x)
+    {
+      cv::Vec3b color = cropped.at<cv::Vec3b>(y, x);
+      color[0] = color[0] - (float)_image_mean / _image_std;
+      color[1] = color[1] - (float)_image_mean / _image_std;
+      color[2] = color[2] - (float)_image_mean / _image_std;
+
+      _fdata.push_back(color[0]);
+      _fdata.push_back(color[1]);
+      _fdata.push_back(color[2]);
+
+      cropped.at<cv::Vec3b>(y, x) = color;
+    }
+  }
+
+  // Copy the input data into model
+  _inference->feed(_input_name, _fdata, 1, _input_size, _input_size, 3);
+
+  // Run the inference call
+  _inference->run(_output_name);
+
+  // Copy the output tensor back into the output array
+  _inference->fetch(_output_name, _outputs);
+
+  // Find the best classifications
+  auto compare = [](const Recognition &lhs, const Recognition &rhs) {
+    return lhs.confidence < rhs.confidence;
+  };
+
+  std::priority_queue<Recognition, std::vector<Recognition>, decltype(compare)> pq(compare);
+  for (int i = 0; i < _num_classes; ++i)
+  {
+    if (_outputs[i] > _threshold)
+    {
+      pq.push(Recognition(_outputs[i], _labels[i]));
+    }
+  }
+
+  std::vector<Recognition> results;
+  int min = std::min(pq.size(), _max_results);
+  for (int i = 0; i < min; ++i)
+  {
+    results.push_back(pq.top());
+    pq.pop();
+  }
+
+  return results;
+}
diff --git a/runtime/contrib/tflite_classify/src/ImageClassifier.h b/runtime/contrib/tflite_classify/src/ImageClassifier.h
new file mode 100644
index 000000000..1ba19afb0
--- /dev/null
+++ b/runtime/contrib/tflite_classify/src/ImageClassifier.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     ImageClassifier.h
+ * @brief    This file contains ImageClassifier class and Recognition structure
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __TFLITE_CLASSIFY_IMAGE_CLASSIFIER_H__
+#define __TFLITE_CLASSIFY_IMAGE_CLASSIFIER_H__
+
+#include "InferenceInterface.h"
+
+#include <iostream>
+#include <string>
+#include <vector>
+
+#include <opencv2/opencv.hpp>
+
+/**
+ * @brief struct to define an immutable result returned by a Classifier
+ */
+struct Recognition
+{
+public:
+  /**
+   * @brief Construct a new Recognition object with confidence and title
+   * @param[in] _confidence A sortable score for how good the recognition is relative to others.
+   * Higher should be better.
+   * @param[in] _title      Display name for the recognition
+   */
+  Recognition(float _confidence, std::string _title) : confidence(_confidence), title(_title) {}
+
+  float confidence;  /** A sortable score for how good the recognition is relative to others. Higher
+                        should be better. */
+  std::string title; /** Display name for the recognition */
+};
+
+/**
+ * @brief Class to define a classifier specialized to label images
+ */
+class ImageClassifier
+{
+public:
+  /**
+   * @brief Construct a new ImageClassifier object with parameters
+   * @param[in] model_file  The filepath of the model FlatBuffer protocol buffer
+   * @param[in] label_file  The filepath of label file for classes
+   * @param[in] input_size  The input size. A square image of input_size x input_size is assumed
+   * @param[in] image_mean  The assumed mean of the image values
+   * @param[in] image_std   The assumed std of the image values
+   * @param[in] input_name  The label of the image input node
+   * @param[in] output_name The label of the output node
+   * @param[in] use_nnapi   The flag to distinguish between TfLite interpreter and NNFW runtime
+   */
+  ImageClassifier(const std::string &model_file, const std::string &label_file,
+                  const int input_size, const int image_mean, const int image_std,
+                  const std::string &input_name, const std::string &output_name,
+                  const bool use_nnapi);
+
+  /**
+   * @brief Recognize the given image data
+   * @param[in] image   The image data to recognize
+   * @return An immutable result vector array
+   */
+  std::vector<Recognition> recognizeImage(const cv::Mat &image);
+
+private:
+  const float _threshold = 0.1f;
+  const unsigned int _max_results = 3;
+
+  std::unique_ptr<InferenceInterface> _inference;
+  int _input_size;
+  int _image_mean;
+  int _image_std;
+  std::string _input_name;
+  std::string _output_name;
+
+  std::vector<std::string> _labels;
+  std::vector<float> _fdata;
+  std::vector<float> _outputs;
+  int _num_classes;
+};
+
+#endif // __TFLITE_CLASSIFY_IMAGE_CLASSIFIER_H__
diff --git a/runtime/contrib/tflite_classify/src/InferenceInterface.cc b/runtime/contrib/tflite_classify/src/InferenceInterface.cc
new file mode 100644
index 000000000..160943477
--- /dev/null
+++ b/runtime/contrib/tflite_classify/src/InferenceInterface.cc
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "InferenceInterface.h"
+
+using namespace tflite;
+using namespace tflite::ops::builtin;
+
+InferenceInterface::InferenceInterface(const std::string &model_file, const bool use_nnapi)
+    : _interpreter(nullptr), _model(nullptr), _sess(nullptr)
+{
+  // Load model
+  StderrReporter error_reporter;
+  _model = FlatBufferModel::BuildFromFile(model_file.c_str(), &error_reporter);
+  BuiltinOpResolver resolver;
+  InterpreterBuilder builder(*_model, resolver);
+  builder(&_interpreter);
+
+  if (use_nnapi)
+  {
+    _sess = std::make_shared<nnfw::tflite::NNAPISession>(_interpreter.get());
+  }
+  else
+  {
+    _sess = std::make_shared<nnfw::tflite::InterpreterSession>(_interpreter.get());
+  }
+
+  _sess->prepare();
+}
+
+InferenceInterface::~InferenceInterface() { _sess->teardown(); }
+
+void InferenceInterface::feed(const std::string &input_name, const std::vector<float> &data,
+                              const int batch, const int height, const int width, const int channel)
+{
+  // Set input tensor
+  for (const auto &id : _interpreter->inputs())
+  {
+    if (_interpreter->tensor(id)->name == input_name)
+    {
+      assert(_interpreter->tensor(id)->type == kTfLiteFloat32);
+      float *p = _interpreter->tensor(id)->data.f;
+
+      // TODO consider batch
+      for (int y = 0; y < height; ++y)
+      {
+        for (int x = 0; x < width; ++x)
+        {
+          for (int c = 0; c < channel; ++c)
+          {
+            *p++ = data[y * width * channel + x * channel + c];
+          }
+        }
+      }
+    }
+  }
+}
+
+void InferenceInterface::run(const std::string &output_name)
+{
+  // Run model
+  _sess->run();
+}
+
+void InferenceInterface::fetch(const std::string &output_name, std::vector<float> &outputs)
+{
+  // Get output tensor
+  for (const auto &id : _interpreter->outputs())
+  {
+    if (_interpreter->tensor(id)->name == output_name)
+    {
+      assert(_interpreter->tensor(id)->type == kTfLiteFloat32);
+      assert(getTensorSize(output_name) == outputs.capacity());
+      float *p = _interpreter->tensor(id)->data.f;
+
+      outputs.clear();
+      for (int i = 0; i < outputs.capacity(); ++i)
+      {
+        outputs.push_back(p[i]);
+      }
+    }
+  }
+}
+
+int InferenceInterface::getTensorSize(const std::string &name)
+{
+  for (const auto &id : _interpreter->outputs())
+  {
+    if (_interpreter->tensor(id)->name == name)
+    {
+      TfLiteTensor *t = _interpreter->tensor(id);
+      int v = 1;
+      for (int i = 0; i < t->dims->size; ++i)
+      {
+        v *= t->dims->data[i];
+      }
+      return v;
+    }
+  }
+  return -1;
+}
diff --git a/runtime/contrib/tflite_classify/src/InferenceInterface.h b/runtime/contrib/tflite_classify/src/InferenceInterface.h
new file mode 100644
index 000000000..fe2c1aa6c
--- /dev/null
+++ b/runtime/contrib/tflite_classify/src/InferenceInterface.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     InferenceInterface.h
+ * @brief    This file contains class for running the actual inference model
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __TFLITE_CLASSIFY_INFERENCE_INTERFACE_H__
+#define __TFLITE_CLASSIFY_INFERENCE_INTERFACE_H__
+
+#include "tflite/ext/kernels/register.h"
+#include "tensorflow/lite/model.h"
+
+#include "tflite/InterpreterSession.h"
+#include "tflite/NNAPISession.h"
+
+#include <iostream>
+#include <string>
+
+/**
+ * @brief Class to define a inference interface for recognizing data
+ */
+class InferenceInterface
+{
+public:
+  /**
+   * @brief Construct a new InferenceInterface object with parameters
+   * @param[in] model_file  The filepath of the model FlatBuffer protocol buffer
+   * @param[in] use_nnapi   The flag to distinguish between TfLite interpreter and NNFW runtime
+   */
+  InferenceInterface(const std::string &model_file, const bool use_nnapi);
+
+  /**
+   * @brief Destructor an InferenceInterface object
+   */
+  ~InferenceInterface();
+
+  /**
+   * @brief Copy the input data into model
+   * @param[in] input_name  The label of the image input node
+   * @param[in] data        The actual data to be copied into input tensor
+   * @param[in] batch       The number of batch size
+   * @param[in] height      The number of height size
+   * @param[in] width       The number of width size
+   * @param[in] channel     The number of channel size
+   * @return N/A
+   */
+  void feed(const std::string &input_name, const std::vector<float> &data, const int batch,
+            const int height, const int width, const int channel);
+  /**
+   * @brief Run the inference call
+   * @param[in] output_name The label of the output node
+   * @return N/A
+   */
+  void run(const std::string &output_name);
+
+  /**
+   * @brief Copy the output tensor back into the output array
+   * @param[in] output_node The label of the output node
+   * @param[in] outputs     The output data array
+   * @return N/A
+   */
+  void fetch(const std::string &output_name, std::vector<float> &outputs);
+
+  /**
+   * @brief Get tensor size
+   * @param[in] name  The label of the node
+   * @result The size of tensor
+   */
+  int getTensorSize(const std::string &name);
+
+private:
+  std::unique_ptr<tflite::Interpreter> _interpreter;
+  std::unique_ptr<tflite::FlatBufferModel> _model;
+  std::shared_ptr<nnfw::tflite::Session> _sess;
+};
+
+#endif // __TFLITE_CLASSIFY_INFERENCE_INTERFACE_H__
diff --git a/runtime/contrib/tflite_classify/src/tflite_classify.cc b/runtime/contrib/tflite_classify/src/tflite_classify.cc
new file mode 100644
index 000000000..40c15f331
--- /dev/null
+++ b/runtime/contrib/tflite_classify/src/tflite_classify.cc
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ImageClassifier.h"
+
+#include <iostream>
+
+#include <boost/filesystem.hpp>
+#include <opencv2/opencv.hpp>
+
+namespace fs = boost::filesystem;
+
+int main(const int argc, char **argv)
+{
+  const std::string MODEL_FILE = "tensorflow_inception_graph.tflite";
+  const std::string LABEL_FILE = "imagenet_comp_graph_label_strings.txt";
+
+  const std::string INPUT_NAME = "input";
+  const std::string OUTPUT_NAME = "output";
+  const int INPUT_SIZE = 224;
+  const int IMAGE_MEAN = 117;
+  const int IMAGE_STD = 1;
+  const int OUTPUT_SIZE = 1008;
+
+  const int FRAME_WIDTH = 640;
+  const int FRAME_HEIGHT = 480;
+
+  bool use_nnapi = false;
+  bool debug_mode = false;
+
+  if (std::getenv("USE_NNAPI") != nullptr)
+  {
+    use_nnapi = true;
+  }
+
+  if (std::getenv("DEBUG_MODE") != nullptr)
+  {
+    debug_mode = true;
+  }
+
+  std::cout << "USE_NNAPI : " << use_nnapi << std::endl;
+  std::cout << "DEBUG_MODE : " << debug_mode << std::endl;
+
+  std::cout << "Model : " << MODEL_FILE << std::endl;
+  std::cout << "Label : " << LABEL_FILE << std::endl;
+
+  if (!fs::exists(MODEL_FILE))
+  {
+    std::cerr << "model file not found: " << MODEL_FILE << std::endl;
+    exit(1);
+  }
+
+  if (!fs::exists(LABEL_FILE))
+  {
+    std::cerr << "label file not found: " << LABEL_FILE << std::endl;
+    exit(1);
+  }
+
+  // Create ImageClassifier
+  std::unique_ptr<ImageClassifier> classifier(
+      new ImageClassifier(MODEL_FILE, LABEL_FILE, INPUT_SIZE, IMAGE_MEAN, IMAGE_STD, INPUT_NAME,
+                          OUTPUT_NAME, use_nnapi));
+
+  // Cam setting
+  cv::VideoCapture cap(0);
+  cv::Mat frame;
+
+  // Initialize camera
+  cap.set(CV_CAP_PROP_FRAME_WIDTH, FRAME_WIDTH);
+  cap.set(CV_CAP_PROP_FRAME_HEIGHT, FRAME_HEIGHT);
+  cap.set(CV_CAP_PROP_FPS, 5);
+
+  std::vector<Recognition> results;
+  clock_t begin, end;
+  while (cap.isOpened())
+  {
+    // Get image data
+    if (!cap.read(frame))
+    {
+      std::cout << "Frame is null..." << std::endl;
+      break;
+    }
+
+    if (debug_mode)
+    {
+      begin = clock();
+    }
+    // Recognize image
+    results = classifier->recognizeImage(frame);
+    if (debug_mode)
+    {
+      end = clock();
+    }
+
+    // Show result data
+    std::cout << std::endl;
+    if (results.size() > 0)
+    {
+      for (int i = 0; i < results.size(); ++i)
+      {
+        std::cout << results[i].title << ": " << results[i].confidence << std::endl;
+      }
+    }
+    else
+    {
+      std::cout << "." << std::endl;
+    }
+    if (debug_mode)
+    {
+      std::cout << "Frame: " << FRAME_WIDTH << "x" << FRAME_HEIGHT << std::endl;
+      std::cout << "Crop: " << INPUT_SIZE << "x" << INPUT_SIZE << std::endl;
+      std::cout << "Inference time(ms): " << ((end - begin) / (CLOCKS_PER_SEC / 1000)) << std::endl;
+    }
+  }
+
+  cap.release();
+
+  return 0;
+}
diff --git a/runtime/contrib/tflite_test/CMakeLists.txt b/runtime/contrib/tflite_test/CMakeLists.txt
new file mode 100644
index 000000000..760952a84
--- /dev/null
+++ b/runtime/contrib/tflite_test/CMakeLists.txt
@@ -0,0 +1,16 @@
+if(NOT BUILD_TFLITE_TEST)
+  return()
+endif(NOT BUILD_TFLITE_TEST)
+
+nnfw_find_package(Tensorflow QUIET)
+
+if(NOT Tensorflow_FOUND)
+  return()
+endif(NOT Tensorflow_FOUND)
+
+list(APPEND SOURCES tflite_test.cpp)
+
+add_executable(tflite_test ${SOURCES})
+target_link_libraries(tflite_test PRIVATE nnfw_lib_tflite)
+target_link_libraries(tflite_test PRIVATE tensorflow-lite)
+target_link_libraries(tflite_test PRIVATE tensorflow-core)
diff --git a/runtime/contrib/tflite_test/tflite_test.cpp b/runtime/contrib/tflite_test/tflite_test.cpp
new file mode 100644
index 000000000..80ba448c6
--- /dev/null
+++ b/runtime/contrib/tflite_test/tflite_test.cpp
@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <tensorflow/lite/model.h>
+#include <tensorflow/core/public/session.h>
+
+#include "tflite/Assert.h"
+#include "tflite/Session.h"
+#include "tflite/InterpreterSession.h"
+#include "tflite/NNAPISession.h"
+#include "tflite/ext/kernels/register.h"
+
+#include "misc/fp32.h"
+
+#include <iostream>
+
+#include <string>
+#include <vector>
+
+#define TF_ENSURE(e)                               \
+  {                                                \
+    if (!(e).ok())                                 \
+    {                                              \
+      throw std::runtime_error{"'" #e "' FAILED"}; \
+    }                                              \
+  }
+
+using namespace tflite;
+using namespace tflite::ops::builtin;
+
+std::unique_ptr<FlatBufferModel> BuildModelFromFile(const std::string &path)
+{
+  static StderrReporter reporter;
+  return FlatBufferModel::BuildFromFile(path.c_str(), &reporter);
+}
+
+std::unique_ptr<Interpreter> BuildInterpFromModel(const std::unique_ptr<FlatBufferModel> &model)
+{
+  std::unique_ptr<Interpreter> interp;
+
+  BuiltinOpResolver resolver;
+  InterpreterBuilder builder(*model, resolver);
+
+  TFLITE_ENSURE(builder(&interp));
+
+  return std::move(interp);
+}
+
+tensorflow::TensorShape asTensorflowShape(const TfLiteTensor *tensor)
+{
+  tensorflow::TensorShape shape;
+
+  const int rank = tensor->dims->size;
+
+  for (int axis = 0; axis < rank; ++axis)
+  {
+    shape.AddDim(tensor->dims->data[axis]);
+  }
+
+  return shape;
+}
+
+uint32_t count_elements(const TfLiteTensor *tensor)
+{
+  const int rank = tensor->dims->size;
+
+  if (rank == 0)
+  {
+    return 0;
+  }
+
+  uint32_t res = 1;
+
+  for (int axis = 0; axis < rank; ++axis)
+  {
+    res *= tensor->dims->data[axis];
+  }
+
+  return res;
+}
+
+int main(int argc, char **argv)
+{
+  bool use_nnapi = false;
+
+  if (std::getenv("USE_NNAPI") != nullptr)
+  {
+    use_nnapi = true;
+  }
+
+  if (argc < 3)
+  {
+    std::cerr << "USAGE: " << argv[0] << " [T/F lite model] [T/F model]" << std::endl;
+    return 255;
+  }
+
+  //
+  // Prepare Tensorflow Lite session
+  //
+  const std::string lite_model_path{argv[1]};
+
+  auto lite_model = BuildModelFromFile(lite_model_path);
+  auto lite_interp = BuildInterpFromModel(lite_model);
+
+  std::shared_ptr<nnfw::tflite::Session> lite_sess;
+
+  if (use_nnapi)
+  {
+    lite_sess = std::make_shared<nnfw::tflite::NNAPISession>(lite_interp.get());
+  }
+  else
+  {
+    lite_sess = std::make_shared<nnfw::tflite::InterpreterSession>(lite_interp.get());
+  }
+
+  //
+  // Prepare Tensorflow session
+  //
+  const std::string full_model_path{argv[2]};
+
+  tensorflow::Session *full_sess;
+  tensorflow::GraphDef full_model;
+
+  TF_ENSURE(tensorflow::NewSession(tensorflow::SessionOptions(), &full_sess));
+  TF_ENSURE(ReadBinaryProto(tensorflow::Env::Default(), full_model_path, &full_model));
+  TF_ENSURE(full_sess->Create(full_model));
+
+  //
+  //
+  //
+  std::vector<tensorflow::Tensor> input_nodes;
+  std::vector<std::string> input_names;
+
+  for (uint32_t n = 0; n < lite_interp->inputs().size(); ++n)
+  {
+    const TfLiteTensor *tensor = lite_interp->tensor(lite_interp->inputs().at(n));
+
+    input_nodes.emplace_back(tensorflow::DT_FLOAT, asTensorflowShape(tensor));
+    input_names.emplace_back(tensor->name);
+  }
+
+  assert(input_nodes.size() == input_names.size());
+  assert(input_nodes.size() == lite_interp->inputs().size());
+
+  std::vector<std::string> output_names;
+  std::vector<tensorflow::Tensor> output_nodes;
+
+  for (uint32_t n = 0; n < lite_interp->outputs().size(); ++n)
+  {
+    const TfLiteTensor *tensor = lite_interp->tensor(lite_interp->outputs().at(n));
+
+    output_names.emplace_back(tensor->name);
+  }
+
+  assert(output_names.size() == lite_interp->outputs().size());
+  // output_nodes will be initialized after Tensorflow Session run
+  assert(output_nodes.size() == 0);
+
+  //
+  // Prepare inference
+  //
+  lite_sess->prepare();
+
+  // TODO Feed Inputs (for both Tensorflow and Tensorflow Lite)
+  std::vector<std::pair<std::string, tensorflow::Tensor>> inputs;
+
+  for (uint32_t n = 0; n < input_nodes.size(); ++n)
+  {
+    inputs.emplace_back(input_names.at(0), input_nodes.at(0));
+  }
+
+  //
+  // Run inference
+  //
+  TF_ENSURE(full_sess->Run(inputs, output_names, {}, &output_nodes));
+
+  lite_sess->run();
+
+  //
+  // Compare Output
+  //
+  auto equals = [](float lhs, float rhs) {
+    // TODO Allow users to set tolerance
+    if (nnfw::misc::fp32::absolute_epsilon_equal(lhs, rhs))
+    {
+      return true;
+    }
+
+    return nnfw::misc::fp32::epsilon_equal(lhs, rhs);
+  };
+
+  const uint32_t output_count = output_names.size();
+
+  bool matched = true;
+
+  for (uint32_t n = 0; n < output_count; ++n)
+  {
+    const TfLiteTensor *tensor = lite_interp->tensor(lite_interp->outputs().at(n));
+
+    // TODO Compare shape
+
+    const auto element_count = count_elements(tensor);
+
+    std::cout << "Compare output #" << n << "(" << tensor->name << ", " << element_count
+              << " elements)" << std::endl;
+    for (uint32_t index = 0; index < element_count; ++index)
+    {
+      const auto full_value = output_nodes.at(n).flat<float>().data()[index];
+      const auto lite_value = lite_sess->interp()->typed_output_tensor<float>(n)[index];
+
+      if (!equals(full_value, lite_value))
+      {
+        std::cerr << full_value << " is expected, but " << lite_value << " is obtaeind (at " << n
+                  << ":" << index << ")" << std::endl;
+        matched = false;
+      }
+    }
+  }
+
+  //
+  // Cleanup
+  //
+  lite_sess->teardown();
+
+  return matched ? 0 : 255;
+}
diff --git a/runtime/contrib/uben/CMakeLists.txt b/runtime/contrib/uben/CMakeLists.txt
new file mode 100644
index 000000000..59cd52d16
--- /dev/null
+++ b/runtime/contrib/uben/CMakeLists.txt
@@ -0,0 +1,29 @@
+if(NOT BUILD_UBEN)
+  return()
+endif(NOT BUILD_UBEN)
+
+nnas_find_package(ARMCompute QUIET)
+nnas_find_package(Nonius QUIET)
+
+if(NOT ARMCompute_FOUND)
+  return()
+endif(NOT ARMCompute_FOUND)
+
+if(NOT Nonius_FOUND)
+  return()
+endif(NOT Nonius_FOUND)
+
+# 3x3 Convolution with unit stride
+add_executable(uben_conv_3x3 Convolution.cpp)
+target_compile_definitions(uben_conv_3x3 PRIVATE KER_H=3 KER_W=3 STRIDE_H=1 STRIDE_W=1)
+target_compile_definitions(uben_conv_3x3 PRIVATE CL_DIRECT_CONVOLUTION=1)
+target_compile_definitions(uben_conv_3x3 PRIVATE CL_GEMM_CONVOLUTION=1)
+target_compile_definitions(uben_conv_3x3 PRIVATE CL_WINOGRAD_CONVOLUTION=1)
+target_link_libraries(uben_conv_3x3 PRIVATE nonius)
+target_link_libraries(uben_conv_3x3 PRIVATE arm_compute)
+target_link_libraries(uben_conv_3x3 PRIVATE pthread)
+
+add_executable(uben_softmax Softmax.cpp)
+target_link_libraries(uben_softmax PRIVATE nonius)
+target_link_libraries(uben_softmax PRIVATE nnfw_lib_cker)
+target_link_libraries(uben_softmax PRIVATE pthread)
diff --git a/runtime/contrib/uben/Convolution.cpp b/runtime/contrib/uben/Convolution.cpp
new file mode 100644
index 000000000..ad69f1cec
--- /dev/null
+++ b/runtime/contrib/uben/Convolution.cpp
@@ -0,0 +1,429 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Conv2D (with SAME padding) benchmark with various algorithms
+ */
+
+#ifndef KER_H
+#error "KER_H is undefined"
+#endif // KER_H
+#ifndef KER_W
+#error "KER_W is undefined"
+#endif // KER_W
+#ifndef STRIDE_H
+#error "STRIDE_H is undefined"
+#endif // STRIDE_H
+#ifndef STRIDE_W
+#error "STRIDE_W is undefined"
+#endif // STRIDE_W
+
+#define NONIUS_RUNNER
+#include <nonius/nonius_single.h++>
+
+#include <arm_compute/core/Types.h>
+#include <arm_compute/runtime/CL/CLScheduler.h>
+#include <arm_compute/runtime/CL/CLFunctions.h>
+
+#include <cstdint>
+#include <cassert>
+#include <stdexcept>
+
+using namespace arm_compute;
+
+//
+// Helpers
+//
+namespace
+{
+
+enum Layout
+{
+  NCHW,
+  NHWC
+};
+
+struct Initializer
+{
+  Initializer() { CLScheduler::get().default_init(); }
+};
+
+Initializer initializer;
+
+TensorInfo make_info(uint32_t N)
+{
+  TensorShape shape{N};
+  return TensorInfo{shape, 1, DataType::F32};
+}
+
+template <enum Layout> TensorInfo make_info(uint32_t N, uint32_t C, uint32_t H, uint32_t W);
+
+template <> TensorInfo make_info<NCHW>(uint32_t N, uint32_t C, uint32_t H, uint32_t W)
+{
+  TensorShape shape{W, H, C, N};
+  TensorInfo info{shape, 1, DataType::F32};
+  info.set_data_layout(DataLayout::NCHW);
+  return info;
+}
+
+template <> TensorInfo make_info<NHWC>(uint32_t N, uint32_t C, uint32_t H, uint32_t W)
+{
+  TensorShape shape{C, W, H, N};
+  TensorInfo info{shape, 1, DataType::F32};
+  info.set_data_layout(DataLayout::NHWC);
+  return info;
+}
+
+inline void check(const Status &status)
+{
+  if (!status)
+  {
+    std::cerr << status.error_description() << std::endl;
+    throw std::runtime_error{"ERROR"};
+  }
+}
+
+inline bool is_odd(uint32_t n) { return (n % 2 != 0) ? true : false; }
+
+} // namespace
+
+//
+// Benchmark Parameters
+//
+NONIUS_PARAM(BATCH, 1);
+
+NONIUS_PARAM(IFM_C, 3);
+NONIUS_PARAM(IFM_H, 244);
+NONIUS_PARAM(IFM_W, 244);
+
+NONIUS_PARAM(OFM_C, 3);
+NONIUS_PARAM(OFM_H, 244);
+NONIUS_PARAM(OFM_W, 244);
+
+//
+// Configuration Helpers
+//
+namespace
+{
+
+struct Configuration
+{
+  uint32_t ifm_N;
+  uint32_t ifm_C;
+  uint32_t ifm_H;
+  uint32_t ifm_W;
+
+  uint32_t ofm_N;
+  uint32_t ofm_C;
+  uint32_t ofm_H;
+  uint32_t ofm_W;
+
+  uint32_t ker_N;
+  uint32_t ker_C;
+  uint32_t ker_H;
+  uint32_t ker_W;
+
+  uint32_t vertical_stride;
+  uint32_t horizontal_stride;
+
+  uint32_t top_padding;
+  uint32_t bottom_padding;
+  uint32_t left_padding;
+  uint32_t right_padding;
+
+  Configuration(nonius::chronometer meter)
+  {
+    ifm_N = meter.param<BATCH>();
+    ifm_C = meter.param<IFM_C>();
+    ifm_H = meter.param<IFM_H>();
+    ifm_W = meter.param<IFM_W>();
+
+    ofm_N = meter.param<BATCH>();
+    ofm_C = meter.param<OFM_C>();
+    ofm_H = meter.param<OFM_H>();
+    ofm_W = meter.param<OFM_W>();
+
+    ker_N = meter.param<OFM_C>();
+    ker_C = meter.param<IFM_C>();
+    ker_H = KER_H;
+    ker_W = KER_W;
+
+    vertical_stride = STRIDE_H;
+    horizontal_stride = STRIDE_W;
+
+    assert((ifm_H - ker_H) % vertical_stride == 0);
+    assert((ifm_W - ker_H) % horizontal_stride == 0);
+
+    uint32_t const effective_ofm_H = (ifm_H - ker_H) / vertical_stride + 1;
+    uint32_t const effective_ofm_W = (ifm_W - ker_H) / horizontal_stride + 1;
+
+    assert(ofm_H >= effective_ofm_H);
+    assert(ofm_W >= effective_ofm_W);
+
+    uint32_t const pad_H = ofm_H - effective_ofm_H;
+    uint32_t const pad_W = ofm_W - effective_ofm_W;
+
+    top_padding = pad_H / 2;
+    bottom_padding = pad_H / 2;
+    left_padding = pad_W / 2;
+    right_padding = pad_W / 2;
+
+    if (is_odd(pad_H))
+      top_padding += 1;
+    if (is_odd(pad_W))
+      left_padding += 1;
+  }
+
+  template <Layout L> TensorInfo src_info() const
+  {
+    return make_info<L>(ifm_N, ifm_C, ifm_H, ifm_W);
+  }
+  template <Layout L> TensorInfo dst_info() const
+  {
+    return make_info<L>(ofm_N, ofm_C, ofm_H, ofm_W);
+  }
+  template <Layout L> TensorInfo ker_info() const
+  {
+    return make_info<L>(ker_N, ker_C, ker_H, ker_W);
+  }
+  TensorInfo bias_info(void) const { return make_info(ker_N); }
+
+  PadStrideInfo pad_stride_info(void) const
+  {
+    return PadStrideInfo{horizontal_stride,
+                         vertical_stride,
+                         left_padding,
+                         right_padding,
+                         top_padding,
+                         bottom_padding,
+                         DimensionRoundingType::FLOOR};
+  }
+};
+
+} // namespace
+
+//
+// Benchmakr Implementations
+//
+#ifndef CL_DIRECT_CONVOLUTION
+#error "CL_DIRECT_CONVOLUTION is undefined"
+#endif // CL_DIRECT_CONVOLUTION
+
+#if CL_DIRECT_CONVOLUTION
+NONIUS_BENCHMARK("CLDirectConvolutionLayer(NCHW)", [](nonius::chronometer meter) {
+  CLDirectConvolutionLayer conv;
+
+  // Configure
+  Configuration p{meter};
+
+  CLTensor src_tensor{};
+  CLTensor dst_tensor{};
+  CLTensor ker_tensor{};
+  CLTensor bias_tensor{};
+
+  src_tensor.allocator()->init(p.src_info<NCHW>());
+  dst_tensor.allocator()->init(p.dst_info<NCHW>());
+  ker_tensor.allocator()->init(p.ker_info<NCHW>());
+  bias_tensor.allocator()->init(p.bias_info());
+
+  check(conv.validate(src_tensor.info(), ker_tensor.info(), bias_tensor.info(), dst_tensor.info(),
+                      p.pad_stride_info()));
+  conv.configure(&src_tensor, &ker_tensor, &bias_tensor, &dst_tensor, p.pad_stride_info());
+
+  src_tensor.allocator()->allocate();
+  ker_tensor.allocator()->allocate();
+  bias_tensor.allocator()->allocate();
+  dst_tensor.allocator()->allocate();
+
+  // Run!
+  meter.measure([&](int) {
+    conv.run();
+    CLScheduler::get().sync();
+  });
+})
+
+NONIUS_BENCHMARK("CLDirectConvolutionLayer(NHWC)", [](nonius::chronometer meter) {
+  CLDirectConvolutionLayer conv;
+
+  // Configure
+  Configuration p{meter};
+
+  CLTensor src_tensor{};
+  CLTensor dst_tensor{};
+  CLTensor ker_tensor{};
+  CLTensor bias_tensor{};
+
+  src_tensor.allocator()->init(p.src_info<NHWC>());
+  dst_tensor.allocator()->init(p.dst_info<NHWC>());
+  ker_tensor.allocator()->init(p.ker_info<NHWC>());
+  bias_tensor.allocator()->init(p.bias_info());
+
+  check(conv.validate(src_tensor.info(), ker_tensor.info(), bias_tensor.info(), dst_tensor.info(),
+                      p.pad_stride_info()));
+  conv.configure(&src_tensor, &ker_tensor, &bias_tensor, &dst_tensor, p.pad_stride_info());
+
+  src_tensor.allocator()->allocate();
+  ker_tensor.allocator()->allocate();
+  bias_tensor.allocator()->allocate();
+  dst_tensor.allocator()->allocate();
+
+  // Run!
+  meter.measure([&](int) {
+    conv.run();
+    CLScheduler::get().sync();
+  });
+})
+#endif // CL_DIRECT_CONVOLUTION
+
+#ifndef CL_GEMM_CONVOLUTION
+#error "CL_GEMM_CONVOLUTION is undefined"
+#endif // CL_GEMM_CONVOLUTION
+
+#if CL_GEMM_CONVOLUTION
+NONIUS_BENCHMARK("CLGEMMConvolutionLayer(NCHW)", [](nonius::chronometer meter) {
+  CLGEMMConvolutionLayer conv;
+
+  // Configure
+  Configuration p{meter};
+
+  CLTensor src_tensor{};
+  CLTensor dst_tensor{};
+  CLTensor ker_tensor{};
+  CLTensor bias_tensor{};
+
+  src_tensor.allocator()->init(p.src_info<NCHW>());
+  dst_tensor.allocator()->init(p.dst_info<NCHW>());
+  ker_tensor.allocator()->init(p.ker_info<NCHW>());
+  bias_tensor.allocator()->init(p.bias_info());
+
+  check(conv.validate(src_tensor.info(), ker_tensor.info(), bias_tensor.info(), dst_tensor.info(),
+                      p.pad_stride_info()));
+  conv.configure(&src_tensor, &ker_tensor, &bias_tensor, &dst_tensor, p.pad_stride_info());
+
+  src_tensor.allocator()->allocate();
+  ker_tensor.allocator()->allocate();
+  bias_tensor.allocator()->allocate();
+  dst_tensor.allocator()->allocate();
+
+  // Run
+  meter.measure([&](int) {
+    conv.run();
+    CLScheduler::get().sync();
+  });
+})
+
+NONIUS_BENCHMARK("CLGEMMConvolutionLayer(NHWC)", [](nonius::chronometer meter) {
+  CLGEMMConvolutionLayer conv;
+
+  // Configure
+  Configuration p{meter};
+
+  CLTensor src_tensor{};
+  CLTensor dst_tensor{};
+  CLTensor ker_tensor{};
+  CLTensor bias_tensor{};
+
+  src_tensor.allocator()->init(p.src_info<NHWC>());
+  dst_tensor.allocator()->init(p.dst_info<NHWC>());
+  ker_tensor.allocator()->init(p.ker_info<NHWC>());
+  bias_tensor.allocator()->init(p.bias_info());
+
+  check(conv.validate(src_tensor.info(), ker_tensor.info(), bias_tensor.info(), dst_tensor.info(),
+                      p.pad_stride_info()));
+  conv.configure(&src_tensor, &ker_tensor, &bias_tensor, &dst_tensor, p.pad_stride_info());
+
+  src_tensor.allocator()->allocate();
+  ker_tensor.allocator()->allocate();
+  bias_tensor.allocator()->allocate();
+  dst_tensor.allocator()->allocate();
+
+  // Run
+  meter.measure([&](int) {
+    conv.run();
+    CLScheduler::get().sync();
+  });
+})
+#endif // CL_GEMM_CONVOLUTION
+
+#ifndef CL_WINOGRAD_CONVOLUTION
+#error "CL_WINOGRAD_CONVOLUTION is undefined"
+#endif // CL_WINOGRAD_CONVOLUTION
+
+#if CL_WINOGRAD_CONVOLUTION
+NONIUS_BENCHMARK("CLWinogradConvolutionLayer(NCHW)", [](nonius::chronometer meter) {
+  CLWinogradConvolutionLayer conv;
+
+  // Configure
+  Configuration p{meter};
+
+  CLTensor src_tensor{};
+  CLTensor dst_tensor{};
+  CLTensor ker_tensor{};
+  CLTensor bias_tensor{};
+
+  src_tensor.allocator()->init(p.src_info<NCHW>());
+  dst_tensor.allocator()->init(p.dst_info<NCHW>());
+  ker_tensor.allocator()->init(p.ker_info<NCHW>());
+  bias_tensor.allocator()->init(p.bias_info());
+
+  check(conv.validate(src_tensor.info(), ker_tensor.info(), bias_tensor.info(), dst_tensor.info(),
+                      p.pad_stride_info()));
+  conv.configure(&src_tensor, &ker_tensor, &bias_tensor, &dst_tensor, p.pad_stride_info());
+
+  src_tensor.allocator()->allocate();
+  ker_tensor.allocator()->allocate();
+  bias_tensor.allocator()->allocate();
+  dst_tensor.allocator()->allocate();
+
+  // Run
+  meter.measure([&](int) {
+    conv.run();
+    CLScheduler::get().sync();
+  });
+})
+
+NONIUS_BENCHMARK("CLWinogradConvolutionLayer(NHWC)", [](nonius::chronometer meter) {
+  CLWinogradConvolutionLayer conv;
+
+  // Configure
+  Configuration p{meter};
+
+  CLTensor src_tensor{};
+  CLTensor dst_tensor{};
+  CLTensor ker_tensor{};
+  CLTensor bias_tensor{};
+
+  src_tensor.allocator()->init(p.src_info<NHWC>());
+  dst_tensor.allocator()->init(p.dst_info<NHWC>());
+  ker_tensor.allocator()->init(p.ker_info<NHWC>());
+  bias_tensor.allocator()->init(p.bias_info());
+
+  check(conv.validate(src_tensor.info(), ker_tensor.info(), bias_tensor.info(), dst_tensor.info(),
+                      p.pad_stride_info()));
+  conv.configure(&src_tensor, &ker_tensor, &bias_tensor, &dst_tensor, p.pad_stride_info());
+
+  src_tensor.allocator()->allocate();
+  ker_tensor.allocator()->allocate();
+  bias_tensor.allocator()->allocate();
+  dst_tensor.allocator()->allocate();
+
+  // Run
+  meter.measure([&](int) {
+    conv.run();
+    CLScheduler::get().sync();
+  });
+})
+#endif // CL_WINOGRAD_CONVOLUTION
diff --git a/runtime/contrib/uben/Softmax.cpp b/runtime/contrib/uben/Softmax.cpp
new file mode 100644
index 000000000..1c4a6b197
--- /dev/null
+++ b/runtime/contrib/uben/Softmax.cpp
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Softmax benchmark
+ */
+
+#define NONIUS_RUNNER
+#include <nonius/nonius_single.h++>
+
+#include <cker/operation/SoftMax.h>
+
+#include <vector>
+
+//
+// Parameters
+//
+NONIUS_PARAM(LEN, 1000);
+
+//
+// Implementations
+//
+NONIUS_BENCHMARK("cker::Softmax(float)", [](nonius::chronometer meter) {
+  auto len = meter.param<LEN>();
+
+  nnfw::cker::SoftmaxParams params;
+  nnfw::cker::Shape shape{1, len};
+
+  params.beta = 1.0;
+
+  std::vector<float> input;
+  std::vector<float> output;
+
+  input.resize(len);
+  output.resize(len);
+
+  meter.measure([&](int) {
+    // Run!
+    nnfw::cker::Softmax(params, shape, input.data(), shape, output.data());
+  });
+})
diff --git a/runtime/libs/CMakeLists.txt b/runtime/libs/CMakeLists.txt
new file mode 100644
index 000000000..99d2028f4
--- /dev/null
+++ b/runtime/libs/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Add all subdirectories.
+# Each library in sub-directory must have it's own CMakeLists.txt
+# to build library's binaries or to support interface.
+add_subdirectories()
diff --git a/runtime/libs/benchmark/CMakeLists.txt b/runtime/libs/benchmark/CMakeLists.txt
new file mode 100644
index 000000000..2af0ffaa3
--- /dev/null
+++ b/runtime/libs/benchmark/CMakeLists.txt
@@ -0,0 +1,6 @@
+file(GLOB_RECURSE SOURCES "src/*.cpp")
+
+add_library(nnfw_lib_benchmark SHARED ${SOURCES})
+target_include_directories(nnfw_lib_benchmark PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/include)
+target_link_libraries(nnfw_lib_benchmark PRIVATE ${LIB_PTHREAD})
+install(TARGETS nnfw_lib_benchmark DESTINATION lib)
diff --git a/runtime/libs/benchmark/include/benchmark.h b/runtime/libs/benchmark/include/benchmark.h
new file mode 100644
index 000000000..7d3238210
--- /dev/null
+++ b/runtime/libs/benchmark/include/benchmark.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NNFW_BENCHMARK_H__
+#define __NNFW_BENCHMARK_H__
+
+#include "benchmark/Result.h"
+#include "benchmark/MemoryPoller.h"
+#include "benchmark/CsvWriter.h"
+#include "benchmark/Util.h"
+
+#endif // __NNFW_BENCHMARK_H__
diff --git a/runtime/libs/benchmark/include/benchmark/CsvHeader.lst b/runtime/libs/benchmark/include/benchmark/CsvHeader.lst
new file mode 100644
index 000000000..c76b6131f
--- /dev/null
+++ b/runtime/libs/benchmark/include/benchmark/CsvHeader.lst
@@ -0,0 +1,15 @@
+"Model",
+"Backend",
+"ModelLoad_Time",
+"Prepare_Time",
+"Execute_Time_Min",
+"Execute_Time_Max",
+"Execute_Time_Mean",
+"ModelLoad_RSS",
+"Prepare_RSS",
+"Execute_RSS",
+"Peak_RSS",
+"ModelLoad_HWM",
+"Prepare_HWM",
+"Execute_HWM",
+"Peak_HWM",
diff --git a/runtime/libs/benchmark/include/benchmark/CsvWriter.h b/runtime/libs/benchmark/include/benchmark/CsvWriter.h
new file mode 100644
index 000000000..3e141216b
--- /dev/null
+++ b/runtime/libs/benchmark/include/benchmark/CsvWriter.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NNFW_BENCHMARK_CSV_WRITER_H__
+#define __NNFW_BENCHMARK_CSV_WRITER_H__
+
+#include <vector>
+#include <string>
+#include <fstream>
+
+namespace benchmark
+{
+
+class CsvWriter
+{
+public:
+  CsvWriter(const std::string &csv_filename);
+  CsvWriter(const std::string &csv_filename, const std::vector<std::string> &header);
+  virtual ~CsvWriter();
+
+  void write(const std::string &val);
+  void write(double val);
+  void write(uint32_t val);
+  void write(char val);
+  bool done();
+
+public:
+  static const char delimiter = ',';
+  static const char newline = '\n';
+
+  friend CsvWriter &operator<<(CsvWriter &csvw, const std::string &val);
+  friend CsvWriter &operator<<(CsvWriter &csvw, double val);
+  friend CsvWriter &operator<<(CsvWriter &csvw, uint32_t val);
+  friend CsvWriter &operator<<(CsvWriter &csvw, char val);
+
+private:
+  void writeHeader(const std::vector<std::string> &header);
+  inline void postWrite();
+
+private:
+  std::ofstream _ofs;
+  uint32_t _header_size;
+  uint32_t _col_idx;
+};
+
+} // namespace benchmark
+
+#endif // __NNFW_BENCHMARK_CSV_WRITER_H__
diff --git a/runtime/libs/benchmark/include/benchmark/MemoryPoller.h b/runtime/libs/benchmark/include/benchmark/MemoryPoller.h
new file mode 100644
index 000000000..31f4edc0e
--- /dev/null
+++ b/runtime/libs/benchmark/include/benchmark/MemoryPoller.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NNFW_BENCHMARK_MEMORY_POLLER_H__
+#define __NNFW_BENCHMARK_MEMORY_POLLER_H__
+
+#include <cstdint>
+#include <algorithm>
+#include <unordered_map>
+#include <string>
+#include <chrono>
+#include <thread>
+#include <mutex>
+#include <condition_variable>
+#include <list>
+
+#include "Phase.h"
+
+namespace benchmark
+{
+
+// NOTE. gpu_poll is not necessary on general targets. This is used on the only tv targets.
+// TODO finally should be separated from data
+// TODO Use ctor() and dtor() instead of start() and end()
+class MemoryPoller
+{
+public:
+  MemoryPoller(std::chrono::milliseconds duration = std::chrono::milliseconds(5),
+               bool gpu_poll = false);
+
+  virtual ~MemoryPoller()
+  {
+    _term = true;
+    _cond_var_started.notify_all();
+    _thread.join();
+  }
+
+  bool start(Phase phase);
+  bool end(Phase phase);
+  const std::unordered_map<Phase, uint32_t> &getRssMap() const { return _rss_map; }
+  const std::unordered_map<Phase, uint32_t> &getHwmMap() const { return _hwm_map; }
+
+private:
+  void process();
+  bool prepareMemoryPolling();
+  uint32_t getVmRSS();
+  uint32_t getVmHWM();
+  uint32_t getGpuMemory();
+
+private:
+  std::chrono::milliseconds _duration;
+  std::thread _thread;
+  std::list<Phase> _phases;
+  std::unordered_map<Phase, uint32_t> _rss_map;
+  std::unordered_map<Phase, uint32_t> _hwm_map;
+
+  std::mutex _mutex;
+  std::mutex _mutex_started;
+  std::condition_variable _cond_var_started;
+
+  bool _term;
+  bool _run;
+  bool _gpu_poll;
+  std::string _process_name;
+};
+
+} // namespace benchmark
+
+#endif // __NNFW_BENCHMARK_MEMORY_POLLER_H__
diff --git a/runtime/libs/benchmark/include/benchmark/Phase.h b/runtime/libs/benchmark/include/benchmark/Phase.h
new file mode 100644
index 000000000..bea9a87b2
--- /dev/null
+++ b/runtime/libs/benchmark/include/benchmark/Phase.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NNFW_BENCHMARK_PHASE_H__
+#define __NNFW_BENCHMARK_PHASE_H__
+
+#include <string>
+#include <cassert>
+
+namespace benchmark
+{
+
+enum class Phase
+{
+  MODEL_LOAD,
+  PREPARE,
+  EXECUTE,
+};
+
+inline std::string getPhaseString(Phase phase)
+{
+  switch (phase)
+  {
+    case Phase::MODEL_LOAD:
+      return "MODEL_LOAD";
+    case Phase::PREPARE:
+      return "PREPARE";
+    case Phase::EXECUTE:
+      return "EXECUTE";
+    default:
+      assert(false);
+      return "";
+  }
+}
+
+} // namespace benchmark
+
+#endif // __NNFW_BENCHMARK_PHASE_H__
diff --git a/runtime/libs/benchmark/include/benchmark/Result.h b/runtime/libs/benchmark/include/benchmark/Result.h
new file mode 100644
index 000000000..570fa2114
--- /dev/null
+++ b/runtime/libs/benchmark/include/benchmark/Result.h
@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NNFW_BENCHMARK_RESULT_H__
+#define __NNFW_BENCHMARK_RESULT_H__
+
+#include "Phase.h"
+#include "MemoryPoller.h"
+
+#include <string>
+#include <vector>
+#include <numeric>
+#include <algorithm>
+#include <cassert>
+#include <memory>
+
+namespace
+{
+
+uint32_t maxMemory(const std::unordered_map<benchmark::Phase, uint32_t> &map)
+{
+  auto answer = *std::max_element(
+      map.begin(), map.end(),
+      [](const std::pair<benchmark::Phase, uint32_t> &p1,
+         const std::pair<benchmark::Phase, uint32_t> &p2) { return p1.second < p2.second; });
+  return answer.second;
+}
+
+} // namespace anonymous
+
+namespace benchmark
+{
+
+// Data class between runner(nnpackage_run and tflite_run) and libbenchmark
+class Result
+{
+public:
+  Result(double model_load_time, double prepare_time, const std::vector<double> &execute_times)
+      : _model_load_time(model_load_time), _prepare_time(prepare_time), _model_load_rss(0),
+        _prepare_rss(0), _execute_rss(0), _peak_rss(0), _model_load_hwm(0), _prepare_hwm(0),
+        _execute_hwm(0), _peak_hwm(0)
+  {
+    // execute
+    double sum = 0.0;
+    double min = std::numeric_limits<double>::max();
+    double max = std::numeric_limits<double>::lowest();
+    for (auto t : execute_times)
+    {
+      sum += t;
+      min = std::min(min, t);
+      max = std::max(max, t);
+    }
+    _execute_time_mean = sum / static_cast<double>(execute_times.size());
+    _execute_time_min = min;
+    _execute_time_max = max;
+  }
+
+  Result(double model_load_time, double prepare_time, const std::vector<double> &execute_times,
+         const std::unique_ptr<MemoryPoller> &memory_poller)
+      : Result(model_load_time, prepare_time, execute_times)
+  {
+    if (!memory_poller)
+      return;
+
+    const auto &rss = memory_poller->getRssMap();
+    const auto &hwm = memory_poller->getHwmMap();
+
+    // rss
+    assert(rss.size() > 0);
+    assert(rss.find(Phase::MODEL_LOAD) != rss.end());
+    assert(rss.find(Phase::PREPARE) != rss.end());
+    assert(rss.find(Phase::EXECUTE) != rss.end());
+    _model_load_rss = rss.at(Phase::MODEL_LOAD);
+    _prepare_rss = rss.at(Phase::PREPARE);
+    _execute_rss = rss.at(Phase::EXECUTE);
+    _peak_rss = maxMemory(rss);
+
+    // hwm
+    assert(hwm.size() > 0);
+    assert(hwm.find(Phase::MODEL_LOAD) != hwm.end());
+    assert(hwm.find(Phase::PREPARE) != hwm.end());
+    assert(hwm.find(Phase::EXECUTE) != hwm.end());
+    _model_load_hwm = hwm.at(Phase::MODEL_LOAD);
+    _prepare_hwm = hwm.at(Phase::PREPARE);
+    _execute_hwm = hwm.at(Phase::EXECUTE);
+    _peak_hwm = maxMemory(hwm);
+  }
+
+public:
+  double getModelLoadTime() const { return _model_load_time; }
+  double getPrepareTime() const { return _prepare_time; }
+  double getExecuteTimeMean() const { return _execute_time_mean; }
+  double getExecuteTimeMin() const { return _execute_time_min; }
+  double getExecuteTimeMax() const { return _execute_time_max; }
+
+  uint32_t getModelLoadRss() const { return _model_load_rss; }
+  uint32_t getPrepareRss() const { return _prepare_rss; }
+  uint32_t getExecuteRss() const { return _execute_rss; }
+  uint32_t getPeakRss() const { return _peak_rss; }
+
+  uint32_t getModelLoadHwm() const { return _model_load_hwm; }
+  uint32_t getPrepareHwm() const { return _prepare_hwm; }
+  uint32_t getExecuteHwm() const { return _execute_hwm; }
+  uint32_t getPeakHwm() const { return _peak_hwm; }
+
+private:
+  double _model_load_time;
+  double _prepare_time;
+  double _execute_time_mean;
+  double _execute_time_min;
+  double _execute_time_max;
+
+  uint32_t _model_load_rss;
+  uint32_t _prepare_rss;
+  uint32_t _execute_rss;
+  uint32_t _peak_rss;
+
+  uint32_t _model_load_hwm;
+  uint32_t _prepare_hwm;
+  uint32_t _execute_hwm;
+  uint32_t _peak_hwm;
+};
+
+} // namespace benchmark
+
+#endif // __NNFW_BENCHMARK_RESULT_H__
diff --git a/runtime/libs/benchmark/include/benchmark/Util.h b/runtime/libs/benchmark/include/benchmark/Util.h
new file mode 100644
index 000000000..b10360fa0
--- /dev/null
+++ b/runtime/libs/benchmark/include/benchmark/Util.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NNFW_BENCHMARK_UTIL_H__
+#define __NNFW_BENCHMARK_UTIL_H__
+
+#include "Result.h"
+#include "CsvWriter.h"
+
+#include <chrono>
+#include <string>
+#include <iostream>
+
+namespace benchmark
+{
+
+inline uint64_t nowMicros()
+{
+  auto time_point = std::chrono::high_resolution_clock::now();
+  auto since_epoch = time_point.time_since_epoch();
+  // default precision of high resolution clock is 10e-9 (nanoseconds)
+  return std::chrono::duration_cast<std::chrono::microseconds>(since_epoch).count();
+}
+
+// TODO Support not only stdout but also ostream
+inline void printResult(const Result &result, bool print_memory)
+{
+  std::cout << "===================================" << std::endl;
+  std::cout << getPhaseString(Phase::MODEL_LOAD) << " takes " << result.getModelLoadTime() / 1e3
+            << " ms" << std::endl;
+  std::cout << getPhaseString(Phase::PREPARE) << "    takes " << result.getPrepareTime() / 1e3
+            << " ms" << std::endl;
+  std::cout << getPhaseString(Phase::EXECUTE) << "    takes " << std::endl;
+  std::cout << "- Min:  " << result.getExecuteTimeMin() / 1e3 << " ms" << std::endl;
+  std::cout << "- Max:  " << result.getExecuteTimeMax() / 1e3 << " ms" << std::endl;
+  std::cout << "- Mean: " << result.getExecuteTimeMean() / 1e3 << " ms" << std::endl;
+  std::cout << "===================================" << std::endl;
+
+  if (print_memory == false)
+    return;
+
+  std::cout << "RSS" << std::endl;
+  std::cout << "- " << getPhaseString(Phase::MODEL_LOAD) << " takes " << result.getModelLoadRss()
+            << " kb" << std::endl;
+  std::cout << "- " << getPhaseString(Phase::PREPARE) << "    takes " << result.getPrepareRss()
+            << " kb" << std::endl;
+  std::cout << "- " << getPhaseString(Phase::EXECUTE) << "    takes " << result.getExecuteRss()
+            << " kb" << std::endl;
+  std::cout << "- PEAK "
+            << "      takes " << result.getPeakRss() << " kb" << std::endl;
+  std::cout << "===================================" << std::endl;
+  std::cout << "HWM" << std::endl;
+  std::cout << "- " << getPhaseString(Phase::MODEL_LOAD) << " takes " << result.getModelLoadHwm()
+            << " kb" << std::endl;
+  std::cout << "- " << getPhaseString(Phase::PREPARE) << "    takes " << result.getPrepareHwm()
+            << " kb" << std::endl;
+  std::cout << "- " << getPhaseString(Phase::EXECUTE) << "    takes " << result.getExecuteHwm()
+            << " kb" << std::endl;
+  std::cout << "- PEAK "
+            << "      takes " << result.getPeakHwm() << " kb" << std::endl;
+  std::cout << "===================================" << std::endl;
+}
+
+// TODO Support not only csv but also other datafile format such as xml, json, ...
+inline void writeResult(const Result &result, const std::string &exec, const std::string &model,
+                        const std::string &backend)
+{
+  std::string csv_filename = exec + "-" + model + "-" + backend + ".csv";
+
+  // write to csv
+  CsvWriter writer(csv_filename);
+  writer << model << backend << result.getModelLoadTime() / 1e3 << result.getPrepareTime() / 1e3
+         << result.getExecuteTimeMin() / 1e3 << result.getExecuteTimeMax() / 1e3
+         << result.getExecuteTimeMean() / 1e3 << result.getModelLoadRss() << result.getPrepareRss()
+         << result.getExecuteRss() << result.getPeakRss() << result.getModelLoadHwm()
+         << result.getPrepareHwm() << result.getExecuteHwm() << result.getPeakHwm();
+
+  bool done = writer.done();
+
+  std::cout << "Writing to " << csv_filename << " is ";
+  if (done)
+    std::cout << "done" << std::endl;
+  else
+    std::cout << "failed" << std::endl;
+}
+
+} // namespace benchmark
+
+#endif // __NNFW_BENCHMARK_UTIL_H__
diff --git a/runtime/libs/benchmark/src/CsvWriter.cpp b/runtime/libs/benchmark/src/CsvWriter.cpp
new file mode 100644
index 000000000..9f2c5b09d
--- /dev/null
+++ b/runtime/libs/benchmark/src/CsvWriter.cpp
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "benchmark/CsvWriter.h"
+#include <cassert>
+
+namespace
+{
+
+const std::vector<std::string> csv_header{
+#include "benchmark/CsvHeader.lst"
+};
+
+} // namespace anonymous
+
+namespace benchmark
+{
+
+CsvWriter::CsvWriter(const std::string &csv_filename) : CsvWriter(csv_filename, csv_header)
+{
+  // DO NOTHING
+}
+
+CsvWriter::CsvWriter(const std::string &csv_filename, const std::vector<std::string> &header)
+    : _ofs(csv_filename), _header_size(header.size()), _col_idx(0)
+{
+  assert(csv_filename.empty() == false);
+  assert(header.size() != 0);
+  assert(_ofs.is_open());
+
+  writeHeader(header);
+}
+
+CsvWriter::~CsvWriter()
+{
+  if (_ofs.is_open())
+    _ofs.close();
+}
+
+void CsvWriter::writeHeader(const std::vector<std::string> &header)
+{
+  for (const auto &col : header)
+    write(col);
+}
+
+void CsvWriter::postWrite()
+{
+  if (++_col_idx == _header_size)
+  {
+    _ofs << newline;
+    _col_idx = 0;
+  }
+  else
+  {
+    _ofs << delimiter;
+  }
+}
+
+void CsvWriter::write(const std::string &val)
+{
+  _ofs << val;
+  postWrite();
+}
+
+void CsvWriter::write(double val)
+{
+  _ofs << val;
+  postWrite();
+}
+
+void CsvWriter::write(uint32_t val)
+{
+  _ofs << val;
+  postWrite();
+}
+
+void CsvWriter::write(char val)
+{
+  _ofs << val;
+  postWrite();
+}
+
+bool CsvWriter::done() { return _col_idx == 0; }
+
+CsvWriter &operator<<(CsvWriter &csvw, const std::string &val)
+{
+  csvw.write(val);
+  return csvw;
+}
+
+CsvWriter &operator<<(CsvWriter &csvw, double val)
+{
+  csvw.write(val);
+  return csvw;
+}
+
+CsvWriter &operator<<(CsvWriter &csvw, uint32_t val)
+{
+  csvw.write(val);
+  return csvw;
+}
+
+CsvWriter &operator<<(CsvWriter &csvw, char val)
+{
+  csvw.write(val);
+  return csvw;
+}
+
+} // namespace benchmark
diff --git a/runtime/libs/benchmark/src/MemoryPoller.cpp b/runtime/libs/benchmark/src/MemoryPoller.cpp
new file mode 100644
index 000000000..436d536e4
--- /dev/null
+++ b/runtime/libs/benchmark/src/MemoryPoller.cpp
@@ -0,0 +1,263 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "benchmark/MemoryPoller.h"
+#include <vector>
+#include <fstream>
+#include <sstream>
+#include <stdexcept>
+#include <cassert>
+#include <iostream>
+
+namespace
+{
+
+const std::string proc_status_path("/proc/self/status");
+const std::string gpu_memory_path("/sys/kernel/debug/mali0/gpu_memory");
+
+bool isStrNumber(const std::string &s)
+{
+  return !s.empty() &&
+         std::find_if(s.begin(), s.end(), [](char c) { return !std::isdigit(c); }) == s.end();
+}
+
+std::vector<std::string> splitLine(std::string line, std::string delimiters = " \n\t")
+{
+  std::vector<std::string> words;
+  size_t prev = 0, pos;
+
+  while ((pos = line.find_first_of(delimiters, prev)) != std::string::npos)
+  {
+    if (pos > prev)
+      words.emplace_back(line.substr(prev, pos - prev));
+    prev = pos + 1;
+  }
+
+  if (prev < line.length())
+    words.emplace_back(line.substr(prev, std::string::npos));
+
+  return words;
+}
+
+std::vector<std::string> getValueFromFileStatus(const std::string &file, const std::string &key)
+{
+  std::ifstream ifs(file);
+  assert(ifs.is_open());
+
+  std::string line;
+  std::vector<std::string> val;
+
+  bool found = false;
+  while (std::getline(ifs, line))
+  {
+    if (line.find(key) != std::string::npos)
+    {
+      found = true;
+      break;
+    }
+  }
+  ifs.close();
+
+  if (!found)
+  {
+    // NOTE. the process which uses gpu resources cannot be there yet at the model-load phase.
+    // At that time, just return empty.
+    return val;
+  }
+
+  val = splitLine(line);
+  return val;
+}
+
+} // namespace anonymous
+
+namespace benchmark
+{
+
+MemoryPoller::MemoryPoller(std::chrono::milliseconds duration, bool gpu_poll)
+    : _duration(duration), _run(false), _term(false), _gpu_poll(gpu_poll)
+{
+  if (prepareMemoryPolling() == false)
+    throw std::runtime_error("failed to prepare memory pooling");
+
+  _thread = std::thread{&MemoryPoller::process, this};
+}
+
+bool MemoryPoller::start(Phase phase)
+{
+  if (std::find(_phases.begin(), _phases.end(), phase) != _phases.end())
+  {
+    std::cerr << getPhaseString(phase) << " is already processing/processed..." << std::endl;
+    return false;
+  }
+
+  {
+    std::lock_guard<std::mutex> lock(_mutex);
+    _phases.emplace_back(phase);
+    _rss_map[phase] = 0;
+    _hwm_map[phase] = 0;
+  }
+
+  _run = true;
+  _cond_var_started.notify_all();
+  return true;
+}
+
+bool MemoryPoller::end(Phase phase)
+{
+  if (std::find(_phases.begin(), _phases.end(), phase) == _phases.end())
+  {
+    std::cerr << getPhaseString(phase) << " is not started..." << std::endl;
+    return false;
+  }
+
+  uint32_t mem = 0;
+  bool stop = false;
+  {
+    std::lock_guard<std::mutex> lock(_mutex);
+    _phases.remove(phase);
+    stop = (_phases.size() == 0);
+  }
+
+  if (_rss_map[phase] == 0)
+  {
+    uint32_t mem = getVmRSS();
+    if (_gpu_poll)
+    {
+      mem += getGpuMemory();
+    }
+    _rss_map[phase] = mem;
+  }
+
+  if (_hwm_map[phase] == 0)
+  {
+    uint32_t mem = getVmHWM();
+    if (_gpu_poll)
+    {
+      mem += getGpuMemory();
+    }
+    _hwm_map[phase] = mem;
+  }
+
+  if (stop)
+  {
+    _run = false;
+    _cond_var_started.notify_all();
+  }
+
+  return true;
+}
+
+void MemoryPoller::process()
+{
+  std::unique_lock<std::mutex> lock_started(_mutex_started);
+  while (true)
+  {
+    _cond_var_started.wait(lock_started, [&]() { return _run || _term; });
+    if (_term)
+      break;
+
+    std::unique_lock<std::mutex> lock(_mutex);
+
+    uint32_t cur_rss = getVmRSS();
+    uint32_t cur_hwm = getVmHWM();
+    if (_gpu_poll)
+    {
+      auto gpu_mem = getGpuMemory();
+      cur_rss += gpu_mem;
+      cur_hwm += gpu_mem;
+    }
+
+    for (auto &phase : _phases)
+    {
+      auto &rss = _rss_map.at(phase);
+      if (rss < cur_rss)
+        rss = cur_rss;
+      // hwm is gradually increasing
+      auto &hwm = _hwm_map.at(phase);
+      hwm = cur_hwm;
+    }
+
+    lock.unlock();
+
+    std::this_thread::sleep_for(std::chrono::milliseconds(_duration));
+  }
+}
+
+bool MemoryPoller::prepareMemoryPolling()
+{
+  // VmRSS
+  {
+    std::ifstream ifs(proc_status_path);
+    if (!ifs.is_open())
+    {
+      std::cerr << "failed to open " << proc_status_path << std::endl;
+      return false;
+    }
+    ifs.close();
+  }
+
+  // (Additionally) GpuMemory
+  if (_gpu_poll)
+  {
+    std::ifstream ifs(gpu_memory_path);
+    if (!ifs.is_open())
+    {
+      std::cerr << "failed to open " << gpu_memory_path << std::endl;
+      return false;
+    }
+    ifs.close();
+
+    // Needs process name
+    auto val = getValueFromFileStatus(proc_status_path, "Name");
+    assert(val.size() != 0);
+    _process_name = val[1];
+  }
+
+  return true;
+}
+
+uint32_t MemoryPoller::getVmRSS()
+{
+  auto val = getValueFromFileStatus(proc_status_path, "VmRSS");
+  if (val.size() == 0)
+    return 0;
+  assert(isStrNumber(val[1]));
+  return std::stoul(val[1]);
+}
+
+uint32_t MemoryPoller::getVmHWM()
+{
+  auto val = getValueFromFileStatus(proc_status_path, "VmHWM");
+  if (val.size() == 0)
+    return 0;
+  // key: value
+  assert(isStrNumber(val[1]));
+  return std::stoul(val[1]);
+}
+
+uint32_t MemoryPoller::getGpuMemory()
+{
+  assert(!_process_name.empty());
+  auto val = getValueFromFileStatus(gpu_memory_path, _process_name);
+  if (val.size() == 0)
+    return 0;
+  // process_name -> pid -> gpu_mem -> max_gpu_mem
+  assert(isStrNumber(val[2]));
+  return std::stoul(val[2]);
+}
+
+} // namespace benchmark
diff --git a/runtime/libs/cpp14/CMakeLists.txt b/runtime/libs/cpp14/CMakeLists.txt
new file mode 100644
index 000000000..bba9e132d
--- /dev/null
+++ b/runtime/libs/cpp14/CMakeLists.txt
@@ -0,0 +1,2 @@
+add_library(nnfw_lib_cpp14 INTERFACE)
+target_include_directories(nnfw_lib_cpp14 INTERFACE ${CMAKE_CURRENT_SOURCE_DIR}/include)
diff --git a/runtime/libs/cpp14/include/cpp14/memory.h b/runtime/libs/cpp14/include/cpp14/memory.h
new file mode 100644
index 000000000..7070e1c99
--- /dev/null
+++ b/runtime/libs/cpp14/include/cpp14/memory.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file memory.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief This file contains @c make_unique which is not supported by C++11
+ * @details Implementation is based on http://isocpp.org/files/papers/N3656.txt
+ */
+#ifndef __NNFW_CPP14_MEMORY_H__
+#define __NNFW_CPP14_MEMORY_H__
+
+#include <memory>
+
+namespace nnfw
+{
+namespace cpp14
+{
+
+template <typename T> struct _Unique_if
+{
+  typedef std::unique_ptr<T> _Single_object;
+};
+
+template <typename T> struct _Unique_if<T[]>
+{
+  typedef std::unique_ptr<T[]> _Unknown_bound;
+};
+
+template <typename T, size_t N> struct _Unique_if<T[N]>
+{
+  typedef void _Known_bound;
+};
+
+template <typename T, typename... Args>
+typename _Unique_if<T>::_Single_object make_unique(Args &&... args)
+{
+  return std::unique_ptr<T>(new T(std::forward<Args>(args)...));
+}
+
+template <typename T> typename _Unique_if<T>::_Unknown_bound make_unique(size_t n)
+{
+  typedef typename std::remove_extent<T>::type U;
+  return std::unique_ptr<T>(new U[n]());
+}
+
+template <typename T, typename... Args>
+typename _Unique_if<T>::_Known_bound make_unique(Args &&...) = delete;
+
+} // namespace cpp14
+} // namespace nnfw
+
+#endif // __NNFW_CPP14_MEMORY_H__
diff --git a/runtime/libs/jsoncpp/CMakeLists.txt b/runtime/libs/jsoncpp/CMakeLists.txt
new file mode 100644
index 000000000..5720cec5b
--- /dev/null
+++ b/runtime/libs/jsoncpp/CMakeLists.txt
@@ -0,0 +1,6 @@
+file(GLOB_RECURSE SRCS "*.cpp")
+
+add_library(jsoncpp STATIC ${SRCS})
+set_property(TARGET jsoncpp PROPERTY POSITION_INDEPENDENT_CODE ON)
+set_property(TARGET jsoncpp APPEND PROPERTY INTERFACE_INCLUDE_DIRECTORIES
+  $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}>)
diff --git a/runtime/libs/jsoncpp/README.md b/runtime/libs/jsoncpp/README.md
new file mode 100644
index 000000000..da5a06d71
--- /dev/null
+++ b/runtime/libs/jsoncpp/README.md
@@ -0,0 +1,11 @@
+# Origin of source code
+
+This library is based on Json-cpp amalgated header and cpp files(https://github.com/open-source-parsers/jsoncpp/wiki/Amalgamated)
+
+# Background
+
+Since jsoncpp on tizen does not support static jsoncpp library, nnfw project will link this local library.
+
+# Version
+
+- 1.7.7 : https://github.com/open-source-parsers/jsoncpp/archive/1.7.7.tar.gz
diff --git a/runtime/libs/jsoncpp/json/json-forwards.h b/runtime/libs/jsoncpp/json/json-forwards.h
new file mode 100644
index 000000000..9fe95c055
--- /dev/null
+++ b/runtime/libs/jsoncpp/json/json-forwards.h
@@ -0,0 +1,315 @@
+/// Json-cpp amalgated forward header (http://jsoncpp.sourceforge.net/).
+/// It is intended to be used with #include "json/json-forwards.h"
+/// This header provides forward declaration for all JsonCpp types.
+
+// //////////////////////////////////////////////////////////////////////
+// Beginning of content of file: LICENSE
+// //////////////////////////////////////////////////////////////////////
+
+/*
+The JsonCpp library's source code, including accompanying documentation,
+tests and demonstration applications, are licensed under the following
+conditions...
+
+The author (Baptiste Lepilleur) explicitly disclaims copyright in all
+jurisdictions which recognize such a disclaimer. In such jurisdictions,
+this software is released into the Public Domain.
+
+In jurisdictions which do not recognize Public Domain property (e.g. Germany as of
+2010), this software is Copyright (c) 2007-2010 by Baptiste Lepilleur, and is
+released under the terms of the MIT License (see below).
+
+In jurisdictions which recognize Public Domain property, the user of this
+software may choose to accept it either as 1) Public Domain, 2) under the
+conditions of the MIT License (see below), or 3) under the terms of dual
+Public Domain/MIT License conditions described here, as they choose.
+
+The MIT License is about as close to Public Domain as a license can get, and is
+described in clear, concise terms at:
+
+   http://en.wikipedia.org/wiki/MIT_License
+
+The full text of the MIT License follows:
+
+========================================================================
+Copyright (c) 2007-2010 Baptiste Lepilleur
+
+Permission is hereby granted, free of charge, to any person
+obtaining a copy of this software and associated documentation
+files (the "Software"), to deal in the Software without
+restriction, including without limitation the rights to use, copy,
+modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be
+included in all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+========================================================================
+(END LICENSE TEXT)
+
+The MIT license is compatible with both the GPL and commercial
+software, affording one all of the rights of Public Domain with the
+minor nuisance of being required to keep the above copyright notice
+and license text in the source code. Note also that by accepting the
+Public Domain "license" you can re-license your copy using whatever
+license you like.
+
+*/
+
+// //////////////////////////////////////////////////////////////////////
+// End of content of file: LICENSE
+// //////////////////////////////////////////////////////////////////////
+
+#ifndef JSON_FORWARD_AMALGATED_H_INCLUDED
+#define JSON_FORWARD_AMALGATED_H_INCLUDED
+/// If defined, indicates that the source file is amalgated
+/// to prevent private header inclusion.
+#define JSON_IS_AMALGAMATION
+
+// //////////////////////////////////////////////////////////////////////
+// Beginning of content of file: include/json/config.h
+// //////////////////////////////////////////////////////////////////////
+
+// Copyright 2007-2010 Baptiste Lepilleur
+// Distributed under MIT license, or public domain if desired and
+// recognized in your jurisdiction.
+// See file LICENSE for detail or copy at http://jsoncpp.sourceforge.net/LICENSE
+
+#ifndef JSON_CONFIG_H_INCLUDED
+#define JSON_CONFIG_H_INCLUDED
+#include <stddef.h>
+#include <string>   //typedef String
+#include <stdint.h> //typedef int64_t, uint64_t
+
+/// If defined, indicates that json library is embedded in CppTL library.
+//# define JSON_IN_CPPTL 1
+
+/// If defined, indicates that json may leverage CppTL library
+//#  define JSON_USE_CPPTL 1
+/// If defined, indicates that cpptl vector based map should be used instead of
+/// std::map
+/// as Value container.
+//#  define JSON_USE_CPPTL_SMALLMAP 1
+
+// If non-zero, the library uses exceptions to report bad input instead of C
+// assertion macros. The default is to use exceptions.
+#ifndef JSON_USE_EXCEPTION
+#define JSON_USE_EXCEPTION 1
+#endif
+
+/// If defined, indicates that the source file is amalgated
+/// to prevent private header inclusion.
+/// Remarks: it is automatically defined in the generated amalgated header.
+// #define JSON_IS_AMALGAMATION
+
+#ifdef JSON_IN_CPPTL
+#include <cpptl/config.h>
+#ifndef JSON_USE_CPPTL
+#define JSON_USE_CPPTL 1
+#endif
+#endif
+
+#ifdef JSON_IN_CPPTL
+#define JSON_API CPPTL_API
+#elif defined(JSON_DLL_BUILD)
+#if defined(_MSC_VER) || defined(__MINGW32__)
+#define JSON_API __declspec(dllexport)
+#define JSONCPP_DISABLE_DLL_INTERFACE_WARNING
+#endif // if defined(_MSC_VER)
+#elif defined(JSON_DLL)
+#if defined(_MSC_VER) || defined(__MINGW32__)
+#define JSON_API __declspec(dllimport)
+#define JSONCPP_DISABLE_DLL_INTERFACE_WARNING
+#endif // if defined(_MSC_VER)
+#endif // ifdef JSON_IN_CPPTL
+#if !defined(JSON_API)
+#define JSON_API
+#endif
+
+// If JSON_NO_INT64 is defined, then Json only support C++ "int" type for
+// integer
+// Storages, and 64 bits integer support is disabled.
+// #define JSON_NO_INT64 1
+
+#if defined(_MSC_VER) // MSVC
+#if _MSC_VER <= 1200  // MSVC 6
+                      // Microsoft Visual Studio 6 only support conversion from __int64 to double
+                      // (no conversion from unsigned __int64).
+#define JSON_USE_INT64_DOUBLE_CONVERSION 1
+// Disable warning 4786 for VS6 caused by STL (identifier was truncated to '255'
+// characters in the debug information)
+// All projects I've ever seen with VS6 were using this globally (not bothering
+// with pragma push/pop).
+#pragma warning(disable : 4786)
+#endif // MSVC 6
+
+#if _MSC_VER >= 1500 // MSVC 2008
+                     /// Indicates that the following function is deprecated.
+#define JSONCPP_DEPRECATED(message) __declspec(deprecated(message))
+#endif
+
+#endif // defined(_MSC_VER)
+
+// In c++11 the override keyword allows you to explicity define that a function
+// is intended to override the base-class version.  This makes the code more
+// managable and fixes a set of common hard-to-find bugs.
+#if __cplusplus >= 201103L
+#define JSONCPP_OVERRIDE override
+#elif defined(_MSC_VER) && _MSC_VER > 1600
+#define JSONCPP_OVERRIDE override
+#else
+#define JSONCPP_OVERRIDE
+#endif
+
+#ifndef JSON_HAS_RVALUE_REFERENCES
+
+#if defined(_MSC_VER) && _MSC_VER >= 1600 // MSVC >= 2010
+#define JSON_HAS_RVALUE_REFERENCES 1
+#endif // MSVC >= 2010
+
+#ifdef __clang__
+#if __has_feature(cxx_rvalue_references)
+#define JSON_HAS_RVALUE_REFERENCES 1
+#endif // has_feature
+
+#elif defined __GNUC__ // not clang (gcc comes later since clang emulates gcc)
+#if defined(__GXX_EXPERIMENTAL_CXX0X__) || (__cplusplus >= 201103L)
+#define JSON_HAS_RVALUE_REFERENCES 1
+#endif // GXX_EXPERIMENTAL
+
+#endif // __clang__ || __GNUC__
+
+#endif // not defined JSON_HAS_RVALUE_REFERENCES
+
+#ifndef JSON_HAS_RVALUE_REFERENCES
+#define JSON_HAS_RVALUE_REFERENCES 0
+#endif
+
+#ifdef __clang__
+#elif defined __GNUC__ // not clang (gcc comes later since clang emulates gcc)
+#if (__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5))
+#define JSONCPP_DEPRECATED(message) __attribute__((deprecated(message)))
+#elif (__GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 1))
+#define JSONCPP_DEPRECATED(message) __attribute__((__deprecated__))
+#endif // GNUC version
+#endif // __clang__ || __GNUC__
+
+#if !defined(JSONCPP_DEPRECATED)
+#define JSONCPP_DEPRECATED(message)
+#endif // if !defined(JSONCPP_DEPRECATED)
+
+#if __GNUC__ >= 6
+#define JSON_USE_INT64_DOUBLE_CONVERSION 1
+#endif
+
+#if !defined(JSON_IS_AMALGAMATION)
+
+#include "version.h"
+
+#if JSONCPP_USING_SECURE_MEMORY
+#include "allocator.h" //typedef Allocator
+#endif
+
+#endif // if !defined(JSON_IS_AMALGAMATION)
+
+namespace Json
+{
+typedef int Int;
+typedef unsigned int UInt;
+#if defined(JSON_NO_INT64)
+typedef int LargestInt;
+typedef unsigned int LargestUInt;
+#undef JSON_HAS_INT64
+#else                 // if defined(JSON_NO_INT64)
+// For Microsoft Visual use specific types as long long is not supported
+#if defined(_MSC_VER) // Microsoft Visual Studio
+typedef __int64 Int64;
+typedef unsigned __int64 UInt64;
+#else                 // if defined(_MSC_VER) // Other platforms, use long long
+typedef int64_t Int64;
+typedef uint64_t UInt64;
+#endif                // if defined(_MSC_VER)
+typedef Int64 LargestInt;
+typedef UInt64 LargestUInt;
+#define JSON_HAS_INT64
+#endif // if defined(JSON_NO_INT64)
+#if JSONCPP_USING_SECURE_MEMORY
+#define JSONCPP_STRING std::basic_string<char, std::char_traits<char>, Json::SecureAllocator<char>>
+#define JSONCPP_OSTRINGSTREAM \
+  std::basic_ostringstream<char, std::char_traits<char>, Json::SecureAllocator<char>>
+#define JSONCPP_OSTREAM std::basic_ostream<char, std::char_traits<char>>
+#define JSONCPP_ISTRINGSTREAM \
+  std::basic_istringstream<char, std::char_traits<char>, Json::SecureAllocator<char>>
+#define JSONCPP_ISTREAM std::istream
+#else
+#define JSONCPP_STRING std::string
+#define JSONCPP_OSTRINGSTREAM std::ostringstream
+#define JSONCPP_OSTREAM std::ostream
+#define JSONCPP_ISTRINGSTREAM std::istringstream
+#define JSONCPP_ISTREAM std::istream
+#endif // if JSONCPP_USING_SECURE_MEMORY
+} // end namespace Json
+
+#endif // JSON_CONFIG_H_INCLUDED
+
+// //////////////////////////////////////////////////////////////////////
+// End of content of file: include/json/config.h
+// //////////////////////////////////////////////////////////////////////
+
+// //////////////////////////////////////////////////////////////////////
+// Beginning of content of file: include/json/forwards.h
+// //////////////////////////////////////////////////////////////////////
+
+// Copyright 2007-2010 Baptiste Lepilleur
+// Distributed under MIT license, or public domain if desired and
+// recognized in your jurisdiction.
+// See file LICENSE for detail or copy at http://jsoncpp.sourceforge.net/LICENSE
+
+#ifndef JSON_FORWARDS_H_INCLUDED
+#define JSON_FORWARDS_H_INCLUDED
+
+#if !defined(JSON_IS_AMALGAMATION)
+#include "config.h"
+#endif // if !defined(JSON_IS_AMALGAMATION)
+
+namespace Json
+{
+
+// writer.h
+class FastWriter;
+class StyledWriter;
+
+// reader.h
+class Reader;
+
+// features.h
+class Features;
+
+// value.h
+typedef unsigned int ArrayIndex;
+class StaticString;
+class Path;
+class PathArgument;
+class Value;
+class ValueIteratorBase;
+class ValueIterator;
+class ValueConstIterator;
+
+} // namespace Json
+
+#endif // JSON_FORWARDS_H_INCLUDED
+
+// //////////////////////////////////////////////////////////////////////
+// End of content of file: include/json/forwards.h
+// //////////////////////////////////////////////////////////////////////
+
+#endif // ifndef JSON_FORWARD_AMALGATED_H_INCLUDED
diff --git a/runtime/libs/jsoncpp/json/json.h b/runtime/libs/jsoncpp/json/json.h
new file mode 100644
index 000000000..19c591267
--- /dev/null
+++ b/runtime/libs/jsoncpp/json/json.h
@@ -0,0 +1,2133 @@
+/// Json-cpp amalgated header (http://jsoncpp.sourceforge.net/).
+/// It is intended to be used with #include "json/json.h"
+
+// //////////////////////////////////////////////////////////////////////
+// Beginning of content of file: LICENSE
+// //////////////////////////////////////////////////////////////////////
+
+/*
+The JsonCpp library's source code, including accompanying documentation,
+tests and demonstration applications, are licensed under the following
+conditions...
+
+The author (Baptiste Lepilleur) explicitly disclaims copyright in all
+jurisdictions which recognize such a disclaimer. In such jurisdictions,
+this software is released into the Public Domain.
+
+In jurisdictions which do not recognize Public Domain property (e.g. Germany as of
+2010), this software is Copyright (c) 2007-2010 by Baptiste Lepilleur, and is
+released under the terms of the MIT License (see below).
+
+In jurisdictions which recognize Public Domain property, the user of this
+software may choose to accept it either as 1) Public Domain, 2) under the
+conditions of the MIT License (see below), or 3) under the terms of dual
+Public Domain/MIT License conditions described here, as they choose.
+
+The MIT License is about as close to Public Domain as a license can get, and is
+described in clear, concise terms at:
+
+   http://en.wikipedia.org/wiki/MIT_License
+
+The full text of the MIT License follows:
+
+========================================================================
+Copyright (c) 2007-2010 Baptiste Lepilleur
+
+Permission is hereby granted, free of charge, to any person
+obtaining a copy of this software and associated documentation
+files (the "Software"), to deal in the Software without
+restriction, including without limitation the rights to use, copy,
+modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be
+included in all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+========================================================================
+(END LICENSE TEXT)
+
+The MIT license is compatible with both the GPL and commercial
+software, affording one all of the rights of Public Domain with the
+minor nuisance of being required to keep the above copyright notice
+and license text in the source code. Note also that by accepting the
+Public Domain "license" you can re-license your copy using whatever
+license you like.
+
+*/
+
+// //////////////////////////////////////////////////////////////////////
+// End of content of file: LICENSE
+// //////////////////////////////////////////////////////////////////////
+
+#ifndef JSON_AMALGATED_H_INCLUDED
+#define JSON_AMALGATED_H_INCLUDED
+/// If defined, indicates that the source file is amalgated
+/// to prevent private header inclusion.
+#define JSON_IS_AMALGAMATION
+
+// //////////////////////////////////////////////////////////////////////
+// Beginning of content of file: include/json/version.h
+// //////////////////////////////////////////////////////////////////////
+
+// DO NOT EDIT. This file (and "version") is generated by CMake.
+// Run CMake configure step to update it.
+#ifndef JSON_VERSION_H_INCLUDED
+#define JSON_VERSION_H_INCLUDED
+
+#define JSONCPP_VERSION_STRING "1.7.7"
+#define JSONCPP_VERSION_MAJOR 1
+#define JSONCPP_VERSION_MINOR 7
+#define JSONCPP_VERSION_PATCH 7
+#define JSONCPP_VERSION_QUALIFIER
+#define JSONCPP_VERSION_HEXA \
+  ((JSONCPP_VERSION_MAJOR << 24) | (JSONCPP_VERSION_MINOR << 16) | (JSONCPP_VERSION_PATCH << 8))
+
+#ifdef JSONCPP_USING_SECURE_MEMORY
+#undef JSONCPP_USING_SECURE_MEMORY
+#endif
+#define JSONCPP_USING_SECURE_MEMORY 0
+// If non-zero, the library zeroes any memory that it has allocated before
+// it frees its memory.
+
+#endif // JSON_VERSION_H_INCLUDED
+
+// //////////////////////////////////////////////////////////////////////
+// End of content of file: include/json/version.h
+// //////////////////////////////////////////////////////////////////////
+
+// //////////////////////////////////////////////////////////////////////
+// Beginning of content of file: include/json/config.h
+// //////////////////////////////////////////////////////////////////////
+
+// Copyright 2007-2010 Baptiste Lepilleur
+// Distributed under MIT license, or public domain if desired and
+// recognized in your jurisdiction.
+// See file LICENSE for detail or copy at http://jsoncpp.sourceforge.net/LICENSE
+
+#ifndef JSON_CONFIG_H_INCLUDED
+#define JSON_CONFIG_H_INCLUDED
+#include <stddef.h>
+#include <string>   //typedef String
+#include <stdint.h> //typedef int64_t, uint64_t
+
+/// If defined, indicates that json library is embedded in CppTL library.
+//# define JSON_IN_CPPTL 1
+
+/// If defined, indicates that json may leverage CppTL library
+//#  define JSON_USE_CPPTL 1
+/// If defined, indicates that cpptl vector based map should be used instead of
+/// std::map
+/// as Value container.
+//#  define JSON_USE_CPPTL_SMALLMAP 1
+
+// If non-zero, the library uses exceptions to report bad input instead of C
+// assertion macros. The default is to use exceptions.
+#ifndef JSON_USE_EXCEPTION
+#define JSON_USE_EXCEPTION 1
+#endif
+
+/// If defined, indicates that the source file is amalgated
+/// to prevent private header inclusion.
+/// Remarks: it is automatically defined in the generated amalgated header.
+// #define JSON_IS_AMALGAMATION
+
+#ifdef JSON_IN_CPPTL
+#include <cpptl/config.h>
+#ifndef JSON_USE_CPPTL
+#define JSON_USE_CPPTL 1
+#endif
+#endif
+
+#ifdef JSON_IN_CPPTL
+#define JSON_API CPPTL_API
+#elif defined(JSON_DLL_BUILD)
+#if defined(_MSC_VER) || defined(__MINGW32__)
+#define JSON_API __declspec(dllexport)
+#define JSONCPP_DISABLE_DLL_INTERFACE_WARNING
+#endif // if defined(_MSC_VER)
+#elif defined(JSON_DLL)
+#if defined(_MSC_VER) || defined(__MINGW32__)
+#define JSON_API __declspec(dllimport)
+#define JSONCPP_DISABLE_DLL_INTERFACE_WARNING
+#endif // if defined(_MSC_VER)
+#endif // ifdef JSON_IN_CPPTL
+#if !defined(JSON_API)
+#define JSON_API
+#endif
+
+// If JSON_NO_INT64 is defined, then Json only support C++ "int" type for
+// integer
+// Storages, and 64 bits integer support is disabled.
+// #define JSON_NO_INT64 1
+
+#if defined(_MSC_VER) // MSVC
+#if _MSC_VER <= 1200  // MSVC 6
+                      // Microsoft Visual Studio 6 only support conversion from __int64 to double
+                      // (no conversion from unsigned __int64).
+#define JSON_USE_INT64_DOUBLE_CONVERSION 1
+// Disable warning 4786 for VS6 caused by STL (identifier was truncated to '255'
+// characters in the debug information)
+// All projects I've ever seen with VS6 were using this globally (not bothering
+// with pragma push/pop).
+#pragma warning(disable : 4786)
+#endif // MSVC 6
+
+#if _MSC_VER >= 1500 // MSVC 2008
+                     /// Indicates that the following function is deprecated.
+#define JSONCPP_DEPRECATED(message) __declspec(deprecated(message))
+#endif
+
+#endif // defined(_MSC_VER)
+
+// In c++11 the override keyword allows you to explicity define that a function
+// is intended to override the base-class version.  This makes the code more
+// managable and fixes a set of common hard-to-find bugs.
+#if __cplusplus >= 201103L
+#define JSONCPP_OVERRIDE override
+#elif defined(_MSC_VER) && _MSC_VER > 1600
+#define JSONCPP_OVERRIDE override
+#else
+#define JSONCPP_OVERRIDE
+#endif
+
+#ifndef JSON_HAS_RVALUE_REFERENCES
+
+#if defined(_MSC_VER) && _MSC_VER >= 1600 // MSVC >= 2010
+#define JSON_HAS_RVALUE_REFERENCES 1
+#endif // MSVC >= 2010
+
+#ifdef __clang__
+#if __has_feature(cxx_rvalue_references)
+#define JSON_HAS_RVALUE_REFERENCES 1
+#endif // has_feature
+
+#elif defined __GNUC__ // not clang (gcc comes later since clang emulates gcc)
+#if defined(__GXX_EXPERIMENTAL_CXX0X__) || (__cplusplus >= 201103L)
+#define JSON_HAS_RVALUE_REFERENCES 1
+#endif // GXX_EXPERIMENTAL
+
+#endif // __clang__ || __GNUC__
+
+#endif // not defined JSON_HAS_RVALUE_REFERENCES
+
+#ifndef JSON_HAS_RVALUE_REFERENCES
+#define JSON_HAS_RVALUE_REFERENCES 0
+#endif
+
+#ifdef __clang__
+#elif defined __GNUC__ // not clang (gcc comes later since clang emulates gcc)
+#if (__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5))
+#define JSONCPP_DEPRECATED(message) __attribute__((deprecated(message)))
+#elif (__GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 1))
+#define JSONCPP_DEPRECATED(message) __attribute__((__deprecated__))
+#endif // GNUC version
+#endif // __clang__ || __GNUC__
+
+#if !defined(JSONCPP_DEPRECATED)
+#define JSONCPP_DEPRECATED(message)
+#endif // if !defined(JSONCPP_DEPRECATED)
+
+#if __GNUC__ >= 6
+#define JSON_USE_INT64_DOUBLE_CONVERSION 1
+#endif
+
+#if !defined(JSON_IS_AMALGAMATION)
+
+#include "version.h"
+
+#if JSONCPP_USING_SECURE_MEMORY
+#include "allocator.h" //typedef Allocator
+#endif
+
+#endif // if !defined(JSON_IS_AMALGAMATION)
+
+namespace Json
+{
+typedef int Int;
+typedef unsigned int UInt;
+#if defined(JSON_NO_INT64)
+typedef int LargestInt;
+typedef unsigned int LargestUInt;
+#undef JSON_HAS_INT64
+#else                 // if defined(JSON_NO_INT64)
+// For Microsoft Visual use specific types as long long is not supported
+#if defined(_MSC_VER) // Microsoft Visual Studio
+typedef __int64 Int64;
+typedef unsigned __int64 UInt64;
+#else                 // if defined(_MSC_VER) // Other platforms, use long long
+typedef int64_t Int64;
+typedef uint64_t UInt64;
+#endif                // if defined(_MSC_VER)
+typedef Int64 LargestInt;
+typedef UInt64 LargestUInt;
+#define JSON_HAS_INT64
+#endif // if defined(JSON_NO_INT64)
+#if JSONCPP_USING_SECURE_MEMORY
+#define JSONCPP_STRING std::basic_string<char, std::char_traits<char>, Json::SecureAllocator<char>>
+#define JSONCPP_OSTRINGSTREAM \
+  std::basic_ostringstream<char, std::char_traits<char>, Json::SecureAllocator<char>>
+#define JSONCPP_OSTREAM std::basic_ostream<char, std::char_traits<char>>
+#define JSONCPP_ISTRINGSTREAM \
+  std::basic_istringstream<char, std::char_traits<char>, Json::SecureAllocator<char>>
+#define JSONCPP_ISTREAM std::istream
+#else
+#define JSONCPP_STRING std::string
+#define JSONCPP_OSTRINGSTREAM std::ostringstream
+#define JSONCPP_OSTREAM std::ostream
+#define JSONCPP_ISTRINGSTREAM std::istringstream
+#define JSONCPP_ISTREAM std::istream
+#endif // if JSONCPP_USING_SECURE_MEMORY
+} // end namespace Json
+
+#endif // JSON_CONFIG_H_INCLUDED
+
+// //////////////////////////////////////////////////////////////////////
+// End of content of file: include/json/config.h
+// //////////////////////////////////////////////////////////////////////
+
+// //////////////////////////////////////////////////////////////////////
+// Beginning of content of file: include/json/forwards.h
+// //////////////////////////////////////////////////////////////////////
+
+// Copyright 2007-2010 Baptiste Lepilleur
+// Distributed under MIT license, or public domain if desired and
+// recognized in your jurisdiction.
+// See file LICENSE for detail or copy at http://jsoncpp.sourceforge.net/LICENSE
+
+#ifndef JSON_FORWARDS_H_INCLUDED
+#define JSON_FORWARDS_H_INCLUDED
+
+#if !defined(JSON_IS_AMALGAMATION)
+#include "config.h"
+#endif // if !defined(JSON_IS_AMALGAMATION)
+
+namespace Json
+{
+
+// writer.h
+class FastWriter;
+class StyledWriter;
+
+// reader.h
+class Reader;
+
+// features.h
+class Features;
+
+// value.h
+typedef unsigned int ArrayIndex;
+class StaticString;
+class Path;
+class PathArgument;
+class Value;
+class ValueIteratorBase;
+class ValueIterator;
+class ValueConstIterator;
+
+} // namespace Json
+
+#endif // JSON_FORWARDS_H_INCLUDED
+
+// //////////////////////////////////////////////////////////////////////
+// End of content of file: include/json/forwards.h
+// //////////////////////////////////////////////////////////////////////
+
+// //////////////////////////////////////////////////////////////////////
+// Beginning of content of file: include/json/features.h
+// //////////////////////////////////////////////////////////////////////
+
+// Copyright 2007-2010 Baptiste Lepilleur
+// Distributed under MIT license, or public domain if desired and
+// recognized in your jurisdiction.
+// See file LICENSE for detail or copy at http://jsoncpp.sourceforge.net/LICENSE
+
+#ifndef CPPTL_JSON_FEATURES_H_INCLUDED
+#define CPPTL_JSON_FEATURES_H_INCLUDED
+
+#if !defined(JSON_IS_AMALGAMATION)
+#include "forwards.h"
+#endif // if !defined(JSON_IS_AMALGAMATION)
+
+namespace Json
+{
+
+/** \brief Configuration passed to reader and writer.
+ * This configuration object can be used to force the Reader or Writer
+ * to behave in a standard conforming way.
+ */
+class JSON_API Features
+{
+public:
+  /** \brief A configuration that allows all features and assumes all strings
+   * are UTF-8.
+   * - C & C++ comments are allowed
+   * - Root object can be any JSON value
+   * - Assumes Value strings are encoded in UTF-8
+   */
+  static Features all();
+
+  /** \brief A configuration that is strictly compatible with the JSON
+   * specification.
+   * - Comments are forbidden.
+   * - Root object must be either an array or an object value.
+   * - Assumes Value strings are encoded in UTF-8
+   */
+  static Features strictMode();
+
+  /** \brief Initialize the configuration like JsonConfig::allFeatures;
+   */
+  Features();
+
+  /// \c true if comments are allowed. Default: \c true.
+  bool allowComments_;
+
+  /// \c true if root must be either an array or an object value. Default: \c
+  /// false.
+  bool strictRoot_;
+
+  /// \c true if dropped null placeholders are allowed. Default: \c false.
+  bool allowDroppedNullPlaceholders_;
+
+  /// \c true if numeric object key are allowed. Default: \c false.
+  bool allowNumericKeys_;
+};
+
+} // namespace Json
+
+#endif // CPPTL_JSON_FEATURES_H_INCLUDED
+
+// //////////////////////////////////////////////////////////////////////
+// End of content of file: include/json/features.h
+// //////////////////////////////////////////////////////////////////////
+
+// //////////////////////////////////////////////////////////////////////
+// Beginning of content of file: include/json/value.h
+// //////////////////////////////////////////////////////////////////////
+
+// Copyright 2007-2010 Baptiste Lepilleur
+// Distributed under MIT license, or public domain if desired and
+// recognized in your jurisdiction.
+// See file LICENSE for detail or copy at http://jsoncpp.sourceforge.net/LICENSE
+
+#ifndef CPPTL_JSON_H_INCLUDED
+#define CPPTL_JSON_H_INCLUDED
+
+#if !defined(JSON_IS_AMALGAMATION)
+#include "forwards.h"
+#endif // if !defined(JSON_IS_AMALGAMATION)
+#include <string>
+#include <vector>
+#include <exception>
+
+#ifndef JSON_USE_CPPTL_SMALLMAP
+#include <map>
+#else
+#include <cpptl/smallmap.h>
+#endif
+#ifdef JSON_USE_CPPTL
+#include <cpptl/forwards.h>
+#endif
+
+// Conditional NORETURN attribute on the throw functions would:
+// a) suppress false positives from static code analysis
+// b) possibly improve optimization opportunities.
+#if !defined(JSONCPP_NORETURN)
+#if defined(_MSC_VER)
+#define JSONCPP_NORETURN __declspec(noreturn)
+#elif defined(__GNUC__)
+#define JSONCPP_NORETURN __attribute__((__noreturn__))
+#else
+#define JSONCPP_NORETURN
+#endif
+#endif
+
+// Disable warning C4251: <data member>: <type> needs to have dll-interface to
+// be used by...
+#if defined(JSONCPP_DISABLE_DLL_INTERFACE_WARNING)
+#pragma warning(push)
+#pragma warning(disable : 4251)
+#endif // if defined(JSONCPP_DISABLE_DLL_INTERFACE_WARNING)
+
+/** \brief JSON (JavaScript Object Notation).
+ */
+namespace Json
+{
+
+/** Base class for all exceptions we throw.
+ *
+ * We use nothing but these internally. Of course, STL can throw others.
+ */
+class JSON_API Exception : public std::exception
+{
+public:
+  Exception(JSONCPP_STRING const &msg);
+  ~Exception() throw() JSONCPP_OVERRIDE;
+  char const *what() const throw() JSONCPP_OVERRIDE;
+
+protected:
+  JSONCPP_STRING msg_;
+};
+
+/** Exceptions which the user cannot easily avoid.
+ *
+ * E.g. out-of-memory (when we use malloc), stack-overflow, malicious input
+ *
+ * \remark derived from Json::Exception
+ */
+class JSON_API RuntimeError : public Exception
+{
+public:
+  RuntimeError(JSONCPP_STRING const &msg);
+};
+
+/** Exceptions thrown by JSON_ASSERT/JSON_FAIL macros.
+ *
+ * These are precondition-violations (user bugs) and internal errors (our bugs).
+ *
+ * \remark derived from Json::Exception
+ */
+class JSON_API LogicError : public Exception
+{
+public:
+  LogicError(JSONCPP_STRING const &msg);
+};
+
+/// used internally
+JSONCPP_NORETURN void throwRuntimeError(JSONCPP_STRING const &msg);
+/// used internally
+JSONCPP_NORETURN void throwLogicError(JSONCPP_STRING const &msg);
+
+/** \brief Type of the value held by a Value object.
+ */
+enum ValueType
+{
+  nullValue = 0, ///< 'null' value
+  intValue,      ///< signed integer value
+  uintValue,     ///< unsigned integer value
+  realValue,     ///< double value
+  stringValue,   ///< UTF-8 string value
+  booleanValue,  ///< bool value
+  arrayValue,    ///< array value (ordered list)
+  objectValue    ///< object value (collection of name/value pairs).
+};
+
+enum CommentPlacement
+{
+  commentBefore = 0,      ///< a comment placed on the line before a value
+  commentAfterOnSameLine, ///< a comment just after a value on the same line
+  commentAfter,           ///< a comment on the line after a value (only make sense for
+  /// root value)
+  numberOfCommentPlacement
+};
+
+//# ifdef JSON_USE_CPPTL
+//   typedef CppTL::AnyEnumerator<const char *> EnumMemberNames;
+//   typedef CppTL::AnyEnumerator<const Value &> EnumValues;
+//# endif
+
+/** \brief Lightweight wrapper to tag static string.
+ *
+ * Value constructor and objectValue member assignement takes advantage of the
+ * StaticString and avoid the cost of string duplication when storing the
+ * string or the member name.
+ *
+ * Example of usage:
+ * \code
+ * Json::Value aValue( StaticString("some text") );
+ * Json::Value object;
+ * static const StaticString code("code");
+ * object[code] = 1234;
+ * \endcode
+ */
+class JSON_API StaticString
+{
+public:
+  explicit StaticString(const char *czstring) : c_str_(czstring) {}
+
+  operator const char *() const { return c_str_; }
+
+  const char *c_str() const { return c_str_; }
+
+private:
+  const char *c_str_;
+};
+
+/** \brief Represents a <a HREF="http://www.json.org">JSON</a> value.
+ *
+ * This class is a discriminated union wrapper that can represents a:
+ * - signed integer [range: Value::minInt - Value::maxInt]
+ * - unsigned integer (range: 0 - Value::maxUInt)
+ * - double
+ * - UTF-8 string
+ * - boolean
+ * - 'null'
+ * - an ordered list of Value
+ * - collection of name/value pairs (javascript object)
+ *
+ * The type of the held value is represented by a #ValueType and
+ * can be obtained using type().
+ *
+ * Values of an #objectValue or #arrayValue can be accessed using operator[]()
+ * methods.
+ * Non-const methods will automatically create the a #nullValue element
+ * if it does not exist.
+ * The sequence of an #arrayValue will be automatically resized and initialized
+ * with #nullValue. resize() can be used to enlarge or truncate an #arrayValue.
+ *
+ * The get() methods can be used to obtain default value in the case the
+ * required element does not exist.
+ *
+ * It is possible to iterate over the list of a #objectValue values using
+ * the getMemberNames() method.
+ *
+ * \note #Value string-length fit in size_t, but keys must be < 2^30.
+ * (The reason is an implementation detail.) A #CharReader will raise an
+ * exception if a bound is exceeded to avoid security holes in your app,
+ * but the Value API does *not* check bounds. That is the responsibility
+ * of the caller.
+ */
+class JSON_API Value
+{
+  friend class ValueIteratorBase;
+
+public:
+  typedef std::vector<JSONCPP_STRING> Members;
+  typedef ValueIterator iterator;
+  typedef ValueConstIterator const_iterator;
+  typedef Json::UInt UInt;
+  typedef Json::Int Int;
+#if defined(JSON_HAS_INT64)
+  typedef Json::UInt64 UInt64;
+  typedef Json::Int64 Int64;
+#endif // defined(JSON_HAS_INT64)
+  typedef Json::LargestInt LargestInt;
+  typedef Json::LargestUInt LargestUInt;
+  typedef Json::ArrayIndex ArrayIndex;
+
+  static const Value
+      &null; ///< We regret this reference to a global instance; prefer the simpler Value().
+  static const Value &nullRef;         ///< just a kludge for binary-compatibility; same as null
+  static Value const &nullSingleton(); ///< Prefer this to null or nullRef.
+
+  /// Minimum signed integer value that can be stored in a Json::Value.
+  static const LargestInt minLargestInt;
+  /// Maximum signed integer value that can be stored in a Json::Value.
+  static const LargestInt maxLargestInt;
+  /// Maximum unsigned integer value that can be stored in a Json::Value.
+  static const LargestUInt maxLargestUInt;
+
+  /// Minimum signed int value that can be stored in a Json::Value.
+  static const Int minInt;
+  /// Maximum signed int value that can be stored in a Json::Value.
+  static const Int maxInt;
+  /// Maximum unsigned int value that can be stored in a Json::Value.
+  static const UInt maxUInt;
+
+#if defined(JSON_HAS_INT64)
+  /// Minimum signed 64 bits int value that can be stored in a Json::Value.
+  static const Int64 minInt64;
+  /// Maximum signed 64 bits int value that can be stored in a Json::Value.
+  static const Int64 maxInt64;
+  /// Maximum unsigned 64 bits int value that can be stored in a Json::Value.
+  static const UInt64 maxUInt64;
+#endif // defined(JSON_HAS_INT64)
+
+private:
+#ifndef JSONCPP_DOC_EXCLUDE_IMPLEMENTATION
+  class CZString
+  {
+  public:
+    enum DuplicationPolicy
+    {
+      noDuplication = 0,
+      duplicate,
+      duplicateOnCopy
+    };
+    CZString(ArrayIndex index);
+    CZString(char const *str, unsigned length, DuplicationPolicy allocate);
+    CZString(CZString const &other);
+#if JSON_HAS_RVALUE_REFERENCES
+    CZString(CZString &&other);
+#endif
+    ~CZString();
+    CZString &operator=(CZString other);
+    bool operator<(CZString const &other) const;
+    bool operator==(CZString const &other) const;
+    ArrayIndex index() const;
+    // const char* c_str() const; ///< \deprecated
+    char const *data() const;
+    unsigned length() const;
+    bool isStaticString() const;
+
+  private:
+    void swap(CZString &other);
+
+    struct StringStorage
+    {
+      unsigned policy_ : 2;
+      unsigned length_ : 30; // 1GB max
+    };
+
+    char const *cstr_; // actually, a prefixed string, unless policy is noDup
+    union {
+      ArrayIndex index_;
+      StringStorage storage_;
+    };
+  };
+
+public:
+#ifndef JSON_USE_CPPTL_SMALLMAP
+  typedef std::map<CZString, Value> ObjectValues;
+#else
+  typedef CppTL::SmallMap<CZString, Value> ObjectValues;
+#endif // ifndef JSON_USE_CPPTL_SMALLMAP
+#endif // ifndef JSONCPP_DOC_EXCLUDE_IMPLEMENTATION
+
+public:
+  /** \brief Create a default Value of the given type.
+
+    This is a very useful constructor.
+    To create an empty array, pass arrayValue.
+    To create an empty object, pass objectValue.
+    Another Value can then be set to this one by assignment.
+This is useful since clear() and resize() will not alter types.
+
+    Examples:
+\code
+Json::Value null_value; // null
+Json::Value arr_value(Json::arrayValue); // []
+Json::Value obj_value(Json::objectValue); // {}
+\endcode
+  */
+  Value(ValueType type = nullValue);
+  Value(Int value);
+  Value(UInt value);
+#if defined(JSON_HAS_INT64)
+  Value(Int64 value);
+  Value(UInt64 value);
+#endif // if defined(JSON_HAS_INT64)
+  Value(double value);
+  Value(const char *value);                  ///< Copy til first 0. (NULL causes to seg-fault.)
+  Value(const char *begin, const char *end); ///< Copy all, incl zeroes.
+  /** \brief Constructs a value from a static string.
+
+   * Like other value string constructor but do not duplicate the string for
+   * internal storage. The given string must remain alive after the call to this
+   * constructor.
+   * \note This works only for null-terminated strings. (We cannot change the
+   *   size of this class, so we have nowhere to store the length,
+   *   which might be computed later for various operations.)
+   *
+   * Example of usage:
+   * \code
+   * static StaticString foo("some text");
+   * Json::Value aValue(foo);
+   * \endcode
+   */
+  Value(const StaticString &value);
+  Value(const JSONCPP_STRING &value); ///< Copy data() til size(). Embedded zeroes too.
+#ifdef JSON_USE_CPPTL
+  Value(const CppTL::ConstString &value);
+#endif
+  Value(bool value);
+  /// Deep copy.
+  Value(const Value &other);
+#if JSON_HAS_RVALUE_REFERENCES
+  /// Move constructor
+  Value(Value &&other);
+#endif
+  ~Value();
+
+  /// Deep copy, then swap(other).
+  /// \note Over-write existing comments. To preserve comments, use #swapPayload().
+  Value &operator=(Value other);
+  /// Swap everything.
+  void swap(Value &other);
+  /// Swap values but leave comments and source offsets in place.
+  void swapPayload(Value &other);
+
+  ValueType type() const;
+
+  /// Compare payload only, not comments etc.
+  bool operator<(const Value &other) const;
+  bool operator<=(const Value &other) const;
+  bool operator>=(const Value &other) const;
+  bool operator>(const Value &other) const;
+  bool operator==(const Value &other) const;
+  bool operator!=(const Value &other) const;
+  int compare(const Value &other) const;
+
+  const char *asCString() const; ///< Embedded zeroes could cause you trouble!
+#if JSONCPP_USING_SECURE_MEMORY
+  unsigned getCStringLength() const; // Allows you to understand the length of the CString
+#endif
+  JSONCPP_STRING asString() const; ///< Embedded zeroes are possible.
+  /** Get raw char* of string-value.
+   *  \return false if !string. (Seg-fault if str or end are NULL.)
+   */
+  bool getString(char const **begin, char const **end) const;
+#ifdef JSON_USE_CPPTL
+  CppTL::ConstString asConstString() const;
+#endif
+  Int asInt() const;
+  UInt asUInt() const;
+#if defined(JSON_HAS_INT64)
+  Int64 asInt64() const;
+  UInt64 asUInt64() const;
+#endif // if defined(JSON_HAS_INT64)
+  LargestInt asLargestInt() const;
+  LargestUInt asLargestUInt() const;
+  float asFloat() const;
+  double asDouble() const;
+  bool asBool() const;
+
+  bool isNull() const;
+  bool isBool() const;
+  bool isInt() const;
+  bool isInt64() const;
+  bool isUInt() const;
+  bool isUInt64() const;
+  bool isIntegral() const;
+  bool isDouble() const;
+  bool isNumeric() const;
+  bool isString() const;
+  bool isArray() const;
+  bool isObject() const;
+
+  bool isConvertibleTo(ValueType other) const;
+
+  /// Number of values in array or object
+  ArrayIndex size() const;
+
+  /// \brief Return true if empty array, empty object, or null;
+  /// otherwise, false.
+  bool empty() const;
+
+  /// Return isNull()
+  bool operator!() const;
+
+  /// Remove all object members and array elements.
+  /// \pre type() is arrayValue, objectValue, or nullValue
+  /// \post type() is unchanged
+  void clear();
+
+  /// Resize the array to size elements.
+  /// New elements are initialized to null.
+  /// May only be called on nullValue or arrayValue.
+  /// \pre type() is arrayValue or nullValue
+  /// \post type() is arrayValue
+  void resize(ArrayIndex size);
+
+  /// Access an array element (zero based index ).
+  /// If the array contains less than index element, then null value are
+  /// inserted
+  /// in the array so that its size is index+1.
+  /// (You may need to say 'value[0u]' to get your compiler to distinguish
+  ///  this from the operator[] which takes a string.)
+  Value &operator[](ArrayIndex index);
+
+  /// Access an array element (zero based index ).
+  /// If the array contains less than index element, then null value are
+  /// inserted
+  /// in the array so that its size is index+1.
+  /// (You may need to say 'value[0u]' to get your compiler to distinguish
+  ///  this from the operator[] which takes a string.)
+  Value &operator[](int index);
+
+  /// Access an array element (zero based index )
+  /// (You may need to say 'value[0u]' to get your compiler to distinguish
+  ///  this from the operator[] which takes a string.)
+  const Value &operator[](ArrayIndex index) const;
+
+  /// Access an array element (zero based index )
+  /// (You may need to say 'value[0u]' to get your compiler to distinguish
+  ///  this from the operator[] which takes a string.)
+  const Value &operator[](int index) const;
+
+  /// If the array contains at least index+1 elements, returns the element
+  /// value,
+  /// otherwise returns defaultValue.
+  Value get(ArrayIndex index, const Value &defaultValue) const;
+  /// Return true if index < size().
+  bool isValidIndex(ArrayIndex index) const;
+  /// \brief Append value to array at the end.
+  ///
+  /// Equivalent to jsonvalue[jsonvalue.size()] = value;
+  Value &append(const Value &value);
+
+  /// Access an object value by name, create a null member if it does not exist.
+  /// \note Because of our implementation, keys are limited to 2^30 -1 chars.
+  ///  Exceeding that will cause an exception.
+  Value &operator[](const char *key);
+  /// Access an object value by name, returns null if there is no member with
+  /// that name.
+  const Value &operator[](const char *key) const;
+  /// Access an object value by name, create a null member if it does not exist.
+  /// \param key may contain embedded nulls.
+  Value &operator[](const JSONCPP_STRING &key);
+  /// Access an object value by name, returns null if there is no member with
+  /// that name.
+  /// \param key may contain embedded nulls.
+  const Value &operator[](const JSONCPP_STRING &key) const;
+  /** \brief Access an object value by name, create a null member if it does not
+   exist.
+
+   * If the object has no entry for that name, then the member name used to store
+   * the new entry is not duplicated.
+   * Example of use:
+   * \code
+   * Json::Value object;
+   * static const StaticString code("code");
+   * object[code] = 1234;
+   * \endcode
+   */
+  Value &operator[](const StaticString &key);
+#ifdef JSON_USE_CPPTL
+  /// Access an object value by name, create a null member if it does not exist.
+  Value &operator[](const CppTL::ConstString &key);
+  /// Access an object value by name, returns null if there is no member with
+  /// that name.
+  const Value &operator[](const CppTL::ConstString &key) const;
+#endif
+  /// Return the member named key if it exist, defaultValue otherwise.
+  /// \note deep copy
+  Value get(const char *key, const Value &defaultValue) const;
+  /// Return the member named key if it exist, defaultValue otherwise.
+  /// \note deep copy
+  /// \note key may contain embedded nulls.
+  Value get(const char *begin, const char *end, const Value &defaultValue) const;
+  /// Return the member named key if it exist, defaultValue otherwise.
+  /// \note deep copy
+  /// \param key may contain embedded nulls.
+  Value get(const JSONCPP_STRING &key, const Value &defaultValue) const;
+#ifdef JSON_USE_CPPTL
+  /// Return the member named key if it exist, defaultValue otherwise.
+  /// \note deep copy
+  Value get(const CppTL::ConstString &key, const Value &defaultValue) const;
+#endif
+  /// Most general and efficient version of isMember()const, get()const,
+  /// and operator[]const
+  /// \note As stated elsewhere, behavior is undefined if (end-begin) >= 2^30
+  Value const *find(char const *begin, char const *end) const;
+  /// Most general and efficient version of object-mutators.
+  /// \note As stated elsewhere, behavior is undefined if (end-begin) >= 2^30
+  /// \return non-zero, but JSON_ASSERT if this is neither object nor nullValue.
+  Value const *demand(char const *begin, char const *end);
+  /// \brief Remove and return the named member.
+  ///
+  /// Do nothing if it did not exist.
+  /// \return the removed Value, or null.
+  /// \pre type() is objectValue or nullValue
+  /// \post type() is unchanged
+  /// \deprecated
+  Value removeMember(const char *key);
+  /// Same as removeMember(const char*)
+  /// \param key may contain embedded nulls.
+  /// \deprecated
+  Value removeMember(const JSONCPP_STRING &key);
+  /// Same as removeMember(const char* begin, const char* end, Value* removed),
+  /// but 'key' is null-terminated.
+  bool removeMember(const char *key, Value *removed);
+  /** \brief Remove the named map member.
+
+      Update 'removed' iff removed.
+      \param key may contain embedded nulls.
+      \return true iff removed (no exceptions)
+  */
+  bool removeMember(JSONCPP_STRING const &key, Value *removed);
+  /// Same as removeMember(JSONCPP_STRING const& key, Value* removed)
+  bool removeMember(const char *begin, const char *end, Value *removed);
+  /** \brief Remove the indexed array element.
+
+      O(n) expensive operations.
+      Update 'removed' iff removed.
+      \return true iff removed (no exceptions)
+  */
+  bool removeIndex(ArrayIndex i, Value *removed);
+
+  /// Return true if the object has a member named key.
+  /// \note 'key' must be null-terminated.
+  bool isMember(const char *key) const;
+  /// Return true if the object has a member named key.
+  /// \param key may contain embedded nulls.
+  bool isMember(const JSONCPP_STRING &key) const;
+  /// Same as isMember(JSONCPP_STRING const& key)const
+  bool isMember(const char *begin, const char *end) const;
+#ifdef JSON_USE_CPPTL
+  /// Return true if the object has a member named key.
+  bool isMember(const CppTL::ConstString &key) const;
+#endif
+
+  /// \brief Return a list of the member names.
+  ///
+  /// If null, return an empty list.
+  /// \pre type() is objectValue or nullValue
+  /// \post if type() was nullValue, it remains nullValue
+  Members getMemberNames() const;
+
+  //# ifdef JSON_USE_CPPTL
+  //      EnumMemberNames enumMemberNames() const;
+  //      EnumValues enumValues() const;
+  //# endif
+
+  /// \deprecated Always pass len.
+  JSONCPP_DEPRECATED("Use setComment(JSONCPP_STRING const&) instead.")
+  void setComment(const char *comment, CommentPlacement placement);
+  /// Comments must be //... or /* ... */
+  void setComment(const char *comment, size_t len, CommentPlacement placement);
+  /// Comments must be //... or /* ... */
+  void setComment(const JSONCPP_STRING &comment, CommentPlacement placement);
+  bool hasComment(CommentPlacement placement) const;
+  /// Include delimiters and embedded newlines.
+  JSONCPP_STRING getComment(CommentPlacement placement) const;
+
+  JSONCPP_STRING toStyledString() const;
+
+  const_iterator begin() const;
+  const_iterator end() const;
+
+  iterator begin();
+  iterator end();
+
+  // Accessors for the [start, limit) range of bytes within the JSON text from
+  // which this value was parsed, if any.
+  void setOffsetStart(ptrdiff_t start);
+  void setOffsetLimit(ptrdiff_t limit);
+  ptrdiff_t getOffsetStart() const;
+  ptrdiff_t getOffsetLimit() const;
+
+private:
+  void initBasic(ValueType type, bool allocated = false);
+
+  Value &resolveReference(const char *key);
+  Value &resolveReference(const char *key, const char *end);
+
+  struct CommentInfo
+  {
+    CommentInfo();
+    ~CommentInfo();
+
+    void setComment(const char *text, size_t len);
+
+    char *comment_;
+  };
+
+  // struct MemberNamesTransform
+  //{
+  //   typedef const char *result_type;
+  //   const char *operator()( const CZString &name ) const
+  //   {
+  //      return name.c_str();
+  //   }
+  //};
+
+  union ValueHolder {
+    LargestInt int_;
+    LargestUInt uint_;
+    double real_;
+    bool bool_;
+    char *string_; // actually ptr to unsigned, followed by str, unless !allocated_
+    ObjectValues *map_;
+  } value_;
+  ValueType type_ : 8;
+  unsigned int allocated_ : 1; // Notes: if declared as bool, bitfield is useless.
+                               // If not allocated_, string_ must be null-terminated.
+  CommentInfo *comments_;
+
+  // [start, limit) byte offsets in the source JSON text from which this Value
+  // was extracted.
+  ptrdiff_t start_;
+  ptrdiff_t limit_;
+};
+
+/** \brief Experimental and untested: represents an element of the "path" to
+ * access a node.
+ */
+class JSON_API PathArgument
+{
+public:
+  friend class Path;
+
+  PathArgument();
+  PathArgument(ArrayIndex index);
+  PathArgument(const char *key);
+  PathArgument(const JSONCPP_STRING &key);
+
+private:
+  enum Kind
+  {
+    kindNone = 0,
+    kindIndex,
+    kindKey
+  };
+  JSONCPP_STRING key_;
+  ArrayIndex index_;
+  Kind kind_;
+};
+
+/** \brief Experimental and untested: represents a "path" to access a node.
+ *
+ * Syntax:
+ * - "." => root node
+ * - ".[n]" => elements at index 'n' of root node (an array value)
+ * - ".name" => member named 'name' of root node (an object value)
+ * - ".name1.name2.name3"
+ * - ".[0][1][2].name1[3]"
+ * - ".%" => member name is provided as parameter
+ * - ".[%]" => index is provied as parameter
+ */
+class JSON_API Path
+{
+public:
+  Path(const JSONCPP_STRING &path, const PathArgument &a1 = PathArgument(),
+       const PathArgument &a2 = PathArgument(), const PathArgument &a3 = PathArgument(),
+       const PathArgument &a4 = PathArgument(), const PathArgument &a5 = PathArgument());
+
+  const Value &resolve(const Value &root) const;
+  Value resolve(const Value &root, const Value &defaultValue) const;
+  /// Creates the "path" to access the specified node and returns a reference on
+  /// the node.
+  Value &make(Value &root) const;
+
+private:
+  typedef std::vector<const PathArgument *> InArgs;
+  typedef std::vector<PathArgument> Args;
+
+  void makePath(const JSONCPP_STRING &path, const InArgs &in);
+  void addPathInArg(const JSONCPP_STRING &path, const InArgs &in, InArgs::const_iterator &itInArg,
+                    PathArgument::Kind kind);
+  void invalidPath(const JSONCPP_STRING &path, int location);
+
+  Args args_;
+};
+
+/** \brief base class for Value iterators.
+ *
+ */
+class JSON_API ValueIteratorBase
+{
+public:
+  typedef std::bidirectional_iterator_tag iterator_category;
+  typedef unsigned int size_t;
+  typedef int difference_type;
+  typedef ValueIteratorBase SelfType;
+
+  bool operator==(const SelfType &other) const { return isEqual(other); }
+
+  bool operator!=(const SelfType &other) const { return !isEqual(other); }
+
+  difference_type operator-(const SelfType &other) const { return other.computeDistance(*this); }
+
+  /// Return either the index or the member name of the referenced value as a
+  /// Value.
+  Value key() const;
+
+  /// Return the index of the referenced Value, or -1 if it is not an arrayValue.
+  UInt index() const;
+
+  /// Return the member name of the referenced Value, or "" if it is not an
+  /// objectValue.
+  /// \note Avoid `c_str()` on result, as embedded zeroes are possible.
+  JSONCPP_STRING name() const;
+
+  /// Return the member name of the referenced Value. "" if it is not an
+  /// objectValue.
+  /// \deprecated This cannot be used for UTF-8 strings, since there can be embedded nulls.
+  JSONCPP_DEPRECATED("Use `key = name();` instead.")
+  char const *memberName() const;
+  /// Return the member name of the referenced Value, or NULL if it is not an
+  /// objectValue.
+  /// \note Better version than memberName(). Allows embedded nulls.
+  char const *memberName(char const **end) const;
+
+protected:
+  Value &deref() const;
+
+  void increment();
+
+  void decrement();
+
+  difference_type computeDistance(const SelfType &other) const;
+
+  bool isEqual(const SelfType &other) const;
+
+  void copy(const SelfType &other);
+
+private:
+  Value::ObjectValues::iterator current_;
+  // Indicates that iterator is for a null value.
+  bool isNull_;
+
+public:
+  // For some reason, BORLAND needs these at the end, rather
+  // than earlier. No idea why.
+  ValueIteratorBase();
+  explicit ValueIteratorBase(const Value::ObjectValues::iterator &current);
+};
+
+/** \brief const iterator for object and array value.
+ *
+ */
+class JSON_API ValueConstIterator : public ValueIteratorBase
+{
+  friend class Value;
+
+public:
+  typedef const Value value_type;
+  // typedef unsigned int size_t;
+  // typedef int difference_type;
+  typedef const Value &reference;
+  typedef const Value *pointer;
+  typedef ValueConstIterator SelfType;
+
+  ValueConstIterator();
+  ValueConstIterator(ValueIterator const &other);
+
+private:
+  /*! \internal Use by Value to create an iterator.
+   */
+  explicit ValueConstIterator(const Value::ObjectValues::iterator &current);
+
+public:
+  SelfType &operator=(const ValueIteratorBase &other);
+
+  SelfType operator++(int)
+  {
+    SelfType temp(*this);
+    ++*this;
+    return temp;
+  }
+
+  SelfType operator--(int)
+  {
+    SelfType temp(*this);
+    --*this;
+    return temp;
+  }
+
+  SelfType &operator--()
+  {
+    decrement();
+    return *this;
+  }
+
+  SelfType &operator++()
+  {
+    increment();
+    return *this;
+  }
+
+  reference operator*() const { return deref(); }
+
+  pointer operator->() const { return &deref(); }
+};
+
+/** \brief Iterator for object and array value.
+ */
+class JSON_API ValueIterator : public ValueIteratorBase
+{
+  friend class Value;
+
+public:
+  typedef Value value_type;
+  typedef unsigned int size_t;
+  typedef int difference_type;
+  typedef Value &reference;
+  typedef Value *pointer;
+  typedef ValueIterator SelfType;
+
+  ValueIterator();
+  explicit ValueIterator(const ValueConstIterator &other);
+  ValueIterator(const ValueIterator &other);
+
+private:
+  /*! \internal Use by Value to create an iterator.
+   */
+  explicit ValueIterator(const Value::ObjectValues::iterator &current);
+
+public:
+  SelfType &operator=(const SelfType &other);
+
+  SelfType operator++(int)
+  {
+    SelfType temp(*this);
+    ++*this;
+    return temp;
+  }
+
+  SelfType operator--(int)
+  {
+    SelfType temp(*this);
+    --*this;
+    return temp;
+  }
+
+  SelfType &operator--()
+  {
+    decrement();
+    return *this;
+  }
+
+  SelfType &operator++()
+  {
+    increment();
+    return *this;
+  }
+
+  reference operator*() const { return deref(); }
+
+  pointer operator->() const { return &deref(); }
+};
+
+} // namespace Json
+
+namespace std
+{
+/// Specialize std::swap() for Json::Value.
+template <> inline void swap(Json::Value &a, Json::Value &b) { a.swap(b); }
+}
+
+#if defined(JSONCPP_DISABLE_DLL_INTERFACE_WARNING)
+#pragma warning(pop)
+#endif // if defined(JSONCPP_DISABLE_DLL_INTERFACE_WARNING)
+
+#endif // CPPTL_JSON_H_INCLUDED
+
+// //////////////////////////////////////////////////////////////////////
+// End of content of file: include/json/value.h
+// //////////////////////////////////////////////////////////////////////
+
+// //////////////////////////////////////////////////////////////////////
+// Beginning of content of file: include/json/reader.h
+// //////////////////////////////////////////////////////////////////////
+
+// Copyright 2007-2010 Baptiste Lepilleur
+// Distributed under MIT license, or public domain if desired and
+// recognized in your jurisdiction.
+// See file LICENSE for detail or copy at http://jsoncpp.sourceforge.net/LICENSE
+
+#ifndef CPPTL_JSON_READER_H_INCLUDED
+#define CPPTL_JSON_READER_H_INCLUDED
+
+#if !defined(JSON_IS_AMALGAMATION)
+#include "features.h"
+#include "value.h"
+#endif // if !defined(JSON_IS_AMALGAMATION)
+#include <deque>
+#include <iosfwd>
+#include <stack>
+#include <string>
+#include <istream>
+
+// Disable warning C4251: <data member>: <type> needs to have dll-interface to
+// be used by...
+#if defined(JSONCPP_DISABLE_DLL_INTERFACE_WARNING)
+#pragma warning(push)
+#pragma warning(disable : 4251)
+#endif // if defined(JSONCPP_DISABLE_DLL_INTERFACE_WARNING)
+
+namespace Json
+{
+
+/** \brief Unserialize a <a HREF="http://www.json.org">JSON</a> document into a
+ *Value.
+ *
+ * \deprecated Use CharReader and CharReaderBuilder.
+ */
+class JSON_API Reader
+{
+public:
+  typedef char Char;
+  typedef const Char *Location;
+
+  /** \brief An error tagged with where in the JSON text it was encountered.
+   *
+   * The offsets give the [start, limit) range of bytes within the text. Note
+   * that this is bytes, not codepoints.
+   *
+   */
+  struct StructuredError
+  {
+    ptrdiff_t offset_start;
+    ptrdiff_t offset_limit;
+    JSONCPP_STRING message;
+  };
+
+  /** \brief Constructs a Reader allowing all features
+   * for parsing.
+   */
+  Reader();
+
+  /** \brief Constructs a Reader allowing the specified feature set
+   * for parsing.
+   */
+  Reader(const Features &features);
+
+  /** \brief Read a Value from a <a HREF="http://www.json.org">JSON</a>
+   * document.
+   * \param document UTF-8 encoded string containing the document to read.
+   * \param root [out] Contains the root value of the document if it was
+   *             successfully parsed.
+   * \param collectComments \c true to collect comment and allow writing them
+   * back during
+   *                        serialization, \c false to discard comments.
+   *                        This parameter is ignored if
+   * Features::allowComments_
+   *                        is \c false.
+   * \return \c true if the document was successfully parsed, \c false if an
+   * error occurred.
+   */
+  bool parse(const std::string &document, Value &root, bool collectComments = true);
+
+  /** \brief Read a Value from a <a HREF="http://www.json.org">JSON</a>
+   document.
+   * \param beginDoc Pointer on the beginning of the UTF-8 encoded string of the
+   document to read.
+   * \param endDoc Pointer on the end of the UTF-8 encoded string of the
+   document to read.
+   *               Must be >= beginDoc.
+   * \param root [out] Contains the root value of the document if it was
+   *             successfully parsed.
+   * \param collectComments \c true to collect comment and allow writing them
+   back during
+   *                        serialization, \c false to discard comments.
+   *                        This parameter is ignored if
+   Features::allowComments_
+   *                        is \c false.
+   * \return \c true if the document was successfully parsed, \c false if an
+   error occurred.
+   */
+  bool parse(const char *beginDoc, const char *endDoc, Value &root, bool collectComments = true);
+
+  /// \brief Parse from input stream.
+  /// \see Json::operator>>(std::istream&, Json::Value&).
+  bool parse(JSONCPP_ISTREAM &is, Value &root, bool collectComments = true);
+
+  /** \brief Returns a user friendly string that list errors in the parsed
+   * document.
+   * \return Formatted error message with the list of errors with their location
+   * in
+   *         the parsed document. An empty string is returned if no error
+   * occurred
+   *         during parsing.
+   * \deprecated Use getFormattedErrorMessages() instead (typo fix).
+   */
+  JSONCPP_DEPRECATED("Use getFormattedErrorMessages() instead.")
+  JSONCPP_STRING getFormatedErrorMessages() const;
+
+  /** \brief Returns a user friendly string that list errors in the parsed
+   * document.
+   * \return Formatted error message with the list of errors with their location
+   * in
+   *         the parsed document. An empty string is returned if no error
+   * occurred
+   *         during parsing.
+   */
+  JSONCPP_STRING getFormattedErrorMessages() const;
+
+  /** \brief Returns a vector of structured erros encounted while parsing.
+   * \return A (possibly empty) vector of StructuredError objects. Currently
+   *         only one error can be returned, but the caller should tolerate
+   * multiple
+   *         errors.  This can occur if the parser recovers from a non-fatal
+   *         parse error and then encounters additional errors.
+   */
+  std::vector<StructuredError> getStructuredErrors() const;
+
+  /** \brief Add a semantic error message.
+   * \param value JSON Value location associated with the error
+   * \param message The error message.
+   * \return \c true if the error was successfully added, \c false if the
+   * Value offset exceeds the document size.
+   */
+  bool pushError(const Value &value, const JSONCPP_STRING &message);
+
+  /** \brief Add a semantic error message with extra context.
+   * \param value JSON Value location associated with the error
+   * \param message The error message.
+   * \param extra Additional JSON Value location to contextualize the error
+   * \return \c true if the error was successfully added, \c false if either
+   * Value offset exceeds the document size.
+   */
+  bool pushError(const Value &value, const JSONCPP_STRING &message, const Value &extra);
+
+  /** \brief Return whether there are any errors.
+   * \return \c true if there are no errors to report \c false if
+   * errors have occurred.
+   */
+  bool good() const;
+
+private:
+  enum TokenType
+  {
+    tokenEndOfStream = 0,
+    tokenObjectBegin,
+    tokenObjectEnd,
+    tokenArrayBegin,
+    tokenArrayEnd,
+    tokenString,
+    tokenNumber,
+    tokenTrue,
+    tokenFalse,
+    tokenNull,
+    tokenArraySeparator,
+    tokenMemberSeparator,
+    tokenComment,
+    tokenError
+  };
+
+  class Token
+  {
+  public:
+    TokenType type_;
+    Location start_;
+    Location end_;
+  };
+
+  class ErrorInfo
+  {
+  public:
+    Token token_;
+    JSONCPP_STRING message_;
+    Location extra_;
+  };
+
+  typedef std::deque<ErrorInfo> Errors;
+
+  bool readToken(Token &token);
+  void skipSpaces();
+  bool match(Location pattern, int patternLength);
+  bool readComment();
+  bool readCStyleComment();
+  bool readCppStyleComment();
+  bool readString();
+  void readNumber();
+  bool readValue();
+  bool readObject(Token &token);
+  bool readArray(Token &token);
+  bool decodeNumber(Token &token);
+  bool decodeNumber(Token &token, Value &decoded);
+  bool decodeString(Token &token);
+  bool decodeString(Token &token, JSONCPP_STRING &decoded);
+  bool decodeDouble(Token &token);
+  bool decodeDouble(Token &token, Value &decoded);
+  bool decodeUnicodeCodePoint(Token &token, Location &current, Location end, unsigned int &unicode);
+  bool decodeUnicodeEscapeSequence(Token &token, Location &current, Location end,
+                                   unsigned int &unicode);
+  bool addError(const JSONCPP_STRING &message, Token &token, Location extra = 0);
+  bool recoverFromError(TokenType skipUntilToken);
+  bool addErrorAndRecover(const JSONCPP_STRING &message, Token &token, TokenType skipUntilToken);
+  void skipUntilSpace();
+  Value &currentValue();
+  Char getNextChar();
+  void getLocationLineAndColumn(Location location, int &line, int &column) const;
+  JSONCPP_STRING getLocationLineAndColumn(Location location) const;
+  void addComment(Location begin, Location end, CommentPlacement placement);
+  void skipCommentTokens(Token &token);
+
+  typedef std::stack<Value *> Nodes;
+  Nodes nodes_;
+  Errors errors_;
+  JSONCPP_STRING document_;
+  Location begin_;
+  Location end_;
+  Location current_;
+  Location lastValueEnd_;
+  Value *lastValue_;
+  JSONCPP_STRING commentsBefore_;
+  Features features_;
+  bool collectComments_;
+}; // Reader
+
+/** Interface for reading JSON from a char array.
+ */
+class JSON_API CharReader
+{
+public:
+  virtual ~CharReader() {}
+  /** \brief Read a Value from a <a HREF="http://www.json.org">JSON</a>
+   document.
+   * The document must be a UTF-8 encoded string containing the document to read.
+   *
+   * \param beginDoc Pointer on the beginning of the UTF-8 encoded string of the
+   document to read.
+   * \param endDoc Pointer on the end of the UTF-8 encoded string of the
+   document to read.
+   *        Must be >= beginDoc.
+   * \param root [out] Contains the root value of the document if it was
+   *             successfully parsed.
+   * \param errs [out] Formatted error messages (if not NULL)
+   *        a user friendly string that lists errors in the parsed
+   * document.
+   * \return \c true if the document was successfully parsed, \c false if an
+   error occurred.
+   */
+  virtual bool parse(char const *beginDoc, char const *endDoc, Value *root,
+                     JSONCPP_STRING *errs) = 0;
+
+  class JSON_API Factory
+  {
+  public:
+    virtual ~Factory() {}
+    /** \brief Allocate a CharReader via operator new().
+     * \throw std::exception if something goes wrong (e.g. invalid settings)
+     */
+    virtual CharReader *newCharReader() const = 0;
+  }; // Factory
+};   // CharReader
+
+/** \brief Build a CharReader implementation.
+
+Usage:
+\code
+  using namespace Json;
+  CharReaderBuilder builder;
+  builder["collectComments"] = false;
+  Value value;
+  JSONCPP_STRING errs;
+  bool ok = parseFromStream(builder, std::cin, &value, &errs);
+\endcode
+*/
+class JSON_API CharReaderBuilder : public CharReader::Factory
+{
+public:
+  // Note: We use a Json::Value so that we can add data-members to this class
+  // without a major version bump.
+  /** Configuration of this builder.
+    These are case-sensitive.
+    Available settings (case-sensitive):
+    - `"collectComments": false or true`
+      - true to collect comment and allow writing them
+        back during serialization, false to discard comments.
+        This parameter is ignored if allowComments is false.
+    - `"allowComments": false or true`
+      - true if comments are allowed.
+    - `"strictRoot": false or true`
+      - true if root must be either an array or an object value
+    - `"allowDroppedNullPlaceholders": false or true`
+      - true if dropped null placeholders are allowed. (See StreamWriterBuilder.)
+    - `"allowNumericKeys": false or true`
+      - true if numeric object keys are allowed.
+    - `"allowSingleQuotes": false or true`
+      - true if '' are allowed for strings (both keys and values)
+    - `"stackLimit": integer`
+      - Exceeding stackLimit (recursive depth of `readValue()`) will
+        cause an exception.
+      - This is a security issue (seg-faults caused by deeply nested JSON),
+        so the default is low.
+    - `"failIfExtra": false or true`
+      - If true, `parse()` returns false when extra non-whitespace trails
+        the JSON value in the input string.
+    - `"rejectDupKeys": false or true`
+      - If true, `parse()` returns false when a key is duplicated within an object.
+    - `"allowSpecialFloats": false or true`
+      - If true, special float values (NaNs and infinities) are allowed
+        and their values are lossfree restorable.
+
+    You can examine 'settings_` yourself
+    to see the defaults. You can also write and read them just like any
+    JSON Value.
+    \sa setDefaults()
+    */
+  Json::Value settings_;
+
+  CharReaderBuilder();
+  ~CharReaderBuilder() JSONCPP_OVERRIDE;
+
+  CharReader *newCharReader() const JSONCPP_OVERRIDE;
+
+  /** \return true if 'settings' are legal and consistent;
+   *   otherwise, indicate bad settings via 'invalid'.
+   */
+  bool validate(Json::Value *invalid) const;
+
+  /** A simple way to update a specific setting.
+   */
+  Value &operator[](JSONCPP_STRING key);
+
+  /** Called by ctor, but you can use this to reset settings_.
+   * \pre 'settings' != NULL (but Json::null is fine)
+   * \remark Defaults:
+   * \snippet src/lib_json/json_reader.cpp CharReaderBuilderDefaults
+   */
+  static void setDefaults(Json::Value *settings);
+  /** Same as old Features::strictMode().
+   * \pre 'settings' != NULL (but Json::null is fine)
+   * \remark Defaults:
+   * \snippet src/lib_json/json_reader.cpp CharReaderBuilderStrictMode
+   */
+  static void strictMode(Json::Value *settings);
+};
+
+/** Consume entire stream and use its begin/end.
+  * Someday we might have a real StreamReader, but for now this
+  * is convenient.
+  */
+bool JSON_API parseFromStream(CharReader::Factory const &, JSONCPP_ISTREAM &, Value *root,
+                              std::string *errs);
+
+/** \brief Read from 'sin' into 'root'.
+
+ Always keep comments from the input JSON.
+
+ This can be used to read a file into a particular sub-object.
+ For example:
+ \code
+ Json::Value root;
+ cin >> root["dir"]["file"];
+ cout << root;
+ \endcode
+ Result:
+ \verbatim
+ {
+ "dir": {
+     "file": {
+     // The input stream JSON would be nested here.
+     }
+ }
+ }
+ \endverbatim
+ \throw std::exception on parse error.
+ \see Json::operator<<()
+*/
+JSON_API JSONCPP_ISTREAM &operator>>(JSONCPP_ISTREAM &, Value &);
+
+} // namespace Json
+
+#if defined(JSONCPP_DISABLE_DLL_INTERFACE_WARNING)
+#pragma warning(pop)
+#endif // if defined(JSONCPP_DISABLE_DLL_INTERFACE_WARNING)
+
+#endif // CPPTL_JSON_READER_H_INCLUDED
+
+// //////////////////////////////////////////////////////////////////////
+// End of content of file: include/json/reader.h
+// //////////////////////////////////////////////////////////////////////
+
+// //////////////////////////////////////////////////////////////////////
+// Beginning of content of file: include/json/writer.h
+// //////////////////////////////////////////////////////////////////////
+
+// Copyright 2007-2010 Baptiste Lepilleur
+// Distributed under MIT license, or public domain if desired and
+// recognized in your jurisdiction.
+// See file LICENSE for detail or copy at http://jsoncpp.sourceforge.net/LICENSE
+
+#ifndef JSON_WRITER_H_INCLUDED
+#define JSON_WRITER_H_INCLUDED
+
+#if !defined(JSON_IS_AMALGAMATION)
+#include "value.h"
+#endif // if !defined(JSON_IS_AMALGAMATION)
+#include <vector>
+#include <string>
+#include <ostream>
+
+// Disable warning C4251: <data member>: <type> needs to have dll-interface to
+// be used by...
+#if defined(JSONCPP_DISABLE_DLL_INTERFACE_WARNING)
+#pragma warning(push)
+#pragma warning(disable : 4251)
+#endif // if defined(JSONCPP_DISABLE_DLL_INTERFACE_WARNING)
+
+namespace Json
+{
+
+class Value;
+
+/**
+
+Usage:
+\code
+  using namespace Json;
+  void writeToStdout(StreamWriter::Factory const& factory, Value const& value) {
+    std::unique_ptr<StreamWriter> const writer(
+      factory.newStreamWriter());
+    writer->write(value, &std::cout);
+    std::cout << std::endl;  // add lf and flush
+  }
+\endcode
+*/
+class JSON_API StreamWriter
+{
+protected:
+  JSONCPP_OSTREAM *sout_; // not owned; will not delete
+public:
+  StreamWriter();
+  virtual ~StreamWriter();
+  /** Write Value into document as configured in sub-class.
+      Do not take ownership of sout, but maintain a reference during function.
+      \pre sout != NULL
+      \return zero on success (For now, we always return zero, so check the stream instead.)
+      \throw std::exception possibly, depending on configuration
+   */
+  virtual int write(Value const &root, JSONCPP_OSTREAM *sout) = 0;
+
+  /** \brief A simple abstract factory.
+   */
+  class JSON_API Factory
+  {
+  public:
+    virtual ~Factory();
+    /** \brief Allocate a CharReader via operator new().
+     * \throw std::exception if something goes wrong (e.g. invalid settings)
+     */
+    virtual StreamWriter *newStreamWriter() const = 0;
+  }; // Factory
+};   // StreamWriter
+
+/** \brief Write into stringstream, then return string, for convenience.
+ * A StreamWriter will be created from the factory, used, and then deleted.
+ */
+JSONCPP_STRING JSON_API writeString(StreamWriter::Factory const &factory, Value const &root);
+
+/** \brief Build a StreamWriter implementation.
+
+Usage:
+\code
+  using namespace Json;
+  Value value = ...;
+  StreamWriterBuilder builder;
+  builder["commentStyle"] = "None";
+  builder["indentation"] = "   ";  // or whatever you like
+  std::unique_ptr<Json::StreamWriter> writer(
+      builder.newStreamWriter());
+  writer->write(value, &std::cout);
+  std::cout << std::endl;  // add lf and flush
+\endcode
+*/
+class JSON_API StreamWriterBuilder : public StreamWriter::Factory
+{
+public:
+  // Note: We use a Json::Value so that we can add data-members to this class
+  // without a major version bump.
+  /** Configuration of this builder.
+    Available settings (case-sensitive):
+    - "commentStyle": "None" or "All"
+    - "indentation":  "<anything>"
+    - "enableYAMLCompatibility": false or true
+      - slightly change the whitespace around colons
+    - "dropNullPlaceholders": false or true
+      - Drop the "null" string from the writer's output for nullValues.
+        Strictly speaking, this is not valid JSON. But when the output is being
+        fed to a browser's Javascript, it makes for smaller output and the
+        browser can handle the output just fine.
+    - "useSpecialFloats": false or true
+      - If true, outputs non-finite floating point values in the following way:
+        NaN values as "NaN", positive infinity as "Infinity", and negative infinity
+        as "-Infinity".
+
+    You can examine 'settings_` yourself
+    to see the defaults. You can also write and read them just like any
+    JSON Value.
+    \sa setDefaults()
+    */
+  Json::Value settings_;
+
+  StreamWriterBuilder();
+  ~StreamWriterBuilder() JSONCPP_OVERRIDE;
+
+  /**
+   * \throw std::exception if something goes wrong (e.g. invalid settings)
+   */
+  StreamWriter *newStreamWriter() const JSONCPP_OVERRIDE;
+
+  /** \return true if 'settings' are legal and consistent;
+   *   otherwise, indicate bad settings via 'invalid'.
+   */
+  bool validate(Json::Value *invalid) const;
+  /** A simple way to update a specific setting.
+   */
+  Value &operator[](JSONCPP_STRING key);
+
+  /** Called by ctor, but you can use this to reset settings_.
+   * \pre 'settings' != NULL (but Json::null is fine)
+   * \remark Defaults:
+   * \snippet src/lib_json/json_writer.cpp StreamWriterBuilderDefaults
+   */
+  static void setDefaults(Json::Value *settings);
+};
+
+/** \brief Abstract class for writers.
+ * \deprecated Use StreamWriter. (And really, this is an implementation detail.)
+ */
+class JSON_API Writer
+{
+public:
+  virtual ~Writer();
+
+  virtual JSONCPP_STRING write(const Value &root) = 0;
+};
+
+/** \brief Outputs a Value in <a HREF="http://www.json.org">JSON</a> format
+ *without formatting (not human friendly).
+ *
+ * The JSON document is written in a single line. It is not intended for 'human'
+ *consumption,
+ * but may be usefull to support feature such as RPC where bandwith is limited.
+ * \sa Reader, Value
+ * \deprecated Use StreamWriterBuilder.
+ */
+class JSON_API FastWriter : public Writer
+{
+
+public:
+  FastWriter();
+  ~FastWriter() JSONCPP_OVERRIDE {}
+
+  void enableYAMLCompatibility();
+
+  /** \brief Drop the "null" string from the writer's output for nullValues.
+   * Strictly speaking, this is not valid JSON. But when the output is being
+   * fed to a browser's Javascript, it makes for smaller output and the
+   * browser can handle the output just fine.
+   */
+  void dropNullPlaceholders();
+
+  void omitEndingLineFeed();
+
+public: // overridden from Writer
+  JSONCPP_STRING write(const Value &root) JSONCPP_OVERRIDE;
+
+private:
+  void writeValue(const Value &value);
+
+  JSONCPP_STRING document_;
+  bool yamlCompatiblityEnabled_;
+  bool dropNullPlaceholders_;
+  bool omitEndingLineFeed_;
+};
+
+/** \brief Writes a Value in <a HREF="http://www.json.org">JSON</a> format in a
+ *human friendly way.
+ *
+ * The rules for line break and indent are as follow:
+ * - Object value:
+ *     - if empty then print {} without indent and line break
+ *     - if not empty the print '{', line break & indent, print one value per
+ *line
+ *       and then unindent and line break and print '}'.
+ * - Array value:
+ *     - if empty then print [] without indent and line break
+ *     - if the array contains no object value, empty array or some other value
+ *types,
+ *       and all the values fit on one lines, then print the array on a single
+ *line.
+ *     - otherwise, it the values do not fit on one line, or the array contains
+ *       object or non empty array, then print one value per line.
+ *
+ * If the Value have comments then they are outputed according to their
+ *#CommentPlacement.
+ *
+ * \sa Reader, Value, Value::setComment()
+ * \deprecated Use StreamWriterBuilder.
+ */
+class JSON_API StyledWriter : public Writer
+{
+public:
+  StyledWriter();
+  ~StyledWriter() JSONCPP_OVERRIDE {}
+
+public: // overridden from Writer
+  /** \brief Serialize a Value in <a HREF="http://www.json.org">JSON</a> format.
+   * \param root Value to serialize.
+   * \return String containing the JSON document that represents the root value.
+   */
+  JSONCPP_STRING write(const Value &root) JSONCPP_OVERRIDE;
+
+private:
+  void writeValue(const Value &value);
+  void writeArrayValue(const Value &value);
+  bool isMultineArray(const Value &value);
+  void pushValue(const JSONCPP_STRING &value);
+  void writeIndent();
+  void writeWithIndent(const JSONCPP_STRING &value);
+  void indent();
+  void unindent();
+  void writeCommentBeforeValue(const Value &root);
+  void writeCommentAfterValueOnSameLine(const Value &root);
+  bool hasCommentForValue(const Value &value);
+  static JSONCPP_STRING normalizeEOL(const JSONCPP_STRING &text);
+
+  typedef std::vector<JSONCPP_STRING> ChildValues;
+
+  ChildValues childValues_;
+  JSONCPP_STRING document_;
+  JSONCPP_STRING indentString_;
+  unsigned int rightMargin_;
+  unsigned int indentSize_;
+  bool addChildValues_;
+};
+
+/** \brief Writes a Value in <a HREF="http://www.json.org">JSON</a> format in a
+ human friendly way,
+     to a stream rather than to a string.
+ *
+ * The rules for line break and indent are as follow:
+ * - Object value:
+ *     - if empty then print {} without indent and line break
+ *     - if not empty the print '{', line break & indent, print one value per
+ line
+ *       and then unindent and line break and print '}'.
+ * - Array value:
+ *     - if empty then print [] without indent and line break
+ *     - if the array contains no object value, empty array or some other value
+ types,
+ *       and all the values fit on one lines, then print the array on a single
+ line.
+ *     - otherwise, it the values do not fit on one line, or the array contains
+ *       object or non empty array, then print one value per line.
+ *
+ * If the Value have comments then they are outputed according to their
+ #CommentPlacement.
+ *
+ * \param indentation Each level will be indented by this amount extra.
+ * \sa Reader, Value, Value::setComment()
+ * \deprecated Use StreamWriterBuilder.
+ */
+class JSON_API StyledStreamWriter
+{
+public:
+  StyledStreamWriter(JSONCPP_STRING indentation = "\t");
+  ~StyledStreamWriter() {}
+
+public:
+  /** \brief Serialize a Value in <a HREF="http://www.json.org">JSON</a> format.
+   * \param out Stream to write to. (Can be ostringstream, e.g.)
+   * \param root Value to serialize.
+   * \note There is no point in deriving from Writer, since write() should not
+   * return a value.
+   */
+  void write(JSONCPP_OSTREAM &out, const Value &root);
+
+private:
+  void writeValue(const Value &value);
+  void writeArrayValue(const Value &value);
+  bool isMultineArray(const Value &value);
+  void pushValue(const JSONCPP_STRING &value);
+  void writeIndent();
+  void writeWithIndent(const JSONCPP_STRING &value);
+  void indent();
+  void unindent();
+  void writeCommentBeforeValue(const Value &root);
+  void writeCommentAfterValueOnSameLine(const Value &root);
+  bool hasCommentForValue(const Value &value);
+  static JSONCPP_STRING normalizeEOL(const JSONCPP_STRING &text);
+
+  typedef std::vector<JSONCPP_STRING> ChildValues;
+
+  ChildValues childValues_;
+  JSONCPP_OSTREAM *document_;
+  JSONCPP_STRING indentString_;
+  unsigned int rightMargin_;
+  JSONCPP_STRING indentation_;
+  bool addChildValues_ : 1;
+  bool indented_ : 1;
+};
+
+#if defined(JSON_HAS_INT64)
+JSONCPP_STRING JSON_API valueToString(Int value);
+JSONCPP_STRING JSON_API valueToString(UInt value);
+#endif // if defined(JSON_HAS_INT64)
+JSONCPP_STRING JSON_API valueToString(LargestInt value);
+JSONCPP_STRING JSON_API valueToString(LargestUInt value);
+JSONCPP_STRING JSON_API valueToString(double value);
+JSONCPP_STRING JSON_API valueToString(bool value);
+JSONCPP_STRING JSON_API valueToQuotedString(const char *value);
+
+/// \brief Output using the StyledStreamWriter.
+/// \see Json::operator>>()
+JSON_API JSONCPP_OSTREAM &operator<<(JSONCPP_OSTREAM &, const Value &root);
+
+} // namespace Json
+
+#if defined(JSONCPP_DISABLE_DLL_INTERFACE_WARNING)
+#pragma warning(pop)
+#endif // if defined(JSONCPP_DISABLE_DLL_INTERFACE_WARNING)
+
+#endif // JSON_WRITER_H_INCLUDED
+
+// //////////////////////////////////////////////////////////////////////
+// End of content of file: include/json/writer.h
+// //////////////////////////////////////////////////////////////////////
+
+// //////////////////////////////////////////////////////////////////////
+// Beginning of content of file: include/json/assertions.h
+// //////////////////////////////////////////////////////////////////////
+
+// Copyright 2007-2010 Baptiste Lepilleur
+// Distributed under MIT license, or public domain if desired and
+// recognized in your jurisdiction.
+// See file LICENSE for detail or copy at http://jsoncpp.sourceforge.net/LICENSE
+
+#ifndef CPPTL_JSON_ASSERTIONS_H_INCLUDED
+#define CPPTL_JSON_ASSERTIONS_H_INCLUDED
+
+#include <stdlib.h>
+#include <sstream>
+
+#if !defined(JSON_IS_AMALGAMATION)
+#include "config.h"
+#endif // if !defined(JSON_IS_AMALGAMATION)
+
+/** It should not be possible for a maliciously designed file to
+ *  cause an abort() or seg-fault, so these macros are used only
+ *  for pre-condition violations and internal logic errors.
+ */
+#if JSON_USE_EXCEPTION
+
+// @todo <= add detail about condition in exception
+#define JSON_ASSERT(condition)                     \
+  {                                                \
+    if (!(condition))                              \
+    {                                              \
+      Json::throwLogicError("assert json failed"); \
+    }                                              \
+  }
+
+#define JSON_FAIL_MESSAGE(message)    \
+  {                                   \
+    JSONCPP_OSTRINGSTREAM oss;        \
+    oss << message;                   \
+    Json::throwLogicError(oss.str()); \
+    abort();                          \
+  }
+
+#else // JSON_USE_EXCEPTION
+
+#define JSON_ASSERT(condition) assert(condition)
+
+// The call to assert() will show the failure message in debug builds. In
+// release builds we abort, for a core-dump or debugger.
+#define JSON_FAIL_MESSAGE(message)      \
+  {                                     \
+    JSONCPP_OSTRINGSTREAM oss;          \
+    oss << message;                     \
+    assert(false && oss.str().c_str()); \
+    abort();                            \
+  }
+
+#endif
+
+#define JSON_ASSERT_MESSAGE(condition, message) \
+  if (!(condition))                             \
+  {                                             \
+    JSON_FAIL_MESSAGE(message);                 \
+  }
+
+#endif // CPPTL_JSON_ASSERTIONS_H_INCLUDED
+
+// //////////////////////////////////////////////////////////////////////
+// End of content of file: include/json/assertions.h
+// //////////////////////////////////////////////////////////////////////
+
+#endif // ifndef JSON_AMALGATED_H_INCLUDED
diff --git a/runtime/libs/jsoncpp/jsoncpp.cpp b/runtime/libs/jsoncpp/jsoncpp.cpp
new file mode 100644
index 000000000..5b3cd691d
--- /dev/null
+++ b/runtime/libs/jsoncpp/jsoncpp.cpp
@@ -0,0 +1,5651 @@
+/// Json-cpp amalgated source (http://jsoncpp.sourceforge.net/).
+/// It is intended to be used with #include "json/json.h"
+
+// //////////////////////////////////////////////////////////////////////
+// Beginning of content of file: LICENSE
+// //////////////////////////////////////////////////////////////////////
+
+/*
+The JsonCpp library's source code, including accompanying documentation,
+tests and demonstration applications, are licensed under the following
+conditions...
+
+The author (Baptiste Lepilleur) explicitly disclaims copyright in all
+jurisdictions which recognize such a disclaimer. In such jurisdictions,
+this software is released into the Public Domain.
+
+In jurisdictions which do not recognize Public Domain property (e.g. Germany as of
+2010), this software is Copyright (c) 2007-2010 by Baptiste Lepilleur, and is
+released under the terms of the MIT License (see below).
+
+In jurisdictions which recognize Public Domain property, the user of this
+software may choose to accept it either as 1) Public Domain, 2) under the
+conditions of the MIT License (see below), or 3) under the terms of dual
+Public Domain/MIT License conditions described here, as they choose.
+
+The MIT License is about as close to Public Domain as a license can get, and is
+described in clear, concise terms at:
+
+   http://en.wikipedia.org/wiki/MIT_License
+
+The full text of the MIT License follows:
+
+========================================================================
+Copyright (c) 2007-2010 Baptiste Lepilleur
+
+Permission is hereby granted, free of charge, to any person
+obtaining a copy of this software and associated documentation
+files (the "Software"), to deal in the Software without
+restriction, including without limitation the rights to use, copy,
+modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be
+included in all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+========================================================================
+(END LICENSE TEXT)
+
+The MIT license is compatible with both the GPL and commercial
+software, affording one all of the rights of Public Domain with the
+minor nuisance of being required to keep the above copyright notice
+and license text in the source code. Note also that by accepting the
+Public Domain "license" you can re-license your copy using whatever
+license you like.
+
+*/
+
+// //////////////////////////////////////////////////////////////////////
+// End of content of file: LICENSE
+// //////////////////////////////////////////////////////////////////////
+
+#include "json/json.h"
+
+#ifndef JSON_IS_AMALGAMATION
+#error "Compile with -I PATH_TO_JSON_DIRECTORY"
+#endif
+
+// //////////////////////////////////////////////////////////////////////
+// Beginning of content of file: src/lib_json/json_tool.h
+// //////////////////////////////////////////////////////////////////////
+
+// Copyright 2007-2010 Baptiste Lepilleur
+// Distributed under MIT license, or public domain if desired and
+// recognized in your jurisdiction.
+// See file LICENSE for detail or copy at http://jsoncpp.sourceforge.net/LICENSE
+
+#ifndef LIB_JSONCPP_JSON_TOOL_H_INCLUDED
+#define LIB_JSONCPP_JSON_TOOL_H_INCLUDED
+
+#ifndef NO_LOCALE_SUPPORT
+#include <clocale>
+#endif
+
+/* This header provides common string manipulation support, such as UTF-8,
+ * portable conversion from/to string...
+ *
+ * It is an internal header that must not be exposed.
+ */
+
+namespace Json
+{
+static char getDecimalPoint()
+{
+#ifdef NO_LOCALE_SUPPORT
+  return '\0';
+#else
+  struct lconv *lc = localeconv();
+  return lc ? *(lc->decimal_point) : '\0';
+#endif
+}
+
+/// Converts a unicode code-point to UTF-8.
+static inline JSONCPP_STRING codePointToUTF8(unsigned int cp)
+{
+  JSONCPP_STRING result;
+
+  // based on description from http://en.wikipedia.org/wiki/UTF-8
+
+  if (cp <= 0x7f)
+  {
+    result.resize(1);
+    result[0] = static_cast<char>(cp);
+  }
+  else if (cp <= 0x7FF)
+  {
+    result.resize(2);
+    result[1] = static_cast<char>(0x80 | (0x3f & cp));
+    result[0] = static_cast<char>(0xC0 | (0x1f & (cp >> 6)));
+  }
+  else if (cp <= 0xFFFF)
+  {
+    result.resize(3);
+    result[2] = static_cast<char>(0x80 | (0x3f & cp));
+    result[1] = static_cast<char>(0x80 | (0x3f & (cp >> 6)));
+    result[0] = static_cast<char>(0xE0 | (0xf & (cp >> 12)));
+  }
+  else if (cp <= 0x10FFFF)
+  {
+    result.resize(4);
+    result[3] = static_cast<char>(0x80 | (0x3f & cp));
+    result[2] = static_cast<char>(0x80 | (0x3f & (cp >> 6)));
+    result[1] = static_cast<char>(0x80 | (0x3f & (cp >> 12)));
+    result[0] = static_cast<char>(0xF0 | (0x7 & (cp >> 18)));
+  }
+
+  return result;
+}
+
+/// Returns true if ch is a control character (in range [1,31]).
+static inline bool isControlCharacter(char ch) { return ch > 0 && ch <= 0x1F; }
+
+enum
+{
+  /// Constant that specify the size of the buffer that must be passed to
+  /// uintToString.
+  uintToStringBufferSize = 3 * sizeof(LargestUInt) + 1
+};
+
+// Defines a char buffer for use with uintToString().
+typedef char UIntToStringBuffer[uintToStringBufferSize];
+
+/** Converts an unsigned integer to string.
+ * @param value Unsigned interger to convert to string
+ * @param current Input/Output string buffer.
+ *        Must have at least uintToStringBufferSize chars free.
+ */
+static inline void uintToString(LargestUInt value, char *&current)
+{
+  *--current = 0;
+  do
+  {
+    *--current = static_cast<char>(value % 10U + static_cast<unsigned>('0'));
+    value /= 10;
+  } while (value != 0);
+}
+
+/** Change ',' to '.' everywhere in buffer.
+ *
+ * We had a sophisticated way, but it did not work in WinCE.
+ * @see https://github.com/open-source-parsers/jsoncpp/pull/9
+ */
+static inline void fixNumericLocale(char *begin, char *end)
+{
+  while (begin < end)
+  {
+    if (*begin == ',')
+    {
+      *begin = '.';
+    }
+    ++begin;
+  }
+}
+
+static inline void fixNumericLocaleInput(char *begin, char *end)
+{
+  char decimalPoint = getDecimalPoint();
+  if (decimalPoint != '\0' && decimalPoint != '.')
+  {
+    while (begin < end)
+    {
+      if (*begin == '.')
+      {
+        *begin = decimalPoint;
+      }
+      ++begin;
+    }
+  }
+}
+
+} // namespace Json {
+
+#endif // LIB_JSONCPP_JSON_TOOL_H_INCLUDED
+
+// //////////////////////////////////////////////////////////////////////
+// End of content of file: src/lib_json/json_tool.h
+// //////////////////////////////////////////////////////////////////////
+
+// //////////////////////////////////////////////////////////////////////
+// Beginning of content of file: src/lib_json/json_reader.cpp
+// //////////////////////////////////////////////////////////////////////
+
+// Copyright 2007-2011 Baptiste Lepilleur
+// Distributed under MIT license, or public domain if desired and
+// recognized in your jurisdiction.
+// See file LICENSE for detail or copy at http://jsoncpp.sourceforge.net/LICENSE
+
+#if !defined(JSON_IS_AMALGAMATION)
+#include <json/assertions.h>
+#include <json/reader.h>
+#include <json/value.h>
+#include "json_tool.h"
+#endif // if !defined(JSON_IS_AMALGAMATION)
+#include <utility>
+#include <cstdio>
+#include <cassert>
+#include <cstring>
+#include <istream>
+#include <sstream>
+#include <memory>
+#include <set>
+#include <limits>
+
+#if defined(_MSC_VER)
+#if !defined(WINCE) && defined(__STDC_SECURE_LIB__) && _MSC_VER >= 1500 // VC++ 9.0 and above
+#define snprintf sprintf_s
+#elif _MSC_VER >= 1900 // VC++ 14.0 and above
+#define snprintf std::snprintf
+#else
+#define snprintf _snprintf
+#endif
+#elif defined(__ANDROID__) || defined(__QNXNTO__)
+#define snprintf snprintf
+#elif __cplusplus >= 201103L
+#if !defined(__MINGW32__) && !defined(__CYGWIN__)
+#define snprintf std::snprintf
+#endif
+#endif
+
+#if defined(__QNXNTO__)
+#define sscanf std::sscanf
+#endif
+
+#if defined(_MSC_VER) && _MSC_VER >= 1400 // VC++ 8.0
+// Disable warning about strdup being deprecated.
+#pragma warning(disable : 4996)
+#endif
+
+static int const stackLimit_g = 1000;
+static int stackDepth_g = 0; // see readValue()
+
+namespace Json
+{
+
+#if __cplusplus >= 201103L || (defined(_CPPLIB_VER) && _CPPLIB_VER >= 520)
+typedef std::unique_ptr<CharReader> CharReaderPtr;
+#else
+typedef std::auto_ptr<CharReader> CharReaderPtr;
+#endif
+
+// Implementation of class Features
+// ////////////////////////////////
+
+Features::Features()
+    : allowComments_(true), strictRoot_(false), allowDroppedNullPlaceholders_(false),
+      allowNumericKeys_(false)
+{
+}
+
+Features Features::all() { return Features(); }
+
+Features Features::strictMode()
+{
+  Features features;
+  features.allowComments_ = false;
+  features.strictRoot_ = true;
+  features.allowDroppedNullPlaceholders_ = false;
+  features.allowNumericKeys_ = false;
+  return features;
+}
+
+// Implementation of class Reader
+// ////////////////////////////////
+
+static bool containsNewLine(Reader::Location begin, Reader::Location end)
+{
+  for (; begin < end; ++begin)
+    if (*begin == '\n' || *begin == '\r')
+      return true;
+  return false;
+}
+
+// Class Reader
+// //////////////////////////////////////////////////////////////////
+
+Reader::Reader()
+    : errors_(), document_(), begin_(), end_(), current_(), lastValueEnd_(), lastValue_(),
+      commentsBefore_(), features_(Features::all()), collectComments_()
+{
+}
+
+Reader::Reader(const Features &features)
+    : errors_(), document_(), begin_(), end_(), current_(), lastValueEnd_(), lastValue_(),
+      commentsBefore_(), features_(features), collectComments_()
+{
+}
+
+bool Reader::parse(const std::string &document, Value &root, bool collectComments)
+{
+  JSONCPP_STRING documentCopy(document.data(), document.data() + document.capacity());
+  std::swap(documentCopy, document_);
+  const char *begin = document_.c_str();
+  const char *end = begin + document_.length();
+  return parse(begin, end, root, collectComments);
+}
+
+bool Reader::parse(std::istream &sin, Value &root, bool collectComments)
+{
+  // std::istream_iterator<char> begin(sin);
+  // std::istream_iterator<char> end;
+  // Those would allow streamed input from a file, if parse() were a
+  // template function.
+
+  // Since JSONCPP_STRING is reference-counted, this at least does not
+  // create an extra copy.
+  JSONCPP_STRING doc;
+  std::getline(sin, doc, (char)EOF);
+  return parse(doc.data(), doc.data() + doc.size(), root, collectComments);
+}
+
+bool Reader::parse(const char *beginDoc, const char *endDoc, Value &root, bool collectComments)
+{
+  if (!features_.allowComments_)
+  {
+    collectComments = false;
+  }
+
+  begin_ = beginDoc;
+  end_ = endDoc;
+  collectComments_ = collectComments;
+  current_ = begin_;
+  lastValueEnd_ = 0;
+  lastValue_ = 0;
+  commentsBefore_ = "";
+  errors_.clear();
+  while (!nodes_.empty())
+    nodes_.pop();
+  nodes_.push(&root);
+
+  stackDepth_g = 0; // Yes, this is bad coding, but options are limited.
+  bool successful = readValue();
+  Token token;
+  skipCommentTokens(token);
+  if (collectComments_ && !commentsBefore_.empty())
+    root.setComment(commentsBefore_, commentAfter);
+  if (features_.strictRoot_)
+  {
+    if (!root.isArray() && !root.isObject())
+    {
+      // Set error location to start of doc, ideally should be first token found
+      // in doc
+      token.type_ = tokenError;
+      token.start_ = beginDoc;
+      token.end_ = endDoc;
+      addError("A valid JSON document must be either an array or an object value.", token);
+      return false;
+    }
+  }
+  return successful;
+}
+
+bool Reader::readValue()
+{
+  // This is a non-reentrant way to support a stackLimit. Terrible!
+  // But this deprecated class has a security problem: Bad input can
+  // cause a seg-fault. This seems like a fair, binary-compatible way
+  // to prevent the problem.
+  if (stackDepth_g >= stackLimit_g)
+    throwRuntimeError("Exceeded stackLimit in readValue().");
+  ++stackDepth_g;
+
+  Token token;
+  skipCommentTokens(token);
+  bool successful = true;
+
+  if (collectComments_ && !commentsBefore_.empty())
+  {
+    currentValue().setComment(commentsBefore_, commentBefore);
+    commentsBefore_ = "";
+  }
+
+  switch (token.type_)
+  {
+    case tokenObjectBegin:
+      successful = readObject(token);
+      currentValue().setOffsetLimit(current_ - begin_);
+      break;
+    case tokenArrayBegin:
+      successful = readArray(token);
+      currentValue().setOffsetLimit(current_ - begin_);
+      break;
+    case tokenNumber:
+      successful = decodeNumber(token);
+      break;
+    case tokenString:
+      successful = decodeString(token);
+      break;
+    case tokenTrue:
+    {
+      Value v(true);
+      currentValue().swapPayload(v);
+      currentValue().setOffsetStart(token.start_ - begin_);
+      currentValue().setOffsetLimit(token.end_ - begin_);
+    }
+    break;
+    case tokenFalse:
+    {
+      Value v(false);
+      currentValue().swapPayload(v);
+      currentValue().setOffsetStart(token.start_ - begin_);
+      currentValue().setOffsetLimit(token.end_ - begin_);
+    }
+    break;
+    case tokenNull:
+    {
+      Value v;
+      currentValue().swapPayload(v);
+      currentValue().setOffsetStart(token.start_ - begin_);
+      currentValue().setOffsetLimit(token.end_ - begin_);
+    }
+    break;
+    case tokenArraySeparator:
+    case tokenObjectEnd:
+    case tokenArrayEnd:
+      if (features_.allowDroppedNullPlaceholders_)
+      {
+        // "Un-read" the current token and mark the current value as a null
+        // token.
+        current_--;
+        Value v;
+        currentValue().swapPayload(v);
+        currentValue().setOffsetStart(current_ - begin_ - 1);
+        currentValue().setOffsetLimit(current_ - begin_);
+        break;
+      } // Else, fall through...
+    default:
+      currentValue().setOffsetStart(token.start_ - begin_);
+      currentValue().setOffsetLimit(token.end_ - begin_);
+      return addError("Syntax error: value, object or array expected.", token);
+  }
+
+  if (collectComments_)
+  {
+    lastValueEnd_ = current_;
+    lastValue_ = &currentValue();
+  }
+
+  --stackDepth_g;
+  return successful;
+}
+
+void Reader::skipCommentTokens(Token &token)
+{
+  if (features_.allowComments_)
+  {
+    do
+    {
+      readToken(token);
+    } while (token.type_ == tokenComment);
+  }
+  else
+  {
+    readToken(token);
+  }
+}
+
+bool Reader::readToken(Token &token)
+{
+  skipSpaces();
+  token.start_ = current_;
+  Char c = getNextChar();
+  bool ok = true;
+  switch (c)
+  {
+    case '{':
+      token.type_ = tokenObjectBegin;
+      break;
+    case '}':
+      token.type_ = tokenObjectEnd;
+      break;
+    case '[':
+      token.type_ = tokenArrayBegin;
+      break;
+    case ']':
+      token.type_ = tokenArrayEnd;
+      break;
+    case '"':
+      token.type_ = tokenString;
+      ok = readString();
+      break;
+    case '/':
+      token.type_ = tokenComment;
+      ok = readComment();
+      break;
+    case '0':
+    case '1':
+    case '2':
+    case '3':
+    case '4':
+    case '5':
+    case '6':
+    case '7':
+    case '8':
+    case '9':
+    case '-':
+      token.type_ = tokenNumber;
+      readNumber();
+      break;
+    case 't':
+      token.type_ = tokenTrue;
+      ok = match("rue", 3);
+      break;
+    case 'f':
+      token.type_ = tokenFalse;
+      ok = match("alse", 4);
+      break;
+    case 'n':
+      token.type_ = tokenNull;
+      ok = match("ull", 3);
+      break;
+    case ',':
+      token.type_ = tokenArraySeparator;
+      break;
+    case ':':
+      token.type_ = tokenMemberSeparator;
+      break;
+    case 0:
+      token.type_ = tokenEndOfStream;
+      break;
+    default:
+      ok = false;
+      break;
+  }
+  if (!ok)
+    token.type_ = tokenError;
+  token.end_ = current_;
+  return true;
+}
+
+void Reader::skipSpaces()
+{
+  while (current_ != end_)
+  {
+    Char c = *current_;
+    if (c == ' ' || c == '\t' || c == '\r' || c == '\n')
+      ++current_;
+    else
+      break;
+  }
+}
+
+bool Reader::match(Location pattern, int patternLength)
+{
+  if (end_ - current_ < patternLength)
+    return false;
+  int index = patternLength;
+  while (index--)
+    if (current_[index] != pattern[index])
+      return false;
+  current_ += patternLength;
+  return true;
+}
+
+bool Reader::readComment()
+{
+  Location commentBegin = current_ - 1;
+  Char c = getNextChar();
+  bool successful = false;
+  if (c == '*')
+    successful = readCStyleComment();
+  else if (c == '/')
+    successful = readCppStyleComment();
+  if (!successful)
+    return false;
+
+  if (collectComments_)
+  {
+    CommentPlacement placement = commentBefore;
+    if (lastValueEnd_ && !containsNewLine(lastValueEnd_, commentBegin))
+    {
+      if (c != '*' || !containsNewLine(commentBegin, current_))
+        placement = commentAfterOnSameLine;
+    }
+
+    addComment(commentBegin, current_, placement);
+  }
+  return true;
+}
+
+static JSONCPP_STRING normalizeEOL(Reader::Location begin, Reader::Location end)
+{
+  JSONCPP_STRING normalized;
+  normalized.reserve(static_cast<size_t>(end - begin));
+  Reader::Location current = begin;
+  while (current != end)
+  {
+    char c = *current++;
+    if (c == '\r')
+    {
+      if (current != end && *current == '\n')
+        // convert dos EOL
+        ++current;
+      // convert Mac EOL
+      normalized += '\n';
+    }
+    else
+    {
+      normalized += c;
+    }
+  }
+  return normalized;
+}
+
+void Reader::addComment(Location begin, Location end, CommentPlacement placement)
+{
+  assert(collectComments_);
+  const JSONCPP_STRING &normalized = normalizeEOL(begin, end);
+  if (placement == commentAfterOnSameLine)
+  {
+    assert(lastValue_ != 0);
+    lastValue_->setComment(normalized, placement);
+  }
+  else
+  {
+    commentsBefore_ += normalized;
+  }
+}
+
+bool Reader::readCStyleComment()
+{
+  while ((current_ + 1) < end_)
+  {
+    Char c = getNextChar();
+    if (c == '*' && *current_ == '/')
+      break;
+  }
+  return getNextChar() == '/';
+}
+
+bool Reader::readCppStyleComment()
+{
+  while (current_ != end_)
+  {
+    Char c = getNextChar();
+    if (c == '\n')
+      break;
+    if (c == '\r')
+    {
+      // Consume DOS EOL. It will be normalized in addComment.
+      if (current_ != end_ && *current_ == '\n')
+        getNextChar();
+      // Break on Moc OS 9 EOL.
+      break;
+    }
+  }
+  return true;
+}
+
+void Reader::readNumber()
+{
+  const char *p = current_;
+  char c = '0'; // stopgap for already consumed character
+  // integral part
+  while (c >= '0' && c <= '9')
+    c = (current_ = p) < end_ ? *p++ : '\0';
+  // fractional part
+  if (c == '.')
+  {
+    c = (current_ = p) < end_ ? *p++ : '\0';
+    while (c >= '0' && c <= '9')
+      c = (current_ = p) < end_ ? *p++ : '\0';
+  }
+  // exponential part
+  if (c == 'e' || c == 'E')
+  {
+    c = (current_ = p) < end_ ? *p++ : '\0';
+    if (c == '+' || c == '-')
+      c = (current_ = p) < end_ ? *p++ : '\0';
+    while (c >= '0' && c <= '9')
+      c = (current_ = p) < end_ ? *p++ : '\0';
+  }
+}
+
+bool Reader::readString()
+{
+  Char c = '\0';
+  while (current_ != end_)
+  {
+    c = getNextChar();
+    if (c == '\\')
+      getNextChar();
+    else if (c == '"')
+      break;
+  }
+  return c == '"';
+}
+
+bool Reader::readObject(Token &tokenStart)
+{
+  Token tokenName;
+  JSONCPP_STRING name;
+  Value init(objectValue);
+  currentValue().swapPayload(init);
+  currentValue().setOffsetStart(tokenStart.start_ - begin_);
+  while (readToken(tokenName))
+  {
+    bool initialTokenOk = true;
+    while (tokenName.type_ == tokenComment && initialTokenOk)
+      initialTokenOk = readToken(tokenName);
+    if (!initialTokenOk)
+      break;
+    if (tokenName.type_ == tokenObjectEnd && name.empty()) // empty object
+      return true;
+    name = "";
+    if (tokenName.type_ == tokenString)
+    {
+      if (!decodeString(tokenName, name))
+        return recoverFromError(tokenObjectEnd);
+    }
+    else if (tokenName.type_ == tokenNumber && features_.allowNumericKeys_)
+    {
+      Value numberName;
+      if (!decodeNumber(tokenName, numberName))
+        return recoverFromError(tokenObjectEnd);
+      name = JSONCPP_STRING(numberName.asCString());
+    }
+    else
+    {
+      break;
+    }
+
+    Token colon;
+    if (!readToken(colon) || colon.type_ != tokenMemberSeparator)
+    {
+      return addErrorAndRecover("Missing ':' after object member name", colon, tokenObjectEnd);
+    }
+    Value &value = currentValue()[name];
+    nodes_.push(&value);
+    bool ok = readValue();
+    nodes_.pop();
+    if (!ok) // error already set
+      return recoverFromError(tokenObjectEnd);
+
+    Token comma;
+    if (!readToken(comma) || (comma.type_ != tokenObjectEnd && comma.type_ != tokenArraySeparator &&
+                              comma.type_ != tokenComment))
+    {
+      return addErrorAndRecover("Missing ',' or '}' in object declaration", comma, tokenObjectEnd);
+    }
+    bool finalizeTokenOk = true;
+    while (comma.type_ == tokenComment && finalizeTokenOk)
+      finalizeTokenOk = readToken(comma);
+    if (comma.type_ == tokenObjectEnd)
+      return true;
+  }
+  return addErrorAndRecover("Missing '}' or object member name", tokenName, tokenObjectEnd);
+}
+
+bool Reader::readArray(Token &tokenStart)
+{
+  Value init(arrayValue);
+  currentValue().swapPayload(init);
+  currentValue().setOffsetStart(tokenStart.start_ - begin_);
+  skipSpaces();
+  if (current_ != end_ && *current_ == ']') // empty array
+  {
+    Token endArray;
+    readToken(endArray);
+    return true;
+  }
+  int index = 0;
+  for (;;)
+  {
+    Value &value = currentValue()[index++];
+    nodes_.push(&value);
+    bool ok = readValue();
+    nodes_.pop();
+    if (!ok) // error already set
+      return recoverFromError(tokenArrayEnd);
+
+    Token token;
+    // Accept Comment after last item in the array.
+    ok = readToken(token);
+    while (token.type_ == tokenComment && ok)
+    {
+      ok = readToken(token);
+    }
+    bool badTokenType = (token.type_ != tokenArraySeparator && token.type_ != tokenArrayEnd);
+    if (!ok || badTokenType)
+    {
+      return addErrorAndRecover("Missing ',' or ']' in array declaration", token, tokenArrayEnd);
+    }
+    if (token.type_ == tokenArrayEnd)
+      break;
+  }
+  return true;
+}
+
+bool Reader::decodeNumber(Token &token)
+{
+  Value decoded;
+  if (!decodeNumber(token, decoded))
+    return false;
+  currentValue().swapPayload(decoded);
+  currentValue().setOffsetStart(token.start_ - begin_);
+  currentValue().setOffsetLimit(token.end_ - begin_);
+  return true;
+}
+
+bool Reader::decodeNumber(Token &token, Value &decoded)
+{
+  // Attempts to parse the number as an integer. If the number is
+  // larger than the maximum supported value of an integer then
+  // we decode the number as a double.
+  Location current = token.start_;
+  bool isNegative = *current == '-';
+  if (isNegative)
+    ++current;
+  // TODO: Help the compiler do the div and mod at compile time or get rid of them.
+  Value::LargestUInt maxIntegerValue =
+      isNegative ? Value::LargestUInt(Value::maxLargestInt) + 1 : Value::maxLargestUInt;
+  Value::LargestUInt threshold = maxIntegerValue / 10;
+  Value::LargestUInt value = 0;
+  while (current < token.end_)
+  {
+    Char c = *current++;
+    if (c < '0' || c > '9')
+      return decodeDouble(token, decoded);
+    Value::UInt digit(static_cast<Value::UInt>(c - '0'));
+    if (value >= threshold)
+    {
+      // We've hit or exceeded the max value divided by 10 (rounded down). If
+      // a) we've only just touched the limit, b) this is the last digit, and
+      // c) it's small enough to fit in that rounding delta, we're okay.
+      // Otherwise treat this number as a double to avoid overflow.
+      if (value > threshold || current != token.end_ || digit > maxIntegerValue % 10)
+      {
+        return decodeDouble(token, decoded);
+      }
+    }
+    value = value * 10 + digit;
+  }
+  if (isNegative && value == maxIntegerValue)
+    decoded = Value::minLargestInt;
+  else if (isNegative)
+    decoded = -Value::LargestInt(value);
+  else if (value <= Value::LargestUInt(Value::maxInt))
+    decoded = Value::LargestInt(value);
+  else
+    decoded = value;
+  return true;
+}
+
+bool Reader::decodeDouble(Token &token)
+{
+  Value decoded;
+  if (!decodeDouble(token, decoded))
+    return false;
+  currentValue().swapPayload(decoded);
+  currentValue().setOffsetStart(token.start_ - begin_);
+  currentValue().setOffsetLimit(token.end_ - begin_);
+  return true;
+}
+
+bool Reader::decodeDouble(Token &token, Value &decoded)
+{
+  double value = 0;
+  JSONCPP_STRING buffer(token.start_, token.end_);
+  JSONCPP_ISTRINGSTREAM is(buffer);
+  if (!(is >> value))
+    return addError("'" + JSONCPP_STRING(token.start_, token.end_) + "' is not a number.", token);
+  decoded = value;
+  return true;
+}
+
+bool Reader::decodeString(Token &token)
+{
+  JSONCPP_STRING decoded_string;
+  if (!decodeString(token, decoded_string))
+    return false;
+  Value decoded(decoded_string);
+  currentValue().swapPayload(decoded);
+  currentValue().setOffsetStart(token.start_ - begin_);
+  currentValue().setOffsetLimit(token.end_ - begin_);
+  return true;
+}
+
+bool Reader::decodeString(Token &token, JSONCPP_STRING &decoded)
+{
+  decoded.reserve(static_cast<size_t>(token.end_ - token.start_ - 2));
+  Location current = token.start_ + 1; // skip '"'
+  Location end = token.end_ - 1;       // do not include '"'
+  while (current != end)
+  {
+    Char c = *current++;
+    if (c == '"')
+      break;
+    else if (c == '\\')
+    {
+      if (current == end)
+        return addError("Empty escape sequence in string", token, current);
+      Char escape = *current++;
+      switch (escape)
+      {
+        case '"':
+          decoded += '"';
+          break;
+        case '/':
+          decoded += '/';
+          break;
+        case '\\':
+          decoded += '\\';
+          break;
+        case 'b':
+          decoded += '\b';
+          break;
+        case 'f':
+          decoded += '\f';
+          break;
+        case 'n':
+          decoded += '\n';
+          break;
+        case 'r':
+          decoded += '\r';
+          break;
+        case 't':
+          decoded += '\t';
+          break;
+        case 'u':
+        {
+          unsigned int unicode;
+          if (!decodeUnicodeCodePoint(token, current, end, unicode))
+            return false;
+          decoded += codePointToUTF8(unicode);
+        }
+        break;
+        default:
+          return addError("Bad escape sequence in string", token, current);
+      }
+    }
+    else
+    {
+      decoded += c;
+    }
+  }
+  return true;
+}
+
+bool Reader::decodeUnicodeCodePoint(Token &token, Location &current, Location end,
+                                    unsigned int &unicode)
+{
+
+  if (!decodeUnicodeEscapeSequence(token, current, end, unicode))
+    return false;
+  if (unicode >= 0xD800 && unicode <= 0xDBFF)
+  {
+    // surrogate pairs
+    if (end - current < 6)
+      return addError("additional six characters expected to parse unicode surrogate pair.", token,
+                      current);
+    unsigned int surrogatePair;
+    if (*(current++) == '\\' && *(current++) == 'u')
+    {
+      if (decodeUnicodeEscapeSequence(token, current, end, surrogatePair))
+      {
+        unicode = 0x10000 + ((unicode & 0x3FF) << 10) + (surrogatePair & 0x3FF);
+      }
+      else
+        return false;
+    }
+    else
+      return addError("expecting another \\u token to begin the second half of "
+                      "a unicode surrogate pair",
+                      token, current);
+  }
+  return true;
+}
+
+bool Reader::decodeUnicodeEscapeSequence(Token &token, Location &current, Location end,
+                                         unsigned int &ret_unicode)
+{
+  if (end - current < 4)
+    return addError("Bad unicode escape sequence in string: four digits expected.", token, current);
+  int unicode = 0;
+  for (int index = 0; index < 4; ++index)
+  {
+    Char c = *current++;
+    unicode *= 16;
+    if (c >= '0' && c <= '9')
+      unicode += c - '0';
+    else if (c >= 'a' && c <= 'f')
+      unicode += c - 'a' + 10;
+    else if (c >= 'A' && c <= 'F')
+      unicode += c - 'A' + 10;
+    else
+      return addError("Bad unicode escape sequence in string: hexadecimal digit expected.", token,
+                      current);
+  }
+  ret_unicode = static_cast<unsigned int>(unicode);
+  return true;
+}
+
+bool Reader::addError(const JSONCPP_STRING &message, Token &token, Location extra)
+{
+  ErrorInfo info;
+  info.token_ = token;
+  info.message_ = message;
+  info.extra_ = extra;
+  errors_.push_back(info);
+  return false;
+}
+
+bool Reader::recoverFromError(TokenType skipUntilToken)
+{
+  size_t const errorCount = errors_.size();
+  Token skip;
+  for (;;)
+  {
+    if (!readToken(skip))
+      errors_.resize(errorCount); // discard errors caused by recovery
+    if (skip.type_ == skipUntilToken || skip.type_ == tokenEndOfStream)
+      break;
+  }
+  errors_.resize(errorCount);
+  return false;
+}
+
+bool Reader::addErrorAndRecover(const JSONCPP_STRING &message, Token &token,
+                                TokenType skipUntilToken)
+{
+  addError(message, token);
+  return recoverFromError(skipUntilToken);
+}
+
+Value &Reader::currentValue() { return *(nodes_.top()); }
+
+Reader::Char Reader::getNextChar()
+{
+  if (current_ == end_)
+    return 0;
+  return *current_++;
+}
+
+void Reader::getLocationLineAndColumn(Location location, int &line, int &column) const
+{
+  Location current = begin_;
+  Location lastLineStart = current;
+  line = 0;
+  while (current < location && current != end_)
+  {
+    Char c = *current++;
+    if (c == '\r')
+    {
+      if (*current == '\n')
+        ++current;
+      lastLineStart = current;
+      ++line;
+    }
+    else if (c == '\n')
+    {
+      lastLineStart = current;
+      ++line;
+    }
+  }
+  // column & line start at 1
+  column = int(location - lastLineStart) + 1;
+  ++line;
+}
+
+JSONCPP_STRING Reader::getLocationLineAndColumn(Location location) const
+{
+  int line, column;
+  getLocationLineAndColumn(location, line, column);
+  char buffer[18 + 16 + 16 + 1];
+  snprintf(buffer, sizeof(buffer), "Line %d, Column %d", line, column);
+  return buffer;
+}
+
+// Deprecated. Preserved for backward compatibility
+JSONCPP_STRING Reader::getFormatedErrorMessages() const { return getFormattedErrorMessages(); }
+
+JSONCPP_STRING Reader::getFormattedErrorMessages() const
+{
+  JSONCPP_STRING formattedMessage;
+  for (Errors::const_iterator itError = errors_.begin(); itError != errors_.end(); ++itError)
+  {
+    const ErrorInfo &error = *itError;
+    formattedMessage += "* " + getLocationLineAndColumn(error.token_.start_) + "\n";
+    formattedMessage += "  " + error.message_ + "\n";
+    if (error.extra_)
+      formattedMessage += "See " + getLocationLineAndColumn(error.extra_) + " for detail.\n";
+  }
+  return formattedMessage;
+}
+
+std::vector<Reader::StructuredError> Reader::getStructuredErrors() const
+{
+  std::vector<Reader::StructuredError> allErrors;
+  for (Errors::const_iterator itError = errors_.begin(); itError != errors_.end(); ++itError)
+  {
+    const ErrorInfo &error = *itError;
+    Reader::StructuredError structured;
+    structured.offset_start = error.token_.start_ - begin_;
+    structured.offset_limit = error.token_.end_ - begin_;
+    structured.message = error.message_;
+    allErrors.push_back(structured);
+  }
+  return allErrors;
+}
+
+bool Reader::pushError(const Value &value, const JSONCPP_STRING &message)
+{
+  ptrdiff_t const length = end_ - begin_;
+  if (value.getOffsetStart() > length || value.getOffsetLimit() > length)
+    return false;
+  Token token;
+  token.type_ = tokenError;
+  token.start_ = begin_ + value.getOffsetStart();
+  token.end_ = end_ + value.getOffsetLimit();
+  ErrorInfo info;
+  info.token_ = token;
+  info.message_ = message;
+  info.extra_ = 0;
+  errors_.push_back(info);
+  return true;
+}
+
+bool Reader::pushError(const Value &value, const JSONCPP_STRING &message, const Value &extra)
+{
+  ptrdiff_t const length = end_ - begin_;
+  if (value.getOffsetStart() > length || value.getOffsetLimit() > length ||
+      extra.getOffsetLimit() > length)
+    return false;
+  Token token;
+  token.type_ = tokenError;
+  token.start_ = begin_ + value.getOffsetStart();
+  token.end_ = begin_ + value.getOffsetLimit();
+  ErrorInfo info;
+  info.token_ = token;
+  info.message_ = message;
+  info.extra_ = begin_ + extra.getOffsetStart();
+  errors_.push_back(info);
+  return true;
+}
+
+bool Reader::good() const { return !errors_.size(); }
+
+// exact copy of Features
+class OurFeatures
+{
+public:
+  static OurFeatures all();
+  bool allowComments_;
+  bool strictRoot_;
+  bool allowDroppedNullPlaceholders_;
+  bool allowNumericKeys_;
+  bool allowSingleQuotes_;
+  bool failIfExtra_;
+  bool rejectDupKeys_;
+  bool allowSpecialFloats_;
+  int stackLimit_;
+}; // OurFeatures
+
+// exact copy of Implementation of class Features
+// ////////////////////////////////
+
+OurFeatures OurFeatures::all() { return OurFeatures(); }
+
+// Implementation of class Reader
+// ////////////////////////////////
+
+// exact copy of Reader, renamed to OurReader
+class OurReader
+{
+public:
+  typedef char Char;
+  typedef const Char *Location;
+  struct StructuredError
+  {
+    ptrdiff_t offset_start;
+    ptrdiff_t offset_limit;
+    JSONCPP_STRING message;
+  };
+
+  OurReader(OurFeatures const &features);
+  bool parse(const char *beginDoc, const char *endDoc, Value &root, bool collectComments = true);
+  JSONCPP_STRING getFormattedErrorMessages() const;
+  std::vector<StructuredError> getStructuredErrors() const;
+  bool pushError(const Value &value, const JSONCPP_STRING &message);
+  bool pushError(const Value &value, const JSONCPP_STRING &message, const Value &extra);
+  bool good() const;
+
+private:
+  OurReader(OurReader const &);      // no impl
+  void operator=(OurReader const &); // no impl
+
+  enum TokenType
+  {
+    tokenEndOfStream = 0,
+    tokenObjectBegin,
+    tokenObjectEnd,
+    tokenArrayBegin,
+    tokenArrayEnd,
+    tokenString,
+    tokenNumber,
+    tokenTrue,
+    tokenFalse,
+    tokenNull,
+    tokenNaN,
+    tokenPosInf,
+    tokenNegInf,
+    tokenArraySeparator,
+    tokenMemberSeparator,
+    tokenComment,
+    tokenError
+  };
+
+  class Token
+  {
+  public:
+    TokenType type_;
+    Location start_;
+    Location end_;
+  };
+
+  class ErrorInfo
+  {
+  public:
+    Token token_;
+    JSONCPP_STRING message_;
+    Location extra_;
+  };
+
+  typedef std::deque<ErrorInfo> Errors;
+
+  bool readToken(Token &token);
+  void skipSpaces();
+  bool match(Location pattern, int patternLength);
+  bool readComment();
+  bool readCStyleComment();
+  bool readCppStyleComment();
+  bool readString();
+  bool readStringSingleQuote();
+  bool readNumber(bool checkInf);
+  bool readValue();
+  bool readObject(Token &token);
+  bool readArray(Token &token);
+  bool decodeNumber(Token &token);
+  bool decodeNumber(Token &token, Value &decoded);
+  bool decodeString(Token &token);
+  bool decodeString(Token &token, JSONCPP_STRING &decoded);
+  bool decodeDouble(Token &token);
+  bool decodeDouble(Token &token, Value &decoded);
+  bool decodeUnicodeCodePoint(Token &token, Location &current, Location end, unsigned int &unicode);
+  bool decodeUnicodeEscapeSequence(Token &token, Location &current, Location end,
+                                   unsigned int &unicode);
+  bool addError(const JSONCPP_STRING &message, Token &token, Location extra = 0);
+  bool recoverFromError(TokenType skipUntilToken);
+  bool addErrorAndRecover(const JSONCPP_STRING &message, Token &token, TokenType skipUntilToken);
+  void skipUntilSpace();
+  Value &currentValue();
+  Char getNextChar();
+  void getLocationLineAndColumn(Location location, int &line, int &column) const;
+  JSONCPP_STRING getLocationLineAndColumn(Location location) const;
+  void addComment(Location begin, Location end, CommentPlacement placement);
+  void skipCommentTokens(Token &token);
+
+  typedef std::stack<Value *> Nodes;
+  Nodes nodes_;
+  Errors errors_;
+  JSONCPP_STRING document_;
+  Location begin_;
+  Location end_;
+  Location current_;
+  Location lastValueEnd_;
+  Value *lastValue_;
+  JSONCPP_STRING commentsBefore_;
+  int stackDepth_;
+
+  OurFeatures const features_;
+  bool collectComments_;
+}; // OurReader
+
+// complete copy of Read impl, for OurReader
+
+OurReader::OurReader(OurFeatures const &features)
+    : errors_(), document_(), begin_(), end_(), current_(), lastValueEnd_(), lastValue_(),
+      commentsBefore_(), stackDepth_(0), features_(features), collectComments_()
+{
+}
+
+bool OurReader::parse(const char *beginDoc, const char *endDoc, Value &root, bool collectComments)
+{
+  if (!features_.allowComments_)
+  {
+    collectComments = false;
+  }
+
+  begin_ = beginDoc;
+  end_ = endDoc;
+  collectComments_ = collectComments;
+  current_ = begin_;
+  lastValueEnd_ = 0;
+  lastValue_ = 0;
+  commentsBefore_ = "";
+  errors_.clear();
+  while (!nodes_.empty())
+    nodes_.pop();
+  nodes_.push(&root);
+
+  stackDepth_ = 0;
+  bool successful = readValue();
+  Token token;
+  skipCommentTokens(token);
+  if (features_.failIfExtra_)
+  {
+    if ((features_.strictRoot_ || token.type_ != tokenError) && token.type_ != tokenEndOfStream)
+    {
+      addError("Extra non-whitespace after JSON value.", token);
+      return false;
+    }
+  }
+  if (collectComments_ && !commentsBefore_.empty())
+    root.setComment(commentsBefore_, commentAfter);
+  if (features_.strictRoot_)
+  {
+    if (!root.isArray() && !root.isObject())
+    {
+      // Set error location to start of doc, ideally should be first token found
+      // in doc
+      token.type_ = tokenError;
+      token.start_ = beginDoc;
+      token.end_ = endDoc;
+      addError("A valid JSON document must be either an array or an object value.", token);
+      return false;
+    }
+  }
+  return successful;
+}
+
+bool OurReader::readValue()
+{
+  if (stackDepth_ >= features_.stackLimit_)
+    throwRuntimeError("Exceeded stackLimit in readValue().");
+  ++stackDepth_;
+  Token token;
+  skipCommentTokens(token);
+  bool successful = true;
+
+  if (collectComments_ && !commentsBefore_.empty())
+  {
+    currentValue().setComment(commentsBefore_, commentBefore);
+    commentsBefore_ = "";
+  }
+
+  switch (token.type_)
+  {
+    case tokenObjectBegin:
+      successful = readObject(token);
+      currentValue().setOffsetLimit(current_ - begin_);
+      break;
+    case tokenArrayBegin:
+      successful = readArray(token);
+      currentValue().setOffsetLimit(current_ - begin_);
+      break;
+    case tokenNumber:
+      successful = decodeNumber(token);
+      break;
+    case tokenString:
+      successful = decodeString(token);
+      break;
+    case tokenTrue:
+    {
+      Value v(true);
+      currentValue().swapPayload(v);
+      currentValue().setOffsetStart(token.start_ - begin_);
+      currentValue().setOffsetLimit(token.end_ - begin_);
+    }
+    break;
+    case tokenFalse:
+    {
+      Value v(false);
+      currentValue().swapPayload(v);
+      currentValue().setOffsetStart(token.start_ - begin_);
+      currentValue().setOffsetLimit(token.end_ - begin_);
+    }
+    break;
+    case tokenNull:
+    {
+      Value v;
+      currentValue().swapPayload(v);
+      currentValue().setOffsetStart(token.start_ - begin_);
+      currentValue().setOffsetLimit(token.end_ - begin_);
+    }
+    break;
+    case tokenNaN:
+    {
+      Value v(std::numeric_limits<double>::quiet_NaN());
+      currentValue().swapPayload(v);
+      currentValue().setOffsetStart(token.start_ - begin_);
+      currentValue().setOffsetLimit(token.end_ - begin_);
+    }
+    break;
+    case tokenPosInf:
+    {
+      Value v(std::numeric_limits<double>::infinity());
+      currentValue().swapPayload(v);
+      currentValue().setOffsetStart(token.start_ - begin_);
+      currentValue().setOffsetLimit(token.end_ - begin_);
+    }
+    break;
+    case tokenNegInf:
+    {
+      Value v(-std::numeric_limits<double>::infinity());
+      currentValue().swapPayload(v);
+      currentValue().setOffsetStart(token.start_ - begin_);
+      currentValue().setOffsetLimit(token.end_ - begin_);
+    }
+    break;
+    case tokenArraySeparator:
+    case tokenObjectEnd:
+    case tokenArrayEnd:
+      if (features_.allowDroppedNullPlaceholders_)
+      {
+        // "Un-read" the current token and mark the current value as a null
+        // token.
+        current_--;
+        Value v;
+        currentValue().swapPayload(v);
+        currentValue().setOffsetStart(current_ - begin_ - 1);
+        currentValue().setOffsetLimit(current_ - begin_);
+        break;
+      } // else, fall through ...
+    default:
+      currentValue().setOffsetStart(token.start_ - begin_);
+      currentValue().setOffsetLimit(token.end_ - begin_);
+      return addError("Syntax error: value, object or array expected.", token);
+  }
+
+  if (collectComments_)
+  {
+    lastValueEnd_ = current_;
+    lastValue_ = &currentValue();
+  }
+
+  --stackDepth_;
+  return successful;
+}
+
+void OurReader::skipCommentTokens(Token &token)
+{
+  if (features_.allowComments_)
+  {
+    do
+    {
+      readToken(token);
+    } while (token.type_ == tokenComment);
+  }
+  else
+  {
+    readToken(token);
+  }
+}
+
+bool OurReader::readToken(Token &token)
+{
+  skipSpaces();
+  token.start_ = current_;
+  Char c = getNextChar();
+  bool ok = true;
+  switch (c)
+  {
+    case '{':
+      token.type_ = tokenObjectBegin;
+      break;
+    case '}':
+      token.type_ = tokenObjectEnd;
+      break;
+    case '[':
+      token.type_ = tokenArrayBegin;
+      break;
+    case ']':
+      token.type_ = tokenArrayEnd;
+      break;
+    case '"':
+      token.type_ = tokenString;
+      ok = readString();
+      break;
+    case '\'':
+      if (features_.allowSingleQuotes_)
+      {
+        token.type_ = tokenString;
+        ok = readStringSingleQuote();
+        break;
+      } // else continue
+    case '/':
+      token.type_ = tokenComment;
+      ok = readComment();
+      break;
+    case '0':
+    case '1':
+    case '2':
+    case '3':
+    case '4':
+    case '5':
+    case '6':
+    case '7':
+    case '8':
+    case '9':
+      token.type_ = tokenNumber;
+      readNumber(false);
+      break;
+    case '-':
+      if (readNumber(true))
+      {
+        token.type_ = tokenNumber;
+      }
+      else
+      {
+        token.type_ = tokenNegInf;
+        ok = features_.allowSpecialFloats_ && match("nfinity", 7);
+      }
+      break;
+    case 't':
+      token.type_ = tokenTrue;
+      ok = match("rue", 3);
+      break;
+    case 'f':
+      token.type_ = tokenFalse;
+      ok = match("alse", 4);
+      break;
+    case 'n':
+      token.type_ = tokenNull;
+      ok = match("ull", 3);
+      break;
+    case 'N':
+      if (features_.allowSpecialFloats_)
+      {
+        token.type_ = tokenNaN;
+        ok = match("aN", 2);
+      }
+      else
+      {
+        ok = false;
+      }
+      break;
+    case 'I':
+      if (features_.allowSpecialFloats_)
+      {
+        token.type_ = tokenPosInf;
+        ok = match("nfinity", 7);
+      }
+      else
+      {
+        ok = false;
+      }
+      break;
+    case ',':
+      token.type_ = tokenArraySeparator;
+      break;
+    case ':':
+      token.type_ = tokenMemberSeparator;
+      break;
+    case 0:
+      token.type_ = tokenEndOfStream;
+      break;
+    default:
+      ok = false;
+      break;
+  }
+  if (!ok)
+    token.type_ = tokenError;
+  token.end_ = current_;
+  return true;
+}
+
+void OurReader::skipSpaces()
+{
+  while (current_ != end_)
+  {
+    Char c = *current_;
+    if (c == ' ' || c == '\t' || c == '\r' || c == '\n')
+      ++current_;
+    else
+      break;
+  }
+}
+
+bool OurReader::match(Location pattern, int patternLength)
+{
+  if (end_ - current_ < patternLength)
+    return false;
+  int index = patternLength;
+  while (index--)
+    if (current_[index] != pattern[index])
+      return false;
+  current_ += patternLength;
+  return true;
+}
+
+bool OurReader::readComment()
+{
+  Location commentBegin = current_ - 1;
+  Char c = getNextChar();
+  bool successful = false;
+  if (c == '*')
+    successful = readCStyleComment();
+  else if (c == '/')
+    successful = readCppStyleComment();
+  if (!successful)
+    return false;
+
+  if (collectComments_)
+  {
+    CommentPlacement placement = commentBefore;
+    if (lastValueEnd_ && !containsNewLine(lastValueEnd_, commentBegin))
+    {
+      if (c != '*' || !containsNewLine(commentBegin, current_))
+        placement = commentAfterOnSameLine;
+    }
+
+    addComment(commentBegin, current_, placement);
+  }
+  return true;
+}
+
+void OurReader::addComment(Location begin, Location end, CommentPlacement placement)
+{
+  assert(collectComments_);
+  const JSONCPP_STRING &normalized = normalizeEOL(begin, end);
+  if (placement == commentAfterOnSameLine)
+  {
+    assert(lastValue_ != 0);
+    lastValue_->setComment(normalized, placement);
+  }
+  else
+  {
+    commentsBefore_ += normalized;
+  }
+}
+
+bool OurReader::readCStyleComment()
+{
+  while ((current_ + 1) < end_)
+  {
+    Char c = getNextChar();
+    if (c == '*' && *current_ == '/')
+      break;
+  }
+  return getNextChar() == '/';
+}
+
+bool OurReader::readCppStyleComment()
+{
+  while (current_ != end_)
+  {
+    Char c = getNextChar();
+    if (c == '\n')
+      break;
+    if (c == '\r')
+    {
+      // Consume DOS EOL. It will be normalized in addComment.
+      if (current_ != end_ && *current_ == '\n')
+        getNextChar();
+      // Break on Moc OS 9 EOL.
+      break;
+    }
+  }
+  return true;
+}
+
+bool OurReader::readNumber(bool checkInf)
+{
+  const char *p = current_;
+  if (checkInf && p != end_ && *p == 'I')
+  {
+    current_ = ++p;
+    return false;
+  }
+  char c = '0'; // stopgap for already consumed character
+  // integral part
+  while (c >= '0' && c <= '9')
+    c = (current_ = p) < end_ ? *p++ : '\0';
+  // fractional part
+  if (c == '.')
+  {
+    c = (current_ = p) < end_ ? *p++ : '\0';
+    while (c >= '0' && c <= '9')
+      c = (current_ = p) < end_ ? *p++ : '\0';
+  }
+  // exponential part
+  if (c == 'e' || c == 'E')
+  {
+    c = (current_ = p) < end_ ? *p++ : '\0';
+    if (c == '+' || c == '-')
+      c = (current_ = p) < end_ ? *p++ : '\0';
+    while (c >= '0' && c <= '9')
+      c = (current_ = p) < end_ ? *p++ : '\0';
+  }
+  return true;
+}
+bool OurReader::readString()
+{
+  Char c = 0;
+  while (current_ != end_)
+  {
+    c = getNextChar();
+    if (c == '\\')
+      getNextChar();
+    else if (c == '"')
+      break;
+  }
+  return c == '"';
+}
+
+bool OurReader::readStringSingleQuote()
+{
+  Char c = 0;
+  while (current_ != end_)
+  {
+    c = getNextChar();
+    if (c == '\\')
+      getNextChar();
+    else if (c == '\'')
+      break;
+  }
+  return c == '\'';
+}
+
+bool OurReader::readObject(Token &tokenStart)
+{
+  Token tokenName;
+  JSONCPP_STRING name;
+  Value init(objectValue);
+  currentValue().swapPayload(init);
+  currentValue().setOffsetStart(tokenStart.start_ - begin_);
+  while (readToken(tokenName))
+  {
+    bool initialTokenOk = true;
+    while (tokenName.type_ == tokenComment && initialTokenOk)
+      initialTokenOk = readToken(tokenName);
+    if (!initialTokenOk)
+      break;
+    if (tokenName.type_ == tokenObjectEnd && name.empty()) // empty object
+      return true;
+    name = "";
+    if (tokenName.type_ == tokenString)
+    {
+      if (!decodeString(tokenName, name))
+        return recoverFromError(tokenObjectEnd);
+    }
+    else if (tokenName.type_ == tokenNumber && features_.allowNumericKeys_)
+    {
+      Value numberName;
+      if (!decodeNumber(tokenName, numberName))
+        return recoverFromError(tokenObjectEnd);
+      name = numberName.asString();
+    }
+    else
+    {
+      break;
+    }
+
+    Token colon;
+    if (!readToken(colon) || colon.type_ != tokenMemberSeparator)
+    {
+      return addErrorAndRecover("Missing ':' after object member name", colon, tokenObjectEnd);
+    }
+    if (name.length() >= (1U << 30))
+      throwRuntimeError("keylength >= 2^30");
+    if (features_.rejectDupKeys_ && currentValue().isMember(name))
+    {
+      JSONCPP_STRING msg = "Duplicate key: '" + name + "'";
+      return addErrorAndRecover(msg, tokenName, tokenObjectEnd);
+    }
+    Value &value = currentValue()[name];
+    nodes_.push(&value);
+    bool ok = readValue();
+    nodes_.pop();
+    if (!ok) // error already set
+      return recoverFromError(tokenObjectEnd);
+
+    Token comma;
+    if (!readToken(comma) || (comma.type_ != tokenObjectEnd && comma.type_ != tokenArraySeparator &&
+                              comma.type_ != tokenComment))
+    {
+      return addErrorAndRecover("Missing ',' or '}' in object declaration", comma, tokenObjectEnd);
+    }
+    bool finalizeTokenOk = true;
+    while (comma.type_ == tokenComment && finalizeTokenOk)
+      finalizeTokenOk = readToken(comma);
+    if (comma.type_ == tokenObjectEnd)
+      return true;
+  }
+  return addErrorAndRecover("Missing '}' or object member name", tokenName, tokenObjectEnd);
+}
+
+bool OurReader::readArray(Token &tokenStart)
+{
+  Value init(arrayValue);
+  currentValue().swapPayload(init);
+  currentValue().setOffsetStart(tokenStart.start_ - begin_);
+  skipSpaces();
+  if (current_ != end_ && *current_ == ']') // empty array
+  {
+    Token endArray;
+    readToken(endArray);
+    return true;
+  }
+  int index = 0;
+  for (;;)
+  {
+    Value &value = currentValue()[index++];
+    nodes_.push(&value);
+    bool ok = readValue();
+    nodes_.pop();
+    if (!ok) // error already set
+      return recoverFromError(tokenArrayEnd);
+
+    Token token;
+    // Accept Comment after last item in the array.
+    ok = readToken(token);
+    while (token.type_ == tokenComment && ok)
+    {
+      ok = readToken(token);
+    }
+    bool badTokenType = (token.type_ != tokenArraySeparator && token.type_ != tokenArrayEnd);
+    if (!ok || badTokenType)
+    {
+      return addErrorAndRecover("Missing ',' or ']' in array declaration", token, tokenArrayEnd);
+    }
+    if (token.type_ == tokenArrayEnd)
+      break;
+  }
+  return true;
+}
+
+bool OurReader::decodeNumber(Token &token)
+{
+  Value decoded;
+  if (!decodeNumber(token, decoded))
+    return false;
+  currentValue().swapPayload(decoded);
+  currentValue().setOffsetStart(token.start_ - begin_);
+  currentValue().setOffsetLimit(token.end_ - begin_);
+  return true;
+}
+
+bool OurReader::decodeNumber(Token &token, Value &decoded)
+{
+  // Attempts to parse the number as an integer. If the number is
+  // larger than the maximum supported value of an integer then
+  // we decode the number as a double.
+  Location current = token.start_;
+  bool isNegative = *current == '-';
+  if (isNegative)
+    ++current;
+  // TODO: Help the compiler do the div and mod at compile time or get rid of them.
+  Value::LargestUInt maxIntegerValue =
+      isNegative ? Value::LargestUInt(-Value::minLargestInt) : Value::maxLargestUInt;
+  Value::LargestUInt threshold = maxIntegerValue / 10;
+  Value::LargestUInt value = 0;
+  while (current < token.end_)
+  {
+    Char c = *current++;
+    if (c < '0' || c > '9')
+      return decodeDouble(token, decoded);
+    Value::UInt digit(static_cast<Value::UInt>(c - '0'));
+    if (value >= threshold)
+    {
+      // We've hit or exceeded the max value divided by 10 (rounded down). If
+      // a) we've only just touched the limit, b) this is the last digit, and
+      // c) it's small enough to fit in that rounding delta, we're okay.
+      // Otherwise treat this number as a double to avoid overflow.
+      if (value > threshold || current != token.end_ || digit > maxIntegerValue % 10)
+      {
+        return decodeDouble(token, decoded);
+      }
+    }
+    value = value * 10 + digit;
+  }
+  if (isNegative)
+    decoded = -Value::LargestInt(value);
+  else if (value <= Value::LargestUInt(Value::maxInt))
+    decoded = Value::LargestInt(value);
+  else
+    decoded = value;
+  return true;
+}
+
+bool OurReader::decodeDouble(Token &token)
+{
+  Value decoded;
+  if (!decodeDouble(token, decoded))
+    return false;
+  currentValue().swapPayload(decoded);
+  currentValue().setOffsetStart(token.start_ - begin_);
+  currentValue().setOffsetLimit(token.end_ - begin_);
+  return true;
+}
+
+bool OurReader::decodeDouble(Token &token, Value &decoded)
+{
+  double value = 0;
+  const int bufferSize = 32;
+  int count;
+  ptrdiff_t const length = token.end_ - token.start_;
+
+  // Sanity check to avoid buffer overflow exploits.
+  if (length < 0)
+  {
+    return addError("Unable to parse token length", token);
+  }
+  size_t const ulength = static_cast<size_t>(length);
+
+  // Avoid using a string constant for the format control string given to
+  // sscanf, as this can cause hard to debug crashes on OS X. See here for more
+  // info:
+  //
+  //     http://developer.apple.com/library/mac/#DOCUMENTATION/DeveloperTools/gcc-4.0.1/gcc/Incompatibilities.html
+  char format[] = "%lf";
+
+  if (length <= bufferSize)
+  {
+    Char buffer[bufferSize + 1];
+    memcpy(buffer, token.start_, ulength);
+    buffer[length] = 0;
+    fixNumericLocaleInput(buffer, buffer + length);
+    count = sscanf(buffer, format, &value);
+  }
+  else
+  {
+    JSONCPP_STRING buffer(token.start_, token.end_);
+    count = sscanf(buffer.c_str(), format, &value);
+  }
+
+  if (count != 1)
+    return addError("'" + JSONCPP_STRING(token.start_, token.end_) + "' is not a number.", token);
+  decoded = value;
+  return true;
+}
+
+bool OurReader::decodeString(Token &token)
+{
+  JSONCPP_STRING decoded_string;
+  if (!decodeString(token, decoded_string))
+    return false;
+  Value decoded(decoded_string);
+  currentValue().swapPayload(decoded);
+  currentValue().setOffsetStart(token.start_ - begin_);
+  currentValue().setOffsetLimit(token.end_ - begin_);
+  return true;
+}
+
+bool OurReader::decodeString(Token &token, JSONCPP_STRING &decoded)
+{
+  decoded.reserve(static_cast<size_t>(token.end_ - token.start_ - 2));
+  Location current = token.start_ + 1; // skip '"'
+  Location end = token.end_ - 1;       // do not include '"'
+  while (current != end)
+  {
+    Char c = *current++;
+    if (c == '"')
+      break;
+    else if (c == '\\')
+    {
+      if (current == end)
+        return addError("Empty escape sequence in string", token, current);
+      Char escape = *current++;
+      switch (escape)
+      {
+        case '"':
+          decoded += '"';
+          break;
+        case '/':
+          decoded += '/';
+          break;
+        case '\\':
+          decoded += '\\';
+          break;
+        case 'b':
+          decoded += '\b';
+          break;
+        case 'f':
+          decoded += '\f';
+          break;
+        case 'n':
+          decoded += '\n';
+          break;
+        case 'r':
+          decoded += '\r';
+          break;
+        case 't':
+          decoded += '\t';
+          break;
+        case 'u':
+        {
+          unsigned int unicode;
+          if (!decodeUnicodeCodePoint(token, current, end, unicode))
+            return false;
+          decoded += codePointToUTF8(unicode);
+        }
+        break;
+        default:
+          return addError("Bad escape sequence in string", token, current);
+      }
+    }
+    else
+    {
+      decoded += c;
+    }
+  }
+  return true;
+}
+
+bool OurReader::decodeUnicodeCodePoint(Token &token, Location &current, Location end,
+                                       unsigned int &unicode)
+{
+
+  if (!decodeUnicodeEscapeSequence(token, current, end, unicode))
+    return false;
+  if (unicode >= 0xD800 && unicode <= 0xDBFF)
+  {
+    // surrogate pairs
+    if (end - current < 6)
+      return addError("additional six characters expected to parse unicode surrogate pair.", token,
+                      current);
+    unsigned int surrogatePair;
+    if (*(current++) == '\\' && *(current++) == 'u')
+    {
+      if (decodeUnicodeEscapeSequence(token, current, end, surrogatePair))
+      {
+        unicode = 0x10000 + ((unicode & 0x3FF) << 10) + (surrogatePair & 0x3FF);
+      }
+      else
+        return false;
+    }
+    else
+      return addError("expecting another \\u token to begin the second half of "
+                      "a unicode surrogate pair",
+                      token, current);
+  }
+  return true;
+}
+
+bool OurReader::decodeUnicodeEscapeSequence(Token &token, Location &current, Location end,
+                                            unsigned int &ret_unicode)
+{
+  if (end - current < 4)
+    return addError("Bad unicode escape sequence in string: four digits expected.", token, current);
+  int unicode = 0;
+  for (int index = 0; index < 4; ++index)
+  {
+    Char c = *current++;
+    unicode *= 16;
+    if (c >= '0' && c <= '9')
+      unicode += c - '0';
+    else if (c >= 'a' && c <= 'f')
+      unicode += c - 'a' + 10;
+    else if (c >= 'A' && c <= 'F')
+      unicode += c - 'A' + 10;
+    else
+      return addError("Bad unicode escape sequence in string: hexadecimal digit expected.", token,
+                      current);
+  }
+  ret_unicode = static_cast<unsigned int>(unicode);
+  return true;
+}
+
+bool OurReader::addError(const JSONCPP_STRING &message, Token &token, Location extra)
+{
+  ErrorInfo info;
+  info.token_ = token;
+  info.message_ = message;
+  info.extra_ = extra;
+  errors_.push_back(info);
+  return false;
+}
+
+bool OurReader::recoverFromError(TokenType skipUntilToken)
+{
+  size_t errorCount = errors_.size();
+  Token skip;
+  for (;;)
+  {
+    if (!readToken(skip))
+      errors_.resize(errorCount); // discard errors caused by recovery
+    if (skip.type_ == skipUntilToken || skip.type_ == tokenEndOfStream)
+      break;
+  }
+  errors_.resize(errorCount);
+  return false;
+}
+
+bool OurReader::addErrorAndRecover(const JSONCPP_STRING &message, Token &token,
+                                   TokenType skipUntilToken)
+{
+  addError(message, token);
+  return recoverFromError(skipUntilToken);
+}
+
+Value &OurReader::currentValue() { return *(nodes_.top()); }
+
+OurReader::Char OurReader::getNextChar()
+{
+  if (current_ == end_)
+    return 0;
+  return *current_++;
+}
+
+void OurReader::getLocationLineAndColumn(Location location, int &line, int &column) const
+{
+  Location current = begin_;
+  Location lastLineStart = current;
+  line = 0;
+  while (current < location && current != end_)
+  {
+    Char c = *current++;
+    if (c == '\r')
+    {
+      if (*current == '\n')
+        ++current;
+      lastLineStart = current;
+      ++line;
+    }
+    else if (c == '\n')
+    {
+      lastLineStart = current;
+      ++line;
+    }
+  }
+  // column & line start at 1
+  column = int(location - lastLineStart) + 1;
+  ++line;
+}
+
+JSONCPP_STRING OurReader::getLocationLineAndColumn(Location location) const
+{
+  int line, column;
+  getLocationLineAndColumn(location, line, column);
+  char buffer[18 + 16 + 16 + 1];
+  snprintf(buffer, sizeof(buffer), "Line %d, Column %d", line, column);
+  return buffer;
+}
+
+JSONCPP_STRING OurReader::getFormattedErrorMessages() const
+{
+  JSONCPP_STRING formattedMessage;
+  for (Errors::const_iterator itError = errors_.begin(); itError != errors_.end(); ++itError)
+  {
+    const ErrorInfo &error = *itError;
+    formattedMessage += "* " + getLocationLineAndColumn(error.token_.start_) + "\n";
+    formattedMessage += "  " + error.message_ + "\n";
+    if (error.extra_)
+      formattedMessage += "See " + getLocationLineAndColumn(error.extra_) + " for detail.\n";
+  }
+  return formattedMessage;
+}
+
+std::vector<OurReader::StructuredError> OurReader::getStructuredErrors() const
+{
+  std::vector<OurReader::StructuredError> allErrors;
+  for (Errors::const_iterator itError = errors_.begin(); itError != errors_.end(); ++itError)
+  {
+    const ErrorInfo &error = *itError;
+    OurReader::StructuredError structured;
+    structured.offset_start = error.token_.start_ - begin_;
+    structured.offset_limit = error.token_.end_ - begin_;
+    structured.message = error.message_;
+    allErrors.push_back(structured);
+  }
+  return allErrors;
+}
+
+bool OurReader::pushError(const Value &value, const JSONCPP_STRING &message)
+{
+  ptrdiff_t length = end_ - begin_;
+  if (value.getOffsetStart() > length || value.getOffsetLimit() > length)
+    return false;
+  Token token;
+  token.type_ = tokenError;
+  token.start_ = begin_ + value.getOffsetStart();
+  token.end_ = end_ + value.getOffsetLimit();
+  ErrorInfo info;
+  info.token_ = token;
+  info.message_ = message;
+  info.extra_ = 0;
+  errors_.push_back(info);
+  return true;
+}
+
+bool OurReader::pushError(const Value &value, const JSONCPP_STRING &message, const Value &extra)
+{
+  ptrdiff_t length = end_ - begin_;
+  if (value.getOffsetStart() > length || value.getOffsetLimit() > length ||
+      extra.getOffsetLimit() > length)
+    return false;
+  Token token;
+  token.type_ = tokenError;
+  token.start_ = begin_ + value.getOffsetStart();
+  token.end_ = begin_ + value.getOffsetLimit();
+  ErrorInfo info;
+  info.token_ = token;
+  info.message_ = message;
+  info.extra_ = begin_ + extra.getOffsetStart();
+  errors_.push_back(info);
+  return true;
+}
+
+bool OurReader::good() const { return !errors_.size(); }
+
+class OurCharReader : public CharReader
+{
+  bool const collectComments_;
+  OurReader reader_;
+
+public:
+  OurCharReader(bool collectComments, OurFeatures const &features)
+      : collectComments_(collectComments), reader_(features)
+  {
+  }
+  bool parse(char const *beginDoc, char const *endDoc, Value *root,
+             JSONCPP_STRING *errs) JSONCPP_OVERRIDE
+  {
+    bool ok = reader_.parse(beginDoc, endDoc, *root, collectComments_);
+    if (errs)
+    {
+      *errs = reader_.getFormattedErrorMessages();
+    }
+    return ok;
+  }
+};
+
+CharReaderBuilder::CharReaderBuilder() { setDefaults(&settings_); }
+CharReaderBuilder::~CharReaderBuilder() {}
+CharReader *CharReaderBuilder::newCharReader() const
+{
+  bool collectComments = settings_["collectComments"].asBool();
+  OurFeatures features = OurFeatures::all();
+  features.allowComments_ = settings_["allowComments"].asBool();
+  features.strictRoot_ = settings_["strictRoot"].asBool();
+  features.allowDroppedNullPlaceholders_ = settings_["allowDroppedNullPlaceholders"].asBool();
+  features.allowNumericKeys_ = settings_["allowNumericKeys"].asBool();
+  features.allowSingleQuotes_ = settings_["allowSingleQuotes"].asBool();
+  features.stackLimit_ = settings_["stackLimit"].asInt();
+  features.failIfExtra_ = settings_["failIfExtra"].asBool();
+  features.rejectDupKeys_ = settings_["rejectDupKeys"].asBool();
+  features.allowSpecialFloats_ = settings_["allowSpecialFloats"].asBool();
+  return new OurCharReader(collectComments, features);
+}
+static void getValidReaderKeys(std::set<JSONCPP_STRING> *valid_keys)
+{
+  valid_keys->clear();
+  valid_keys->insert("collectComments");
+  valid_keys->insert("allowComments");
+  valid_keys->insert("strictRoot");
+  valid_keys->insert("allowDroppedNullPlaceholders");
+  valid_keys->insert("allowNumericKeys");
+  valid_keys->insert("allowSingleQuotes");
+  valid_keys->insert("stackLimit");
+  valid_keys->insert("failIfExtra");
+  valid_keys->insert("rejectDupKeys");
+  valid_keys->insert("allowSpecialFloats");
+}
+bool CharReaderBuilder::validate(Json::Value *invalid) const
+{
+  Json::Value my_invalid;
+  if (!invalid)
+    invalid = &my_invalid; // so we do not need to test for NULL
+  Json::Value &inv = *invalid;
+  std::set<JSONCPP_STRING> valid_keys;
+  getValidReaderKeys(&valid_keys);
+  Value::Members keys = settings_.getMemberNames();
+  size_t n = keys.size();
+  for (size_t i = 0; i < n; ++i)
+  {
+    JSONCPP_STRING const &key = keys[i];
+    if (valid_keys.find(key) == valid_keys.end())
+    {
+      inv[key] = settings_[key];
+    }
+  }
+  return 0u == inv.size();
+}
+Value &CharReaderBuilder::operator[](JSONCPP_STRING key) { return settings_[key]; }
+// static
+void CharReaderBuilder::strictMode(Json::Value *settings)
+{
+  //! [CharReaderBuilderStrictMode]
+  (*settings)["allowComments"] = false;
+  (*settings)["strictRoot"] = true;
+  (*settings)["allowDroppedNullPlaceholders"] = false;
+  (*settings)["allowNumericKeys"] = false;
+  (*settings)["allowSingleQuotes"] = false;
+  (*settings)["stackLimit"] = 1000;
+  (*settings)["failIfExtra"] = true;
+  (*settings)["rejectDupKeys"] = true;
+  (*settings)["allowSpecialFloats"] = false;
+  //! [CharReaderBuilderStrictMode]
+}
+// static
+void CharReaderBuilder::setDefaults(Json::Value *settings)
+{
+  //! [CharReaderBuilderDefaults]
+  (*settings)["collectComments"] = true;
+  (*settings)["allowComments"] = true;
+  (*settings)["strictRoot"] = false;
+  (*settings)["allowDroppedNullPlaceholders"] = false;
+  (*settings)["allowNumericKeys"] = false;
+  (*settings)["allowSingleQuotes"] = false;
+  (*settings)["stackLimit"] = 1000;
+  (*settings)["failIfExtra"] = false;
+  (*settings)["rejectDupKeys"] = false;
+  (*settings)["allowSpecialFloats"] = false;
+  //! [CharReaderBuilderDefaults]
+}
+
+//////////////////////////////////
+// global functions
+
+bool parseFromStream(CharReader::Factory const &fact, JSONCPP_ISTREAM &sin, Value *root,
+                     JSONCPP_STRING *errs)
+{
+  JSONCPP_OSTRINGSTREAM ssin;
+  ssin << sin.rdbuf();
+  JSONCPP_STRING doc = ssin.str();
+  char const *begin = doc.data();
+  char const *end = begin + doc.size();
+  // Note that we do not actually need a null-terminator.
+  CharReaderPtr const reader(fact.newCharReader());
+  return reader->parse(begin, end, root, errs);
+}
+
+JSONCPP_ISTREAM &operator>>(JSONCPP_ISTREAM &sin, Value &root)
+{
+  CharReaderBuilder b;
+  JSONCPP_STRING errs;
+  bool ok = parseFromStream(b, sin, &root, &errs);
+  if (!ok)
+  {
+    fprintf(stderr, "Error from reader: %s", errs.c_str());
+
+    throwRuntimeError(errs);
+  }
+  return sin;
+}
+
+} // namespace Json
+
+// //////////////////////////////////////////////////////////////////////
+// End of content of file: src/lib_json/json_reader.cpp
+// //////////////////////////////////////////////////////////////////////
+
+// //////////////////////////////////////////////////////////////////////
+// Beginning of content of file: src/lib_json/json_valueiterator.inl
+// //////////////////////////////////////////////////////////////////////
+
+// Copyright 2007-2010 Baptiste Lepilleur
+// Distributed under MIT license, or public domain if desired and
+// recognized in your jurisdiction.
+// See file LICENSE for detail or copy at http://jsoncpp.sourceforge.net/LICENSE
+
+// included by json_value.cpp
+
+namespace Json
+{
+
+// //////////////////////////////////////////////////////////////////
+// //////////////////////////////////////////////////////////////////
+// //////////////////////////////////////////////////////////////////
+// class ValueIteratorBase
+// //////////////////////////////////////////////////////////////////
+// //////////////////////////////////////////////////////////////////
+// //////////////////////////////////////////////////////////////////
+
+ValueIteratorBase::ValueIteratorBase() : current_(), isNull_(true) {}
+
+ValueIteratorBase::ValueIteratorBase(const Value::ObjectValues::iterator &current)
+    : current_(current), isNull_(false)
+{
+}
+
+Value &ValueIteratorBase::deref() const { return current_->second; }
+
+void ValueIteratorBase::increment() { ++current_; }
+
+void ValueIteratorBase::decrement() { --current_; }
+
+ValueIteratorBase::difference_type ValueIteratorBase::computeDistance(const SelfType &other) const
+{
+#ifdef JSON_USE_CPPTL_SMALLMAP
+  return other.current_ - current_;
+#else
+  // Iterator for null value are initialized using the default
+  // constructor, which initialize current_ to the default
+  // std::map::iterator. As begin() and end() are two instance
+  // of the default std::map::iterator, they can not be compared.
+  // To allow this, we handle this comparison specifically.
+  if (isNull_ && other.isNull_)
+  {
+    return 0;
+  }
+
+  // Usage of std::distance is not portable (does not compile with Sun Studio 12
+  // RogueWave STL,
+  // which is the one used by default).
+  // Using a portable hand-made version for non random iterator instead:
+  //   return difference_type( std::distance( current_, other.current_ ) );
+  difference_type myDistance = 0;
+  for (Value::ObjectValues::iterator it = current_; it != other.current_; ++it)
+  {
+    ++myDistance;
+  }
+  return myDistance;
+#endif
+}
+
+bool ValueIteratorBase::isEqual(const SelfType &other) const
+{
+  if (isNull_)
+  {
+    return other.isNull_;
+  }
+  return current_ == other.current_;
+}
+
+void ValueIteratorBase::copy(const SelfType &other)
+{
+  current_ = other.current_;
+  isNull_ = other.isNull_;
+}
+
+Value ValueIteratorBase::key() const
+{
+  const Value::CZString czstring = (*current_).first;
+  if (czstring.data())
+  {
+    if (czstring.isStaticString())
+      return Value(StaticString(czstring.data()));
+    return Value(czstring.data(), czstring.data() + czstring.length());
+  }
+  return Value(czstring.index());
+}
+
+UInt ValueIteratorBase::index() const
+{
+  const Value::CZString czstring = (*current_).first;
+  if (!czstring.data())
+    return czstring.index();
+  return Value::UInt(-1);
+}
+
+JSONCPP_STRING ValueIteratorBase::name() const
+{
+  char const *keey;
+  char const *end;
+  keey = memberName(&end);
+  if (!keey)
+    return JSONCPP_STRING();
+  return JSONCPP_STRING(keey, end);
+}
+
+char const *ValueIteratorBase::memberName() const
+{
+  const char *cname = (*current_).first.data();
+  return cname ? cname : "";
+}
+
+char const *ValueIteratorBase::memberName(char const **end) const
+{
+  const char *cname = (*current_).first.data();
+  if (!cname)
+  {
+    *end = NULL;
+    return NULL;
+  }
+  *end = cname + (*current_).first.length();
+  return cname;
+}
+
+// //////////////////////////////////////////////////////////////////
+// //////////////////////////////////////////////////////////////////
+// //////////////////////////////////////////////////////////////////
+// class ValueConstIterator
+// //////////////////////////////////////////////////////////////////
+// //////////////////////////////////////////////////////////////////
+// //////////////////////////////////////////////////////////////////
+
+ValueConstIterator::ValueConstIterator() {}
+
+ValueConstIterator::ValueConstIterator(const Value::ObjectValues::iterator &current)
+    : ValueIteratorBase(current)
+{
+}
+
+ValueConstIterator::ValueConstIterator(ValueIterator const &other) : ValueIteratorBase(other) {}
+
+ValueConstIterator &ValueConstIterator::operator=(const ValueIteratorBase &other)
+{
+  copy(other);
+  return *this;
+}
+
+// //////////////////////////////////////////////////////////////////
+// //////////////////////////////////////////////////////////////////
+// //////////////////////////////////////////////////////////////////
+// class ValueIterator
+// //////////////////////////////////////////////////////////////////
+// //////////////////////////////////////////////////////////////////
+// //////////////////////////////////////////////////////////////////
+
+ValueIterator::ValueIterator() {}
+
+ValueIterator::ValueIterator(const Value::ObjectValues::iterator &current)
+    : ValueIteratorBase(current)
+{
+}
+
+ValueIterator::ValueIterator(const ValueConstIterator &other) : ValueIteratorBase(other)
+{
+  throwRuntimeError("ConstIterator to Iterator should never be allowed.");
+}
+
+ValueIterator::ValueIterator(const ValueIterator &other) : ValueIteratorBase(other) {}
+
+ValueIterator &ValueIterator::operator=(const SelfType &other)
+{
+  copy(other);
+  return *this;
+}
+
+} // namespace Json
+
+// //////////////////////////////////////////////////////////////////////
+// End of content of file: src/lib_json/json_valueiterator.inl
+// //////////////////////////////////////////////////////////////////////
+
+// //////////////////////////////////////////////////////////////////////
+// Beginning of content of file: src/lib_json/json_value.cpp
+// //////////////////////////////////////////////////////////////////////
+
+// Copyright 2011 Baptiste Lepilleur
+// Distributed under MIT license, or public domain if desired and
+// recognized in your jurisdiction.
+// See file LICENSE for detail or copy at http://jsoncpp.sourceforge.net/LICENSE
+
+#if !defined(JSON_IS_AMALGAMATION)
+#include <json/assertions.h>
+#include <json/value.h>
+#include <json/writer.h>
+#endif // if !defined(JSON_IS_AMALGAMATION)
+#include <math.h>
+#include <sstream>
+#include <utility>
+#include <cstring>
+#include <cassert>
+#ifdef JSON_USE_CPPTL
+#include <cpptl/conststring.h>
+#endif
+#include <cstddef>   // size_t
+#include <algorithm> // min()
+
+#define JSON_ASSERT_UNREACHABLE assert(false)
+
+namespace Json
+{
+
+// This is a walkaround to avoid the static initialization of Value::null.
+// kNull must be word-aligned to avoid crashing on ARM.  We use an alignment of
+// 8 (instead of 4) as a bit of future-proofing.
+#if defined(__ARMEL__)
+#define ALIGNAS(byte_alignment) __attribute__((aligned(byte_alignment)))
+#else
+#define ALIGNAS(byte_alignment)
+#endif
+// static const unsigned char ALIGNAS(8) kNull[sizeof(Value)] = { 0 };
+// const unsigned char& kNullRef = kNull[0];
+// const Value& Value::null = reinterpret_cast<const Value&>(kNullRef);
+// const Value& Value::nullRef = null;
+
+// static
+Value const &Value::nullSingleton()
+{
+  static Value const nullStatic;
+  return nullStatic;
+}
+
+// for backwards compatibility, we'll leave these global references around, but DO NOT
+// use them in JSONCPP library code any more!
+Value const &Value::null = Value::nullSingleton();
+Value const &Value::nullRef = Value::nullSingleton();
+
+const Int Value::minInt = Int(~(UInt(-1) / 2));
+const Int Value::maxInt = Int(UInt(-1) / 2);
+const UInt Value::maxUInt = UInt(-1);
+#if defined(JSON_HAS_INT64)
+const Int64 Value::minInt64 = Int64(~(UInt64(-1) / 2));
+const Int64 Value::maxInt64 = Int64(UInt64(-1) / 2);
+const UInt64 Value::maxUInt64 = UInt64(-1);
+// The constant is hard-coded because some compiler have trouble
+// converting Value::maxUInt64 to a double correctly (AIX/xlC).
+// Assumes that UInt64 is a 64 bits integer.
+static const double maxUInt64AsDouble = 18446744073709551615.0;
+#endif // defined(JSON_HAS_INT64)
+const LargestInt Value::minLargestInt = LargestInt(~(LargestUInt(-1) / 2));
+const LargestInt Value::maxLargestInt = LargestInt(LargestUInt(-1) / 2);
+const LargestUInt Value::maxLargestUInt = LargestUInt(-1);
+
+#if !defined(JSON_USE_INT64_DOUBLE_CONVERSION)
+template <typename T, typename U> static inline bool InRange(double d, T min, U max)
+{
+  // The casts can lose precision, but we are looking only for
+  // an approximate range. Might fail on edge cases though. ~cdunn
+  // return d >= static_cast<double>(min) && d <= static_cast<double>(max);
+  return d >= min && d <= max;
+}
+#else  // if !defined(JSON_USE_INT64_DOUBLE_CONVERSION)
+static inline double integerToDouble(Json::UInt64 value)
+{
+  return static_cast<double>(Int64(value / 2)) * 2.0 + static_cast<double>(Int64(value & 1));
+}
+
+template <typename T> static inline double integerToDouble(T value)
+{
+  return static_cast<double>(value);
+}
+
+template <typename T, typename U> static inline bool InRange(double d, T min, U max)
+{
+  return d >= integerToDouble(min) && d <= integerToDouble(max);
+}
+#endif // if !defined(JSON_USE_INT64_DOUBLE_CONVERSION)
+
+/** Duplicates the specified string value.
+ * @param value Pointer to the string to duplicate. Must be zero-terminated if
+ *              length is "unknown".
+ * @param length Length of the value. if equals to unknown, then it will be
+ *               computed using strlen(value).
+ * @return Pointer on the duplicate instance of string.
+ */
+static inline char *duplicateStringValue(const char *value, size_t length)
+{
+  // Avoid an integer overflow in the call to malloc below by limiting length
+  // to a sane value.
+  if (length >= static_cast<size_t>(Value::maxInt))
+    length = Value::maxInt - 1;
+
+  char *newString = static_cast<char *>(malloc(length + 1));
+  if (newString == NULL)
+  {
+    throwRuntimeError("in Json::Value::duplicateStringValue(): "
+                      "Failed to allocate string value buffer");
+  }
+  memcpy(newString, value, length);
+  newString[length] = 0;
+  return newString;
+}
+
+/* Record the length as a prefix.
+ */
+static inline char *duplicateAndPrefixStringValue(const char *value, unsigned int length)
+{
+  // Avoid an integer overflow in the call to malloc below by limiting length
+  // to a sane value.
+  JSON_ASSERT_MESSAGE(length <= static_cast<unsigned>(Value::maxInt) - sizeof(unsigned) - 1U,
+                      "in Json::Value::duplicateAndPrefixStringValue(): "
+                      "length too big for prefixing");
+  unsigned actualLength = length + static_cast<unsigned>(sizeof(unsigned)) + 1U;
+  char *newString = static_cast<char *>(malloc(actualLength));
+  if (newString == 0)
+  {
+    throwRuntimeError("in Json::Value::duplicateAndPrefixStringValue(): "
+                      "Failed to allocate string value buffer");
+  }
+  *reinterpret_cast<unsigned *>(newString) = length;
+  memcpy(newString + sizeof(unsigned), value, length);
+  newString[actualLength - 1U] = 0; // to avoid buffer over-run accidents by users later
+  return newString;
+}
+inline static void decodePrefixedString(bool isPrefixed, char const *prefixed, unsigned *length,
+                                        char const **value)
+{
+  if (!isPrefixed)
+  {
+    *length = static_cast<unsigned>(strlen(prefixed));
+    *value = prefixed;
+  }
+  else
+  {
+    *length = *reinterpret_cast<unsigned const *>(prefixed);
+    *value = prefixed + sizeof(unsigned);
+  }
+}
+/** Free the string duplicated by duplicateStringValue()/duplicateAndPrefixStringValue().
+ */
+#if JSONCPP_USING_SECURE_MEMORY
+static inline void releasePrefixedStringValue(char *value)
+{
+  unsigned length = 0;
+  char const *valueDecoded;
+  decodePrefixedString(true, value, &length, &valueDecoded);
+  size_t const size = sizeof(unsigned) + length + 1U;
+  memset(value, 0, size);
+  free(value);
+}
+static inline void releaseStringValue(char *value, unsigned length)
+{
+  // length==0 => we allocated the strings memory
+  size_t size = (length == 0) ? strlen(value) : length;
+  memset(value, 0, size);
+  free(value);
+}
+#else  // !JSONCPP_USING_SECURE_MEMORY
+static inline void releasePrefixedStringValue(char *value) { free(value); }
+static inline void releaseStringValue(char *value, unsigned) { free(value); }
+#endif // JSONCPP_USING_SECURE_MEMORY
+
+} // namespace Json
+
+// //////////////////////////////////////////////////////////////////
+// //////////////////////////////////////////////////////////////////
+// //////////////////////////////////////////////////////////////////
+// ValueInternals...
+// //////////////////////////////////////////////////////////////////
+// //////////////////////////////////////////////////////////////////
+// //////////////////////////////////////////////////////////////////
+#if !defined(JSON_IS_AMALGAMATION)
+
+#include "json_valueiterator.inl"
+#endif // if !defined(JSON_IS_AMALGAMATION)
+
+namespace Json
+{
+
+Exception::Exception(JSONCPP_STRING const &msg) : msg_(msg) {}
+Exception::~Exception() throw() {}
+char const *Exception::what() const throw() { return msg_.c_str(); }
+RuntimeError::RuntimeError(JSONCPP_STRING const &msg) : Exception(msg) {}
+LogicError::LogicError(JSONCPP_STRING const &msg) : Exception(msg) {}
+JSONCPP_NORETURN void throwRuntimeError(JSONCPP_STRING const &msg) { throw RuntimeError(msg); }
+JSONCPP_NORETURN void throwLogicError(JSONCPP_STRING const &msg) { throw LogicError(msg); }
+
+// //////////////////////////////////////////////////////////////////
+// //////////////////////////////////////////////////////////////////
+// //////////////////////////////////////////////////////////////////
+// class Value::CommentInfo
+// //////////////////////////////////////////////////////////////////
+// //////////////////////////////////////////////////////////////////
+// //////////////////////////////////////////////////////////////////
+
+Value::CommentInfo::CommentInfo() : comment_(0) {}
+
+Value::CommentInfo::~CommentInfo()
+{
+  if (comment_)
+    releaseStringValue(comment_, 0u);
+}
+
+void Value::CommentInfo::setComment(const char *text, size_t len)
+{
+  if (comment_)
+  {
+    releaseStringValue(comment_, 0u);
+    comment_ = 0;
+  }
+  JSON_ASSERT(text != 0);
+  JSON_ASSERT_MESSAGE(text[0] == '\0' || text[0] == '/',
+                      "in Json::Value::setComment(): Comments must start with /");
+  // It seems that /**/ style comments are acceptable as well.
+  comment_ = duplicateStringValue(text, len);
+}
+
+// //////////////////////////////////////////////////////////////////
+// //////////////////////////////////////////////////////////////////
+// //////////////////////////////////////////////////////////////////
+// class Value::CZString
+// //////////////////////////////////////////////////////////////////
+// //////////////////////////////////////////////////////////////////
+// //////////////////////////////////////////////////////////////////
+
+// Notes: policy_ indicates if the string was allocated when
+// a string is stored.
+
+Value::CZString::CZString(ArrayIndex aindex) : cstr_(0), index_(aindex) {}
+
+Value::CZString::CZString(char const *str, unsigned ulength, DuplicationPolicy allocate)
+    : cstr_(str)
+{
+  // allocate != duplicate
+  storage_.policy_ = allocate & 0x3;
+  storage_.length_ = ulength & 0x3FFFFFFF;
+}
+
+Value::CZString::CZString(const CZString &other)
+{
+  cstr_ = (other.storage_.policy_ != noDuplication && other.cstr_ != 0
+               ? duplicateStringValue(other.cstr_, other.storage_.length_)
+               : other.cstr_);
+  storage_.policy_ =
+      static_cast<unsigned>(
+          other.cstr_ ? (static_cast<DuplicationPolicy>(other.storage_.policy_) == noDuplication
+                             ? noDuplication
+                             : duplicate)
+                      : static_cast<DuplicationPolicy>(other.storage_.policy_)) &
+      3U;
+  storage_.length_ = other.storage_.length_;
+}
+
+#if JSON_HAS_RVALUE_REFERENCES
+Value::CZString::CZString(CZString &&other) : cstr_(other.cstr_), index_(other.index_)
+{
+  other.cstr_ = nullptr;
+}
+#endif
+
+Value::CZString::~CZString()
+{
+  if (cstr_ && storage_.policy_ == duplicate)
+  {
+    releaseStringValue(const_cast<char *>(cstr_), storage_.length_ + 1u); //+1 for null terminating
+                                                                          // character for sake of
+    // completeness but not
+    // actually necessary
+  }
+}
+
+void Value::CZString::swap(CZString &other)
+{
+  std::swap(cstr_, other.cstr_);
+  std::swap(index_, other.index_);
+}
+
+Value::CZString &Value::CZString::operator=(CZString other)
+{
+  swap(other);
+  return *this;
+}
+
+bool Value::CZString::operator<(const CZString &other) const
+{
+  if (!cstr_)
+    return index_ < other.index_;
+  // return strcmp(cstr_, other.cstr_) < 0;
+  // Assume both are strings.
+  unsigned this_len = this->storage_.length_;
+  unsigned other_len = other.storage_.length_;
+  unsigned min_len = std::min(this_len, other_len);
+  JSON_ASSERT(this->cstr_ && other.cstr_);
+  int comp = memcmp(this->cstr_, other.cstr_, min_len);
+  if (comp < 0)
+    return true;
+  if (comp > 0)
+    return false;
+  return (this_len < other_len);
+}
+
+bool Value::CZString::operator==(const CZString &other) const
+{
+  if (!cstr_)
+    return index_ == other.index_;
+  // return strcmp(cstr_, other.cstr_) == 0;
+  // Assume both are strings.
+  unsigned this_len = this->storage_.length_;
+  unsigned other_len = other.storage_.length_;
+  if (this_len != other_len)
+    return false;
+  JSON_ASSERT(this->cstr_ && other.cstr_);
+  int comp = memcmp(this->cstr_, other.cstr_, this_len);
+  return comp == 0;
+}
+
+ArrayIndex Value::CZString::index() const { return index_; }
+
+// const char* Value::CZString::c_str() const { return cstr_; }
+const char *Value::CZString::data() const { return cstr_; }
+unsigned Value::CZString::length() const { return storage_.length_; }
+bool Value::CZString::isStaticString() const { return storage_.policy_ == noDuplication; }
+
+// //////////////////////////////////////////////////////////////////
+// //////////////////////////////////////////////////////////////////
+// //////////////////////////////////////////////////////////////////
+// class Value::Value
+// //////////////////////////////////////////////////////////////////
+// //////////////////////////////////////////////////////////////////
+// //////////////////////////////////////////////////////////////////
+
+/*! \internal Default constructor initialization must be equivalent to:
+ * memset( this, 0, sizeof(Value) )
+ * This optimization is used in ValueInternalMap fast allocator.
+ */
+Value::Value(ValueType vtype)
+{
+  static char const empty[] = "";
+  initBasic(vtype);
+  switch (vtype)
+  {
+    case nullValue:
+      break;
+    case intValue:
+    case uintValue:
+      value_.int_ = 0;
+      break;
+    case realValue:
+      value_.real_ = 0.0;
+      break;
+    case stringValue:
+      // allocated_ == false, so this is safe.
+      value_.string_ = const_cast<char *>(static_cast<char const *>(empty));
+      break;
+    case arrayValue:
+    case objectValue:
+      value_.map_ = new ObjectValues();
+      break;
+    case booleanValue:
+      value_.bool_ = false;
+      break;
+    default:
+      JSON_ASSERT_UNREACHABLE;
+  }
+}
+
+Value::Value(Int value)
+{
+  initBasic(intValue);
+  value_.int_ = value;
+}
+
+Value::Value(UInt value)
+{
+  initBasic(uintValue);
+  value_.uint_ = value;
+}
+#if defined(JSON_HAS_INT64)
+Value::Value(Int64 value)
+{
+  initBasic(intValue);
+  value_.int_ = value;
+}
+Value::Value(UInt64 value)
+{
+  initBasic(uintValue);
+  value_.uint_ = value;
+}
+#endif // defined(JSON_HAS_INT64)
+
+Value::Value(double value)
+{
+  initBasic(realValue);
+  value_.real_ = value;
+}
+
+Value::Value(const char *value)
+{
+  initBasic(stringValue, true);
+  value_.string_ = duplicateAndPrefixStringValue(value, static_cast<unsigned>(strlen(value)));
+}
+
+Value::Value(const char *beginValue, const char *endValue)
+{
+  initBasic(stringValue, true);
+  value_.string_ =
+      duplicateAndPrefixStringValue(beginValue, static_cast<unsigned>(endValue - beginValue));
+}
+
+Value::Value(const JSONCPP_STRING &value)
+{
+  initBasic(stringValue, true);
+  value_.string_ =
+      duplicateAndPrefixStringValue(value.data(), static_cast<unsigned>(value.length()));
+}
+
+Value::Value(const StaticString &value)
+{
+  initBasic(stringValue);
+  value_.string_ = const_cast<char *>(value.c_str());
+}
+
+#ifdef JSON_USE_CPPTL
+Value::Value(const CppTL::ConstString &value)
+{
+  initBasic(stringValue, true);
+  value_.string_ = duplicateAndPrefixStringValue(value, static_cast<unsigned>(value.length()));
+}
+#endif
+
+Value::Value(bool value)
+{
+  initBasic(booleanValue);
+  value_.bool_ = value;
+}
+
+Value::Value(Value const &other)
+    : type_(other.type_), allocated_(false), comments_(0), start_(other.start_),
+      limit_(other.limit_)
+{
+  switch (type_)
+  {
+    case nullValue:
+    case intValue:
+    case uintValue:
+    case realValue:
+    case booleanValue:
+      value_ = other.value_;
+      break;
+    case stringValue:
+      if (other.value_.string_ && other.allocated_)
+      {
+        unsigned len;
+        char const *str;
+        decodePrefixedString(other.allocated_, other.value_.string_, &len, &str);
+        value_.string_ = duplicateAndPrefixStringValue(str, len);
+        allocated_ = true;
+      }
+      else
+      {
+        value_.string_ = other.value_.string_;
+        allocated_ = false;
+      }
+      break;
+    case arrayValue:
+    case objectValue:
+      value_.map_ = new ObjectValues(*other.value_.map_);
+      break;
+    default:
+      JSON_ASSERT_UNREACHABLE;
+  }
+  if (other.comments_)
+  {
+    comments_ = new CommentInfo[numberOfCommentPlacement];
+    for (int comment = 0; comment < numberOfCommentPlacement; ++comment)
+    {
+      const CommentInfo &otherComment = other.comments_[comment];
+      if (otherComment.comment_)
+        comments_[comment].setComment(otherComment.comment_, strlen(otherComment.comment_));
+    }
+  }
+}
+
+#if JSON_HAS_RVALUE_REFERENCES
+// Move constructor
+Value::Value(Value &&other)
+{
+  initBasic(nullValue);
+  swap(other);
+}
+#endif
+
+Value::~Value()
+{
+  switch (type_)
+  {
+    case nullValue:
+    case intValue:
+    case uintValue:
+    case realValue:
+    case booleanValue:
+      break;
+    case stringValue:
+      if (allocated_)
+        releasePrefixedStringValue(value_.string_);
+      break;
+    case arrayValue:
+    case objectValue:
+      delete value_.map_;
+      break;
+    default:
+      JSON_ASSERT_UNREACHABLE;
+  }
+
+  delete[] comments_;
+
+  value_.uint_ = 0;
+}
+
+Value &Value::operator=(Value other)
+{
+  swap(other);
+  return *this;
+}
+
+void Value::swapPayload(Value &other)
+{
+  ValueType temp = type_;
+  type_ = other.type_;
+  other.type_ = temp;
+  std::swap(value_, other.value_);
+  int temp2 = allocated_;
+  allocated_ = other.allocated_;
+  other.allocated_ = temp2 & 0x1;
+}
+
+void Value::swap(Value &other)
+{
+  swapPayload(other);
+  std::swap(comments_, other.comments_);
+  std::swap(start_, other.start_);
+  std::swap(limit_, other.limit_);
+}
+
+ValueType Value::type() const { return type_; }
+
+int Value::compare(const Value &other) const
+{
+  if (*this < other)
+    return -1;
+  if (*this > other)
+    return 1;
+  return 0;
+}
+
+bool Value::operator<(const Value &other) const
+{
+  int typeDelta = type_ - other.type_;
+  if (typeDelta)
+    return typeDelta < 0 ? true : false;
+  switch (type_)
+  {
+    case nullValue:
+      return false;
+    case intValue:
+      return value_.int_ < other.value_.int_;
+    case uintValue:
+      return value_.uint_ < other.value_.uint_;
+    case realValue:
+      return value_.real_ < other.value_.real_;
+    case booleanValue:
+      return value_.bool_ < other.value_.bool_;
+    case stringValue:
+    {
+      if ((value_.string_ == 0) || (other.value_.string_ == 0))
+      {
+        if (other.value_.string_)
+          return true;
+        else
+          return false;
+      }
+      unsigned this_len;
+      unsigned other_len;
+      char const *this_str;
+      char const *other_str;
+      decodePrefixedString(this->allocated_, this->value_.string_, &this_len, &this_str);
+      decodePrefixedString(other.allocated_, other.value_.string_, &other_len, &other_str);
+      unsigned min_len = std::min(this_len, other_len);
+      JSON_ASSERT(this_str && other_str);
+      int comp = memcmp(this_str, other_str, min_len);
+      if (comp < 0)
+        return true;
+      if (comp > 0)
+        return false;
+      return (this_len < other_len);
+    }
+    case arrayValue:
+    case objectValue:
+    {
+      int delta = int(value_.map_->size() - other.value_.map_->size());
+      if (delta)
+        return delta < 0;
+      return (*value_.map_) < (*other.value_.map_);
+    }
+    default:
+      JSON_ASSERT_UNREACHABLE;
+  }
+  return false; // unreachable
+}
+
+bool Value::operator<=(const Value &other) const { return !(other < *this); }
+
+bool Value::operator>=(const Value &other) const { return !(*this < other); }
+
+bool Value::operator>(const Value &other) const { return other < *this; }
+
+bool Value::operator==(const Value &other) const
+{
+  // if ( type_ != other.type_ )
+  // GCC 2.95.3 says:
+  // attempt to take address of bit-field structure member `Json::Value::type_'
+  // Beats me, but a temp solves the problem.
+  int temp = other.type_;
+  if (type_ != temp)
+    return false;
+  switch (type_)
+  {
+    case nullValue:
+      return true;
+    case intValue:
+      return value_.int_ == other.value_.int_;
+    case uintValue:
+      return value_.uint_ == other.value_.uint_;
+    case realValue:
+      return value_.real_ == other.value_.real_;
+    case booleanValue:
+      return value_.bool_ == other.value_.bool_;
+    case stringValue:
+    {
+      if ((value_.string_ == 0) || (other.value_.string_ == 0))
+      {
+        return (value_.string_ == other.value_.string_);
+      }
+      unsigned this_len;
+      unsigned other_len;
+      char const *this_str;
+      char const *other_str;
+      decodePrefixedString(this->allocated_, this->value_.string_, &this_len, &this_str);
+      decodePrefixedString(other.allocated_, other.value_.string_, &other_len, &other_str);
+      if (this_len != other_len)
+        return false;
+      JSON_ASSERT(this_str && other_str);
+      int comp = memcmp(this_str, other_str, this_len);
+      return comp == 0;
+    }
+    case arrayValue:
+    case objectValue:
+      return value_.map_->size() == other.value_.map_->size() &&
+             (*value_.map_) == (*other.value_.map_);
+    default:
+      JSON_ASSERT_UNREACHABLE;
+  }
+  return false; // unreachable
+}
+
+bool Value::operator!=(const Value &other) const { return !(*this == other); }
+
+const char *Value::asCString() const
+{
+  JSON_ASSERT_MESSAGE(type_ == stringValue, "in Json::Value::asCString(): requires stringValue");
+  if (value_.string_ == 0)
+    return 0;
+  unsigned this_len;
+  char const *this_str;
+  decodePrefixedString(this->allocated_, this->value_.string_, &this_len, &this_str);
+  return this_str;
+}
+
+#if JSONCPP_USING_SECURE_MEMORY
+unsigned Value::getCStringLength() const
+{
+  JSON_ASSERT_MESSAGE(type_ == stringValue, "in Json::Value::asCString(): requires stringValue");
+  if (value_.string_ == 0)
+    return 0;
+  unsigned this_len;
+  char const *this_str;
+  decodePrefixedString(this->allocated_, this->value_.string_, &this_len, &this_str);
+  return this_len;
+}
+#endif
+
+bool Value::getString(char const **str, char const **cend) const
+{
+  if (type_ != stringValue)
+    return false;
+  if (value_.string_ == 0)
+    return false;
+  unsigned length;
+  decodePrefixedString(this->allocated_, this->value_.string_, &length, str);
+  *cend = *str + length;
+  return true;
+}
+
+JSONCPP_STRING Value::asString() const
+{
+  switch (type_)
+  {
+    case nullValue:
+      return "";
+    case stringValue:
+    {
+      if (value_.string_ == 0)
+        return "";
+      unsigned this_len;
+      char const *this_str;
+      decodePrefixedString(this->allocated_, this->value_.string_, &this_len, &this_str);
+      return JSONCPP_STRING(this_str, this_len);
+    }
+    case booleanValue:
+      return value_.bool_ ? "true" : "false";
+    case intValue:
+      return valueToString(value_.int_);
+    case uintValue:
+      return valueToString(value_.uint_);
+    case realValue:
+      return valueToString(value_.real_);
+    default:
+      JSON_FAIL_MESSAGE("Type is not convertible to string");
+  }
+}
+
+#ifdef JSON_USE_CPPTL
+CppTL::ConstString Value::asConstString() const
+{
+  unsigned len;
+  char const *str;
+  decodePrefixedString(allocated_, value_.string_, &len, &str);
+  return CppTL::ConstString(str, len);
+}
+#endif
+
+Value::Int Value::asInt() const
+{
+  switch (type_)
+  {
+    case intValue:
+      JSON_ASSERT_MESSAGE(isInt(), "LargestInt out of Int range");
+      return Int(value_.int_);
+    case uintValue:
+      JSON_ASSERT_MESSAGE(isInt(), "LargestUInt out of Int range");
+      return Int(value_.uint_);
+    case realValue:
+      JSON_ASSERT_MESSAGE(InRange(value_.real_, minInt, maxInt), "double out of Int range");
+      return Int(value_.real_);
+    case nullValue:
+      return 0;
+    case booleanValue:
+      return value_.bool_ ? 1 : 0;
+    default:
+      break;
+  }
+  JSON_FAIL_MESSAGE("Value is not convertible to Int.");
+}
+
+Value::UInt Value::asUInt() const
+{
+  switch (type_)
+  {
+    case intValue:
+      JSON_ASSERT_MESSAGE(isUInt(), "LargestInt out of UInt range");
+      return UInt(value_.int_);
+    case uintValue:
+      JSON_ASSERT_MESSAGE(isUInt(), "LargestUInt out of UInt range");
+      return UInt(value_.uint_);
+    case realValue:
+      JSON_ASSERT_MESSAGE(InRange(value_.real_, 0, maxUInt), "double out of UInt range");
+      return UInt(value_.real_);
+    case nullValue:
+      return 0;
+    case booleanValue:
+      return value_.bool_ ? 1 : 0;
+    default:
+      break;
+  }
+  JSON_FAIL_MESSAGE("Value is not convertible to UInt.");
+}
+
+#if defined(JSON_HAS_INT64)
+
+Value::Int64 Value::asInt64() const
+{
+  switch (type_)
+  {
+    case intValue:
+      return Int64(value_.int_);
+    case uintValue:
+      JSON_ASSERT_MESSAGE(isInt64(), "LargestUInt out of Int64 range");
+      return Int64(value_.uint_);
+    case realValue:
+      JSON_ASSERT_MESSAGE(InRange(value_.real_, minInt64, maxInt64), "double out of Int64 range");
+      return Int64(value_.real_);
+    case nullValue:
+      return 0;
+    case booleanValue:
+      return value_.bool_ ? 1 : 0;
+    default:
+      break;
+  }
+  JSON_FAIL_MESSAGE("Value is not convertible to Int64.");
+}
+
+Value::UInt64 Value::asUInt64() const
+{
+  switch (type_)
+  {
+    case intValue:
+      JSON_ASSERT_MESSAGE(isUInt64(), "LargestInt out of UInt64 range");
+      return UInt64(value_.int_);
+    case uintValue:
+      return UInt64(value_.uint_);
+    case realValue:
+      JSON_ASSERT_MESSAGE(InRange(value_.real_, 0, maxUInt64), "double out of UInt64 range");
+      return UInt64(value_.real_);
+    case nullValue:
+      return 0;
+    case booleanValue:
+      return value_.bool_ ? 1 : 0;
+    default:
+      break;
+  }
+  JSON_FAIL_MESSAGE("Value is not convertible to UInt64.");
+}
+#endif // if defined(JSON_HAS_INT64)
+
+LargestInt Value::asLargestInt() const
+{
+#if defined(JSON_NO_INT64)
+  return asInt();
+#else
+  return asInt64();
+#endif
+}
+
+LargestUInt Value::asLargestUInt() const
+{
+#if defined(JSON_NO_INT64)
+  return asUInt();
+#else
+  return asUInt64();
+#endif
+}
+
+double Value::asDouble() const
+{
+  switch (type_)
+  {
+    case intValue:
+      return static_cast<double>(value_.int_);
+    case uintValue:
+#if !defined(JSON_USE_INT64_DOUBLE_CONVERSION)
+      return static_cast<double>(value_.uint_);
+#else  // if !defined(JSON_USE_INT64_DOUBLE_CONVERSION)
+      return integerToDouble(value_.uint_);
+#endif // if !defined(JSON_USE_INT64_DOUBLE_CONVERSION)
+    case realValue:
+      return value_.real_;
+    case nullValue:
+      return 0.0;
+    case booleanValue:
+      return value_.bool_ ? 1.0 : 0.0;
+    default:
+      break;
+  }
+  JSON_FAIL_MESSAGE("Value is not convertible to double.");
+}
+
+float Value::asFloat() const
+{
+  switch (type_)
+  {
+    case intValue:
+      return static_cast<float>(value_.int_);
+    case uintValue:
+#if !defined(JSON_USE_INT64_DOUBLE_CONVERSION)
+      return static_cast<float>(value_.uint_);
+#else  // if !defined(JSON_USE_INT64_DOUBLE_CONVERSION)
+      // This can fail (silently?) if the value is bigger than MAX_FLOAT.
+      return static_cast<float>(integerToDouble(value_.uint_));
+#endif // if !defined(JSON_USE_INT64_DOUBLE_CONVERSION)
+    case realValue:
+      return static_cast<float>(value_.real_);
+    case nullValue:
+      return 0.0;
+    case booleanValue:
+      return value_.bool_ ? 1.0f : 0.0f;
+    default:
+      break;
+  }
+  JSON_FAIL_MESSAGE("Value is not convertible to float.");
+}
+
+bool Value::asBool() const
+{
+  switch (type_)
+  {
+    case booleanValue:
+      return value_.bool_;
+    case nullValue:
+      return false;
+    case intValue:
+      return value_.int_ ? true : false;
+    case uintValue:
+      return value_.uint_ ? true : false;
+    case realValue:
+      // This is kind of strange. Not recommended.
+      return (value_.real_ != 0.0) ? true : false;
+    default:
+      break;
+  }
+  JSON_FAIL_MESSAGE("Value is not convertible to bool.");
+}
+
+bool Value::isConvertibleTo(ValueType other) const
+{
+  switch (other)
+  {
+    case nullValue:
+      return (isNumeric() && asDouble() == 0.0) ||
+             (type_ == booleanValue && value_.bool_ == false) ||
+             (type_ == stringValue && asString() == "") ||
+             (type_ == arrayValue && value_.map_->size() == 0) ||
+             (type_ == objectValue && value_.map_->size() == 0) || type_ == nullValue;
+    case intValue:
+      return isInt() || (type_ == realValue && InRange(value_.real_, minInt, maxInt)) ||
+             type_ == booleanValue || type_ == nullValue;
+    case uintValue:
+      return isUInt() || (type_ == realValue && InRange(value_.real_, 0, maxUInt)) ||
+             type_ == booleanValue || type_ == nullValue;
+    case realValue:
+      return isNumeric() || type_ == booleanValue || type_ == nullValue;
+    case booleanValue:
+      return isNumeric() || type_ == booleanValue || type_ == nullValue;
+    case stringValue:
+      return isNumeric() || type_ == booleanValue || type_ == stringValue || type_ == nullValue;
+    case arrayValue:
+      return type_ == arrayValue || type_ == nullValue;
+    case objectValue:
+      return type_ == objectValue || type_ == nullValue;
+  }
+  JSON_ASSERT_UNREACHABLE;
+  return false;
+}
+
+/// Number of values in array or object
+ArrayIndex Value::size() const
+{
+  switch (type_)
+  {
+    case nullValue:
+    case intValue:
+    case uintValue:
+    case realValue:
+    case booleanValue:
+    case stringValue:
+      return 0;
+    case arrayValue: // size of the array is highest index + 1
+      if (!value_.map_->empty())
+      {
+        ObjectValues::const_iterator itLast = value_.map_->end();
+        --itLast;
+        return (*itLast).first.index() + 1;
+      }
+      return 0;
+    case objectValue:
+      return ArrayIndex(value_.map_->size());
+  }
+  JSON_ASSERT_UNREACHABLE;
+  return 0; // unreachable;
+}
+
+bool Value::empty() const
+{
+  if (isNull() || isArray() || isObject())
+    return size() == 0u;
+  else
+    return false;
+}
+
+bool Value::operator!() const { return isNull(); }
+
+void Value::clear()
+{
+  JSON_ASSERT_MESSAGE(type_ == nullValue || type_ == arrayValue || type_ == objectValue,
+                      "in Json::Value::clear(): requires complex value");
+  start_ = 0;
+  limit_ = 0;
+  switch (type_)
+  {
+    case arrayValue:
+    case objectValue:
+      value_.map_->clear();
+      break;
+    default:
+      break;
+  }
+}
+
+void Value::resize(ArrayIndex newSize)
+{
+  JSON_ASSERT_MESSAGE(type_ == nullValue || type_ == arrayValue,
+                      "in Json::Value::resize(): requires arrayValue");
+  if (type_ == nullValue)
+    *this = Value(arrayValue);
+  ArrayIndex oldSize = size();
+  if (newSize == 0)
+    clear();
+  else if (newSize > oldSize)
+    (*this)[newSize - 1];
+  else
+  {
+    for (ArrayIndex index = newSize; index < oldSize; ++index)
+    {
+      value_.map_->erase(index);
+    }
+    JSON_ASSERT(size() == newSize);
+  }
+}
+
+Value &Value::operator[](ArrayIndex index)
+{
+  JSON_ASSERT_MESSAGE(type_ == nullValue || type_ == arrayValue,
+                      "in Json::Value::operator[](ArrayIndex): requires arrayValue");
+  if (type_ == nullValue)
+    *this = Value(arrayValue);
+  CZString key(index);
+  ObjectValues::iterator it = value_.map_->lower_bound(key);
+  if (it != value_.map_->end() && (*it).first == key)
+    return (*it).second;
+
+  ObjectValues::value_type defaultValue(key, nullSingleton());
+  it = value_.map_->insert(it, defaultValue);
+  return (*it).second;
+}
+
+Value &Value::operator[](int index)
+{
+  JSON_ASSERT_MESSAGE(index >= 0,
+                      "in Json::Value::operator[](int index): index cannot be negative");
+  return (*this)[ArrayIndex(index)];
+}
+
+const Value &Value::operator[](ArrayIndex index) const
+{
+  JSON_ASSERT_MESSAGE(type_ == nullValue || type_ == arrayValue,
+                      "in Json::Value::operator[](ArrayIndex)const: requires arrayValue");
+  if (type_ == nullValue)
+    return nullSingleton();
+  CZString key(index);
+  ObjectValues::const_iterator it = value_.map_->find(key);
+  if (it == value_.map_->end())
+    return nullSingleton();
+  return (*it).second;
+}
+
+const Value &Value::operator[](int index) const
+{
+  JSON_ASSERT_MESSAGE(index >= 0,
+                      "in Json::Value::operator[](int index) const: index cannot be negative");
+  return (*this)[ArrayIndex(index)];
+}
+
+void Value::initBasic(ValueType vtype, bool allocated)
+{
+  type_ = vtype;
+  allocated_ = allocated;
+  comments_ = 0;
+  start_ = 0;
+  limit_ = 0;
+}
+
+// Access an object value by name, create a null member if it does not exist.
+// @pre Type of '*this' is object or null.
+// @param key is null-terminated.
+Value &Value::resolveReference(const char *key)
+{
+  JSON_ASSERT_MESSAGE(type_ == nullValue || type_ == objectValue,
+                      "in Json::Value::resolveReference(): requires objectValue");
+  if (type_ == nullValue)
+    *this = Value(objectValue);
+  CZString actualKey(key, static_cast<unsigned>(strlen(key)), CZString::noDuplication); // NOTE!
+  ObjectValues::iterator it = value_.map_->lower_bound(actualKey);
+  if (it != value_.map_->end() && (*it).first == actualKey)
+    return (*it).second;
+
+  ObjectValues::value_type defaultValue(actualKey, nullSingleton());
+  it = value_.map_->insert(it, defaultValue);
+  Value &value = (*it).second;
+  return value;
+}
+
+// @param key is not null-terminated.
+Value &Value::resolveReference(char const *key, char const *cend)
+{
+  JSON_ASSERT_MESSAGE(type_ == nullValue || type_ == objectValue,
+                      "in Json::Value::resolveReference(key, end): requires objectValue");
+  if (type_ == nullValue)
+    *this = Value(objectValue);
+  CZString actualKey(key, static_cast<unsigned>(cend - key), CZString::duplicateOnCopy);
+  ObjectValues::iterator it = value_.map_->lower_bound(actualKey);
+  if (it != value_.map_->end() && (*it).first == actualKey)
+    return (*it).second;
+
+  ObjectValues::value_type defaultValue(actualKey, nullSingleton());
+  it = value_.map_->insert(it, defaultValue);
+  Value &value = (*it).second;
+  return value;
+}
+
+Value Value::get(ArrayIndex index, const Value &defaultValue) const
+{
+  const Value *value = &((*this)[index]);
+  return value == &nullSingleton() ? defaultValue : *value;
+}
+
+bool Value::isValidIndex(ArrayIndex index) const { return index < size(); }
+
+Value const *Value::find(char const *key, char const *cend) const
+{
+  JSON_ASSERT_MESSAGE(type_ == nullValue || type_ == objectValue,
+                      "in Json::Value::find(key, end, found): requires objectValue or nullValue");
+  if (type_ == nullValue)
+    return NULL;
+  CZString actualKey(key, static_cast<unsigned>(cend - key), CZString::noDuplication);
+  ObjectValues::const_iterator it = value_.map_->find(actualKey);
+  if (it == value_.map_->end())
+    return NULL;
+  return &(*it).second;
+}
+const Value &Value::operator[](const char *key) const
+{
+  Value const *found = find(key, key + strlen(key));
+  if (!found)
+    return nullSingleton();
+  return *found;
+}
+Value const &Value::operator[](JSONCPP_STRING const &key) const
+{
+  Value const *found = find(key.data(), key.data() + key.length());
+  if (!found)
+    return nullSingleton();
+  return *found;
+}
+
+Value &Value::operator[](const char *key) { return resolveReference(key, key + strlen(key)); }
+
+Value &Value::operator[](const JSONCPP_STRING &key)
+{
+  return resolveReference(key.data(), key.data() + key.length());
+}
+
+Value &Value::operator[](const StaticString &key) { return resolveReference(key.c_str()); }
+
+#ifdef JSON_USE_CPPTL
+Value &Value::operator[](const CppTL::ConstString &key)
+{
+  return resolveReference(key.c_str(), key.end_c_str());
+}
+Value const &Value::operator[](CppTL::ConstString const &key) const
+{
+  Value const *found = find(key.c_str(), key.end_c_str());
+  if (!found)
+    return nullSingleton();
+  return *found;
+}
+#endif
+
+Value &Value::append(const Value &value) { return (*this)[size()] = value; }
+
+Value Value::get(char const *key, char const *cend, Value const &defaultValue) const
+{
+  Value const *found = find(key, cend);
+  return !found ? defaultValue : *found;
+}
+Value Value::get(char const *key, Value const &defaultValue) const
+{
+  return get(key, key + strlen(key), defaultValue);
+}
+Value Value::get(JSONCPP_STRING const &key, Value const &defaultValue) const
+{
+  return get(key.data(), key.data() + key.length(), defaultValue);
+}
+
+bool Value::removeMember(const char *key, const char *cend, Value *removed)
+{
+  if (type_ != objectValue)
+  {
+    return false;
+  }
+  CZString actualKey(key, static_cast<unsigned>(cend - key), CZString::noDuplication);
+  ObjectValues::iterator it = value_.map_->find(actualKey);
+  if (it == value_.map_->end())
+    return false;
+  *removed = it->second;
+  value_.map_->erase(it);
+  return true;
+}
+bool Value::removeMember(const char *key, Value *removed)
+{
+  return removeMember(key, key + strlen(key), removed);
+}
+bool Value::removeMember(JSONCPP_STRING const &key, Value *removed)
+{
+  return removeMember(key.data(), key.data() + key.length(), removed);
+}
+Value Value::removeMember(const char *key)
+{
+  JSON_ASSERT_MESSAGE(type_ == nullValue || type_ == objectValue,
+                      "in Json::Value::removeMember(): requires objectValue");
+  if (type_ == nullValue)
+    return nullSingleton();
+
+  Value removed; // null
+  removeMember(key, key + strlen(key), &removed);
+  return removed; // still null if removeMember() did nothing
+}
+Value Value::removeMember(const JSONCPP_STRING &key) { return removeMember(key.c_str()); }
+
+bool Value::removeIndex(ArrayIndex index, Value *removed)
+{
+  if (type_ != arrayValue)
+  {
+    return false;
+  }
+  CZString key(index);
+  ObjectValues::iterator it = value_.map_->find(key);
+  if (it == value_.map_->end())
+  {
+    return false;
+  }
+  *removed = it->second;
+  ArrayIndex oldSize = size();
+  // shift left all items left, into the place of the "removed"
+  for (ArrayIndex i = index; i < (oldSize - 1); ++i)
+  {
+    CZString keey(i);
+    (*value_.map_)[keey] = (*this)[i + 1];
+  }
+  // erase the last one ("leftover")
+  CZString keyLast(oldSize - 1);
+  ObjectValues::iterator itLast = value_.map_->find(keyLast);
+  value_.map_->erase(itLast);
+  return true;
+}
+
+#ifdef JSON_USE_CPPTL
+Value Value::get(const CppTL::ConstString &key, const Value &defaultValue) const
+{
+  return get(key.c_str(), key.end_c_str(), defaultValue);
+}
+#endif
+
+bool Value::isMember(char const *key, char const *cend) const
+{
+  Value const *value = find(key, cend);
+  return NULL != value;
+}
+bool Value::isMember(char const *key) const { return isMember(key, key + strlen(key)); }
+bool Value::isMember(JSONCPP_STRING const &key) const
+{
+  return isMember(key.data(), key.data() + key.length());
+}
+
+#ifdef JSON_USE_CPPTL
+bool Value::isMember(const CppTL::ConstString &key) const
+{
+  return isMember(key.c_str(), key.end_c_str());
+}
+#endif
+
+Value::Members Value::getMemberNames() const
+{
+  JSON_ASSERT_MESSAGE(type_ == nullValue || type_ == objectValue,
+                      "in Json::Value::getMemberNames(), value must be objectValue");
+  if (type_ == nullValue)
+    return Value::Members();
+  Members members;
+  members.reserve(value_.map_->size());
+  ObjectValues::const_iterator it = value_.map_->begin();
+  ObjectValues::const_iterator itEnd = value_.map_->end();
+  for (; it != itEnd; ++it)
+  {
+    members.push_back(JSONCPP_STRING((*it).first.data(), (*it).first.length()));
+  }
+  return members;
+}
+//
+//# ifdef JSON_USE_CPPTL
+// EnumMemberNames
+// Value::enumMemberNames() const
+//{
+//   if ( type_ == objectValue )
+//   {
+//      return CppTL::Enum::any(  CppTL::Enum::transform(
+//         CppTL::Enum::keys( *(value_.map_), CppTL::Type<const CZString &>() ),
+//         MemberNamesTransform() ) );
+//   }
+//   return EnumMemberNames();
+//}
+//
+//
+// EnumValues
+// Value::enumValues() const
+//{
+//   if ( type_ == objectValue  ||  type_ == arrayValue )
+//      return CppTL::Enum::anyValues( *(value_.map_),
+//                                     CppTL::Type<const Value &>() );
+//   return EnumValues();
+//}
+//
+//# endif
+
+static bool IsIntegral(double d)
+{
+  double integral_part;
+  return modf(d, &integral_part) == 0.0;
+}
+
+bool Value::isNull() const { return type_ == nullValue; }
+
+bool Value::isBool() const { return type_ == booleanValue; }
+
+bool Value::isInt() const
+{
+  switch (type_)
+  {
+    case intValue:
+      return value_.int_ >= minInt && value_.int_ <= maxInt;
+    case uintValue:
+      return value_.uint_ <= UInt(maxInt);
+    case realValue:
+      return value_.real_ >= minInt && value_.real_ <= maxInt && IsIntegral(value_.real_);
+    default:
+      break;
+  }
+  return false;
+}
+
+bool Value::isUInt() const
+{
+  switch (type_)
+  {
+    case intValue:
+      return value_.int_ >= 0 && LargestUInt(value_.int_) <= LargestUInt(maxUInt);
+    case uintValue:
+      return value_.uint_ <= maxUInt;
+    case realValue:
+      return value_.real_ >= 0 && value_.real_ <= maxUInt && IsIntegral(value_.real_);
+    default:
+      break;
+  }
+  return false;
+}
+
+bool Value::isInt64() const
+{
+#if defined(JSON_HAS_INT64)
+  switch (type_)
+  {
+    case intValue:
+      return true;
+    case uintValue:
+      return value_.uint_ <= UInt64(maxInt64);
+    case realValue:
+      // Note that maxInt64 (= 2^63 - 1) is not exactly representable as a
+      // double, so double(maxInt64) will be rounded up to 2^63. Therefore we
+      // require the value to be strictly less than the limit.
+      return value_.real_ >= double(minInt64) && value_.real_ < double(maxInt64) &&
+             IsIntegral(value_.real_);
+    default:
+      break;
+  }
+#endif // JSON_HAS_INT64
+  return false;
+}
+
+bool Value::isUInt64() const
+{
+#if defined(JSON_HAS_INT64)
+  switch (type_)
+  {
+    case intValue:
+      return value_.int_ >= 0;
+    case uintValue:
+      return true;
+    case realValue:
+      // Note that maxUInt64 (= 2^64 - 1) is not exactly representable as a
+      // double, so double(maxUInt64) will be rounded up to 2^64. Therefore we
+      // require the value to be strictly less than the limit.
+      return value_.real_ >= 0 && value_.real_ < maxUInt64AsDouble && IsIntegral(value_.real_);
+    default:
+      break;
+  }
+#endif // JSON_HAS_INT64
+  return false;
+}
+
+bool Value::isIntegral() const
+{
+#if defined(JSON_HAS_INT64)
+  return isInt64() || isUInt64();
+#else
+  return isInt() || isUInt();
+#endif
+}
+
+bool Value::isDouble() const { return type_ == realValue || isIntegral(); }
+
+bool Value::isNumeric() const { return isIntegral() || isDouble(); }
+
+bool Value::isString() const { return type_ == stringValue; }
+
+bool Value::isArray() const { return type_ == arrayValue; }
+
+bool Value::isObject() const { return type_ == objectValue; }
+
+void Value::setComment(const char *comment, size_t len, CommentPlacement placement)
+{
+  if (!comments_)
+    comments_ = new CommentInfo[numberOfCommentPlacement];
+  if ((len > 0) && (comment[len - 1] == '\n'))
+  {
+    // Always discard trailing newline, to aid indentation.
+    len -= 1;
+  }
+  comments_[placement].setComment(comment, len);
+}
+
+void Value::setComment(const char *comment, CommentPlacement placement)
+{
+  setComment(comment, strlen(comment), placement);
+}
+
+void Value::setComment(const JSONCPP_STRING &comment, CommentPlacement placement)
+{
+  setComment(comment.c_str(), comment.length(), placement);
+}
+
+bool Value::hasComment(CommentPlacement placement) const
+{
+  return comments_ != 0 && comments_[placement].comment_ != 0;
+}
+
+JSONCPP_STRING Value::getComment(CommentPlacement placement) const
+{
+  if (hasComment(placement))
+    return comments_[placement].comment_;
+  return "";
+}
+
+void Value::setOffsetStart(ptrdiff_t start) { start_ = start; }
+
+void Value::setOffsetLimit(ptrdiff_t limit) { limit_ = limit; }
+
+ptrdiff_t Value::getOffsetStart() const { return start_; }
+
+ptrdiff_t Value::getOffsetLimit() const { return limit_; }
+
+JSONCPP_STRING Value::toStyledString() const
+{
+  StyledWriter writer;
+  return writer.write(*this);
+}
+
+Value::const_iterator Value::begin() const
+{
+  switch (type_)
+  {
+    case arrayValue:
+    case objectValue:
+      if (value_.map_)
+        return const_iterator(value_.map_->begin());
+      break;
+    default:
+      break;
+  }
+  return const_iterator();
+}
+
+Value::const_iterator Value::end() const
+{
+  switch (type_)
+  {
+    case arrayValue:
+    case objectValue:
+      if (value_.map_)
+        return const_iterator(value_.map_->end());
+      break;
+    default:
+      break;
+  }
+  return const_iterator();
+}
+
+Value::iterator Value::begin()
+{
+  switch (type_)
+  {
+    case arrayValue:
+    case objectValue:
+      if (value_.map_)
+        return iterator(value_.map_->begin());
+      break;
+    default:
+      break;
+  }
+  return iterator();
+}
+
+Value::iterator Value::end()
+{
+  switch (type_)
+  {
+    case arrayValue:
+    case objectValue:
+      if (value_.map_)
+        return iterator(value_.map_->end());
+      break;
+    default:
+      break;
+  }
+  return iterator();
+}
+
+// class PathArgument
+// //////////////////////////////////////////////////////////////////
+
+PathArgument::PathArgument() : key_(), index_(), kind_(kindNone) {}
+
+PathArgument::PathArgument(ArrayIndex index) : key_(), index_(index), kind_(kindIndex) {}
+
+PathArgument::PathArgument(const char *key) : key_(key), index_(), kind_(kindKey) {}
+
+PathArgument::PathArgument(const JSONCPP_STRING &key) : key_(key.c_str()), index_(), kind_(kindKey)
+{
+}
+
+// class Path
+// //////////////////////////////////////////////////////////////////
+
+Path::Path(const JSONCPP_STRING &path, const PathArgument &a1, const PathArgument &a2,
+           const PathArgument &a3, const PathArgument &a4, const PathArgument &a5)
+{
+  InArgs in;
+  in.push_back(&a1);
+  in.push_back(&a2);
+  in.push_back(&a3);
+  in.push_back(&a4);
+  in.push_back(&a5);
+  makePath(path, in);
+}
+
+void Path::makePath(const JSONCPP_STRING &path, const InArgs &in)
+{
+  const char *current = path.c_str();
+  const char *end = current + path.length();
+  InArgs::const_iterator itInArg = in.begin();
+  while (current != end)
+  {
+    if (*current == '[')
+    {
+      ++current;
+      if (*current == '%')
+        addPathInArg(path, in, itInArg, PathArgument::kindIndex);
+      else
+      {
+        ArrayIndex index = 0;
+        for (; current != end && *current >= '0' && *current <= '9'; ++current)
+          index = index * 10 + ArrayIndex(*current - '0');
+        args_.push_back(index);
+      }
+      if (current == end || *++current != ']')
+        invalidPath(path, int(current - path.c_str()));
+    }
+    else if (*current == '%')
+    {
+      addPathInArg(path, in, itInArg, PathArgument::kindKey);
+      ++current;
+    }
+    else if (*current == '.' || *current == ']')
+    {
+      ++current;
+    }
+    else
+    {
+      const char *beginName = current;
+      while (current != end && !strchr("[.", *current))
+        ++current;
+      args_.push_back(JSONCPP_STRING(beginName, current));
+    }
+  }
+}
+
+void Path::addPathInArg(const JSONCPP_STRING & /*path*/, const InArgs &in,
+                        InArgs::const_iterator &itInArg, PathArgument::Kind kind)
+{
+  if (itInArg == in.end())
+  {
+    // Error: missing argument %d
+  }
+  else if ((*itInArg)->kind_ != kind)
+  {
+    // Error: bad argument type
+  }
+  else
+  {
+    args_.push_back(**itInArg++);
+  }
+}
+
+void Path::invalidPath(const JSONCPP_STRING & /*path*/, int /*location*/)
+{
+  // Error: invalid path.
+}
+
+const Value &Path::resolve(const Value &root) const
+{
+  const Value *node = &root;
+  for (Args::const_iterator it = args_.begin(); it != args_.end(); ++it)
+  {
+    const PathArgument &arg = *it;
+    if (arg.kind_ == PathArgument::kindIndex)
+    {
+      if (!node->isArray() || !node->isValidIndex(arg.index_))
+      {
+        // Error: unable to resolve path (array value expected at position...
+        return Value::null;
+      }
+      node = &((*node)[arg.index_]);
+    }
+    else if (arg.kind_ == PathArgument::kindKey)
+    {
+      if (!node->isObject())
+      {
+        // Error: unable to resolve path (object value expected at position...)
+        return Value::null;
+      }
+      node = &((*node)[arg.key_]);
+      if (node == &Value::nullSingleton())
+      {
+        // Error: unable to resolve path (object has no member named '' at
+        // position...)
+        return Value::null;
+      }
+    }
+  }
+  return *node;
+}
+
+Value Path::resolve(const Value &root, const Value &defaultValue) const
+{
+  const Value *node = &root;
+  for (Args::const_iterator it = args_.begin(); it != args_.end(); ++it)
+  {
+    const PathArgument &arg = *it;
+    if (arg.kind_ == PathArgument::kindIndex)
+    {
+      if (!node->isArray() || !node->isValidIndex(arg.index_))
+        return defaultValue;
+      node = &((*node)[arg.index_]);
+    }
+    else if (arg.kind_ == PathArgument::kindKey)
+    {
+      if (!node->isObject())
+        return defaultValue;
+      node = &((*node)[arg.key_]);
+      if (node == &Value::nullSingleton())
+        return defaultValue;
+    }
+  }
+  return *node;
+}
+
+Value &Path::make(Value &root) const
+{
+  Value *node = &root;
+  for (Args::const_iterator it = args_.begin(); it != args_.end(); ++it)
+  {
+    const PathArgument &arg = *it;
+    if (arg.kind_ == PathArgument::kindIndex)
+    {
+      if (!node->isArray())
+      {
+        // Error: node is not an array at position ...
+      }
+      node = &((*node)[arg.index_]);
+    }
+    else if (arg.kind_ == PathArgument::kindKey)
+    {
+      if (!node->isObject())
+      {
+        // Error: node is not an object at position...
+      }
+      node = &((*node)[arg.key_]);
+    }
+  }
+  return *node;
+}
+
+} // namespace Json
+
+// //////////////////////////////////////////////////////////////////////
+// End of content of file: src/lib_json/json_value.cpp
+// //////////////////////////////////////////////////////////////////////
+
+// //////////////////////////////////////////////////////////////////////
+// Beginning of content of file: src/lib_json/json_writer.cpp
+// //////////////////////////////////////////////////////////////////////
+
+// Copyright 2011 Baptiste Lepilleur
+// Distributed under MIT license, or public domain if desired and
+// recognized in your jurisdiction.
+// See file LICENSE for detail or copy at http://jsoncpp.sourceforge.net/LICENSE
+
+#if !defined(JSON_IS_AMALGAMATION)
+#include <json/writer.h>
+#include "json_tool.h"
+#endif // if !defined(JSON_IS_AMALGAMATION)
+#include <iomanip>
+#include <memory>
+#include <sstream>
+#include <utility>
+#include <set>
+#include <cassert>
+#include <cstring>
+#include <cstdio>
+
+#if defined(_MSC_VER) && _MSC_VER >= 1200 && _MSC_VER < 1800 // Between VC++ 6.0 and VC++ 11.0
+#include <float.h>
+#define isfinite _finite
+#elif defined(__sun) && defined(__SVR4) // Solaris
+#if !defined(isfinite)
+#include <ieeefp.h>
+#define isfinite finite
+#endif
+#elif defined(_AIX)
+#if !defined(isfinite)
+#include <math.h>
+#define isfinite finite
+#endif
+#elif defined(__hpux)
+#if !defined(isfinite)
+#if defined(__ia64) && !defined(finite)
+#define isfinite(x) ((sizeof(x) == sizeof(float) ? _Isfinitef(x) : _IsFinite(x)))
+#else
+#include <math.h>
+#define isfinite finite
+#endif
+#endif
+#else
+#include <cmath>
+#if !(defined(__QNXNTO__)) // QNX already defines isfinite
+#define isfinite std::isfinite
+#endif
+#endif
+
+#if defined(_MSC_VER)
+#if !defined(WINCE) && defined(__STDC_SECURE_LIB__) && _MSC_VER >= 1500 // VC++ 9.0 and above
+#define snprintf sprintf_s
+#elif _MSC_VER >= 1900 // VC++ 14.0 and above
+#define snprintf std::snprintf
+#else
+#define snprintf _snprintf
+#endif
+#elif defined(__ANDROID__) || defined(__QNXNTO__)
+#define snprintf snprintf
+#elif __cplusplus >= 201103L
+#if !defined(__MINGW32__) && !defined(__CYGWIN__)
+#define snprintf std::snprintf
+#endif
+#endif
+
+#if defined(__BORLANDC__)
+#include <float.h>
+#define isfinite _finite
+#define snprintf _snprintf
+#endif
+
+#if defined(_MSC_VER) && _MSC_VER >= 1400 // VC++ 8.0
+// Disable warning about strdup being deprecated.
+#pragma warning(disable : 4996)
+#endif
+
+namespace Json
+{
+
+#if __cplusplus >= 201103L || (defined(_CPPLIB_VER) && _CPPLIB_VER >= 520)
+typedef std::unique_ptr<StreamWriter> StreamWriterPtr;
+#else
+typedef std::auto_ptr<StreamWriter> StreamWriterPtr;
+#endif
+
+static bool containsControlCharacter(const char *str)
+{
+  while (*str)
+  {
+    if (isControlCharacter(*(str++)))
+      return true;
+  }
+  return false;
+}
+
+static bool containsControlCharacter0(const char *str, unsigned len)
+{
+  char const *end = str + len;
+  while (end != str)
+  {
+    if (isControlCharacter(*str) || 0 == *str)
+      return true;
+    ++str;
+  }
+  return false;
+}
+
+JSONCPP_STRING valueToString(LargestInt value)
+{
+  UIntToStringBuffer buffer;
+  char *current = buffer + sizeof(buffer);
+  if (value == Value::minLargestInt)
+  {
+    uintToString(LargestUInt(Value::maxLargestInt) + 1, current);
+    *--current = '-';
+  }
+  else if (value < 0)
+  {
+    uintToString(LargestUInt(-value), current);
+    *--current = '-';
+  }
+  else
+  {
+    uintToString(LargestUInt(value), current);
+  }
+  assert(current >= buffer);
+  return current;
+}
+
+JSONCPP_STRING valueToString(LargestUInt value)
+{
+  UIntToStringBuffer buffer;
+  char *current = buffer + sizeof(buffer);
+  uintToString(value, current);
+  assert(current >= buffer);
+  return current;
+}
+
+#if defined(JSON_HAS_INT64)
+
+JSONCPP_STRING valueToString(Int value) { return valueToString(LargestInt(value)); }
+
+JSONCPP_STRING valueToString(UInt value) { return valueToString(LargestUInt(value)); }
+
+#endif // # if defined(JSON_HAS_INT64)
+
+namespace
+{
+JSONCPP_STRING valueToString(double value, bool useSpecialFloats, unsigned int precision)
+{
+  // Allocate a buffer that is more than large enough to store the 16 digits of
+  // precision requested below.
+  char buffer[32];
+  int len = -1;
+
+  char formatString[6];
+  sprintf(formatString, "%%.%dg", precision);
+
+  // Print into the buffer. We need not request the alternative representation
+  // that always has a decimal point because JSON doesn't distingish the
+  // concepts of reals and integers.
+  if (isfinite(value))
+  {
+    len = snprintf(buffer, sizeof(buffer), formatString, value);
+  }
+  else
+  {
+    // IEEE standard states that NaN values will not compare to themselves
+    if (value != value)
+    {
+      len = snprintf(buffer, sizeof(buffer), useSpecialFloats ? "NaN" : "null");
+    }
+    else if (value < 0)
+    {
+      len = snprintf(buffer, sizeof(buffer), useSpecialFloats ? "-Infinity" : "-1e+9999");
+    }
+    else
+    {
+      len = snprintf(buffer, sizeof(buffer), useSpecialFloats ? "Infinity" : "1e+9999");
+    }
+    // For those, we do not need to call fixNumLoc, but it is fast.
+  }
+  assert(len >= 0);
+  fixNumericLocale(buffer, buffer + len);
+  return buffer;
+}
+}
+
+JSONCPP_STRING valueToString(double value) { return valueToString(value, false, 17); }
+
+JSONCPP_STRING valueToString(bool value) { return value ? "true" : "false"; }
+
+JSONCPP_STRING valueToQuotedString(const char *value)
+{
+  if (value == NULL)
+    return "";
+  // Not sure how to handle unicode...
+  if (strpbrk(value, "\"\\\b\f\n\r\t") == NULL && !containsControlCharacter(value))
+    return JSONCPP_STRING("\"") + value + "\"";
+  // We have to walk value and escape any special characters.
+  // Appending to JSONCPP_STRING is not efficient, but this should be rare.
+  // (Note: forward slashes are *not* rare, but I am not escaping them.)
+  JSONCPP_STRING::size_type maxsize = strlen(value) * 2 + 3; // allescaped+quotes+NULL
+  JSONCPP_STRING result;
+  result.reserve(maxsize); // to avoid lots of mallocs
+  result += "\"";
+  for (const char *c = value; *c != 0; ++c)
+  {
+    switch (*c)
+    {
+      case '\"':
+        result += "\\\"";
+        break;
+      case '\\':
+        result += "\\\\";
+        break;
+      case '\b':
+        result += "\\b";
+        break;
+      case '\f':
+        result += "\\f";
+        break;
+      case '\n':
+        result += "\\n";
+        break;
+      case '\r':
+        result += "\\r";
+        break;
+      case '\t':
+        result += "\\t";
+        break;
+      // case '/':
+      // Even though \/ is considered a legal escape in JSON, a bare
+      // slash is also legal, so I see no reason to escape it.
+      // (I hope I am not misunderstanding something.
+      // blep notes: actually escaping \/ may be useful in javascript to avoid </
+      // sequence.
+      // Should add a flag to allow this compatibility mode and prevent this
+      // sequence from occurring.
+      default:
+        if (isControlCharacter(*c))
+        {
+          JSONCPP_OSTRINGSTREAM oss;
+          oss << "\\u" << std::hex << std::uppercase << std::setfill('0') << std::setw(4)
+              << static_cast<int>(*c);
+          result += oss.str();
+        }
+        else
+        {
+          result += *c;
+        }
+        break;
+    }
+  }
+  result += "\"";
+  return result;
+}
+
+// https://github.com/upcaste/upcaste/blob/master/src/upcore/src/cstring/strnpbrk.cpp
+static char const *strnpbrk(char const *s, char const *accept, size_t n)
+{
+  assert((s || !n) && accept);
+
+  char const *const end = s + n;
+  for (char const *cur = s; cur < end; ++cur)
+  {
+    int const c = *cur;
+    for (char const *a = accept; *a; ++a)
+    {
+      if (*a == c)
+      {
+        return cur;
+      }
+    }
+  }
+  return NULL;
+}
+static JSONCPP_STRING valueToQuotedStringN(const char *value, unsigned length)
+{
+  if (value == NULL)
+    return "";
+  // Not sure how to handle unicode...
+  if (strnpbrk(value, "\"\\\b\f\n\r\t", length) == NULL &&
+      !containsControlCharacter0(value, length))
+    return JSONCPP_STRING("\"") + value + "\"";
+  // We have to walk value and escape any special characters.
+  // Appending to JSONCPP_STRING is not efficient, but this should be rare.
+  // (Note: forward slashes are *not* rare, but I am not escaping them.)
+  JSONCPP_STRING::size_type maxsize = length * 2 + 3; // allescaped+quotes+NULL
+  JSONCPP_STRING result;
+  result.reserve(maxsize); // to avoid lots of mallocs
+  result += "\"";
+  char const *end = value + length;
+  for (const char *c = value; c != end; ++c)
+  {
+    switch (*c)
+    {
+      case '\"':
+        result += "\\\"";
+        break;
+      case '\\':
+        result += "\\\\";
+        break;
+      case '\b':
+        result += "\\b";
+        break;
+      case '\f':
+        result += "\\f";
+        break;
+      case '\n':
+        result += "\\n";
+        break;
+      case '\r':
+        result += "\\r";
+        break;
+      case '\t':
+        result += "\\t";
+        break;
+      // case '/':
+      // Even though \/ is considered a legal escape in JSON, a bare
+      // slash is also legal, so I see no reason to escape it.
+      // (I hope I am not misunderstanding something.)
+      // blep notes: actually escaping \/ may be useful in javascript to avoid </
+      // sequence.
+      // Should add a flag to allow this compatibility mode and prevent this
+      // sequence from occurring.
+      default:
+        if ((isControlCharacter(*c)) || (*c == 0))
+        {
+          JSONCPP_OSTRINGSTREAM oss;
+          oss << "\\u" << std::hex << std::uppercase << std::setfill('0') << std::setw(4)
+              << static_cast<int>(*c);
+          result += oss.str();
+        }
+        else
+        {
+          result += *c;
+        }
+        break;
+    }
+  }
+  result += "\"";
+  return result;
+}
+
+// Class Writer
+// //////////////////////////////////////////////////////////////////
+Writer::~Writer() {}
+
+// Class FastWriter
+// //////////////////////////////////////////////////////////////////
+
+FastWriter::FastWriter()
+    : yamlCompatiblityEnabled_(false), dropNullPlaceholders_(false), omitEndingLineFeed_(false)
+{
+}
+
+void FastWriter::enableYAMLCompatibility() { yamlCompatiblityEnabled_ = true; }
+
+void FastWriter::dropNullPlaceholders() { dropNullPlaceholders_ = true; }
+
+void FastWriter::omitEndingLineFeed() { omitEndingLineFeed_ = true; }
+
+JSONCPP_STRING FastWriter::write(const Value &root)
+{
+  document_ = "";
+  writeValue(root);
+  if (!omitEndingLineFeed_)
+    document_ += "\n";
+  return document_;
+}
+
+void FastWriter::writeValue(const Value &value)
+{
+  switch (value.type())
+  {
+    case nullValue:
+      if (!dropNullPlaceholders_)
+        document_ += "null";
+      break;
+    case intValue:
+      document_ += valueToString(value.asLargestInt());
+      break;
+    case uintValue:
+      document_ += valueToString(value.asLargestUInt());
+      break;
+    case realValue:
+      document_ += valueToString(value.asDouble());
+      break;
+    case stringValue:
+    {
+      // Is NULL possible for value.string_? No.
+      char const *str;
+      char const *end;
+      bool ok = value.getString(&str, &end);
+      if (ok)
+        document_ += valueToQuotedStringN(str, static_cast<unsigned>(end - str));
+      break;
+    }
+    case booleanValue:
+      document_ += valueToString(value.asBool());
+      break;
+    case arrayValue:
+    {
+      document_ += '[';
+      ArrayIndex size = value.size();
+      for (ArrayIndex index = 0; index < size; ++index)
+      {
+        if (index > 0)
+          document_ += ',';
+        writeValue(value[index]);
+      }
+      document_ += ']';
+    }
+    break;
+    case objectValue:
+    {
+      Value::Members members(value.getMemberNames());
+      document_ += '{';
+      for (Value::Members::iterator it = members.begin(); it != members.end(); ++it)
+      {
+        const JSONCPP_STRING &name = *it;
+        if (it != members.begin())
+          document_ += ',';
+        document_ += valueToQuotedStringN(name.data(), static_cast<unsigned>(name.length()));
+        document_ += yamlCompatiblityEnabled_ ? ": " : ":";
+        writeValue(value[name]);
+      }
+      document_ += '}';
+    }
+    break;
+  }
+}
+
+// Class StyledWriter
+// //////////////////////////////////////////////////////////////////
+
+StyledWriter::StyledWriter() : rightMargin_(74), indentSize_(3), addChildValues_() {}
+
+JSONCPP_STRING StyledWriter::write(const Value &root)
+{
+  document_ = "";
+  addChildValues_ = false;
+  indentString_ = "";
+  writeCommentBeforeValue(root);
+  writeValue(root);
+  writeCommentAfterValueOnSameLine(root);
+  document_ += "\n";
+  return document_;
+}
+
+void StyledWriter::writeValue(const Value &value)
+{
+  switch (value.type())
+  {
+    case nullValue:
+      pushValue("null");
+      break;
+    case intValue:
+      pushValue(valueToString(value.asLargestInt()));
+      break;
+    case uintValue:
+      pushValue(valueToString(value.asLargestUInt()));
+      break;
+    case realValue:
+      pushValue(valueToString(value.asDouble()));
+      break;
+    case stringValue:
+    {
+      // Is NULL possible for value.string_? No.
+      char const *str;
+      char const *end;
+      bool ok = value.getString(&str, &end);
+      if (ok)
+        pushValue(valueToQuotedStringN(str, static_cast<unsigned>(end - str)));
+      else
+        pushValue("");
+      break;
+    }
+    case booleanValue:
+      pushValue(valueToString(value.asBool()));
+      break;
+    case arrayValue:
+      writeArrayValue(value);
+      break;
+    case objectValue:
+    {
+      Value::Members members(value.getMemberNames());
+      if (members.empty())
+        pushValue("{}");
+      else
+      {
+        writeWithIndent("{");
+        indent();
+        Value::Members::iterator it = members.begin();
+        for (;;)
+        {
+          const JSONCPP_STRING &name = *it;
+          const Value &childValue = value[name];
+          writeCommentBeforeValue(childValue);
+          writeWithIndent(valueToQuotedString(name.c_str()));
+          document_ += " : ";
+          writeValue(childValue);
+          if (++it == members.end())
+          {
+            writeCommentAfterValueOnSameLine(childValue);
+            break;
+          }
+          document_ += ',';
+          writeCommentAfterValueOnSameLine(childValue);
+        }
+        unindent();
+        writeWithIndent("}");
+      }
+    }
+    break;
+  }
+}
+
+void StyledWriter::writeArrayValue(const Value &value)
+{
+  unsigned size = value.size();
+  if (size == 0)
+    pushValue("[]");
+  else
+  {
+    bool isArrayMultiLine = isMultineArray(value);
+    if (isArrayMultiLine)
+    {
+      writeWithIndent("[");
+      indent();
+      bool hasChildValue = !childValues_.empty();
+      unsigned index = 0;
+      for (;;)
+      {
+        const Value &childValue = value[index];
+        writeCommentBeforeValue(childValue);
+        if (hasChildValue)
+          writeWithIndent(childValues_[index]);
+        else
+        {
+          writeIndent();
+          writeValue(childValue);
+        }
+        if (++index == size)
+        {
+          writeCommentAfterValueOnSameLine(childValue);
+          break;
+        }
+        document_ += ',';
+        writeCommentAfterValueOnSameLine(childValue);
+      }
+      unindent();
+      writeWithIndent("]");
+    }
+    else // output on a single line
+    {
+      assert(childValues_.size() == size);
+      document_ += "[ ";
+      for (unsigned index = 0; index < size; ++index)
+      {
+        if (index > 0)
+          document_ += ", ";
+        document_ += childValues_[index];
+      }
+      document_ += " ]";
+    }
+  }
+}
+
+bool StyledWriter::isMultineArray(const Value &value)
+{
+  ArrayIndex const size = value.size();
+  bool isMultiLine = size * 3 >= rightMargin_;
+  childValues_.clear();
+  for (ArrayIndex index = 0; index < size && !isMultiLine; ++index)
+  {
+    const Value &childValue = value[index];
+    isMultiLine = ((childValue.isArray() || childValue.isObject()) && childValue.size() > 0);
+  }
+  if (!isMultiLine) // check if line length > max line length
+  {
+    childValues_.reserve(size);
+    addChildValues_ = true;
+    ArrayIndex lineLength = 4 + (size - 1) * 2; // '[ ' + ', '*n + ' ]'
+    for (ArrayIndex index = 0; index < size; ++index)
+    {
+      if (hasCommentForValue(value[index]))
+      {
+        isMultiLine = true;
+      }
+      writeValue(value[index]);
+      lineLength += static_cast<ArrayIndex>(childValues_[index].length());
+    }
+    addChildValues_ = false;
+    isMultiLine = isMultiLine || lineLength >= rightMargin_;
+  }
+  return isMultiLine;
+}
+
+void StyledWriter::pushValue(const JSONCPP_STRING &value)
+{
+  if (addChildValues_)
+    childValues_.push_back(value);
+  else
+    document_ += value;
+}
+
+void StyledWriter::writeIndent()
+{
+  if (!document_.empty())
+  {
+    char last = document_[document_.length() - 1];
+    if (last == ' ') // already indented
+      return;
+    if (last != '\n') // Comments may add new-line
+      document_ += '\n';
+  }
+  document_ += indentString_;
+}
+
+void StyledWriter::writeWithIndent(const JSONCPP_STRING &value)
+{
+  writeIndent();
+  document_ += value;
+}
+
+void StyledWriter::indent() { indentString_ += JSONCPP_STRING(indentSize_, ' '); }
+
+void StyledWriter::unindent()
+{
+  assert(indentString_.size() >= indentSize_);
+  indentString_.resize(indentString_.size() - indentSize_);
+}
+
+void StyledWriter::writeCommentBeforeValue(const Value &root)
+{
+  if (!root.hasComment(commentBefore))
+    return;
+
+  document_ += "\n";
+  writeIndent();
+  const JSONCPP_STRING &comment = root.getComment(commentBefore);
+  JSONCPP_STRING::const_iterator iter = comment.begin();
+  while (iter != comment.end())
+  {
+    document_ += *iter;
+    if (*iter == '\n' && (iter != comment.end() && *(iter + 1) == '/'))
+      writeIndent();
+    ++iter;
+  }
+
+  // Comments are stripped of trailing newlines, so add one here
+  document_ += "\n";
+}
+
+void StyledWriter::writeCommentAfterValueOnSameLine(const Value &root)
+{
+  if (root.hasComment(commentAfterOnSameLine))
+    document_ += " " + root.getComment(commentAfterOnSameLine);
+
+  if (root.hasComment(commentAfter))
+  {
+    document_ += "\n";
+    document_ += root.getComment(commentAfter);
+    document_ += "\n";
+  }
+}
+
+bool StyledWriter::hasCommentForValue(const Value &value)
+{
+  return value.hasComment(commentBefore) || value.hasComment(commentAfterOnSameLine) ||
+         value.hasComment(commentAfter);
+}
+
+// Class StyledStreamWriter
+// //////////////////////////////////////////////////////////////////
+
+StyledStreamWriter::StyledStreamWriter(JSONCPP_STRING indentation)
+    : document_(NULL), rightMargin_(74), indentation_(indentation), addChildValues_()
+{
+}
+
+void StyledStreamWriter::write(JSONCPP_OSTREAM &out, const Value &root)
+{
+  document_ = &out;
+  addChildValues_ = false;
+  indentString_ = "";
+  indented_ = true;
+  writeCommentBeforeValue(root);
+  if (!indented_)
+    writeIndent();
+  indented_ = true;
+  writeValue(root);
+  writeCommentAfterValueOnSameLine(root);
+  *document_ << "\n";
+  document_ = NULL; // Forget the stream, for safety.
+}
+
+void StyledStreamWriter::writeValue(const Value &value)
+{
+  switch (value.type())
+  {
+    case nullValue:
+      pushValue("null");
+      break;
+    case intValue:
+      pushValue(valueToString(value.asLargestInt()));
+      break;
+    case uintValue:
+      pushValue(valueToString(value.asLargestUInt()));
+      break;
+    case realValue:
+      pushValue(valueToString(value.asDouble()));
+      break;
+    case stringValue:
+    {
+      // Is NULL possible for value.string_? No.
+      char const *str;
+      char const *end;
+      bool ok = value.getString(&str, &end);
+      if (ok)
+        pushValue(valueToQuotedStringN(str, static_cast<unsigned>(end - str)));
+      else
+        pushValue("");
+      break;
+    }
+    case booleanValue:
+      pushValue(valueToString(value.asBool()));
+      break;
+    case arrayValue:
+      writeArrayValue(value);
+      break;
+    case objectValue:
+    {
+      Value::Members members(value.getMemberNames());
+      if (members.empty())
+        pushValue("{}");
+      else
+      {
+        writeWithIndent("{");
+        indent();
+        Value::Members::iterator it = members.begin();
+        for (;;)
+        {
+          const JSONCPP_STRING &name = *it;
+          const Value &childValue = value[name];
+          writeCommentBeforeValue(childValue);
+          writeWithIndent(valueToQuotedString(name.c_str()));
+          *document_ << " : ";
+          writeValue(childValue);
+          if (++it == members.end())
+          {
+            writeCommentAfterValueOnSameLine(childValue);
+            break;
+          }
+          *document_ << ",";
+          writeCommentAfterValueOnSameLine(childValue);
+        }
+        unindent();
+        writeWithIndent("}");
+      }
+    }
+    break;
+  }
+}
+
+void StyledStreamWriter::writeArrayValue(const Value &value)
+{
+  unsigned size = value.size();
+  if (size == 0)
+    pushValue("[]");
+  else
+  {
+    bool isArrayMultiLine = isMultineArray(value);
+    if (isArrayMultiLine)
+    {
+      writeWithIndent("[");
+      indent();
+      bool hasChildValue = !childValues_.empty();
+      unsigned index = 0;
+      for (;;)
+      {
+        const Value &childValue = value[index];
+        writeCommentBeforeValue(childValue);
+        if (hasChildValue)
+          writeWithIndent(childValues_[index]);
+        else
+        {
+          if (!indented_)
+            writeIndent();
+          indented_ = true;
+          writeValue(childValue);
+          indented_ = false;
+        }
+        if (++index == size)
+        {
+          writeCommentAfterValueOnSameLine(childValue);
+          break;
+        }
+        *document_ << ",";
+        writeCommentAfterValueOnSameLine(childValue);
+      }
+      unindent();
+      writeWithIndent("]");
+    }
+    else // output on a single line
+    {
+      assert(childValues_.size() == size);
+      *document_ << "[ ";
+      for (unsigned index = 0; index < size; ++index)
+      {
+        if (index > 0)
+          *document_ << ", ";
+        *document_ << childValues_[index];
+      }
+      *document_ << " ]";
+    }
+  }
+}
+
+bool StyledStreamWriter::isMultineArray(const Value &value)
+{
+  ArrayIndex const size = value.size();
+  bool isMultiLine = size * 3 >= rightMargin_;
+  childValues_.clear();
+  for (ArrayIndex index = 0; index < size && !isMultiLine; ++index)
+  {
+    const Value &childValue = value[index];
+    isMultiLine = ((childValue.isArray() || childValue.isObject()) && childValue.size() > 0);
+  }
+  if (!isMultiLine) // check if line length > max line length
+  {
+    childValues_.reserve(size);
+    addChildValues_ = true;
+    ArrayIndex lineLength = 4 + (size - 1) * 2; // '[ ' + ', '*n + ' ]'
+    for (ArrayIndex index = 0; index < size; ++index)
+    {
+      if (hasCommentForValue(value[index]))
+      {
+        isMultiLine = true;
+      }
+      writeValue(value[index]);
+      lineLength += static_cast<ArrayIndex>(childValues_[index].length());
+    }
+    addChildValues_ = false;
+    isMultiLine = isMultiLine || lineLength >= rightMargin_;
+  }
+  return isMultiLine;
+}
+
+void StyledStreamWriter::pushValue(const JSONCPP_STRING &value)
+{
+  if (addChildValues_)
+    childValues_.push_back(value);
+  else
+    *document_ << value;
+}
+
+void StyledStreamWriter::writeIndent()
+{
+  // blep intended this to look at the so-far-written string
+  // to determine whether we are already indented, but
+  // with a stream we cannot do that. So we rely on some saved state.
+  // The caller checks indented_.
+  *document_ << '\n' << indentString_;
+}
+
+void StyledStreamWriter::writeWithIndent(const JSONCPP_STRING &value)
+{
+  if (!indented_)
+    writeIndent();
+  *document_ << value;
+  indented_ = false;
+}
+
+void StyledStreamWriter::indent() { indentString_ += indentation_; }
+
+void StyledStreamWriter::unindent()
+{
+  assert(indentString_.size() >= indentation_.size());
+  indentString_.resize(indentString_.size() - indentation_.size());
+}
+
+void StyledStreamWriter::writeCommentBeforeValue(const Value &root)
+{
+  if (!root.hasComment(commentBefore))
+    return;
+
+  if (!indented_)
+    writeIndent();
+  const JSONCPP_STRING &comment = root.getComment(commentBefore);
+  JSONCPP_STRING::const_iterator iter = comment.begin();
+  while (iter != comment.end())
+  {
+    *document_ << *iter;
+    if (*iter == '\n' && (iter != comment.end() && *(iter + 1) == '/'))
+      // writeIndent();  // would include newline
+      *document_ << indentString_;
+    ++iter;
+  }
+  indented_ = false;
+}
+
+void StyledStreamWriter::writeCommentAfterValueOnSameLine(const Value &root)
+{
+  if (root.hasComment(commentAfterOnSameLine))
+    *document_ << ' ' << root.getComment(commentAfterOnSameLine);
+
+  if (root.hasComment(commentAfter))
+  {
+    writeIndent();
+    *document_ << root.getComment(commentAfter);
+  }
+  indented_ = false;
+}
+
+bool StyledStreamWriter::hasCommentForValue(const Value &value)
+{
+  return value.hasComment(commentBefore) || value.hasComment(commentAfterOnSameLine) ||
+         value.hasComment(commentAfter);
+}
+
+//////////////////////////
+// BuiltStyledStreamWriter
+
+/// Scoped enums are not available until C++11.
+struct CommentStyle
+{
+  /// Decide whether to write comments.
+  enum Enum
+  {
+    None, ///< Drop all comments.
+    Most, ///< Recover odd behavior of previous versions (not implemented yet).
+    All   ///< Keep all comments.
+  };
+};
+
+struct BuiltStyledStreamWriter : public StreamWriter
+{
+  BuiltStyledStreamWriter(JSONCPP_STRING const &indentation, CommentStyle::Enum cs,
+                          JSONCPP_STRING const &colonSymbol, JSONCPP_STRING const &nullSymbol,
+                          JSONCPP_STRING const &endingLineFeedSymbol, bool useSpecialFloats,
+                          unsigned int precision);
+  int write(Value const &root, JSONCPP_OSTREAM *sout) JSONCPP_OVERRIDE;
+
+private:
+  void writeValue(Value const &value);
+  void writeArrayValue(Value const &value);
+  bool isMultineArray(Value const &value);
+  void pushValue(JSONCPP_STRING const &value);
+  void writeIndent();
+  void writeWithIndent(JSONCPP_STRING const &value);
+  void indent();
+  void unindent();
+  void writeCommentBeforeValue(Value const &root);
+  void writeCommentAfterValueOnSameLine(Value const &root);
+  static bool hasCommentForValue(const Value &value);
+
+  typedef std::vector<JSONCPP_STRING> ChildValues;
+
+  ChildValues childValues_;
+  JSONCPP_STRING indentString_;
+  unsigned int rightMargin_;
+  JSONCPP_STRING indentation_;
+  CommentStyle::Enum cs_;
+  JSONCPP_STRING colonSymbol_;
+  JSONCPP_STRING nullSymbol_;
+  JSONCPP_STRING endingLineFeedSymbol_;
+  bool addChildValues_ : 1;
+  bool indented_ : 1;
+  bool useSpecialFloats_ : 1;
+  unsigned int precision_;
+};
+BuiltStyledStreamWriter::BuiltStyledStreamWriter(JSONCPP_STRING const &indentation,
+                                                 CommentStyle::Enum cs,
+                                                 JSONCPP_STRING const &colonSymbol,
+                                                 JSONCPP_STRING const &nullSymbol,
+                                                 JSONCPP_STRING const &endingLineFeedSymbol,
+                                                 bool useSpecialFloats, unsigned int precision)
+    : rightMargin_(74), indentation_(indentation), cs_(cs), colonSymbol_(colonSymbol),
+      nullSymbol_(nullSymbol), endingLineFeedSymbol_(endingLineFeedSymbol), addChildValues_(false),
+      indented_(false), useSpecialFloats_(useSpecialFloats), precision_(precision)
+{
+}
+int BuiltStyledStreamWriter::write(Value const &root, JSONCPP_OSTREAM *sout)
+{
+  sout_ = sout;
+  addChildValues_ = false;
+  indented_ = true;
+  indentString_ = "";
+  writeCommentBeforeValue(root);
+  if (!indented_)
+    writeIndent();
+  indented_ = true;
+  writeValue(root);
+  writeCommentAfterValueOnSameLine(root);
+  *sout_ << endingLineFeedSymbol_;
+  sout_ = NULL;
+  return 0;
+}
+void BuiltStyledStreamWriter::writeValue(Value const &value)
+{
+  switch (value.type())
+  {
+    case nullValue:
+      pushValue(nullSymbol_);
+      break;
+    case intValue:
+      pushValue(valueToString(value.asLargestInt()));
+      break;
+    case uintValue:
+      pushValue(valueToString(value.asLargestUInt()));
+      break;
+    case realValue:
+      pushValue(valueToString(value.asDouble(), useSpecialFloats_, precision_));
+      break;
+    case stringValue:
+    {
+      // Is NULL is possible for value.string_? No.
+      char const *str;
+      char const *end;
+      bool ok = value.getString(&str, &end);
+      if (ok)
+        pushValue(valueToQuotedStringN(str, static_cast<unsigned>(end - str)));
+      else
+        pushValue("");
+      break;
+    }
+    case booleanValue:
+      pushValue(valueToString(value.asBool()));
+      break;
+    case arrayValue:
+      writeArrayValue(value);
+      break;
+    case objectValue:
+    {
+      Value::Members members(value.getMemberNames());
+      if (members.empty())
+        pushValue("{}");
+      else
+      {
+        writeWithIndent("{");
+        indent();
+        Value::Members::iterator it = members.begin();
+        for (;;)
+        {
+          JSONCPP_STRING const &name = *it;
+          Value const &childValue = value[name];
+          writeCommentBeforeValue(childValue);
+          writeWithIndent(valueToQuotedStringN(name.data(), static_cast<unsigned>(name.length())));
+          *sout_ << colonSymbol_;
+          writeValue(childValue);
+          if (++it == members.end())
+          {
+            writeCommentAfterValueOnSameLine(childValue);
+            break;
+          }
+          *sout_ << ",";
+          writeCommentAfterValueOnSameLine(childValue);
+        }
+        unindent();
+        writeWithIndent("}");
+      }
+    }
+    break;
+  }
+}
+
+void BuiltStyledStreamWriter::writeArrayValue(Value const &value)
+{
+  unsigned size = value.size();
+  if (size == 0)
+    pushValue("[]");
+  else
+  {
+    bool isMultiLine = (cs_ == CommentStyle::All) || isMultineArray(value);
+    if (isMultiLine)
+    {
+      writeWithIndent("[");
+      indent();
+      bool hasChildValue = !childValues_.empty();
+      unsigned index = 0;
+      for (;;)
+      {
+        Value const &childValue = value[index];
+        writeCommentBeforeValue(childValue);
+        if (hasChildValue)
+          writeWithIndent(childValues_[index]);
+        else
+        {
+          if (!indented_)
+            writeIndent();
+          indented_ = true;
+          writeValue(childValue);
+          indented_ = false;
+        }
+        if (++index == size)
+        {
+          writeCommentAfterValueOnSameLine(childValue);
+          break;
+        }
+        *sout_ << ",";
+        writeCommentAfterValueOnSameLine(childValue);
+      }
+      unindent();
+      writeWithIndent("]");
+    }
+    else // output on a single line
+    {
+      assert(childValues_.size() == size);
+      *sout_ << "[";
+      if (!indentation_.empty())
+        *sout_ << " ";
+      for (unsigned index = 0; index < size; ++index)
+      {
+        if (index > 0)
+          *sout_ << ((!indentation_.empty()) ? ", " : ",");
+        *sout_ << childValues_[index];
+      }
+      if (!indentation_.empty())
+        *sout_ << " ";
+      *sout_ << "]";
+    }
+  }
+}
+
+bool BuiltStyledStreamWriter::isMultineArray(Value const &value)
+{
+  ArrayIndex const size = value.size();
+  bool isMultiLine = size * 3 >= rightMargin_;
+  childValues_.clear();
+  for (ArrayIndex index = 0; index < size && !isMultiLine; ++index)
+  {
+    Value const &childValue = value[index];
+    isMultiLine = ((childValue.isArray() || childValue.isObject()) && childValue.size() > 0);
+  }
+  if (!isMultiLine) // check if line length > max line length
+  {
+    childValues_.reserve(size);
+    addChildValues_ = true;
+    ArrayIndex lineLength = 4 + (size - 1) * 2; // '[ ' + ', '*n + ' ]'
+    for (ArrayIndex index = 0; index < size; ++index)
+    {
+      if (hasCommentForValue(value[index]))
+      {
+        isMultiLine = true;
+      }
+      writeValue(value[index]);
+      lineLength += static_cast<ArrayIndex>(childValues_[index].length());
+    }
+    addChildValues_ = false;
+    isMultiLine = isMultiLine || lineLength >= rightMargin_;
+  }
+  return isMultiLine;
+}
+
+void BuiltStyledStreamWriter::pushValue(JSONCPP_STRING const &value)
+{
+  if (addChildValues_)
+    childValues_.push_back(value);
+  else
+    *sout_ << value;
+}
+
+void BuiltStyledStreamWriter::writeIndent()
+{
+  // blep intended this to look at the so-far-written string
+  // to determine whether we are already indented, but
+  // with a stream we cannot do that. So we rely on some saved state.
+  // The caller checks indented_.
+
+  if (!indentation_.empty())
+  {
+    // In this case, drop newlines too.
+    *sout_ << '\n' << indentString_;
+  }
+}
+
+void BuiltStyledStreamWriter::writeWithIndent(JSONCPP_STRING const &value)
+{
+  if (!indented_)
+    writeIndent();
+  *sout_ << value;
+  indented_ = false;
+}
+
+void BuiltStyledStreamWriter::indent() { indentString_ += indentation_; }
+
+void BuiltStyledStreamWriter::unindent()
+{
+  assert(indentString_.size() >= indentation_.size());
+  indentString_.resize(indentString_.size() - indentation_.size());
+}
+
+void BuiltStyledStreamWriter::writeCommentBeforeValue(Value const &root)
+{
+  if (cs_ == CommentStyle::None)
+    return;
+  if (!root.hasComment(commentBefore))
+    return;
+
+  if (!indented_)
+    writeIndent();
+  const JSONCPP_STRING &comment = root.getComment(commentBefore);
+  JSONCPP_STRING::const_iterator iter = comment.begin();
+  while (iter != comment.end())
+  {
+    *sout_ << *iter;
+    if (*iter == '\n' && (iter != comment.end() && *(iter + 1) == '/'))
+      // writeIndent();  // would write extra newline
+      *sout_ << indentString_;
+    ++iter;
+  }
+  indented_ = false;
+}
+
+void BuiltStyledStreamWriter::writeCommentAfterValueOnSameLine(Value const &root)
+{
+  if (cs_ == CommentStyle::None)
+    return;
+  if (root.hasComment(commentAfterOnSameLine))
+    *sout_ << " " + root.getComment(commentAfterOnSameLine);
+
+  if (root.hasComment(commentAfter))
+  {
+    writeIndent();
+    *sout_ << root.getComment(commentAfter);
+  }
+}
+
+// static
+bool BuiltStyledStreamWriter::hasCommentForValue(const Value &value)
+{
+  return value.hasComment(commentBefore) || value.hasComment(commentAfterOnSameLine) ||
+         value.hasComment(commentAfter);
+}
+
+///////////////
+// StreamWriter
+
+StreamWriter::StreamWriter() : sout_(NULL) {}
+StreamWriter::~StreamWriter() {}
+StreamWriter::Factory::~Factory() {}
+StreamWriterBuilder::StreamWriterBuilder() { setDefaults(&settings_); }
+StreamWriterBuilder::~StreamWriterBuilder() {}
+StreamWriter *StreamWriterBuilder::newStreamWriter() const
+{
+  JSONCPP_STRING indentation = settings_["indentation"].asString();
+  JSONCPP_STRING cs_str = settings_["commentStyle"].asString();
+  bool eyc = settings_["enableYAMLCompatibility"].asBool();
+  bool dnp = settings_["dropNullPlaceholders"].asBool();
+  bool usf = settings_["useSpecialFloats"].asBool();
+  unsigned int pre = settings_["precision"].asUInt();
+  CommentStyle::Enum cs = CommentStyle::All;
+  if (cs_str == "All")
+  {
+    cs = CommentStyle::All;
+  }
+  else if (cs_str == "None")
+  {
+    cs = CommentStyle::None;
+  }
+  else
+  {
+    throwRuntimeError("commentStyle must be 'All' or 'None'");
+  }
+  JSONCPP_STRING colonSymbol = " : ";
+  if (eyc)
+  {
+    colonSymbol = ": ";
+  }
+  else if (indentation.empty())
+  {
+    colonSymbol = ":";
+  }
+  JSONCPP_STRING nullSymbol = "null";
+  if (dnp)
+  {
+    nullSymbol = "";
+  }
+  if (pre > 17)
+    pre = 17;
+  JSONCPP_STRING endingLineFeedSymbol = "";
+  return new BuiltStyledStreamWriter(indentation, cs, colonSymbol, nullSymbol, endingLineFeedSymbol,
+                                     usf, pre);
+}
+static void getValidWriterKeys(std::set<JSONCPP_STRING> *valid_keys)
+{
+  valid_keys->clear();
+  valid_keys->insert("indentation");
+  valid_keys->insert("commentStyle");
+  valid_keys->insert("enableYAMLCompatibility");
+  valid_keys->insert("dropNullPlaceholders");
+  valid_keys->insert("useSpecialFloats");
+  valid_keys->insert("precision");
+}
+bool StreamWriterBuilder::validate(Json::Value *invalid) const
+{
+  Json::Value my_invalid;
+  if (!invalid)
+    invalid = &my_invalid; // so we do not need to test for NULL
+  Json::Value &inv = *invalid;
+  std::set<JSONCPP_STRING> valid_keys;
+  getValidWriterKeys(&valid_keys);
+  Value::Members keys = settings_.getMemberNames();
+  size_t n = keys.size();
+  for (size_t i = 0; i < n; ++i)
+  {
+    JSONCPP_STRING const &key = keys[i];
+    if (valid_keys.find(key) == valid_keys.end())
+    {
+      inv[key] = settings_[key];
+    }
+  }
+  return 0u == inv.size();
+}
+Value &StreamWriterBuilder::operator[](JSONCPP_STRING key) { return settings_[key]; }
+// static
+void StreamWriterBuilder::setDefaults(Json::Value *settings)
+{
+  //! [StreamWriterBuilderDefaults]
+  (*settings)["commentStyle"] = "All";
+  (*settings)["indentation"] = "\t";
+  (*settings)["enableYAMLCompatibility"] = false;
+  (*settings)["dropNullPlaceholders"] = false;
+  (*settings)["useSpecialFloats"] = false;
+  (*settings)["precision"] = 17;
+  //! [StreamWriterBuilderDefaults]
+}
+
+JSONCPP_STRING writeString(StreamWriter::Factory const &builder, Value const &root)
+{
+  JSONCPP_OSTRINGSTREAM sout;
+  StreamWriterPtr const writer(builder.newStreamWriter());
+  writer->write(root, &sout);
+  return sout.str();
+}
+
+JSONCPP_OSTREAM &operator<<(JSONCPP_OSTREAM &sout, Value const &root)
+{
+  StreamWriterBuilder builder;
+  StreamWriterPtr const writer(builder.newStreamWriter());
+  writer->write(root, &sout);
+  return sout;
+}
+
+} // namespace Json
+
+// //////////////////////////////////////////////////////////////////////
+// End of content of file: src/lib_json/json_writer.cpp
+// //////////////////////////////////////////////////////////////////////
diff --git a/runtime/libs/misc/CMakeLists.txt b/runtime/libs/misc/CMakeLists.txt
new file mode 100644
index 000000000..557d403ec
--- /dev/null
+++ b/runtime/libs/misc/CMakeLists.txt
@@ -0,0 +1,11 @@
+# Library `nnfw_lib_misc`
+file(GLOB_RECURSE NNFW_UTILITY_SRCS "src/*.cpp")
+
+add_library(nnfw_lib_misc STATIC ${NNFW_UTILITY_SRCS})
+target_include_directories(nnfw_lib_misc PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/include)
+set_target_properties(nnfw_lib_misc PROPERTIES POSITION_INDEPENDENT_CODE ON)
+target_link_libraries(nnfw_lib_misc PRIVATE nnfw_common)
+target_link_libraries(nnfw_lib_misc PRIVATE nnfw_coverage)
+
+add_executable(nnfw_tensor_index_iterator "examples/tensor_index_iterator.cpp")
+target_link_libraries(nnfw_tensor_index_iterator nnfw_lib_misc)
diff --git a/runtime/libs/misc/examples/tensor_index_iterator.cpp b/runtime/libs/misc/examples/tensor_index_iterator.cpp
new file mode 100644
index 000000000..d94da9f49
--- /dev/null
+++ b/runtime/libs/misc/examples/tensor_index_iterator.cpp
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "misc/tensor/IndexIterator.h"
+
+#include <array>
+
+#include <iostream>
+#include <algorithm>
+
+#include <cassert>
+
+void test_iterate(void)
+{
+  const nnfw::misc::tensor::Shape shape{3, 4, 7};
+
+  std::array<int, 3 * 4 * 7> array;
+
+  array.fill(0);
+
+  using nnfw::misc::tensor::iterate;
+  using nnfw::misc::tensor::Index;
+
+  iterate(shape) << [&](const Index &index) {
+    assert(index.rank() == shape.rank());
+
+    const uint32_t rank = index.rank();
+
+    uint32_t offset = index.at(0);
+
+    for (uint32_t axis = 1; axis < rank; ++axis)
+    {
+      offset *= shape.dim(axis);
+      offset += index.at(axis);
+    }
+
+    array[offset] += 1;
+  };
+
+  assert(std::all_of(array.begin(), array.end(), [](int num) { return num == 1; }));
+}
+
+int main(int argc, char **argv)
+{
+  test_iterate();
+
+  nnfw::misc::tensor::Shape shape{3, 4, 3, 4};
+
+  std::cout << "Iterate over tensor{3, 4, 3, 4}" << std::endl;
+
+  nnfw::misc::tensor::iterate(shape) << [](const nnfw::misc::tensor::Index &index) {
+    std::cout << "rank: " << index.rank() << std::endl;
+
+    for (uint32_t d = 0; d < index.rank(); ++d)
+    {
+      std::cout << "  offset(" << d << ") = " << index.at(d) << std::endl;
+    }
+  };
+
+  return 0;
+}
diff --git a/runtime/libs/misc/include/misc/EnvVar.h b/runtime/libs/misc/include/misc/EnvVar.h
new file mode 100644
index 000000000..db28a3c7d
--- /dev/null
+++ b/runtime/libs/misc/include/misc/EnvVar.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file EnvVar.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief This file contains nnfw::misc::EnvVar class
+ */
+
+#ifndef __NNFW_MISC_ENV_VAR__
+#define __NNFW_MISC_ENV_VAR__
+
+#include <algorithm>
+#include <array>
+#include <cstdlib>
+#include <string>
+
+namespace nnfw
+{
+namespace misc
+{
+/**
+ * @brief Class to access environment variable
+ */
+class EnvVar
+{
+public:
+  /**
+   * @brief Construct a new EnvVar object
+   * @param[in] key   environment variable
+   */
+  EnvVar(const std::string &key)
+  {
+    const char *value = std::getenv(key.c_str());
+    if (value == nullptr)
+    {
+      // An empty string is considered as an empty value
+      _value = "";
+    }
+    else
+    {
+      _value = value;
+    }
+  }
+
+  /**
+   * @brief Get environment variable of string type
+   * @param[in] def   Default value of environment variable
+   * @return Defaut value passed as a parameter when there is no environment variable,
+   *         otherwise the value of environment variable passed into constructor
+   */
+  std::string asString(const std::string &def) const
+  {
+    if (_value.empty())
+      return def;
+    return _value;
+  }
+
+  /**
+   * @brief Get environment variable of boolean type
+   * @param[in] def   Default value of environment variable
+   * @return Defaut value passed as a parameter when there is no environment variable,
+   *         otherwise the value of environment variable passed into constructor
+   */
+  bool asBool(bool def) const
+  {
+    if (_value.empty())
+      return def;
+    static const std::array<std::string, 5> false_list{"0", "OFF", "FALSE", "N", "NO"};
+    auto false_found = std::find(false_list.begin(), false_list.end(), _value);
+    return (false_found == false_list.end());
+  }
+
+  /**
+   * @brief Get environment variable of int type
+   * @param[in] def   Default value of environment variable
+   * @return Defaut value passed as a parameter when there is no environment variable,
+   *         otherwise the value of environment variable passed into constructor
+   */
+  int asInt(int def) const
+  {
+    if (_value.empty())
+      return def;
+    return std::stoi(_value);
+  }
+
+  /**
+   * @brief Get environment variable of float type
+   * @param[in] def   Default value of environment variable
+   * @return Defaut value passed as a parameter when there is no environment variable,
+   *         otherwise the value of environment variable passed into constructor
+   */
+  float asFloat(float def) const
+  {
+    if (_value.empty())
+      return def;
+    return std::stof(_value);
+  }
+
+private:
+  std::string _value;
+};
+
+} // namespace misc
+} // namespace nnfw
+
+#endif // __NNFW_MISC_ENV_VAR__
diff --git a/runtime/libs/misc/include/misc/EventCollector.h b/runtime/libs/misc/include/misc/EventCollector.h
new file mode 100644
index 000000000..530a90906
--- /dev/null
+++ b/runtime/libs/misc/include/misc/EventCollector.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __EVENT_COLLECTOR_H__
+#define __EVENT_COLLECTOR_H__
+
+#include "misc/EventRecorder.h"
+
+class EventCollector
+{
+public:
+  enum class Edge
+  {
+    BEGIN,
+    END
+  };
+
+  struct Event
+  {
+    Edge edge;
+    std::string backend;
+    std::string label;
+  };
+
+public:
+  EventCollector(EventRecorder *rec) : _rec{rec}
+  {
+    // DO NOTHING
+  }
+
+public:
+  void onEvent(const Event &event);
+
+protected:
+  EventRecorder *_rec;
+};
+
+#endif // __EVENT_COLLECTOR_H__
diff --git a/runtime/libs/misc/include/misc/EventRecorder.h b/runtime/libs/misc/include/misc/EventRecorder.h
new file mode 100644
index 000000000..1e621fdf8
--- /dev/null
+++ b/runtime/libs/misc/include/misc/EventRecorder.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __EVENT_RECORDER_H__
+#define __EVENT_RECORDER_H__
+
+#include <map>
+#include <memory>
+#include <mutex>
+
+#include <ostream>
+#include <sstream>
+
+struct Event
+{
+  std::string name;
+  std::string tid;
+  std::string ph; /* REQUIRED */
+  std::string ts; /* REQUIRED */
+};
+
+struct DurationEvent : public Event
+{
+  // TO BE FILLED
+};
+
+struct CounterEvent : public Event
+{
+  std::map<std::string, std::string> values;
+};
+
+//
+// Record Event as Chrome Trace Event File Format
+//
+// Refrence: https://docs.google.com/document/d/1CvAClvFfyA5R-PhYUmn5OOQtYMH4h6I0nSsKchNAySU/edit
+//
+class EventRecorder
+{
+public:
+  EventRecorder() = default;
+
+public:
+  void emit(const DurationEvent &evt);
+  void emit(const CounterEvent &evt);
+
+public:
+  void writeToFile(std::ostream &os);
+
+private:
+  std::mutex _mu;
+  std::stringstream _ss;
+};
+
+#endif // __EVENT_RECORDER_H__
diff --git a/runtime/libs/misc/include/misc/benchmark.h b/runtime/libs/misc/include/misc/benchmark.h
new file mode 100644
index 000000000..fe5b97585
--- /dev/null
+++ b/runtime/libs/misc/include/misc/benchmark.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file benchmark.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief This file contains nnfw::misc::benchmark::Accumulator class
+ */
+#ifndef __NNFW_MISC_BENCHMARK_H__
+#define __NNFW_MISC_BENCHMARK_H__
+
+#include <chrono>
+
+namespace nnfw
+{
+namespace misc
+{
+// Benckmark support
+namespace benchmark
+{
+
+/**
+ * @brief Class to accumulate time during benchmark
+ */
+template <typename T> class Accumulator
+{
+public:
+  /**
+   * @brief Construct a new Accumulator object
+   * @param[in] ref   Object to keep time duration
+   */
+  Accumulator(T &ref) : _ref(ref)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Return the reference of @c ref passed to constructor
+   * @return Reference of @c ref
+   */
+  T &operator()(void) { return _ref; }
+
+private:
+  T &_ref;
+};
+
+/**
+ * @brief Run passed function and returns accumulated time
+ * @tparam T            Period used by @c std::chrono::duration_cast
+ * @tparam Callable     Function type to benchmark
+ * @param[in] acc       Accumulated time after running @cb
+ * @param[in] cb        Function to run and benchmark
+ * @return Accumulated time
+ */
+template <typename T, typename Callable>
+Accumulator<T> &operator<<(Accumulator<T> &&acc, Callable cb)
+{
+  auto begin = std::chrono::steady_clock::now();
+  cb();
+  auto end = std::chrono::steady_clock::now();
+
+  acc() += std::chrono::duration_cast<T>(end - begin);
+
+  return acc;
+}
+
+template <typename T> Accumulator<T> measure(T &out) { return Accumulator<T>(out); }
+
+} // namespace benchmark
+} // namespace misc
+} // namespace nnfw
+
+#endif // __NNFW_MISC_BENCHMARK_H__
diff --git a/runtime/libs/misc/include/misc/feature/Index.h b/runtime/libs/misc/include/misc/feature/Index.h
new file mode 100644
index 000000000..a361d8dd2
--- /dev/null
+++ b/runtime/libs/misc/include/misc/feature/Index.h
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     Index.h
+ * @brief    This file contains Index class
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_MISC_FEATURE_INDEX_H__
+#define __NNFW_MISC_FEATURE_INDEX_H__
+
+#include <cstdint>
+
+namespace nnfw
+{
+namespace misc
+{
+namespace feature
+{
+
+/**
+ * @brief  Class to have the index information for calculating the offset.
+ */
+class Index
+{
+public:
+  /**
+   * @brief  Construct Index object using default constrcutor
+   */
+  Index() = default;
+
+public:
+  /**
+   * @brief  Construct Index object with three indexes of dimensions
+   * @param[in]  ch    The depth index
+   * @param[in]  row   The heigth index
+   * @param[in]  col   The width index
+   */
+  Index(int32_t ch, int32_t row, int32_t col) : _batch{1}, _ch{ch}, _row{row}, _col{col}
+  {
+    // DO NOTHING
+  }
+  /**
+   * @brief  Construct Index object with four indexes of dimensions
+   * @param[in]  batch The batch index
+   * @param[in]  ch    The depth index
+   * @param[in]  row   The height index
+   * @param[in]  col   The width index
+   */
+  Index(int32_t batch, int32_t ch, int32_t row, int32_t col)
+      : _batch{batch}, _ch{ch}, _row{row}, _col{col}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief   Get the batch index
+   * @return  The batch index
+   */
+  int32_t batch(void) const { return _batch; }
+  /**
+   * @brief   Get the depth index
+   * @return  The depth index
+   */
+  int32_t ch(void) const { return _ch; }
+  /**
+   * @brief   Get the height index
+   * @return  The height index
+   */
+  int32_t row(void) const { return _row; }
+  /**
+   * @brief   Get the width index
+   * @return  The width index
+   */
+  int32_t col(void) const { return _col; }
+
+public:
+  /**
+   * @brief   Get the batch index as the lvalue reference
+   * @return  The reference of the batch value
+   */
+  int32_t &batch(void) { return _batch; }
+  /**
+   * @brief   Get the depth index as the lvalue reference
+   * @return  The reference of the depth value
+   */
+  int32_t &ch(void) { return _ch; }
+  /**
+   * @brief   Get the height index as the lvalue reference
+   * @return  The reference of the height value
+   */
+  int32_t &row(void) { return _row; }
+  /**
+   * @brief   Get the width index as the lvalue reference
+   * @return  The reference of the width value
+   */
+  int32_t &col(void) { return _col; }
+
+private:
+  /**
+   * @brief  The batch index
+   */
+  int32_t _batch;
+  /**
+   * @brief  The depth index
+   */
+  int32_t _ch;
+  /**
+   * @brief  The height index
+   */
+  int32_t _row;
+  /**
+   * @brief  The width index
+   */
+  int32_t _col;
+};
+
+} // namespace feature
+} // namespace misc
+} // namespace nnfw
+
+#endif // __NNFW_MISC_FEATURE_INDEX_H__
diff --git a/runtime/libs/misc/include/misc/feature/IndexIterator.h b/runtime/libs/misc/include/misc/feature/IndexIterator.h
new file mode 100644
index 000000000..1cf675526
--- /dev/null
+++ b/runtime/libs/misc/include/misc/feature/IndexIterator.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     IndexIterator.h
+ * @brief    This file contains IndexIterator class
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_MISC_FEATURE_INDEX_ITERATOR_H__
+#define __NNFW_MISC_FEATURE_INDEX_ITERATOR_H__
+
+#include "misc/feature/Shape.h"
+
+namespace nnfw
+{
+namespace misc
+{
+namespace feature
+{
+
+/**
+ * @brief  Class to iterate Callable with Index of feature
+ */
+class IndexIterator
+{
+public:
+  /**
+   * @brief  Construct IndexIterator object with Shape of feature
+   * @param[in]  shape   Shape reference of feature
+   */
+  IndexIterator(const Shape &shape) : _shape{shape}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief   Call a function iterated
+   * @param[in]   cb     A callback function
+   * @return  Current IndexIterator object
+   */
+  template <typename Callable> IndexIterator &iter(Callable cb)
+  {
+    for (int32_t batch = 0; batch < _shape.N; ++batch)
+    {
+      for (int32_t ch = 0; ch < _shape.C; ++ch)
+      {
+        for (int32_t row = 0; row < _shape.H; ++row)
+        {
+          for (int32_t col = 0; col < _shape.W; ++col)
+          {
+            cb(batch, ch, row, col);
+          }
+        }
+      }
+    }
+
+    return (*this);
+  }
+
+private:
+  /**
+   * @brief   Shape for feature
+   */
+  const Shape _shape;
+};
+
+/**
+ * @brief   Create an object of IndexIterator for feature
+ * @param[in]   Shape   reference of feature
+ * @return  Created IndexIterator object
+ */
+static inline IndexIterator iterate(const Shape &shape) { return IndexIterator{shape}; }
+
+/**
+ * @brief   Call a function iterated using IndexIterator of feature
+ *          Overloaded operator<<
+ * @param[in]   it    An IndexIterator reference
+ * @param[in]   cb    A callback function
+ * @return  created IndexIterator object
+ */
+template <typename Callable> IndexIterator &operator<<(IndexIterator &&it, Callable cb)
+{
+  return it.iter(cb);
+}
+
+} // namespace feature
+} // namespace misc
+} // namespace nnfw
+
+#endif // __NNFW_MISC_FEATURE_INDEX_ITERATOR_H__
diff --git a/runtime/libs/misc/include/misc/feature/Object.h b/runtime/libs/misc/include/misc/feature/Object.h
new file mode 100644
index 000000000..7af0e28f4
--- /dev/null
+++ b/runtime/libs/misc/include/misc/feature/Object.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     Object.h
+ * @brief    This file contains Object class
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_MISC_FEATURE_OBJECT_H__
+#define __NNFW_MISC_FEATURE_OBJECT_H__
+
+#include "misc/feature/Shape.h"
+#include "misc/feature/Index.h"
+#include "misc/feature/Reader.h"
+
+#include <vector>
+
+namespace nnfw
+{
+namespace misc
+{
+namespace feature
+{
+
+/**
+ * @brief  Class to have information of the operand for feature
+ */
+template <typename T> class Object final : public Reader<T>
+{
+public:
+  using Generator = std::function<T(const Shape &shape, const Index &index)>;
+
+public:
+  /**
+   * @brief  Construct Object object with Shape of feature and set value used by Generator
+   * @param[in]  shape   Reference of Shape for feature
+   * @param[in]  fn      A function to set values of operand tensor
+   */
+  Object(const Shape &shape, const Generator &fn) : _shape{shape}
+  {
+    _value.resize(_shape.C * _shape.H * _shape.W);
+
+    for (int32_t ch = 0; ch < _shape.C; ++ch)
+    {
+      for (int32_t row = 0; row < _shape.H; ++row)
+      {
+        for (int32_t col = 0; col < _shape.W; ++col)
+        {
+          _value.at(offsetOf(ch, row, col)) = fn(_shape, Index{ch, row, col});
+        }
+      }
+    }
+  }
+
+public:
+  /**
+   * @brief   Get Shape of feature as the reference
+   * @return  The reference of the width value
+   */
+  const Shape &shape(void) const { return _shape; }
+
+public:
+  /**
+   * @brief   Get the value used by three indexes
+   * @param[in]   ch   The depth index
+   * @param[in]   row  The height index
+   * @param[in]   col  The width index
+   * @return  The value at the offset
+   */
+  T at(uint32_t ch, uint32_t row, uint32_t col) const override
+  {
+    return _value.at(offsetOf(ch, row, col));
+  }
+
+private:
+  /**
+   * @brief   Get the offset value at three indexes
+   * @param[in]   ch   The depth index
+   * @param[in]   row  The height index
+   * @param[in]   col  The width index
+   * @return  The offset value
+   */
+  uint32_t offsetOf(uint32_t ch, uint32_t row, uint32_t col) const
+  {
+    return ch * _shape.H * _shape.W + row * _shape.W + col;
+  }
+
+private:
+  /**
+   * @brief   Shape of operand
+   */
+  Shape _shape;
+  /**
+   * @brief   The tensor vector of operand
+   */
+  std::vector<T> _value;
+};
+
+} // namespace feature
+} // namespace misc
+} // namespace nnfw
+
+#endif // __NNFW_MISC_FEATURE_OBJECT_H__
diff --git a/runtime/libs/misc/include/misc/feature/Reader.h b/runtime/libs/misc/include/misc/feature/Reader.h
new file mode 100644
index 000000000..b09209789
--- /dev/null
+++ b/runtime/libs/misc/include/misc/feature/Reader.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     Reader.h
+ * @brief    This file contains Reader class
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_MISC_FEATURE_READER_H__
+#define __NNFW_MISC_FEATURE_READER_H__
+
+#include <cstdint>
+
+namespace nnfw
+{
+namespace misc
+{
+namespace feature
+{
+
+/**
+ * @brief  Class reads values of feature
+ *         The interface class
+ */
+template <typename T> struct Reader
+{
+  /**
+   * @brief  Destruct Reader object using default destructor
+   */
+  virtual ~Reader() = default;
+
+  /**
+   * @brief   Get the value used by three indexes
+   * @param[in]  ch    The depth index
+   * @param[in]  row   The height index
+   * @param[in]  col   The width index
+   * @return  The value at the offset
+   */
+  virtual T at(uint32_t ch, uint32_t row, uint32_t col) const = 0;
+  /**
+   * @brief   Get the value used by four indexes
+   * @param[in]  batch The batch index
+   * @param[in]  ch    The depth index
+   * @param[in]  row   The height index
+   * @param[in]  col   The width index
+   * @return  The value at the offset
+   */
+  virtual T at(uint32_t batch, uint32_t ch, uint32_t row, uint32_t col) const = 0;
+};
+
+} // namespace feature
+} // namespace misc
+} // namespace nnfw
+
+#endif // __NNFW_MISC_FEATURE_READER_H__
diff --git a/runtime/libs/misc/include/misc/feature/Shape.h b/runtime/libs/misc/include/misc/feature/Shape.h
new file mode 100644
index 000000000..09881f58b
--- /dev/null
+++ b/runtime/libs/misc/include/misc/feature/Shape.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     Shape.h
+ * @brief    This file contains Shape class for feature
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_MISC_FEATURE_SHAPE_H__
+#define __NNFW_MISC_FEATURE_SHAPE_H__
+
+#include <cstdint>
+
+namespace nnfw
+{
+namespace misc
+{
+namespace feature
+{
+
+/**
+ * @brief  Structure to have values of dimensions for feature
+ */
+struct Shape
+{
+  int32_t N; /**< The batch value  */
+  int32_t C; /**< The depth value  */
+  int32_t H; /**< The height value */
+  int32_t W; /**< The width value  */
+
+  /**
+   * @brief  Construct Shape object using default constrcutor
+   */
+  Shape() = default;
+  /**
+   * @brief  Construct Shape object with three values of dimensions
+   * @param[in]  depth  The depth value
+   * @param[in]  height The height value
+   * @param[in]  width  The width value
+   */
+  Shape(int32_t depth, int32_t height, int32_t width) : N{1}, C{depth}, H{height}, W{width}
+  {
+    // DO NOTHING
+  }
+  /**
+   * @brief  Construct Shape object with four values of dimensions
+   * @param[in]  batch  The batch value
+   * @param[in]  depth  The depth value
+   * @param[in]  height The height value
+   * @param[in]  width  The width value
+   */
+  Shape(int32_t batch, int32_t depth, int32_t height, int32_t width)
+      : N{batch}, C{depth}, H{height}, W{width}
+  {
+    // DO NOTHING
+  }
+};
+
+} // namespace feature
+} // namespace misc
+} // namespace nnfw
+
+#endif // __NNFW_MISC_FEATURE_H__
diff --git a/runtime/libs/misc/include/misc/feature/TextFormatter.h b/runtime/libs/misc/include/misc/feature/TextFormatter.h
new file mode 100644
index 000000000..e053f1c61
--- /dev/null
+++ b/runtime/libs/misc/include/misc/feature/TextFormatter.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     TextFormatter.h
+ * @brief    This file contains TextFormatter class
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_MISC_FEATURE_TEXT_FORMATTER_H__
+#define __NNFW_MISC_FEATURE_TEXT_FORMATTER_H__
+
+#include "misc/feature/Shape.h"
+#include "misc/feature/Reader.h"
+
+#include <ostream>
+#include <iomanip>
+#include <limits>
+
+namespace nnfw
+{
+namespace misc
+{
+namespace feature
+{
+
+/**
+ * @brief   Class to print operand of feature to ostream in the given string format
+ */
+template <typename T> class TextFormatter
+{
+public:
+  /**
+   * @brief  Construct TextFormatter object with an operand's information.
+   * @param[in]  shape  The shape of an operand
+   * @param[in]  data   The data of an operand
+   */
+  TextFormatter(const Shape &shape, const Reader<T> &data) : _shape(shape), _data(data)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief   Get Shape of feature as the lvalue reference
+   * @return  Shape of feature
+   */
+  const Shape &shape(void) const { return _shape; }
+  /**
+   * @brief   Get Reader<T> that can read the data of an operand
+   * @return  Reader<T>
+   */
+  const Reader<T> &data(void) const { return _data; }
+
+private:
+  /**
+   * @brief   Shape of feature
+   */
+  const Shape &_shape;
+  /**
+   * @brief   Reader<T> that can read the data of an operand
+   */
+  const Reader<T> &_data;
+};
+
+/**
+ * @brief   Print operand of feature
+ * @param[in]   os   Standard output stream
+ * @param[in]   fmt  TextFormatter to print information of an operand
+ * @return  Standard output stream
+ */
+template <typename T> std::ostream &operator<<(std::ostream &os, const TextFormatter<T> &fmt)
+{
+  const auto &shape = fmt.shape();
+
+  for (uint32_t ch = 0; ch < shape.C; ++ch)
+  {
+    os << "  Channel " << ch << ":" << std::endl;
+    for (uint32_t row = 0; row < shape.H; ++row)
+    {
+      os << "    ";
+      for (uint32_t col = 0; col < shape.W; ++col)
+      {
+        const auto value = fmt.data().at(ch, row, col);
+        os << std::right;
+        os << std::fixed;
+        os << std::setw(std::numeric_limits<T>::digits10 + 2);
+        os << std::setprecision(5);
+        os << value;
+        os << " ";
+      }
+      os << std::endl;
+    }
+  }
+
+  return os;
+}
+
+} // namespace feature
+} // namespace misc
+} // namespace nnfw
+
+#endif // __NNFW_MISC_FEATURE_TEXT_FORMATTER_H__
diff --git a/runtime/libs/misc/include/misc/fp32.h b/runtime/libs/misc/include/misc/fp32.h
new file mode 100644
index 000000000..c310402ba
--- /dev/null
+++ b/runtime/libs/misc/include/misc/fp32.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     fp32.h
+ * @brief    This file contains functions to compare float values
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_MISC_FP32_H__
+#define __NNFW_MISC_FP32_H__
+
+#include <cmath>
+#include <cfloat>
+#include <algorithm>
+#include <cstdint>
+
+namespace nnfw
+{
+namespace misc
+{
+namespace fp32
+{
+
+/**
+ * @brief   Get the difference between two float values as a relative value.
+ * @param[in]   lhs   A float value to be compared
+ * @param[in]   rhs   A float value to be compared
+ * @return  A relative value of difference between two float values.
+ */
+inline float relative_diff(float lhs, float rhs)
+{
+  const auto diff = std::fabs(lhs - rhs);
+  const auto base = std::max(std::fabs(lhs), std::fabs(rhs));
+
+  return diff / base;
+}
+
+/**
+ * @brief   Verify that an obtained float value is equal to the expected float value
+ *          by using FLT_EPSILON
+ * @param[in]   expected   An expected float value to be compared
+ * @param[in]   obtained   An obtained float value to be compared
+ * @param[in]   tolerance  A tolerance value
+ * @return  @c true if both values are equal, otherwise @c false
+ */
+inline bool epsilon_equal(float expected, float obtained, uint32_t tolerance = 1)
+{
+  if (std::isnan(expected) && std::isnan(obtained))
+  {
+    return true;
+  }
+
+  // Let's use relative epsilon comparision
+  const auto diff = std::fabs(expected - obtained);
+  const auto max = std::max(std::fabs(expected), std::fabs(obtained));
+
+  return diff <= (max * FLT_EPSILON * tolerance);
+}
+
+/**
+ * @brief   Verify that an obtained float value is equal to the expected float value
+ *          by comparing absolute tolerance value
+ * @param[in]   expected   An expected float value to be compared
+ * @param[in]   obtained   An obtained float value to be compared
+ * @param[in]   tolerance  A tolerance value
+ * @return  @c true if both values are equal, otherwise @c false
+ */
+inline bool absolute_epsilon_equal(float expected, float obtained, float tolerance = 0.001)
+{
+  if (std::isnan(expected) && std::isnan(obtained))
+  {
+    return true;
+  }
+
+  // Let's use absolute epsilon comparision
+  const auto diff = std::fabs(expected - obtained);
+
+  return diff <= tolerance;
+}
+
+} // namespace fp32
+} // namespace misc
+} // namespace nnfw
+
+#endif // __NNFW_MISC_FP32_H__
diff --git a/runtime/libs/misc/include/misc/kernel/IndexIterator.h b/runtime/libs/misc/include/misc/kernel/IndexIterator.h
new file mode 100644
index 000000000..59e0f0095
--- /dev/null
+++ b/runtime/libs/misc/include/misc/kernel/IndexIterator.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     IndexIterator.h
+ * @brief    This file contains IndexIterator class
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_MISC_KERNEL_INDEX_ITERATOR_H__
+#define __NNFW_MISC_KERNEL_INDEX_ITERATOR_H__
+
+#include "misc/kernel/Shape.h"
+
+namespace nnfw
+{
+namespace misc
+{
+namespace kernel
+{
+
+/**
+ * @brief Class to iterate Callable with Index of kernel
+ */
+class IndexIterator
+{
+public:
+  /**
+   * @brief Construct IndexIterator object with Shape of kernel
+   * @param[in] shape Shape reference of feature
+   */
+  IndexIterator(const Shape &shape) : _shape{shape}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Call a function iterated
+   * @param[in] cb A callback function
+   * @return Current IndexIterator object
+   */
+  template <typename Callable> IndexIterator &iter(Callable cb)
+  {
+    for (int32_t nth = 0; nth < _shape.N; ++nth)
+    {
+      for (int32_t ch = 0; ch < _shape.C; ++ch)
+      {
+        for (int32_t row = 0; row < _shape.H; ++row)
+        {
+          for (int32_t col = 0; col < _shape.W; ++col)
+          {
+            cb(nth, ch, row, col);
+          }
+        }
+      }
+    }
+
+    return (*this);
+  }
+
+private:
+  const Shape _shape; /**< Shape for kernel */
+};
+
+/**
+ * @brief Create an object of IndexIterator for kernel
+ * @param[in] shape reference of feature
+ * @return Created IndexIterator object
+ */
+inline IndexIterator iterate(const Shape &shape) { return IndexIterator{shape}; }
+
+/**
+ * @brief Call a function iterated using IndexIterator of kernel
+ *        Overloaded operator<<
+ * @param[in] it An IndexIterator reference
+ * @param[in] cb A callback function
+ * @return Created IndexIterator object
+ */
+template <typename Callable> IndexIterator &operator<<(IndexIterator &&it, Callable cb)
+{
+  return it.iter(cb);
+}
+
+} // namespace kernel
+} // namespace misc
+} // namespace nnfw
+
+#endif // __NNFW_MISC_FEATURE_INDEX_ITERATOR_H__
diff --git a/runtime/libs/misc/include/misc/kernel/Reader.h b/runtime/libs/misc/include/misc/kernel/Reader.h
new file mode 100644
index 000000000..019c809ee
--- /dev/null
+++ b/runtime/libs/misc/include/misc/kernel/Reader.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     Reader.h
+ * @brief    This file contains Reader structure
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_MISC_KERNEL_READER_H__
+#define __NNFW_MISC_KERNEL_READER_H__
+
+#include <cstdint>
+
+namespace nnfw
+{
+namespace misc
+{
+namespace kernel
+{
+
+/**
+ * @brief Structure to Reader
+ */
+template <typename T> struct Reader
+{
+  /**
+   * @brief Destroy the Reader object as default
+   */
+  virtual ~Reader() = default;
+
+  /**
+   * @brief Get the value used by four indexes
+   * @param[in] nth The kernel index
+   * @param[in] ch The channel index
+   * @param[in] row The row index
+   * @param[in] col The column index
+   * @return The value at the offset
+   */
+  virtual T at(uint32_t nth, uint32_t ch, uint32_t row, uint32_t col) const = 0;
+};
+
+} // namespace kernel
+} // namespace misc
+} // namespace nnfw
+
+#endif // __NNFW_MISC_KERNEL_READER_H__
diff --git a/runtime/libs/misc/include/misc/kernel/Shape.h b/runtime/libs/misc/include/misc/kernel/Shape.h
new file mode 100644
index 000000000..27d6a8bf0
--- /dev/null
+++ b/runtime/libs/misc/include/misc/kernel/Shape.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     Shape.h
+ * @brief    This file contains Shape structure
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_MISC_KERNEL_SHAPE_H__
+#define __NNFW_MISC_KERNEL_SHAPE_H__
+
+#include <cstdint>
+
+namespace nnfw
+{
+namespace misc
+{
+namespace kernel
+{
+
+/**
+ * @brief Structure to Shape
+ */
+struct Shape
+{
+  int32_t N; /**< The kernel index */
+  int32_t C; /**< The channel index */
+  int32_t H; /**< The height index */
+  int32_t W; /**< The width index */
+
+  /**
+   * @brief Construct a new Shape object as default
+   */
+  Shape() = default;
+
+  /**
+   * @brief Construct a new Shape object with parameters
+   * @param[in] count The kernel index
+   * @param[in] depth The channel index
+   * @param[in] height The height index
+   * @param[in] width The width index
+   */
+  Shape(int32_t count, int32_t depth, int32_t height, int32_t width)
+      : N{count}, C{depth}, H{height}, W{width}
+  {
+    // DO NOTHING
+  }
+};
+
+} // namespace kernel
+} // namespace misc
+} // namespace nnfw
+
+#endif // __NNFW_MISC_KERNEL_SHAPE_H__
diff --git a/runtime/libs/misc/include/misc/matrix/IndexIterator.h b/runtime/libs/misc/include/misc/matrix/IndexIterator.h
new file mode 100644
index 000000000..742ed3a65
--- /dev/null
+++ b/runtime/libs/misc/include/misc/matrix/IndexIterator.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     IndexIterator.h
+ * @brief    This file contains IndexIterator class
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_MISC_MATRIX_INDEX_ITERATOR_H__
+#define __NNFW_MISC_MATRIX_INDEX_ITERATOR_H__
+
+#include "misc/matrix/Shape.h"
+
+namespace nnfw
+{
+namespace misc
+{
+namespace matrix
+{
+
+/**
+ * @brief  Class to iterate Callable with Index of matrix
+ */
+class IndexIterator
+{
+public:
+  /**
+   * @brief  Construct IndexIterator object with Shape of matrix
+   * @param[in]  shape   Shape reference of matrix
+   */
+  IndexIterator(const Shape &shape) : _shape{shape}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief   Call a function iterated
+   * @param[in]   cb     A callback function
+   * @return  Current IndexIterator object
+   */
+  template <typename Callable> IndexIterator &iter(Callable cb)
+  {
+    for (uint32_t row = 0; row < _shape.H; ++row)
+    {
+      for (uint32_t col = 0; col < _shape.W; ++col)
+      {
+        cb(row, col);
+      }
+    }
+
+    return (*this);
+  }
+
+private:
+  /**
+   * @brief   Shape for matrix
+   */
+  const Shape _shape;
+};
+
+/**
+ * @brief   Create an object of IndexIterator for matrix
+ * @param[in]   Shape   reference of matrix
+ * @return  Created IndexIterator object
+ */
+inline IndexIterator iterate(const Shape &shape) { return IndexIterator{shape}; }
+
+/**
+ * @brief   Call a function iterated using IndexIterator of matrix
+ *          Overloaded operator<<
+ * @param[in]   it    An IndexIterator reference
+ * @param[in]   cb    A callback function
+ * @return  created IndexIterator object
+ */
+template <typename Callable> IndexIterator &operator<<(IndexIterator &&it, Callable cb)
+{
+  return it.iter(cb);
+}
+
+} // namespace matrix
+} // namespace misc
+} // namespace nnfw
+
+#endif // __NNFW_MISC_MATRIX_INDEX_ITERATOR_H__
diff --git a/runtime/libs/misc/include/misc/matrix/Reader.h b/runtime/libs/misc/include/misc/matrix/Reader.h
new file mode 100644
index 000000000..ea222c9d1
--- /dev/null
+++ b/runtime/libs/misc/include/misc/matrix/Reader.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     Reader.h
+ * @brief    This file contains Reader class
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_MISC_MATRIX_READER_H__
+#define __NNFW_MISC_MATRIX_READER_H__
+
+#include <cstdint>
+
+namespace nnfw
+{
+namespace misc
+{
+namespace matrix
+{
+
+/**
+ * @brief  Class reads values of matrix
+ *         The interface class
+ */
+template <typename T> struct Reader
+{
+  /**
+   * @brief  Destruct Reader object using default destructor
+   */
+  virtual ~Reader() = default;
+
+  /**
+   * @brief   Get the value used by two indexes
+   * @param[in]  row   The height index
+   * @param[in]  col   The width index
+   * @return  The value at the offset
+   */
+  virtual T at(uint32_t row, uint32_t col) const = 0;
+};
+
+} // namespace matrix
+} // namespace misc
+} // namespace nnfw
+
+#endif // __NNFW_MISC_MATRIX_READER_H__
diff --git a/runtime/libs/misc/include/misc/matrix/Shape.h b/runtime/libs/misc/include/misc/matrix/Shape.h
new file mode 100644
index 000000000..8cbcc1e12
--- /dev/null
+++ b/runtime/libs/misc/include/misc/matrix/Shape.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     Shape.h
+ * @brief    This file contains Shape class for matrix
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_MISC_MATRIX_SHAPE_H__
+#define __NNFW_MISC_MATRIX_SHAPE_H__
+
+#include <cstdint>
+
+namespace nnfw
+{
+namespace misc
+{
+namespace matrix
+{
+
+/**
+ * @brief  Structure to have values of dimensions for matrix
+ */
+struct Shape
+{
+  int32_t H; /**< The height value */
+  int32_t W; /**< The width value  */
+
+  /**
+   * @brief  Construct Shape object using default constrcutor
+   */
+  Shape() = default;
+
+  /**
+   * @brief  Construct Shape object with two values of dimensions
+   * @param[in]  height The height value
+   * @param[in]  width  The width value
+   */
+  Shape(int32_t height, int32_t width) : H{height}, W{width}
+  {
+    // DO NOTHING
+  }
+};
+
+} // namespace matrix
+} // namespace misc
+} // namespace nnfw
+
+#endif // __NNFW_MISC_MATRIX_SHAPE_H__
diff --git a/runtime/libs/misc/include/misc/polymorphic_downcast.h b/runtime/libs/misc/include/misc/polymorphic_downcast.h
new file mode 100644
index 000000000..ee885eb70
--- /dev/null
+++ b/runtime/libs/misc/include/misc/polymorphic_downcast.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NNFW_MISC_POLYMORPHIC_DOWNCAST_H__
+#define __NNFW_MISC_POLYMORPHIC_DOWNCAST_H__
+
+#include <cassert>
+#include <memory>
+
+namespace nnfw
+{
+namespace misc
+{
+
+template <typename DstType, typename SrcType> inline DstType polymorphic_downcast(SrcType *x)
+{
+  assert(dynamic_cast<DstType>(x) == x);
+  return static_cast<DstType>(x);
+}
+
+template <typename DstType, typename SrcType> inline DstType polymorphic_downcast(SrcType &x)
+{
+  assert(std::addressof(dynamic_cast<DstType>(x)) == std::addressof(x));
+  return static_cast<DstType>(x);
+}
+
+} // namespace misc
+} // namespace nnfw
+
+#endif // __NNFW_MISC_POLYMORPHIC_DOWNCAST_H__
diff --git a/runtime/libs/misc/include/misc/string_helpers.h b/runtime/libs/misc/include/misc/string_helpers.h
new file mode 100644
index 000000000..e42a12754
--- /dev/null
+++ b/runtime/libs/misc/include/misc/string_helpers.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file string_helpers.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief This file contains helper functions for std::string
+ */
+
+#include <ostream>
+#include <string>
+#include <sstream>
+#include <vector>
+
+namespace
+{
+
+template <typename Arg> void _str(std::ostream &os, Arg &&arg) { os << std::forward<Arg>(arg); }
+
+template <typename Arg, typename... Args> void _str(std::ostream &os, Arg &&arg, Args &&... args)
+{
+  _str(os, std::forward<Arg>(arg));
+  _str(os, std::forward<Args>(args)...);
+}
+
+} // namespace {anonymous}
+
+namespace nnfw
+{
+namespace misc
+{
+
+inline std::vector<std::string> split(const std::string &s, char delim)
+{
+  std::stringstream ss(s);
+  std::string item;
+  std::vector<std::string> elems;
+  while (std::getline(ss, item, delim))
+  {
+    elems.push_back(std::move(item));
+  }
+  return elems;
+}
+
+template <typename... Args> std::string str(Args &&... args)
+{
+  std::stringstream ss;
+  _str(ss, std::forward<Args>(args)...);
+  return ss.str();
+}
+
+} // namespace misc
+} // namespace nnfw
diff --git a/runtime/libs/misc/include/misc/tensor/Comparator.h b/runtime/libs/misc/include/misc/tensor/Comparator.h
new file mode 100644
index 000000000..80f53043c
--- /dev/null
+++ b/runtime/libs/misc/include/misc/tensor/Comparator.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Comparator.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief This file contains nnfw::misc::tensor::Comparator class
+ */
+
+#ifndef __NNFW_MISC_TENSOR_COMPARATOR_H__
+#define __NNFW_MISC_TENSOR_COMPARATOR_H__
+
+#include "misc/tensor/Index.h"
+#include "misc/tensor/Shape.h"
+#include "misc/tensor/Reader.h"
+#include "misc/tensor/Diff.h"
+
+#include <functional>
+
+#include <vector>
+
+namespace nnfw
+{
+namespace misc
+{
+namespace tensor
+{
+
+/**
+ * @brief Class to compare two tensors (expected and obtained to compare)
+ */
+class Comparator
+{
+public:
+  /**
+   * @brief Construct a new @c Comparator object
+   * @param[in] fn     Function that compares two float values
+   */
+  Comparator(const std::function<bool(float lhs, float rhs)> &fn) : _compare_fn{fn}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Struct to observe comparison results
+   */
+  struct Observer
+  {
+    /**
+     * @brief Get notification of comparison result at every index of two tensors
+     * @param[in] index       Index of tensors compared
+     * @param[in] expected    Expected value of element at @c index
+     * @param[in] obtained    Obtained value of element at @c index
+     * @return    N/A
+     */
+    virtual void notify(const Index &index, float expected, float obtained) = 0;
+  };
+
+public:
+  /**
+   * @brief Compare two tensors
+   * @param[in] shape       Shape of two tensors
+   * @param[in] expected    @c Reader<float> object that accesses expected tensor
+   * @param[in] obtained    @c Reader<float> object that accesses obtained tensor
+   * @param[in] observer    @c Observer notified of expected value and obtained value at every index
+   * @return    @c std::vector<Diff<float>> containing information of failed comparison
+   */
+  // NOTE Observer should live longer than comparator
+  std::vector<Diff<float>> compare(const Shape &shape, const Reader<float> &expected,
+                                   const Reader<float> &obtained,
+                                   Observer *observer = nullptr) const;
+
+private:
+  std::function<bool(float lhs, float rhs)> _compare_fn;
+};
+
+} // namespace tensor
+} // namespace misc
+} // namespace nnfw
+
+#endif // __NNFW_MISC_TENSOR_COMPARATOR_H__
diff --git a/runtime/libs/misc/include/misc/tensor/Diff.h b/runtime/libs/misc/include/misc/tensor/Diff.h
new file mode 100644
index 000000000..c41a97987
--- /dev/null
+++ b/runtime/libs/misc/include/misc/tensor/Diff.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Diff.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief This file contains nnfw::misc::tensor::Diff struct
+ */
+
+#ifndef __NNFW_MISC_TENSOR_DIFF_H__
+#define __NNFW_MISC_TENSOR_DIFF_H__
+
+#include "misc/tensor/Index.h"
+
+namespace nnfw
+{
+namespace misc
+{
+namespace tensor
+{
+
+/**
+ * @brief Struct to have information after comparing two elements of two tensors
+ */
+template <typename T> struct Diff
+{
+  Index index; /**< Index of elements in two tensors, which turn out to be different */
+
+  T expected; /**< Expected value of element of first tensor */
+  T obtained; /**< Obtained value of element of second tensor */
+
+  /**
+   * @brief Construct a new @c Diff object
+   * @param[in] i   Initial value of index
+   */
+  Diff(const Index &i) : index(i)
+  {
+    // DO NOTHING
+  }
+
+  /**
+   * @brief Construct a new @c Diff object
+   * @param[in] i   Index value
+   * @param[in] e   Expected value of element of first tensor
+   * @param[in] o   Obtained value of element of second tensor
+   */
+  Diff(const Index &i, const T &e, const T &o) : index(i), expected{e}, obtained{o}
+  {
+    // DO NOTHING
+  }
+};
+
+} // namespace tensor
+} // namespace misc
+} // namespace nnfw
+
+#endif // __NNFW_MISC_TENSOR_DIFF_H__
diff --git a/runtime/libs/misc/include/misc/tensor/Index.h b/runtime/libs/misc/include/misc/tensor/Index.h
new file mode 100644
index 000000000..a633b4ce0
--- /dev/null
+++ b/runtime/libs/misc/include/misc/tensor/Index.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Index.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief This file contains nnfw::misc::tensor::Index struct
+ */
+#ifndef __NNFW_MISC_TENSOR_INDEX_H__
+#define __NNFW_MISC_TENSOR_INDEX_H__
+
+#include <cstdint>
+#include <cstddef>
+
+#include <vector>
+#include <initializer_list>
+
+namespace nnfw
+{
+namespace misc
+{
+namespace tensor
+{
+
+/**
+ * @brief Struct to represent index of each dimension of a tensor
+ */
+struct Index
+{
+public:
+  /**
+   * @brief Construct a new @c Index object
+   * @param[in] rank    Rank of a tensor
+   */
+  Index(uint32_t rank) { _offsets.resize(rank); }
+
+public:
+  /**
+   * @brief Construct a new @c Index object
+   * @param[in] offsets    Rank of a tensor of @c std::initializer_list<int32_t> type
+   */
+  Index(std::initializer_list<int32_t> offsets) : _offsets{offsets}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Get the rank
+   * @return Rank that this @c Index object can handle
+   * @note   We can use static_cast\n
+   *         because size of _offsets is decieded by constructor's uintt_32 type argument
+   */
+  uint32_t rank(void) const { return static_cast<uint32_t>(_offsets.size()); }
+
+public:
+  /**
+   * @brief Get the index n'th dimension
+   * @param[in] n   Dimension
+   * @return index of n'th dimension
+   */
+  int32_t at(uint32_t n) const { return _offsets.at(n); }
+
+  /**
+   * @brief Get the reference of the index n'th dimension
+   * @param[in] n   Dimension
+   * @return reference of index of n'th dimension
+   */
+  int32_t &at(uint32_t n) { return _offsets.at(n); }
+
+private:
+  std::vector<int32_t> _offsets;
+};
+
+/**
+ * @brief Copy an @c Index with reversed order
+ * @param[in] origin    @c Index object to copy
+ * @return  an @c Index object with reversed order
+ * @note    This is used to convert NNAPI tensor index to ARM tensor index or vice versa
+ */
+inline static Index copy_reverse(const Index &origin)
+{
+  uint32_t rank = origin.rank();
+  Index target(rank);
+  for (uint32_t i = 0; i < rank; i++)
+    target.at(i) = origin.at(rank - 1 - i);
+  return target;
+}
+
+} // namespace tensor
+} // namespace misc
+} // namespace nnfw
+
+#endif // __NNFW_MISC_TENSOR_INDEX_H__
diff --git a/runtime/libs/misc/include/misc/tensor/IndexEnumerator.h b/runtime/libs/misc/include/misc/tensor/IndexEnumerator.h
new file mode 100644
index 000000000..6ce3add77
--- /dev/null
+++ b/runtime/libs/misc/include/misc/tensor/IndexEnumerator.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file IndexEnumerator.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief This file contains nnfw::misc::tensor::IndexEnumerator class
+ */
+
+#ifndef __NNFW_MISC_TENSOR_INDEX_ENUMERATOR_H__
+#define __NNFW_MISC_TENSOR_INDEX_ENUMERATOR_H__
+
+#include "misc/tensor/Shape.h"
+#include "misc/tensor/Index.h"
+
+namespace nnfw
+{
+namespace misc
+{
+namespace tensor
+{
+/**
+ * @brief Class to enumerate index of a tensor
+ *
+ */
+class IndexEnumerator
+{
+public:
+  /**
+   * @brief Construct a new @c IndexEnumerator object
+   * @param[in] shape   Shape of tensor of which index will be enumerate
+   */
+  explicit IndexEnumerator(const Shape &shape) : _shape(shape), _cursor(0), _index(shape.rank())
+  {
+    const uint32_t rank = _shape.rank();
+
+    for (uint32_t axis = 0; axis < rank; ++axis)
+    {
+      _index.at(axis) = 0;
+    }
+
+    for (_cursor = 0; _cursor < rank; ++_cursor)
+    {
+      if (_index.at(_cursor) < _shape.dim(_cursor))
+      {
+        break;
+      }
+    }
+  }
+
+public:
+  /**
+   * @brief Prevent constructing @c IndexEnumerator object by using R-value reference
+   */
+  IndexEnumerator(IndexEnumerator &&) = delete;
+  /**
+   * @brief Prevent copy constructor
+   */
+  IndexEnumerator(const IndexEnumerator &) = delete;
+
+public:
+  /**
+   * @brief Check if more enumeration is available
+   * @return @c true if more @c advance() is available, otherwise @c false
+   */
+  bool valid(void) const { return _cursor < _shape.rank(); }
+
+public:
+  /**
+   * @brief Get the current index to enumerate
+   * @return Current index
+   */
+  const Index &curr(void) const { return _index; }
+
+public:
+  /**
+   * @brief Advance index by +1
+   */
+  void advance(void)
+  {
+    const uint32_t rank = _shape.rank();
+
+    // Find axis to be updated
+    while ((_cursor < rank) && !(_index.at(_cursor) + 1 < _shape.dim(_cursor)))
+    {
+      ++_cursor;
+    }
+
+    if (_cursor == rank)
+    {
+      return;
+    }
+
+    // Update index
+    _index.at(_cursor) += 1;
+
+    for (uint32_t axis = 0; axis < _cursor; ++axis)
+    {
+      _index.at(axis) = 0;
+    }
+
+    // Update cursor
+    _cursor = 0;
+  }
+
+public:
+  const Shape _shape; //!< Shape to enumerate
+
+private:
+  uint32_t _cursor;
+  Index _index;
+};
+
+} // namespace tensor
+} // namespace misc
+} // namespace nnfw
+
+#endif // __NNFW_MISC_TENSOR_INDEX_ENUMERATOR_H__
diff --git a/runtime/libs/misc/include/misc/tensor/IndexFormatter.h b/runtime/libs/misc/include/misc/tensor/IndexFormatter.h
new file mode 100644
index 000000000..7ae34eec1
--- /dev/null
+++ b/runtime/libs/misc/include/misc/tensor/IndexFormatter.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file IndexFormatter.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief This file contains nnfw::misc::tensor::IndexFormatter class
+ */
+
+#ifndef __NNFW_MISC_TENSOR_INDEX_FORMATTER_H__
+#define __NNFW_MISC_TENSOR_INDEX_FORMATTER_H__
+
+#include "misc/tensor/Index.h"
+
+#include <ostream>
+
+namespace nnfw
+{
+namespace misc
+{
+namespace tensor
+{
+
+/**
+ * @brief Class to send @c Index object to output stream
+ */
+class IndexFormatter
+{
+public:
+  /**
+   * @brief Construct a new @c IndexFormatter object
+   * @param[in] index   index to be sent to output stream
+   */
+  IndexFormatter(const nnfw::misc::tensor::Index &index) : _index(index)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Get an @c Index object
+   * @return @c Index object previously passed to the constructor
+   */
+  const nnfw::misc::tensor::Index &index(void) const { return _index; }
+
+private:
+  const nnfw::misc::tensor::Index &_index;
+};
+
+/**
+ * @brief Send @c IndexFormatter object to output stream
+ * @param[in] os    Output stream
+ * @param[in] fmt   @c IndexFormatter object that is sent to output stream
+ * @return Output stream
+ */
+std::ostream &operator<<(std::ostream &os, const IndexFormatter &fmt);
+
+} // namespace tensor
+} // namespace misc
+} // namespace nnfw
+
+#endif // __NNFW_MISC_TENSOR_INDEX_FORMATTER_H__
diff --git a/runtime/libs/misc/include/misc/tensor/IndexIterator.h b/runtime/libs/misc/include/misc/tensor/IndexIterator.h
new file mode 100644
index 000000000..f6428e19e
--- /dev/null
+++ b/runtime/libs/misc/include/misc/tensor/IndexIterator.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file IndexIterator.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief This file contains nnfw::misc::tensor::IndexIterator class and
+ *        helper function and operator
+ */
+#ifndef __NNFW_MISC_TENSOR_INDEX_ITERATOR_H__
+#define __NNFW_MISC_TENSOR_INDEX_ITERATOR_H__
+
+#include "misc/tensor/Shape.h"
+#include "misc/tensor/Index.h"
+#include "misc/tensor/IndexEnumerator.h"
+
+namespace nnfw
+{
+namespace misc
+{
+namespace tensor
+{
+
+/**
+ * @brief Class to iterate indexes available for given shape
+ */
+class IndexIterator
+{
+public:
+  /**
+   * @brief Construct a new @c IndexIterator object
+   * @param[in] shape   Shape of tensor of which index will be iterated
+   */
+  IndexIterator(const Shape &shape) : _shape(shape)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Construct a new IndexIterator object using reference
+   * @param[in] IndexIterator    @c IndexIterator object to move
+   */
+  IndexIterator(IndexIterator &&) = default;
+
+  /**
+   * @brief Prevent copy constructor
+   */
+  IndexIterator(const IndexIterator &) = delete;
+
+public:
+  /**
+   * @brief Iterate all available indexes and run a function for each index
+   * @param[in] fn      Function that requires an index as a parameter.
+   * @return @c IndexIterator object
+   */
+  template <typename Callable> IndexIterator &iter(Callable fn)
+  {
+    for (IndexEnumerator e{_shape}; e.valid(); e.advance())
+    {
+      fn(e.curr());
+    }
+
+    return (*this);
+  }
+
+private:
+  const Shape &_shape;
+};
+
+/**
+ * @brief Get an @c IndexItator object
+ * @param[in] shape     Shape of tensor of which index will be iterated
+ * @return @c IndexIterator object
+ */
+inline IndexIterator iterate(const Shape &shape) { return IndexIterator{shape}; }
+
+/**
+ * @brief Iterate all indexes and apply a function
+ * @param[in] it    @c IndexIterator object that is constructed with a tensor shape
+ * @param[in] cb    A function that will receive a specific index.
+ *                  Inside the function, the index is used to manipulate tensor element.
+ * @return @c IndexIterator object
+ */
+template <typename Callable> IndexIterator &operator<<(IndexIterator &&it, Callable cb)
+{
+  return it.iter(cb);
+}
+
+} // namespace tensor
+} // namespace misc
+} // namespace nnfw
+
+#endif // __NNFW_MISC_TENSOR_INDEX_ITERATOR_H__
diff --git a/runtime/libs/misc/include/misc/tensor/NonIncreasingStride.h b/runtime/libs/misc/include/misc/tensor/NonIncreasingStride.h
new file mode 100644
index 000000000..3bc0c115c
--- /dev/null
+++ b/runtime/libs/misc/include/misc/tensor/NonIncreasingStride.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file NonIncreasingStride.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief This file contains nnfw::misc::tensor::NonIncreasingStride class
+ */
+#ifndef __NNFW_MISC_TENSOR_NON_INCREASING_STRIDE_H__
+#define __NNFW_MISC_TENSOR_NON_INCREASING_STRIDE_H__
+
+#include "misc/tensor/Shape.h"
+#include "misc/tensor/Index.h"
+
+#include <vector>
+
+namespace nnfw
+{
+namespace misc
+{
+namespace tensor
+{
+
+/**
+ * @brief Class to represent strides where stride[N-1] >= stride[N] holds for all N < rank
+ */
+class NonIncreasingStride
+{
+public:
+  /**
+   * @brief Initialize the stride data using @c Shape
+   * @param[in] shape to build stride info
+   * @return N/A
+   */
+  void init(const Shape &shape)
+  {
+    _stride.resize(shape.rank());
+
+    // Scalar
+    if (shape.rank() == 0)
+      return;
+
+    _stride.at(shape.rank() - 1) = 1;
+
+    for (uint32_t axis = shape.rank() - 1; axis > 0; --axis)
+    {
+      _stride.at(axis - 1) = _stride.at(axis) * shape.dim(axis);
+    }
+  }
+
+public:
+  /**
+   * @brief Get an stride value for specific axis
+   * @param[in] axis   Axis of stride
+   * @return The value of stride
+   */
+  uint32_t at(uint32_t axis) const { return _stride.at(axis); }
+
+public:
+  /**
+   * @brief Get the 1-D offset of specified index for n-D tensor
+   * @param index @c Index object
+   * @return  1-D offset of index
+   */
+  uint32_t offset(const Index &index) const;
+
+private:
+  std::vector<uint32_t> _stride;
+};
+
+} // namespace tensor
+} // namespace misc
+} // namespace nnfw
+
+#endif // __NNFW_MISC_TENSOR_NON_INCREASING_STRIDE_H__
diff --git a/runtime/libs/misc/include/misc/tensor/Object.h b/runtime/libs/misc/include/misc/tensor/Object.h
new file mode 100644
index 000000000..cba4f1baf
--- /dev/null
+++ b/runtime/libs/misc/include/misc/tensor/Object.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Object.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief This file contains nnfw::misc::tensor::Object class
+ */
+
+#ifndef __NNFW_MISC_TENSOR_OBJECT_H__
+#define __NNFW_MISC_TENSOR_OBJECT_H__
+
+#include "misc/tensor/Shape.h"
+#include "misc/tensor/Index.h"
+#include "misc/tensor/IndexIterator.h"
+#include "misc/tensor/NonIncreasingStride.h"
+#include "misc/tensor/Reader.h"
+
+#include <vector>
+
+namespace nnfw
+{
+namespace misc
+{
+namespace tensor
+{
+
+/**
+ * @brief Class to build a tensor using specific generator
+ * @tparam T  Type of tensor element
+ */
+
+template <typename T> class Object final : public Reader<T>
+{
+public:
+  /**
+   * @brief Function to generate tensor element
+   */
+  using Generator = std::function<T(const Shape &shape, const Index &index)>;
+
+public:
+  /**
+   * @brief Construct a new @c Object object
+   * @param[in] shape   Tensor shape
+   * @param[in] fn      Function to generate tensor elements
+   */
+  Object(const Shape &shape, const Generator &fn) : _shape{shape}
+  {
+    // Set 'stride'
+    _stride.init(shape);
+
+    // Handle scalar object
+    if (shape.rank() == 0)
+    {
+      _values.resize(1);
+      _values.at(0) = fn(_shape, 0);
+    }
+    else
+    {
+      // Pre-allocate buffer
+      _values.resize(_shape.dim(0) * _stride.at(0));
+
+      // Set 'value'
+      iterate(_shape) << [this, &fn](const Index &index) {
+        _values.at(_stride.offset(index)) = fn(_shape, index);
+      };
+    }
+  }
+
+public:
+  /**
+   * @brief Get reference of shape
+   * @return Reference of shape
+   */
+  const Shape &shape(void) const { return _shape; }
+
+public:
+  /**
+   * @brief Get and element of tensor
+   * @param[in] index   Index of a tensor element
+   * @return Value of tensor element
+   */
+  T at(const Index &index) const override { return _values.at(_stride.offset(index)); }
+
+private:
+  Shape _shape;
+  NonIncreasingStride _stride;
+
+private:
+  std::vector<T> _values;
+};
+
+} // namespace tensor
+} // namespace misc
+} // namespace nnfw
+
+#endif // __NNFW_MISC_FEATURE_OBJECT_H__
diff --git a/runtime/libs/misc/include/misc/tensor/Reader.h b/runtime/libs/misc/include/misc/tensor/Reader.h
new file mode 100644
index 000000000..9175a913e
--- /dev/null
+++ b/runtime/libs/misc/include/misc/tensor/Reader.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Reader.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief This file contains nnfw::misc::tensor::Reader struct
+ */
+
+#ifndef __NNFW_MISC_TENSOR_READER_H__
+#define __NNFW_MISC_TENSOR_READER_H__
+
+#include "misc/tensor/Index.h"
+
+namespace nnfw
+{
+namespace misc
+{
+namespace tensor
+{
+
+/**
+ * @brief     Struct to read element of tensor
+ * @tparam T  Type of elements in tensor
+ */
+template <typename T> struct Reader
+{
+  /**
+   * @brief Destroy the Reader object
+   */
+  virtual ~Reader() = default;
+
+  /**
+   * @brief Get an element of tensor
+   * @param[in] index   Index specifying indexes of tensor element
+   * @return The value of specificed element
+   */
+  virtual T at(const Index &index) const = 0;
+};
+
+} // namespace tensor
+} // namespace misc
+} // namespace nnfw
+
+#endif // __NNFW_MISC_TENSOR_READER_H__
diff --git a/runtime/libs/misc/include/misc/tensor/Shape.h b/runtime/libs/misc/include/misc/tensor/Shape.h
new file mode 100644
index 000000000..bd0eac0a5
--- /dev/null
+++ b/runtime/libs/misc/include/misc/tensor/Shape.h
@@ -0,0 +1,150 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Shape.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief This file contains nnfw::misc::tensor::Shape class
+ */
+
+#ifndef __NNFW_MISC_TENSOR_SHAPE_H__
+#define __NNFW_MISC_TENSOR_SHAPE_H__
+
+#include <cstdint>
+#include <cstddef>
+#include <deque>
+#include <initializer_list>
+#include <ostream>
+#include <string>
+#include <cassert>
+
+namespace nnfw
+{
+namespace misc
+{
+namespace tensor
+{
+
+/**
+ * @brief Class to represent shape of a tensor
+ */
+class Shape
+{
+public:
+  /**
+   * @brief Construct a new Shape object
+   * @param[in] rank    Rank of a tensor
+   */
+  Shape(uint32_t rank) { _dimensions.resize(rank); }
+
+public:
+  /**
+   * @brief Construct a new Shape object
+   * @param[in] dimensions    @c initializer_list<int32_t> of dimensions of tensor
+   */
+  Shape(const std::initializer_list<int32_t> &dimensions) : _dimensions{dimensions}
+  {
+    // Check overflow because initializer_list type can be larger size than max of uint32_t
+    assert(dimensions.size() <= 0xFFFFFFFF);
+  }
+
+  /**
+   * @brief Construct a new Shape object
+   * @param[in] origin    @c Shape object to copy
+   */
+  Shape(const Shape &origin) = default;
+
+public:
+  /**
+   * @brief Add dimension to the beginning
+   * @param[in] d     dimension to add to the beginning
+   * @return N/A
+   */
+  void prepend(int32_t d) { _dimensions.emplace_front(d); }
+
+  /**
+   * @brief Add dimension to the back
+   * @param[in] d     dimension to add to the back
+   * @return N/A
+   */
+  void append(int32_t d) { _dimensions.emplace_back(d); }
+
+public:
+  /**
+   * @brief Get the rank of this shape
+   * @return rank
+   * @note   We can use static_cast\n
+   *         because we don't support larger than max of uint32_t on constructor
+   */
+  uint32_t rank(void) const { return static_cast<uint32_t>(_dimensions.size()); }
+
+public:
+  /**
+   * @brief Get specific dimension
+   * @param[in] n  Index of dimension
+   * @return n'th dimension
+   */
+  int32_t dim(uint32_t n) const { return _dimensions.at(n); }
+
+  /**
+   * @brief Get the reference of specific dimension
+   * @param[in] n  Index of dimension
+   * @return Reference of n'th dimension
+   */
+  int32_t &dim(uint32_t n) { return _dimensions.at(n); }
+
+  const std::deque<int32_t> &dims() const { return _dimensions; }
+
+public:
+  /**
+   * @brief Get the number of elements specified by this shape
+   * @return The number of elements
+   */
+  uint64_t num_elements() const;
+
+private:
+  std::deque<int32_t> _dimensions;
+
+public:
+  /**
+   * @brief Get a @c Shape object after parsing string
+   * @param[in] s  String of dimension list. Accepted format is numbers separated by comma.
+   * @return @c Shape object
+   */
+  static Shape from(const std::string &s);
+};
+
+/**
+ * @brief Check equality of two @c Shape
+ * @param[in] Shape First shape to compare
+ * @param[in] Shape Second shape to compare
+ * @return @c true if both shapes are equal, otherwise @c false
+ */
+bool operator==(const Shape &, const Shape &);
+
+/**
+ * @brief Send @c Shape to @c std::ostream
+ * @param[in] os        @c std::ostream to process this @c Shape
+ * @param[in] shape     @c Shape to send to @c ostream
+ * @return Reference of @c std::ostream
+ */
+std::ostream &operator<<(std::ostream &os, const Shape &shape);
+
+} // namespace tensor
+} // namespace misc
+} // namespace nnfw
+
+#endif // __NNFW_MISC_TENSOR_SHAPE_H__
diff --git a/runtime/libs/misc/include/misc/tensor/Zipper.h b/runtime/libs/misc/include/misc/tensor/Zipper.h
new file mode 100644
index 000000000..8f0ec4ab6
--- /dev/null
+++ b/runtime/libs/misc/include/misc/tensor/Zipper.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Zipper.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief This file contains nnfw::misc::tensor::Zipper class
+ */
+
+#ifndef __NNFW_MISC_TENSOR_ZIPPER_H__
+#define __NNFW_MISC_TENSOR_ZIPPER_H__
+
+#include "misc/tensor/Index.h"
+#include "misc/tensor/IndexIterator.h"
+#include "misc/tensor/Reader.h"
+
+namespace nnfw
+{
+namespace misc
+{
+namespace tensor
+{
+
+/**
+ * @brief Class to apply a function with three params: @c Index, elements of a tensor
+ * at passed index read by @c Reader objects
+ */
+template <typename T> class Zipper
+{
+public:
+  /**
+   * @brief Construct a new @c Zipper object
+   * @param[in] shape   Shape of @c lhs and @c rhs
+   * @param[in] lhs     @c Reader object of a tensor
+   * @param[in] rhs     @c Reader object of a tensor
+   */
+  Zipper(const Shape &shape, const Reader<T> &lhs, const Reader<T> &rhs)
+      : _shape{shape}, _lhs{lhs}, _rhs{rhs}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Apply @c cb to all elements of tensors. Elements of two tensors
+   *        at passed @c index are read by @c lhs and @c rhs
+   * @param[in] cb   Function to apply
+   * @return    N/A
+   */
+  template <typename Callable> void zip(Callable cb) const
+  {
+    iterate(_shape) <<
+        [this, &cb](const Index &index) { cb(index, _lhs.at(index), _rhs.at(index)); };
+  }
+
+private:
+  const Shape &_shape;
+  const Reader<T> &_lhs;
+  const Reader<T> &_rhs;
+};
+
+/**
+ * @brief Apply @c cb by using @c lhs and @c rhs passed to the constructor of @c zipper
+ * @param[in] zipper    @c Zipper object
+ * @param[in] cb        Function to zpply using @c zip function
+ * @return @c zipper object after applying @c cb to @c zipper
+ */
+template <typename T, typename Callable>
+const Zipper<T> &operator<<(const Zipper<T> &zipper, Callable cb)
+{
+  zipper.zip(cb);
+  return zipper;
+}
+
+/**
+ * @brief Get @c Zipper object constructed using passed params
+ * @param shape   Shape of @c lhs and @c rhs
+ * @param lhs     @c Reader object of a tensor
+ * @param rhs     @c Reader object of a tensor
+ * @return        @c Zipper object
+ */
+template <typename T> Zipper<T> zip(const Shape &shape, const Reader<T> &lhs, const Reader<T> &rhs)
+{
+  return Zipper<T>{shape, lhs, rhs};
+}
+
+} // namespace tensor
+} // namespace misc
+} // namespace nnfw
+
+#endif // __NNFW_MISC_TENSOR_ZIPPER_H__
diff --git a/runtime/libs/misc/include/misc/vector.h b/runtime/libs/misc/include/misc/vector.h
new file mode 100644
index 000000000..395b08912
--- /dev/null
+++ b/runtime/libs/misc/include/misc/vector.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file vector.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief This file contains @c == operator to check equality of elements in two vectors
+ */
+#ifndef __NNFW_MISC_VECTOR_H__
+#define __NNFW_MISC_VECTOR_H__
+
+#include <vector>
+
+/**
+ * @brief       Compare elements of two vectors
+ * @tparam T    Type of elements in vectors
+ * @param[in] lhs   First vector to compare
+ * @param[in] rhs   Second vector to compare
+ * @return    @c true if all elements are equal, otherwise @c false.
+ */
+template <typename T> bool operator==(const std::vector<T> &lhs, const std::vector<T> &rhs)
+{
+  if (lhs.size() != rhs.size())
+  {
+    return false;
+  }
+
+  for (size_t ind = 0; ind < lhs.size(); ++ind)
+  {
+    if (lhs.at(ind) != rhs.at(ind))
+    {
+      return false;
+    }
+  }
+
+  return true;
+}
+
+#endif // __NNFW_MISC_VECTOR_H__
diff --git a/runtime/libs/misc/include/misc/vector/Object.h b/runtime/libs/misc/include/misc/vector/Object.h
new file mode 100644
index 000000000..65d4bc613
--- /dev/null
+++ b/runtime/libs/misc/include/misc/vector/Object.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     Object.h
+ * @brief    This file contains Object class
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_MISC_VECTOR_OBJECT_H__
+#define __NNFW_MISC_VECTOR_OBJECT_H__
+
+#include "misc/vector/Reader.h"
+
+#include <vector>
+#include <functional>
+
+namespace nnfw
+{
+namespace misc
+{
+namespace vector
+{
+
+/**
+ * @brief  Class to have information of the operand for vector
+ */
+template <typename T> class Object final : public Reader<T>
+{
+public:
+  using Generator = std::function<T(int32_t size, int32_t offset)>;
+
+public:
+  /**
+   * @brief  Construct Object object with size of vector and set value used by Generator
+   * @param[in]  size    The size of vector
+   * @param[in]  gen     A function to set values of operand tensor
+   */
+  Object(int32_t size, const Generator &gen) : _size{size}
+  {
+    _value.resize(_size);
+
+    for (int32_t offset = 0; offset < size; ++offset)
+    {
+      _value.at(offset) = gen(size, offset);
+    }
+  }
+
+public:
+  /**
+   * @brief   Get size of vector
+   * @return  Size of vector
+   */
+  int32_t size(void) const { return _size; }
+
+public:
+  /**
+   * @brief   Get the value used by index
+   * @param[in]  nth    The vector index
+   * @return  The value at the offset
+   */
+  T at(uint32_t nth) const override { return _value.at(nth); }
+
+private:
+  /**
+   * @brief   Size of vector
+   */
+  const int32_t _size;
+  /**
+   * @brief   The tensor vector of operand
+   */
+  std::vector<T> _value;
+};
+
+} // namespace vector
+} // namespace misc
+} // namespace nnfw
+
+#endif // __NNFW_MISC_VECTOR_OBJECT_H__
diff --git a/runtime/libs/misc/include/misc/vector/Reader.h b/runtime/libs/misc/include/misc/vector/Reader.h
new file mode 100644
index 000000000..eab4c427b
--- /dev/null
+++ b/runtime/libs/misc/include/misc/vector/Reader.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     Reader.h
+ * @brief    This file contains Reader class
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_MISC_VECTOR_READER_H__
+#define __NNFW_MISC_VECTOR_READER_H__
+
+#include <cstdint>
+
+namespace nnfw
+{
+namespace misc
+{
+namespace vector
+{
+
+/**
+ * @brief  Class reads values of vector
+ *         The interface class
+ */
+template <typename T> struct Reader
+{
+  /**
+   * @brief  Destruct Reader object using default destructor
+   */
+  virtual ~Reader() = default;
+
+  /**
+   * @brief   Get the value used by the index
+   * @param[in]  nth    The vector index
+   * @return  The value at the offset
+   */
+  virtual T at(uint32_t nth) const = 0;
+};
+
+} // namespace vector
+} // namespace misc
+} // namespace nnfw
+
+#endif // __NNFW_MISC_VECTOR_READER_H__
diff --git a/runtime/libs/misc/src/EventCollector.cpp b/runtime/libs/misc/src/EventCollector.cpp
new file mode 100644
index 000000000..452a29166
--- /dev/null
+++ b/runtime/libs/misc/src/EventCollector.cpp
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "misc/EventCollector.h"
+
+// C++ standard libraries
+#include <chrono>
+
+// POSIX standard libraries
+#include <sys/time.h>
+#include <sys/resource.h>
+
+namespace
+{
+
+std::string timestamp(void)
+{
+  auto now = std::chrono::steady_clock::now();
+  return std::to_string(
+      std::chrono::duration_cast<std::chrono::microseconds>(now.time_since_epoch()).count());
+}
+
+class DurationEventBuilder
+{
+public:
+  DurationEventBuilder(const std::string &ts) : _ts{ts} {}
+
+  DurationEvent build(const std::string &tid, const std::string &name, const std::string &ph) const
+  {
+    DurationEvent evt;
+
+    evt.name = name;
+    evt.tid = tid;
+    evt.ph = ph;
+    evt.ts = _ts;
+
+    return evt;
+  }
+
+private:
+  std::string _ts;
+};
+
+void emit_rusage(EventRecorder *rec, const std::string &ts)
+{
+  struct rusage ru;
+
+  getrusage(RUSAGE_SELF, &ru);
+  {
+    CounterEvent evt;
+
+    evt.name = "maxrss";
+    evt.ph = "C";
+    evt.ts = ts;
+    evt.values["value"] = std::to_string(ru.ru_maxrss);
+
+    rec->emit(evt);
+  }
+
+  {
+    CounterEvent evt;
+
+    evt.name = "minflt";
+    evt.ph = "C";
+    evt.ts = ts;
+    evt.values["value"] = std::to_string(ru.ru_minflt);
+
+    rec->emit(evt);
+  }
+}
+
+} // namespace
+
+void EventCollector::onEvent(const Event &event)
+{
+  auto ts = timestamp();
+
+  switch (event.edge)
+  {
+    case Edge::BEGIN:
+      _rec->emit(DurationEventBuilder(ts).build(event.backend, event.label, "B"));
+      break;
+
+    case Edge::END:
+      _rec->emit(DurationEventBuilder(ts).build(event.backend, event.label, "E"));
+      break;
+  }
+
+  // Trace resource usage per each event notification
+  emit_rusage(_rec, ts);
+}
diff --git a/runtime/libs/misc/src/EventRecorder.cpp b/runtime/libs/misc/src/EventRecorder.cpp
new file mode 100644
index 000000000..5fdeef5fe
--- /dev/null
+++ b/runtime/libs/misc/src/EventRecorder.cpp
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "misc/EventRecorder.h"
+
+#include <sstream>
+#include <vector>
+
+namespace
+{
+
+std::string quote(const std::string &value)
+{
+  std::stringstream ss;
+  ss << '"' << value << '"';
+  return ss.str();
+}
+
+std::string field(const std::string &k, const std::string &v)
+{
+  std::stringstream ss;
+  ss << quote(k) << " : " << quote(v);
+  return ss.str();
+}
+
+struct Content // One Entry in Chrome Event Trace
+{
+  std::vector<std::pair<std::string, std::string>> flds;
+  std::vector<std::pair<std::string, std::string>> args;
+};
+
+std::string object(const Content &content)
+{
+  std::stringstream ss;
+
+  ss << "{ ";
+
+  ss << field(content.flds[0].first, content.flds[0].second);
+
+  for (uint32_t n = 1; n < content.flds.size(); ++n)
+  {
+    ss << ", " << field(content.flds.at(n).first, content.flds.at(n).second);
+  }
+
+  if (content.args.size() > 0)
+  {
+    ss << ", " << quote("args") << " : { ";
+    ss << field(content.args.at(0).first, content.args.at(0).second);
+
+    for (uint32_t n = 1; n < content.args.size(); ++n)
+    {
+      ss << ", " << field(content.args.at(n).first, content.args.at(n).second);
+    }
+
+    ss << "}";
+  }
+
+  ss << " }";
+
+  return ss.str();
+}
+
+void fill(Content &content, const Event &evt)
+{
+  content.flds.emplace_back("name", evt.name);
+  content.flds.emplace_back("pid", "0");
+  content.flds.emplace_back("tid", evt.tid);
+  content.flds.emplace_back("ph", evt.ph);
+  content.flds.emplace_back("ts", evt.ts);
+}
+
+std::string object(const DurationEvent &evt)
+{
+  Content content;
+
+  fill(content, evt);
+
+  return ::object(content);
+}
+
+std::string object(const CounterEvent &evt)
+{
+  Content content;
+
+  fill(content, evt);
+
+  for (auto it = evt.values.begin(); it != evt.values.end(); ++it)
+  {
+    content.args.emplace_back(it->first, it->second);
+  }
+
+  return ::object(content);
+}
+
+} // namespace
+
+void EventRecorder::emit(const DurationEvent &evt)
+{
+  std::lock_guard<std::mutex> lock{_mu};
+
+  _ss << "    " << object(evt) << ",\n";
+}
+
+void EventRecorder::emit(const CounterEvent &evt)
+{
+  std::lock_guard<std::mutex> lock{_mu};
+
+  _ss << "    " << object(evt) << ",\n";
+}
+
+void EventRecorder::writeToFile(std::ostream &os)
+{
+  std::lock_guard<std::mutex> lock{_mu};
+
+  os << "{\n";
+  os << "  " << quote("traceEvents") << ": [\n";
+
+  os << _ss.str();
+
+  os << "    { }\n";
+  os << "  ]\n";
+  os << "}\n";
+}
diff --git a/runtime/libs/misc/src/tensor/Comparator.cpp b/runtime/libs/misc/src/tensor/Comparator.cpp
new file mode 100644
index 000000000..e765e77b2
--- /dev/null
+++ b/runtime/libs/misc/src/tensor/Comparator.cpp
@@ -0,0 +1,38 @@
+#include "misc/tensor/Comparator.h"
+#include "misc/tensor/Zipper.h"
+
+#include "misc/fp32.h"
+
+namespace nnfw
+{
+namespace misc
+{
+namespace tensor
+{
+
+std::vector<Diff<float>> Comparator::compare(const Shape &shape, const Reader<float> &expected,
+                                             const Reader<float> &obtained,
+                                             Observer *observer) const
+{
+  std::vector<Diff<float>> res;
+
+  zip(shape, expected, obtained) <<
+      [&](const Index &index, float expected_value, float obtained_value) {
+        if (!_compare_fn(expected_value, obtained_value))
+        {
+          res.emplace_back(index, expected_value, obtained_value);
+        }
+
+        // Update max_diff_index, if necessary
+        if (observer != nullptr)
+        {
+          observer->notify(index, expected_value, obtained_value);
+        }
+      };
+
+  return res;
+}
+
+} // namespace tensor
+} // namespace misc
+} // namespace nnfw
diff --git a/runtime/libs/misc/src/tensor/IndexFormatter.cpp b/runtime/libs/misc/src/tensor/IndexFormatter.cpp
new file mode 100644
index 000000000..c949db7a8
--- /dev/null
+++ b/runtime/libs/misc/src/tensor/IndexFormatter.cpp
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "misc/tensor/IndexFormatter.h"
+
+#include <cassert>
+
+namespace nnfw
+{
+namespace misc
+{
+namespace tensor
+{
+
+std::ostream &operator<<(std::ostream &os, const IndexFormatter &fmt)
+{
+  const auto rank = fmt.index().rank();
+
+  assert(rank > 0);
+
+  os << fmt.index().at(0);
+
+  if (rank > 1)
+  {
+    for (uint32_t axis = 1; axis < rank; ++axis)
+    {
+      os << ", " << fmt.index().at(axis);
+    }
+  }
+
+  return os;
+}
+
+} // namespace tensor
+} // namespace misc
+} // namespace nnfw
diff --git a/runtime/libs/misc/src/tensor/NonIncreasingStride.cpp b/runtime/libs/misc/src/tensor/NonIncreasingStride.cpp
new file mode 100644
index 000000000..c51ad0324
--- /dev/null
+++ b/runtime/libs/misc/src/tensor/NonIncreasingStride.cpp
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "misc/tensor/NonIncreasingStride.h"
+
+#include <cassert>
+
+namespace nnfw
+{
+namespace misc
+{
+namespace tensor
+{
+
+uint32_t NonIncreasingStride::offset(const Index &index) const
+{
+  const size_t rank = _stride.size();
+
+  assert(index.rank() == rank);
+
+  uint32_t offset = 0;
+
+  for (size_t axis = 0; axis < rank; ++axis)
+  {
+    offset += _stride.at(axis) * index.at(axis);
+  }
+
+  return offset;
+}
+
+} // namespace tensor
+} // namespace misc
+} // namespace nnfw
diff --git a/runtime/libs/misc/src/tensor/Shape.cpp b/runtime/libs/misc/src/tensor/Shape.cpp
new file mode 100644
index 000000000..70d3bdfdb
--- /dev/null
+++ b/runtime/libs/misc/src/tensor/Shape.cpp
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "misc/tensor/Shape.h"
+
+#include <cassert>
+#include <functional>
+#include <numeric>
+
+namespace nnfw
+{
+namespace misc
+{
+namespace tensor
+{
+
+bool operator==(const Shape &lhs, const Shape &rhs)
+{
+  if (lhs.rank() != rhs.rank())
+  {
+    return false;
+  }
+
+  for (uint32_t axis = 0; axis < lhs.rank(); ++axis)
+  {
+    if (lhs.dim(axis) != rhs.dim(axis))
+    {
+      return false;
+    }
+  }
+
+  return true;
+}
+
+Shape Shape::from(const std::string &str)
+{
+  Shape shape(0);
+
+  bool pending = false;
+  int value = 0;
+
+  for (const char *cur = str.c_str(); true; ++cur)
+  {
+    if (*cur == ',' || *cur == '\0')
+    {
+      if (pending)
+      {
+        shape.append(value);
+      }
+
+      if (*cur == '\0')
+      {
+        break;
+      }
+
+      pending = false;
+      value = 0;
+      continue;
+    }
+
+    assert(*cur >= '0' && *cur <= '9');
+
+    pending = true;
+    value *= 10;
+    value += *cur - '0';
+  }
+
+  return shape;
+}
+
+uint64_t Shape::num_elements() const
+{
+  return std::accumulate(_dimensions.cbegin(), _dimensions.cend(), UINT64_C(1),
+                         std::multiplies<uint64_t>());
+}
+
+std::ostream &operator<<(std::ostream &os, const Shape &shape)
+{
+  if (shape.rank() > 0)
+  {
+    os << shape.dim(0);
+
+    for (uint32_t axis = 1; axis < shape.rank(); ++axis)
+    {
+      os << "," << shape.dim(axis);
+    }
+  }
+
+  return os;
+}
+
+} // namespace tensor
+} // namespace misc
+} // namespace nnfw
diff --git a/runtime/libs/ndarray/CMakeLists.txt b/runtime/libs/ndarray/CMakeLists.txt
new file mode 100644
index 000000000..b040f5115
--- /dev/null
+++ b/runtime/libs/ndarray/CMakeLists.txt
@@ -0,0 +1,19 @@
+add_library(ndarray STATIC src/Array.cpp src/ContiguousSpan.cpp)
+
+set_target_properties(ndarray PROPERTIES POSITION_INDEPENDENT_CODE ON)
+
+target_include_directories(ndarray PUBLIC include)
+#can't make this private because of c++ templates
+target_include_directories(ndarray PUBLIC src)
+
+option(NDARRAY_INLINE_TEMPLATES "Set to ON to disable extern declarations for common types")
+
+if(${NDARRAY_INLINE_TEMPLATES})
+    target_compile_definitions(ndarray PUBLIC -DNDARRAY_INLINE_TEMPLATES=1)
+endif()
+
+target_link_libraries(ndarray PRIVATE nnfw_common)
+target_link_libraries(ndarray PRIVATE nnfw_coverage)
+
+add_subdirectory(test)
+add_subdirectory(example)
diff --git a/runtime/libs/ndarray/example/CMakeLists.txt b/runtime/libs/ndarray/example/CMakeLists.txt
new file mode 100644
index 000000000..c4b575dad
--- /dev/null
+++ b/runtime/libs/ndarray/example/CMakeLists.txt
@@ -0,0 +1,4 @@
+add_executable(example_no_array example_no_array.cpp)
+
+add_executable(example_array example_array.cpp)
+target_link_libraries(example_array PRIVATE ndarray)
diff --git a/runtime/libs/ndarray/example/example_array.cpp b/runtime/libs/ndarray/example/example_array.cpp
new file mode 100644
index 000000000..85d274681
--- /dev/null
+++ b/runtime/libs/ndarray/example/example_array.cpp
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ndarray/Array.h"
+
+#include <iostream>
+#include <iterator>
+
+using namespace ndarray;
+
+void gather_array(const Array<float> &input, Array<float> &output, const Array<int> &indices)
+{
+  assert(indices.shape().rank() == 3);
+  assert(input.shape().rank() == 3);
+  assert(indices.shape().dim(1) == input.shape().rank());
+
+  for (size_t i = 0; i < indices.shape().dim(0); ++i)
+  {
+    for (size_t j = 0; j < indices.shape().dim(1); ++j)
+    {
+      auto index = indices.slice(i, j);
+      output.slice(i, j).assign(input.slice(index[0], index[1]));
+    }
+  }
+}
+
+int main()
+{
+  // fill tensor of shape[3,3,4] with sequential numbers from [0..36)
+  Shape in_shape{3, 3, 4};
+  std::vector<float> input_data(in_shape.element_count());
+  for (size_t i = 0; i < in_shape.element_count(); ++i)
+    input_data[i] = i;
+
+  Array<float> input(input_data.data(), in_shape);
+
+  // select column-vectors on main diagonal
+  Shape indices_shape{1, 3, 2};
+  std::vector<int> indices_data(indices_shape.element_count());
+  Array<int> indices(indices_data.data(), indices_shape);
+
+  indices.slice(0, 0) = {0, 0};
+  indices.slice(0, 1) = {1, 1};
+  indices.slice(0, 2) = {2, 2};
+
+  Shape output_shape{1, 3, 4};
+  std::vector<float> output_data(output_shape.element_count());
+
+  Array<float> output(output_data.data(), output_shape);
+
+  gather_array(input, output, indices);
+
+  for (size_t i = 0; i < indices_shape.dim(0); ++i)
+  {
+    for (size_t j = 0; j < indices_shape.dim(1); ++j)
+    {
+      auto output_piece = output.slice(i, j);
+      std::ostream_iterator<int> cout_it(std::cout, ", ");
+      std::copy(output_piece.begin(), output_piece.end(), cout_it);
+      std::cout << std::endl;
+    }
+  }
+}
diff --git a/runtime/libs/ndarray/example/example_no_array.cpp b/runtime/libs/ndarray/example/example_no_array.cpp
new file mode 100644
index 000000000..3a4d05dca
--- /dev/null
+++ b/runtime/libs/ndarray/example/example_no_array.cpp
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <array>
+#include <vector>
+#include <algorithm>
+#include <cassert>
+#include <iostream>
+
+void gather_no_array(const float *in_data, const std::array<size_t, 3> &dims, float *out_data,
+                     const std::array<size_t, 3> &out_dims, //[nselections,
+                     const int *indices, const std::array<size_t, 3> &indices_dims)
+{
+  assert(indices_dims[1] == dims.size());
+
+  for (int i = 0; i < indices_dims[0]; ++i)
+  {
+    for (int j = 0; j < indices_dims[1]; ++j)
+    {
+      const int *index_ptr = indices + i * indices_dims[2] * indices_dims[1] + j * indices_dims[2];
+
+      size_t in_offset = index_ptr[0] * dims[2] * dims[1] + index_ptr[1] * dims[2];
+
+      const float *in_ptr = in_data + in_offset;
+
+      size_t out_offset = i * out_dims[2] * out_dims[1] + j * out_dims[2];
+
+      float *out_ptr = out_data + out_offset;
+
+      for (int k = 0; k < dims[2]; ++k)
+      {
+        out_ptr[k] = in_ptr[k];
+      }
+    }
+  }
+}
+
+int main()
+{
+  std::array<size_t, 3> in_dims{3, 3, 4};
+  std::vector<float> input(3 * 3 * 4);
+  for (size_t i = 0; i < 3 * 3 * 4; ++i)
+    input[i] = i;
+
+  std::array<size_t, 3> indices_shape{1, 3, 2};
+  std::vector<int> indices(1 * 3 * 2);
+
+  indices[0] = 0;
+  indices[1] = 0;
+  indices[2] = 1;
+  indices[3] = 1;
+  indices[4] = 2;
+  indices[5] = 2;
+
+  std::array<size_t, 3> output_dims{1, 3, 4};
+  std::vector<float> output(1 * 3 * 4);
+
+  gather_no_array(input.data(), in_dims, output.data(), output_dims, indices.data(), indices_shape);
+
+  for (size_t i = 0; i < output_dims[0]; ++i)
+  {
+    for (size_t j = 0; j < output_dims[1]; ++j)
+    {
+      auto out_ptr = output.data() + i * output_dims[1] * output_dims[2] + j * output_dims[2];
+      for (size_t k = 0; k < output_dims[2]; ++k)
+      {
+        std::cout << out_ptr[k] << ", ";
+      }
+      std::cout << std::endl;
+    }
+  }
+}
diff --git a/runtime/libs/ndarray/include/ndarray/Array.h b/runtime/libs/ndarray/include/ndarray/Array.h
new file mode 100644
index 000000000..3890cc26b
--- /dev/null
+++ b/runtime/libs/ndarray/include/ndarray/Array.h
@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _NDARRAY_ARRAY_H_
+#define _NDARRAY_ARRAY_H_
+
+#include "Common.h"
+
+#include "ContiguousSpan.h"
+#include "Shape.h"
+
+#if __cplusplus < 201402L
+#include "detail/cxx14.h" //integer_sequence and make_index_dequence definitions
+#else
+#include <utility>
+#endif
+
+#include <algorithm>
+#include <cassert>
+#include <type_traits>
+#include <array>
+#include <tuple>
+#include <cstddef>
+
+namespace ndarray
+{
+
+// there is no index_sequence before c++14
+#if __cplusplus < 201402L
+
+template <size_t... Nums> using index_sequence = cxx14::index_sequence<Nums...>;
+
+template <size_t Num> using make_index_sequence = cxx14::make_index_sequence<Num>;
+
+#else
+
+template <size_t... Nums> using index_sequence = std::index_sequence<Nums...>;
+
+template <size_t _Num> using make_index_sequence = std::make_index_sequence<_Num>;
+
+#endif //__cplusplus < 201402L
+
+struct Strides
+{
+  explicit Strides(Shape s) : _strides{} { fillStrides(s); }
+
+  int operator[](size_t idx) const noexcept { return _strides[idx]; }
+
+  // since we don't have c++14 fold expression
+  template <typename Seq, typename... Ts> struct _calc_offset;
+
+  template <size_t Num, size_t... Nums, typename T, typename... Ts>
+  struct _calc_offset<index_sequence<Num, Nums...>, T, Ts...>
+  {
+    static constexpr size_t get(const std::array<int, 8> &strides, int x, Ts... xs)
+    {
+      return _calc_offset<index_sequence<Nums...>, Ts...>::get(strides, xs...) +
+             x * std::get<Num>(strides);
+    }
+  };
+
+  template <size_t Num, typename T> struct _calc_offset<index_sequence<Num>, T>
+  {
+    static constexpr size_t get(const std::array<int, 8> &strides, int x)
+    {
+      return x * std::get<Num>(strides);
+    }
+  };
+
+  template <typename Seq, typename... Ts> constexpr size_t offset(Seq, Ts... x) const noexcept
+  {
+    // return ( 0 + ... + (std::get<Nums>(_strides) * x)); in c++14
+    return _calc_offset<Seq, Ts...>::get(_strides, x...);
+  }
+
+private:
+  void fillStrides(const Shape &s) noexcept
+  {
+    int rank = s.rank();
+    _strides[rank - 1] = 1;
+    for (int d = rank - 2; d >= 0; --d)
+    {
+      _strides[d] = _strides[d + 1] * s.dim(d + 1);
+    }
+  }
+
+  std::array<int, NDARRAY_MAX_DIMENSION_COUNT> _strides;
+};
+
+template <typename T> class Array
+{
+public:
+  Array(T *data, Shape shape) noexcept : _data(data), _shape(shape), _strides(shape) {}
+
+  Array(const Array &) = delete;
+
+  Array(Array &&a) noexcept : _data(a._data), _shape(a._shape), _strides(a._strides)
+  {
+    a._data = nullptr;
+  }
+
+  template <typename... Ts> T &at(Ts... x) const noexcept { return _at(static_cast<size_t>(x)...); }
+
+  /**
+   * @brief returns last dimension as ContigniousSpan
+   * @param x indices of slice to take. See tests for usage details
+   * @return slice at given position
+   */
+  template <typename... Ts> ContiguousSpan<T, std::is_const<T>::value> slice(Ts... x) noexcept
+  {
+    assert(sizeof...(Ts) == _shape.rank() - 1);
+    return {&at(x..., 0ul), _shape.dim(_shape.rank() - 1)};
+  }
+
+  /**
+   * @brief returns last dimension as ContigniousSpan
+   * @param x indices of slice to take. See tests for usage details
+   * @return slice at given position
+   */
+  template <typename... Ts> ContiguousSpan<T, true> slice(Ts... x) const noexcept
+  {
+    assert(sizeof...(Ts) == _shape.rank() - 1);
+    return {&at(x..., 0ul), _shape.dim(_shape.rank() - 1)};
+  }
+
+  ContiguousSpan<T, std::is_const<T>::value> flat() noexcept
+  {
+    return {_data, _shape.element_count()};
+  }
+
+  ContiguousSpan<T, true> flat() const noexcept { return {_data, _shape.element_count()}; }
+
+  const Shape &shape() const noexcept { return _shape; }
+
+private:
+  template <typename... Ts> T &_at(Ts... x) const noexcept
+  {
+    assert(sizeof...(x) == _shape.rank());
+    using Indices = make_index_sequence<sizeof...(Ts)>;
+    return _data[offset(Indices{}, x...)];
+  }
+
+  template <typename... Ts, size_t... Nums>
+  size_t offset(index_sequence<Nums...> seq, Ts... x) const noexcept
+  {
+    static_assert(
+        sizeof...(Ts) == sizeof...(Nums),
+        "Sanity check failed. Generated index sequence size is not equal to argument count");
+
+    return _strides.offset(seq, x...);
+  }
+
+  T *_data;
+  Shape _shape;
+  Strides _strides;
+};
+
+template <typename To, typename From> Array<To> array_cast(Array<From> &&from, Shape newShape)
+{
+  assert(from.shape().element_count() / (sizeof(To) / sizeof(From)) == newShape.element_count());
+  return Array<To>(reinterpret_cast<To *>(from.flat().data()), newShape);
+}
+
+template <typename To, typename From>
+Array<const To> array_cast(const Array<From> &from, Shape newShape)
+{
+  assert(from.shape().element_count() / (sizeof(To) / sizeof(From)) == newShape.element_count());
+  return Array<To>(reinterpret_cast<const To *>(from.flat().data()), newShape);
+}
+
+#ifndef NDARRAY_INLINE_TEMPLATES
+
+extern template class Array<float>;
+extern template class Array<int32_t>;
+extern template class Array<uint32_t>;
+extern template class Array<uint8_t>;
+
+#endif // NDARRAY_INLINE_TEMPLATES
+
+} // namespace ndarray
+
+#endif //_NDARRAY_ARRAY_H_
diff --git a/runtime/libs/ndarray/include/ndarray/Common.h b/runtime/libs/ndarray/include/ndarray/Common.h
new file mode 100644
index 000000000..aa0cc6fe2
--- /dev/null
+++ b/runtime/libs/ndarray/include/ndarray/Common.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _NDARRAY_COMMON_H_
+#define _NDARRAY_COMMON_H_
+
+#define NDARRAY_MAX_DIMENSION_COUNT 8
+
+#endif //_NDARRAY_COMMON_H_
diff --git a/runtime/libs/ndarray/include/ndarray/ContiguousSpan.h b/runtime/libs/ndarray/include/ndarray/ContiguousSpan.h
new file mode 100644
index 000000000..8caa6a686
--- /dev/null
+++ b/runtime/libs/ndarray/include/ndarray/ContiguousSpan.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _NDARRAY_CONTIGNIOUS_SPAN_H_
+#define _NDARRAY_CONTIGNIOUS_SPAN_H_
+
+#include <type_traits>
+#include <vector>
+#include <cstdint>
+#include <cstddef>
+#include <cassert>
+
+namespace ndarray
+{
+
+template <typename T, bool isConst = false> class ContiguousSpan
+{
+public:
+  using pointer_type = typename std::conditional<isConst, const T *, T *>::type;
+  using reference_type = typename std::conditional<isConst, const T &, T &>::type;
+  using iterator_type = pointer_type;
+
+  ContiguousSpan(pointer_type data, size_t len) noexcept : _data(data), _len(len) {}
+
+  template <typename It>
+  explicit ContiguousSpan(It first, It last) noexcept
+      : _data(&*first), _len(std::distance(first, last))
+  {
+  }
+
+  ContiguousSpan(const ContiguousSpan &) = delete;
+
+  ContiguousSpan(ContiguousSpan &&s) noexcept : _data(s._data), _len(s._len) { s._data = nullptr; }
+
+  operator ContiguousSpan<T, true>() { return ContiguousSpan<T, true>{_data, _len}; }
+
+  reference_type operator[](size_t idx) const noexcept { return _data[idx]; }
+
+  reference_type at(size_t idx) const noexcept { return _data[idx]; }
+
+  ContiguousSpan<T, isConst> offset(size_t offset)
+  {
+    assert(offset <= _len);
+    return {_data + offset, _len - offset};
+  }
+
+  template <typename From, bool _ = isConst>
+  typename std::enable_if<!_, void>::type assign(const From &f) noexcept
+  {
+    assignFrom(std::begin(f), std::end(f));
+  }
+
+  template <typename U, bool _ = isConst>
+  typename std::enable_if<!_, ContiguousSpan &>::type
+  operator=(std::initializer_list<U> list) noexcept
+  {
+    assignFrom(std::begin(list), std::end(list));
+    return *this;
+  }
+
+  template <typename It, bool _ = isConst>
+  typename std::enable_if<!_, void>::type assignFrom(It first, It last) noexcept
+  {
+    std::copy(first, last, begin());
+  }
+
+  size_t size() const { return _len; }
+
+  iterator_type begin() const { return iterator_type{_data}; }
+
+  iterator_type end() const { return iterator_type{_data + _len}; }
+
+  pointer_type data() { return _data; }
+
+private:
+  pointer_type _data;
+  size_t _len;
+};
+
+#ifndef NDARRAY_INLINE_TEMPLATES
+
+extern template class ContiguousSpan<float, true>;
+extern template class ContiguousSpan<float, false>;
+extern template class ContiguousSpan<int32_t, true>;
+extern template class ContiguousSpan<int32_t, false>;
+extern template class ContiguousSpan<uint32_t, true>;
+extern template class ContiguousSpan<uint32_t, false>;
+extern template class ContiguousSpan<uint8_t, true>;
+extern template class ContiguousSpan<uint8_t, false>;
+
+#endif // NDARRAY_INLINE_TEMPLATES
+
+} // namespace ndarray
+
+#endif //_NDARRAY_CONTIGNIOUS_SPAN_H_
diff --git a/runtime/libs/ndarray/include/ndarray/Shape.h b/runtime/libs/ndarray/include/ndarray/Shape.h
new file mode 100644
index 000000000..fa58613b8
--- /dev/null
+++ b/runtime/libs/ndarray/include/ndarray/Shape.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _NDARRAY_SHAPE_H_
+#define _NDARRAY_SHAPE_H_
+
+#include "Common.h"
+
+#include <array>
+#include <cassert>
+#include <cstddef>
+
+namespace ndarray
+{
+
+class Shape
+{
+public:
+  //_dims{} here and later since array does not have std::initializer_list ctor
+  // and aggregate initialization is not allowed here
+  explicit Shape(size_t rank) noexcept : _dims{}, _rank(rank)
+  {
+    std::fill(_dims.begin(), _dims.end(), 0);
+  }
+
+  Shape(std::initializer_list<size_t> list) noexcept : _dims{}, _rank(list.size())
+  {
+    std::copy(list.begin(), list.end(), _dims.begin());
+  }
+
+  size_t dim(int i) const noexcept { return _dims.at(i); }
+
+  size_t &dim(int i) noexcept { return _dims.at(i); }
+
+  size_t element_count() const noexcept
+  {
+    uint32_t res = 1;
+    for (size_t i = 0; i < rank(); ++i)
+      res *= dim(i);
+    assert(res <= 0xffffffff);
+    return res;
+  }
+
+  size_t rank() const noexcept { return _rank; }
+
+private:
+  std::array<size_t, NDARRAY_MAX_DIMENSION_COUNT> _dims;
+  size_t _rank;
+};
+
+} // namespace ndarray
+
+#endif //_NDARRAY_SHAPE_H_
diff --git a/runtime/libs/ndarray/src/Array.cpp b/runtime/libs/ndarray/src/Array.cpp
new file mode 100644
index 000000000..f9c9de9d3
--- /dev/null
+++ b/runtime/libs/ndarray/src/Array.cpp
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ndarray/Array.h"
+
+namespace ndarray
+{
+
+template class Array<float>;
+template class Array<int32_t>;
+template class Array<uint32_t>;
+template class Array<uint8_t>;
+
+} // namespace ndarray
diff --git a/runtime/libs/ndarray/src/ContiguousSpan.cpp b/runtime/libs/ndarray/src/ContiguousSpan.cpp
new file mode 100644
index 000000000..e06cfc2a1
--- /dev/null
+++ b/runtime/libs/ndarray/src/ContiguousSpan.cpp
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ndarray/ContiguousSpan.h"
+
+namespace ndarray
+{
+
+template class ContiguousSpan<float, true>;
+template class ContiguousSpan<float, false>;
+template class ContiguousSpan<int32_t, true>;
+template class ContiguousSpan<int32_t, false>;
+template class ContiguousSpan<uint32_t, true>;
+template class ContiguousSpan<uint32_t, false>;
+template class ContiguousSpan<uint8_t, true>;
+template class ContiguousSpan<uint8_t, false>;
+
+} // namespace ndarray
diff --git a/runtime/libs/ndarray/src/detail/cxx14.h b/runtime/libs/ndarray/src/detail/cxx14.h
new file mode 100644
index 000000000..81135b3f2
--- /dev/null
+++ b/runtime/libs/ndarray/src/detail/cxx14.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _NDARRAY_CXX14_H_
+#define _NDARRAY_CXX14_H_
+
+namespace ndarray
+{
+
+namespace cxx14
+{
+
+template <size_t... Nums> struct index_sequence
+{
+  using value_type = size_t;
+
+  static constexpr std::size_t size() noexcept { return sizeof...(Nums); }
+};
+
+namespace detail
+{
+
+template <size_t v, typename Seq> struct _append;
+
+template <size_t v, size_t... Nums> struct _append<v, index_sequence<Nums...>>
+{
+  using result = index_sequence<Nums..., v>;
+};
+
+template <size_t Len> struct make_index_sequence
+{
+  using result =
+      typename detail::_append<Len - 1, typename make_index_sequence<Len - 1>::result>::result;
+};
+
+template <> struct make_index_sequence<1>
+{
+  using result = index_sequence<0>;
+};
+
+template <> struct make_index_sequence<0>
+{
+  using result = index_sequence<>;
+};
+
+} // namespace detail
+
+template <size_t Num> using make_index_sequence = typename detail::make_index_sequence<Num>::result;
+
+} // namespace cxx14
+
+} // namespace ndarray
+
+#endif //_NDARRAY_CXX14_H_
diff --git a/runtime/libs/ndarray/test/CMakeLists.txt b/runtime/libs/ndarray/test/CMakeLists.txt
new file mode 100644
index 000000000..16f8779ee
--- /dev/null
+++ b/runtime/libs/ndarray/test/CMakeLists.txt
@@ -0,0 +1,17 @@
+if(NOT BUILD_NDARRAY_TEST)
+    return()
+endif()
+
+add_executable(ndarray_test ndarray_test.cpp)
+
+target_link_libraries(ndarray_test PRIVATE ndarray)
+
+nnfw_find_package(GTest)
+if(NOT GTest_FOUND)
+    message(STATUS "GTest not avaialble. Skipping NDArray test build")
+    return()
+endif(NOT GTest_FOUND)
+
+target_link_libraries(ndarray_test PUBLIC gtest gtest_main ${LIB_PTHREAD})
+
+add_test(ndarray_test ndarray_test)
diff --git a/runtime/libs/ndarray/test/ndarray_test.cpp b/runtime/libs/ndarray/test/ndarray_test.cpp
new file mode 100644
index 000000000..0aa948c72
--- /dev/null
+++ b/runtime/libs/ndarray/test/ndarray_test.cpp
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "gtest/gtest.h"
+
+#include "ndarray/Array.h"
+
+using namespace ndarray;
+
+TEST(NDArray_tests, basic_data_test)
+{
+
+  float raw_data[] = {1, 2, 3, 4};
+
+  Array<float> data22{raw_data, {2, 2}};
+
+  ASSERT_FLOAT_EQ(data22.at(0, 0), 1);
+  ASSERT_FLOAT_EQ(data22.at(0, 1), 2);
+  ASSERT_FLOAT_EQ(data22.at(1, 0), 3);
+  ASSERT_FLOAT_EQ(data22.at(1, 1), 4);
+
+  Array<float> data14{raw_data, {1, 4}};
+  ASSERT_FLOAT_EQ(data22.at(0, 0), 1);
+  ASSERT_FLOAT_EQ(data22.at(0, 1), 2);
+  ASSERT_FLOAT_EQ(data22.at(0, 2), 3);
+  ASSERT_FLOAT_EQ(data22.at(0, 3), 4);
+}
+
+TEST(NDArray_tests, slice_write_test)
+{
+  float raw_data[4] = {0};
+
+  Array<float> data22{raw_data, {2, 2}};
+
+  data22.slice(1) = {1, 2};
+
+  ASSERT_FLOAT_EQ(data22.at(0, 0), 0);
+  ASSERT_FLOAT_EQ(data22.at(0, 1), 0);
+  ASSERT_FLOAT_EQ(data22.at(1, 0), 1);
+  ASSERT_FLOAT_EQ(data22.at(1, 1), 2);
+}
+
+TEST(NDArray_tests, slice_read_test)
+{
+  float raw_data[4] = {1, 2, 3, 4};
+
+  Array<float> data22{raw_data, {2, 2}};
+
+  auto slice = data22.slice(1);
+
+  ASSERT_FLOAT_EQ(slice[0], 3);
+  ASSERT_FLOAT_EQ(slice[1], 4);
+}
+
+TEST(NDArray_tests, multidim_test)
+{
+  float raw_data[5] = {0, 1, 2, 3, 4};
+
+  Array<float> data22{raw_data, {1, 1, 1, 1, 5}};
+
+  ASSERT_FLOAT_EQ(data22.at(0, 0, 0, 0, 0), 0);
+  ASSERT_FLOAT_EQ(data22.at(0, 0, 0, 0, 1), 1);
+  ASSERT_FLOAT_EQ(data22.at(0, 0, 0, 0, 2), 2);
+  ASSERT_FLOAT_EQ(data22.at(0, 0, 0, 0, 3), 3);
+  ASSERT_FLOAT_EQ(data22.at(0, 0, 0, 0, 4), 4);
+}
+
+TEST(NDArray_tests, slice_assign_test)
+{
+  std::vector<float> v1{1, 2, 3, 4, 5};
+  std::vector<float> v2(5);
+
+  ContiguousSpan<float> span1(v1.begin(), v1.end());
+  ContiguousSpan<float> span2(v2.begin(), v2.end());
+
+  span2.assign(span1);
+
+  ASSERT_EQ(v1, v2);
+}
diff --git a/runtime/libs/nnapi/CMakeLists.txt b/runtime/libs/nnapi/CMakeLists.txt
new file mode 100644
index 000000000..a5d9490d1
--- /dev/null
+++ b/runtime/libs/nnapi/CMakeLists.txt
@@ -0,0 +1,3 @@
+add_subdirectories()
+
+add_library(nnfw_lib_nnapi ALIAS nnfw_lib_nnapi_1_2)
diff --git a/runtime/libs/nnapi/v1.1/CMakeLists.txt b/runtime/libs/nnapi/v1.1/CMakeLists.txt
new file mode 100644
index 000000000..dc018c60f
--- /dev/null
+++ b/runtime/libs/nnapi/v1.1/CMakeLists.txt
@@ -0,0 +1,4 @@
+add_library(nnfw_lib_nnapi_1_1 INTERFACE)
+
+target_include_directories(nnfw_lib_nnapi_1_1 INTERFACE ${CMAKE_CURRENT_SOURCE_DIR}/include)
+target_link_libraries(nnfw_lib_nnapi_1_1 INTERFACE nnfw-nnapi-header)
diff --git a/runtime/libs/nnapi/v1.1/include/NeuralNetworksExShim.h b/runtime/libs/nnapi/v1.1/include/NeuralNetworksExShim.h
new file mode 100644
index 000000000..f684dab90
--- /dev/null
+++ b/runtime/libs/nnapi/v1.1/include/NeuralNetworksExShim.h
@@ -0,0 +1,64 @@
+/* Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+   Copyright 2017 The TensorFlow Authors. All Rights Reserved.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+==============================================================================*/
+
+/**
+ * @file     NeuralNetworksExShim.h
+ * @brief    This file contains an actual implementation of
+ *           ANeuralNetworksModel_addOperationEx function
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef NN_API_EX_SHIM_H
+#define NN_API_EX_SHIM_H
+
+#include "NeuralNetworksEx.h"
+#include "NeuralNetworksLoadHelpers.h"
+
+typedef int (*ANeuralNetworksModel_addOperationEx_fn)(ANeuralNetworksModel *model,
+                                                      ANeuralNetworksOperationTypeEx type,
+                                                      uint32_t inputCount, const uint32_t *inputs,
+                                                      uint32_t outputCount,
+                                                      const uint32_t *outputs);
+
+/**
+ * @brief Add an extended operation to a model.
+ *
+ * @param[in] model The model to be modified.
+ * @param[in] type The type of extended operation.
+ * @param[in] inputCount The number of entries in the inputs array.
+ * @param[in] inputs An array of indexes identifying each operand.
+ * @param[in] outputCount The number of entries in the outputs array.
+ * @param[in] outputs An array of indexes identifying each operand.
+ *
+ * @note The operands specified by inputs and outputs must have been
+ *       previously added by calls to {@link ANeuralNetworksModel_addOperand}.\n
+ *       Attempting to modify a model once {@link ANeuralNetworksModel_finish}
+ *       has been called will return an error.\n
+ *       See {@link ANeuralNetworksModel} for information on multithreaded usage.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+
+inline int ANeuralNetworksModel_addOperationEx(ANeuralNetworksModel *model,
+                                               ANeuralNetworksOperationTypeEx type,
+                                               uint32_t inputCount, const uint32_t *inputs,
+                                               uint32_t outputCount, const uint32_t *outputs)
+{
+  LOAD_FUNCTION(ANeuralNetworksModel_addOperationEx);
+  EXECUTE_FUNCTION_RETURN(model, type, inputCount, inputs, outputCount, outputs);
+}
+
+#endif // NN_API_EX_SHIM_H
diff --git a/runtime/libs/nnapi/v1.1/include/NeuralNetworksLoadHelpers.h b/runtime/libs/nnapi/v1.1/include/NeuralNetworksLoadHelpers.h
new file mode 100644
index 000000000..201465f9c
--- /dev/null
+++ b/runtime/libs/nnapi/v1.1/include/NeuralNetworksLoadHelpers.h
@@ -0,0 +1,141 @@
+/* Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+   Copyright 2017 The TensorFlow Authors. All Rights Reserved.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+==============================================================================*/
+
+// NOTE To minimize diff with upstream tensorflow, disable clang-format
+// clang-format off
+
+// NOTE This header is derived from part of the following file (in TensorFlow v1.12)
+//       'externals/tensorflow/tensorflow/contrib/lite/nnapi/NeuralNetworksShim.h'
+
+/**
+ * @file NeuralNetworksLoadHelpers.h
+ * @ingroup COM_AI_RUNTIME
+ * @brief This file contains functions to load NN API runtime library
+ */
+
+#ifndef __NEURAL_NETWORKS_LOAD_HELPER_H__
+#define __NEURAL_NETWORKS_LOAD_HELPER_H__
+
+#include <dlfcn.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+/**
+ * @brief Print log data
+ * @param[in] format    Format string of @c printf
+ * @param[in] args      Argument after format string. (Same with @c printf)
+ */
+#define NNAPI_LOG(format, ...) printf(format "\n", __VA_ARGS__);
+
+/**
+ * @brief Create a function pointer named @c fn after loading NN API library
+ * @param[in] name    Name of a function
+ */
+#define LOAD_FUNCTION(name) \
+  static name##_fn fn = reinterpret_cast<name##_fn>(nnfw::loadFunction(#name));
+
+/**
+ * @brief Run @c fn function. @c fn is created by @ref LOAD_FUNCTION
+ * @param[in] args    List of arguments for the function @c fn
+ */
+#define EXECUTE_FUNCTION(...) \
+  if (fn != nullptr) {        \
+    fn(__VA_ARGS__);          \
+  }
+
+/**
+ * @brief Run @c fn function. @c fn is created by @ref LOAD_FUNCTION
+ * @param[in] args    List of arguments for the function @c fn
+ * @return            the return value of @c fn
+ */
+#define EXECUTE_FUNCTION_RETURN(...) return fn != nullptr ? fn(__VA_ARGS__) : 0;
+
+namespace nnfw
+{
+
+/**
+ * @brief Load NN API library
+ * @param[in] name path of NN API library
+ * @return a symbol table handle of NN API library
+ */
+inline void* loadLibrary(const char* name) {
+  // TODO: change RTLD_LOCAL? Assumes there can be multiple instances of nn
+  // api RT
+  void* handle = nullptr;
+#if 1 //#ifdef __ANDROID__
+  handle = dlopen(name, RTLD_LAZY | RTLD_LOCAL);
+  if (handle == nullptr) {
+    NNAPI_LOG("nnapi error: unable to open library %s", name);
+    NNAPI_LOG("             %s", dlerror());
+  }
+#endif
+  return handle;
+}
+
+/**
+ * @brief Load libneuralnetworks.so and return handle of library
+ * @return a symbol table handle of NN API library
+ */
+inline void* getLibraryHandle() {
+  static void* handle = loadLibrary("libneuralnetworks.so");
+  return handle;
+}
+
+/**
+ * @brief Return function ptr in libneuralnetworks.so
+ * @param[in] name    Name of function
+ * @return function pointer
+ */
+inline void* loadFunction(const char* name) {
+  void* fn = nullptr;
+  if (getLibraryHandle() != nullptr) {
+    fn = dlsym(getLibraryHandle(), name);
+  }
+  if (fn == nullptr) {
+    NNAPI_LOG("nnapi error: unable to open function %s", name);
+    NNAPI_LOG("             %s", dlerror());
+    abort();
+  }
+  else {
+#ifdef _GNU_SOURCE
+    Dl_info info;
+    if (dladdr(fn, &info))
+    {
+      NNAPI_LOG("nnapi function '%s' is loaded from '%s' ", name, info.dli_fname);
+    }
+    else
+    {
+      NNAPI_LOG("nnapi function '%s' is failed to load", name);
+    }
+
+#endif // _GNU_SOURCE
+  }
+  return fn;
+}
+
+/**
+ * @brief Check if libneuralnetworks.so can be loaded
+ * @return @c true if loading is successful, otherwise @c false.
+ */
+inline bool NNAPIExists() {
+  static bool nnapi_is_available = getLibraryHandle();
+  return nnapi_is_available;
+}
+
+} // namespace nnfw
+
+#endif // __NEURAL_NETWORKS_LOAD_HELPER_H__
diff --git a/runtime/libs/nnapi/v1.1/include/NeuralNetworksShim.h b/runtime/libs/nnapi/v1.1/include/NeuralNetworksShim.h
new file mode 100644
index 000000000..60b16f766
--- /dev/null
+++ b/runtime/libs/nnapi/v1.1/include/NeuralNetworksShim.h
@@ -0,0 +1,709 @@
+/* Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+   Copyright 2017 The TensorFlow Authors. All Rights Reserved.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+==============================================================================*/
+
+// NOTE To minimize diff with upstream tensorflow, disable clang-format
+// clang-format off
+
+// NOTE This header is derived from part of the following file (in TensorFlow v1.12)
+//       'externals/tensorflow/tensorflow/contrib/lite/nnapi/NeuralNetworksShim.h'
+#ifndef __NEURAL_NETWORKS_SHIM__
+#define __NEURAL_NETWORKS_SHIM__
+
+#include "NeuralNetworks.h"
+#include "NeuralNetworksLoadHelpers.h"
+
+// nn api function types
+
+typedef int (*ANeuralNetworksMemory_createFromFd_fn)(
+    size_t size, int protect, int fd, size_t offset,
+    ANeuralNetworksMemory** memory);
+
+typedef void (*ANeuralNetworksMemory_free_fn)(ANeuralNetworksMemory* memory);
+
+typedef int (*ANeuralNetworksModel_create_fn)(ANeuralNetworksModel** model);
+
+typedef int (*ANeuralNetworksModel_finish_fn)(ANeuralNetworksModel* model);
+
+typedef void (*ANeuralNetworksModel_free_fn)(ANeuralNetworksModel* model);
+
+typedef int (*ANeuralNetworksCompilation_create_fn)(
+    ANeuralNetworksModel* model, ANeuralNetworksCompilation** compilation);
+
+typedef void (*ANeuralNetworksCompilation_free_fn)(
+    ANeuralNetworksCompilation* compilation);
+
+typedef int (*ANeuralNetworksCompilation_setPreference_fn)(
+    ANeuralNetworksCompilation* compilation, int32_t preference);
+
+typedef int (*ANeuralNetworksCompilation_finish_fn)(
+    ANeuralNetworksCompilation* compilation);
+
+typedef int (*ANeuralNetworksModel_addOperand_fn)(
+    ANeuralNetworksModel* model, const ANeuralNetworksOperandType* type);
+
+typedef int (*ANeuralNetworksModel_setOperandValue_fn)(
+    ANeuralNetworksModel* model, int32_t index, const void* buffer,
+    size_t length);
+
+typedef int (*ANeuralNetworksModel_setOperandValueFromMemory_fn)(
+    ANeuralNetworksModel* model, int32_t index,
+    const ANeuralNetworksMemory* memory, size_t offset, size_t length);
+
+typedef int (*ANeuralNetworksModel_addOperation_fn)(
+    ANeuralNetworksModel* model, ANeuralNetworksOperationType type,
+    uint32_t inputCount, const uint32_t* inputs, uint32_t outputCount,
+    const uint32_t* outputs);
+
+typedef int (*ANeuralNetworksModel_identifyInputsAndOutputs_fn)(
+    ANeuralNetworksModel* model, uint32_t inputCount, const uint32_t* inputs,
+    uint32_t outputCount, const uint32_t* outputs);
+
+typedef int (*ANeuralNetworksModel_relaxComputationFloat32toFloat16_fn)(
+    ANeuralNetworksModel* model, bool allow);
+
+typedef int (*ANeuralNetworksExecution_create_fn)(
+    ANeuralNetworksCompilation* compilation,
+    ANeuralNetworksExecution** execution);
+
+typedef void (*ANeuralNetworksExecution_free_fn)(
+    ANeuralNetworksExecution* execution);
+
+typedef int (*ANeuralNetworksExecution_setInput_fn)(
+    ANeuralNetworksExecution* execution, int32_t index,
+    const ANeuralNetworksOperandType* type, const void* buffer, size_t length);
+
+typedef int (*ANeuralNetworksExecution_setInputFromMemory_fn)(
+    ANeuralNetworksExecution* execution, int32_t index,
+    const ANeuralNetworksOperandType* type, const ANeuralNetworksMemory* memory,
+    size_t offset, size_t length);
+
+typedef int (*ANeuralNetworksExecution_setOutput_fn)(
+    ANeuralNetworksExecution* execution, int32_t index,
+    const ANeuralNetworksOperandType* type, void* buffer, size_t length);
+
+typedef int (*ANeuralNetworksExecution_setOutputFromMemory_fn)(
+    ANeuralNetworksExecution* execution, int32_t index,
+    const ANeuralNetworksOperandType* type, const ANeuralNetworksMemory* memory,
+    size_t offset, size_t length);
+
+typedef int (*ANeuralNetworksExecution_startCompute_fn)(
+    ANeuralNetworksExecution* execution, ANeuralNetworksEvent** event);
+
+typedef int (*ANeuralNetworksEvent_wait_fn)(ANeuralNetworksEvent* event);
+
+typedef void (*ANeuralNetworksEvent_free_fn)(ANeuralNetworksEvent* event);
+
+/**
+ * Creates a shared memory object from a file descriptor.
+ *
+ * The shared memory is backed by a file descriptor via mmap.
+ * See {@link ANeuralNetworksMemory} for a description on how to use
+ * this shared memory.
+ *
+ * @param size The requested size in bytes.
+ *             Must not be larger than the file size.
+ * @param prot The desired memory protection for the mapping.
+ *             It is either PROT_NONE or the bitwise OR of one or
+ *             more of the following flags: PROT_READ, PROT_WRITE.
+ * @param fd The requested file descriptor.
+ *           The file descriptor has to be mmap-able. The file
+ *           descriptor will be duplicated.
+ * @param offset The offset to the beginning of the file of the area to map.
+ *               The offset has to be aligned to a page size.
+ * @param memory The memory object to be created.
+ *               Set to NULL if unsuccessful.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if the request completed normally.
+ */
+inline int ANeuralNetworksMemory_createFromFd(size_t size, int protect, int fd,
+                                              size_t offset,
+                                              ANeuralNetworksMemory** memory) {
+  LOAD_FUNCTION(ANeuralNetworksMemory_createFromFd);
+  EXECUTE_FUNCTION_RETURN(size, protect, fd, offset, memory);
+}
+
+/**
+ * Delete a memory object.
+ *
+ * Destroys the object used by the run time to keep track of the memory.
+ * This will free the underlying actual memory if no other code has open
+ * handles to this memory.
+ *
+ * @param memory The memory object to be freed.
+ */
+inline void ANeuralNetworksMemory_free(ANeuralNetworksMemory* memory) {
+  LOAD_FUNCTION(ANeuralNetworksMemory_free);
+  EXECUTE_FUNCTION(memory);
+}
+
+/**
+ * Create an empty {@link ANeuralNetworksModel}.
+ *
+ * <p>This only creates the object. Computation is performed once
+ * {@link ANeuralNetworksExecution_startCompute} is invoked.
+ *
+ * The model should be constructed with calls to
+ * {@link ANeuralNetworksModel_addOperation} and
+ * {@link ANeuralNetworksModel_addOperand}
+ *
+ * <p>{@link ANeuralNetworksModel_finish} should be called once the model
+ * has been fully constructed.</p>
+ *
+ * <p>{@link ANeuralNetworksModel_free} should be called once the model
+ * is no longer needed.</p>
+ *
+ * @param model The {@link ANeuralNetworksModel} to be created.
+ *              Set to NULL if unsuccessful.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+inline int ANeuralNetworksModel_create(ANeuralNetworksModel** model) {
+  LOAD_FUNCTION(ANeuralNetworksModel_create);
+  EXECUTE_FUNCTION_RETURN(model);
+}
+
+/**
+ * Destroy a model.
+ *
+ * The model need not have been finished by a call to
+ * {@link ANeuralNetworksModel_finish}.
+ *
+ * See {@link ANeuralNetworksModel} for information on multithreaded usage.
+ *
+ * @param model The model to be destroyed. Passing NULL is acceptable and
+ *              results in no operation.
+ */
+inline void ANeuralNetworksModel_free(ANeuralNetworksModel* model) {
+  LOAD_FUNCTION(ANeuralNetworksModel_free);
+  EXECUTE_FUNCTION(model);
+}
+
+/**
+ * Indicate that we have finished modifying a model. Required before
+ * calling {@link ANeuralNetworksCompilation_compile}.
+ *
+ * An application is responsible to make sure that no other thread uses
+ * the model at the same time.
+ *
+ * See {@link ANeuralNetworksModel} for information on multithreaded usage.
+ *
+ * @param model The model to be finished.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+inline int ANeuralNetworksModel_finish(ANeuralNetworksModel* model) {
+  LOAD_FUNCTION(ANeuralNetworksModel_finish);
+  EXECUTE_FUNCTION_RETURN(model);
+}
+
+/**
+ * Add an operand to a model.
+ *
+ * The order in which the operands are added is important. The first one added
+ * to a model will have the index value 0, the second 1, etc. These indexes are
+ * used as operand identifiers in {@link ANeuralNetworksModel_addOperation},
+ * {@link ANeuralNetworksExecution_setInput},
+ * {@link ANeuralNetworksExecution_setInputFromMemory},
+ * {@link ANeuralNetworksExecution_setOutput},
+ * {@link ANeuralNetworksExecution_setOutputFromMemory} and
+ * {@link ANeuralNetworksExecution_setOperandValue}.
+ *
+ * To build a model that can accommodate inputs of various sizes, as you may
+ * want to do for a CNN, set the size of the dimensions that will vary at run
+ * time to 0. If you do so, provide the full dimensions when calling
+ * {@link ANeuralNetworksExecution_setInput} or {@link
+ * ANeuralNetworksExecution_setInputFromMemory}.
+ *
+ * Attempting to modify a model once {@link ANeuralNetworksModel_finish} has
+ * been called will return an error.
+ *
+ * See {@link ANeuralNetworksModel} for information on multithreaded usage.
+ *
+ * @param model The model to be modified.
+ * @param type The {@link ANeuralNetworksOperandType} that describes the shape
+ * of the operand.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+inline int ANeuralNetworksModel_addOperand(
+    ANeuralNetworksModel* model, const ANeuralNetworksOperandType* type) {
+  LOAD_FUNCTION(ANeuralNetworksModel_addOperand);
+  EXECUTE_FUNCTION_RETURN(model, type);
+}
+
+/**
+ * Sets an operand to a constant value.
+ *
+ * For scalar values, the content of buffer is copied into the model.
+ *
+ * For tensor values, a pointer to the buffer is stored within the model.
+ * The application is responsible for not changing the content of this region
+ * until all executions using this model have completed. As the data may
+ * be copied during processing, modifying the data after this call yields
+ * undefined results.
+ *
+ * Attempting to modify a model once {@link ANeuralNetworksModel_finish} has
+ * been called will return an error.
+ *
+ * See {@link ANeuralNetworksModel} for information on multithreaded usage.
+ *
+ * @param model The model to be modified.
+ * @param index The index of the model operand we're setting.
+ * @param buffer A pointer to the data to use.
+ * @param length The size in bytes of the data value.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+inline int ANeuralNetworksModel_setOperandValue(ANeuralNetworksModel* model,
+                                                int32_t index,
+                                                const void* buffer,
+                                                size_t length) {
+  LOAD_FUNCTION(ANeuralNetworksModel_setOperandValue);
+  EXECUTE_FUNCTION_RETURN(model, index, buffer, length);
+}
+
+/**
+ * Sets an operand to a value stored in a memory object.
+ *
+ * The content of the memory is not copied. A reference to that memory is stored
+ * inside the model. The application is responsible for not changing the content
+ * of the memory region until all executions using this model have completed.
+ * As the data may be copied during processing, modifying the data after this
+ * call yields undefined results.
+ *
+ * Attempting to modify a model once {@link ANeuralNetworksModel_finish} has
+ * been called will return an error.
+ *
+ * See {@link ANeuralNetworksModel} for information on multithreaded usage.
+ *
+ * @param model The model to be modified.
+ * @param index The index of the model operand we're setting.
+ * @param buffer A pointer to the data to use.
+ * @param memory The memory containing the data.
+ * @param offset This specifies the location of the data within the memory.
+ *               The offset is in bytes from the start of memory.
+ * @param length The size in bytes of the data value.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+inline int ANeuralNetworksModel_setOperandValueFromMemory(
+    ANeuralNetworksModel* model, int32_t index,
+    const ANeuralNetworksMemory* memory, size_t offset, size_t length) {
+  LOAD_FUNCTION(ANeuralNetworksModel_setOperandValueFromMemory);
+  EXECUTE_FUNCTION_RETURN(model, index, memory, offset, length);
+}
+
+/**
+ * Add an operation to a model.
+ *
+ * @param model The model to be modified.
+ * @param type The type of the operation.
+ * @param inputCount The number of entries in the inputs array.
+ * @param inputs An array of indexes identifying each operand.
+ * @param outputCount The number of entries in the outputs array.
+ * @param outputs An array of indexes identifying each operand.
+ *
+ * The operands specified by inputs and outputs must have been
+ * previously added by calls to {@link ANeuralNetworksModel_addOperand}.
+ *
+ * Attempting to modify a model once {@link ANeuralNetworksModel_finish} has
+ * been called will return an error.
+ *
+ * See {@link ANeuralNetworksModel} for information on multithreaded usage.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+inline int ANeuralNetworksModel_addOperation(ANeuralNetworksModel* model,
+                                             ANeuralNetworksOperationType type,
+                                             uint32_t inputCount,
+                                             const uint32_t* inputs,
+                                             uint32_t outputCount,
+                                             const uint32_t* outputs) {
+  LOAD_FUNCTION(ANeuralNetworksModel_addOperation);
+  EXECUTE_FUNCTION_RETURN(model, type, inputCount, inputs, outputCount,
+                          outputs);
+}
+
+/**
+ * Specifies which operands will be the model's inputs and outputs.
+ *
+ * An operand cannot be used for both input and output. Doing so will
+ * return an error.
+ *
+ * @param model The model to be modified.
+ * @param inputCount The number of entries in the inputs array.
+ * @param inputs An array of indexes identifying the input operands.
+ * @param outputCount The number of entries in the outputs array.
+ * @param outputs An array of indexes identifying the output operands.
+ *
+ * The operands specified by inputs and outputs must have been
+ * previously added by calls to {@link ANeuralNetworksModel_addOperand}.
+ *
+ * Attempting to modify a model once {@link ANeuralNetworksModel_finish} has
+ * been called will return an error.
+ *
+ * See {@link ANeuralNetworksModel} for information on multithreaded usage.
+ *
+ */
+inline int ANeuralNetworksModel_identifyInputsAndOutputs(
+    ANeuralNetworksModel* model, uint32_t inputCount, const uint32_t* inputs,
+    uint32_t outputCount, const uint32_t* outputs) {
+  LOAD_FUNCTION(ANeuralNetworksModel_identifyInputsAndOutputs);
+  EXECUTE_FUNCTION_RETURN(model, inputCount, inputs, outputCount, outputs);
+}
+
+/**
+ * Specifies whether {@link ANEURALNETWORKS_TENSOR_FLOAT32} is allowed to be
+ * calculated with range and/or precision as low as that of the IEEE 754 16-bit
+ * floating-point format. By default, {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+ * must be calculated using at least the range and precision of the IEEE 754
+ * 32-bit floating-point format.
+ *
+ * @param model The model to be modified.
+ * @param allow 'true' indicates {@link ANEURALNETWORKS_TENSOR_FLOAT32} may be
+ *              calculated with range and/or precision as low as that of the
+ *              IEEE 754 16-bit floating point format. 'false' indicates
+ *              {@link ANEURALNETWORKS_TENSOR_FLOAT32} must be calculated using
+ *              at least the range and precision of the IEEE 754 32-bit floating
+ *              point format.
+ *
+ * Attempting to modify a model once {@link ANeuralNetworksModel_finish} has
+ * been called will return an error.
+ *
+ * Available since API level 28.
+ *
+ * See {@link ANeuralNetworksModel} for information on multithreaded usage.
+ */
+inline int ANeuralNetworksModel_relaxComputationFloat32toFloat16(
+    ANeuralNetworksModel* model, bool allow) {
+  LOAD_FUNCTION(ANeuralNetworksModel_relaxComputationFloat32toFloat16);
+  EXECUTE_FUNCTION_RETURN(model, allow);
+}
+
+/**
+ * Create a {@link ANeuralNetworksCompilation} to compile the given model.
+ * This only creates the object. Compilation is only performed once
+ * {@link ANeuralNetworksCompilation_start} is invoked.
+ *
+ * <p>The provided model must outlive the compilation.</p>
+ *
+ * The model must already have been finished by a call to
+ * {@link ANeuralNetworksModel_finish}.
+ *
+ * See {@link ANeuralNetworksCompilation} for information on multithreaded
+ * usage.
+ *
+ * @param model The {@link ANeuralNetworksModel} to be compiled.
+ * @param compilation The newly created object or NULL if unsuccessful.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_BAD_DATA
+ *         if the model is invalid.
+ */
+inline int ANeuralNetworksCompilation_create(
+    ANeuralNetworksModel* model, ANeuralNetworksCompilation** compilation) {
+  LOAD_FUNCTION(ANeuralNetworksCompilation_create);
+  EXECUTE_FUNCTION_RETURN(model, compilation);
+}
+
+/**
+ * Destroy a compilation.
+ *
+ * <p>If called on a compilation for which
+ * {@link ANeuralNetworksCompilation_start} has been called, the
+ * function will return immediately but will mark the compilation to be deleted
+ * once the compilation completes. The {@link ANeuralNetworksCompilation_wait}
+ * will return ERROR_DELETED.
+ *
+ * See {@link ANeuralNetworksCompilation} for information on multithreaded
+ * usage.
+ *
+ * @param compilation The compilation to be destroyed. Passing NULL is
+ * acceptable and results in no operation.
+ */
+inline void ANeuralNetworksCompilation_free(
+    ANeuralNetworksCompilation* compilation) {
+  LOAD_FUNCTION(ANeuralNetworksCompilation_free);
+  EXECUTE_FUNCTION(compilation);
+}
+
+/**
+ * Sets the execution preference.
+ *
+ * <p>Provides guidance to the runtime when trade-offs are possible.</p>
+ *
+ * See {@link ANeuralNetworksCompilation} for information on multithreaded
+ * usage.
+ *
+ * @param compilation The compilation to be modified.
+ * @param preference Either {@link PREFER_LOW_POWER},
+ *                  {@link PREFER_SINGLE_FAST_ANSWER}, or
+ *                  {@link PREFER_SUSTAINED_SPEED}.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+inline int ANeuralNetworksCompilation_setPreference(
+    ANeuralNetworksCompilation* compilation, int32_t preference) {
+  LOAD_FUNCTION(ANeuralNetworksCompilation_setPreference);
+  EXECUTE_FUNCTION_RETURN(compilation, preference);
+}
+
+/**
+ * Waits until the compilation completes.
+ *
+ * More than one thread can wait on a compilation. When the compilation
+ * completes, all threads will be released.
+ *
+ * See {@link ANeuralNetworksCompilation} for information on multithreaded
+ * usage.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if the compilation completed normally.
+ */
+inline int ANeuralNetworksCompilation_finish(
+    ANeuralNetworksCompilation* compilation) {
+  LOAD_FUNCTION(ANeuralNetworksCompilation_finish);
+  EXECUTE_FUNCTION_RETURN(compilation);
+}
+/**
+ * Create a {@link ANeuralNetworksExecution} to apply the given compilation.
+ * This only creates the object. Computation is only performed once
+ * {@link ANeuralNetworksExecution_startCompute} is invoked.
+ *
+ * <p>The provided compilation must outlive the execution.</p>
+ *
+ * See {@link ANeuralNetworksExecution} for information on multithreaded usage.
+ *
+ * @param compilation The {@link ANeuralNetworksCompilation} to be evaluated.
+ * @param execution The newly created object or NULL if unsuccessful.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_BAD_DATA
+ *         if the compilation is invalid.
+ */
+inline int ANeuralNetworksExecution_create(
+    ANeuralNetworksCompilation* compilation,
+    ANeuralNetworksExecution** execution) {
+  LOAD_FUNCTION(ANeuralNetworksExecution_create);
+  EXECUTE_FUNCTION_RETURN(compilation, execution);
+}
+
+/**
+ * Destroy an execution.
+ *
+ * <p>If called on an execution for which
+ * {@link ANeuralNetworksExecution_startCompute} has been called, the
+ * function will return immediately but will mark the execution to be deleted
+ * once the computation completes.   The {link ANeuralNetworksExecution_wait}
+ * will return ANEURALNETWORKS_ERROR_DELETED.
+ *
+ * See {@link ANeuralNetworksExecution} for information on multithreaded usage.
+ *
+ * @param execution The execution to be destroyed. Passing NULL is acceptable
+ * and results in no operation.
+ */
+inline void ANeuralNetworksExecution_free(ANeuralNetworksExecution* execution) {
+  LOAD_FUNCTION(ANeuralNetworksExecution_free);
+  EXECUTE_FUNCTION(execution);
+}
+
+/**
+ * Associate a user buffer with an input of the model of the
+ * {@link ANeuralNetworksExecution}.
+ *
+ * <p>The provided buffer must outlive the execution.</p>
+ *
+ * See {@link ANeuralNetworksExecution} for information on multithreaded usage.
+ *
+ * @param execution The execution to be modified.
+ * @param index The index of the input argument we are setting. It is
+ *              an index into the lists passed to
+ *              {@link ANeuralNetworksModel_identifyInputsAndOutputs}. It is not
+ *              the index associated with {@link
+ * ANeuralNetworksModel_addOperand}.
+ * @param type The type of the operand. This should be used to specify the
+ *             dimensions that were set to 0 when the operand was added to the
+ *             model. All other properties of the type must be the same as
+ *             specified in the model. If the type is the same as specified
+ *             when the model was built, NULL can be passed.
+ * @param buffer The buffer containing the data.
+ * @param length The length in bytes of the buffer.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_BAD_DATA if
+ * the name is not recognized or the buffer is too small for the input.
+ */
+inline int ANeuralNetworksExecution_setInput(
+    ANeuralNetworksExecution* execution, int32_t index,
+    const ANeuralNetworksOperandType* type, const void* buffer, size_t length) {
+  LOAD_FUNCTION(ANeuralNetworksExecution_setInput);
+  EXECUTE_FUNCTION_RETURN(execution, index, type, buffer, length);
+}
+
+/**
+ * Associate part of a memory object with an input of the model of the
+ * {@link ANeuralNetworksExecution}.
+ *
+ * <p>The provided memory must outlive the execution.</p>
+ *
+ * See {@link ANeuralNetworksExecution} for information on multithreaded usage.
+ *
+ * @param execution The execution to be modified.
+ * @param index The index of the input argument we are setting. It is
+ *              an index into the lists passed to
+ *              {@link ANeuralNetworksModel_identifyInputsAndOutputs}. It is not
+ *              the index associated with {@link
+ * ANeuralNetworksModel_addOperand}.
+ * @param type The type of the operand. This can be used to specify the
+ *             dimensions that were set to 0 when the operand was added to the
+ *             model. All other values must be the same as specified in the
+ *             model. If the type is the same as specified when the model
+ *             was built, NULL can be passed.
+ * @param memory The memory containing the data.
+ * @param offset This specifies the location of the data within the memory.
+ *               The offset is in bytes from the start of memory.
+ * @param length The size in bytes of the data value.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_BAD_DATA if
+ * the name is not recognized or the buffer is too small for the input.
+ */
+inline int ANeuralNetworksExecution_setInputFromMemory(
+    ANeuralNetworksExecution* execution, int32_t index,
+    const ANeuralNetworksOperandType* type, const ANeuralNetworksMemory* memory,
+    size_t offset, size_t length) {
+  LOAD_FUNCTION(ANeuralNetworksExecution_setInputFromMemory);
+  EXECUTE_FUNCTION_RETURN(execution, index, type, memory, offset, length);
+}
+
+/**
+ * Associate a user buffer with an output of the model of the
+ * {@link ANeuralNetworksExecution}.
+ *
+ * <p>The provided buffer must outlive the execution.</p>
+ *
+ * See {@link ANeuralNetworksExecution} for information on multithreaded usage.
+ *
+ * @param execution The execution to be modified.
+ * @param index The index of the output argument we are setting. It is
+ *              an index into the lists passed to
+ *              {@link ANeuralNetworksModel_identifyInputsAndOutputs}. It is not
+ *              the index associated with {@link
+ * ANeuralNetworksModel_addOperand}.
+ * @param type The type of the operand. This can be used to specify the
+ *             dimensions that were set to 0 when the operand was added to the
+ *             model. All other values must be the same as specified in the
+ *             model. If the type is the same as specified when the model
+ *             was built, NULL can be passed.
+ * @param buffer The buffer where the data is to be written.
+ * @param length The length in bytes of the buffer.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_BAD_DATA if
+ * the name is not recognized or the buffer is too small for the output.
+ */
+inline int ANeuralNetworksExecution_setOutput(
+    ANeuralNetworksExecution* execution, int32_t index,
+    const ANeuralNetworksOperandType* type, void* buffer, size_t length) {
+  LOAD_FUNCTION(ANeuralNetworksExecution_setOutput);
+  EXECUTE_FUNCTION_RETURN(execution, index, type, buffer, length);
+}
+
+/**
+ * Associate part of a memory object with an output of the model of the
+ * {@link ANeuralNetworksExecution}.
+ *
+ * <p>The provided memory must outlive the execution.</p>
+ *
+ * See {@link ANeuralNetworksExecution} for information on multithreaded usage.
+ *
+ * @param execution The execution to be modified.
+ * @param index The index of the output argument we are setting. It is
+ *              an index into the lists passed to
+ *              {@link ANeuralNetworksModel_identifyInputsAndOutputs}. It is not
+ *              the index associated with {@link
+ * ANeuralNetworksModel_addOperand}.
+ * @param type The type of the operand. This can be used to specify the
+ *             dimensions that were set to 0 when the operand was added to the
+ *             model. All other values must be the same as specified in the
+ *             model. If the type is the same as specified when the model
+ *             was built, NULL can be passed.
+ * @param memory The memory where the data is to be stored.
+ * @param offset This specifies the location of the data within the memory.
+ *               The offset is in bytes from the start of memory.
+ * @param length The length in bytes of the data value.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_BAD_DATA if
+ * the name is not recognized or the buffer is too small for the output.
+ */
+inline int ANeuralNetworksExecution_setOutputFromMemory(
+    ANeuralNetworksExecution* execution, int32_t index,
+    const ANeuralNetworksOperandType* type, const ANeuralNetworksMemory* memory,
+    size_t offset, size_t length) {
+  LOAD_FUNCTION(ANeuralNetworksExecution_setOutputFromMemory);
+  EXECUTE_FUNCTION_RETURN(execution, index, type, memory, offset, length);
+}
+
+/**
+ * Schedule evaluation of the execution.
+ *
+ * <p>Schedules evaluation of the execution. Once the model has been
+ * applied and the outputs are ready to be consumed, the execution will be
+ * signaled. Use {@link ANeuralNetworksExecution_wait} to wait for that signal.
+ * </p>
+ *
+ * Multiple executions can be scheduled and evaluated concurrently, and
+ * compilations can be performed concurrently with executions. The runtime makes
+ * no guarantee on the ordering of the completion of compilations and
+ * executions. If it's important to the application, the application should
+ * enforce the ordering by using {@link ANeuralNetworksCompilation_wait} and
+ * {@link ANeuralNetworksExecution_wait}.
+ *
+ * ANeuralNetworksExecution_wait must be called to recuperate the resources used
+ * by the execution.
+ *
+ * See {@link ANeuralNetworksExecution} for information on multithreaded usage.
+ *
+ * @param execution The execution to be scheduled and executed.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+inline int ANeuralNetworksExecution_startCompute(
+    ANeuralNetworksExecution* execution, ANeuralNetworksEvent** event) {
+  LOAD_FUNCTION(ANeuralNetworksExecution_startCompute);
+  EXECUTE_FUNCTION_RETURN(execution, event);
+}
+
+/**
+ * Waits until the execution completes.
+ *
+ * More than one thread can wait on an event. When the execution completes,
+ * all threads will be released.
+ *
+ * See {@link ANeuralNetworksExecution} for information on multithreaded usage.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if the execution completed normally.
+ */
+inline int ANeuralNetworksEvent_wait(ANeuralNetworksEvent* event) {
+  LOAD_FUNCTION(ANeuralNetworksEvent_wait);
+  EXECUTE_FUNCTION_RETURN(event);
+}
+
+/**
+ * Destroys the event.
+ *
+ * See {@link ANeuralNetworksExecution} for information on multithreaded usage.
+ */
+inline void ANeuralNetworksEvent_free(ANeuralNetworksEvent* event) {
+  LOAD_FUNCTION(ANeuralNetworksEvent_free);
+  EXECUTE_FUNCTION(event);
+}
+
+#endif  // __NEURAL_NETWORKS_SHIM__
diff --git a/runtime/libs/nnapi/v1.2/CMakeLists.txt b/runtime/libs/nnapi/v1.2/CMakeLists.txt
new file mode 100644
index 000000000..21ec3015f
--- /dev/null
+++ b/runtime/libs/nnapi/v1.2/CMakeLists.txt
@@ -0,0 +1,4 @@
+add_library(nnfw_lib_nnapi_1_2 INTERFACE)
+
+target_include_directories(nnfw_lib_nnapi_1_2 INTERFACE ${CMAKE_CURRENT_SOURCE_DIR}/include)
+target_link_libraries(nnfw_lib_nnapi_1_2 INTERFACE nnfw-nnapi-header)
diff --git a/runtime/libs/nnapi/v1.2/include/NeuralNetworksExShim.h b/runtime/libs/nnapi/v1.2/include/NeuralNetworksExShim.h
new file mode 100644
index 000000000..855613241
--- /dev/null
+++ b/runtime/libs/nnapi/v1.2/include/NeuralNetworksExShim.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ * Copyright 2017 The TensorFlow Authors. All Rights Reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     NeuralNetworksExShim.h
+ * @brief    This file contains an actual implementation of
+ *           ANeuralNetworksModel_addOperationEx function
+ */
+
+#ifndef __NEURAL_NETWORKS_EX_SHIM_H__
+#define __NEURAL_NETWORKS_EX_SHIM_H__
+
+#include "NeuralNetworks.h"
+#include "NeuralNetworksEx.h"
+#include "NeuralNetworksLoadHelpers.h"
+
+typedef int (*ANeuralNetworksModel_addOperationEx_fn)(ANeuralNetworksModel *model,
+                                                      ANeuralNetworksOperationTypeEx type,
+                                                      uint32_t inputCount, const uint32_t *inputs,
+                                                      uint32_t outputCount,
+                                                      const uint32_t *outputs);
+
+/**
+ * @brief Add an extended operation to a model.
+ *
+ * @param[in] model The model to be modified.
+ * @param[in] type The type of extended operation.
+ * @param[in] inputCount The number of entries in the inputs array.
+ * @param[in] inputs An array of indexes identifying each operand.
+ * @param[in] outputCount The number of entries in the outputs array.
+ * @param[in] outputs An array of indexes identifying each operand.
+ *
+ * @note The operands specified by inputs and outputs must have been
+ *       previously added by calls to {@link ANeuralNetworksModel_addOperand}.\n
+ *       Attempting to modify a model once {@link ANeuralNetworksModel_finish}
+ *       has been called will return an error.\n
+ *       See {@link ANeuralNetworksModel} for information on multithreaded usage.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+
+inline int ANeuralNetworksModel_addOperationEx(ANeuralNetworksModel *model,
+                                               ANeuralNetworksOperationTypeEx type,
+                                               uint32_t inputCount, const uint32_t *inputs,
+                                               uint32_t outputCount, const uint32_t *outputs)
+{
+  LOAD_FUNCTION(ANeuralNetworksModel_addOperationEx);
+  EXECUTE_FUNCTION_RETURN(model, type, inputCount, inputs, outputCount, outputs);
+}
+
+#endif // __NEURAL_NETWORKS_EX_SHIM_H__
diff --git a/runtime/libs/nnapi/v1.2/include/NeuralNetworksLoadHelpers.h b/runtime/libs/nnapi/v1.2/include/NeuralNetworksLoadHelpers.h
new file mode 100644
index 000000000..1c482b54c
--- /dev/null
+++ b/runtime/libs/nnapi/v1.2/include/NeuralNetworksLoadHelpers.h
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ * Copyright 2017 The TensorFlow Authors. All Rights Reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+// NOTE To minimize diff with upstream tensorflow, disable clang-format
+// clang-format off
+
+// NOTE This header is derived from part of the following file (in TensorFlow v1.12)
+//       'externals/tensorflow/tensorflow/contrib/lite/nnapi/NeuralNetworksShim.h'
+
+/**
+ * @file NeuralNetworksLoadHelpers.h
+ * @brief This file contains functions to load NN API runtime library
+ */
+
+#ifndef __NEURAL_NETWORKS_LOAD_HELPER_H__
+#define __NEURAL_NETWORKS_LOAD_HELPER_H__
+
+#include <dlfcn.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+/**
+ * @brief Print log data
+ * @param[in] format    Format string of @c printf
+ * @param[in] args      Argument after format string. (Same with @c printf)
+ */
+#define NNAPI_LOG(format, ...) printf(format "\n", __VA_ARGS__);
+
+/**
+ * @brief Create a function pointer named @c fn after loading NN API library
+ * @param[in] name    Name of a function
+ */
+#define LOAD_FUNCTION(name) \
+  static name##_fn fn = reinterpret_cast<name##_fn>(nnfw::loadFunction(#name));
+
+/**
+ * @brief Run @c fn function. @c fn is created by @ref LOAD_FUNCTION
+ * @param[in] args    List of arguments for the function @c fn
+ */
+#define EXECUTE_FUNCTION(...) \
+  if (fn != nullptr) {        \
+    fn(__VA_ARGS__);          \
+  }
+
+/**
+ * @brief Run @c fn function. @c fn is created by @ref LOAD_FUNCTION
+ * @param[in] args    List of arguments for the function @c fn
+ * @return            the return value of @c fn
+ */
+#define EXECUTE_FUNCTION_RETURN(...) return fn != nullptr ? fn(__VA_ARGS__) : 0;
+
+namespace nnfw
+{
+
+/**
+ * @brief Load NN API library
+ * @param[in] name path of NN API library
+ * @return a symbol table handle of NN API library
+ */
+inline void* loadLibrary(const char* name) {
+  // TODO: change RTLD_LOCAL? Assumes there can be multiple instances of nn
+  // api RT
+  void* handle = nullptr;
+#if 1 //#ifdef __ANDROID__
+  handle = dlopen(name, RTLD_LAZY | RTLD_LOCAL);
+  if (handle == nullptr) {
+    NNAPI_LOG("nnapi error: unable to open library %s", name);
+  }
+#endif
+  return handle;
+}
+
+/**
+ * @brief Load libneuralnetworks.so and return handle of library
+ * @return a symbol table handle of NN API library
+ */
+inline void* getLibraryHandle() {
+  static void* handle = loadLibrary("libneuralnetworks.so");
+  return handle;
+}
+
+/**
+ * @brief Return function ptr in libneuralnetworks.so
+ * @param[in] name    Name of function
+ * @return function pointer
+ */
+inline void* loadFunction(const char* name) {
+  void* fn = nullptr;
+  if (getLibraryHandle() != nullptr) {
+    fn = dlsym(getLibraryHandle(), name);
+  }
+  if (fn == nullptr) {
+    NNAPI_LOG("nnapi error: unable to open function %s", name);
+    abort();
+  }
+  else {
+#ifdef _GNU_SOURCE
+    Dl_info info;
+    if (dladdr(fn, &info))
+    {
+      NNAPI_LOG("nnapi function '%s' is loaded from '%s' ", name, info.dli_fname);
+    }
+    else
+    {
+      NNAPI_LOG("nnapi function '%s' is failed to load", name);
+    }
+#endif // _GNU_SOURCE
+  }
+  return fn;
+}
+
+/**
+ * @brief Check if libneuralnetworks.so can be loaded
+ * @return @c true if loading is successful, otherwise @c false.
+ */
+inline bool NNAPIExists() {
+  static bool nnapi_is_available = getLibraryHandle();
+  return nnapi_is_available;
+}
+
+} // namespace nnfw
+
+#endif // __NEURAL_NETWORKS_LOAD_HELPER_H__
diff --git a/runtime/libs/nnapi/v1.2/include/NeuralNetworksShim.h b/runtime/libs/nnapi/v1.2/include/NeuralNetworksShim.h
new file mode 100644
index 000000000..80082383f
--- /dev/null
+++ b/runtime/libs/nnapi/v1.2/include/NeuralNetworksShim.h
@@ -0,0 +1,1136 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ * Copyright 2017 The TensorFlow Authors. All Rights Reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+// NOTE This header is derived from part of the following file
+// https://github.com/tensorflow/tensorflow/blob/a59ad83d06abd38b5e142c41043db8886a92fca8/tensorflow/lite/nnapi/NeuralNetworksShim.h
+
+#ifndef __NEURAL_NETWORKS_SHIM_H__
+#define __NEURAL_NETWORKS_SHIM_H__
+
+#include "NeuralNetworksTypes.h"
+#include "NeuralNetworksLoadHelpers.h"
+
+// This interface is now deprecated. You should use instead
+// nnapi_implementation.
+
+// TODO(b/123017568): Update all current usages of this file.
+
+// NN api types based on NNAPI header file
+// https://developer.android.com/ndk/reference/group/neural-networks
+
+/**
+ * Creates a shared memory object from a file descriptor.
+ *
+ * The shared memory is backed by a file descriptor via mmap.
+ * See {@link ANeuralNetworksMemory} for a description on how to use
+ * this shared memory.
+ *
+ * @param size The requested size in bytes.
+ *             Must not be larger than the file size.
+ * @param prot The desired memory protection for the mapping.
+ *             It is either PROT_NONE or the bitwise OR of one or
+ *             more of the following flags: PROT_READ, PROT_WRITE.
+ * @param fd The requested file descriptor.
+ *           The file descriptor has to be mmap-able. The file
+ *           descriptor will be duplicated.
+ * @param offset The offset to the beginning of the file of the area to map.
+ *               The offset has to be aligned to a page size.
+ * @param memory The memory object to be created.
+ *               Set to NULL if unsuccessful.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if the request completed normally.
+ */
+inline int ANeuralNetworksMemory_createFromFd(size_t size, int protect, int fd, size_t offset,
+                                              ANeuralNetworksMemory **memory)
+{
+  LOAD_FUNCTION(ANeuralNetworksMemory_createFromFd);
+  EXECUTE_FUNCTION_RETURN(size, protect, fd, offset, memory);
+}
+
+/**
+ * Delete a memory object.
+ *
+ * Destroys the object used by the run time to keep track of the memory.
+ * This will free the underlying actual memory if no other code has open
+ * handles to this memory.
+ *
+ * @param memory The memory object to be freed.
+ */
+inline void ANeuralNetworksMemory_free(ANeuralNetworksMemory *memory)
+{
+  LOAD_FUNCTION(ANeuralNetworksMemory_free);
+  EXECUTE_FUNCTION(memory);
+}
+
+/**
+ * Create an empty {@link ANeuralNetworksModel}.
+ *
+ * <p>This only creates the object. Computation is performed once
+ * {@link ANeuralNetworksExecution_startCompute} is invoked.
+ *
+ * The model should be constructed with calls to
+ * {@link ANeuralNetworksModel_addOperation} and
+ * {@link ANeuralNetworksModel_addOperand}
+ *
+ * <p>{@link ANeuralNetworksModel_finish} should be called once the model
+ * has been fully constructed.</p>
+ *
+ * <p>{@link ANeuralNetworksModel_free} should be called once the model
+ * is no longer needed.</p>
+ *
+ * @param model The {@link ANeuralNetworksModel} to be created.
+ *              Set to NULL if unsuccessful.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+inline int ANeuralNetworksModel_create(ANeuralNetworksModel **model)
+{
+  LOAD_FUNCTION(ANeuralNetworksModel_create);
+  EXECUTE_FUNCTION_RETURN(model);
+}
+
+/**
+ * Destroy a model.
+ *
+ * The model need not have been finished by a call to
+ * {@link ANeuralNetworksModel_finish}.
+ *
+ * See {@link ANeuralNetworksModel} for information on multithreaded usage.
+ *
+ * @param model The model to be destroyed. Passing NULL is acceptable and
+ *              results in no operation.
+ */
+inline void ANeuralNetworksModel_free(ANeuralNetworksModel *model)
+{
+  LOAD_FUNCTION(ANeuralNetworksModel_free);
+  EXECUTE_FUNCTION(model);
+}
+
+/**
+ * Indicate that we have finished modifying a model. Required before
+ * calling {@link ANeuralNetworksCompilation_compile}.
+ *
+ * An application is responsible to make sure that no other thread uses
+ * the model at the same time.
+ *
+ * See {@link ANeuralNetworksModel} for information on multithreaded usage.
+ *
+ * @param model The model to be finished.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+inline int ANeuralNetworksModel_finish(ANeuralNetworksModel *model)
+{
+  LOAD_FUNCTION(ANeuralNetworksModel_finish);
+  EXECUTE_FUNCTION_RETURN(model);
+}
+
+/**
+ * Add an operand to a model.
+ *
+ * The order in which the operands are added is important. The first one added
+ * to a model will have the index value 0, the second 1, etc. These indexes are
+ * used as operand identifiers in {@link ANeuralNetworksModel_addOperation},
+ * {@link ANeuralNetworksExecution_setInput},
+ * {@link ANeuralNetworksExecution_setInputFromMemory},
+ * {@link ANeuralNetworksExecution_setOutput},
+ * {@link ANeuralNetworksExecution_setOutputFromMemory} and
+ * {@link ANeuralNetworksExecution_setOperandValue}.
+ *
+ * To build a model that can accommodate inputs of various sizes, as you may
+ * want to do for a CNN, set the size of the dimensions that will vary at run
+ * time to 0. If you do so, provide the full dimensions when calling
+ * {@link ANeuralNetworksExecution_setInput} or {@link
+ * ANeuralNetworksExecution_setInputFromMemory}.
+ *
+ * Attempting to modify a model once {@link ANeuralNetworksModel_finish} has
+ * been called will return an error.
+ *
+ * See {@link ANeuralNetworksModel} for information on multithreaded usage.
+ *
+ * @param model The model to be modified.
+ * @param type The {@link ANeuralNetworksOperandType} that describes the shape
+ * of the operand.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+inline int ANeuralNetworksModel_addOperand(ANeuralNetworksModel *model,
+                                           const ANeuralNetworksOperandType *type)
+{
+  LOAD_FUNCTION(ANeuralNetworksModel_addOperand);
+  EXECUTE_FUNCTION_RETURN(model, type);
+}
+
+/**
+ * Sets an operand to a constant value.
+ *
+ * For scalar values, the content of buffer is copied into the model.
+ *
+ * For tensor values, a pointer to the buffer is stored within the model.
+ * The application is responsible for not changing the content of this region
+ * until all executions using this model have completed. As the data may
+ * be copied during processing, modifying the data after this call yields
+ * undefined results.
+ *
+ * Attempting to modify a model once {@link ANeuralNetworksModel_finish} has
+ * been called will return an error.
+ *
+ * See {@link ANeuralNetworksModel} for information on multithreaded usage.
+ *
+ * @param model The model to be modified.
+ * @param index The index of the model operand we're setting.
+ * @param buffer A pointer to the data to use.
+ * @param length The size in bytes of the data value.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+inline int ANeuralNetworksModel_setOperandValue(ANeuralNetworksModel *model, int32_t index,
+                                                const void *buffer, size_t length)
+{
+  LOAD_FUNCTION(ANeuralNetworksModel_setOperandValue);
+  EXECUTE_FUNCTION_RETURN(model, index, buffer, length);
+}
+
+/**
+ * Sets an operand's per channel quantization parameters.
+ *
+ * Sets parameters required by a tensor of type
+ * {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL}.
+ * This function must be called for every tensor of type
+ * {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL} before
+ * calling {@link ANeuralNetworksModel_finish}.
+ *
+ * Available since API level 29.
+ *
+ * @param model The model to be modified.
+ * @param index The index of the model operand we're setting.
+ * @param channelQuant The per channel quantization parameters for the operand.
+ *                    No memory in this struct needs to outlive the call to
+ *                    this function.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+inline int ANeuralNetworksModel_setOperandSymmPerChannelQuantParams(
+    ANeuralNetworksModel *model, int32_t index,
+    const ANeuralNetworksSymmPerChannelQuantParams *channelQuant)
+{
+  LOAD_FUNCTION(ANeuralNetworksModel_setOperandSymmPerChannelQuantParams);
+  EXECUTE_FUNCTION_RETURN(model, index, channelQuant);
+}
+
+/**
+ * Sets an operand to a value stored in a memory object.
+ *
+ * The content of the memory is not copied. A reference to that memory is stored
+ * inside the model. The application is responsible for not changing the content
+ * of the memory region until all executions using this model have completed.
+ * As the data may be copied during processing, modifying the data after this
+ * call yields undefined results.
+ *
+ * Attempting to modify a model once {@link ANeuralNetworksModel_finish} has
+ * been called will return an error.
+ *
+ * See {@link ANeuralNetworksModel} for information on multithreaded usage.
+ *
+ * @param model The model to be modified.
+ * @param index The index of the model operand we're setting.
+ * @param buffer A pointer to the data to use.
+ * @param memory The memory containing the data.
+ * @param offset This specifies the location of the data within the memory.
+ *               The offset is in bytes from the start of memory.
+ * @param length The size in bytes of the data value.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+inline int ANeuralNetworksModel_setOperandValueFromMemory(ANeuralNetworksModel *model,
+                                                          int32_t index,
+                                                          const ANeuralNetworksMemory *memory,
+                                                          size_t offset, size_t length)
+{
+  LOAD_FUNCTION(ANeuralNetworksModel_setOperandValueFromMemory);
+  EXECUTE_FUNCTION_RETURN(model, index, memory, offset, length);
+}
+
+/**
+ * Add an operation to a model.
+ *
+ * @param model The model to be modified.
+ * @param type The type of the operation.
+ * @param inputCount The number of entries in the inputs array.
+ * @param inputs An array of indexes identifying each operand.
+ * @param outputCount The number of entries in the outputs array.
+ * @param outputs An array of indexes identifying each operand.
+ *
+ * The operands specified by inputs and outputs must have been
+ * previously added by calls to {@link ANeuralNetworksModel_addOperand}.
+ *
+ * Attempting to modify a model once {@link ANeuralNetworksModel_finish} has
+ * been called will return an error.
+ *
+ * See {@link ANeuralNetworksModel} for information on multithreaded usage.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+inline int ANeuralNetworksModel_addOperation(ANeuralNetworksModel *model,
+                                             ANeuralNetworksOperationType type, uint32_t inputCount,
+                                             const uint32_t *inputs, uint32_t outputCount,
+                                             const uint32_t *outputs)
+{
+  LOAD_FUNCTION(ANeuralNetworksModel_addOperation);
+  EXECUTE_FUNCTION_RETURN(model, type, inputCount, inputs, outputCount, outputs);
+}
+
+/**
+ * Specifies which operands will be the model's inputs and outputs.
+ *
+ * An operand cannot be used for both input and output. Doing so will
+ * return an error.
+ *
+ * @param model The model to be modified.
+ * @param inputCount The number of entries in the inputs array.
+ * @param inputs An array of indexes identifying the input operands.
+ * @param outputCount The number of entries in the outputs array.
+ * @param outputs An array of indexes identifying the output operands.
+ *
+ * The operands specified by inputs and outputs must have been
+ * previously added by calls to {@link ANeuralNetworksModel_addOperand}.
+ *
+ * Attempting to modify a model once {@link ANeuralNetworksModel_finish} has
+ * been called will return an error.
+ *
+ * See {@link ANeuralNetworksModel} for information on multithreaded usage.
+ *
+ */
+inline int ANeuralNetworksModel_identifyInputsAndOutputs(ANeuralNetworksModel *model,
+                                                         uint32_t inputCount,
+                                                         const uint32_t *inputs,
+                                                         uint32_t outputCount,
+                                                         const uint32_t *outputs)
+{
+  LOAD_FUNCTION(ANeuralNetworksModel_identifyInputsAndOutputs);
+  EXECUTE_FUNCTION_RETURN(model, inputCount, inputs, outputCount, outputs);
+}
+
+/**
+ * Specifies whether {@link ANEURALNETWORKS_TENSOR_FLOAT32} is allowed to be
+ * calculated with range and/or precision as low as that of the IEEE 754 16-bit
+ * floating-point format. By default, {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+ * must be calculated using at least the range and precision of the IEEE 754
+ * 32-bit floating-point format.
+ *
+ * @param model The model to be modified.
+ * @param allow 'true' indicates {@link ANEURALNETWORKS_TENSOR_FLOAT32} may be
+ *              calculated with range and/or precision as low as that of the
+ *              IEEE 754 16-bit floating point format. 'false' indicates
+ *              {@link ANEURALNETWORKS_TENSOR_FLOAT32} must be calculated using
+ *              at least the range and precision of the IEEE 754 32-bit floating
+ *              point format.
+ *
+ * Attempting to modify a model once {@link ANeuralNetworksModel_finish} has
+ * been called will return an error.
+ *
+ * Available since API level 28.
+ *
+ * See {@link ANeuralNetworksModel} for information on multithreaded usage.
+ */
+inline int ANeuralNetworksModel_relaxComputationFloat32toFloat16(ANeuralNetworksModel *model,
+                                                                 bool allow)
+{
+  LOAD_FUNCTION(ANeuralNetworksModel_relaxComputationFloat32toFloat16);
+  EXECUTE_FUNCTION_RETURN(model, allow);
+}
+
+/**
+ * Create a {@link ANeuralNetworksCompilation} to compile the given model.
+ * This only creates the object. Compilation is only performed once
+ * {@link ANeuralNetworksCompilation_start} is invoked.
+ *
+ * <p>The provided model must outlive the compilation.</p>
+ *
+ * The model must already have been finished by a call to
+ * {@link ANeuralNetworksModel_finish}.
+ *
+ * See {@link ANeuralNetworksCompilation} for information on multithreaded
+ * usage.
+ *
+ * @param model The {@link ANeuralNetworksModel} to be compiled.
+ * @param compilation The newly created object or NULL if unsuccessful.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_BAD_DATA
+ *         if the model is invalid.
+ */
+inline int ANeuralNetworksCompilation_create(ANeuralNetworksModel *model,
+                                             ANeuralNetworksCompilation **compilation)
+{
+  LOAD_FUNCTION(ANeuralNetworksCompilation_create);
+  EXECUTE_FUNCTION_RETURN(model, compilation);
+}
+
+/**
+ * Destroy a compilation.
+ *
+ * <p>If called on a compilation for which
+ * {@link ANeuralNetworksCompilation_start} has been called, the
+ * function will return immediately but will mark the compilation to be deleted
+ * once the compilation completes. The {@link ANeuralNetworksCompilation_wait}
+ * will return ERROR_DELETED.
+ *
+ * See {@link ANeuralNetworksCompilation} for information on multithreaded
+ * usage.
+ *
+ * @param compilation The compilation to be destroyed. Passing NULL is
+ * acceptable and results in no operation.
+ */
+inline void ANeuralNetworksCompilation_free(ANeuralNetworksCompilation *compilation)
+{
+  LOAD_FUNCTION(ANeuralNetworksCompilation_free);
+  EXECUTE_FUNCTION(compilation);
+}
+
+/**
+ * Sets the execution preference.
+ *
+ * <p>Provides guidance to the runtime when trade-offs are possible.</p>
+ *
+ * See {@link ANeuralNetworksCompilation} for information on multithreaded
+ * usage.
+ *
+ * @param compilation The compilation to be modified.
+ * @param preference Either {@link PREFER_LOW_POWER},
+ *                  {@link PREFER_SINGLE_FAST_ANSWER}, or
+ *                  {@link PREFER_SUSTAINED_SPEED}.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+inline int ANeuralNetworksCompilation_setPreference(ANeuralNetworksCompilation *compilation,
+                                                    int32_t preference)
+{
+  LOAD_FUNCTION(ANeuralNetworksCompilation_setPreference);
+  EXECUTE_FUNCTION_RETURN(compilation, preference);
+}
+
+/**
+ * Waits until the compilation completes.
+ *
+ * More than one thread can wait on a compilation. When the compilation
+ * completes, all threads will be released.
+ *
+ * See {@link ANeuralNetworksCompilation} for information on multithreaded
+ * usage.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if the compilation completed normally.
+ */
+inline int ANeuralNetworksCompilation_finish(ANeuralNetworksCompilation *compilation)
+{
+  LOAD_FUNCTION(ANeuralNetworksCompilation_finish);
+  EXECUTE_FUNCTION_RETURN(compilation);
+}
+/**
+ * Create a {@link ANeuralNetworksExecution} to apply the given compilation.
+ * This only creates the object. Computation is only performed once
+ * {@link ANeuralNetworksExecution_startCompute} is invoked.
+ *
+ * <p>The provided compilation must outlive the execution.</p>
+ *
+ * See {@link ANeuralNetworksExecution} for information on multithreaded usage.
+ *
+ * @param compilation The {@link ANeuralNetworksCompilation} to be evaluated.
+ * @param execution The newly created object or NULL if unsuccessful.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_BAD_DATA
+ *         if the compilation is invalid.
+ */
+inline int ANeuralNetworksExecution_create(ANeuralNetworksCompilation *compilation,
+                                           ANeuralNetworksExecution **execution)
+{
+  LOAD_FUNCTION(ANeuralNetworksExecution_create);
+  EXECUTE_FUNCTION_RETURN(compilation, execution);
+}
+
+/**
+ * Destroy an execution.
+ *
+ * <p>If called on an execution for which
+ * {@link ANeuralNetworksExecution_startCompute} has been called, the
+ * function will return immediately but will mark the execution to be deleted
+ * once the computation completes.   The {link ANeuralNetworksExecution_wait}
+ * will return ANEURALNETWORKS_ERROR_DELETED.
+ *
+ * See {@link ANeuralNetworksExecution} for information on multithreaded usage.
+ *
+ * @param execution The execution to be destroyed. Passing NULL is acceptable
+ * and results in no operation.
+ */
+inline void ANeuralNetworksExecution_free(ANeuralNetworksExecution *execution)
+{
+  LOAD_FUNCTION(ANeuralNetworksExecution_free);
+  EXECUTE_FUNCTION(execution);
+}
+
+/**
+ * Associate a user buffer with an input of the model of the
+ * {@link ANeuralNetworksExecution}.
+ *
+ * <p>The provided buffer must outlive the execution.</p>
+ *
+ * See {@link ANeuralNetworksExecution} for information on multithreaded usage.
+ *
+ * @param execution The execution to be modified.
+ * @param index The index of the input argument we are setting. It is
+ *              an index into the lists passed to
+ *              {@link ANeuralNetworksModel_identifyInputsAndOutputs}. It is not
+ *              the index associated with {@link
+ * ANeuralNetworksModel_addOperand}.
+ * @param type The type of the operand. This should be used to specify the
+ *             dimensions that were set to 0 when the operand was added to the
+ *             model. All other properties of the type must be the same as
+ *             specified in the model. If the type is the same as specified
+ *             when the model was built, NULL can be passed.
+ * @param buffer The buffer containing the data.
+ * @param length The length in bytes of the buffer.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_BAD_DATA if
+ * the name is not recognized or the buffer is too small for the input.
+ */
+inline int ANeuralNetworksExecution_setInput(ANeuralNetworksExecution *execution, int32_t index,
+                                             const ANeuralNetworksOperandType *type,
+                                             const void *buffer, size_t length)
+{
+  LOAD_FUNCTION(ANeuralNetworksExecution_setInput);
+  EXECUTE_FUNCTION_RETURN(execution, index, type, buffer, length);
+}
+
+/**
+ * Associate part of a memory object with an input of the model of the
+ * {@link ANeuralNetworksExecution}.
+ *
+ * <p>The provided memory must outlive the execution.</p>
+ *
+ * See {@link ANeuralNetworksExecution} for information on multithreaded usage.
+ *
+ * @param execution The execution to be modified.
+ * @param index The index of the input argument we are setting. It is
+ *              an index into the lists passed to
+ *              {@link ANeuralNetworksModel_identifyInputsAndOutputs}. It is not
+ *              the index associated with {@link
+ * ANeuralNetworksModel_addOperand}.
+ * @param type The type of the operand. This can be used to specify the
+ *             dimensions that were set to 0 when the operand was added to the
+ *             model. All other values must be the same as specified in the
+ *             model. If the type is the same as specified when the model
+ *             was built, NULL can be passed.
+ * @param memory The memory containing the data.
+ * @param offset This specifies the location of the data within the memory.
+ *               The offset is in bytes from the start of memory.
+ * @param length The size in bytes of the data value.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_BAD_DATA if
+ * the name is not recognized or the buffer is too small for the input.
+ */
+inline int ANeuralNetworksExecution_setInputFromMemory(ANeuralNetworksExecution *execution,
+                                                       int32_t index,
+                                                       const ANeuralNetworksOperandType *type,
+                                                       const ANeuralNetworksMemory *memory,
+                                                       size_t offset, size_t length)
+{
+  LOAD_FUNCTION(ANeuralNetworksExecution_setInputFromMemory);
+  EXECUTE_FUNCTION_RETURN(execution, index, type, memory, offset, length);
+}
+
+/**
+ * Associate a user buffer with an output of the model of the
+ * {@link ANeuralNetworksExecution}.
+ *
+ * <p>The provided buffer must outlive the execution.</p>
+ *
+ * See {@link ANeuralNetworksExecution} for information on multithreaded usage.
+ *
+ * @param execution The execution to be modified.
+ * @param index The index of the output argument we are setting. It is
+ *              an index into the lists passed to
+ *              {@link ANeuralNetworksModel_identifyInputsAndOutputs}. It is not
+ *              the index associated with {@link
+ * ANeuralNetworksModel_addOperand}.
+ * @param type The type of the operand. This can be used to specify the
+ *             dimensions that were set to 0 when the operand was added to the
+ *             model. All other values must be the same as specified in the
+ *             model. If the type is the same as specified when the model
+ *             was built, NULL can be passed.
+ * @param buffer The buffer where the data is to be written.
+ * @param length The length in bytes of the buffer.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_BAD_DATA if
+ * the name is not recognized or the buffer is too small for the output.
+ */
+inline int ANeuralNetworksExecution_setOutput(ANeuralNetworksExecution *execution, int32_t index,
+                                              const ANeuralNetworksOperandType *type, void *buffer,
+                                              size_t length)
+{
+  LOAD_FUNCTION(ANeuralNetworksExecution_setOutput);
+  EXECUTE_FUNCTION_RETURN(execution, index, type, buffer, length);
+}
+
+/**
+ * Associate part of a memory object with an output of the model of the
+ * {@link ANeuralNetworksExecution}.
+ *
+ * <p>The provided memory must outlive the execution.</p>
+ *
+ * See {@link ANeuralNetworksExecution} for information on multithreaded usage.
+ *
+ * @param execution The execution to be modified.
+ * @param index The index of the output argument we are setting. It is
+ *              an index into the lists passed to
+ *              {@link ANeuralNetworksModel_identifyInputsAndOutputs}. It is not
+ *              the index associated with {@link
+ * ANeuralNetworksModel_addOperand}.
+ * @param type The type of the operand. This can be used to specify the
+ *             dimensions that were set to 0 when the operand was added to the
+ *             model. All other values must be the same as specified in the
+ *             model. If the type is the same as specified when the model
+ *             was built, NULL can be passed.
+ * @param memory The memory where the data is to be stored.
+ * @param offset This specifies the location of the data within the memory.
+ *               The offset is in bytes from the start of memory.
+ * @param length The length in bytes of the data value.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_BAD_DATA if
+ * the name is not recognized or the buffer is too small for the output.
+ */
+inline int ANeuralNetworksExecution_setOutputFromMemory(ANeuralNetworksExecution *execution,
+                                                        int32_t index,
+                                                        const ANeuralNetworksOperandType *type,
+                                                        const ANeuralNetworksMemory *memory,
+                                                        size_t offset, size_t length)
+{
+  LOAD_FUNCTION(ANeuralNetworksExecution_setOutputFromMemory);
+  EXECUTE_FUNCTION_RETURN(execution, index, type, memory, offset, length);
+}
+
+/**
+ * Schedule evaluation of the execution.
+ *
+ * <p>Schedules evaluation of the execution. Once the model has been
+ * applied and the outputs are ready to be consumed, the execution will be
+ * signaled. Use {@link ANeuralNetworksExecution_wait} to wait for that signal.
+ * </p>
+ *
+ * Multiple executions can be scheduled and evaluated concurrently, and
+ * compilations can be performed concurrently with executions. The runtime makes
+ * no guarantee on the ordering of the completion of compilations and
+ * executions. If it's important to the application, the application should
+ * enforce the ordering by using {@link ANeuralNetworksCompilation_wait} and
+ * {@link ANeuralNetworksExecution_wait}.
+ *
+ * ANeuralNetworksExecution_wait must be called to recuperate the resources used
+ * by the execution.
+ *
+ * See {@link ANeuralNetworksExecution} for information on multithreaded usage.
+ *
+ * @param execution The execution to be scheduled and executed.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+inline int ANeuralNetworksExecution_startCompute(ANeuralNetworksExecution *execution,
+                                                 ANeuralNetworksEvent **event)
+{
+  LOAD_FUNCTION(ANeuralNetworksExecution_startCompute);
+  EXECUTE_FUNCTION_RETURN(execution, event);
+}
+
+/**
+ * Waits until the execution completes.
+ *
+ * More than one thread can wait on an event. When the execution completes,
+ * all threads will be released.
+ *
+ * See {@link ANeuralNetworksExecution} for information on multithreaded usage.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if the execution completed normally.
+ */
+inline int ANeuralNetworksEvent_wait(ANeuralNetworksEvent *event)
+{
+  LOAD_FUNCTION(ANeuralNetworksEvent_wait);
+  EXECUTE_FUNCTION_RETURN(event);
+}
+
+/**
+ * Destroys the event.
+ *
+ * See {@link ANeuralNetworksExecution} for information on multithreaded usage.
+ */
+inline void ANeuralNetworksEvent_free(ANeuralNetworksEvent *event)
+{
+  LOAD_FUNCTION(ANeuralNetworksEvent_free);
+  EXECUTE_FUNCTION(event);
+}
+
+/**
+ * Get the number of available devices.
+ *
+ * @param numDevices Used to return the number of devices.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ *
+ * Available since API level 29.
+ */
+inline int ANeuralNetworks_getDeviceCount(uint32_t *numDevices)
+{
+  LOAD_FUNCTION(ANeuralNetworks_getDeviceCount);
+  EXECUTE_FUNCTION_RETURN(numDevices);
+}
+
+/**
+ * Get the representation of the specified device.
+ *
+ * @param devIndex The index of the specified device. Must be less than the
+ *                 number of available devices.
+ * @param device The representation of the specified device.
+ *               The same representation will always be returned for the
+ *               specified device.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ *
+ * Available since API level 29.
+ */
+
+inline int ANeuralNetworks_getDevice(uint32_t devIndex, ANeuralNetworksDevice **device)
+{
+  LOAD_FUNCTION(ANeuralNetworks_getDevice);
+  EXECUTE_FUNCTION_RETURN(devIndex, device);
+}
+
+/**
+ * Get the name of the specified device.
+ *
+ * @param device The representation of the specified device.
+ * @param name   The returned name of the specified device. The name will be in
+ *               UTF-8 and will be null-terminated. It will be recognizable as a
+ *               known device name rather than a cryptic string. For devices
+ *               with API level 29 and above, the format of the name is
+ *               {VENDOR}-{DEVICE}, e.g. “google-ipu”. For devices with feature
+ *               level 28 or lower, the name will always be “unknown-device”.
+ *               The name will remain valid for the duration of the application.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ *
+ * Available since API level 29.
+ */
+inline int ANeuralNetworksDevice_getName(const ANeuralNetworksDevice *device, const char **name)
+{
+  LOAD_FUNCTION(ANeuralNetworksDevice_getName);
+  EXECUTE_FUNCTION_RETURN(device, name);
+}
+
+/**
+ * Get the version of the driver implementation of the specified device.
+ *
+ * It’s the responsibility of the driver implementor to insure that this version
+ * string uniquely distinguishes this implementation from all previous
+ * implementations.
+ *
+ * This version string must not be confused with the feature level which is
+ * solely defined by {@link ANeuralNetworksDevice_getFeatureLevel}. There is no
+ * implicit ordering of the versions. For example, it is not possible to filter
+ * all drivers older than a certain version.
+ *
+ * Application developers may use this version string to avoid or prefer
+ * specific driver implementations. For example, an application may want to do
+ * so because:
+ *     - A specific version of the driver does not provide the required
+ * performance, perhaps because of a performance regression.
+ *     - A specific version of the driver has a bug or returns results that
+ * don’t match the minimum precision requirement for the application.
+ *
+ * @param device  The representation of the specified device.
+ * @param version The returned version string of the driver for the specified
+ *                device. The string will be in UTF-8 and will be
+ *                null-terminated. For devices with feature level 28 or lower,
+ *                "UNKNOWN" will be returned. The version string will remain
+ *                valid for the duration of the application.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ *
+ * Available since API level 29.
+ */
+inline int ANeuralNetworksDevice_getVersion(const ANeuralNetworksDevice *device,
+                                            const char **version)
+{
+  LOAD_FUNCTION(ANeuralNetworksDevice_getVersion);
+  EXECUTE_FUNCTION_RETURN(device, version);
+}
+
+/**
+ * Get the supported NNAPI version of the specified device.
+ *
+ * Each device has a supported feature level, which is the most advanced feature
+ * this driver implements. For example, if the driver implements the features
+ * introduced in Android P, but does not implement the features introduced after
+ * Android P, the value would be 28. Developers could decide whether or not the
+ * specified device should be used for a Model that has certain feature
+ * requirements.
+ *
+ * @param device       The representation of the specified device.
+ * @param featureLevel The API level of the most advanced feature this driver
+ *                     implements.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ *
+ * Available since API level 29.
+ */
+inline int ANeuralNetworksDevice_getFeatureLevel(const ANeuralNetworksDevice *device,
+                                                 int64_t *featureLevel)
+{
+  LOAD_FUNCTION(ANeuralNetworksDevice_getFeatureLevel);
+  EXECUTE_FUNCTION_RETURN(device, featureLevel);
+}
+
+/**
+ * Get the supported operations for a specified set of devices. If multiple
+ * devices are selected, the supported operation list is a union of supported
+ * operations of all selected devices.
+ *
+ * @param model        The model to be queried.
+ * @param devices      The set of devices. Must not contain duplicates.
+ * @param numDevices   The number of devices in the set.
+ * @param supportedOps The boolean array to be filled. True means supported. The
+ *                     size of the boolean array must be at least as large as
+ *                     the number of operations in the model. The order of
+ *                     elements in the supportedOps array matches the order in
+ *                     which the corresponding operations were added to the
+ *                     model.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ *
+ * Available since API level 29.
+ */
+inline int
+ANeuralNetworksModel_getSupportedOperationsForDevices(const ANeuralNetworksModel *model,
+                                                      const ANeuralNetworksDevice *const *devices,
+                                                      uint32_t numDevices, bool *supportedOps)
+{
+  LOAD_FUNCTION(ANeuralNetworksModel_getSupportedOperationsForDevices);
+  EXECUTE_FUNCTION_RETURN(model, devices, numDevices, supportedOps);
+}
+
+/**
+ * Create a {@link ANeuralNetworksCompilation} to compile the given model for a
+ * specified set of devices. If more than one device is specified, the
+ * compilation will distribute the workload automatically across the devices.
+ * The model must be fully supported by the specified set of devices. This means
+ * that ANeuralNetworksModel_getSupportedOperationsForDevices() must have
+ * returned true for every operation for that model/devices pair.
+ *
+ * @param model       The {@link ANeuralNetworksModel} to be compiled.
+ * @param devices     The set of devices. Must not contain duplicates.
+ * @param numDevices  The number of devices in the set.
+ * @param compilation The newly created object or NULL if unsuccessful.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_BAD_DATA
+ *         if the model is invalid.
+ *
+ * Available since API level 29.
+ */
+inline int ANeuralNetworksCompilation_createForDevices(ANeuralNetworksModel *model,
+                                                       const ANeuralNetworksDevice *const *devices,
+                                                       uint32_t numDevices,
+                                                       ANeuralNetworksCompilation **compilation)
+{
+  LOAD_FUNCTION(ANeuralNetworksCompilation_createForDevices);
+  EXECUTE_FUNCTION_RETURN(model, devices, numDevices, compilation);
+}
+
+/**
+ * Sets the compilation caching signature and the cache directory.
+ *
+ * Provides optional caching information to the runtime for faster repeated
+ * compilation.
+ *
+ * See {@link ANeuralNetworksCompilation} for information on multithreaded
+ * usage.
+ *
+ * @param compilation The compilation to be modified.
+ * @param cacheDir The cache directory to store and retrieve caching data. It is
+ *                 recommended to use the code_cache provided by the Android
+ *                 runtime. If not using the code_cache, the user should choose
+ *                 a directory local to the application, and is responsible to
+ *                 manage and clean the cache entries.
+ * @param token The token provided by the user to specify a model, must be of
+ *              length ANEURALNETWORKS_BYTE_SIZE_OF_CACHE_TOKEN. The user should
+ *              ensure that the token is unique to a model within the
+ *              application. The NNAPI runtime will not detected token
+ *              collisions. If there is a collision, the compilation outcome may
+ *              be incorrect without notifying with error.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ *
+ * Available since API level 29.
+ */
+inline int ANeuralNetworksCompilation_setCaching(ANeuralNetworksCompilation *compilation,
+                                                 const char *cacheDir, const uint8_t *token)
+{
+  LOAD_FUNCTION(ANeuralNetworksCompilation_setCaching);
+  EXECUTE_FUNCTION_RETURN(compilation, cacheDir, token);
+}
+
+/**
+ * Schedule synchronous evaluation of the execution.
+ *
+ * <p>Schedules synchronous evaluation of the execution. Returns once the
+ * execution has completed and the outputs are ready to be consumed.
+ * </p>
+ *
+ * See {@link ANeuralNetworksExecution} for information on multithreaded usage.
+ *
+ * See {@link ANeuralNetworksExecution_startCompute} for asynchronous execution.
+ * Synchronous execution incurs lower overhead than asynchronous execution.
+ *
+ * Available since API level 29.
+ *
+ * @param execution The execution to be scheduled and executed.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if the execution completed normally.
+ *         ANEURALNETWORKS_UNMAPPABLE if the execution input or output memory
+ *         cannot be properly mapped.
+ */
+inline int ANeuralNetworksExecution_compute(ANeuralNetworksExecution *execution)
+{
+  LOAD_FUNCTION(ANeuralNetworksExecution_compute);
+  EXECUTE_FUNCTION_RETURN(execution);
+}
+
+/**
+ * Get the dimensional information of the specified output operand of the model
+ * of the
+ * {@link ANeuralNetworksExecution}.
+ *
+ * On asynchronous execution initiated by {@link
+ * ANeuralNetworksExecution_startCompute},
+ * {@link ANeuralNetworksEvent_wait} must be called prior to this function to
+ * recuperate the resources used by the execution.
+ *
+ * @param execution The execution to be queried.
+ * @param index The index of the output argument we are querying. It is
+ *              an index into the lists passed to
+ *              {@link ANeuralNetworksModel_identifyInputsAndOutputs}. It is not
+ *              the index associated with {@link
+ * ANeuralNetworksModel_addOperand}.
+ * @param rank The rank of the output operand.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful,
+ * ANEURALNETWORKS_OUTPUT_INSUFFICIENT_SIZE if the target output is provided an
+ * insufficient buffer at execution time, ANEURALNETWORKS_BAD_DATA if the index
+ * is invalid.
+ *
+ * Available since API level 29.
+ */
+inline int ANeuralNetworksExecution_getOutputOperandRank(ANeuralNetworksExecution *execution,
+                                                         int32_t index, uint32_t *rank)
+{
+  LOAD_FUNCTION(ANeuralNetworksExecution_getOutputOperandRank);
+  EXECUTE_FUNCTION_RETURN(execution, index, rank);
+}
+
+/**
+ * Get the dimensional information of the specified output operand of the model
+ * of the
+ * {@link ANeuralNetworksExecution}. The target output operand cannot be a
+ * scalar.
+ *
+ * On asynchronous execution initiated by
+ * {@link ANeuralNetworksExecution_startCompute},
+ * {@link ANeuralNetworksEvent_wait} must be called prior to this function to
+ * recuperate the resources used by the execution.
+ *
+ * @param execution The execution to be queried.
+ * @param index The index of the output argument we are querying. It is an index
+ *              into the lists passed to
+ *              {@link ANeuralNetworksModel_identifyInputsAndOutputs}. It is not
+ *              the index associated with
+ *              {@link ANeuralNetworksModel_addOperand}.
+ * @param dimensions The dimension array to be filled. The size of the array
+ *                   must be exactly as large as the rank of the output operand
+ *                   to be queried in the model.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful,
+ * ANEURALNETWORKS_OUTPUT_INSUFFICIENT_SIZE if the target output is provided an
+ * insufficient buffer at execution time, ANEURALNETWORKS_BAD_DATA if the index
+ * is invalid or if the target is a scalar.
+ *
+ * Available since API level 29.
+ */
+inline int ANeuralNetworksExecution_getOutputOperandDimensions(ANeuralNetworksExecution *execution,
+                                                               int32_t index, uint32_t *dimensions)
+{
+  LOAD_FUNCTION(ANeuralNetworksExecution_getOutputOperandDimensions);
+  EXECUTE_FUNCTION_RETURN(execution, index, dimensions);
+}
+
+/**
+ * Create a {@link ANeuralNetworksBurst} to apply the given compilation.
+ * This only creates the burst object. Computation is only performed once
+ * {@link ANeuralNetworksExecution_burstCompute} is invoked with a valid
+ * {@link ANeuralNetworksExecution} and {@link ANeuralNetworksBurst}.
+ *
+ * <p>The provided compilation must outlive the burst object.</p>
+ *
+ * Available since API level 29.
+ *
+ * @param compilation The {@link ANeuralNetworksCompilation} to be evaluated.
+ * @param burst The newly created object or NULL if unsuccessful.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_BAD_DATA
+ *         if the compilation is invalid.
+ */
+inline int ANeuralNetworksBurst_create(ANeuralNetworksCompilation *compilation,
+                                       ANeuralNetworksBurst **burst)
+{
+  LOAD_FUNCTION(ANeuralNetworksBurst_create);
+  EXECUTE_FUNCTION_RETURN(compilation, burst);
+}
+
+/**
+ * Destroys the burst object.
+ *
+ * Available since API level 29.
+ *
+ * @param burst The burst object to be destroyed. Passing NULL is acceptable and
+ *              results in no operation.
+ */
+inline void ANeuralNetworksBurst_free(ANeuralNetworksBurst *burst)
+{
+  LOAD_FUNCTION(ANeuralNetworksBurst_free);
+  EXECUTE_FUNCTION(burst);
+}
+
+/**
+ * Schedule synchronous evaluation of the execution on a burst object.
+ *
+ * <p>Schedules synchronous evaluation of the execution. Returns once the
+ * execution has completed and the outputs are ready to be consumed.</p>
+ *
+ * <p>There must be at most one {@link ANeuralNetworksExecution} processing at
+ * any given time for any given burst object. Any
+ * {@link ANeuralNetworksExecution} launched before the previous has finished
+ * will result in ANEURALNETWORKS_BAD_STATE.</p>
+ *
+ * Available since API level 29.
+ *
+ * @param burst The burst object to execute on.
+ * @param execution The execution to be scheduled and executed. The execution
+ *                  must be created from the same {@link
+ *                  ANeuralNetworksCompilation} as the burst object.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if the execution completed normally.
+ */
+inline int ANeuralNetworksExecution_burstCompute(ANeuralNetworksExecution *execution,
+                                                 ANeuralNetworksBurst *burst)
+{
+  LOAD_FUNCTION(ANeuralNetworksExecution_burstCompute);
+  EXECUTE_FUNCTION_RETURN(execution, burst);
+}
+
+/**
+ * Creates a shared memory object from an AHardwareBuffer handle.
+ *
+ * If the shared memory is backed by an AHardwareBuffer of
+ * AHARDWAREBUFFER_FORMAT_BLOB format, it can be used the same way as shared
+ * memory created from a file handle. See
+ * {@link ANeuralNetworksMemory} for a description on how to use this shared
+ * memory.
+ *
+ * If the shared memory is backed by an AHardwareBuffer of a format other than
+ * AHARDWAREBUFFER_FORMAT_BLOB, it can only be used for Model inputs and
+ * outputs. When calling {@link ANeuralNetworksExecution_setInputFromMemory} or
+ * {@link ANeuralNetworksExecution_setOutputFromMemory} with the shared memory,
+ * both offset and length must be set to zero and the entire memory region will
+ * be associated with the specified input or output operand. There is no
+ * guarantee that an arbitrary AHardwareBuffer_Format and
+ * AHardwareBuffer_UsageFlags combination can be used by arbitrary devices. The
+ * execution will fail if selected set of devices cannot consume the buffer.
+ *
+ * Calling {@link ANeuralNetworksModel_setOperandValueFromMemory} with shared
+ * memory backed by an AHardwareBuffer of a format other than
+ * AHARDWAREBUFFER_FORMAT_BLOB is disallowed.
+ *
+ * TODO(miaowang): add documentation about intended usage with introspection
+ * API.
+ *
+ * Available since API level 29.
+ *
+ * @param ahwb The AHardwareBuffer handle.
+ * @param memory The memory object to be created.
+ *               Set to NULL if unsuccessful.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if the request completed normally.
+ *
+ * @see AHardwareBuffer
+ */
+inline int ANeuralNetworksMemory_createFromAHardwareBuffer(const AHardwareBuffer *ahwb,
+                                                           ANeuralNetworksMemory **memory)
+{
+  LOAD_FUNCTION(ANeuralNetworksMemory_createFromAHardwareBuffer);
+  EXECUTE_FUNCTION_RETURN(ahwb, memory);
+}
+
+/**
+ * Specifies whether duration of the {@link ANeuralNetworksExecution} is to be
+ * measured. By default, duration is not measured.
+ *
+ * The {@link ANeuralNetworksExecution} must have been created with
+ * {@link ANeuralNetworksCompilation_createForDevices} with numDevices = 1.
+ *
+ * See {@link ANeuralNetworksExecution} for information on multithreaded usage.
+ *
+ * Available since API level 29.
+ *
+ * @param execution The execution to be modified.
+ * @param measure 'true' if duration is to be measured, 'false' if not.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+inline int ANeuralNetworksExecution_setMeasureTiming(ANeuralNetworksExecution *execution,
+                                                     bool measure)
+{
+  LOAD_FUNCTION(ANeuralNetworksExecution_setMeasureTiming);
+  EXECUTE_FUNCTION_RETURN(execution, measure);
+}
+
+/**
+ * Get the time spent in the specified {@link ANeuralNetworksExecution}, in
+ * nanoseconds. The execution must have completed.
+ *
+ * @param execution The execution to be queried.
+ * @param durationCode The measurement to be queried, specified by {@link
+ * DurationCode}.
+ * @param duration The returned duration. If no measurement was requested by
+ *                 {@link ANeuralNetworksExecution_setMeasureTiming}, or for
+ * some other reason the duration is not available, UINT64_MAX will be returned.
+ *                 A particular device need not support any given measurement.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+inline int ANeuralNetworksExecution_getDuration(const ANeuralNetworksExecution *execution,
+                                                int32_t durationCode, uint64_t *duration)
+{
+  LOAD_FUNCTION(ANeuralNetworksExecution_getDuration);
+  EXECUTE_FUNCTION_RETURN(execution, durationCode, duration);
+}
+
+/**/
+
+#endif // __NEURAL_NETWORKS_SHIM_H__
diff --git a/runtime/libs/nnapi/v1.2/include/NeuralNetworksTypes.h b/runtime/libs/nnapi/v1.2/include/NeuralNetworksTypes.h
new file mode 100644
index 000000000..d74402749
--- /dev/null
+++ b/runtime/libs/nnapi/v1.2/include/NeuralNetworksTypes.h
@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ * Copyright 2017 The TensorFlow Authors. All Rights Reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+// NOTE This header is derived from part of the following file
+// https://github.com/tensorflow/tensorflow/blob/a59ad83d06abd38b5e142c41043db8886a92fca8/tensorflow/lite/nnapi/NeuralNetworksTypes.h
+
+#ifndef __NEURAL_NETWORKS_TYPES_H__
+#define __NEURAL_NETWORKS_TYPES_H__
+
+#include "NeuralNetworks.h"
+
+// NN api types based on NNAPI header file
+// https://developer.android.com/ndk/reference/group/neural-networks
+
+// nn api function types
+
+typedef int (*ANeuralNetworksMemory_createFromFd_fn)(size_t size, int protect, int fd,
+                                                     size_t offset, ANeuralNetworksMemory **memory);
+
+typedef void (*ANeuralNetworksMemory_free_fn)(ANeuralNetworksMemory *memory);
+
+typedef int (*ANeuralNetworksModel_create_fn)(ANeuralNetworksModel **model);
+
+typedef int (*ANeuralNetworksModel_finish_fn)(ANeuralNetworksModel *model);
+
+typedef void (*ANeuralNetworksModel_free_fn)(ANeuralNetworksModel *model);
+
+typedef int (*ANeuralNetworksCompilation_create_fn)(ANeuralNetworksModel *model,
+                                                    ANeuralNetworksCompilation **compilation);
+
+typedef void (*ANeuralNetworksCompilation_free_fn)(ANeuralNetworksCompilation *compilation);
+
+typedef int (*ANeuralNetworksCompilation_setPreference_fn)(ANeuralNetworksCompilation *compilation,
+                                                           int32_t preference);
+
+typedef int (*ANeuralNetworksCompilation_finish_fn)(ANeuralNetworksCompilation *compilation);
+
+typedef int (*ANeuralNetworksModel_addOperand_fn)(ANeuralNetworksModel *model,
+                                                  const ANeuralNetworksOperandType *type);
+
+typedef int (*ANeuralNetworksModel_setOperandValue_fn)(ANeuralNetworksModel *model, int32_t index,
+                                                       const void *buffer, size_t length);
+
+typedef int (*ANeuralNetworksModel_setOperandSymmPerChannelQuantParams_fn)(
+    ANeuralNetworksModel *model, int32_t index,
+    const ANeuralNetworksSymmPerChannelQuantParams *channelQuant);
+
+typedef int (*ANeuralNetworksModel_setOperandValueFromMemory_fn)(
+    ANeuralNetworksModel *model, int32_t index, const ANeuralNetworksMemory *memory, size_t offset,
+    size_t length);
+
+typedef int (*ANeuralNetworksModel_addOperation_fn)(ANeuralNetworksModel *model,
+                                                    ANeuralNetworksOperationType type,
+                                                    uint32_t inputCount, const uint32_t *inputs,
+                                                    uint32_t outputCount, const uint32_t *outputs);
+
+typedef int (*ANeuralNetworksModel_identifyInputsAndOutputs_fn)(ANeuralNetworksModel *model,
+                                                                uint32_t inputCount,
+                                                                const uint32_t *inputs,
+                                                                uint32_t outputCount,
+                                                                const uint32_t *outputs);
+
+typedef int (*ANeuralNetworksModel_relaxComputationFloat32toFloat16_fn)(ANeuralNetworksModel *model,
+                                                                        bool allow);
+
+typedef int (*ANeuralNetworksExecution_create_fn)(ANeuralNetworksCompilation *compilation,
+                                                  ANeuralNetworksExecution **execution);
+
+typedef void (*ANeuralNetworksExecution_free_fn)(ANeuralNetworksExecution *execution);
+
+typedef int (*ANeuralNetworksExecution_setInput_fn)(ANeuralNetworksExecution *execution,
+                                                    int32_t index,
+                                                    const ANeuralNetworksOperandType *type,
+                                                    const void *buffer, size_t length);
+
+typedef int (*ANeuralNetworksExecution_setInputFromMemory_fn)(
+    ANeuralNetworksExecution *execution, int32_t index, const ANeuralNetworksOperandType *type,
+    const ANeuralNetworksMemory *memory, size_t offset, size_t length);
+
+typedef int (*ANeuralNetworksExecution_setOutput_fn)(ANeuralNetworksExecution *execution,
+                                                     int32_t index,
+                                                     const ANeuralNetworksOperandType *type,
+                                                     void *buffer, size_t length);
+
+typedef int (*ANeuralNetworksExecution_setOutputFromMemory_fn)(
+    ANeuralNetworksExecution *execution, int32_t index, const ANeuralNetworksOperandType *type,
+    const ANeuralNetworksMemory *memory, size_t offset, size_t length);
+
+typedef int (*ANeuralNetworksExecution_startCompute_fn)(ANeuralNetworksExecution *execution,
+                                                        ANeuralNetworksEvent **event);
+
+typedef int (*ANeuralNetworksEvent_wait_fn)(ANeuralNetworksEvent *event);
+
+typedef void (*ANeuralNetworksEvent_free_fn)(ANeuralNetworksEvent *event);
+
+typedef int (*ASharedMemory_create_fn)(const char *name, size_t size);
+
+typedef int (*ANeuralNetworks_getDeviceCount_fn)(uint32_t *numDevices);
+
+typedef int (*ANeuralNetworks_getDevice_fn)(uint32_t devIndex, ANeuralNetworksDevice **device);
+
+typedef int (*ANeuralNetworksDevice_getName_fn)(const ANeuralNetworksDevice *device,
+                                                const char **name);
+
+typedef int (*ANeuralNetworksDevice_getType_fn)(const ANeuralNetworksDevice *device, int32_t *type);
+
+typedef int (*ANeuralNetworksDevice_getVersion_fn)(const ANeuralNetworksDevice *device,
+                                                   const char **version);
+
+typedef int (*ANeuralNetworksDevice_getFeatureLevel_fn)(const ANeuralNetworksDevice *device,
+                                                        int64_t *featureLevel);
+
+typedef int (*ANeuralNetworksModel_getSupportedOperationsForDevices_fn)(
+    const ANeuralNetworksModel *model, const ANeuralNetworksDevice *const *devices,
+    uint32_t numDevices, bool *supportedOps);
+
+typedef int (*ANeuralNetworksCompilation_createForDevices_fn)(
+    ANeuralNetworksModel *model, const ANeuralNetworksDevice *const *devices, uint32_t numDevices,
+    ANeuralNetworksCompilation **compilation);
+
+typedef int (*ANeuralNetworksCompilation_setCaching_fn)(ANeuralNetworksCompilation *compilation,
+                                                        const char *cacheDir, const uint8_t *token);
+
+typedef int (*ANeuralNetworksExecution_compute_fn)(ANeuralNetworksExecution *execution);
+
+typedef int (*ANeuralNetworksExecution_getOutputOperandRank_fn)(ANeuralNetworksExecution *execution,
+                                                                int32_t index, uint32_t *rank);
+
+typedef int (*ANeuralNetworksExecution_getOutputOperandDimensions_fn)(
+    ANeuralNetworksExecution *execution, int32_t index, uint32_t *dimensions);
+
+typedef int (*ANeuralNetworksBurst_create_fn)(ANeuralNetworksCompilation *compilation,
+                                              ANeuralNetworksBurst **burst);
+
+typedef void (*ANeuralNetworksBurst_free_fn)(ANeuralNetworksBurst *burst);
+
+typedef int (*ANeuralNetworksExecution_burstCompute_fn)(ANeuralNetworksExecution *execution,
+                                                        ANeuralNetworksBurst *burst);
+
+typedef int (*ANeuralNetworksMemory_createFromAHardwareBuffer_fn)(const AHardwareBuffer *ahwb,
+                                                                  ANeuralNetworksMemory **memory);
+
+typedef int (*ANeuralNetworksExecution_setMeasureTiming_fn)(ANeuralNetworksExecution *execution,
+                                                            bool measure);
+
+typedef int (*ANeuralNetworksExecution_getDuration_fn)(const ANeuralNetworksExecution *execution,
+                                                       int32_t durationCode, uint64_t *duration);
+
+#endif // __NEURAL_NETWORKS_TYPES_H__
diff --git a/runtime/libs/profiling/CMakeLists.txt b/runtime/libs/profiling/CMakeLists.txt
new file mode 100644
index 000000000..e0398ce93
--- /dev/null
+++ b/runtime/libs/profiling/CMakeLists.txt
@@ -0,0 +1,7 @@
+file(GLOB_RECURSE SOURCES "src/*.cpp")
+
+add_library(nnfw_lib_profiling STATIC ${SOURCES})
+set_property(TARGET nnfw_lib_profiling PROPERTY POSITION_INDEPENDENT_CODE ON)
+target_include_directories(nnfw_lib_profiling PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/include)
+target_link_libraries(nnfw_lib_profiling PRIVATE nnfw_common)
+target_link_libraries(nnfw_lib_profiling PRIVATE nnfw_coverage)
diff --git a/runtime/libs/profiling/include/profiling/profile_buffer.h b/runtime/libs/profiling/include/profiling/profile_buffer.h
new file mode 100644
index 000000000..bc8d75e7c
--- /dev/null
+++ b/runtime/libs/profiling/include/profiling/profile_buffer.h
@@ -0,0 +1,170 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Copyright 2018 The TensorFlow Authors. All Rights Reserved.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+==============================================================================*/
+
+// NOTE To minimize diff with upstream tensorflow, disable clang-format
+// clang-format off
+
+// NOTE This header is derived from the following file (in TensorFlow v1.12)
+//        'externals/tensorflow/tensorflow/lite/profiling/profile_buffer.h
+#ifndef TENSORFLOW_CONTRIB_LITE_PROFILING_PROFILE_BUFFER_H_
+#define TENSORFLOW_CONTRIB_LITE_PROFILING_PROFILE_BUFFER_H_
+
+#include <cstddef>
+#include <cstdint>
+
+#include "profiling/time.h"
+
+namespace tflite {
+namespace profiling {
+
+// A profiling event.
+struct ProfileEvent {
+  // Describes the type of event.
+  // The event_metadata field may contain additional data for interpreting
+  // the event.
+  enum class EventType {
+    // Default event type, the metadata field has no special significance.
+    DEFAULT = 0,
+    // The event is an operator invocation and the event_metadata field is the
+    // index of operator node.
+    OPERATOR_INVOKE_EVENT = 1
+  };
+
+  // Label of the event. This usually describes the event.
+  const char* tag;
+  // Timestamp in microseconds when the event began.
+  uint64_t begin_timestamp_us;
+  // Timestamp in microseconds when the event ended.
+  uint64_t end_timestamp_us;
+  // The field containing the type of event. This must be one of the event types
+  // in EventType.
+  EventType event_type;
+  // Extra data describing the details of the event.
+  uint32_t event_metadata;
+};
+}  // namespace profiling
+}  // namespace tflite
+
+#ifdef TFLITE_PROFILING_ENABLED
+
+#include <sys/time.h>
+#include <vector>
+
+namespace tflite {
+namespace profiling {
+constexpr uint32_t kInvalidEventHandle = static_cast<uint32_t>(~0) - 1;
+
+// A ring buffer of profile events.
+// This class is not thread safe.
+class ProfileBuffer {
+ public:
+  ProfileBuffer(uint32_t max_num_entries, bool enabled)
+      : enabled_(enabled), current_index_(0), event_buffer_(max_num_entries) {}
+
+  // Adds an event to the buffer with begin timestamp set to the current
+  // timestamp. Returns a handle to event that can be used to call EndEvent. If
+  // buffer is disabled this has no affect.
+  // The tag of the event should remain valid till the buffer is valid.
+  uint32_t BeginEvent(const char* tag, ProfileEvent::EventType event_type,
+                      uint32_t event_metadata) {
+    if (!enabled_) {
+      return kInvalidEventHandle;
+    }
+    uint64_t timestamp = time::NowMicros();
+    int index = current_index_ % event_buffer_.size();
+    event_buffer_[index].tag = tag;
+    event_buffer_[index].event_type = event_type;
+    event_buffer_[index].event_metadata = event_metadata;
+    event_buffer_[index].begin_timestamp_us = timestamp;
+    event_buffer_[index].end_timestamp_us = 0;
+    current_index_++;
+    return index;
+  }
+
+  // Sets the enabled state of buffer to |enabled|
+  void SetEnabled(bool enabled) { enabled_ = enabled; }
+
+  // Sets the end timestamp for event for the handle to current time.
+  // If the buffer is disabled or previous event has been overwritten this
+  // operation has not effect.
+  void EndEvent(uint32_t event_handle) {
+    if (!enabled_ || event_handle == kInvalidEventHandle ||
+        event_handle > current_index_) {
+      return;
+    }
+    const uint32_t max_size = event_buffer_.size();
+    if (current_index_ > (max_size + event_handle)) {
+      // Ignore, buffer has already overflowed.
+      return;
+    }
+
+    int event_index = event_handle % max_size;
+    event_buffer_[event_index].end_timestamp_us = time::NowMicros();
+  }
+
+  // Returns the size of the buffer.
+  size_t Size() const {
+    return (current_index_ >= event_buffer_.size()) ? event_buffer_.size()
+                                                    : current_index_;
+  }
+
+  // Resets the buffer.
+  void Reset() {
+    enabled_ = false;
+    current_index_ = 0;
+  }
+
+  // Returns the profile event at the given index. If the index is invalid a
+  // nullptr is returned. The return event may get overwritten if more events
+  // are added to buffer.
+  const struct ProfileEvent* const At(int index) const {
+    size_t size = Size();
+    if (index >= size) {
+      return nullptr;
+    }
+    const uint32_t max_size = event_buffer_.size();
+    uint32_t start =
+        (current_index_ > max_size) ? current_index_ % max_size : max_size;
+    index = (index + start) % max_size;
+    return &event_buffer_[index];
+  }
+
+ private:
+  bool enabled_;
+  uint32_t current_index_;
+  std::vector<ProfileEvent> event_buffer_;
+};
+}  // namespace profiling
+}  // namespace tflite
+#endif  // TFLITE_PROFILING_ENABLED
+#endif  // TENSORFLOW_CONTRIB_LITE_PROFILING_PROFILE_BUFFER_H_
+
+// clang-format on
diff --git a/runtime/libs/profiling/include/profiling/profiler.h b/runtime/libs/profiling/include/profiling/profiler.h
new file mode 100644
index 000000000..ed3688140
--- /dev/null
+++ b/runtime/libs/profiling/include/profiling/profiler.h
@@ -0,0 +1,203 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Copyright 2018 The TensorFlow Authors. All Rights Reserved.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+==============================================================================*/
+
+// NOTE To minimize diff with upstream tensorflow, disable clang-format
+// clang-format off
+
+// NOTE This header is derived from the following file (in TensorFlow v1.12)
+//        'externals/tensorflow/tensorflow/lite/profiling/profiler.h
+#ifndef TENSORFLOW_CONTRIB_LITE_PROFILING_PROFILER_H_
+#define TENSORFLOW_CONTRIB_LITE_PROFILING_PROFILER_H_
+
+#include <vector>
+
+#include "profiling/profile_buffer.h"
+
+#ifdef TFLITE_PROFILING_ENABLED
+
+namespace tflite {
+namespace profiling {
+class ScopedProfile;
+class ScopedOperatorProfile;
+
+// Controls whether profiling is enabled or disabled and collects profiles.
+// TFLite is used on platforms that don't have posix threads, so the profiler is
+// kept as simple as possible. It is designed to be used only on a single
+// thread.
+//
+// Profiles are collected using Scoped*Profile objects that begin and end a
+// profile event.
+// An example usage is shown in the example below:
+//
+// Say Worker class has a DoWork method and we are interested in profiling
+// the overall execution time for DoWork and time spent in Task1 and Task2
+// functions.
+//
+// class Worker {
+//  public:
+//   void DoWork() {
+//    ScopedProfile(&controller, "DoWork");
+//    Task1();
+//    Task2();
+//    .....
+//   }
+//
+//   void Task1() {
+//    ScopedProfile(&controller, "Task1");
+//    ....
+//   }
+//
+//   void Task2() {
+//    ScopedProfile(&controller, "Task2");
+//   }
+//
+//    Profiler profiler;
+// }
+//
+// We instrument the functions that need to be profiled.
+//
+// Profile can be collected by enable profiling and then getting profile
+// events.
+//
+//  void ProfileWorker() {
+//    Worker worker;
+//    worker.profiler.EnableProfiling();
+//    worker.DoWork();
+//    worker.profiler.DisableProfiling();
+//    // Profiling is complete, extract profiles.
+//    auto profile_events = worker.profiler.GetProfiles();
+//  }
+//
+//
+class Profiler {
+ public:
+  Profiler() : buffer_(1024, false) {}
+
+  void StartProfiling() { buffer_.SetEnabled(true); }
+  void StopProfiling() { buffer_.SetEnabled(false); }
+  void Reset() { buffer_.Reset(); }
+  std::vector<const ProfileEvent*> GetProfileEvents() {
+    std::vector<const ProfileEvent*> profile_events;
+    profile_events.reserve(buffer_.Size());
+    for (size_t i = 0; i < buffer_.Size(); i++) {
+      profile_events.push_back(buffer_.At(i));
+    }
+    return profile_events;
+  }
+
+ private:
+  friend class ScopedProfile;
+  friend class ScopedOperatorProfile;
+  ProfileBuffer* GetProfileBuffer() { return &buffer_; }
+  ProfileBuffer buffer_;
+};
+
+class ScopedProfile {
+ public:
+  // Adds a profile event to profile that begins with the construction
+  // of object and ends when the object goes out of scope.
+  // The lifetime of tag should be at least the lifetime of profiler.
+
+  ScopedProfile(Profiler* profiler, const char* tag)
+      : buffer_(nullptr), event_handle_(0) {
+    if (profiler) {
+      buffer_ = profiler->GetProfileBuffer();
+      event_handle_ =
+          buffer_->BeginEvent(tag, ProfileEvent::EventType::DEFAULT, 0);
+    }
+  }
+  ~ScopedProfile() {
+    if (buffer_) {
+      buffer_->EndEvent(event_handle_);
+    }
+  }
+
+ private:
+  ProfileBuffer* buffer_;
+  int32_t event_handle_;
+};
+
+class ScopedOperatorProfile {
+ public:
+  // Adds a profile event to profile that begins with the construction
+  // of object and ends when the object goes out of scope.
+  // The lifetime of tag should be at least the lifetime of profiler.
+  ScopedOperatorProfile(Profiler* profiler, const char* tag, int node_index)
+      : buffer_(nullptr), event_handle_(0) {
+    if (profiler) {
+      buffer_ = profiler->GetProfileBuffer();
+      event_handle_ = buffer_->BeginEvent(
+          tag, ProfileEvent::EventType::OPERATOR_INVOKE_EVENT, node_index);
+    }
+  }
+
+  ~ScopedOperatorProfile() {
+    if (buffer_) {
+      buffer_->EndEvent(event_handle_);
+    }
+  }
+
+ private:
+  ProfileBuffer* buffer_;
+  int32_t event_handle_;
+};
+
+}  // namespace profiling
+}  // namespace tflite
+
+#define VARNAME_UNIQ(name, ctr) name##ctr
+
+#define SCOPED_OPERATOR_PROFILE(profiler, node_index)    \
+  tflite::profiling::ScopedOperatorProfile VARNAME_UNIQ( \
+      _profile_, __COUNTER__)((profiler), "OpInvoke", (node_index))
+#else
+
+namespace tflite {
+namespace profiling {
+// A noop version of profiler when profiling is disabled.
+class Profiler {
+ public:
+  Profiler() {}
+  void StartProfiling() {}
+  void StopProfiling() {}
+  void Reset() {}
+  std::vector<const ProfileEvent*> GetProfileEvents() { return {}; }
+};
+}  // namespace profiling
+}  // namespace tflite
+
+#define SCOPED_OPERATOR_PROFILE(profiler, node_index)
+
+#endif  // TFLITE_PROFILING_ENABLED
+
+#endif  // TENSORFLOW_CONTRIB_LITE_PROFILING_PROFILER_H_
+
+// clang-format on
diff --git a/runtime/libs/profiling/include/profiling/profiling.h b/runtime/libs/profiling/include/profiling/profiling.h
new file mode 100644
index 000000000..ee0df1338
--- /dev/null
+++ b/runtime/libs/profiling/include/profiling/profiling.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NNFW_MISC_PROFILING_H__
+#define __NNFW_MISC_PROFILING_H__
+
+#include <iostream>
+
+namespace tflite
+{
+namespace profiling
+{
+class Profiler; // forward declaration
+}
+}
+
+namespace profiling
+{
+
+class Context
+{
+public:
+  Context() : _sync(false), _profiler(nullptr) {}
+
+public:
+  const bool &sync(void) const { return _sync; }
+  tflite::profiling::Profiler *getProfiler() { return _profiler; }
+  void setProfiler(tflite::profiling::Profiler *p) { _profiler = p; }
+  void setSync(void) { _sync = true; }
+
+private:
+  bool _sync;
+  tflite::profiling::Profiler *_profiler;
+
+public:
+  static Context &get(void)
+  {
+    static Context ctx{};
+    return ctx;
+  }
+};
+
+} // namespace profiling
+#endif // __NNFW_MISC_PROFILING_H__
diff --git a/runtime/libs/profiling/include/profiling/time.h b/runtime/libs/profiling/include/profiling/time.h
new file mode 100644
index 000000000..200563aa6
--- /dev/null
+++ b/runtime/libs/profiling/include/profiling/time.h
@@ -0,0 +1,35 @@
+/* Copyright 2018 The TensorFlow Authors. All Rights Reserved.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+==============================================================================*/
+
+// NOTE To minimize diff with upstream tensorflow, disable clang-format
+// clang-format off
+
+// NOTE This header is derived from the following file (in TensorFlow v1.12)
+//        'externals/tensorflow/tensorflow/lite/profiling/time.h
+#ifndef TENSORFLOW_CONTRIB_LITE_PROFILING_TIME_H_
+#define TENSORFLOW_CONTRIB_LITE_PROFILING_TIME_H_
+
+#include <cstdint>
+
+namespace tflite {
+namespace profiling {
+namespace time {
+uint64_t NowMicros();
+}  // namespace time
+}  // namespace profiling
+}  // namespace tflite
+#endif  // TENSORFLOW_CONTRIB_LITE_PROFILING_TIME_H_
+
+// clang-format on
diff --git a/runtime/libs/profiling/src/profiling/time.cpp b/runtime/libs/profiling/src/profiling/time.cpp
new file mode 100644
index 000000000..761023e6d
--- /dev/null
+++ b/runtime/libs/profiling/src/profiling/time.cpp
@@ -0,0 +1,55 @@
+/* Copyright 2018 The TensorFlow Authors. All Rights Reserved.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+==============================================================================*/
+
+// NOTE To minimize diff with upstream tensorflow, disable clang-format
+// clang-format off
+
+// NOTE This header is derived from the following file (in TensorFlow v1.12)
+//        'externals/tensorflow/tensorflow/lite/profiling/time.cpp
+#include "profiling/time.h"
+
+#if defined(_MSC_VER)
+#include <chrono>  // NOLINT(build/c++11)
+#else
+#include <sys/time.h>
+#endif
+
+namespace tflite {
+namespace profiling {
+namespace time {
+
+#if defined(_MSC_VER)
+
+uint64_t NowMicros() {
+  return std::chrono::duration_cast<std::chrono::microseconds>(
+             std::chrono::system_clock::now().time_since_epoch())
+      .count();
+}
+
+#else
+
+uint64_t NowMicros() {
+  struct timeval tv;
+  gettimeofday(&tv, nullptr);
+  return static_cast<uint64_t>(tv.tv_sec) * 1000000 + tv.tv_usec;
+}
+
+#endif  // defined(_MSC_VER)
+
+}  // namespace time
+}  // namespace profiling
+}  // namespace tflite
+
+// clang-format on
diff --git a/runtime/libs/rua/CMakeLists.txt b/runtime/libs/rua/CMakeLists.txt
new file mode 100644
index 000000000..07ad9ea26
--- /dev/null
+++ b/runtime/libs/rua/CMakeLists.txt
@@ -0,0 +1,4 @@
+add_subdirectory(core)
+add_subdirectory(dyn)
+add_subdirectory(anchor)
+add_subdirectory(shim)
diff --git a/runtime/libs/rua/README.md b/runtime/libs/rua/README.md
new file mode 100644
index 000000000..aea4ce033
--- /dev/null
+++ b/runtime/libs/rua/README.md
@@ -0,0 +1,4 @@
+# rua
+
+_rua_ is a **RU**ntime **A**bstraction layer which allows us to switch between multiple
+Android NN rutime during execution (not loading time).
diff --git a/runtime/libs/rua/anchor/CMakeLists.txt b/runtime/libs/rua/anchor/CMakeLists.txt
new file mode 100644
index 000000000..6e65641f4
--- /dev/null
+++ b/runtime/libs/rua/anchor/CMakeLists.txt
@@ -0,0 +1,9 @@
+file(GLOB_RECURSE SOURCES "src/*.cpp")
+
+add_library(nnfw_lib_rua_anchor STATIC ${SOURCES})
+set_target_properties(nnfw_lib_rua_anchor PROPERTIES POSITION_INDEPENDENT_CODE ON)
+target_include_directories(nnfw_lib_rua_anchor PUBLIC include)
+target_link_libraries(nnfw_lib_rua_anchor PUBLIC nnfw_lib_rua_core)
+target_link_libraries(nnfw_lib_rua_anchor PRIVATE nnfw_lib_rua_dyn)
+target_link_libraries(nnfw_lib_rua_anchor PRIVATE nnfw_common)
+target_link_libraries(nnfw_lib_rua_anchor PRIVATE nnfw_coverage)
diff --git a/runtime/libs/rua/anchor/include/rua/Anchor.h b/runtime/libs/rua/anchor/include/rua/Anchor.h
new file mode 100644
index 000000000..f6056ab4e
--- /dev/null
+++ b/runtime/libs/rua/anchor/include/rua/Anchor.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NNFW_RUA_ANCHOR_H__
+#define __NNFW_RUA_ANCHOR_H__
+
+#include <rua/Service.h>
+
+namespace rua
+{
+
+/**
+ * @brief Global Runtime Abstraction Context
+ *
+ * "set" will have global effect (within each process).
+ */
+struct Anchor
+{
+  static const RuntimeService *get(void);
+  static void set(const RuntimeService *svc);
+};
+
+} // namespace rua
+
+#endif // __NNFW_RUA_ANCHOR_H__
diff --git a/runtime/libs/rua/anchor/src/Anchor.cpp b/runtime/libs/rua/anchor/src/Anchor.cpp
new file mode 100644
index 000000000..a78cca19e
--- /dev/null
+++ b/runtime/libs/rua/anchor/src/Anchor.cpp
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "rua/Anchor.h"
+#include <rua/DynamicBinder.h>
+
+namespace
+{
+
+const rua::RuntimeService *anchored_service = rua::DynamicBinder::get();
+
+} // namespace
+
+namespace rua
+{
+
+const RuntimeService *Anchor::get(void) { return anchored_service; }
+void Anchor::set(const RuntimeService *service) { anchored_service = service; }
+
+} // namespace rua
diff --git a/runtime/libs/rua/core/CMakeLists.txt b/runtime/libs/rua/core/CMakeLists.txt
new file mode 100644
index 000000000..f7d41f657
--- /dev/null
+++ b/runtime/libs/rua/core/CMakeLists.txt
@@ -0,0 +1,3 @@
+add_library(nnfw_lib_rua_core INTERFACE)
+target_include_directories(nnfw_lib_rua_core INTERFACE include)
+target_link_libraries(nnfw_lib_rua_core INTERFACE nnfw_lib_nnapi)
diff --git a/runtime/libs/rua/core/include/rua/Service.h b/runtime/libs/rua/core/include/rua/Service.h
new file mode 100644
index 000000000..a79524a8a
--- /dev/null
+++ b/runtime/libs/rua/core/include/rua/Service.h
@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Service.h
+ * @brief Core abstraction that RUA depends on.
+ */
+#ifndef __NNFW_RUA_SERVICE_H__
+#define __NNFW_RUA_SERVICE_H__
+
+#include "NeuralNetworks.h"
+
+struct ANeuralNetworksMemory;
+struct ANeuralNetworksEvent;
+
+struct ANeuralNetworksModel;
+struct ANeuralNetworksCompilation;
+struct ANeuralNetworksExecution;
+
+namespace rua
+{
+
+/**
+ * @brief A wrapper for ANeuralNetworkMemory API
+ */
+struct MemoryService
+{
+  virtual ~MemoryService() = default;
+
+  virtual int createFromFd(size_t size, int protect, int fd, size_t offset,
+                           ANeuralNetworksMemory **memory) const = 0;
+
+  virtual void free(ANeuralNetworksMemory *memory) const = 0;
+};
+
+/**
+ * @brief A wrapper for ANeuralNetworkModel API
+ */
+struct ModelService
+{
+  virtual ~ModelService() = default;
+
+  virtual int create(ANeuralNetworksModel **model) const = 0;
+
+  virtual int addOperand(ANeuralNetworksModel *model,
+                         const ANeuralNetworksOperandType *type) const = 0;
+
+  virtual int setOperandValue(ANeuralNetworksModel *model, int32_t index, const void *buffer,
+                              size_t length) const = 0;
+
+  virtual int setOperandValueFromMemory(ANeuralNetworksModel *model, int32_t index,
+                                        const ANeuralNetworksMemory *memory, size_t offset,
+                                        size_t length) const = 0;
+
+  virtual int addOperation(ANeuralNetworksModel *model, ANeuralNetworksOperationType type,
+                           uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+                           const uint32_t *outputs) const = 0;
+
+  virtual int identifyInputsAndOutputs(ANeuralNetworksModel *model, uint32_t inputCount,
+                                       const uint32_t *inputs, uint32_t outputCount,
+                                       const uint32_t *outputs) const = 0;
+
+  virtual int relaxComputationFloat32toFloat16(ANeuralNetworksModel *model, bool allow) const = 0;
+
+  virtual int finish(ANeuralNetworksModel *model) const = 0;
+
+  virtual void free(ANeuralNetworksModel *model) const = 0;
+};
+
+/**
+ * @brief A wrapper for ANeuralNetworkCompilation API
+ */
+struct CompilationService
+{
+  virtual ~CompilationService() = default;
+
+  virtual int create(ANeuralNetworksModel *model,
+                     ANeuralNetworksCompilation **compilation) const = 0;
+
+  virtual int setPreference(ANeuralNetworksCompilation *compilation, int32_t preference) const = 0;
+  virtual int finish(ANeuralNetworksCompilation *compilation) const = 0;
+
+  virtual void free(ANeuralNetworksCompilation *compilation) const = 0;
+};
+
+/**
+ * @brief A wrapper for ANeuralNetworkExecution API
+ */
+struct ExecutionService
+{
+  virtual ~ExecutionService() = default;
+
+  virtual int create(ANeuralNetworksCompilation *compilation,
+                     ANeuralNetworksExecution **execution) const = 0;
+
+  virtual void free(ANeuralNetworksExecution *execution) const = 0;
+
+  virtual int setInput(ANeuralNetworksExecution *execution, int32_t index,
+                       const ANeuralNetworksOperandType *type, const void *buffer,
+                       size_t length) const = 0;
+
+  virtual int setInputFromMemory(ANeuralNetworksExecution *execution, int32_t index,
+                                 const ANeuralNetworksOperandType *type,
+                                 const ANeuralNetworksMemory *memory, size_t offset,
+                                 size_t length) const = 0;
+
+  virtual int setOutput(ANeuralNetworksExecution *execution, int32_t index,
+                        const ANeuralNetworksOperandType *type, void *buffer,
+                        size_t length) const = 0;
+
+  virtual int setOutputFromMemory(ANeuralNetworksExecution *execution, int32_t index,
+                                  const ANeuralNetworksOperandType *type,
+                                  const ANeuralNetworksMemory *memory, size_t offset,
+                                  size_t length) const = 0;
+
+  virtual int startCompute(ANeuralNetworksExecution *execution,
+                           ANeuralNetworksEvent **event) const = 0;
+};
+
+/**
+ * @brief A wrapper for ANeuralNetworkEvent API
+ */
+struct EventService
+{
+  virtual int wait(ANeuralNetworksEvent *event) const = 0;
+  virtual void free(ANeuralNetworksEvent *event) const = 0;
+};
+
+/**
+ * @brief A wrapper for Android NN rutime itself
+ */
+struct RuntimeService
+{
+  virtual ~RuntimeService() = default;
+
+  virtual const MemoryService *memory(void) const = 0;
+  virtual const ModelService *model(void) const = 0;
+  virtual const CompilationService *compilation(void) const = 0;
+  virtual const ExecutionService *execution(void) const = 0;
+  virtual const EventService *event(void) const = 0;
+};
+
+} // namespace rua
+
+#endif // __NNFW_RUA_SERVICE_H__
diff --git a/runtime/libs/rua/dyn/CMakeLists.txt b/runtime/libs/rua/dyn/CMakeLists.txt
new file mode 100644
index 000000000..3f9ac8928
--- /dev/null
+++ b/runtime/libs/rua/dyn/CMakeLists.txt
@@ -0,0 +1,8 @@
+file(GLOB_RECURSE SOURCES "src/*.cpp")
+
+add_library(nnfw_lib_rua_dyn STATIC ${SOURCES})
+set_target_properties(nnfw_lib_rua_dyn PROPERTIES POSITION_INDEPENDENT_CODE ON)
+target_include_directories(nnfw_lib_rua_dyn PUBLIC include)
+target_link_libraries(nnfw_lib_rua_dyn PUBLIC nnfw_lib_rua_core)
+target_link_libraries(nnfw_lib_rua_dyn PRIVATE nnfw_common)
+target_link_libraries(nnfw_lib_rua_dyn PRIVATE nnfw_coverage)
diff --git a/runtime/libs/rua/dyn/include/rua/DynamicBinder.h b/runtime/libs/rua/dyn/include/rua/DynamicBinder.h
new file mode 100644
index 000000000..8ce0c42f8
--- /dev/null
+++ b/runtime/libs/rua/dyn/include/rua/DynamicBinder.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NNFW_RUA_DYNAMIC_BINDER_H__
+#define __NNFW_RUA_DYNAMIC_BINDER_H__
+
+#include <rua/Service.h>
+
+namespace rua
+{
+
+/**
+ * @brief Bind Android NN runtime implementation via dlopen & dlsym
+ */
+struct DynamicBinder
+{
+  static const rua::RuntimeService *get(void);
+};
+
+} // namespace
+
+#endif // __NNFW_RUA_DYNAMIC_BINDER_H__
diff --git a/runtime/libs/rua/dyn/src/DynamicBinder.cpp b/runtime/libs/rua/dyn/src/DynamicBinder.cpp
new file mode 100644
index 000000000..68dae6262
--- /dev/null
+++ b/runtime/libs/rua/dyn/src/DynamicBinder.cpp
@@ -0,0 +1,353 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "rua/DynamicBinder.h"
+
+#include "NeuralNetworksLoadHelpers.h"
+
+using namespace rua;
+
+//
+// Memory
+//
+namespace
+{
+
+typedef int (*ANeuralNetworksMemory_createFromFd_fn)(size_t size, int protect, int fd,
+                                                     size_t offset, ANeuralNetworksMemory **memory);
+
+typedef void (*ANeuralNetworksMemory_free_fn)(ANeuralNetworksMemory *memory);
+
+struct MemoryServiceImpl final : public MemoryService
+{
+  int createFromFd(size_t size, int protect, int fd, size_t offset,
+                   ANeuralNetworksMemory **memory) const override
+  {
+    LOAD_FUNCTION(ANeuralNetworksMemory_createFromFd);
+    EXECUTE_FUNCTION_RETURN(size, protect, fd, offset, memory);
+  }
+
+  void free(ANeuralNetworksMemory *memory) const override
+  {
+    LOAD_FUNCTION(ANeuralNetworksMemory_free);
+    EXECUTE_FUNCTION(memory);
+  }
+};
+
+} // namespace
+
+//
+// Event
+//
+namespace
+{
+
+typedef int (*ANeuralNetworksEvent_wait_fn)(ANeuralNetworksEvent *event);
+
+typedef void (*ANeuralNetworksEvent_free_fn)(ANeuralNetworksEvent *event);
+
+struct EventServiceImpl final : public EventService
+{
+
+  int wait(ANeuralNetworksEvent *event) const override
+  {
+    LOAD_FUNCTION(ANeuralNetworksEvent_wait);
+    EXECUTE_FUNCTION_RETURN(event);
+  }
+
+  void free(ANeuralNetworksEvent *event) const override
+  {
+    LOAD_FUNCTION(ANeuralNetworksEvent_free);
+    EXECUTE_FUNCTION(event);
+  }
+};
+
+} // namespace
+
+//
+// Model
+//
+namespace
+{
+
+typedef int (*ANeuralNetworksModel_create_fn)(ANeuralNetworksModel **model);
+
+typedef int (*ANeuralNetworksModel_finish_fn)(ANeuralNetworksModel *model);
+
+typedef void (*ANeuralNetworksModel_free_fn)(ANeuralNetworksModel *model);
+
+typedef int (*ANeuralNetworksModel_addOperand_fn)(ANeuralNetworksModel *model,
+                                                  const ANeuralNetworksOperandType *type);
+
+typedef int (*ANeuralNetworksModel_setOperandValue_fn)(ANeuralNetworksModel *model, int32_t index,
+                                                       const void *buffer, size_t length);
+
+typedef int (*ANeuralNetworksModel_setOperandValueFromMemory_fn)(
+    ANeuralNetworksModel *model, int32_t index, const ANeuralNetworksMemory *memory, size_t offset,
+    size_t length);
+
+typedef int (*ANeuralNetworksModel_addOperation_fn)(ANeuralNetworksModel *model,
+                                                    ANeuralNetworksOperationType type,
+                                                    uint32_t inputCount, const uint32_t *inputs,
+                                                    uint32_t outputCount, const uint32_t *outputs);
+
+typedef int (*ANeuralNetworksModel_identifyInputsAndOutputs_fn)(ANeuralNetworksModel *model,
+                                                                uint32_t inputCount,
+                                                                const uint32_t *inputs,
+                                                                uint32_t outputCount,
+                                                                const uint32_t *outputs);
+
+typedef int (*ANeuralNetworksModel_relaxComputationFloat32toFloat16_fn)(ANeuralNetworksModel *model,
+                                                                        bool allow);
+
+struct ModelServiceImpl final : public ModelService
+{
+  int create(ANeuralNetworksModel **model) const override
+  {
+    LOAD_FUNCTION(ANeuralNetworksModel_create);
+    EXECUTE_FUNCTION_RETURN(model);
+  }
+
+  int addOperand(ANeuralNetworksModel *model, const ANeuralNetworksOperandType *type) const override
+  {
+    LOAD_FUNCTION(ANeuralNetworksModel_addOperand);
+    EXECUTE_FUNCTION_RETURN(model, type);
+  }
+  int setOperandValue(ANeuralNetworksModel *model, int32_t index, const void *buffer,
+                      size_t length) const override
+  {
+    LOAD_FUNCTION(ANeuralNetworksModel_setOperandValue);
+    EXECUTE_FUNCTION_RETURN(model, index, buffer, length);
+  }
+
+  int setOperandValueFromMemory(ANeuralNetworksModel *model, int32_t index,
+                                const ANeuralNetworksMemory *memory, size_t offset,
+                                size_t length) const override
+  {
+    LOAD_FUNCTION(ANeuralNetworksModel_setOperandValueFromMemory);
+    EXECUTE_FUNCTION_RETURN(model, index, memory, offset, length);
+  }
+
+  int addOperation(ANeuralNetworksModel *model, ANeuralNetworksOperationType type,
+                   uint32_t inputCount, const uint32_t *inputs, uint32_t outputCount,
+                   const uint32_t *outputs) const override
+  {
+    LOAD_FUNCTION(ANeuralNetworksModel_addOperation);
+    EXECUTE_FUNCTION_RETURN(model, type, inputCount, inputs, outputCount, outputs);
+  }
+
+  int identifyInputsAndOutputs(ANeuralNetworksModel *model, uint32_t inputCount,
+                               const uint32_t *inputs, uint32_t outputCount,
+                               const uint32_t *outputs) const override
+  {
+    LOAD_FUNCTION(ANeuralNetworksModel_identifyInputsAndOutputs);
+    EXECUTE_FUNCTION_RETURN(model, inputCount, inputs, outputCount, outputs);
+  }
+
+  int relaxComputationFloat32toFloat16(ANeuralNetworksModel *model, bool allow) const override
+  {
+    LOAD_FUNCTION(ANeuralNetworksModel_relaxComputationFloat32toFloat16);
+    EXECUTE_FUNCTION_RETURN(model, allow);
+  }
+
+  int finish(ANeuralNetworksModel *model) const override
+  {
+    LOAD_FUNCTION(ANeuralNetworksModel_finish);
+    EXECUTE_FUNCTION_RETURN(model);
+  }
+
+  void free(ANeuralNetworksModel *model) const override
+  {
+    LOAD_FUNCTION(ANeuralNetworksModel_free);
+    EXECUTE_FUNCTION(model);
+  }
+};
+
+} // namespace
+
+//
+// Compilation
+//
+namespace
+{
+
+typedef int (*ANeuralNetworksCompilation_create_fn)(ANeuralNetworksModel *model,
+                                                    ANeuralNetworksCompilation **compilation);
+
+typedef void (*ANeuralNetworksCompilation_free_fn)(ANeuralNetworksCompilation *compilation);
+
+typedef int (*ANeuralNetworksCompilation_setPreference_fn)(ANeuralNetworksCompilation *compilation,
+                                                           int32_t preference);
+
+typedef int (*ANeuralNetworksCompilation_finish_fn)(ANeuralNetworksCompilation *compilation);
+
+struct CompilationServiceImpl : public CompilationService
+{
+
+  int create(ANeuralNetworksModel *model, ANeuralNetworksCompilation **compilation) const override
+  {
+    LOAD_FUNCTION(ANeuralNetworksCompilation_create);
+    EXECUTE_FUNCTION_RETURN(model, compilation);
+  }
+
+  int setPreference(ANeuralNetworksCompilation *compilation, int32_t preference) const override
+  {
+    LOAD_FUNCTION(ANeuralNetworksCompilation_setPreference);
+    EXECUTE_FUNCTION_RETURN(compilation, preference);
+  }
+
+  int finish(ANeuralNetworksCompilation *compilation) const override
+  {
+    LOAD_FUNCTION(ANeuralNetworksCompilation_finish);
+    EXECUTE_FUNCTION_RETURN(compilation);
+  }
+
+  void free(ANeuralNetworksCompilation *compilation) const override
+  {
+    LOAD_FUNCTION(ANeuralNetworksCompilation_free);
+    EXECUTE_FUNCTION(compilation);
+  }
+};
+
+} // namespace
+
+//
+// Exceution
+//
+namespace
+{
+
+typedef int (*ANeuralNetworksExecution_create_fn)(ANeuralNetworksCompilation *compilation,
+                                                  ANeuralNetworksExecution **execution);
+
+typedef void (*ANeuralNetworksExecution_free_fn)(ANeuralNetworksExecution *execution);
+
+typedef int (*ANeuralNetworksExecution_setInput_fn)(ANeuralNetworksExecution *execution,
+                                                    int32_t index,
+                                                    const ANeuralNetworksOperandType *type,
+                                                    const void *buffer, size_t length);
+
+typedef int (*ANeuralNetworksExecution_setInputFromMemory_fn)(
+    ANeuralNetworksExecution *execution, int32_t index, const ANeuralNetworksOperandType *type,
+    const ANeuralNetworksMemory *memory, size_t offset, size_t length);
+
+typedef int (*ANeuralNetworksExecution_setOutput_fn)(ANeuralNetworksExecution *execution,
+                                                     int32_t index,
+                                                     const ANeuralNetworksOperandType *type,
+                                                     void *buffer, size_t length);
+
+typedef int (*ANeuralNetworksExecution_setOutputFromMemory_fn)(
+    ANeuralNetworksExecution *execution, int32_t index, const ANeuralNetworksOperandType *type,
+    const ANeuralNetworksMemory *memory, size_t offset, size_t length);
+
+typedef int (*ANeuralNetworksExecution_startCompute_fn)(ANeuralNetworksExecution *execution,
+                                                        ANeuralNetworksEvent **event);
+
+struct ExecutionServiceImpl : public ExecutionService
+{
+
+  int create(ANeuralNetworksCompilation *compilation,
+             ANeuralNetworksExecution **execution) const override
+  {
+    LOAD_FUNCTION(ANeuralNetworksExecution_create);
+    EXECUTE_FUNCTION_RETURN(compilation, execution);
+  }
+
+  int setInput(ANeuralNetworksExecution *execution, int32_t index,
+               const ANeuralNetworksOperandType *type, const void *buffer,
+               size_t length) const override
+  {
+    LOAD_FUNCTION(ANeuralNetworksExecution_setInput);
+    EXECUTE_FUNCTION_RETURN(execution, index, type, buffer, length);
+  }
+
+  int setInputFromMemory(ANeuralNetworksExecution *execution, int32_t index,
+                         const ANeuralNetworksOperandType *type,
+                         const ANeuralNetworksMemory *memory, size_t offset,
+                         size_t length) const override
+  {
+    LOAD_FUNCTION(ANeuralNetworksExecution_setInputFromMemory);
+    EXECUTE_FUNCTION_RETURN(execution, index, type, memory, offset, length);
+  }
+
+  int setOutput(ANeuralNetworksExecution *execution, int32_t index,
+                const ANeuralNetworksOperandType *type, void *buffer, size_t length) const override
+  {
+    LOAD_FUNCTION(ANeuralNetworksExecution_setOutput);
+    EXECUTE_FUNCTION_RETURN(execution, index, type, buffer, length);
+  }
+
+  int setOutputFromMemory(ANeuralNetworksExecution *execution, int32_t index,
+                          const ANeuralNetworksOperandType *type,
+                          const ANeuralNetworksMemory *memory, size_t offset,
+                          size_t length) const override
+  {
+    LOAD_FUNCTION(ANeuralNetworksExecution_setOutputFromMemory);
+    EXECUTE_FUNCTION_RETURN(execution, index, type, memory, offset, length);
+  }
+
+  int startCompute(ANeuralNetworksExecution *execution, ANeuralNetworksEvent **event) const override
+  {
+    LOAD_FUNCTION(ANeuralNetworksExecution_startCompute);
+    EXECUTE_FUNCTION_RETURN(execution, event);
+  }
+
+  void free(ANeuralNetworksExecution *execution) const override
+  {
+    LOAD_FUNCTION(ANeuralNetworksExecution_free);
+    EXECUTE_FUNCTION(execution);
+  }
+};
+
+} // namespace
+
+//
+// Runtime
+//
+namespace
+{
+
+class RuntimeImpl final : public RuntimeService
+{
+public:
+  const MemoryService *memory(void) const override { return &_memory; }
+  const EventService *event(void) const override { return &_event; }
+
+  const ModelService *model(void) const override { return &_model; }
+  const CompilationService *compilation(void) const override { return &_compilation; }
+  const ExecutionService *execution(void) const override { return &_execution; }
+
+private:
+  MemoryServiceImpl _memory;
+  EventServiceImpl _event;
+
+  ModelServiceImpl _model;
+  CompilationServiceImpl _compilation;
+  ExecutionServiceImpl _execution;
+};
+
+} // namespace
+
+namespace rua
+{
+
+const RuntimeService *DynamicBinder::get(void)
+{
+  static RuntimeImpl runtime;
+  return &runtime;
+}
+
+} // namespace rua
diff --git a/runtime/libs/rua/shim/CMakeLists.txt b/runtime/libs/rua/shim/CMakeLists.txt
new file mode 100644
index 000000000..814db5f7f
--- /dev/null
+++ b/runtime/libs/rua/shim/CMakeLists.txt
@@ -0,0 +1,4 @@
+add_library(nnfw_lib_rua_shim INTERFACE)
+target_include_directories(nnfw_lib_rua_shim INTERFACE include)
+target_link_libraries(nnfw_lib_rua_shim INTERFACE nnfw_lib_rua_core)
+target_link_libraries(nnfw_lib_rua_shim INTERFACE nnfw_lib_rua_anchor)
diff --git a/runtime/libs/rua/shim/include/rua/Shim.h b/runtime/libs/rua/shim/include/rua/Shim.h
new file mode 100644
index 000000000..07a4bb2fd
--- /dev/null
+++ b/runtime/libs/rua/shim/include/rua/Shim.h
@@ -0,0 +1,192 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NNFW_RUA_SHIM_H__
+#define __NNFW_RUA_SHIM_H__
+
+#include <rua/Anchor.h>
+
+//
+// Memory
+//
+inline int ANeuralNetworksMemory_createFromFd(size_t size, int protect, int fd, size_t offset,
+                                              ANeuralNetworksMemory **memory)
+{
+  return rua::Anchor::get()->memory()->createFromFd(size, protect, fd, offset, memory);
+}
+
+inline void ANeuralNetworksMemory_free(ANeuralNetworksMemory *memory)
+{
+  return rua::Anchor::get()->memory()->free(memory);
+}
+
+//
+// Event
+//
+inline int ANeuralNetworksEvent_wait(ANeuralNetworksEvent *event)
+{
+  return rua::Anchor::get()->event()->wait(event);
+}
+
+inline void ANeuralNetworksEvent_free(ANeuralNetworksEvent *event)
+{
+  return rua::Anchor::get()->event()->free(event);
+}
+
+//
+// Model
+//
+inline int ANeuralNetworksModel_create(ANeuralNetworksModel **model)
+{
+  return rua::Anchor::get()->model()->create(model);
+}
+
+inline int ANeuralNetworksModel_addOperand(ANeuralNetworksModel *model,
+                                           const ANeuralNetworksOperandType *type)
+{
+  return rua::Anchor::get()->model()->addOperand(model, type);
+}
+
+inline int ANeuralNetworksModel_setOperandValue(ANeuralNetworksModel *model, int32_t index,
+                                                const void *buffer, size_t length)
+{
+  return rua::Anchor::get()->model()->setOperandValue(model, index, buffer, length);
+}
+
+inline int ANeuralNetworksModel_setOperandValueFromMemory(ANeuralNetworksModel *model,
+                                                          int32_t index,
+                                                          const ANeuralNetworksMemory *memory,
+                                                          size_t offset, size_t length)
+{
+  return rua::Anchor::get()->model()->setOperandValueFromMemory(model, index, memory, offset,
+                                                                length);
+}
+
+inline int ANeuralNetworksModel_addOperation(ANeuralNetworksModel *model,
+                                             ANeuralNetworksOperationType type, uint32_t inputCount,
+                                             const uint32_t *inputs, uint32_t outputCount,
+                                             const uint32_t *outputs)
+{
+  return rua::Anchor::get()->model()->addOperation(model, type, inputCount, inputs, outputCount,
+                                                   outputs);
+}
+
+inline int ANeuralNetworksModel_identifyInputsAndOutputs(ANeuralNetworksModel *model,
+                                                         uint32_t inputCount,
+                                                         const uint32_t *inputs,
+                                                         uint32_t outputCount,
+                                                         const uint32_t *outputs)
+{
+  return rua::Anchor::get()->model()->identifyInputsAndOutputs(model, inputCount, inputs,
+                                                               outputCount, outputs);
+}
+
+inline int ANeuralNetworksModel_relaxComputationFloat32toFloat16(ANeuralNetworksModel *model,
+                                                                 bool allow)
+{
+  return rua::Anchor::get()->model()->relaxComputationFloat32toFloat16(model, allow);
+}
+
+inline int ANeuralNetworksModel_finish(ANeuralNetworksModel *model)
+{
+  return rua::Anchor::get()->model()->finish(model);
+}
+
+inline void ANeuralNetworksModel_free(ANeuralNetworksModel *model)
+{
+  return rua::Anchor::get()->model()->free(model);
+}
+
+//
+// Compilation
+//
+inline int ANeuralNetworksCompilation_create(ANeuralNetworksModel *model,
+                                             ANeuralNetworksCompilation **compilation)
+{
+  return rua::Anchor::get()->compilation()->create(model, compilation);
+}
+
+inline int ANeuralNetworksCompilation_setPreference(ANeuralNetworksCompilation *compilation,
+                                                    int32_t preference)
+{
+  return rua::Anchor::get()->compilation()->setPreference(compilation, preference);
+}
+
+inline int ANeuralNetworksCompilation_finish(ANeuralNetworksCompilation *compilation)
+{
+  return rua::Anchor::get()->compilation()->finish(compilation);
+}
+
+inline void ANeuralNetworksCompilation_free(ANeuralNetworksCompilation *compilation)
+{
+  return rua::Anchor::get()->compilation()->free(compilation);
+}
+
+//
+// Execution
+//
+inline int ANeuralNetworksExecution_create(ANeuralNetworksCompilation *compilation,
+                                           ANeuralNetworksExecution **execution)
+{
+  return rua::Anchor::get()->execution()->create(compilation, execution);
+}
+
+inline int ANeuralNetworksExecution_setInput(ANeuralNetworksExecution *execution, int32_t index,
+                                             const ANeuralNetworksOperandType *type,
+                                             const void *buffer, size_t length)
+{
+  return rua::Anchor::get()->execution()->setInput(execution, index, type, buffer, length);
+}
+
+inline int ANeuralNetworksExecution_setInputFromMemory(ANeuralNetworksExecution *execution,
+                                                       int32_t index,
+                                                       const ANeuralNetworksOperandType *type,
+                                                       const ANeuralNetworksMemory *memory,
+                                                       size_t offset, size_t length)
+{
+  return rua::Anchor::get()->execution()->setInputFromMemory(execution, index, type, memory, offset,
+                                                             length);
+}
+
+inline int ANeuralNetworksExecution_setOutput(ANeuralNetworksExecution *execution, int32_t index,
+                                              const ANeuralNetworksOperandType *type, void *buffer,
+                                              size_t length)
+{
+  return rua::Anchor::get()->execution()->setOutput(execution, index, type, buffer, length);
+}
+
+inline int ANeuralNetworksExecution_setOutputFromMemory(ANeuralNetworksExecution *execution,
+                                                        int32_t index,
+                                                        const ANeuralNetworksOperandType *type,
+                                                        const ANeuralNetworksMemory *memory,
+                                                        size_t offset, size_t length)
+{
+  return rua::Anchor::get()->execution()->setOutputFromMemory(execution, index, type, memory,
+                                                              offset, length);
+}
+
+inline int ANeuralNetworksExecution_startCompute(ANeuralNetworksExecution *execution,
+                                                 ANeuralNetworksEvent **event)
+{
+  return rua::Anchor::get()->execution()->startCompute(execution, event);
+}
+
+inline void ANeuralNetworksExecution_free(ANeuralNetworksExecution *execution)
+{
+  return rua::Anchor::get()->execution()->free(execution);
+}
+
+#endif // __NNFW_RUA_SHIM_H__
diff --git a/runtime/libs/tflite/CMakeLists.txt b/runtime/libs/tflite/CMakeLists.txt
new file mode 100644
index 000000000..b5a16bcd9
--- /dev/null
+++ b/runtime/libs/tflite/CMakeLists.txt
@@ -0,0 +1,17 @@
+add_subdirectory(port)
+
+file(GLOB_RECURSE SOURCES "src/*.cpp")
+file(GLOB_RECURSE TESTS "src/*.test.cpp")
+list(REMOVE_ITEM SOURCES ${TESTS})
+
+add_library(nnfw_lib_tflite STATIC ${SOURCES})
+set_target_properties(nnfw_lib_tflite PROPERTIES POSITION_INDEPENDENT_CODE ON)
+target_include_directories(nnfw_lib_tflite PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/include)
+target_link_libraries(nnfw_lib_tflite PUBLIC tensorflow-lite-ex)
+target_link_libraries(nnfw_lib_tflite PUBLIC nnfw_lib_misc)
+target_link_libraries(nnfw_lib_tflite PRIVATE ${LIB_PTHREAD} dl)
+target_link_libraries(nnfw_lib_tflite PRIVATE nnfw_common)
+target_link_libraries(nnfw_lib_tflite PRIVATE nnfw_coverage)
+
+add_executable(nnfw_lib_tflite_test_TensorView src/TensorView.test.cpp)
+target_link_libraries(nnfw_lib_tflite_test_TensorView nnfw_lib_tflite)
diff --git a/runtime/libs/tflite/include/tflite/Assert.h b/runtime/libs/tflite/include/tflite/Assert.h
new file mode 100644
index 000000000..148ac7e01
--- /dev/null
+++ b/runtime/libs/tflite/include/tflite/Assert.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     Assert.h
+ * @brief    This file contains helper function of assertion
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_TFLITE_ASSERT_H__
+#define __NNFW_TFLITE_ASSERT_H__
+
+#include "tensorflow/lite/context.h"
+
+#include <sstream>
+
+#define STR_DETAIL(value) #value
+#define STR(value) STR_DETAIL(value)
+
+#define TFLITE_ENSURE(exp)                                             \
+  {                                                                    \
+    const TfLiteStatus status = (exp);                                 \
+                                                                       \
+    if (status != kTfLiteOk)                                           \
+    {                                                                  \
+      std::ostringstream ss;                                           \
+      ss << #exp << " failed (" << __FILE__ << ":" << __LINE__ << ")"; \
+      throw std::runtime_error{ss.str()};                              \
+    }                                                                  \
+  }
+
+#endif // __NNFW_TFLITE_ASSERT_H__
diff --git a/runtime/libs/tflite/include/tflite/Diff.h b/runtime/libs/tflite/include/tflite/Diff.h
new file mode 100644
index 000000000..eca2fd502
--- /dev/null
+++ b/runtime/libs/tflite/include/tflite/Diff.h
@@ -0,0 +1,201 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     Diff.h
+ * @brief    This file contains classes for testing correctess of implementation
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_TFLITE_DIFF_H__
+#define __NNFW_TFLITE_DIFF_H__
+
+#include "tensorflow/lite/interpreter.h"
+
+#include "misc/tensor/Index.h"
+#include "misc/tensor/Diff.h"
+#include "misc/tensor/Shape.h"
+#include "misc/tensor/Comparator.h"
+
+#include "tflite/TensorView.h"
+
+#include <functional>
+#include <vector>
+
+/**
+ * @brief Class to define TfLite interpreter match application
+ */
+class TfLiteInterpMatchApp
+{
+public:
+  /**
+   * @brief Construct a new TfLiteInterpMatchApp object with Comparator
+   * @param[in] comparator   Comparator object for tensor comparation
+   */
+  TfLiteInterpMatchApp(const nnfw::misc::tensor::Comparator &comparator)
+      : _verbose{false}, _comparator(comparator)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Get reference verbose for debugging information
+   * @return Reference of verbose value
+   */
+  int &verbose(void) { return _verbose; }
+
+private:
+  int _verbose;
+
+public:
+  /**
+   * @brief Run two interpreter and return the output matching
+   * @param[in] pure   Interpreter object of expected(with TfLite)
+   * @param[in] nnapi  Interpreter object of obtained(through NNAPI)
+   * @return  @c true if two Interpreter results are same, otherwise @c false
+   */
+  bool run(::tflite::Interpreter &pure, ::tflite::Interpreter &nnapi) const;
+  /**
+   * @brief Compare two TensorView values and return the match result
+   * @param[in] expected  TensorView object to read expected values
+   * @param[in] obtained  TensorView object to read obtained values
+   * @param[in] id        Tensor ID value used for debug message
+   * @return  @c true if two TensorView values are same, otherwise @c false
+   */
+  template <typename T>
+  bool compareSingleTensorView(const nnfw::tflite::TensorView<T> &expected,
+                               const nnfw::tflite::TensorView<T> &obtained, int id) const;
+
+private:
+  const nnfw::misc::tensor::Comparator &_comparator;
+};
+
+#include "tflite/interp/Builder.h"
+#include "tflite/Quantization.h"
+
+#include <random>
+
+/**
+ * @brief Class to generate random values
+ */
+class RandomGenerator
+{
+public:
+  /**
+   * @brief Construct a new RandomGenerator object
+   * @param[in] seed          Random seed value
+   * @param[in] mean          Mean value of normal random number generation
+   * @param[in] stddev        Standard deviation of random number generation
+   * @param[in] quantization  TfLiteQuantizationParams type to represent quantization value
+   *                          (not used yet)
+   */
+  RandomGenerator(uint32_t seed, float mean, float stddev,
+                  const TfLiteQuantizationParams quantization = make_default_quantization())
+      : _rand{seed}, _dist{mean, stddev}, _quantization{quantization}
+  {
+    (void)_quantization;
+  }
+
+public:
+  /**
+   * @brief  Generate random numbers for type T
+   * @param[in] s Shape value
+   * @param[in] i Index value
+   * @return Random generated value
+   * @note   This is same as T generate(void) as two input parameters are not used
+   */
+  template <typename T>
+  T generate(const ::nnfw::misc::tensor::Shape &, const ::nnfw::misc::tensor::Index &)
+  {
+    return generate<T>();
+  }
+
+  /**
+   * @brief  Generate random numbers for type T
+   * @return Random generated value
+   */
+  template <typename T> T generate(void) { return _dist(_rand); }
+
+private:
+  std::minstd_rand _rand;
+  std::normal_distribution<float> _dist;
+  // unused
+  const TfLiteQuantizationParams _quantization;
+};
+
+template <> uint8_t RandomGenerator::generate<uint8_t>(void);
+template <> bool RandomGenerator::generate<bool>(void);
+
+/**
+ * @brief Structure for NNAPI correctness test
+ */
+struct RandomTestParam
+{
+  int verbose;               //!< Verbosity of debug information
+  int tolerance;             //!< Torlerance of value difference
+  int tensor_logging = 0;    //!< Save logging to a file if not 0
+  std::string log_path = ""; //!< Path of log file, meaningful only when tensor_logging is 1
+};
+
+/**
+ * @brief Class to define Random test runner
+ */
+class RandomTestRunner
+{
+public:
+  /**
+   * @brief Construct a new RandomTestRunner object
+   * @param[in] seed          Random seed value
+   * @param[in] param         RandomTestParam object for test runner
+   * @param[in] quantization  TfLiteQuantizationParams type to represent quantization value
+   */
+  RandomTestRunner(uint32_t seed, const RandomTestParam &param,
+                   const TfLiteQuantizationParams quantization = make_default_quantization())
+      : _randgen{seed, 0.0f, 2.0f, quantization}, _param{param}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief  Run the random test runner
+   * @param[in] builder  Interpreter Builder used to run
+   * @return 0 if test succeeds, otherwise failure
+   */
+  int run(const nnfw::tflite::Builder &builder);
+
+public:
+  /**
+   * @brief  Get RandomGenerator reference
+   * @return RandomGenerator reference
+   */
+  RandomGenerator &generator() { return _randgen; };
+
+private:
+  RandomGenerator _randgen;
+  const RandomTestParam _param;
+
+public:
+  /**
+   * @brief  Create a RandomTestRunner object
+   * @param[in] seed  Random seed value
+   * @return RandomGenerator object
+   */
+  static RandomTestRunner make(uint32_t seed);
+};
+
+#endif // __NNFW_TFLITE_DIFF_H__
diff --git a/runtime/libs/tflite/include/tflite/FeatureView.h b/runtime/libs/tflite/include/tflite/FeatureView.h
new file mode 100644
index 000000000..a8f069c40
--- /dev/null
+++ b/runtime/libs/tflite/include/tflite/FeatureView.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     FeatureView.h
+ * @brief    This file contains FeatureView class
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_TFLITE_FEATURE_VIEW_H__
+#define __NNFW_TFLITE_FEATURE_VIEW_H__
+
+#include "tensorflow/lite/interpreter.h"
+
+#include "tflite/InputIndex.h"
+#include "tflite/OutputIndex.h"
+
+#include "misc/feature/Shape.h"
+#include "misc/feature/Reader.h"
+
+namespace nnfw
+{
+namespace tflite
+{
+
+template <typename T> class FeatureView;
+
+/**
+ * @brief Class to support reading element of float type feature
+ */
+template <> class FeatureView<float> : public nnfw::misc::feature::Reader<float>
+{
+public:
+  /**
+   * @brief     Construct a new FeatureView object
+   * @param[in] interp  Interpreter to read from
+   * @param[in] index   InputIndex index of input
+   */
+  FeatureView(::tflite::Interpreter &interp, const InputIndex &index);
+  /**
+   * @brief     Construct a new FeatureView object
+   * @param[in] interp  Interpreter to read from
+   * @param[in] index   OutputIndex index of output
+   */
+  FeatureView(::tflite::Interpreter &interp, const OutputIndex &index);
+
+public:
+  /**
+   * @brief     Get value of element using channel, row and column index
+   * @param[in] ch    Channel index
+   * @param[in] row   Row index
+   * @param[in] col   Column index
+   * @return    Value of element
+   */
+  float at(uint32_t ch, uint32_t row, uint32_t col) const;
+  /**
+   * @brief     Get reference of element using channel, row and column index
+   * @param[in] ch  Channel index
+   * @param[in] row Row index
+   * @param[in] col Column index
+   * @return    Reference of element
+   */
+  float &at(uint32_t ch, uint32_t row, uint32_t col);
+
+  float at(uint32_t batch, uint32_t ch, uint32_t row, uint32_t col) const = 0;
+
+private:
+  /**
+   * @brief     Get offset of element from channel, row and column index
+   * @param[in] ch  Channel index
+   * @param[in] row Row index
+   * @param[in] col Column index
+   * @return    Offset of element
+   */
+  uint32_t getElementOffset(uint32_t ch, uint32_t row, uint32_t col) const
+  {
+    uint32_t res = 0;
+
+    // TensorFlow Lite assumes that NHWC ordering for tessor
+    res += row * _shape.W * _shape.C;
+    res += col * _shape.C;
+    res += ch;
+
+    return res;
+  }
+
+private:
+  nnfw::misc::feature::Shape _shape;
+  float *_base;
+};
+
+} // namespace tflite
+} // namespace nnfw
+
+#endif // __NNFW_TFLITE_FEATURE_VIEW_H__
diff --git a/runtime/libs/tflite/include/tflite/InputIndex.h b/runtime/libs/tflite/include/tflite/InputIndex.h
new file mode 100644
index 000000000..f535b2626
--- /dev/null
+++ b/runtime/libs/tflite/include/tflite/InputIndex.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     InputIndex.h
+ * @brief    This file contains InputIndex class
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_TFLITE_INPUT_INDEX_H__
+#define __NNFW_TFLITE_INPUT_INDEX_H__
+
+namespace nnfw
+{
+namespace tflite
+{
+
+/**
+ * @brief Class to express index of input
+ */
+class InputIndex
+{
+public:
+  /**
+   * @brief Construct a new InputIndex object with index value
+   * @param [in] index  The value of index
+   */
+  InputIndex(int index) : _index(index)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Get index value as int
+   * @return Index value as int
+   */
+  int asInt(void) const { return _index; }
+
+private:
+  int _index;
+};
+
+} // namespace tflite
+} // namespace nnfw
+
+#endif // __NNFW_TFLITE_INPUT_INDEX_H__
diff --git a/runtime/libs/tflite/include/tflite/InterpreterSession.h b/runtime/libs/tflite/include/tflite/InterpreterSession.h
new file mode 100644
index 000000000..deaf05a7f
--- /dev/null
+++ b/runtime/libs/tflite/include/tflite/InterpreterSession.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     InterpreterSession.h
+ * @brief    This file contains InterpreterSession class
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_TFLITE_INTERPRETER_SESSION_H__
+#define __NNFW_TFLITE_INTERPRETER_SESSION_H__
+
+#include "Session.h"
+
+namespace nnfw
+{
+namespace tflite
+{
+
+/**
+ * @brief Class to define TfLite interpreter session which is inherited from Session class
+ */
+class InterpreterSession final : public Session
+{
+public:
+  /**
+   * @brief Construct a InterpreterSession object with interpreter of TfLite
+   * @param[in] interp The TfLite interpreter pointer
+   */
+  InterpreterSession(::tflite::Interpreter *interp) : _interp{interp}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Get TfLite interpreter pointer
+   * @return The TfLite interpreter
+   */
+  ::tflite::Interpreter *interp(void) override { return _interp; }
+
+public:
+  /**
+   * @brief Prepare the TfLite interpreter session
+   * @return @c true if tensor preparation is successful, otherwise @c false
+   */
+  bool prepare(void) override
+  {
+    _interp->UseNNAPI(false);
+
+    if (kTfLiteOk != _interp->AllocateTensors())
+    {
+      return false;
+    }
+
+    return true;
+  }
+
+  /**
+   * @brief Run the Invoke function of TfLite interpreter
+   * @return @c true if Invoke() is successful, otherwise @c false
+   */
+  bool run(void) override
+  {
+    // Return true if Invoke returns kTfLiteOk
+    return kTfLiteOk == _interp->Invoke();
+  }
+
+  /**
+   * @brief Tear down TfLite interpreter session
+   * @return @c true always
+   */
+  bool teardown(void) override
+  {
+    // Do NOTHING currently
+    return true;
+  }
+
+private:
+  ::tflite::Interpreter *const _interp;
+};
+
+} // namespace tflite
+} // namespace nnfw
+
+#endif // __NNFW_TFLITE_INTERPRETER_SESSION_H__
diff --git a/runtime/libs/tflite/include/tflite/NNAPISession.h b/runtime/libs/tflite/include/tflite/NNAPISession.h
new file mode 100644
index 000000000..f430e86d3
--- /dev/null
+++ b/runtime/libs/tflite/include/tflite/NNAPISession.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     NNAPISession.h
+ * @brief    This file contains NNAPISession class
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_TFLITE_NNAPI_SESSION_H__
+#define __NNFW_TFLITE_NNAPI_SESSION_H__
+
+#include "Session.h"
+#include "tflite/ext/nnapi_delegate.h"
+
+namespace nnfw
+{
+namespace tflite
+{
+
+/**
+ * @brief Class to define NNAPI interpreter session which is inherited from Session class
+ */
+class NNAPISession final : public Session
+{
+public:
+  /**
+   * @brief Construct a NNAPISession object with interpreter of TfLite
+   * @param[in] interp The TfLite interpreter pointer
+   * @note Invoke BuildGraph() of NNAPI delegate from Interpreter
+   */
+  NNAPISession(::tflite::Interpreter *interp) : _interp{interp}
+  {
+    // Construct Graph from Interpreter
+    // primary_subgraph: Experimental interface. Return 1st sugbraph
+    _delegate.BuildGraph(&interp->primary_subgraph());
+  }
+
+public:
+  /**
+   * @brief Get TfLite interpreter pointer
+   * @return The TfLite interpreter
+   */
+  ::tflite::Interpreter *interp(void) override { return _interp; }
+
+public:
+  /**
+   * @brief Prepare the TfLite interpreter session
+   * @return @c true if tensor preparation is successful, otherwise @c false
+   */
+  bool prepare(void) override
+  {
+    // Explicitly turn off T/F lite internal NNAPI delegation in order to use locally defined
+    // NNAPI delegation.
+    _interp->UseNNAPI(false);
+
+    if (kTfLiteOk != _interp->AllocateTensors())
+    {
+      return false;
+    }
+
+    return true;
+  }
+
+  /**
+   * @brief Run the Invoke function of NNAPI delegate
+   * @return @c true if Invoke() is successful, otherwise @c false
+   */
+  bool run(void) override { return kTfLiteOk == _delegate.Invoke(&_interp->primary_subgraph()); }
+
+  /**
+   * @brief Tear down TfLite interpreter session
+   * @return @c true always
+   */
+  bool teardown(void) override
+  {
+    // DO NOTHING
+    return true;
+  }
+
+private:
+  ::tflite::Interpreter *const _interp;
+  nnfw::tflite::NNAPIDelegate _delegate;
+};
+
+} // namespace tflite
+} // namespace nnfw
+
+#endif // __NNFW_TFLITE_NNAPI_SESSION_H__
diff --git a/runtime/libs/tflite/include/tflite/OutputIndex.h b/runtime/libs/tflite/include/tflite/OutputIndex.h
new file mode 100644
index 000000000..dd1ca8d44
--- /dev/null
+++ b/runtime/libs/tflite/include/tflite/OutputIndex.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     OutputIndex.h
+ * @brief    This file contains OutputIndex class
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_TFLITE_OUTPUT_INDEX_H__
+#define __NNFW_TFLITE_OUTPUT_INDEX_H__
+
+namespace nnfw
+{
+namespace tflite
+{
+
+/**
+ * @brief Class to define OutputIndex
+ */
+class OutputIndex
+{
+public:
+  /**
+   * @brief Construct a OutputIndex object with index value
+   * @param[in] index The value of index
+   */
+  OutputIndex(int index) : _index(index)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Get index value as int
+   * @return Index valuel as int
+   */
+  int asInt(void) const { return _index; }
+
+private:
+  int _index;
+};
+
+} // namespace tflite
+} // namespace nnfw
+
+#endif // __NNFW_TFLITE_OUTPUT_INDEX_H__
diff --git a/runtime/libs/tflite/include/tflite/Quantization.h b/runtime/libs/tflite/include/tflite/Quantization.h
new file mode 100644
index 000000000..8272bcdc0
--- /dev/null
+++ b/runtime/libs/tflite/include/tflite/Quantization.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     Quantization.h
+ * @brief    This file contains BitwiseIntToFloat union and quantization related
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_TFLITE_QUANTIZATION_H__
+#define __NNFW_TFLITE_QUANTIZATION_H__
+
+/**
+ * @brief Union to provide bitwise conversion of integer and float
+ */
+union BitwiseIntToFloat {
+  int i;
+  float f;
+};
+
+static const float FLOAT_NEAREST_TO_1 = BitwiseIntToFloat{0x3f7fffff}.f;
+
+#include "tensorflow/lite/context.h"
+
+/**
+ * @brief   Get TfLiteQuantizationParams object with default values
+ * @return  TfLiteQuantizationParams object
+ */
+TfLiteQuantizationParams make_default_quantization(void);
+
+#endif // __NNFW_TFLITE_QUANTIZATION_H__
diff --git a/runtime/libs/tflite/include/tflite/Session.h b/runtime/libs/tflite/include/tflite/Session.h
new file mode 100644
index 000000000..b653acf61
--- /dev/null
+++ b/runtime/libs/tflite/include/tflite/Session.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     Session.h
+ * @brief    This file contains Session class
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_TFLITE_SESSION_H__
+#define __NNFW_TFLITE_SESSION_H__
+
+#include <tensorflow/lite/interpreter.h>
+
+namespace nnfw
+{
+namespace tflite
+{
+
+/**
+ * @brief Structure to provide interface methods of interpreter session
+ */
+struct Session
+{
+  /**
+   * @brief  Destruct Session object using default destructor
+   */
+  virtual ~Session() = default;
+
+  /**
+   * @brief   Get the Interpreter object pointer
+   * @return  The Interpreter object pointer
+   */
+  virtual ::tflite::Interpreter *interp(void) = 0;
+
+  /**
+   * @brief   Prepare the session
+   * @return  @c true if prepare method succeeded, otherwise @c false
+   */
+  virtual bool prepare(void) = 0;
+  /**
+   * @brief   Run the session
+   * @return  @c true if run method succeeded, otherwise @c false
+   */
+  virtual bool run(void) = 0;
+  /**
+   * @brief   Teardown(release) the session
+   * @return  @c true if teardown method succeeded, otherwise @c false
+   */
+  virtual bool teardown(void) = 0;
+};
+
+} // namespace tflite
+} // namespace nnfw
+
+#endif // __NNFW_TFLITE_INTERP_SESSION_H__
diff --git a/runtime/libs/tflite/include/tflite/TensorLogger.h b/runtime/libs/tflite/include/tflite/TensorLogger.h
new file mode 100644
index 000000000..a824c3411
--- /dev/null
+++ b/runtime/libs/tflite/include/tflite/TensorLogger.h
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     TensorLogger.h
+ * @brief    This file contains TensorLogger class
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_TFLITE_TENSOR_LOGGER_H__
+#define __NNFW_TFLITE_TENSOR_LOGGER_H__
+
+#include "misc/tensor/IndexIterator.h"
+#include "tflite/TensorView.h"
+
+#include <tensorflow/lite/interpreter.h>
+#include <tensorflow/lite/context.h>
+#include <fstream>
+#include <iomanip>
+
+namespace nnfw
+{
+namespace tflite
+{
+
+/**
+ * @brief Class to write input and output value / shape into a file in python form
+ * @note This is a utility to write input and output value / shape into a file in python form.\n
+ *       any python app can load this value by running the python code below:\n
+ *       exec(open(filename).read())\n
+ *       generated python code looks like the following: \n
+ *       tensor_shape_gen = []\n
+ *       tensor_value_gen = []\n\n
+ *       tensor_shape_gen.append("{2, 1, 2}")\n
+ *       tensor_value_gen.append([1, 2, 3, 4])\n\n
+ *       tensor_shape_gen.append("{2}")\n
+ *       tensor_value_gen.append([1, 2])\n\n
+ *       tensor_shape_gen.append("{2, 1, 2}")\n
+ *       tensor_value_gen.append([1, 4, 3, 8])\n
+ */
+class TensorLogger
+{
+private:
+  std::ofstream _outfile;
+
+public:
+  /**
+   * @brief Get TensorLogger instance
+   * @return The TensorLogger instance
+   */
+  static TensorLogger &get()
+  {
+    static TensorLogger instance;
+    return instance;
+  }
+
+  /**
+   * @brief Save the tensor details to file from interpreter
+   * @param[in] path The file path to save
+   * @param[in] interp The TfLite interpreter
+   */
+  void save(const std::string &path, ::tflite::Interpreter &interp)
+  {
+    open(path);
+
+    int log_index = 0;
+    for (const auto id : interp.inputs())
+    {
+      _outfile << "# input tensors" << std::endl;
+      printTensor(interp, id, log_index++);
+    }
+    for (const auto id : interp.outputs())
+    {
+      _outfile << "# output tensors" << std::endl;
+      printTensor(interp, id, log_index++);
+    }
+    close();
+  }
+
+private:
+  void open(const std::string &path)
+  {
+    if (!_outfile.is_open())
+      _outfile.open(path, std::ios_base::out);
+
+    _outfile << "# ------ file: " << path << " ------" << std::endl
+             << "tensor_shape_gen = []" << std::endl
+             << "tensor_value_gen = []" << std::endl
+             << std::endl;
+  }
+
+  void printTensor(::tflite::Interpreter &interp, const int id, const int log_index)
+  {
+    const TfLiteTensor *tensor = interp.tensor(id);
+
+    _outfile << "# tensor name: " << tensor->name << std::endl;
+    _outfile << "# tflite::interpreter.tensor(" << id << ") -> "
+                                                         "tensor_value_gen["
+             << log_index << "]" << std::endl;
+
+    if (tensor->type == kTfLiteInt32)
+    {
+      printTensorShape(tensor);
+      printTensorValue<int32_t>(tensor, tensor->data.i32);
+    }
+    else if (interp.tensor(id)->type == kTfLiteUInt8)
+    {
+      printTensorShape(tensor);
+      printTensorValue<uint8_t>(tensor, tensor->data.uint8);
+    }
+    else if (tensor->type == kTfLiteFloat32)
+    {
+      printTensorShape(tensor);
+      printTensorValue<float>(tensor, tensor->data.f);
+    }
+  }
+
+  void printTensorShape(const TfLiteTensor *tensor)
+  {
+    _outfile << "tensor_shape_gen.append('{";
+
+    int r = 0;
+    for (; r < tensor->dims->size - 1; r++)
+    {
+      _outfile << tensor->dims->data[r] << ", ";
+    }
+    _outfile << tensor->dims->data[r];
+
+    _outfile << "}')" << std::endl;
+  }
+
+  template <typename T> void printTensorValue(const TfLiteTensor *tensor, T *tensor_data_ptr)
+  {
+    _outfile << "tensor_value_gen.append([";
+
+    _outfile << std::fixed << std::setprecision(10);
+
+    const T *end = reinterpret_cast<const T *>(tensor->data.raw_const + tensor->bytes);
+    for (T *ptr = tensor_data_ptr; ptr < end; ptr++)
+      _outfile << *ptr << ", ";
+
+    _outfile << "])" << std::endl << std::endl;
+  }
+
+  void close()
+  {
+    _outfile << "# --------- tensor shape and value defined above ---------" << std::endl;
+    _outfile.close();
+  }
+};
+
+} // namespace tflite
+} // namespace nnfw
+
+#endif // __NNFW_TFLITE_TENSOR_LOGGER_H__
diff --git a/runtime/libs/tflite/include/tflite/TensorShapeUtils.h b/runtime/libs/tflite/include/tflite/TensorShapeUtils.h
new file mode 100644
index 000000000..ba8687413
--- /dev/null
+++ b/runtime/libs/tflite/include/tflite/TensorShapeUtils.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     TensorShapeUtils.h
+ * @brief    This file contains utilities function of tensor shape
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_TFLITE_TENSOR_SHAPE_UTILS_H__
+#define __NNFW_TFLITE_TENSOR_SHAPE_UTILS_H__
+
+#include "misc/tensor/Shape.h"
+
+#include <vector>
+
+namespace nnfw
+{
+namespace tflite
+{
+
+/**
+ * @brief Converts tensor::Shape into a vector
+ * @param[in] shape The tensor shape to be converted
+ * @return vector value of given shape object
+ */
+static inline std::vector<int32_t> as_dims(const nnfw::misc::tensor::Shape &shape)
+{
+  std::vector<int32_t> dims;
+
+  for (uint32_t axis = 0; axis < shape.rank(); ++axis)
+  {
+    dims.emplace_back(shape.dim(axis));
+  }
+
+  return dims;
+}
+
+/**
+ * @brief Broadcasts between two given shapes
+ * @param[in] lhs_shape The left hand side shape
+ * @param[in] rhs_shape The right hand side shape
+ * @return The broadcasted shape
+ */
+nnfw::misc::tensor::Shape broadcast(const nnfw::misc::tensor::Shape &lhs_shape,
+                                    const nnfw::misc::tensor::Shape &rhs_shape);
+
+} // namespace tflite
+} // namespace nnfw
+
+#endif // __NNFW_TFLITE_TENSOR_SHAPE_UTILS_H__
diff --git a/runtime/libs/tflite/include/tflite/TensorUtils.h b/runtime/libs/tflite/include/tflite/TensorUtils.h
new file mode 100644
index 000000000..08af1468b
--- /dev/null
+++ b/runtime/libs/tflite/include/tflite/TensorUtils.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file    TensorUtils.h
+ * @brief   This file contains utilities function
+ * @ingroup COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_TFLITE_TENSOR_UTILS_H__
+#define __NNFW_TFLITE_TENSOR_UTILS_H__
+
+#include <tensorflow/lite/context.h>
+
+namespace nnfw
+{
+namespace tflite
+{
+
+/**
+ * @brief Get @c true if tensor type is kTfLiteFloat32, otherwise @c false
+ * @param[in] tensor The tensor object to be compared
+ * @return @c true if tensor type is kTfLiteFloat32, otherwise @c false
+ */
+inline bool isFloatTensor(const TfLiteTensor *tensor) { return tensor->type == kTfLiteFloat32; }
+
+/**
+ * @brief Get @c true if tensor is 4-D tensor and the first dimension length is 1,
+ *        otherwise @c false
+ * @param[in] tensor The tensor object to be compared
+ * @return @c true if tensor is 4-D tensor and the first dimension length is 1, otherwise @c false
+ */
+inline bool isFeatureTensor(const TfLiteTensor *tensor)
+{
+  return (tensor->dims->size == 4) && (tensor->dims->data[0] == 1);
+}
+
+} // namespace tflite
+} // namespace nnfw
+
+#endif // __NNFW_TFLITE_TENSOR_UTILS_H__
diff --git a/runtime/libs/tflite/include/tflite/TensorView.h b/runtime/libs/tflite/include/tflite/TensorView.h
new file mode 100644
index 000000000..ce791a73f
--- /dev/null
+++ b/runtime/libs/tflite/include/tflite/TensorView.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     TensorView.h
+ * @brief    This file contains TensorView class
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_TFLITE_TENSOR_VIEW_H__
+#define __NNFW_TFLITE_TENSOR_VIEW_H__
+
+#include "tensorflow/lite/interpreter.h"
+
+#include "misc/tensor/Shape.h"
+#include "misc/tensor/Index.h"
+#include "misc/tensor/Reader.h"
+#include "misc/tensor/NonIncreasingStride.h"
+
+namespace nnfw
+{
+namespace tflite
+{
+
+/**
+ * @brief Class to define TensorView which is inherited from nnfw::misc::tensor::Reader<T> class
+ */
+template <typename T> class TensorView final : public nnfw::misc::tensor::Reader<T>
+{
+public:
+  /**
+   * @brief Construct a TensorView object with base and shape informations
+   * @param[in] shape The shape of a tensor
+   * @param[in] base The base address of a tensor
+   */
+  TensorView(const nnfw::misc::tensor::Shape &shape, T *base) : _shape{shape}, _base{base}
+  {
+    // Set 'stride'
+    _stride.init(_shape);
+  }
+
+public:
+  /**
+   * @brief Get shape of tensor
+   * @return Reference of shape
+   */
+  const nnfw::misc::tensor::Shape &shape(void) const { return _shape; }
+
+public:
+  /**
+   * @brief Get value of tensor index
+   * @param[in] index The tensor index
+   * @return The value at the index
+   */
+  T at(const nnfw::misc::tensor::Index &index) const override
+  {
+    const auto offset = _stride.offset(index);
+    return *(_base + offset);
+  }
+
+public:
+  /**
+   * @brief Get reference value of tensor index
+   * @param[in] index The tensor index
+   * @return The reference value at the index
+   */
+  T &at(const nnfw::misc::tensor::Index &index)
+  {
+    const auto offset = _stride.offset(index);
+    return *(_base + offset);
+  }
+
+private:
+  nnfw::misc::tensor::Shape _shape; /**< The tensor shape */
+
+public:
+  T *_base;                                        /**< The base address of tensor */
+  nnfw::misc::tensor::NonIncreasingStride _stride; /**< The NonIncreasingStride object */
+
+public:
+  // TODO Introduce Operand ID class
+  /**
+   * @brief Create TensorView object using given parameters
+   * @param[in] interp The TfLite interpreter
+   * @param[in] tensor_index The tensor index
+   * @return The new TensorView<T> object
+   */
+  static TensorView<T> make(::tflite::Interpreter &interp, int tensor_index)
+  {
+    auto tensor_ptr = interp.tensor(tensor_index);
+
+    // Set 'shape'
+    nnfw::misc::tensor::Shape shape(tensor_ptr->dims->size);
+
+    for (uint32_t axis = 0; axis < shape.rank(); ++axis)
+    {
+      shape.dim(axis) = tensor_ptr->dims->data[axis];
+    }
+
+    return TensorView<T>(shape, interp.typed_tensor<T>(tensor_index));
+  }
+};
+
+} // namespace tflite
+} // namespace nnfw
+
+#endif // __NNFW_TFLITE_TENSOR_VIEW_H__
diff --git a/runtime/libs/tflite/include/tflite/interp/Builder.h b/runtime/libs/tflite/include/tflite/interp/Builder.h
new file mode 100644
index 000000000..0f54e1779
--- /dev/null
+++ b/runtime/libs/tflite/include/tflite/interp/Builder.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     Builder.h
+ * @brief    This file contains Builder structure
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_TFLITE_INTERP_BUILDER_H__
+#define __NNFW_TFLITE_INTERP_BUILDER_H__
+
+#include <tensorflow/lite/interpreter.h>
+
+namespace nnfw
+{
+namespace tflite
+{
+
+/**
+ * @brief Structure to Builder
+ */
+struct Builder
+{
+  /**
+   * @brief Destroy the Builder object
+   */
+  virtual ~Builder() = default;
+
+  /**
+   * @brief Build a FlatBuffer model
+   * @return The TfLite interpreter object
+   */
+  virtual std::unique_ptr<::tflite::Interpreter> build(void) const = 0;
+};
+
+} // namespace tflite
+} // namespace nnfw
+
+#endif // __NNFW_TFLITE_INTERP_BUILDER_H__
diff --git a/runtime/libs/tflite/include/tflite/interp/FlatBufferBuilder.h b/runtime/libs/tflite/include/tflite/interp/FlatBufferBuilder.h
new file mode 100644
index 000000000..2d96af50b
--- /dev/null
+++ b/runtime/libs/tflite/include/tflite/interp/FlatBufferBuilder.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     FlatBufferBuilder.h
+ * @brief    This file contains FlatBufferBuilder class
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_TFLITE_INTERP_FLAT_BUFFER_BUILDER_H__
+#define __NNFW_TFLITE_INTERP_FLAT_BUFFER_BUILDER_H__
+
+#include <tensorflow/lite/model.h>
+
+#include "tflite/interp/Builder.h"
+
+namespace nnfw
+{
+namespace tflite
+{
+
+/**
+ * @brief Class to define FlatBufferBuilder which is inherited from Builder
+ */
+class FlatBufferBuilder final : public Builder
+{
+public:
+  /**
+   * @brief Construct a FlatBufferBuilder object with FlatBufferModel of TfLite
+   * @param[in] model The TfLite Flatbuffer model
+   */
+  FlatBufferBuilder(const ::tflite::FlatBufferModel &model) : _model{model}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Build a FlatBuffer model
+   * @return The TfLite interpreter pointer address
+   */
+  std::unique_ptr<::tflite::Interpreter> build(void) const override;
+
+private:
+  const ::tflite::FlatBufferModel &_model;
+};
+
+} // namespace tflite
+} // namespace nnfw
+
+#endif // __NNFW_TFLITE_INTERP_FLAT_BUFFER_BUILDER_H__
diff --git a/runtime/libs/tflite/include/tflite/interp/FunctionBuilder.h b/runtime/libs/tflite/include/tflite/interp/FunctionBuilder.h
new file mode 100644
index 000000000..7bfb8db2d
--- /dev/null
+++ b/runtime/libs/tflite/include/tflite/interp/FunctionBuilder.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     FunctionBuilder.h
+ * @brief    This file contains FunctionBuilder class
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_TFLITE_INTERP_FUNCTION_BUILDER_H__
+#define __NNFW_TFLITE_INTERP_FUNCTION_BUILDER_H__
+
+#include <tensorflow/lite/model.h>
+
+#include "tflite/interp/Builder.h"
+
+namespace nnfw
+{
+namespace tflite
+{
+
+/**
+ * @brief Class to define FunctionBuilder which is inherited from Builder
+ */
+class FunctionBuilder final : public Builder
+{
+public:
+  using SetupFunc = std::function<void(::tflite::Interpreter &)>;
+
+public:
+  /**
+   * @brief Construct a FunctionBuilder object with SetupFunction
+   * @param[in] fn The SetupFunc object
+   */
+  FunctionBuilder(const SetupFunc &fn) : _fn{fn}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Build a SetupFunc
+   * @return The TfLite interpreter pointer address
+   */
+  std::unique_ptr<::tflite::Interpreter> build(void) const override;
+
+private:
+  SetupFunc _fn;
+};
+
+} // namespace tflite
+} // namespace nnfw
+
+#endif // __NNFW_TFLITE_INTERP_FUNCTION_BUILDER_H__
diff --git a/runtime/libs/tflite/port/1.13.1/CMakeLists.txt b/runtime/libs/tflite/port/1.13.1/CMakeLists.txt
new file mode 100644
index 000000000..311e11cae
--- /dev/null
+++ b/runtime/libs/tflite/port/1.13.1/CMakeLists.txt
@@ -0,0 +1,16 @@
+if(NOT SUPPORT_TFLITE_VERSION VERSION_EQUAL 1.13.1)
+  return()
+endif(NOT SUPPORT_TFLITE_VERSION VERSION_EQUAL 1.13.1)
+
+nnfw_find_package(TensorFlowLite REQUIRED)
+
+file(GLOB_RECURSE SOURCES "src/*.cpp")
+
+add_library(tensorflow-lite-ex STATIC ${SOURCES})
+set_target_properties(tensorflow-lite-ex PROPERTIES POSITION_INDEPENDENT_CODE ON)
+target_include_directories(tensorflow-lite-ex PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/include)
+target_link_libraries(tensorflow-lite-ex PUBLIC tensorflow-lite)
+target_link_libraries(tensorflow-lite-ex PUBLIC nnfw_lib_misc nnfw_lib_rua_shim)
+target_link_libraries(tensorflow-lite-ex PRIVATE ${LIB_PTHREAD} dl)
+target_link_libraries(tensorflow-lite-ex PRIVATE nnfw_common)
+target_link_libraries(tensorflow-lite-ex PRIVATE nnfw_coverage)
diff --git a/runtime/libs/tflite/port/1.13.1/include/tflite/ext/kernels/Abs.h b/runtime/libs/tflite/port/1.13.1/include/tflite/ext/kernels/Abs.h
new file mode 100644
index 000000000..697ba33e9
--- /dev/null
+++ b/runtime/libs/tflite/port/1.13.1/include/tflite/ext/kernels/Abs.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NNFW_TFLITE_EXT_KERNELS_ABS_H__
+#define __NNFW_TFLITE_EXT_KERNELS_ABS_H__
+
+#include "tensorflow/lite/context.h"
+
+namespace nnfw
+{
+namespace tflite
+{
+namespace custom
+{
+namespace Abs
+{
+
+void *InitAbs(TfLiteContext *context, const char *buffer, size_t length);
+void FreeAbs(TfLiteContext *context, void *buffer);
+TfLiteStatus PrepareAbs(TfLiteContext *context, TfLiteNode *node);
+TfLiteStatus EvalAbs(TfLiteContext *context, TfLiteNode *node);
+
+} // namespace Abs
+} // namespace custom
+} // namespace tflite
+} // namespace nnfw
+
+#endif // __NNFW_TFLITE_EXT_KERNELS_ABS_H__
diff --git a/runtime/libs/tflite/port/1.13.1/include/tflite/ext/kernels/CustomOps.h b/runtime/libs/tflite/port/1.13.1/include/tflite/ext/kernels/CustomOps.h
new file mode 100644
index 000000000..3370db778
--- /dev/null
+++ b/runtime/libs/tflite/port/1.13.1/include/tflite/ext/kernels/CustomOps.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     CustomOps.h
+ * @brief    This file contains registration of custom operands
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_TFLITE_EXT_KERNELS_CUSTOM_OP_H__
+#define __NNFW_TFLITE_EXT_KERNELS_CUSTOM_OP_H__
+
+#include "tensorflow/lite/context.h"
+#include "tflite/ext/kernels/TensorFlowMax.h"
+#include "tflite/ext/kernels/SquaredDifference.h"
+#include "tflite/ext/kernels/TensorFlowSum.h"
+#include "tflite/ext/kernels/Abs.h"
+
+namespace nnfw
+{
+namespace tflite
+{
+namespace custom
+{
+
+#define REGISTER_FUNCTION(Name)             \
+  TfLiteRegistration *Register_##Name(void) \
+  {                                         \
+    static TfLiteRegistration r = {};       \
+    r.init = Name::Init##Name;              \
+    r.free = Name::Free##Name;              \
+    r.prepare = Name::Prepare##Name;        \
+    r.invoke = Name::Eval##Name;            \
+    r.custom_name = #Name;                  \
+    return &r;                              \
+  }
+
+REGISTER_FUNCTION(TensorFlowMax)
+REGISTER_FUNCTION(SquaredDifference)
+REGISTER_FUNCTION(TensorFlowSum)
+REGISTER_FUNCTION(Abs)
+
+#undef REGISTER_FUNCTION
+
+} // namespace custom
+} // namespace tflite
+} // namespace nnfw
+
+#endif // __NNFW_TFLITE_EXT_KERNELS_CUSTOM_OP_H__
diff --git a/runtime/libs/tflite/port/1.13.1/include/tflite/ext/kernels/SquaredDifference.h b/runtime/libs/tflite/port/1.13.1/include/tflite/ext/kernels/SquaredDifference.h
new file mode 100644
index 000000000..5512ead78
--- /dev/null
+++ b/runtime/libs/tflite/port/1.13.1/include/tflite/ext/kernels/SquaredDifference.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     SquaredDifference.h
+ * @brief    This file contains SquaredDifference namespace and SquaredDifference function
+ *           definitions
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_TFLITE_EXT_KERNELS_SQUARED_DIFFERENCE_H__
+#define __NNFW_TFLITE_EXT_KERNELS_SQUARED_DIFFERENCE_H__
+
+#include "tensorflow/lite/context.h"
+
+namespace nnfw
+{
+namespace tflite
+{
+namespace custom
+{
+namespace SquaredDifference
+{
+
+/**
+ * @brief Initialize SquaredDifference operand using the contents of buffer
+ * @param[in] context The TfLite context
+ * @param[in] buffer The buffer with contents
+ * @param[in] length The buffer length
+ * @return The void pointer for user data
+ */
+void *InitSquaredDifference(TfLiteContext *context, const char *buffer, size_t length);
+
+/**
+ * @brief Release any memory it might have allocated via 'InitSquaredDifference'
+ * @param[in] context The TfLite context
+ * @param[in] buffer The buffer with contents
+ * @return N/A
+ */
+void FreeSquaredDifference(TfLiteContext *context, void *buffer);
+
+/**
+ * @brief Prepare the SquaredDifference operand for execution
+ * @param[in] context The TfLite context
+ * @param[in] node The operand node
+ * @return The TfLite status
+ */
+TfLiteStatus PrepareSquaredDifference(TfLiteContext *context, TfLiteNode *node);
+
+/**
+ * @brief Evaluation the SquaredDifference operand for execution
+ * @param[in] context The TfLite context
+ * @param[in] node The operand node
+ * @return The TfLite status
+ */
+TfLiteStatus EvalSquaredDifference(TfLiteContext *context, TfLiteNode *node);
+
+} // namespace SquaredDifference
+} // namespace custom
+} // namespace tflite
+} // namespace nnfw
+
+#endif // __NNFW_TFLITE_EXT_KERNELS_SQUARED_DIFFERENCE_H__
diff --git a/runtime/libs/tflite/port/1.13.1/include/tflite/ext/kernels/TensorFlowMax.h b/runtime/libs/tflite/port/1.13.1/include/tflite/ext/kernels/TensorFlowMax.h
new file mode 100644
index 000000000..d573308ed
--- /dev/null
+++ b/runtime/libs/tflite/port/1.13.1/include/tflite/ext/kernels/TensorFlowMax.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     TensorFlowMax.h
+ * @brief    This file contains TensorFlowMax namespace and TensorFlowMax function definitions
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NNFW_TFLITE_EXT_KERNELS_TENSORFLOW_MAX_H__
+#define __NNFW_TFLITE_EXT_KERNELS_TENSORFLOW_MAX_H__
+
+#include "tensorflow/lite/context.h"
+
+namespace nnfw
+{
+namespace tflite
+{
+namespace custom
+{
+namespace TensorFlowMax
+{
+
+/**
+ * @brief Initialize TensorFlowMax operand using the contents of buffer
+ * @param[in] context The TfLite context
+ * @param[in] buffer The buffer with contents
+ * @param[in] length The buffer length
+ * @return The void pointer for user data
+ */
+void *InitTensorFlowMax(TfLiteContext *context, const char *buffer, size_t length);
+
+/**
+ * @brief Release any memory it might have allocated via 'InitTensorFlowMax'
+ * @param[in] context The TfLite context
+ * @param[in] buffer The buffer with contents
+ * @return N/A
+ */
+void FreeTensorFlowMax(TfLiteContext *context, void *buffer);
+
+/**
+ * @brief Prepare the TensorFlowMax operand for execution
+ * @param[in] context The TfLite context
+ * @param[in] node The operand node
+ * @return The TfLite status
+ */
+TfLiteStatus PrepareTensorFlowMax(TfLiteContext *context, TfLiteNode *node);
+
+/**
+ * @brief Evaluation the TensorFlowMax operand for execution
+ * @param[in] context The TfLite context
+ * @param[in] node The operand node
+ * @return The TfLite status
+ */
+TfLiteStatus EvalTensorFlowMax(TfLiteContext *context, TfLiteNode *node);
+
+} // namespace TensorFlowMax
+} // namespace custom
+} // namespace tflite
+} // namespace nnfw
+
+#endif // __NNFW_TFLITE_EXT_KERNELS_TENSORFLOW_MAX_H__
diff --git a/runtime/libs/tflite/port/1.13.1/include/tflite/ext/kernels/TensorFlowSum.h b/runtime/libs/tflite/port/1.13.1/include/tflite/ext/kernels/TensorFlowSum.h
new file mode 100644
index 000000000..29455aac5
--- /dev/null
+++ b/runtime/libs/tflite/port/1.13.1/include/tflite/ext/kernels/TensorFlowSum.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NNFW_TFLITE_EXT_KERNELS_TENSORFLOW_SUM_H__
+#define __NNFW_TFLITE_EXT_KERNELS_TENSORFLOW_SUM_H__
+
+#include "tensorflow/lite/context.h"
+
+namespace nnfw
+{
+namespace tflite
+{
+namespace custom
+{
+namespace TensorFlowSum
+{
+
+void *InitTensorFlowSum(TfLiteContext *context, const char *buffer, size_t length);
+void FreeTensorFlowSum(TfLiteContext *context, void *buffer);
+TfLiteStatus PrepareTensorFlowSum(TfLiteContext *context, TfLiteNode *node);
+TfLiteStatus EvalTensorFlowSum(TfLiteContext *context, TfLiteNode *node);
+
+} // namespace TensorFlowSum
+} // namespace custom
+} // namespace tflite
+} // namespace nnfw
+
+#endif // __NNFW_TFLITE_EXT_KERNELS_TENSORFLOW_SUM_H__
diff --git a/runtime/libs/tflite/port/1.13.1/include/tflite/ext/kernels/register.h b/runtime/libs/tflite/port/1.13.1/include/tflite/ext/kernels/register.h
new file mode 100644
index 000000000..6e32b35fb
--- /dev/null
+++ b/runtime/libs/tflite/port/1.13.1/include/tflite/ext/kernels/register.h
@@ -0,0 +1,46 @@
+/* Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+   Copyright 2017 The TensorFlow Authors. All Rights Reserved.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+==============================================================================*/
+
+// NOTE To minimize diff with upstream tensorflow, disable clang-format
+// clang-format off
+
+// NOTE This header is derived from the following file (in TensorFlow v1.13.1)
+//        'externals/tensorflow/tensorflow/lite/kernels/register.h'
+#ifndef __NNFW_TFLITE_EXT_KERNELS_REGISTER_H__
+#define __NNFW_TFLITE_EXT_KERNELS_REGISTER_H__
+
+#include <unordered_map>
+#include "tensorflow/lite/context.h"
+#include "tensorflow/lite/model.h"
+
+namespace nnfw {
+namespace tflite {
+
+class BuiltinOpResolver : public ::tflite::MutableOpResolver {
+ public:
+  BuiltinOpResolver();
+
+  const TfLiteRegistration* FindOp(::tflite::BuiltinOperator op,
+                                   int version) const override;
+  const TfLiteRegistration* FindOp(const char* op, int version) const override;
+};
+
+}  // namespace tflite
+}  // namespace nnfw
+
+#endif // __NNFW_TFLITE_EXT_KERNELS_REGISTER_H__
+
+// clang-format on
diff --git a/runtime/libs/tflite/port/1.13.1/include/tflite/ext/nnapi_delegate.h b/runtime/libs/tflite/port/1.13.1/include/tflite/ext/nnapi_delegate.h
new file mode 100644
index 000000000..231baa25c
--- /dev/null
+++ b/runtime/libs/tflite/port/1.13.1/include/tflite/ext/nnapi_delegate.h
@@ -0,0 +1,92 @@
+/* Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+   Copyright 2017 The TensorFlow Authors. All Rights Reserved.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+==============================================================================*/
+
+// NOTE To minimize diff with upstream tensorflow, disable clang-format
+// clang-format off
+
+// NOTE This header is derived from the following file (in TensorFlow v1.13.1)
+//        'externals/tensorflow/tensorflow/lite/nnapi_delegate.h'
+#ifndef __NNFW_TFLITE_EXT_NNAPI_DELEGATE_H__
+#define __NNFW_TFLITE_EXT_NNAPI_DELEGATE_H__
+
+#include "tensorflow/lite/allocation.h"
+#include "tensorflow/lite/c/c_api_internal.h"
+#include "tensorflow/lite/core/api/error_reporter.h"
+#include "tensorflow/lite/core/subgraph.h"
+#include "tensorflow/lite/interpreter.h"
+
+struct ANeuralNetworksModel;
+struct ANeuralNetworksMemory;
+struct ANeuralNetworksCompilation;
+
+namespace nnfw {
+namespace tflite {
+
+class NNAPIAllocation : public ::tflite::MMAPAllocation {
+ public:
+  NNAPIAllocation(const char* filename, ::tflite::ErrorReporter* error_reporter);
+  ~NNAPIAllocation();
+
+  size_t offset(const void* ptr) const {
+    auto signed_offset = reinterpret_cast<const uint8_t*>(ptr) -
+                         reinterpret_cast<const uint8_t*>(mmapped_buffer_);
+
+    return static_cast<size_t>(signed_offset);
+  }
+
+  ANeuralNetworksMemory* memory() const { return handle_; }
+  bool valid() const override { return handle_ != nullptr; }
+
+ private:
+  mutable ANeuralNetworksMemory* handle_ = nullptr;
+};
+
+class NNAPIDelegate {
+ public:
+  ~NNAPIDelegate();
+
+  // Convert a tflite graph to NNAPI
+  TfLiteStatus BuildGraph(::tflite::Subgraph* subgraph);
+
+  // Run
+  TfLiteStatus Invoke(::tflite::Subgraph* subgraph);
+
+  // Whether the current platform supports NNAPI delegation.
+  static bool IsSupported();
+
+ private:
+  // The NN API model handle
+  ANeuralNetworksModel* nn_model_ = nullptr;
+  // The NN API compilation handle
+  ANeuralNetworksCompilation* nn_compiled_model_ = nullptr;
+  // Model status
+  TfLiteStatus model_status_ = kTfLiteOk;
+
+  // List of state tensors for LSTM, RNN, SVDF.
+  // NN API does not allow ops to maintain states across multiple
+  // invocations. We need to manually create state input tensors from
+  // corresponding state output tensors of TFLite operations, and map them
+  // correctly.
+  std::vector<int> model_states_inputs_;   // holds NNAPI operand ids
+  std::vector<int> model_states_outputs_;  // holds TFLite tensor ids
+};
+
+} // namespace tflite
+} // namespace nnfw
+
+#endif  // __NNFW_TFLITE_EXT_NNAPI_DELEGATE_H__
+
+// clang-format on
diff --git a/runtime/libs/tflite/port/1.13.1/src/kernels/Abs.cpp b/runtime/libs/tflite/port/1.13.1/src/kernels/Abs.cpp
new file mode 100644
index 000000000..61181465d
--- /dev/null
+++ b/runtime/libs/tflite/port/1.13.1/src/kernels/Abs.cpp
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "tflite/ext/kernels/Abs.h"
+#include "tensorflow/lite/kernels/kernel_util.h"
+
+#include <iostream>
+#include <cmath>
+
+namespace nnfw
+{
+namespace tflite
+{
+namespace custom
+{
+namespace Abs
+{
+
+void *InitAbs(TfLiteContext *, const char *, size_t) { return nullptr; }
+
+void FreeAbs(TfLiteContext *, void *) {}
+
+TfLiteStatus PrepareAbs(TfLiteContext *context, TfLiteNode *node)
+{
+  TF_LITE_ENSURE_EQ(context, ::tflite::NumInputs(node), 1);
+  TF_LITE_ENSURE_EQ(context, ::tflite::NumOutputs(node), 1);
+
+  const TfLiteTensor *input = ::tflite::GetInput(context, node, 0);
+  TfLiteTensor *output = ::tflite::GetOutput(context, node, 0);
+
+  TF_LITE_ENSURE_EQ(context, input->type, output->type);
+
+  return context->ResizeTensor(context, output, TfLiteIntArrayCopy(input->dims));
+}
+
+TfLiteStatus EvalAbs(TfLiteContext *context, TfLiteNode *node)
+{
+  const TfLiteTensor *input = ::tflite::GetInput(context, node, 0);
+  TfLiteTensor *output = ::tflite::GetOutput(context, node, 0);
+  size_t elements = ::tflite::NumElements(input);
+  switch (input->type)
+  {
+    case kTfLiteFloat32:
+    {
+      auto *in = input->data.f;
+      auto *in_end = in + elements;
+      auto *out = output->data.f;
+      for (; in < in_end; in++, out++)
+        *out = std::abs(*in);
+      return kTfLiteOk;
+    }
+    case kTfLiteInt32:
+    {
+      auto *in = input->data.i32;
+      auto *in_end = in + elements;
+      auto *out = output->data.i32;
+      for (; in < in_end; in++, out++)
+        *out = std::abs(*in);
+      return kTfLiteOk;
+    }
+    case kTfLiteInt64:
+    {
+      auto *in = input->data.i64;
+      auto *in_end = in + elements;
+      auto *out = output->data.i64;
+      for (; in < in_end; in++, out++)
+        *out = std::abs(*in);
+      return kTfLiteOk;
+    }
+    case kTfLiteUInt8:
+    {
+      auto *in = input->data.uint8;
+      auto *in_end = in + elements;
+      auto *out = output->data.uint8;
+      for (; in < in_end; in++, out++)
+        *out = *in;
+      return kTfLiteOk;
+    }
+    default:
+    {
+      context->ReportError(context, "Input type %d is not supported", input->type);
+      return kTfLiteError;
+    }
+  }
+}
+
+} // namespace Abs
+} // namespace custom
+} // namespace tflite
+} // namespace nnfw
diff --git a/runtime/libs/tflite/port/1.13.1/src/kernels/SquaredDifference.cpp b/runtime/libs/tflite/port/1.13.1/src/kernels/SquaredDifference.cpp
new file mode 100644
index 000000000..615878513
--- /dev/null
+++ b/runtime/libs/tflite/port/1.13.1/src/kernels/SquaredDifference.cpp
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "tflite/ext/kernels/SquaredDifference.h"
+#include "tensorflow/lite/kernels/kernel_util.h"
+
+#include <iostream>
+
+namespace nnfw
+{
+namespace tflite
+{
+namespace custom
+{
+namespace SquaredDifference
+{
+
+void *InitSquaredDifference(TfLiteContext *, const char *, size_t) { return nullptr; }
+
+void FreeSquaredDifference(TfLiteContext *, void *) {}
+
+TfLiteStatus PrepareSquaredDifference(TfLiteContext *context, TfLiteNode *node)
+{
+  TF_LITE_ENSURE_EQ(context, ::tflite::NumInputs(node), 2);
+  TF_LITE_ENSURE_EQ(context, ::tflite::NumOutputs(node), 1);
+
+  const TfLiteTensor *input1 = ::tflite::GetInput(context, node, 0);
+  const TfLiteTensor *input2 = ::tflite::GetInput(context, node, 1);
+  TfLiteTensor *output = ::tflite::GetOutput(context, node, 0);
+
+  TF_LITE_ENSURE_EQ(context, input1->type, input2->type);
+  TF_LITE_ENSURE_EQ(context, input1->type, output->type);
+
+  return context->ResizeTensor(context, output, TfLiteIntArrayCopy(input1->dims));
+}
+
+TfLiteStatus EvalSquaredDifference(TfLiteContext *context, TfLiteNode *node)
+{
+
+  const TfLiteTensor *input1 = ::tflite::GetInput(context, node, 0);
+  const TfLiteTensor *input2 = ::tflite::GetInput(context, node, 1);
+
+  TfLiteTensor *output = ::tflite::GetOutput(context, node, 0);
+
+  size_t elements = ::tflite::NumElements(input1);
+
+  switch (input1->type)
+  {
+    case kTfLiteFloat32:
+    {
+      const float *in1 = input1->data.f;
+      const float *in2 = input2->data.f;
+      const float *in_end1 = in1 + elements;
+      float *out = output->data.f;
+
+      for (; in1 < in_end1; in1++, in2++, out++)
+        *out = ((*in1 - *in2) * (*in1 - *in2));
+
+      return kTfLiteOk;
+    }
+    case kTfLiteInt32:
+    {
+      const int *in1 = input1->data.i32;
+      const int *in2 = input2->data.i32;
+      const int *in_end1 = in1 + elements;
+      int *out = output->data.i32;
+
+      for (; in1 < in_end1; in1++, in2++, out++)
+        *out = ((*in1 - *in2) * (*in1 - *in2));
+
+      return kTfLiteOk;
+    }
+    case kTfLiteInt64:
+    {
+      const int64_t *in1 = input1->data.i64;
+      const int64_t *in2 = input1->data.i64;
+      const int64_t *in_end1 = in1 + elements;
+      int64_t *out = output->data.i64;
+
+      for (; in1 < in_end1; in1++, in2++, out++)
+        *out = ((*in1 - *in2) * (*in1 - *in2));
+
+      return kTfLiteOk;
+    }
+    default:
+    {
+      context->ReportError(context, "InputType is %d Unsupported", input1->type);
+      return kTfLiteError;
+    }
+  }
+}
+
+} // namespace SquaredDifference
+} // namespace custom
+} // namespace tflite
+} // namespace nnfw
diff --git a/runtime/libs/tflite/port/1.13.1/src/kernels/TensorFlowMax.cpp b/runtime/libs/tflite/port/1.13.1/src/kernels/TensorFlowMax.cpp
new file mode 100644
index 000000000..207de98f5
--- /dev/null
+++ b/runtime/libs/tflite/port/1.13.1/src/kernels/TensorFlowMax.cpp
@@ -0,0 +1,405 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "tflite/ext/kernels/TensorFlowMax.h"
+#include "tensorflow/lite/kernels/kernel_util.h"
+
+#include <iostream>
+
+namespace nnfw
+{
+namespace tflite
+{
+namespace custom
+{
+namespace TensorFlowMax
+{
+
+struct TensorFlowMaxOp
+{
+  TensorFlowMaxOp(TfLiteContext *context, TfLiteNode *node)
+  {
+    input = ::tflite::GetInput(context, node, 0);
+    axis = ::tflite::GetInput(context, node, 1);
+    output = ::tflite::GetOutput(context, node, 0);
+  }
+  const TfLiteTensor *input;
+  const TfLiteTensor *axis;
+  TfLiteTensor *output;
+};
+
+void *InitTensorFlowMax(TfLiteContext *context, const char *, size_t)
+{
+  // Creates two temp tensors to store index and axis for internal
+  // implementation only.
+  auto *scratch_tensor_index = new int;
+  context->AddTensors(context, 2, scratch_tensor_index);
+  return scratch_tensor_index;
+}
+
+void FreeTensorFlowMax(TfLiteContext *, void *buffer)
+{
+  delete static_cast<TensorFlowMaxOp *>(buffer);
+}
+
+// Resizes the temp tensor that stores resolved axis.
+TfLiteStatus ResizeTempAxis(TfLiteContext *context, TensorFlowMaxOp *op_context,
+                            TfLiteTensor *resolved_axis)
+{
+  TfLiteIntArray *axis_size = TfLiteIntArrayCreate(1);
+  axis_size->data[0] = static_cast<int>(::tflite::NumElements(op_context->axis));
+  return context->ResizeTensor(context, resolved_axis, axis_size);
+}
+
+// Resizes output array based on the input size and resolved axis.
+TfLiteStatus ResizeOutputTensor(TfLiteContext *context, TensorFlowMaxOp *op_context)
+{
+  int64_t num_axis = ::tflite::NumElements(op_context->axis);
+  TfLiteIntArray *input_dims = op_context->input->dims;
+  int input_num_dims = ::tflite::NumDimensions(op_context->input);
+  const int *axis = op_context->axis->data.i32;
+
+  {
+    // Calculates size of reducing axis.
+    int64_t num_reduce_axis = num_axis;
+    for (int64_t i = 0; i < num_axis; ++i)
+    {
+      int current = axis[i];
+      if (current < 0)
+      {
+        current += input_num_dims;
+      }
+      TF_LITE_ENSURE(context, current >= 0 && current < input_num_dims);
+      for (int64_t j = 0; j < i; ++j)
+      {
+        int previous = axis[j];
+        if (previous < 0)
+        {
+          previous += input_num_dims;
+        }
+        if (current == previous)
+        {
+          --num_reduce_axis;
+          break;
+        }
+      }
+    }
+    // Determines output dimensions.
+    int output_num_dims = ::tflite::NumDimensions(op_context->output);
+    TF_LITE_ENSURE(context, (input_num_dims == output_num_dims) ||
+                                (input_num_dims - num_reduce_axis == output_num_dims));
+
+    if (input_num_dims == output_num_dims)
+    {
+      TfLiteIntArray *output_dims = TfLiteIntArrayCopy(input_dims);
+      for (int64_t axis_idx = 0; axis_idx < num_axis; ++axis_idx)
+      {
+        int current = axis[axis_idx];
+        output_dims->data[current] = 1;
+      }
+      return context->ResizeTensor(context, op_context->output, output_dims);
+    }
+    else
+    {
+      TfLiteIntArray *output_dims = TfLiteIntArrayCreate(output_num_dims);
+      int num_skip_axis = 0;
+      for (int idx = 0; idx < input_num_dims; ++idx)
+      {
+        bool is_axis = false;
+        for (int axis_idx = 0; axis_idx < num_axis; ++axis_idx)
+        {
+          if (axis[axis_idx] == idx || axis[axis_idx] + input_num_dims == idx)
+          {
+            ++num_skip_axis;
+            is_axis = true;
+            break;
+          }
+        }
+        if (!is_axis)
+        {
+          output_dims->data[idx - num_skip_axis] = input_dims->data[idx];
+        }
+      }
+      return context->ResizeTensor(context, op_context->output, output_dims);
+    }
+  }
+}
+
+// Initializes temp tensors to store index and resolved axis.
+TfLiteStatus InitializeTemporaries(TfLiteContext *context, TfLiteNode *node,
+                                   TensorFlowMaxOp *op_context)
+{
+  // Creates a temp index to iterate through input data.
+  int *scratch_tensor_index = reinterpret_cast<int *>(node->user_data);
+  TfLiteIntArrayFree(node->temporaries);
+  node->temporaries = TfLiteIntArrayCreate(2);
+  node->temporaries->data[0] = *scratch_tensor_index;
+  TfLiteTensor *scratch_tensor = &context->tensors[node->temporaries->data[0]];
+  scratch_tensor->type = kTfLiteInt32;
+  scratch_tensor->allocation_type = kTfLiteArenaRw;
+  TfLiteIntArray *index_size = TfLiteIntArrayCreate(1);
+  index_size->data[0] = ::tflite::NumDimensions(op_context->input);
+  TF_LITE_ENSURE_OK(context, context->ResizeTensor(context, scratch_tensor, index_size));
+
+  // Creates a temp tensor to store resolved axis given input data.
+  node->temporaries->data[1] = *scratch_tensor_index + 1;
+  TfLiteTensor *resolved_axis = &context->tensors[node->temporaries->data[1]];
+  resolved_axis->type = kTfLiteInt32;
+  return kTfLiteOk;
+}
+
+TfLiteStatus PrepareTensorFlowMax(TfLiteContext *context, TfLiteNode *node)
+{
+  TF_LITE_ENSURE_EQ(context, ::tflite::NumInputs(node), 2);
+  TF_LITE_ENSURE_EQ(context, ::tflite::NumOutputs(node), 1);
+
+  TensorFlowMaxOp op_context(context, node);
+  TF_LITE_ENSURE_OK(context, InitializeTemporaries(context, node, &op_context));
+
+  TfLiteTensor *resolved_axis = &context->tensors[node->temporaries->data[1]];
+  // Leaves work to Eval if axis is not constant; else resizes output.
+  if (!::tflite::IsConstantTensor(op_context.axis))
+  {
+    ::tflite::SetTensorToDynamic(op_context.output);
+    ::tflite::SetTensorToDynamic(resolved_axis);
+    return kTfLiteOk;
+  }
+  resolved_axis->allocation_type = kTfLiteArenaRw;
+  TF_LITE_ENSURE_OK(context, ResizeTempAxis(context, &op_context, resolved_axis));
+  return ResizeOutputTensor(context, &op_context);
+}
+
+// Gets offset of index if expanded on axis. When expanded, the flattened offset
+// will not change, if the output index changes on the given axis. For example,
+// if you have a 2D tensor and you are expanding to 3D on axis 0,
+// then index (0, 1, 2) and index (1, 1, 2) will map from the same flattened
+// offset.
+inline size_t ExpandedInputOffset(const int num_dims, const int *dims, const int *index,
+                                  const int num_axis, const int *axis)
+{
+  size_t offset = 0;
+  int out_idx = 0;
+  for (int in_idx = 0; in_idx < num_dims; ++in_idx)
+  {
+    // if we need to expand this axis
+    bool is_axis = false;
+    if (axis != nullptr)
+    {
+      for (int axis_idx = 0; axis_idx < num_axis; ++axis_idx)
+      {
+        if (in_idx == axis[axis_idx])
+        {
+          is_axis = true;
+          break;
+        }
+      }
+    }
+    if (!is_axis)
+    {
+      offset = offset * static_cast<size_t>(dims[in_idx]) + static_cast<size_t>(index[out_idx]);
+      out_idx++;
+    }
+    else
+    {
+      offset = offset * static_cast<size_t>(dims[in_idx]);
+    }
+  }
+  return offset;
+}
+
+// Gets offset of index if reducing on axis. When reducing, the flattened offset
+// will not change, if the input index changes on the given axis. For example,
+// if you have a 3D tensor and you are reducing to 2D by eliminating axis 0,
+// then index (0, 1, 2) and index (1, 1, 2) will map to the same flattened
+// offset.
+// TODO(kanlig): uses Dims to represent dimensions.
+inline size_t ReducedOutputOffset(const int num_dims, const int *dims, const int *index,
+                                  const int num_axis, const int *axis)
+{
+  size_t offset = 0;
+  for (int idx = 0; idx < num_dims; ++idx)
+  {
+    // if we need to skip this axis
+    bool is_axis = false;
+    if (axis != nullptr)
+    {
+      for (int axis_idx = 0; axis_idx < num_axis; ++axis_idx)
+      {
+        if (idx == axis[axis_idx])
+        {
+          is_axis = true;
+          break;
+        }
+      }
+    }
+    if (!is_axis)
+    {
+      offset = offset * static_cast<size_t>(dims[idx]) + static_cast<size_t>(index[idx]);
+    }
+  }
+  return offset;
+}
+
+// Gets next index to iterate through a multidimensional array.
+inline bool NextIndex(TfLiteContext *context, const int num_dims, const int *dims, int *current)
+{
+  int carry = 1;
+  for (int idx = num_dims - 1; idx >= 0; --idx)
+  {
+    int current_val = current[idx] + carry;
+    TF_LITE_ENSURE(context, (dims[idx] >= current_val));
+    if (dims[idx] == current_val)
+    {
+      current[idx] = 0;
+    }
+    else
+    {
+      current[idx] = current_val;
+      carry = 0;
+      break;
+    }
+  }
+  return (carry == 0);
+}
+
+template <typename T>
+inline TfLiteStatus
+CustomMax(TfLiteContext *context, T *input_data, const int *input_dims, const int input_num_dims,
+          T *output_data, const int *output_dims, const int output_num_dims, const int *axis,
+          const int num_axis_dimensions, bool /*keep_dims*/, int *temp_index, int *resolved_axis)
+{
+  // resolves axis.
+  int num_resolved_axis = 0;
+  for (int idx = 0; idx < num_axis_dimensions; ++idx)
+  {
+    int current = axis[idx];
+    TF_LITE_ENSURE(context, (current < input_num_dims && current + input_num_dims >= 0));
+    if (current < 0)
+    {
+      current += input_num_dims;
+    }
+    bool is_dup = false;
+    for (int j = 0; j < num_resolved_axis; ++j)
+    {
+      if (resolved_axis[j] == current)
+      {
+        is_dup = true;
+        break;
+      }
+    }
+    if (!is_dup)
+    {
+      resolved_axis[num_resolved_axis++] = current;
+    }
+  }
+
+  TF_LITE_ENSURE(context, (input_num_dims > 0));
+  TF_LITE_ENSURE(context, (input_dims != nullptr));
+  TF_LITE_ENSURE(context, (temp_index != nullptr));
+
+  // resets output data.
+  for (int idx = 0; idx < output_num_dims; ++idx)
+  {
+    temp_index[idx] = 0;
+  }
+  for (bool has_next = true; has_next;
+       has_next = NextIndex(context, output_num_dims, output_dims, temp_index))
+  {
+    size_t output_offset =
+        ReducedOutputOffset(output_num_dims, output_dims, temp_index, 0, nullptr);
+    size_t input_offset = ExpandedInputOffset(input_num_dims, input_dims, temp_index,
+                                              num_resolved_axis, resolved_axis);
+    output_data[output_offset] = input_data[input_offset];
+  }
+
+  // resets temp index.
+  for (int idx = 0; idx < input_num_dims; ++idx)
+  {
+    temp_index[idx] = 0;
+  }
+
+  // iterates through input_data.
+  for (bool has_next = true; has_next;
+       has_next = NextIndex(context, input_num_dims, input_dims, temp_index))
+  {
+    size_t input_offset = ReducedOutputOffset(input_num_dims, input_dims, temp_index, 0, nullptr);
+    size_t output_offset = ReducedOutputOffset(input_num_dims, input_dims, temp_index,
+                                               num_resolved_axis, resolved_axis);
+    if (output_data[output_offset] < input_data[input_offset])
+    {
+      output_data[output_offset] = input_data[input_offset];
+    }
+  }
+
+  return kTfLiteOk;
+}
+
+TfLiteStatus EvalTensorFlowMax(TfLiteContext *context, TfLiteNode *node)
+{
+
+  TensorFlowMaxOp op_context(context, node);
+  int num_axis = static_cast<int>(::tflite::NumElements(op_context.axis));
+  TfLiteTensor *temp_index = &context->tensors[node->temporaries->data[0]];
+  TfLiteTensor *resolved_axis = &context->tensors[node->temporaries->data[1]];
+  // Resize the output tensor if the output tensor is dynamic.
+  if (::tflite::IsDynamicTensor(op_context.output))
+  {
+    TF_LITE_ENSURE_OK(context, ResizeTempAxis(context, &op_context, resolved_axis));
+    TF_LITE_ENSURE_OK(context, ResizeOutputTensor(context, &op_context));
+  }
+
+  TfLiteStatus returnStatus = kTfLiteOk;
+  switch (op_context.input->type)
+  {
+    case kTfLiteFloat32:
+      returnStatus = CustomMax<float>(
+          context, op_context.input->data.f, op_context.input->dims->data,
+          op_context.input->dims->size, op_context.output->data.f, op_context.output->dims->data,
+          op_context.output->dims->size, op_context.axis->data.i32, num_axis, false,
+          temp_index->data.i32, resolved_axis->data.i32);
+      break;
+    case kTfLiteInt32:
+      returnStatus = CustomMax<int>(context, op_context.input->data.i32,
+                                    op_context.input->dims->data, op_context.input->dims->size,
+                                    op_context.output->data.i32, op_context.output->dims->data,
+                                    op_context.output->dims->size, op_context.axis->data.i32,
+                                    num_axis, false, temp_index->data.i32, resolved_axis->data.i32);
+      break;
+    case kTfLiteUInt8:
+      returnStatus = CustomMax<uint8_t>(
+          context, op_context.input->data.uint8, op_context.input->dims->data,
+          op_context.input->dims->size, op_context.output->data.uint8,
+          op_context.output->dims->data, op_context.output->dims->size, op_context.axis->data.i32,
+          num_axis, false, temp_index->data.i32, resolved_axis->data.i32);
+      break;
+    case kTfLiteInt64:
+      returnStatus = CustomMax<int64_t>(
+          context, op_context.input->data.i64, op_context.input->dims->data,
+          op_context.input->dims->size, op_context.output->data.i64, op_context.output->dims->data,
+          op_context.output->dims->size, op_context.axis->data.i32, num_axis, false,
+          temp_index->data.i32, resolved_axis->data.i32);
+      break;
+    default:
+      returnStatus = kTfLiteError;
+  }
+
+  return returnStatus;
+}
+
+} // namespace TensorFlowMax
+} // namespace custom
+} // namespace tflite
+} // namespace nnfw
diff --git a/runtime/libs/tflite/port/1.13.1/src/kernels/TensorFlowSum.cpp b/runtime/libs/tflite/port/1.13.1/src/kernels/TensorFlowSum.cpp
new file mode 100644
index 000000000..40f266baa
--- /dev/null
+++ b/runtime/libs/tflite/port/1.13.1/src/kernels/TensorFlowSum.cpp
@@ -0,0 +1,400 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "tflite/ext/kernels/TensorFlowSum.h"
+#include "tensorflow/lite/kernels/kernel_util.h"
+
+#include <iostream>
+
+namespace nnfw
+{
+namespace tflite
+{
+namespace custom
+{
+namespace TensorFlowSum
+{
+
+struct TensorFlowSumOp
+{
+  TensorFlowSumOp(TfLiteContext *context, TfLiteNode *node)
+  {
+    input = ::tflite::GetInput(context, node, 0);
+    axis = ::tflite::GetInput(context, node, 1);
+    output = ::tflite::GetOutput(context, node, 0);
+  }
+  const TfLiteTensor *input;
+  const TfLiteTensor *axis;
+  TfLiteTensor *output;
+};
+
+void *InitTensorFlowSum(TfLiteContext *context, const char *, size_t)
+{
+  // Creates two temp tensors to store index and axis for internal
+  // implementation only.
+  auto *scratch_tensor_index = new int;
+  context->AddTensors(context, 2, scratch_tensor_index);
+  return scratch_tensor_index;
+}
+
+void FreeTensorFlowSum(TfLiteContext *, void *buffer)
+{
+  delete static_cast<TensorFlowSumOp *>(buffer);
+}
+
+// Resizes the temp tensor that stores resolved axis.
+TfLiteStatus ResizeTempAxis(TfLiteContext *context, TensorFlowSumOp *op_context,
+                            TfLiteTensor *resolved_axis)
+{
+  TfLiteIntArray *axis_size = TfLiteIntArrayCreate(1);
+  axis_size->data[0] = static_cast<int>(::tflite::NumElements(op_context->axis));
+  return context->ResizeTensor(context, resolved_axis, axis_size);
+}
+
+// Resizes output array based on the input size and resolved axis.
+TfLiteStatus ResizeOutputTensor(TfLiteContext *context, TensorFlowSumOp *op_context)
+{
+  int64_t num_axis = ::tflite::NumElements(op_context->axis);
+  TfLiteIntArray *input_dims = op_context->input->dims;
+  int input_num_dims = ::tflite::NumDimensions(op_context->input);
+  const int *axis = op_context->axis->data.i32;
+
+  {
+    // Calculates size of reducing axis.
+    int64_t num_reduce_axis = num_axis;
+    for (int64_t i = 0; i < num_axis; ++i)
+    {
+      int current = axis[i];
+      if (current < 0)
+      {
+        current += input_num_dims;
+      }
+      TF_LITE_ENSURE(context, current >= 0 && current < input_num_dims);
+      for (int64_t j = 0; j < i; ++j)
+      {
+        int previous = axis[j];
+        if (previous < 0)
+        {
+          previous += input_num_dims;
+        }
+        if (current == previous)
+        {
+          --num_reduce_axis;
+          break;
+        }
+      }
+    }
+    // Determines output dimensions.
+    int output_num_dims = ::tflite::NumDimensions(op_context->output);
+    TF_LITE_ENSURE(context, (input_num_dims == output_num_dims) ||
+                                (input_num_dims - num_reduce_axis == output_num_dims));
+
+    if (input_num_dims == output_num_dims)
+    {
+      TfLiteIntArray *output_dims = TfLiteIntArrayCopy(input_dims);
+      for (int64_t axis_idx = 0; axis_idx < num_axis; ++axis_idx)
+      {
+        int current = axis[axis_idx];
+        output_dims->data[current] = 1;
+      }
+      return context->ResizeTensor(context, op_context->output, output_dims);
+    }
+    else
+    {
+      TfLiteIntArray *output_dims = TfLiteIntArrayCreate(output_num_dims);
+      int num_skip_axis = 0;
+      for (int idx = 0; idx < input_num_dims; ++idx)
+      {
+        bool is_axis = false;
+        for (int axis_idx = 0; axis_idx < num_axis; ++axis_idx)
+        {
+          if (axis[axis_idx] == idx || axis[axis_idx] + input_num_dims == idx)
+          {
+            ++num_skip_axis;
+            is_axis = true;
+            break;
+          }
+        }
+        if (!is_axis)
+        {
+          output_dims->data[idx - num_skip_axis] = input_dims->data[idx];
+        }
+      }
+      return context->ResizeTensor(context, op_context->output, output_dims);
+    }
+  }
+}
+
+// Initializes temp tensors to store index and resolved axis.
+TfLiteStatus InitializeTemporaries(TfLiteContext *context, TfLiteNode *node,
+                                   TensorFlowSumOp *op_context)
+{
+  // Creates a temp index to iterate through input data.
+  int *scratch_tensor_index = reinterpret_cast<int *>(node->user_data);
+  TfLiteIntArrayFree(node->temporaries);
+  node->temporaries = TfLiteIntArrayCreate(2);
+  node->temporaries->data[0] = *scratch_tensor_index;
+  TfLiteTensor *scratch_tensor = &context->tensors[node->temporaries->data[0]];
+  scratch_tensor->type = kTfLiteInt32;
+  scratch_tensor->allocation_type = kTfLiteArenaRw;
+  TfLiteIntArray *index_size = TfLiteIntArrayCreate(1);
+  index_size->data[0] = ::tflite::NumDimensions(op_context->input);
+  TF_LITE_ENSURE_OK(context, context->ResizeTensor(context, scratch_tensor, index_size));
+
+  // Creates a temp tensor to store resolved axis given input data.
+  node->temporaries->data[1] = *scratch_tensor_index + 1;
+  TfLiteTensor *resolved_axis = &context->tensors[node->temporaries->data[1]];
+  resolved_axis->type = kTfLiteInt32;
+  return kTfLiteOk;
+}
+
+TfLiteStatus PrepareTensorFlowSum(TfLiteContext *context, TfLiteNode *node)
+{
+  TF_LITE_ENSURE_EQ(context, ::tflite::NumInputs(node), 2);
+  TF_LITE_ENSURE_EQ(context, ::tflite::NumOutputs(node), 1);
+
+  TensorFlowSumOp op_context(context, node);
+  TF_LITE_ENSURE_OK(context, InitializeTemporaries(context, node, &op_context));
+
+  TfLiteTensor *resolved_axis = &context->tensors[node->temporaries->data[1]];
+  // Leaves work to Eval if axis is not constant; else resizes output.
+  if (!::tflite::IsConstantTensor(op_context.axis))
+  {
+    ::tflite::SetTensorToDynamic(op_context.output);
+    ::tflite::SetTensorToDynamic(resolved_axis);
+    return kTfLiteOk;
+  }
+  resolved_axis->allocation_type = kTfLiteArenaRw;
+  TF_LITE_ENSURE_OK(context, ResizeTempAxis(context, &op_context, resolved_axis));
+  return ResizeOutputTensor(context, &op_context);
+}
+
+// Gets offset of index if expanded on axis. When expanded, the flattened offset
+// will not change, if the output index changes on the given axis. For example,
+// if you have a 2D tensor and you are expanding to 3D on axis 0,
+// then index (0, 1, 2) and index (1, 1, 2) will map from the same flattened
+// offset.
+inline size_t ExpandedInputOffset(const int num_dims, const int *dims, const int *index,
+                                  const int num_axis, const int *axis)
+{
+  size_t offset = 0;
+  int out_idx = 0;
+  for (int in_idx = 0; in_idx < num_dims; ++in_idx)
+  {
+    // if we need to expand this axis
+    bool is_axis = false;
+    if (axis != nullptr)
+    {
+      for (int axis_idx = 0; axis_idx < num_axis; ++axis_idx)
+      {
+        if (in_idx == axis[axis_idx])
+        {
+          is_axis = true;
+          break;
+        }
+      }
+    }
+    if (!is_axis)
+    {
+      offset = offset * static_cast<size_t>(dims[in_idx]) + static_cast<size_t>(index[out_idx]);
+      out_idx++;
+    }
+    else
+    {
+      offset = offset * static_cast<size_t>(dims[in_idx]);
+    }
+  }
+  return offset;
+}
+
+// Gets offset of index if reducing on axis. When reducing, the flattened offset
+// will not change, if the input index changes on the given axis. For example,
+// if you have a 3D tensor and you are reducing to 2D by eliminating axis 0,
+// then index (0, 1, 2) and index (1, 1, 2) will map to the same flattened
+// offset.
+// TODO(kanlig): uses Dims to represent dimensions.
+inline size_t ReducedOutputOffset(const int num_dims, const int *dims, const int *index,
+                                  const int num_axis, const int *axis)
+{
+  size_t offset = 0;
+  for (int idx = 0; idx < num_dims; ++idx)
+  {
+    // if we need to skip this axis
+    bool is_axis = false;
+    if (axis != nullptr)
+    {
+      for (int axis_idx = 0; axis_idx < num_axis; ++axis_idx)
+      {
+        if (idx == axis[axis_idx])
+        {
+          is_axis = true;
+          break;
+        }
+      }
+    }
+    if (!is_axis)
+    {
+      offset = offset * static_cast<size_t>(dims[idx]) + static_cast<size_t>(index[idx]);
+    }
+  }
+  return offset;
+}
+
+// Gets next index to iterate through a multidimensional array.
+inline bool NextIndex(TfLiteContext *context, const int num_dims, const int *dims, int *current)
+{
+  int carry = 1;
+  for (int idx = num_dims - 1; idx >= 0; --idx)
+  {
+    int current_val = current[idx] + carry;
+    TF_LITE_ENSURE(context, (dims[idx] >= current_val));
+    if (dims[idx] == current_val)
+    {
+      current[idx] = 0;
+    }
+    else
+    {
+      current[idx] = current_val;
+      carry = 0;
+      break;
+    }
+  }
+  return (carry == 0);
+}
+
+template <typename T>
+inline TfLiteStatus
+CustomSum(TfLiteContext *context, T *input_data, const int *input_dims, const int input_num_dims,
+          T *output_data, const int *output_dims, const int output_num_dims, const int *axis,
+          const int num_axis_dimensions, bool /*keep_dims*/, int *temp_index, int *resolved_axis)
+{
+  // resolves axis.
+  int num_resolved_axis = 0;
+  for (int idx = 0; idx < num_axis_dimensions; ++idx)
+  {
+    int current = axis[idx];
+    TF_LITE_ENSURE(context, (current < input_num_dims && current + input_num_dims >= 0));
+    if (current < 0)
+    {
+      current += input_num_dims;
+    }
+    bool is_dup = false;
+    for (int j = 0; j < num_resolved_axis; ++j)
+    {
+      if (resolved_axis[j] == current)
+      {
+        is_dup = true;
+        break;
+      }
+    }
+    if (!is_dup)
+    {
+      resolved_axis[num_resolved_axis++] = current;
+    }
+  }
+
+  TF_LITE_ENSURE(context, (input_num_dims > 0));
+  TF_LITE_ENSURE(context, (input_dims != nullptr));
+  TF_LITE_ENSURE(context, (temp_index != nullptr));
+
+  // resets output data.
+  for (int idx = 0; idx < output_num_dims; ++idx)
+  {
+    temp_index[idx] = 0;
+  }
+  for (bool has_next = true; has_next;
+       has_next = NextIndex(context, output_num_dims, output_dims, temp_index))
+  {
+    size_t output_offset =
+        ReducedOutputOffset(output_num_dims, output_dims, temp_index, 0, nullptr);
+    output_data[output_offset] = 0;
+  }
+
+  // resets temp index.
+  for (int idx = 0; idx < input_num_dims; ++idx)
+  {
+    temp_index[idx] = 0;
+  }
+
+  // iterates through input_data.
+  for (bool has_next = true; has_next;
+       has_next = NextIndex(context, input_num_dims, input_dims, temp_index))
+  {
+    size_t input_offset = ReducedOutputOffset(input_num_dims, input_dims, temp_index, 0, nullptr);
+    size_t output_offset = ReducedOutputOffset(input_num_dims, input_dims, temp_index,
+                                               num_resolved_axis, resolved_axis);
+    output_data[output_offset] += input_data[input_offset];
+  }
+
+  return kTfLiteOk;
+}
+
+TfLiteStatus EvalTensorFlowSum(TfLiteContext *context, TfLiteNode *node)
+{
+
+  TensorFlowSumOp op_context(context, node);
+  int num_axis = static_cast<int>(::tflite::NumElements(op_context.axis));
+  TfLiteTensor *temp_index = &context->tensors[node->temporaries->data[0]];
+  TfLiteTensor *resolved_axis = &context->tensors[node->temporaries->data[1]];
+  // Resize the output tensor if the output tensor is dynamic.
+  if (::tflite::IsDynamicTensor(op_context.output))
+  {
+    TF_LITE_ENSURE_OK(context, ResizeTempAxis(context, &op_context, resolved_axis));
+    TF_LITE_ENSURE_OK(context, ResizeOutputTensor(context, &op_context));
+  }
+
+  TfLiteStatus returnStatus = kTfLiteOk;
+  switch (op_context.input->type)
+  {
+    case kTfLiteFloat32:
+      returnStatus = CustomSum<float>(
+          context, op_context.input->data.f, op_context.input->dims->data,
+          op_context.input->dims->size, op_context.output->data.f, op_context.output->dims->data,
+          op_context.output->dims->size, op_context.axis->data.i32, num_axis, false,
+          temp_index->data.i32, resolved_axis->data.i32);
+      break;
+    case kTfLiteInt32:
+      returnStatus = CustomSum<int>(context, op_context.input->data.i32,
+                                    op_context.input->dims->data, op_context.input->dims->size,
+                                    op_context.output->data.i32, op_context.output->dims->data,
+                                    op_context.output->dims->size, op_context.axis->data.i32,
+                                    num_axis, false, temp_index->data.i32, resolved_axis->data.i32);
+      break;
+    case kTfLiteUInt8:
+      returnStatus = CustomSum<uint8_t>(
+          context, op_context.input->data.uint8, op_context.input->dims->data,
+          op_context.input->dims->size, op_context.output->data.uint8,
+          op_context.output->dims->data, op_context.output->dims->size, op_context.axis->data.i32,
+          num_axis, false, temp_index->data.i32, resolved_axis->data.i32);
+      break;
+    case kTfLiteInt64:
+      returnStatus = CustomSum<int64_t>(
+          context, op_context.input->data.i64, op_context.input->dims->data,
+          op_context.input->dims->size, op_context.output->data.i64, op_context.output->dims->data,
+          op_context.output->dims->size, op_context.axis->data.i32, num_axis, false,
+          temp_index->data.i32, resolved_axis->data.i32);
+      break;
+    default:
+      returnStatus = kTfLiteError;
+  }
+
+  return returnStatus;
+}
+
+} // namespace TensorFlowSum
+} // namespace custom
+} // namespace tflite
+} // namespace nnfw
diff --git a/runtime/libs/tflite/port/1.13.1/src/kernels/register.cpp b/runtime/libs/tflite/port/1.13.1/src/kernels/register.cpp
new file mode 100644
index 000000000..b2088b277
--- /dev/null
+++ b/runtime/libs/tflite/port/1.13.1/src/kernels/register.cpp
@@ -0,0 +1,317 @@
+/* Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+   Copyright 2017 The TensorFlow Authors. All Rights Reserved.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+==============================================================================*/
+
+// NOTE To minimize diff with upstream tensorflow, disable clang-format
+// clang-format off
+
+// NOTE This code is derived from the following file (in TensorFlow v1.13.1)
+//        'externals/tensorflow/tensorflow/lite/kernels/register.cc'
+#include "tflite/ext/kernels/register.h"
+#include "tensorflow/lite/util.h"
+#include "tflite/ext/kernels/CustomOps.h"
+
+namespace tflite {
+namespace ops {
+
+namespace custom {
+
+// Need additional external library for AUDIO_SPECTROGRAM
+//TfLiteRegistration* Register_AUDIO_SPECTROGRAM();
+TfLiteRegistration* Register_LAYER_NORM_LSTM();
+TfLiteRegistration* Register_MFCC();
+TfLiteRegistration* Register_DETECTION_POSTPROCESS();
+TfLiteRegistration* Register_RELU_1();
+
+}  // namespace custom
+}
+}
+
+namespace tflite {
+namespace ops {
+namespace builtin {
+
+TfLiteRegistration* Register_ABS();
+TfLiteRegistration* Register_RELU();
+TfLiteRegistration* Register_RELU_N1_TO_1();
+TfLiteRegistration* Register_RELU6();
+TfLiteRegistration* Register_TANH();
+TfLiteRegistration* Register_LOGISTIC();
+TfLiteRegistration* Register_AVERAGE_POOL_2D();
+TfLiteRegistration* Register_MAX_POOL_2D();
+TfLiteRegistration* Register_L2_POOL_2D();
+TfLiteRegistration* Register_CONV_2D();
+TfLiteRegistration* Register_DEPTHWISE_CONV_2D();
+TfLiteRegistration* Register_SVDF();
+TfLiteRegistration* Register_RNN();
+TfLiteRegistration* Register_BIDIRECTIONAL_SEQUENCE_RNN();
+TfLiteRegistration* Register_UNIDIRECTIONAL_SEQUENCE_RNN();
+TfLiteRegistration* Register_EMBEDDING_LOOKUP();
+TfLiteRegistration* Register_EMBEDDING_LOOKUP_SPARSE();
+TfLiteRegistration* Register_FULLY_CONNECTED();
+TfLiteRegistration* Register_LSH_PROJECTION();
+TfLiteRegistration* Register_HASHTABLE_LOOKUP();
+TfLiteRegistration* Register_SOFTMAX();
+TfLiteRegistration* Register_CONCATENATION();
+TfLiteRegistration* Register_ADD();
+TfLiteRegistration* Register_SPACE_TO_BATCH_ND();
+TfLiteRegistration* Register_DIV();
+TfLiteRegistration* Register_SUB();
+TfLiteRegistration* Register_BATCH_TO_SPACE_ND();
+TfLiteRegistration* Register_MUL();
+TfLiteRegistration* Register_L2_NORMALIZATION();
+TfLiteRegistration* Register_LOCAL_RESPONSE_NORMALIZATION();
+TfLiteRegistration* Register_LSTM();
+TfLiteRegistration* Register_BIDIRECTIONAL_SEQUENCE_LSTM();
+TfLiteRegistration* Register_UNIDIRECTIONAL_SEQUENCE_LSTM();
+TfLiteRegistration* Register_PAD();
+TfLiteRegistration* Register_PADV2();
+TfLiteRegistration* Register_RESHAPE();
+TfLiteRegistration* Register_RESIZE_BILINEAR();
+TfLiteRegistration* Register_RESIZE_NEAREST_NEIGHBOR();
+TfLiteRegistration* Register_SKIP_GRAM();
+TfLiteRegistration* Register_SPACE_TO_DEPTH();
+TfLiteRegistration* Register_GATHER();
+TfLiteRegistration* Register_TRANSPOSE();
+TfLiteRegistration* Register_MEAN();
+TfLiteRegistration* Register_SPLIT();
+TfLiteRegistration* Register_SPLIT_V();
+TfLiteRegistration* Register_SQUEEZE();
+TfLiteRegistration* Register_STRIDED_SLICE();
+TfLiteRegistration* Register_EXP();
+TfLiteRegistration* Register_TOPK_V2();
+TfLiteRegistration* Register_LOG();
+TfLiteRegistration* Register_LOG_SOFTMAX();
+TfLiteRegistration* Register_CAST();
+TfLiteRegistration* Register_DEQUANTIZE();
+TfLiteRegistration* Register_PRELU();
+TfLiteRegistration* Register_MAXIMUM();
+TfLiteRegistration* Register_MINIMUM();
+TfLiteRegistration* Register_ARG_MAX();
+TfLiteRegistration* Register_ARG_MIN();
+TfLiteRegistration* Register_GREATER();
+TfLiteRegistration* Register_GREATER_EQUAL();
+TfLiteRegistration* Register_LESS();
+TfLiteRegistration* Register_LESS_EQUAL();
+TfLiteRegistration* Register_FLOOR();
+TfLiteRegistration* Register_TILE();
+TfLiteRegistration* Register_NEG();
+TfLiteRegistration* Register_SUM();
+TfLiteRegistration* Register_REDUCE_PROD();
+TfLiteRegistration* Register_REDUCE_MAX();
+TfLiteRegistration* Register_REDUCE_MIN();
+TfLiteRegistration* Register_REDUCE_ANY();
+TfLiteRegistration* Register_SELECT();
+TfLiteRegistration* Register_SLICE();
+TfLiteRegistration* Register_SIN();
+TfLiteRegistration* Register_TRANSPOSE_CONV();
+TfLiteRegistration* Register_EXPAND_DIMS();
+TfLiteRegistration* Register_SPARSE_TO_DENSE();
+TfLiteRegistration* Register_EQUAL();
+TfLiteRegistration* Register_NOT_EQUAL();
+TfLiteRegistration* Register_SQRT();
+TfLiteRegistration* Register_RSQRT();
+TfLiteRegistration* Register_SHAPE();
+TfLiteRegistration* Register_POW();
+TfLiteRegistration* Register_FAKE_QUANT();
+TfLiteRegistration* Register_PACK();
+TfLiteRegistration* Register_ONE_HOT();
+TfLiteRegistration* Register_LOGICAL_OR();
+TfLiteRegistration* Register_LOGICAL_AND();
+TfLiteRegistration* Register_LOGICAL_NOT();
+TfLiteRegistration* Register_UNPACK();
+TfLiteRegistration* Register_FLOOR_DIV();
+TfLiteRegistration* Register_SQUARE();
+TfLiteRegistration* Register_ZEROS_LIKE();
+TfLiteRegistration* Register_FLOOR_MOD();
+TfLiteRegistration* Register_RANGE();
+TfLiteRegistration* Register_LEAKY_RELU();
+TfLiteRegistration* Register_SQUARED_DIFFERENCE();
+TfLiteRegistration* Register_FILL();
+TfLiteRegistration* Register_MIRROR_PAD();
+
+}  // namespace builtin
+}  // namespace ops
+}  // namespace tflite
+
+namespace nnfw {
+namespace tflite {
+
+// Using namespace directive to minimize diff with upstream tensorflow
+using namespace ::tflite::ops::custom;
+using namespace ::tflite::ops::builtin;
+using namespace ::tflite;
+
+// Fix to use strict build option
+TfLiteStatus UnsupportedTensorFlowOp(TfLiteContext* context, TfLiteNode* /*node*/) {
+  context->ReportError(
+      context,
+      "Regular TensorFlow ops are not supported by this interpreter. Make sure "
+      "you invoke the Flex delegate before inference.");
+  return kTfLiteError;
+}
+
+const TfLiteRegistration* BuiltinOpResolver::FindOp(tflite::BuiltinOperator op,
+                                                    int version) const {
+  return MutableOpResolver::FindOp(op, version);
+}
+
+const TfLiteRegistration* BuiltinOpResolver::FindOp(const char* op,
+                                                    int version) const {
+  // Return the NULL Op for all ops whose name start with "Flex", allowing
+  // the interpreter to delegate their execution.
+  if (IsFlexOp(op)) {
+    static TfLiteRegistration null_op{
+        nullptr, nullptr, &UnsupportedTensorFlowOp,
+        nullptr, nullptr, BuiltinOperator_CUSTOM,
+        "Flex",  1};
+    return &null_op;
+  }
+  return MutableOpResolver::FindOp(op, version);
+}
+
+BuiltinOpResolver::BuiltinOpResolver() {
+  AddBuiltin(BuiltinOperator_ABS, Register_ABS());
+  AddBuiltin(BuiltinOperator_RELU, Register_RELU());
+  AddBuiltin(BuiltinOperator_RELU_N1_TO_1, Register_RELU_N1_TO_1());
+  AddBuiltin(BuiltinOperator_RELU6, Register_RELU6());
+  AddBuiltin(BuiltinOperator_TANH, Register_TANH());
+  AddBuiltin(BuiltinOperator_LOGISTIC, Register_LOGISTIC());
+  AddBuiltin(BuiltinOperator_AVERAGE_POOL_2D, Register_AVERAGE_POOL_2D());
+  AddBuiltin(BuiltinOperator_MAX_POOL_2D, Register_MAX_POOL_2D());
+  AddBuiltin(BuiltinOperator_L2_POOL_2D, Register_L2_POOL_2D());
+  AddBuiltin(BuiltinOperator_CONV_2D, Register_CONV_2D());
+  AddBuiltin(BuiltinOperator_DEPTHWISE_CONV_2D, Register_DEPTHWISE_CONV_2D(),
+             /* min_version */ 1,
+             /* max_version */ 2);
+  AddBuiltin(BuiltinOperator_SVDF, Register_SVDF());
+  AddBuiltin(BuiltinOperator_RNN, Register_RNN());
+  AddBuiltin(BuiltinOperator_BIDIRECTIONAL_SEQUENCE_RNN,
+             Register_BIDIRECTIONAL_SEQUENCE_RNN());
+  AddBuiltin(BuiltinOperator_UNIDIRECTIONAL_SEQUENCE_RNN,
+             Register_UNIDIRECTIONAL_SEQUENCE_RNN());
+  AddBuiltin(BuiltinOperator_EMBEDDING_LOOKUP, Register_EMBEDDING_LOOKUP());
+  AddBuiltin(BuiltinOperator_EMBEDDING_LOOKUP_SPARSE,
+             Register_EMBEDDING_LOOKUP_SPARSE());
+  AddBuiltin(BuiltinOperator_FULLY_CONNECTED, Register_FULLY_CONNECTED(),
+             /* min_version */ 1,
+             /* max_version */ 2);
+  AddBuiltin(BuiltinOperator_LSH_PROJECTION, Register_LSH_PROJECTION());
+  AddBuiltin(BuiltinOperator_HASHTABLE_LOOKUP, Register_HASHTABLE_LOOKUP());
+  AddBuiltin(BuiltinOperator_SOFTMAX, Register_SOFTMAX());
+  AddBuiltin(BuiltinOperator_CONCATENATION, Register_CONCATENATION());
+  AddBuiltin(BuiltinOperator_ADD, Register_ADD());
+  AddBuiltin(BuiltinOperator_SPACE_TO_BATCH_ND, Register_SPACE_TO_BATCH_ND());
+  AddBuiltin(BuiltinOperator_BATCH_TO_SPACE_ND, Register_BATCH_TO_SPACE_ND());
+  AddBuiltin(BuiltinOperator_MUL, Register_MUL());
+  AddBuiltin(BuiltinOperator_L2_NORMALIZATION, Register_L2_NORMALIZATION());
+  AddBuiltin(BuiltinOperator_LOCAL_RESPONSE_NORMALIZATION,
+             Register_LOCAL_RESPONSE_NORMALIZATION());
+  AddBuiltin(BuiltinOperator_LSTM, Register_LSTM(), /* min_version */ 1,
+             /* max_version */ 2);
+  AddBuiltin(BuiltinOperator_BIDIRECTIONAL_SEQUENCE_LSTM,
+             Register_BIDIRECTIONAL_SEQUENCE_LSTM());
+  AddBuiltin(BuiltinOperator_UNIDIRECTIONAL_SEQUENCE_LSTM,
+             Register_UNIDIRECTIONAL_SEQUENCE_LSTM());
+  AddBuiltin(BuiltinOperator_PAD, Register_PAD());
+  AddBuiltin(BuiltinOperator_PADV2, Register_PADV2());
+  AddBuiltin(BuiltinOperator_RESHAPE, Register_RESHAPE());
+  AddBuiltin(BuiltinOperator_RESIZE_BILINEAR, Register_RESIZE_BILINEAR());
+  AddBuiltin(BuiltinOperator_RESIZE_NEAREST_NEIGHBOR,
+             Register_RESIZE_NEAREST_NEIGHBOR());
+  AddBuiltin(BuiltinOperator_SKIP_GRAM, Register_SKIP_GRAM());
+  AddBuiltin(BuiltinOperator_SPACE_TO_DEPTH, Register_SPACE_TO_DEPTH());
+  AddBuiltin(BuiltinOperator_GATHER, Register_GATHER());
+  AddBuiltin(BuiltinOperator_TRANSPOSE, Register_TRANSPOSE());
+  AddBuiltin(BuiltinOperator_MEAN, Register_MEAN());
+  AddBuiltin(BuiltinOperator_DIV, Register_DIV());
+  AddBuiltin(BuiltinOperator_SUB, Register_SUB());
+  AddBuiltin(BuiltinOperator_SPLIT, Register_SPLIT());
+  AddBuiltin(BuiltinOperator_SPLIT_V, Register_SPLIT_V());
+  AddBuiltin(BuiltinOperator_SQUEEZE, Register_SQUEEZE());
+  AddBuiltin(BuiltinOperator_STRIDED_SLICE, Register_STRIDED_SLICE());
+  AddBuiltin(BuiltinOperator_EXP, Register_EXP());
+  AddBuiltin(BuiltinOperator_TOPK_V2, Register_TOPK_V2());
+  AddBuiltin(BuiltinOperator_LOG, Register_LOG());
+  AddBuiltin(BuiltinOperator_LOG_SOFTMAX, Register_LOG_SOFTMAX());
+  AddBuiltin(BuiltinOperator_CAST, Register_CAST());
+  AddBuiltin(BuiltinOperator_DEQUANTIZE, Register_DEQUANTIZE(),
+             /* min_version */ 1,
+             /* max_version */ 2);
+  AddBuiltin(BuiltinOperator_PRELU, Register_PRELU());
+  AddBuiltin(BuiltinOperator_MAXIMUM, Register_MAXIMUM());
+  AddBuiltin(BuiltinOperator_MINIMUM, Register_MINIMUM());
+  AddBuiltin(BuiltinOperator_ARG_MAX, Register_ARG_MAX());
+  AddBuiltin(BuiltinOperator_ARG_MIN, Register_ARG_MIN());
+  AddBuiltin(BuiltinOperator_GREATER, Register_GREATER());
+  AddBuiltin(BuiltinOperator_GREATER_EQUAL, Register_GREATER_EQUAL());
+  AddBuiltin(BuiltinOperator_LESS, Register_LESS());
+  AddBuiltin(BuiltinOperator_LESS_EQUAL, Register_LESS_EQUAL());
+  AddBuiltin(BuiltinOperator_FLOOR, Register_FLOOR());
+  AddBuiltin(BuiltinOperator_NEG, Register_NEG());
+  AddBuiltin(BuiltinOperator_SELECT, Register_SELECT());
+  AddBuiltin(BuiltinOperator_SLICE, Register_SLICE());
+  AddBuiltin(BuiltinOperator_SIN, Register_SIN());
+  AddBuiltin(BuiltinOperator_TRANSPOSE_CONV, Register_TRANSPOSE_CONV());
+  AddBuiltin(BuiltinOperator_TILE, Register_TILE());
+  AddBuiltin(BuiltinOperator_SUM, Register_SUM());
+  AddBuiltin(BuiltinOperator_REDUCE_PROD, Register_REDUCE_PROD());
+  AddBuiltin(BuiltinOperator_REDUCE_MAX, Register_REDUCE_MAX());
+  AddBuiltin(BuiltinOperator_REDUCE_MIN, Register_REDUCE_MIN());
+  AddBuiltin(BuiltinOperator_REDUCE_ANY, Register_REDUCE_ANY());
+  AddBuiltin(BuiltinOperator_EXPAND_DIMS, Register_EXPAND_DIMS());
+  AddBuiltin(BuiltinOperator_SPARSE_TO_DENSE, Register_SPARSE_TO_DENSE());
+  AddBuiltin(BuiltinOperator_EQUAL, Register_EQUAL());
+  AddBuiltin(BuiltinOperator_NOT_EQUAL, Register_NOT_EQUAL());
+  AddBuiltin(BuiltinOperator_SQRT, Register_SQRT());
+  AddBuiltin(BuiltinOperator_RSQRT, Register_RSQRT());
+  AddBuiltin(BuiltinOperator_SHAPE, Register_SHAPE());
+  AddBuiltin(BuiltinOperator_POW, Register_POW());
+  AddBuiltin(BuiltinOperator_FAKE_QUANT, Register_FAKE_QUANT(), 1, 2);
+  AddBuiltin(BuiltinOperator_PACK, Register_PACK());
+  AddBuiltin(BuiltinOperator_ONE_HOT, Register_ONE_HOT());
+  AddBuiltin(BuiltinOperator_LOGICAL_OR, Register_LOGICAL_OR());
+  AddBuiltin(BuiltinOperator_LOGICAL_AND, Register_LOGICAL_AND());
+  AddBuiltin(BuiltinOperator_LOGICAL_NOT, Register_LOGICAL_NOT());
+  AddBuiltin(BuiltinOperator_UNPACK, Register_UNPACK());
+  AddBuiltin(BuiltinOperator_FLOOR_DIV, Register_FLOOR_DIV());
+  AddBuiltin(BuiltinOperator_SQUARE, Register_SQUARE());
+  AddBuiltin(BuiltinOperator_ZEROS_LIKE, Register_ZEROS_LIKE());
+  AddBuiltin(BuiltinOperator_FLOOR_MOD, Register_FLOOR_MOD());
+  AddBuiltin(BuiltinOperator_RANGE, Register_RANGE());
+  AddBuiltin(BuiltinOperator_LEAKY_RELU, Register_LEAKY_RELU());
+  AddBuiltin(BuiltinOperator_SQUARED_DIFFERENCE, Register_SQUARED_DIFFERENCE());
+  AddBuiltin(BuiltinOperator_FILL, Register_FILL());
+  AddBuiltin(BuiltinOperator_MIRROR_PAD, Register_MIRROR_PAD());
+
+  AddCustom("TensorFlowMax", nnfw::tflite::custom::Register_TensorFlowMax());
+  AddCustom("SquaredDifference", nnfw::tflite::custom::Register_SquaredDifference());
+  AddCustom("TensorFlowSum", nnfw::tflite::custom::Register_TensorFlowSum());
+  AddCustom("Abs", nnfw::tflite::custom::Register_Abs());
+
+  // TODO(andrewharp, ahentz): Move these somewhere more appropriate so that
+  // custom ops aren't always included by default.
+  AddCustom("Mfcc", tflite::ops::custom::Register_MFCC());
+  // Need additional external library for audio spectrogram
+  //AddCustom("AudioSpectrogram",
+  //          tflite::ops::custom::Register_AUDIO_SPECTROGRAM());
+  AddCustom("LayerNormLstm", tflite::ops::custom::Register_LAYER_NORM_LSTM());
+  AddCustom("Relu1", tflite::ops::custom::Register_RELU_1());
+  AddCustom("TFLite_Detection_PostProcess",
+            tflite::ops::custom::Register_DETECTION_POSTPROCESS());
+}
+
+}  // namespace tflite
+}  // namespace nnfw
diff --git a/runtime/libs/tflite/port/1.13.1/src/nnapi_delegate.cpp b/runtime/libs/tflite/port/1.13.1/src/nnapi_delegate.cpp
new file mode 100644
index 000000000..99272f0e5
--- /dev/null
+++ b/runtime/libs/tflite/port/1.13.1/src/nnapi_delegate.cpp
@@ -0,0 +1,1217 @@
+/* Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+   Copyright 2017 The TensorFlow Authors. All Rights Reserved.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+==============================================================================*/
+
+// NOTE To minimize diff with upstream tensorflow, disable clang-format
+// clang-format off
+
+// NOTE This code is derived from the following file (in TensorFlow v1.13.1)
+//        'externals/tensorflow/tensorflow/lite/nnapi_delegate.cc'
+#include "tflite/ext/nnapi_delegate.h"
+#include <fcntl.h>
+#include <sys/mman.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+#include "tensorflow/lite/c/builtin_op_data.h"
+#include "tensorflow/lite/core/api/error_reporter.h"
+#include "tensorflow/lite/model.h"
+#include <rua/Shim.h>
+#include "NeuralNetworksExShim.h"
+
+#ifdef __ANDROID__
+#include <android/log.h>
+#include <sys/system_properties.h>
+#endif
+
+namespace nnfw {
+namespace tflite {
+
+void logError(const char* format, ...) {
+  // stderr is convenient for native tests, but is not captured for apps
+  va_list args_for_stderr;
+  va_start(args_for_stderr, format);
+  vfprintf(stderr, format, args_for_stderr);
+  va_end(args_for_stderr);
+  fprintf(stderr, "\n");
+  fflush(stderr);
+#ifdef __ANDROID__
+  // produce logcat output for general consumption
+  va_list args_for_log;
+  va_start(args_for_log, format);
+  __android_log_vprint(ANDROID_LOG_ERROR, "tflite", format, args_for_log);
+  va_end(args_for_log);
+#endif
+}
+
+#define FATAL(...)       \
+  logError(__VA_ARGS__); \
+  exit(1);
+
+// TODO(aselle): Change the error model to use status codes.
+#define CHECK_TFLITE_SUCCESS(x)                                           \
+  if (x != kTfLiteOk) {                                                   \
+    FATAL("Aborting since tflite returned failure nnapi_delegate.cc:%d.", \
+          __LINE__);                                                      \
+  }
+
+#define CHECK_NN(x)                                                     \
+  if (x != ANEURALNETWORKS_NO_ERROR) {                                  \
+    FATAL("Aborting since NNAPI returned failure nnapi_delegate.cc:%d", \
+          __LINE__);                                                    \
+  }
+
+#define RETURN_ERROR_IF_TFLITE_FAILED(x)                                       \
+  if (x != kTfLiteOk) {                                                        \
+    logError(                                                                  \
+        "Returning error since TFLite returned failure nnapi_delegate.cc:%d.", \
+        __LINE__);                                                             \
+    return kTfLiteError;                                                       \
+  }
+
+#define RETURN_ERROR_IF_NN_FAILED(x)                                          \
+  if (x != ANEURALNETWORKS_NO_ERROR) {                                        \
+    logError(                                                                 \
+        "Returning error since NNAPI returned failure nnapi_delegate.cc:%d.", \
+        __LINE__);                                                            \
+    return kTfLiteError;                                                      \
+  }
+
+// Tracking of NNAPI operand ids
+static const int64_t kOperandIdNotSet = -1;
+static const int64_t kOperandNotNeeded = -2;
+
+namespace {
+
+int32_t GetAndroidSdkVersion() {
+#ifdef __ANDROID__
+  const char* sdkProp = "ro.build.version.sdk";
+  char sdkVersion[PROP_VALUE_MAX];
+  int length = __system_property_get(sdkProp, sdkVersion);
+  if (length != 0) {
+    for (int i = 0; i < length; ++i) {
+      int digit = sdkVersion[i] - '0';
+      if (digit < 0 || digit > 9) {
+        // Non-numeric SDK version, assume it's higher then expected;
+        return 0xFFFF;
+      }
+    }
+    // NOTE use std::strtol instead of atoi: security issue
+    return std::strtol(sdkVersion, NULL, 0);
+  }
+  FATAL("No %s prop", sdkProp);
+#endif  // __ANDROID__
+  return 0;
+}
+
+int32_t GetAndroidSdkVersionCached() {
+  static int32_t androidSdkVersion = GetAndroidSdkVersion();
+  return androidSdkVersion;
+}
+
+// WORKAROUND Some model have dimension zero
+// Consider scalar as vector size 1
+static const uint32_t dimension_for_scalar[1] = {1};
+
+}  // namespace
+
+NNAPIAllocation::NNAPIAllocation(const char* filename,
+                                 ::tflite::ErrorReporter* error_reporter)
+    : MMAPAllocation(filename, error_reporter) {
+  if (mmapped_buffer_ != MAP_FAILED)
+    CHECK_NN(ANeuralNetworksMemory_createFromFd(buffer_size_bytes_, PROT_READ,
+                                                mmap_fd_, 0, &handle_));
+}
+
+NNAPIAllocation::~NNAPIAllocation() {
+  if (handle_) {
+    ANeuralNetworksMemory_free(handle_);
+  }
+}
+
+NNAPIDelegate::~NNAPIDelegate() {
+  if (nn_compiled_model_) {
+    ANeuralNetworksCompilation_free(nn_compiled_model_);
+    nn_compiled_model_ = nullptr;
+  }
+  if (nn_model_) {
+    ANeuralNetworksModel_free(nn_model_);
+    nn_model_ = nullptr;
+    // TODO(aselle): Is this thread-safe and callable multiple times?
+  }
+  // ANeuralNetworksShutdown();
+}
+
+// Adds the tensors of the subgraph to the NN API model.
+TfLiteStatus addTensorOperands(::tflite::Subgraph* subgraph,
+                               ANeuralNetworksModel* nn_model,
+                               uint32_t* no_of_operands_added,
+                               std::vector<int64_t>* nnapi_ids) {
+  uint32_t next_id = 0;
+  for (size_t i = 0; i < subgraph->tensors_size(); i++) {
+    // Skip temporaries and RNN back-edges.
+    if ((*nnapi_ids)[i] == kOperandNotNeeded) continue;
+
+    (*nnapi_ids)[i] = int64_t(next_id);
+
+    int32_t nn_type = 0;
+    // NNAPI requires 32-bit float scale to be zero, tflite doesn't care
+    float scale = 0.0f;
+    int32_t zeroPoint = 0;
+    TfLiteTensor* tensor = subgraph->tensor(i);
+    switch (tensor->type) {
+      case kTfLiteNoType:
+        // Tensors added during initialization of Ops don't have a type yet and
+        // should not be registered with the NNAPI.
+        continue;
+      case kTfLiteFloat32:
+        nn_type = ANEURALNETWORKS_TENSOR_FLOAT32;
+        break;
+      case kTfLiteUInt8:
+        // NNAPI uses ANEURALNETWORKS_TENSOR_QUANT8_ASYMM to represent uint8 type
+        // ex. ANEURALNETWORKS_CAST
+        nn_type = ANEURALNETWORKS_TENSOR_QUANT8_ASYMM;
+        scale = tensor->params.scale;
+        // ANEURALNETWORKS_TENSOR_QUANT8_ASYMM type requires scale > 0,
+        // zeroPoint >= 0 and zeroPoint <= 255
+        scale = (scale == 0.0f) ? 1.0f : scale;
+        zeroPoint = tensor->params.zero_point;
+        break;
+      case kTfLiteInt32:
+        nn_type = ANEURALNETWORKS_TENSOR_INT32;
+        scale = tensor->params.scale;
+        zeroPoint = tensor->params.zero_point;
+        break;
+      case kTfLiteBool:
+        // Workaround to pass bool type under NNAPI
+        // Use bool type using ANEURALNETWORKS_TENSOR_QUANT8_ASYMM with scale = 1.0f and zero_point = 0
+        nn_type = ANEURALNETWORKS_TENSOR_QUANT8_ASYMM;
+        scale = 1.0f;
+        zeroPoint = 0;
+        break;
+      default:
+        logError("Unsupported tensor type %d", tensor->type);
+        return kTfLiteError;
+    }
+    if (tensor->dims->size == 0) {
+      // WORKAROUND Some model have dimension zero
+      switch (tensor->type) {
+        case kTfLiteFloat32:
+          nn_type = ANEURALNETWORKS_TENSOR_FLOAT32;
+          break;
+        case kTfLiteInt32:
+          nn_type = ANEURALNETWORKS_TENSOR_INT32;
+          break;
+        default:
+          logError("NNAPI doesn't support tensors with rank 0 (index %d name %s)",
+                   i, tensor->name);
+          return kTfLiteError;
+      }
+    }
+    if (tensor->dims->size > 4) {
+      logError("NNAPI doesn't support tensors with rank > 4 (index %d name %s)",
+               i, tensor->name);
+      return kTfLiteError;
+    }
+    // TODO(aselle): Note, many of these are intermediate results. Do I need
+    // to ever specify these sizes. I am currently below doing setValue
+    // on all of them, but I shouldn't in the future.
+    // Answer(jeanluc): If all the operators can set the dimension correctly,
+    // you won't need to.
+    ANeuralNetworksOperandType operand_type{
+        nn_type, static_cast<uint32_t>(tensor->dims->size),
+        reinterpret_cast<uint32_t*>(tensor->dims->data), scale, zeroPoint};
+    if (tensor->dims->size == 0) {
+      // WORKAROUND Some model have dimension zero
+      // Consider scalar as vector size 1
+      operand_type.dimensions = dimension_for_scalar;
+      operand_type.dimensionCount = 1;
+    }
+    RETURN_ERROR_IF_NN_FAILED(
+        ANeuralNetworksModel_addOperand(nn_model, &operand_type));
+    // TODO(aselle): Based on Michael's suggestion, limiting this to read
+    // only memory
+    if (tensor->allocation_type == kTfLiteMmapRo) {
+      if (const NNAPIAllocation* alloc = dynamic_cast<const NNAPIAllocation*>(
+              static_cast<const ::tflite::Allocation*>(tensor->allocation))) {
+        RETURN_ERROR_IF_NN_FAILED(
+            ANeuralNetworksModel_setOperandValueFromMemory(
+                nn_model, next_id, alloc->memory(),
+                alloc->offset(tensor->data.raw), tensor->bytes));
+      } else {
+        RETURN_ERROR_IF_NN_FAILED(ANeuralNetworksModel_setOperandValue(
+            nn_model, next_id, tensor->data.raw, tensor->bytes));
+      }
+    } else if (tensor->bytes == 0) {
+      // These size 0 tensors are optional tensors reserved.
+      RETURN_ERROR_IF_NN_FAILED(
+          ANeuralNetworksModel_setOperandValue(nn_model, next_id, nullptr, 0));
+    }
+
+    ++next_id;
+  }
+  *no_of_operands_added = next_id;
+  return kTfLiteOk;
+}
+
+void MapAndAddTensorIds(const int* from_ids_buf, size_t from_ids_count,
+                        std::vector<uint32_t>* into,
+                        const std::vector<int64_t>& map) {
+  for (size_t i = 0; i < from_ids_count; i++) {
+    int from_id = from_ids_buf[i];
+    if (from_id == kOptionalTensor) {
+      into->push_back(from_id);
+    } else {
+      into->push_back(map[from_id]);
+    }
+  }
+}
+
+// Adds the operations and their parameters to the NN API model.
+// 'next-id' is the operand ID of the next operand of the model.
+TfLiteStatus AddOpsAndParams(
+    ::tflite::Subgraph* subgraph, ANeuralNetworksModel* nn_model,
+    uint32_t next_id, std::vector<int>* model_state_inputs,
+    std::vector<int>* model_state_outputs,
+    const std::vector<int64_t>& tensor_id_to_nnapi_id) {
+  for (size_t i = 0; i < subgraph->nodes_size(); i++) {
+    const auto* node_and_registration = subgraph->node_and_registration(i);
+    const TfLiteNode& node = node_and_registration->first;
+    const TfLiteRegistration& registration = node_and_registration->second;
+    ::tflite::BuiltinOperator builtin =
+        static_cast<::tflite::BuiltinOperator>(registration.builtin_code);
+
+    // Add the parameters.
+    std::vector<uint32_t> augmented_inputs, augmented_outputs;
+    MapAndAddTensorIds(node.inputs->data, node.inputs->size, &augmented_inputs,
+                       tensor_id_to_nnapi_id);
+    MapAndAddTensorIds(node.outputs->data, node.outputs->size,
+                       &augmented_outputs, tensor_id_to_nnapi_id);
+
+    auto add_scalar_int32 = [&nn_model, &augmented_inputs,
+                             &next_id](int value) {
+      // Fix to use strict build option
+      ANeuralNetworksOperandType operand_type{}; operand_type.type = ANEURALNETWORKS_INT32;
+      CHECK_NN(ANeuralNetworksModel_addOperand(nn_model, &operand_type))
+      CHECK_NN(ANeuralNetworksModel_setOperandValue(nn_model, next_id, &value,
+                                                    sizeof(int32_t)))
+      augmented_inputs.push_back(next_id++);
+    };
+
+    auto add_scalar_float32 = [&nn_model, &augmented_inputs,
+                               &next_id](float value) {
+      // Fix to use strict build option
+      ANeuralNetworksOperandType operand_type{}; operand_type.type = ANEURALNETWORKS_FLOAT32;
+      CHECK_NN(ANeuralNetworksModel_addOperand(nn_model, &operand_type))
+      CHECK_NN(ANeuralNetworksModel_setOperandValue(nn_model, next_id, &value,
+                                                    sizeof(float)))
+      augmented_inputs.push_back(next_id++);
+    };
+
+    auto add_vector_int32 = [&](const int* values, uint32_t num_values) {
+      // Fix to use strict build option
+      ANeuralNetworksOperandType operand_type{};
+      operand_type.type = ANEURALNETWORKS_TENSOR_INT32;
+      operand_type.dimensionCount = 1;
+      operand_type.dimensions = &num_values;
+      CHECK_NN(ANeuralNetworksModel_addOperand(nn_model, &operand_type))
+      CHECK_NN(ANeuralNetworksModel_setOperandValue(
+          nn_model, next_id, values, sizeof(int32_t) * num_values));
+      augmented_inputs.push_back(next_id++);
+    };
+
+    // Handle state tensors of RNN, LSTM, SVDF.
+    // For each state_out tensor, a corresponding state_in operand needs to be
+    // created for NNAPI.
+    auto duplicate_state_tensor_float32 =
+        [subgraph, &nn_model, &next_id, &augmented_inputs, &model_state_inputs,
+         &model_state_outputs](int tensor_id) {
+          const TfLiteTensor* tensor = subgraph->tensor(tensor_id);
+          ANeuralNetworksOperandType operand_type{
+              ANEURALNETWORKS_TENSOR_FLOAT32,
+              static_cast<uint32_t>(tensor->dims->size),
+              reinterpret_cast<uint32_t*>(tensor->dims->data),
+              tensor->params.scale, tensor->params.zero_point};
+          CHECK_NN(ANeuralNetworksModel_addOperand(nn_model, &operand_type));
+          augmented_inputs.push_back(next_id);
+          model_state_inputs->push_back(next_id);
+          model_state_outputs->push_back(tensor_id);
+          next_id++;
+        };
+    auto check_and_add_activation = [&add_scalar_int32](int activation) {
+      if (activation > kTfLiteActRelu6) {
+        logError("NNAPI only supports RELU, RELU1 and RELU6 activations");
+        return kTfLiteError;
+      }
+      add_scalar_int32(activation);
+      return kTfLiteOk;
+    };
+
+    auto add_add_params = [&add_scalar_int32](void* data) {
+      auto* builtin = reinterpret_cast<TfLiteAddParams*>(data);
+      if (builtin->activation > kTfLiteActRelu6) {
+        logError("NNAPI only supports RELU, RELU1 and RELU6 activations");
+        return kTfLiteError;
+      }
+      add_scalar_int32(builtin->activation);
+      return kTfLiteOk;
+    };
+
+    auto add_pooling_params = [&add_scalar_int32,
+                               &check_and_add_activation](void* data) {
+      auto builtin = reinterpret_cast<TfLitePoolParams*>(data);
+      add_scalar_int32(builtin->padding);
+      add_scalar_int32(builtin->stride_width);
+      add_scalar_int32(builtin->stride_height);
+      add_scalar_int32(builtin->filter_width);
+      add_scalar_int32(builtin->filter_height);
+      return check_and_add_activation(builtin->activation);
+    };
+
+    auto add_convolution_params = [&add_scalar_int32,
+                                   &check_and_add_activation](void* data) {
+      auto builtin = reinterpret_cast<TfLiteConvParams*>(data);
+      add_scalar_int32(builtin->padding);
+      add_scalar_int32(builtin->stride_width);
+      add_scalar_int32(builtin->stride_height);
+      return check_and_add_activation(builtin->activation);
+    };
+
+    auto add_depthwise_conv_params = [&add_scalar_int32,
+                                      &check_and_add_activation](void* data) {
+      auto builtin = reinterpret_cast<TfLiteDepthwiseConvParams*>(data);
+      add_scalar_int32(builtin->padding);
+      add_scalar_int32(builtin->stride_width);
+      add_scalar_int32(builtin->stride_height);
+      add_scalar_int32(builtin->depth_multiplier);
+      return check_and_add_activation(builtin->activation);
+    };
+
+    auto add_fully_connected_params = [&check_and_add_activation](void* data) {
+      auto builtin = reinterpret_cast<TfLiteFullyConnectedParams*>(data);
+      return check_and_add_activation(builtin->activation);
+    };
+
+    auto add_concatenation_params = [&add_scalar_int32](void* data) {
+      auto builtin = reinterpret_cast<TfLiteConcatenationParams*>(data);
+      add_scalar_int32(builtin->axis);
+      if (builtin->activation != kTfLiteActNone) {
+        logError("Concatenation does not support fused activation in NNAPI");
+        return kTfLiteError;
+      }
+      return kTfLiteOk;
+    };
+
+    auto add_softmax_params = [&add_scalar_float32](void* data) {
+      auto builtin = reinterpret_cast<TfLiteSoftmaxParams*>(data);
+      add_scalar_float32(builtin->beta);
+    };
+
+    auto add_space_to_depth_params = [&add_scalar_int32](void* data) {
+      auto builtin = reinterpret_cast<TfLiteSpaceToDepthParams*>(data);
+      add_scalar_int32(builtin->block_size);
+    };
+
+    auto add_lstm_params = [&add_scalar_int32,
+                            &add_scalar_float32](void* data) {
+      auto builtin = reinterpret_cast<TfLiteLSTMParams*>(data);
+      add_scalar_int32(builtin->activation);
+      add_scalar_float32(builtin->cell_clip);
+      add_scalar_float32(builtin->proj_clip);
+    };
+
+    // LSTM in NNAPI requires scratch tensor as an output operand.
+    auto add_lstm_scratch_tensor_float32 = [subgraph, &node, &nn_model,
+                                            &next_id, &augmented_outputs]() {
+      if (node.temporaries->size == 0) return;
+      int scratch_buffer_index = node.temporaries->data[0];
+      const TfLiteTensor* tensor = subgraph->tensor(scratch_buffer_index);
+      ANeuralNetworksOperandType operand_type{
+          ANEURALNETWORKS_TENSOR_FLOAT32,
+          static_cast<uint32_t>(tensor->dims->size),
+          reinterpret_cast<uint32_t*>(tensor->dims->data), tensor->params.scale,
+          tensor->params.zero_point};
+      CHECK_NN(ANeuralNetworksModel_addOperand(nn_model, &operand_type));
+      augmented_outputs.insert(augmented_outputs.begin(), next_id++);
+    };
+
+    auto add_mean_params = [&add_scalar_int32](void* data) {
+      auto builtin = reinterpret_cast<TfLiteReducerParams*>(data);
+      add_scalar_int32(builtin->keep_dims);
+    };
+
+    auto add_svdf_params = [&add_scalar_int32](void* data) {
+      auto builtin = reinterpret_cast<TfLiteSVDFParams*>(data);
+      add_scalar_int32(builtin->rank);
+      add_scalar_int32(builtin->activation);
+    };
+
+    auto add_rnn_params = [&add_scalar_int32](void* data) {
+      auto builtin = reinterpret_cast<TfLiteRNNParams*>(data);
+      add_scalar_int32(builtin->activation);
+    };
+
+    auto add_squeeze_params = [&](void* data) {
+      const auto* builtin = reinterpret_cast<TfLiteSqueezeParams*>(data);
+      // Note that we add the squeeze dimensions even if the dimensions were
+      // unspecified (empty), as NNAPI requires the operand.
+      add_vector_int32(builtin->squeeze_dims,
+                       static_cast<uint32_t>(builtin->num_squeeze_dims));
+    };
+
+    // Handle optional input tensors.
+    auto add_optional_tensors = [&nn_model, &augmented_inputs,
+                                 &next_id](int nn_type) {
+      for (size_t idx = 0; idx < augmented_inputs.size(); idx++) {
+        // Fix to use strict build option
+        if (augmented_inputs[idx] == static_cast<uint32_t>(kOptionalTensor)) {
+          const std::vector<uint32_t> dim = {0, 0};
+          ANeuralNetworksOperandType operand_type{nn_type, 2, dim.data(), 0, 0};
+          CHECK_NN(ANeuralNetworksModel_addOperand(nn_model, &operand_type))
+          CHECK_NN(ANeuralNetworksModel_setOperandValue(nn_model, next_id,
+                                                        nullptr, 0))
+          augmented_inputs[idx] = next_id++;
+        }
+      }
+    };
+
+    int nnapi_version = 10;
+#include "nnapi_delegate_ex_AddOpsAndParams_lambda.inc"
+
+    // Fix to use strict build option
+    ANeuralNetworksOperationType nn_op_type = -1;
+
+    // Using namespace directive to minimize diff with upstream tensorflow
+    namespace tflite = ::tflite;
+
+    switch (builtin) {
+      case tflite::BuiltinOperator_ADD:
+        nn_op_type = ANEURALNETWORKS_ADD;
+        RETURN_ERROR_IF_TFLITE_FAILED(add_add_params(node.builtin_data));
+        break;
+      case tflite::BuiltinOperator_MUL:
+        nn_op_type = ANEURALNETWORKS_MUL;
+        RETURN_ERROR_IF_TFLITE_FAILED(add_add_params(node.builtin_data));
+        break;
+      case tflite::BuiltinOperator_AVERAGE_POOL_2D:
+        RETURN_ERROR_IF_TFLITE_FAILED(add_pooling_params(node.builtin_data));
+        nn_op_type = ANEURALNETWORKS_AVERAGE_POOL_2D;
+        break;
+      case tflite::BuiltinOperator_MAX_POOL_2D:
+        RETURN_ERROR_IF_TFLITE_FAILED(add_pooling_params(node.builtin_data));
+        nn_op_type = ANEURALNETWORKS_MAX_POOL_2D;
+        break;
+      case tflite::BuiltinOperator_L2_POOL_2D:
+        RETURN_ERROR_IF_TFLITE_FAILED(add_pooling_params(node.builtin_data));
+        nn_op_type = ANEURALNETWORKS_L2_POOL_2D;
+        break;
+      case tflite::BuiltinOperator_CONV_2D: {
+        auto builtin = reinterpret_cast<TfLiteConvParams*>(node.builtin_data);
+        if (builtin->dilation_width_factor != 1 ||
+            builtin->dilation_height_factor != 1 || node.inputs->size != 3) {
+          logError("NNAPI does not support dilated Conv2D.");
+          return kTfLiteError;
+        }
+      }
+        RETURN_ERROR_IF_TFLITE_FAILED(
+            add_convolution_params(node.builtin_data));
+        nn_op_type = ANEURALNETWORKS_CONV_2D;
+        break;
+      case tflite::BuiltinOperator_RELU:
+        nn_op_type = ANEURALNETWORKS_RELU;
+        break;
+      case tflite::BuiltinOperator_RELU_N1_TO_1:
+        nn_op_type = ANEURALNETWORKS_RELU1;
+        break;
+      case tflite::BuiltinOperator_RELU6:
+        nn_op_type = ANEURALNETWORKS_RELU6;
+        break;
+      case tflite::BuiltinOperator_TANH:
+        nn_op_type = ANEURALNETWORKS_TANH;
+        break;
+      case tflite::BuiltinOperator_FLOOR:
+        nn_op_type = ANEURALNETWORKS_FLOOR;
+        break;
+      case tflite::BuiltinOperator_LOGISTIC:
+        nn_op_type = ANEURALNETWORKS_LOGISTIC;
+        break;
+      case tflite::BuiltinOperator_DEPTHWISE_CONV_2D:
+        RETURN_ERROR_IF_TFLITE_FAILED(
+            add_depthwise_conv_params(node.builtin_data));
+        nn_op_type = ANEURALNETWORKS_DEPTHWISE_CONV_2D;
+        break;
+      case tflite::BuiltinOperator_CONCATENATION:
+        RETURN_ERROR_IF_TFLITE_FAILED(
+            add_concatenation_params(node.builtin_data));
+        nn_op_type = ANEURALNETWORKS_CONCATENATION;
+        break;
+      case tflite::BuiltinOperator_SOFTMAX:
+        add_softmax_params(node.builtin_data);
+        nn_op_type = ANEURALNETWORKS_SOFTMAX;
+        break;
+      case tflite::BuiltinOperator_FULLY_CONNECTED:
+        RETURN_ERROR_IF_TFLITE_FAILED(
+            add_fully_connected_params(node.builtin_data));
+        nn_op_type = ANEURALNETWORKS_FULLY_CONNECTED;
+        break;
+      case tflite::BuiltinOperator_RESHAPE:
+        if (node.inputs->size != 2) {
+          logError("NNAPI only supports 2-input RESHAPE");
+          return kTfLiteError;
+        }
+        nn_op_type = ANEURALNETWORKS_RESHAPE;
+        // add_reshape_params(node.builtin_data);
+        break;
+      case tflite::BuiltinOperator_RESIZE_BILINEAR:
+        add_resize_bilinear_params(node.builtin_data);
+        nn_op_type = ANEURALNETWORKS_RESIZE_BILINEAR;
+        break;
+      case tflite::BuiltinOperator_SPACE_TO_DEPTH:
+        add_space_to_depth_params(node.builtin_data);
+        nn_op_type = ANEURALNETWORKS_SPACE_TO_DEPTH;
+        break;
+      case tflite::BuiltinOperator_LSTM: {
+        if (node.inputs->size + /* no of params */ 3 != 21) {
+          logError("NNAPI only supports 21-input LSTMs");
+          return kTfLiteError;
+        }
+        duplicate_state_tensor_float32(
+            node.outputs->data[/*kOutputStateTensor*/ 0]);
+        duplicate_state_tensor_float32(
+            node.outputs->data[/*kCellStateTensor*/ 1]);
+        add_lstm_params(node.builtin_data);
+        add_lstm_scratch_tensor_float32();
+        add_optional_tensors(ANEURALNETWORKS_TENSOR_FLOAT32);
+        nn_op_type = ANEURALNETWORKS_LSTM;
+        break;
+      }
+      case tflite::BuiltinOperator_DEQUANTIZE:
+        nn_op_type = ANEURALNETWORKS_DEQUANTIZE;
+        break;
+      case tflite::BuiltinOperator_SVDF: {
+        duplicate_state_tensor_float32(node.outputs->data[/*kStateTensor*/ 0]);
+        add_svdf_params(node.builtin_data);
+        nn_op_type = ANEURALNETWORKS_SVDF;
+        break;
+      }
+      case tflite::BuiltinOperator_RNN: {
+        duplicate_state_tensor_float32(
+            node.outputs->data[/*kHiddenStateTensor*/ 0]);
+        add_rnn_params(node.builtin_data);
+        nn_op_type = ANEURALNETWORKS_RNN;
+        break;
+      }
+      case tflite::BuiltinOperator_EMBEDDING_LOOKUP:
+        nn_op_type = ANEURALNETWORKS_EMBEDDING_LOOKUP;
+        break;
+      case tflite::BuiltinOperator_PAD:
+        nnapi_version = 11;  // require NNAPI 1.1
+        nn_op_type = ANEURALNETWORKS_PAD;
+        break;
+      case tflite::BuiltinOperator_MEAN:
+        nnapi_version = 11;  // require NNAPI 1.1
+        add_mean_params(node.builtin_data);
+        nn_op_type = ANEURALNETWORKS_MEAN;
+        break;
+      case tflite::BuiltinOperator_LOCAL_RESPONSE_NORMALIZATION:
+        nn_op_type = ANEURALNETWORKS_LOCAL_RESPONSE_NORMALIZATION;
+        add_lrn_params(node.builtin_data);
+        break;
+      case tflite::BuiltinOperator_DIV:
+        nnapi_version = 11;  // require NNAPI 1.1
+        nn_op_type = ANEURALNETWORKS_DIV;
+        RETURN_ERROR_IF_TFLITE_FAILED(check_and_add_activation(
+            reinterpret_cast<TfLiteDivParams*>(node.builtin_data)->activation));
+        break;
+      case tflite::BuiltinOperator_SUB:
+        nnapi_version = 11;  // require NNAPI 1.1
+        nn_op_type = ANEURALNETWORKS_SUB;
+        RETURN_ERROR_IF_TFLITE_FAILED(check_and_add_activation(
+            reinterpret_cast<TfLiteSubParams*>(node.builtin_data)->activation));
+        break;
+      case tflite::BuiltinOperator_SQUEEZE:
+        nnapi_version = 11;  // requires NNAPI 1.1
+        add_squeeze_params(node.builtin_data);
+        nn_op_type = ANEURALNETWORKS_SQUEEZE;
+        break;
+      case tflite::BuiltinOperator_TRANSPOSE:
+        // The permutation input tensor value dictates the output dimensions.
+        // TODO(b/110888333): Support dynamically-sized tensors in delegates.
+        if ((node.inputs->size > 1) &&
+            (subgraph->tensor(node.inputs->data[1])->allocation_type !=
+             kTfLiteMmapRo)) {
+          logError("NNAPI does not yet support dynamic tensors.");
+          return kTfLiteError;
+        }
+        nnapi_version = 11;  // require NNAPI 1.1
+        nn_op_type = ANEURALNETWORKS_TRANSPOSE;
+        break;
+      case tflite::BuiltinOperator_L2_NORMALIZATION:
+        nn_op_type = ANEURALNETWORKS_L2_NORMALIZATION;
+        if (reinterpret_cast<TfLiteL2NormParams*>(node.builtin_data)
+                ->activation != kTfLiteActNone) {
+          logError(
+              "NNAPI does not support L2Normalization with fused activations");
+          return kTfLiteError;
+        }
+        if ((node.inputs->size > 0) &&
+            (subgraph->tensor(node.inputs->data[0])->dims->size != 4)) {
+          logError("NNAPI only supports input rank 4 for L2Normalization");
+          return kTfLiteError;
+        }
+        break;
+      case tflite::BuiltinOperator_HASHTABLE_LOOKUP:
+        if (subgraph->tensor(node.outputs->data[0])->type != kTfLiteFloat32) {
+          logError("NNAPI only support HASHTABLE_LOOKUP with float32 output",
+                   builtin);
+          return kTfLiteError;
+        }
+        nn_op_type = ANEURALNETWORKS_HASHTABLE_LOOKUP;
+        break;
+      case tflite::BuiltinOperator_SLICE:
+        nn_op_type = ANEURALNETWORKS_SLICE;
+        break;
+      case tflite::BuiltinOperator_STRIDED_SLICE:
+        add_strided_slice_params(node.builtin_data);
+        nn_op_type = ANEURALNETWORKS_STRIDED_SLICE;
+        break;
+      case tflite::BuiltinOperator_SPACE_TO_BATCH_ND:
+        nnapi_version = 11;  // require NNAPI 1.1
+        nn_op_type = ANEURALNETWORKS_SPACE_TO_BATCH_ND;
+        break;
+      case tflite::BuiltinOperator_BATCH_TO_SPACE_ND:
+        nnapi_version = 11;  // require NNAPI 1.1
+        nn_op_type = ANEURALNETWORKS_BATCH_TO_SPACE_ND;
+        check_batch_to_space_params();
+        break;
+      case tflite::BuiltinOperator_CAST:
+        nnapi_version = 12;  // require NNAPI 1.2
+        nn_op_type = ANEURALNETWORKS_CAST;
+        break;
+      case tflite::BuiltinOperator_TOPK_V2:
+        nnapi_version = 12;  // require NNAPI 1.2
+        nn_op_type = ANEURALNETWORKS_TOPK_V2;
+        break;
+      case tflite::BuiltinOperator_GATHER:
+        nnapi_version = 12;  // require NNAPI 1.2
+        nn_op_type = ANEURALNETWORKS_GATHER;
+        add_gather_params(node.builtin_data);
+        break;
+      case tflite::BuiltinOperator_SPLIT:
+        add_split_params(node.builtin_data);
+        CHECK_NN(ANeuralNetworksModel_addOperationEx(
+            nn_model, ANEURALNETWORKS_SPLIT_EX,
+            static_cast<uint32_t>(augmented_inputs.size()),
+            augmented_inputs.data(), static_cast<uint32_t>(node.outputs->size),
+            reinterpret_cast<uint32_t*>(node.outputs->data)));
+        continue;
+      case tflite::BuiltinOperator_NEG:
+        nnapi_version = 12;  // require NNAPI 1.2
+        nn_op_type = ANEURALNETWORKS_NEG;
+        break;
+      case tflite::BuiltinOperator_EXP:
+        nnapi_version = 12;  // require NNAPI 1.2
+        nn_op_type = ANEURALNETWORKS_EXP;
+        break;
+      case tflite::BuiltinOperator_TRANSPOSE_CONV:
+        add_transpose_conv_params(node.builtin_data);
+        CHECK_NN(ANeuralNetworksModel_addOperationEx(
+            nn_model, ANEURALNETWORKS_TRANSPOSE_CONV_EX,
+            static_cast<uint32_t>(augmented_inputs.size()),
+            augmented_inputs.data(), static_cast<uint32_t>(node.outputs->size),
+            reinterpret_cast<uint32_t*>(node.outputs->data)));
+        continue;
+      case tflite::BuiltinOperator_PRELU:
+        CHECK_NN(ANeuralNetworksModel_addOperationEx(
+            nn_model, ANEURALNETWORKS_PRELU_EX,
+            static_cast<uint32_t>(augmented_inputs.size()),
+            augmented_inputs.data(),
+            static_cast<uint32_t>(node.outputs->size),
+            reinterpret_cast<uint32_t*>(node.outputs->data)));
+        continue;
+      case tflite::BuiltinOperator_ARG_MAX:
+        check_arg_max_input(node.builtin_data);
+        CHECK_NN(ANeuralNetworksModel_addOperationEx(
+            nn_model, ANEURALNETWORKS_ARGMAX_EX,
+            static_cast<uint32_t>(augmented_inputs.size()),
+            augmented_inputs.data(), static_cast<uint32_t>(node.outputs->size),
+            reinterpret_cast<uint32_t*>(node.outputs->data)));
+        continue;
+      case tflite::BuiltinOperator_PACK:
+        add_pack_ex_params(node.builtin_data);
+        CHECK_NN(ANeuralNetworksModel_addOperationEx(
+            nn_model, ANEURALNETWORKS_PACK_EX,
+            static_cast<uint32_t>(augmented_inputs.size()),
+            augmented_inputs.data(), static_cast<uint32_t>(node.outputs->size),
+            reinterpret_cast<uint32_t*>(node.outputs->data)));
+        continue;
+      case tflite::BuiltinOperator_UNPACK:
+        add_unpack_ex_params(node.builtin_data);
+        CHECK_NN(ANeuralNetworksModel_addOperationEx(
+            nn_model, ANEURALNETWORKS_UNPACK_EX,
+            static_cast<uint32_t>(augmented_inputs.size()),
+            augmented_inputs.data(), static_cast<uint32_t>(node.outputs->size),
+            reinterpret_cast<uint32_t*>(node.outputs->data)));
+        continue;
+      case tflite::BuiltinOperator_SQRT:
+        nnapi_version = 12;  // require NNAPI 1.2
+        nn_op_type = ANEURALNETWORKS_SQRT;
+        break;
+      case tflite::BuiltinOperator_RSQRT:
+        nnapi_version = 12;  // require NNAPI 1.2
+        nn_op_type = ANEURALNETWORKS_RSQRT;
+        break;
+      case tflite::BuiltinOperator_EQUAL:
+        CHECK_NN(ANeuralNetworksModel_addOperationEx(
+            nn_model, ANEURALNETWORKS_EQUAL_EX,
+            static_cast<uint32_t>(augmented_inputs.size()),
+            augmented_inputs.data(), static_cast<uint32_t>(node.outputs->size),
+            reinterpret_cast<uint32_t*>(node.outputs->data)));
+        continue;
+      case tflite::BuiltinOperator_NOT_EQUAL:
+        CHECK_NN(ANeuralNetworksModel_addOperationEx(
+            nn_model, ANEURALNETWORKS_NOT_EQUAL_EX,
+            static_cast<uint32_t>(augmented_inputs.size()),
+            augmented_inputs.data(), static_cast<uint32_t>(node.outputs->size),
+            reinterpret_cast<uint32_t*>(node.outputs->data)));
+        continue;
+      case tflite::BuiltinOperator_SUM:
+        add_reducer_params(node.builtin_data);
+        CHECK_NN(ANeuralNetworksModel_addOperationEx(
+            nn_model, ANEURALNETWORKS_REDUCE_SUM_EX,
+            static_cast<uint32_t>(augmented_inputs.size()),
+            augmented_inputs.data(),
+            static_cast<uint32_t>(node.outputs->size),
+            reinterpret_cast<uint32_t*>(node.outputs->data)));
+        continue;
+      case tflite::BuiltinOperator_REDUCE_MAX:
+        add_reducer_v12_params(node.builtin_data);
+        nnapi_version = 12;  // require NNAPI 1.2
+        nn_op_type = ANEURALNETWORKS_REDUCE_MAX;
+        break;
+      case tflite::BuiltinOperator_REDUCE_MIN:
+        add_reducer_params(node.builtin_data);
+        CHECK_NN(ANeuralNetworksModel_addOperationEx(
+            nn_model, ANEURALNETWORKS_REDUCE_MIN_EX,
+            static_cast<uint32_t>(augmented_inputs.size()),
+            augmented_inputs.data(),
+            static_cast<uint32_t>(node.outputs->size),
+            reinterpret_cast<uint32_t*>(node.outputs->data)));
+        continue;
+      case tflite::BuiltinOperator_LOGICAL_AND:
+        CHECK_NN(ANeuralNetworksModel_addOperationEx(
+            nn_model, ANEURALNETWORKS_LOGICAL_AND_EX,
+            static_cast<uint32_t>(augmented_inputs.size()),
+            augmented_inputs.data(),
+            static_cast<uint32_t>(node.outputs->size),
+            reinterpret_cast<uint32_t*>(node.outputs->data)));
+        continue;
+      case tflite::BuiltinOperator_LOGICAL_OR:
+        CHECK_NN(ANeuralNetworksModel_addOperationEx(
+            nn_model, ANEURALNETWORKS_LOGICAL_OR_EX,
+            static_cast<uint32_t>(augmented_inputs.size()),
+            augmented_inputs.data(),
+            static_cast<uint32_t>(node.outputs->size),
+            reinterpret_cast<uint32_t*>(node.outputs->data)));
+        continue;
+      case tflite::BuiltinOperator_LOGICAL_NOT:
+        CHECK_NN(ANeuralNetworksModel_addOperationEx(
+            nn_model, ANEURALNETWORKS_LOGICAL_NOT_EX,
+            static_cast<uint32_t>(augmented_inputs.size()),
+            augmented_inputs.data(),
+            static_cast<uint32_t>(node.outputs->size),
+            reinterpret_cast<uint32_t*>(node.outputs->data)));
+        continue;
+      case tflite::BuiltinOperator_SQUARED_DIFFERENCE:
+        CHECK_NN(ANeuralNetworksModel_addOperationEx(
+            nn_model, ANEURALNETWORKS_SQUARED_DIFFERENCE_EX,
+            static_cast<uint32_t>(augmented_inputs.size()),
+            augmented_inputs.data(),
+            static_cast<uint32_t>(node.outputs->size),
+            reinterpret_cast<uint32_t*>(node.outputs->data)));
+        continue;
+      case tflite::BuiltinOperator_MAXIMUM:
+        nn_op_type = ANEURALNETWORKS_MAXIMUM;
+        break;
+      case tflite::BuiltinOperator_MINIMUM:
+        nn_op_type = ANEURALNETWORKS_MINIMUM;
+        break;
+      case tflite::BuiltinOperator_ABS:
+        nnapi_version = 12;  // require NNAPI 1.2
+        nn_op_type = ANEURALNETWORKS_ABS;
+        break;
+      case tflite::BuiltinOperator_CONCAT_EMBEDDINGS:
+      case tflite::BuiltinOperator_LSH_PROJECTION:
+      case tflite::BuiltinOperator_BIDIRECTIONAL_SEQUENCE_RNN:
+      case tflite::BuiltinOperator_UNIDIRECTIONAL_SEQUENCE_RNN:
+      case tflite::BuiltinOperator_EMBEDDING_LOOKUP_SPARSE:
+      case tflite::BuiltinOperator_BIDIRECTIONAL_SEQUENCE_LSTM:
+      case tflite::BuiltinOperator_UNIDIRECTIONAL_SEQUENCE_LSTM:
+      //case tflite::BuiltinOperator_LOCAL_RESPONSE_NORMALIZATION:
+      case tflite::BuiltinOperator_PADV2:
+      //case tflite::BuiltinOperator_RESIZE_BILINEAR:
+      case tflite::BuiltinOperator_RESIZE_NEAREST_NEIGHBOR:
+      case tflite::BuiltinOperator_CALL:
+      case tflite::BuiltinOperator_SKIP_GRAM:
+      //case tflite::BuiltinOperator_RELU_N1_TO_1:
+      //case tflite::BuiltinOperator_GATHER:
+      //case tflite::BuiltinOperator_SPACE_TO_BATCH_ND:
+      //case tflite::BuiltinOperator_BATCH_TO_SPACE_ND:
+      //case tflite::BuiltinOperator_TOPK_V2:
+      //case tflite::BuiltinOperator_SPLIT:
+      //case tflite::BuiltinOperator_STRIDED_SLICE:
+      //case tflite::BuiltinOperator_EXP:
+      case tflite::BuiltinOperator_LOG_SOFTMAX:
+      //case tflite::BuiltinOperator_DEQUANTIZE:
+      case tflite::BuiltinOperator_DELEGATE:
+      //case tflite::BuiltinOperator_CAST:
+      //case tflite::BuiltinOperator_PRELU:
+      //case tflite::BuiltinOperator_MAXIMUM:
+      //case tflite::BuiltinOperator_MINIMUM:
+      //case tflite::BuiltinOperator_ARG_MAX:
+      case tflite::BuiltinOperator_ARG_MIN:
+      case tflite::BuiltinOperator_GREATER:
+      case tflite::BuiltinOperator_GREATER_EQUAL:
+      case tflite::BuiltinOperator_LESS:
+      case tflite::BuiltinOperator_LESS_EQUAL:
+      //case tflite::BuiltinOperator_NEG:
+      case tflite::BuiltinOperator_SELECT:
+      // case tflite::BuiltinOperator_SLICE:
+      case tflite::BuiltinOperator_SIN:
+      case tflite::BuiltinOperator_LOG:
+      //case tflite::BuiltinOperator_TRANSPOSE_CONV:
+      case tflite::BuiltinOperator_TILE:
+      case tflite::BuiltinOperator_EXPAND_DIMS:
+      case tflite::BuiltinOperator_SPARSE_TO_DENSE:
+      //case tflite::BuiltinOperator_EQUAL:
+      //case tflite::BuiltinOperator_NOT_EQUAL:
+      //case tflite::BuiltinOperator_SUM:
+      //case tflite::BuiltinOperator_REDUCE_MAX:
+      //case tflite::BuiltinOperator_REDUCE_MIN:
+      case tflite::BuiltinOperator_REDUCE_PROD:
+      //case tflite::BuiltinOperator_SQRT:
+      //case tflite::BuiltinOperator_RSQRT:
+      case tflite::BuiltinOperator_SHAPE:
+      case tflite::BuiltinOperator_POW:
+      case tflite::BuiltinOperator_FAKE_QUANT:
+      //case tflite::BuiltinOperator_PACK:
+      //case tflite::BuiltinOperator_LOGICAL_OR:
+      case tflite::BuiltinOperator_ONE_HOT:
+      //case tflite::BuiltinOperator_LOGICAL_AND:
+      //case tflite::BuiltinOperator_LOGICAL_NOT:
+      //case tflite::BuiltinOperator_UNPACK:
+      case tflite::BuiltinOperator_FLOOR_DIV:
+      case tflite::BuiltinOperator_REDUCE_ANY:
+      case tflite::BuiltinOperator_SQUARE:
+      case tflite::BuiltinOperator_ZEROS_LIKE:
+      case tflite::BuiltinOperator_FILL:
+      case tflite::BuiltinOperator_FLOOR_MOD:
+      case tflite::BuiltinOperator_RANGE:
+      case tflite::BuiltinOperator_LEAKY_RELU:
+      //case tflite::BuiltinOperator_SQUARED_DIFFERENCE:
+      case tflite::BuiltinOperator_MIRROR_PAD:
+      //case tflite::BuiltinOperator_ABS:
+      case tflite::BuiltinOperator_SPLIT_V:
+        logError("Op code %d is currently not delegated to NNAPI", builtin);
+        return kTfLiteError;
+        break;
+      case tflite::BuiltinOperator_CUSTOM: {
+        std::string custom_name(registration.custom_name);
+        if (custom_name.compare("TensorFlowMax") == 0) {
+          add_reducer_v12_params(node.builtin_data);
+          nnapi_version = 12;  // require NNAPI 1.2
+          nn_op_type = ANEURALNETWORKS_REDUCE_MAX;
+          break;
+        }
+        else if (custom_name.compare("SquaredDifference") == 0) {
+          CHECK_NN(ANeuralNetworksModel_addOperationEx(
+              nn_model, ANEURALNETWORKS_SQUARED_DIFFERENCE_EX,
+              static_cast<uint32_t>(augmented_inputs.size()),
+              augmented_inputs.data(),
+              static_cast<uint32_t>(node.outputs->size),
+              reinterpret_cast<uint32_t*>(node.outputs->data)));
+          continue;
+        }
+        else if (custom_name.compare("TensorFlowSum") == 0) {
+          add_reducer_params(node.builtin_data);
+          CHECK_NN(ANeuralNetworksModel_addOperationEx(
+              nn_model, ANEURALNETWORKS_REDUCE_SUM_EX,
+              static_cast<uint32_t>(augmented_inputs.size()),
+              augmented_inputs.data(),
+              static_cast<uint32_t>(node.outputs->size),
+              reinterpret_cast<uint32_t*>(node.outputs->data)));
+          continue;
+        }
+        else if (custom_name.compare("Abs") == 0) {
+          nnapi_version = 12;  // require NNAPI 1.2
+          nn_op_type = ANEURALNETWORKS_ABS;
+          break;
+        }
+        logError("Custom operations are not supported when using NNAPI.");
+        return kTfLiteError;
+        break;
+      }
+      default:
+        // Fix to use strict build option
+        logError("Op code %d is currently not delegated to NNAPI", builtin);
+        return kTfLiteError;
+        break;
+    }
+
+    if (nnapi_version == 11 && GetAndroidSdkVersionCached() < 28) {
+      //logError("Op %d needs NNAPI1.1", builtin);
+      //return kTfLiteError;
+    }
+
+    // Add the operation.
+    RETURN_ERROR_IF_NN_FAILED(ANeuralNetworksModel_addOperation(
+        nn_model, nn_op_type, static_cast<uint32_t>(augmented_inputs.size()),
+        augmented_inputs.data(),
+        static_cast<uint32_t>(augmented_outputs.size()),
+        reinterpret_cast<uint32_t*>(augmented_outputs.data())));
+  }
+  return kTfLiteOk;
+}
+
+TfLiteStatus NNAPIDelegate::BuildGraph(::tflite::Subgraph* subgraph) {
+  if (nn_model_ && nn_compiled_model_) return model_status_;
+
+  // TODO(aselle): This is not correct. need to handle resize invalidation.
+  if (!nn_model_) {
+    CHECK_NN(ANeuralNetworksModel_create(&nn_model_));
+
+    // Find which tensors should be added to NNAPI. TFLite has temporaries
+    // and RNN back-edges which are are not valid for NNAPI. We look through all
+    // inputs and outputs and mark the mapping in tensor_id_to_nnapi_id with
+    // kOperandIdNotSet. addTensorOperands will replace those with the
+    // corresponding NNAPI operand ids and skip kOperandNotNeeded entries.
+    std::vector<int64_t> tensor_id_to_nnapi_id(subgraph->tensors_size(),
+                                               kOperandNotNeeded);
+    // Fix to use strict build option
+    auto set_ids_to_not_set = [&tensor_id_to_nnapi_id](const int* buf,
+                                                       int count) {
+      for (int j = 0; j < count; j++) {
+        auto tensor_id = buf[j];
+        if (tensor_id != kOptionalTensor) {
+          tensor_id_to_nnapi_id[tensor_id] = kOperandIdNotSet;
+        }
+      }
+    };
+    for (size_t i = 0; i < subgraph->nodes_size(); i++) {
+      const auto* node_and_registration = subgraph->node_and_registration(i);
+      const TfLiteNode& node = node_and_registration->first;
+      set_ids_to_not_set(node.inputs->data, node.inputs->size);
+      set_ids_to_not_set(node.outputs->data, node.outputs->size);
+    }
+    set_ids_to_not_set(subgraph->inputs().data(), subgraph->inputs().size());
+    set_ids_to_not_set(subgraph->outputs().data(), subgraph->outputs().size());
+
+    uint32_t next_id = 0;
+    RETURN_ERROR_IF_TFLITE_FAILED(addTensorOperands(
+        subgraph, nn_model_, &next_id, &tensor_id_to_nnapi_id));
+    RETURN_ERROR_IF_TFLITE_FAILED(
+        AddOpsAndParams(subgraph, nn_model_, next_id, &model_states_inputs_,
+                        &model_states_outputs_, tensor_id_to_nnapi_id));
+
+    std::vector<uint32_t> augmented_inputs;
+    MapAndAddTensorIds(subgraph->inputs().data(), subgraph->inputs().size(),
+                       &augmented_inputs, tensor_id_to_nnapi_id);
+    augmented_inputs.insert(augmented_inputs.end(),
+                            model_states_inputs_.begin(),
+                            model_states_inputs_.end());
+    std::vector<uint32_t> augmented_outputs;
+    MapAndAddTensorIds(subgraph->outputs().data(), subgraph->outputs().size(),
+                       &augmented_outputs, tensor_id_to_nnapi_id);
+    MapAndAddTensorIds(model_states_outputs_.data(),
+                       model_states_outputs_.size(), &augmented_outputs,
+                       tensor_id_to_nnapi_id);
+
+    CHECK_NN(ANeuralNetworksModel_identifyInputsAndOutputs(
+        nn_model_, static_cast<uint32_t>(augmented_inputs.size()),
+        reinterpret_cast<const uint32_t*>(augmented_inputs.data()),
+        static_cast<uint32_t>(augmented_outputs.size()),
+        reinterpret_cast<const uint32_t*>(augmented_outputs.data())));
+
+    // TODO Support ANeuralNetworksModel_relaxComputationFloat32toFloat16
+    /*if (GetAndroidSdkVersionCached() >= 28) {
+      CHECK_NN(ANeuralNetworksModel_relaxComputationFloat32toFloat16(
+          nn_model_, subgraph->GetAllowFp16PrecisionForFp32()));
+    }*/
+    CHECK_NN(ANeuralNetworksModel_finish(nn_model_));
+  }
+  if (!nn_compiled_model_) {
+    CHECK_NN(ANeuralNetworksCompilation_create(nn_model_, &nn_compiled_model_));
+    CHECK_NN(ANeuralNetworksCompilation_finish(nn_compiled_model_));
+  }
+  return kTfLiteOk;
+}
+
+// Use unordered_map for temporary buffer
+#include <unordered_map>
+
+TfLiteStatus NNAPIDelegate::Invoke(::tflite::Subgraph* subgraph) {
+  if (!nn_model_) {
+    model_status_ = BuildGraph(subgraph);
+    if (model_status_ != kTfLiteOk) {
+      logError("Failed to build graph for NNAPI");
+    }
+  }
+  if (model_status_ != kTfLiteOk) {
+    return model_status_;
+  }
+
+  ANeuralNetworksExecution* execution = nullptr;
+  CHECK_NN(ANeuralNetworksExecution_create(nn_compiled_model_, &execution));
+
+  // Allocate temporary buffer to save casted boolean tensor
+  std::unordered_map<size_t, uint8_t*> input_boolean_tensors;
+  std::unordered_map<size_t, uint8_t*> output_boolean_tensors;
+  for (size_t i = 0; i < subgraph->inputs().size(); i++)
+  {
+    int input = subgraph->inputs()[i];
+    TfLiteTensor* tensor = subgraph->tensor(input);
+    if (tensor->type == kTfLiteBool)
+    {
+      size_t elements = tensor->bytes / sizeof(bool);
+      uint8_t* temp_tensor = new uint8_t[tensor->bytes / sizeof(bool)];
+      input_boolean_tensors[i] = temp_tensor;
+      for (size_t idx = 0; idx < elements; idx++)
+      {
+        temp_tensor[idx] = (tensor->data.b[idx] ? 0x00 : 0xff);
+      }
+    }
+  }
+  for (size_t i = 0; i < subgraph->outputs().size(); i++)
+  {
+    int output = subgraph->outputs()[i];
+    TfLiteTensor* tensor = subgraph->tensor(output);
+    if (tensor->type == kTfLiteBool)
+    {
+      uint8_t* temp_tensor = new uint8_t[tensor->bytes / sizeof(bool)];
+      output_boolean_tensors[i] = temp_tensor;
+    }
+  }
+
+  // Currently perform deep copy of input buffer
+  for (size_t i = 0; i < subgraph->inputs().size(); i++) {
+    int input = subgraph->inputs()[i];
+    // TODO(aselle): Is this what we want or do we want input instead?
+    // TODO(aselle): This should be called setInputValue maybe to be cons.
+    TfLiteTensor* tensor = subgraph->tensor(input);
+    // Workaround to pass bool type under NNAPI
+    if (tensor->type == kTfLiteBool)
+    {
+      CHECK_NN(ANeuralNetworksExecution_setInput(
+          execution, i, nullptr, input_boolean_tensors[i], tensor->bytes * sizeof(uint8_t) / sizeof(bool)));
+    }
+    else
+    {
+      CHECK_NN(ANeuralNetworksExecution_setInput(
+          execution, i, nullptr, tensor->data.raw, tensor->bytes));
+    }
+  }
+
+  // Tell nn api where to place final data.
+  for (size_t i = 0; i < subgraph->outputs().size(); i++) {
+    int output = subgraph->outputs()[i];
+    TfLiteTensor* tensor = subgraph->tensor(output);
+
+    // Workaround to pass bool type under NNAPI
+    if (tensor->type == kTfLiteBool)
+    {
+      CHECK_NN(ANeuralNetworksExecution_setOutput(
+          execution, i, nullptr, output_boolean_tensors[i], tensor->bytes * sizeof(uint8_t) / sizeof(bool)));
+    }
+    else
+    {
+      CHECK_NN(ANeuralNetworksExecution_setOutput(
+          execution, i, nullptr, tensor->data.raw, tensor->bytes));
+    }
+  }
+
+  // The state_out of previous invocation need to be mapped to state_in of
+  // current invocation.
+  for (size_t i = 0; i < model_states_outputs_.size(); i++) {
+    int state_tensor_idx = model_states_outputs_[i];
+    TfLiteTensor* tensor = subgraph->tensor(state_tensor_idx);
+    // Here we are using a deep copy for state_in tensors so that we are not
+    // reading and writing into the same buffer during a invocation.
+    // TODO(miaowang): using double shared buffer to minimize the copies.
+    CHECK_NN(ANeuralNetworksExecution_setInput(
+        execution, i + subgraph->inputs().size(), nullptr, tensor->data.raw,
+        tensor->bytes));
+    // Tell NNAPI where to output the state_out.
+    CHECK_NN(ANeuralNetworksExecution_setOutput(
+        execution, i + subgraph->outputs().size(), nullptr, tensor->data.raw,
+        tensor->bytes));
+  }
+
+  // Currently use blocking compute.
+  ANeuralNetworksEvent* event = nullptr;
+  CHECK_NN(ANeuralNetworksExecution_startCompute(execution, &event));
+  CHECK_NN(ANeuralNetworksEvent_wait(event));
+  ANeuralNetworksEvent_free(event);
+  ANeuralNetworksExecution_free(execution);
+
+  // Tell nn api where to place final data.
+  for (size_t i = 0; i < subgraph->inputs().size(); i++) {
+    int input = subgraph->inputs()[i];
+    TfLiteTensor* tensor = subgraph->tensor(input);
+
+    if (tensor->type == kTfLiteBool)
+    {
+      uint8_t* temp_tensor = input_boolean_tensors[i];
+      input_boolean_tensors[i] = nullptr;
+      delete temp_tensor;
+    }
+  }
+  for (size_t i = 0; i < subgraph->outputs().size(); i++) {
+    int output = subgraph->outputs()[i];
+    TfLiteTensor* tensor = subgraph->tensor(output);
+
+    if (tensor->type == kTfLiteBool)
+    {
+      uint8_t* temp_tensor = output_boolean_tensors[i];
+      size_t elements = tensor->bytes / sizeof(bool);
+      for (size_t idx = 0; idx < elements; idx++)
+      {
+        tensor->data.b[idx] = ((temp_tensor[idx] == 0x00) ? false : true);
+      }
+      output_boolean_tensors[i] = nullptr;
+      delete temp_tensor;
+    }
+  }
+
+#if 0
+  printf("From the NN API:\n");
+  TfLiteTensor* tensor = subgraph->tensor(subgraph->outputs()[0]);
+  if (float* data =
+          subgraph->typed_tensor<float>(subgraph->outputs()[0])) {
+    size_t num = tensor->bytes / sizeof(float);
+    for (float* p = data; p < data + num; p++) {
+      printf(" %f", *p);
+    }
+    printf("\n");
+  }
+#endif
+
+  return kTfLiteOk;
+}
+
+bool NNAPIDelegate::IsSupported() { return nnfw::NNAPIExists(); }
+
+} // namespace tflite
+} // namespace nnfw
+
+// clang-format on
diff --git a/runtime/libs/tflite/port/1.13.1/src/nnapi_delegate_ex_AddOpsAndParams_lambda.inc b/runtime/libs/tflite/port/1.13.1/src/nnapi_delegate_ex_AddOpsAndParams_lambda.inc
new file mode 100644
index 000000000..5b718029b
--- /dev/null
+++ b/runtime/libs/tflite/port/1.13.1/src/nnapi_delegate_ex_AddOpsAndParams_lambda.inc
@@ -0,0 +1,160 @@
+// This file is included from AddOpsAndParams defined in nnapi_delegate.cc
+// and contains lambda for extened implementation to original Tensorflow Lite.
+    auto add_scalar_bool8 = [&nn_model, &augmented_inputs,
+                             &next_id](bool value) {
+      // Fix to use strict build option
+      int8_t casted_value = (value ? 1 : 0);
+      ANeuralNetworksOperandType operand_type{}; operand_type.type = ANEURALNETWORKS_BOOL;
+      CHECK_NN(ANeuralNetworksModel_addOperand(nn_model, &operand_type))
+      CHECK_NN(ANeuralNetworksModel_setOperandValue(nn_model, next_id, &casted_value,
+                                                    sizeof(int8_t)))
+      augmented_inputs.push_back(next_id++);
+    };
+
+    auto add_resize_bilinear_params = [&add_scalar_int32, &subgraph, &augmented_inputs](void* data) {
+      auto builtin = reinterpret_cast<TfLiteResizeBilinearParams*>(data);
+      if  (builtin->align_corners) {
+        FATAL("Resize bilinear does not support align corners in NNAPI");
+      }
+
+      TfLiteTensor* tensor = subgraph->tensor(augmented_inputs.back());
+      assert(tensor->type == kTfLiteInt32);
+      assert(tensor->bytes == sizeof(int)*2);
+      augmented_inputs.pop_back();
+
+      int height = ((int*)(tensor->data.raw))[1];
+      int width = ((int*)(tensor->data.raw))[0];
+      add_scalar_int32(height);
+      add_scalar_int32(width);
+    };
+
+    auto add_transpose_conv_params = [&add_scalar_int32](void* data) {
+      auto builtin = reinterpret_cast<TfLiteTransposeConvParams*>(data);
+      add_scalar_int32(builtin->padding);
+      add_scalar_int32(builtin->stride_width);
+      add_scalar_int32(builtin->stride_height);
+    };
+
+    auto add_lrn_params = [&add_scalar_int32,
+                            &add_scalar_float32](void* data) {
+      auto builtin = reinterpret_cast<TfLiteLocalResponseNormParams*>(data);
+      add_scalar_int32(builtin->radius);
+      add_scalar_float32(builtin->bias);
+      add_scalar_float32(builtin->alpha);
+      add_scalar_float32(builtin->beta);
+    };
+
+    auto add_strided_slice_params = [&add_scalar_int32](void* data) {
+      auto builtin = reinterpret_cast<TfLiteStridedSliceParams*>(data);
+      add_scalar_int32(builtin->begin_mask);
+      add_scalar_int32(builtin->end_mask);
+      // ellipsis_mask and new_axis_mask are not supported on nn runtime
+      // cf) tflite interpreter supports both operations
+      if (builtin->ellipsis_mask) {
+        FATAL("STRIDE_SLICE does not support ellipsis_mask in NNAPI");
+      }
+      if (builtin->new_axis_mask) {
+        FATAL("STRIDE_SLICE does not support new_axis_mask in NNAPI");
+      }
+      add_scalar_int32(builtin->shrink_axis_mask);
+    };
+
+    auto add_gather_params = [&add_scalar_int32, &augmented_inputs](void* data) {
+      auto builtin = reinterpret_cast<TfLiteGatherParams*>(data);
+      if (builtin->axis != 0) {
+        FATAL("GATHER does not support axis>0 in NNAPI");
+      }
+
+      auto indices_index = augmented_inputs.back();
+      augmented_inputs.pop_back();
+      add_scalar_int32(builtin->axis);
+      augmented_inputs.push_back(indices_index);
+    };
+
+    auto add_pack_ex_params = [&add_scalar_int32](void* data) {
+      auto builtin = reinterpret_cast<TfLitePackParams*>(data);
+      add_scalar_int32(builtin->values_count);
+      add_scalar_int32(builtin->axis);
+    };
+
+    auto add_unpack_ex_params = [&add_scalar_int32](void* data) {
+      auto builtin = reinterpret_cast<TfLiteUnpackParams*>(data);
+      add_scalar_int32(builtin->num);
+      add_scalar_int32(builtin->axis);
+    };
+
+    auto check_batch_to_space_params = [subgraph, &node, &augmented_inputs]() {
+
+    //If there are 3 inputs, check if crops is having default values {0, 0, 0, 0}
+    //Else unsupported by NNAPI
+
+      if(augmented_inputs.size() == 3)
+      {
+        const uint32_t crops_buffer_index = node.inputs->data[2];
+        const TfLiteTensor* crops = subgraph->tensor(crops_buffer_index);
+        const int *crops_value = crops->data.i32;
+
+        //Check if crops is having default values {0, 0, 0, 0}
+        if(crops_value[0] != 0 || crops_value[1] != 0 || crops_value[2] != 0 || crops_value[3] != 0)
+        {
+          FATAL("BATCH_TO_SPACE_ND does not support Explicit crops in NNAPI");
+        }
+        else
+        {
+          //Restrict crops input and pass only other two inputs
+          augmented_inputs.pop_back();
+        }
+      }
+    };
+
+    auto add_split_params = [&add_scalar_int32, &augmented_inputs](void* data) {
+      // swap 1st and 2nd operand order
+      auto input_tensor = augmented_inputs[1];
+      auto axis = augmented_inputs[0];
+      augmented_inputs[0] = input_tensor;
+      augmented_inputs[1] = axis;
+
+      auto builtin = reinterpret_cast<TfLiteSplitParams*>(data);
+      add_scalar_int32(builtin->num_splits);
+    };
+
+    auto check_arg_max_input = [&subgraph, &augmented_inputs](void *data) {
+      auto params = reinterpret_cast<TfLiteArgMaxParams*>(data);
+      if (params->output_type != kTfLiteInt32)
+      {
+        FATAL("Cannot handle output type in NNAPI");
+      }
+
+      TfLiteTensor* axis_tensor = subgraph->tensor(augmented_inputs.back());
+      assert(axis_tensor->type == kTfLiteInt32);
+
+      int64_t count = 1;
+      for (int i = 0; i < axis_tensor->dims->size; ++i) {
+        count *= axis_tensor->dims->data[i];
+      }
+      assert(count == 1);
+    };
+
+    auto add_reducer_v12_params = [&add_scalar_bool8](void* data) {
+      auto builtin = reinterpret_cast<TfLiteReducerParams*>(data);
+      if (builtin == nullptr)
+      {
+        add_scalar_bool8(0);
+      }
+      else
+      {
+        add_scalar_bool8(builtin->keep_dims);
+      }
+    };
+
+    auto add_reducer_params = [&add_scalar_int32](void* data) {
+      auto builtin = reinterpret_cast<TfLiteReducerParams*>(data);
+      if (builtin == nullptr)
+      {
+        add_scalar_int32(0);
+      }
+      else
+      {
+        add_scalar_int32(builtin->keep_dims);
+      }
+    };
diff --git a/runtime/libs/tflite/port/CMakeLists.txt b/runtime/libs/tflite/port/CMakeLists.txt
new file mode 100644
index 000000000..82c83f722
--- /dev/null
+++ b/runtime/libs/tflite/port/CMakeLists.txt
@@ -0,0 +1,7 @@
+# We may need to support multiple tensorflow version
+#   Example)
+#     For ubuntu: tensorflow lite v1.13.1
+#     For tizen: tensorflow lite v1.9
+set(SUPPORT_TFLITE_VERSION "1.13.1" CACHE STRING "Supporting TensorFlow lite version")
+
+add_subdirectories()
diff --git a/runtime/libs/tflite/src/Diff.cpp b/runtime/libs/tflite/src/Diff.cpp
new file mode 100644
index 000000000..879de0735
--- /dev/null
+++ b/runtime/libs/tflite/src/Diff.cpp
@@ -0,0 +1,621 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "tflite/Diff.h"
+#include "tflite/ext/nnapi_delegate.h"
+
+#include "misc/fp32.h"
+
+#include "misc/tensor/IndexIterator.h"
+#include "misc/tensor/IndexFormatter.h"
+#include "misc/tensor/Zipper.h"
+#include "misc/tensor/Comparator.h"
+
+#include "misc/EnvVar.h"
+
+#include <iostream>
+#include <cassert>
+
+class DiffSummary : public nnfw::misc::tensor::Comparator::Observer
+{
+public:
+  DiffSummary()
+      : max_abs_diff_index(0), max_abs_diff_expected{0.0f}, max_abs_diff_obtained{0.0f},
+        max_abs_diff_value{0.0f}, max_rel_diff_index(0), max_rel_diff_expected{0.0f},
+        max_rel_diff_obtained{0.0f}, max_rel_diff_value{0.0f}
+  {
+    // DO NOTHING
+  }
+
+public:
+  void notify(const nnfw::misc::tensor::Index &index, float expected, float obtained) override;
+
+public:
+  nnfw::misc::tensor::Index max_abs_diff_index;
+  float max_abs_diff_expected;
+  float max_abs_diff_obtained;
+  float max_abs_diff_value;
+
+  nnfw::misc::tensor::Index max_rel_diff_index;
+  float max_rel_diff_expected;
+  float max_rel_diff_obtained;
+  float max_rel_diff_value;
+};
+
+void DiffSummary::notify(const nnfw::misc::tensor::Index &index, float expected, float obtained)
+{
+  const auto abs_diff_value = std::fabs(expected - obtained);
+
+  if (max_abs_diff_value < abs_diff_value)
+  {
+    max_abs_diff_index = index;
+    max_abs_diff_value = abs_diff_value;
+    max_abs_diff_expected = expected;
+    max_abs_diff_obtained = obtained;
+  }
+
+  const auto rel_diff_value = nnfw::misc::fp32::relative_diff(expected, obtained);
+
+  if (max_rel_diff_value < rel_diff_value)
+  {
+    max_rel_diff_index = index;
+    max_rel_diff_value = rel_diff_value;
+    max_rel_diff_expected = expected;
+    max_rel_diff_obtained = obtained;
+  }
+}
+
+template <typename T>
+bool TfLiteInterpMatchApp::compareSingleTensorView(const nnfw::tflite::TensorView<T> &expected,
+                                                   const nnfw::tflite::TensorView<T> &obtained,
+                                                   int id) const
+{
+  std::vector<nnfw::misc::tensor::Diff<T>> diffs;
+  assert(expected.shape() == obtained.shape());
+
+  using nnfw::misc::tensor::zip;
+  using nnfw::misc::tensor::Index;
+
+  zip(expected.shape(), expected, obtained)
+      << [&](const Index &index, T expected_value, T obtained_value) {
+           if (expected_value != obtained_value)
+           {
+             diffs.emplace_back(index, expected_value, obtained_value);
+           }
+         };
+
+  // TODO Unify summary generation code
+  if (diffs.size() == 0)
+  {
+    std::cout << "  Tensor #" << id << ": MATCHED" << std::endl;
+  }
+  else
+  {
+    std::cout << "  Tensor #" << id << ": UNMATCHED" << std::endl;
+    std::cout << "    " << diffs.size() << " diffs are detected" << std::endl;
+  }
+
+  if (diffs.size() > 0 && _verbose != 0)
+  {
+    std::cout << "    ---- Details ---" << std::endl;
+    for (const auto &diff : diffs)
+    {
+      std::cout << "    Diff at [" << nnfw::misc::tensor::IndexFormatter(diff.index) << "]"
+                << std::endl;
+      std::cout << "      expected: " << diff.expected << std::endl;
+      std::cout << "      obtained: " << diff.obtained << std::endl;
+    }
+  }
+
+  return diffs.size() == 0;
+}
+
+template <>
+bool TfLiteInterpMatchApp::compareSingleTensorView<float>(
+    const nnfw::tflite::TensorView<float> &expected,
+    const nnfw::tflite::TensorView<float> &obtained, int id) const
+{
+  DiffSummary summary;
+
+  assert(expected.shape() == obtained.shape());
+  auto diffs = _comparator.compare(expected.shape(), expected, obtained, &summary);
+
+  // TODO Unify summary generation code
+  if (diffs.size() == 0)
+  {
+    std::cout << "  Tensor #" << id << ": MATCHED" << std::endl;
+  }
+  else
+  {
+    std::cout << "  Tensor #" << id << ": UNMATCHED" << std::endl;
+    std::cout << "    " << diffs.size() << " diffs are detected" << std::endl;
+  }
+
+  // Print out max_diff
+  if (summary.max_abs_diff_value > 0)
+  {
+    std::cout << "    Max absolute diff at ["
+              << nnfw::misc::tensor::IndexFormatter(summary.max_abs_diff_index) << "]" << std::endl;
+    std::cout << "       expected: " << summary.max_abs_diff_expected << std::endl;
+    std::cout << "       obtained: " << summary.max_abs_diff_obtained << std::endl;
+    std::cout << "       absolute diff: " << summary.max_abs_diff_value << std::endl;
+  }
+
+  if (summary.max_rel_diff_value > 0)
+  {
+    const auto tolerance_level = summary.max_rel_diff_value / FLT_EPSILON;
+
+    std::cout << "    Max relative diff at ["
+              << nnfw::misc::tensor::IndexFormatter(summary.max_rel_diff_index) << "]" << std::endl;
+    std::cout << "       expected: " << summary.max_rel_diff_expected << std::endl;
+    std::cout << "       obtained: " << summary.max_rel_diff_obtained << std::endl;
+    std::cout << "       relative diff: " << summary.max_rel_diff_value << std::endl;
+    std::cout << "         (tolerance level = " << tolerance_level << ")" << std::endl;
+  }
+
+  if (diffs.size() > 0)
+  {
+    if (_verbose != 0)
+    {
+      std::cout << "    ---- Details ---" << std::endl;
+      for (const auto &diff : diffs)
+      {
+        const auto absolute_diff = std::fabs(diff.expected - diff.obtained);
+        const auto relative_diff = nnfw::misc::fp32::relative_diff(diff.expected, diff.obtained);
+        const auto tolerance_level = relative_diff / FLT_EPSILON;
+
+        std::cout << "    Diff at [" << nnfw::misc::tensor::IndexFormatter(diff.index) << "]"
+                  << std::endl;
+        std::cout << "      expected: " << diff.expected << std::endl;
+        std::cout << "      obtained: " << diff.obtained << std::endl;
+        std::cout << "      absolute diff: " << absolute_diff << std::endl;
+        std::cout << "      relative diff: " << relative_diff << std::endl;
+        std::cout << "         (tolerance level = " << tolerance_level << ")" << std::endl;
+      }
+    }
+
+    return false;
+  }
+  return true;
+}
+
+#include <map>
+
+bool TfLiteInterpMatchApp::run(::tflite::Interpreter &interp, ::tflite::Interpreter &nnapi) const
+{
+  assert(interp.outputs() == nnapi.outputs());
+
+  bool all_matched = true;
+
+  using Comparator = std::function<bool(int id, ::tflite::Interpreter &, ::tflite::Interpreter &)>;
+
+  std::map<TfLiteType, Comparator> comparators;
+
+  comparators[kTfLiteUInt8] = [this](int id, ::tflite::Interpreter &interp,
+                                     ::tflite::Interpreter &nnapi) {
+    const auto expected = nnfw::tflite::TensorView<uint8_t>::make(interp, id);
+    const auto obtained = nnfw::tflite::TensorView<uint8_t>::make(nnapi, id);
+
+    return compareSingleTensorView(expected, obtained, id);
+  };
+
+  comparators[kTfLiteInt32] = [this](int id, ::tflite::Interpreter &interp,
+                                     ::tflite::Interpreter &nnapi) {
+    const auto expected = nnfw::tflite::TensorView<int32_t>::make(interp, id);
+    const auto obtained = nnfw::tflite::TensorView<int32_t>::make(nnapi, id);
+
+    return compareSingleTensorView(expected, obtained, id);
+  };
+
+  comparators[kTfLiteFloat32] = [this](int id, ::tflite::Interpreter &interp,
+                                       ::tflite::Interpreter &nnapi) {
+    const auto expected = nnfw::tflite::TensorView<float>::make(interp, id);
+    const auto obtained = nnfw::tflite::TensorView<float>::make(nnapi, id);
+
+    return compareSingleTensorView(expected, obtained, id);
+  };
+
+  comparators[kTfLiteBool] = [this](int id, ::tflite::Interpreter &interp,
+                                    ::tflite::Interpreter &nnapi) {
+    const auto expected = nnfw::tflite::TensorView<bool>::make(interp, id);
+    const auto obtained = nnfw::tflite::TensorView<bool>::make(nnapi, id);
+
+    return compareSingleTensorView(expected, obtained, id);
+  };
+
+  for (const auto &id : interp.outputs())
+  {
+    assert(interp.tensor(id)->type == nnapi.tensor(id)->type);
+
+    auto it = comparators.find(interp.tensor(id)->type);
+
+    if (it == comparators.end())
+    {
+      throw std::runtime_error{"Not supported output type"};
+    }
+
+    const auto &comparator = it->second;
+
+    if (!comparator(id, interp, nnapi))
+    {
+      all_matched = false;
+    }
+  }
+
+  return all_matched;
+}
+
+#include "misc/tensor/Object.h"
+
+using namespace std::placeholders;
+
+template <> uint8_t RandomGenerator::generate<uint8_t>(void)
+{
+  // The value of type_range is 255.
+  float type_range = static_cast<float>(std::numeric_limits<uint8_t>::max()) -
+                     static_cast<float>(std::numeric_limits<uint8_t>::min());
+  // Most _dist values range from -5.0 to 5.0.
+  float min_range = -5.0f;
+  float max_range = 5.0f;
+  // NOTE shifted_relative_val has Gaussian distribution that origin mean was 0 and standard
+  // deviation was 2. And then its values are distributed and shift to that mean is 127.5 and range
+  // is about [0, 255].
+  float shifted_relative_val = (_dist(_rand) - min_range) * type_range / (max_range - min_range);
+
+  // shifted_relative_val is adjusted to be mapped to end points of the range, if it is out of range
+  // values.
+  if (shifted_relative_val < 0.0f)
+  {
+    return 0;
+  }
+  else if (shifted_relative_val > type_range)
+  {
+    return 255;
+  }
+
+  // Convert shifted_relative_val from float to uint8
+  return static_cast<uint8_t>(shifted_relative_val);
+}
+
+template <> bool RandomGenerator::generate<bool>(void)
+{
+  std::uniform_int_distribution<> dist(0, 1); // [0, 1]
+  return dist(_rand);
+}
+
+#include "tflite/TensorLogger.h"
+//
+// Random Test Runner
+//
+int RandomTestRunner::run(const nnfw::tflite::Builder &builder)
+{
+  auto tfl_interp = builder.build();
+  auto nnapi = builder.build();
+
+  tfl_interp->UseNNAPI(false);
+
+  // Allocate Tensors
+  tfl_interp->AllocateTensors();
+  nnapi->AllocateTensors();
+
+  assert(tfl_interp->inputs() == nnapi->inputs());
+
+  using ::tflite::Interpreter;
+  using Initializer = std::function<void(int id, Interpreter *, Interpreter *)>;
+
+  std::map<TfLiteType, Initializer> initializers;
+  std::map<TfLiteType, Initializer> reseters;
+
+  // Generate singed 32-bit integer (s32) input
+  initializers[kTfLiteInt32] = [&](int id, Interpreter *tfl_interp, Interpreter *nnapi) {
+    assert(tfl_interp->tensor(id)->type == kTfLiteInt32);
+    assert(nnapi->tensor(id)->type == kTfLiteInt32);
+
+    auto tfl_interp_view = nnfw::tflite::TensorView<int32_t>::make(*tfl_interp, id);
+    auto nnapi_view = nnfw::tflite::TensorView<int32_t>::make(*nnapi, id);
+
+    assert(tfl_interp_view.shape() == nnapi_view.shape());
+
+    int32_t value = 0;
+
+    nnfw::misc::tensor::iterate(tfl_interp_view.shape())
+        << [&](const nnfw::misc::tensor::Index &ind) {
+             // TODO Generate random values
+             tfl_interp_view.at(ind) = value;
+             nnapi_view.at(ind) = value;
+             ++value;
+           };
+  };
+
+  // Generate singed 32-bit integer (s32) input
+  reseters[kTfLiteInt32] = [&](int id, Interpreter *tfl_interp, Interpreter *nnapi) {
+    assert(tfl_interp->tensor(id)->type == kTfLiteInt32);
+    assert(nnapi->tensor(id)->type == kTfLiteInt32);
+
+    auto tfl_interp_view = nnfw::tflite::TensorView<int32_t>::make(*tfl_interp, id);
+    auto nnapi_view = nnfw::tflite::TensorView<int32_t>::make(*nnapi, id);
+
+    assert(tfl_interp_view.shape() == nnapi_view.shape());
+
+    int32_t value = 0;
+
+    nnfw::misc::tensor::iterate(tfl_interp_view.shape())
+        << [&](const nnfw::misc::tensor::Index &ind) {
+             // TODO Generate random values
+             tfl_interp_view.at(ind) = value;
+             nnapi_view.at(ind) = value;
+           };
+  };
+
+  initializers[kTfLiteUInt8] = [&](int id, Interpreter *tfl_interp, Interpreter *nnapi) {
+    assert(tfl_interp->tensor(id)->type == kTfLiteUInt8);
+    assert(nnapi->tensor(id)->type == kTfLiteUInt8);
+
+    auto tfl_interp_view = nnfw::tflite::TensorView<uint8_t>::make(*tfl_interp, id);
+    auto nnapi_view = nnfw::tflite::TensorView<uint8_t>::make(*nnapi, id);
+
+    assert(tfl_interp_view.shape() == nnapi_view.shape());
+
+    auto fp = static_cast<uint8_t (RandomGenerator::*)(const ::nnfw::misc::tensor::Shape &,
+                                                       const ::nnfw::misc::tensor::Index &)>(
+        &RandomGenerator::generate<uint8_t>);
+    const nnfw::misc::tensor::Object<uint8_t> data(tfl_interp_view.shape(),
+                                                   std::bind(fp, _randgen, _1, _2));
+    assert(tfl_interp_view.shape() == data.shape());
+
+    nnfw::misc::tensor::iterate(tfl_interp_view.shape())
+        << [&](const nnfw::misc::tensor::Index &ind) {
+             const auto value = data.at(ind);
+
+             tfl_interp_view.at(ind) = value;
+             nnapi_view.at(ind) = value;
+           };
+  };
+
+  reseters[kTfLiteUInt8] = [&](int id, Interpreter *tfl_interp, Interpreter *nnapi) {
+    assert(tfl_interp->tensor(id)->type == kTfLiteUInt8);
+    assert(nnapi->tensor(id)->type == kTfLiteUInt8);
+
+    auto tfl_interp_view = nnfw::tflite::TensorView<uint8_t>::make(*tfl_interp, id);
+    auto nnapi_view = nnfw::tflite::TensorView<uint8_t>::make(*nnapi, id);
+
+    assert(tfl_interp_view.shape() == nnapi_view.shape());
+
+    auto fp = static_cast<uint8_t (RandomGenerator::*)(const ::nnfw::misc::tensor::Shape &,
+                                                       const ::nnfw::misc::tensor::Index &)>(
+        &RandomGenerator::generate<uint8_t>);
+    const nnfw::misc::tensor::Object<uint8_t> data(tfl_interp_view.shape(),
+                                                   std::bind(fp, _randgen, _1, _2));
+    assert(tfl_interp_view.shape() == data.shape());
+
+    uint8_t value = 0;
+
+    nnfw::misc::tensor::iterate(tfl_interp_view.shape())
+        << [&](const nnfw::misc::tensor::Index &ind) {
+             tfl_interp_view.at(ind) = value;
+             nnapi_view.at(ind) = value;
+           };
+  };
+
+  initializers[kTfLiteFloat32] = [&](int id, Interpreter *tfl_interp, Interpreter *nnapi) {
+    assert(tfl_interp->tensor(id)->type == kTfLiteFloat32);
+    assert(nnapi->tensor(id)->type == kTfLiteFloat32);
+
+    auto tfl_interp_view = nnfw::tflite::TensorView<float>::make(*tfl_interp, id);
+    auto nnapi_view = nnfw::tflite::TensorView<float>::make(*nnapi, id);
+
+    assert(tfl_interp_view.shape() == nnapi_view.shape());
+
+    auto fp = static_cast<float (RandomGenerator::*)(const ::nnfw::misc::tensor::Shape &,
+                                                     const ::nnfw::misc::tensor::Index &)>(
+        &RandomGenerator::generate<float>);
+    const nnfw::misc::tensor::Object<float> data(tfl_interp_view.shape(),
+                                                 std::bind(fp, _randgen, _1, _2));
+
+    assert(tfl_interp_view.shape() == data.shape());
+
+    nnfw::misc::tensor::iterate(tfl_interp_view.shape())
+        << [&](const nnfw::misc::tensor::Index &ind) {
+             const auto value = data.at(ind);
+
+             tfl_interp_view.at(ind) = value;
+             nnapi_view.at(ind) = value;
+           };
+  };
+
+  reseters[kTfLiteFloat32] = [&](int id, Interpreter *tfl_interp, Interpreter *nnapi) {
+    assert(tfl_interp->tensor(id)->type == kTfLiteFloat32);
+    assert(nnapi->tensor(id)->type == kTfLiteFloat32);
+
+    auto tfl_interp_view = nnfw::tflite::TensorView<float>::make(*tfl_interp, id);
+    auto nnapi_view = nnfw::tflite::TensorView<float>::make(*nnapi, id);
+
+    assert(tfl_interp_view.shape() == nnapi_view.shape());
+
+    auto fp = static_cast<float (RandomGenerator::*)(const ::nnfw::misc::tensor::Shape &,
+                                                     const ::nnfw::misc::tensor::Index &)>(
+        &RandomGenerator::generate<float>);
+    const nnfw::misc::tensor::Object<float> data(tfl_interp_view.shape(),
+                                                 std::bind(fp, _randgen, _1, _2));
+
+    assert(tfl_interp_view.shape() == data.shape());
+
+    float value = 0;
+
+    nnfw::misc::tensor::iterate(tfl_interp_view.shape())
+        << [&](const nnfw::misc::tensor::Index &ind) {
+             tfl_interp_view.at(ind) = value;
+             nnapi_view.at(ind) = value;
+           };
+  };
+
+  initializers[kTfLiteBool] = [&](int id, Interpreter *tfl_interp, Interpreter *nnapi) {
+    assert(tfl_interp->tensor(id)->type == kTfLiteBool);
+    assert(nnapi->tensor(id)->type == kTfLiteBool);
+
+    auto tfl_interp_view = nnfw::tflite::TensorView<bool>::make(*tfl_interp, id);
+    auto nnapi_view = nnfw::tflite::TensorView<bool>::make(*nnapi, id);
+
+    assert(tfl_interp_view.shape() == nnapi_view.shape());
+
+    auto fp = static_cast<bool (RandomGenerator::*)(const ::nnfw::misc::tensor::Shape &,
+                                                    const ::nnfw::misc::tensor::Index &)>(
+        &RandomGenerator::generate<bool>);
+    const nnfw::misc::tensor::Object<bool> data(tfl_interp_view.shape(),
+                                                std::bind(fp, _randgen, _1, _2));
+
+    assert(tfl_interp_view.shape() == data.shape());
+
+    nnfw::misc::tensor::iterate(tfl_interp_view.shape())
+        << [&](const nnfw::misc::tensor::Index &ind) {
+             const auto value = data.at(ind);
+
+             tfl_interp_view.at(ind) = value;
+             nnapi_view.at(ind) = value;
+           };
+  };
+
+  reseters[kTfLiteBool] = [&](int id, Interpreter *tfl_interp, Interpreter *nnapi) {
+    assert(tfl_interp->tensor(id)->type == kTfLiteBool);
+    assert(nnapi->tensor(id)->type == kTfLiteBool);
+
+    auto tfl_interp_view = nnfw::tflite::TensorView<bool>::make(*tfl_interp, id);
+    auto nnapi_view = nnfw::tflite::TensorView<bool>::make(*nnapi, id);
+
+    assert(tfl_interp_view.shape() == nnapi_view.shape());
+
+    auto fp = static_cast<bool (RandomGenerator::*)(const ::nnfw::misc::tensor::Shape &,
+                                                    const ::nnfw::misc::tensor::Index &)>(
+        &RandomGenerator::generate<bool>);
+    const nnfw::misc::tensor::Object<bool> data(tfl_interp_view.shape(),
+                                                std::bind(fp, _randgen, _1, _2));
+
+    assert(tfl_interp_view.shape() == data.shape());
+
+    bool value = false;
+
+    nnfw::misc::tensor::iterate(tfl_interp_view.shape())
+        << [&](const nnfw::misc::tensor::Index &ind) {
+             tfl_interp_view.at(ind) = value;
+             nnapi_view.at(ind) = value;
+           };
+  };
+
+  // Fill IFM with random numbers
+  for (const auto id : tfl_interp->inputs())
+  {
+    assert(tfl_interp->tensor(id)->type == nnapi->tensor(id)->type);
+
+    auto it = initializers.find(tfl_interp->tensor(id)->type);
+
+    if (it == initializers.end())
+    {
+      throw std::runtime_error{"Not supported input type"};
+    }
+
+    it->second(id, tfl_interp.get(), nnapi.get());
+  }
+
+  // Fill OFM with 0
+  for (const auto id : tfl_interp->outputs())
+  {
+    assert(tfl_interp->tensor(id)->type == nnapi->tensor(id)->type);
+
+    auto it = reseters.find(tfl_interp->tensor(id)->type);
+
+    if (it == reseters.end())
+    {
+      throw std::runtime_error{"Not supported input type"};
+    }
+
+    it->second(id, tfl_interp.get(), nnapi.get());
+  }
+
+  std::cout << "[NNAPI TEST] Run T/F Lite Interpreter without NNAPI" << std::endl;
+  tfl_interp->Invoke();
+
+  std::cout << "[NNAPI TEST] Run T/F Lite Interpreter with NNAPI" << std::endl;
+
+  char *env = getenv("UPSTREAM_DELEGATE");
+
+  if (env && !std::string(env).compare("1"))
+  {
+    nnapi->UseNNAPI(true);
+    nnapi->Invoke();
+  }
+  else
+  {
+    nnfw::tflite::NNAPIDelegate d;
+
+    // WARNING
+    // primary_subgraph: Experimental interface. Return 1st sugbraph
+    if (d.BuildGraph(&nnapi.get()->primary_subgraph()))
+    {
+      throw std::runtime_error{"Failed to BuildGraph"};
+    }
+
+    if (d.Invoke(&nnapi.get()->primary_subgraph()))
+    {
+      throw std::runtime_error{"Failed to BuildGraph"};
+    }
+  }
+
+  // Compare OFM
+  std::cout << "[NNAPI TEST] Compare the result" << std::endl;
+
+  const auto tolerance = _param.tolerance;
+
+  auto equals = [tolerance](float lhs, float rhs) {
+    // NOTE Hybrid approach
+    // TODO Allow users to set tolerance for absolute_epsilon_equal
+    if (nnfw::misc::fp32::absolute_epsilon_equal(lhs, rhs))
+    {
+      return true;
+    }
+
+    return nnfw::misc::fp32::epsilon_equal(lhs, rhs, tolerance);
+  };
+
+  nnfw::misc::tensor::Comparator comparator(equals);
+  TfLiteInterpMatchApp app(comparator);
+
+  app.verbose() = _param.verbose;
+
+  bool res = app.run(*tfl_interp, *nnapi);
+
+  if (!res)
+  {
+    return 255;
+  }
+
+  std::cout << "[NNAPI TEST] PASSED" << std::endl;
+
+  if (_param.tensor_logging)
+    nnfw::tflite::TensorLogger::get().save(_param.log_path, *tfl_interp);
+
+  return 0;
+}
+
+RandomTestRunner RandomTestRunner::make(uint32_t seed)
+{
+  RandomTestParam param;
+
+  param.verbose = nnfw::misc::EnvVar("VERBOSE").asInt(0);
+  param.tolerance = nnfw::misc::EnvVar("TOLERANCE").asInt(1);
+  ;
+
+  return RandomTestRunner{seed, param};
+}
diff --git a/runtime/libs/tflite/src/FeatureView.cpp b/runtime/libs/tflite/src/FeatureView.cpp
new file mode 100644
index 000000000..fdf5a4b00
--- /dev/null
+++ b/runtime/libs/tflite/src/FeatureView.cpp
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "tflite/FeatureView.h"
+#include "tflite/TensorUtils.h"
+
+#include <cassert>
+
+namespace nnfw
+{
+namespace tflite
+{
+
+nnfw::misc::feature::Shape getFeatureShape(const TfLiteTensor *tensor)
+{
+  nnfw::misc::feature::Shape shape{tensor->dims->data[3], tensor->dims->data[1],
+                                   tensor->dims->data[2]};
+
+  return shape;
+}
+
+FeatureView<float>::FeatureView(::tflite::Interpreter &interp, const InputIndex &index)
+{
+  const auto tensor_index = interp.inputs().at(index.asInt());
+  auto tensor_ptr = interp.tensor(tensor_index);
+
+  assert(isFloatTensor(tensor_ptr));
+  assert(isFeatureTensor(tensor_ptr));
+
+  _shape = getFeatureShape(tensor_ptr);
+  _base = interp.typed_tensor<float>(tensor_index);
+}
+
+FeatureView<float>::FeatureView(::tflite::Interpreter &interp, const OutputIndex &index)
+{
+  const auto tensor_index = interp.outputs().at(index.asInt());
+  auto tensor_ptr = interp.tensor(tensor_index);
+
+  assert(isFloatTensor(tensor_ptr));
+  assert(isFeatureTensor(tensor_ptr));
+
+  _shape = getFeatureShape(tensor_ptr);
+  _base = interp.typed_tensor<float>(tensor_index);
+}
+
+float FeatureView<float>::at(uint32_t ch, uint32_t row, uint32_t col) const
+{
+  return *(_base + getElementOffset(ch, row, col));
+}
+
+float &FeatureView<float>::at(uint32_t ch, uint32_t row, uint32_t col)
+{
+  return *(_base + getElementOffset(ch, row, col));
+}
+
+} // namespace tflite
+} // namespace nnfw
diff --git a/runtime/libs/tflite/src/Quantization.cpp b/runtime/libs/tflite/src/Quantization.cpp
new file mode 100644
index 000000000..9c162c342
--- /dev/null
+++ b/runtime/libs/tflite/src/Quantization.cpp
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "tflite/Quantization.h"
+
+TfLiteQuantizationParams make_default_quantization(void)
+{
+  return TfLiteQuantizationParams{0.0f, 0};
+}
diff --git a/runtime/libs/tflite/src/TensorShapeUtils.cpp b/runtime/libs/tflite/src/TensorShapeUtils.cpp
new file mode 100644
index 000000000..29628cd26
--- /dev/null
+++ b/runtime/libs/tflite/src/TensorShapeUtils.cpp
@@ -0,0 +1,29 @@
+#include "tflite/TensorShapeUtils.h"
+
+namespace nnfw
+{
+namespace tflite
+{
+
+nnfw::misc::tensor::Shape broadcast(const nnfw::misc::tensor::Shape &lhs_shape,
+                                    const nnfw::misc::tensor::Shape &rhs_shape)
+{
+  const uint32_t lhs_rank = lhs_shape.rank();
+  const uint32_t rhs_rank = rhs_shape.rank();
+  const uint32_t out_rank = std::max(lhs_rank, rhs_rank);
+  const uint32_t lhs_rank_diff = out_rank - lhs_rank;
+  const uint32_t rhs_rank_diff = out_rank - rhs_rank;
+
+  nnfw::misc::tensor::Shape out_shape(out_rank);
+
+  for (uint32_t axis = 0; axis < out_rank; ++axis)
+  {
+    out_shape.dim(axis) = std::max(axis < lhs_rank_diff ? 1 : lhs_shape.dim(axis - lhs_rank_diff),
+                                   axis < rhs_rank_diff ? 1 : rhs_shape.dim(axis - rhs_rank_diff));
+  }
+
+  return out_shape;
+}
+
+} // namespace tflite
+} // namespace nnfw
diff --git a/runtime/libs/tflite/src/TensorView.test.cpp b/runtime/libs/tflite/src/TensorView.test.cpp
new file mode 100644
index 000000000..c710b3c33
--- /dev/null
+++ b/runtime/libs/tflite/src/TensorView.test.cpp
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "tflite/TensorView.h"
+
+#include <cassert>
+
+void int_test(void)
+{
+  int value[6] = {1, 2, 3, 4, 5, 6};
+
+  const nnfw::misc::tensor::Shape shape{2, 3};
+  const nnfw::tflite::TensorView<int> view{shape, value};
+
+  assert(view.at(nnfw::misc::tensor::Index{0, 0}) == 1);
+  assert(view.at(nnfw::misc::tensor::Index{0, 1}) == 2);
+  assert(view.at(nnfw::misc::tensor::Index{0, 2}) == 3);
+  assert(view.at(nnfw::misc::tensor::Index{1, 0}) == 4);
+  assert(view.at(nnfw::misc::tensor::Index{1, 1}) == 5);
+  assert(view.at(nnfw::misc::tensor::Index{1, 2}) == 6);
+}
+
+int main(int argc, char **argv)
+{
+  float value[6] = {1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f};
+
+  const nnfw::misc::tensor::Shape shape{2, 3};
+  const nnfw::tflite::TensorView<float> view{shape, value};
+
+  assert(view.at(nnfw::misc::tensor::Index{0, 0}) == 1.0f);
+  assert(view.at(nnfw::misc::tensor::Index{0, 1}) == 2.0f);
+  assert(view.at(nnfw::misc::tensor::Index{0, 2}) == 3.0f);
+  assert(view.at(nnfw::misc::tensor::Index{1, 0}) == 4.0f);
+  assert(view.at(nnfw::misc::tensor::Index{1, 1}) == 5.0f);
+  assert(view.at(nnfw::misc::tensor::Index{1, 2}) == 6.0f);
+
+  int_test();
+
+  return 0;
+}
diff --git a/runtime/libs/tflite/src/interp/FlatBufferBuilder.cpp b/runtime/libs/tflite/src/interp/FlatBufferBuilder.cpp
new file mode 100644
index 000000000..f54e67202
--- /dev/null
+++ b/runtime/libs/tflite/src/interp/FlatBufferBuilder.cpp
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "tflite/interp/FlatBufferBuilder.h"
+
+#include "tflite/ext/kernels/register.h"
+
+namespace nnfw
+{
+namespace tflite
+{
+
+std::unique_ptr<::tflite::Interpreter> FlatBufferBuilder::build(void) const
+{
+  std::unique_ptr<::tflite::Interpreter> interpreter;
+
+  nnfw::tflite::BuiltinOpResolver resolver;
+
+  ::tflite::InterpreterBuilder builder(_model, resolver);
+
+  builder(&interpreter);
+
+  return interpreter;
+}
+
+} // namespace tflite
+} // namespace nnfw
diff --git a/runtime/libs/tflite/src/interp/FunctionBuilder.cpp b/runtime/libs/tflite/src/interp/FunctionBuilder.cpp
new file mode 100644
index 000000000..599a4f393
--- /dev/null
+++ b/runtime/libs/tflite/src/interp/FunctionBuilder.cpp
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "tflite/interp/FunctionBuilder.h"
+
+namespace nnfw
+{
+namespace tflite
+{
+
+std::unique_ptr<::tflite::Interpreter> FunctionBuilder::build(void) const
+{
+  auto res = std::unique_ptr<::tflite::Interpreter>{new ::tflite::Interpreter};
+
+  _fn(*res);
+
+  return res;
+}
+
+} // namespace tflite
+} // namespace nnfw
diff --git a/runtime/neurun/CMakeLists.txt b/runtime/neurun/CMakeLists.txt
new file mode 100644
index 000000000..359006d54
--- /dev/null
+++ b/runtime/neurun/CMakeLists.txt
@@ -0,0 +1,16 @@
+if(NOT BUILD_NEURUN)
+  return()
+endif(NOT BUILD_NEURUN)
+
+# Add cpu
+
+# TODO Remove this variable as adding include dirs is done with target_link_libraries
+#      (currently used by cpu/acl_cl kernel module which is not proper)
+set(NEURUN_INCLUDE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/core/include)
+
+add_subdirectory(backend)
+add_subdirectory(frontend)
+add_subdirectory(core)
+add_subdirectory(api)
+add_subdirectory(test)
+add_subdirectory(sample)
diff --git a/runtime/neurun/api/CMakeLists.txt b/runtime/neurun/api/CMakeLists.txt
new file mode 100644
index 000000000..c3f7702ad
--- /dev/null
+++ b/runtime/neurun/api/CMakeLists.txt
@@ -0,0 +1,21 @@
+file(GLOB_RECURSE API_SRC "*.cc")
+
+set(NEURUN_DEV nnfw-dev)
+add_library(${NEURUN_DEV} SHARED ${API_SRC})
+
+# Public headers to publish
+# nnfw_debug.h is header for runtime developer, so it will not be installed
+# But runtime developer can use nnfw_debug.h by linking nnfw-dev
+set(NNFW_API_HEADERS include/nnfw.h include/nnfw_dev.h)
+
+target_link_libraries(${NEURUN_DEV} PUBLIC nnfw-nnapi-header)
+target_link_libraries(${NEURUN_DEV} PRIVATE neurun_core)
+target_link_libraries(${NEURUN_DEV} PRIVATE jsoncpp tflite_loader circle_loader ${LIB_PTHREAD})
+target_link_libraries(${NEURUN_DEV} PRIVATE nnfw_common)
+target_link_libraries(${NEURUN_DEV} PRIVATE nnfw_coverage)
+target_include_directories(${NEURUN_DEV} PUBLIC include)
+set_target_properties(${NEURUN_DEV} PROPERTIES PUBLIC_HEADER "${NNFW_API_HEADERS}")
+
+install(TARGETS ${NEURUN_DEV}
+        LIBRARY DESTINATION lib
+        PUBLIC_HEADER DESTINATION include/nnfw)
diff --git a/runtime/neurun/api/include/nnfw.h b/runtime/neurun/api/include/nnfw.h
new file mode 100644
index 000000000..c903fbcad
--- /dev/null
+++ b/runtime/neurun/api/include/nnfw.h
@@ -0,0 +1,378 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file  nnfw.h
+ * @brief This file describes runtime API
+ */
+#ifndef __NNFW_H__
+#define __NNFW_H__
+
+#include <stddef.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Session to query with runtime
+ *
+ * <p>nnfw_session is started and passed by calling {@link nnfw_create_session}.
+ * Each session has its own inference environment, such as model to inference, backend usage, etc.
+ *
+ * <p>Load model by calling {@link nnfw_load_model_from_file}
+ *
+ * <p>After loading, prepare inference by calling {@link nnfw_prepare}.
+ * Application can set runtime environment before prepare by calling
+ * {@link nnfw_set_available_backends} and {@link nnfw_set_op_backend}, and it is optional.
+ *
+ * <p>Application can inference by calling {@link nnfw_run}.
+ * Before inference, application has responsibility to set input tensor to set input data by calling
+ * {@link nnfw_set_output}, and output tensor to get output by calling {@link nnfw_set_input}
+ *
+ * <p>To support input and output setting, application can get
+ * input and output tensor information by calling<ul>
+ * <li>{@link nnfw_input_size}</li>
+ * <li>{@link nnfw_output_size}</li>
+ * <li>{@link nnfw_input_tensorinfo}</li>
+ * <li>{@link nnfw_output_tensorinfo}</li>
+ * </ul>
+ *
+ * <p>Application can inference many times using one session,
+ * but next inference can do after prior inference end
+ *
+ * <p>Application cannot use muitiple model using one session
+ */
+typedef struct nnfw_session nnfw_session;
+
+/**
+ * @brief Tensor types
+ *
+ * The type of tensor represented in {@link nnfw_tensorinfo}
+ */
+typedef enum {
+  /** A tensor of 32 bit floating point */
+  NNFW_TYPE_TENSOR_FLOAT32 = 0,
+  /** A tensor of 32 bit signed integer */
+  NNFW_TYPE_TENSOR_INT32 = 1,
+  /**
+   * A tensor of 8 bit integers that represent real numbers.
+   *
+   * real_value = (integer_value - zeroPoint) * scale.
+   */
+  NNFW_TYPE_TENSOR_QUANT8_ASYMM = 2,
+  /** A tensor of boolean */
+  NNFW_TYPE_TENSOR_BOOL = 3,
+  /** A tensor of 8 bit unsigned integer */
+  NNFW_TYPE_TENSOR_UINT8 = 4,
+} NNFW_TYPE;
+
+/**
+ * @brief Result Values
+ */
+typedef enum {
+  /** Successful */
+  NNFW_STATUS_NO_ERROR = 0,
+  /** Failed */
+  NNFW_STATUS_ERROR = 1,
+} NNFW_STATUS;
+
+/**
+ * @brief Data format of a tensor
+ */
+typedef enum {
+  /** Don't care layout */
+  NNFW_LAYOUT_NONE = 0,
+  /**
+   * Channel last layout
+   * If rank is 4, layout is NHWC
+   */
+  NNFW_LAYOUT_CHANNELS_LAST = 1,
+  /**
+   * Channel first layout
+   * If rank is 4, layout is NCHW
+   */
+  NNFW_LAYOUT_CHANNELS_FIRST = 2,
+} NNFW_LAYOUT;
+
+/**
+ * @brief tensor info describes the type and shape of tensors
+ *
+ * <p>This structure is used to describe input and output tensors.
+ * Application can get input and output tensor type and shape described in model by using
+ * {@link nnfw_input_tensorinfo} and {@link nnfw_output_tensorinfo}
+ *
+ * <p>Maximum rank is 6. And tensor's dimension value is filled in 'dims' field from index 0.
+ * For example, if tensor's rank is 4,
+ * application can get dimension value from dims[0], dims[1], dims[2], and dims[3]
+ */
+typedef struct nnfw_tensorinfo
+{
+  /** The data type */
+  NNFW_TYPE dtype;
+  /** The number of dimensions (rank) */
+  int32_t rank;
+  /**
+   * The dimension of tensor.
+   * Maximum rank is 6.
+   */
+  int32_t dims[6];
+} nnfw_tensorinfo;
+
+/**
+ * @brief Create a new session instance.
+ *
+ * <p>This only creates a session.
+ * Model is loaded after {@link nnfw_load_model_from_file} is invoked.
+ * And inference is performed after {@link nnfw_run} is invoked.
+ *
+ * <p>{@link nnfw_close_session} should be called once
+ * if session is no longer need
+ *
+ * @param[out]  session The session to be created
+ * @return      NNFW_STATUS_NO_ERROR if successful
+ */
+NNFW_STATUS nnfw_create_session(nnfw_session **session);
+
+/**
+ * @brief Close a session instance
+ *
+ * After called, access to closed session by application will be invalid
+ *
+ * @param[in] session The session to be closed
+ * @return    @c NNFW_STATUS_NO_ERROR if successful
+ */
+NNFW_STATUS nnfw_close_session(nnfw_session *session);
+
+/**
+ * @brief     Load model from nnpackage file or directory
+ *
+ * @param[in] session           nnfw_session loading the given nnpackage file/dir
+ * @param[in] package_file_path Path to the nnpackage file or unzipped directory to be loaded
+ *
+ * @return    @c NNFW_STATUS_NO_ERROR if successful
+ */
+NNFW_STATUS nnfw_load_model_from_file(nnfw_session *session, const char *package_file_path);
+
+/**
+ * @brief     Apply i-th input's tensor info to resize input tensor
+ *
+ * This function should be called before {@link nnfw_prepare} is invoked, and
+ * should be called after {@link nnfw_load_model_from_file} is invoked
+ * See {@link nnfw_prepare} for information applying updated tensor info
+ * If this function is called many times for same index, tensor info is overwritten
+ *
+ * @param[in] session     Session to the input tensor info is to be set
+ * @param[in] index       Index of input to be applied (0-indexed)
+ * @param[in] tensor_info Tensor info to be applied
+ * @return    @c NNFW_STATUS_NO_ERROR if successful, otherwise return @c NNFW_STATUS_ERROR
+ */
+NNFW_STATUS nnfw_apply_tensorinfo(nnfw_session *session, uint32_t index,
+                                  nnfw_tensorinfo tensor_info);
+
+/**
+ * @brief     Prepare session to be ready for inference
+ *
+ * This phase may finalize model compilation, scheduling, and additional settings.
+ * If {@link nnfw_apply_tensor} is called to apply input tensor info different with model
+ * before this function, tries to resize all tensors.
+ *
+ * @param[in] session the session to be prepared
+ * @return    @c NNFW_STATUS_NO_ERROR if successful, otherwise return @c NNFW_STATUS_ERROR
+ */
+NNFW_STATUS nnfw_prepare(nnfw_session *session);
+
+/**
+ * @brief     Run inference
+ *
+ * <p>This function should be called after model is loaded by {@link nnfw_load_model_from_file},
+ * session is prepared for inference by {@link nnfw_prepare}, set input and output buffers
+ * by {@link nnfw_set_input} and {@link nnfw_set_output}.</p>
+ *
+ * <p>This function return after inference is finished.</p>
+ *
+ * @param[in] session The session to run inference
+ * @return    @c NNFW_STATUS_NO_ERROR if successful
+ */
+NNFW_STATUS nnfw_run(nnfw_session *session);
+
+/**
+ * @brief     Set input buffer
+ *
+ * This function should be called after {@link nnfw_prepare}, and before first inference
+ * on session by {@link nnfw_run}. Application can reuse buffer for many inferences.
+ *
+ * @param[in] session Session to the input is to be set
+ * @param[in] index   Index of input to be set (0-indexed)
+ * @param[in] type    Type of the input
+ * @param[in] buffer  Raw buffer for input
+ * @param[in] length  Size of bytes of input buffer
+ *
+ * @return    @c NNFW_STATUS_NO_ERROR if successful
+ */
+NNFW_STATUS nnfw_set_input(nnfw_session *session, uint32_t index, NNFW_TYPE type,
+                           const void *buffer, size_t length);
+
+/**
+ * @brief       Set output buffer
+ *
+ * This function should be called after {@link nnfw_prepare}, and before first inference
+ * on session by {@link nnfw_run}. Application can reuse buffer for many inferences.
+ *
+ * @param[in]   session Session from inference output is to be extracted
+ * @param[in]   index   Index of output to be set (0-indexed)
+ * @param[in]   type    Type of the output
+ * @param[out]  buffer  Raw buffer for output
+ * @param[in]   length  Size of bytes of output buffer
+ *
+ * @return      @c NNFW_STATUS_NO_ERROR if successful
+ */
+NNFW_STATUS nnfw_set_output(nnfw_session *session, uint32_t index, NNFW_TYPE type, void *buffer,
+                            size_t length);
+
+/**
+ * @brief       Get the number of inputs
+ *
+ * Application can call this function to get number of inputs defined in loaded model.
+ * This function should be called after {@link nnfw_load_model_from_file} is invoked to load model
+ *
+ * @param[in]   session Session from input information is to be extracted
+ * @param[out]  number  Variable which the number of inputs is put into
+ *
+ * @return      @c NNFW_STATUS_NO_ERROR if successful
+ */
+NNFW_STATUS nnfw_input_size(nnfw_session *session, uint32_t *number);
+
+/**
+ * @brief       Get the number of outputs
+ *
+ * Application can call this function to get number of outputs defined in loaded model.
+ * This function should be called after {@link nnfw_load_model_from_file} is invoked to load model
+ *
+ * @param[in]   session Session from output information is to be extracted
+ * @param[out]  number  Variable which the number of outputs is put into
+ *
+ * @return      @c NNFW_STATUS_NO_ERROR if successful
+ */
+NNFW_STATUS nnfw_output_size(nnfw_session *session, uint32_t *number);
+
+/**
+ * @brief Set the layout of an input
+ *
+ * The input that does not call this has NNFW_LAYOUT_NHWC layout
+ *
+ * @param[in] session session from inference input is to be extracted
+ * @param[in] index   index of input to be set (0-indexed)
+ * @param[in] layout  layout to set to target input
+ *
+ * @return NNFW_STATUS_NO_ERROR if successful
+ */
+NNFW_STATUS nnfw_set_input_layout(nnfw_session *session, uint32_t index, NNFW_LAYOUT layout);
+
+/**
+ * @brief Set the layout of an output
+ *
+ * The output that does not call this has NNFW_LAYOUT_NHWC layout
+ *
+ * @param[in] session session from inference output is to be extracted
+ * @param[in] index   index of output to be set (0-indexed)
+ * @param[in] layout  layout to set to target output
+ *
+ * @return NNFW_STATUS_NO_ERROR if successful
+ */
+NNFW_STATUS nnfw_set_output_layout(nnfw_session *session, uint32_t index, NNFW_LAYOUT layout);
+
+/**
+ * @brief       Get i-th input tensor info
+ *
+ * <p>Before {@link nnfw_prepare} is invoked, this function return tensor info in model,
+ * so updated tensor info by {@link nnfw_apply_tensorinfo} is not returned.</p>
+ *
+ * <p>After {@link nnfw_prepare} is invoked, this function return updated tensor info
+ * if tensor info is updated by {@link nnfw_apply_tensorinfo}.</p>
+ *
+ * @param[in]   session     Session from input information is to be extracted
+ * @param[in]   index       Index of input
+ * @param[out]  tensor_info Tensor info (shape, type, etc)
+ *
+ * @return      @c NNFW_STATUS_NO_ERROR if successful
+ */
+NNFW_STATUS nnfw_input_tensorinfo(nnfw_session *session, uint32_t index,
+                                  nnfw_tensorinfo *tensor_info);
+
+/**
+ * @brief     Get i-th output tensor info
+ *
+ * <p>Before {@link nnfw_prepare} is invoked, this function return tensor info in model,
+ * so updated tensor info by {@link nnfw_apply_tensorinfo} is not returned.</p>
+ *
+ * <p>After {@link nnfw_prepare} is invoked, this function return updated tensor info
+ * if tensor info is updated by {@link nnfw_apply_tensorinfo}.</p>
+ *
+ * @param[in]   session     Session from output information is to be extracted
+ * @param[in]   index       Index of output
+ * @param[out]  tensor_info Tensor info (shape, type, etc)
+ *
+ * @return      @c NNFW_STATUS_NO_ERROR if successful
+ */
+NNFW_STATUS nnfw_output_tensorinfo(nnfw_session *session, uint32_t index,
+                                   nnfw_tensorinfo *tensor_info);
+
+/**
+ * @brief     Set available backends
+ *
+ * This function should be called before {@link nnfw_prepare} is invoked.
+ *
+ * <p>Supported backends differs on each platforms.
+ * For example, `x86_64` supports "cpu" only.
+ * Can set multiple backends by semicolon (ex: "acl_cl;cpu").
+ * Among the multiple backends, the 1st element is used as default backend.</p>
+ *
+ * @note      Possible backend strings are: "cpu", "acl_cl", "acl_neon", "srcn"
+ *
+ * @param[in] session session to which avilable backends are set
+ * @param[in] backends available backends on which nnfw uses
+ *
+ * @return @c NNFW_STATUS_NO_ERROR if successful
+ */
+NNFW_STATUS nnfw_set_available_backends(nnfw_session *session, const char *backends);
+
+/**
+ * @brief     Set the operation's backend
+ *
+ * This function should be called before {@link nnfw_prepare} is invoked.
+ *
+ * <p>Supported backends differs on each platforms.
+ * For example, `x86_64` supports "cpu" only.
+ * The backend for op has higher priority than default backend specified by
+ * nnfw_set_default_backend.</p>
+ *
+ * @note      Possible backend strings are: "cpu", "acl_cl", "acl_neon"
+ *
+ * @param[in] session session to be modified
+ * @param[in] op operation to be set
+ * @param[in] backend bakcend on which operation run
+ *
+ * @return @c NNFW_STATUS_NO_ERROR if successful
+ */
+NNFW_STATUS nnfw_set_op_backend(nnfw_session *session, const char *op, const char *backend);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/runtime/neurun/api/include/nnfw_debug.h b/runtime/neurun/api/include/nnfw_debug.h
new file mode 100644
index 000000000..eefca0d29
--- /dev/null
+++ b/runtime/neurun/api/include/nnfw_debug.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NNFW_DEBUG_H__
+#define __NNFW_DEBUG_H__
+
+#include "nnfw.h"
+
+NNFW_STATUS nnfw_create_debug_session(nnfw_session **session);
+
+#endif // __NNFW_DEBUG_H__
diff --git a/runtime/neurun/api/include/nnfw_dev.h b/runtime/neurun/api/include/nnfw_dev.h
new file mode 100644
index 000000000..ecf0597cf
--- /dev/null
+++ b/runtime/neurun/api/include/nnfw_dev.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NNFW_DEV_H__
+#define __NNFW_DEV_H__
+
+#include "nnfw.h"
+
+// Used for custom kernel development
+
+/*
+ * operand type, used only for custom operations
+ */
+typedef struct
+{
+  nnfw_tensorinfo type;
+  void *allocation;
+} nnfw_operand;
+
+/*
+ * Used as input to custom operation eval function
+ */
+typedef struct
+{
+  size_t ninputs;
+  nnfw_operand *inputs;
+
+  size_t noutputs;
+  nnfw_operand *outputs;
+} nnfw_custom_kernel_params;
+
+/*
+ * Custom kernel evaluation function
+ *
+ * param[in] params custom operation parameters
+ * param[in] userdata pointer to user-specified buffer( kernel instance specific )
+ */
+typedef void (*nnfw_custom_eval)(nnfw_custom_kernel_params *params, char *userdata,
+                                 size_t userdata_size);
+
+/*
+ * custom operation registration info
+ */
+typedef struct
+{
+  nnfw_custom_eval eval_function;
+} custom_kernel_registration_info;
+
+NNFW_STATUS nnfw_register_custom_op_info(nnfw_session *session, const char *id,
+                                         custom_kernel_registration_info *info);
+
+#endif // __NNFW_DEV_H__
diff --git a/runtime/neurun/api/src/CustomKernel.cc b/runtime/neurun/api/src/CustomKernel.cc
new file mode 100644
index 000000000..60ddeedc2
--- /dev/null
+++ b/runtime/neurun/api/src/CustomKernel.cc
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "CustomKernel.h"
+
+namespace neurun
+{
+namespace frontend
+{
+namespace custom
+{
+
+using namespace backend::custom;
+
+class APIConverter
+{
+public:
+  static nnfw_operand convertOperand(void *alloc, const TypeInfo &type)
+  {
+    nnfw_operand api_operand;
+    api_operand.allocation = alloc;
+    api_operand.type = convertType(type);
+    return api_operand;
+  }
+
+  static nnfw_tensorinfo convertType(const TypeInfo &type)
+  {
+    nnfw_tensorinfo api_type;
+    api_type.rank = type.shape.rank();
+    assert(type.shape.rank() <= 6);
+    std::copy(type.shape.dims().begin(), type.shape.dims().end(), std::begin(api_type.dims));
+
+    switch (type.dtype)
+    {
+      case ir::DataType::FLOAT32:
+        api_type.dtype = NNFW_TYPE_TENSOR_FLOAT32;
+        break;
+      case ir::DataType::INT32:
+        api_type.dtype = NNFW_TYPE_TENSOR_INT32;
+        break;
+      case ir::DataType::QUANT8_ASYMM:
+        api_type.dtype = NNFW_TYPE_TENSOR_QUANT8_ASYMM;
+        break;
+      case ir::DataType::BOOL8:
+        api_type.dtype = NNFW_TYPE_TENSOR_BOOL;
+        break;
+      default:
+        throw std::runtime_error("Unsupported tensor datatype");
+    }
+    return api_type;
+  }
+};
+
+Kernel::Kernel(const nnfw_custom_eval evalFunction)
+    : _params(), _userdata(nullptr), _userdata_size(0), _evalFunction(evalFunction)
+{
+}
+
+void Kernel::configure(CustomKernelConfigParams &&inParams)
+{
+  _userdata = inParams.userdata;
+  _userdata_size = inParams.userdata_size;
+
+  _params.ninputs = inParams.input_allocations.size();
+  _params.inputs = new nnfw_operand[_params.ninputs];
+  for (size_t i = 0; i < _params.ninputs; ++i)
+  {
+    _params.inputs[i] =
+        APIConverter::convertOperand(inParams.input_allocations[i], inParams.input_types[i]);
+  }
+
+  _params.noutputs = inParams.output_allocations.size();
+  _params.outputs = new nnfw_operand[_params.noutputs];
+  for (size_t i = 0; i < _params.noutputs; ++i)
+  {
+    _params.outputs[i] =
+        APIConverter::convertOperand(inParams.output_allocations[i], inParams.output_types[i]);
+  }
+}
+
+void Kernel::run() { _evalFunction(&_params, _userdata, _userdata_size); }
+
+} // namespace custom
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/api/src/CustomKernel.h b/runtime/neurun/api/src/CustomKernel.h
new file mode 100644
index 000000000..8cafc2061
--- /dev/null
+++ b/runtime/neurun/api/src/CustomKernel.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_CUSTOM_KERNEL_H__
+#define __NEURUN_BACKEND_CUSTOM_KERNEL_H__
+
+#include "nnfw_dev.h"
+
+#include "backend/CustomKernelBuilder.h"
+
+#include <vector>
+
+namespace neurun
+{
+namespace frontend
+{
+namespace custom
+{
+
+class Kernel : public ::neurun::exec::IFunction
+{
+public:
+  explicit Kernel(nnfw_custom_eval evalFunction);
+
+  nnfw_custom_kernel_params _params;
+  char *_userdata;
+  size_t _userdata_size;
+
+  nnfw_custom_eval _evalFunction;
+  // nnfw_custom_type_infer _type_infer_function; //Unused for now
+
+  /**
+   * Fills _params field used later by user specified eval function
+   * @param inParams custom kernel parameters
+   */
+  virtual void configure(backend::custom::CustomKernelConfigParams &&inParams);
+
+  void run() override;
+  void runSync() override { run(); }
+};
+
+} // namespace custom
+} // namespace frontend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_CUSTOM_KERNEL_H__
diff --git a/runtime/neurun/api/src/CustomKernelRegistry.cc b/runtime/neurun/api/src/CustomKernelRegistry.cc
new file mode 100644
index 000000000..b223682b8
--- /dev/null
+++ b/runtime/neurun/api/src/CustomKernelRegistry.cc
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "CustomKernelRegistry.h"
+
+#include "cpp14/memory.h"
+
+namespace neurun
+{
+namespace frontend
+{
+namespace custom
+{
+
+void KernelRegistry::registerKernel(const std::string &id, nnfw_custom_eval evalFunction)
+{
+  _storage.emplace(id, evalFunction);
+}
+
+std::shared_ptr<backend::custom::IKernelBuilder> KernelRegistry::getBuilder()
+{
+  return nnfw::cpp14::make_unique<KernelBuilder>(this);
+}
+
+std::unique_ptr<Kernel> KernelRegistry::buildKernelForOp(const std::string &id)
+{
+  auto it = _storage.find(id);
+  if (it == _storage.end())
+  {
+    throw std::runtime_error("Unable to find associated kernel for op");
+  }
+
+  return nnfw::cpp14::make_unique<Kernel>(it->second);
+}
+
+// Kernel builder
+std::unique_ptr<exec::IFunction>
+KernelBuilder::buildKernel(const std::string &id,
+                           backend::custom::CustomKernelConfigParams &&params) const
+{
+  auto kernel = _registry->buildKernelForOp(id);
+  kernel->configure(std::move(params));
+
+  return kernel;
+}
+
+KernelBuilder::KernelBuilder(KernelRegistry *registry) : _registry(registry) {}
+
+} // namespace custom
+} // namespace frontend
+} // namespace neurun
diff --git a/runtime/neurun/api/src/CustomKernelRegistry.h b/runtime/neurun/api/src/CustomKernelRegistry.h
new file mode 100644
index 000000000..207a82a0a
--- /dev/null
+++ b/runtime/neurun/api/src/CustomKernelRegistry.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_CUSTOM_KERNEL_REGISTRY_H__
+#define __NEURUN_BACKEND_CUSTOM_KERNEL_REGISTRY_H__
+
+#include "CustomKernel.h"
+
+#include <unordered_map>
+#include <functional>
+#include <memory>
+
+#include <iostream>
+
+namespace neurun
+{
+namespace frontend
+{
+namespace custom
+{
+
+class KernelRegistry
+{
+public:
+  void registerKernel(const std::string &id, nnfw_custom_eval evalFunction);
+
+  std::shared_ptr<backend::custom::IKernelBuilder> getBuilder();
+  std::unique_ptr<Kernel> buildKernelForOp(const std::string &id);
+
+private:
+  std::unordered_map<std::string, nnfw_custom_eval> _storage;
+};
+
+class KernelBuilder : public backend::custom::IKernelBuilder
+{
+public:
+  KernelBuilder(KernelRegistry *registry);
+
+  std::unique_ptr<exec::IFunction>
+  buildKernel(const std::string &id,
+              backend::custom::CustomKernelConfigParams &&params) const override;
+
+private:
+  KernelRegistry *_registry;
+};
+
+} // namespace custom
+} // namespace frontend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_CUSTOM_KERNEL_REGISTRY_H__
diff --git a/runtime/neurun/api/src/OpMap.lst b/runtime/neurun/api/src/OpMap.lst
new file mode 100644
index 000000000..5e93275b8
--- /dev/null
+++ b/runtime/neurun/api/src/OpMap.lst
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2020 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MAP_MACRO
+#error  Define MAP_MACRO before including this file
+#endif
+
+//        circle operation  | neurun internal operation
+MAP_MACRO(ADD               , Add)
+MAP_MACRO(SUB               , Sub)
+MAP_MACRO(BATCH_TO_SPACE_ND , BatchToSpaceND)
+MAP_MACRO(CAST              , Cast)
+MAP_MACRO(CONV_2D           , Conv2D)
+MAP_MACRO(DEPTHWISE_CONV_2D , DepthwiseConv2D)
+MAP_MACRO(AVERAGE_POOL_2D   , AvgPool2D)
+MAP_MACRO(MAX_POOL_2D       , MaxPool2D)
+MAP_MACRO(CONCATENATION     , Concat)
+MAP_MACRO(FULLY_CONNECTED   , FullyConnected)
+MAP_MACRO(SUM               , ReduceSum)
+MAP_MACRO(RESHAPE           , Reshape)
+MAP_MACRO(MUL               , Mul)
+MAP_MACRO(SOFTMAX           , Softmax)
+MAP_MACRO(SQUEEZE           , Squeeze)
+MAP_MACRO(SLICE             , Slice)
+MAP_MACRO(STRIDED_SLICE     , StridedSlice)
+MAP_MACRO(TANH              , Tanh)
+MAP_MACRO(LOGISTIC          , Logistic)
+MAP_MACRO(DIV               , Div)
+MAP_MACRO(TRANSPOSE         , Transpose)
+MAP_MACRO(EXP               , Exp)
+MAP_MACRO(REDUCE_MAX        , ReduceMax)
+// UNMATCHED
+//MAP_MACRO(Comparison)
+MAP_MACRO(LOGICAL_AND       , LogicalAnd)
+MAP_MACRO(LOGICAL_OR        , LogicalOr)
+MAP_MACRO(LOGICAL_NOT       , LogicalNot)
+MAP_MACRO(LSTM              , LSTM)
+MAP_MACRO(RSQRT             , RSQRT)
+MAP_MACRO(RELU              , ReLU)
+MAP_MACRO(RESIZE_BILINEAR   , ResizeBilinear)
+MAP_MACRO(RELU_N1_TO_1      , ReLU1)
+MAP_MACRO(RELU6             , ReLU6)
+MAP_MACRO(RNN , RNN)
+MAP_MACRO(FLOOR , Floor)
+MAP_MACRO(SPACE_TO_BATCH_ND , SpaceToBatchND)
+MAP_MACRO(SPACE_TO_DEPTH  , SpaceToDepth)
+MAP_MACRO(L2_POOL_2D  , L2Pool2D)
+MAP_MACRO(EMBEDDING_LOOKUP  , EmbeddingLookup)
+MAP_MACRO(L2_NORMALIZATION  , L2Normalization)
+MAP_MACRO(HASHTABLE_LOOKUP  , HashtableLookup)
+MAP_MACRO(INSTANCE_NORM , InstanceNorm)
+MAP_MACRO(PRELU , PReLU)
+MAP_MACRO(TRANSPOSE_CONV  , TransposeConv)
+MAP_MACRO(SQRT  , SQRT)
+MAP_MACRO(SQUARED_DIFFERENCE  , SquaredDifference)
+MAP_MACRO(TOPK_V2 , TopKV2)
+MAP_MACRO(GATHER  , Gather)
+MAP_MACRO(NEG , Neg)
+MAP_MACRO(ABS , Abs)
+MAP_MACRO(ARG_MAX , ArgMax)
+MAP_MACRO(DEQUANTIZE  , Dequantize)
+MAP_MACRO(MEAN  , Mean)
+MAP_MACRO(LOCAL_RESPONSE_NORMALIZATION  , LocalResponseNormalization)
+// UNDEFINED IN CIRCLE
+//MAP_MACRO(DepthToSpace)
+MAP_MACRO(PACK  , Pack)
+MAP_MACRO(REDUCE_MIN  , ReduceMin)
+MAP_MACRO(SPLIT , Split)
+MAP_MACRO(UNPACK  , Unpack)
+MAP_MACRO(PAD , Pad)
+MAP_MACRO(CUSTOM  , Custom)
+// UNDEFINED IN CIRCLE
+//MAP_MACRO(Permute)
+MAP_MACRO(MINIMUM , Min)
+MAP_MACRO(MAXIMUM , Max)
+MAP_MACRO(ONE_HOT , OneHot)
diff --git a/runtime/neurun/api/src/nnfw_api.cc b/runtime/neurun/api/src/nnfw_api.cc
new file mode 100644
index 000000000..bdac4c89b
--- /dev/null
+++ b/runtime/neurun/api/src/nnfw_api.cc
@@ -0,0 +1,267 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "nnfw_api_internal.h"
+
+/*
+ * Create a new session instance
+ *
+ * @param session the session to be created
+ * @return NNFW_STATUS_NO_ERROR if successful
+ */
+NNFW_STATUS nnfw_create_session(nnfw_session **session)
+{
+  *session = new nnfw_session();
+
+  return NNFW_STATUS_NO_ERROR;
+}
+
+/*
+ * Close a session instance
+ *
+ * @param session the session to be closed
+ * @return NNFW_STATUS_NO_ERROR if successful
+ */
+NNFW_STATUS nnfw_close_session(nnfw_session *session)
+{
+  delete session;
+  return NNFW_STATUS_NO_ERROR;
+}
+
+#define NNFW_RETURN_ERROR_IF_NULL(p) \
+  do                                 \
+  {                                  \
+    if ((p) == NULL)                 \
+      return NNFW_STATUS_ERROR;      \
+  } while (0)
+
+/*
+ * Load model from nnpackage file or directory
+ *
+ * @param session nnfw_session loading the given nnpackage file/dir
+ * @param package_file_path path to the nnpackage file or unzipped directory to be loaded
+ *
+ * @return NNFW_STATUS_NO_ERROR if successful
+ */
+NNFW_STATUS nnfw_load_model_from_file(nnfw_session *session, const char *pacakge_file_path)
+{
+  NNFW_RETURN_ERROR_IF_NULL(session);
+  return session->load_model_from_file(pacakge_file_path);
+}
+
+/*
+ * Prepare session to be ready for inference
+ * This phase may finalize model compilation, scheduling, and additional settings.
+ *
+ * @param session the session to be prepared
+ * @return NNFW_STATUS_NO_ERROR if successful
+ */
+NNFW_STATUS nnfw_prepare(nnfw_session *session)
+{
+  NNFW_RETURN_ERROR_IF_NULL(session);
+  return session->prepare();
+}
+
+/*
+ * Run inference
+ *
+ * @param session the session to run inference
+ * @return NNFW_STATUS_NO_ERROR if successful
+ */
+NNFW_STATUS nnfw_run(nnfw_session *session)
+{
+  NNFW_RETURN_ERROR_IF_NULL(session);
+  return session->run();
+}
+
+/*
+ * Set input
+ *
+ * @param session session to the input is to be set
+ * @param index index of input to be set (0-indexed)
+ * @param type type of the input
+ * @param buffer raw buffer for input
+ * @param length size of bytes of output
+ *
+ * @return NNFW_STATUS_NO_ERROR if successful
+ */
+
+NNFW_STATUS nnfw_set_input(nnfw_session *session, uint32_t index, NNFW_TYPE type,
+                           const void *buffer, size_t length)
+{
+  NNFW_RETURN_ERROR_IF_NULL(session);
+  return session->set_input(index, type, buffer, length);
+}
+
+/*
+ * Set output
+ *
+ * @param session session from inference output is to be extracted
+ * @param index index of output to be set (0-indexed)
+ * @param type type of the output
+ * @param buffer raw buffer for output
+ * @param length size of bytes of output
+ *
+ * @return NNFW_STATUS_NO_ERROR if successful
+ */
+
+NNFW_STATUS nnfw_set_output(nnfw_session *session, uint32_t index, NNFW_TYPE type, void *buffer,
+                            size_t length)
+{
+  NNFW_RETURN_ERROR_IF_NULL(session);
+  return session->set_output(index, type, buffer, length);
+}
+
+/*
+ * Get the number of inputs
+ *
+ * @param[in] session session from input information is to be extracted
+ * @param[out] number variable which the number of inputs is put into
+ *
+ * @return NNFW_STATUS_NO_ERROR if successful
+ */
+
+NNFW_STATUS nnfw_input_size(nnfw_session *session, uint32_t *number)
+{
+  NNFW_RETURN_ERROR_IF_NULL(session);
+  return session->input_size(number);
+}
+
+/*
+ * Get the number of outputs
+ *
+ * @param[in] session session from output information is to be extracted
+ * @param[out] number variable which the number of outputs is put into
+ *
+ * @return NNFW_STATUS_NO_ERROR if successful
+ */
+NNFW_STATUS nnfw_output_size(nnfw_session *session, uint32_t *number)
+{
+  NNFW_RETURN_ERROR_IF_NULL(session);
+  return session->output_size(number);
+}
+
+/*
+ * Set the layout of an input
+ * @note The input that does not call this has NNFW_LAYOUT_CHANNELS_LAST layout
+ *
+ * @param[in] session session from inference input is to be extracted
+ * @param[in] index   index of input to be set (0-indexed)
+ * @param[in] layout  layout to set to target input
+ *
+ * @return NNFW_STATUS_NO_ERROR if successful
+ */
+NNFW_STATUS nnfw_set_input_layout(nnfw_session *session, uint32_t index, NNFW_LAYOUT layout)
+{
+  NNFW_RETURN_ERROR_IF_NULL(session);
+  return session->set_input_layout(index, layout);
+}
+
+/*
+ * Set the layout of an output
+ * @note The output that does not call this has NNFW_LAYOUT_CHANNELS_LAST layout
+ *
+ * @param[in] session session from inference output is to be extracted
+ * @param[in] index   index of output to be set (0-indexed)
+ * @param[in] layout  layout to set to target output
+ *
+ * @return NNFW_STATUS_NO_ERROR if successful
+ */
+NNFW_STATUS nnfw_set_output_layout(nnfw_session *session, uint32_t index, NNFW_LAYOUT layout)
+{
+  NNFW_RETURN_ERROR_IF_NULL(session);
+  return session->set_output_layout(index, layout);
+}
+
+/*
+ * Get i-th input tensor info
+ *
+ * @param[in] session session from input information is to be extracted
+ * @param[in] index index of input
+ * @param[out] tensor_info nnfw_tensor_info
+ *
+ * @return NNFW_STATUS_NO_ERROR if successful
+ */
+NNFW_STATUS nnfw_input_tensorinfo(nnfw_session *session, uint32_t index,
+                                  nnfw_tensorinfo *tensor_info)
+{
+  NNFW_RETURN_ERROR_IF_NULL(session);
+  return session->input_tensorinfo(index, tensor_info);
+}
+
+/*
+ * Get i-th output tensor info
+ *
+ * @param[in] session session from output information is to be extracted
+ * @param[in] index index of output
+ * @param[out] tensor_info nnfw_tensor_info
+ *
+ * @return NNFW_STATUS_NO_ERROR if successful
+ */
+NNFW_STATUS nnfw_output_tensorinfo(nnfw_session *session, uint32_t index,
+                                   nnfw_tensorinfo *tensor_info)
+{
+  NNFW_RETURN_ERROR_IF_NULL(session);
+  return session->output_tensorinfo(index, tensor_info);
+}
+
+/*
+ * Register custom operation
+ * @param session session to register this operation
+ * @param id operation id
+ * @param info registration info ( eval function, etc. )
+ * @return NNFW_STATUS_NO_ERROR if successful
+ */
+NNFW_STATUS nnfw_register_custom_op_info(nnfw_session *session, const char *id,
+                                         custom_kernel_registration_info *info)
+{
+  NNFW_RETURN_ERROR_IF_NULL(session);
+  return session->register_custom_operation(id, info->eval_function);
+}
+
+NNFW_STATUS nnfw_apply_tensorinfo(nnfw_session *session, uint32_t index,
+                                  nnfw_tensorinfo tensor_info)
+{
+  NNFW_RETURN_ERROR_IF_NULL(session);
+  return session->apply_tensorinfo(index, tensor_info);
+}
+
+/*
+ * Set available backends
+ *
+ * @param[in] session session to which a avilable backends are set
+ * @param[in] backends available backends on which nnfw uses
+ */
+NNFW_STATUS nnfw_set_available_backends(nnfw_session *session, const char *backends)
+{
+  NNFW_RETURN_ERROR_IF_NULL(session);
+  return session->set_available_backends(backends);
+}
+
+/*
+ * Set the operation's backend
+ *
+ * @param[in] session session to be modified
+ * @param[in] op operation to be set
+ * @param[in] backend bakcend on which operation run
+ *
+ * @return NNFW_STATUS_NO_ERROR if successful
+ */
+NNFW_STATUS nnfw_set_op_backend(nnfw_session *session, const char *op, const char *backend)
+{
+  NNFW_RETURN_ERROR_IF_NULL(session);
+  return session->set_op_backend(op, backend);
+}
diff --git a/runtime/neurun/api/src/nnfw_api_internal.cc b/runtime/neurun/api/src/nnfw_api_internal.cc
new file mode 100644
index 000000000..037cd3bca
--- /dev/null
+++ b/runtime/neurun/api/src/nnfw_api_internal.cc
@@ -0,0 +1,435 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "nnfw_api_internal.h"
+#include "CustomKernelRegistry.h"
+#include "compiler/Compiler.h"
+#include "exec/Execution.h"
+#include "circle_loader.h"
+#include "tflite_loader.h"
+#include "json/json.h"
+#include <fstream>
+#include <iostream>
+#include <string>
+#include <dirent.h>
+#include <util/ConfigSource.h>
+
+/*
+ * API does not accept string argument longer than max length below
+ */
+#define MAX_BACKEND_NAME_LENGTH 32
+#define MAX_OP_NAME_LENGTH 64
+
+// Is null-terminating in length ?
+static bool null_terminating(const char *str, uint32_t length)
+{
+  for (uint32_t i = 0; i < length; i++)
+  {
+    if (*(str + i) == '\0')
+    {
+      return true;
+    }
+  }
+  return false;
+}
+
+static neurun::ir::Layout convertLayout(NNFW_LAYOUT layout)
+{
+  if (layout == NNFW_LAYOUT_CHANNELS_LAST)
+  {
+    return neurun::ir::Layout::NHWC;
+  }
+  else if (layout == NNFW_LAYOUT_CHANNELS_FIRST)
+  {
+    return neurun::ir::Layout::NCHW;
+  }
+  return neurun::ir::Layout::UNKNOWN;
+}
+
+nnfw_session::nnfw_session()
+    : _graph{nullptr}, _execution{nullptr},
+      _kernel_registry{std::make_shared<neurun::frontend::custom::KernelRegistry>()},
+      _source{nnfw::cpp14::make_unique<neurun::util::GeneralConfigSource>()}
+{
+  // DO NOTHING
+}
+
+NNFW_STATUS nnfw_session::load_model_from_file(const char *package_dir)
+{
+  // TODO : add support for zipped package file load
+  DIR *dir;
+  if (!(dir = opendir(package_dir)))
+  {
+    std::cerr << "invalid nnpackge directory: " << package_dir << std::endl;
+    return NNFW_STATUS_ERROR;
+  }
+  closedir(dir);
+
+  try
+  {
+    std::string manifest_file_name(package_dir);
+    manifest_file_name += "/metadata/MANIFEST";
+    std::ifstream mfs(manifest_file_name);
+
+    // extract the filename of the first(index 0) model
+    // e.g. In MANIFEST file, { "models" : [ "firstmodel.tflite", "2nd.tflite" ] }
+    Json::Value root;
+    mfs >> root;
+    Json::Value models = root["models"];
+    Json::Value model_types = root["model-types"];
+
+    auto model_file_path = package_dir + std::string("/") + models[0].asString(); // first model
+    auto model_type = model_types[0].asString(); // first model's type
+    if (model_type == "tflite")
+    {
+      _graph = neurun::tflite_loader::loadModel(model_file_path.c_str());
+    }
+    else if (model_type == "circle")
+    {
+      _graph = neurun::circle_loader::loadModel(model_file_path.c_str());
+    }
+    else
+    {
+      std::cerr << "Unsupported model type in MANIFEST" << std::endl;
+      return NNFW_STATUS_ERROR;
+    }
+    _graph->bindKernelBuilder(_kernel_registry->getBuilder());
+  }
+  catch (const std::exception &e)
+  {
+    std::cerr << "Error during model loading : " << e.what() << std::endl;
+    return NNFW_STATUS_ERROR;
+  }
+  return NNFW_STATUS_NO_ERROR;
+}
+
+NNFW_STATUS nnfw_session::prepare()
+{
+  // TODO : add additional setting routine(executor type, backend)
+  // Note that we assume acl_cl backend
+
+  try
+  {
+    // config_source setting
+    using neurun::util::config_source;
+    config_source(std::move(_source));
+
+    auto compiler = nnfw::cpp14::make_unique<neurun::compiler::Compiler>(_graph);
+    compiler->compile();
+    std::shared_ptr<neurun::exec::IExecutor> executor;
+    compiler->release(executor);
+    _execution = std::make_shared<neurun::exec::Execution>(executor);
+  }
+  catch (const std::exception &e)
+  {
+    std::cerr << "Error during model prepare : " << e.what() << std::endl;
+    return NNFW_STATUS_ERROR;
+  }
+  return NNFW_STATUS_NO_ERROR;
+}
+
+NNFW_STATUS nnfw_session::run()
+{
+  try
+  {
+    _execution->execute();
+  }
+  catch (const std::exception &e)
+  {
+    std::cerr << "Error during nnfw_session::run : " << e.what() << std::endl;
+    return NNFW_STATUS_ERROR;
+  }
+  return NNFW_STATUS_NO_ERROR;
+}
+
+NNFW_STATUS nnfw_session::set_input(uint32_t index, NNFW_TYPE /*type*/, const void *buffer,
+                                    size_t length)
+{
+  try
+  {
+    _execution->setInput(neurun::ir::IOIndex(index), buffer, length);
+  }
+  catch (const std::exception &e)
+  {
+    std::cerr << "Error during nnfw_session::set_input : " << e.what() << std::endl;
+    return NNFW_STATUS_ERROR;
+  }
+  return NNFW_STATUS_NO_ERROR;
+}
+
+NNFW_STATUS nnfw_session::set_output(uint32_t index, NNFW_TYPE /*type*/, void *buffer,
+                                     size_t length)
+{
+  try
+  {
+    _execution->setOutput(neurun::ir::IOIndex(index), buffer, length);
+  }
+  catch (const std::exception &e)
+  {
+    std::cerr << "Error during nnfw_session::set_output : " << e.what() << std::endl;
+    return NNFW_STATUS_ERROR;
+  }
+  return NNFW_STATUS_NO_ERROR;
+}
+
+NNFW_STATUS nnfw_session::input_size(uint32_t *number)
+{
+  try
+  {
+    if (number == nullptr)
+    {
+      std::cerr << "Error during nnfw_session::input_size, number is null pointer." << std::endl;
+      return NNFW_STATUS_ERROR;
+    }
+    *number = _graph->getInputs().size();
+  }
+  catch (const std::exception &e)
+  {
+    std::cerr << "Error during nnfw_session::input_size : " << e.what() << std::endl;
+    return NNFW_STATUS_ERROR;
+  }
+  return NNFW_STATUS_NO_ERROR;
+}
+
+NNFW_STATUS nnfw_session::output_size(uint32_t *number)
+{
+  try
+  {
+    if (number == nullptr)
+    {
+      std::cerr << "Error during nnfw_session::output_size, number is null pointer." << std::endl;
+      return NNFW_STATUS_ERROR;
+    }
+    *number = _graph->getOutputs().size();
+  }
+  catch (const std::exception &e)
+  {
+    std::cerr << "Error during nnfw_session::output_size" << e.what() << std::endl;
+    return NNFW_STATUS_ERROR;
+  }
+  return NNFW_STATUS_NO_ERROR;
+}
+
+NNFW_STATUS nnfw_session::set_input_layout(uint32_t index, NNFW_LAYOUT layout)
+{
+  try
+  {
+    if (layout != NNFW_LAYOUT_NONE && layout != NNFW_LAYOUT_CHANNELS_FIRST &&
+        layout != NNFW_LAYOUT_CHANNELS_LAST)
+    {
+      std::cerr << "Error during nnfw_session::set_input_layout, not supported layout" << std::endl;
+      return NNFW_STATUS_ERROR;
+    }
+    _execution->setInputLayout(neurun::ir::IOIndex(index), convertLayout(layout));
+  }
+  catch (const std::exception &e)
+  {
+    std::cerr << "Error during nnfw_session::set_input_layout : " << e.what() << std::endl;
+    return NNFW_STATUS_ERROR;
+  }
+  return NNFW_STATUS_NO_ERROR;
+}
+
+NNFW_STATUS nnfw_session::set_output_layout(uint32_t index, NNFW_LAYOUT layout)
+{
+  try
+  {
+    if (layout != NNFW_LAYOUT_NONE && layout != NNFW_LAYOUT_CHANNELS_FIRST &&
+        layout != NNFW_LAYOUT_CHANNELS_LAST)
+    {
+      std::cerr << "Error during nnfw_session::set_output_layout, not supported layout"
+                << std::endl;
+      return NNFW_STATUS_ERROR;
+    }
+    _execution->setOutputLayout(neurun::ir::IOIndex(index), convertLayout(layout));
+  }
+  catch (const std::exception &e)
+  {
+    std::cerr << "Error during nnfw_session::set_output_layout : " << e.what() << std::endl;
+    return NNFW_STATUS_ERROR;
+  }
+  return NNFW_STATUS_NO_ERROR;
+}
+
+static NNFW_TYPE datatype_to_nnfw_dtype(neurun::ir::DataType dt)
+{
+  using neurun::ir::DataType;
+  switch (dt)
+  {
+    case DataType::FLOAT32:
+      return NNFW_TYPE_TENSOR_FLOAT32;
+    case DataType::INT32:
+      return NNFW_TYPE_TENSOR_INT32;
+    case DataType::QUANT8_ASYMM:
+      return NNFW_TYPE_TENSOR_QUANT8_ASYMM;
+    case DataType::BOOL8:
+      return NNFW_TYPE_TENSOR_BOOL;
+    case DataType::UINT8:
+      return NNFW_TYPE_TENSOR_UINT8;
+    case DataType::UINT32:
+    case DataType::QUANT8_SYMM:
+    default:
+      std::cerr << "Error: Model has type that runtime API does not support." << std::endl;
+      exit(-1);
+  }
+}
+
+NNFW_STATUS nnfw_session::apply_tensorinfo(uint32_t /*index*/, nnfw_tensorinfo /*ti*/)
+{
+  std::cerr << "Error: NYI" << std::endl;
+  return NNFW_STATUS_ERROR;
+}
+
+NNFW_STATUS nnfw_session::input_tensorinfo(uint32_t index, nnfw_tensorinfo *ti)
+{
+  try
+  {
+    if (ti == nullptr)
+    {
+      std::cerr << "Error during nnfw_session::input_tensorinfo, tensorinfo is null pointer."
+                << std::endl;
+      return NNFW_STATUS_ERROR;
+    }
+    if (index >= _graph->getInputs().size())
+    {
+      std::cerr << "Error during nnfw_session::input_tensorinfo, index is out of range."
+                << std::endl;
+      return NNFW_STATUS_ERROR;
+    }
+    auto opidx = _graph->getInputs().at(index);
+    auto shape = _graph->operands().at(opidx).shape();
+    ti->rank = shape.rank();
+    for (int j = 0; j < ti->rank; ++j)
+    {
+      ti->dims[j] = shape.dim(j);
+    }
+    ti->dtype = datatype_to_nnfw_dtype(_graph->operands().at(opidx).typeInfo().type());
+  }
+  catch (const std::exception &e)
+  {
+    std::cerr << "Error during nnfw_session::input_tensorinfo : " << e.what() << std::endl;
+    return NNFW_STATUS_ERROR;
+  }
+  return NNFW_STATUS_NO_ERROR;
+}
+
+NNFW_STATUS nnfw_session::output_tensorinfo(uint32_t index, nnfw_tensorinfo *ti)
+{
+  try
+  {
+    if (ti == nullptr)
+    {
+      std::cerr << "Error during nnfw_session::output_tensorinfo, tensorinfo is null pointer."
+                << std::endl;
+      return NNFW_STATUS_ERROR;
+    }
+    if (index >= _graph->getOutputs().size())
+    {
+      std::cerr << "Error during nnfw_session::output_tensorinfo, index is out of range."
+                << std::endl;
+      return NNFW_STATUS_ERROR;
+    }
+    auto opidx = _graph->getOutputs().at(index);
+    auto shape = _graph->operands().at(opidx).shape();
+    ti->rank = shape.rank();
+    for (int j = 0; j < ti->rank; ++j)
+    {
+      ti->dims[j] = shape.dim(j);
+    }
+    ti->dtype = datatype_to_nnfw_dtype(_graph->operands().at(opidx).typeInfo().type());
+  }
+  catch (const std::exception &e)
+  {
+    std::cerr << "Error during nnfw_session::output_tensorinfo : " << e.what() << std::endl;
+    return NNFW_STATUS_ERROR;
+  }
+  return NNFW_STATUS_NO_ERROR;
+}
+NNFW_STATUS nnfw_session::register_custom_operation(const std::string &id,
+                                                    nnfw_custom_eval eval_func)
+{
+  _kernel_registry->registerKernel(id, eval_func);
+  return NNFW_STATUS_NO_ERROR;
+}
+
+static std::string get_op_backend_string(std::string op)
+{
+#define MAP_MACRO(CircleName, NeurunName) {#CircleName, "OP_BACKEND_" #NeurunName},
+
+  static std::unordered_map<std::string, std::string> operation_map = {
+#include "OpMap.lst"
+  };
+
+#undef MAP_MACRO
+
+  auto n = operation_map.find(op);
+
+  if (n == operation_map.end())
+  {
+    // this return value is handled by a caller to return error code
+    return std::string("");
+  }
+  else
+  {
+    return n->second;
+  }
+}
+
+NNFW_STATUS nnfw_session::set_available_backends(const char *backends)
+{
+  try
+  {
+    if (!backends || null_terminating(backends, MAX_BACKEND_NAME_LENGTH) == false)
+    {
+      return NNFW_STATUS_ERROR;
+    }
+
+    _source->set("BACKENDS", backends);
+  }
+  catch (const std::exception &e)
+  {
+    std::cerr << "Error during nnfw_session::set_available_backends : " << e.what() << std::endl;
+    return NNFW_STATUS_ERROR;
+  }
+  return NNFW_STATUS_NO_ERROR;
+}
+
+NNFW_STATUS nnfw_session::set_op_backend(const char *op, const char *backend)
+{
+  try
+  {
+    if (!op || !null_terminating(op, MAX_OP_NAME_LENGTH) || !backend ||
+        !null_terminating(backend, MAX_BACKEND_NAME_LENGTH))
+    {
+      return NNFW_STATUS_ERROR;
+    }
+
+    auto key = get_op_backend_string(op);
+
+    if (key.empty())
+    {
+      return NNFW_STATUS_ERROR;
+    }
+
+    _source->set(key, backend);
+  }
+  catch (const std::exception &e)
+  {
+    std::cerr << "Error during nnfw_session::set_op_backend : " << e.what() << std::endl;
+    return NNFW_STATUS_ERROR;
+  }
+  return NNFW_STATUS_NO_ERROR;
+}
diff --git a/runtime/neurun/api/src/nnfw_api_internal.h b/runtime/neurun/api/src/nnfw_api_internal.h
new file mode 100644
index 000000000..40069cc55
--- /dev/null
+++ b/runtime/neurun/api/src/nnfw_api_internal.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __API_NNFW_API_INTERNAL_H__
+#define __API_NNFW_API_INTERNAL_H__
+
+#include "nnfw.h"
+#include "nnfw_dev.h"
+
+#include <util/GeneralConfigSource.h>
+
+#include <string>
+#include <memory>
+
+namespace neurun
+{
+namespace frontend
+{
+namespace custom
+{
+class KernelRegistry;
+}
+} // namespace frontend
+namespace exec
+{
+class Execution;
+}
+namespace ir
+{
+class Graph;
+} // namespace ir
+} // namespace neurun
+
+struct nnfw_session
+{
+public:
+  nnfw_session();
+
+  NNFW_STATUS load_model_from_file(const char *package_file_path);
+  NNFW_STATUS prepare();
+  NNFW_STATUS run();
+
+  NNFW_STATUS set_input(uint32_t index, NNFW_TYPE type, const void *buffer, size_t length);
+  NNFW_STATUS set_output(uint32_t index, NNFW_TYPE type, void *buffer, size_t length);
+
+  NNFW_STATUS input_size(uint32_t *number);
+  NNFW_STATUS output_size(uint32_t *number);
+
+  NNFW_STATUS set_input_layout(uint32_t index, NNFW_LAYOUT layout);
+  NNFW_STATUS set_output_layout(uint32_t index, NNFW_LAYOUT layout);
+
+  NNFW_STATUS apply_tensorinfo(uint32_t index, nnfw_tensorinfo ti);
+
+  NNFW_STATUS input_tensorinfo(uint32_t index, nnfw_tensorinfo *ti);
+  NNFW_STATUS output_tensorinfo(uint32_t index, nnfw_tensorinfo *ti);
+
+  NNFW_STATUS register_custom_operation(const std::string &id, nnfw_custom_eval eval_func);
+
+  NNFW_STATUS set_available_backends(const char *backends);
+  NNFW_STATUS set_op_backend(const char *op, const char *backend);
+
+private:
+  std::shared_ptr<neurun::ir::Graph> _graph;
+  std::shared_ptr<neurun::exec::Execution> _execution;
+  std::shared_ptr<neurun::frontend::custom::KernelRegistry> _kernel_registry;
+
+protected:
+  std::unique_ptr<neurun::util::GeneralConfigSource> _source;
+};
+
+#endif // __API_NNFW_API_INTERNAL_H__
diff --git a/runtime/neurun/api/src/nnfw_debug.cc b/runtime/neurun/api/src/nnfw_debug.cc
new file mode 100644
index 000000000..4ea0a203f
--- /dev/null
+++ b/runtime/neurun/api/src/nnfw_debug.cc
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "nnfw_debug_internal.h"
+
+NNFW_STATUS nnfw_create_debug_session(nnfw_session **session)
+{
+  *session = new nnfw_debug_session();
+
+  return NNFW_STATUS_NO_ERROR;
+}
diff --git a/runtime/neurun/api/src/nnfw_debug_internal.cc b/runtime/neurun/api/src/nnfw_debug_internal.cc
new file mode 100644
index 000000000..778efbc5c
--- /dev/null
+++ b/runtime/neurun/api/src/nnfw_debug_internal.cc
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "nnfw_debug_internal.h"
+#include "util/EnvConfigSource.h"
+
+#include <cpp14/memory.h>
+
+nnfw_debug_session::nnfw_debug_session() : nnfw_session()
+{
+  _source = nnfw::cpp14::make_unique<neurun::util::EnvConfigSource>();
+}
diff --git a/runtime/neurun/api/src/nnfw_debug_internal.h b/runtime/neurun/api/src/nnfw_debug_internal.h
new file mode 100644
index 000000000..f4984e7a1
--- /dev/null
+++ b/runtime/neurun/api/src/nnfw_debug_internal.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __API_NNFW_DEBUG_INTERNAL_H__
+#define __API_NNFW_DEBUG_INTERNAL_H__
+
+#include "nnfw_debug.h"
+#include "nnfw_api_internal.h"
+
+class nnfw_debug_session : public nnfw_session
+{
+public:
+  nnfw_debug_session();
+};
+
+#endif // __API_NNFW_DEBUG_INTERNAL_H__
diff --git a/runtime/neurun/backend/CMakeLists.txt b/runtime/neurun/backend/CMakeLists.txt
new file mode 100644
index 000000000..fc363e031
--- /dev/null
+++ b/runtime/neurun/backend/CMakeLists.txt
@@ -0,0 +1,10 @@
+set(LIB_NEURUN_BACKEND_ACL_COMMON neurun_backend_acl_common)
+set(LIB_NEURUN_BACKEND_CPU_COMMON neurun_backend_cpu_common)
+
+add_subdirectory(cpu)
+add_subdirectory(cpu_common)
+add_subdirectory(acl_cl)
+add_subdirectory(acl_neon)
+add_subdirectory(acl_common)
+add_subdirectory(hi_perf_cpu)
+add_subdirectory(srcn)
diff --git a/runtime/neurun/backend/acl_cl/Backend.h b/runtime/neurun/backend/acl_cl/Backend.h
new file mode 100644
index 000000000..2033b42e7
--- /dev/null
+++ b/runtime/neurun/backend/acl_cl/Backend.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ACL_CL_BACKEND_H__
+#define __NEURUN_BACKEND_ACL_CL_BACKEND_H__
+
+#include <memory>
+#include <backend/Backend.h>
+#include <ir/Operands.h>
+
+#include "Config.h"
+#include "ConstantInitializer.h"
+#include "KernelGenerator.h"
+#include "ShapeFixer.h"
+#include "TensorManager.h"
+#include "TensorRegister.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_cl
+{
+
+class Backend : public ::neurun::backend::Backend
+{
+public:
+  Backend() : _config{std::make_shared<Config>()} {}
+
+  std::shared_ptr<IConfig> config() const override { return _config; }
+
+  std::unique_ptr<BackendContext>
+  newContext(const ir::Operands &operands,
+             const std::shared_ptr<custom::IKernelBuilder> &) const override
+  {
+    auto tensor_builder = std::make_shared<TensorBuilder>(createTensorManager());
+    return std::unique_ptr<BackendContext>{new BackendContext{
+        this, tensor_builder, std::make_shared<ConstantInitializer>(operands, tensor_builder),
+        std::make_shared<KernelGenerator>(operands, tensor_builder),
+        std::make_shared<ShapeFixer>(operands, tensor_builder),
+        std::make_shared<TensorRegister>(operands, tensor_builder)}};
+  }
+
+private:
+  std::shared_ptr<IConfig> _config;
+};
+
+} // namespace acl_cl
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ACL_CL_BACKEND_H__
diff --git a/runtime/neurun/backend/acl_cl/CLTimer.h b/runtime/neurun/backend/acl_cl/CLTimer.h
new file mode 100644
index 000000000..3939ee722
--- /dev/null
+++ b/runtime/neurun/backend/acl_cl/CLTimer.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ACL_CL_CLTIMER_H__
+#define __NEURUN_BACKEND_ACL_CL_CLTIMER_H__
+
+#include <util/ITimer.h>
+#include <arm_compute/core/CL/OpenCL.h>
+#include <arm_compute/runtime/CL/CLScheduler.h>
+#include <chrono>
+#include <list>
+#include <sstream>
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_cl
+{
+
+/**
+ * @brief Class to measure CL kernels execution time
+ */
+class CLTimer : public util::ITimer
+{
+public:
+  /**
+   * @brief This function replaces CL function, which enqueues a command to execute a kernel
+   *        with a wrapper which remembers enqueued kernels
+   */
+  void handleBegin() override
+  {
+    _measured_events.clear();
+
+    _origin_enqueue_function = arm_compute::CLSymbols::get().clEnqueueNDRangeKernel_ptr;
+
+    auto _timer_enqueue_function = [this](cl_command_queue command_queue, cl_kernel kernel,
+                                          cl_uint work_dim, const size_t *gwo, const size_t *gws,
+                                          const size_t *lws, cl_uint num_events_in_wait_list,
+                                          const cl_event *event_wait_list, cl_event *usr_event) {
+      cl_event event;
+      cl_int enqueue_res =
+          this->_origin_enqueue_function(command_queue, kernel, work_dim, gwo, gws, lws,
+                                         num_events_in_wait_list, event_wait_list, &event);
+      this->_measured_events.emplace_back(event);
+
+      // According to spec, if NULL was provided in usr_event - event shouldn't be returned
+      if (usr_event != nullptr)
+      {
+        clRetainEvent(event);
+        *usr_event = event;
+      }
+      return enqueue_res;
+    };
+    arm_compute::CLSymbols::get().clEnqueueNDRangeKernel_ptr = _timer_enqueue_function;
+
+    // Set CL_QUEUE_PROFILING_ENABLE flag for the CL command-queue, if it isn't already set
+    auto &cl_scheduler = arm_compute::CLScheduler::get();
+    auto props = cl_scheduler.queue().getInfo<CL_QUEUE_PROPERTIES>();
+    if ((props & CL_QUEUE_PROFILING_ENABLE) == 0)
+    {
+      cl_scheduler.set_queue(
+          cl::CommandQueue(cl_scheduler.context(), props | CL_QUEUE_PROFILING_ENABLE));
+    }
+  };
+
+  /**
+   * @brief Get timer result by addition executed CL kernels durations
+   */
+  void handleEnd() override
+  {
+    _timer_res = 0;
+    for (auto const &event : _measured_events)
+    {
+      cl_ulong start;
+      cl_ulong end;
+      event.getProfilingInfo(CL_PROFILING_COMMAND_START, &start);
+      event.getProfilingInfo(CL_PROFILING_COMMAND_END, &end);
+      _timer_res += (end - start) / 1000.f; // nanoseconds -> microseconds
+    }
+
+    // Restore origin CL enqueue function
+    arm_compute::CLSymbols::get().clEnqueueNDRangeKernel_ptr = _origin_enqueue_function;
+  };
+
+private:
+  std::function<decltype(clEnqueueNDRangeKernel)> _origin_enqueue_function;
+  std::list<::cl::Event> _measured_events;
+};
+
+} // namespace acl_cl
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ACL_CL_CLTIMER_H__
diff --git a/runtime/neurun/backend/acl_cl/CMakeLists.txt b/runtime/neurun/backend/acl_cl/CMakeLists.txt
new file mode 100644
index 000000000..aaf6a4d62
--- /dev/null
+++ b/runtime/neurun/backend/acl_cl/CMakeLists.txt
@@ -0,0 +1,21 @@
+# Unsupported architecture
+nnas_find_package(ARMCompute QUIET)
+if(NOT ARMCompute_FOUND)
+  return()
+endif(NOT ARMCompute_FOUND)
+
+set(LIB_NEURUN_BACKEND_ACL_CL neurun_backend_acl_cl)
+
+file(GLOB_RECURSE SOURCES "*.cc")
+
+add_library(${LIB_NEURUN_BACKEND_ACL_CL} SHARED ${SOURCES})
+
+target_include_directories(${LIB_NEURUN_BACKEND_ACL_CL} PRIVATE ${CMAKE_CURRENT_SOURCE_DIR})
+target_link_libraries(${LIB_NEURUN_BACKEND_ACL_CL} PRIVATE neurun_core)
+target_link_libraries(${LIB_NEURUN_BACKEND_ACL_CL} PRIVATE ${LIB_NEURUN_BACKEND_ACL_COMMON})
+target_link_libraries(${LIB_NEURUN_BACKEND_ACL_CL} PRIVATE nnfw_common)
+target_link_libraries(${LIB_NEURUN_BACKEND_ACL_CL} PRIVATE nnfw_coverage)
+
+set_target_properties(${LIB_NEURUN_BACKEND_ACL_CL} PROPERTIES OUTPUT_NAME backend_acl_cl)
+
+install(TARGETS ${LIB_NEURUN_BACKEND_ACL_CL} DESTINATION lib)
diff --git a/runtime/neurun/backend/acl_cl/Config.cc b/runtime/neurun/backend/acl_cl/Config.cc
new file mode 100644
index 000000000..36bf83686
--- /dev/null
+++ b/runtime/neurun/backend/acl_cl/Config.cc
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+// For CLKernelLibraryEx initialization
+#include "arm_compute/core/CL/CLHelpers.h"
+#include "arm_compute/core/CL/CLKernelLibrary.h"
+#include "arm_compute/core/CL/CLKernelLibraryEx.h"
+
+#include <arm_compute/runtime/CL/CLScheduler.h>
+
+#include "Config.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_cl
+{
+
+bool Config::initialize()
+{
+  if (!arm_compute::opencl_is_available())
+  {
+    return false;
+  }
+  arm_compute::CLScheduler::get().default_init();
+  // NOTE CLKernelLibraryEx must use the same context as CLScheduler
+  // It did not check whether another device is available.
+  arm_compute::CLKernelLibraryEx::get().init(
+      "./cl_kernels/", arm_compute::CLScheduler::get().context(), cl::Device::getDefault());
+
+  return true;
+}
+
+} // namespace acl_cl
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/acl_cl/Config.h b/runtime/neurun/backend/acl_cl/Config.h
new file mode 100644
index 000000000..a7ceaac26
--- /dev/null
+++ b/runtime/neurun/backend/acl_cl/Config.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ACL_CL_CONFIG_H__
+#define __NEURUN_BACKEND_ACL_CL_CONFIG_H__
+
+#include "CLTimer.h"
+#include <cpp14/memory.h>
+#include <backend/IConfig.h>
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_cl
+{
+
+class Config : public IConfig
+{
+public:
+  std::string id() override { return "acl_cl"; }
+  bool initialize() override;
+  bool SupportPermutation() override { return true; }
+  bool SupportSubTensorAlloc() override { return true; }
+  std::unique_ptr<util::ITimer> timer() override { return nnfw::cpp14::make_unique<CLTimer>(); }
+};
+
+} // namespace acl_cl
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ACL_CL_CONFIG_H__
diff --git a/runtime/neurun/backend/acl_cl/ConstantInitializer.cc b/runtime/neurun/backend/acl_cl/ConstantInitializer.cc
new file mode 100644
index 000000000..165b17cd1
--- /dev/null
+++ b/runtime/neurun/backend/acl_cl/ConstantInitializer.cc
@@ -0,0 +1,266 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ConstantInitializer.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_cl
+{
+
+ConstantInitializer::ConstantInitializer(const ir::Operands &operands,
+                                         const std::shared_ptr<TensorBuilder> &tensor_builder)
+    : _operands{operands}, _tensor_builder{tensor_builder}
+{
+  // DO NOTHING
+}
+
+void ConstantInitializer::visit(const ir::operation::BatchToSpaceND &node)
+{
+  const auto &block_size_index = node.getInputs().at(ir::operation::BatchToSpaceND::BLOCK_SIZE);
+  const auto &block_size_obj = _operands.at(block_size_index);
+
+  if (block_size_obj.isConstant())
+  {
+    _init_map[block_size_index] = [](const ir::Operand &model_obj, backend::operand::ITensor &obj) {
+      const auto &shape = model_obj.shape();
+      const auto base = reinterpret_cast<const int32_t *>(model_obj.data().base());
+      assert(model_obj.shape().rank() == 1);
+      obj.access([&](::neurun::backend::operand::ITensor &tensor) {
+        for (size_t i = 0; i < shape.num_elements(); ++i)
+        {
+          const int32_t value = base[shape.num_elements() - i - 1];
+          int32_t *into = reinterpret_cast<int32_t *>(tensor.buffer() +
+                                                      tensor.calcOffset({static_cast<int32_t>(i)}));
+          *into = value;
+        }
+      });
+    };
+  }
+}
+
+void ConstantInitializer::visit(const ir::operation::Conv2D &node)
+{
+  const auto &kernel_index = node.getInputs().at(ir::operation::Conv2D::KERNEL);
+  const auto &kernel_obj = _operands.at(kernel_index);
+  registerPermuteInitializer(kernel_index, kernel_obj);
+
+  const auto &bias_index = node.getInputs().at(ir::operation::Conv2D::BIAS);
+  const auto &bias_obj = _operands.at(bias_index);
+  registerCopyInitializer(bias_index, bias_obj);
+}
+
+void ConstantInitializer::visit(const ir::operation::DepthwiseConv2D &node)
+{
+  const auto &kernel_index = node.getInputs().at(ir::operation::DepthwiseConv2D::KERNEL);
+  const auto &kernel_obj = _operands.at(kernel_index);
+  registerPermuteInitializer(kernel_index, kernel_obj);
+
+  const auto &bias_index = node.getInputs().at(ir::operation::DepthwiseConv2D::BIAS);
+  const auto &bias_obj = _operands.at(bias_index);
+  registerCopyInitializer(bias_index, bias_obj);
+}
+
+void ConstantInitializer::visit(const ir::operation::EmbeddingLookup &node)
+{
+  const auto &lookups_index = node.getInputs().at(ir::operation::EmbeddingLookup::LOOKUPS);
+  const auto &lookups_obj = _operands.at(lookups_index);
+  registerCopyInitializer(lookups_index, lookups_obj);
+}
+
+void ConstantInitializer::visit(const ir::operation::FullyConnected &node)
+{
+  const auto &weight_index = node.getInputs().at(ir::operation::FullyConnected::WEIGHT);
+  const auto &weight_obj = _operands.at(weight_index);
+  registerCopyInitializer(weight_index, weight_obj);
+
+  const auto &bias_index = node.getInputs().at(ir::operation::FullyConnected::BIAS);
+  const auto &bias_obj = _operands.at(bias_index);
+  registerCopyInitializer(bias_index, bias_obj);
+}
+
+void ConstantInitializer::visit(const ir::operation::Gather &node)
+{
+  const auto &indices_index = node.getInputs().at(ir::operation::Gather::INDICES);
+  const auto &indices_obj = _operands.at(indices_index);
+  registerCopyInitializer(indices_index, indices_obj);
+}
+
+void ConstantInitializer::visit(const ir::operation::HashtableLookup &node)
+{
+  const auto &lookups_index = node.getInputs().at(ir::operation::HashtableLookup::LOOKUPS);
+  const auto &lookups_obj = _operands.at(lookups_index);
+  registerCopyInitializer(lookups_index, lookups_obj);
+
+  const auto &keys_index = node.getInputs().at(ir::operation::HashtableLookup::KEYS);
+  const auto &keys_obj = _operands.at(keys_index);
+  registerCopyInitializer(keys_index, keys_obj);
+}
+
+void ConstantInitializer::visit(const ir::operation::LSTM &node)
+{
+  const auto &input_to_input_weights_index =
+      node.getInputs().at(ir::operation::LSTM::INPUT_TO_INPUT_WEIGHTS);
+  const auto &input_to_input_weights_obj = _operands.at(input_to_input_weights_index);
+  registerCopyInitializer(input_to_input_weights_index, input_to_input_weights_obj);
+
+  const auto &input_to_forget_weights_index =
+      node.getInputs().at(ir::operation::LSTM::INPUT_TO_FORGET_WEIGHTS);
+  const auto &input_to_forget_weights_obj = _operands.at(input_to_forget_weights_index);
+  registerCopyInitializer(input_to_forget_weights_index, input_to_forget_weights_obj);
+
+  const auto &input_to_cell_weights_index =
+      node.getInputs().at(ir::operation::LSTM::INPUT_TO_CELL_WEIGHTS);
+  const auto &input_to_cell_weights_obj = _operands.at(input_to_cell_weights_index);
+  registerCopyInitializer(input_to_cell_weights_index, input_to_cell_weights_obj);
+
+  const auto &input_to_output_weights_index =
+      node.getInputs().at(ir::operation::LSTM::INPUT_TO_OUTPUT_WEIGHTS);
+  const auto &input_to_output_weights_obj = _operands.at(input_to_output_weights_index);
+  registerCopyInitializer(input_to_output_weights_index, input_to_output_weights_obj);
+
+  const auto &recurrent_to_input_weights_index =
+      node.getInputs().at(ir::operation::LSTM::RECURRENT_TO_INPUT_WEIGHTS);
+  const auto &recurrent_to_input_weights_obj = _operands.at(recurrent_to_input_weights_index);
+  registerCopyInitializer(recurrent_to_input_weights_index, recurrent_to_input_weights_obj);
+
+  const auto &recurrent_to_forget_weights_index =
+      node.getInputs().at(ir::operation::LSTM::RECURRENT_TO_FORGET_WEIGHTS);
+  const auto &recurrent_to_forget_weights_obj = _operands.at(recurrent_to_forget_weights_index);
+  registerCopyInitializer(recurrent_to_forget_weights_index, recurrent_to_forget_weights_obj);
+
+  const auto &recurrent_to_cell_weights_index =
+      node.getInputs().at(ir::operation::LSTM::RECURRENT_TO_CELL_WEIGHTS);
+  const auto &recurrent_to_cell_weights_obj = _operands.at(recurrent_to_cell_weights_index);
+  registerCopyInitializer(recurrent_to_cell_weights_index, recurrent_to_cell_weights_obj);
+
+  const auto &recurrent_to_output_weights_index =
+      node.getInputs().at(ir::operation::LSTM::RECURRENT_TO_OUTPUT_WEIGHTS);
+  const auto &recurrent_to_output_weights_obj = _operands.at(recurrent_to_output_weights_index);
+  registerCopyInitializer(recurrent_to_output_weights_index, recurrent_to_output_weights_obj);
+
+  const auto &cell_to_input_weights_index =
+      node.getInputs().at(ir::operation::LSTM::CELL_TO_INPUT_WEIGHTS);
+  const auto &cell_to_input_weights_obj = _operands.at(cell_to_input_weights_index);
+  registerCopyInitializer(cell_to_input_weights_index, cell_to_input_weights_obj);
+
+  const auto &cell_to_forget_weights_index =
+      node.getInputs().at(ir::operation::LSTM::CELL_TO_FORGET_WEIGHTS);
+  const auto &cell_to_forget_weights_obj = _operands.at(cell_to_forget_weights_index);
+  registerCopyInitializer(cell_to_forget_weights_index, cell_to_forget_weights_obj);
+
+  const auto &cell_to_output_weights_index =
+      node.getInputs().at(ir::operation::LSTM::CELL_TO_OUTPUT_WEIGHTS);
+  const auto &cell_to_output_weights_obj = _operands.at(cell_to_output_weights_index);
+  registerCopyInitializer(cell_to_output_weights_index, cell_to_output_weights_obj);
+
+  const auto &input_gate_bias_index = node.getInputs().at(ir::operation::LSTM::INPUT_GATE_BIAS);
+  const auto &input_gate_bias_obj = _operands.at(input_gate_bias_index);
+  registerCopyInitializer(input_gate_bias_index, input_gate_bias_obj);
+
+  const auto &forget_gate_bias_index = node.getInputs().at(ir::operation::LSTM::FORGET_GATE_BIAS);
+  const auto &forget_gate_bias_obj = _operands.at(forget_gate_bias_index);
+  registerCopyInitializer(forget_gate_bias_index, forget_gate_bias_obj);
+
+  const auto &output_gate_bias_index = node.getInputs().at(ir::operation::LSTM::OUTPUT_GATE_BIAS);
+  const auto &output_gate_bias_obj = _operands.at(output_gate_bias_index);
+  registerCopyInitializer(output_gate_bias_index, output_gate_bias_obj);
+
+  const auto &projection_weights_index =
+      node.getInputs().at(ir::operation::LSTM::PROJECTION_WEIGHTS);
+  const auto &projection_weights_obj = _operands.at(projection_weights_index);
+  registerCopyInitializer(projection_weights_index, projection_weights_obj);
+
+  const auto &projection_bias_index = node.getInputs().at(ir::operation::LSTM::PROJECTION_BIAS);
+  const auto &projection_bias_obj = _operands.at(projection_bias_index);
+  registerCopyInitializer(projection_bias_index, projection_bias_obj);
+}
+
+void ConstantInitializer::visit(const ir::operation::RNN &node)
+{
+  const auto &weights_index = node.getInputs().at(ir::operation::RNN::WEIGHTS);
+  const auto &weights_obj = _operands.at(weights_index);
+  registerCopyInitializer(weights_index, weights_obj);
+
+  const auto &recurrent_weights_index = node.getInputs().at(ir::operation::RNN::RECURRENT_WEIGHTS);
+  const auto &recurrent_weights_obj = _operands.at(recurrent_weights_index);
+  registerCopyInitializer(recurrent_weights_index, recurrent_weights_obj);
+
+  const auto &bias_index = node.getInputs().at(ir::operation::RNN::BIAS);
+  const auto &bias_obj = _operands.at(bias_index);
+  registerCopyInitializer(bias_index, bias_obj);
+}
+
+void ConstantInitializer::visit(const ir::operation::SpaceToBatchND &node)
+{
+  const auto &block_size_index = node.getInputs().at(ir::operation::SpaceToBatchND::BLOCK_SIZE);
+  const auto &block_size_obj = _operands.at(block_size_index);
+
+  if (block_size_obj.isConstant())
+  {
+    _init_map[block_size_index] = [](const ir::Operand &model_obj, backend::operand::ITensor &obj) {
+      const auto &shape = model_obj.shape();
+      const auto base = reinterpret_cast<const int32_t *>(model_obj.data().base());
+      assert(model_obj.shape().rank() == 1);
+      obj.access([&](::neurun::backend::operand::ITensor &tensor) {
+        for (size_t i = 0; i < shape.num_elements(); ++i)
+        {
+          const int32_t value = base[shape.num_elements() - i - 1];
+          int32_t *into = reinterpret_cast<int32_t *>(tensor.buffer() +
+                                                      tensor.calcOffset({static_cast<int32_t>(i)}));
+          *into = value;
+        }
+      });
+    };
+  }
+
+  const auto &paddings_index = node.getInputs().at(ir::operation::SpaceToBatchND::PADDINGS);
+  const auto &paddings_obj = _operands.at(paddings_index);
+  if (paddings_obj.isConstant())
+  {
+    _init_map[paddings_index] = [](const ir::Operand &model_obj, backend::operand::ITensor &obj) {
+      const auto &shape = model_obj.shape();
+      const auto base = reinterpret_cast<const int32_t *>(model_obj.data().base());
+      assert(model_obj.shape().rank() == 2);
+      assert(obj.dimension(0) == 2);
+      obj.access([&](::neurun::backend::operand::ITensor &tensor) {
+        for (auto i = 0; i < shape.dim(0); ++i)
+        {
+          for (auto j = 0; j < shape.dim(1); ++j)
+          {
+            const int32_t value = base[i * 2 + j];
+            int32_t *into = reinterpret_cast<int32_t *>(
+                tensor.buffer() + tensor.calcOffset({shape.dim(0) - i - 1, j}));
+            *into = value;
+          }
+        }
+      });
+    };
+  }
+}
+
+void ConstantInitializer::visit(const ir::operation::TransposeConv &node)
+{
+  const auto &kernel_index = node.getInputs().at(ir::operation::TransposeConv::KERNEL);
+  const auto &kernel_obj = _operands.at(kernel_index);
+  registerPermuteInitializer(kernel_index, kernel_obj);
+}
+
+} // namespace acl_cl
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/acl_cl/ConstantInitializer.h b/runtime/neurun/backend/acl_cl/ConstantInitializer.h
new file mode 100644
index 000000000..5965d2046
--- /dev/null
+++ b/runtime/neurun/backend/acl_cl/ConstantInitializer.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_COMPILER_ACL_CL_CONSTANT_INITIALIZER_H__
+#define __NEURUN_COMPILER_ACL_CL_CONSTANT_INITIALIZER_H__
+
+#include <backend/IConstantInitializer.h>
+#include <ir/Operands.h>
+#include "TensorBuilder.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_cl
+{
+
+class ConstantInitializer : public IConstantInitializer
+{
+public:
+  ConstantInitializer(const ir::Operands &operands,
+                      const std::shared_ptr<TensorBuilder> &tensor_builder);
+
+public:
+  void visit(const ir::operation::BatchToSpaceND &) override;
+  void visit(const ir::operation::Conv2D &) override;
+  void visit(const ir::operation::DepthwiseConv2D &) override;
+  void visit(const ir::operation::EmbeddingLookup &) override;
+  void visit(const ir::operation::FullyConnected &) override;
+  void visit(const ir::operation::Gather &) override;
+  void visit(const ir::operation::HashtableLookup &) override;
+  void visit(const ir::operation::LSTM &) override;
+  void visit(const ir::operation::RNN &) override;
+  void visit(const ir::operation::SpaceToBatchND &) override;
+  void visit(const ir::operation::TransposeConv &) override;
+
+private:
+  const ir::Operands &operands() const override { return _operands; }
+  std::shared_ptr<ITensorBuilder> tensor_builder() const override { return _tensor_builder; }
+
+private:
+  const ir::Operands &_operands;
+  std::shared_ptr<TensorBuilder> _tensor_builder;
+};
+
+} // namespace acl_cl
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_COMPILER_ACL_CL_CONSTANT_INITIALIZER_H__
diff --git a/runtime/neurun/backend/acl_cl/KernelGenerator.cc b/runtime/neurun/backend/acl_cl/KernelGenerator.cc
new file mode 100644
index 000000000..bffb60b61
--- /dev/null
+++ b/runtime/neurun/backend/acl_cl/KernelGenerator.cc
@@ -0,0 +1,2151 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "KernelGenerator.h"
+
+#include <arm_compute/runtime/CL/CLFunctions.h>   // Include all ARM Compute CL functions
+#include <arm_compute/runtime/CL/CLFunctionsEx.h> // Include all ARM Compute EX CL functions
+
+#include <AclFunction.h>
+#include <Convert.h>
+#include <Swizzle.h>
+
+#include "ir/Index.h"
+#include "ir/DataType.h"
+#include "ir/InternalType.h"
+#include "compiler/IExecutionBuilder.h"
+#include "exec/NopFunction.h"
+#include "util/logging.h"
+#include "util/Utils.h"
+#include "util/Padding.h"
+
+using ::neurun::compiler::IExecutionBuilder;
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_cl
+{
+
+using ::neurun::backend::acl_common::asAclFunction;
+
+//
+// ActivationBuilder
+//
+class ActivationBuilder
+{
+public:
+  explicit ActivationBuilder(IExecutionBuilder &builder) : _builder(builder)
+  {
+    // DO NOTHING
+  }
+
+private:
+  void appendReLU(::arm_compute::ICLTensor *ifm_alloc);
+  void appendReLU1(::arm_compute::ICLTensor *ifm_alloc);
+  void appendReLU6(::arm_compute::ICLTensor *ifm_alloc);
+
+public:
+  void append(ir::Activation code, ::arm_compute::ICLTensor *ifm_alloc);
+
+private:
+  IExecutionBuilder &_builder;
+};
+
+void ActivationBuilder::appendReLU(::arm_compute::ICLTensor *ifm_alloc)
+{
+  const ::arm_compute::ActivationLayerInfo act_info{
+      ::arm_compute::ActivationLayerInfo::ActivationFunction::RELU};
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLActivationLayer>();
+
+  fn->configure(ifm_alloc, nullptr, act_info);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _builder.append(std::move(acl_fn));
+}
+
+void ActivationBuilder::appendReLU1(::arm_compute::ICLTensor *ifm_alloc)
+{
+  const ::arm_compute::ActivationLayerInfo act_info{
+      ::arm_compute::ActivationLayerInfo::ActivationFunction::LU_BOUNDED_RELU, 1.0f, -1.0f};
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLActivationLayer>();
+
+  fn->configure(ifm_alloc, nullptr, act_info);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _builder.append(std::move(acl_fn));
+}
+
+void ActivationBuilder::appendReLU6(::arm_compute::ICLTensor *ifm_alloc)
+{
+  const ::arm_compute::ActivationLayerInfo act_info{
+      ::arm_compute::ActivationLayerInfo::ActivationFunction::LU_BOUNDED_RELU, 6.0f, 0.0f};
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLActivationLayer>();
+
+  fn->configure(ifm_alloc, nullptr, act_info);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _builder.append(std::move(acl_fn));
+}
+
+void ActivationBuilder::append(ir::Activation code, ::arm_compute::ICLTensor *ifm_alloc)
+{
+  switch (code)
+  {
+    case ir::Activation::NONE:
+    {
+      // DO NOTHING
+      break;
+    }
+    case ir::Activation::RELU:
+    {
+      appendReLU(ifm_alloc);
+      break;
+    }
+    case ir::Activation::RELU1:
+    {
+      appendReLU1(ifm_alloc);
+      break;
+    }
+    case ir::Activation::RELU6:
+    {
+      appendReLU6(ifm_alloc);
+      break;
+    }
+    default:
+    {
+      throw std::runtime_error("Not supported, yet");
+    }
+  }
+}
+
+//
+// KernelGenerator
+//
+KernelGenerator::KernelGenerator(const ir::Operands &ctx,
+                                 const std::shared_ptr<TensorBuilder> &tensor_builder)
+    : _ctx(ctx), _tensor_builder(tensor_builder), _current_subg_layout(ir::Layout::UNKNOWN)
+{
+  // DO NOTHING
+}
+
+void KernelGenerator::visit(const ir::OpSequence &op_seq)
+{
+  _current_subg_layout = op_seq.getLayout();
+  for (const auto &e : op_seq.operations())
+  {
+    const auto &node = *(e.node);
+    _tensor_builder->preVisit(node);
+    node.accept(*this);
+    _tensor_builder->postVisit(node);
+  }
+}
+
+void KernelGenerator::visit(const ir::operation::BatchToSpaceND &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::BatchToSpaceND::Input::INPUT)};
+  const auto block_size_index{
+      node.getInputs().at(ir::operation::BatchToSpaceND::Input::BLOCK_SIZE)};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+  auto block_size_alloc = _tensor_builder->at(block_size_index).get();
+
+  assert(_ctx.at(block_size_index).isConstant());
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLBatchToSpaceLayer>();
+
+  fn->configure(ifm_alloc->handle(), block_size_alloc->handle(), ofm_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Cast &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::Cast::Input::INPUT)};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+  const auto input_sub_type = _ctx.at(ifm_index).typeInfo().type() == ir::DataType::BOOL8
+                                  ? arm_compute::SubDataType::BOOL
+                                  : arm_compute::SubDataType::NONE;
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLCast>();
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle(), input_sub_type);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Conv2D &node)
+{
+  using ir::operation::Conv2D;
+
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(Conv2D::Input::INPUT)};
+  const auto ker_index{node.getInputs().at(Conv2D::Input::KERNEL)};
+  const auto bias_index{node.getInputs().at(Conv2D::Input::BIAS)};
+
+  const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature(_current_subg_layout);
+  const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature(_current_subg_layout);
+  // Kernel format is [depth_out, kernel_height, kernel_width, depth_in].
+  const auto &ker_shape = _ctx.at(ker_index).shape();
+  const auto ker_height = ker_shape.dim(1);
+  const auto ker_width = ker_shape.dim(2);
+
+  const auto stride = node.param().stride;
+  const auto padding = neurun::util::calculatePadding(node.param().padding, ifm_shape, ofm_shape,
+                                                      stride, ker_width, ker_height);
+  const auto activation = node.param().activation;
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+  auto ker_alloc = _tensor_builder->at(ker_index).get();
+  auto bias_alloc = _tensor_builder->at(bias_index).get();
+
+  const auto conv_info = acl_common::asPadStrideInfo(padding, stride);
+  const auto act_info = acl_common::asActivationLayerInfo(activation);
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLConvolutionLayer>(
+      _tensor_builder->acl_tensor_manager()->internal_buffer_manager());
+
+  fn->configure(ifm_alloc->handle(), ker_alloc->handle(), bias_alloc->handle(), ofm_alloc->handle(),
+                conv_info, ::arm_compute::WeightsInfo(), ::arm_compute::Size2D(1U, 1U), act_info);
+
+  _execution_builder->append(asAclFunction(std::move(fn)));
+}
+
+void KernelGenerator::visit(const ir::operation::DepthwiseConv2D &node)
+{
+  using ir::operation::DepthwiseConv2D;
+
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(DepthwiseConv2D::Input::INPUT)};
+  const auto ker_index{node.getInputs().at(DepthwiseConv2D::Input::KERNEL)};
+  const auto bias_index{node.getInputs().at(DepthwiseConv2D::Input::BIAS)};
+
+  const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature(_current_subg_layout);
+  const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature(_current_subg_layout);
+  // Kernel format is [1, kernel_height, kernel_width, depth_out].
+  const auto &ker_shape = _ctx.at(ker_index).shape();
+  const auto ker_height = ker_shape.dim(1);
+  const auto ker_width = ker_shape.dim(2);
+
+  const auto stride = node.param().stride;
+  const auto padding = neurun::util::calculatePadding(node.param().padding, ifm_shape, ofm_shape,
+                                                      stride, ker_width, ker_height);
+  const auto multiplier = node.param().multiplier;
+  const auto activation = node.param().activation;
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+  auto ker_alloc = _tensor_builder->at(ker_index).get();
+  auto bias_alloc = _tensor_builder->at(bias_index).get();
+
+  const auto conv_info = acl_common::asPadStrideInfo(padding, stride);
+  const auto act_info = acl_common::asActivationLayerInfo(activation);
+
+  if (ker_height == 3 && ker_width == 3)
+  {
+    auto fn = nnfw::cpp14::make_unique<::arm_compute::CLDepthwiseConvolutionLayer3x3>(
+        _tensor_builder->acl_tensor_manager()->internal_buffer_manager());
+
+    fn->configure(ifm_alloc->handle(), ker_alloc->handle(), bias_alloc->handle(),
+                  ofm_alloc->handle(), conv_info, multiplier, act_info);
+
+    _execution_builder->append(asAclFunction(std::move(fn)));
+  }
+  else
+  {
+    auto fn = nnfw::cpp14::make_unique<::arm_compute::CLDepthwiseConvolutionLayer>();
+
+    fn->configure(ifm_alloc->handle(), ker_alloc->handle(), bias_alloc->handle(),
+                  ofm_alloc->handle(), conv_info, multiplier, act_info);
+
+    _execution_builder->append(asAclFunction(std::move(fn)));
+  }
+}
+
+void KernelGenerator::visit(const ir::operation::MaxPool2D &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::MaxPool2D::Input::INPUT)};
+
+  const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature(_current_subg_layout);
+  const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature(_current_subg_layout);
+
+  const auto kh = node.param().kh;
+  const auto kw = node.param().kw;
+  const auto stride = node.param().stride;
+  const auto padding =
+      neurun::util::calculatePadding(node.param().padding, ifm_shape, ofm_shape, stride, kw, kh);
+  const auto activation = node.param().activation;
+
+  VERBOSE(MaxPool2D) << "IFM_H: " << ifm_shape.H << std::endl;
+  VERBOSE(MaxPool2D) << "IFM_W: " << ifm_shape.W << std::endl;
+  VERBOSE(MaxPool2D) << "OFM_H: " << ofm_shape.H << std::endl;
+  VERBOSE(MaxPool2D) << "OFM_W: " << ofm_shape.W << std::endl;
+  VERBOSE(MaxPool2D) << "KER_H: " << kh << std::endl;
+  VERBOSE(MaxPool2D) << "KER_W: " << kw << std::endl;
+  VERBOSE(MaxPool2D) << "STRIDE_H: " << stride.vertical << std::endl;
+  VERBOSE(MaxPool2D) << "STRIDE_W: " << stride.horizontal << std::endl;
+  VERBOSE(MaxPool2D) << "PAD(T): " << padding.top << std::endl;
+  VERBOSE(MaxPool2D) << "PAD(B): " << padding.bottom << std::endl;
+  VERBOSE(MaxPool2D) << "PAD(L): " << padding.left << std::endl;
+  VERBOSE(MaxPool2D) << "PAD(R): " << padding.right << std::endl;
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+
+  ::arm_compute::PoolingLayerInfo info{::arm_compute::PoolingType::MAX,
+                                       ::arm_compute::Size2D{kw, kh},
+                                       acl_common::asPadStrideInfo(padding, stride)};
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLPoolingLayer>();
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle(), info);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append((std::move(acl_fn)));
+
+  ActivationBuilder{*_execution_builder}.append(activation, ofm_alloc->handle());
+}
+
+void KernelGenerator::visit(const ir::operation::AvgPool2D &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::AvgPool2D::Input::INPUT)};
+
+  const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature(_current_subg_layout);
+  const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature(_current_subg_layout);
+
+  const auto kh = node.param().kh;
+  const auto kw = node.param().kw;
+  const auto stride = node.param().stride;
+  const auto padding =
+      neurun::util::calculatePadding(node.param().padding, ifm_shape, ofm_shape, stride, kw, kh);
+  const auto activation = node.param().activation;
+
+  VERBOSE(AvgPool2D) << "IFM_H: " << ifm_shape.H << std::endl;
+  VERBOSE(AvgPool2D) << "IFM_W: " << ifm_shape.W << std::endl;
+  VERBOSE(AvgPool2D) << "OFM_H: " << ofm_shape.H << std::endl;
+  VERBOSE(AvgPool2D) << "OFM_W: " << ofm_shape.W << std::endl;
+  VERBOSE(AvgPool2D) << "KER_H: " << kh << std::endl;
+  VERBOSE(AvgPool2D) << "KER_W: " << kw << std::endl;
+  VERBOSE(AvgPool2D) << "STRIDE_H: " << stride.vertical << std::endl;
+  VERBOSE(AvgPool2D) << "STRIDE_W: " << stride.horizontal << std::endl;
+  VERBOSE(AvgPool2D) << "PAD(T): " << padding.top << std::endl;
+  VERBOSE(AvgPool2D) << "PAD(B): " << padding.bottom << std::endl;
+  VERBOSE(AvgPool2D) << "PAD(L): " << padding.left << std::endl;
+  VERBOSE(AvgPool2D) << "PAD(R): " << padding.right << std::endl;
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+
+  ::arm_compute::PoolingLayerInfo info{
+      ::arm_compute::PoolingType::AVG, ::arm_compute::Size2D{kw, kh},
+      acl_common::asPadStrideInfo(padding, stride), true /* exclude_padding */};
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLPoolingLayer>();
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle(), info);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append((std::move(acl_fn)));
+
+  ActivationBuilder{*_execution_builder}.append(activation, ofm_alloc->handle());
+}
+
+void KernelGenerator::visit(const ir::operation::Concat &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+
+  std::vector<ir::OperandIndex> input_indexes;
+
+  for (const auto &input : node.getInputs())
+    input_indexes.emplace_back(input);
+
+  const auto axis = node.param().axis;
+
+  // If tensor allocator allocate as subtensor
+  bool canEliminate = true;
+  for (auto &ifm_ind : input_indexes)
+  {
+    if (!_tensor_builder->isSubTensorOf(ofm_index, ifm_ind))
+    {
+      canEliminate = false;
+      break;
+    }
+  }
+  if (canEliminate)
+  {
+    // If concat eliminated, return a NOP IFunction
+    _execution_builder->append(nnfw::cpp14::make_unique<exec::NopFunction>());
+    return;
+  }
+
+  auto output_alloc = _tensor_builder->at(ofm_index).get();
+  std::vector<::arm_compute::ICLTensor *> input_tensors;
+  for (auto &ifm_ind : input_indexes)
+    input_tensors.emplace_back(_tensor_builder->at(ifm_ind)->handle());
+
+  std::unique_ptr<::arm_compute::IFunction> fn;
+  if (input_indexes.size() < 2)
+  {
+    auto l = nnfw::cpp14::make_unique<::arm_compute::CLCopy>();
+    l->configure(input_tensors.at(0), output_alloc->handle());
+    fn = std::move(l);
+  }
+  else
+  {
+    auto l = nnfw::cpp14::make_unique<::arm_compute::CLConcatenateLayer>();
+    const auto rank = node.param().rank;
+    const auto frontend_layout = _current_subg_layout;
+    const auto backend_layout = output_alloc->layout();
+    const auto fixed_axis =
+        acl_common::ToARMComputeAxis(rank, axis, frontend_layout, backend_layout).value();
+    l->configure(input_tensors, output_alloc->handle(), fixed_axis);
+    fn = std::move(l);
+  }
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::FullyConnected &node)
+{
+  using ir::operation::FullyConnected;
+
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(FullyConnected::Input::INPUT)};
+  const auto weight_index{node.getInputs().at(FullyConnected::Input::WEIGHT)};
+  const auto bias_index{node.getInputs().at(FullyConnected::Input::BIAS)};
+
+  const auto input_rank = _ctx.at(input_index).shape().rank();
+  // TODO Currently we are not handling where the case is that the input's rank is 3.
+  // The handling should be added in the future.
+  assert(input_rank != 3);
+
+  const auto output_size =
+      _ctx.at(output_index).shape().dim(_ctx.at(output_index).shape().rank() - 1);
+  UNUSED_RELEASE(output_size);
+  assert(_ctx.at(bias_index).shape().dim(0) == output_size);
+  assert(_ctx.at(weight_index).shape().dim(0) == output_size);
+  const auto batch_size =
+      _ctx.at(output_index).shape().dim(_ctx.at(output_index).shape().rank() - 2);
+  const auto input_size =
+      _ctx.at(weight_index).shape().dim(_ctx.at(weight_index).shape().rank() - 1);
+
+  // Check for reshaping input's shape into rank-2
+  bool needs_reshape = false;
+  ir::Shape reshape(2);
+  if (input_rank == 4)
+  {
+    const auto feature_size = _ctx.at(input_index).shape().num_elements();
+
+    UNUSED_RELEASE(feature_size);
+    assert(batch_size >= 0 && input_size >= 0);
+    assert(feature_size == static_cast<uint64_t>(batch_size) * static_cast<uint64_t>(input_size));
+
+    // for reshaping
+    needs_reshape = true;
+    reshape.dim(0) = batch_size; /* H */
+    reshape.dim(1) = input_size; /* W */
+  }
+
+  const auto activation = node.param().activation;
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  const auto input_alloc = _tensor_builder->at(input_index).get();
+  const auto weight_alloc = _tensor_builder->at(weight_index).get();
+  const auto bias_alloc = _tensor_builder->at(bias_index).get();
+  const auto frontend_layout = _current_subg_layout;
+  const auto acl_layout = output_alloc->handle()->info()->data_layout();
+
+  auto fn = nnfw::cpp14::make_unique<arm_compute::CLFullyConnectedReshapingLayer>(
+      _tensor_builder->acl_tensor_manager()->internal_buffer_manager());
+
+  fn->configure(
+      input_alloc->handle(), weight_alloc->handle(), bias_alloc->handle(), output_alloc->handle(),
+      needs_reshape,
+      ::neurun::backend::acl_common::asTensorShape(
+          reshape, frontend_layout, ::neurun::backend::acl_common::asRuntimeLayout(acl_layout)));
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+
+  ActivationBuilder{*_execution_builder}.append(activation, output_alloc->handle());
+}
+
+void KernelGenerator::visit(const ir::operation::Mul &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto lhs_index{node.getInputs().at(ir::operation::Mul::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::Mul::Input::RHS)};
+
+  const auto activation = node.param().activation;
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto lhs_alloc = _tensor_builder->at(lhs_index).get();
+  auto rhs_alloc = _tensor_builder->at(rhs_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLPixelWiseMultiplication>();
+
+  fn->configure(lhs_alloc->handle(), rhs_alloc->handle(), ofm_alloc->handle(), 1.0, // scale
+                arm_compute::ConvertPolicy::SATURATE, arm_compute::RoundingPolicy::TO_NEAREST_EVEN);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+
+  ActivationBuilder{*_execution_builder}.append(activation, ofm_alloc->handle());
+}
+
+void KernelGenerator::visit(const ir::operation::ReduceSum &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::ReduceSum::Input::INPUT)};
+  const auto &axes{node.param().axes};
+  const auto keep_dims{node.param().keep_dims};
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input_alloc = _tensor_builder->at(input_index).get();
+  const auto frontend_layout = _current_subg_layout;
+  const auto backend_layout = input_alloc->layout();
+
+  // Convert to ACL axes taking into account negative values and possible duplicates.
+  std::set<std::uint32_t> acl_axes;
+  const int input_rank = node.param().rank;
+  for (int axis : axes)
+  {
+    if (axis < 0)
+      axis += input_rank;
+    acl_axes.insert(
+        acl_common::ToARMComputeAxis(input_rank, axis, frontend_layout, backend_layout).value());
+  }
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLReduceOperation>(
+      _tensor_builder->acl_tensor_manager()->internal_buffer_manager());
+
+  fn->configure(input_alloc->handle(), output_alloc->handle(), acl_axes, keep_dims,
+                ::arm_compute::ReduceOperation::SUM);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Reshape &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::Reshape::Input::INPUT)};
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input_alloc = _tensor_builder->at(input_index).get();
+
+  // NOTE This operation must not be changed the layout from frontend to backend
+  //      So, PermutationOperationPass makes layouts of frontend and backend the same.
+  const auto frontend_layout = _current_subg_layout;
+  const auto backend_layout = output_alloc->layout();
+  assert((_ctx.at(input_index).shape().rank() < 4 && _ctx.at(output_index).shape().rank() < 4) ||
+         frontend_layout == backend_layout);
+  UNUSED_RELEASE(frontend_layout);
+  UNUSED_RELEASE(backend_layout);
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLReshapeLayer>();
+
+  fn->configure(input_alloc->handle(), output_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Squeeze &node)
+{
+  // Squeeze is identical to reshape except that it has an optional dimensions input.
+  // In addition, optional dims_index is ignored since output tensor already has squeezed shape
+  // by freezer and toco
+  // TODO Support multi-layout for frontend and backend
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::Squeeze::Input::INPUT)};
+  const auto dims{node.param().dims};
+  const auto ndim{node.param().ndim};
+  (void)dims;
+  (void)ndim;
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input_alloc = _tensor_builder->at(input_index).get();
+  auto fn = nnfw::cpp14::make_unique<arm_compute::CLReshapeLayer>();
+  fn->configure(input_alloc->handle(), output_alloc->handle());
+  auto acl_fn = asAclFunction(std::move(fn));
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Tanh &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::Tanh::Input::INPUT)};
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input_alloc = _tensor_builder->at(input_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<arm_compute::CLActivationLayer>();
+
+  const ::arm_compute::ActivationLayerInfo act_info{
+      ::arm_compute::ActivationLayerInfo::ActivationFunction::TANH, 1.0f, 1.0f};
+
+  fn->configure(input_alloc->handle(), output_alloc->handle(), act_info);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Softmax &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::Softmax::Input::INPUT)};
+
+  const auto beta = node.param().beta;
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input_alloc = _tensor_builder->at(input_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLSoftmaxLayer>(
+      _tensor_builder->acl_tensor_manager()->internal_buffer_manager());
+
+  fn->configure(input_alloc->handle(), output_alloc->handle(), beta);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Slice &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::Slice::Input::INPUT)};
+  const auto begins_index{node.getInputs().at(ir::operation::Slice::Input::BEGINS)};
+  const auto sizes_index{node.getInputs().at(ir::operation::Slice::Input::SIZES)};
+
+  auto outputData_alloc = _tensor_builder->at(output_index).get();
+  auto inputData_alloc = _tensor_builder->at(input_index).get();
+  const auto frontend_layout = _current_subg_layout;
+  const auto backend_layout = inputData_alloc->layout();
+
+  // Set initializers for indices data such as order of inputData
+  int input_rank = node.param().rank;
+  std::vector<int32_t> starts;
+  std::vector<int32_t> ends;
+  starts.resize(input_rank, 0);
+  ends.resize(input_rank, 0);
+  {
+    auto beginData_base = _ctx.at(begins_index).data().base();
+    auto sizeData_base = _ctx.at(sizes_index).data().base();
+    const int beginData_size = _ctx.at(begins_index).shape().num_elements();
+    const int sizeData_size = _ctx.at(sizes_index).shape().num_elements();
+
+    using ir::DataType;
+
+    UNUSED_RELEASE(beginData_size);
+    UNUSED_RELEASE(sizeData_size);
+
+    assert(_ctx.at(begins_index).typeInfo().type() == DataType::INT32);
+    assert(_ctx.at(sizes_index).typeInfo().type() == DataType::INT32);
+    assert(beginData_size == input_rank);
+    assert(sizeData_size == input_rank);
+
+    assert(beginData_base != nullptr);
+    for (int n = 0; n < input_rank; ++n)
+    {
+      auto axis = ::neurun::backend::acl_common::ToARMComputeAxis(input_rank, n, frontend_layout,
+                                                                  backend_layout)
+                      .value();
+
+      int32_t begin_value = *(reinterpret_cast<const int32_t *>(beginData_base) + n);
+      starts[axis] = begin_value;
+
+      int32_t size_value = *(reinterpret_cast<const int32_t *>(sizeData_base) + n);
+      ends[axis] = begin_value + size_value;
+    }
+  }
+
+  ::arm_compute::Coordinates starts_set;
+  ::arm_compute::Coordinates ends_set;
+
+  for (size_t i = 0; i < starts.size(); ++i)
+  {
+    starts_set.set(i, starts[i]);
+    ends_set.set(i, ends[i]);
+  }
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLSlice>();
+
+  fn->configure(inputData_alloc->handle(), outputData_alloc->handle(), starts_set, ends_set);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::StridedSlice &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::StridedSlice::Input::INPUT)};
+  const auto starts_index{node.getInputs().at(ir::operation::StridedSlice::Input::STARTS)};
+  const auto ends_index{node.getInputs().at(ir::operation::StridedSlice::Input::ENDS)};
+  const auto strides_index{node.getInputs().at(ir::operation::StridedSlice::Input::STRIDES)};
+
+  auto outputData_alloc = _tensor_builder->at(output_index).get();
+  auto inputData_alloc = _tensor_builder->at(input_index).get();
+  const auto frontend_layout = _current_subg_layout;
+  const auto backend_layout = inputData_alloc->layout();
+
+  // Set initializers for indices data such as order of inputData
+  int input_rank = node.param().rank;
+  std::vector<int32_t> starts;
+  std::vector<int32_t> ends;
+  std::vector<int32_t> strides;
+  starts.resize(input_rank, 0);
+  ends.resize(input_rank, 0);
+  strides.resize(input_rank, 0);
+  {
+    auto startData_base = _ctx.at(starts_index).data().base();
+    auto endData_base = _ctx.at(ends_index).data().base();
+    auto stridesData_base = _ctx.at(strides_index).data().base();
+    const int startData_size = _ctx.at(starts_index).shape().num_elements();
+    const int endData_size = _ctx.at(ends_index).shape().num_elements();
+    const int stridesData_size = _ctx.at(strides_index).shape().num_elements();
+
+    using ir::DataType;
+
+    UNUSED_RELEASE(startData_size);
+    UNUSED_RELEASE(endData_size);
+    UNUSED_RELEASE(stridesData_size);
+
+    assert(_ctx.at(starts_index).typeInfo().type() == DataType::INT32);
+    assert(_ctx.at(ends_index).typeInfo().type() == DataType::INT32);
+    assert(_ctx.at(strides_index).typeInfo().type() == DataType::INT32);
+    assert(startData_size == input_rank);
+    assert(endData_size == input_rank);
+    assert(stridesData_size == input_rank);
+
+    assert(startData_base != nullptr);
+    for (int n = 0; n < input_rank; ++n)
+    {
+      auto axis = ::neurun::backend::acl_common::ToARMComputeAxis(input_rank, n, frontend_layout,
+                                                                  backend_layout)
+                      .value();
+
+      int32_t start_value = *(reinterpret_cast<const int32_t *>(startData_base) + n);
+      starts[axis] = start_value;
+
+      int32_t end_value = *(reinterpret_cast<const int32_t *>(endData_base) + n);
+      ends[axis] = end_value;
+
+      int32_t strides_value = *(reinterpret_cast<const int32_t *>(stridesData_base) + n);
+      strides[axis] = strides_value;
+    }
+  }
+
+  // Set mask bits such as order of inputData
+  const auto begin_mask = acl_common::ReorderBits<int32_t>(node.param().begin_mask, input_rank,
+                                                           frontend_layout, backend_layout);
+  const auto end_mask = acl_common::ReorderBits<int32_t>(node.param().end_mask, input_rank,
+                                                         frontend_layout, backend_layout);
+  const auto shrink_axis_mask = acl_common::ReorderBits<int32_t>(
+      node.param().shrink_axis_mask, input_rank, frontend_layout, backend_layout);
+
+  ::arm_compute::Coordinates starts_set;
+  ::arm_compute::Coordinates ends_set;
+  ::arm_compute::BiStrides strides_set;
+
+  for (size_t i = 0; i < starts.size(); ++i)
+  {
+    starts_set.set(i, starts[i]);
+    ends_set.set(i, ends[i]);
+    strides_set.set(i, strides[i]);
+  }
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLStridedSlice>();
+
+  fn->configure(inputData_alloc->handle(), outputData_alloc->handle(), starts_set, ends_set,
+                strides_set, begin_mask, end_mask, shrink_axis_mask);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Transpose &node)
+{
+  const auto ofm_idx{node.getOutputs().at(0)};
+  const auto ifm_idx{node.getInputs().at(ir::operation::Transpose::Input::INPUT)};
+  const auto &perm{node.param().perm};
+
+  const auto rank = node.param().rank;
+
+  auto ofm_alloc = _tensor_builder->at(ofm_idx).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_idx).get();
+  const auto frontend_layout = _current_subg_layout;
+  const auto backend_layout = ifm_alloc->layout();
+
+  std::vector<std::int32_t> pv(perm.cbegin(), perm.cend());
+  // Reversed
+  auto backend_pv = ::neurun::backend::acl_common::getARMComputePermutationVector(
+      rank, pv, frontend_layout, backend_layout);
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLPermute>();
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle(), backend_pv);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Add &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto lhs_index{node.getInputs().at(ir::operation::Add::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::Add::Input::RHS)};
+
+  const auto activation = node.param().activation;
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto lhs_alloc = _tensor_builder->at(lhs_index).get();
+  auto rhs_alloc = _tensor_builder->at(rhs_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLArithmeticAddition>();
+
+  fn->configure(lhs_alloc->handle(), rhs_alloc->handle(), ofm_alloc->handle(),
+                arm_compute::ConvertPolicy::SATURATE);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+
+  ActivationBuilder{*_execution_builder}.append(activation, ofm_alloc->handle());
+}
+
+void KernelGenerator::visit(const ir::operation::Sub &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto lhs_index{node.getInputs().at(ir::operation::Sub::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::Sub::Input::RHS)};
+
+  const auto activation = node.param().activation;
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto lhs_alloc = _tensor_builder->at(lhs_index).get();
+  auto rhs_alloc = _tensor_builder->at(rhs_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLArithmeticSubtraction>();
+
+  fn->configure(lhs_alloc->handle(), rhs_alloc->handle(), ofm_alloc->handle(),
+                arm_compute::ConvertPolicy::SATURATE);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+
+  ActivationBuilder{*_execution_builder}.append(activation, ofm_alloc->handle());
+}
+
+void KernelGenerator::visit(const ir::operation::Div &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto lhs_index{node.getInputs().at(ir::operation::Div::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::Div::Input::RHS)};
+
+  const auto activation = node.param().activation;
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto lhs_alloc = _tensor_builder->at(lhs_index).get();
+  auto rhs_alloc = _tensor_builder->at(rhs_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLArithmeticDivision>();
+
+  fn->configure(lhs_alloc->handle(), rhs_alloc->handle(), ofm_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+
+  ActivationBuilder{*_execution_builder}.append(activation, ofm_alloc->handle());
+}
+
+void KernelGenerator::visit(const ir::operation::Exp &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::Exp::Input::INPUT)};
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input_alloc = _tensor_builder->at(input_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLExpLayer>();
+
+  fn->configure(input_alloc->handle(), output_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::InstanceNorm &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::InstanceNorm::Input::INPUT)};
+  const auto gamma_index{node.getInputs().at(ir::operation::InstanceNorm::Input::GAMMA)};
+  const auto beta_index{node.getInputs().at(ir::operation::InstanceNorm::Input::BETA)};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+  auto gamma_alloc = _tensor_builder->at(gamma_index).get();
+  auto beta_alloc = _tensor_builder->at(beta_index).get();
+  auto epsilon = node.param().epsilon;
+  auto activation = node.param().activation;
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLInstanceNormalizationLayerEx>();
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle(), gamma_alloc->handle(),
+                beta_alloc->handle(), epsilon);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+
+  ActivationBuilder{*_execution_builder}.append(activation, ofm_alloc->handle());
+}
+
+void KernelGenerator::visit(const ir::operation::Logistic &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::Logistic::Input::INPUT)};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+
+  const ::arm_compute::ActivationLayerInfo act_info{
+      ::arm_compute::ActivationLayerInfo::ActivationFunction::LOGISTIC};
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLActivationLayer>();
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle(), act_info);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::LogicalAnd &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input0_index{node.getInputs().at(ir::operation::LogicalAnd::Input::INPUT0)};
+  const auto input1_index{node.getInputs().at(ir::operation::LogicalAnd::Input::INPUT1)};
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input0_alloc = _tensor_builder->at(input0_index).get();
+  auto input1_alloc = _tensor_builder->at(input1_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLBinaryLogicalOp>();
+
+  fn->configure(input0_alloc->handle(), input1_alloc->handle(), output_alloc->handle(),
+                ::arm_compute::BinaryLogicalOperation::AND);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::LSTM &node)
+{
+  // TODO Support dynamic rnn
+  // TODO Fix subtle error in the case of non-CIFG, non-peephole and No Projection.
+  const auto scratch_buffer_index{
+      node.getOutputs().at(ir::operation::LSTM::Output::SCRATCH_BUFFER)};
+  const auto output_state_out_index{
+      node.getOutputs().at(ir::operation::LSTM::Output::OUTPUT_STATE_OUT)};
+  const auto cell_state_out_index{
+      node.getOutputs().at(ir::operation::LSTM::Output::CELL_STATE_OUT)};
+  const auto output_index{node.getOutputs().at(ir::operation::LSTM::Output::OUTPUT)};
+
+  const auto input_index{node.getInputs().at(ir::operation::LSTM::Input::INPUT)};
+  const auto input_to_input_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::INPUT_TO_INPUT_WEIGHTS)}; // optional
+  const auto input_to_forget_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::INPUT_TO_FORGET_WEIGHTS)};
+  const auto input_to_cell_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::INPUT_TO_CELL_WEIGHTS)};
+  const auto input_to_output_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::INPUT_TO_OUTPUT_WEIGHTS)};
+  const auto recurrent_to_input_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::RECURRENT_TO_INPUT_WEIGHTS)}; // optional
+  const auto recurrent_to_forget_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::RECURRENT_TO_FORGET_WEIGHTS)};
+  const auto recurrent_to_cell_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::RECURRENT_TO_CELL_WEIGHTS)};
+  const auto recurrent_to_output_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::RECURRENT_TO_OUTPUT_WEIGHTS)};
+  const auto cell_to_input_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::CELL_TO_INPUT_WEIGHTS)}; // optional
+  const auto cell_to_forget_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::CELL_TO_FORGET_WEIGHTS)}; // optional
+  const auto cell_to_output_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::CELL_TO_OUTPUT_WEIGHTS)}; // optional
+  const auto input_gate_bias_index{
+      node.getInputs().at(ir::operation::LSTM::Input::INPUT_GATE_BIAS)};
+  const auto forget_gate_bias_index{
+      node.getInputs().at(ir::operation::LSTM::Input::FORGET_GATE_BIAS)};
+  const auto cell_bias_index{node.getInputs().at(ir::operation::LSTM::Input::CELL_BIAS)};
+  const auto output_gate_bias_index{
+      node.getInputs().at(ir::operation::LSTM::Input::OUTPUT_GATE_BIAS)};
+  const auto projection_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::PROJECTION_WEIGHTS)}; // optional
+  const auto projection_bias_index{
+      node.getInputs().at(ir::operation::LSTM::Input::PROJECTION_BIAS)}; // optional
+  const auto output_state_in_index{
+      node.getInputs().at(ir::operation::LSTM::Input::OUTPUT_STATE_IN)};
+  const auto cell_state_in_index{node.getInputs().at(ir::operation::LSTM::Input::CELL_STATE_IN)};
+  const auto cell_threshold = node.param().cell_threshold;
+  const auto projection_threshold = node.param().projection_threshold;
+
+  bool has_input_to_input_weights = _ctx.at(input_to_input_weights_index).shape().dim(0) != 0 &&
+                                    _ctx.at(input_to_input_weights_index).shape().dim(1) != 0;
+  bool has_recurrent_to_input_weights =
+      _ctx.at(recurrent_to_input_weights_index).shape().dim(0) != 0 &&
+      _ctx.at(recurrent_to_input_weights_index).shape().dim(1) != 0;
+  bool has_cell_to_forget_weights = _ctx.at(cell_to_forget_weights_index).shape().dim(0) != 0;
+  bool has_cell_to_output_weights = _ctx.at(cell_to_output_weights_index).shape().dim(0) != 0;
+  bool has_projection_weights = _ctx.at(projection_weights_index).shape().dim(0) != 0 &&
+                                _ctx.at(projection_weights_index).shape().dim(1) != 0;
+  bool has_projection_bias = _ctx.at(projection_bias_index).shape().dim(0);
+
+  // NOTE The input_to_input_weights and the recurrent_to_input_weights do not exist in CIFG.
+  // true: no CIFG
+  // false: CIFG
+  // NOTE The cell_to_input_weights does not exist in non-peephole although regular LSTM(non-CIFG).
+  bool has_cifg_param = has_input_to_input_weights && has_recurrent_to_input_weights;
+
+  // NOTE The cell_to_forget_weights and the cell_to_output_weights exist in peephole.
+  // But the cell_to_input_weights does not exist in regular CIFG although peephole.
+  // true: peephole
+  // false: no peephole
+  bool has_peephole_param = has_cell_to_forget_weights && has_cell_to_output_weights;
+
+  // NOTE Although the projection weights has data the projection bias may not have data.
+  bool has_projection_param = has_projection_weights;
+
+  const auto activation = node.param().activation;
+  const auto cell_clip = cell_threshold;
+  const auto projection_clip = projection_threshold;
+  assert(cell_clip >= 0.f && projection_clip >= 0.f);
+
+  auto scratch_buffer_alloc = _tensor_builder->at(scratch_buffer_index).get();
+  auto output_state_out_alloc = _tensor_builder->at(output_state_out_index).get();
+  auto cell_state_out_alloc = _tensor_builder->at(cell_state_out_index).get();
+  auto output_alloc = _tensor_builder->at(output_index).get();
+
+  auto input_alloc = _tensor_builder->at(input_index).get();
+
+  auto input_to_forget_weights_alloc = _tensor_builder->at(input_to_forget_weights_index).get();
+  auto input_to_cell_weights_alloc = _tensor_builder->at(input_to_cell_weights_index).get();
+  auto input_to_output_weights_alloc = _tensor_builder->at(input_to_output_weights_index).get();
+  auto recurrent_to_forget_weights_alloc =
+      _tensor_builder->at(recurrent_to_forget_weights_index).get();
+  auto recurrent_to_cell_weights_alloc = _tensor_builder->at(recurrent_to_cell_weights_index).get();
+  auto recurrent_to_output_weights_alloc =
+      _tensor_builder->at(recurrent_to_output_weights_index).get();
+
+  auto forget_gate_bias_alloc = _tensor_builder->at(forget_gate_bias_index).get();
+  auto cell_bias_alloc = _tensor_builder->at(cell_bias_index).get();
+  auto output_gate_bias_alloc = _tensor_builder->at(output_gate_bias_index).get();
+  auto output_state_in_alloc = _tensor_builder->at(output_state_in_index).get();
+  auto cell_state_in_alloc = _tensor_builder->at(cell_state_in_index).get();
+
+  auto act_info = ::neurun::backend::acl_common::asActivationLayerInfo(activation);
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLLSTMLayer>();
+
+  ::arm_compute::LSTMParams<::arm_compute::ICLTensor> lstm_params{};
+  if (has_cifg_param)
+  {
+    auto input_to_input_weights_alloc =
+        _tensor_builder->at(input_to_input_weights_index).get(); // optional
+    auto recurrent_to_input_weights_alloc =
+        _tensor_builder->at(recurrent_to_input_weights_index).get(); // optional
+    auto cell_to_input_weights_handle =
+        has_peephole_param ? _tensor_builder->at(cell_to_input_weights_index).get()->handle()
+                           : nullptr; // optional (non-cifg && peephole)
+    auto input_gate_bias_alloc = _tensor_builder->at(input_gate_bias_index).get(); // optional
+    lstm_params.set_cifg_params(input_to_input_weights_alloc->handle(),
+                                recurrent_to_input_weights_alloc->handle(),
+                                cell_to_input_weights_handle, input_gate_bias_alloc->handle());
+  }
+  if (has_peephole_param)
+  {
+    auto cell_to_forget_weights_alloc =
+        _tensor_builder->at(cell_to_forget_weights_index).get(); // optional
+    auto cell_to_output_weights_alloc =
+        _tensor_builder->at(cell_to_output_weights_index).get(); // optional
+    lstm_params.set_peephole_params(cell_to_forget_weights_alloc->handle(),
+                                    cell_to_output_weights_alloc->handle());
+  }
+  if (has_projection_param)
+  {
+    auto projection_weights_alloc = _tensor_builder->at(projection_weights_index).get(); // optional
+    auto projection_bias_handle = has_projection_bias
+                                      ? _tensor_builder->at(projection_bias_index).get()->handle()
+                                      : nullptr; // optional
+    lstm_params.set_projection_params(projection_weights_alloc->handle(), projection_bias_handle);
+  }
+
+  fn->configure(
+      input_alloc->handle(), input_to_forget_weights_alloc->handle(),
+      input_to_cell_weights_alloc->handle(), input_to_output_weights_alloc->handle(),
+      recurrent_to_forget_weights_alloc->handle(), recurrent_to_cell_weights_alloc->handle(),
+      recurrent_to_output_weights_alloc->handle(), forget_gate_bias_alloc->handle(),
+      cell_bias_alloc->handle(), output_gate_bias_alloc->handle(), output_state_in_alloc->handle(),
+      cell_state_in_alloc->handle(), scratch_buffer_alloc->handle(),
+      output_state_out_alloc->handle(), cell_state_out_alloc->handle(), output_alloc->handle(),
+      lstm_params, act_info, cell_clip, projection_clip);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::ReduceMax &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::ReduceMax::Input::INPUT)};
+  const auto &axes{node.param().axes};
+  const auto keep_dims{node.param().keep_dims};
+
+  auto ofm_alloc = _tensor_builder->at(output_index).get();
+  auto ifm_alloc = _tensor_builder->at(input_index).get();
+  const auto frontend_layout = _current_subg_layout;
+  const auto backend_layout = ifm_alloc->layout();
+
+  // Convert to ACL axes taking into account negative values and possible duplicates.
+  std::set<std::uint32_t> acl_axes;
+  const int ifm_rank = node.param().rank;
+  for (int axis : axes)
+  {
+    if (axis < 0)
+      axis += ifm_rank;
+    acl_axes.insert(
+        acl_common::ToARMComputeAxis(ifm_rank, axis, frontend_layout, backend_layout).value());
+  }
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLReduceOperation>(
+      _tensor_builder->acl_tensor_manager()->internal_buffer_manager());
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle(), acl_axes, keep_dims,
+                arm_compute::ReduceOperation::MAX);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Comparison &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input0_index{node.getInputs().at(ir::operation::Comparison::Input::INPUT0)};
+  const auto input1_index{node.getInputs().at(ir::operation::Comparison::Input::INPUT1)};
+
+  const auto comparison_type = node.param().comparison_type;
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input0_alloc = _tensor_builder->at(input0_index).get();
+  auto input1_alloc = _tensor_builder->at(input1_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLComparison>();
+
+  fn->configure(input0_alloc->handle(), input1_alloc->handle(), output_alloc->handle(),
+                (arm_compute::ComparisonOperation)comparison_type);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Pack &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  auto axis{node.param().axis};
+
+  const auto output_rank = node.param().rank;
+
+  std::vector<ir::OperandIndex> input_indexes;
+  for (const auto &input_index : node.getInputs())
+    input_indexes.emplace_back(input_index);
+
+  auto output = _tensor_builder->at(output_index).get()->handle();
+  std::vector<arm_compute::ICLTensor *> inputs;
+  for (const auto &input_index : input_indexes)
+    inputs.emplace_back(_tensor_builder->at(input_index)->handle());
+
+  const auto frontend_layout = _current_subg_layout;
+  const auto backend_layout = _tensor_builder->at(output_index).get()->layout();
+
+  if (axis < 0)
+    axis += output_rank;
+  axis = acl_common::ToARMComputeAxis(output_rank, axis, frontend_layout, backend_layout).value();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLStackLayer>();
+
+  fn->configure(inputs, axis, output);
+
+  _execution_builder->append(asAclFunction(std::move(fn)));
+}
+
+void KernelGenerator::visit(const ir::operation::Permute &node)
+{
+  const auto ofm_idx{node.getOutputs().at(0)};
+  const auto ifm_idx{node.getInputs().at(0)};
+  const auto permute_type = node.getPermuteType();
+  auto ofm_alloc = _tensor_builder->at(ofm_idx).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_idx).get();
+  const auto rank = _ctx.at(ofm_idx).shape().rank();
+  assert(_ctx.at(ifm_idx).shape().rank() == _ctx.at(ofm_idx).shape().rank());
+
+  std::unique_ptr<::arm_compute::IFunction> fn;
+  arm_compute::PermutationVector pv;
+  if (permute_type == ir::operation::Permute::Type::NCHW_TO_NHWC && rank == 4)
+  {
+    // WHCN -> CWHN
+    pv = arm_compute::PermutationVector{2, 0, 1};
+
+    auto l = nnfw::cpp14::make_unique<::arm_compute::CLPermute>();
+
+    l->configure(ifm_alloc->handle(), ofm_alloc->handle(), pv);
+
+    fn = std::move(l);
+  }
+  else if (permute_type == ir::operation::Permute::Type::NHWC_TO_NCHW && rank == 4)
+  {
+    // CWHN -> WHCN
+    pv = arm_compute::PermutationVector{1, 2, 0};
+
+    auto l = nnfw::cpp14::make_unique<::arm_compute::CLPermute>();
+
+    l->configure(ifm_alloc->handle(), ofm_alloc->handle(), pv);
+
+    fn = std::move(l);
+  }
+  else
+  {
+    auto l = nnfw::cpp14::make_unique<::arm_compute::CLCopy>();
+
+    l->configure(ifm_alloc->handle(), ofm_alloc->handle());
+
+    fn = std::move(l);
+  }
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::RSQRT &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::RSQRT::Input::INPUT)};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLRsqrtLayer>();
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle());
+
+  _execution_builder->append(asAclFunction(std::move(fn)));
+}
+
+void KernelGenerator::visit(const ir::operation::ReLU &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::ReLU::Input::INPUT)};
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input_alloc = _tensor_builder->at(input_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<arm_compute::CLActivationLayer>();
+
+  const ::arm_compute::ActivationLayerInfo act_info{
+      ::arm_compute::ActivationLayerInfo::ActivationFunction::RELU};
+
+  fn->configure(input_alloc->handle(), output_alloc->handle(), act_info);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::ResizeBilinear &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+
+  const auto ifm_index{node.getInputs().at(ir::operation::ResizeBilinear::Input::INPUT)};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLScale>();
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle(),
+                ::arm_compute::InterpolationPolicy::BILINEAR, ::arm_compute::BorderMode::REPLICATE,
+                ::arm_compute::PixelValue(0.f), ::arm_compute::SamplingPolicy::TOP_LEFT);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::ReLU1 &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::ReLU1::Input::INPUT)};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+
+  const ::arm_compute::ActivationLayerInfo act_info{
+      ::arm_compute::ActivationLayerInfo::ActivationFunction::LU_BOUNDED_RELU, 1.0f, -1.0f};
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLActivationLayer>();
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle(), act_info);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::ReLU6 &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::ReLU6::Input::INPUT)};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+
+  const ::arm_compute::ActivationLayerInfo act_info{
+      ::arm_compute::ActivationLayerInfo::ActivationFunction::BOUNDED_RELU, 6.0f};
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLActivationLayer>();
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle(), act_info);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::RNN &node)
+{
+  const auto output_index{node.getOutputs().at(ir::operation::RNN::Output::OUTPUT)};
+  const auto hidden_state_out_index{
+      node.getOutputs().at(ir::operation::RNN::Output::HIDDEN_STATE_OUT)};
+
+  const auto input_index{node.getInputs().at(ir::operation::RNN::Input::INPUT)};
+  const auto weights_index{node.getInputs().at(ir::operation::RNN::Input::WEIGHTS)};
+  const auto recurrent_weights_index{
+      node.getInputs().at(ir::operation::RNN::Input::RECURRENT_WEIGHTS)};
+  const auto bias_index{node.getInputs().at(ir::operation::RNN::Input::BIAS)};
+  const auto hidden_state_in_index{node.getInputs().at(ir::operation::RNN::Input::HIDDEN_STATE_IN)};
+
+  const auto activation = node.param().activation;
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto hidden_state_out_alloc = _tensor_builder->at(hidden_state_out_index).get();
+
+  auto input_alloc = _tensor_builder->at(input_index).get();
+  auto weights_alloc = _tensor_builder->at(weights_index).get();
+  auto recurrent_weights_alloc = _tensor_builder->at(recurrent_weights_index).get();
+  auto bias_alloc = _tensor_builder->at(bias_index).get();
+  auto hidden_state_in_alloc = _tensor_builder->at(hidden_state_in_index).get();
+  auto act_info = ::neurun::backend::acl_common::asActivationLayerInfo(activation);
+
+  auto copy_layer = nnfw::cpp14::make_unique<::arm_compute::CLCopy>();
+  copy_layer->configure(hidden_state_in_alloc->handle(), hidden_state_out_alloc->handle());
+  _execution_builder->append(asAclFunction(std::move(copy_layer)));
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLRNNLayerEx>(
+      _tensor_builder->acl_tensor_manager()->internal_buffer_manager());
+  fn->configure(input_alloc->handle(), weights_alloc->handle(), recurrent_weights_alloc->handle(),
+                bias_alloc->handle(), hidden_state_out_alloc->handle(), output_alloc->handle(),
+                act_info);
+  _execution_builder->append(asAclFunction(std::move(fn)));
+}
+
+void KernelGenerator::visit(const ir::operation::Floor &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::Floor::Input::INPUT)};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLFloor>();
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::SpaceToBatchND &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::SpaceToBatchND::Input::INPUT)};
+  const auto block_size_index{
+      node.getInputs().at(ir::operation::SpaceToBatchND::Input::BLOCK_SIZE)};
+  const auto paddings_index{node.getInputs().at(ir::operation::SpaceToBatchND::Input::PADDINGS)};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+  auto block_size_alloc = _tensor_builder->at(block_size_index).get();
+  auto paddings_alloc = _tensor_builder->at(paddings_index).get();
+
+  assert(_ctx.at(block_size_index).isConstant());
+  assert(_ctx.at(paddings_index).isConstant());
+
+  std::unique_ptr<::arm_compute::IFunction> fn;
+  if (_ctx.at(ofm_index).typeInfo().type() == ir::DataType::QUANT8_ASYMM)
+  {
+    // NOTE CLSpaceToBatchLayer has a bug that padding's values are 0 even when zero point of
+    // QASYMM8 is not 0.
+    auto l = nnfw::cpp14::make_unique<::arm_compute::CLSpaceToBatchND>();
+    l->configure(ifm_alloc->handle(), block_size_alloc->handle(), paddings_alloc->handle(),
+                 ofm_alloc->handle());
+    fn = std::move(l);
+  }
+  else
+  {
+    auto l = nnfw::cpp14::make_unique<::arm_compute::CLSpaceToBatchLayer>();
+    l->configure(ifm_alloc->handle(), block_size_alloc->handle(), paddings_alloc->handle(),
+                 ofm_alloc->handle());
+    fn = std::move(l);
+  }
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::SpaceToDepth &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::SpaceToDepth::Input::INPUT)};
+
+  auto block_size = node.param().block_size;
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLSpaceToDepth>();
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle(), block_size);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::L2Pool2D &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::L2Pool2D::Input::INPUT)};
+
+  const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature(_current_subg_layout);
+  const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature(_current_subg_layout);
+
+  uint32_t kw = node.param().kw;
+  uint32_t kh = node.param().kh;
+  const auto stride = node.param().stride;
+  const auto padding =
+      neurun::util::calculatePadding(node.param().padding, ifm_shape, ofm_shape, stride, kw, kh);
+  const auto activation = node.param().activation;
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+
+  ::arm_compute::PoolingLayerInfo info{
+      ::arm_compute::PoolingType::L2, ::arm_compute::Size2D{kw, kh},
+      ::neurun::backend::acl_common::asPadStrideInfo(padding, stride)};
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLPoolingLayer>();
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle(), info);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+
+  ActivationBuilder{*_execution_builder}.append(activation, ofm_alloc->handle());
+}
+
+void KernelGenerator::visit(const ir::operation::EmbeddingLookup &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto lookups_index{node.getInputs().at(ir::operation::EmbeddingLookup::Input::LOOKUPS)};
+  const auto values_index{node.getInputs().at(ir::operation::EmbeddingLookup::Input::VALUES)};
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto lookups_alloc = _tensor_builder->at(lookups_index).get();
+  auto values_alloc = _tensor_builder->at(values_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLEmbeddingLookup>();
+
+  fn->configure(values_alloc->handle(), output_alloc->handle(), lookups_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::L2Normalization &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::L2Normalization::Input::INPUT)};
+
+  // {CL|Neon}L2Normalization performs the reduction only along dimension 0
+  // L2 Normalization always performs the reduction along the depth axis
+  // Thus, we repurpose {CL|Neon}NormalizationLayers to act as depthwise L2 normalizations by
+  // choosing normalization parameters as below
+
+  const auto &ifm_shape = _ctx.at(ifm_index).shape();
+  // TODO Support optional constant dimension that normalization would be performed on
+  const auto normalization_axis = node.param().rank - 1;
+  int32_t radius =
+      2 * ifm_shape.dim(normalization_axis) + 1; // normSize = depth(last dimension) * 2 + 1
+  float alpha = 1.0f;                            // In the implementation to make alpha_ become 1
+  float beta = 0.5f;                             // pow(reduction, -0.5) = 1 / sqrt(reduction)
+  float bias = 0.0f;                             // Don't offset the reduction.
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+
+  const auto norm_info = ::arm_compute::NormalizationLayerInfo(::arm_compute::NormType::CROSS_MAP,
+                                                               radius, alpha, beta, bias, false);
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLNormalizationLayer>();
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle(), norm_info);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::HashtableLookup &node)
+{
+  const auto output_index{node.getOutputs().at(ir::operation::HashtableLookup::Output::OUTPUT)};
+  const auto hits_index{node.getOutputs().at(ir::operation::HashtableLookup::Output::HITS)};
+
+  const auto lookups_index{node.getInputs().at(ir::operation::HashtableLookup::Input::LOOKUPS)};
+  const auto keys_index{node.getInputs().at(ir::operation::HashtableLookup::Input::KEYS)};
+  const auto values_index{node.getInputs().at(ir::operation::HashtableLookup::Input::VALUES)};
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto hits_alloc = _tensor_builder->at(hits_index).get();
+
+  auto lookups_alloc = _tensor_builder->at(lookups_index).get();
+  auto keys_alloc = _tensor_builder->at(keys_index).get();
+  auto values_alloc = _tensor_builder->at(values_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLHashtableLookup>();
+
+  fn->configure(lookups_alloc->handle(), keys_alloc->handle(), values_alloc->handle(),
+                output_alloc->handle(), hits_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::PReLU &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::PReLU::Input::INPUT)};
+  const auto alpha_index{node.getInputs().at(ir::operation::PReLU::Input::ALPHA)};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+  auto alpha_alloc = _tensor_builder->at(alpha_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLPReLU>();
+
+  fn->configure(ifm_alloc->handle(), alpha_alloc->handle(), ofm_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::TransposeConv &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto output_shape_index{
+      node.getInputs().at(ir::operation::TransposeConv::Input::OUTPUT_SHAPE)};
+  const auto ker_index{node.getInputs().at(ir::operation::TransposeConv::Input::KERNEL)};
+  const auto ifm_index{node.getInputs().at(ir::operation::TransposeConv::Input::INPUT)};
+
+  const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature(_current_subg_layout);
+  const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature(_current_subg_layout);
+  const auto ker_shape = _ctx.at(ker_index).shape().asFeature(_current_subg_layout);
+
+  const auto stride = node.param().stride;
+
+  assert((node.param().padding.type == ir::PaddingType::SAME) ||
+         (node.param().padding.type == ir::PaddingType::VALID));
+  auto padding = neurun::util::calculatePadding(node.param().padding, ofm_shape, ifm_shape, stride,
+                                                ker_shape.W, ker_shape.H);
+
+  uint32_t invalid_horizontal = 0;
+  uint32_t invalid_vertical = 0;
+  if (node.param().padding.type == ir::PaddingType::VALID)
+  {
+    invalid_horizontal =
+        ofm_shape.W - (1 + (ifm_shape.W - 1) * stride.horizontal) - (ker_shape.W - 1);
+    invalid_vertical = ofm_shape.H - (1 + (ifm_shape.H - 1) * stride.vertical) - (ker_shape.H - 1);
+  }
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+  auto ker_alloc = _tensor_builder->at(ker_index).get();
+
+  const auto tconv_info = acl_common::asPadStrideInfo(padding, stride);
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLTransposeConvLayer>(
+      _tensor_builder->acl_tensor_manager()->internal_buffer_manager());
+
+  fn->configure(ifm_alloc->handle(), ker_alloc->handle(), nullptr, ofm_alloc->handle(), tconv_info,
+                invalid_horizontal, invalid_vertical);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::SQRT &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::SQRT::Input::INPUT)};
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input_alloc = _tensor_builder->at(input_index).get();
+
+  const ::arm_compute::ActivationLayerInfo act_info{
+      ::arm_compute::ActivationLayerInfo::ActivationFunction::SQRT};
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLActivationLayer>();
+
+  fn->configure(input_alloc->handle(), output_alloc->handle(), act_info);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::LogicalOr &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input0_index{node.getInputs().at(ir::operation::LogicalOr::Input::INPUT0)};
+  const auto input1_index{node.getInputs().at(ir::operation::LogicalOr::Input::INPUT1)};
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input0_alloc = _tensor_builder->at(input0_index).get();
+  auto input1_alloc = _tensor_builder->at(input1_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLBitwiseOr>();
+
+  fn->configure(input0_alloc->handle(), input1_alloc->handle(), output_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::LogicalNot &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::LogicalNot::Input::INPUT)};
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input_alloc = _tensor_builder->at(input_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLBitwiseNot>();
+
+  fn->configure(input_alloc->handle(), output_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::SquaredDifference &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto lhs_index{node.getInputs().at(ir::operation::SquaredDifference::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::SquaredDifference::Input::RHS)};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto lhs_alloc = _tensor_builder->at(lhs_index).get();
+  auto rhs_alloc = _tensor_builder->at(rhs_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLElementwiseSquaredDiff>();
+
+  fn->configure(lhs_alloc->handle(), rhs_alloc->handle(), ofm_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::TopKV2 &node)
+{
+  const auto outputValues_index{node.getOutputs().at(ir::operation::TopKV2::Output::OUTPUT_VALUES)};
+  const auto outputIndices_index{
+      node.getOutputs().at(ir::operation::TopKV2::Output::OUTPUT_INDICES)};
+
+  const auto inputData_index{node.getInputs().at(ir::operation::TopKV2::Input::INPUT)};
+
+  // Currently, we only support the vector input.
+  assert(_ctx.at(inputData_index).shape().rank() == 1 ||
+         _ctx.at(inputData_index).shape().rank() == 2);
+
+  const auto k = node.param().k;
+
+  auto values_alloc = _tensor_builder->at(outputValues_index).get();
+  auto indices_alloc = _tensor_builder->at(outputIndices_index).get();
+  auto input_alloc = _tensor_builder->at(inputData_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLTopKV2>();
+
+  fn->configure(input_alloc->handle(), k, values_alloc->handle(), indices_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Gather &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+
+  const auto ifm_index{node.getInputs().at(ir::operation::Gather::Input::INPUT)};
+  const auto indices_index{node.getInputs().at(ir::operation::Gather::Input::INDICES)};
+
+  const auto ifm_shape = _ctx.at(ifm_index).shape();
+
+  const auto ifm_rank = node.param().rank;
+  const auto axis_raw = node.param().axis;
+  const auto axis_value = (axis_raw < 0 ? (ifm_rank + axis_raw) : axis_raw);
+  const int axis = ::neurun::backend::acl_common::ToARMComputeAxis(ifm_rank, axis_value).value();
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+  auto indices_alloc = _tensor_builder->at(indices_index).get();
+
+  // NOTE The frontend layout and backend layout must be the same for this operation.
+  //      If not the same, we have to add a stage(?) to perform permutation of output tensor. It
+  //      is not not efficient even if it works well. If so, it would be better to set the
+  //      layout of these backend tensors to the same layout.
+  //      There is also one thing we have to think about. This operation depends on the layout of
+  //      a model. For example, if a model in NHWC has this operation as output rank == 4, indices
+  //      rank == 2 and axis == 2, this operation should work as the axis W and C, but the axis W
+  //      and C are not sequential in NCHW. So the backend in NCHW cannot handle this case.
+  const auto backend_layout = ofm_alloc->layout();
+  UNUSED_RELEASE(backend_layout);
+  assert(backend_layout == ifm_alloc->layout());
+  assert(backend_layout == indices_alloc->layout());
+  assert(ifm_rank < 4 || _current_subg_layout == backend_layout);
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLGatherEx>();
+
+  fn->configure(ifm_alloc->handle(), indices_alloc->handle(), ofm_alloc->handle(), axis);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Neg &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::Neg::Input::INPUT)};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLNeg>();
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Abs &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::Abs::Input::INPUT)};
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input_alloc = _tensor_builder->at(input_index).get();
+
+  const ::arm_compute::ActivationLayerInfo act_info{
+      ::arm_compute::ActivationLayerInfo::ActivationFunction::ABS};
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLActivationLayer>();
+
+  fn->configure(input_alloc->handle(), output_alloc->handle(), act_info);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::ArgMax &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::ArgMax::Input::INPUT)};
+
+  auto ifm_shape = _ctx.at(ifm_index).shape();
+  auto ofm_shape = _ctx.at(ofm_index).shape();
+
+  assert((ifm_shape.rank() - 1) == ofm_shape.rank());
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+  const auto ifm_rank = node.param().rank;
+  auto frontend_layout = _current_subg_layout;
+  auto backend_layout = ifm_alloc->layout();
+
+  int axis_value = node.param().axis;
+  if (axis_value < 0)
+  {
+    axis_value += ifm_rank;
+  }
+
+  auto acl_axis =
+      acl_common::ToARMComputeAxis(ifm_rank, axis_value, frontend_layout, backend_layout).value();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLArgOperation>();
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle(), {acl_axis},
+                ::arm_compute::ArgOperation::MAX);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Dequantize &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::Dequantize::Input::INPUT)};
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input_alloc = _tensor_builder->at(input_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLCast>();
+
+  fn->configure(input_alloc->handle(), output_alloc->handle(), arm_compute::SubDataType::NONE);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Mean &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::Mean::Input::INPUT)};
+  const auto &axes{node.param().axes};
+  const auto keep_dims{node.param().keep_dims};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+  const auto frontend_layout = _current_subg_layout;
+  const auto backend_layout = ifm_alloc->layout();
+
+  // Convert to ACL axes taking into account negative values and possible duplicates.
+  std::set<std::uint32_t> acl_axes;
+  const int ifm_rank = node.param().rank;
+  for (int axis : axes)
+  {
+    if (axis < 0)
+      axis += ifm_rank;
+    acl_axes.insert(
+        acl_common::ToARMComputeAxis(ifm_rank, axis, frontend_layout, backend_layout).value());
+  }
+
+  arm_compute::Coordinates reduce_axes;
+  for (const auto axis : acl_axes)
+  {
+    reduce_axes.set(reduce_axes.num_dimensions(), axis);
+  }
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLReduceMean>();
+
+  fn->configure(ifm_alloc->handle(), reduce_axes, keep_dims, ofm_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::LocalResponseNormalization &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{
+      node.getInputs().at(ir::operation::LocalResponseNormalization::Input::INPUT)};
+
+  auto radius = node.param().radius;
+  auto alpha = node.param().alpha;
+  auto beta = node.param().beta;
+  auto bias = node.param().bias;
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+
+  const auto norm_info = ::arm_compute::NormalizationLayerInfo(
+      ::arm_compute::NormType::CROSS_MAP, radius * 2 + 1, alpha, beta, bias, false);
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLNormalizationLayer>();
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle(), norm_info);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::DepthToSpace &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::DepthToSpace::Input::INPUT)};
+
+  auto block_size = node.param().block_size;
+  assert(block_size > 0);
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input_alloc = _tensor_builder->at(input_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLDepthToSpace>();
+
+  fn->configure(input_alloc->handle(), output_alloc->handle(), block_size);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::ReduceMin &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::ReduceMin::Input::INPUT)};
+  const auto &axes{node.param().axes};
+  const auto keep_dims{node.param().keep_dims};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+  const auto frontend_layout = _current_subg_layout;
+  const auto backend_layout = ifm_alloc->layout();
+
+  // Convert to ACL axes taking into account negative values and possible duplicates.
+  std::set<std::uint32_t> acl_axes;
+  const int ifm_rank = node.param().rank;
+  for (int axis : axes)
+  {
+    if (axis < 0)
+      axis += ifm_rank;
+    acl_axes.insert(
+        acl_common::ToARMComputeAxis(ifm_rank, axis, frontend_layout, backend_layout).value());
+  }
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLReduceOperation>(
+      _tensor_builder->acl_tensor_manager()->internal_buffer_manager());
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle(), acl_axes, keep_dims,
+                ::arm_compute::ReduceOperation::MIN);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Split &node)
+{
+  const auto ifm_index{node.getInputs().at(ir::operation::Split::Input::INPUT)};
+
+  assert(node.param().num_splits == static_cast<int>(node.getOutputs().size()));
+
+  const auto ifm_rank = node.param().rank;
+  std::vector<ir::OperandIndex> output_indexes;
+  for (const auto &output : node.getOutputs())
+    output_indexes.emplace_back(output);
+
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+  std::vector<arm_compute::ICLTensor *> output_allocs;
+  for (const auto &ofm_ind : output_indexes)
+    output_allocs.emplace_back(_tensor_builder->at(ofm_ind).get()->handle());
+
+  const auto frontend_layout = _current_subg_layout;
+  const auto backend_layout = ifm_alloc->layout();
+  auto axis = node.param().axis;
+  if (axis < 0)
+    axis += ifm_rank;
+  axis = acl_common::ToARMComputeAxis(ifm_rank, axis, frontend_layout, backend_layout).value();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLSplit>();
+
+  fn->configure(ifm_alloc->handle(), output_allocs, axis);
+
+  _execution_builder->append(asAclFunction(std::move(fn)));
+}
+
+void KernelGenerator::visit(const ir::operation::Unpack &node)
+{
+  const auto input_index{node.getInputs().at(ir::operation::Unpack::Input::INPUT)};
+  auto axis{node.param().axis};
+
+  const auto input_rank = node.param().rank;
+
+  std::vector<ir::OperandIndex> output_indexes;
+  for (const auto &output_index : node.getOutputs())
+    output_indexes.emplace_back(output_index);
+
+  auto input = _tensor_builder->at(input_index).get()->handle();
+  std::vector<arm_compute::ICLTensor *> outputs;
+  for (const auto &output_index : output_indexes)
+    outputs.emplace_back(_tensor_builder->at(output_index)->handle());
+
+  const auto frontend_layout = _current_subg_layout;
+  const auto backend_layout = _tensor_builder->at(input_index).get()->layout();
+  if (axis < 0)
+    axis += input_rank;
+  axis = acl_common::ToARMComputeAxis(input_rank, axis, frontend_layout, backend_layout).value();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLUnstack>();
+
+  fn->configure(input, outputs, axis);
+
+  _execution_builder->append(asAclFunction(std::move(fn)));
+}
+
+void KernelGenerator::visit(const ir::operation::Pad &node)
+{
+  const auto input_index{node.getInputs().at(ir::operation::Pad::Input::INPUT)};
+  const auto pad_index{node.getInputs().at(ir::operation::Pad::Input::PAD)};
+  const auto output_index{node.getOutputs().at(0)};
+  assert(_ctx.at(pad_index).isConstant());
+
+  auto rank = node.param().rank;
+  auto pad_base = _ctx.at(pad_index).data().base();
+
+  auto input_type = _ctx.at(input_index).typeInfo();
+  auto data_type = acl_common::asDataType(input_type.type());
+  auto quant_info = ::arm_compute::QuantizationInfo(input_type.scale(), input_type.offset());
+  const auto pixel_value = ::arm_compute::PixelValue(0, data_type, quant_info);
+
+  auto input = _tensor_builder->at(input_index).get()->handle();
+  auto output = _tensor_builder->at(output_index).get()->handle();
+
+  ::arm_compute::PaddingList padding_list;
+  padding_list.resize(rank);
+  for (int32_t n = 0; n < rank; ++n)
+  {
+    const int32_t *from = reinterpret_cast<const int32_t *>(pad_base) + (n * 2);
+
+    const auto frontend_layout = _current_subg_layout;
+    const auto backend_layout = _tensor_builder->at(input_index).get()->layout();
+    const auto axis =
+        acl_common::ToARMComputeAxis(rank, n, frontend_layout, backend_layout).value();
+    padding_list[axis] = ::arm_compute::PaddingInfo{from[0], from[1]};
+  }
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLPadLayer>();
+  fn->configure(input, output, padding_list, pixel_value);
+
+  _execution_builder->append(asAclFunction(std::move(fn)));
+}
+
+void KernelGenerator::visit(const ir::operation::Min &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto lhs_index{node.getInputs().at(ir::operation::Min::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::Min::Input::RHS)};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto lhs_alloc = _tensor_builder->at(lhs_index).get();
+  auto rhs_alloc = _tensor_builder->at(rhs_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLElementwiseMin>();
+
+  fn->configure(lhs_alloc->handle(), rhs_alloc->handle(), ofm_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Max &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto lhs_index{node.getInputs().at(ir::operation::Max::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::Max::Input::RHS)};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto lhs_alloc = _tensor_builder->at(lhs_index).get();
+  auto rhs_alloc = _tensor_builder->at(rhs_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::CLElementwiseMax>();
+
+  fn->configure(lhs_alloc->handle(), rhs_alloc->handle(), ofm_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+} // namespace acl_cl
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/acl_cl/KernelGenerator.h b/runtime/neurun/backend/acl_cl/KernelGenerator.h
new file mode 100644
index 000000000..a577f1ebc
--- /dev/null
+++ b/runtime/neurun/backend/acl_cl/KernelGenerator.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ACL_CL_KERNEL_GENERATOR_H__
+#define __NEURUN_BACKEND_ACL_CL_KERNEL_GENERATOR_H__
+
+#include <backend/IKernelGenerator.h>
+
+#include "ir/Operands.h"
+#include "TensorBuilder.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_cl
+{
+
+class KernelGenerator : public IKernelGenerator
+{
+public:
+  KernelGenerator(const ir::Operands &ctx, const std::shared_ptr<TensorBuilder> &tensor_builder);
+
+  void visit(const ir::OpSequence &) override;
+  void visit(const ir::operation::BatchToSpaceND &) override;
+  void visit(const ir::operation::Conv2D &) override;
+  void visit(const ir::operation::DepthwiseConv2D &) override;
+  void visit(const ir::operation::MaxPool2D &) override;
+  void visit(const ir::operation::AvgPool2D &) override;
+  void visit(const ir::operation::Concat &) override;
+  void visit(const ir::operation::FullyConnected &) override;
+  void visit(const ir::operation::Mul &) override;
+  void visit(const ir::operation::ReduceSum &) override;
+  void visit(const ir::operation::Reshape &) override;
+  void visit(const ir::operation::Squeeze &) override;
+  void visit(const ir::operation::Tanh &) override;
+  void visit(const ir::operation::Softmax &) override;
+  void visit(const ir::operation::Slice &) override;
+  void visit(const ir::operation::StridedSlice &) override;
+  void visit(const ir::operation::Transpose &) override;
+  void visit(const ir::operation::Add &) override;
+  void visit(const ir::operation::Sub &) override;
+  void visit(const ir::operation::Cast &) override;
+  void visit(const ir::operation::Div &) override;
+  void visit(const ir::operation::Exp &) override;
+  void visit(const ir::operation::InstanceNorm &) override;
+  void visit(const ir::operation::Logistic &) override;
+  void visit(const ir::operation::ReduceMax &) override;
+  void visit(const ir::operation::Comparison &) override;
+  void visit(const ir::operation::LogicalAnd &) override;
+  void visit(const ir::operation::LSTM &) override;
+  void visit(const ir::operation::Pack &) override;
+  void visit(const ir::operation::Permute &) override;
+  void visit(const ir::operation::RSQRT &) override;
+  void visit(const ir::operation::ReLU &) override;
+  void visit(const ir::operation::ResizeBilinear &) override;
+  void visit(const ir::operation::ReLU1 &) override;
+  void visit(const ir::operation::ReLU6 &) override;
+  void visit(const ir::operation::RNN &) override;
+  void visit(const ir::operation::Floor &) override;
+  void visit(const ir::operation::SpaceToBatchND &) override;
+  void visit(const ir::operation::SpaceToDepth &) override;
+  void visit(const ir::operation::L2Pool2D &) override;
+  void visit(const ir::operation::EmbeddingLookup &) override;
+  void visit(const ir::operation::L2Normalization &) override;
+  void visit(const ir::operation::HashtableLookup &) override;
+  void visit(const ir::operation::PReLU &) override;
+  void visit(const ir::operation::TransposeConv &) override;
+  void visit(const ir::operation::SQRT &) override;
+  void visit(const ir::operation::LogicalOr &) override;
+  void visit(const ir::operation::LogicalNot &) override;
+  void visit(const ir::operation::SquaredDifference &) override;
+  void visit(const ir::operation::TopKV2 &) override;
+  void visit(const ir::operation::Gather &) override;
+  void visit(const ir::operation::Neg &) override;
+  void visit(const ir::operation::Abs &) override;
+  void visit(const ir::operation::ArgMax &) override;
+  void visit(const ir::operation::Dequantize &) override;
+  void visit(const ir::operation::Mean &) override;
+  void visit(const ir::operation::LocalResponseNormalization &) override;
+  void visit(const ir::operation::DepthToSpace &) override;
+  void visit(const ir::operation::ReduceMin &) override;
+  void visit(const ir::operation::Split &) override;
+  void visit(const ir::operation::Unpack &) override;
+  void visit(const ir::operation::Pad &) override;
+  void visit(const ir::operation::Min &) override;
+  void visit(const ir::operation::Max &) override;
+
+private:
+  const ir::Operands &_ctx;
+  std::shared_ptr<TensorBuilder> _tensor_builder;
+  ir::Layout _current_subg_layout;
+};
+
+} // namespace acl_cl
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ACL_CL_KERNEL_GENERATOR_H__
diff --git a/runtime/neurun/backend/acl_cl/PluginClassesAllocator.cc b/runtime/neurun/backend/acl_cl/PluginClassesAllocator.cc
new file mode 100644
index 000000000..ac3f0acff
--- /dev/null
+++ b/runtime/neurun/backend/acl_cl/PluginClassesAllocator.cc
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <util/logging.h>
+
+#include "Backend.h"
+
+extern "C" {
+neurun::backend::Backend *neurun_backend_create()
+{
+  VERBOSE(neurun_backend_create) << "'acl_cl' loaded\n";
+  return new neurun::backend::acl_cl::Backend;
+}
+
+void neurun_backend_destroy(neurun::backend::Backend *backend)
+{
+  VERBOSE(neurun_backend_create) << "'acl_cl' unloaded\n";
+  delete backend;
+}
+}
diff --git a/runtime/neurun/backend/acl_cl/ShapeFixer.cc b/runtime/neurun/backend/acl_cl/ShapeFixer.cc
new file mode 100644
index 000000000..e1cbeab6c
--- /dev/null
+++ b/runtime/neurun/backend/acl_cl/ShapeFixer.cc
@@ -0,0 +1,434 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ShapeFixer.h"
+
+#include <arm_compute/runtime/CL/CLFunctions.h>   // Include all ARM Compute CL functions
+#include <arm_compute/runtime/CL/CLFunctionsEx.h> // Include all ARM Compute EX CL functions
+
+#include <AclFunction.h>
+#include <Convert.h>
+#include <Swizzle.h>
+
+#include "ir/Index.h"
+#include "compiler/IExecutionBuilder.h"
+#include "exec/NopFunction.h"
+#include "util/logging.h"
+#include "util/Utils.h"
+#include "util/Padding.h"
+
+using ::neurun::compiler::IExecutionBuilder;
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_cl
+{
+
+using ::neurun::backend::acl_common::asAclFunction;
+
+ShapeFixer::ShapeFixer(const ir::Operands &ctx,
+                       const std::shared_ptr<TensorBuilder> &tensor_builder)
+    : _ctx(ctx), _tensor_builder(tensor_builder)
+{
+  assert(tensor_builder);
+}
+
+void ShapeFixer::visit(const ir::operation::BatchToSpaceND &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::BatchToSpaceND::Input::INPUT)};
+  _tensor_builder->dimCorrection(ofm_index, false);
+  _tensor_builder->dimCorrection(ifm_index, false);
+}
+
+void ShapeFixer::visit(const ir::operation::Cast &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Conv2D &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::DepthwiseConv2D &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::MaxPool2D &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::AvgPool2D &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Concat &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  _tensor_builder->dimCorrection(ofm_index, false);
+  for (const auto &input : node.getInputs())
+    _tensor_builder->dimCorrection(input, false);
+}
+
+void ShapeFixer::visit(const ir::operation::FullyConnected &node)
+{
+  using ir::operation::FullyConnected;
+  const auto input_index{node.getInputs().at(FullyConnected::Input::INPUT)};
+  const auto input_rank = _ctx.at(input_index).shape().rank();
+  if (input_rank == 4)
+    _tensor_builder->dimCorrection(input_index, false);
+}
+
+void ShapeFixer::visit(const ir::operation::Mul &node)
+{
+  const auto lhs_index{node.getInputs().at(ir::operation::Mul::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::Mul::Input::RHS)};
+
+  if (!(_ctx.at(lhs_index).shape() == _ctx.at(rhs_index).shape()))
+  {
+    const auto broadcast_rank =
+        std::max(_ctx.at(lhs_index).shape().rank(), _ctx.at(rhs_index).shape().rank());
+
+    // TODO remove const_cast later. For example, _ctx may need to be a non const variable or
+    //      a node to extend shape may be inserted in front of this operation
+    const_cast<ir::Shape &>(_ctx.at(lhs_index).shape()).extendRank(broadcast_rank);
+    const_cast<ir::Shape &>(_ctx.at(rhs_index).shape()).extendRank(broadcast_rank);
+  }
+}
+
+void ShapeFixer::visit(const ir::operation::ReduceSum &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Reshape &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::Reshape::Input::INPUT)};
+  _tensor_builder->dimCorrection(input_index, false);
+  _tensor_builder->dimCorrection(output_index, false);
+}
+
+void ShapeFixer::visit(const ir::operation::Squeeze &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  if (_ctx.at(output_index).shape().rank() == 0)
+    const_cast<ir::Shape &>(_ctx.at(output_index).shape()).extendRank(1);
+  const auto input_index{node.getInputs().at(ir::operation::Squeeze::Input::INPUT)};
+  _tensor_builder->dimCorrection(input_index, false);
+  _tensor_builder->dimCorrection(output_index, false);
+}
+
+void ShapeFixer::visit(const ir::operation::Tanh &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Softmax &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Slice &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::StridedSlice &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::StridedSlice::Input::INPUT)};
+  _tensor_builder->dimCorrection(ofm_index, false);
+  _tensor_builder->dimCorrection(ifm_index, false);
+}
+
+void ShapeFixer::visit(const ir::operation::Transpose &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Add &node)
+{
+  const auto lhs_index{node.getInputs().at(ir::operation::Add::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::Add::Input::RHS)};
+
+  if (!(_ctx.at(lhs_index).shape() == _ctx.at(rhs_index).shape()))
+  {
+    const auto broadcast_rank =
+        std::max(_ctx.at(lhs_index).shape().rank(), _ctx.at(rhs_index).shape().rank());
+    const_cast<ir::Shape &>(_ctx.at(lhs_index).shape()).extendRank(broadcast_rank);
+    const_cast<ir::Shape &>(_ctx.at(rhs_index).shape()).extendRank(broadcast_rank);
+  }
+}
+
+void ShapeFixer::visit(const ir::operation::Sub &node)
+{
+  const auto lhs_index{node.getInputs().at(ir::operation::Sub::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::Sub::Input::RHS)};
+
+  if (!(_ctx.at(lhs_index).shape() == _ctx.at(rhs_index).shape()))
+  {
+    const auto broadcast_rank =
+        std::max(_ctx.at(lhs_index).shape().rank(), _ctx.at(rhs_index).shape().rank());
+
+    // TODO remove const_cast later. For example, _ctx may need to be a non const variable or
+    //      a node to extend shape may be inserted in front of this operation
+    const_cast<ir::Shape &>(_ctx.at(lhs_index).shape()).extendRank(broadcast_rank);
+    const_cast<ir::Shape &>(_ctx.at(rhs_index).shape()).extendRank(broadcast_rank);
+  }
+}
+
+void ShapeFixer::visit(const ir::operation::Div &node)
+{
+  const auto lhs_index{node.getInputs().at(ir::operation::Div::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::Div::Input::RHS)};
+
+  if (!(_ctx.at(lhs_index).shape() == _ctx.at(rhs_index).shape()))
+  {
+    const auto broadcast_rank =
+        std::max(_ctx.at(lhs_index).shape().rank(), _ctx.at(rhs_index).shape().rank());
+
+    // TODO remove const_cast later. For example, _ctx may need to be a non const variable or
+    //      a node to extend shape may be inserted in front of this operation
+    const_cast<ir::Shape &>(_ctx.at(lhs_index).shape()).extendRank(broadcast_rank);
+    const_cast<ir::Shape &>(_ctx.at(rhs_index).shape()).extendRank(broadcast_rank);
+  }
+}
+
+void ShapeFixer::visit(const ir::operation::Exp &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::InstanceNorm &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Logistic &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::LogicalAnd &node)
+{
+  const auto input0_index{node.getInputs().at(ir::operation::LogicalAnd::Input::INPUT0)};
+  const auto input1_index{node.getInputs().at(ir::operation::LogicalAnd::Input::INPUT1)};
+
+  if (!(_ctx.at(input0_index).shape() == _ctx.at(input1_index).shape()))
+  {
+    const auto broadcast_rank =
+        std::max(_ctx.at(input0_index).shape().rank(), _ctx.at(input1_index).shape().rank());
+
+    // TODO remove const_cast later. For example, _ctx may need to be a non const variable or
+    //      a node to extend shape may be inserted in front of this operation
+    const_cast<ir::Shape &>(_ctx.at(input0_index).shape()).extendRank(broadcast_rank);
+    const_cast<ir::Shape &>(_ctx.at(input1_index).shape()).extendRank(broadcast_rank);
+  }
+}
+
+void ShapeFixer::visit(const ir::operation::LSTM &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::ReduceMax &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Comparison &node)
+{
+  const auto input0_index{node.getInputs().at(ir::operation::Comparison::Input::INPUT0)};
+  const auto input1_index{node.getInputs().at(ir::operation::Comparison::Input::INPUT1)};
+
+  if (!(_ctx.at(input0_index).shape() == _ctx.at(input1_index).shape()))
+  {
+    const auto broadcast_rank =
+        std::max(_ctx.at(input0_index).shape().rank(), _ctx.at(input1_index).shape().rank());
+
+    // TODO remove const_cast later. For example, _ctx may need to be a non const variable or
+    //      a node to extend shape may be inserted in front of this operation
+    const_cast<ir::Shape &>(_ctx.at(input0_index).shape()).extendRank(broadcast_rank);
+    const_cast<ir::Shape &>(_ctx.at(input1_index).shape()).extendRank(broadcast_rank);
+  }
+}
+
+void ShapeFixer::visit(const ir::operation::Pack &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  _tensor_builder->dimCorrection(ofm_index, false);
+  for (const auto &inputs : node.getInputs())
+  {
+    _tensor_builder->dimCorrection(inputs, false);
+    const auto ofm_rank = _ctx.at(ofm_index).shape().rank();
+
+    // TODO remove const_cast later. For example, _ctx may need to be a non const variable or
+    //      a node to extend shape may be inserted in front of this operation
+    const_cast<ir::Shape &>(_ctx.at(inputs).shape()).extendRank(ofm_rank);
+  }
+}
+
+void ShapeFixer::visit(const ir::operation::Permute &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::RSQRT &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::ReLU &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::ResizeBilinear &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::ReLU1 &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::ReLU6 &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::RNN &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Floor &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::SpaceToBatchND &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::SpaceToBatchND::Input::INPUT)};
+  _tensor_builder->dimCorrection(ofm_index, false);
+  _tensor_builder->dimCorrection(ifm_index, false);
+}
+
+void ShapeFixer::visit(const ir::operation::SpaceToDepth &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::SpaceToDepth::Input::INPUT)};
+  _tensor_builder->dimCorrection(ofm_index, false);
+  _tensor_builder->dimCorrection(ifm_index, false);
+}
+
+void ShapeFixer::visit(const ir::operation::L2Pool2D &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::EmbeddingLookup &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto values_index{node.getInputs().at(ir::operation::EmbeddingLookup::Input::VALUES)};
+  _tensor_builder->dimCorrection(values_index, false);
+  _tensor_builder->dimCorrection(output_index, false);
+}
+
+void ShapeFixer::visit(const ir::operation::L2Normalization &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::HashtableLookup &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::PReLU &node)
+{
+  const auto ifm_index{node.getInputs().at(ir::operation::PReLU::Input::INPUT)};
+  const auto alpha_index{node.getInputs().at(ir::operation::PReLU::Input::ALPHA)};
+
+  if (!(_ctx.at(ifm_index).shape() == _ctx.at(alpha_index).shape()))
+  {
+    const auto broadcast_rank =
+        std::max(_ctx.at(ifm_index).shape().rank(), _ctx.at(alpha_index).shape().rank());
+    const_cast<ir::Shape &>(_ctx.at(ifm_index).shape()).extendRank(broadcast_rank);
+    const_cast<ir::Shape &>(_ctx.at(alpha_index).shape()).extendRank(broadcast_rank);
+  }
+}
+
+void ShapeFixer::visit(const ir::operation::TransposeConv &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::SQRT &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::LogicalOr &node)
+{
+  const auto input0_index{node.getInputs().at(ir::operation::LogicalOr::Input::INPUT0)};
+  const auto input1_index{node.getInputs().at(ir::operation::LogicalOr::Input::INPUT1)};
+
+  if (!(_ctx.at(input0_index).shape() == _ctx.at(input1_index).shape()))
+  {
+    const auto broadcast_rank =
+        std::max(_ctx.at(input0_index).shape().rank(), _ctx.at(input1_index).shape().rank());
+    const_cast<ir::Shape &>(_ctx.at(input0_index).shape()).extendRank(broadcast_rank);
+    const_cast<ir::Shape &>(_ctx.at(input1_index).shape()).extendRank(broadcast_rank);
+  }
+}
+
+void ShapeFixer::visit(const ir::operation::LogicalNot &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::SquaredDifference &node)
+{
+  const auto lhs_index{node.getInputs().at(ir::operation::SquaredDifference::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::SquaredDifference::Input::RHS)};
+
+  if (!(_ctx.at(lhs_index).shape() == _ctx.at(rhs_index).shape()))
+  {
+    const auto broadcast_rank =
+        std::max(_ctx.at(lhs_index).shape().rank(), _ctx.at(rhs_index).shape().rank());
+    const_cast<ir::Shape &>(_ctx.at(lhs_index).shape()).extendRank(broadcast_rank);
+    const_cast<ir::Shape &>(_ctx.at(rhs_index).shape()).extendRank(broadcast_rank);
+  }
+}
+
+void ShapeFixer::visit(const ir::operation::TopKV2 &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Gather &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::Gather::Input::INPUT)};
+  const auto indices_index{node.getInputs().at(ir::operation::Gather::Input::INDICES)};
+  _tensor_builder->dimCorrection(ofm_index, false);
+  _tensor_builder->dimCorrection(ifm_index, false);
+  _tensor_builder->dimCorrection(indices_index, false);
+}
+
+void ShapeFixer::visit(const ir::operation::Neg &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Abs &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::ArgMax &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::ArgMax::Input::INPUT)};
+  _tensor_builder->dimCorrection(ofm_index, false);
+  _tensor_builder->dimCorrection(ifm_index, false);
+}
+
+void ShapeFixer::visit(const ir::operation::Dequantize &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Mean &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::LocalResponseNormalization &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::DepthToSpace &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::ReduceMin &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Split &node)
+{
+  const auto input_index{node.getInputs().at(ir::operation::Split::Input::INPUT)};
+  _tensor_builder->dimCorrection(input_index, false);
+  for (const auto &output : node.getOutputs())
+    _tensor_builder->dimCorrection(output, false);
+}
+
+void ShapeFixer::visit(const ir::operation::Unpack &node)
+{
+  const auto input_index{node.getInputs().at(ir::operation::Unpack::Input::INPUT)};
+  _tensor_builder->dimCorrection(input_index, false);
+  for (const auto &output_index : node.getOutputs())
+    _tensor_builder->dimCorrection(output_index, false);
+}
+
+void ShapeFixer::visit(const ir::operation::Pad &node)
+{
+  const auto input_index{node.getInputs().at(ir::operation::Pad::Input::INPUT)};
+  const auto output_index{node.getOutputs().at(0)};
+  _tensor_builder->dimCorrection(input_index, false);
+  _tensor_builder->dimCorrection(output_index, false);
+}
+
+void ShapeFixer::visit(const ir::operation::Min &node)
+{
+  const auto lhs_index{node.getInputs().at(ir::operation::Min::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::Min::Input::RHS)};
+
+  if (!(_ctx.at(lhs_index).shape() == _ctx.at(rhs_index).shape()))
+  {
+    const auto broadcast_rank =
+        std::max(_ctx.at(lhs_index).shape().rank(), _ctx.at(rhs_index).shape().rank());
+
+    // TODO remove const_cast later. For example, _ctx may need to be a non const variable or
+    //      a node to extend shape may be inserted in front of this operation
+    const_cast<ir::Shape &>(_ctx.at(lhs_index).shape()).extendRank(broadcast_rank);
+    const_cast<ir::Shape &>(_ctx.at(rhs_index).shape()).extendRank(broadcast_rank);
+  }
+}
+
+void ShapeFixer::visit(const ir::operation::Max &node)
+{
+  const auto lhs_index{node.getInputs().at(ir::operation::Max::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::Max::Input::RHS)};
+
+  if (!(_ctx.at(lhs_index).shape() == _ctx.at(rhs_index).shape()))
+  {
+    const auto broadcast_rank =
+        std::max(_ctx.at(lhs_index).shape().rank(), _ctx.at(rhs_index).shape().rank());
+
+    // TODO remove const_cast later. For example, _ctx may need to be a non const variable or
+    //      a node to extend shape may be inserted in front of this operation
+    const_cast<ir::Shape &>(_ctx.at(lhs_index).shape()).extendRank(broadcast_rank);
+    const_cast<ir::Shape &>(_ctx.at(rhs_index).shape()).extendRank(broadcast_rank);
+  }
+}
+
+} // namespace acl_cl
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/acl_cl/ShapeFixer.h b/runtime/neurun/backend/acl_cl/ShapeFixer.h
new file mode 100644
index 000000000..ec5f5c896
--- /dev/null
+++ b/runtime/neurun/backend/acl_cl/ShapeFixer.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ACL_CL_SHAPE_FIXER_H__
+#define __NEURUN_BACKEND_ACL_CL_SHAPE_FIXER_H__
+
+#include <backend/IShapeFixer.h>
+
+#include "ir/Operands.h"
+#include "TensorBuilder.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_cl
+{
+
+class ShapeFixer : public IShapeFixer
+{
+public:
+  ShapeFixer(const ir::Operands &ctx, const std::shared_ptr<TensorBuilder> &tensor_builder);
+
+  void visit(const ir::operation::BatchToSpaceND &) override;
+  void visit(const ir::operation::Conv2D &) override;
+  void visit(const ir::operation::DepthwiseConv2D &) override;
+  void visit(const ir::operation::MaxPool2D &) override;
+  void visit(const ir::operation::AvgPool2D &) override;
+  void visit(const ir::operation::Concat &) override;
+  void visit(const ir::operation::FullyConnected &) override;
+  void visit(const ir::operation::Mul &) override;
+  void visit(const ir::operation::ReduceSum &) override;
+  void visit(const ir::operation::Reshape &) override;
+  void visit(const ir::operation::Squeeze &) override;
+  void visit(const ir::operation::Tanh &) override;
+  void visit(const ir::operation::Softmax &) override;
+  void visit(const ir::operation::Slice &) override;
+  void visit(const ir::operation::StridedSlice &) override;
+  void visit(const ir::operation::Transpose &) override;
+  void visit(const ir::operation::Add &) override;
+  void visit(const ir::operation::Sub &) override;
+  void visit(const ir::operation::Cast &) override;
+  void visit(const ir::operation::Div &) override;
+  void visit(const ir::operation::Exp &) override;
+  void visit(const ir::operation::InstanceNorm &) override;
+  void visit(const ir::operation::Logistic &) override;
+  void visit(const ir::operation::ReduceMax &) override;
+  void visit(const ir::operation::Comparison &) override;
+  void visit(const ir::operation::LogicalAnd &) override;
+  void visit(const ir::operation::LSTM &) override;
+  void visit(const ir::operation::Pack &) override;
+  void visit(const ir::operation::Permute &) override;
+  void visit(const ir::operation::RSQRT &) override;
+  void visit(const ir::operation::ReLU &) override;
+  void visit(const ir::operation::ResizeBilinear &) override;
+  void visit(const ir::operation::ReLU1 &) override;
+  void visit(const ir::operation::ReLU6 &) override;
+  void visit(const ir::operation::RNN &) override;
+  void visit(const ir::operation::Floor &) override;
+  void visit(const ir::operation::SpaceToBatchND &) override;
+  void visit(const ir::operation::SpaceToDepth &) override;
+  void visit(const ir::operation::L2Pool2D &) override;
+  void visit(const ir::operation::EmbeddingLookup &) override;
+  void visit(const ir::operation::L2Normalization &) override;
+  void visit(const ir::operation::HashtableLookup &) override;
+  void visit(const ir::operation::PReLU &) override;
+  void visit(const ir::operation::TransposeConv &) override;
+  void visit(const ir::operation::SQRT &) override;
+  void visit(const ir::operation::LogicalOr &) override;
+  void visit(const ir::operation::LogicalNot &) override;
+  void visit(const ir::operation::SquaredDifference &) override;
+  void visit(const ir::operation::TopKV2 &) override;
+  void visit(const ir::operation::Gather &) override;
+  void visit(const ir::operation::Neg &) override;
+  void visit(const ir::operation::Abs &) override;
+  void visit(const ir::operation::ArgMax &) override;
+  void visit(const ir::operation::Dequantize &) override;
+  void visit(const ir::operation::Mean &) override;
+  void visit(const ir::operation::LocalResponseNormalization &) override;
+  void visit(const ir::operation::DepthToSpace &) override;
+  void visit(const ir::operation::ReduceMin &) override;
+  void visit(const ir::operation::Split &) override;
+  void visit(const ir::operation::Unpack &) override;
+  void visit(const ir::operation::Pad &) override;
+  void visit(const ir::operation::Min &) override;
+  void visit(const ir::operation::Max &) override;
+
+private:
+  const ir::Operands &_ctx;
+  std::shared_ptr<TensorBuilder> _tensor_builder;
+};
+
+} // namespace acl_cl
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ACL_CL_SHAPE_FIXER_H__
diff --git a/runtime/neurun/backend/acl_cl/TensorBuilder.h b/runtime/neurun/backend/acl_cl/TensorBuilder.h
new file mode 100644
index 000000000..b9a0dd4a6
--- /dev/null
+++ b/runtime/neurun/backend/acl_cl/TensorBuilder.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ACL_CL_TENSOR_BUILDER_H__
+#define __NEURUN_BACKEND_ACL_CL_TENSOR_BUILDER_H__
+
+#include <TemplTensorBuilder.h>
+
+#include "operand/CLTensor.h"
+#include "operand/CLSubTensor.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_cl
+{
+
+using TensorBuilder =
+    acl_common::TemplTensorBuilder<operand::ICLTensor, operand::CLTensor, operand::CLSubTensor>;
+
+} // namespace acl_cl
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ACL_CL_TENSOR_BUILDER_H__
diff --git a/runtime/neurun/backend/acl_cl/TensorManager.h b/runtime/neurun/backend/acl_cl/TensorManager.h
new file mode 100644
index 000000000..fd2a9059c
--- /dev/null
+++ b/runtime/neurun/backend/acl_cl/TensorManager.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ACL_CL_TENSOR_MANAGER_H__
+#define __NEURUN_BACKEND_ACL_CL_TENSOR_MANAGER_H__
+
+#include <arm_compute/runtime/CL/CLBufferAllocator.h>
+#include <arm_compute/runtime/PoolManager.h>
+#include <arm_compute/runtime/BlobLifetimeManager.h>
+#include <arm_compute/runtime/MemoryManagerOnDemand.h>
+#include <arm_compute/runtime/CL/CLMemoryGroup.h>
+
+#include <AclMemoryManager.h>
+#include <AclLinearMemoryManager.h>
+#include <AclInternalBufferManager.h>
+#include <AclTensorManager.h>
+
+#include "operand/CLTensor.h"
+#include "operand/CLSubTensor.h"
+
+#include "util/logging.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_cl
+{
+
+using MemoryManager =
+    acl_common::AclMemoryManager<operand::ICLTensor, operand::CLTensor, operand::CLSubTensor>;
+
+using LinearMemoryManager = acl_common::AclLinearMemoryManager<
+    operand::ICLTensor, operand::CLTensor, operand::CLSubTensor,
+    ::arm_compute::MemoryManagerOnDemand, ::arm_compute::PoolManager,
+    ::arm_compute::BlobLifetimeManager, ::arm_compute::CLBufferAllocator,
+    ::arm_compute::CLMemoryGroup>;
+
+using InternalBufferManager = acl_common::AclInternalBufferManager<
+    ::arm_compute::MemoryManagerOnDemand, ::arm_compute::PoolManager,
+    ::arm_compute::BlobLifetimeManager, ::arm_compute::CLBufferAllocator>;
+
+using TensorManager =
+    acl_common::AclTensorManager<operand::ICLTensor, operand::CLTensor, operand::CLSubTensor>;
+
+TensorManager *createTensorManager()
+{
+  const std::string executor_str = util::getConfigString(util::config::EXECUTOR);
+
+  if (executor_str == "Linear")
+  {
+    VERBOSE(acl_cl_createTensorManager) << "AclTensorManager as Linear" << std::endl;
+    return new TensorManager(new MemoryManager(), new LinearMemoryManager(),
+                             new InternalBufferManager());
+  }
+  else
+  {
+    VERBOSE(acl_cl_createTensorManager) << "AclTensorManager" << std::endl;
+    return new TensorManager(new MemoryManager(), new MemoryManager(), new InternalBufferManager());
+  }
+}
+
+} // namespace acl_cl
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ACL_CL_TENSOR_MANAGER_H__
diff --git a/runtime/neurun/backend/acl_cl/TensorRegister.h b/runtime/neurun/backend/acl_cl/TensorRegister.h
new file mode 100644
index 000000000..02de45580
--- /dev/null
+++ b/runtime/neurun/backend/acl_cl/TensorRegister.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ACL_CL_TENSOR_REGISTER_H__
+#define __NEURUN_BACKEND_ACL_CL_TENSOR_REGISTER_H__
+
+#include <AclTensorRegister.h>
+#include <misc/polymorphic_downcast.h>
+#include "TensorBuilder.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_cl
+{
+
+class TensorRegister : public acl_common::AclTensorRegister
+{
+public:
+  TensorRegister(const ir::Operands &operands, const std::shared_ptr<TensorBuilder> &tensor_builder)
+      : acl_common::AclTensorRegister{operands, tensor_builder}
+  {
+    // DO NOTHING
+  }
+
+  void setUsesCount(const ir::OperandIndex &ind, size_t num_uses) const override
+  {
+    nnfw::misc::polymorphic_downcast<TensorBuilder *>(tensor_builder().get())
+        ->setUsesCount(ind, num_uses);
+  }
+};
+
+} // namespace acl_cl
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ACL_CL_TENSOR_REGISTER_H__
diff --git a/runtime/neurun/backend/acl_cl/operand/CLSubTensor.cc b/runtime/neurun/backend/acl_cl/operand/CLSubTensor.cc
new file mode 100644
index 000000000..70c8829d9
--- /dev/null
+++ b/runtime/neurun/backend/acl_cl/operand/CLSubTensor.cc
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "CLSubTensor.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_cl
+{
+namespace operand
+{
+
+CLSubTensor::CLSubTensor(ICLTensor *parent, const arm_compute::TensorShape &tensor_shape,
+                         const arm_compute::Coordinates &coords, size_t rank, bool extend_parent)
+    : _cl_sub_tensor(std::make_shared<arm_compute::CLSubTensor>(parent->handle(), tensor_shape,
+                                                                coords, extend_parent)),
+      _rank{rank}
+{
+  // DO NOTHING
+}
+
+const arm_compute::CLSubTensor *CLSubTensor::handle() const { return _cl_sub_tensor.get(); }
+
+arm_compute::CLSubTensor *CLSubTensor::handle() { return _cl_sub_tensor.get(); }
+
+} // namespace operand
+} // namespace acl_cl
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/acl_cl/operand/CLSubTensor.h b/runtime/neurun/backend/acl_cl/operand/CLSubTensor.h
new file mode 100644
index 000000000..8eba3760f
--- /dev/null
+++ b/runtime/neurun/backend/acl_cl/operand/CLSubTensor.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ACL_CL_OPERAND_CL_SUB_TENSOR_H__
+#define __NEURUN_BACKEND_ACL_CL_OPERAND_CL_SUB_TENSOR_H__
+
+#include <arm_compute/runtime/CL/CLSubTensor.h>
+#include "ICLTensor.h"
+#include "compiler/SubTensorInfo.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_cl
+{
+namespace operand
+{
+
+class CLSubTensor : public ICLTensor
+{
+public:
+  CLSubTensor() = delete;
+
+public:
+  CLSubTensor(ICLTensor *parent, const arm_compute::TensorShape &tensor_shape,
+              const arm_compute::Coordinates &coords, size_t rank, bool extend_parent = false);
+
+public:
+  size_t num_dimensions() const final { return _rank; }
+
+public:
+  const arm_compute::CLSubTensor *handle() const override;
+  arm_compute::CLSubTensor *handle() override;
+
+public:
+  // This method is used to prevent the use of memcpy for SubTensor
+  bool has_padding() const override { return true; }
+
+private:
+  std::shared_ptr<arm_compute::CLSubTensor> _cl_sub_tensor;
+  size_t _rank;
+};
+
+} // namespace operand
+} // namespace acl_cl
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ACL_CL_OPERAND_CL_SUB_TENSOR_H__
diff --git a/runtime/neurun/backend/acl_cl/operand/CLTensor.cc b/runtime/neurun/backend/acl_cl/operand/CLTensor.cc
new file mode 100644
index 000000000..dab74e65f
--- /dev/null
+++ b/runtime/neurun/backend/acl_cl/operand/CLTensor.cc
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "CLTensor.h"
+
+#include <arm_compute/runtime/CL/CLScheduler.h>
+#include <arm_compute/runtime/CL/CLMemory.h>
+#include <arm_compute/runtime/CL/CLMemoryRegion.h>
+
+#include <Convert.h>
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_cl
+{
+namespace operand
+{
+
+CLTensor::CLTensor(const arm_compute::TensorInfo &info, size_t rank, size_t num_uses)
+    : _cl_tensor(std::make_shared<arm_compute::CLTensor>()), _rank{rank}, _num_uses{num_uses}
+{
+  allocator()->init(info);
+}
+
+const arm_compute::CLTensor *CLTensor::handle() const { return _cl_tensor.get(); }
+
+arm_compute::CLTensor *CLTensor::handle() { return _cl_tensor.get(); }
+
+arm_compute::CLTensorAllocator *CLTensor::allocator() { return _cl_tensor->allocator(); }
+
+void CLTensor::map(bool blocking) { _cl_tensor->map(blocking); }
+
+void CLTensor::unmap() { _cl_tensor->unmap(); }
+
+void CLTensor::setBuffer(void *host_ptr)
+{
+  // Constructs a Buffer on a user-supplied memory
+  auto buffer = cl::Buffer(arm_compute::CLScheduler::get().context(),
+                           CL_MEM_USE_HOST_PTR | CL_MEM_READ_WRITE, info()->total_size(), host_ptr);
+  // import memory
+  allocator()->import_memory(buffer);
+}
+
+} // namespace operand
+} // namespace acl_cl
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/acl_cl/operand/CLTensor.h b/runtime/neurun/backend/acl_cl/operand/CLTensor.h
new file mode 100644
index 000000000..8518bf0c3
--- /dev/null
+++ b/runtime/neurun/backend/acl_cl/operand/CLTensor.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ACL_CL_OPERAND_CL_TENSOR_H__
+#define __NEURUN_BACKEND_ACL_CL_OPERAND_CL_TENSOR_H__
+
+#include <arm_compute/core/TensorInfo.h>
+#include <arm_compute/runtime/CL/CLTensor.h>
+#include <arm_compute/runtime/CL/CLScheduler.h>
+#include "arm_compute/runtime/CL/CLTensorAllocator.h"
+#include "ICLTensor.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_cl
+{
+namespace operand
+{
+
+class CLTensor : public ICLTensor
+{
+public:
+  CLTensor() = delete;
+
+public:
+  CLTensor(const arm_compute::TensorInfo &info, size_t rank, size_t num_uses);
+
+public:
+  size_t num_dimensions() const final { return _rank; }
+
+public:
+  const arm_compute::CLTensor *handle() const override;
+  arm_compute::CLTensor *handle() override;
+  size_t num_uses() const { return _num_uses; }
+
+public:
+  arm_compute::CLTensorAllocator *allocator();
+  void map(bool blocking = true);
+  void unmap();
+  /** Set given buffer as the buffer of the tensor
+   *
+   * @note Ownership of the memory is not transferred to this object.
+   *       Thus management (allocate/free) should be done by the client.
+   *
+   * @param[in] host_ptr Storage to be used.
+   */
+  void setBuffer(void *host_ptr);
+
+private:
+  std::shared_ptr<arm_compute::CLTensor> _cl_tensor;
+  size_t _rank;
+  size_t _num_uses;
+};
+
+} // namespace operand
+} // namespace acl_cl
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ACL_CL_OPERAND_CL_TENSOR_H__
diff --git a/runtime/neurun/backend/acl_cl/operand/ICLTensor.cc b/runtime/neurun/backend/acl_cl/operand/ICLTensor.cc
new file mode 100644
index 000000000..6b14584e0
--- /dev/null
+++ b/runtime/neurun/backend/acl_cl/operand/ICLTensor.cc
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ICLTensor.h"
+
+#include <arm_compute/runtime/CL/CLScheduler.h>
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_cl
+{
+namespace operand
+{
+
+void ICLTensor::access(const std::function<void(ITensor &tensor)> &fn)
+{
+  auto &queue = ::arm_compute::CLScheduler::get().queue();
+
+  // This is an optional input
+  if (total_size() == 0)
+    return;
+
+  map(queue);
+  fn(*this);
+  unmap(queue);
+}
+} // namespace operand
+} // namespace acl_cl
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/acl_cl/operand/ICLTensor.h b/runtime/neurun/backend/acl_cl/operand/ICLTensor.h
new file mode 100644
index 000000000..68e4e7fc5
--- /dev/null
+++ b/runtime/neurun/backend/acl_cl/operand/ICLTensor.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ACL_CL_OPERAND_I_CL_TENSOR_H__
+#define __NEURUN_BACKEND_ACL_CL_OPERAND_I_CL_TENSOR_H__
+
+#include <arm_compute/core/CL/ICLTensor.h>
+
+#include <IACLTensor.h>
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_cl
+{
+namespace operand
+{
+
+class ICLTensor : public acl_common::IACLTensor
+{
+public:
+  const arm_compute::ICLTensor *handle() const override = 0;
+  arm_compute::ICLTensor *handle() override = 0;
+
+public:
+  void map(cl::CommandQueue &q, bool blocking = true) { return handle()->map(q, blocking); }
+  void unmap(cl::CommandQueue &q) { return handle()->unmap(q); }
+  void access(const std::function<void(ITensor &tensor)> &fn) final;
+};
+
+} // namespace operand
+} // namespace acl_cl
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ACL_CL_OPERAND_I_CL_TENSOR_H__
diff --git a/runtime/neurun/backend/acl_common/AclFunction.h b/runtime/neurun/backend/acl_common/AclFunction.h
new file mode 100644
index 000000000..a63f3807b
--- /dev/null
+++ b/runtime/neurun/backend/acl_common/AclFunction.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ACL_COMMON_KERNEL_ACL_FUNCTION_H__
+#define __NEURUN_BACKEND_ACL_COMMON_KERNEL_ACL_FUNCTION_H__
+
+#include <exec/IFunction.h>
+#include <arm_compute/runtime/IFunction.h>
+#include <arm_compute/runtime/CL/CLScheduler.h>
+#include <memory>
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_common
+{
+
+class AclFunction : public ::neurun::exec::IFunction
+{
+public:
+  AclFunction() = delete;
+
+public:
+  AclFunction(std::unique_ptr<::arm_compute::IFunction> &&func) : _func(std::move(func))
+  {
+    // DO NOTHING
+  }
+
+public:
+  void run() override { _func->run(); }
+  void runSync() override
+  {
+    run();
+    arm_compute::CLScheduler::get().sync();
+  }
+  void prepare() override { _func->prepare(); }
+
+private:
+  std::unique_ptr<::arm_compute::IFunction> _func;
+};
+
+} // namespace acl_common
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ACL_COMMON_KERNEL_ACL_FUNCTION_H__
diff --git a/runtime/neurun/backend/acl_common/AclInternalBufferManager.h b/runtime/neurun/backend/acl_common/AclInternalBufferManager.h
new file mode 100644
index 000000000..b7183c86e
--- /dev/null
+++ b/runtime/neurun/backend/acl_common/AclInternalBufferManager.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ACL_COMMON_INTERNAL_BUFFER_MANAGER_H__
+#define __NEURUN_BACKEND_ACL_COMMON_INTERNAL_BUFFER_MANAGER_H__
+
+#include <arm_compute/runtime/IMemoryManager.h>
+#include <cassert>
+#include <memory>
+#include <backend/IMemoryManager.h>
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_common
+{
+
+// NOTE. If any backend can use something like InternalBufferManager,
+// this interface can be moved to core/include/backend/
+/**
+ * @brief Interface for InternalBufferManager which has ::arm_compute::IMemoryManager pointer
+ */
+struct IInternalBufferManager : public backend::IMemoryManager
+{
+  virtual ~IInternalBufferManager() = default;
+
+  /**
+   * @brief Get shared_ptr of ::arm_compute::IMemoryManager
+   */
+  virtual std::shared_ptr<::arm_compute::IMemoryManager> internal_buffer_manager(void) = 0;
+};
+
+/**
+ * @brief class for InternalBufferManager which has ::arm_compute::IMemoryManager pointer
+ */
+template <typename T_MemoryManager, typename T_PoolManager, typename T_LifetimeManager,
+          typename T_Allocator>
+class AclInternalBufferManager : public IInternalBufferManager
+{
+public:
+  AclInternalBufferManager() : _allocator{nullptr}
+  {
+    std::shared_ptr<T_LifetimeManager> lifetime_mgr = std::make_shared<T_LifetimeManager>();
+    std::shared_ptr<T_PoolManager> pool_mgr = std::make_shared<T_PoolManager>();
+
+    _internal_manager = std::make_shared<T_MemoryManager>(lifetime_mgr, pool_mgr);
+    assert(_internal_manager);
+  }
+
+  virtual ~AclInternalBufferManager() = default;
+
+  /**
+   * @brief Allocate the internal buffer manager on acl
+   */
+  void allocate(void) override
+  {
+    _allocator = std::make_shared<T_Allocator>();
+    _internal_manager->populate(*_allocator, 1);
+  }
+
+  /**
+   * @brief Deallocate the internal buffer manager on acl
+   */
+  void deallocate(void) override { _internal_manager->clear(); }
+
+  /**
+   * @brief Get shared_ptr of ::arm_compute::IMemoryManager
+   */
+  std::shared_ptr<::arm_compute::IMemoryManager> internal_buffer_manager(void) override
+  {
+    return _internal_manager;
+  }
+
+private:
+  std::shared_ptr<T_Allocator> _allocator;
+  std::shared_ptr<T_MemoryManager> _internal_manager;
+};
+
+} // namespace acl_common
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ACL_COMMON_INTERNAL_BUFFER_MANAGER_H__
diff --git a/runtime/neurun/backend/acl_common/AclLinearMemoryManager.h b/runtime/neurun/backend/acl_common/AclLinearMemoryManager.h
new file mode 100644
index 000000000..7ed719bc3
--- /dev/null
+++ b/runtime/neurun/backend/acl_common/AclLinearMemoryManager.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ACL_COMMON_LINEAR_MEMORY_MANAGER_H__
+#define __NEURUN_BACKEND_ACL_COMMON_LINEAR_MEMORY_MANAGER_H__
+
+#include <cassert>
+
+#include "AclMemoryManager.h"
+#include "ir/OperandIndexMap.h"
+#include "util/logging.h"
+
+namespace
+{
+
+template <typename T_MemoryManager, typename T_PoolManager, typename T_LifetimeManager>
+std::shared_ptr<T_MemoryManager> createMemoryManager()
+{
+  std::shared_ptr<T_LifetimeManager> lifetime_mgr = std::make_shared<T_LifetimeManager>();
+  std::shared_ptr<T_PoolManager> pool_mgr = std::make_shared<T_PoolManager>();
+
+  std::shared_ptr<T_MemoryManager> mem_mgr =
+      std::make_shared<T_MemoryManager>(lifetime_mgr, pool_mgr);
+  return mem_mgr;
+}
+
+} // namespace anonymous
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_common
+{
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor, typename T_MemoryManager,
+          typename T_PoolManager, typename T_LifetimeManager, typename T_Allocator,
+          typename T_MemoryGroup>
+class AclLinearMemoryManager : public AclMemoryManager<T_ITensor, T_Tensor, T_SubTensor>
+{
+public:
+  AclLinearMemoryManager()
+      : _allocator{nullptr},
+        _io_manager{createMemoryManager<T_MemoryManager, T_PoolManager, T_LifetimeManager>()},
+        _io_group{std::make_shared<T_MemoryGroup>(_io_manager)}
+  {
+    // DO NOTHING
+  }
+
+  virtual ~AclLinearMemoryManager() = default;
+
+  void allocate(void) override
+  {
+    _allocator = std::make_shared<T_Allocator>();
+    _io_manager->populate(*_allocator, 1);
+    _io_group->acquire();
+  }
+
+  void deallocate(void) override
+  {
+    _io_group->release();
+    _io_manager->clear();
+  }
+
+  void startLifetime(const ir::OperandIndex &ind) override
+  {
+    auto &tensors = this->tensors();
+    assert(tensors.find(ind) != tensors.end());
+
+    auto tensor = tensors[ind];
+    assert(tensor->handle());
+
+    _io_group->manage(tensor->handle());
+  }
+
+  void finishLifetime(const ir::OperandIndex &ind) override
+  {
+    auto &tensors = this->tensors();
+    assert(tensors.find(ind) != tensors.end());
+
+    auto tensor = tensors[ind];
+    assert(tensor->allocator());
+
+    tensor->allocator()->allocate();
+  }
+
+private:
+  std::shared_ptr<T_Allocator> _allocator;
+  std::shared_ptr<T_MemoryManager> _io_manager;
+  std::shared_ptr<T_MemoryGroup> _io_group;
+};
+
+} // namespace acl_common
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ACL_COMMON_LINEAR_MEMORY_MANAGER_H__
diff --git a/runtime/neurun/backend/acl_common/AclMemoryManager.h b/runtime/neurun/backend/acl_common/AclMemoryManager.h
new file mode 100644
index 000000000..af7f3a460
--- /dev/null
+++ b/runtime/neurun/backend/acl_common/AclMemoryManager.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ACL_COMMON_MEMORY_MANAGER_H__
+#define __NEURUN_BACKEND_ACL_COMMON_MEMORY_MANAGER_H__
+
+#include <arm_compute/core/Types.h>
+#include <arm_compute/runtime/IMemoryManager.h>
+#include <cassert>
+
+#include "backend/IMemoryManager.h"
+#include "ir/OperandIndexMap.h"
+#include "Convert.h"
+#include "util/logging.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_common
+{
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+class AclMemoryManager : public backend::IMemoryManager
+{
+public:
+  AclMemoryManager()
+  {
+    // DO NOTHING
+  }
+
+  virtual ~AclMemoryManager() = default;
+
+  void allocate(void) override
+  {
+    for (const auto &tensor_entry : _tensors)
+    {
+      auto tensor = tensor_entry.second;
+      tensor->allocator()->allocate();
+    }
+  }
+
+  void deallocate(void) override
+  {
+    for (const auto &tensor_entry : _tensors)
+    {
+      auto tensor = tensor_entry.second;
+      tensor->allocator()->free();
+    }
+  }
+
+  virtual void startLifetime(const ir::OperandIndex &) { /* DO NOTHING */}
+  virtual void finishLifetime(const ir::OperandIndex &) { /* DO NOTHING */}
+
+  void buildTensor(const ir::OperandIndex &ind, const ::arm_compute::TensorInfo &info, size_t rank,
+                   size_t num_uses)
+  {
+    auto tensor = std::make_shared<T_Tensor>(info, rank, num_uses);
+    _tensors[ind] = tensor;
+  }
+
+  void buildSubtensor(std::shared_ptr<T_ITensor> parent_tensor, const ir::OperandIndex &child_ind,
+                      const ::arm_compute::TensorShape &shape,
+                      const ::arm_compute::Coordinates &coordinates, size_t rank,
+                      bool extent_parent)
+  {
+    auto subtensor =
+        std::make_shared<T_SubTensor>(parent_tensor.get(), shape, coordinates, rank, extent_parent);
+    _subtensors[child_ind] = subtensor;
+  }
+
+  ir::OperandIndexMap<std::shared_ptr<T_Tensor>> &tensors(void) { return _tensors; }
+
+  ir::OperandIndexMap<std::shared_ptr<T_SubTensor>> &subtensors(void) { return _subtensors; }
+
+private:
+  ir::OperandIndexMap<std::shared_ptr<T_Tensor>> _tensors;
+  ir::OperandIndexMap<std::shared_ptr<T_SubTensor>> _subtensors;
+};
+
+} // namespace acl_common
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ACL_COMMON_MEMORY_MANAGER_H__
diff --git a/runtime/neurun/backend/acl_common/AclTensorManager.h b/runtime/neurun/backend/acl_common/AclTensorManager.h
new file mode 100644
index 000000000..48a4c2599
--- /dev/null
+++ b/runtime/neurun/backend/acl_common/AclTensorManager.h
@@ -0,0 +1,300 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ACL_COMMON_TENSOR_MANAGER_H__
+#define __NEURUN_BACKEND_ACL_COMMON_TENSOR_MANAGER_H__
+
+#include <arm_compute/runtime/IMemoryManager.h>
+
+#include "backend/ITensorManager.h"
+#include "AclMemoryManager.h"
+#include "AclInternalBufferManager.h"
+#include "ir/OperandIndexMap.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_common
+{
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+class AclTensorManager : public backend::ITensorManager
+{
+public:
+  using T_AclMemoryManager = AclMemoryManager<T_ITensor, T_Tensor, T_SubTensor>;
+
+  AclTensorManager(T_AclMemoryManager *const_mgr, T_AclMemoryManager *nonconst_mgr,
+                   IInternalBufferManager *inter_mgr);
+
+  virtual ~AclTensorManager() = default;
+
+  void allocateConsts(void) override;
+  void allocateNonconsts(void) override;
+  void deallocateConsts(void) override;
+  void deallocateNonconsts(void) override;
+
+  void allocateInternalBufferManager(void);
+  void deallocateInternalBufferManager(void);
+
+  void buildTensor(const ir::OperandIndex &ind, const ::arm_compute::TensorInfo &info, size_t rank,
+                   bool as_const, size_t num_uses);
+  void buildSubtensor(const ir::OperandIndex &parent, const ir::OperandIndex &child,
+                      const ::arm_compute::TensorShape &shape,
+                      const ::arm_compute::Coordinates &coordinates, size_t rank,
+                      bool extent_parent);
+
+  std::shared_ptr<T_ITensor> findTensorAsParent(const ir::OperandIndex &ind);
+
+  void startLifetime(const ir::OperandIndex &ind);
+  void finishLifetime(const ir::OperandIndex &ind);
+
+  std::shared_ptr<T_ITensor> at(const ir::OperandIndex &ind);
+
+  ir::OperandIndexMap<std::shared_ptr<T_Tensor>> &constTensors(void);
+  ir::OperandIndexMap<std::shared_ptr<T_Tensor>> &nonconstTensors(void);
+  ir::OperandIndexMap<std::shared_ptr<T_SubTensor>> &nonconstSubtensors(void);
+
+  std::shared_ptr<::arm_compute::IMemoryManager> internal_buffer_manager(void);
+
+  void iterate(const std::function<void(const ir::OperandIndex &)> &fn);
+
+  void tryDeallocConstants(void);
+
+private:
+  std::unique_ptr<T_AclMemoryManager> _const_mgr;
+  std::unique_ptr<T_AclMemoryManager> _nonconst_mgr;
+  std::unique_ptr<IInternalBufferManager> _inter_mgr;
+  ir::OperandIndexMap<T_AclMemoryManager &> _ind_to_mgr;
+};
+
+} // namespace acl_common
+} // namespace backend
+} // namespace neurun
+
+#include <cassert>
+#include "util/logging.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_common
+{
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+AclTensorManager<T_ITensor, T_Tensor, T_SubTensor>::AclTensorManager(
+    T_AclMemoryManager *const_mgr, T_AclMemoryManager *nonconst_mgr,
+    IInternalBufferManager *inter_mgr)
+    : _const_mgr{const_mgr}, _nonconst_mgr{nonconst_mgr}, _inter_mgr{inter_mgr}
+{
+  // DO NOTHING
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+void AclTensorManager<T_ITensor, T_Tensor, T_SubTensor>::allocateConsts(void)
+{
+  _const_mgr->allocate();
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+void AclTensorManager<T_ITensor, T_Tensor, T_SubTensor>::allocateNonconsts(void)
+{
+  _nonconst_mgr->allocate();
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+void AclTensorManager<T_ITensor, T_Tensor, T_SubTensor>::deallocateConsts(void)
+{
+  _const_mgr->deallocate();
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+void AclTensorManager<T_ITensor, T_Tensor, T_SubTensor>::deallocateNonconsts(void)
+{
+  _nonconst_mgr->deallocate();
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+void AclTensorManager<T_ITensor, T_Tensor, T_SubTensor>::allocateInternalBufferManager(void)
+{
+  _inter_mgr->allocate();
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+void AclTensorManager<T_ITensor, T_Tensor, T_SubTensor>::deallocateInternalBufferManager(void)
+{
+  _inter_mgr->deallocate();
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+void AclTensorManager<T_ITensor, T_Tensor, T_SubTensor>::buildTensor(
+    const ir::OperandIndex &ind, const ::arm_compute::TensorInfo &info, size_t rank, bool as_const,
+    size_t num_uses)
+{
+  assert(_ind_to_mgr.find(ind) == _ind_to_mgr.end());
+  if (as_const)
+  {
+    _const_mgr->buildTensor(ind, info, rank, num_uses);
+    _ind_to_mgr.insert({ind, *_const_mgr});
+  }
+  else
+  {
+    _nonconst_mgr->buildTensor(ind, info, rank, num_uses);
+    _ind_to_mgr.insert({ind, *_nonconst_mgr});
+  }
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+void AclTensorManager<T_ITensor, T_Tensor, T_SubTensor>::buildSubtensor(
+    const ir::OperandIndex &parent, const ir::OperandIndex &child,
+    const ::arm_compute::TensorShape &shape, const ::arm_compute::Coordinates &coordinates,
+    size_t rank, bool extent_parent)
+{
+  assert(_ind_to_mgr.find(child) == _ind_to_mgr.end());
+  std::shared_ptr<T_ITensor> parent_tensor = findTensorAsParent(parent);
+  assert(parent_tensor);
+  _nonconst_mgr->buildSubtensor(parent_tensor, child, shape, coordinates, rank, extent_parent);
+  _ind_to_mgr.insert({child, *_nonconst_mgr});
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+std::shared_ptr<T_ITensor>
+AclTensorManager<T_ITensor, T_Tensor, T_SubTensor>::findTensorAsParent(const ir::OperandIndex &ind)
+{
+
+  auto &tensors = _nonconst_mgr->tensors();
+  auto &subtensors = _nonconst_mgr->subtensors();
+  if (tensors.find(ind) != tensors.end())
+  {
+    // Parent is allocated as tensor
+    return tensors[ind];
+  }
+  else if (subtensors.find(ind) != subtensors.end())
+  {
+    // Parent is allocated as subtensor
+    return subtensors[ind];
+  }
+  else
+  {
+    return nullptr;
+  }
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+void AclTensorManager<T_ITensor, T_Tensor, T_SubTensor>::startLifetime(const ir::OperandIndex &ind)
+{
+  assert(_ind_to_mgr.find(ind) != _ind_to_mgr.end());
+  _ind_to_mgr.at(ind).startLifetime(ind);
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+void AclTensorManager<T_ITensor, T_Tensor, T_SubTensor>::finishLifetime(const ir::OperandIndex &ind)
+{
+  assert(_ind_to_mgr.find(ind) != _ind_to_mgr.end());
+  _ind_to_mgr.at(ind).finishLifetime(ind);
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+std::shared_ptr<T_ITensor>
+AclTensorManager<T_ITensor, T_Tensor, T_SubTensor>::at(const ir::OperandIndex &ind)
+{
+  assert(_ind_to_mgr.find(ind) != _ind_to_mgr.end());
+
+  auto &tensors = _ind_to_mgr.at(ind).tensors();
+  if (tensors.find(ind) != tensors.end())
+  {
+    return tensors.at(ind);
+  }
+  else
+  {
+    return _ind_to_mgr.at(ind).subtensors().at(ind);
+  }
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+ir::OperandIndexMap<std::shared_ptr<T_Tensor>> &
+AclTensorManager<T_ITensor, T_Tensor, T_SubTensor>::constTensors(void)
+{
+  return _const_mgr->tensors();
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+ir::OperandIndexMap<std::shared_ptr<T_Tensor>> &
+AclTensorManager<T_ITensor, T_Tensor, T_SubTensor>::nonconstTensors(void)
+{
+  return _nonconst_mgr->tensors();
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+ir::OperandIndexMap<std::shared_ptr<T_SubTensor>> &
+AclTensorManager<T_ITensor, T_Tensor, T_SubTensor>::nonconstSubtensors(void)
+{
+  return _nonconst_mgr->subtensors();
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+std::shared_ptr<::arm_compute::IMemoryManager>
+AclTensorManager<T_ITensor, T_Tensor, T_SubTensor>::internal_buffer_manager(void)
+{
+  return _inter_mgr->internal_buffer_manager();
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+void AclTensorManager<T_ITensor, T_Tensor, T_SubTensor>::iterate(
+    const std::function<void(const ir::OperandIndex &)> &fn)
+{
+  for (auto it : _nonconst_mgr->tensors())
+    fn(it.first);
+
+  for (auto it : _nonconst_mgr->subtensors())
+    fn(it.first);
+
+  for (auto it : _const_mgr->tensors())
+    fn(it.first);
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+void AclTensorManager<T_ITensor, T_Tensor, T_SubTensor>::tryDeallocConstants(void)
+{
+  auto &tensors = _const_mgr->tensors();
+
+  for (auto it = tensors.begin(); it != tensors.end();)
+  {
+    const auto &ind = it->first;
+    auto tensor = it->second;
+    // NOTE The condition "tensor->num_uses() < 2" is used to prevent deallocating a constant tensor
+    // used in several nodes.
+    if (tensor->handle() && !tensor->handle()->is_used() && tensor->num_uses() < 2)
+    {
+      VERBOSE(AclTensorManager) << "Tensor #" << ind.value()
+                                << " will be deallocated as an unused constant tensor" << std::endl;
+      tensor->allocator()->free();
+      tensor.reset();
+      it = tensors.erase(it);
+    }
+    else
+    {
+      ++it;
+    }
+  }
+}
+
+} // namespace acl_common
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ACL_COMMON_TENSOR_MANAGER_H__
diff --git a/runtime/neurun/backend/acl_common/AclTensorRegister.cc b/runtime/neurun/backend/acl_common/AclTensorRegister.cc
new file mode 100644
index 000000000..07cbece1e
--- /dev/null
+++ b/runtime/neurun/backend/acl_common/AclTensorRegister.cc
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "AclTensorRegister.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_common
+{
+
+AclTensorRegister::AclTensorRegister(const ir::Operands &operands,
+                                     const std::shared_ptr<ITensorBuilder> &tensor_builder)
+    : _operands{operands}, _tensor_builder{tensor_builder}
+{
+  assert(tensor_builder != nullptr);
+}
+
+void AclTensorRegister::visit(const ir::OpSequence &op_seq)
+{
+  for (const auto &e : op_seq.operations())
+  {
+    const auto &node = *(e.node);
+    node.accept(*this);
+    // Set count of nodes to use operand
+    for (const auto &input : node.getInputs())
+    {
+      setUsesCount(input, _operands.at(input).getUses().size());
+    }
+  }
+}
+
+} // namespace acl_common
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/acl_common/AclTensorRegister.h b/runtime/neurun/backend/acl_common/AclTensorRegister.h
new file mode 100644
index 000000000..905e19adb
--- /dev/null
+++ b/runtime/neurun/backend/acl_common/AclTensorRegister.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ACL_COMMON_TENSOR_REGISTER_H__
+#define __NEURUN_BACKEND_ACL_COMMON_TENSOR_REGISTER_H__
+
+#include <backend/ITensorRegister.h>
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_common
+{
+
+class AclTensorRegister : public ITensorRegister
+{
+protected:
+  AclTensorRegister(const ir::Operands &operands,
+                    const std::shared_ptr<ITensorBuilder> &tensor_builder);
+
+public:
+  virtual ~AclTensorRegister() = default;
+
+protected:
+  void visit(const ir::OpSequence &op_seq);
+  virtual void setUsesCount(const ir::OperandIndex &ind, size_t num_uses) const = 0;
+
+protected:
+  const ir::Operands &operands() const override { return _operands; }
+  std::shared_ptr<ITensorBuilder> tensor_builder() const override { return _tensor_builder; }
+  bool supportSubTensor() const final { return true; }
+
+private:
+  const ir::Operands &_operands;
+  const std::shared_ptr<ITensorBuilder> _tensor_builder;
+};
+
+} // namespace acl_common
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ACL_COMMON_TENSOR_REGISTER_H__
diff --git a/runtime/neurun/backend/acl_common/CMakeLists.txt b/runtime/neurun/backend/acl_common/CMakeLists.txt
new file mode 100644
index 000000000..32d01291f
--- /dev/null
+++ b/runtime/neurun/backend/acl_common/CMakeLists.txt
@@ -0,0 +1,19 @@
+# Unsupported architecture
+nnas_find_package(ARMCompute QUIET)
+if(NOT ARMCompute_FOUND)
+  return()
+endif(NOT ARMCompute_FOUND)
+
+file(GLOB SOURCES "*.cc")
+
+add_library(${LIB_NEURUN_BACKEND_ACL_COMMON} STATIC ${SOURCES})
+
+target_include_directories(${LIB_NEURUN_BACKEND_ACL_COMMON} PUBLIC ${NEURUN_INCLUDE_DIR})
+target_include_directories(${LIB_NEURUN_BACKEND_ACL_COMMON} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR})
+target_link_libraries(${LIB_NEURUN_BACKEND_ACL_COMMON} PUBLIC arm_compute arm_compute_ex)
+target_link_libraries(${LIB_NEURUN_BACKEND_ACL_COMMON} PUBLIC nnfw_lib_misc nnfw_lib_cpp14)
+target_link_libraries(${LIB_NEURUN_BACKEND_ACL_COMMON} PRIVATE nnfw_common)
+target_link_libraries(${LIB_NEURUN_BACKEND_ACL_COMMON} PRIVATE nnfw_coverage)
+
+set_target_properties(${LIB_NEURUN_BACKEND_ACL_COMMON} PROPERTIES POSITION_INDEPENDENT_CODE ON)
+set_target_properties(${LIB_NEURUN_BACKEND_ACL_COMMON} PROPERTIES OUTPUT_NAME backend_acl_common)
diff --git a/runtime/neurun/backend/acl_common/Convert.cc b/runtime/neurun/backend/acl_common/Convert.cc
new file mode 100644
index 000000000..fc5be72a2
--- /dev/null
+++ b/runtime/neurun/backend/acl_common/Convert.cc
@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "Convert.h"
+
+#include "Swizzle.h"
+#include "ir/DataType.h"
+#include <cpp14/memory.h>
+
+namespace
+{
+
+::arm_compute::DataLayout asDataLayout(neurun::ir::Layout layout)
+{
+  switch (layout)
+  {
+    case neurun::ir::Layout::NHWC:
+      return ::arm_compute::DataLayout::NHWC;
+    case neurun::ir::Layout::NCHW:
+      return ::arm_compute::DataLayout::NCHW;
+    default:
+      return ::arm_compute::DataLayout::UNKNOWN;
+  }
+}
+
+} // namespace
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_common
+{
+
+::arm_compute::TensorShape asTensorShape(const ir::Shape &shape, ir::Layout frontend_layout,
+                                         ir::Layout backend_layout, bool apply_dim_correction)
+{
+  const uint32_t rank = shape.rank();
+
+  ::arm_compute::TensorShape res{};
+
+  res.set_num_dimensions(rank);
+
+  for (uint32_t axis = 0; axis < rank; ++axis)
+  {
+    // NOTE In some cases, in incorrect dimensions is required.
+    // For example, intput_size is 1 in LSTM. The input-to-input weights([num_units, input_size]) of
+    // LSTM is used as the weight of the FullyConnected.
+    // The FullyConnected's weight must be greater or equal than 2-dimensions.
+    // However, if the dimension correction is applied to input_to_input_weights with input_size
+    // equal to 1, it will be changed to 1-D.
+    // So input_to_input_weights is not used by the weight of FullyConnected.
+    res.set(ToARMComputeAxis(rank, axis, frontend_layout, backend_layout).value(), shape.dim(axis),
+            apply_dim_correction);
+  }
+
+  return res;
+}
+
+::arm_compute::Coordinates asTensorCoordinate(const ::neurun::util::Coordinates &coord,
+                                              ir::Layout frontend_layout, ir::Layout backend_layout)
+{
+  const uint32_t rank = coord.size();
+
+  ::arm_compute::Coordinates res{};
+
+  res.set_num_dimensions(rank);
+
+  for (uint32_t axis = 0; axis < rank; ++axis)
+  {
+    res.set(ToARMComputeAxis(rank, axis, frontend_layout, backend_layout).value(), coord[axis]);
+  }
+
+  return res;
+}
+
+::arm_compute::DataType asDataType(const ir::DataType type)
+{
+  switch (type)
+  {
+    case ir::DataType::FLOAT32:
+      return ::arm_compute::DataType::F32;
+    case ir::DataType::INT32:
+      return ::arm_compute::DataType::S32;
+    case ir::DataType::UINT32:
+      return ::arm_compute::DataType::U32;
+    case ir::DataType::QUANT8_ASYMM:
+      return ::arm_compute::DataType::QASYMM8;
+    case ir::DataType::BOOL8:
+    case ir::DataType::UINT8:
+      return ::arm_compute::DataType::U8;
+    case ir::DataType::QUANT8_SYMM:
+      return ::arm_compute::DataType::S8;
+    default:
+      throw std::runtime_error("Not supported, yet");
+      break;
+  }
+}
+
+::arm_compute::QuantizationInfo asQuantizationInfo(const float scale, const int32_t offset)
+{
+  return ::arm_compute::QuantizationInfo(scale, offset);
+}
+
+::arm_compute::TensorInfo asTensorInfo(const ir::Shape &shape, const ir::TypeInfo &typeInfo,
+                                       ir::Layout frontend_layout, ir::Layout backend_layout,
+                                       bool apply_dim_correction)
+{
+  ::arm_compute::TensorInfo info(
+      asTensorShape(shape, frontend_layout, backend_layout, apply_dim_correction), 1,
+      asDataType(typeInfo.type()), asQuantizationInfo(typeInfo.scale(), typeInfo.offset()));
+  info.set_data_layout(asDataLayout(backend_layout));
+  return info;
+}
+
+::arm_compute::PadStrideInfo asPadStrideInfo(const ir::ExplicitPadding &padding,
+                                             const ir::Stride &stride)
+{
+  return ::arm_compute::PadStrideInfo{stride.horizontal,
+                                      stride.vertical,
+                                      padding.left,
+                                      padding.right,
+                                      padding.top,
+                                      padding.bottom,
+                                      ::arm_compute::DimensionRoundingType::FLOOR};
+}
+
+::arm_compute::ActivationLayerInfo asActivationLayerInfo(const ir::Activation act_code)
+{
+  switch (act_code)
+  {
+    case ir::Activation::NONE:
+      return ::arm_compute::ActivationLayerInfo{};
+    case ir::Activation::RELU:
+      return ::arm_compute::ActivationLayerInfo{
+          ::arm_compute::ActivationLayerInfo::ActivationFunction::RELU};
+    case ir::Activation::RELU1:
+      return ::arm_compute::ActivationLayerInfo{
+          ::arm_compute::ActivationLayerInfo::ActivationFunction::LU_BOUNDED_RELU, 1.0f, -1.0f};
+    case ir::Activation::RELU6:
+      return ::arm_compute::ActivationLayerInfo{
+          ::arm_compute::ActivationLayerInfo::ActivationFunction::LU_BOUNDED_RELU, 6.0f, 0.0f};
+    // Cases for activation of LSTM.
+    case ir::Activation::TANH:
+      return ::arm_compute::ActivationLayerInfo{
+          ::arm_compute::ActivationLayerInfo::ActivationFunction::TANH, 1.0f, 1.0f};
+    case ir::Activation::SIGMOID:
+      // NOTE The sigmoid function is a special case of the Logistic function when L=1, k=1, x0=0.
+      // TODO In ACL and nnapi sepc, currently, Logistic's L always is 1, k always is 1, x0 always
+      // 0(always sigmoid) regardless of values of the parameter.
+      //      If ACL support non-sigmoid logistic, should fix param values.
+      return ::arm_compute::ActivationLayerInfo{
+          ::arm_compute::ActivationLayerInfo::ActivationFunction::LOGISTIC, 0.0f, 0.0f};
+    default:
+      throw std::runtime_error{"Not supported, yet"};
+      break;
+  }
+}
+
+std::unique_ptr<AclFunction> asAclFunction(std::unique_ptr<::arm_compute::IFunction> &&layer)
+{
+  return nnfw::cpp14::make_unique<AclFunction>(std::move(layer));
+}
+
+ir::Layout asRuntimeLayout(::arm_compute::DataLayout data_layout)
+{
+  switch (data_layout)
+  {
+    case ::arm_compute::DataLayout::NHWC:
+      return ir::Layout::NHWC;
+    case ::arm_compute::DataLayout::NCHW:
+      return ir::Layout::NCHW;
+    default:
+      return ir::Layout::UNKNOWN;
+  }
+}
+
+} // namespace acl_common
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/acl_common/Convert.h b/runtime/neurun/backend/acl_common/Convert.h
new file mode 100644
index 000000000..4c638157b
--- /dev/null
+++ b/runtime/neurun/backend/acl_common/Convert.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ACL_COMMON_CONVERT_H__
+#define __NEURUN_BACKEND_ACL_COMMON_CONVERT_H__
+
+#include <arm_compute/core/TensorInfo.h>
+#include <arm_compute/core/SubTensorInfo.h>
+#include <arm_compute/core/TensorShape.h>
+
+#include "ir/Layout.h"
+#include "ir/InternalType.h"
+#include "ir/Operand.h"
+#include "ir/Shape.h"
+#include "ir/TypeInfo.h"
+#include "misc/feature/Shape.h"
+#include "misc/kernel/Shape.h"
+
+#include "util/Padding.h"
+#include "util/Coordinates.h"
+
+#include "AclFunction.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_common
+{
+
+::arm_compute::TensorShape asTensorShape(const ir::Shape &shape, ir::Layout frontend_layout,
+                                         ir::Layout backend_layout,
+                                         bool apply_dim_correction = true);
+::arm_compute::Coordinates asTensorCoordinate(const ::neurun::util::Coordinates &coord,
+                                              ir::Layout frontend_layout,
+                                              ir::Layout backend_layout);
+::arm_compute::DataType asDataType(ir::DataType type);
+::arm_compute::TensorInfo asTensorInfo(const ir::Shape &shape, const ir::TypeInfo &typeInfo,
+                                       ir::Layout frontend_layout, ir::Layout backend_layout,
+                                       bool apply_dim_correction = true);
+
+::arm_compute::PadStrideInfo asPadStrideInfo(const ir::ExplicitPadding &padding,
+                                             const ir::Stride &stride);
+
+::arm_compute::ActivationLayerInfo asActivationLayerInfo(ir::Activation act_code);
+
+std::unique_ptr<AclFunction> asAclFunction(std::unique_ptr<::arm_compute::IFunction> &&layer);
+
+ir::Layout asRuntimeLayout(::arm_compute::DataLayout data_layout);
+
+} // namespace acl_common
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ACL_COMMON_CONVERT_H__
diff --git a/runtime/neurun/backend/acl_common/IACLTensor.cc b/runtime/neurun/backend/acl_common/IACLTensor.cc
new file mode 100644
index 000000000..70ffbdcf0
--- /dev/null
+++ b/runtime/neurun/backend/acl_common/IACLTensor.cc
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "IACLTensor.h"
+#include "Convert.h"
+#include "Swizzle.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_common
+{
+
+size_t IACLTensor::num_dimensions() const
+{
+  throw std::runtime_error("No definition of num_dimensions()");
+  return 0;
+}
+
+size_t IACLTensor::dimension(size_t index) const
+{
+  // Assume that the front is higher dimensional.
+  // i.g. N: 0, C: 1, H: 2, W: 3 for NCHW layout
+  // NOTE This tensor must not be applied dim correction
+  assert(num_dimensions() > index);
+  const ARMComputeAxis reversed{(static_cast<uint32_t>(num_dimensions() - index) - 1)};
+  return info()->dimension(reversed.value());
+}
+
+size_t IACLTensor::calcOffset(const neurun::util::Coordinates &coords) const
+{
+  const auto rank = num_dimensions();
+  assert(rank == coords.size());
+
+  ::arm_compute::Coordinates acl_coords;
+  for (uint32_t i = 0; i < rank; ++i)
+  {
+    const ARMComputeAxis reversed{static_cast<uint32_t>((rank - i) - 1)};
+    acl_coords.set(reversed.value(), coords[i]);
+  }
+
+  return info()->offset_element_in_bytes(acl_coords);
+}
+
+ir::Layout IACLTensor::layout() const { return acl_common::asRuntimeLayout(info()->data_layout()); }
+
+} // namespace acl_common
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/acl_common/IACLTensor.h b/runtime/neurun/backend/acl_common/IACLTensor.h
new file mode 100644
index 000000000..b0dcbb409
--- /dev/null
+++ b/runtime/neurun/backend/acl_common/IACLTensor.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ACL_COMMON_I_ACL_TENSOR_H__
+#define __NEURUN_BACKEND_ACL_COMMON_I_ACL_TENSOR_H__
+
+#include <backend/operand/ITensor.h>
+#include <arm_compute/core/ITensor.h>
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_common
+{
+
+class IACLTensor : public operand::ITensor
+{
+public:
+  IACLTensor() = default;
+  IACLTensor(const IACLTensor &) = delete;
+  IACLTensor &operator=(const IACLTensor &) = delete;
+  IACLTensor(IACLTensor &&) = default;
+  IACLTensor &operator=(IACLTensor &&) = default;
+
+public:
+  uint8_t *buffer() const final { return handle()->buffer(); }
+  size_t total_size() const final { return info()->total_size(); }
+  size_t dimension(size_t index) const final;
+  size_t num_dimensions() const override;
+  size_t calcOffset(const neurun::util::Coordinates &coords) const final;
+  ir::Layout layout() const final;
+  bool has_padding() const override { return info()->has_padding(); }
+
+public:
+  virtual const arm_compute::ITensor *handle() const = 0;
+  virtual arm_compute::ITensor *handle() = 0;
+
+  const arm_compute::ITensorInfo *info() const { return handle()->info(); }
+  arm_compute::ITensorInfo *info() { return handle()->info(); }
+
+  arm_compute::DataType data_type() const { return info()->data_type(); }
+};
+
+} // namespace acl_common
+} // namespace backend
+} // namespace neurun
+
+#endif //__NEURUN_BACKEND_ACL_COMMON_I_ACL_TENSOR_H__
diff --git a/runtime/neurun/backend/acl_common/Swizzle.h b/runtime/neurun/backend/acl_common/Swizzle.h
new file mode 100644
index 000000000..11874b592
--- /dev/null
+++ b/runtime/neurun/backend/acl_common/Swizzle.h
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ACL_COMMON_SWIZZLE_H__
+#define __NEURUN_BACKEND_ACL_COMMON_SWIZZLE_H__
+
+#include <cassert>
+#include <ir/Layout.h>
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_common
+{
+
+class ARMComputeAxis
+{
+public:
+  ARMComputeAxis() = default;
+
+public:
+  explicit ARMComputeAxis(uint32_t value) : _value{value}
+  {
+    // DO NOTHING
+  }
+
+public:
+  uint32_t value(void) const { return _value; }
+
+private:
+  uint32_t _value;
+};
+
+// Convert axis in acl order
+inline ARMComputeAxis ToARMComputeAxis(uint32_t rank, uint32_t axis,
+                                       const ir::Layout org_layout = ir::Layout::UNKNOWN,
+                                       const ir::Layout acl_layout = ir::Layout::UNKNOWN)
+{
+  assert(rank > axis);
+
+  const ARMComputeAxis reversed{(rank - axis) - 1};
+
+  if (rank >= 4 && org_layout == ir::Layout::NHWC && acl_layout == ir::Layout::NCHW)
+  {
+    // NHWC -> WHCN
+    // DEPTH
+    if (0 == reversed.value())
+    {
+      return ARMComputeAxis{2};
+    }
+    // WIDTH
+    if (1 == reversed.value())
+    {
+      return ARMComputeAxis{0};
+    }
+    // HEIGHT
+    if (2 == reversed.value())
+    {
+      return ARMComputeAxis{1};
+    }
+  }
+  if (rank >= 4 && org_layout == ir::Layout::NCHW && acl_layout == ir::Layout::NHWC)
+  {
+    // NCHW -> CWHN
+    // WIDTH
+    if (0 == reversed.value())
+    {
+      return ARMComputeAxis{1};
+    }
+    // HEIGHT
+    if (1 == reversed.value())
+    {
+      return ARMComputeAxis{2};
+    }
+    // DEPTH
+    if (2 == reversed.value())
+    {
+      return ARMComputeAxis{0};
+    }
+  }
+
+  return reversed;
+}
+
+inline ::arm_compute::Coordinates
+getARMComputeAxises(uint32_t rank, const ir::Layout org_layout = ir::Layout::UNKNOWN,
+                    const ir::Layout acl_layout = ir::Layout::UNKNOWN)
+{
+  ::arm_compute::Coordinates res{};
+
+  res.set_num_dimensions(rank);
+
+  for (uint32_t axis = 0; axis < rank; ++axis)
+  {
+    res.set(axis, ToARMComputeAxis(rank, axis, org_layout, acl_layout).value());
+  }
+
+  return res;
+}
+
+// Restructure runtime_permutationVector to ACL_permutationVector
+inline ::arm_compute::PermutationVector
+getARMComputePermutationVector(uint32_t rank, const std::vector<int32_t> runtime_pv,
+                               const ir::Layout org_layout = ir::Layout::UNKNOWN,
+                               const ir::Layout acl_layout = ir::Layout::UNKNOWN)
+{
+  // rank upto 4 is supported
+  assert(rank <= 4);
+  assert(runtime_pv.size() > 0);
+
+  int new_pv[4] = {0};
+  ::arm_compute::Coordinates axises = getARMComputeAxises(rank, org_layout, acl_layout);
+
+  for (uint32_t i = 0; i < rank; ++i)
+  {
+    new_pv[axises[i]] = ToARMComputeAxis(rank, runtime_pv[i], org_layout, acl_layout).value();
+  }
+
+  ::arm_compute::PermutationVector ACL_PV =
+      ::arm_compute::PermutationVector{new_pv[0], new_pv[1], new_pv[2], new_pv[3]};
+  ACL_PV.set_num_dimensions(rank);
+
+  return ACL_PV;
+}
+
+template <typename T>
+inline T ReorderBits(T in, size_t numOfBits, const ir::Layout org_layout = ir::Layout::UNKNOWN,
+                     const ir::Layout acl_layout = ir::Layout::UNKNOWN)
+{
+  assert(numOfBits > 0);
+  T out = 0;
+  for (int32_t i = numOfBits - 1; i >= 0; --i)
+  {
+    const uint32_t toShift =
+        numOfBits - ToARMComputeAxis(numOfBits, i, org_layout, acl_layout).value() - 1;
+    out += ((in & 1) << toShift);
+    in >>= 1;
+  }
+  return out;
+}
+
+} // namespace acl_common
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ACL_COMMON_SWIZZLE_H__
diff --git a/runtime/neurun/backend/acl_common/TemplTensorBuilder.h b/runtime/neurun/backend/acl_common/TemplTensorBuilder.h
new file mode 100644
index 000000000..bb43823ed
--- /dev/null
+++ b/runtime/neurun/backend/acl_common/TemplTensorBuilder.h
@@ -0,0 +1,612 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ACL_COMMON_TEMPL_TENSOR_BUILDER_H__
+#define __NEURUN_BACKEND_ACL_COMMON_TEMPL_TENSOR_BUILDER_H__
+
+#include <memory>
+#include <queue>
+
+#include <arm_compute/core/Types.h>
+#include <backend/ITensorBuilder.h>
+#include "ir/OperandIndexMap.h"
+#include "AclTensorManager.h"
+#include "cpp14/memory.h"
+#include <util/Utils.h>
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_common
+{
+
+enum class UsesType
+{
+  FIRST,
+  LAST
+};
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+class TemplTensorBuilder : public ITensorBuilder
+{
+public:
+  using T_AclTensorManager = AclTensorManager<T_ITensor, T_Tensor, T_SubTensor>;
+
+  TemplTensorBuilder(T_AclTensorManager *tensor_mgr);
+
+  /**
+   * @brief     Register tensor information to allocate on ACL-CL backend
+   * @param[in] ind    Operand index
+   * @param[in] info   Tensor information
+   * @param[in] layout Tensor data layout
+   */
+  void registerTensorInfo(const ir::OperandIndex &ind, const ir::OperandInfo &info,
+                          ir::Layout backend_layout, bool as_const) override;
+  /**
+   * @brief     Register subtensor information to allocate on ACL-CL backend
+   * @param[in] ind   Operand index
+   * @param[in] info  Tensor information
+   */
+  void registerSubTensorInfo(const ir::OperandIndex &ind,
+                             const compiler::SubTensorInfo &info) override;
+
+  void notifyFirstUse(const ir::OperandIndex &) override;
+  void notifyLastUse(const ir::OperandIndex &) override;
+
+  bool isRegistered(const ir::OperandIndex &) const override;
+
+  void prepare(void) override;
+  void allocateConsts() override;
+  void allocateNonconsts() override;
+  void postFunctionPrepare() override;
+  void finalize() override;
+
+  std::shared_ptr<::neurun::backend::operand::ITensor>
+  tensorAt(const ir::OperandIndex &ind) override;
+  void iterate(const IterateFunction &fn) override;
+
+  void preVisit(const ir::Operation &node) override;
+  void postVisit(const ir::Operation &node) override;
+
+  std::unique_ptr<ITensorManager> releaseTensorManager(void) override;
+
+  std::shared_ptr<T_ITensor> at(const ir::OperandIndex &ind);
+  /**
+   * @brief     Check child tensor is allocated as subtensor of parent tensor
+   * @param[in] parent  Index of parent
+   * @param[in] child   Index of child
+   * @return    @c true if child is allocated as subtensor of parent, otherwise @c false
+   */
+  bool isSubTensorOf(const ir::OperandIndex &parent, const ir::OperandIndex &child);
+
+  void dimCorrection(const ir::OperandIndex &index, bool apply_dim_correction);
+
+  T_AclTensorManager *acl_tensor_manager(void) { return _tensor_mgr.get(); }
+
+  void setUsesCount(const ir::OperandIndex &index, size_t num_uses)
+  {
+    assert(_uses_count_map.find(index) != _uses_count_map.end() ? _uses_count_map[index] == num_uses
+                                                                : true);
+    _uses_count_map[index] = num_uses;
+  }
+
+private:
+  void buildTensors(void);
+  void buildSubtensors(void);
+  void validate(void);
+  ir::OperandIndex findRootParent(ir::OperandIndex index);
+
+private:
+  ir::OperandIndexMap<ir::OperandInfo> _tensor_info_map;
+  ir::OperandIndexMap<compiler::SubTensorInfo> _subtensor_info_map;
+  ir::OperandIndexMap<bool> _apply_dim_correction_map;
+  ir::OperandIndexMap<ir::Layout> _tensor_layout_map;
+  ir::OperandIndexMap<size_t> _uses_count_map;
+
+  std::unique_ptr<T_AclTensorManager> _tensor_mgr;
+  ir::OperandIndexSequence _constants;
+
+  // TODO Consider dividing TensorBuilder into Linear and others
+  const std::string _executor_str;
+
+  // for linear executor
+  std::queue<std::pair<UsesType, ir::OperandIndex>> _uses_queue;
+  uint32_t _first_uses_num;
+  ir::OperandIndexMap<bool> _first_uses_visit;
+
+  // for subtensors
+  ir::OperandIndexMap<uint32_t> _parent_def;
+  ir::OperandIndexMap<uint32_t> _parent_uses;
+};
+
+} // namespace acl_common
+} // namespace backend
+} // namespace neurun
+
+#include <cassert>
+#include <stack>
+
+#include "Convert.h"
+
+#include "util/logging.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_common
+{
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+TemplTensorBuilder<T_ITensor, T_Tensor, T_SubTensor>::TemplTensorBuilder(
+    T_AclTensorManager *tensor_mgr)
+    : _tensor_mgr{tensor_mgr}, _executor_str(util::getConfigString(util::config::EXECUTOR)),
+      _first_uses_num(0)
+{
+  assert(_tensor_mgr);
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+void TemplTensorBuilder<T_ITensor, T_Tensor, T_SubTensor>::registerTensorInfo(
+    const ir::OperandIndex &ind, const ir::OperandInfo &info, ir::Layout backend_layout,
+    bool as_const)
+{
+  assert(_tensor_mgr->constTensors().size() == 0);
+  assert(_tensor_mgr->nonconstTensors().size() == 0);
+
+  _tensor_info_map.emplace(ind, info);
+  _apply_dim_correction_map.emplace(ind, true);
+  _tensor_layout_map.insert({ind, backend_layout});
+  if (as_const)
+    _constants.append(ind);
+
+  assert(_first_uses_visit.find(ind) == _first_uses_visit.end());
+  _first_uses_visit[ind] = false;
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+void TemplTensorBuilder<T_ITensor, T_Tensor, T_SubTensor>::registerSubTensorInfo(
+    const ir::OperandIndex &ind, const compiler::SubTensorInfo &info)
+{
+  assert(_tensor_mgr->constTensors().size() == 0);
+  assert(_tensor_mgr->nonconstTensors().size() == 0);
+
+  _subtensor_info_map.emplace(ind, info);
+  _apply_dim_correction_map.emplace(ind, true);
+
+  assert(_first_uses_visit.find(ind) == _first_uses_visit.end());
+  _first_uses_visit[ind] = false;
+
+  const auto &parent_ind = info.parent();
+
+  // parent_def
+  _parent_def[parent_ind] = 1;
+
+  // parent_use
+  if (_parent_uses.find(parent_ind) == _parent_uses.end())
+    _parent_uses[parent_ind] = 1; // 1 means including parent it-self
+  _parent_uses[parent_ind]++;
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+void TemplTensorBuilder<T_ITensor, T_Tensor, T_SubTensor>::notifyFirstUse(
+    const ir::OperandIndex &ind)
+{
+  _first_uses_num++;
+  _uses_queue.emplace(UsesType::FIRST, ind);
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+void TemplTensorBuilder<T_ITensor, T_Tensor, T_SubTensor>::notifyLastUse(
+    const ir::OperandIndex &ind)
+{
+  _uses_queue.emplace(UsesType::LAST, ind);
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+bool TemplTensorBuilder<T_ITensor, T_Tensor, T_SubTensor>::isRegistered(
+    const ir::OperandIndex &ind) const
+{
+  return _tensor_info_map.find(ind) != _tensor_info_map.end() ||
+         _subtensor_info_map.find(ind) != _subtensor_info_map.end();
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+void TemplTensorBuilder<T_ITensor, T_Tensor, T_SubTensor>::prepare(void)
+{
+  buildTensors();
+  buildSubtensors();
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+void TemplTensorBuilder<T_ITensor, T_Tensor, T_SubTensor>::allocateConsts(void)
+{
+  assert(_constants.size() == _tensor_mgr->constTensors().size());
+  _tensor_mgr->allocateConsts();
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+void TemplTensorBuilder<T_ITensor, T_Tensor, T_SubTensor>::allocateNonconsts(void)
+{
+  assert(_tensor_info_map.size() == _tensor_mgr->nonconstTensors().size() + _constants.size());
+  _tensor_mgr->allocateNonconsts();
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+void TemplTensorBuilder<T_ITensor, T_Tensor, T_SubTensor>::postFunctionPrepare(void)
+{
+  _tensor_mgr->tryDeallocConstants();
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+void TemplTensorBuilder<T_ITensor, T_Tensor, T_SubTensor>::finalize(void)
+{
+  validate();
+  _tensor_mgr->allocateInternalBufferManager();
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+std::shared_ptr<::neurun::backend::operand::ITensor>
+TemplTensorBuilder<T_ITensor, T_Tensor, T_SubTensor>::tensorAt(const ir::OperandIndex &ind)
+{
+  return _tensor_mgr->at(ind);
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+void TemplTensorBuilder<T_ITensor, T_Tensor, T_SubTensor>::iterate(const IterateFunction &fn)
+{
+  _tensor_mgr->iterate(fn);
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+std::shared_ptr<T_ITensor>
+TemplTensorBuilder<T_ITensor, T_Tensor, T_SubTensor>::at(const ir::OperandIndex &ind)
+{
+  return _tensor_mgr->at(ind);
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+bool TemplTensorBuilder<T_ITensor, T_Tensor, T_SubTensor>::isSubTensorOf(
+    const ir::OperandIndex &parent, const ir::OperandIndex &child)
+{
+  if (_subtensor_info_map.find(child) == _subtensor_info_map.end())
+  {
+    return false;
+  }
+
+  auto &subtensors = _tensor_mgr->nonconstSubtensors();
+  if (subtensors.find(child) == subtensors.end())
+  {
+    return false;
+  }
+
+  if (_subtensor_info_map.at(child).parent() != parent)
+  {
+    return false;
+  }
+
+  return true;
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+void TemplTensorBuilder<T_ITensor, T_Tensor, T_SubTensor>::dimCorrection(
+    const ir::OperandIndex &index, bool apply_dim_correction)
+{
+  _apply_dim_correction_map[index] = apply_dim_correction;
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+std::unique_ptr<ITensorManager>
+TemplTensorBuilder<T_ITensor, T_Tensor, T_SubTensor>::releaseTensorManager(void)
+{
+  return std::move(_tensor_mgr);
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+void TemplTensorBuilder<T_ITensor, T_Tensor, T_SubTensor>::buildTensors(void)
+{
+  assert(_tensor_mgr->constTensors().size() == 0);
+  assert(_tensor_mgr->nonconstTensors().size() == 0);
+
+  for (auto &entry : _tensor_info_map)
+  {
+    auto ind = entry.first;
+    const auto &info = entry.second;
+    // NOTE SubTensor's layout must be the same with layout of parent tensor
+    const auto &root_parent = findRootParent(ind);
+    const auto &backend_layout = _tensor_layout_map[root_parent];
+    auto tensor_info = asTensorInfo(info.shape(), info.typeInfo(), ir::Layout::UNKNOWN,
+                                    backend_layout, _apply_dim_correction_map[ind]);
+    _tensor_mgr->buildTensor(ind, tensor_info, info.shape().rank(), _constants.contains(ind),
+                             _uses_count_map[ind]);
+  }
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+void TemplTensorBuilder<T_ITensor, T_Tensor, T_SubTensor>::buildSubtensors(void)
+{
+  // TODO Handle SubTensor(subsumption)
+  //      Currently this TemplTensorBuilder does not have subsumption info yet
+  //      Allocated subtensor will be mapped to _subtensors instead of _tensors
+  assert(_tensor_mgr->nonconstSubtensors().size() == 0);
+
+  // To make subtensor, parent tensor must be made first
+  // For this condition, use stack
+  //  1) Push one subtensor index to stack (iterate subtensors)
+  //  2) If tensor at stack top is already made, pop and go to 4)
+  //  3) If tensor pushed at 1) is not made, check parent tensor
+  //    3-1) If parent tensor is already made, we can make child tensor
+  //         Make child tensor and pop, go to 4)
+  //    3-2) If parent tensor is not made, we can't make child tensor yet
+  //         Push parent tensor index to stack and return to 4)
+  //  4) If stack is empty, return to 1), else return to 2)
+  auto &subtensors = _tensor_mgr->nonconstSubtensors();
+  for (auto &entry : _subtensor_info_map)
+  {
+    ir::OperandIndex ind = entry.first;
+
+    std::stack<ir::OperandIndex> stack;
+    stack.push(ind);
+
+    while (!stack.empty())
+    {
+      const auto current = stack.top();
+      const auto &info = _subtensor_info_map.at(current);
+
+      // Already generated SubTensor
+      if (subtensors.find(current) != subtensors.end())
+      {
+        stack.pop();
+        continue;
+      }
+
+      auto parent = info.parent();
+      std::shared_ptr<T_ITensor> parent_tensor = _tensor_mgr->findTensorAsParent(parent);
+      if (!parent_tensor)
+      {
+        // Cannot find allocated parent tensor: allocate parent first
+        assert(_subtensor_info_map.find(parent) != _subtensor_info_map.end());
+        stack.push(parent);
+        continue;
+      }
+      assert(parent_tensor != nullptr);
+
+      // Child's type should be same with parent
+      assert(info.type().offset() == parent_tensor->info()->quantization_info().offset);
+      assert(info.type().scale() == parent_tensor->info()->quantization_info().scale);
+      assert(asDataType(info.type().type()) == parent_tensor->info()->data_type());
+
+      // NOTE SubTensor's layout must be the same with layout of parent tensor
+      const auto &root_parent = findRootParent(parent);
+      const auto &backend_layout = _tensor_layout_map[root_parent];
+
+      auto shape = asTensorShape(info.shape(), ir::Layout::UNKNOWN, backend_layout,
+                                 _apply_dim_correction_map[current]);
+      ::arm_compute::Coordinates coordinates =
+          asTensorCoordinate(info.offset(), ir::Layout::UNKNOWN, backend_layout);
+      _tensor_mgr->buildSubtensor(parent, current, shape, coordinates, info.shape().rank(), true);
+      stack.pop();
+    }
+  }
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+void TemplTensorBuilder<T_ITensor, T_Tensor, T_SubTensor>::preVisit(const ir::Operation &node)
+{
+  // For now others executor doesn't need this step
+  if (_executor_str != "Linear")
+  {
+    return;
+  }
+
+  std::function<void(const ir::OperandIndex &ind)> def_handler =
+      [this, &def_handler](const ir::OperandIndex &ind) {
+        bool is_subtensor = _subtensor_info_map.find(ind) != _subtensor_info_map.end();
+        bool is_parent = _parent_def.find(ind) != _parent_def.end();
+        if (!is_subtensor && !is_parent)
+        {
+          _tensor_mgr->startLifetime(ind);
+          return;
+        }
+
+        if (is_parent)
+        {
+          if (_parent_def[ind] == 0)
+            return;
+
+          _parent_def[ind] = 0;
+
+          if (is_subtensor)
+          {
+            const auto &it = _parent_def.find(ind);
+            _parent_def.erase(it);
+            def_handler(ind);
+          }
+          else
+          {
+            _tensor_mgr->startLifetime(ind);
+          }
+        }
+        else if (is_subtensor)
+        {
+          const ir::OperandIndex &parent_ind = _subtensor_info_map.at(ind).parent();
+          if (_parent_def[parent_ind] == 0)
+            return;
+          def_handler(parent_ind);
+        }
+      };
+
+  // See #5642
+  ir::OperandIndexMap<bool> outputs_map;
+  for (const auto &ind : node.getOutputs())
+  {
+    assert(_first_uses_visit.find(ind) != _first_uses_visit.end());
+    outputs_map[ind] = _first_uses_visit[ind];
+  }
+
+  // outputs_map's all elements are true?
+  auto outputs_map_all_check = [&outputs_map]() {
+    return std::all_of(outputs_map.begin(), outputs_map.end(),
+                       [](std::pair<const ir::OperandIndex, bool> it) { return it.second; });
+  };
+
+  std::pair<UsesType, ir::OperandIndex> peak;
+  while (!outputs_map_all_check() && (peak = _uses_queue.front()).first == UsesType::FIRST)
+  {
+    _uses_queue.pop();
+    _first_uses_num--;
+
+    const auto &popped_idx = peak.second;
+    def_handler(popped_idx);
+
+    outputs_map[popped_idx] = true;
+    _first_uses_visit[popped_idx] = true;
+  }
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+void TemplTensorBuilder<T_ITensor, T_Tensor, T_SubTensor>::postVisit(const ir::Operation &node)
+{
+  // For now others executor doesn't need this step
+  if (_executor_str != "Linear")
+  {
+    return;
+  }
+
+  std::function<void(const ir::OperandIndex &ind)> use_handler =
+      [this, &use_handler](const ir::OperandIndex &ind) {
+        bool is_subtensor = _subtensor_info_map.find(ind) != _subtensor_info_map.end();
+        bool is_parent = _parent_uses.find(ind) != _parent_uses.end();
+        if (!is_subtensor && !is_parent)
+        {
+          _tensor_mgr->finishLifetime(ind);
+          return;
+        }
+
+        // This handler shall be executed by the linear executor so that
+        // The parent operand will always be done after the subtensor
+        if (is_parent)
+        {
+          --_parent_uses[ind];
+          assert(_parent_uses[ind] == 0);
+
+          if (is_subtensor)
+          {
+            const auto &it = _parent_uses.find(ind);
+            _parent_uses.erase(it);
+            use_handler(ind);
+          }
+          else
+          {
+            _tensor_mgr->finishLifetime(ind);
+          }
+        }
+        else if (is_subtensor)
+        {
+          const ir::OperandIndex &parent_ind = _subtensor_info_map.at(ind).parent();
+          --_parent_uses[parent_ind];
+          assert(_parent_uses[parent_ind] > 0);
+        }
+      };
+
+  // See #5642
+  const auto &inputs = node.getInputs();
+  std::pair<UsesType, ir::OperandIndex> peak;
+  while ((peak = _uses_queue.front()).first == UsesType::LAST)
+  {
+    const auto &popped_idx = peak.second;
+    if (inputs.contains(popped_idx))
+    {
+      _uses_queue.pop();
+      use_handler(popped_idx);
+    }
+    else
+    {
+      break;
+    }
+  }
+
+  if (_first_uses_num == 0)
+  {
+    while (!_uses_queue.empty())
+    {
+      peak = _uses_queue.front();
+      assert(peak.first == UsesType::LAST);
+
+      _uses_queue.pop();
+
+      use_handler(peak.second);
+    }
+  }
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+void TemplTensorBuilder<T_ITensor, T_Tensor, T_SubTensor>::validate(void)
+{
+  // For now others executor doesn't need this step
+  if (_executor_str != "Linear")
+  {
+    return;
+  }
+
+  for (auto it : _tensor_info_map)
+  {
+    assert(_first_uses_visit.find(it.first) != _first_uses_visit.end());
+    assert(_first_uses_visit[it.first]);
+  }
+
+  for (auto it : _subtensor_info_map)
+  {
+    assert(_first_uses_visit.find(it.first) != _first_uses_visit.end());
+    assert(_first_uses_visit[it.first]);
+  }
+
+  for (auto it : _tensor_layout_map)
+  {
+    assert(_first_uses_visit.find(it.first) != _first_uses_visit.end());
+    assert(_first_uses_visit[it.first]);
+    UNUSED_RELEASE(it);
+  }
+
+  assert(_uses_queue.size() == 0);
+  assert(_first_uses_num == 0);
+
+  assert(
+      std::all_of(_parent_def.begin(), _parent_def.end(),
+                  [](std::pair<const ir::OperandIndex, uint32_t> it) { return it.second == 0; }));
+
+  assert(
+      std::all_of(_parent_uses.begin(), _parent_uses.end(),
+                  [](std::pair<const ir::OperandIndex, uint32_t> it) { return it.second == 0; }));
+}
+
+template <typename T_ITensor, typename T_Tensor, typename T_SubTensor>
+ir::OperandIndex
+TemplTensorBuilder<T_ITensor, T_Tensor, T_SubTensor>::findRootParent(ir::OperandIndex ind)
+{
+  if (_subtensor_info_map.find(ind) == _subtensor_info_map.end())
+    return ind;
+
+  const auto &parent_ind = _subtensor_info_map.at(ind).parent();
+  return findRootParent(parent_ind);
+}
+
+} // namespace acl_common
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ACL_COMMON_TEMPL_TENSOR_BUILDER_H__
diff --git a/runtime/neurun/backend/acl_neon/Backend.h b/runtime/neurun/backend/acl_neon/Backend.h
new file mode 100644
index 000000000..2fcf66933
--- /dev/null
+++ b/runtime/neurun/backend/acl_neon/Backend.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ACL_NEON_BACKEND_H__
+#define __NEURUN_BACKEND_ACL_NEON_BACKEND_H__
+
+#include <memory>
+#include <backend/Backend.h>
+#include <ir/Operands.h>
+
+#include "Config.h"
+#include "ConstantInitializer.h"
+#include "KernelGenerator.h"
+#include "ShapeFixer.h"
+#include "TensorManager.h"
+#include "TensorRegister.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_neon
+{
+
+class Backend : public ::neurun::backend::Backend
+{
+public:
+  Backend() : _config{std::make_shared<Config>()} {}
+
+  std::shared_ptr<IConfig> config() const override { return _config; }
+
+  std::unique_ptr<BackendContext>
+  newContext(const ir::Operands &operands,
+             const std::shared_ptr<custom::IKernelBuilder> &) const override
+  {
+    auto tensor_builder = std::make_shared<TensorBuilder>(createTensorManager());
+    return std::unique_ptr<BackendContext>{new BackendContext{
+        this, tensor_builder, std::make_shared<ConstantInitializer>(operands, tensor_builder),
+        std::make_shared<KernelGenerator>(operands, tensor_builder),
+        std::make_shared<ShapeFixer>(operands, tensor_builder),
+        std::make_shared<TensorRegister>(operands, tensor_builder)}};
+  }
+
+private:
+  std::shared_ptr<IConfig> _config;
+};
+
+} // namespace acl_neon
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ACL_NEON_BACKEND_H__
diff --git a/runtime/neurun/backend/acl_neon/CMakeLists.txt b/runtime/neurun/backend/acl_neon/CMakeLists.txt
new file mode 100644
index 000000000..061246d36
--- /dev/null
+++ b/runtime/neurun/backend/acl_neon/CMakeLists.txt
@@ -0,0 +1,21 @@
+# Unsupported architecture
+nnas_find_package(ARMCompute QUIET)
+if(NOT ARMCompute_FOUND)
+  return()
+endif(NOT ARMCompute_FOUND)
+
+set(LIB_NEURUN_BACKEND_ACL_NEON neurun_backend_acl_neon)
+
+file(GLOB_RECURSE SOURCES "*.cc")
+
+add_library(${LIB_NEURUN_BACKEND_ACL_NEON} SHARED ${SOURCES})
+
+target_include_directories(${LIB_NEURUN_BACKEND_ACL_NEON} PRIVATE ${CMAKE_CURRENT_SOURCE_DIR})
+target_link_libraries(${LIB_NEURUN_BACKEND_ACL_NEON} PRIVATE neurun_core)
+target_link_libraries(${LIB_NEURUN_BACKEND_ACL_NEON} PRIVATE ${LIB_NEURUN_BACKEND_ACL_COMMON})
+target_link_libraries(${LIB_NEURUN_BACKEND_ACL_NEON} PRIVATE nnfw_common)
+target_link_libraries(${LIB_NEURUN_BACKEND_ACL_NEON} PRIVATE nnfw_coverage)
+
+set_target_properties(${LIB_NEURUN_BACKEND_ACL_NEON} PROPERTIES OUTPUT_NAME backend_acl_neon)
+
+install(TARGETS ${LIB_NEURUN_BACKEND_ACL_NEON} DESTINATION lib)
diff --git a/runtime/neurun/backend/acl_neon/Config.cc b/runtime/neurun/backend/acl_neon/Config.cc
new file mode 100644
index 000000000..352bc0b41
--- /dev/null
+++ b/runtime/neurun/backend/acl_neon/Config.cc
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "Config.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_neon
+{
+
+bool Config::initialize() { return true; }
+
+} // namespace acl_neon
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/acl_neon/Config.h b/runtime/neurun/backend/acl_neon/Config.h
new file mode 100644
index 000000000..430c194ee
--- /dev/null
+++ b/runtime/neurun/backend/acl_neon/Config.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ACL_NEON_CONFIG_H__
+#define __NEURUN_BACKEND_ACL_NEON_CONFIG_H__
+
+#include <backend/IConfig.h>
+#include <cpp14/memory.h>
+#include <util/ITimer.h>
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_neon
+{
+
+class Config : public IConfig
+{
+public:
+  std::string id() override { return "acl_neon"; }
+  bool initialize() override;
+  bool SupportPermutation() override { return true; }
+  bool SupportSubTensorAlloc() override { return true; }
+
+  std::unique_ptr<util::ITimer> timer() override
+  {
+    return nnfw::cpp14::make_unique<util::CPUTimer>();
+  }
+};
+
+} // namespace acl_neon
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ACL_NEON_CONFIG_H__
diff --git a/runtime/neurun/backend/acl_neon/ConstantInitializer.cc b/runtime/neurun/backend/acl_neon/ConstantInitializer.cc
new file mode 100644
index 000000000..9a74bda29
--- /dev/null
+++ b/runtime/neurun/backend/acl_neon/ConstantInitializer.cc
@@ -0,0 +1,246 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ConstantInitializer.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_neon
+{
+
+ConstantInitializer::ConstantInitializer(const ir::Operands &operands,
+                                         const std::shared_ptr<TensorBuilder> &tensor_builder)
+    : _operands{operands}, _tensor_builder{tensor_builder}
+{
+  // DO NOTHING
+}
+
+void ConstantInitializer::visit(const ir::operation::BatchToSpaceND &node)
+{
+  const auto &block_size_index = node.getInputs().at(ir::operation::BatchToSpaceND::BLOCK_SIZE);
+  const auto &block_size_obj = _operands.at(block_size_index);
+
+  if (block_size_obj.isConstant())
+  {
+    _init_map[block_size_index] = [](const ir::Operand &model_obj, backend::operand::ITensor &obj) {
+      const auto &shape = model_obj.shape();
+      const auto base = reinterpret_cast<const int32_t *>(model_obj.data().base());
+      assert(model_obj.shape().rank() == 1);
+      obj.access([&](::neurun::backend::operand::ITensor &tensor) {
+        for (size_t i = 0; i < shape.num_elements(); ++i)
+        {
+          const int32_t value = base[shape.num_elements() - i - 1];
+          int32_t *into = reinterpret_cast<int32_t *>(tensor.buffer() +
+                                                      tensor.calcOffset({static_cast<int32_t>(i)}));
+          *into = value;
+        }
+      });
+    };
+  }
+}
+
+void ConstantInitializer::visit(const ir::operation::Conv2D &node)
+{
+  const auto &kernel_index = node.getInputs().at(ir::operation::Conv2D::KERNEL);
+  const auto &kernel_obj = _operands.at(kernel_index);
+  registerPermuteInitializer(kernel_index, kernel_obj);
+
+  const auto &bias_index = node.getInputs().at(ir::operation::Conv2D::BIAS);
+  const auto &bias_obj = _operands.at(bias_index);
+  registerCopyInitializer(bias_index, bias_obj);
+}
+
+void ConstantInitializer::visit(const ir::operation::DepthwiseConv2D &node)
+{
+  const auto &kernel_index = node.getInputs().at(ir::operation::DepthwiseConv2D::KERNEL);
+  const auto &kernel_obj = _operands.at(kernel_index);
+  registerPermuteInitializer(kernel_index, kernel_obj);
+
+  const auto &bias_index = node.getInputs().at(ir::operation::DepthwiseConv2D::BIAS);
+  const auto &bias_obj = _operands.at(bias_index);
+  registerCopyInitializer(bias_index, bias_obj);
+}
+
+void ConstantInitializer::visit(const ir::operation::FullyConnected &node)
+{
+  const auto &weight_index = node.getInputs().at(ir::operation::FullyConnected::WEIGHT);
+  const auto &weight_obj = _operands.at(weight_index);
+  registerCopyInitializer(weight_index, weight_obj);
+
+  const auto &bias_index = node.getInputs().at(ir::operation::FullyConnected::BIAS);
+  const auto &bias_obj = _operands.at(bias_index);
+  registerCopyInitializer(bias_index, bias_obj);
+}
+
+void ConstantInitializer::visit(const ir::operation::LSTM &node)
+{
+  const auto &input_to_input_weights_index =
+      node.getInputs().at(ir::operation::LSTM::INPUT_TO_INPUT_WEIGHTS);
+  const auto &input_to_input_weights_obj = _operands.at(input_to_input_weights_index);
+  registerCopyInitializer(input_to_input_weights_index, input_to_input_weights_obj);
+
+  const auto &input_to_forget_weights_index =
+      node.getInputs().at(ir::operation::LSTM::INPUT_TO_FORGET_WEIGHTS);
+  const auto &input_to_forget_weights_obj = _operands.at(input_to_forget_weights_index);
+  registerCopyInitializer(input_to_forget_weights_index, input_to_forget_weights_obj);
+
+  const auto &input_to_cell_weights_index =
+      node.getInputs().at(ir::operation::LSTM::INPUT_TO_CELL_WEIGHTS);
+  const auto &input_to_cell_weights_obj = _operands.at(input_to_cell_weights_index);
+  registerCopyInitializer(input_to_cell_weights_index, input_to_cell_weights_obj);
+
+  const auto &input_to_output_weights_index =
+      node.getInputs().at(ir::operation::LSTM::INPUT_TO_OUTPUT_WEIGHTS);
+  const auto &input_to_output_weights_obj = _operands.at(input_to_output_weights_index);
+  registerCopyInitializer(input_to_output_weights_index, input_to_output_weights_obj);
+
+  const auto &recurrent_to_input_weights_index =
+      node.getInputs().at(ir::operation::LSTM::RECURRENT_TO_INPUT_WEIGHTS);
+  const auto &recurrent_to_input_weights_obj = _operands.at(recurrent_to_input_weights_index);
+  registerCopyInitializer(recurrent_to_input_weights_index, recurrent_to_input_weights_obj);
+
+  const auto &recurrent_to_forget_weights_index =
+      node.getInputs().at(ir::operation::LSTM::RECURRENT_TO_FORGET_WEIGHTS);
+  const auto &recurrent_to_forget_weights_obj = _operands.at(recurrent_to_forget_weights_index);
+  registerCopyInitializer(recurrent_to_forget_weights_index, recurrent_to_forget_weights_obj);
+
+  const auto &recurrent_to_cell_weights_index =
+      node.getInputs().at(ir::operation::LSTM::RECURRENT_TO_CELL_WEIGHTS);
+  const auto &recurrent_to_cell_weights_obj = _operands.at(recurrent_to_cell_weights_index);
+  registerCopyInitializer(recurrent_to_cell_weights_index, recurrent_to_cell_weights_obj);
+
+  const auto &recurrent_to_output_weights_index =
+      node.getInputs().at(ir::operation::LSTM::RECURRENT_TO_OUTPUT_WEIGHTS);
+  const auto &recurrent_to_output_weights_obj = _operands.at(recurrent_to_output_weights_index);
+  registerCopyInitializer(recurrent_to_output_weights_index, recurrent_to_output_weights_obj);
+
+  const auto &cell_to_input_weights_index =
+      node.getInputs().at(ir::operation::LSTM::CELL_TO_INPUT_WEIGHTS);
+  const auto &cell_to_input_weights_obj = _operands.at(cell_to_input_weights_index);
+  registerCopyInitializer(cell_to_input_weights_index, cell_to_input_weights_obj);
+
+  const auto &cell_to_forget_weights_index =
+      node.getInputs().at(ir::operation::LSTM::CELL_TO_FORGET_WEIGHTS);
+  const auto &cell_to_forget_weights_obj = _operands.at(cell_to_forget_weights_index);
+  registerCopyInitializer(cell_to_forget_weights_index, cell_to_forget_weights_obj);
+
+  const auto &cell_to_output_weights_index =
+      node.getInputs().at(ir::operation::LSTM::CELL_TO_OUTPUT_WEIGHTS);
+  const auto &cell_to_output_weights_obj = _operands.at(cell_to_output_weights_index);
+  registerCopyInitializer(cell_to_output_weights_index, cell_to_output_weights_obj);
+
+  const auto &input_gate_bias_index = node.getInputs().at(ir::operation::LSTM::INPUT_GATE_BIAS);
+  const auto &input_gate_bias_obj = _operands.at(input_gate_bias_index);
+  registerCopyInitializer(input_gate_bias_index, input_gate_bias_obj);
+
+  const auto &forget_gate_bias_index = node.getInputs().at(ir::operation::LSTM::FORGET_GATE_BIAS);
+  const auto &forget_gate_bias_obj = _operands.at(forget_gate_bias_index);
+  registerCopyInitializer(forget_gate_bias_index, forget_gate_bias_obj);
+
+  const auto &output_gate_bias_index = node.getInputs().at(ir::operation::LSTM::OUTPUT_GATE_BIAS);
+  const auto &output_gate_bias_obj = _operands.at(output_gate_bias_index);
+  registerCopyInitializer(output_gate_bias_index, output_gate_bias_obj);
+
+  const auto &projection_weights_index =
+      node.getInputs().at(ir::operation::LSTM::PROJECTION_WEIGHTS);
+  const auto &projection_weights_obj = _operands.at(projection_weights_index);
+  registerCopyInitializer(projection_weights_index, projection_weights_obj);
+
+  const auto &projection_bias_index = node.getInputs().at(ir::operation::LSTM::PROJECTION_BIAS);
+  const auto &projection_bias_obj = _operands.at(projection_bias_index);
+  registerCopyInitializer(projection_bias_index, projection_bias_obj);
+}
+
+void ConstantInitializer::visit(const ir::operation::RNN &node)
+{
+  const auto &weights_index = node.getInputs().at(ir::operation::RNN::WEIGHTS);
+  const auto &weights_obj = _operands.at(weights_index);
+  registerCopyInitializer(weights_index, weights_obj);
+
+  const auto &recurrent_weights_index = node.getInputs().at(ir::operation::RNN::RECURRENT_WEIGHTS);
+  const auto &recurrent_weights_obj = _operands.at(recurrent_weights_index);
+  registerCopyInitializer(recurrent_weights_index, recurrent_weights_obj);
+
+  const auto &bias_index = node.getInputs().at(ir::operation::RNN::BIAS);
+  const auto &bias_obj = _operands.at(bias_index);
+  registerCopyInitializer(bias_index, bias_obj);
+}
+
+void ConstantInitializer::visit(const ir::operation::SpaceToBatchND &node)
+{
+  const auto &block_size_index = node.getInputs().at(ir::operation::SpaceToBatchND::BLOCK_SIZE);
+  const auto &block_size_obj = _operands.at(block_size_index);
+
+  if (block_size_obj.isConstant())
+  {
+    _init_map[block_size_index] = [](const ir::Operand &model_obj, backend::operand::ITensor &obj) {
+      const auto &shape = model_obj.shape();
+      const auto base = reinterpret_cast<const int32_t *>(model_obj.data().base());
+      assert(model_obj.shape().rank() == 1);
+      obj.access([&](::neurun::backend::operand::ITensor &tensor) {
+        for (size_t i = 0; i < shape.num_elements(); ++i)
+        {
+          const int32_t value = base[shape.num_elements() - i - 1];
+          int32_t *into = reinterpret_cast<int32_t *>(tensor.buffer() +
+                                                      tensor.calcOffset({static_cast<int32_t>(i)}));
+          *into = value;
+        }
+      });
+    };
+  }
+
+  const auto &paddings_index = node.getInputs().at(ir::operation::SpaceToBatchND::PADDINGS);
+  const auto &paddings_obj = _operands.at(paddings_index);
+  if (paddings_obj.isConstant())
+  {
+    _init_map[paddings_index] = [](const ir::Operand &model_obj, backend::operand::ITensor &obj) {
+      const auto &shape = model_obj.shape();
+      const auto base = reinterpret_cast<const int32_t *>(model_obj.data().base());
+      assert(model_obj.shape().rank() == 2);
+      assert(shape.dim(0) == 2);
+      assert(shape.dim(1) == 2);
+      obj.access([&](::neurun::backend::operand::ITensor &tensor) {
+        for (auto i = 0; i < shape.dim(0); ++i)
+        {
+          for (auto j = 0; j < shape.dim(1); ++j)
+          {
+            const int32_t value = base[i * 2 + j];
+            int32_t *into = reinterpret_cast<int32_t *>(
+                // The coordinates of NETensor are different from the coordiantes of CLTensor in
+                // this operand.
+                // NEON : {j, reversed i}
+                // CL : {reversed i, j}
+                tensor.buffer() + tensor.calcOffset({j, shape.dim(0) - i - 1}));
+            *into = value;
+          }
+        }
+      });
+    };
+  }
+}
+
+void ConstantInitializer::visit(const ir::operation::TransposeConv &node)
+{
+  const auto &kernel_index = node.getInputs().at(ir::operation::TransposeConv::KERNEL);
+  const auto &kernel_obj = _operands.at(kernel_index);
+  registerPermuteInitializer(kernel_index, kernel_obj);
+}
+
+} // namespace acl_neon
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/acl_neon/ConstantInitializer.h b/runtime/neurun/backend/acl_neon/ConstantInitializer.h
new file mode 100644
index 000000000..0f2b2d05b
--- /dev/null
+++ b/runtime/neurun/backend/acl_neon/ConstantInitializer.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_COMPILER_ACL_NEON_CONSTANT_INITIALIZER_H__
+#define __NEURUN_COMPILER_ACL_NEON_CONSTANT_INITIALIZER_H__
+
+#include <backend/IConstantInitializer.h>
+#include <ir/Operands.h>
+#include "TensorBuilder.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_neon
+{
+
+class ConstantInitializer : public IConstantInitializer
+{
+public:
+  ConstantInitializer(const ir::Operands &operands,
+                      const std::shared_ptr<TensorBuilder> &tensor_builder);
+
+public:
+  void visit(const ir::operation::BatchToSpaceND &) override;
+  void visit(const ir::operation::Conv2D &) override;
+  void visit(const ir::operation::DepthwiseConv2D &) override;
+  void visit(const ir::operation::FullyConnected &) override;
+  void visit(const ir::operation::LSTM &) override;
+  void visit(const ir::operation::RNN &) override;
+  void visit(const ir::operation::SpaceToBatchND &) override;
+  void visit(const ir::operation::TransposeConv &) override;
+
+private:
+  const ir::Operands &operands() const override { return _operands; }
+  std::shared_ptr<ITensorBuilder> tensor_builder() const override { return _tensor_builder; }
+
+private:
+  const ir::Operands &_operands;
+  std::shared_ptr<TensorBuilder> _tensor_builder;
+};
+
+} // namespace acl_neon
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_COMPILER_ACL_NEON_CONSTANT_INITIALIZER_H__
diff --git a/runtime/neurun/backend/acl_neon/KernelGenerator.cc b/runtime/neurun/backend/acl_neon/KernelGenerator.cc
new file mode 100644
index 000000000..85c6a0633
--- /dev/null
+++ b/runtime/neurun/backend/acl_neon/KernelGenerator.cc
@@ -0,0 +1,2152 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "KernelGenerator.h"
+
+#include <arm_compute/runtime/NEON/NEFunctions.h>   // Include all ARM Compute NEON functions
+#include <arm_compute/runtime/NEON/NEFunctionsEx.h> // Include all ARM Compute EX NEON functions
+
+#include <Convert.h>
+#include <Swizzle.h>
+
+#include "util/Padding.h"
+#include "ir/Index.h"
+#include "ir/DataType.h"
+#include "ir/InternalType.h"
+#include "compiler/IExecutionBuilder.h"
+#include "exec/NopFunction.h"
+#include "util/logging.h"
+#include "util/Utils.h"
+
+using ::neurun::compiler::IExecutionBuilder;
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_neon
+{
+
+using ::neurun::backend::acl_common::asAclFunction;
+
+//
+// ActivationBuilder
+//
+class ActivationBuilder
+{
+public:
+  ActivationBuilder(IExecutionBuilder &builder) : _builder(builder)
+  {
+    // DO NOTHING
+  }
+
+private:
+  void appendReLU(::arm_compute::ITensor *ifm_alloc);
+  void appendReLU1(::arm_compute::ITensor *ifm_alloc);
+  void appendReLU6(::arm_compute::ITensor *ifm_alloc);
+
+public:
+  void append(ir::Activation act, ::arm_compute::ITensor *ifm_alloc);
+
+private:
+  IExecutionBuilder &_builder;
+};
+
+void ActivationBuilder::appendReLU(::arm_compute::ITensor *ifm_alloc)
+{
+  const ::arm_compute::ActivationLayerInfo act_info{
+      ::arm_compute::ActivationLayerInfo::ActivationFunction::RELU};
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEActivationLayer>();
+
+  fn->configure(ifm_alloc, nullptr, act_info);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _builder.append(std::move(acl_fn));
+}
+
+void ActivationBuilder::appendReLU1(::arm_compute::ITensor *ifm_alloc)
+{
+  const ::arm_compute::ActivationLayerInfo act_info{
+      ::arm_compute::ActivationLayerInfo::ActivationFunction::LU_BOUNDED_RELU, 1.0f, -1.0f};
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEActivationLayer>();
+
+  fn->configure(ifm_alloc, nullptr, act_info);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _builder.append(std::move(acl_fn));
+}
+
+void ActivationBuilder::appendReLU6(::arm_compute::ITensor *ifm_alloc)
+{
+  const ::arm_compute::ActivationLayerInfo act_info{
+      ::arm_compute::ActivationLayerInfo::ActivationFunction::LU_BOUNDED_RELU, 6.0f, 0.0f};
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEActivationLayer>();
+
+  fn->configure(ifm_alloc, nullptr, act_info);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _builder.append(std::move(acl_fn));
+}
+
+void ActivationBuilder::append(ir::Activation act, ::arm_compute::ITensor *ifm_alloc)
+{
+  switch (act)
+  {
+    case ir::Activation::NONE:
+    {
+      // DO NOTHING
+      break;
+    }
+    case ir::Activation::RELU:
+    {
+      appendReLU(ifm_alloc);
+      break;
+    }
+    case ir::Activation::RELU1:
+    {
+      appendReLU1(ifm_alloc);
+      break;
+    }
+    case ir::Activation::RELU6:
+    {
+      appendReLU6(ifm_alloc);
+      break;
+    }
+    default:
+    {
+      throw std::runtime_error("Not supported, yet");
+    }
+  }
+}
+
+//
+// KernelGenerator
+//
+KernelGenerator::KernelGenerator(const ir::Operands &ctx,
+                                 const std::shared_ptr<TensorBuilder> &tensor_builder)
+    : _ctx(ctx), _tensor_builder(tensor_builder), _current_subg_layout(ir::Layout::UNKNOWN)
+{
+  // DO NOTHING
+}
+
+void KernelGenerator::visit(const ir::OpSequence &op_seq)
+{
+  _current_subg_layout = op_seq.getLayout();
+  for (const auto &e : op_seq.operations())
+  {
+    const auto &node = *(e.node);
+    _tensor_builder->preVisit(node);
+    node.accept(*this);
+    _tensor_builder->postVisit(node);
+  }
+}
+
+void KernelGenerator::visit(const ir::operation::Abs &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::Abs::Input::INPUT)};
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input_alloc = _tensor_builder->at(input_index).get();
+
+  const ::arm_compute::ActivationLayerInfo act_info{
+      ::arm_compute::ActivationLayerInfo::ActivationFunction::ABS};
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEActivationLayer>();
+
+  fn->configure(input_alloc->handle(), output_alloc->handle(), act_info);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::ArgMax &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::ArgMax::Input::INPUT)};
+
+  const auto ifm_rank = node.param().rank;
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+  auto frontend_layout = _current_subg_layout;
+  auto backend_layout = ifm_alloc->layout();
+
+  int axis_value = node.param().axis;
+  if (axis_value < 0)
+  {
+    axis_value += ifm_rank;
+  }
+  assert(axis_value >= 0 && axis_value < ifm_rank);
+  const auto fixed_axis =
+      acl_common::ToARMComputeAxis(ifm_rank, axis_value, frontend_layout, backend_layout).value();
+
+  // auto fn = nnfw::cpp14::make_unique<::arm_compute::NEArgMinMaxLayer>();
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEArgMax>();
+
+  // NOTE
+  // if (ofm_alloc->info()->data_type() == arm_compute::DataType::S32)
+  //{
+  ofm_alloc->info()->set_data_type(arm_compute::DataType::U32);
+  //}
+  fn->configure(ifm_alloc->handle(), fixed_axis, ofm_alloc->handle());
+  // fn->configure(ifm_alloc->handle(), fixed_axis, ofm_alloc->handle(),
+  // arm_compute::ReductionOperation::ARG_IDX_MAX);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::BatchToSpaceND &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::BatchToSpaceND::Input::INPUT)};
+  const auto block_size_index{
+      node.getInputs().at(ir::operation::BatchToSpaceND::Input::BLOCK_SIZE)};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+  auto block_size_alloc = _tensor_builder->at(block_size_index).get();
+
+  assert(_ctx.at(block_size_index).isConstant());
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEBatchToSpaceLayer>();
+
+  fn->configure(ifm_alloc->handle(), block_size_alloc->handle(), ofm_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Cast &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::Cast::Input::INPUT)};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NECast>();
+
+  auto input_sub_type = _ctx.at(ifm_index).typeInfo().type() == ir::DataType::BOOL8
+                            ? arm_compute::SubDataType::BOOL
+                            : arm_compute::SubDataType::NONE;
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle(), input_sub_type);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Conv2D &node)
+{
+  using ir::operation::Conv2D;
+
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(Conv2D::Input::INPUT)};
+  const auto ker_index{node.getInputs().at(Conv2D::Input::KERNEL)};
+  const auto bias_index{node.getInputs().at(Conv2D::Input::BIAS)};
+
+  const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature(_current_subg_layout);
+  const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature(_current_subg_layout);
+  // Kernel format is [depth_out, kernel_height, kernel_width, depth_in].
+  const auto &ker_shape = _ctx.at(ker_index).shape();
+  const auto ker_height = ker_shape.dim(1);
+  const auto ker_width = ker_shape.dim(2);
+
+  const auto stride = node.param().stride;
+  const auto padding = neurun::util::calculatePadding(node.param().padding, ifm_shape, ofm_shape,
+                                                      stride, ker_width, ker_height);
+  const auto activation = node.param().activation;
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+  auto ker_alloc = _tensor_builder->at(ker_index).get();
+  auto bias_alloc = _tensor_builder->at(bias_index).get();
+
+  const auto conv_info = acl_common::asPadStrideInfo(padding, stride);
+  const auto act_info = acl_common::asActivationLayerInfo(activation);
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEConvolutionLayer>(
+      _tensor_builder->acl_tensor_manager()->internal_buffer_manager());
+
+  fn->configure(ifm_alloc->handle(), ker_alloc->handle(), bias_alloc->handle(), ofm_alloc->handle(),
+                conv_info, ::arm_compute::WeightsInfo(), ::arm_compute::Size2D(1U, 1U), act_info);
+
+  _execution_builder->append(asAclFunction(std::move(fn)));
+}
+
+void KernelGenerator::visit(const ir::operation::DepthToSpace &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::DepthToSpace::Input::INPUT)};
+
+  auto block_size = node.param().block_size;
+  assert(block_size > 0);
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input_alloc = _tensor_builder->at(input_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEDepthToSpaceLayerEx>();
+
+  fn->configure(input_alloc->handle(), output_alloc->handle(), block_size);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::DepthwiseConv2D &node)
+{
+  using ir::operation::DepthwiseConv2D;
+
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(DepthwiseConv2D::Input::INPUT)};
+  const auto ker_index{node.getInputs().at(DepthwiseConv2D::Input::KERNEL)};
+  const auto bias_index{node.getInputs().at(DepthwiseConv2D::Input::BIAS)};
+
+  const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature(_current_subg_layout);
+  const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature(_current_subg_layout);
+  // Kernel format is [1, kernel_height, kernel_width, depth_out].
+  const auto &ker_shape = _ctx.at(ker_index).shape();
+  const auto ker_height = ker_shape.dim(1);
+  const auto ker_width = ker_shape.dim(2);
+
+  const auto stride = node.param().stride;
+  const auto padding = neurun::util::calculatePadding(node.param().padding, ifm_shape, ofm_shape,
+                                                      stride, ker_width, ker_height);
+  const auto multiplier = node.param().multiplier;
+  const auto activation = node.param().activation;
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+  auto ker_alloc = _tensor_builder->at(ker_index).get();
+  auto bias_alloc = _tensor_builder->at(bias_index).get();
+
+  const auto conv_info = acl_common::asPadStrideInfo(padding, stride);
+  const auto act_info = acl_common::asActivationLayerInfo(activation);
+
+  if (ker_height == 3 && ker_width == 3)
+  {
+    auto fn = nnfw::cpp14::make_unique<::arm_compute::NEDepthwiseConvolutionLayer3x3>();
+
+    fn->configure(ifm_alloc->handle(), ker_alloc->handle(), bias_alloc->handle(),
+                  ofm_alloc->handle(), conv_info, multiplier, act_info);
+
+    _execution_builder->append(asAclFunction(std::move(fn)));
+  }
+  else
+  {
+    auto fn = nnfw::cpp14::make_unique<::arm_compute::NEDepthwiseConvolutionLayer>();
+
+    fn->configure(ifm_alloc->handle(), ker_alloc->handle(), bias_alloc->handle(),
+                  ofm_alloc->handle(), conv_info, multiplier, act_info);
+
+    _execution_builder->append(asAclFunction(std::move(fn)));
+  }
+}
+
+void KernelGenerator::visit(const ir::operation::Dequantize &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::Dequantize::Input::INPUT)};
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input_alloc = _tensor_builder->at(input_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEDequantizationLayer>();
+
+  fn->configure(input_alloc->handle(), output_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::MaxPool2D &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::MaxPool2D::Input::INPUT)};
+
+  const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature(_current_subg_layout);
+  const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature(_current_subg_layout);
+
+  const auto kh = node.param().kh;
+  const auto kw = node.param().kw;
+  const auto stride = node.param().stride;
+  const auto padding =
+      neurun::util::calculatePadding(node.param().padding, ifm_shape, ofm_shape, stride, kw, kh);
+  const auto activation = node.param().activation;
+
+  VERBOSE(MaxPool2D) << "IFM_H: " << ifm_shape.H << std::endl;
+  VERBOSE(MaxPool2D) << "IFM_W: " << ifm_shape.W << std::endl;
+  VERBOSE(MaxPool2D) << "OFM_H: " << ofm_shape.H << std::endl;
+  VERBOSE(MaxPool2D) << "OFM_W: " << ofm_shape.W << std::endl;
+  VERBOSE(MaxPool2D) << "KER_H: " << kh << std::endl;
+  VERBOSE(MaxPool2D) << "KER_W: " << kw << std::endl;
+  VERBOSE(MaxPool2D) << "STRIDE_H: " << stride.vertical << std::endl;
+  VERBOSE(MaxPool2D) << "STRIDE_W: " << stride.horizontal << std::endl;
+  VERBOSE(MaxPool2D) << "PAD(T): " << padding.top << std::endl;
+  VERBOSE(MaxPool2D) << "PAD(B): " << padding.bottom << std::endl;
+  VERBOSE(MaxPool2D) << "PAD(L): " << padding.left << std::endl;
+  VERBOSE(MaxPool2D) << "PAD(R): " << padding.right << std::endl;
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+
+  ::arm_compute::PoolingLayerInfo info{::arm_compute::PoolingType::MAX,
+                                       ::arm_compute::Size2D{kw, kh},
+                                       acl_common::asPadStrideInfo(padding, stride)};
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEPoolingLayer>();
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle(), info);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append((std::move(acl_fn)));
+
+  ActivationBuilder{*_execution_builder}.append(activation, ofm_alloc->handle());
+}
+
+void KernelGenerator::visit(const ir::operation::Mean &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::Mean::Input::INPUT)};
+  const auto &axes{node.param().axes};
+  const auto keep_dims{node.param().keep_dims};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+  const auto frontend_layout = _current_subg_layout;
+  const auto backend_layout = ifm_alloc->layout();
+
+  // Convert to ACL axes taking into account negative values and possible duplicates.
+  std::set<std::uint32_t> acl_axes;
+  const int ifm_rank = node.param().rank;
+  for (int axis : axes)
+  {
+    if (axis < 0)
+      axis += ifm_rank;
+    acl_axes.insert(
+        acl_common::ToARMComputeAxis(ifm_rank, axis, frontend_layout, backend_layout).value());
+  }
+
+  arm_compute::Coordinates fixed_axis;
+  for (const auto axis : acl_axes)
+  {
+    fixed_axis.set(fixed_axis.num_dimensions(), axis);
+  }
+
+  // NOTE NEReduceMean has a bug that does not support NHWC layout
+  //      NEReduceMean intermediate tensors are always NCHW layout
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEReduceMeanEx>();
+
+  fn->configure(ifm_alloc->handle(), fixed_axis, keep_dims, ofm_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::AvgPool2D &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::AvgPool2D::Input::INPUT)};
+
+  const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature(_current_subg_layout);
+  const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature(_current_subg_layout);
+
+  const auto kh = node.param().kh;
+  const auto kw = node.param().kw;
+  const auto stride = node.param().stride;
+  const auto padding =
+      neurun::util::calculatePadding(node.param().padding, ifm_shape, ofm_shape, stride, kw, kh);
+  const auto activation = node.param().activation;
+
+  VERBOSE(AvgPool2D) << "IFM_H: " << ifm_shape.H << std::endl;
+  VERBOSE(AvgPool2D) << "IFM_W: " << ifm_shape.W << std::endl;
+  VERBOSE(AvgPool2D) << "OFM_H: " << ofm_shape.H << std::endl;
+  VERBOSE(AvgPool2D) << "OFM_W: " << ofm_shape.W << std::endl;
+  VERBOSE(AvgPool2D) << "KER_H: " << kh << std::endl;
+  VERBOSE(AvgPool2D) << "KER_W: " << kw << std::endl;
+  VERBOSE(AvgPool2D) << "STRIDE_H: " << stride.vertical << std::endl;
+  VERBOSE(AvgPool2D) << "STRIDE_W: " << stride.horizontal << std::endl;
+  VERBOSE(AvgPool2D) << "PAD(T): " << padding.top << std::endl;
+  VERBOSE(AvgPool2D) << "PAD(B): " << padding.bottom << std::endl;
+  VERBOSE(AvgPool2D) << "PAD(L): " << padding.left << std::endl;
+  VERBOSE(AvgPool2D) << "PAD(R): " << padding.right << std::endl;
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+
+  ::arm_compute::PoolingLayerInfo info{
+      ::arm_compute::PoolingType::AVG, ::arm_compute::Size2D{kw, kh},
+      acl_common::asPadStrideInfo(padding, stride), true /* exclude_padding */};
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEPoolingLayer>();
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle(), info);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append((std::move(acl_fn)));
+
+  ActivationBuilder{*_execution_builder}.append(activation, ofm_alloc->handle());
+}
+
+void KernelGenerator::visit(const ir::operation::Concat &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+
+  std::vector<ir::OperandIndex> input_indexes;
+  for (const auto &input : node.getInputs())
+    input_indexes.emplace_back(input);
+
+  const auto axis = node.param().axis;
+
+  // If tensor allocator allocate as subtensor
+  bool canEliminate = true;
+  for (auto ifm_ind : input_indexes)
+  {
+    if (!_tensor_builder->isSubTensorOf(ofm_index, ifm_ind))
+    {
+      canEliminate = false;
+      break;
+    }
+  }
+  if (canEliminate)
+  {
+    // If concat eliminated, return a NOP IFunction
+    _execution_builder->append(nnfw::cpp14::make_unique<exec::NopFunction>());
+    return;
+  }
+
+  auto output_alloc = _tensor_builder->at(ofm_index).get();
+  std::vector<::arm_compute::ITensor *> input_tensors;
+  for (const auto &ifm_ind : input_indexes)
+    input_tensors.emplace_back(_tensor_builder->at(ifm_ind)->handle());
+
+  std::unique_ptr<::arm_compute::IFunction> fn;
+  if (input_indexes.size() < 2)
+  {
+    auto l = nnfw::cpp14::make_unique<::arm_compute::NECopy>();
+    l->configure(input_tensors.at(0), output_alloc->handle());
+    fn = std::move(l);
+  }
+  else
+  {
+    auto l = nnfw::cpp14::make_unique<::arm_compute::NEConcatenateLayer>();
+    const auto rank = node.param().rank;
+    const auto frontend_layout = _current_subg_layout;
+    const auto backend_layout = output_alloc->layout();
+    const auto fixed_axis =
+        acl_common::ToARMComputeAxis(rank, axis, frontend_layout, backend_layout).value();
+    l->configure(input_tensors, output_alloc->handle(), fixed_axis);
+    fn = std::move(l);
+  }
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::EmbeddingLookup &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto lookups_index{node.getInputs().at(ir::operation::EmbeddingLookup::Input::LOOKUPS)};
+  const auto values_index{node.getInputs().at(ir::operation::EmbeddingLookup::Input::VALUES)};
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto lookups_alloc = _tensor_builder->at(lookups_index).get();
+  auto values_alloc = _tensor_builder->at(values_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEEmbeddingLookup>();
+
+  fn->configure(values_alloc->handle(), output_alloc->handle(), lookups_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Floor &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::Floor::Input::INPUT)};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEFloor>();
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::FullyConnected &node)
+{
+  using ir::operation::FullyConnected;
+
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(FullyConnected::Input::INPUT)};
+  const auto weight_index{node.getInputs().at(FullyConnected::Input::WEIGHT)};
+  const auto bias_index{node.getInputs().at(FullyConnected::Input::BIAS)};
+
+  const auto input_rank = _ctx.at(input_index).shape().rank();
+
+  const auto output_size =
+      _ctx.at(output_index).shape().dim(_ctx.at(output_index).shape().rank() - 1);
+  UNUSED_RELEASE(output_size);
+  assert(_ctx.at(bias_index).shape().dim(0) == output_size);
+  assert(_ctx.at(weight_index).shape().dim(0) == output_size);
+  const auto batch_size =
+      _ctx.at(output_index).shape().dim(_ctx.at(output_index).shape().rank() - 2);
+  const auto input_size =
+      _ctx.at(weight_index).shape().dim(_ctx.at(weight_index).shape().rank() - 1);
+
+  // Check for reshaping input's shape into rank-2
+  bool needs_reshape = false;
+  ir::Shape reshape(2);
+  if (input_rank == 3 || input_rank == 4)
+  {
+    const auto &ifm_shape = _ctx.at(input_index).shape();
+    auto feature_size = 1;
+    for (int i = 0; i < ifm_shape.rank(); ++i)
+    {
+      feature_size *= ifm_shape.dim(i);
+    }
+
+    UNUSED_RELEASE(feature_size);
+    assert(feature_size == batch_size * input_size);
+
+    // for reshaping
+    needs_reshape = true;
+    reshape.dim(0) = batch_size; /* H */
+    reshape.dim(1) = input_size; /* W */
+  }
+
+  const auto activation = node.param().activation;
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  const auto input_alloc = _tensor_builder->at(input_index).get();
+  const auto weight_alloc = _tensor_builder->at(weight_index).get();
+  const auto bias_alloc = _tensor_builder->at(bias_index).get();
+  const auto frontend_layout = _current_subg_layout;
+  const auto acl_layout = output_alloc->handle()->info()->data_layout();
+
+  auto fn = nnfw::cpp14::make_unique<arm_compute::NEFullyConnectedReshapingLayer>(
+      _tensor_builder->acl_tensor_manager()->internal_buffer_manager());
+
+  arm_compute::NEFullyConnectedReshapingLayer::KernelType kernel_type =
+      _ctx.at(weight_index).isConstant()
+          ? arm_compute::NEFullyConnectedReshapingLayer::KernelType::PREPROCESSED_WEIGHTS
+          : arm_compute::NEFullyConnectedReshapingLayer::KernelType::GENERAL;
+
+  fn->configure(
+      input_alloc->handle(), weight_alloc->handle(), bias_alloc->handle(), output_alloc->handle(),
+      needs_reshape,
+      ::neurun::backend::acl_common::asTensorShape(
+          reshape, frontend_layout, ::neurun::backend::acl_common::asRuntimeLayout(acl_layout)),
+      kernel_type);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+
+  ActivationBuilder{*_execution_builder}.append(activation, output_alloc->handle());
+}
+
+void KernelGenerator::visit(const ir::operation::HashtableLookup &node)
+{
+  const auto output_index{node.getOutputs().at(ir::operation::HashtableLookup::Output::OUTPUT)};
+  const auto hits_index{node.getOutputs().at(ir::operation::HashtableLookup::Output::HITS)};
+
+  const auto lookups_index{node.getInputs().at(ir::operation::HashtableLookup::Input::LOOKUPS)};
+  const auto keys_index{node.getInputs().at(ir::operation::HashtableLookup::Input::KEYS)};
+  const auto values_index{node.getInputs().at(ir::operation::HashtableLookup::Input::VALUES)};
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto hits_alloc = _tensor_builder->at(hits_index).get();
+
+  auto lookups_alloc = _tensor_builder->at(lookups_index).get();
+  auto keys_alloc = _tensor_builder->at(keys_index).get();
+  auto values_alloc = _tensor_builder->at(values_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEHashtableLookup>();
+
+  fn->configure(lookups_alloc->handle(), keys_alloc->handle(), values_alloc->handle(),
+                output_alloc->handle(), hits_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Gather &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+
+  const auto ifm_index{node.getInputs().at(ir::operation::Gather::Input::INPUT)};
+  const auto indices_index{node.getInputs().at(ir::operation::Gather::Input::INDICES)};
+
+  const auto ifm_shape = _ctx.at(ifm_index).shape();
+
+  const auto ifm_rank = node.param().rank;
+  const auto axis_raw = node.param().axis;
+  const auto axis_value = (axis_raw < 0 ? (ifm_rank + axis_raw) : axis_raw);
+  // Converting in reverse order
+  const int axis = ::neurun::backend::acl_common::ToARMComputeAxis(ifm_rank, axis_value).value();
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+  auto indices_alloc = _tensor_builder->at(indices_index).get();
+  const auto backend_layout = ofm_alloc->layout();
+  UNUSED_RELEASE(backend_layout);
+
+  // NOTE The frontend layout and backend layout must be the same for this operation.
+  //      If not the same, we have to add a stage(?) to perform permutation of output tensor. It
+  //      is not not efficient even if it works well. If so, it would be better to set the
+  //      layout of these backend tensors to the same layout.
+  //      There is also one thing we have to think about. This operation depends on the layout of
+  //      a model. For example, if a model in NHWC has this operation as output rank == 4, indices
+  //      rank == 2 and axis == 2, this operation should work as the axis W and C, but the axis W
+  //      and C are not sequential in NCHW. So the backend in NCHW cannot handle this case.
+  assert(backend_layout == ifm_alloc->layout());
+  assert(backend_layout == indices_alloc->layout());
+  assert(ifm_rank < 4 || _current_subg_layout == backend_layout);
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEGatherEx>();
+
+  fn->configure(ifm_alloc->handle(), indices_alloc->handle(), ofm_alloc->handle(), axis);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::InstanceNorm &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::InstanceNorm::Input::INPUT)};
+  const auto gamma_index{node.getInputs().at(ir::operation::InstanceNorm::Input::GAMMA)};
+  const auto beta_index{node.getInputs().at(ir::operation::InstanceNorm::Input::BETA)};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+  auto gamma_alloc = _tensor_builder->at(gamma_index).get();
+  auto beta_alloc = _tensor_builder->at(beta_index).get();
+  auto epsilon = node.param().epsilon;
+  auto activation = node.param().activation;
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEInstanceNormalizationLayerEx>();
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle(), gamma_alloc->handle(),
+                beta_alloc->handle(), epsilon);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+
+  ActivationBuilder{*_execution_builder}.append(activation, ofm_alloc->handle());
+}
+
+void KernelGenerator::visit(const ir::operation::L2Normalization &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::L2Normalization::Input::INPUT)};
+
+  // {CL|Neon}L2Normalization performs the reduction only along dimension 0
+  // L2 Normalization always performs the reduction along the depth axis
+  // Thus, we repurpose {CL|Neon}NormalizationLayers to act as depthwise L2 normalizations by
+  // choosing normalization parameters as below
+
+  const auto &ifm_shape = _ctx.at(ifm_index).shape();
+  // TODO Support optional constant dimension that normalization would be performed on
+  const auto normalization_axis = node.param().rank - 1;
+  int32_t radius =
+      2 * ifm_shape.dim(normalization_axis) + 1; // normSize = depth(last dimension) * 2 + 1
+  float alpha = 1.0f;                            // In the implementation to make alpha_ become 1
+  float beta = 0.5f;                             // pow(reduction, -0.5) = 1 / sqrt(reduction)
+  float bias = 0.0f;                             // Don't offset the reduction.
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+
+  const auto norm_info = ::arm_compute::NormalizationLayerInfo(::arm_compute::NormType::CROSS_MAP,
+                                                               radius, alpha, beta, bias, false);
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NENormalizationLayer>();
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle(), norm_info);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::L2Pool2D &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::L2Pool2D::Input::INPUT)};
+
+  const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature(_current_subg_layout);
+  const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature(_current_subg_layout);
+
+  uint32_t kw = node.param().kw;
+  uint32_t kh = node.param().kh;
+  const auto stride = node.param().stride;
+  const auto padding =
+      neurun::util::calculatePadding(node.param().padding, ifm_shape, ofm_shape, stride, kw, kh);
+  const auto activation = node.param().activation;
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+
+  ::arm_compute::PoolingLayerInfo info{
+      ::arm_compute::PoolingType::L2, ::arm_compute::Size2D{kw, kh},
+      ::neurun::backend::acl_common::asPadStrideInfo(padding, stride)};
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEPoolingLayer>();
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle(), info);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+
+  ActivationBuilder{*_execution_builder}.append(activation, ofm_alloc->handle());
+}
+
+void KernelGenerator::visit(const ir::operation::LocalResponseNormalization &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{
+      node.getInputs().at(ir::operation::LocalResponseNormalization::Input::INPUT)};
+
+  auto radius = node.param().radius;
+  auto alpha = node.param().alpha;
+  auto beta = node.param().beta;
+  auto bias = node.param().bias;
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+
+  const auto norm_info = ::arm_compute::NormalizationLayerInfo(
+      ::arm_compute::NormType::CROSS_MAP, radius * 2 + 1, alpha, beta, bias, false);
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NENormalizationLayer>();
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle(), norm_info);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::LogicalAnd &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input0_index{node.getInputs().at(ir::operation::LogicalAnd::Input::INPUT0)};
+  const auto input1_index{node.getInputs().at(ir::operation::LogicalAnd::Input::INPUT1)};
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input0_alloc = _tensor_builder->at(input0_index).get();
+  auto input1_alloc = _tensor_builder->at(input1_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NELogicalAnd>();
+
+  fn->configure(input0_alloc->handle(), input1_alloc->handle(), output_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::LogicalNot &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::LogicalNot::Input::INPUT)};
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input_alloc = _tensor_builder->at(input_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEBitwiseNot>();
+
+  fn->configure(input_alloc->handle(), output_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::LogicalOr &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input0_index{node.getInputs().at(ir::operation::LogicalOr::Input::INPUT0)};
+  const auto input1_index{node.getInputs().at(ir::operation::LogicalOr::Input::INPUT1)};
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input0_alloc = _tensor_builder->at(input0_index).get();
+  auto input1_alloc = _tensor_builder->at(input1_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NELogicalOr>();
+
+  fn->configure(input0_alloc->handle(), input1_alloc->handle(), output_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Logistic &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::Logistic::Input::INPUT)};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+
+  const ::arm_compute::ActivationLayerInfo act_info{
+      ::arm_compute::ActivationLayerInfo::ActivationFunction::LOGISTIC};
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEActivationLayer>();
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle(), act_info);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::LSTM &node)
+{
+  // TODO Support dynamic rnn
+  // TODO Fix subtle error in the case of non-CIFG, non-peephole and No Projection.
+  const auto scratch_buffer_index{
+      node.getOutputs().at(ir::operation::LSTM::Output::SCRATCH_BUFFER)};
+  const auto output_state_out_index{
+      node.getOutputs().at(ir::operation::LSTM::Output::OUTPUT_STATE_OUT)};
+  const auto cell_state_out_index{
+      node.getOutputs().at(ir::operation::LSTM::Output::CELL_STATE_OUT)};
+  const auto output_index{node.getOutputs().at(ir::operation::LSTM::Output::OUTPUT)};
+
+  const auto input_index{node.getInputs().at(ir::operation::LSTM::Input::INPUT)};
+  const auto input_to_input_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::INPUT_TO_INPUT_WEIGHTS)}; // optional
+  const auto input_to_forget_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::INPUT_TO_FORGET_WEIGHTS)};
+  const auto input_to_cell_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::INPUT_TO_CELL_WEIGHTS)};
+  const auto input_to_output_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::INPUT_TO_OUTPUT_WEIGHTS)};
+  const auto recurrent_to_input_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::RECURRENT_TO_INPUT_WEIGHTS)}; // optional
+  const auto recurrent_to_forget_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::RECURRENT_TO_FORGET_WEIGHTS)};
+  const auto recurrent_to_cell_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::RECURRENT_TO_CELL_WEIGHTS)};
+  const auto recurrent_to_output_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::RECURRENT_TO_OUTPUT_WEIGHTS)};
+  const auto cell_to_input_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::CELL_TO_INPUT_WEIGHTS)}; // optional
+  const auto cell_to_forget_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::CELL_TO_FORGET_WEIGHTS)}; // optional
+  const auto cell_to_output_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::CELL_TO_OUTPUT_WEIGHTS)}; // optional
+  const auto input_gate_bias_index{
+      node.getInputs().at(ir::operation::LSTM::Input::INPUT_GATE_BIAS)};
+  const auto forget_gate_bias_index{
+      node.getInputs().at(ir::operation::LSTM::Input::FORGET_GATE_BIAS)};
+  const auto cell_bias_index{node.getInputs().at(ir::operation::LSTM::Input::CELL_BIAS)};
+  const auto output_gate_bias_index{
+      node.getInputs().at(ir::operation::LSTM::Input::OUTPUT_GATE_BIAS)};
+  const auto projection_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::PROJECTION_WEIGHTS)}; // optional
+  const auto projection_bias_index{
+      node.getInputs().at(ir::operation::LSTM::Input::PROJECTION_BIAS)}; // optional
+  const auto output_state_in_index{
+      node.getInputs().at(ir::operation::LSTM::Input::OUTPUT_STATE_IN)};
+  const auto cell_state_in_index{node.getInputs().at(ir::operation::LSTM::Input::CELL_STATE_IN)};
+  const auto cell_threshold = node.param().cell_threshold;
+  const auto projection_threshold = node.param().projection_threshold;
+
+  bool has_input_to_input_weights = _ctx.at(input_to_input_weights_index).shape().dim(0) != 0 &&
+                                    _ctx.at(input_to_input_weights_index).shape().dim(1) != 0;
+  bool has_recurrent_to_input_weights =
+      _ctx.at(recurrent_to_input_weights_index).shape().dim(0) != 0 &&
+      _ctx.at(recurrent_to_input_weights_index).shape().dim(1) != 0;
+  bool has_cell_to_forget_weights = _ctx.at(cell_to_forget_weights_index).shape().dim(0) != 0;
+  bool has_cell_to_output_weights = _ctx.at(cell_to_output_weights_index).shape().dim(0) != 0;
+  bool has_projection_weights = _ctx.at(projection_weights_index).shape().dim(0) != 0 &&
+                                _ctx.at(projection_weights_index).shape().dim(1) != 0;
+  bool has_projection_bias = _ctx.at(projection_bias_index).shape().dim(0);
+
+  // NOTE The input_to_input_weights and the recurrent_to_input_weights do not exist in CIFG.
+  // true: no CIFG
+  // false: CIFG
+  // NOTE The cell_to_input_weights does not exist in non-peephole although regular LSTM(non-CIFG).
+  bool has_cifg_param = has_input_to_input_weights && has_recurrent_to_input_weights;
+
+  // NOTE The cell_to_forget_weights and the cell_to_output_weights exist in peephole.
+  // But the cell_to_input_weights does not exist in regular CIFG although peephole.
+  // true: peephole
+  // false: no peephole
+  bool has_peephole_param = has_cell_to_forget_weights && has_cell_to_output_weights;
+
+  // NOTE Although the projection weights has data the projection bias may not have data.
+  bool has_projection_param = has_projection_weights;
+
+  const auto activation = node.param().activation;
+  const auto cell_clip = cell_threshold;
+  const auto projection_clip = projection_threshold;
+  assert(cell_clip >= 0.f && projection_clip >= 0.f);
+
+  auto scratch_buffer_alloc = _tensor_builder->at(scratch_buffer_index).get();
+  auto output_state_out_alloc = _tensor_builder->at(output_state_out_index).get();
+  auto cell_state_out_alloc = _tensor_builder->at(cell_state_out_index).get();
+  auto output_alloc = _tensor_builder->at(output_index).get();
+
+  auto input_alloc = _tensor_builder->at(input_index).get();
+
+  auto input_to_forget_weights_alloc = _tensor_builder->at(input_to_forget_weights_index).get();
+  auto input_to_cell_weights_alloc = _tensor_builder->at(input_to_cell_weights_index).get();
+  auto input_to_output_weights_alloc = _tensor_builder->at(input_to_output_weights_index).get();
+  auto recurrent_to_forget_weights_alloc =
+      _tensor_builder->at(recurrent_to_forget_weights_index).get();
+  auto recurrent_to_cell_weights_alloc = _tensor_builder->at(recurrent_to_cell_weights_index).get();
+  auto recurrent_to_output_weights_alloc =
+      _tensor_builder->at(recurrent_to_output_weights_index).get();
+
+  auto forget_gate_bias_alloc = _tensor_builder->at(forget_gate_bias_index).get();
+  auto cell_bias_alloc = _tensor_builder->at(cell_bias_index).get();
+  auto output_gate_bias_alloc = _tensor_builder->at(output_gate_bias_index).get();
+  auto output_state_in_alloc = _tensor_builder->at(output_state_in_index).get();
+  auto cell_state_in_alloc = _tensor_builder->at(cell_state_in_index).get();
+
+  auto act_info = ::neurun::backend::acl_common::asActivationLayerInfo(activation);
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NELSTMLayer>();
+
+  ::arm_compute::LSTMParams<::arm_compute::ITensor> lstm_params{};
+  if (has_cifg_param)
+  {
+    auto input_to_input_weights_alloc =
+        _tensor_builder->at(input_to_input_weights_index).get(); // optional
+    auto recurrent_to_input_weights_alloc =
+        _tensor_builder->at(recurrent_to_input_weights_index).get(); // optional
+    auto cell_to_input_weights_handle =
+        has_peephole_param ? _tensor_builder->at(cell_to_input_weights_index).get()->handle()
+                           : nullptr; // optional (non-cifg && peephole)
+    auto input_gate_bias_alloc = _tensor_builder->at(input_gate_bias_index).get(); // optional
+    lstm_params.set_cifg_params(input_to_input_weights_alloc->handle(),
+                                recurrent_to_input_weights_alloc->handle(),
+                                cell_to_input_weights_handle, input_gate_bias_alloc->handle());
+  }
+  if (has_peephole_param)
+  {
+    auto cell_to_forget_weights_alloc =
+        _tensor_builder->at(cell_to_forget_weights_index).get(); // optional
+    auto cell_to_output_weights_alloc =
+        _tensor_builder->at(cell_to_output_weights_index).get(); // optional
+    lstm_params.set_peephole_params(cell_to_forget_weights_alloc->handle(),
+                                    cell_to_output_weights_alloc->handle());
+  }
+  if (has_projection_param)
+  {
+    auto projection_weights_alloc = _tensor_builder->at(projection_weights_index).get(); // optional
+    auto projection_bias_handle = has_projection_bias
+                                      ? _tensor_builder->at(projection_bias_index).get()->handle()
+                                      : nullptr; // optional
+    lstm_params.set_projection_params(projection_weights_alloc->handle(), projection_bias_handle);
+  }
+
+  fn->configure(
+      input_alloc->handle(), input_to_forget_weights_alloc->handle(),
+      input_to_cell_weights_alloc->handle(), input_to_output_weights_alloc->handle(),
+      recurrent_to_forget_weights_alloc->handle(), recurrent_to_cell_weights_alloc->handle(),
+      recurrent_to_output_weights_alloc->handle(), forget_gate_bias_alloc->handle(),
+      cell_bias_alloc->handle(), output_gate_bias_alloc->handle(), output_state_in_alloc->handle(),
+      cell_state_in_alloc->handle(), scratch_buffer_alloc->handle(),
+      output_state_out_alloc->handle(), cell_state_out_alloc->handle(), output_alloc->handle(),
+      lstm_params, act_info, cell_clip, projection_clip);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Mul &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto lhs_index{node.getInputs().at(ir::operation::Mul::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::Mul::Input::RHS)};
+
+  const auto activation = node.param().activation;
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto lhs_alloc = _tensor_builder->at(lhs_index).get();
+  auto rhs_alloc = _tensor_builder->at(rhs_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEPixelWiseMultiplication>();
+
+  // RoundingPolicy for scale:1.0 is only allowed RoundingPolicy::TO_ZERO
+  fn->configure(lhs_alloc->handle(), rhs_alloc->handle(), ofm_alloc->handle(), 1.0, // scale
+                arm_compute::ConvertPolicy::SATURATE, arm_compute::RoundingPolicy::TO_ZERO);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+
+  ActivationBuilder{*_execution_builder}.append(activation, ofm_alloc->handle());
+}
+
+void KernelGenerator::visit(const ir::operation::Neg &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::Neg::Input::INPUT)};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NENegLayer>();
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Pack &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  auto axis{node.param().axis};
+
+  const auto output_rank = node.param().rank;
+
+  std::vector<ir::OperandIndex> input_indexes;
+  for (const auto &input_index : node.getInputs())
+    input_indexes.emplace_back(input_index);
+
+  auto output = _tensor_builder->at(output_index).get()->handle();
+  std::vector<arm_compute::ITensor *> inputs;
+  for (const auto &input_index : input_indexes)
+    inputs.emplace_back(_tensor_builder->at(input_index)->handle());
+
+  const auto frontend_layout = _current_subg_layout;
+  const auto backend_layout = _tensor_builder->at(output_index).get()->layout();
+
+  if (axis < 0)
+    axis += output_rank;
+  axis = acl_common::ToARMComputeAxis(output_rank, axis, frontend_layout, backend_layout).value();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEStackLayer>();
+
+  fn->configure(inputs, axis, output);
+
+  _execution_builder->append(asAclFunction(std::move(fn)));
+}
+
+void KernelGenerator::visit(const ir::operation::Pad &node)
+{
+  const auto input_index{node.getInputs().at(ir::operation::Pad::Input::INPUT)};
+  const auto pad_index{node.getInputs().at(ir::operation::Pad::Input::PAD)};
+  const auto output_index{node.getOutputs().at(0)};
+  assert(_ctx.at(pad_index).isConstant());
+
+  auto rank = node.param().rank;
+  auto pad_base = _ctx.at(pad_index).data().base();
+
+  auto input = _tensor_builder->at(input_index).get()->handle();
+  auto output = _tensor_builder->at(output_index).get()->handle();
+
+  ::arm_compute::PaddingList padding_list;
+  padding_list.resize(rank);
+  for (int32_t n = 0; n < rank; ++n)
+  {
+    const int32_t *from = reinterpret_cast<const int32_t *>(pad_base) + (n * 2);
+
+    const auto frontend_layout = _current_subg_layout;
+    const auto backend_layout = _tensor_builder->at(input_index).get()->layout();
+    const auto axis =
+        acl_common::ToARMComputeAxis(rank, n, frontend_layout, backend_layout).value();
+    padding_list[axis] = ::arm_compute::PaddingInfo{from[0], from[1]};
+  }
+
+  const auto input_type = _ctx.at(input_index).typeInfo();
+  UNUSED_RELEASE(input_type);
+  assert(input->info()->data_type() == acl_common::asDataType(input_type.type()));
+  assert(input->info()->quantization_info() ==
+         ::arm_compute::QuantizationInfo(input_type.scale(), input_type.offset()));
+  const auto pixel_value =
+      ::arm_compute::PixelValue(0, input->info()->data_type(), input->info()->quantization_info());
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEPadLayer>();
+  fn->configure(input, output, padding_list, pixel_value);
+
+  _execution_builder->append(asAclFunction(std::move(fn)));
+}
+
+void KernelGenerator::visit(const ir::operation::Permute &node)
+{
+  const auto ofm_idx{node.getOutputs().at(0)};
+  const auto ifm_idx{node.getInputs().at(0)};
+  const auto permute_type = node.getPermuteType();
+  auto ofm_alloc = _tensor_builder->at(ofm_idx).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_idx).get();
+  const auto rank = _ctx.at(ofm_idx).shape().rank();
+  assert(_ctx.at(ifm_idx).shape().rank() == _ctx.at(ofm_idx).shape().rank());
+
+  std::unique_ptr<::arm_compute::IFunction> fn;
+  arm_compute::PermutationVector pv;
+  if (permute_type == ir::operation::Permute::Type::NCHW_TO_NHWC && rank == 4)
+  {
+    // WHCN -> CWHN
+    pv = arm_compute::PermutationVector{2, 0, 1};
+
+    auto l = nnfw::cpp14::make_unique<::arm_compute::NEPermute>();
+
+    l->configure(ifm_alloc->handle(), ofm_alloc->handle(), pv);
+
+    fn = std::move(l);
+  }
+  else if (permute_type == ir::operation::Permute::Type::NHWC_TO_NCHW && rank == 4)
+  {
+    // CWHN -> WHCN
+    pv = arm_compute::PermutationVector{1, 2, 0};
+
+    auto l = nnfw::cpp14::make_unique<::arm_compute::NEPermute>();
+
+    l->configure(ifm_alloc->handle(), ofm_alloc->handle(), pv);
+
+    fn = std::move(l);
+  }
+  else
+  {
+    auto l = nnfw::cpp14::make_unique<::arm_compute::NECopy>();
+
+    l->configure(ifm_alloc->handle(), ofm_alloc->handle());
+
+    fn = std::move(l);
+  }
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::PReLU &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::PReLU::Input::INPUT)};
+  const auto alpha_index{node.getInputs().at(ir::operation::PReLU::Input::ALPHA)};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+  auto alpha_alloc = _tensor_builder->at(alpha_index).get();
+
+  std::unique_ptr<::arm_compute::IFunction> fn;
+
+  auto l = nnfw::cpp14::make_unique<::arm_compute::NEPReLU>();
+
+  l->configure(ifm_alloc->handle(), alpha_alloc->handle(), ofm_alloc->handle());
+
+  fn = std::move(l);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::ReduceMax &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::ReduceMax::Input::INPUT)};
+  const auto &axes{node.param().axes};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+  const auto frontend_layout = _current_subg_layout;
+  const auto backend_layout = ifm_alloc->layout();
+
+  // Convert to ACL axes taking into account negative values and possible duplicates.
+  std::set<std::uint32_t> acl_axes;
+  const int ifm_rank = node.param().rank;
+  for (int axis : axes)
+  {
+    if (axis < 0)
+      axis += ifm_rank;
+    acl_axes.insert(
+        acl_common::ToARMComputeAxis(ifm_rank, axis, frontend_layout, backend_layout).value());
+  }
+
+  arm_compute::Coordinates reduce_axes;
+  for (const auto axis : acl_axes)
+  {
+    reduce_axes.set(reduce_axes.num_dimensions(), axis);
+  }
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEReduceOperation>();
+
+  fn->configure(ifm_alloc->handle(), reduce_axes, false, ofm_alloc->handle(),
+                ::arm_compute::ReduceOperation::MAX);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::ReduceMin &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::ReduceMin::Input::INPUT)};
+  const auto &axes{node.param().axes};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+  const auto frontend_layout = _current_subg_layout;
+  const auto backend_layout = ifm_alloc->layout();
+
+  // Convert to ACL axes taking into account negative values and possible duplicates.
+  std::set<std::uint32_t> acl_axes;
+  const int ifm_rank = node.param().rank;
+  for (int axis : axes)
+  {
+    if (axis < 0)
+      axis += ifm_rank;
+    acl_axes.insert(
+        acl_common::ToARMComputeAxis(ifm_rank, axis, frontend_layout, backend_layout).value());
+  }
+
+  arm_compute::Coordinates reduce_axes;
+  for (const auto axis : acl_axes)
+  {
+    reduce_axes.set(reduce_axes.num_dimensions(), axis);
+  }
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEReduceOperation>();
+
+  fn->configure(ifm_alloc->handle(), reduce_axes, false, ofm_alloc->handle(),
+                ::arm_compute::ReduceOperation::MIN);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::ReduceSum &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::ReduceSum::Input::INPUT)};
+  const auto &axes{node.param().axes};
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input_alloc = _tensor_builder->at(input_index).get();
+  const auto frontend_layout = _current_subg_layout;
+  const auto backend_layout = input_alloc->layout();
+
+  // Convert to ACL axes taking into account negative values and possible duplicates.
+  std::set<std::uint32_t> acl_axes;
+  const int input_rank = node.param().rank;
+  for (int axis : axes)
+  {
+    if (axis < 0)
+      axis += input_rank;
+    acl_axes.insert(
+        acl_common::ToARMComputeAxis(input_rank, axis, frontend_layout, backend_layout).value());
+  }
+
+  arm_compute::Coordinates fixed_axes;
+  for (const auto axis : acl_axes)
+  {
+    fixed_axes.set(fixed_axes.num_dimensions(), axis);
+  }
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEReduceSum>();
+
+  fn->configure(input_alloc->handle(), fixed_axes, false, output_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::ReLU &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::ReLU::Input::INPUT)};
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input_alloc = _tensor_builder->at(input_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<arm_compute::NEActivationLayer>();
+
+  const ::arm_compute::ActivationLayerInfo act_info{
+      ::arm_compute::ActivationLayerInfo::ActivationFunction::RELU};
+
+  fn->configure(input_alloc->handle(), output_alloc->handle(), act_info);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::ReLU1 &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::ReLU1::Input::INPUT)};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+
+  const ::arm_compute::ActivationLayerInfo act_info{
+      ::arm_compute::ActivationLayerInfo::ActivationFunction::LU_BOUNDED_RELU, 1.0f, -1.0f};
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEActivationLayer>();
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle(), act_info);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::ReLU6 &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::ReLU6::Input::INPUT)};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+
+  const ::arm_compute::ActivationLayerInfo act_info{
+      ::arm_compute::ActivationLayerInfo::ActivationFunction::BOUNDED_RELU, 6.0f};
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEActivationLayer>();
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle(), act_info);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Reshape &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::Reshape::Input::INPUT)};
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input_alloc = _tensor_builder->at(input_index).get();
+
+  // NOTE This operation must not be changed the layout from frontend to backend
+  //      So, PermutationOperationPass makes layouts of frontend and backend the same.
+  const auto frontend_layout = _current_subg_layout;
+  const auto backend_layout = output_alloc->layout();
+  assert((_ctx.at(input_index).shape().rank() < 4 && _ctx.at(output_index).shape().rank() < 4) ||
+         frontend_layout == backend_layout);
+  UNUSED_RELEASE(frontend_layout);
+  UNUSED_RELEASE(backend_layout);
+
+  auto fn = nnfw::cpp14::make_unique<arm_compute::NEReshapeLayer>();
+
+  fn->configure(input_alloc->handle(), output_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::ResizeBilinear &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+
+  const auto ifm_index{node.getInputs().at(ir::operation::ResizeBilinear::Input::INPUT)};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEScale>();
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle(),
+                ::arm_compute::InterpolationPolicy::BILINEAR, ::arm_compute::BorderMode::REPLICATE,
+                ::arm_compute::PixelValue(0.f), ::arm_compute::SamplingPolicy::TOP_LEFT);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::RNN &node)
+{
+  const auto output_index{node.getOutputs().at(ir::operation::RNN::Output::OUTPUT)};
+  const auto hidden_state_out_index{
+      node.getOutputs().at(ir::operation::RNN::Output::HIDDEN_STATE_OUT)};
+
+  const auto input_index{node.getInputs().at(ir::operation::RNN::Input::INPUT)};
+  const auto weights_index{node.getInputs().at(ir::operation::RNN::Input::WEIGHTS)};
+  const auto recurrent_weights_index{
+      node.getInputs().at(ir::operation::RNN::Input::RECURRENT_WEIGHTS)};
+  const auto bias_index{node.getInputs().at(ir::operation::RNN::Input::BIAS)};
+  const auto hidden_state_in_index{node.getInputs().at(ir::operation::RNN::Input::HIDDEN_STATE_IN)};
+
+  const auto activation = node.param().activation;
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto hidden_state_out_alloc = _tensor_builder->at(hidden_state_out_index).get();
+
+  auto input_alloc = _tensor_builder->at(input_index).get();
+  auto weights_alloc = _tensor_builder->at(weights_index).get();
+  auto recurrent_weights_alloc = _tensor_builder->at(recurrent_weights_index).get();
+  auto bias_alloc = _tensor_builder->at(bias_index).get();
+  auto hidden_state_in_alloc = _tensor_builder->at(hidden_state_in_index).get();
+  auto act_info = ::neurun::backend::acl_common::asActivationLayerInfo(activation);
+
+  auto copy_layer = nnfw::cpp14::make_unique<::arm_compute::NECopy>();
+  copy_layer->configure(hidden_state_in_alloc->handle(), hidden_state_out_alloc->handle());
+  _execution_builder->append(asAclFunction(std::move(copy_layer)));
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NERNNLayerEx>(
+      _tensor_builder->acl_tensor_manager()->internal_buffer_manager());
+  fn->configure(input_alloc->handle(), weights_alloc->handle(), recurrent_weights_alloc->handle(),
+                bias_alloc->handle(), hidden_state_out_alloc->handle(), output_alloc->handle(),
+                act_info);
+  _execution_builder->append(asAclFunction(std::move(fn)));
+}
+
+void KernelGenerator::visit(const ir::operation::RSQRT &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::RSQRT::Input::INPUT)};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NERsqrtLayer>();
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle());
+
+  _execution_builder->append(asAclFunction(std::move(fn)));
+}
+
+void KernelGenerator::visit(const ir::operation::Squeeze &node)
+{
+  // Squeeze is identical to reshape except that it has an optional dimensions input.
+  // In addition, optional dims_index is ignored since output tensor already has squeezed shape
+  // by freezer and toco
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::Squeeze::Input::INPUT)};
+  const auto dims{node.param().dims};
+  const auto ndim{node.param().ndim};
+  (void)dims;
+  (void)ndim;
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input_alloc = _tensor_builder->at(input_index).get();
+  auto fn = nnfw::cpp14::make_unique<arm_compute::NEReshapeLayer>();
+  fn->configure(input_alloc->handle(), output_alloc->handle());
+  auto acl_fn = asAclFunction(std::move(fn));
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Tanh &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::Tanh::Input::INPUT)};
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input_alloc = _tensor_builder->at(input_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<arm_compute::NEActivationLayer>();
+
+  const ::arm_compute::ActivationLayerInfo act_info{
+      ::arm_compute::ActivationLayerInfo::ActivationFunction::TANH, 1.0f, 1.0f};
+
+  fn->configure(input_alloc->handle(), output_alloc->handle(), act_info);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Softmax &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::Softmax::Input::INPUT)};
+  const auto beta = node.param().beta;
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input_alloc = _tensor_builder->at(input_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NESoftmaxLayer>(
+      _tensor_builder->acl_tensor_manager()->internal_buffer_manager());
+
+  fn->configure(input_alloc->handle(), output_alloc->handle(), beta);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::SpaceToBatchND &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::SpaceToBatchND::Input::INPUT)};
+  const auto block_size_index{
+      node.getInputs().at(ir::operation::SpaceToBatchND::Input::BLOCK_SIZE)};
+  const auto paddings_index{node.getInputs().at(ir::operation::SpaceToBatchND::Input::PADDINGS)};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+  auto block_size_alloc = _tensor_builder->at(block_size_index).get();
+  auto paddings_alloc = _tensor_builder->at(paddings_index).get();
+
+  assert(_ctx.at(block_size_index).isConstant());
+  assert(_ctx.at(paddings_index).isConstant());
+
+  // NESpaceToBatchLayer has a bug that padding's values are 0 even when zero point of QASYMM8 is
+  // not 0.
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NESpaceToBatchLayerEx>();
+
+  fn->configure(ifm_alloc->handle(), block_size_alloc->handle(), paddings_alloc->handle(),
+                ofm_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::SpaceToDepth &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::SpaceToDepth::Input::INPUT)};
+
+  auto block_size = node.param().block_size;
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NESpaceToDepthLayerEx>();
+
+  fn->configure(ifm_alloc->handle(), ofm_alloc->handle(), block_size);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Split &node)
+{
+  // TODO Support this op by SubTensor
+  const auto ifm_index{node.getInputs().at(ir::operation::Split::Input::INPUT)};
+
+  assert(node.param().num_splits == static_cast<int>(node.getOutputs().size()));
+
+  const auto ifm_rank = node.param().rank;
+  std::vector<ir::OperandIndex> output_indexes;
+  for (const auto &output : node.getOutputs())
+    output_indexes.emplace_back(output);
+
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+  std::vector<arm_compute::ITensor *> output_allocs;
+  for (const auto &ofm_ind : output_indexes)
+    output_allocs.emplace_back(_tensor_builder->at(ofm_ind).get()->handle());
+
+  const auto frontend_layout = _current_subg_layout;
+  const auto backend_layout = ifm_alloc->layout();
+  auto axis = node.param().axis;
+  if (axis < 0)
+    axis += ifm_rank;
+  axis = acl_common::ToARMComputeAxis(ifm_rank, axis, frontend_layout, backend_layout).value();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NESplit>();
+
+  fn->configure(ifm_alloc->handle(), output_allocs, axis);
+
+  _execution_builder->append(asAclFunction(std::move(fn)));
+}
+
+void KernelGenerator::visit(const ir::operation::SQRT &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::SQRT::Input::INPUT)};
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input_alloc = _tensor_builder->at(input_index).get();
+
+  const ::arm_compute::ActivationLayerInfo act_info{
+      ::arm_compute::ActivationLayerInfo::ActivationFunction::SQRT};
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEActivationLayer>();
+
+  fn->configure(input_alloc->handle(), output_alloc->handle(), act_info);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::SquaredDifference &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto lhs_index{node.getInputs().at(ir::operation::SquaredDifference::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::SquaredDifference::Input::RHS)};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto lhs_alloc = _tensor_builder->at(lhs_index).get();
+  auto rhs_alloc = _tensor_builder->at(rhs_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEElementwiseSquaredDiff>();
+
+  fn->configure(lhs_alloc->handle(), rhs_alloc->handle(), ofm_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Sub &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto lhs_index{node.getInputs().at(ir::operation::Sub::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::Sub::Input::RHS)};
+
+  const auto activation = node.param().activation;
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto lhs_alloc = _tensor_builder->at(lhs_index).get();
+  auto rhs_alloc = _tensor_builder->at(rhs_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEArithmeticSubtraction>();
+
+  fn->configure(lhs_alloc->handle(), rhs_alloc->handle(), ofm_alloc->handle(),
+                arm_compute::ConvertPolicy::SATURATE);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+
+  ActivationBuilder{*_execution_builder}.append(activation, ofm_alloc->handle());
+}
+
+void KernelGenerator::visit(const ir::operation::Slice &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::Slice::Input::INPUT)};
+  const auto begins_index{node.getInputs().at(ir::operation::Slice::Input::BEGINS)};
+  const auto sizes_index{node.getInputs().at(ir::operation::Slice::Input::SIZES)};
+
+  auto outputData_alloc = _tensor_builder->at(output_index).get();
+  auto inputData_alloc = _tensor_builder->at(input_index).get();
+  const auto frontend_layout = _current_subg_layout;
+  const auto backend_layout = inputData_alloc->layout();
+
+  // Set initializers for indices data such as order of inputData
+  int input_rank = node.param().rank;
+  std::vector<int32_t> starts;
+  std::vector<int32_t> ends;
+  starts.resize(input_rank, 0);
+  ends.resize(input_rank, 0);
+  {
+    auto beginData_base = _ctx.at(begins_index).data().base();
+    auto sizeData_base = _ctx.at(sizes_index).data().base();
+    const int beginData_size = _ctx.at(begins_index).shape().num_elements();
+    const int sizeData_size = _ctx.at(sizes_index).shape().num_elements();
+
+    using ir::DataType;
+
+    UNUSED_RELEASE(beginData_size);
+    UNUSED_RELEASE(sizeData_size);
+
+    assert(_ctx.at(begins_index).typeInfo().type() == DataType::INT32);
+    assert(_ctx.at(sizes_index).typeInfo().type() == DataType::INT32);
+    assert(beginData_size == input_rank);
+    assert(sizeData_size == input_rank);
+
+    assert(beginData_base != nullptr);
+    for (int n = 0; n < input_rank; ++n)
+    {
+      auto axis = ::neurun::backend::acl_common::ToARMComputeAxis(input_rank, n, frontend_layout,
+                                                                  backend_layout)
+                      .value();
+
+      int32_t begin_value = *(reinterpret_cast<const int32_t *>(beginData_base) + n);
+      starts[axis] = begin_value;
+
+      int32_t size_value = *(reinterpret_cast<const int32_t *>(sizeData_base) + n);
+      ends[axis] = begin_value + size_value;
+    }
+  }
+
+  ::arm_compute::Coordinates starts_set;
+  ::arm_compute::Coordinates ends_set;
+
+  for (size_t i = 0; i < starts.size(); ++i)
+  {
+    starts_set.set(i, starts[i]);
+    ends_set.set(i, ends[i]);
+  }
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NESlice>();
+
+  fn->configure(inputData_alloc->handle(), outputData_alloc->handle(), starts_set, ends_set);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::StridedSlice &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::StridedSlice::Input::INPUT)};
+  const auto starts_index{node.getInputs().at(ir::operation::StridedSlice::Input::STARTS)};
+  const auto ends_index{node.getInputs().at(ir::operation::StridedSlice::Input::ENDS)};
+  const auto strides_index{node.getInputs().at(ir::operation::StridedSlice::Input::STRIDES)};
+
+  auto outputData_alloc = _tensor_builder->at(output_index).get();
+  auto inputData_alloc = _tensor_builder->at(input_index).get();
+  const auto frontend_layout = _current_subg_layout;
+  const auto backend_layout = inputData_alloc->layout();
+
+  // Set initializers for indices data such as order of inputData
+  int input_rank = node.param().rank;
+  std::vector<int32_t> starts;
+  std::vector<int32_t> ends;
+  std::vector<int32_t> strides;
+  starts.resize(input_rank, 0);
+  ends.resize(input_rank, 0);
+  strides.resize(input_rank, 0);
+  {
+    auto startData_base = _ctx.at(starts_index).data().base();
+    auto endData_base = _ctx.at(ends_index).data().base();
+    auto stridesData_base = _ctx.at(strides_index).data().base();
+    const int startData_size = _ctx.at(starts_index).shape().num_elements();
+    const int endData_size = _ctx.at(ends_index).shape().num_elements();
+    const int stridesData_size = _ctx.at(strides_index).shape().num_elements();
+
+    using ir::DataType;
+
+    UNUSED_RELEASE(startData_size);
+    UNUSED_RELEASE(endData_size);
+    UNUSED_RELEASE(stridesData_size);
+
+    assert(_ctx.at(starts_index).typeInfo().type() == DataType::INT32);
+    assert(_ctx.at(ends_index).typeInfo().type() == DataType::INT32);
+    assert(_ctx.at(strides_index).typeInfo().type() == DataType::INT32);
+    assert(startData_size == input_rank);
+    assert(endData_size == input_rank);
+    assert(stridesData_size == input_rank);
+
+    assert(startData_base != nullptr);
+    for (int n = 0; n < input_rank; ++n)
+    {
+      auto axis = ::neurun::backend::acl_common::ToARMComputeAxis(input_rank, n, frontend_layout,
+                                                                  backend_layout)
+                      .value();
+
+      int32_t start_value = *(reinterpret_cast<const int32_t *>(startData_base) + n);
+      starts[axis] = start_value;
+
+      int32_t end_value = *(reinterpret_cast<const int32_t *>(endData_base) + n);
+      ends[axis] = end_value;
+
+      int32_t strides_value = *(reinterpret_cast<const int32_t *>(stridesData_base) + n);
+      strides[axis] = strides_value;
+    }
+  }
+
+  // Set mask bits such as order of inputData
+  // FIXME Take the layouts into account.
+  const auto begin_mask = acl_common::ReorderBits<int32_t>(node.param().begin_mask, input_rank);
+  const auto end_mask = acl_common::ReorderBits<int32_t>(node.param().end_mask, input_rank);
+  const auto shrink_axis_mask =
+      acl_common::ReorderBits<int32_t>(node.param().shrink_axis_mask, input_rank);
+
+  ::arm_compute::Coordinates starts_set;
+  ::arm_compute::Coordinates ends_set;
+  ::arm_compute::BiStrides strides_set;
+
+  for (size_t i = 0; i < starts.size(); ++i)
+  {
+    starts_set.set(i, starts[i]);
+    ends_set.set(i, ends[i]);
+    strides_set.set(i, strides[i]);
+  }
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEStridedSlice>();
+
+  fn->configure(inputData_alloc->handle(), outputData_alloc->handle(), starts_set, ends_set,
+                strides_set, begin_mask, end_mask, shrink_axis_mask);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::TransposeConv &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto output_shape_index{
+      node.getInputs().at(ir::operation::TransposeConv::Input::OUTPUT_SHAPE)};
+  const auto ker_index{node.getInputs().at(ir::operation::TransposeConv::Input::KERNEL)};
+  const auto ifm_index{node.getInputs().at(ir::operation::TransposeConv::Input::INPUT)};
+
+  const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature(_current_subg_layout);
+  const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature(_current_subg_layout);
+  const auto ker_shape = _ctx.at(ker_index).shape().asFeature(_current_subg_layout);
+
+  const auto stride = node.param().stride;
+
+  assert((node.param().padding.type == ir::PaddingType::SAME) ||
+         (node.param().padding.type == ir::PaddingType::VALID));
+  auto padding = neurun::util::calculatePadding(node.param().padding, ofm_shape, ifm_shape, stride,
+                                                ker_shape.W, ker_shape.H);
+
+  uint32_t invalid_horizontal = 0;
+  uint32_t invalid_vertical = 0;
+  if (node.param().padding.type == ir::PaddingType::VALID)
+  {
+    invalid_horizontal =
+        ofm_shape.W - (1 + (ifm_shape.W - 1) * stride.horizontal) - (ker_shape.W - 1);
+    invalid_vertical = ofm_shape.H - (1 + (ifm_shape.H - 1) * stride.vertical) - (ker_shape.H - 1);
+  }
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+  auto ker_alloc = _tensor_builder->at(ker_index).get();
+
+  const auto tconv_info = acl_common::asPadStrideInfo(padding, stride);
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NETransposeConvLayer>();
+
+  fn->configure(ifm_alloc->handle(), ker_alloc->handle(), nullptr, ofm_alloc->handle(), tconv_info,
+                invalid_horizontal, invalid_vertical);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Transpose &node)
+{
+  const auto ofm_idx{node.getOutputs().at(0)};
+  const auto ifm_idx{node.getInputs().at(ir::operation::Transpose::Input::INPUT)};
+  const auto &perm{node.param().perm};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_idx).get();
+  const auto ifm_alloc = _tensor_builder->at(ifm_idx).get();
+  const auto frontend_layout = _current_subg_layout;
+  const auto backend_layout = ifm_alloc->layout();
+
+  const auto rank = node.param().rank;
+  std::vector<std::int32_t> pv(perm.cbegin(), perm.cend());
+  auto backend_pv = ::neurun::backend::acl_common::getARMComputePermutationVector(
+      rank, pv, frontend_layout, backend_layout);
+
+  std::unique_ptr<::arm_compute::IFunction> fn;
+
+  if (ifm_alloc->num_dimensions() <= 2 && ofm_alloc->num_dimensions() <= 2)
+  {
+    auto l = nnfw::cpp14::make_unique<::arm_compute::NETranspose>();
+
+    l->configure(ifm_alloc->handle(), ofm_alloc->handle());
+
+    fn = std::move(l);
+  }
+  else
+  {
+    auto l = nnfw::cpp14::make_unique<::arm_compute::NEPermute>();
+
+    l->configure(ifm_alloc->handle(), ofm_alloc->handle(), backend_pv);
+
+    fn = std::move(l);
+  }
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Unpack &node)
+{
+  const auto input_index{node.getInputs().at(ir::operation::Unpack::Input::INPUT)};
+  auto axis{node.param().axis};
+
+  const auto input_rank = node.param().rank;
+
+  std::vector<ir::OperandIndex> output_indexes;
+  for (const auto &output_index : node.getOutputs())
+    output_indexes.emplace_back(output_index);
+
+  auto input = _tensor_builder->at(input_index).get()->handle();
+  std::vector<arm_compute::ITensor *> outputs;
+  for (const auto &output_index : output_indexes)
+    outputs.emplace_back(_tensor_builder->at(output_index)->handle());
+
+  const auto frontend_layout = _current_subg_layout;
+  const auto backend_layout = _tensor_builder->at(input_index).get()->layout();
+  if (axis < 0)
+    axis += input_rank;
+  axis = acl_common::ToARMComputeAxis(input_rank, axis, frontend_layout, backend_layout).value();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEUnstack>();
+
+  fn->configure(input, outputs, axis);
+
+  _execution_builder->append(asAclFunction(std::move(fn)));
+}
+
+void KernelGenerator::visit(const ir::operation::Add &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto lhs_index{node.getInputs().at(ir::operation::Add::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::Add::Input::RHS)};
+
+  const auto activation = node.param().activation;
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto lhs_alloc = _tensor_builder->at(lhs_index).get();
+  auto rhs_alloc = _tensor_builder->at(rhs_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEArithmeticAddition>();
+
+  fn->configure(lhs_alloc->handle(), rhs_alloc->handle(), ofm_alloc->handle(),
+                arm_compute::ConvertPolicy::SATURATE);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+
+  ActivationBuilder{*_execution_builder}.append(activation, ofm_alloc->handle());
+}
+
+void KernelGenerator::visit(const ir::operation::Div &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto lhs_index{node.getInputs().at(ir::operation::Div::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::Div::Input::RHS)};
+
+  const auto activation = node.param().activation;
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto lhs_alloc = _tensor_builder->at(lhs_index).get();
+  auto rhs_alloc = _tensor_builder->at(rhs_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEElementwiseDivision>();
+
+  fn->configure(lhs_alloc->handle(), rhs_alloc->handle(), ofm_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+
+  ActivationBuilder{*_execution_builder}.append(activation, ofm_alloc->handle());
+}
+
+void KernelGenerator::visit(const ir::operation::Exp &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::Exp::Input::INPUT)};
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input_alloc = _tensor_builder->at(input_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEExpLayer>();
+
+  fn->configure(input_alloc->handle(), output_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Comparison &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input0_index{node.getInputs().at(ir::operation::Comparison::Input::INPUT0)};
+  const auto input1_index{node.getInputs().at(ir::operation::Comparison::Input::INPUT1)};
+
+  const auto comparison_type = node.param().comparison_type;
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input0_alloc = _tensor_builder->at(input0_index).get();
+  auto input1_alloc = _tensor_builder->at(input1_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEElementwiseComparison>();
+
+  fn->configure(input0_alloc->handle(), input1_alloc->handle(), output_alloc->handle(),
+                (arm_compute::ComparisonOperation)comparison_type);
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Min &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto lhs_index{node.getInputs().at(ir::operation::Min::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::Min::Input::RHS)};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto lhs_alloc = _tensor_builder->at(lhs_index).get();
+  auto rhs_alloc = _tensor_builder->at(rhs_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEElementwiseMin>();
+
+  fn->configure(lhs_alloc->handle(), rhs_alloc->handle(), ofm_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Max &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto lhs_index{node.getInputs().at(ir::operation::Max::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::Max::Input::RHS)};
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto lhs_alloc = _tensor_builder->at(lhs_index).get();
+  auto rhs_alloc = _tensor_builder->at(rhs_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::arm_compute::NEElementwiseMax>();
+
+  fn->configure(lhs_alloc->handle(), rhs_alloc->handle(), ofm_alloc->handle());
+
+  auto acl_fn = asAclFunction(std::move(fn));
+
+  _execution_builder->append(std::move(acl_fn));
+}
+
+} // namespace acl_neon
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/acl_neon/KernelGenerator.h b/runtime/neurun/backend/acl_neon/KernelGenerator.h
new file mode 100644
index 000000000..f041fb725
--- /dev/null
+++ b/runtime/neurun/backend/acl_neon/KernelGenerator.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ACL_NEON_KERNEL_GENERATOR_H__
+#define __NEURUN_BACKEND_ACL_NEON_KERNEL_GENERATOR_H__
+
+#include <backend/IKernelGenerator.h>
+
+#include "ir/Operands.h"
+#include "TensorBuilder.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_neon
+{
+
+class KernelGenerator : public IKernelGenerator
+{
+public:
+  KernelGenerator(const ir::Operands &ctx, const std::shared_ptr<TensorBuilder> &tensor_builder);
+
+  void visit(const ir::OpSequence &) override;
+  void visit(const ir::operation::Abs &) override;
+  void visit(const ir::operation::ArgMax &) override;
+  void visit(const ir::operation::BatchToSpaceND &) override;
+  void visit(const ir::operation::Cast &) override;
+  void visit(const ir::operation::Conv2D &) override;
+  void visit(const ir::operation::DepthToSpace &) override;
+  void visit(const ir::operation::DepthwiseConv2D &) override;
+  void visit(const ir::operation::Dequantize &) override;
+  void visit(const ir::operation::MaxPool2D &) override;
+  void visit(const ir::operation::Mean &) override;
+  void visit(const ir::operation::AvgPool2D &) override;
+  void visit(const ir::operation::Concat &) override;
+  void visit(const ir::operation::EmbeddingLookup &) override;
+  void visit(const ir::operation::Floor &) override;
+  void visit(const ir::operation::FullyConnected &) override;
+  void visit(const ir::operation::Gather &) override;
+  void visit(const ir::operation::HashtableLookup &) override;
+  void visit(const ir::operation::InstanceNorm &) override;
+  void visit(const ir::operation::L2Normalization &) override;
+  void visit(const ir::operation::L2Pool2D &) override;
+  void visit(const ir::operation::LocalResponseNormalization &) override;
+  void visit(const ir::operation::LogicalAnd &) override;
+  void visit(const ir::operation::LogicalNot &) override;
+  void visit(const ir::operation::LogicalOr &) override;
+  void visit(const ir::operation::Logistic &) override;
+  void visit(const ir::operation::LSTM &) override;
+  void visit(const ir::operation::Mul &) override;
+  void visit(const ir::operation::Neg &) override;
+  void visit(const ir::operation::Pack &) override;
+  void visit(const ir::operation::Pad &) override;
+  void visit(const ir::operation::Permute &) override;
+  void visit(const ir::operation::PReLU &) override;
+  void visit(const ir::operation::ReduceMax &) override;
+  void visit(const ir::operation::ReduceMin &) override;
+  void visit(const ir::operation::ReduceSum &) override;
+  void visit(const ir::operation::ReLU &) override;
+  void visit(const ir::operation::ReLU1 &) override;
+  void visit(const ir::operation::ReLU6 &) override;
+  void visit(const ir::operation::Reshape &) override;
+  void visit(const ir::operation::ResizeBilinear &) override;
+  void visit(const ir::operation::RNN &) override;
+  void visit(const ir::operation::RSQRT &) override;
+  void visit(const ir::operation::Squeeze &) override;
+  void visit(const ir::operation::Tanh &) override;
+  void visit(const ir::operation::Softmax &) override;
+  void visit(const ir::operation::SpaceToBatchND &) override;
+  void visit(const ir::operation::SpaceToDepth &) override;
+  void visit(const ir::operation::Split &) override;
+  void visit(const ir::operation::SQRT &) override;
+  void visit(const ir::operation::SquaredDifference &) override;
+  void visit(const ir::operation::Sub &) override;
+  void visit(const ir::operation::Slice &) override;
+  void visit(const ir::operation::StridedSlice &) override;
+  void visit(const ir::operation::TransposeConv &) override;
+  void visit(const ir::operation::Transpose &) override;
+  void visit(const ir::operation::Unpack &) override;
+  void visit(const ir::operation::Add &) override;
+  void visit(const ir::operation::Div &) override;
+  void visit(const ir::operation::Exp &) override;
+  void visit(const ir::operation::Comparison &) override;
+  void visit(const ir::operation::Min &) override;
+  void visit(const ir::operation::Max &) override;
+
+private:
+  const ir::Operands &_ctx;
+  std::shared_ptr<TensorBuilder> _tensor_builder;
+  ir::Layout _current_subg_layout;
+};
+
+} // namespace acl_neon
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ACL_NEON_KERNEL_GENERATOR_H__
diff --git a/runtime/neurun/backend/acl_neon/PluginClassesAllocator.cc b/runtime/neurun/backend/acl_neon/PluginClassesAllocator.cc
new file mode 100644
index 000000000..75f2e9797
--- /dev/null
+++ b/runtime/neurun/backend/acl_neon/PluginClassesAllocator.cc
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <util/logging.h>
+
+#include "Backend.h"
+
+extern "C" {
+neurun::backend::Backend *neurun_backend_create()
+{
+  VERBOSE(neurun_backend_create) << "'acl_neon' loaded\n";
+  return new neurun::backend::acl_neon::Backend;
+}
+
+void neurun_backend_destroy(neurun::backend::Backend *backend)
+{
+  VERBOSE(neurun_backend_create) << "'acl_neon' unloaded\n";
+  delete backend;
+}
+}
diff --git a/runtime/neurun/backend/acl_neon/ShapeFixer.cc b/runtime/neurun/backend/acl_neon/ShapeFixer.cc
new file mode 100644
index 000000000..1d80e57e9
--- /dev/null
+++ b/runtime/neurun/backend/acl_neon/ShapeFixer.cc
@@ -0,0 +1,439 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ShapeFixer.h"
+
+#include <arm_compute/runtime/NEON/functions/NESoftmaxLayer.h>
+#include <arm_compute/runtime/NEON/functions/NEArithmeticAddition.h>
+#include <arm_compute/runtime/NEON/functions/NEArithmeticSubtraction.h>
+#include <arm_compute/runtime/NEON/functions/NEPixelWiseMultiplication.h>
+#include <arm_compute/runtime/NEON/functions/NEPoolingLayer.h>
+#include <arm_compute/runtime/NEON/functions/NEActivationLayer.h>
+#include <arm_compute/runtime/NEON/functions/NEConvolutionLayer.h>
+#include <arm_compute/runtime/NEON/functions/NEDepthwiseConvolutionLayer.h>
+#include <arm_compute/runtime/NEON/functions/NEReshapeLayer.h>
+#include <arm_compute/runtime/NEON/functions/NEFullyConnectedLayer.h>
+#include <arm_compute/runtime/NEON/functions/NEFullyConnectedReshapingLayer.h>
+
+#include <Convert.h>
+#include <Swizzle.h>
+
+#include "util/Padding.h"
+#include "ir/Index.h"
+#include "compiler/IExecutionBuilder.h"
+#include "exec/NopFunction.h"
+#include "util/logging.h"
+#include "util/Utils.h"
+
+using ::neurun::compiler::IExecutionBuilder;
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_neon
+{
+
+using ::neurun::backend::acl_common::asAclFunction;
+
+ShapeFixer::ShapeFixer(const ir::Operands &ctx,
+                       const std::shared_ptr<TensorBuilder> &tensor_builder)
+    : _ctx(ctx), _tensor_builder(tensor_builder)
+{
+  assert(tensor_builder);
+}
+
+void ShapeFixer::visit(const ir::operation::Abs &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::ArgMax &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::BatchToSpaceND &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::BatchToSpaceND::Input::INPUT)};
+  _tensor_builder->dimCorrection(ofm_index, false);
+  _tensor_builder->dimCorrection(ifm_index, false);
+}
+
+void ShapeFixer::visit(const ir::operation::Cast &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Conv2D &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::DepthToSpace &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::DepthwiseConv2D &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Dequantize &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::MaxPool2D &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Mean &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::AvgPool2D &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Concat &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  _tensor_builder->dimCorrection(ofm_index, false);
+  for (const auto &inputs : node.getInputs())
+    _tensor_builder->dimCorrection(inputs, false);
+}
+
+void ShapeFixer::visit(const ir::operation::EmbeddingLookup &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto values_index{node.getInputs().at(ir::operation::EmbeddingLookup::Input::VALUES)};
+  _tensor_builder->dimCorrection(values_index, false);
+  _tensor_builder->dimCorrection(output_index, false);
+}
+
+void ShapeFixer::visit(const ir::operation::Exp &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Floor &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::FullyConnected &node)
+{
+  using ir::operation::FullyConnected;
+  const auto input_index{node.getInputs().at(FullyConnected::Input::INPUT)};
+  const auto input_rank = _ctx.at(input_index).shape().rank();
+  // Check for reshaping input's shape into rank-2
+  if (input_rank == 3 || input_rank == 4)
+    _tensor_builder->dimCorrection(input_index, false);
+}
+
+void ShapeFixer::visit(const ir::operation::HashtableLookup &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto values_index{node.getInputs().at(ir::operation::EmbeddingLookup::Input::VALUES)};
+  _tensor_builder->dimCorrection(values_index, false);
+  _tensor_builder->dimCorrection(output_index, false);
+}
+
+void ShapeFixer::visit(const ir::operation::Gather &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::Gather::Input::INPUT)};
+  const auto indices_index{node.getInputs().at(ir::operation::Gather::Input::INDICES)};
+  _tensor_builder->dimCorrection(ofm_index, false);
+  _tensor_builder->dimCorrection(ifm_index, false);
+  _tensor_builder->dimCorrection(indices_index, false);
+}
+
+void ShapeFixer::visit(const ir::operation::InstanceNorm &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::L2Normalization &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::L2Pool2D &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::LocalResponseNormalization &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::LogicalAnd &node)
+{
+  const auto input0_index{node.getInputs().at(ir::operation::LogicalAnd::Input::INPUT0)};
+  const auto input1_index{node.getInputs().at(ir::operation::LogicalAnd::Input::INPUT1)};
+
+  if (!(_ctx.at(input0_index).shape() == _ctx.at(input1_index).shape()))
+  {
+    const auto broadcast_rank =
+        std::max(_ctx.at(input0_index).shape().rank(), _ctx.at(input1_index).shape().rank());
+
+    // TODO remove const_cast later. For example, _ctx may need to be a non const variable or
+    //      a node to extend shape may be inserted in front of this operation
+    const_cast<ir::Shape &>(_ctx.at(input0_index).shape()).extendRank(broadcast_rank);
+    const_cast<ir::Shape &>(_ctx.at(input1_index).shape()).extendRank(broadcast_rank);
+  }
+}
+
+void ShapeFixer::visit(const ir::operation::LogicalNot &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::LogicalOr &node)
+{
+  const auto input0_index{node.getInputs().at(ir::operation::LogicalOr::Input::INPUT0)};
+  const auto input1_index{node.getInputs().at(ir::operation::LogicalOr::Input::INPUT1)};
+
+  if (!(_ctx.at(input0_index).shape() == _ctx.at(input1_index).shape()))
+  {
+    const auto broadcast_rank =
+        std::max(_ctx.at(input0_index).shape().rank(), _ctx.at(input1_index).shape().rank());
+
+    // TODO remove const_cast later. For example, _ctx may need to be a non const variable or
+    //      a node to extend shape may be inserted in front of this operation
+    const_cast<ir::Shape &>(_ctx.at(input0_index).shape()).extendRank(broadcast_rank);
+    const_cast<ir::Shape &>(_ctx.at(input1_index).shape()).extendRank(broadcast_rank);
+  }
+}
+
+void ShapeFixer::visit(const ir::operation::Logistic &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::LSTM &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Pack &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  _tensor_builder->dimCorrection(ofm_index, false);
+  for (const auto &inputs : node.getInputs())
+  {
+    _tensor_builder->dimCorrection(inputs, false);
+    const auto ofm_rank = _ctx.at(ofm_index).shape().rank();
+
+    // TODO remove const_cast later. For example, _ctx may need to be a non const variable or
+    //      a node to extend shape may be inserted in front of this operation
+    const_cast<ir::Shape &>(_ctx.at(inputs).shape()).extendRank(ofm_rank);
+  }
+}
+
+void ShapeFixer::visit(const ir::operation::Pad &node)
+{
+  const auto input_index{node.getInputs().at(ir::operation::Pad::Input::INPUT)};
+  const auto output_index{node.getOutputs().at(0)};
+  _tensor_builder->dimCorrection(input_index, false);
+  _tensor_builder->dimCorrection(output_index, false);
+}
+
+void ShapeFixer::visit(const ir::operation::Mul &node)
+{
+  const auto lhs_index{node.getInputs().at(ir::operation::Mul::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::Mul::Input::RHS)};
+
+  if (!(_ctx.at(lhs_index).shape() == _ctx.at(rhs_index).shape()))
+  {
+    const auto broadcast_rank =
+        std::max(_ctx.at(lhs_index).shape().rank(), _ctx.at(rhs_index).shape().rank());
+
+    // TODO remove const_cast later. For example, _ctx may need to be a non const variable or
+    //      a node to extend shape may be inserted in front of this operation
+    const_cast<ir::Shape &>(_ctx.at(lhs_index).shape()).extendRank(broadcast_rank);
+    const_cast<ir::Shape &>(_ctx.at(rhs_index).shape()).extendRank(broadcast_rank);
+  }
+}
+
+void ShapeFixer::visit(const ir::operation::Neg &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Permute &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::PReLU &node)
+{
+  const auto ifm_index{node.getInputs().at(ir::operation::PReLU::Input::INPUT)};
+  const auto alpha_index{node.getInputs().at(ir::operation::PReLU::Input::ALPHA)};
+
+  if (!(_ctx.at(ifm_index).shape() == _ctx.at(alpha_index).shape()))
+  {
+    const auto broadcast_rank =
+        std::max(_ctx.at(ifm_index).shape().rank(), _ctx.at(alpha_index).shape().rank());
+    const_cast<ir::Shape &>(_ctx.at(ifm_index).shape()).extendRank(broadcast_rank);
+    const_cast<ir::Shape &>(_ctx.at(alpha_index).shape()).extendRank(broadcast_rank);
+  }
+}
+
+void ShapeFixer::visit(const ir::operation::ReduceMax &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::ReduceMin &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::ReduceSum &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::ReLU &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::ReLU1 &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::ReLU6 &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Reshape &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::Reshape::Input::INPUT)};
+
+  _tensor_builder->dimCorrection(input_index, false);
+  _tensor_builder->dimCorrection(output_index, false);
+}
+
+void ShapeFixer::visit(const ir::operation::ResizeBilinear &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::RNN &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Comparison &node)
+{
+  const auto input0_index{node.getInputs().at(ir::operation::Comparison::Input::INPUT0)};
+  const auto input1_index{node.getInputs().at(ir::operation::Comparison::Input::INPUT1)};
+
+  if (!(_ctx.at(input0_index).shape() == _ctx.at(input1_index).shape()))
+  {
+    const auto broadcast_rank =
+        std::max(_ctx.at(input0_index).shape().rank(), _ctx.at(input1_index).shape().rank());
+
+    // TODO remove const_cast later. For example, _ctx may need to be a non const variable or
+    //      a node to extend shape may be inserted in front of this operation
+    const_cast<ir::Shape &>(_ctx.at(input0_index).shape()).extendRank(broadcast_rank);
+    const_cast<ir::Shape &>(_ctx.at(input1_index).shape()).extendRank(broadcast_rank);
+  }
+}
+
+void ShapeFixer::visit(const ir::operation::RSQRT &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Squeeze &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::Squeeze::Input::INPUT)};
+  _tensor_builder->dimCorrection(input_index, false);
+  _tensor_builder->dimCorrection(output_index, false);
+}
+
+void ShapeFixer::visit(const ir::operation::Tanh &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Slice &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::StridedSlice &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::StridedSlice::Input::INPUT)};
+  _tensor_builder->dimCorrection(ofm_index, false);
+  _tensor_builder->dimCorrection(ifm_index, false);
+}
+
+void ShapeFixer::visit(const ir::operation::Softmax &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::SpaceToBatchND &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::SpaceToBatchND::Input::INPUT)};
+  _tensor_builder->dimCorrection(ofm_index, false);
+  _tensor_builder->dimCorrection(ifm_index, false);
+}
+
+void ShapeFixer::visit(const ir::operation::SpaceToDepth &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Split &node)
+{
+  const auto input_index{node.getInputs().at(ir::operation::Split::Input::INPUT)};
+  _tensor_builder->dimCorrection(input_index, false);
+  for (const auto &output : node.getOutputs())
+    _tensor_builder->dimCorrection(output, false);
+}
+
+void ShapeFixer::visit(const ir::operation::SQRT &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::SquaredDifference &node)
+{
+  const auto lhs_index{node.getInputs().at(ir::operation::SquaredDifference::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::SquaredDifference::Input::RHS)};
+
+  if (!(_ctx.at(lhs_index).shape() == _ctx.at(rhs_index).shape()))
+  {
+    const auto broadcast_rank =
+        std::max(_ctx.at(lhs_index).shape().rank(), _ctx.at(rhs_index).shape().rank());
+
+    // TODO remove const_cast later. For example, _ctx may need to be a non const variable or
+    //      a node to extend shape may be inserted in front of this operation
+    const_cast<ir::Shape &>(_ctx.at(lhs_index).shape()).extendRank(broadcast_rank);
+    const_cast<ir::Shape &>(_ctx.at(rhs_index).shape()).extendRank(broadcast_rank);
+  }
+}
+
+void ShapeFixer::visit(const ir::operation::Sub &node)
+{
+  const auto lhs_index{node.getInputs().at(ir::operation::Sub::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::Sub::Input::RHS)};
+
+  if (!(_ctx.at(lhs_index).shape() == _ctx.at(rhs_index).shape()))
+  {
+    const auto broadcast_rank =
+        std::max(_ctx.at(lhs_index).shape().rank(), _ctx.at(rhs_index).shape().rank());
+    // TODO remove const_cast later. For example, _ctx may need to be a non const variable or
+    //      a node to extend shape may be inserted in front of this operation
+    const_cast<ir::Shape &>(_ctx.at(lhs_index).shape()).extendRank(broadcast_rank);
+    const_cast<ir::Shape &>(_ctx.at(rhs_index).shape()).extendRank(broadcast_rank);
+  }
+}
+
+void ShapeFixer::visit(const ir::operation::TransposeConv &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Transpose &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Unpack &node)
+{
+  const auto input_index{node.getInputs().at(ir::operation::Unpack::Input::INPUT)};
+  _tensor_builder->dimCorrection(input_index, false);
+  for (const auto &output_index : node.getOutputs())
+    _tensor_builder->dimCorrection(output_index, false);
+}
+
+void ShapeFixer::visit(const ir::operation::Add &node)
+{
+  const auto lhs_index{node.getInputs().at(ir::operation::Add::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::Add::Input::RHS)};
+
+  if (!(_ctx.at(lhs_index).shape() == _ctx.at(rhs_index).shape()))
+  {
+    const auto broadcast_rank =
+        std::max(_ctx.at(lhs_index).shape().rank(), _ctx.at(rhs_index).shape().rank());
+    const_cast<ir::Shape &>(_ctx.at(lhs_index).shape()).extendRank(broadcast_rank);
+    const_cast<ir::Shape &>(_ctx.at(rhs_index).shape()).extendRank(broadcast_rank);
+  }
+}
+
+void ShapeFixer::visit(const ir::operation::Div &node)
+{
+  const auto lhs_index{node.getInputs().at(ir::operation::Div::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::Div::Input::RHS)};
+
+  if (!(_ctx.at(lhs_index).shape() == _ctx.at(rhs_index).shape()))
+  {
+    const auto broadcast_rank =
+        std::max(_ctx.at(lhs_index).shape().rank(), _ctx.at(rhs_index).shape().rank());
+
+    // TODO remove const_cast later. For example, _ctx may need to be a non const variable or
+    //      a node to extend shape may be inserted in front of this operation
+    const_cast<ir::Shape &>(_ctx.at(lhs_index).shape()).extendRank(broadcast_rank);
+    const_cast<ir::Shape &>(_ctx.at(rhs_index).shape()).extendRank(broadcast_rank);
+  }
+}
+
+void ShapeFixer::visit(const ir::operation::Min &node)
+{
+  const auto lhs_index{node.getInputs().at(ir::operation::Min::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::Min::Input::RHS)};
+
+  if (!(_ctx.at(lhs_index).shape() == _ctx.at(rhs_index).shape()))
+  {
+    const auto broadcast_rank =
+        std::max(_ctx.at(lhs_index).shape().rank(), _ctx.at(rhs_index).shape().rank());
+
+    // TODO remove const_cast later. For example, _ctx may need to be a non const variable or
+    //      a node to extend shape may be inserted in front of this operation
+    const_cast<ir::Shape &>(_ctx.at(lhs_index).shape()).extendRank(broadcast_rank);
+    const_cast<ir::Shape &>(_ctx.at(rhs_index).shape()).extendRank(broadcast_rank);
+  }
+}
+
+void ShapeFixer::visit(const ir::operation::Max &node)
+{
+  const auto lhs_index{node.getInputs().at(ir::operation::Max::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::Max::Input::RHS)};
+
+  if (!(_ctx.at(lhs_index).shape() == _ctx.at(rhs_index).shape()))
+  {
+    const auto broadcast_rank =
+        std::max(_ctx.at(lhs_index).shape().rank(), _ctx.at(rhs_index).shape().rank());
+
+    // TODO remove const_cast later. For example, _ctx may need to be a non const variable or
+    //      a node to extend shape may be inserted in front of this operation
+    const_cast<ir::Shape &>(_ctx.at(lhs_index).shape()).extendRank(broadcast_rank);
+    const_cast<ir::Shape &>(_ctx.at(rhs_index).shape()).extendRank(broadcast_rank);
+  }
+}
+
+} // namespace acl_neon
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/acl_neon/ShapeFixer.h b/runtime/neurun/backend/acl_neon/ShapeFixer.h
new file mode 100644
index 000000000..aa1f8f75a
--- /dev/null
+++ b/runtime/neurun/backend/acl_neon/ShapeFixer.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ACL_NEON_SHAPE_FIXER_H__
+#define __NEURUN_BACKEND_ACL_NEON_SHAPE_FIXER_H__
+
+#include <backend/IShapeFixer.h>
+
+#include "ir/Operands.h"
+#include "TensorBuilder.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_neon
+{
+
+class ShapeFixer : public IShapeFixer
+{
+public:
+  ShapeFixer(const ir::Operands &ctx, const std::shared_ptr<TensorBuilder> &tensor_builder);
+
+  void visit(const ir::operation::Abs &) override;
+  void visit(const ir::operation::ArgMax &) override;
+  void visit(const ir::operation::BatchToSpaceND &) override;
+  void visit(const ir::operation::Cast &) override;
+  void visit(const ir::operation::Conv2D &) override;
+  void visit(const ir::operation::DepthToSpace &) override;
+  void visit(const ir::operation::DepthwiseConv2D &) override;
+  void visit(const ir::operation::Dequantize &) override;
+  void visit(const ir::operation::MaxPool2D &) override;
+  void visit(const ir::operation::Mean &) override;
+  void visit(const ir::operation::AvgPool2D &) override;
+  void visit(const ir::operation::Concat &) override;
+  void visit(const ir::operation::EmbeddingLookup &) override;
+  void visit(const ir::operation::Exp &) override;
+  void visit(const ir::operation::Floor &) override;
+  void visit(const ir::operation::FullyConnected &) override;
+  void visit(const ir::operation::Gather &) override;
+  void visit(const ir::operation::HashtableLookup &) override;
+  void visit(const ir::operation::InstanceNorm &) override;
+  void visit(const ir::operation::L2Normalization &) override;
+  void visit(const ir::operation::L2Pool2D &) override;
+  void visit(const ir::operation::LocalResponseNormalization &) override;
+  void visit(const ir::operation::LogicalAnd &) override;
+  void visit(const ir::operation::LogicalNot &) override;
+  void visit(const ir::operation::LogicalOr &) override;
+  void visit(const ir::operation::Logistic &) override;
+  void visit(const ir::operation::LSTM &) override;
+  void visit(const ir::operation::Mul &) override;
+  void visit(const ir::operation::Neg &) override;
+  void visit(const ir::operation::Pack &) override;
+  void visit(const ir::operation::Pad &) override;
+  void visit(const ir::operation::Permute &) override;
+  void visit(const ir::operation::PReLU &) override;
+  void visit(const ir::operation::ReduceMax &) override;
+  void visit(const ir::operation::ReduceMin &) override;
+  void visit(const ir::operation::ReduceSum &) override;
+  void visit(const ir::operation::ReLU &) override;
+  void visit(const ir::operation::ReLU1 &) override;
+  void visit(const ir::operation::ReLU6 &) override;
+  void visit(const ir::operation::Reshape &) override;
+  void visit(const ir::operation::ResizeBilinear &) override;
+  void visit(const ir::operation::RNN &) override;
+  void visit(const ir::operation::RSQRT &) override;
+  void visit(const ir::operation::Squeeze &) override;
+  void visit(const ir::operation::Tanh &) override;
+  void visit(const ir::operation::Softmax &) override;
+  void visit(const ir::operation::SpaceToBatchND &) override;
+  void visit(const ir::operation::SpaceToDepth &) override;
+  void visit(const ir::operation::Split &) override;
+  void visit(const ir::operation::SQRT &) override;
+  void visit(const ir::operation::SquaredDifference &) override;
+  void visit(const ir::operation::Sub &) override;
+  void visit(const ir::operation::Slice &) override;
+  void visit(const ir::operation::StridedSlice &) override;
+  void visit(const ir::operation::TransposeConv &) override;
+  void visit(const ir::operation::Transpose &) override;
+  void visit(const ir::operation::Unpack &) override;
+  void visit(const ir::operation::Add &) override;
+  void visit(const ir::operation::Div &) override;
+  void visit(const ir::operation::Comparison &) override;
+  void visit(const ir::operation::Min &) override;
+  void visit(const ir::operation::Max &) override;
+
+private:
+  const ir::Operands &_ctx;
+  std::shared_ptr<TensorBuilder> _tensor_builder;
+};
+
+} // namespace acl_neon
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ACL_NEON_SHAPE_FIXER_H__
diff --git a/runtime/neurun/backend/acl_neon/TensorBuilder.h b/runtime/neurun/backend/acl_neon/TensorBuilder.h
new file mode 100644
index 000000000..0a6b4921d
--- /dev/null
+++ b/runtime/neurun/backend/acl_neon/TensorBuilder.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ACL_NEON_TENSOR_BUILDER_H__
+#define __NEURUN_BACKEND_ACL_NEON_TENSOR_BUILDER_H__
+
+#include <TemplTensorBuilder.h>
+
+#include "operand/NETensor.h"
+#include "operand/NESubTensor.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_neon
+{
+
+using TensorBuilder =
+    acl_common::TemplTensorBuilder<operand::INETensor, operand::NETensor, operand::NESubTensor>;
+
+} // namespace acl_neon
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ACL_NEON_TENSOR_BUILDER_H__
diff --git a/runtime/neurun/backend/acl_neon/TensorManager.h b/runtime/neurun/backend/acl_neon/TensorManager.h
new file mode 100644
index 000000000..725275cef
--- /dev/null
+++ b/runtime/neurun/backend/acl_neon/TensorManager.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ACL_NEON_TENSOR_MANAGER_H__
+#define __NEURUN_BACKEND_ACL_NEON_TENSOR_MANAGER_H__
+
+#include <arm_compute/runtime/Allocator.h>
+#include <arm_compute/runtime/PoolManager.h>
+#include <arm_compute/runtime/OffsetLifetimeManager.h>
+#include <arm_compute/runtime/MemoryManagerOnDemand.h>
+#include <arm_compute/runtime/MemoryGroup.h>
+
+#include <AclMemoryManager.h>
+#include <AclLinearMemoryManager.h>
+#include <AclInternalBufferManager.h>
+#include <AclTensorManager.h>
+
+#include "operand/NETensor.h"
+#include "operand/NESubTensor.h"
+
+#include "util/logging.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_neon
+{
+
+using MemoryManager =
+    acl_common::AclMemoryManager<operand::INETensor, operand::NETensor, operand::NESubTensor>;
+
+using LinearMemoryManager = acl_common::AclLinearMemoryManager<
+    operand::INETensor, operand::NETensor, operand::NESubTensor,
+    ::arm_compute::MemoryManagerOnDemand, ::arm_compute::PoolManager,
+    ::arm_compute::OffsetLifetimeManager, ::arm_compute::Allocator, ::arm_compute::MemoryGroup>;
+
+using InternalBufferManager = acl_common::AclInternalBufferManager<
+    ::arm_compute::MemoryManagerOnDemand, ::arm_compute::PoolManager,
+    ::arm_compute::OffsetLifetimeManager, ::arm_compute::Allocator>;
+
+using TensorManager = acl_common::AclTensorManager<acl_neon::operand::INETensor, operand::NETensor,
+                                                   operand::NESubTensor>;
+
+TensorManager *createTensorManager()
+{
+  const std::string executor_str = util::getConfigString(util::config::EXECUTOR);
+  if (executor_str == "Linear")
+  {
+    VERBOSE(acl_neon_createTensorManager) << "AclTensorManager as Linear" << std::endl;
+    return new TensorManager(new MemoryManager(), new LinearMemoryManager(),
+                             new InternalBufferManager());
+  }
+  else
+  {
+    VERBOSE(acl_neon_createTensorManager) << "AclTensorManager" << std::endl;
+    return new TensorManager(new MemoryManager(), new MemoryManager(), new InternalBufferManager());
+  }
+}
+
+} // namespace acl_neon
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ACL_NEON_TENSOR_MANAGER_H__
diff --git a/runtime/neurun/backend/acl_neon/TensorRegister.cc b/runtime/neurun/backend/acl_neon/TensorRegister.cc
new file mode 100644
index 000000000..fe766cdf9
--- /dev/null
+++ b/runtime/neurun/backend/acl_neon/TensorRegister.cc
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "TensorRegister.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_neon
+{
+
+// NOTHING
+
+} // srcn
+} // backend
+} // neurun
diff --git a/runtime/neurun/backend/acl_neon/TensorRegister.h b/runtime/neurun/backend/acl_neon/TensorRegister.h
new file mode 100644
index 000000000..115e05dee
--- /dev/null
+++ b/runtime/neurun/backend/acl_neon/TensorRegister.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ACL_NEON_TENSOR_REGISTER_H__
+#define __NEURUN_BACKEND_ACL_NEON_TENSOR_REGISTER_H__
+
+#include <AclTensorRegister.h>
+#include <misc/polymorphic_downcast.h>
+#include "TensorBuilder.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_neon
+{
+
+class TensorRegister : public acl_common::AclTensorRegister
+{
+public:
+  TensorRegister(const ir::Operands &operands, const std::shared_ptr<TensorBuilder> &tensor_builder)
+      : acl_common::AclTensorRegister{operands, tensor_builder}
+  {
+    // DO NOTHING
+  }
+
+  void setUsesCount(const ir::OperandIndex &ind, size_t num_uses) const override
+  {
+    nnfw::misc::polymorphic_downcast<TensorBuilder *>(tensor_builder().get())
+        ->setUsesCount(ind, num_uses);
+  }
+};
+
+} // namespace acl_neon
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ACL_NEON_TENSOR_REGISTER_H__
diff --git a/runtime/neurun/backend/acl_neon/operand/INETensor.cc b/runtime/neurun/backend/acl_neon/operand/INETensor.cc
new file mode 100644
index 000000000..fdb20970d
--- /dev/null
+++ b/runtime/neurun/backend/acl_neon/operand/INETensor.cc
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "INETensor.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_neon
+{
+namespace operand
+{
+
+void INETensor::access(const std::function<void(ITensor &tensor)> &fn) { fn(*this); }
+
+} // namespace operand
+} // namespace acl_neon
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/acl_neon/operand/INETensor.h b/runtime/neurun/backend/acl_neon/operand/INETensor.h
new file mode 100644
index 000000000..22b1140cf
--- /dev/null
+++ b/runtime/neurun/backend/acl_neon/operand/INETensor.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ACL_NEON_OPERAND_I_NE_TENSOR_H__
+#define __NEURUN_BACKEND_ACL_NEON_OPERAND_I_NE_TENSOR_H__
+
+#include <arm_compute/core/ITensor.h>
+
+#include <IACLTensor.h>
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_neon
+{
+namespace operand
+{
+
+class INETensor : public acl_common::IACLTensor
+{
+public:
+  const arm_compute::ITensor *handle() const override = 0;
+  arm_compute::ITensor *handle() override = 0;
+  void access(const std::function<void(ITensor &tensor)> &fn) final;
+};
+
+} // namespace operand
+} // namespace acl_neon
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ACL_NEON_OPERAND_I_NE_TENSOR_H__
diff --git a/runtime/neurun/backend/acl_neon/operand/NESubTensor.cc b/runtime/neurun/backend/acl_neon/operand/NESubTensor.cc
new file mode 100644
index 000000000..a36af609c
--- /dev/null
+++ b/runtime/neurun/backend/acl_neon/operand/NESubTensor.cc
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "NESubTensor.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_neon
+{
+namespace operand
+{
+
+NESubTensor::NESubTensor(INETensor *parent, const arm_compute::TensorShape &tensor_shape,
+                         const arm_compute::Coordinates &coords, size_t rank, bool extend_parent)
+    : _ne_sub_tensor(std::make_shared<arm_compute::SubTensor>(parent->handle(), tensor_shape,
+                                                              coords, extend_parent)),
+      _rank{rank}
+{
+  // DO NOTHING
+}
+
+const arm_compute::SubTensor *NESubTensor::handle() const { return _ne_sub_tensor.get(); }
+
+arm_compute::SubTensor *NESubTensor::handle() { return _ne_sub_tensor.get(); }
+
+} // namespace operand
+} // namespace acl_neon
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/acl_neon/operand/NESubTensor.h b/runtime/neurun/backend/acl_neon/operand/NESubTensor.h
new file mode 100644
index 000000000..010e4deda
--- /dev/null
+++ b/runtime/neurun/backend/acl_neon/operand/NESubTensor.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ACL_NEON_OPERAND_NE_SUB_TENSOR_H__
+#define __NEURUN_BACKEND_ACL_NEON_OPERAND_NE_SUB_TENSOR_H__
+
+#include <arm_compute/runtime/SubTensor.h>
+#include "INETensor.h"
+#include "compiler/SubTensorInfo.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_neon
+{
+namespace operand
+{
+
+class NESubTensor : public INETensor
+{
+public:
+  NESubTensor() = delete;
+
+public:
+  NESubTensor(INETensor *parent, const arm_compute::TensorShape &tensor_shape,
+              const arm_compute::Coordinates &coords, size_t rank, bool extend_parent = false);
+
+public:
+  size_t num_dimensions() const final { return _rank; }
+
+public:
+  const arm_compute::SubTensor *handle() const override;
+  arm_compute::SubTensor *handle() override;
+
+public:
+  // This method is used to prevent the use of memcpy for SubTensor
+  bool has_padding() const override { return true; }
+
+private:
+  std::shared_ptr<arm_compute::SubTensor> _ne_sub_tensor;
+  size_t _rank;
+};
+
+} // namespace operand
+} // namespace acl_neon
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ACL_NEON_OPERAND_NE_SUB_TENSOR_H__
diff --git a/runtime/neurun/backend/acl_neon/operand/NETensor.cc b/runtime/neurun/backend/acl_neon/operand/NETensor.cc
new file mode 100644
index 000000000..8a9ece88f
--- /dev/null
+++ b/runtime/neurun/backend/acl_neon/operand/NETensor.cc
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <arm_compute/runtime/Memory.h>
+#include <arm_compute/runtime/MemoryRegion.h>
+#include "NETensor.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_neon
+{
+namespace operand
+{
+
+NETensor::NETensor(const arm_compute::TensorInfo &info, size_t rank, size_t num_uses)
+    : _ne_tensor(std::make_shared<arm_compute::Tensor>()), _rank{rank}, _num_uses{num_uses}
+{
+  allocator()->init(info);
+}
+
+const arm_compute::Tensor *NETensor::handle() const { return _ne_tensor.get(); }
+
+arm_compute::Tensor *NETensor::handle() { return _ne_tensor.get(); }
+
+arm_compute::TensorAllocator *NETensor::allocator() { return _ne_tensor->allocator(); }
+
+} // namespace operand
+} // namespace acl_neon
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/acl_neon/operand/NETensor.h b/runtime/neurun/backend/acl_neon/operand/NETensor.h
new file mode 100644
index 000000000..3de4695e9
--- /dev/null
+++ b/runtime/neurun/backend/acl_neon/operand/NETensor.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ACL_NEON_OPERAND_NE_TENSOR_H__
+#define __NEURUN_BACKEND_ACL_NEON_OPERAND_NE_TENSOR_H__
+
+#include <arm_compute/core/TensorInfo.h>
+#include <arm_compute/runtime/Tensor.h>
+#include "arm_compute/runtime/TensorAllocator.h"
+#include "INETensor.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_neon
+{
+namespace operand
+{
+
+class NETensor : public INETensor
+{
+public:
+  NETensor() = delete;
+
+public:
+  NETensor(const arm_compute::TensorInfo &info, size_t rank, size_t num_uses);
+
+public:
+  size_t num_dimensions() const final { return _rank; }
+
+public:
+  const arm_compute::Tensor *handle() const override;
+  arm_compute::Tensor *handle() override;
+  size_t num_uses() const { return _num_uses; }
+
+public:
+  arm_compute::TensorAllocator *allocator();
+
+private:
+  std::shared_ptr<arm_compute::Tensor> _ne_tensor;
+  size_t _rank;
+  size_t _num_uses;
+};
+
+} // namespace operand
+} // namespace acl_neon
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ACL_NEON_OPERAND_NE_TENSOR_H__
diff --git a/runtime/neurun/backend/cpu/Backend.h b/runtime/neurun/backend/cpu/Backend.h
new file mode 100644
index 000000000..e52a776b9
--- /dev/null
+++ b/runtime/neurun/backend/cpu/Backend.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_CPU_BACKEND_H__
+#define __NEURUN_BACKEND_CPU_BACKEND_H__
+
+#include <memory>
+#include <backend/Backend.h>
+#include <ir/Operands.h>
+
+#include "Config.h"
+#include "ConstantInitializer.h"
+#include "KernelGenerator.h"
+#include "ShapeFixer.h"
+#include "TensorRegister.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+
+class Backend : public ::neurun::backend::Backend
+{
+public:
+  Backend() : _config{std::make_shared<Config>()} {}
+
+  std::shared_ptr<IConfig> config() const override { return _config; }
+
+  std::unique_ptr<BackendContext>
+  newContext(const ir::Operands &operands,
+             const std::shared_ptr<custom::IKernelBuilder> &kb) const override
+  {
+    auto tensor_builder = std::make_shared<TensorBuilder>();
+    return std::unique_ptr<BackendContext>{new BackendContext{
+        this, tensor_builder, std::make_shared<ConstantInitializer>(operands, tensor_builder),
+        std::make_shared<KernelGenerator>(operands, tensor_builder, kb),
+        std::make_shared<ShapeFixer>(operands, tensor_builder),
+        std::make_shared<TensorRegister>(operands, tensor_builder)}};
+  }
+
+private:
+  std::shared_ptr<IConfig> _config;
+};
+
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_CPU_BACKEND_H__
diff --git a/runtime/neurun/backend/cpu/CMakeLists.txt b/runtime/neurun/backend/cpu/CMakeLists.txt
new file mode 100644
index 000000000..82c838b15
--- /dev/null
+++ b/runtime/neurun/backend/cpu/CMakeLists.txt
@@ -0,0 +1,16 @@
+set(LIB_NEURUN_BACKEND_CPU neurun_backend_cpu)
+
+file(GLOB_RECURSE SOURCES "*.cc")
+
+add_library(${LIB_NEURUN_BACKEND_CPU} SHARED ${SOURCES})
+
+target_link_libraries(${LIB_NEURUN_BACKEND_CPU} PUBLIC nnfw_lib_cpp14)
+target_link_libraries(${LIB_NEURUN_BACKEND_CPU} PRIVATE nnfw_lib_misc nnfw_lib_cker)
+target_link_libraries(${LIB_NEURUN_BACKEND_CPU} PRIVATE neurun_core)
+target_link_libraries(${LIB_NEURUN_BACKEND_CPU} PRIVATE ${LIB_NEURUN_BACKEND_CPU_COMMON})
+target_link_libraries(${LIB_NEURUN_BACKEND_CPU} PRIVATE nnfw_common)
+target_link_libraries(${LIB_NEURUN_BACKEND_CPU} PRIVATE nnfw_coverage)
+
+set_target_properties(${LIB_NEURUN_BACKEND_CPU} PROPERTIES OUTPUT_NAME backend_cpu)
+
+install(TARGETS ${LIB_NEURUN_BACKEND_CPU} DESTINATION lib)
diff --git a/runtime/neurun/backend/cpu/Config.cc b/runtime/neurun/backend/cpu/Config.cc
new file mode 100644
index 000000000..39127406f
--- /dev/null
+++ b/runtime/neurun/backend/cpu/Config.cc
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "Config.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+
+bool Config::initialize() { return true; }
+
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/cpu/Config.h b/runtime/neurun/backend/cpu/Config.h
new file mode 100644
index 000000000..be303b556
--- /dev/null
+++ b/runtime/neurun/backend/cpu/Config.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_CPU_CONFIG_H__
+#define __NEURUN_BACKEND_CPU_CONFIG_H__
+
+#include <backend/IConfig.h>
+#include <cpp14/memory.h>
+#include <util/ITimer.h>
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+
+class Config : public IConfig
+{
+public:
+  std::string id() override { return "cpu"; }
+  bool initialize() override;
+  bool SupportPermutation() override { return true; }
+  bool SupportSubTensorAlloc() override
+  {
+    // NOTE CPU allocator cannot support subtensor allocation yet
+    return false;
+  }
+
+  std::unique_ptr<util::ITimer> timer() override
+  {
+    return nnfw::cpp14::make_unique<util::CPUTimer>();
+  }
+};
+
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_CPU_CONFIG_H__
diff --git a/runtime/neurun/backend/cpu/ConstantInitializer.cc b/runtime/neurun/backend/cpu/ConstantInitializer.cc
new file mode 100644
index 000000000..e6e7d8deb
--- /dev/null
+++ b/runtime/neurun/backend/cpu/ConstantInitializer.cc
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ConstantInitializer.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+
+ConstantInitializer::ConstantInitializer(const ir::Operands &operands,
+                                         const std::shared_ptr<TensorBuilder> &tensor_builder)
+    : _operands{operands}, _tensor_builder{tensor_builder}
+{
+  // DO NOTHING
+}
+
+void ConstantInitializer::visit(const ir::operation::Conv2D &node)
+{
+  const auto &kernel_index = node.getInputs().at(ir::operation::Conv2D::KERNEL);
+  const auto &kernel_obj = _operands.at(kernel_index);
+  registerCopyInitializer(kernel_index, kernel_obj);
+
+  const auto &bias_index = node.getInputs().at(ir::operation::Conv2D::BIAS);
+  const auto &bias_obj = _operands.at(bias_index);
+  registerCopyInitializer(bias_index, bias_obj);
+}
+
+void ConstantInitializer::visit(const ir::operation::DepthwiseConv2D &node)
+{
+  const auto &kernel_index = node.getInputs().at(ir::operation::DepthwiseConv2D::KERNEL);
+  const auto &kernel_obj = _operands.at(kernel_index);
+  registerCopyInitializer(kernel_index, kernel_obj);
+
+  const auto &bias_index = node.getInputs().at(ir::operation::DepthwiseConv2D::BIAS);
+  const auto &bias_obj = _operands.at(bias_index);
+  registerCopyInitializer(bias_index, bias_obj);
+}
+
+void ConstantInitializer::visit(const ir::operation::FullyConnected &node)
+{
+  const auto &weight_index = node.getInputs().at(ir::operation::FullyConnected::WEIGHT);
+  const auto &weight_obj = _operands.at(weight_index);
+  registerCopyInitializer(weight_index, weight_obj);
+
+  const auto &bias_index = node.getInputs().at(ir::operation::FullyConnected::BIAS);
+  const auto &bias_obj = _operands.at(bias_index);
+  registerCopyInitializer(bias_index, bias_obj);
+}
+
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/cpu/ConstantInitializer.h b/runtime/neurun/backend/cpu/ConstantInitializer.h
new file mode 100644
index 000000000..a53321997
--- /dev/null
+++ b/runtime/neurun/backend/cpu/ConstantInitializer.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_COMPILER_CPU_CONSTANT_INITIALIZER_H__
+#define __NEURUN_COMPILER_CPU_CONSTANT_INITIALIZER_H__
+
+#include <backend/IConstantInitializer.h>
+#include <ir/Operands.h>
+#include "TensorBuilder.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+
+class ConstantInitializer : public IConstantInitializer
+{
+public:
+  ConstantInitializer(const ir::Operands &operands,
+                      const std::shared_ptr<TensorBuilder> &tensor_builder);
+
+public:
+  void visit(const ir::operation::Conv2D &) override;
+  void visit(const ir::operation::DepthwiseConv2D &) override;
+  void visit(const ir::operation::FullyConnected &) override;
+
+private:
+  const ir::Operands &operands() const override { return _operands; }
+  std::shared_ptr<ITensorBuilder> tensor_builder() const override { return _tensor_builder; }
+
+private:
+  const ir::Operands &_operands;
+  std::shared_ptr<TensorBuilder> _tensor_builder;
+};
+
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_COMPILER_CPU_CONSTANT_INITIALIZER_H__
diff --git a/runtime/neurun/backend/cpu/KernelGenerator.cc b/runtime/neurun/backend/cpu/KernelGenerator.cc
new file mode 100644
index 000000000..09bd1367d
--- /dev/null
+++ b/runtime/neurun/backend/cpu/KernelGenerator.cc
@@ -0,0 +1,624 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "KernelGenerator.h"
+
+#include <stdexcept>
+
+#include "cpp14/memory.h"
+#include "util/Padding.h"
+#include "kernel/OperationUtils.h"
+#include "kernel/ConvolutionLayer.h"
+#include "kernel/AvgPoolLayer.h"
+#include "kernel/MaxPoolLayer.h"
+#include "kernel/ConcatLayer.h"
+#include "kernel/FullyConnectedLayer.h"
+#include "kernel/ReshapeLayer.h"
+#include "kernel/SoftMaxLayer.h"
+#include "kernel/PermuteLayer.h"
+#include "kernel/DepthwiseConvolutionLayer.h"
+#include "kernel/AddLayer.h"
+#include "kernel/SubLayer.h"
+#include "kernel/MulLayer.h"
+#include "kernel/GatherLayer.h"
+#include "kernel/LogisticLayer.h"
+#include "kernel/PadLayer.h"
+
+#include <backend/Backend.h>
+#include <backend/IConfig.h>
+
+#include "util/logging.h"
+
+#include "util/Utils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+
+KernelGenerator::KernelGenerator(
+    const ir::Operands &operand_ctx, const std::shared_ptr<TensorBuilder> &tensor_builder,
+    const std::shared_ptr<backend::custom::IKernelBuilder> &kernel_builer)
+    : _ctx(operand_ctx), _tensor_builder(tensor_builder), _kernel_builder(kernel_builer),
+      _current_subg_layout(ir::Layout::UNKNOWN)
+{
+  // DO NOTHING
+}
+
+void KernelGenerator::visit(const ir::OpSequence &op_seq)
+{
+  _current_subg_layout = op_seq.getLayout();
+  for (const auto &e : op_seq.operations())
+  {
+    const auto &node = *(e.node);
+    _tensor_builder->preVisit(node);
+    node.accept(*this);
+    _tensor_builder->postVisit(node);
+  }
+}
+
+void KernelGenerator::visit(const ir::operation::Conv2D &node)
+{
+  using ir::operation::Conv2D;
+
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(Conv2D::Input::INPUT)};
+  const auto ker_index{node.getInputs().at(Conv2D::Input::KERNEL)};
+  const auto bias_index{node.getInputs().at(Conv2D::Input::BIAS)};
+
+  const auto stride = node.param().stride;
+  const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature(_current_subg_layout);
+  const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature(_current_subg_layout);
+  // Kernel format is [depth_out, kernel_height, kernel_width, depth_in].
+  const auto &ker_shape = _ctx.at(ker_index).shape();
+  const auto ker_height = ker_shape.dim(1);
+  const auto ker_width = ker_shape.dim(2);
+  const auto padding = neurun::util::calculatePadding(node.param().padding, ifm_shape, ofm_shape,
+                                                      stride, ker_width, ker_height);
+  const auto activation = node.param().activation;
+
+  const auto ofm_backend_descr =
+      ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(ofm_index), _current_subg_layout);
+  const auto ifm_backend_descr =
+      ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(ifm_index), _current_subg_layout);
+  const auto ker_backend_descr =
+      ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(ker_index), ir::Layout::UNKNOWN);
+  const auto bias_backend_descr =
+      ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(bias_index), ir::Layout::UNKNOWN);
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index);
+  auto ifm_alloc = _tensor_builder->at(ifm_index);
+  auto ker_alloc = _tensor_builder->at(ker_index);
+  auto bias_alloc = _tensor_builder->at(bias_index);
+
+  auto fn = nnfw::cpp14::make_unique<::neurun::backend::cpu::kernel::ConvolutionLayer>();
+
+  fn->configure(ifm_alloc->buffer(), ifm_backend_descr, ker_alloc->buffer(), ker_backend_descr,
+                bias_alloc->buffer(), bias_backend_descr, padding.left, padding.right, padding.top,
+                padding.bottom, stride.horizontal, stride.vertical, activation, ofm_alloc->buffer(),
+                ofm_backend_descr);
+
+  _execution_builder->append(std::move(fn));
+}
+
+void KernelGenerator::visit(const ir::operation::DepthwiseConv2D &node)
+{
+  using ir::operation::DepthwiseConv2D;
+
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(DepthwiseConv2D::Input::INPUT)};
+  const auto ker_index{node.getInputs().at(DepthwiseConv2D::Input::KERNEL)};
+  const auto bias_index{node.getInputs().at(DepthwiseConv2D::Input::BIAS)};
+
+  const auto stride = node.param().stride;
+  const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature(_current_subg_layout);
+  const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature(_current_subg_layout);
+  // Kernel format is [1, kernel_height, kernel_width, depth_out].
+  const auto &ker_shape = _ctx.at(ker_index).shape();
+  const auto ker_height = ker_shape.dim(1);
+  const auto ker_width = ker_shape.dim(2);
+  const auto padding = neurun::util::calculatePadding(node.param().padding, ifm_shape, ofm_shape,
+                                                      stride, ker_width, ker_height);
+
+  const auto ofm_backend_descr =
+      ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(ofm_index), _current_subg_layout);
+  const auto ifm_backend_descr =
+      ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(ifm_index), _current_subg_layout);
+  const auto ker_backend_descr =
+      ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(ker_index), ir::Layout::UNKNOWN);
+  const auto bias_backend_descr =
+      ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(bias_index), ir::Layout::UNKNOWN);
+
+  const auto multiplier = node.param().multiplier;
+  const auto activation = node.param().activation;
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index);
+  auto ifm_alloc = _tensor_builder->at(ifm_index);
+  auto ker_alloc = _tensor_builder->at(ker_index);
+  auto bias_alloc = _tensor_builder->at(bias_index);
+
+  auto fn = nnfw::cpp14::make_unique<::neurun::backend::cpu::kernel::DepthwiseConvolutionLayer>();
+
+  fn->configure(ifm_alloc->buffer(), ifm_backend_descr, ker_alloc->buffer(), ker_backend_descr,
+                bias_alloc->buffer(), bias_backend_descr, padding.left, padding.right, padding.top,
+                padding.bottom, stride.horizontal, stride.vertical, multiplier, activation,
+                ofm_alloc->buffer(), ofm_backend_descr);
+
+  _execution_builder->append(std::move(fn));
+}
+
+void KernelGenerator::visit(const ir::operation::MaxPool2D &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::MaxPool2D::Input::INPUT)};
+
+  const auto kh = node.param().kh;
+  const auto kw = node.param().kw;
+
+  const auto stride = node.param().stride;
+  const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature(_current_subg_layout);
+  const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature(_current_subg_layout);
+  const auto padding =
+      neurun::util::calculatePadding(node.param().padding, ifm_shape, ofm_shape, stride, kw, kh);
+  const auto activation = node.param().activation;
+
+  const auto ofm_backend_descr =
+      ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(ofm_index), _current_subg_layout);
+  const auto ifm_backend_descr =
+      ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(ifm_index), _current_subg_layout);
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::neurun::backend::cpu::kernel::MaxPoolLayer>();
+
+  fn->configure(ifm_alloc->buffer(), ifm_backend_descr, padding.left, padding.right, padding.top,
+                padding.bottom, stride.horizontal, stride.vertical, kw, kh, activation,
+                ofm_alloc->buffer(), ofm_backend_descr);
+
+  _execution_builder->append(std::move(fn));
+}
+
+void KernelGenerator::visit(const ir::operation::AvgPool2D &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::AvgPool2D::Input::INPUT)};
+
+  const auto kh = node.param().kh;
+  const auto kw = node.param().kw;
+  const auto stride = node.param().stride;
+  const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature(_current_subg_layout);
+  const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature(_current_subg_layout);
+  const auto padding =
+      neurun::util::calculatePadding(node.param().padding, ifm_shape, ofm_shape, stride, kw, kh);
+  const auto activation = node.param().activation;
+
+  const auto ofm_backend_descr =
+      ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(ofm_index), _current_subg_layout);
+  const auto ifm_backend_descr =
+      ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(ifm_index), _current_subg_layout);
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto ifm_alloc = _tensor_builder->at(ifm_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::neurun::backend::cpu::kernel::AvgPoolLayer>();
+
+  fn->configure(ifm_alloc->buffer(), ifm_backend_descr, padding.left, padding.right, padding.top,
+                padding.bottom, stride.horizontal, stride.vertical, kw, kh, activation,
+                ofm_alloc->buffer(), ofm_backend_descr);
+
+  _execution_builder->append(std::move(fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Concat &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+
+  const auto rank = _ctx.at(ofm_index).shape().rank();
+  const auto axis =
+      ::neurun::backend::cpu::kernel::getAxis(rank, node.param().axis, _current_subg_layout);
+
+  const auto ofm_backend_descr =
+      ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(ofm_index), _current_subg_layout);
+  std::vector<::neurun::backend::cpu::kernel::TensorDescriptor> ifm_backend_descrs;
+  for (auto &in_idx : node.getInputs())
+    ifm_backend_descrs.emplace_back(
+        ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(in_idx), _current_subg_layout));
+
+  auto output_alloc = _tensor_builder->at(ofm_index).get();
+
+  std::vector<const uint8_t *> input_buffers;
+  for (auto &ifm_idx : node.getInputs())
+    input_buffers.emplace_back(_tensor_builder->at(ifm_idx).get()->buffer());
+
+  auto fn = nnfw::cpp14::make_unique<::neurun::backend::cpu::kernel::ConcatLayer>();
+
+  fn->configure(input_buffers, ifm_backend_descrs, axis, output_alloc->buffer(), ofm_backend_descr);
+
+  _execution_builder->append(std::move(fn));
+}
+
+void KernelGenerator::visit(const ir::operation::FullyConnected &node)
+{
+  using ir::operation::FullyConnected;
+
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(FullyConnected::Input::INPUT)};
+  const auto weight_index{node.getInputs().at(FullyConnected::Input::WEIGHT)};
+  const auto bias_index{node.getInputs().at(FullyConnected::Input::BIAS)};
+
+  const auto ofm_backend_descr = ::neurun::backend::cpu::kernel::getTensorDescriptor(
+      _ctx.at(output_index), _current_subg_layout);
+  const auto ifm_backend_descr = ::neurun::backend::cpu::kernel::getTensorDescriptor(
+      _ctx.at(input_index), _current_subg_layout);
+  const auto weight_backend_descr = ::neurun::backend::cpu::kernel::getTensorDescriptor(
+      _ctx.at(weight_index), ir::Layout::UNKNOWN);
+  const auto bias_backend_descr =
+      ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(bias_index), ir::Layout::UNKNOWN);
+
+  const auto activation = node.param().activation;
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input_alloc = _tensor_builder->at(input_index).get();
+  auto weight_alloc = _tensor_builder->at(weight_index).get();
+  auto bias_alloc = _tensor_builder->at(bias_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::neurun::backend::cpu::kernel::FullyConnectedLayer>();
+
+  fn->configure(input_alloc->buffer(), ifm_backend_descr, weight_alloc->buffer(),
+                weight_backend_descr, bias_alloc->buffer(), bias_backend_descr, activation,
+                output_alloc->buffer(), ofm_backend_descr);
+
+  _execution_builder->append(std::move(fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Reshape &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::Reshape::Input::INPUT)};
+
+  const auto ofm_backend_descr = ::neurun::backend::cpu::kernel::getTensorDescriptor(
+      _ctx.at(output_index), _current_subg_layout);
+  const auto ifm_backend_descr = ::neurun::backend::cpu::kernel::getTensorDescriptor(
+      _ctx.at(input_index), _current_subg_layout);
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input_alloc = _tensor_builder->at(input_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::neurun::backend::cpu::kernel::ReshapeLayer>();
+
+  fn->configure(input_alloc->buffer(), ifm_backend_descr, output_alloc->buffer(),
+                ofm_backend_descr);
+
+  _execution_builder->append(std::move(fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Squeeze &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::Squeeze::Input::INPUT)};
+
+  const auto ofm_backend_descr = ::neurun::backend::cpu::kernel::getTensorDescriptor(
+      _ctx.at(output_index), _current_subg_layout);
+  const auto ifm_backend_descr = ::neurun::backend::cpu::kernel::getTensorDescriptor(
+      _ctx.at(input_index), _current_subg_layout);
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input_alloc = _tensor_builder->at(input_index).get();
+
+  // Squeeze can share same kernel with reshape
+  auto fn = nnfw::cpp14::make_unique<::neurun::backend::cpu::kernel::ReshapeLayer>();
+
+  fn->configure(input_alloc->buffer(), ifm_backend_descr, output_alloc->buffer(),
+                ofm_backend_descr);
+
+  _execution_builder->append(std::move(fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Softmax &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::Softmax::Input::INPUT)};
+
+  const auto ofm_backend_descr = ::neurun::backend::cpu::kernel::getTensorDescriptor(
+      _ctx.at(output_index), _current_subg_layout);
+  const auto ifm_backend_descr = ::neurun::backend::cpu::kernel::getTensorDescriptor(
+      _ctx.at(input_index), _current_subg_layout);
+
+  const auto beta = node.param().beta;
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input_alloc = _tensor_builder->at(input_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::neurun::backend::cpu::kernel::SoftMaxLayer>();
+
+  fn->configure(input_alloc->buffer(), ifm_backend_descr, beta, output_alloc->buffer(),
+                ofm_backend_descr);
+
+  _execution_builder->append(std::move(fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Add &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto lhs_index{node.getInputs().at(ir::operation::Add::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::Add::Input::RHS)};
+
+  const auto ofm_backend_descr =
+      ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(ofm_index), _current_subg_layout);
+  const auto lhs_backend_descr =
+      ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(lhs_index), _current_subg_layout);
+  const auto rhs_backend_descr =
+      ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(rhs_index), _current_subg_layout);
+
+  const auto activation = node.param().activation;
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto lhs_alloc = _tensor_builder->at(lhs_index).get();
+  auto rhs_alloc = _tensor_builder->at(rhs_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::neurun::backend::cpu::kernel::AddLayer>();
+
+  fn->configure(lhs_alloc->buffer(), lhs_backend_descr, rhs_alloc->buffer(), rhs_backend_descr,
+                activation, ofm_alloc->buffer(), ofm_backend_descr);
+
+  _execution_builder->append(std::move(fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Gather &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::Gather::Input::INPUT)};
+  const auto indices_index{node.getInputs().at(ir::operation::Gather::Input::INDICES)};
+
+  const auto output_backend_descr = ::neurun::backend::cpu::kernel::getTensorDescriptor(
+      _ctx.at(output_index), _current_subg_layout);
+  const auto input_backend_descr = ::neurun::backend::cpu::kernel::getTensorDescriptor(
+      _ctx.at(input_index), _current_subg_layout);
+  const auto indices_backend_descr = ::neurun::backend::cpu::kernel::getTensorDescriptor(
+      _ctx.at(indices_index), _current_subg_layout);
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input_alloc = _tensor_builder->at(input_index).get();
+  auto indices_alloc = _tensor_builder->at(indices_index).get();
+
+  const auto backend_layout = output_alloc->layout();
+  UNUSED_RELEASE(backend_layout);
+
+  // NOTE The frontend layout and backend layout must be the same for this operation.
+  //      If not the same, we have to add a stage(?) to perform permutation of output tensor. It
+  //      is not not efficient even if it works well. If so, it would be better to set the
+  //      layout of these backend tensors to the same layout.
+  //      There is also one thing we have to think about. This operation depends on the layout of
+  //      a model. For example, if a model in NHWC has this operation as output rank == 4, indices
+  //      rank == 2 and axis == 2, this operation should work as the axis W and C, but the axis W
+  //      and C are not sequential in NCHW. So the backend in NCHW cannot handle this case.
+  assert(backend_layout == input_alloc->layout());
+  assert(backend_layout == indices_alloc->layout());
+  const auto &input_shape = _ctx.at(input_index).shape();
+  UNUSED_RELEASE(input_shape);
+  assert(input_shape.rank() < 4 || _current_subg_layout == backend_layout);
+
+  const auto axis_raw = node.param().axis;
+  const auto axis_value = (axis_raw < 0 ? (input_shape.rank() + axis_raw) : axis_raw);
+
+  auto fn = nnfw::cpp14::make_unique<::neurun::backend::cpu::kernel::GatherLayer>();
+
+  fn->configure(input_alloc->buffer(), input_backend_descr, indices_alloc->buffer(),
+                indices_backend_descr, output_alloc->buffer(), output_backend_descr, axis_value);
+
+  _execution_builder->append(std::move(fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Sub &node)
+{
+  // The same as Add
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto lhs_index{node.getInputs().at(ir::operation::Sub::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::Sub::Input::RHS)};
+
+  const auto ofm_backend_descr =
+      ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(ofm_index), _current_subg_layout);
+  const auto lhs_backend_descr =
+      ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(lhs_index), _current_subg_layout);
+  const auto rhs_backend_descr =
+      ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(rhs_index), _current_subg_layout);
+
+  const auto activation = node.param().activation;
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto lhs_alloc = _tensor_builder->at(lhs_index).get();
+  auto rhs_alloc = _tensor_builder->at(rhs_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::neurun::backend::cpu::kernel::SubLayer>();
+
+  fn->configure(lhs_alloc->buffer(), lhs_backend_descr, rhs_alloc->buffer(), rhs_backend_descr,
+                activation, ofm_alloc->buffer(), ofm_backend_descr);
+
+  _execution_builder->append(std::move(fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Mul &node)
+{
+  // The same as Add
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto lhs_index{node.getInputs().at(ir::operation::Sub::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::Sub::Input::RHS)};
+
+  const auto ofm_backend_descr =
+      ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(ofm_index), _current_subg_layout);
+  const auto lhs_backend_descr =
+      ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(lhs_index), _current_subg_layout);
+  const auto rhs_backend_descr =
+      ::neurun::backend::cpu::kernel::getTensorDescriptor(_ctx.at(rhs_index), _current_subg_layout);
+
+  const auto activation = node.param().activation;
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto lhs_alloc = _tensor_builder->at(lhs_index).get();
+  auto rhs_alloc = _tensor_builder->at(rhs_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::neurun::backend::cpu::kernel::MulLayer>();
+
+  fn->configure(lhs_alloc->buffer(), lhs_backend_descr, rhs_alloc->buffer(), rhs_backend_descr,
+                activation, ofm_alloc->buffer(), ofm_backend_descr);
+
+  _execution_builder->append(std::move(fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Permute &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(0)};
+
+  const auto &shape = _ctx.at(output_index).shape();
+  const auto input_backend_ctx = node.param().input_backend_ctx;
+  const auto output_backend_ctx = node.param().output_backend_ctx;
+  const auto data_type = node.getDataType();
+
+  output_backend_ctx->tensor_builder->preVisit(node);
+
+  auto output_object = output_backend_ctx->tensor_builder->tensorAt(output_index);
+  auto input_object = input_backend_ctx->tensor_builder->tensorAt(input_index);
+
+  auto fn = nnfw::cpp14::make_unique<::neurun::backend::cpu::kernel::PermuteLayer>();
+
+  // TODO Support NCHW frontend
+  auto out_shape = shape;
+  if (shape.rank() == 4 && output_object->layout() == ir::Layout::NCHW)
+  {
+    out_shape.dim(1) = shape.dim(3);
+    out_shape.dim(2) = shape.dim(1);
+    out_shape.dim(3) = shape.dim(2);
+  }
+
+  const auto permute_type = node.getPermuteType();
+  // Check Permutation Type
+  const auto inferPermuteType = [&]() {
+    if (input_object->layout() == ir::Layout::NHWC && output_object->layout() == ir::Layout::NCHW)
+    {
+      return ir::operation::Permute::Type::NHWC_TO_NCHW;
+    }
+    else if (input_object->layout() == ir::Layout::NCHW &&
+             output_object->layout() == ir::Layout::NHWC)
+    {
+      return ir::operation::Permute::Type::NCHW_TO_NHWC;
+    }
+    else
+    {
+      return ir::operation::Permute::Type::COPY;
+    }
+  }();
+  UNUSED_RELEASE(inferPermuteType);
+  assert(permute_type == inferPermuteType);
+
+  fn->configure(input_object, output_object, out_shape, permute_type, data_type);
+
+  input_backend_ctx->tensor_builder->postVisit(node);
+
+  _execution_builder->append(std::move(fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Custom &node)
+{
+  auto get_type_info = [this](const ir::Operand &operand) -> custom::TypeInfo {
+    auto backendDescr =
+        ::neurun::backend::cpu::kernel::getTensorDescriptor(operand, _current_subg_layout);
+
+    custom::Shape shape(backendDescr.dimensions.size());
+    for (size_t d = 0; d < backendDescr.dimensions.size(); ++d)
+    {
+      shape.dim(d) = backendDescr.dimensions[d];
+    }
+
+    return {shape, backendDescr.type};
+  };
+
+  auto fill_op_info = [&](const ir::OperandIndexSequence &opSeq,
+                          std::vector<custom::TypeInfo> &types, std::vector<void *> &allocs) {
+    for (auto &idx : opSeq)
+    {
+      const auto &operand = _ctx.at(idx);
+      // TODO make sure using `_current_subg_layout` is correct for custom operations
+      types.emplace_back(get_type_info(operand));
+      auto in_alloc = _tensor_builder->at(idx)->buffer();
+      allocs.emplace_back(in_alloc);
+    }
+  };
+
+  backend::custom::CustomKernelConfigParams params{};
+
+  fill_op_info(node.getInputs(), params.input_types, params.input_allocations);
+  fill_op_info(node.getOutputs(), params.output_types, params.output_allocations);
+
+  params.userdata = node.userdata().data;
+  params.userdata_size = node.userdata().size;
+
+  auto fn = _kernel_builder->buildKernel(node.id(), std::move(params));
+
+  _execution_builder->append(std::move(fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Logistic &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::Logistic::Input::INPUT)};
+
+  const auto ofm_backend_descr = ::neurun::backend::cpu::kernel::getTensorDescriptor(
+      _ctx.at(output_index), _current_subg_layout);
+  const auto ifm_backend_descr = ::neurun::backend::cpu::kernel::getTensorDescriptor(
+      _ctx.at(input_index), _current_subg_layout);
+
+  auto output_alloc = _tensor_builder->at(output_index).get();
+  auto input_alloc = _tensor_builder->at(input_index).get();
+
+  auto fn = nnfw::cpp14::make_unique<::neurun::backend::cpu::kernel::LogisticLayer>();
+
+  fn->configure(input_alloc->buffer(), ifm_backend_descr, output_alloc->buffer(),
+                ofm_backend_descr);
+
+  _execution_builder->append(std::move(fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Pad &node)
+{
+  const auto input_index{node.getInputs().at(ir::operation::Pad::Input::INPUT)};
+  const auto pad_index{node.getInputs().at(ir::operation::Pad::Input::PAD)};
+  const auto output_index{node.getOutputs().at(0)};
+  assert(_ctx.at(pad_index).isConstant());
+
+  auto input = _tensor_builder->at(input_index).get();
+  auto output = _tensor_builder->at(output_index).get();
+  auto pad_rank = _ctx.at(pad_index).shape().dim(0);
+  auto pad_base = reinterpret_cast<const int32_t *>(_ctx.at(pad_index).data().base());
+  const auto ofm_backend_descr = ::neurun::backend::cpu::kernel::getTensorDescriptor(
+      _ctx.at(output_index), _current_subg_layout);
+  const auto ifm_backend_descr = ::neurun::backend::cpu::kernel::getTensorDescriptor(
+      _ctx.at(input_index), _current_subg_layout);
+
+  auto fn = nnfw::cpp14::make_unique<::neurun::backend::cpu::kernel::PadLayer>();
+
+  fn->configure(input->buffer(), ifm_backend_descr, output->buffer(), ofm_backend_descr, pad_base,
+                pad_rank);
+
+  _execution_builder->append(std::move(fn));
+}
+
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/cpu/KernelGenerator.h b/runtime/neurun/backend/cpu/KernelGenerator.h
new file mode 100644
index 000000000..0083d6791
--- /dev/null
+++ b/runtime/neurun/backend/cpu/KernelGenerator.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_CPU_KERNEL_GENERATOR_H__
+#define __NEURUN_BACKEND_CPU_KERNEL_GENERATOR_H__
+
+#include "backend/IKernelGenerator.h"
+#include "ir/Operands.h"
+#include "operand/Tensor.h"
+#include "backend/CustomKernelBuilder.h"
+#include "TensorBuilder.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+
+class KernelGenerator : public IKernelGenerator
+{
+public:
+  KernelGenerator(const ir::Operands &ctx, const std::shared_ptr<TensorBuilder> &tensor_builder,
+                  const std::shared_ptr<custom::IKernelBuilder> &kernel_builder);
+
+  using IKernelGenerator::visit;
+
+  void visit(const ir::OpSequence &) override;
+  void visit(const ir::operation::Conv2D &) override;
+  void visit(const ir::operation::DepthwiseConv2D &) override;
+  void visit(const ir::operation::MaxPool2D &) override;
+  void visit(const ir::operation::AvgPool2D &) override;
+  void visit(const ir::operation::Concat &) override;
+  void visit(const ir::operation::FullyConnected &) override;
+  void visit(const ir::operation::Reshape &) override;
+  void visit(const ir::operation::Squeeze &) override;
+  void visit(const ir::operation::Softmax &) override;
+  void visit(const ir::operation::Add &) override;
+  void visit(const ir::operation::Sub &) override;
+  void visit(const ir::operation::Mul &) override;
+  void visit(const ir::operation::Permute &) override;
+  void visit(const ir::operation::Gather &) override;
+  void visit(const ir::operation::Custom &node) override;
+  void visit(const ir::operation::Logistic &) override;
+  void visit(const ir::operation::Pad &) override;
+
+private:
+  const ir::Operands &_ctx;
+  std::shared_ptr<TensorBuilder> _tensor_builder;
+  std::shared_ptr<backend::custom::IKernelBuilder> _kernel_builder;
+  ir::Layout _current_subg_layout;
+};
+
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_CPU_KERNEL_GENERATOR_H__
diff --git a/runtime/neurun/backend/cpu/MemoryManager.cc b/runtime/neurun/backend/cpu/MemoryManager.cc
new file mode 100644
index 000000000..926d8fb4c
--- /dev/null
+++ b/runtime/neurun/backend/cpu/MemoryManager.cc
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "MemoryManager.h"
+
+#include <cassert>
+
+#include <MemoryPlannerFactory.h>
+#include "util/logging.h"
+#include "util/ConfigSource.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+
+MemoryManager::MemoryManager() : _mem_planner{createMemoryPlanner()}
+{
+  // DO NOTHING
+}
+
+MemoryManager::MemoryManager(const std::string planner_id)
+    : _mem_planner{createMemoryPlanner(planner_id)}
+{
+  // DO NOTHING
+}
+
+cpu_common::IMemoryPlanner *MemoryManager::createMemoryPlanner()
+{
+  auto planner_id = util::getConfigString(util::config::CPU_MEMORY_PLANNER);
+  return cpu_common::MemoryPlannerFactory::get().create(planner_id);
+}
+
+cpu_common::IMemoryPlanner *MemoryManager::createMemoryPlanner(const std::string planner_id)
+{
+  return cpu_common::MemoryPlannerFactory::get().create(planner_id);
+}
+
+void MemoryManager::buildTensor(const ir::OperandIndex &ind, const ir::OperandInfo &info)
+{
+  auto tensor = std::make_shared<operand::Tensor>(info);
+  _tensors[ind] = tensor;
+}
+
+void MemoryManager::claimPlan(const ir::OperandIndex &ind, uint32_t size)
+{
+  _mem_planner->claim(ind, size);
+}
+
+void MemoryManager::releasePlan(const ir::OperandIndex &ind) { _mem_planner->release(ind); }
+
+void MemoryManager::allocate(void)
+{
+  _mem_alloc = std::make_shared<cpu_common::Allocator>(_mem_planner->capacity());
+  assert(_mem_alloc->base());
+
+  for (auto &mem_plan : _mem_planner->memory_plans())
+  {
+    auto ind = mem_plan.first;
+    auto mem_blk = mem_plan.second;
+
+    uint8_t *buffer = _mem_alloc->base() + mem_blk.offset;
+    auto tensor = _tensors[ind];
+    tensor->setBuffer(buffer);
+
+    VERBOSE(CPU_MEMORYMANAGER) << "TENSOR(#" << ind.value() << "): " << static_cast<void *>(buffer)
+                               << std::endl;
+
+    // If we do not make tensor here currently, kernel generation would cause segmentation fault.
+    // See also : Comments in `allocate` method.
+  }
+}
+
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/cpu/MemoryManager.h b/runtime/neurun/backend/cpu/MemoryManager.h
new file mode 100644
index 000000000..267e8001b
--- /dev/null
+++ b/runtime/neurun/backend/cpu/MemoryManager.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_CPU_MEMORY_MANAGER_H__
+#define __NEURUN_BACKEND_CPU_MEMORY_MANAGER_H__
+
+#include "backend/IMemoryManager.h"
+#include <MemoryPlanner.h>
+#include "operand/Tensor.h"
+#include "ir/OperandIndexMap.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+
+class MemoryManager : public backend::IMemoryManager
+{
+public:
+  MemoryManager();
+  MemoryManager(const std::string);
+  virtual ~MemoryManager() = default;
+
+  void allocate(void) override;
+  void deallocate(void) override { _mem_alloc->release(); }
+
+  void buildTensor(const ir::OperandIndex &ind, const ir::OperandInfo &info);
+  void claimPlan(const ir::OperandIndex &ind, uint32_t size);
+  void releasePlan(const ir::OperandIndex &ind);
+
+  ir::OperandIndexMap<std::shared_ptr<operand::Tensor>> &tensors(void) { return _tensors; }
+
+private:
+  cpu_common::IMemoryPlanner *createMemoryPlanner();
+  cpu_common::IMemoryPlanner *createMemoryPlanner(const std::string);
+
+private:
+  ir::OperandIndexMap<std::shared_ptr<operand::Tensor>> _tensors;
+  ir::OperandIndexMap<cpu_common::Block> _tensor_mem_map;
+  std::shared_ptr<cpu_common::IMemoryPlanner> _mem_planner;
+  std::shared_ptr<cpu_common::Allocator> _mem_alloc;
+};
+
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_CPU_MEMORY_MANAGER_H__
diff --git a/runtime/neurun/backend/cpu/PluginClassesAllocator.cc b/runtime/neurun/backend/cpu/PluginClassesAllocator.cc
new file mode 100644
index 000000000..caba78447
--- /dev/null
+++ b/runtime/neurun/backend/cpu/PluginClassesAllocator.cc
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <util/logging.h>
+
+#include "Backend.h"
+
+extern "C" {
+neurun::backend::Backend *neurun_backend_create()
+{
+  VERBOSE(neurun_backend_create) << "'cpu' loaded\n";
+  return new neurun::backend::cpu::Backend;
+}
+
+void neurun_backend_destroy(neurun::backend::Backend *backend)
+{
+  VERBOSE(neurun_backend_create) << "'cpu' unloaded\n";
+  delete backend;
+}
+}
diff --git a/runtime/neurun/backend/cpu/ShapeFixer.cc b/runtime/neurun/backend/cpu/ShapeFixer.cc
new file mode 100644
index 000000000..835592b30
--- /dev/null
+++ b/runtime/neurun/backend/cpu/ShapeFixer.cc
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ShapeFixer.h"
+
+#include <stdexcept>
+
+#include "cpp14/memory.h"
+#include "util/Padding.h"
+#include "kernel/OperationUtils.h"
+#include "kernel/ConvolutionLayer.h"
+#include "kernel/AvgPoolLayer.h"
+#include "kernel/MaxPoolLayer.h"
+#include "kernel/ConcatLayer.h"
+#include "kernel/FullyConnectedLayer.h"
+#include "kernel/ReshapeLayer.h"
+#include "kernel/SoftMaxLayer.h"
+#include "kernel/PermuteLayer.h"
+#include "kernel/DepthwiseConvolutionLayer.h"
+#include "kernel/AddLayer.h"
+#include "kernel/SubLayer.h"
+#include "kernel/MulLayer.h"
+#include "kernel/GatherLayer.h"
+
+#include <backend/Backend.h>
+#include <backend/IConfig.h>
+#include "compiler/IExecutionBuilder.h"
+
+#include "util/logging.h"
+
+#include "util/Utils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+
+ShapeFixer::ShapeFixer(const ir::Operands &operand_ctx,
+                       const std::shared_ptr<TensorBuilder> &tensor_builder)
+    : _ctx(operand_ctx), _tensor_builder(tensor_builder)
+{
+  assert(tensor_builder);
+}
+
+void ShapeFixer::visit(const ir::operation::Conv2D &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::DepthwiseConv2D &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::MaxPool2D &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::AvgPool2D &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Concat &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::FullyConnected &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Reshape &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Squeeze &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Softmax &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Gather &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Add &node)
+{
+  const auto lhs_index{node.getInputs().at(ir::operation::Add::Input::LHS)};
+
+  // Quantization : not supported
+  if (_ctx.at(lhs_index).typeInfo().type() == ir::DataType::QUANT8_ASYMM)
+  {
+    throw std::runtime_error{"ShapeFixer: NYI for quantized Add"};
+  }
+}
+
+void ShapeFixer::visit(const ir::operation::Permute &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Sub &node)
+{
+  // The same as Add
+  const auto lhs_index{node.getInputs().at(ir::operation::Sub::Input::LHS)};
+
+  // Quantization : not supported
+  if (_ctx.at(lhs_index).typeInfo().type() == ir::DataType::QUANT8_ASYMM)
+  {
+    throw std::runtime_error{"ShapeFixer: NYI for quantized Sub"};
+  }
+}
+
+void ShapeFixer::visit(const ir::operation::Mul &node)
+{
+  // The same as Add
+  const auto lhs_index{node.getInputs().at(ir::operation::Sub::Input::LHS)};
+
+  // Quantization : not supported
+  if (_ctx.at(lhs_index).typeInfo().type() == ir::DataType::QUANT8_ASYMM)
+  {
+    throw std::runtime_error{"ShapeFixer: NYI for quantized Mul"};
+  }
+}
+
+void ShapeFixer::visit(const ir::operation::Custom &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Logistic &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Pad &node)
+{
+  // TODO: empty this method when quantization is supported
+  const auto lhs_index{node.getInputs().at(ir::operation::Sub::Input::LHS)};
+
+  // Quantization : not supported
+  if (_ctx.at(lhs_index).typeInfo().type() == ir::DataType::QUANT8_ASYMM)
+  {
+    throw std::runtime_error{"ShapeFixer: NYI for quantized Pad"};
+  }
+}
+
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/cpu/ShapeFixer.h b/runtime/neurun/backend/cpu/ShapeFixer.h
new file mode 100644
index 000000000..bbf48498e
--- /dev/null
+++ b/runtime/neurun/backend/cpu/ShapeFixer.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_CPU_SHAPE_FIXER_H__
+#define __NEURUN_BACKEND_CPU_SHAPE_FIXER_H__
+
+#include <backend/IShapeFixer.h>
+
+#include "ir/Operands.h"
+#include "operand/Tensor.h"
+#include "TensorBuilder.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+
+class ShapeFixer : public IShapeFixer
+{
+public:
+  ShapeFixer(const ir::Operands &ctx, const std::shared_ptr<TensorBuilder> &tensor_builder);
+
+  void visit(const ir::operation::Conv2D &) override;
+  void visit(const ir::operation::DepthwiseConv2D &) override;
+  void visit(const ir::operation::MaxPool2D &) override;
+  void visit(const ir::operation::AvgPool2D &) override;
+  void visit(const ir::operation::Concat &) override;
+  void visit(const ir::operation::FullyConnected &) override;
+  void visit(const ir::operation::Reshape &) override;
+  void visit(const ir::operation::Squeeze &) override;
+  void visit(const ir::operation::Softmax &) override;
+  void visit(const ir::operation::Add &) override;
+  void visit(const ir::operation::Gather &) override;
+  void visit(const ir::operation::Sub &) override;
+  void visit(const ir::operation::Mul &) override;
+  void visit(const ir::operation::Permute &) override;
+  void visit(const ir::operation::Custom &) override;
+  void visit(const ir::operation::Logistic &) override;
+  void visit(const ir::operation::Pad &) override;
+
+private:
+  const ir::Operands &_ctx;
+  std::shared_ptr<TensorBuilder> _tensor_builder;
+};
+
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_CPU_SHAPE_FIXER_H__
diff --git a/runtime/neurun/backend/cpu/TensorBuilder.cc b/runtime/neurun/backend/cpu/TensorBuilder.cc
new file mode 100644
index 000000000..2c654c256
--- /dev/null
+++ b/runtime/neurun/backend/cpu/TensorBuilder.cc
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "TensorBuilder.h"
+
+#include <cassert>
+
+#include "util/logging.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+
+TensorBuilder::TensorBuilder() : _tensor_mgr{new TensorManager()}
+{
+  // DO NOTHING
+}
+
+void TensorBuilder::registerTensorInfo(const ir::OperandIndex &ind, const ir::OperandInfo &info,
+                                       ir::Layout, bool as_const)
+{
+  _tensor_info_map.emplace(ind, info);
+
+  if (as_const)
+    _constants.append(ind);
+}
+
+void TensorBuilder::registerSubTensorInfo(const ir::OperandIndex &, const compiler::SubTensorInfo &)
+{
+  // Not supported yet
+  assert(false);
+}
+
+void TensorBuilder::notifyFirstUse(const ir::OperandIndex &ind)
+{
+  assert(_tensor_info_map.find(ind) != _tensor_info_map.end());
+  const auto tensor_info = _tensor_info_map.at(ind);
+  const auto size = tensor_info.total_size();
+  _tensor_mgr->buildTensor(ind, tensor_info, _constants.contains(ind));
+  _tensor_mgr->claimPlan(ind, size);
+}
+
+void TensorBuilder::notifyLastUse(const ir::OperandIndex &ind) { _tensor_mgr->releasePlan(ind); }
+
+bool TensorBuilder::isRegistered(const ir::OperandIndex &ind) const
+{
+  return _tensor_info_map.find(ind) != _tensor_info_map.end();
+}
+
+void TensorBuilder::prepare(void)
+{
+  _tensor_mgr->allocateConsts();
+  _tensor_mgr->allocateNonconsts();
+}
+
+void TensorBuilder::allocateConsts()
+{
+  // NOTE For now nothing to do. Allocation is done in prepare stage, which is not appropriate
+  //      This is because CPU kernels require `ITensor`s to be allocated before Kernel Generation.
+}
+
+void TensorBuilder::allocateNonconsts()
+{
+  // NOTE For now nothing to do. Allocation is done in prepare stage, which is not appropriate
+  //      This is because CPU kernels require `ITensor`s to be allocated before Kernel Generation.
+}
+
+std::shared_ptr<::neurun::backend::operand::ITensor>
+TensorBuilder::tensorAt(const ir::OperandIndex &ind)
+{
+  return _tensor_mgr->at(ind);
+}
+
+void TensorBuilder::iterate(const IterateFunction &fn) { _tensor_mgr->iterate(fn); }
+
+std::shared_ptr<operand::Tensor> TensorBuilder::at(const ir::OperandIndex &ind)
+{
+  return _tensor_mgr->at(ind);
+}
+
+std::unique_ptr<ITensorManager> TensorBuilder::releaseTensorManager(void)
+{
+  return std::move(_tensor_mgr);
+}
+
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/cpu/TensorBuilder.h b/runtime/neurun/backend/cpu/TensorBuilder.h
new file mode 100644
index 000000000..a08db8c9a
--- /dev/null
+++ b/runtime/neurun/backend/cpu/TensorBuilder.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_CPU_TENSOR_BUILDER_H__
+#define __NEURUN_BACKEND_CPU_TENSOR_BUILDER_H__
+
+#include <unordered_map>
+
+#include <backend/ITensorBuilder.h>
+#include "operand/Tensor.h"
+#include "ir/OperandIndexMap.h"
+#include "TensorManager.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+
+class TensorBuilder : public ITensorBuilder
+{
+public:
+  TensorBuilder();
+
+  /**
+   * @brief     Register tensor information to allocate on CPU backend
+   * @param[in] ind    Operand index
+   * @param[in] info   Operand information
+   * @param[in] layout Operand data layout
+   */
+  void registerTensorInfo(const ir::OperandIndex &ind, const ir::OperandInfo &info,
+                          ir::Layout backend_layout, bool as_const) override;
+  /**
+   * @brief     Register subtensor information to allocate on CPU backend
+   * @param[in] ind   Operand index
+   * @param[in] info  Tensor information
+   */
+  void registerSubTensorInfo(const ir::OperandIndex &ind,
+                             const compiler::SubTensorInfo &info) override;
+
+  void notifyFirstUse(const ir::OperandIndex &) override;
+  void notifyLastUse(const ir::OperandIndex &) override;
+
+  bool isRegistered(const ir::OperandIndex &) const override;
+
+  void prepare(void) override;
+  void allocateConsts() override;
+  void allocateNonconsts() override;
+  void postFunctionPrepare() override { /* DO NOTHING */}
+  void finalize() override { /* DO NOTHING */}
+
+  std::shared_ptr<::neurun::backend::operand::ITensor>
+  tensorAt(const ir::OperandIndex &ind) override;
+
+  void iterate(const IterateFunction &fn) override;
+
+  void preVisit(const ir::Operation &) override { /* DO NOTHING */}
+  void postVisit(const ir::Operation &) override { /* DO NOTHING */}
+
+  std::unique_ptr<ITensorManager> releaseTensorManager(void) override;
+
+  std::shared_ptr<operand::Tensor> at(const ir::OperandIndex &ind);
+
+private:
+  std::unique_ptr<TensorManager> _tensor_mgr;
+  ir::OperandIndexMap<ir::OperandInfo> _tensor_info_map;
+  ir::OperandIndexSequence _constants;
+};
+
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_CPU_TENSOR_BUILDER_H__
diff --git a/runtime/neurun/backend/cpu/TensorManager.cc b/runtime/neurun/backend/cpu/TensorManager.cc
new file mode 100644
index 000000000..a346e2cb4
--- /dev/null
+++ b/runtime/neurun/backend/cpu/TensorManager.cc
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "TensorManager.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+
+TensorManager::TensorManager()
+    : _const_mgr{new MemoryManager("Bump")}, _nonconst_mgr{new MemoryManager()}
+{
+  // DO NOTHING
+}
+
+void TensorManager::allocateConsts(void) { _const_mgr->allocate(); }
+
+void TensorManager::allocateNonconsts(void) { _nonconst_mgr->allocate(); }
+
+void TensorManager::deallocateConsts(void) { _const_mgr->deallocate(); }
+
+void TensorManager::deallocateNonconsts(void) { _nonconst_mgr->deallocate(); }
+
+void TensorManager::buildTensor(const ir::OperandIndex &ind, const ir::OperandInfo &tensor_info,
+                                bool as_const)
+{
+  assert(_ind_to_mgr.find(ind) == _ind_to_mgr.end());
+  if (as_const)
+  {
+    _const_mgr->buildTensor(ind, tensor_info);
+    _ind_to_mgr.insert({ind, *_const_mgr});
+  }
+  else
+  {
+    _nonconst_mgr->buildTensor(ind, tensor_info);
+    _ind_to_mgr.insert({ind, *_nonconst_mgr});
+  }
+}
+
+void TensorManager::claimPlan(const ir::OperandIndex &ind, uint32_t size)
+{
+  assert(_ind_to_mgr.find(ind) != _ind_to_mgr.end());
+  _ind_to_mgr.at(ind).claimPlan(ind, size);
+}
+
+void TensorManager::releasePlan(const ir::OperandIndex &ind)
+{
+  assert(_ind_to_mgr.find(ind) != _ind_to_mgr.end());
+  _ind_to_mgr.at(ind).releasePlan(ind);
+}
+
+std::shared_ptr<operand::Tensor> TensorManager::at(const ir::OperandIndex &ind)
+{
+  assert(_ind_to_mgr.find(ind) != _ind_to_mgr.end());
+  return _ind_to_mgr.at(ind).tensors().at(ind);
+}
+
+ir::OperandIndexMap<std::shared_ptr<operand::Tensor>> &TensorManager::constTensors(void)
+{
+  return _const_mgr->tensors();
+}
+
+ir::OperandIndexMap<std::shared_ptr<operand::Tensor>> &TensorManager::nonconstTensors(void)
+{
+  return _nonconst_mgr->tensors();
+}
+
+void TensorManager::iterate(const std::function<void(const ir::OperandIndex &)> &fn)
+{
+  for (auto it : _nonconst_mgr->tensors())
+    fn(it.first);
+
+  for (auto it : _const_mgr->tensors())
+    fn(it.first);
+}
+
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/cpu/TensorManager.h b/runtime/neurun/backend/cpu/TensorManager.h
new file mode 100644
index 000000000..c3ef70663
--- /dev/null
+++ b/runtime/neurun/backend/cpu/TensorManager.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_CPU_TENSOR_MANAGER_H__
+#define __NEURUN_BACKEND_CPU_TENSOR_MANAGER_H__
+
+#include "backend/ITensorManager.h"
+#include "MemoryManager.h"
+#include "ir/OperandIndexMap.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+
+class TensorManager : public backend::ITensorManager
+{
+public:
+  TensorManager();
+  virtual ~TensorManager() = default;
+
+  void allocateConsts(void) override;
+  void allocateNonconsts(void) override;
+  void deallocateConsts(void) override;
+  void deallocateNonconsts(void) override;
+
+  void buildTensor(const ir::OperandIndex &ind, const ir::OperandInfo &tensor_info, bool as_const);
+
+  void claimPlan(const ir::OperandIndex &ind, uint32_t size);
+  void releasePlan(const ir::OperandIndex &ind);
+
+  std::shared_ptr<operand::Tensor> at(const ir::OperandIndex &ind);
+
+  ir::OperandIndexMap<std::shared_ptr<operand::Tensor>> &constTensors(void);
+  ir::OperandIndexMap<std::shared_ptr<operand::Tensor>> &nonconstTensors(void);
+
+  void iterate(const std::function<void(const ir::OperandIndex &)> &fn);
+
+private:
+  std::unique_ptr<MemoryManager> _const_mgr;
+  std::unique_ptr<MemoryManager> _nonconst_mgr;
+  ir::OperandIndexMap<MemoryManager &> _ind_to_mgr;
+};
+
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_CPU_TENSOR_MANAGER_H__
diff --git a/runtime/neurun/backend/cpu/TensorRegister.cc b/runtime/neurun/backend/cpu/TensorRegister.cc
new file mode 100644
index 000000000..2701503f5
--- /dev/null
+++ b/runtime/neurun/backend/cpu/TensorRegister.cc
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "TensorRegister.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+
+TensorRegister::TensorRegister(const ir::Operands &operands,
+                               const std::shared_ptr<TensorBuilder> &tensor_builder)
+    : _operands{operands}, _tensor_builder{tensor_builder}
+{
+  assert(tensor_builder != nullptr);
+}
+
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/cpu/TensorRegister.h b/runtime/neurun/backend/cpu/TensorRegister.h
new file mode 100644
index 000000000..1bda9fca3
--- /dev/null
+++ b/runtime/neurun/backend/cpu/TensorRegister.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_CPU_TENSOR_REGISTER_H__
+#define __NEURUN_BACKEND_CPU_TENSOR_REGISTER_H__
+
+#include <backend/ITensorRegister.h>
+#include "TensorBuilder.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+
+class TensorRegister : public ITensorRegister
+{
+public:
+  TensorRegister(const ir::Operands &operands,
+                 const std::shared_ptr<TensorBuilder> &tensor_builder);
+
+private:
+  const ir::Operands &operands() const override { return _operands; }
+  std::shared_ptr<ITensorBuilder> tensor_builder() const override { return _tensor_builder; }
+  bool supportSubTensor() const final { return false; }
+
+private:
+  const ir::Operands &_operands;
+  const std::shared_ptr<TensorBuilder> _tensor_builder;
+};
+
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_CPU_TENSOR_REGISTER_H__
diff --git a/runtime/neurun/backend/cpu/kernel/AddLayer.cc b/runtime/neurun/backend/cpu/kernel/AddLayer.cc
new file mode 100644
index 000000000..8a2d872e5
--- /dev/null
+++ b/runtime/neurun/backend/cpu/kernel/AddLayer.cc
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "AddLayer.h"
+
+#include <cker/operation/BinaryArithmeticOps.h>
+
+#include "OperationUtils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace kernel
+{
+
+void AddLayer::addFloat32()
+{
+  float output_activation_min, output_activation_max;
+  CalculateActivationRangeFloat(_activation, &output_activation_min, &output_activation_max);
+  nnfw::cker::BinaryArithmeticOpParam op_params;
+  op_params.float_activation_max = output_activation_max;
+  op_params.float_activation_min = output_activation_min;
+
+  const std::function<float(const float &, const float &)> fn = [](const float &a, const float &b) {
+    return a + b;
+  };
+
+  if (!HaveSameShapes(&_lhsDescr, &_rhsDescr))
+  {
+    nnfw::cker::BroadcastBinaryArithmeticOpSlow(
+        op_params, convertToExtendedCkerShape(_lhsDescr), _lhsData.f,
+        convertToExtendedCkerShape(_rhsDescr), _rhsData.f, convertToExtendedCkerShape(_outputDescr),
+        _outputData.f, fn);
+    return;
+  }
+
+  nnfw::cker::BinaryArithmeticOp(op_params, convertTensorDescriptorToCkerShape(_lhsDescr),
+                                 _lhsData.f, convertTensorDescriptorToCkerShape(_rhsDescr),
+                                 _rhsData.f, convertTensorDescriptorToCkerShape(_outputDescr),
+                                 _outputData.f, fn);
+}
+
+void AddLayer::addQuant8()
+{
+  int32_t output_activation_min, output_activation_max;
+  CalculateActivationRangeUint8(_activation, _outputDescr, &output_activation_min,
+                                &output_activation_max);
+  // nnfw::cker::BinaryArithmeticOpParam op_params;
+  // op_params.quantized_activation_max = output_activation_max;
+  // op_params.quantized_activation_min = output_activation_min;
+
+  // cker quant8 add is not implemented yet
+  throw std::runtime_error{"NYI"};
+}
+
+void AddLayer::configure(uint8_t *lhsData, const TensorDescriptor &lhsDescr, uint8_t *rhsData,
+                         const TensorDescriptor &rhsDescr, const ir::Activation activation,
+                         uint8_t *outputData, const TensorDescriptor &outputDescr)
+{
+  _lhsData.u8 = lhsData;
+  _lhsDescr = lhsDescr;
+  _rhsData.u8 = rhsData;
+  _rhsDescr = rhsDescr;
+  _inputType = lhsDescr.type;
+  _activation = activation;
+  _outputData.u8 = outputData;
+  _outputDescr = outputDescr;
+}
+
+void AddLayer::run()
+{
+  if (_inputType == OperandType::FLOAT32)
+  {
+    addFloat32();
+  }
+  else if (_inputType == OperandType::QUANT8_ASYMM)
+  {
+    addQuant8();
+  }
+}
+
+} // namespace kernel
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/cpu/kernel/AddLayer.h b/runtime/neurun/backend/cpu/kernel/AddLayer.h
new file mode 100644
index 000000000..7018e4c48
--- /dev/null
+++ b/runtime/neurun/backend/cpu/kernel/AddLayer.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_CPU_KERNEL_ADDLAYER_H__
+#define __NEURUN_BACKEND_CPU_KERNEL_ADDLAYER_H__
+
+#include <exec/IFunction.h>
+
+#include "OperationUtils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace kernel
+{
+
+class AddLayer : public ::neurun::exec::IFunction
+{
+public:
+  AddLayer() : _lhsData(), _rhsData(), _outputData(), _lhsDescr(), _rhsDescr(), _outputDescr()
+  {
+    // DO NOTHING
+  }
+
+public:
+  void addFloat32();
+
+  void addQuant8();
+
+  void configure(uint8_t *lhsData, const TensorDescriptor &lhsDescr, uint8_t *rhsData,
+                 const TensorDescriptor &rhsDescr, const ir::Activation activation,
+                 uint8_t *outputData, const TensorDescriptor &outputDescr);
+
+  void run();
+  void runSync()
+  {
+    // this abstract method is used just for profiling and called for
+    // backend::acl_common::AclFunction
+    run();
+  }
+
+private:
+  DataPtr _lhsData;
+  DataPtr _rhsData;
+  DataPtr _outputData;
+
+  TensorDescriptor _lhsDescr;
+  TensorDescriptor _rhsDescr;
+  TensorDescriptor _outputDescr;
+
+  ir::Activation _activation{ir::Activation::NONE};
+
+  OperandType _inputType{OperandType::FLOAT32};
+};
+
+} // namespace kernel
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_CPU_KERNEL_ADDLAYER_H__
diff --git a/runtime/neurun/backend/cpu/kernel/AvgPoolLayer.cc b/runtime/neurun/backend/cpu/kernel/AvgPoolLayer.cc
new file mode 100644
index 000000000..389955796
--- /dev/null
+++ b/runtime/neurun/backend/cpu/kernel/AvgPoolLayer.cc
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ * Copyright (C) 2017 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "AvgPoolLayer.h"
+
+#include "OperationUtils.h"
+
+#include <cker/operation/AveragePool.h>
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace kernel
+{
+
+#define AVGPOOLING_PARAMETERS                            \
+  nnfw::cker::PoolParams op_params;                      \
+  op_params.stride_height = _strideHeight;               \
+  op_params.stride_width = _strideWidth;                 \
+  op_params.filter_height = _kernelHeight;               \
+  op_params.filter_width = _kernelWidth;                 \
+  op_params.padding_values.height = (int8_t)_paddingTop; \
+  op_params.padding_values.width = (int8_t)_paddingLeft;
+
+AvgPoolLayer::AvgPoolLayer()
+    : _inputData(), _outputData(), _inputDescr(), _outputDescr(), _paddingLeft(0), _paddingTop(0),
+      _paddingRight(0), _paddingBottom(0), _strideWidth(0), _strideHeight(0), _kernelWidth(0),
+      _kernelHeight(0), _activation(ir::Activation::NONE), _inputType(OperandType::FLOAT32)
+{
+  // DO NOTHING
+}
+
+void AvgPoolLayer::averagePoolFloat32()
+{
+  AVGPOOLING_PARAMETERS
+  float output_activation_min, output_activation_max;
+  CalculateActivationRangeFloat(_activation, &output_activation_min, &output_activation_max);
+  op_params.float_activation_min = output_activation_min;
+  op_params.float_activation_max = output_activation_max;
+
+  nnfw::cker::AveragePool(op_params, convertTensorDescriptorToCkerShape(_inputDescr), _inputData.f,
+                          convertTensorDescriptorToCkerShape(_outputDescr), _outputData.f);
+}
+void AvgPoolLayer::averagePoolQuant8()
+{
+  AVGPOOLING_PARAMETERS
+  int32_t output_activation_min = 0;
+  int32_t output_activation_max = 0;
+  CalculateActivationRangeUint8(_activation, _outputDescr, &output_activation_min,
+                                &output_activation_max);
+  op_params.quantized_activation_min = output_activation_min;
+  op_params.quantized_activation_max = output_activation_max;
+
+  nnfw::cker::AveragePool(op_params, convertTensorDescriptorToCkerShape(_inputDescr), _inputData.u8,
+                          convertTensorDescriptorToCkerShape(_outputDescr), _outputData.u8);
+}
+
+void AvgPoolLayer::configure(uint8_t *inputData, const TensorDescriptor inputDescr,
+                             const uint32_t paddingLeft, const uint32_t paddingRight,
+                             const uint32_t paddingTop, const uint32_t paddingBottom,
+                             const uint32_t strideWidth, const uint32_t strideHeight,
+                             const uint32_t kernelWidth, const uint32_t kernelHeight,
+                             const ir::Activation activation, uint8_t *outputData,
+                             const TensorDescriptor outputDescr)
+{
+  _inputData.u8 = inputData;
+  _inputDescr = inputDescr;
+  _inputType = inputDescr.type;
+  _paddingLeft = paddingLeft;
+  _paddingRight = paddingRight;
+  _paddingTop = paddingTop;
+  _paddingBottom = paddingBottom;
+  _strideWidth = strideWidth;
+  _strideHeight = strideHeight;
+  _kernelWidth = kernelWidth;
+  _kernelHeight = kernelHeight;
+  _activation = activation;
+  _outputData.u8 = outputData;
+  _outputDescr = outputDescr;
+}
+
+void AvgPoolLayer::run()
+{
+  if (_inputType == OperandType::FLOAT32)
+  {
+    averagePoolFloat32();
+  }
+  else if (_inputType == OperandType::QUANT8_ASYMM)
+  {
+    averagePoolQuant8();
+  }
+}
+
+#undef AVGPOOLING_PARAMETERS
+
+} // namespace kernel
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/cpu/kernel/AvgPoolLayer.h b/runtime/neurun/backend/cpu/kernel/AvgPoolLayer.h
new file mode 100644
index 000000000..6339efa41
--- /dev/null
+++ b/runtime/neurun/backend/cpu/kernel/AvgPoolLayer.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_CPU_KERNEL_AVGPOOLLAYER_H__
+#define __NEURUN_BACKEND_CPU_KERNEL_AVGPOOLLAYER_H__
+
+#include <exec/IFunction.h>
+
+#include "OperationUtils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace kernel
+{
+
+class AvgPoolLayer : public ::neurun::exec::IFunction
+{
+public:
+  AvgPoolLayer();
+
+public:
+  void averagePoolFloat32();
+
+  void averagePoolQuant8();
+
+  void configure(uint8_t *inputData, const TensorDescriptor inputDescr, const uint32_t paddingLeft,
+                 const uint32_t paddingRight, const uint32_t paddingTop,
+                 const uint32_t paddingBottom, const uint32_t strideWidth,
+                 const uint32_t strideHeight, const uint32_t kernelWidth,
+                 const uint32_t kernelHeight, const ir::Activation activation, uint8_t *outputData,
+                 const TensorDescriptor outputDescr);
+
+  void run();
+  void runSync()
+  {
+    // this abstract method is used just for profiling and called for
+    // backend::acl_common::AclFunction
+    run();
+  }
+
+private:
+  DataPtr _inputData;
+  DataPtr _outputData;
+
+  TensorDescriptor _inputDescr;
+  TensorDescriptor _outputDescr;
+
+  uint32_t _paddingLeft;
+  uint32_t _paddingTop;
+  uint32_t _paddingRight;
+  uint32_t _paddingBottom;
+
+  uint32_t _strideWidth;
+  uint32_t _strideHeight;
+  uint32_t _kernelWidth;
+  uint32_t _kernelHeight;
+
+  ir::Activation _activation;
+
+  OperandType _inputType;
+};
+
+} // namespace kernel
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_CPU_KERNEL_AVGPOOLLAYER_H__
diff --git a/runtime/neurun/backend/cpu/kernel/ConcatLayer.cc b/runtime/neurun/backend/cpu/kernel/ConcatLayer.cc
new file mode 100644
index 000000000..471c9b3bb
--- /dev/null
+++ b/runtime/neurun/backend/cpu/kernel/ConcatLayer.cc
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ * Copyright (C) 2017 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ConcatLayer.h"
+
+#include "OperationUtils.h"
+
+#include <cker/operation/Concatenation.h>
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace kernel
+{
+
+ConcatLayer::ConcatLayer()
+    : _inputDataPtrs(), _outputData(), _axis(0), _inputDescriptors(), _outputDescr(),
+      _inputType(OperandType::FLOAT32)
+{
+  // DO NOTHING
+}
+
+void ConcatLayer::concatenationFloat32()
+{
+  uint32_t num_inputs = _inputDescriptors.size();
+
+  nnfw::cker::ConcatenationParams op_params;
+  op_params.axis = _axis;
+  op_params.inputs_count = num_inputs;
+
+  std::vector<nnfw::cker::Shape *> inputDimsPtr;
+  std::vector<nnfw::cker::Shape> inputDims;
+  inputDimsPtr.reserve(num_inputs);
+  inputDims.reserve(num_inputs);
+
+  for (uint32_t i = 0; i < num_inputs; i++)
+  {
+    inputDims.push_back(convertTensorDescriptorToCkerShape(_inputDescriptors[i]));
+    inputDimsPtr.push_back(&inputDims[i]);
+  }
+
+  std::vector<const float *> inputFloatPtrs;
+
+  for (auto ptr : _inputDataPtrs)
+  {
+    inputFloatPtrs.emplace_back(reinterpret_cast<const float *>(ptr));
+  }
+
+  nnfw::cker::Concatenation<float>(op_params, inputDimsPtr.data(), inputFloatPtrs.data(),
+                                   convertTensorDescriptorToCkerShape(_outputDescr), _outputData.f);
+}
+void ConcatLayer::concatenationQuant8()
+{
+  uint32_t num_inputs = _inputDescriptors.size();
+
+  std::vector<int32_t> input_zeropoints(num_inputs);
+  std::vector<float> input_scales(num_inputs);
+  for (uint32_t i = 0; i < num_inputs; i++)
+  {
+    input_zeropoints[i] = _inputDescriptors[i].offset;
+    input_scales[i] = _inputDescriptors[i].scale;
+  }
+
+  nnfw::cker::ConcatenationParams op_params;
+  op_params.axis = _axis;
+  op_params.inputs_count = num_inputs;
+  op_params.input_zeropoint = input_zeropoints.data();
+  op_params.input_scale = input_scales.data();
+  op_params.output_zeropoint = _outputDescr.offset;
+  op_params.output_scale = _outputDescr.scale;
+
+  std::vector<nnfw::cker::Shape *> inputDimsPtr;
+  std::vector<nnfw::cker::Shape> inputDims;
+  inputDimsPtr.reserve(num_inputs);
+  inputDims.reserve(num_inputs);
+  for (uint32_t i = 0; i < num_inputs; i++)
+  {
+    inputDims.push_back(convertTensorDescriptorToCkerShape(_inputDescriptors[i]));
+    inputDimsPtr.push_back(&inputDims[i]);
+  }
+
+  nnfw::cker::Concatenation<uint8_t>(op_params, inputDimsPtr.data(), _inputDataPtrs.data(),
+                                     convertTensorDescriptorToCkerShape(_outputDescr),
+                                     _outputData.u8);
+}
+
+void ConcatLayer::configure(const std::vector<const uint8_t *> &inputDataPtrs,
+                            const std::vector<TensorDescriptor> &inputDescriptors, int32_t axis,
+                            uint8_t *outputData, const TensorDescriptor outputDescr)
+{
+  _inputDataPtrs = inputDataPtrs;
+
+  for (auto inputDescr : inputDescriptors)
+  {
+    _inputDescriptors.emplace_back(inputDescr);
+    _inputType = inputDescr.type;
+  }
+
+  _axis = axis;
+
+  _outputData.u8 = outputData;
+  _outputDescr = outputDescr;
+}
+
+void ConcatLayer::run()
+{
+  if (_inputType == OperandType::FLOAT32)
+  {
+    concatenationFloat32();
+  }
+  else if (_inputType == OperandType::QUANT8_ASYMM)
+  {
+    concatenationQuant8();
+  }
+}
+
+} // namespace kernel
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/cpu/kernel/ConcatLayer.h b/runtime/neurun/backend/cpu/kernel/ConcatLayer.h
new file mode 100644
index 000000000..048aa4208
--- /dev/null
+++ b/runtime/neurun/backend/cpu/kernel/ConcatLayer.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ * Copyright (C) 2017 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_CPU_KERNEL_CONCATLAYER_H__
+#define __NEURUN_BACKEND_CPU_KERNEL_CONCATLAYER_H__
+
+#include <exec/IFunction.h>
+
+#include "OperationUtils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace kernel
+{
+
+class ConcatLayer : public ::neurun::exec::IFunction
+{
+public:
+  ConcatLayer();
+
+public:
+  void concatenationFloat32();
+
+  void concatenationQuant8();
+
+  void configure(const std::vector<const uint8_t *> &inputDataPtrs,
+                 const std::vector<TensorDescriptor> &inputDescriptors, int32_t axis,
+                 uint8_t *outputData, const TensorDescriptor outputDescr);
+
+  void run();
+  void runSync()
+  {
+    // this abstract method is used just for profiling and called for
+    // backend::acl_common::AclFunction
+    run();
+  }
+
+private:
+  std::vector<const uint8_t *> _inputDataPtrs;
+  DataPtr _outputData;
+
+  int32_t _axis;
+
+  std::vector<TensorDescriptor> _inputDescriptors;
+  TensorDescriptor _outputDescr;
+
+  OperandType _inputType;
+};
+
+} // namespace kernel
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_CPU_KERNEL_CONCATLAYER_H__
diff --git a/runtime/neurun/backend/cpu/kernel/ConvolutionLayer.cc b/runtime/neurun/backend/cpu/kernel/ConvolutionLayer.cc
new file mode 100644
index 000000000..2fdb0baf7
--- /dev/null
+++ b/runtime/neurun/backend/cpu/kernel/ConvolutionLayer.cc
@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ConvolutionLayer.h"
+
+#include <cker/operation/Conv.h>
+
+#include "OperationUtils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace kernel
+{
+ConvolutionLayer::ConvolutionLayer()
+    : _inputData(), _kernelData(), _outputData(), _biasData(), _inputDescr(), _kernelDescr(),
+      _outputDescr(), _biasDescr(), _paddingLeft(0), _paddingTop(0), _paddingRight(0),
+      _paddingBottom(0), _strideWidth(0), _strideHeight(0), _activation(ir::Activation::NONE),
+      _inputType(OperandType::FLOAT32)
+{
+  // DO NOTHING
+}
+
+void ConvolutionLayer::convFloat32()
+{
+  float output_activation_min, output_activation_max;
+  CalculateActivationRangeFloat(_activation, &output_activation_min, &output_activation_max);
+
+  nnfw::cker::ConvParams op_params;
+  op_params.padding_values.width = _paddingLeft;
+  op_params.padding_values.height = _paddingTop;
+  op_params.stride_width = _strideWidth;
+  op_params.stride_height = _strideHeight;
+  op_params.dilation_width_factor = 1;
+  op_params.dilation_height_factor = 1;
+  op_params.float_activation_min = output_activation_min;
+  op_params.float_activation_max = output_activation_max;
+
+  nnfw::cker::Conv(op_params, convertTensorDescriptorToCkerShape(_inputDescr), _inputData.f,
+                   convertTensorDescriptorToCkerShape(_kernelDescr), _kernelData.f,
+                   convertTensorDescriptorToCkerShape(_biasDescr), _biasData.f,
+                   convertTensorDescriptorToCkerShape(_outputDescr), _outputData.f);
+}
+
+void ConvolutionLayer::convQuant8()
+{
+  int32_t output_activation_min = 0;
+  int32_t output_activation_max = 0;
+  CalculateActivationRangeUint8(_activation, _outputDescr, &output_activation_min,
+                                &output_activation_max);
+
+  float real_multiplier = 0.0;
+  int32_t output_multiplier = 0;
+  int32_t output_shift = 0;
+  GetQuantizedConvolutionMultiplier(_inputDescr, _kernelDescr, _biasDescr, _outputDescr,
+                                    &real_multiplier);
+  QuantizeMultiplier(real_multiplier, &output_multiplier, &output_shift);
+
+  nnfw::cker::ConvParams op_params;
+  op_params.stride_width = _strideWidth;
+  op_params.stride_height = _strideHeight;
+  op_params.dilation_width_factor = 1;
+  op_params.dilation_height_factor = 1;
+  op_params.padding_values.width = _paddingLeft;
+  op_params.padding_values.height = _paddingTop;
+  op_params.input_offset = -_inputDescr.offset;
+  op_params.weights_offset = -_kernelDescr.offset;
+  op_params.output_offset = _outputDescr.offset;
+  op_params.output_multiplier = output_multiplier;
+  op_params.output_shift = output_shift;
+  op_params.quantized_activation_min = output_activation_min;
+  op_params.quantized_activation_max = output_activation_max;
+
+  nnfw::cker::Conv(op_params, convertTensorDescriptorToCkerShape(_inputDescr), _inputData.u8,
+                   convertTensorDescriptorToCkerShape(_kernelDescr), _kernelData.u8,
+                   convertTensorDescriptorToCkerShape(_biasDescr), _biasData.i32,
+                   convertTensorDescriptorToCkerShape(_outputDescr), _outputData.u8);
+}
+
+void ConvolutionLayer::configure(uint8_t *inputData, const TensorDescriptor inputDescr,
+                                 uint8_t *kernelData, const TensorDescriptor kernelDescr,
+                                 uint8_t *biasData, const TensorDescriptor biasDescr,
+                                 const uint32_t paddingLeft, const uint32_t paddingRight,
+                                 const uint32_t paddingTop, const uint32_t paddingBottom,
+                                 const uint32_t strideWidth, const uint32_t strideHeight,
+                                 const ir::Activation activation, uint8_t *outputData,
+                                 const TensorDescriptor outputDescr)
+{
+  _inputData.u8 = inputData;
+  _inputDescr = inputDescr;
+  _inputType = inputDescr.type;
+  _kernelData.u8 = kernelData;
+  _kernelDescr = kernelDescr;
+  _biasData.u8 = biasData;
+  _biasDescr = biasDescr;
+  _paddingLeft = paddingLeft;
+  _paddingRight = paddingRight;
+  _paddingTop = paddingTop;
+  _paddingBottom = paddingBottom;
+  _strideWidth = strideWidth;
+  _strideHeight = strideHeight;
+  _activation = activation;
+  _outputData.u8 = outputData;
+  _outputDescr = outputDescr;
+}
+
+void ConvolutionLayer::run()
+{
+  if (_inputType == OperandType::FLOAT32)
+  {
+    convFloat32();
+  }
+  else if (_inputType == OperandType::QUANT8_ASYMM)
+  {
+    convQuant8();
+  }
+}
+
+#undef ANDROID_NN_CONV_PARAMETERS
+
+} // namespace kernel
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/cpu/kernel/ConvolutionLayer.h b/runtime/neurun/backend/cpu/kernel/ConvolutionLayer.h
new file mode 100644
index 000000000..16669f316
--- /dev/null
+++ b/runtime/neurun/backend/cpu/kernel/ConvolutionLayer.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_CPU_KERNEL_CONVOLUTIONLAYER_H__
+#define __NEURUN_BACKEND_CPU_KERNEL_CONVOLUTIONLAYER_H__
+
+#include <exec/IFunction.h>
+
+#include "OperationUtils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace kernel
+{
+
+class ConvolutionLayer : public ::neurun::exec::IFunction
+{
+public:
+  ConvolutionLayer();
+
+public:
+  void convFloat32();
+
+  void convQuant8();
+
+  void configure(uint8_t *inputData, const TensorDescriptor inputDescr, uint8_t *kernelData,
+                 const TensorDescriptor kernelDescr, uint8_t *biasData,
+                 const TensorDescriptor biasDescr, const uint32_t paddingLeft,
+                 const uint32_t paddingRight, const uint32_t paddingTop,
+                 const uint32_t paddingBottom, const uint32_t strideW, const uint32_t strideH,
+                 const ir::Activation activation, uint8_t *outputData,
+                 const TensorDescriptor outputDescr);
+
+  void run();
+  void runSync()
+  {
+    // this abstract method is used just for profiling and called for
+    // backend::acl_common::AclFunction
+    run();
+  }
+
+private:
+  DataPtr _inputData;
+  DataPtr _kernelData;
+  DataPtr _outputData;
+  DataPtr _biasData;
+
+  TensorDescriptor _inputDescr;
+  TensorDescriptor _kernelDescr;
+  TensorDescriptor _outputDescr;
+  TensorDescriptor _biasDescr;
+
+  uint32_t _paddingLeft;
+  uint32_t _paddingTop;
+  uint32_t _paddingRight;
+  uint32_t _paddingBottom;
+
+  uint32_t _strideWidth;
+  uint32_t _strideHeight;
+
+  ir::Activation _activation;
+
+  OperandType _inputType;
+};
+
+} // namespace kernel
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_CPU_KERNEL_CONVOLUTIONLAYER_H__
diff --git a/runtime/neurun/backend/cpu/kernel/DepthwiseConvolutionLayer.cc b/runtime/neurun/backend/cpu/kernel/DepthwiseConvolutionLayer.cc
new file mode 100644
index 000000000..e33e3465e
--- /dev/null
+++ b/runtime/neurun/backend/cpu/kernel/DepthwiseConvolutionLayer.cc
@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "DepthwiseConvolutionLayer.h"
+
+#include <cker/operation/DepthwiseConv.h>
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace kernel
+{
+
+DepthwiseConvolutionLayer::DepthwiseConvolutionLayer()
+    : _inputData(), _kernelData(), _outputData(), _biasData(), _inputDescr(), _kernelDescr(),
+      _outputDescr(), _biasDescr(), _paddingLeft(0), _paddingTop(0), _paddingRight(0),
+      _paddingBottom(0), _strideWidth(0), _strideHeight(0), _multiplier(0),
+      _activation(ir::Activation::NONE), _inputType(OperandType::FLOAT32)
+{
+  // DO NOTHING
+}
+
+void DepthwiseConvolutionLayer::convFloat32()
+{
+  float output_activation_min, output_activation_max;
+  CalculateActivationRangeFloat(_activation, &output_activation_min, &output_activation_max);
+
+  nnfw::cker::DepthwiseConvParams op_params;
+  op_params.stride_width = _strideWidth;
+  op_params.stride_height = _strideHeight;
+  op_params.dilation_width_factor = 1;
+  op_params.dilation_height_factor = 1;
+  op_params.padding_values.width = _paddingLeft;
+  op_params.padding_values.height = _paddingTop;
+  op_params.depth_multiplier = _multiplier;
+  op_params.float_activation_min = output_activation_min;
+  op_params.float_activation_max = output_activation_max;
+
+  nnfw::cker::DepthwiseConv(op_params, convertTensorDescriptorToCkerShape(_inputDescr),
+                            _inputData.f, convertTensorDescriptorToCkerShape(_kernelDescr),
+                            _kernelData.f, convertTensorDescriptorToCkerShape(_biasDescr),
+                            _biasData.f, convertTensorDescriptorToCkerShape(_outputDescr),
+                            _outputData.f);
+}
+
+void DepthwiseConvolutionLayer::convQuant8()
+{
+  int32_t output_activation_min = 0;
+  int32_t output_activation_max = 0;
+  CalculateActivationRangeUint8(_activation, _outputDescr, &output_activation_min,
+                                &output_activation_max);
+
+  float real_multiplier = 0.0;
+  int32_t output_multiplier = 0;
+  int32_t output_shift = 0;
+  GetQuantizedConvolutionMultiplier(_inputDescr, _kernelDescr, _biasDescr, _outputDescr,
+                                    &real_multiplier);
+  QuantizeMultiplier(real_multiplier, &output_multiplier, &output_shift);
+
+  nnfw::cker::DepthwiseConvParams op_params;
+  op_params.stride_width = _strideWidth;
+  op_params.stride_height = _strideHeight;
+  op_params.dilation_width_factor = 1;
+  op_params.dilation_height_factor = 1;
+  op_params.padding_values.width = _paddingLeft;
+  op_params.padding_values.height = _paddingTop;
+  op_params.depth_multiplier = _multiplier;
+  op_params.input_offset = -_inputDescr.offset;
+  op_params.weights_offset = -_kernelDescr.offset;
+  op_params.output_offset = _outputDescr.offset;
+  op_params.output_multiplier = output_multiplier;
+  op_params.output_shift = output_shift;
+  op_params.quantized_activation_min = output_activation_min;
+  op_params.quantized_activation_max = output_activation_max;
+
+  nnfw::cker::DepthwiseConv(op_params, convertTensorDescriptorToCkerShape(_inputDescr),
+                            _inputData.u8, convertTensorDescriptorToCkerShape(_kernelDescr),
+                            _kernelData.u8, convertTensorDescriptorToCkerShape(_biasDescr),
+                            _biasData.i32, convertTensorDescriptorToCkerShape(_outputDescr),
+                            _outputData.u8);
+}
+
+void DepthwiseConvolutionLayer::configure(uint8_t *inputData, const TensorDescriptor inputDescr,
+                                          uint8_t *kernelData, const TensorDescriptor kernelDescr,
+                                          uint8_t *biasData, const TensorDescriptor biasDescr,
+                                          const uint32_t paddingLeft, const uint32_t paddingRight,
+                                          const uint32_t paddingTop, const uint32_t paddingBottom,
+                                          const uint32_t strideWidth, const uint32_t strideHeight,
+                                          const uint32_t multiplier,
+                                          const ir::Activation activation, uint8_t *outputData,
+                                          const TensorDescriptor outputDescr)
+{
+  _inputData.u8 = inputData;
+  _inputDescr = inputDescr;
+  _inputType = inputDescr.type;
+  _kernelData.u8 = kernelData;
+  _kernelDescr = kernelDescr;
+  _biasData.u8 = biasData;
+  _biasDescr = biasDescr;
+  _paddingLeft = paddingLeft;
+  _paddingRight = paddingRight;
+  _paddingTop = paddingTop;
+  _paddingBottom = paddingBottom;
+  _strideWidth = strideWidth;
+  _strideHeight = strideHeight;
+  _multiplier = multiplier;
+  _activation = activation;
+  _outputData.u8 = outputData;
+  _outputDescr = outputDescr;
+}
+
+void DepthwiseConvolutionLayer::run()
+{
+  if (_inputType == OperandType::FLOAT32)
+  {
+    convFloat32();
+  }
+  else if (_inputType == OperandType::QUANT8_ASYMM)
+  {
+    convQuant8();
+  }
+}
+
+} // namespace kernel
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/cpu/kernel/DepthwiseConvolutionLayer.h b/runtime/neurun/backend/cpu/kernel/DepthwiseConvolutionLayer.h
new file mode 100644
index 000000000..575cc0ab1
--- /dev/null
+++ b/runtime/neurun/backend/cpu/kernel/DepthwiseConvolutionLayer.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_KERNEL_CPU_DEPTHWISECONVOLUTIONLAYER_H__
+#define __NEURUN_KERNEL_CPU_DEPTHWISECONVOLUTIONLAYER_H__
+
+#include <exec/IFunction.h>
+
+#include "OperationUtils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace kernel
+{
+
+class DepthwiseConvolutionLayer : public ::neurun::exec::IFunction
+{
+public:
+  DepthwiseConvolutionLayer();
+
+public:
+  void convFloat32();
+
+  void convQuant8();
+
+  void configure(uint8_t *inputData, const TensorDescriptor inputDescr, uint8_t *kernelData,
+                 const TensorDescriptor kernelDescr, uint8_t *biasData,
+                 const TensorDescriptor biasDescr, const uint32_t paddingLeft,
+                 const uint32_t paddingRight, const uint32_t paddingTop,
+                 const uint32_t paddingBottom, const uint32_t strideW, const uint32_t strideH,
+                 const uint32_t multiplier, const ir::Activation activation, uint8_t *outputData,
+                 const TensorDescriptor outputDescr);
+
+  void run();
+  void runSync()
+  {
+    // this abstract method is used just for profiling and called for
+    // backend::acl_common::AclFunction
+    run();
+  }
+
+private:
+  DataPtr _inputData;
+  DataPtr _kernelData;
+  DataPtr _outputData;
+  DataPtr _biasData;
+
+  TensorDescriptor _inputDescr;
+  TensorDescriptor _kernelDescr;
+  TensorDescriptor _outputDescr;
+  TensorDescriptor _biasDescr;
+
+  uint32_t _paddingLeft;
+  uint32_t _paddingTop;
+  uint32_t _paddingRight;
+  uint32_t _paddingBottom;
+
+  uint32_t _strideWidth;
+  uint32_t _strideHeight;
+
+  uint32_t _multiplier;
+
+  ir::Activation _activation;
+
+  OperandType _inputType;
+};
+
+} // namespace kernel
+} // namespace cpu
+} // backend
+} // namespace neurun
+
+#endif // __NEURUN_KERNEL_CPU_DEPTHWISECONVOLUTIONLAYER_H__
diff --git a/runtime/neurun/backend/cpu/kernel/FullyConnectedLayer.cc b/runtime/neurun/backend/cpu/kernel/FullyConnectedLayer.cc
new file mode 100644
index 000000000..055f71590
--- /dev/null
+++ b/runtime/neurun/backend/cpu/kernel/FullyConnectedLayer.cc
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ * Copyright (C) 2017 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "FullyConnectedLayer.h"
+
+#include <cker/operation/FullyConnected.h>
+
+#include "OperationUtils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace kernel
+{
+
+FullyConnectedLayer::FullyConnectedLayer()
+    : _inputData(), _weightsData(), _biasData(), _outputData(), _inputDescr(), _weightsDescr(),
+      _biasDescr(), _outputDescr(), _activation(ir::Activation::NONE),
+      _inputType(OperandType::FLOAT32)
+{
+  // DO NOTHING
+}
+
+void FullyConnectedLayer::fullyConnectedFloat32()
+{
+  float output_activation_min, output_activation_max;
+  CalculateActivationRangeFloat(_activation, &output_activation_min, &output_activation_max);
+
+  nnfw::cker::FullyConnectedParams op_params;
+  op_params.float_activation_min = output_activation_min;
+  op_params.float_activation_max = output_activation_max;
+
+  nnfw::cker::FullyConnected(op_params, convertToExtendedCkerShape(_inputDescr), _inputData.f,
+                             convertToExtendedCkerShape(_weightsDescr), _weightsData.f,
+                             convertToExtendedCkerShape(_biasDescr), _biasData.f,
+                             convertToExtendedCkerShape(_outputDescr), _outputData.f);
+}
+
+// executionMutex is used to protect concurrent access of non-threadsafe resources
+// like gemmlowp::GemmContext.
+void FullyConnectedLayer::fullyConnectedQuant8()
+{
+  float real_multiplier = 0.0;
+  int32_t output_multiplier = 0;
+  int32_t output_shift = 0;
+  int32_t output_activation_min = 0;
+  int32_t output_activation_max = 0;
+  GetQuantizedConvolutionMultiplier(_inputDescr, _weightsDescr, _biasDescr, _outputDescr,
+                                    &real_multiplier);
+  QuantizeMultiplier(real_multiplier, &output_multiplier, &output_shift);
+  CalculateActivationRangeUint8(_activation, _outputDescr, &output_activation_min,
+                                &output_activation_max);
+
+  nnfw::cker::FullyConnectedParams op_params;
+  op_params.input_offset = -_inputDescr.offset;
+  op_params.weights_offset = -_weightsDescr.offset;
+  op_params.output_offset = _outputDescr.offset;
+  op_params.output_multiplier = output_multiplier;
+  op_params.output_shift = output_shift;
+  op_params.quantized_activation_min = output_activation_min;
+  op_params.quantized_activation_max = output_activation_max;
+
+  nnfw::cker::FullyConnected(op_params, convertToExtendedCkerShape(_inputDescr), _inputData.u8,
+                             convertToExtendedCkerShape(_weightsDescr), _weightsData.u8,
+                             convertToExtendedCkerShape(_biasDescr), _biasData.i32,
+                             convertToExtendedCkerShape(_outputDescr), _outputData.u8);
+}
+
+void FullyConnectedLayer::configure(uint8_t *inputData, const TensorDescriptor inputDescr,
+                                    uint8_t *weightsData, const TensorDescriptor weightsDescr,
+                                    uint8_t *biasData, const TensorDescriptor biasDescr,
+                                    ir::Activation activation, uint8_t *outputData,
+                                    const TensorDescriptor outputDescr)
+{
+  _inputData.u8 = inputData;
+  _inputDescr = inputDescr;
+  _inputType = inputDescr.type;
+  _weightsData.u8 = weightsData;
+  _weightsDescr = weightsDescr;
+  _biasData.u8 = biasData;
+  _biasDescr = biasDescr;
+  _activation = activation;
+  _outputData.u8 = outputData;
+  _outputDescr = outputDescr;
+}
+
+void FullyConnectedLayer::run()
+{
+  if (_inputType == OperandType::FLOAT32)
+  {
+    fullyConnectedFloat32();
+  }
+  else if (_inputType == OperandType::QUANT8_ASYMM)
+  {
+    fullyConnectedQuant8();
+  }
+}
+
+} // namespace kernel
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/cpu/kernel/FullyConnectedLayer.h b/runtime/neurun/backend/cpu/kernel/FullyConnectedLayer.h
new file mode 100644
index 000000000..9fdc393a4
--- /dev/null
+++ b/runtime/neurun/backend/cpu/kernel/FullyConnectedLayer.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_CPU_KERNEL_FULLYCONNECTEDLAYER_H__
+#define __NEURUN_BACKEND_CPU_KERNEL_FULLYCONNECTEDLAYER_H__
+
+#include <exec/IFunction.h>
+
+#include "OperationUtils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace kernel
+{
+
+class FullyConnectedLayer : public ::neurun::exec::IFunction
+{
+public:
+  FullyConnectedLayer();
+
+public:
+  void fullyConnectedFloat32();
+
+  void fullyConnectedQuant8();
+
+  void configure(uint8_t *inputData, const TensorDescriptor inputDescr, uint8_t *weightsData,
+                 const TensorDescriptor weightsDescr, uint8_t *biasData,
+                 const TensorDescriptor biasDescr, ir::Activation activation, uint8_t *outputData,
+                 const TensorDescriptor outputDescr);
+
+  void run();
+  void runSync()
+  {
+    // this abstract method is used just for profiling and called for
+    // backend::acl_common::AclFunction
+    run();
+  }
+
+private:
+  DataPtr _inputData;
+  DataPtr _weightsData;
+  DataPtr _biasData;
+  DataPtr _outputData;
+
+  TensorDescriptor _inputDescr;
+  TensorDescriptor _weightsDescr;
+  TensorDescriptor _biasDescr;
+  TensorDescriptor _outputDescr;
+
+  ir::Activation _activation;
+
+  OperandType _inputType;
+};
+
+} // namespace kernel
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_CPU_KERNEL_FULLYCONNECTEDLAYER_H__
diff --git a/runtime/neurun/backend/cpu/kernel/GatherLayer.cc b/runtime/neurun/backend/cpu/kernel/GatherLayer.cc
new file mode 100644
index 000000000..b29acba79
--- /dev/null
+++ b/runtime/neurun/backend/cpu/kernel/GatherLayer.cc
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "GatherLayer.h"
+
+#include <cker/operation/Gather.h>
+
+#include "OperationUtils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace kernel
+{
+
+void GatherLayer::configure(uint8_t *inputData, const TensorDescriptor &inputDescr,
+                            uint8_t *indicesData, const TensorDescriptor &indicesDescr,
+                            uint8_t *outputData, const TensorDescriptor &outputDescr, int32_t axis)
+{
+  _inputData.u8 = inputData;
+  _inputDescr = inputDescr;
+  _indicesData.u8 = indicesData;
+  _indicesDescr = indicesDescr;
+  _axis = axis;
+  _inputType = inputDescr.type;
+  _outputData.u8 = outputData;
+  _outputDescr = outputDescr;
+}
+
+void GatherLayer::run()
+{
+  nnfw::cker::GatherParams op_params;
+  op_params.axis = _axis;
+
+  switch (_inputType)
+  {
+    case OperandType::FLOAT32:
+      nnfw::cker::Gather<float>(op_params, convertTensorDescriptorToCkerShape(_inputDescr),
+                                _inputData.f, convertTensorDescriptorToCkerShape(_indicesDescr),
+                                _indicesData.i32, convertTensorDescriptorToCkerShape(_outputDescr),
+                                _outputData.f);
+      break;
+    case OperandType::QUANT8_ASYMM:
+      nnfw::cker::Gather<uint8_t>(op_params, convertTensorDescriptorToCkerShape(_inputDescr),
+                                  _inputData.u8, convertTensorDescriptorToCkerShape(_indicesDescr),
+                                  _indicesData.i32,
+                                  convertTensorDescriptorToCkerShape(_outputDescr), _outputData.u8);
+      break;
+    case OperandType::INT32:
+      nnfw::cker::Gather<int32_t>(
+          op_params, convertTensorDescriptorToCkerShape(_inputDescr), _inputData.i32,
+          convertTensorDescriptorToCkerShape(_indicesDescr), _indicesData.i32,
+          convertTensorDescriptorToCkerShape(_outputDescr), _outputData.i32);
+      break;
+    default:
+      throw std::runtime_error("Gather NYI for this operand type!");
+  }
+}
+
+} // namespace kernel
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/cpu/kernel/GatherLayer.h b/runtime/neurun/backend/cpu/kernel/GatherLayer.h
new file mode 100644
index 000000000..af4f8b8f6
--- /dev/null
+++ b/runtime/neurun/backend/cpu/kernel/GatherLayer.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_CPU_KERNEL_GATHERLAYER_H__
+#define __NEURUN_BACKEND_CPU_KERNEL_GATHERLAYER_H__
+
+#include <exec/IFunction.h>
+
+#include "OperationUtils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace kernel
+{
+
+class GatherLayer : public ::neurun::exec::IFunction
+{
+public:
+  GatherLayer()
+      : _inputData{nullptr}, _indicesData{nullptr}, _outputData{nullptr}, _axis{-1},
+        _inputType{OperandType::FLOAT32}
+  {
+    // DO NOTHING
+  }
+
+public:
+  void configure(uint8_t *inputData, const TensorDescriptor &inputDescr, uint8_t *indicesData,
+                 const TensorDescriptor &indicesDescr, uint8_t *outputData,
+                 const TensorDescriptor &outputDescr, int32_t axis);
+
+  void run();
+  void runSync()
+  {
+    // this abstract method is used just for profiling and called for
+    // backend::acl_common::AclFunction
+    run();
+  }
+
+private:
+  DataPtr _inputData;
+  DataPtr _indicesData;
+  DataPtr _outputData;
+
+  TensorDescriptor _inputDescr;
+  TensorDescriptor _indicesDescr;
+  TensorDescriptor _outputDescr;
+
+  int32_t _axis;
+  OperandType _inputType;
+};
+
+} // namespace kernel
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_CPU_KERNEL_GATHERLAYER_H__
diff --git a/runtime/neurun/backend/cpu/kernel/LogisticLayer.cc b/runtime/neurun/backend/cpu/kernel/LogisticLayer.cc
new file mode 100644
index 000000000..d9916964e
--- /dev/null
+++ b/runtime/neurun/backend/cpu/kernel/LogisticLayer.cc
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "LogisticLayer.h"
+
+#include <cker/operation/Logistic.h>
+
+#include "OperationUtils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace kernel
+{
+
+LogisticLayer::LogisticLayer()
+    : _inputData(), _outputData(), _inputDescr(), _outputDescr(), _inputType(OperandType::FLOAT32)
+{
+  // DO NOTHING
+}
+
+void LogisticLayer::logisticFloat32()
+{
+  nnfw::cker::Logistic(convertTensorDescriptorToCkerShape(_inputDescr), _inputData.f,
+                       convertTensorDescriptorToCkerShape(_outputDescr), _outputData.f);
+}
+
+void LogisticLayer::logisticQuant8()
+{
+  // cker quant8 logistic is not implemented yet
+  throw std::runtime_error{"NYI"};
+}
+
+void LogisticLayer::configure(uint8_t *inputData, const TensorDescriptor &inputDescr,
+                              uint8_t *outputData, const TensorDescriptor &outputDescr)
+{
+  _inputData.u8 = inputData;
+  _inputDescr = inputDescr;
+  _inputType = inputDescr.type;
+  _outputData.u8 = outputData;
+  _outputDescr = outputDescr;
+}
+
+void LogisticLayer::run()
+{
+  if (_inputType == OperandType::FLOAT32)
+  {
+    logisticFloat32();
+  }
+  else if (_inputType == OperandType::QUANT8_ASYMM)
+  {
+    logisticQuant8();
+  }
+}
+
+} // namespace kernel
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/cpu/kernel/LogisticLayer.h b/runtime/neurun/backend/cpu/kernel/LogisticLayer.h
new file mode 100644
index 000000000..33fcd6fed
--- /dev/null
+++ b/runtime/neurun/backend/cpu/kernel/LogisticLayer.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_CPU_KERNEL_LOGISTICLAYER_H__
+#define __NEURUN_BACKEND_CPU_KERNEL_LOGISTICLAYER_H__
+
+#include <exec/IFunction.h>
+
+#include "OperationUtils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace kernel
+{
+
+class LogisticLayer : public ::neurun::exec::IFunction
+{
+public:
+  LogisticLayer();
+
+public:
+  void logisticFloat32();
+
+  void logisticQuant8();
+
+  void configure(uint8_t *inputData, const TensorDescriptor &inputDescr, uint8_t *outputData,
+                 const TensorDescriptor &outputDescr);
+
+  void run();
+  void runSync()
+  {
+    // this abstract method is used just for profiling and called for
+    // backend::acl_common::AclFunction
+    run();
+  }
+
+private:
+  DataPtr _inputData;
+  DataPtr _outputData;
+
+  TensorDescriptor _inputDescr;
+  TensorDescriptor _outputDescr;
+
+  OperandType _inputType;
+};
+
+} // namespace kernel
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_CPU_KERNEL_LOGISTICLAYER_H__
diff --git a/runtime/neurun/backend/cpu/kernel/MaxPoolLayer.cc b/runtime/neurun/backend/cpu/kernel/MaxPoolLayer.cc
new file mode 100644
index 000000000..095cd6d1d
--- /dev/null
+++ b/runtime/neurun/backend/cpu/kernel/MaxPoolLayer.cc
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "MaxPoolLayer.h"
+
+#include <cker/operation/MaxPool.h>
+
+#include "OperationUtils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace kernel
+{
+
+#define MAXPOOLING_PARAMETERS                            \
+  nnfw::cker::PoolParams op_params;                      \
+  op_params.stride_height = _strideHeight;               \
+  op_params.stride_width = _strideWidth;                 \
+  op_params.filter_height = _kernelHeight;               \
+  op_params.filter_width = _kernelWidth;                 \
+  op_params.padding_values.height = (int8_t)_paddingTop; \
+  op_params.padding_values.width = (int8_t)_paddingLeft;
+
+MaxPoolLayer::MaxPoolLayer()
+    : _inputData(), _outputData(), _inputDescr(), _outputDescr(), _paddingLeft(0), _paddingTop(0),
+      _paddingRight(0), _paddingBottom(0), _strideWidth(0), _strideHeight(0), _kernelWidth(0),
+      _kernelHeight(0), _activation(ir::Activation::NONE), _inputType(OperandType::FLOAT32)
+{
+  // DO NOTHING
+}
+
+void MaxPoolLayer::maxPoolFloat32()
+{
+  MAXPOOLING_PARAMETERS
+  float output_activation_min, output_activation_max;
+  CalculateActivationRangeFloat(_activation, &output_activation_min, &output_activation_max);
+  op_params.float_activation_min = output_activation_min;
+  op_params.float_activation_max = output_activation_max;
+
+  nnfw::cker::MaxPool(op_params, convertTensorDescriptorToCkerShape(_inputDescr), _inputData.f,
+                      convertTensorDescriptorToCkerShape(_outputDescr), _outputData.f);
+}
+void MaxPoolLayer::maxPoolQuant8()
+{
+  MAXPOOLING_PARAMETERS
+  int32_t output_activation_min = 0;
+  int32_t output_activation_max = 0;
+  CalculateActivationRangeUint8(_activation, _outputDescr, &output_activation_min,
+                                &output_activation_max);
+  op_params.quantized_activation_min = output_activation_min;
+  op_params.quantized_activation_max = output_activation_max;
+
+  nnfw::cker::MaxPool(op_params, convertTensorDescriptorToCkerShape(_inputDescr), _inputData.u8,
+                      convertTensorDescriptorToCkerShape(_outputDescr), _outputData.u8);
+}
+
+void MaxPoolLayer::configure(uint8_t *inputData, const TensorDescriptor inputDescr,
+                             const uint32_t paddingLeft, const uint32_t paddingRight,
+                             const uint32_t paddingTop, const uint32_t paddingBottom,
+                             const uint32_t strideWidth, const uint32_t strideHeight,
+                             const uint32_t kernelWidth, const uint32_t kernelHeight,
+                             const ir::Activation activation, uint8_t *outputData,
+                             const TensorDescriptor outputDescr)
+{
+  _inputData.u8 = inputData;
+
+  _inputDescr = inputDescr;
+  _inputType = inputDescr.type;
+  _paddingLeft = paddingLeft;
+  _paddingRight = paddingRight;
+  _paddingTop = paddingTop;
+  _paddingBottom = paddingBottom;
+  _strideWidth = strideWidth;
+  _strideHeight = strideHeight;
+  _kernelWidth = kernelWidth;
+  _kernelHeight = kernelHeight;
+  _activation = activation;
+  _outputData.u8 = outputData;
+  _outputDescr = outputDescr;
+}
+
+void MaxPoolLayer::run()
+{
+  if (_inputType == OperandType::FLOAT32)
+  {
+    maxPoolFloat32();
+  }
+  else if (_inputType == OperandType::QUANT8_ASYMM)
+  {
+    maxPoolQuant8();
+  }
+}
+
+#undef MAXPOOLING_PARAMETERS
+
+} // namespace kernel
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/cpu/kernel/MaxPoolLayer.h b/runtime/neurun/backend/cpu/kernel/MaxPoolLayer.h
new file mode 100644
index 000000000..88a574c42
--- /dev/null
+++ b/runtime/neurun/backend/cpu/kernel/MaxPoolLayer.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_CPU_KERNEL_MAXPOOLLAYER_H__
+#define __NEURUN_BACKEND_CPU_KERNEL_MAXPOOLLAYER_H__
+
+#include <exec/IFunction.h>
+
+#include "OperationUtils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace kernel
+{
+
+class MaxPoolLayer : public ::neurun::exec::IFunction
+{
+public:
+  MaxPoolLayer();
+
+public:
+  void maxPoolFloat32();
+
+  void maxPoolQuant8();
+
+  void configure(uint8_t *inputData, const TensorDescriptor inputDescr, const uint32_t paddingLeft,
+                 const uint32_t paddingRight, const uint32_t paddingTop,
+                 const uint32_t paddingBottom, const uint32_t strideWidth,
+                 const uint32_t strideHeight, const uint32_t kernelWidth,
+                 const uint32_t kernelHeight, const ir::Activation activation, uint8_t *outputData,
+                 const TensorDescriptor outputDescr);
+
+  void run();
+  void runSync()
+  {
+    // this abstract method is used just for profiling and called for
+    // backend::acl_common::AclFunction
+    run();
+  }
+
+private:
+  DataPtr _inputData;
+  DataPtr _outputData;
+
+  TensorDescriptor _inputDescr;
+  TensorDescriptor _outputDescr;
+
+  uint32_t _paddingLeft;
+  uint32_t _paddingTop;
+  uint32_t _paddingRight;
+  uint32_t _paddingBottom;
+
+  uint32_t _strideWidth;
+  uint32_t _strideHeight;
+  uint32_t _kernelWidth;
+  uint32_t _kernelHeight;
+
+  ir::Activation _activation;
+
+  OperandType _inputType;
+};
+
+} // namespace kernel
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_CPU_KERNEL_MAXPOOLLAYER_H__
diff --git a/runtime/neurun/backend/cpu/kernel/MulLayer.cc b/runtime/neurun/backend/cpu/kernel/MulLayer.cc
new file mode 100644
index 000000000..d6ce2cfad
--- /dev/null
+++ b/runtime/neurun/backend/cpu/kernel/MulLayer.cc
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "MulLayer.h"
+
+#include <cker/operation/BinaryArithmeticOps.h>
+
+#include "OperationUtils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace kernel
+{
+
+void MulLayer::mulFloat32()
+{
+  float output_activation_min, output_activation_max;
+  CalculateActivationRangeFloat(_activation, &output_activation_min, &output_activation_max);
+  nnfw::cker::BinaryArithmeticOpParam op_params;
+  op_params.float_activation_max = output_activation_max;
+  op_params.float_activation_min = output_activation_min;
+
+  const std::function<float(const float &, const float &)> fn = [](const float &a, const float &b) {
+    return a * b;
+  };
+
+  if (!HaveSameShapes(&_lhsDescr, &_rhsDescr))
+  {
+    nnfw::cker::BroadcastBinaryArithmeticOpSlow(
+        op_params, convertToExtendedCkerShape(_lhsDescr), _lhsData.f,
+        convertToExtendedCkerShape(_rhsDescr), _rhsData.f, convertToExtendedCkerShape(_outputDescr),
+        _outputData.f, fn);
+    return;
+  }
+
+  nnfw::cker::BinaryArithmeticOp(op_params, convertTensorDescriptorToCkerShape(_lhsDescr),
+                                 _lhsData.f, convertTensorDescriptorToCkerShape(_rhsDescr),
+                                 _rhsData.f, convertTensorDescriptorToCkerShape(_outputDescr),
+                                 _outputData.f, fn);
+}
+
+void MulLayer::mulQuant8()
+{
+  int32_t output_activation_min, output_activation_max;
+  CalculateActivationRangeUint8(_activation, _outputDescr, &output_activation_min,
+                                &output_activation_max);
+  // nnfw::cker::BinaryArithmeticOpParam op_params;
+  // op_params.quantized_activation_max = output_activation_max;
+  // op_params.quantized_activation_min = output_activation_min;
+
+  // cker quant8 mul is not implemented yet
+  throw std::runtime_error{"Mull NYI for quantized"};
+}
+
+void MulLayer::configure(uint8_t *lhsData, const TensorDescriptor &lhsDescr, uint8_t *rhsData,
+                         const TensorDescriptor &rhsDescr, const ir::Activation activation,
+                         uint8_t *outputData, const TensorDescriptor &outputDescr)
+{
+  _lhsData.u8 = lhsData;
+  _lhsDescr = lhsDescr;
+  _rhsData.u8 = rhsData;
+  _rhsDescr = rhsDescr;
+  _inputType = lhsDescr.type;
+  _activation = activation;
+  _outputData.u8 = outputData;
+  _outputDescr = outputDescr;
+}
+
+void MulLayer::run()
+{
+  if (_inputType == OperandType::FLOAT32)
+  {
+    mulFloat32();
+  }
+  else if (_inputType == OperandType::QUANT8_ASYMM)
+  {
+    mulQuant8();
+  }
+}
+
+} // namespace kernel
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/cpu/kernel/MulLayer.h b/runtime/neurun/backend/cpu/kernel/MulLayer.h
new file mode 100644
index 000000000..05fc3052f
--- /dev/null
+++ b/runtime/neurun/backend/cpu/kernel/MulLayer.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_CPU_KERNEL_MULLAYER_H__
+#define __NEURUN_BACKEND_CPU_KERNEL_MULLAYER_H__
+
+#include <exec/IFunction.h>
+
+#include "OperationUtils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace kernel
+{
+
+class MulLayer : public ::neurun::exec::IFunction
+{
+public:
+  MulLayer() : _lhsData(), _rhsData(), _outputData(), _lhsDescr(), _rhsDescr(), _outputDescr()
+  {
+    // DO NOTHING
+  }
+
+public:
+  void mulFloat32();
+
+  void mulQuant8();
+
+  void configure(uint8_t *lhsData, const TensorDescriptor &lhsDescr, uint8_t *rhsData,
+                 const TensorDescriptor &rhsDescr, const ir::Activation activation,
+                 uint8_t *outputData, const TensorDescriptor &outputDescr);
+
+  void run();
+  void runSync()
+  {
+    // this abstract method is used just for profiling and called for
+    // backend::acl_common::AclFunction
+    run();
+  }
+
+private:
+  DataPtr _lhsData;
+  DataPtr _rhsData;
+  DataPtr _outputData;
+
+  TensorDescriptor _lhsDescr;
+  TensorDescriptor _rhsDescr;
+  TensorDescriptor _outputDescr;
+
+  ir::Activation _activation{ir::Activation::NONE};
+
+  OperandType _inputType{OperandType::FLOAT32};
+};
+
+} // namespace kernel
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_CPU_KERNEL_MULLAYER_H__
diff --git a/runtime/neurun/backend/cpu/kernel/OperationUtils.cc b/runtime/neurun/backend/cpu/kernel/OperationUtils.cc
new file mode 100644
index 000000000..8aa15dcbd
--- /dev/null
+++ b/runtime/neurun/backend/cpu/kernel/OperationUtils.cc
@@ -0,0 +1,273 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "OperationUtils.h"
+
+#include <cmath>
+#include <algorithm>
+#include <cassert>
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace kernel
+{
+
+uint32_t getNumberOfDimensions(const TensorDescriptor &descr) { return descr.dimensions.size(); }
+
+uint32_t getNumberOfElements(const TensorDescriptor &descr)
+{
+  uint32_t count = 1;
+  for (size_t i = 0; i < descr.dimensions.size(); i++)
+  {
+    count *= descr.dimensions[i];
+  }
+  return count;
+}
+
+uint32_t getSizeOfDimension(const TensorDescriptor &descr, uint32_t dimensionIdx)
+{
+  if (dimensionIdx >= descr.dimensions.size())
+  {
+    // TODO, log the error
+    return 0;
+  }
+  return descr.dimensions[dimensionIdx];
+}
+
+void QuantizeMultiplier(double double_multiplier, int32_t *quantized_multiplier, int *shift)
+{
+  if (double_multiplier == 0.)
+  {
+    *quantized_multiplier = 0;
+    *shift = 0;
+    return;
+  }
+  const double q = std::frexp(double_multiplier, shift);
+  auto q_fixed = static_cast<int64_t>(std::round(q * (1ll << 31)));
+
+  assert(q_fixed <= (1ll << 31));
+  if (q_fixed == (1ll << 31))
+  {
+    q_fixed /= 2;
+    ++*shift;
+  }
+  assert(q_fixed <= std::numeric_limits<int32_t>::max());
+  *quantized_multiplier = static_cast<int32_t>(q_fixed);
+}
+
+void GetQuantizedConvolutionMultiplier(const TensorDescriptor &inputDescr,
+                                       const TensorDescriptor &filterDescr,
+                                       const TensorDescriptor &biasDescr,
+                                       const TensorDescriptor &outputDescr, float *multiplier)
+{
+  const float input_product_scale = inputDescr.scale * filterDescr.scale;
+  const float bias_scale = biasDescr.scale;
+  const float output_scale = outputDescr.scale;
+  // The following conditions must be guaranteed by the training pipeline.
+  UNUSED_RELEASE(bias_scale);
+  assert(std::abs(input_product_scale - bias_scale) <=
+         1e-6 * std::min(input_product_scale, bias_scale));
+  assert(input_product_scale >= 0);
+  assert(input_product_scale < output_scale);
+  *multiplier = input_product_scale / output_scale;
+}
+
+void QuantizeMultiplierGreaterThanOne(double double_multiplier, int32_t *quantized_multiplier,
+                                      int *left_shift)
+{
+  assert(double_multiplier > 1.);
+  const double q = std::frexp(double_multiplier, left_shift);
+  int64_t q_fixed = static_cast<int64_t>(std::round(q * (1ll << 31)));
+  assert(q_fixed <= (1ll << 31));
+  if (q_fixed == (1ll << 31))
+  {
+    q_fixed /= 2;
+    ++*left_shift;
+  }
+  assert(*left_shift >= 0);
+  assert(q_fixed <= std::numeric_limits<int32_t>::max());
+  *quantized_multiplier = static_cast<int32_t>(q_fixed);
+}
+
+void CalculateActivationRangeFloat(ir::Activation activation, float *activation_min,
+                                   float *activation_max)
+{
+  if (activation == ir::Activation::RELU)
+  {
+    *activation_min = 0.f;
+    *activation_max = std::numeric_limits<float>::max();
+  }
+  else if (activation == ir::Activation::RELU6)
+  {
+    *activation_min = 0.f;
+    *activation_max = 6.f;
+  }
+  else if (activation == ir::Activation::RELU1)
+  {
+    *activation_min = -1.f;
+    *activation_max = 1.f;
+  }
+  else if (activation == ir::Activation::SIGMOID)
+  {
+    *activation_min = 0.f;
+    *activation_max = 1.f;
+  }
+  else if (activation == ir::Activation::NONE)
+  {
+    *activation_min = std::numeric_limits<float>::lowest();
+    *activation_max = std::numeric_limits<float>::max();
+  }
+  else
+  {
+    std::cout << "Unsupported fused activation function." << std::endl;
+  }
+}
+
+void CalculateActivationRangeUint8(ir::Activation activation, const TensorDescriptor &outputDescr,
+                                   int32_t *act_min, int32_t *act_max)
+{
+  const int32_t qmin = std::numeric_limits<uint8_t>::min();
+  const int32_t qmax = std::numeric_limits<uint8_t>::max();
+  const auto scale = outputDescr.scale;
+  const auto zero_point = outputDescr.offset;
+  auto quantize = [scale, zero_point](float f) {
+    return zero_point + static_cast<int32_t>(std::round(f / scale));
+  };
+  if (activation == ir::Activation::RELU)
+  {
+    *act_min = std::max(qmin, quantize(0.0));
+    *act_max = qmax;
+  }
+  else if (activation == ir::Activation::RELU6)
+  {
+    *act_min = std::max(qmin, quantize(0.0));
+    *act_max = std::min(qmax, quantize(6.0));
+  }
+  else if (activation == ir::Activation::RELU1)
+  {
+    *act_min = std::max(qmin, quantize(-1.0));
+    *act_max = std::min(qmax, quantize(1.0));
+  }
+  else if (activation == ir::Activation::SIGMOID)
+  {
+    *act_min = std::max(qmin, quantize(0.0));
+    *act_max = std::min(qmax, quantize(1.0));
+  }
+  else if (activation == ir::Activation::NONE)
+  {
+    *act_min = qmin;
+    *act_max = qmax;
+  }
+  else
+  {
+    std::cout << "Unsupported fused activation function." << std::endl;
+  }
+}
+
+bool HaveSameShapes(const TensorDescriptor *input1, const TensorDescriptor *input2)
+{
+  if (input1 == input2)
+    return true;
+  if (input2 == NULL || input2 == NULL)
+    return false;
+
+  if (input1 == NULL)
+  {
+    return (getNumberOfDimensions(*input2) == 0);
+  }
+
+  if (getNumberOfDimensions(*input1) != getNumberOfDimensions(*input2))
+    return false;
+
+  for (uint32_t i = 0; i < getNumberOfDimensions(*input1); i++)
+    if (input1->dimensions[i] != input2->dimensions[i])
+      return false;
+
+  return true;
+}
+
+int32_t CalculateInputRadius(int input_integer_bits, int input_left_shift)
+{
+  const double max_input_rescaled = 1.0 * ((1 << input_integer_bits) - 1) *
+                                    (1ll << (31 - input_integer_bits)) / (1ll << input_left_shift);
+  // Tighten bound using floor.  Suppose that we could use the exact value.
+  // After scaling the difference, the result would be at the maximum.  Thus we
+  // must ensure that our value has lower magnitude.
+  return static_cast<int32_t>(std::floor(max_input_rescaled));
+}
+
+TensorDescriptor getTensorDescriptor(const ir::Operand &o, ir::Layout frontend_layout)
+{
+  TensorDescriptor descriptor;
+
+  auto dims = o.shape().dims();
+  if (frontend_layout == ir::Layout::NCHW && o.shape().rank() == 4)
+  {
+    // NCHW -> NHWC
+    uint32_t permutation[4] = {0, 2, 3, 1};
+    for (int i = 0; i < o.shape().rank(); ++i)
+    {
+      dims.at(i) = o.shape().dim(permutation[i]);
+    }
+  }
+  descriptor.dimensions = std::vector<uint32_t>(dims.begin(), dims.end());
+  descriptor.type = static_cast<OperandType>(static_cast<int32_t>(o.typeInfo().type()));
+  descriptor.scale = o.typeInfo().scale();
+  descriptor.offset = o.typeInfo().offset();
+
+  // CPU backend assume that neurun internal shape's rank is always same or less than 4
+  assert(descriptor.dimensions.size() <= 4);
+
+  return descriptor;
+}
+
+uint32_t sizeOfData(OperandType type, const std::vector<uint32_t> &dimensions)
+{
+  uint32_t size = 4;
+
+  switch (type)
+  {
+    case OperandType::FLOAT32:
+    case OperandType::INT32:
+    case OperandType::UINT32:
+      size = 4;
+      break;
+    case OperandType::BOOL8:
+    case OperandType::QUANT8_ASYMM:
+    case OperandType::QUANT8_SYMM:
+      size = 1;
+      break;
+    default:
+      throw std::runtime_error("Not supported operand type.");
+      break;
+  }
+
+  for (auto d : dimensions)
+  {
+    size *= d;
+  }
+
+  return size;
+}
+
+} // namespace kernel
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/cpu/kernel/OperationUtils.h b/runtime/neurun/backend/cpu/kernel/OperationUtils.h
new file mode 100644
index 000000000..b9e8c8974
--- /dev/null
+++ b/runtime/neurun/backend/cpu/kernel/OperationUtils.h
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NNFW_SUPPORT_NNAPI_OPERATION_UTILS_H__
+#define __NNFW_SUPPORT_NNAPI_OPERATION_UTILS_H__
+
+#include <iostream>
+#include <limits>
+#include <vector>
+
+#include <cker/Shape.h>
+
+#include "ir/Operand.h"
+#include "ir/DataType.h"
+#include <ir/InternalType.h>
+
+using OperandType = neurun::ir::DataType;
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace kernel
+{
+
+struct TensorDescriptor
+{
+  OperandType type;
+  std::vector<uint32_t> dimensions;
+  float scale;
+  int32_t offset;
+};
+
+union DataPtr {
+  uint8_t *u8;
+  int8_t *i8;
+  int32_t *i32;
+  float *f;
+  void *v;
+};
+
+uint32_t getNumberOfDimensions(const TensorDescriptor &descr);
+
+uint32_t getNumberOfElements(const TensorDescriptor &descr);
+
+uint32_t getSizeOfDimension(const TensorDescriptor &descr, uint32_t dimensionIdx);
+
+inline nnfw::cker::Shape convertToExtendedCkerShape(const TensorDescriptor &descr)
+{
+  std::vector<int32_t> raw_shape;
+  raw_shape.resize(4);
+
+  uint32_t src = 4 - descr.dimensions.size();
+  for (uint32_t i = 0; i < 4; ++i)
+  {
+    if (i < src)
+    {
+      raw_shape[i] = 1;
+    }
+    else
+    {
+      raw_shape[i] = descr.dimensions[i - src];
+    }
+  }
+
+  return nnfw::cker::GetShape(raw_shape);
+}
+
+inline nnfw::cker::Shape convertTensorDescriptorToCkerShape(const TensorDescriptor &descr)
+{
+  std::vector<int32_t> raw_shape;
+  raw_shape.resize(4);
+
+  for (uint32_t i = 0; i < 4; ++i)
+  {
+    if (i >= descr.dimensions.size())
+    {
+      raw_shape[i] = 1;
+    }
+    else
+    {
+      raw_shape[i] = descr.dimensions[i];
+    }
+  }
+
+  return nnfw::cker::GetShape(raw_shape);
+}
+
+inline int32_t getAxis(uint32_t rank, int32_t axis, ir::Layout frontend_layout)
+{
+  auto ret = axis;
+
+  if (axis < 0)
+  {
+    ret += rank;
+  }
+
+  // NCHW -> NHWC
+  if (frontend_layout == ir::Layout::NCHW)
+  {
+    int32_t permutation[4] = {0, 3, 1, 2};
+    ret = permutation[ret];
+  }
+
+  return ret;
+}
+
+void QuantizeMultiplier(double double_multiplier, int32_t *quantized_multiplier, int *shift);
+
+void GetQuantizedConvolutionMultiplier(const TensorDescriptor &inputDescr,
+                                       const TensorDescriptor &filterDescr,
+                                       const TensorDescriptor &biasDescr,
+                                       const TensorDescriptor &outputDescr, float *multiplier);
+
+void QuantizeMultiplierGreaterThanOne(double double_multiplier, int32_t *quantized_multiplier,
+                                      int *left_shift);
+
+void CalculateActivationRangeFloat(ir::Activation activation, float *activation_min,
+                                   float *activation_max);
+
+void CalculateActivationRangeUint8(ir::Activation activation, const TensorDescriptor &outputDescr,
+                                   int32_t *act_min, int32_t *act_max);
+
+bool HaveSameShapes(const TensorDescriptor *input1, const TensorDescriptor *input2);
+
+int32_t CalculateInputRadius(int input_integer_bits, int input_left_shift);
+
+TensorDescriptor getTensorDescriptor(const ir::Operand &o, ir::Layout frontend_layout);
+
+uint32_t sizeOfData(OperandType type, const std::vector<uint32_t> &dimensions);
+
+} // namespace kernel
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
+
+#endif // __NNFW_SUPPORT_NNAPI_OPERATION_UTILS_H__
diff --git a/runtime/neurun/backend/cpu/kernel/PadLayer.cc b/runtime/neurun/backend/cpu/kernel/PadLayer.cc
new file mode 100644
index 000000000..1fd9429b5
--- /dev/null
+++ b/runtime/neurun/backend/cpu/kernel/PadLayer.cc
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "PadLayer.h"
+
+#include "OperationUtils.h"
+
+#include <cker/operation/Pad.h>
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace kernel
+{
+
+PadLayer::PadLayer()
+    : _inputData(), _outputData(), _inputDescr(), _outputDescr(), _padData(), _padRank(),
+      _constantValueData(), _inputType(OperandType::FLOAT32)
+{
+  // DO NOTHING
+}
+
+void PadLayer::padFloat32()
+{
+  nnfw::cker::Pad(_padData, _padRank, convertTensorDescriptorToCkerShape(_inputDescr), _inputData.f,
+                  convertTensorDescriptorToCkerShape(_outputDescr), _outputData.f,
+                  _constantValueData.f);
+}
+void PadLayer::padQuant8() { throw std::runtime_error("Quantized Pad isn't supported NYI"); }
+
+void PadLayer::configure(uint8_t *inputData, const TensorDescriptor inputDescr, uint8_t *outputData,
+                         const TensorDescriptor outputDescr, const int32_t *padData,
+                         int32_t padRank, uint8_t *constantValueData)
+{
+  _inputData.u8 = inputData;
+  _inputDescr = inputDescr;
+  _inputType = inputDescr.type;
+  _outputData.u8 = outputData;
+  _outputDescr = outputDescr;
+  _padData = padData;
+  _padRank = padRank;
+  _constantValueData.u8 = constantValueData;
+}
+
+void PadLayer::run()
+{
+  if (_inputType == OperandType::FLOAT32)
+  {
+    padFloat32();
+  }
+  else if (_inputType == OperandType::QUANT8_ASYMM)
+  {
+    padQuant8();
+  }
+}
+
+} // namespace kernel
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/cpu/kernel/PadLayer.h b/runtime/neurun/backend/cpu/kernel/PadLayer.h
new file mode 100644
index 000000000..f4413a8ed
--- /dev/null
+++ b/runtime/neurun/backend/cpu/kernel/PadLayer.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_CPU_KERNEL_PADLAYER_H__
+#define __NEURUN_BACKEND_CPU_KERNEL_PADLAYER_H__
+
+#include <exec/IFunction.h>
+
+#include "OperationUtils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace kernel
+{
+
+// Note, this is pad with mode=`CONSTANT`: it doesn't support `REFLECT` and `SYMMETRIC`
+class PadLayer : public ::neurun::exec::IFunction
+{
+public:
+  PadLayer();
+
+public:
+  void padFloat32();
+
+  void padQuant8();
+
+  void configure(uint8_t *inputData, const TensorDescriptor inputDescr, uint8_t *outputData,
+                 const TensorDescriptor outputDescr, const int32_t *padData, int32_t padRank,
+                 uint8_t *constantValueData = nullptr);
+
+  void run();
+  void runSync()
+  {
+    // this abstract method is used just for profiling and called for
+    // backend::acl_common::AclFunction
+    run();
+  }
+
+private:
+  DataPtr _inputData;
+  DataPtr _outputData;
+
+  TensorDescriptor _inputDescr;
+  TensorDescriptor _outputDescr;
+
+  const int32_t *_padData;
+  int32_t _padRank;
+  DataPtr _constantValueData;
+
+  OperandType _inputType;
+};
+
+} // namespace kernel
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_CPU_KERNEL_PADLAYER_H__
diff --git a/runtime/neurun/backend/cpu/kernel/PermuteLayer.cc b/runtime/neurun/backend/cpu/kernel/PermuteLayer.cc
new file mode 100644
index 000000000..6f28d8436
--- /dev/null
+++ b/runtime/neurun/backend/cpu/kernel/PermuteLayer.cc
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "PermuteLayer.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace kernel
+{
+
+using Type = ir::operation::Permute::Type;
+
+void PermuteLayer::configure(std::shared_ptr<backend::operand::ITensor> input,
+                             std::shared_ptr<backend::operand::ITensor> output,
+                             const ir::Shape &output_shape, Type type, ir::DataType dataType)
+{
+  _input = input;
+  _output = output;
+  _output_shape = output_shape;
+  _type = type;
+  _dataType = dataType;
+}
+
+void PermuteLayer::run()
+{
+  using ir::DataType;
+  switch (_dataType)
+  {
+    case DataType::FLOAT32:
+      runTempl<float>();
+      break;
+    case DataType::INT32:
+      runTempl<int32_t>();
+      break;
+    case DataType::UINT32:
+      runTempl<uint32_t>();
+      break;
+    case DataType::BOOL8:
+    case DataType::QUANT8_ASYMM:
+      runTempl<uint8_t>();
+      break;
+    case DataType::QUANT8_SYMM:
+      runTempl<int8_t>();
+      break;
+    default:
+      throw std::runtime_error("NYI");
+      break;
+  }
+}
+
+} // namespace kernel
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/cpu/kernel/PermuteLayer.h b/runtime/neurun/backend/cpu/kernel/PermuteLayer.h
new file mode 100644
index 000000000..1f9110807
--- /dev/null
+++ b/runtime/neurun/backend/cpu/kernel/PermuteLayer.h
@@ -0,0 +1,209 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_CPU_KERNEL_PERMUTE_LAYER_H__
+#define __NEURUN_BACKEND_CPU_KERNEL_PERMUTE_LAYER_H__
+
+#include <exec/IFunction.h>
+
+#include "util/feature/nhwc/View.h"
+#include "OperationUtils.h"
+#include "ir/operation/Permute.h"
+#include "util/feature/nhwc/Reader.h"
+#include "util/feature/nchw/View.h"
+#include "util/Coordinates.h"
+
+#include <misc/feature/IndexIterator.h>
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace kernel
+{
+
+class PermuteLayer : public ::neurun::exec::IFunction
+{
+public:
+  PermuteLayer() = default;
+
+public:
+  void configure(std::shared_ptr<backend::operand::ITensor> input,
+                 std::shared_ptr<backend::operand::ITensor> output, const ir::Shape &output_shape,
+                 ir::operation::Permute::Type type, ir::DataType dataType);
+  void run();
+  void runSync()
+  {
+    // this abstract method is used just for profiling and called for
+    // backend::acl_common::AclFunction
+    run();
+  }
+
+private:
+  template <class T> void runTempl()
+  {
+    auto rank = _output_shape.rank();
+    auto fn = [&](::neurun::backend::operand::ITensor &in_tensor) {
+      _output->access([&](::neurun::backend::operand::ITensor &out_tensor) {
+        auto input_buffer = in_tensor.buffer();
+        auto input_size = in_tensor.total_size();
+        auto output_buffer = out_tensor.buffer();
+        if (_type == ir::operation::Permute::Type::COPY)
+        {
+          assert(in_tensor.layout() == out_tensor.layout());
+          if (!in_tensor.has_padding() && !out_tensor.has_padding())
+          {
+            assert(input_size == out_tensor.total_size());
+            memcpy(output_buffer, input_buffer, input_size);
+            return;
+          }
+        }
+        switch (rank)
+        {
+          case 0:
+          case 1:
+          {
+            const int32_t copy_len = _output_shape.dim(0);
+
+            memcpy(output_buffer, input_buffer, copy_len);
+            break;
+          }
+          case 2:
+          {
+            const int32_t copy_len = _output_shape.dim(1);
+
+            for (auto i = 0; i < _output_shape.dim(0); ++i)
+            {
+              neurun::util::Coordinates coords{i, 0};
+              memcpy(output_buffer + out_tensor.calcOffset(coords),
+                     input_buffer + in_tensor.calcOffset(coords), copy_len * sizeof(T));
+            }
+            break;
+          }
+          case 3:
+          {
+            const int32_t copy_len = _output_shape.dim(2);
+
+            for (auto i = 0; i < _output_shape.dim(0); ++i)
+            {
+              for (auto j = 0; j < _output_shape.dim(1); ++j)
+              {
+                neurun::util::Coordinates coords{i, j, 0};
+                memcpy(output_buffer + out_tensor.calcOffset(coords),
+                       input_buffer + in_tensor.calcOffset(coords), copy_len * sizeof(T));
+              }
+            }
+            break;
+          }
+          case 4:
+          {
+            // TODO Unify permute type and remove switch case
+            switch (_type)
+            {
+              case ir::operation::Permute::Type::NHWC_TO_NCHW:
+              {
+                for (auto n = 0; n < _output_shape.dim(0); ++n)
+                {
+                  for (auto c = 0; c < _output_shape.dim(1); ++c)
+                  {
+                    for (auto h = 0; h < _output_shape.dim(2); ++h)
+                    {
+                      for (auto w = 0; w < _output_shape.dim(3); ++w)
+                      {
+                        const neurun::util::Coordinates in_coords{n, h, w, c};
+                        const auto out_coords =
+                            convertCoordinates(in_coords, in_tensor.layout(), out_tensor.layout());
+                        const auto value =
+                            *reinterpret_cast<T *>(input_buffer + in_tensor.calcOffset(in_coords));
+                        *reinterpret_cast<T *>(output_buffer + out_tensor.calcOffset(out_coords)) =
+                            value;
+                      }
+                    }
+                  }
+                }
+                break;
+              }
+              case ir::operation::Permute::Type::NCHW_TO_NHWC:
+              {
+                for (auto n = 0; n < _output_shape.dim(0); ++n)
+                {
+                  for (auto h = 0; h < _output_shape.dim(1); ++h)
+                  {
+                    for (auto w = 0; w < _output_shape.dim(2); ++w)
+                    {
+                      for (auto c = 0; c < _output_shape.dim(3); ++c)
+                      {
+                        const neurun::util::Coordinates in_coords{n, c, h, w};
+                        const auto out_coords =
+                            convertCoordinates(in_coords, in_tensor.layout(), out_tensor.layout());
+                        const auto value =
+                            *reinterpret_cast<T *>(input_buffer + in_tensor.calcOffset(in_coords));
+                        *reinterpret_cast<T *>(output_buffer + out_tensor.calcOffset(out_coords)) =
+                            value;
+                      }
+                    }
+                  }
+                }
+                break;
+              }
+              case ir::operation::Permute::Type::COPY:
+              {
+                const int32_t copy_len = _output_shape.dim(3);
+
+                for (auto i = 0; i < _output_shape.dim(0); ++i)
+                {
+                  for (auto j = 0; j < _output_shape.dim(1); ++j)
+                  {
+                    for (auto k = 0; k < _output_shape.dim(2); ++k)
+                    {
+                      neurun::util::Coordinates coords{i, j, k, 0};
+                      memcpy(output_buffer + out_tensor.calcOffset(coords),
+                             input_buffer + in_tensor.calcOffset(coords), copy_len * sizeof(T));
+                    }
+                  }
+                }
+                break;
+              }
+              default:
+                throw std::runtime_error("NYI");
+                break;
+            }
+            break;
+          }
+          default:
+            throw std::runtime_error("NYI");
+            break;
+        }
+      });
+    };
+    _input->access(fn);
+  }
+
+private:
+  std::shared_ptr<backend::operand::ITensor> _input{nullptr};
+  std::shared_ptr<backend::operand::ITensor> _output{nullptr};
+  ir::Shape _output_shape{};
+  ir::operation::Permute::Type _type{ir::operation::Permute::Type::COPY};
+  ir::DataType _dataType{ir::DataType::FLOAT32};
+};
+
+} // namespace kernel
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_CPU_KERNEL_PERMUTE_LAYER_H__
diff --git a/runtime/neurun/backend/cpu/kernel/ReshapeLayer.cc b/runtime/neurun/backend/cpu/kernel/ReshapeLayer.cc
new file mode 100644
index 000000000..caeee9f12
--- /dev/null
+++ b/runtime/neurun/backend/cpu/kernel/ReshapeLayer.cc
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ * Copyright (C) 2017 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ReshapeLayer.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace kernel
+{
+
+ReshapeLayer::ReshapeLayer() : _inputData(), _outputData(), _inputDescr(), _outputDescr()
+{
+  // DO NOTHING
+}
+
+void ReshapeLayer::reshapeGeneric()
+{
+  size_t count = sizeOfData(_inputDescr.type, _inputDescr.dimensions);
+  memcpy(_outputData.v, _inputData.v, count);
+}
+
+void ReshapeLayer::configure(uint8_t *inputData, const TensorDescriptor &inputDescr,
+                             uint8_t *outputData, const TensorDescriptor &outputDescr)
+{
+  _inputData.u8 = inputData;
+  _inputDescr = inputDescr;
+  _outputData.u8 = outputData;
+  _outputDescr = outputDescr;
+}
+
+void ReshapeLayer::run() { reshapeGeneric(); }
+
+} // namespace kernel
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/cpu/kernel/ReshapeLayer.h b/runtime/neurun/backend/cpu/kernel/ReshapeLayer.h
new file mode 100644
index 000000000..25dd851b2
--- /dev/null
+++ b/runtime/neurun/backend/cpu/kernel/ReshapeLayer.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_CPU_KERNEL_RESHAPELAYER_H__
+#define __NEURUN_BACKEND_CPU_KERNEL_RESHAPELAYER_H__
+
+#include <exec/IFunction.h>
+
+#include "OperationUtils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace kernel
+{
+
+class ReshapeLayer : public ::neurun::exec::IFunction
+{
+public:
+  ReshapeLayer();
+
+public:
+  void reshapeGeneric();
+
+  void configure(uint8_t *inputData, const TensorDescriptor &inputDescr, uint8_t *outputData,
+                 const TensorDescriptor &outputDescr);
+
+  void run();
+  void runSync()
+  {
+    // this abstract method is used just for profiling and called for
+    // backend::acl_common::AclFunction
+    run();
+  }
+
+private:
+  DataPtr _inputData;
+  DataPtr _outputData;
+
+  TensorDescriptor _inputDescr;
+  TensorDescriptor _outputDescr;
+};
+
+} // namespace kernel
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_CPU_KERNEL_RESHAPELAYER_H__
diff --git a/runtime/neurun/backend/cpu/kernel/SoftMaxLayer.cc b/runtime/neurun/backend/cpu/kernel/SoftMaxLayer.cc
new file mode 100644
index 000000000..58ba109b4
--- /dev/null
+++ b/runtime/neurun/backend/cpu/kernel/SoftMaxLayer.cc
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "SoftMaxLayer.h"
+
+#include <cker/operation/SoftMax.h>
+
+#include "OperationUtils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace kernel
+{
+
+SoftMaxLayer::SoftMaxLayer()
+    : _inputData(), _outputData(), _beta(0.0), _inputDescr(), _outputDescr(),
+      _inputType(OperandType::FLOAT32)
+{
+  // DO NOTHING
+}
+
+// Performs softmax along the input of size (input_size * batch_size).
+void Softmax(const float *in, const int input_size, const int batch_size, const float beta,
+             float *out)
+{
+  assert(input_size > 0);
+
+  // For each batch
+  for (int b = 0; b < batch_size; b++)
+  {
+    // Find the max coeff.
+    float max_coeff = in[0];
+    for (int i = 1; i < input_size; i++)
+    {
+      if (in[i] > max_coeff)
+        max_coeff = in[i];
+    }
+
+    // Compute the normalized sum of exps.
+    float exp_sum = 0.0;
+    for (int i = 0; i < input_size; i++)
+    {
+      out[i] = std::exp((in[i] - max_coeff) * beta);
+      exp_sum += out[i];
+    }
+
+    // Divide by the sum of exps.
+    float reciprocal_sum_exp = 1.f / exp_sum;
+    for (int i = 0; i < input_size; i++)
+    {
+      out[i] *= reciprocal_sum_exp;
+    }
+
+    // Advance in and out pointers for the next batch.
+    in += input_size;
+    out += input_size;
+  }
+}
+
+void SoftMaxLayer::softmaxFloat32()
+{
+  TensorDescriptor descrIn4D;
+
+  if (getNumberOfDimensions(_inputDescr) == 2)
+  {
+    uint32_t batch_size = getSizeOfDimension(_inputDescr, 0);
+    if (batch_size == 0)
+      throw std::runtime_error("batch_size should not be 0");
+
+    uint32_t input_size = getNumberOfElements(_inputDescr) / batch_size;
+    Softmax(_inputData.f, input_size, batch_size, _beta, _outputData.f);
+  }
+  else if (getNumberOfDimensions(_inputDescr) == 4)
+  {
+    nnfw::cker::SoftmaxParams op_params;
+    op_params.beta = _beta;
+    nnfw::cker::Softmax(op_params, convertTensorDescriptorToCkerShape(_inputDescr), _inputData.f,
+                        convertTensorDescriptorToCkerShape(_outputDescr), _outputData.f);
+  }
+  else
+  {
+    throw std::runtime_error{"only 2D and 4D tensors supported"};
+  }
+}
+
+void SoftMaxLayer::softmaxQuant8()
+{
+  TensorDescriptor descrIn4D = _inputDescr;
+
+  if (getNumberOfDimensions(_inputDescr) == 2)
+  {
+    uint32_t batch_size = getSizeOfDimension(_inputDescr, 0);
+    if (batch_size == 0)
+      throw std::runtime_error("batch_size should not be 0");
+
+    uint32_t input_size = getNumberOfElements(_inputDescr) / batch_size;
+    descrIn4D.dimensions = {batch_size, 1, 1, input_size};
+  }
+  else if (getNumberOfDimensions(_inputDescr) == 4)
+  {
+    descrIn4D = _inputDescr;
+  }
+  else
+  {
+    throw std::runtime_error{"only 2D and 4D tensors supported"};
+  }
+  if (_outputDescr.offset != 0 || _outputDescr.scale != 1.f / 256)
+  {
+    throw std::runtime_error{"incorrect scale / offset for output"};
+  }
+  static const int32_t kScaledDiffIntegerBits = 5;
+  const double input_beta_real_multiplier = std::min(
+      1.0 * _beta * _inputDescr.scale * (1 << (31 - kScaledDiffIntegerBits)), (1ll << 31) - 1.0);
+  int32_t input_multiplier = 0;
+  int32_t input_left_shift = 0;
+  QuantizeMultiplierGreaterThanOne(input_beta_real_multiplier, &input_multiplier,
+                                   &input_left_shift);
+  float diff_min = -1.0f * CalculateInputRadius(kScaledDiffIntegerBits, input_left_shift);
+
+  nnfw::cker::SoftmaxParams op_params;
+  op_params.input_multiplier = input_multiplier;
+  op_params.input_left_shift = input_left_shift;
+  op_params.diff_min = diff_min;
+  nnfw::cker::Softmax(op_params, convertTensorDescriptorToCkerShape(descrIn4D), _inputData.u8,
+                      convertTensorDescriptorToCkerShape(descrIn4D), _outputData.u8);
+}
+
+void SoftMaxLayer::configure(uint8_t *inputData, const TensorDescriptor &inputDescr,
+                             const float beta, uint8_t *outputData,
+                             const TensorDescriptor &outputDescr)
+{
+  _inputData.u8 = inputData;
+  _inputDescr = inputDescr;
+  _inputType = inputDescr.type;
+  _outputData.u8 = outputData;
+  _outputDescr = outputDescr;
+  _beta = beta;
+}
+
+void SoftMaxLayer::run()
+{
+  if (_inputType == OperandType::FLOAT32)
+  {
+    softmaxFloat32();
+  }
+  else if (_inputType == OperandType::QUANT8_ASYMM)
+  {
+    softmaxQuant8();
+  }
+}
+
+} // namespace kernel
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/cpu/kernel/SoftMaxLayer.h b/runtime/neurun/backend/cpu/kernel/SoftMaxLayer.h
new file mode 100644
index 000000000..4723afb72
--- /dev/null
+++ b/runtime/neurun/backend/cpu/kernel/SoftMaxLayer.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_CPU_KERNEL_SOFTMAXLAYER_H__
+#define __NEURUN_BACKEND_CPU_KERNEL_SOFTMAXLAYER_H__
+
+#include <exec/IFunction.h>
+
+#include "OperationUtils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace kernel
+{
+
+class SoftMaxLayer : public ::neurun::exec::IFunction
+{
+public:
+  SoftMaxLayer();
+
+public:
+  void softmaxFloat32();
+
+  void softmaxQuant8();
+
+  void configure(uint8_t *inputData, const TensorDescriptor &inputDescr, const float beta,
+                 uint8_t *outputData, const TensorDescriptor &outputDescr);
+
+  void run();
+  void runSync()
+  {
+    // this abstract method is used just for profiling and called for
+    // backend::acl_common::AclFunction
+    run();
+  }
+
+private:
+  DataPtr _inputData;
+  DataPtr _outputData;
+
+  float _beta;
+
+  TensorDescriptor _inputDescr;
+  TensorDescriptor _outputDescr;
+
+  OperandType _inputType;
+};
+
+} // namespace kernel
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_CPU_KERNEL_SOFTMAXLAYER_H__
diff --git a/runtime/neurun/backend/cpu/kernel/SubLayer.cc b/runtime/neurun/backend/cpu/kernel/SubLayer.cc
new file mode 100644
index 000000000..c6f7188e0
--- /dev/null
+++ b/runtime/neurun/backend/cpu/kernel/SubLayer.cc
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "SubLayer.h"
+
+#include <cker/operation/BinaryArithmeticOps.h>
+
+#include "OperationUtils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace kernel
+{
+
+void SubLayer::subFloat32()
+{
+  float output_activation_min, output_activation_max;
+  CalculateActivationRangeFloat(_activation, &output_activation_min, &output_activation_max);
+  nnfw::cker::BinaryArithmeticOpParam op_params;
+  op_params.float_activation_max = output_activation_max;
+  op_params.float_activation_min = output_activation_min;
+  const std::function<float(const float &, const float &)> fn = [](const float &a, const float &b) {
+    return a - b;
+  };
+
+  if (!HaveSameShapes(&_lhsDescr, &_rhsDescr))
+  {
+    nnfw::cker::BroadcastBinaryArithmeticOpSlow(
+        op_params, convertToExtendedCkerShape(_lhsDescr), _lhsData.f,
+        convertToExtendedCkerShape(_rhsDescr), _rhsData.f, convertToExtendedCkerShape(_outputDescr),
+        _outputData.f, fn);
+    return;
+  }
+
+  nnfw::cker::BinaryArithmeticOp(op_params, convertTensorDescriptorToCkerShape(_lhsDescr),
+                                 _lhsData.f, convertTensorDescriptorToCkerShape(_rhsDescr),
+                                 _rhsData.f, convertTensorDescriptorToCkerShape(_outputDescr),
+                                 _outputData.f, fn);
+}
+
+void SubLayer::subQuant8()
+{
+  int32_t output_activation_min, output_activation_max;
+  CalculateActivationRangeUint8(_activation, _outputDescr, &output_activation_min,
+                                &output_activation_max);
+  // nnfw::cker::SubParam op_params;
+  // op_params.quantized_activation_max = output_activation_max;
+  // op_params.quantized_activation_min = output_activation_min;
+
+  // cker quant8 sub is not implemented yet
+  throw std::runtime_error{"NYI"};
+}
+
+void SubLayer::configure(uint8_t *lhsData, const TensorDescriptor &lhsDescr, uint8_t *rhsData,
+                         const TensorDescriptor &rhsDescr, const ir::Activation activation,
+                         uint8_t *outputData, const TensorDescriptor &outputDescr)
+{
+  _lhsData.u8 = lhsData;
+  _lhsDescr = lhsDescr;
+  _rhsData.u8 = rhsData;
+  _rhsDescr = rhsDescr;
+  _inputType = lhsDescr.type;
+  _activation = activation;
+  _outputData.u8 = outputData;
+  _outputDescr = outputDescr;
+}
+
+void SubLayer::run()
+{
+  if (_inputType == OperandType::FLOAT32)
+  {
+    subFloat32();
+  }
+  else if (_inputType == OperandType::QUANT8_ASYMM)
+  {
+    subQuant8();
+  }
+}
+
+} // namespace kernel
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/cpu/kernel/SubLayer.h b/runtime/neurun/backend/cpu/kernel/SubLayer.h
new file mode 100644
index 000000000..c9abdb48c
--- /dev/null
+++ b/runtime/neurun/backend/cpu/kernel/SubLayer.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_CPU_KERNEL_SUBLAYER_H__
+#define __NEURUN_BACKEND_CPU_KERNEL_SUBLAYER_H__
+
+#include <exec/IFunction.h>
+
+#include "OperationUtils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace kernel
+{
+
+class SubLayer : public ::neurun::exec::IFunction
+{
+public:
+  SubLayer() : _lhsData(), _rhsData(), _outputData(), _lhsDescr(), _rhsDescr(), _outputDescr()
+  {
+    // DO NOTHING
+  }
+
+public:
+  void subFloat32();
+
+  void subQuant8();
+
+  void configure(uint8_t *lhsData, const TensorDescriptor &lhsDescr, uint8_t *rhsData,
+                 const TensorDescriptor &rhsDescr, const ir::Activation activation,
+                 uint8_t *outputData, const TensorDescriptor &outputDescr);
+
+  void run();
+  void runSync()
+  {
+    // this abstract method is used just for profiling and called for
+    // backend::acl_common::AclFunction
+    run();
+  }
+
+private:
+  DataPtr _lhsData;
+  DataPtr _rhsData;
+  DataPtr _outputData;
+
+  TensorDescriptor _lhsDescr;
+  TensorDescriptor _rhsDescr;
+  TensorDescriptor _outputDescr;
+
+  ir::Activation _activation{ir::Activation::NONE};
+
+  OperandType _inputType{OperandType::FLOAT32};
+};
+
+} // namespace kernel
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_CPU_KERNEL_SUBLAYER_H__
diff --git a/runtime/neurun/backend/cpu/operand/Tensor.cc b/runtime/neurun/backend/cpu/operand/Tensor.cc
new file mode 100644
index 000000000..21d4a9dce
--- /dev/null
+++ b/runtime/neurun/backend/cpu/operand/Tensor.cc
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "Tensor.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace operand
+{
+
+size_t Tensor::calcOffset(const neurun::util::Coordinates &coords) const
+{
+  size_t rank = num_dimensions();
+  size_t offset = 0;
+  for (size_t i = 0; i < rank; ++i)
+  {
+    offset = offset * dimension(i) + coords[i];
+  }
+  offset *= sizeOfDataType(data_type());
+  return offset;
+}
+
+void Tensor::access(const std::function<void(ITensor &)> &fn) { fn(*this); }
+
+} // namespace operand
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/cpu/operand/Tensor.h b/runtime/neurun/backend/cpu/operand/Tensor.h
new file mode 100644
index 000000000..dec680873
--- /dev/null
+++ b/runtime/neurun/backend/cpu/operand/Tensor.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_CPU_OPERAND_TENSOR_H__
+#define __NEURUN_BACKEND_CPU_OPERAND_TENSOR_H__
+
+#include <backend/operand/ITensor.h>
+#include "ir/OperandInfo.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu
+{
+namespace operand
+{
+
+class Tensor : public ::neurun::backend::operand::ITensor
+{
+public:
+  Tensor() = delete;
+
+public:
+  Tensor(const ir::OperandInfo &info) : _info(info)
+  {
+    // DO NOTHING
+  }
+
+public:
+  void setBuffer(uint8_t *buffer) { _buffer = buffer; }
+  ir::DataType data_type() const { return _info.typeInfo().type(); }
+
+public:
+  uint8_t *buffer() const override { return _buffer; }
+  /**
+   * @brief Get dimension by index
+   *
+   * @param index Index to get diemension
+   * @return size_t Dimension at index
+   * @note N : dimension(0)
+   *       H : dimension(1)
+   *       W : dimension(2)
+   *       C : dimension(3)
+   */
+  size_t dimension(size_t index) const override { return _info.shape().dim(index); }
+  size_t num_dimensions() const override { return _info.shape().rank(); }
+  size_t total_size() const override { return _info.total_size(); }
+  size_t calcOffset(const neurun::util::Coordinates &coords) const override;
+  ir::Layout layout() const override { return ir::Layout::NHWC; }
+  bool has_padding() const override { return false; }
+  void access(const std::function<void(ITensor &tensor)> &fn) final;
+
+private:
+  ir::OperandInfo _info;
+  uint8_t *_buffer = nullptr;
+};
+
+} // namespace operand
+} // namespace cpu
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_CPU_OPERAND_TENSOR_H__
diff --git a/runtime/neurun/backend/cpu_common/CMakeLists.txt b/runtime/neurun/backend/cpu_common/CMakeLists.txt
new file mode 100644
index 000000000..5b6161ba7
--- /dev/null
+++ b/runtime/neurun/backend/cpu_common/CMakeLists.txt
@@ -0,0 +1,28 @@
+file(GLOB SOURCES "*.cc")
+file(GLOB_RECURSE TESTS "*.test.cc")
+list(REMOVE_ITEM SOURCES ${TESTS})
+
+add_library(${LIB_NEURUN_BACKEND_CPU_COMMON} STATIC ${SOURCES})
+
+target_include_directories(${LIB_NEURUN_BACKEND_CPU_COMMON} PUBLIC ${NEURUN_INCLUDE_DIR})
+target_include_directories(${LIB_NEURUN_BACKEND_CPU_COMMON} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR})
+target_link_libraries(${LIB_NEURUN_BACKEND_CPU_COMMON} PUBLIC nnfw_lib_cpp14)
+target_link_libraries(${LIB_NEURUN_BACKEND_CPU_COMMON} PRIVATE nnfw_lib_misc)
+target_link_libraries(${LIB_NEURUN_BACKEND_CPU_COMMON} PRIVATE neurun_core)
+target_link_libraries(${LIB_NEURUN_BACKEND_CPU_COMMON} PRIVATE nnfw_common)
+target_link_libraries(${LIB_NEURUN_BACKEND_CPU_COMMON} PRIVATE nnfw_coverage)
+
+set_target_properties(${LIB_NEURUN_BACKEND_CPU_COMMON} PROPERTIES POSITION_INDEPENDENT_CODE ON)
+set_target_properties(${LIB_NEURUN_BACKEND_CPU_COMMON} PROPERTIES OUTPUT_NAME backend_cpu_common)
+
+# Unit Tests
+set(TEST_NEURUN_BACKEND_CPU_COMMON test_neurun_backend_cpu_common)
+
+add_executable(${TEST_NEURUN_BACKEND_CPU_COMMON} ${TESTS})
+
+target_link_libraries(${TEST_NEURUN_BACKEND_CPU_COMMON} ${LIB_NEURUN_BACKEND_CPU_COMMON})
+target_link_libraries(${TEST_NEURUN_BACKEND_CPU_COMMON} gtest gtest_main dl ${LIB_PTHREAD})
+target_include_directories(${TEST_NEURUN_BACKEND_CPU_COMMON} PRIVATE ${NEURUN_INCLUDE_DIR})
+
+add_test(${TEST_NEURUN_BACKEND_CPU_COMMON} ${TEST_NEURUN_BACKEND_CPU_COMMON})
+install(TARGETS ${TEST_NEURUN_BACKEND_CPU_COMMON} DESTINATION unittest)
diff --git a/runtime/neurun/backend/cpu_common/MemoryPlanner.cc b/runtime/neurun/backend/cpu_common/MemoryPlanner.cc
new file mode 100644
index 000000000..19961362e
--- /dev/null
+++ b/runtime/neurun/backend/cpu_common/MemoryPlanner.cc
@@ -0,0 +1,220 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "MemoryPlanner.h"
+#include "util/logging.h"
+#include <cassert>
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu_common
+{
+
+Allocator::Allocator(uint32_t capacity)
+{
+  _base = nnfw::cpp14::make_unique<uint8_t[]>(capacity);
+
+  VERBOSE(ALLOC) << "allocation capacity: " << capacity << std::endl;
+  VERBOSE(ALLOC) << "base pointer: " << static_cast<void *>(_base.get()) << std::endl;
+}
+
+void BumpPlanner::claim(const ir::OperandIndex &ind, size_t size)
+{
+  assert(size != 0);
+
+  Block blk{_capacity, size};
+  _mem_plans[ind] = blk;
+  _capacity += size;
+
+  VERBOSE(BP_PLANNER) << "CLAIM(#" << ind.value() << "): " << blk.offset << ", " << blk.size
+                      << std::endl;
+}
+
+void BumpPlanner::release(const ir::OperandIndex &ind)
+{
+  VERBOSE(BP_PLANNER) << "RELEASE(#" << ind.value() << "): "
+                      << "NOTHING does" << std::endl;
+}
+
+// There are some assumptions for claiming memory(== making a reservation for memory).
+// 1. About _claim_table(std::map).
+//   - The table's data structure is std::map so that it always sorts
+//     value(OperandIndex) by key(base_offset).
+//   - This claim() inserts key/value into _claim_table and the release() removes the key/value from
+//     _claim_table.
+//   - _claim_table shows the memory status at a certain point in time. Therefore,
+//     - If _claim_table has an offset and a certain size at a certain point in time,
+//       it means the place at the offset has been already claimed(== can't claim now. need to find
+//       someplace new).
+//     - If _claim_table doesn't have any element for an offset and a certain size at a certain
+//       point in time, it means the place at the offset can be claimed.
+// 2. In the loop for _claim_table, we can assume the current claim_base_offset value is bigger than
+//    the previous claim_base_offset.
+void FirstFitPlanner::claim(const ir::OperandIndex &ind, size_t size)
+{
+  assert(size != 0);
+
+  // Find the right position for claiming
+  uint32_t next_offset = 0;
+  for (auto &mem_claim : _claim_table)
+  {
+    auto claimed_base_offset = mem_claim.first;
+    auto claimed_size = _mem_plans[mem_claim.second].size;
+    if (next_offset + size <= claimed_base_offset)
+    {
+      break;
+    }
+    else
+    {
+      next_offset = claimed_base_offset + claimed_size;
+    }
+  }
+
+  // Now next_offset is set to the proper offset
+  _claim_table[next_offset] = ind;
+  _mem_plans[ind] = {next_offset, size};
+
+  VERBOSE(FF_PLANNER) << "claim(#" << ind.value() << "): [+" << next_offset << ", " << size << "sz]"
+                      << std::endl;
+
+  if (_capacity < next_offset + size)
+  {
+    _capacity = next_offset + size;
+  }
+}
+
+void FirstFitPlanner::release(const ir::OperandIndex &ind)
+{
+  for (auto it = _claim_table.cbegin(); it != _claim_table.cend(); ++it)
+  {
+    if (it->second == ind)
+    {
+      uint32_t offset = it->first;
+      uint32_t index = ind.value();
+      uint32_t size = _mem_plans[ind].size;
+
+      _claim_table.erase(it);
+
+      VERBOSE(FF_PLANNER) << "release(#" << index << "): [+" << offset << ", " << size << "sz]"
+                          << std::endl;
+      return;
+    }
+  }
+  assert(!"Cannot release for given index. It has been not claimed or released already.");
+}
+
+WICPlanner::WICPlanner()
+    : _initialized(false), _capacity(0), _mem_plans(), _live_operands(), _interference_graph(),
+      _map_size_to_operands(), _claim_table()
+{
+  // DO NOTHING
+}
+
+void WICPlanner::claim(const ir::OperandIndex &ind, size_t size)
+{
+  assert(size != 0);
+
+  _map_size_to_operands.insert({size, ind});
+  for (auto &live_operand : _live_operands)
+  {
+    _interference_graph[live_operand].insert(ind);
+    _interference_graph[ind].insert(live_operand);
+  }
+  _live_operands.insert(ind);
+
+  VERBOSE(WIC_PLANNER) << "claim(#" << ind.value() << "): [" << size << "sz]" << std::endl;
+}
+
+void WICPlanner::release(const ir::OperandIndex &ind)
+{
+  _live_operands.erase(ind);
+  VERBOSE(WIC_PLANNER) << "release(#" << ind.value() << ")" << std::endl;
+}
+
+/*
+ * Build memory plans using liveness and size of operands
+ * 1. Build inference graph at claim
+ *   - Two operands interfere if they have overlapped live range
+ * 2. Sort operands descending order of size
+ *   - Use std::multimap to sort operands
+ * 3. Allocate memory block for sorted operands
+ *   - Find free memory block which does not overlap with interfered operands
+ */
+void WICPlanner::buildMemoryPlans()
+{
+  for (auto &size_to_operand : _map_size_to_operands)
+  {
+    uint32_t size = size_to_operand.first;
+    ir::OperandIndex ind = size_to_operand.second;
+    VERBOSE(WIC_PLANNER) << "build_plan(#" << ind.value() << "): [" << size << "sz]" << std::endl;
+
+    // Find firstfit which does not interfere with live operands
+    uint32_t next_offset = 0;
+    if (_interference_graph.find(ind) != _interference_graph.end())
+    {
+      std::unordered_set<ir::OperandIndex> &interferences = _interference_graph.find(ind)->second;
+      for (auto &mem_claim : _claim_table)
+      {
+        if (interferences.find(mem_claim.second) != interferences.end())
+        {
+          auto claimed_base_offset = mem_claim.first;
+          auto claimed_size = _mem_plans[mem_claim.second].size;
+          VERBOSE(WIC_PLANNER) << "interfere (#" << mem_claim.second.value() << "): [+"
+                               << claimed_base_offset << ", " << claimed_size << "sz]" << std::endl;
+          if (next_offset + size <= claimed_base_offset)
+          {
+            break;
+          }
+          else if (next_offset < claimed_base_offset + claimed_size)
+          {
+            next_offset = claimed_base_offset + claimed_size;
+          }
+        }
+      }
+    }
+    else
+    {
+      VERBOSE(WIC_PLANNER) << "No interference" << std::endl;
+    }
+
+    _claim_table.insert({next_offset, ind});
+    _mem_plans[ind] = {next_offset, size};
+    VERBOSE(WIC_PLANNER) << "alloc(#" << ind.value() << "): [+" << next_offset << ", " << size
+                         << "sz]" << std::endl;
+
+    if (_capacity < next_offset + size)
+    {
+      _capacity = next_offset + size;
+    }
+  }
+  _initialized = true;
+  _interference_graph.clear();
+  _map_size_to_operands.clear();
+  _claim_table.clear();
+}
+
+WICPlanner::MemoryPlans &WICPlanner::memory_plans()
+{
+  if (!_initialized)
+    buildMemoryPlans();
+  return _mem_plans;
+}
+
+} // namespace cpu_common
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/cpu_common/MemoryPlanner.h b/runtime/neurun/backend/cpu_common/MemoryPlanner.h
new file mode 100644
index 000000000..c4f5e6a9e
--- /dev/null
+++ b/runtime/neurun/backend/cpu_common/MemoryPlanner.h
@@ -0,0 +1,217 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file        MemoryPlanner.h
+ * @brief       This file contains Memory Planning related classes
+ */
+
+#ifndef __NEURUN_BACKEND_CPU_COMMON_MEMORY_PLANNER_H__
+#define __NEURUN_BACKEND_CPU_COMMON_MEMORY_PLANNER_H__
+
+#include <map>
+#include <unordered_set>
+#include <cpp14/memory.h>
+
+#include "ir/OperandIndexMap.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu_common
+{
+
+/**
+ * @brief Structure to have memory offset and size
+ */
+struct Block
+{
+  uint32_t offset;
+  size_t size;
+};
+
+/**
+ * @brief Class to allocate memory
+ */
+class Allocator
+{
+public:
+  Allocator(uint32_t capacity);
+  /**
+   * @brief Get memory base pointer
+   * @return base pointer
+   */
+  uint8_t *base() const { return _base.get(); }
+  void release() { _base.reset(); }
+
+private:
+  std::unique_ptr<uint8_t[]> _base;
+};
+
+/**
+ * @brief Interface to plan memory
+ */
+struct IMemoryPlanner
+{
+  using MemoryPlans = ir::OperandIndexMap<Block>;
+
+  /**
+   * @brief Claim memory for operand
+   * @param[in] index The operand index
+   * @param[in] size The size of the memory
+   */
+  virtual void claim(const ir::OperandIndex &, size_t) = 0;
+  /**
+   * @brief Release memory for operand
+   * @param[in] index The operand index
+   */
+  virtual void release(const ir::OperandIndex &) = 0;
+  /**
+   * @brief Get capacity for memory planning
+   * @return The value of capacity
+   */
+  virtual uint32_t capacity() = 0;
+  /**
+   * @brief Get MemoryPlans
+   * @return MemoryPlans
+   */
+  virtual MemoryPlans &memory_plans() = 0;
+
+  virtual ~IMemoryPlanner() = default;
+};
+
+/**
+ * @brief Class to plan memory by bump way
+ */
+class BumpPlanner : public IMemoryPlanner
+{
+public:
+  /**
+   * @brief Claim memory for operand by bump way
+   * @param[in] index The operand index
+   * @param[in] size The size of the memory
+   */
+  void claim(const ir::OperandIndex &, size_t) override;
+  /**
+   * @brief Release memory for operand by bump way
+   * @param[in] index The operand index
+   */
+  void release(const ir::OperandIndex &) override;
+  /**
+   * @brief Get capacity for memory planning
+   * @return The value of capacity
+   */
+  uint32_t capacity() override { return _capacity; }
+  /**
+   * @brief Get MemoryPlans
+   * @return MemoryPlans
+   */
+  MemoryPlans &memory_plans() override { return _mem_plans; }
+
+private:
+  uint32_t _capacity = 0;
+  MemoryPlans _mem_plans;
+};
+
+/**
+ * @brief Class to plan memory by firstfit way
+ */
+class FirstFitPlanner : public IMemoryPlanner
+{
+public:
+  /**
+   * @brief Claim memory for operand by firstfit way
+   * @param[in] index The operand index
+   * @param[in] size The size of the memory
+   */
+  void claim(const ir::OperandIndex &, size_t) override;
+  /**
+   * @brief Release memory for operand by firstfit way
+   * @param[in] index The operand index
+   */
+  void release(const ir::OperandIndex &) override;
+  /**
+   * @brief Get capacity for memory planning
+   * @return The value of capacity
+   */
+  uint32_t capacity() override { return _capacity; }
+  /**
+   * @brief Get MemoryPlans
+   * @return MemoryPlans
+   */
+  MemoryPlans &memory_plans() override { return _mem_plans; }
+
+private:
+  uint32_t _capacity = 0;
+  MemoryPlans _mem_plans;
+  // Use std::map because claim() assumes that _claim_table is sorted by uint32_t(base_offset)
+  std::map<uint32_t, ir::OperandIndex> _claim_table;
+};
+
+/**
+ * @brief Class to plan memory by Weighted Interval Color algorithm
+ */
+class WICPlanner : public IMemoryPlanner
+{
+public:
+  WICPlanner();
+
+  /**
+   * @brief Claim memory for operand by WIC algorithm
+   * @param[in] index The operand index
+   * @param[in] size The size of the memory
+   */
+  void claim(const ir::OperandIndex &, size_t) override;
+  /**
+   * @brief Release memory for operand by WIC algorithm
+   * @param[in] index The operand index
+   */
+  void release(const ir::OperandIndex &) override;
+  /**
+   * @brief Get capacity for memory planning
+   * @return The value of capacity
+   */
+  uint32_t capacity() override
+  {
+    if (!_initialized)
+      buildMemoryPlans();
+    return _capacity;
+  }
+  /**
+   * @brief Get MemoryPlans
+   * @return MemoryPlans
+   */
+  MemoryPlans &memory_plans() override;
+
+private:
+  void buildMemoryPlans();
+
+  bool _initialized;
+  uint32_t _capacity;
+  MemoryPlans _mem_plans;
+  std::unordered_set<ir::OperandIndex> _live_operands;
+  ir::OperandIndexMap<std::unordered_set<ir::OperandIndex>> _interference_graph;
+  // Sort operands by descending order of size
+  std::multimap<uint32_t, ir::OperandIndex, std::greater<uint32_t>> _map_size_to_operands;
+  std::multimap<uint32_t, ir::OperandIndex> _claim_table;
+};
+
+} // namespace cpu_common
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_CPU_COMMON_MEMORY_PLANNER_H__
diff --git a/runtime/neurun/backend/cpu_common/MemoryPlanner.test.cc b/runtime/neurun/backend/cpu_common/MemoryPlanner.test.cc
new file mode 100644
index 000000000..b2be7db24
--- /dev/null
+++ b/runtime/neurun/backend/cpu_common/MemoryPlanner.test.cc
@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <gtest/gtest.h>
+
+#include "MemoryPlanner.h"
+#include "ir/Index.h"
+
+TEST(Allocator, allocate_test)
+{
+  ::neurun::backend::cpu_common::Allocator allocator(1024);
+  ASSERT_NE(allocator.base(), nullptr);
+}
+
+TEST(BumpPlanner, claim_test)
+{
+  ::neurun::backend::cpu_common::BumpPlanner planner;
+
+  auto claim = [&planner](uint32_t index, size_t size, uint32_t expected_offset) {
+    neurun::ir::OperandIndex mem_idx(index);
+    planner.claim(mem_idx, size);
+    auto mem_blk = planner.memory_plans()[mem_idx];
+    ASSERT_EQ(mem_blk.offset, expected_offset);
+    ASSERT_EQ(mem_blk.size, size);
+  };
+
+  claim(0, 10, 0);
+  claim(1, 20, 10);
+  claim(2, 30, 30);
+}
+
+TEST(FirstFitPlanner, claim_release_test)
+{
+  ::neurun::backend::cpu_common::FirstFitPlanner planner;
+
+  auto claim = [&planner](uint32_t index, size_t size, uint32_t expected_offset) {
+    neurun::ir::OperandIndex mem_idx(index);
+    planner.claim(mem_idx, size);
+    auto mem_blk = planner.memory_plans()[mem_idx];
+    ASSERT_EQ(mem_blk.offset, expected_offset);
+    ASSERT_EQ(mem_blk.size, size);
+  };
+
+  auto release = [&planner](uint32_t index) {
+    neurun::ir::OperandIndex mem_idx(index);
+    planner.release(mem_idx);
+  };
+
+  // 0 CLAIM - 10
+  claim(0, 10, 0);
+
+  // 1 CLAIM - 20
+  claim(1, 20, 10);
+
+  // 2 CLAIM - 30
+  claim(2, 30, 30);
+
+  // 0 RELEASE - 10
+  release(0);
+
+  // 3 CLAIM - 20
+  claim(3, 20, 60);
+
+  // 4 CLAIM - 5
+  claim(4, 5, 0);
+
+  // 5 CLAIM - 10
+  claim(5, 10, 80);
+
+  // 6 CLAIM - 5
+  claim(6, 5, 5);
+
+  // 2 RELEASE - 30
+  release(2);
+
+  // 7 CLAIM - 35
+  claim(7, 35, 90);
+
+  // 8 CLAIM - 10
+  claim(8, 10, 30);
+
+  // 4 RELEASE - 5
+  release(4);
+
+  // 9 CLAIM - 10
+  claim(9, 10, 40);
+
+  // 10 CLAIM - 10
+  claim(10, 10, 50);
+
+  // 6 RELEASE
+  release(6);
+
+  // 1 RELEASE
+  release(1);
+
+  // 8 RELEASE
+  release(8);
+
+  // 9 RELEASE
+  release(9);
+
+  // 10 RELEASE
+  release(10);
+
+  // 3 RELEASE
+  release(3);
+
+  // 5 RELEASE
+  release(5);
+
+  // 7 RELEASE
+  release(7);
+}
+
+TEST(WICPlanner, claim_release_test)
+{
+  ::neurun::backend::cpu_common::WICPlanner planner;
+
+  auto claim = [&planner](uint32_t index, size_t size) {
+    neurun::ir::OperandIndex mem_idx(index);
+    planner.claim(mem_idx, size);
+  };
+
+  auto release = [&planner](uint32_t index) {
+    neurun::ir::OperandIndex mem_idx(index);
+    planner.release(mem_idx);
+  };
+
+  auto verify = [&planner](uint32_t index, uint32_t size, uint32_t expected_offset) {
+    neurun::ir::OperandIndex mem_idx(index);
+    auto mem_blk = planner.memory_plans()[mem_idx];
+    ASSERT_EQ(mem_blk.offset, expected_offset);
+    ASSERT_EQ(mem_blk.size, size);
+  };
+
+  auto capacity = [&planner](uint32_t expected_capacity) {
+    auto actual_capacity = planner.capacity();
+    ASSERT_EQ(actual_capacity, expected_capacity);
+  };
+
+  claim(0, 20);
+  claim(1, 5);
+  release(0);
+  claim(2, 10);
+  release(1);
+  claim(3, 10);
+  release(2);
+  claim(4, 10);
+  release(3);
+  claim(5, 20);
+  release(4);
+  claim(6, 20);
+  release(5);
+  release(7);
+
+  // VERIFY 0 - 0
+  verify(0, 20, 0);
+
+  // VERIFY 1 - 20
+  verify(1, 5, 20);
+
+  // VERIFY 2 - 0
+  verify(2, 10, 0);
+
+  // VERIFY 3 - 10
+  verify(3, 10, 10);
+
+  // VERIFY 4 - 20
+  verify(4, 10, 20);
+
+  // VERIFY 5 - 0
+  verify(5, 20, 0);
+
+  // VERIFY 6 - 20
+  verify(6, 20, 20);
+
+  // CAPACITY - 40
+  capacity(40);
+}
diff --git a/runtime/neurun/backend/cpu_common/MemoryPlannerFactory.cc b/runtime/neurun/backend/cpu_common/MemoryPlannerFactory.cc
new file mode 100644
index 000000000..9da987aa4
--- /dev/null
+++ b/runtime/neurun/backend/cpu_common/MemoryPlannerFactory.cc
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "MemoryPlannerFactory.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu_common
+{
+
+MemoryPlannerFactory &MemoryPlannerFactory::get()
+{
+  static MemoryPlannerFactory instance;
+  return instance;
+}
+
+IMemoryPlanner *MemoryPlannerFactory::create(const std::string &key)
+{
+  if (key == "FirstFit")
+  {
+    return new FirstFitPlanner;
+  }
+  else if (key == "Bump")
+  {
+    return new BumpPlanner;
+  }
+  else if (key == "WIC")
+  {
+    return new WICPlanner;
+  }
+  return new FirstFitPlanner; // Default Planner
+}
+
+} // namespace cpu_common
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/cpu_common/MemoryPlannerFactory.h b/runtime/neurun/backend/cpu_common/MemoryPlannerFactory.h
new file mode 100644
index 000000000..829600e27
--- /dev/null
+++ b/runtime/neurun/backend/cpu_common/MemoryPlannerFactory.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_CPU_COMMON_MEMORY_PLANNER_FACTORY_H__
+#define __NEURUN_BACKEND_CPU_COMMON_MEMORY_PLANNER_FACTORY_H__
+
+#include "MemoryPlanner.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace cpu_common
+{
+
+class MemoryPlannerFactory
+{
+public:
+  static MemoryPlannerFactory &get();
+
+private:
+  MemoryPlannerFactory() = default;
+
+public:
+  IMemoryPlanner *create(const std::string &key);
+};
+
+} // namespace cpu_common
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_CPU_COMMON_MEMORY_PLANNER_FACTORY_H__
diff --git a/runtime/neurun/backend/hi_perf_cpu/CMakeLists.txt b/runtime/neurun/backend/hi_perf_cpu/CMakeLists.txt
new file mode 100644
index 000000000..816edba5e
--- /dev/null
+++ b/runtime/neurun/backend/hi_perf_cpu/CMakeLists.txt
@@ -0,0 +1,44 @@
+set(LIB_NEURUN_BACKEND_HI_PERF_CPU neurun_backend_hi_perf)
+
+nnfw_find_package(NNPACK QUIET)
+
+option(BUILD_NEURUN_HI_PERF_CPU_BACKEND
+  "Build neurun HI_PERF_CPU backend"
+  ${NNPACK_FOUND} # Default value when there is no explicit user request
+)
+
+message(STATUS "Build neurun HI_PERF_CPU backend: ${BUILD_NEURUN_HI_PERF_CPU_BACKEND}")
+
+if(NOT BUILD_NEURUN_HI_PERF_CPU_BACKEND)
+  return()
+endif(NOT BUILD_NEURUN_HI_PERF_CPU_BACKEND)
+
+file(GLOB_RECURSE SOURCES "*.cc")
+file(GLOB_RECURSE TESTS "*.test.cc")
+list(REMOVE_ITEM SOURCES ${TESTS})
+
+add_library(${LIB_NEURUN_BACKEND_HI_PERF_CPU} SHARED ${SOURCES})
+
+target_link_libraries(${LIB_NEURUN_BACKEND_HI_PERF_CPU} PRIVATE nnfw_lib_misc)
+target_link_libraries(${LIB_NEURUN_BACKEND_HI_PERF_CPU} PRIVATE nnfw_lib_cpp14)
+target_link_libraries(${LIB_NEURUN_BACKEND_HI_PERF_CPU} PRIVATE neurun_core)
+target_link_libraries(${LIB_NEURUN_BACKEND_HI_PERF_CPU} PRIVATE nnfw_common)
+target_link_libraries(${LIB_NEURUN_BACKEND_HI_PERF_CPU} PRIVATE nnpack pthreadpool cpuinfo)
+target_link_libraries(${LIB_NEURUN_BACKEND_HI_PERF_CPU} PRIVATE nnfw_coverage)
+target_include_directories(${LIB_NEURUN_BACKEND_HI_PERF_CPU} PRIVATE ${NNPACK_INCLUDE_DIRS})
+
+set_target_properties(${LIB_NEURUN_BACKEND_HI_PERF_CPU} PROPERTIES OUTPUT_NAME backend_NNPACK)
+
+install(TARGETS ${LIB_NEURUN_BACKEND_HI_PERF_CPU} DESTINATION lib)
+
+# Unit Tests
+set(TEST_NEURUN_BACKEND_HI_PERF_CPU test_neurun_backend_hi_perf)
+
+add_executable(${TEST_NEURUN_BACKEND_HI_PERF_CPU} ${TESTS})
+
+target_link_libraries(${TEST_NEURUN_BACKEND_HI_PERF_CPU} ${LIB_NEURUN_BACKEND_HI_PERF_CPU})
+target_link_libraries(${TEST_NEURUN_BACKEND_HI_PERF_CPU} gtest gtest_main ${LIB_PTHREAD})
+target_link_libraries(${TEST_NEURUN_BACKEND_HI_PERF_CPU} nnpack)
+
+add_test(${TEST_NEURUN_BACKEND_HI_PERF_CPU} ${TEST_NEURUN_BACKEND_HI_PERF_CPU})
+install(TARGETS ${TEST_NEURUN_BACKEND_HI_PERF_CPU} DESTINATION unittest)
diff --git a/runtime/neurun/backend/hi_perf_cpu/HighPerformanceBackend.test.cc b/runtime/neurun/backend/hi_perf_cpu/HighPerformanceBackend.test.cc
new file mode 100644
index 000000000..625fe1c36
--- /dev/null
+++ b/runtime/neurun/backend/hi_perf_cpu/HighPerformanceBackend.test.cc
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <gtest/gtest.h>
+
+#include "nnpack.h"
+
+TEST(High_performance_backend, NNPACK_Test)
+{
+  // Check that it is possible to import
+  const enum nnp_status init_status = nnp_initialize();
+
+  // One of the allowed nnp status codes
+  ASSERT_GE(init_status, 0);
+  ASSERT_LE(init_status, 54);
+
+  // If it is possible to test, test relu
+  if (init_status == nnp_status_success)
+  {
+    float in[] = {-1, 1, -1, 1};
+    float out[4];
+    nnp_relu_output(1, 4, in, out, 0, nullptr);
+    for (int i = 0; i < 4; i++)
+    {
+      ASSERT_EQ(out[i], in[i] >= 0 ? in[i] : 0);
+    }
+  }
+  nnp_deinitialize();
+}
diff --git a/runtime/neurun/backend/hi_perf_cpu/KernelGenerator.cc b/runtime/neurun/backend/hi_perf_cpu/KernelGenerator.cc
new file mode 100644
index 000000000..a13fe12b9
--- /dev/null
+++ b/runtime/neurun/backend/hi_perf_cpu/KernelGenerator.cc
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "KernelGenerator.h"
+// to force compilation
diff --git a/runtime/neurun/backend/hi_perf_cpu/KernelGenerator.h b/runtime/neurun/backend/hi_perf_cpu/KernelGenerator.h
new file mode 100644
index 000000000..3197995e1
--- /dev/null
+++ b/runtime/neurun/backend/hi_perf_cpu/KernelGenerator.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_HI_PERF_CPU_KERNEL_GENERATOR_H__
+#define __NEURUN_BACKEND_HI_PERF_CPU_KERNEL_GENERATOR_H__
+
+#include <backend/IKernelGenerator.h>
+
+#include "ir/Operands.h"
+#include "TensorBuilder.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace hi_perf_cpu
+{
+
+class KernelGenerator : public IKernelGenerator
+{
+public:
+  KernelGenerator(const Operands &ctx, const std::shared_ptr<TensorBuilder> &tensor_builder);
+  // TODO add more ops
+
+private:
+  const Operands &_ctx;
+  std::shared_ptr<TensorBuilder> _tensor_builder;
+};
+
+} // namespace hi_perf_cpu
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_HI_PERF_CPU_KERNEL_GENERATOR_H__
diff --git a/runtime/neurun/backend/hi_perf_cpu/TensorBuilder.cc b/runtime/neurun/backend/hi_perf_cpu/TensorBuilder.cc
new file mode 100644
index 000000000..e6ebf5f0b
--- /dev/null
+++ b/runtime/neurun/backend/hi_perf_cpu/TensorBuilder.cc
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "TensorBuilder.h"
+// to force compilation
diff --git a/runtime/neurun/backend/hi_perf_cpu/TensorBuilder.h b/runtime/neurun/backend/hi_perf_cpu/TensorBuilder.h
new file mode 100644
index 000000000..af879a41e
--- /dev/null
+++ b/runtime/neurun/backend/hi_perf_cpu/TensorBuilder.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef NNFW_TENSORBUILDER_H
+#define NNFW_TENSORBUILDER_H
+
+#include <unordered_map>
+
+#include <backend/ITensorBuilder.h>
+#include "ir/OperandIndexMap.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace hi_perf_cpu
+{
+
+class TensorBuilder : public ITensorBuilder
+{
+public:
+  TensorBuilder();
+
+private:
+};
+
+} // namespace hi_perf_cpu
+} // namespace backend
+} // namespace neurun
+
+#endif // NNFW_TENSORBUILDER_H
diff --git a/runtime/neurun/backend/srcn/Backend.h b/runtime/neurun/backend/srcn/Backend.h
new file mode 100644
index 000000000..bc76a7ed2
--- /dev/null
+++ b/runtime/neurun/backend/srcn/Backend.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_SRCN_BACKEND_H__
+#define __NEURUN_BACKEND_SRCN_BACKEND_H__
+
+#include <memory>
+#include <backend/Backend.h>
+#include <ir/Operands.h>
+
+#include "Config.h"
+#include "ConstantInitializer.h"
+#include "KernelGenerator.h"
+#include "ShapeFixer.h"
+#include "TensorRegister.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+
+class Backend : public ::neurun::backend::Backend
+{
+public:
+  Backend() : _config{std::make_shared<Config>()} {}
+
+  std::shared_ptr<IConfig> config() const override { return _config; }
+
+  std::unique_ptr<BackendContext>
+  newContext(const ir::Operands &operands,
+             const std::shared_ptr<custom::IKernelBuilder> &kb) const override
+  {
+    auto tensor_builder = std::make_shared<TensorBuilder>();
+    return std::unique_ptr<BackendContext>{new BackendContext{
+        this, tensor_builder, std::make_shared<ConstantInitializer>(operands, tensor_builder),
+        std::make_shared<KernelGenerator>(operands, tensor_builder, kb),
+        std::make_shared<ShapeFixer>(operands, tensor_builder),
+        std::make_shared<TensorRegister>(operands, tensor_builder)}};
+  }
+
+private:
+  std::shared_ptr<IConfig> _config;
+};
+
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_SRCN_BACKEND_H__
diff --git a/runtime/neurun/backend/srcn/CMakeLists.txt b/runtime/neurun/backend/srcn/CMakeLists.txt
new file mode 100644
index 000000000..3b0440c8e
--- /dev/null
+++ b/runtime/neurun/backend/srcn/CMakeLists.txt
@@ -0,0 +1,21 @@
+if(NOT BUILD_SRCN_KERNEL)
+  message(STATUS "Skip building SRCN backend: SRCN kernel library is not build")
+  return()
+endif()
+
+set(LIB_NEURUN_BACKEND_SRCN neurun_backend_srcn)
+
+file(GLOB_RECURSE SOURCES "*.cc")
+
+add_library(${LIB_NEURUN_BACKEND_SRCN} SHARED ${SOURCES})
+
+target_link_libraries(${LIB_NEURUN_BACKEND_SRCN} PUBLIC nnfw_lib_cpp14)
+target_link_libraries(${LIB_NEURUN_BACKEND_SRCN} PRIVATE nnfw_lib_srcn)
+target_link_libraries(${LIB_NEURUN_BACKEND_SRCN} PRIVATE neurun_core)
+target_link_libraries(${LIB_NEURUN_BACKEND_SRCN} PRIVATE ${LIB_NEURUN_BACKEND_CPU_COMMON})
+target_link_libraries(${LIB_NEURUN_BACKEND_SRCN} PRIVATE nnfw_common)
+target_link_libraries(${LIB_NEURUN_BACKEND_SRCN} PRIVATE nnfw_coverage)
+
+set_target_properties(${LIB_NEURUN_BACKEND_SRCN} PROPERTIES OUTPUT_NAME backend_srcn)
+
+install(TARGETS ${LIB_NEURUN_BACKEND_SRCN} DESTINATION lib)
diff --git a/runtime/neurun/backend/srcn/Config.cc b/runtime/neurun/backend/srcn/Config.cc
new file mode 100644
index 000000000..6865657e7
--- /dev/null
+++ b/runtime/neurun/backend/srcn/Config.cc
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "Config.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+
+bool Config::initialize() { return true; }
+
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/srcn/Config.h b/runtime/neurun/backend/srcn/Config.h
new file mode 100644
index 000000000..efc77fde2
--- /dev/null
+++ b/runtime/neurun/backend/srcn/Config.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_SRCN_CONFIG_H__
+#define __NEURUN_BACKEND_SRCN_CONFIG_H__
+
+#include <backend/IConfig.h>
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+
+class Config : public IConfig
+{
+public:
+  std::string id() override { return "srcn"; }
+  bool initialize() override;
+  bool SupportPermutation() override { return false; }
+  bool SupportSubTensorAlloc() override
+  {
+    // NOTE srcn allocator cannot support subtensor allocation yet
+    return false;
+  }
+};
+
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_SRCN_CONFIG_H__
diff --git a/runtime/neurun/backend/srcn/ConstantInitializer.cc b/runtime/neurun/backend/srcn/ConstantInitializer.cc
new file mode 100644
index 000000000..f03628b1f
--- /dev/null
+++ b/runtime/neurun/backend/srcn/ConstantInitializer.cc
@@ -0,0 +1,191 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ConstantInitializer.h"
+
+#include "kernel/OperationUtils.h"
+
+namespace
+{
+
+template <typename T>
+static void PermuteKernel(const neurun::ir::Operand &model_obj,
+                          neurun::backend::operand::ITensor &obj,
+                          const std::vector<int32_t> &permutation)
+{
+  const auto shape = model_obj.shape();
+  auto base = reinterpret_cast<const T *>(model_obj.data().base());
+
+  assert(shape.rank() == 4);
+  assert(permutation.size() == 4);
+  assert(permutation[0] != permutation[1] && permutation[0] != permutation[2] &&
+         permutation[0] != permutation[3]);
+  assert(permutation[1] != permutation[2] && permutation[1] != permutation[3]);
+  assert(permutation[2] != permutation[3]);
+  assert(permutation[0] < 4 && permutation[1] < 4 && permutation[2] < 4 && permutation[3] < 4);
+
+  obj.access([&](::neurun::backend::operand::ITensor &tensor) {
+    if (permutation[0] == 0 && permutation[1] == 1 && permutation[2] == 2 && permutation[3] == 3)
+    {
+      memcpy(tensor.buffer(), base, shape.num_elements() * sizeof(T));
+    }
+    else
+    {
+      const int32_t dim0 = shape.dim(0);
+      const int32_t dim1 = shape.dim(1);
+      const int32_t dim2 = shape.dim(2);
+      const int32_t dim3 = shape.dim(3);
+      for (auto i = 0; i < dim0; ++i)
+      {
+        for (auto j = 0; j < dim1; ++j)
+        {
+          for (auto k = 0; k < dim2; ++k)
+          {
+            for (auto l = 0; l < dim3; ++l)
+            {
+              Coordinates frontend_coords{i, j, k, l};
+              Coordinates coords = frontend_coords;
+              coords.set(0, frontend_coords[permutation[0]]);
+              coords.set(1, frontend_coords[permutation[1]]);
+              coords.set(2, frontend_coords[permutation[2]]);
+              coords.set(3, frontend_coords[permutation[3]]);
+              T *into = reinterpret_cast<T *>(tensor.buffer() + tensor.calcOffset(coords));
+              T value = *(base + i * dim1 * dim2 * dim3 + j * dim2 * dim3 + k * dim3 + l);
+              *into = value;
+            }
+          }
+        }
+      }
+    }
+  });
+}
+}
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+
+ConstantInitializer::ConstantInitializer(const ir::Operands &operands,
+                                         const std::shared_ptr<TensorBuilder> &tensor_builder)
+    : _operands{operands}, _tensor_builder{tensor_builder}
+{
+  // DO NOTHING
+}
+
+void ConstantInitializer::registerPermuteKernelInitializer(const ir::OperandIndex &index,
+                                                           const ir::Operand &obj,
+                                                           const std::vector<int32_t> &permutation)
+{
+  // For only CONSTANTS
+  if (!obj.isConstant())
+    return;
+
+  VERBOSE(FillOperandData) << "[SRCN] Fill data for operand " << index.value() << std::endl;
+
+  const auto type = obj.typeInfo().type();
+  using ir::DataType;
+  using namespace std::placeholders;
+
+  switch (type)
+  {
+    case DataType::FLOAT32:
+      _init_map[index] = std::bind(PermuteKernel<float>, _1, _2, permutation);
+      break;
+    case DataType::INT32:
+      _init_map[index] = std::bind(PermuteKernel<int32_t>, _1, _2, permutation);
+      break;
+    case DataType::UINT32:
+      _init_map[index] = std::bind(PermuteKernel<uint32_t>, _1, _2, permutation);
+      break;
+    case DataType::BOOL8:
+    case DataType::QUANT8_ASYMM:
+      _init_map[index] = std::bind(PermuteKernel<uint8_t>, _1, _2, permutation);
+      break;
+    case DataType::QUANT8_SYMM:
+      _init_map[index] = std::bind(PermuteKernel<int8_t>, _1, _2, permutation);
+      break;
+    default:
+      throw std::runtime_error("Not supported, yet");
+      break;
+  }
+}
+
+void ConstantInitializer::visit(const ir::operation::Conv2D &node)
+{
+  const auto &kernel_index = node.getInputs().at(ir::operation::Conv2D::KERNEL);
+  const auto &kernel_obj = _operands.at(kernel_index);
+  util::Coordinates permutation{0, 1, 2, 3};
+  const auto frontend_layout = _current_subg_layout;
+  const auto backend_layout = _tensor_builder->tensorAt(kernel_index)->layout();
+  assert(frontend_layout == ir::Layout::NHWC || frontend_layout == ir::Layout::NCHW);
+  assert(backend_layout == ir::Layout::NHWC || backend_layout == ir::Layout::NCHW);
+  const auto frontend_filter_layout =
+      frontend_layout == ir::Layout::NHWC ? kernel::FilterLayout::OHWI : kernel::FilterLayout::OIHW;
+  const auto backend_filter_layout =
+      backend_layout == ir::Layout::NHWC ? kernel::FilterLayout::HWIO : kernel::FilterLayout::OIHW;
+  registerPermuteKernelInitializer(
+      kernel_index, kernel_obj,
+      kernel::getFilterPermutation(frontend_filter_layout, backend_filter_layout));
+}
+
+void ConstantInitializer::visit(const ir::operation::DepthwiseConv2D &node)
+{
+  const auto &kernel_index = node.getInputs().at(ir::operation::DepthwiseConv2D::KERNEL);
+  const auto &kernel_obj = _operands.at(kernel_index);
+  util::Coordinates permutation{0, 1, 2, 3};
+  const auto frontend_layout = _current_subg_layout;
+  const auto backend_layout = _tensor_builder->tensorAt(kernel_index)->layout();
+  assert(frontend_layout == ir::Layout::NHWC || frontend_layout == ir::Layout::NCHW);
+  assert(backend_layout == ir::Layout::NHWC || backend_layout == ir::Layout::NCHW);
+  const auto frontend_filter_layout =
+      frontend_layout == ir::Layout::NHWC ? kernel::FilterLayout::OHWI : kernel::FilterLayout::OIHW;
+  const auto backend_filter_layout =
+      backend_layout == ir::Layout::NHWC ? kernel::FilterLayout::HWIO : kernel::FilterLayout::OIHW;
+  registerPermuteKernelInitializer(
+      kernel_index, kernel_obj,
+      kernel::getFilterPermutation(frontend_filter_layout, backend_filter_layout));
+}
+
+void ConstantInitializer::visit(const ir::operation::TransposeConv &node)
+{
+  // NOTE The srcn deconvolution layer takes a HWOI layout as kernel filter even though image layout
+  //      is NHWC.
+  //      This policy is the same with the tensorflow policy.
+  //      So for using srcn library, we need to change kernel layout to HWOI from OHWI or OIHW in
+  //      this case.
+  //      Also the srcn deconvolution layer takes a OIHW layout as kernel filter if image's layout
+  //      is NCHW
+  const auto &kernel_index = node.getInputs().at(ir::operation::TransposeConv::KERNEL);
+  const auto &kernel_obj = _operands.at(kernel_index);
+  const auto frontend_layout = _current_subg_layout;
+  const auto backend_layout = _tensor_builder->tensorAt(kernel_index)->layout();
+  assert(frontend_layout == ir::Layout::NHWC || frontend_layout == ir::Layout::NCHW);
+  assert(backend_layout == ir::Layout::NHWC || backend_layout == ir::Layout::NCHW);
+  const auto frontend_filter_layout =
+      frontend_layout == ir::Layout::NHWC ? kernel::FilterLayout::OHWI : kernel::FilterLayout::OIHW;
+  const auto backend_filter_layout =
+      backend_layout == ir::Layout::NHWC ? kernel::FilterLayout::HWOI : kernel::FilterLayout::IOHW;
+  registerPermuteKernelInitializer(
+      kernel_index, kernel_obj,
+      kernel::getFilterPermutation(frontend_filter_layout, backend_filter_layout));
+}
+
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/srcn/ConstantInitializer.h b/runtime/neurun/backend/srcn/ConstantInitializer.h
new file mode 100644
index 000000000..eadfe2ae1
--- /dev/null
+++ b/runtime/neurun/backend/srcn/ConstantInitializer.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_COMPILER_SRCN_CONSTANT_INITIALIZER_H__
+#define __NEURUN_COMPILER_SRCN_CONSTANT_INITIALIZER_H__
+
+#include <backend/IConstantInitializer.h>
+#include <ir/Operands.h>
+#include "TensorBuilder.h"
+#include <util/Coordinates.h>
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+
+class ConstantInitializer : public IConstantInitializer
+{
+public:
+  ConstantInitializer(const ir::Operands &operands,
+                      const std::shared_ptr<TensorBuilder> &tensor_builder);
+
+public:
+  void registerPermuteKernelInitializer(const ir::OperandIndex &index, const ir::Operand &obj,
+                                        const std::vector<int32_t> &permutation);
+
+public:
+  void visit(const ir::operation::Conv2D &) override;
+  void visit(const ir::operation::DepthwiseConv2D &) override;
+  void visit(const ir::operation::TransposeConv &) override;
+
+private:
+  const ir::Operands &operands() const override { return _operands; }
+  std::shared_ptr<ITensorBuilder> tensor_builder() const override { return _tensor_builder; }
+
+private:
+  const ir::Operands &_operands;
+  std::shared_ptr<TensorBuilder> _tensor_builder;
+};
+
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_COMPILER_SRCN_CONSTANT_INITIALIZER_H__
diff --git a/runtime/neurun/backend/srcn/Convert.cc b/runtime/neurun/backend/srcn/Convert.cc
new file mode 100644
index 000000000..1d80b2c7c
--- /dev/null
+++ b/runtime/neurun/backend/srcn/Convert.cc
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "Convert.h"
+
+#include <cassert>
+#include <cpp14/memory.h>
+#include <ir/DataType.h>
+#include "Swizzle.h"
+#include <vector>
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+
+ir::Shape asKernelShape(const ir::Shape &shape, kernel::FilterLayout frontend_layout,
+                        kernel::FilterLayout backend_layout)
+{
+  assert(shape.rank() == 4);
+  if (frontend_layout == backend_layout)
+  {
+    return ir::Shape{shape.dim(0), shape.dim(1), shape.dim(2), shape.dim(3)};
+  }
+
+  const auto permutation = getFilterPermutation(frontend_layout, backend_layout);
+  if (permutation.size() == 0)
+  {
+    throw std::runtime_error("Not supported FilterLayout");
+  }
+  return ir::Shape{shape.dim(permutation[0]), shape.dim(permutation[1]), shape.dim(permutation[2]),
+                   shape.dim(permutation[3])};
+}
+
+ir::Shape asTensorShape(const ir::Shape &shape, ir::Layout frontend_layout,
+                        ir::Layout backend_layout)
+{
+  const uint32_t rank = shape.rank();
+
+  ir::Shape ret(rank);
+  for (uint32_t axis = 0; axis < rank; ++axis)
+  {
+    const auto ncnn_axis = ToNCNNAxis(rank, axis, frontend_layout, backend_layout);
+    ret.dim(ncnn_axis) = shape.dim(axis);
+  }
+
+  return ret;
+}
+
+ir::OperandInfo asTensorInfo(const ir::Shape &shape, const ir::TypeInfo &typeInfo,
+                             ir::Layout frontend_layout, ir::Layout backend_layout)
+{
+  ir::OperandInfo info(asTensorShape(shape, frontend_layout, backend_layout), typeInfo);
+
+  return info;
+}
+
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/srcn/Convert.h b/runtime/neurun/backend/srcn/Convert.h
new file mode 100644
index 000000000..64be46e60
--- /dev/null
+++ b/runtime/neurun/backend/srcn/Convert.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_SRCN_CONVERT_H__
+#define __NEURUN_BACKEND_SRCN_CONVERT_H__
+
+#include "kernel/OperationUtils.h"
+#include <ir/Layout.h>
+#include <ir/Shape.h>
+#include <ir/TypeInfo.h>
+#include <ir/OperandInfo.h>
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+
+ir::Shape asKernelShape(const ir::Shape &shape, kernel::FilterLayout frontend_layout,
+                        kernel::FilterLayout backend_layout);
+
+ir::Shape asTensorShape(const ir::Shape &shape, ir::Layout frontend_layout,
+                        ir::Layout backend_layout);
+
+ir::OperandInfo asTensorInfo(const ir::Shape &shape, const ir::TypeInfo &typeInfo,
+                             ir::Layout frontend_layout, ir::Layout backend_layout);
+
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_SRCN_CONVERT_H__
diff --git a/runtime/neurun/backend/srcn/KernelGenerator.cc b/runtime/neurun/backend/srcn/KernelGenerator.cc
new file mode 100644
index 000000000..c096f9230
--- /dev/null
+++ b/runtime/neurun/backend/srcn/KernelGenerator.cc
@@ -0,0 +1,275 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "KernelGenerator.h"
+
+#include <stdexcept>
+
+#include "cpp14/memory.h"
+#include "util/Padding.h"
+#include "kernel/ConvolutionLayer.h"
+#include "kernel/DepthwiseConvolutionLayer.h"
+#include "kernel/InstanceNormLayer.h"
+#include "kernel/TransposeConvLayer.h"
+#include "kernel/AddLayer.h"
+
+#include <backend/Backend.h>
+#include <backend/IConfig.h>
+
+#include "util/logging.h"
+
+#include "util/Utils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+
+KernelGenerator::KernelGenerator(const ir::Operands &operand_ctx,
+                                 const std::shared_ptr<TensorBuilder> &tensor_builder,
+                                 const std::shared_ptr<custom::IKernelBuilder> &kb)
+    : _ctx(operand_ctx), _tensor_builder(tensor_builder), _kernel_builder(kb),
+      _current_subg_layout(ir::Layout::UNKNOWN)
+{
+  // DO NOTHING
+}
+
+void KernelGenerator::visit(const ir::OpSequence &op_seq)
+{
+  _current_subg_layout = op_seq.getLayout();
+  for (const auto &e : op_seq.operations())
+  {
+    const auto &node = *(e.node);
+    _tensor_builder->preVisit(node);
+    node.accept(*this);
+    _tensor_builder->postVisit(node);
+  }
+}
+
+void KernelGenerator::visit(const ir::operation::Conv2D &node)
+{
+  using ir::operation::Conv2D;
+
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(Conv2D::Input::INPUT)};
+  const auto ker_index{node.getInputs().at(Conv2D::Input::KERNEL)};
+  const auto bias_index{node.getInputs().at(Conv2D::Input::BIAS)};
+
+  const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature(_current_subg_layout);
+  const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature(_current_subg_layout);
+  // Kernel format is [depth_out, kernel_height, kernel_width, depth_in] if NHWC and [depth_out,
+  // depth_in, kernel_height, kernel_width] if NCHW.
+  const auto &ker_shape = _ctx.at(ker_index).shape().asFeature(_current_subg_layout);
+  const auto ker_height = ker_shape.H;
+  const auto ker_width = ker_shape.W;
+  const auto stride = node.param().stride;
+  const auto padding = neurun::util::calculatePadding(node.param().padding, ifm_shape, ofm_shape,
+                                                      stride, ker_width, ker_height);
+  const int has_padding = padding.left + padding.right + padding.top + padding.bottom;
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index);
+  auto ifm_alloc = _tensor_builder->at(ifm_index);
+  auto ker_alloc = _tensor_builder->at(ker_index);
+  auto bias_alloc = _tensor_builder->at(bias_index);
+  const auto backend_layout = ifm_alloc->layout();
+  assert(backend_layout == ofm_alloc->layout());
+
+  const auto ofm_backend_descr = ::neurun::backend::srcn::kernel::getTensorDescriptor(
+      _ctx.at(ofm_index), _current_subg_layout, backend_layout);
+  const auto ifm_backend_descr = ::neurun::backend::srcn::kernel::getTensorDescriptor(
+      _ctx.at(ifm_index), _current_subg_layout, backend_layout);
+  const auto ker_backend_descr = ::neurun::backend::srcn::kernel::getTensorDescriptor(
+      _ctx.at(ker_index), _current_subg_layout, backend_layout);
+  const auto bias_backend_descr = ::neurun::backend::srcn::kernel::getTensorDescriptor(
+      _ctx.at(bias_index), _current_subg_layout, backend_layout);
+
+  auto fn = nnfw::cpp14::make_unique<::neurun::backend::srcn::kernel::ConvolutionLayer>();
+
+  // TODO Support activation
+  fn->configure(ifm_alloc->buffer(), ifm_backend_descr, ker_alloc->buffer(), ker_backend_descr,
+                bias_alloc->buffer(), bias_backend_descr, has_padding, padding.left, padding.right,
+                padding.top, padding.bottom, stride.horizontal, stride.vertical,
+                /*activation,*/ ofm_alloc->buffer(), ofm_backend_descr, backend_layout);
+
+  _execution_builder->append(std::move(fn));
+}
+
+void KernelGenerator::visit(const ir::operation::InstanceNorm &node)
+{
+  using ir::operation::InstanceNorm;
+
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(InstanceNorm::Input::INPUT)};
+  const auto gamma_index{node.getInputs().at(InstanceNorm::Input::GAMMA)};
+  const auto beta_index{node.getInputs().at(InstanceNorm::Input::BETA)};
+
+  const auto epsilon = node.param().epsilon;
+  const auto activation = node.param().activation;
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index);
+  auto ifm_alloc = _tensor_builder->at(ifm_index);
+  auto gamma_alloc = _tensor_builder->at(gamma_index);
+  auto beta_alloc = _tensor_builder->at(beta_index);
+
+  const auto backend_layout = ofm_alloc->layout();
+
+  const auto ofm_backend_descr = ::neurun::backend::srcn::kernel::getTensorDescriptor(
+      _ctx.at(ofm_index), _current_subg_layout, backend_layout);
+  const auto ifm_backend_descr = ::neurun::backend::srcn::kernel::getTensorDescriptor(
+      _ctx.at(ifm_index), _current_subg_layout, backend_layout);
+  const auto gamma_backend_descr = ::neurun::backend::srcn::kernel::getTensorDescriptor(
+      _ctx.at(gamma_index), _current_subg_layout, backend_layout);
+  const auto beta_backend_descr = ::neurun::backend::srcn::kernel::getTensorDescriptor(
+      _ctx.at(beta_index), _current_subg_layout, backend_layout);
+
+  auto fn = nnfw::cpp14::make_unique<::neurun::backend::srcn::kernel::InstanceNormLayer>();
+
+  fn->configure(ifm_alloc->buffer(), ifm_backend_descr, gamma_alloc->buffer(), gamma_backend_descr,
+                beta_alloc->buffer(), beta_backend_descr, ofm_alloc->buffer(), ofm_backend_descr,
+                epsilon, activation, backend_layout);
+
+  _execution_builder->append(std::move(fn));
+}
+
+void KernelGenerator::visit(const ir::operation::DepthwiseConv2D &node)
+{
+  using ir::operation::DepthwiseConv2D;
+
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(DepthwiseConv2D::Input::INPUT)};
+  const auto ker_index{node.getInputs().at(DepthwiseConv2D::Input::KERNEL)};
+  const auto bias_index{node.getInputs().at(DepthwiseConv2D::Input::BIAS)};
+
+  const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature(_current_subg_layout);
+  const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature(_current_subg_layout);
+  // Kernel format is [depth_out, kernel_height, kernel_width, depth_in] if NHWC and [depth_out,
+  // depth_in, kernel_height, kernel_width] if NCHW.
+  const auto &ker_shape = _ctx.at(ker_index).shape().asFeature(_current_subg_layout);
+  const auto ker_height = ker_shape.H;
+  const auto ker_width = ker_shape.W;
+  const auto stride = node.param().stride;
+  const auto padding = neurun::util::calculatePadding(node.param().padding, ifm_shape, ofm_shape,
+                                                      stride, ker_width, ker_height);
+  const int padding_type = padding.left + padding.right + padding.top + padding.bottom;
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index);
+  auto ifm_alloc = _tensor_builder->at(ifm_index);
+  auto ker_alloc = _tensor_builder->at(ker_index);
+  auto bias_alloc = _tensor_builder->at(bias_index);
+  const auto backend_layout = ifm_alloc->layout();
+  assert(backend_layout == ofm_alloc->layout());
+
+  const auto ofm_backend_descr = ::neurun::backend::srcn::kernel::getTensorDescriptor(
+      _ctx.at(ofm_index), _current_subg_layout, backend_layout);
+  const auto ifm_backend_descr = ::neurun::backend::srcn::kernel::getTensorDescriptor(
+      _ctx.at(ifm_index), _current_subg_layout, backend_layout);
+  const auto ker_backend_descr = ::neurun::backend::srcn::kernel::getTensorDescriptor(
+      _ctx.at(ker_index), _current_subg_layout, backend_layout);
+  const auto bias_backend_descr = ::neurun::backend::srcn::kernel::getTensorDescriptor(
+      _ctx.at(bias_index), _current_subg_layout, backend_layout);
+
+  auto fn = nnfw::cpp14::make_unique<::neurun::backend::srcn::kernel::DepthwiseConvolutionLayer>();
+
+  // TODO Support activation
+  fn->configure(ifm_alloc->buffer(), ifm_backend_descr, ker_alloc->buffer(), ker_backend_descr,
+                bias_alloc->buffer(), bias_backend_descr, padding_type, padding.left, padding.right,
+                padding.top, padding.bottom, stride.horizontal, stride.vertical,
+                /*activation,*/ ofm_alloc->buffer(), ofm_backend_descr, backend_layout);
+
+  _execution_builder->append(std::move(fn));
+}
+
+void KernelGenerator::visit(const ir::operation::TransposeConv &node)
+{
+  using ir::operation::TransposeConv;
+
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(TransposeConv::Input::INPUT)};
+  const auto ker_index{node.getInputs().at(TransposeConv::Input::KERNEL)};
+  const auto output_shape_index{node.getInputs().at(TransposeConv::Input::OUTPUT_SHAPE)};
+
+  const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature(_current_subg_layout);
+  const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature(_current_subg_layout);
+  // Kernel format is [depth_out, kernel_height, kernel_width, depth_in] if NHWC and [depth_out,
+  // depth_in, kernel_height, kernel_width] if NCHW.
+  const auto &ker_shape = _ctx.at(ker_index).shape().asFeature(_current_subg_layout);
+  const auto ker_height = ker_shape.H;
+  const auto ker_width = ker_shape.W;
+  const auto stride = node.param().stride;
+  const int padding_type = (node.param().padding.type == ir::PaddingType::SAME);
+  const auto padding = neurun::util::calculatePadding(node.param().padding, ofm_shape, ifm_shape,
+                                                      stride, ker_width, ker_height);
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index);
+  auto ifm_alloc = _tensor_builder->at(ifm_index);
+  auto ker_alloc = _tensor_builder->at(ker_index);
+  const auto backend_layout = ofm_alloc->layout();
+  assert(backend_layout == ifm_alloc->layout());
+
+  const auto ofm_backend_descr = ::neurun::backend::srcn::kernel::getTensorDescriptor(
+      _ctx.at(ofm_index), _current_subg_layout, backend_layout);
+  const auto ifm_backend_descr = ::neurun::backend::srcn::kernel::getTensorDescriptor(
+      _ctx.at(ifm_index), _current_subg_layout, backend_layout);
+  const auto ker_backend_descr = ::neurun::backend::srcn::kernel::getTensorDescriptor(
+      _ctx.at(ker_index), _current_subg_layout, backend_layout);
+
+  auto fn = nnfw::cpp14::make_unique<::neurun::backend::srcn::kernel::TransposeConvLayer>();
+
+  fn->configure(ifm_alloc->buffer(), ifm_backend_descr, ker_alloc->buffer(), ker_backend_descr,
+                padding_type, padding.left, padding.right, padding.top, padding.bottom,
+                stride.horizontal, stride.vertical, ofm_alloc->buffer(), ofm_backend_descr,
+                backend_layout);
+
+  _execution_builder->append(std::move(fn));
+}
+
+void KernelGenerator::visit(const ir::operation::Add &node)
+{
+  using ir::operation::Add;
+
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto lhs_index{node.getInputs().at(Add::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(Add::Input::RHS)};
+
+  const auto activation = node.param().activation;
+
+  auto ofm_alloc = _tensor_builder->at(ofm_index).get();
+  auto lhs_alloc = _tensor_builder->at(lhs_index).get();
+  auto rhs_alloc = _tensor_builder->at(rhs_index).get();
+
+  const auto backend_layout = ofm_alloc->layout();
+  assert(backend_layout == lhs_alloc->layout() && backend_layout == rhs_alloc->layout());
+
+  const auto ofm_backend_descr = ::neurun::backend::srcn::kernel::getTensorDescriptor(
+      _ctx.at(ofm_index), _current_subg_layout, backend_layout);
+  const auto lhs_backend_descr = ::neurun::backend::srcn::kernel::getTensorDescriptor(
+      _ctx.at(lhs_index), _current_subg_layout, backend_layout);
+  const auto rhs_backend_descr = ::neurun::backend::srcn::kernel::getTensorDescriptor(
+      _ctx.at(rhs_index), _current_subg_layout, backend_layout);
+
+  auto fn = nnfw::cpp14::make_unique<::neurun::backend::srcn::kernel::AddLayer>();
+
+  fn->configure(lhs_alloc->buffer(), lhs_backend_descr, rhs_alloc->buffer(), rhs_backend_descr,
+                activation, ofm_alloc->buffer(), ofm_backend_descr, backend_layout);
+
+  _execution_builder->append(std::move(fn));
+}
+
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/srcn/KernelGenerator.h b/runtime/neurun/backend/srcn/KernelGenerator.h
new file mode 100644
index 000000000..879aeaf5b
--- /dev/null
+++ b/runtime/neurun/backend/srcn/KernelGenerator.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_SRCN_KERNEL_GENERATOR_H__
+#define __NEURUN_BACKEND_SRCN_KERNEL_GENERATOR_H__
+
+#include "backend/IKernelGenerator.h"
+#include "ir/Operands.h"
+#include "operand/Tensor.h"
+#include "backend/CustomKernelBuilder.h"
+#include "TensorBuilder.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+
+class KernelGenerator : public IKernelGenerator
+{
+public:
+  KernelGenerator(const ir::Operands &ctx, const std::shared_ptr<TensorBuilder> &tensor_builder,
+                  const std::shared_ptr<custom::IKernelBuilder> &kb);
+
+  using IKernelGenerator::visit;
+
+  void visit(const ir::OpSequence &) override;
+  void visit(const ir::operation::Conv2D &) override;
+  void visit(const ir::operation::DepthwiseConv2D &) override;
+  void visit(const ir::operation::InstanceNorm &) override;
+  void visit(const ir::operation::TransposeConv &) override;
+  void visit(const ir::operation::Add &) override;
+
+private:
+  const ir::Operands &_ctx;
+  std::shared_ptr<TensorBuilder> _tensor_builder;
+  std::shared_ptr<custom::IKernelBuilder> _kernel_builder;
+  ir::Layout _current_subg_layout;
+};
+
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_SRCN_KERNEL_GENERATOR_H__
diff --git a/runtime/neurun/backend/srcn/MemoryManager.cc b/runtime/neurun/backend/srcn/MemoryManager.cc
new file mode 100644
index 000000000..aa07ab168
--- /dev/null
+++ b/runtime/neurun/backend/srcn/MemoryManager.cc
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "MemoryManager.h"
+
+#include <cassert>
+
+#include <MemoryPlannerFactory.h>
+#include "util/logging.h"
+#include "util/ConfigSource.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+
+MemoryManager::MemoryManager() : _mem_planner{createMemoryPlanner()}
+{
+  // DO NOTHING
+}
+
+MemoryManager::MemoryManager(const std::string planner_id)
+    : _mem_planner{createMemoryPlanner(planner_id)}
+{
+  // DO NOTHING
+}
+
+cpu_common::IMemoryPlanner *MemoryManager::createMemoryPlanner()
+{
+  auto planner_id = util::getConfigString(util::config::CPU_MEMORY_PLANNER);
+  return cpu_common::MemoryPlannerFactory::get().create(planner_id);
+}
+
+cpu_common::IMemoryPlanner *MemoryManager::createMemoryPlanner(const std::string planner_id)
+{
+  return cpu_common::MemoryPlannerFactory::get().create(planner_id);
+}
+
+void MemoryManager::buildTensor(const ir::OperandIndex &ind, const ir::OperandInfo &info,
+                                ir::Layout layout)
+{
+  auto tensor = std::make_shared<operand::Tensor>(info, layout);
+  _tensors[ind] = tensor;
+}
+
+void MemoryManager::claimPlan(const ir::OperandIndex &ind, uint32_t size)
+{
+  _mem_planner->claim(ind, size);
+}
+
+void MemoryManager::releasePlan(const ir::OperandIndex &ind) { _mem_planner->release(ind); }
+
+void MemoryManager::allocate(void)
+{
+  _mem_alloc = std::make_shared<cpu_common::Allocator>(_mem_planner->capacity());
+  assert(_mem_alloc->base());
+
+  for (auto &mem_plan : _mem_planner->memory_plans())
+  {
+    auto ind = mem_plan.first;
+    auto mem_blk = mem_plan.second;
+
+    uint8_t *buffer = _mem_alloc->base() + mem_blk.offset;
+    auto tensor = _tensors[ind];
+    tensor->setBuffer(buffer);
+
+    VERBOSE(CPU_MEMORYMANAGER) << "TENSOR(#" << ind.value() << "): " << static_cast<void *>(buffer)
+                               << std::endl;
+
+    // If we do not make tensor here currently, kernel generation would cause segmentation fault.
+    // See also : Comments in `allocate` method.
+  }
+}
+
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/srcn/MemoryManager.h b/runtime/neurun/backend/srcn/MemoryManager.h
new file mode 100644
index 000000000..05fa07622
--- /dev/null
+++ b/runtime/neurun/backend/srcn/MemoryManager.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_SRCN_MEMORY_MANAGER_H__
+#define __NEURUN_BACKEND_SRCN_MEMORY_MANAGER_H__
+
+#include "backend/IMemoryManager.h"
+#include <MemoryPlanner.h>
+#include "operand/Tensor.h"
+#include "ir/OperandIndexMap.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+
+class MemoryManager : public backend::IMemoryManager
+{
+public:
+  MemoryManager();
+  MemoryManager(const std::string);
+  virtual ~MemoryManager() = default;
+
+  void allocate(void) override;
+  void deallocate(void) override { _mem_alloc->release(); }
+
+  void buildTensor(const ir::OperandIndex &ind, const ir::OperandInfo &info, ir::Layout layout);
+  void claimPlan(const ir::OperandIndex &ind, uint32_t size);
+  void releasePlan(const ir::OperandIndex &ind);
+
+  ir::OperandIndexMap<std::shared_ptr<operand::Tensor>> &tensors(void) { return _tensors; }
+
+private:
+  cpu_common::IMemoryPlanner *createMemoryPlanner();
+  cpu_common::IMemoryPlanner *createMemoryPlanner(std::string);
+
+private:
+  ir::OperandIndexMap<std::shared_ptr<operand::Tensor>> _tensors;
+  ir::OperandIndexMap<cpu_common::Block> _tensor_mem_map;
+  std::shared_ptr<cpu_common::IMemoryPlanner> _mem_planner;
+  std::shared_ptr<cpu_common::Allocator> _mem_alloc;
+};
+
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_SRCN_MEMORY_MANAGER_H__
diff --git a/runtime/neurun/backend/srcn/PluginClassesAllocator.cc b/runtime/neurun/backend/srcn/PluginClassesAllocator.cc
new file mode 100644
index 000000000..9efc6aaaa
--- /dev/null
+++ b/runtime/neurun/backend/srcn/PluginClassesAllocator.cc
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <util/logging.h>
+
+#include "Backend.h"
+
+extern "C" {
+neurun::backend::Backend *neurun_backend_create()
+{
+  VERBOSE(neurun_backend_create) << "'srcn' loaded\n";
+  return new neurun::backend::srcn::Backend;
+}
+
+void neurun_backend_destroy(neurun::backend::Backend *backend)
+{
+  VERBOSE(neurun_backend_create) << "'srcn' unloaded\n";
+  delete backend;
+}
+}
diff --git a/runtime/neurun/backend/srcn/ShapeFixer.cc b/runtime/neurun/backend/srcn/ShapeFixer.cc
new file mode 100644
index 000000000..0ef190f28
--- /dev/null
+++ b/runtime/neurun/backend/srcn/ShapeFixer.cc
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ShapeFixer.h"
+
+#include <stdexcept>
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+
+ShapeFixer::ShapeFixer(const ir::Operands &operand_ctx,
+                       const std::shared_ptr<TensorBuilder> &tensor_builder)
+    : _ctx(operand_ctx), _tensor_builder(tensor_builder)
+{
+  assert(tensor_builder);
+}
+
+void ShapeFixer::visit(const ir::operation::Conv2D &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::DepthwiseConv2D &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::InstanceNorm &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::TransposeConv &) { /* DO NOTHING */}
+
+void ShapeFixer::visit(const ir::operation::Add &) { /* DO NOTHING */}
+
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/srcn/ShapeFixer.h b/runtime/neurun/backend/srcn/ShapeFixer.h
new file mode 100644
index 000000000..7da1ae731
--- /dev/null
+++ b/runtime/neurun/backend/srcn/ShapeFixer.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_SRCN_SHAPE_FIXER_H__
+#define __NEURUN_BACKEND_SRCN_SHAPE_FIXER_H__
+
+#include <backend/IShapeFixer.h>
+
+#include "ir/Operands.h"
+#include "operand/Tensor.h"
+#include "TensorBuilder.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+
+class ShapeFixer : public IShapeFixer
+{
+public:
+  ShapeFixer(const ir::Operands &ctx, const std::shared_ptr<TensorBuilder> &tensor_builder);
+
+  void visit(const ir::operation::Conv2D &) override;
+  void visit(const ir::operation::DepthwiseConv2D &) override;
+  void visit(const ir::operation::InstanceNorm &) override;
+  void visit(const ir::operation::TransposeConv &) override;
+  void visit(const ir::operation::Add &) override;
+
+private:
+  const ir::Operands &_ctx;
+  std::shared_ptr<TensorBuilder> _tensor_builder;
+};
+
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_SRCN_SHAPE_FIXER_H__
diff --git a/runtime/neurun/backend/srcn/Swizzle.h b/runtime/neurun/backend/srcn/Swizzle.h
new file mode 100644
index 000000000..d1f922367
--- /dev/null
+++ b/runtime/neurun/backend/srcn/Swizzle.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_SRCN_SWIZZLE_H__
+#define __NEURUN_BACKEND_SRCN_SWIZZLE_H__
+
+#include <cassert>
+#include <ir/Layout.h>
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+
+// Convert axis in ncnn order
+inline uint32_t ToNCNNAxis(uint32_t rank, uint32_t axis,
+                           const ir::Layout org_layout = ir::Layout::UNKNOWN,
+                           const ir::Layout ncnn_layout = ir::Layout::UNKNOWN)
+{
+  assert(rank > axis);
+
+  if (rank >= 4 && org_layout == ir::Layout::NHWC && ncnn_layout == ir::Layout::NCHW)
+  {
+    // NHWC -> NCHW
+    // DEPTH
+    if (axis == 3)
+    {
+      return 1;
+    }
+    // WIDTH
+    if (axis == 2)
+    {
+      return 3;
+    }
+    // HEIGHT
+    if (axis == 1)
+    {
+      return 2;
+    }
+  }
+
+  if (rank >= 4 && org_layout == ir::Layout::NCHW && ncnn_layout == ir::Layout::NHWC)
+  {
+    // NCHW -> NHWC
+    // WIDTH
+    if (axis == 3)
+    {
+      return 2;
+    }
+    // HEIGHT
+    if (axis == 2)
+    {
+      return 1;
+    }
+    // DEPTH
+    if (axis == 1)
+    {
+      return 3;
+    }
+  }
+
+  return axis;
+}
+
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_SRCN_SWIZZLE_H__
diff --git a/runtime/neurun/backend/srcn/TensorBuilder.cc b/runtime/neurun/backend/srcn/TensorBuilder.cc
new file mode 100644
index 000000000..5ac25c33e
--- /dev/null
+++ b/runtime/neurun/backend/srcn/TensorBuilder.cc
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "TensorBuilder.h"
+
+#include <cassert>
+#include "Convert.h"
+#include "util/logging.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+
+TensorBuilder::TensorBuilder() : _tensor_mgr{new TensorManager()}
+{
+  // DO NOTHING
+}
+
+void TensorBuilder::registerTensorInfo(const ir::OperandIndex &ind,
+                                       const ir::OperandInfo &tensor_info,
+                                       ir::Layout backend_layout, bool as_const)
+{
+  _tensor_info_map.emplace(ind, tensor_info);
+  _tensor_layout_map.emplace(ind, backend_layout);
+
+  if (as_const)
+    _constants.append(ind);
+}
+
+void TensorBuilder::registerSubTensorInfo(const ir::OperandIndex &, const compiler::SubTensorInfo &)
+{
+  // Not supported yet
+  assert(false);
+}
+
+void TensorBuilder::notifyFirstUse(const ir::OperandIndex &ind)
+{
+  assert(_tensor_info_map.find(ind) != _tensor_info_map.end());
+  const auto &tensor_info = _tensor_info_map.at(ind);
+  const auto size = tensor_info.total_size();
+  const auto &backend_layout = _tensor_layout_map.at(ind);
+  _tensor_mgr->buildTensor(ind, tensor_info, backend_layout, _constants.contains(ind));
+  _tensor_mgr->claimPlan(ind, size);
+}
+
+void TensorBuilder::notifyLastUse(const ir::OperandIndex &ind) { _tensor_mgr->releasePlan(ind); }
+
+bool TensorBuilder::isRegistered(const ir::OperandIndex &ind) const
+{
+  return _tensor_info_map.find(ind) != _tensor_info_map.end();
+}
+
+void TensorBuilder::prepare(void)
+{
+  _tensor_mgr->allocateConsts();
+  _tensor_mgr->allocateNonconsts();
+}
+
+void TensorBuilder::allocateConsts()
+{
+  // NOTE For now nothing to do. Allocation is done in prepare stage, which is not appropriate
+  //      This is because SRCN kernels require `ITensor`s to be allocated before Kernel Generation.
+}
+
+void TensorBuilder::allocateNonconsts()
+{
+  // NOTE For now nothing to do. Allocation is done in prepare stage, which is not appropriate
+  //      This is because SRCN kernels require `ITensor`s to be allocated before Kernel Generation.
+}
+
+std::shared_ptr<::neurun::backend::operand::ITensor>
+TensorBuilder::tensorAt(const ir::OperandIndex &ind)
+{
+  return _tensor_mgr->at(ind);
+}
+
+void TensorBuilder::iterate(const IterateFunction &fn) { _tensor_mgr->iterate(fn); }
+
+std::shared_ptr<operand::Tensor> TensorBuilder::at(const ir::OperandIndex &ind)
+{
+  return _tensor_mgr->at(ind);
+}
+
+std::unique_ptr<ITensorManager> TensorBuilder::releaseTensorManager(void)
+{
+  return std::move(_tensor_mgr);
+}
+
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/srcn/TensorBuilder.h b/runtime/neurun/backend/srcn/TensorBuilder.h
new file mode 100644
index 000000000..38bd6dd89
--- /dev/null
+++ b/runtime/neurun/backend/srcn/TensorBuilder.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_SRCN_TENSOR_BUILDER_H__
+#define __NEURUN_BACKEND_SRCN_TENSOR_BUILDER_H__
+
+#include <unordered_map>
+
+#include <backend/ITensorBuilder.h>
+#include "operand/Tensor.h"
+#include "ir/OperandIndexMap.h"
+#include "TensorManager.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+
+class TensorBuilder : public ITensorBuilder
+{
+public:
+  TensorBuilder();
+
+  /**
+   * @brief     Register tensor information to allocate on CPU backend
+   * @param[in] ind    Operand index
+   * @param[in] info   Operand information
+   * @param[in] layout Operand data layout
+   */
+  void registerTensorInfo(const ir::OperandIndex &ind, const ir::OperandInfo &info,
+                          ir::Layout backend_layout, bool as_const) override;
+  /**
+   * @brief     Register subtensor information to allocate on CPU backend
+   * @param[in] ind   Operand index
+   * @param[in] info  Tensor information
+   */
+  void registerSubTensorInfo(const ir::OperandIndex &ind,
+                             const compiler::SubTensorInfo &info) override;
+
+  void notifyFirstUse(const ir::OperandIndex &) override;
+  void notifyLastUse(const ir::OperandIndex &) override;
+
+  bool isRegistered(const ir::OperandIndex &) const override;
+
+  void prepare(void) override;
+  void allocateConsts() override;
+  void allocateNonconsts() override;
+  void postFunctionPrepare() override { /* DO NOTHING */}
+  void finalize() override { /* DO NOTHING */}
+
+  std::shared_ptr<::neurun::backend::operand::ITensor>
+  tensorAt(const ir::OperandIndex &ind) override;
+
+  void iterate(const IterateFunction &fn) override;
+
+  void preVisit(const ir::Operation &) override { /* DO NOTHING */}
+  void postVisit(const ir::Operation &) override { /* DO NOTHING */}
+
+  std::unique_ptr<ITensorManager> releaseTensorManager(void) override;
+
+  std::shared_ptr<operand::Tensor> at(const ir::OperandIndex &ind);
+
+private:
+  std::unique_ptr<TensorManager> _tensor_mgr;
+  ir::OperandIndexMap<ir::OperandInfo> _tensor_info_map;
+  ir::OperandIndexMap<ir::Layout> _tensor_layout_map;
+  ir::OperandIndexSequence _constants;
+};
+
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_SRCN_TENSOR_BUILDER_H__
diff --git a/runtime/neurun/backend/srcn/TensorManager.cc b/runtime/neurun/backend/srcn/TensorManager.cc
new file mode 100644
index 000000000..717f1bbbc
--- /dev/null
+++ b/runtime/neurun/backend/srcn/TensorManager.cc
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "TensorManager.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+
+TensorManager::TensorManager()
+    : _const_mgr{new MemoryManager("Bump")}, _nonconst_mgr{new MemoryManager()}
+{
+  // DO NOTHING
+}
+
+void TensorManager::allocateConsts(void) { _const_mgr->allocate(); }
+
+void TensorManager::allocateNonconsts(void) { _nonconst_mgr->allocate(); }
+
+void TensorManager::deallocateConsts(void) { _const_mgr->deallocate(); }
+
+void TensorManager::deallocateNonconsts(void) { _nonconst_mgr->deallocate(); }
+
+void TensorManager::buildTensor(const ir::OperandIndex &ind, const ir::OperandInfo &tensor_info,
+                                ir::Layout layout, bool as_const)
+{
+  assert(_ind_to_mgr.find(ind) == _ind_to_mgr.end());
+  if (as_const)
+  {
+    _const_mgr->buildTensor(ind, tensor_info, layout);
+    _ind_to_mgr.insert({ind, *_const_mgr});
+  }
+  else
+  {
+    _nonconst_mgr->buildTensor(ind, tensor_info, layout);
+    _ind_to_mgr.insert({ind, *_nonconst_mgr});
+  }
+}
+
+void TensorManager::claimPlan(const ir::OperandIndex &ind, uint32_t size)
+{
+  assert(_ind_to_mgr.find(ind) != _ind_to_mgr.end());
+  _ind_to_mgr.at(ind).claimPlan(ind, size);
+}
+
+void TensorManager::releasePlan(const ir::OperandIndex &ind)
+{
+  assert(_ind_to_mgr.find(ind) != _ind_to_mgr.end());
+  _ind_to_mgr.at(ind).releasePlan(ind);
+}
+
+std::shared_ptr<operand::Tensor> TensorManager::at(const ir::OperandIndex &ind)
+{
+  assert(_ind_to_mgr.find(ind) != _ind_to_mgr.end());
+  return _ind_to_mgr.at(ind).tensors().at(ind);
+}
+
+ir::OperandIndexMap<std::shared_ptr<operand::Tensor>> &TensorManager::constTensors(void)
+{
+  return _const_mgr->tensors();
+}
+
+ir::OperandIndexMap<std::shared_ptr<operand::Tensor>> &TensorManager::nonconstTensors(void)
+{
+  return _nonconst_mgr->tensors();
+}
+
+void TensorManager::iterate(const std::function<void(const ir::OperandIndex &)> &fn)
+{
+  for (auto it : _nonconst_mgr->tensors())
+    fn(it.first);
+
+  for (auto it : _const_mgr->tensors())
+    fn(it.first);
+}
+
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/srcn/TensorManager.h b/runtime/neurun/backend/srcn/TensorManager.h
new file mode 100644
index 000000000..d4390d80c
--- /dev/null
+++ b/runtime/neurun/backend/srcn/TensorManager.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_SRCN_TENSOR_MANAGER_H__
+#define __NEURUN_BACKEND_SRCN_TENSOR_MANAGER_H__
+
+#include "backend/ITensorManager.h"
+#include "MemoryManager.h"
+#include "ir/OperandIndexMap.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+
+class TensorManager : public backend::ITensorManager
+{
+public:
+  TensorManager();
+  virtual ~TensorManager() = default;
+
+  void allocateConsts(void) override;
+  void allocateNonconsts(void) override;
+  void deallocateConsts(void) override;
+  void deallocateNonconsts(void) override;
+
+  void buildTensor(const ir::OperandIndex &ind, const ir::OperandInfo &tensor_info,
+                   ir::Layout layout, bool as_const);
+
+  void claimPlan(const ir::OperandIndex &ind, uint32_t size);
+  void releasePlan(const ir::OperandIndex &ind);
+
+  std::shared_ptr<operand::Tensor> at(const ir::OperandIndex &ind);
+
+  ir::OperandIndexMap<std::shared_ptr<operand::Tensor>> &constTensors(void);
+  ir::OperandIndexMap<std::shared_ptr<operand::Tensor>> &nonconstTensors(void);
+
+  void iterate(const std::function<void(const ir::OperandIndex &)> &fn);
+
+private:
+  std::unique_ptr<MemoryManager> _const_mgr;
+  std::unique_ptr<MemoryManager> _nonconst_mgr;
+  ir::OperandIndexMap<MemoryManager &> _ind_to_mgr;
+};
+
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_SRCN_TENSOR_MANAGER_H__
diff --git a/runtime/neurun/backend/srcn/TensorRegister.cc b/runtime/neurun/backend/srcn/TensorRegister.cc
new file mode 100644
index 000000000..8c2f59aef
--- /dev/null
+++ b/runtime/neurun/backend/srcn/TensorRegister.cc
@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "TensorRegister.h"
+
+#include "Convert.h"
+#include "kernel/OperationUtils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+
+TensorRegister::TensorRegister(const ir::Operands &operands,
+                               const std::shared_ptr<TensorBuilder> &tensor_builder)
+    : _operands{operands}, _tensor_builder{tensor_builder}
+{
+  assert(tensor_builder != nullptr);
+}
+
+void TensorRegister::visit(const ir::operation::Conv2D &node)
+{
+  // General cases
+  defaultRegisterTensorInfo(node.getInputs().at(ir::operation::Conv2D::INPUT));
+  defaultRegisterTensorInfo(node.getInputs().at(ir::operation::Conv2D::BIAS));
+  defaultRegisterTensorInfo(node.getOutputs().at(0));
+
+  // Special case
+  const auto &kernel_index = node.getInputs().at(ir::operation::Conv2D::KERNEL);
+  const auto &kernel_obj = _operands.at(kernel_index);
+
+  const auto frontend_layout = frontendLayout();
+  assert(frontend_layout == ir::Layout::NCHW || frontend_layout == ir::Layout::NHWC);
+  const auto frontend_filter_layout =
+      frontend_layout == ir::Layout::NHWC ? kernel::FilterLayout::OHWI : kernel::FilterLayout::OIHW;
+  const auto backend_layout = backendLayout(kernel_index);
+  assert(backend_layout == ir::Layout::NCHW || backend_layout == ir::Layout::NHWC);
+  const auto backend_filter_layout =
+      backend_layout == ir::Layout::NHWC ? kernel::FilterLayout::HWIO : kernel::FilterLayout::OIHW;
+
+  ir::OperandInfo backend_info{
+      asKernelShape(kernel_obj.shape(), frontend_filter_layout, backend_filter_layout),
+      kernel_obj.info().typeInfo()};
+  _tensor_builder->registerTensorInfo(kernel_index, backend_info, backend_layout,
+                                      kernel_obj.isConstant());
+}
+
+void TensorRegister::visit(const ir::operation::DepthwiseConv2D &node)
+{
+  // General cases
+  defaultRegisterTensorInfo(node.getInputs().at(ir::operation::DepthwiseConv2D::INPUT));
+  defaultRegisterTensorInfo(node.getInputs().at(ir::operation::DepthwiseConv2D::BIAS));
+  defaultRegisterTensorInfo(node.getOutputs().at(0));
+
+  // Special case
+  const auto &kernel_index = node.getInputs().at(ir::operation::DepthwiseConv2D::KERNEL);
+  const auto &kernel_obj = _operands.at(kernel_index);
+
+  const auto frontend_layout = frontendLayout();
+  assert(frontend_layout == ir::Layout::NCHW || frontend_layout == ir::Layout::NHWC);
+  const auto frontend_filter_layout =
+      frontend_layout == ir::Layout::NHWC ? kernel::FilterLayout::OHWI : kernel::FilterLayout::OIHW;
+  const auto backend_layout = backendLayout(kernel_index);
+  assert(backend_layout == ir::Layout::NCHW || backend_layout == ir::Layout::NHWC);
+  const auto backend_filter_layout =
+      backend_layout == ir::Layout::NHWC ? kernel::FilterLayout::HWIO : kernel::FilterLayout::OIHW;
+
+  ir::OperandInfo backend_info{
+      asKernelShape(kernel_obj.shape(), frontend_filter_layout, backend_filter_layout),
+      kernel_obj.info().typeInfo()};
+  _tensor_builder->registerTensorInfo(kernel_index, backend_info, backend_layout,
+                                      kernel_obj.isConstant());
+}
+
+void TensorRegister::visit(const ir::operation::TransposeConv &node)
+{
+  // General cases
+  defaultRegisterTensorInfo(node.getInputs().at(ir::operation::TransposeConv::INPUT));
+  defaultRegisterTensorInfo(node.getOutputs().at(0));
+
+  // Special case
+  const auto &kernel_index = node.getInputs().at(ir::operation::TransposeConv::KERNEL);
+  const auto &kernel_obj = _operands.at(kernel_index);
+
+  const auto frontend_layout = frontendLayout();
+  assert(frontend_layout == ir::Layout::NCHW || frontend_layout == ir::Layout::NHWC);
+  const auto frontend_filter_layout =
+      frontend_layout == ir::Layout::NHWC ? kernel::FilterLayout::OHWI : kernel::FilterLayout::OIHW;
+  const auto backend_layout = backendLayout(kernel_index);
+  assert(backend_layout == ir::Layout::NCHW || backend_layout == ir::Layout::NHWC);
+  const auto backend_filter_layout =
+      backend_layout == ir::Layout::NHWC ? kernel::FilterLayout::HWOI : kernel::FilterLayout::IOHW;
+
+  ir::OperandInfo backend_info{
+      asKernelShape(kernel_obj.shape(), frontend_filter_layout, backend_filter_layout),
+      kernel_obj.info().typeInfo()};
+  _tensor_builder->registerTensorInfo(kernel_index, backend_info, backend_layout,
+                                      kernel_obj.isConstant());
+}
+
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/srcn/TensorRegister.h b/runtime/neurun/backend/srcn/TensorRegister.h
new file mode 100644
index 000000000..765f29567
--- /dev/null
+++ b/runtime/neurun/backend/srcn/TensorRegister.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_SRCN_TENSOR_REGISTER_H__
+#define __NEURUN_BACKEND_SRCN_TENSOR_REGISTER_H__
+
+#include <backend/ITensorRegister.h>
+#include "TensorBuilder.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+
+class TensorRegister : public ITensorRegister
+{
+public:
+  TensorRegister(const ir::Operands &operands,
+                 const std::shared_ptr<TensorBuilder> &tensor_builder);
+
+public:
+  void visit(const ir::operation::Conv2D &) override;
+  void visit(const ir::operation::DepthwiseConv2D &) override;
+  void visit(const ir::operation::TransposeConv &) override;
+
+private:
+  const ir::Operands &operands() const override { return _operands; }
+  std::shared_ptr<ITensorBuilder> tensor_builder() const override { return _tensor_builder; }
+  bool supportSubTensor() const final { return false; }
+
+private:
+  const ir::Operands &_operands;
+  const std::shared_ptr<TensorBuilder> _tensor_builder;
+};
+
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_SRCN_TENSOR_REGISTER_H__
diff --git a/runtime/neurun/backend/srcn/kernel/AddLayer.cc b/runtime/neurun/backend/srcn/kernel/AddLayer.cc
new file mode 100644
index 000000000..b53dfe89d
--- /dev/null
+++ b/runtime/neurun/backend/srcn/kernel/AddLayer.cc
@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "AddLayer.h"
+
+#include "OperationUtils.h"
+#include "ncnn/layer/binaryop.h"
+
+#include "cpp14/memory.h"
+
+namespace
+{
+std::unique_ptr<nnfw::ncnn::Mat>
+convertMatIgnoreLayout(neurun::backend::srcn::kernel::TensorDescriptor &desc, void *data)
+{
+  if (desc.dimensions.size() == 1)
+  {
+    return nnfw::cpp14::make_unique<nnfw::ncnn::Mat>(desc.dimensions[0], data);
+  }
+  else if (desc.dimensions.size() == 2)
+  {
+    return nnfw::cpp14::make_unique<nnfw::ncnn::Mat>(desc.dimensions[1], desc.dimensions[0], data);
+  }
+  else if (desc.dimensions.size() == 3)
+  {
+    return nnfw::cpp14::make_unique<nnfw::ncnn::Mat>(desc.dimensions[2], desc.dimensions[1],
+                                                     desc.dimensions[0], data);
+  }
+  else // rank == 4 and N == 1
+  {
+    return nnfw::cpp14::make_unique<nnfw::ncnn::Mat>(desc.dimensions[3], desc.dimensions[2],
+                                                     desc.dimensions[1], data);
+  }
+}
+} // namespace
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+namespace kernel
+{
+
+void AddLayer::addFloat32()
+{
+  assert(_activation == ir::Activation::NONE);
+
+  // ncnn kernel support
+  // 1. rank < 4
+  // 2. broadcasting
+  //   2-1 lhs, rhs have same rank, or
+  //   2-2 model layout and backend layout is same
+  // For safety, block all broadcasting (enable when ready)
+
+  assert(_lhsDescr.dimensions.size() < 4 ||
+         (_lhsDescr.dimensions.size() == 4 && _lhsDescr.dimensions[0] == 1));
+  assert(_rhsDescr.dimensions.size() < 4 ||
+         (_rhsDescr.dimensions.size() == 4 && _rhsDescr.dimensions[0] == 1));
+  assert((_lhsDescr.dimensions.size() == _rhsDescr.dimensions.size()));
+
+  nnfw::ncnn::BinaryOpParam param;
+  param.op_type = nnfw::ncnn::BinaryOp::Operation_ADD;
+
+  auto lhs_mat = convertMatIgnoreLayout(_lhsDescr, _lhsData.v);
+  auto rhs_mat = convertMatIgnoreLayout(_rhsDescr, _rhsData.v);
+  auto out_mat = convertMatIgnoreLayout(_outputDescr, _outputData.v);
+
+  ::nnfw::ncnn::ncnn_binary_op(param, *lhs_mat.get(), *rhs_mat.get(), *out_mat.get());
+}
+
+void AddLayer::addQuant8()
+{
+  // quant8 add is not implemented yet
+  throw std::runtime_error{"NYI"};
+}
+
+void AddLayer::configure(uint8_t *lhsData, const TensorDescriptor &lhsDescr, uint8_t *rhsData,
+                         const TensorDescriptor &rhsDescr, const ir::Activation activation,
+                         uint8_t *outputData, const TensorDescriptor &outputDescr,
+                         const ir::Layout backendLayout)
+{
+  _lhsData.u8 = lhsData;
+  _lhsDescr = lhsDescr;
+  _rhsData.u8 = rhsData;
+  _rhsDescr = rhsDescr;
+  _inputType = lhsDescr.type;
+  _activation = activation;
+  _outputData.u8 = outputData;
+  _outputDescr = outputDescr;
+  _backendLayout = backendLayout;
+}
+
+void AddLayer::run()
+{
+  if (_inputType == OperandType::FLOAT32)
+  {
+    addFloat32();
+  }
+  else if (_inputType == OperandType::QUANT8_ASYMM)
+  {
+    addQuant8();
+  }
+}
+
+} // namespace kernel
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/srcn/kernel/AddLayer.h b/runtime/neurun/backend/srcn/kernel/AddLayer.h
new file mode 100644
index 000000000..1cae171b5
--- /dev/null
+++ b/runtime/neurun/backend/srcn/kernel/AddLayer.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_SRCN_KERNEL_ADD_LAYER_H__
+#define __NEURUN_BACKEND_SRCN_KERNEL_ADD_LAYER_H__
+
+#include <exec/IFunction.h>
+
+#include "OperationUtils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+namespace kernel
+{
+
+class AddLayer : public ::neurun::exec::IFunction
+{
+public:
+  AddLayer() : _lhsData(), _rhsData(), _outputData(), _lhsDescr(), _rhsDescr(), _outputDescr()
+  {
+    // DO NOTHING
+  }
+
+public:
+  void addFloat32();
+
+  void addQuant8();
+
+  void configure(uint8_t *lhsData, const TensorDescriptor &lhsDescr, uint8_t *rhsData,
+                 const TensorDescriptor &rhsDescr, const ir::Activation activation,
+                 uint8_t *outputData, const TensorDescriptor &outputDescr,
+                 const ir::Layout backendLayout);
+
+  void run();
+  void runSync()
+  {
+    // this abstract method is used just for profiling and called for
+    // backend::acl_common::AclFunction
+    run();
+  }
+
+private:
+  DataPtr _lhsData;
+  DataPtr _rhsData;
+  DataPtr _outputData;
+
+  TensorDescriptor _lhsDescr;
+  TensorDescriptor _rhsDescr;
+  TensorDescriptor _outputDescr;
+
+  ir::Activation _activation{ir::Activation::NONE};
+
+  OperandType _inputType{OperandType::FLOAT32};
+
+  ir::Layout _backendLayout{ir::Layout::UNKNOWN};
+};
+
+} // namespace kernel
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_SRCN_KERNEL_ADD_LAYER_H__
diff --git a/runtime/neurun/backend/srcn/kernel/ConvolutionLayer.cc b/runtime/neurun/backend/srcn/kernel/ConvolutionLayer.cc
new file mode 100644
index 000000000..4e70f6319
--- /dev/null
+++ b/runtime/neurun/backend/srcn/kernel/ConvolutionLayer.cc
@@ -0,0 +1,233 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ConvolutionLayer.h"
+
+#include "OperationUtils.h"
+#include <ncnn/srcn/srcn_conv.h>
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+namespace kernel
+{
+
+ConvolutionLayer::ConvolutionLayer()
+    : _inputData(), _kernelData(), _biasData(), _outputData(), _inputDescr(), _kernelDescr(),
+      _biasDescr(), _outputDescr(), _paddingType(0), _paddingLeft(0), _paddingTop(0),
+      _paddingRight(0), _paddingBottom(0), _strideWidth(0), _strideHeight(0),
+      _inputType(OperandType::FLOAT32), _layout(nnfw::srcn::col_major), _winograd_weights(nullptr),
+      _sparse_weights(nullptr)
+{
+  // DO NOTHING
+}
+
+ConvolutionLayer::~ConvolutionLayer()
+{
+  // TODO Move managing constant _winograd_data and sparse
+  nnfw::srcn::winograd_release(_winograd_weights);
+  size_t depth_index = _layout == nnfw::srcn::col_major ? 3 : 1;
+  nnfw::srcn::sparse_release(_outputDescr.dimensions[depth_index], _sparse_weights);
+}
+
+void ConvolutionLayer::convFloat32()
+{
+  nnfw::srcn::convMat_t in_mat, out_mat, kernel_mat;
+  nnfw::srcn::convParams_t in_param;
+
+  assert(_layout == nnfw::srcn::col_major || _layout == nnfw::srcn::row_major);
+  size_t height_index = _layout == nnfw::srcn::col_major ? 1 : 2;
+  size_t width_index = _layout == nnfw::srcn::col_major ? 2 : 3;
+  size_t depth_index = _layout == nnfw::srcn::col_major ? 3 : 1;
+  size_t kernel_input_depth_index = _layout == nnfw::srcn::col_major ? 3 : 1;
+  size_t kernel_output_depth_index = 0;
+
+  const int batches = MatchingDim(_inputDescr, 0, _outputDescr, 0);
+  const int input_height = _inputDescr.dimensions[height_index];
+  const int input_width = _inputDescr.dimensions[width_index];
+  const int input_depth =
+      MatchingDim(_inputDescr, depth_index, _kernelDescr, kernel_input_depth_index);
+  in_mat.c = input_depth;
+  in_mat.w = input_width;
+  in_mat.h = input_height;
+  in_mat.n = batches;
+  in_mat.data = _inputData.f;
+
+  const int output_height = _outputDescr.dimensions[height_index];
+  const int output_width = _outputDescr.dimensions[width_index];
+  const int output_depth =
+      MatchingDim(_kernelDescr, kernel_output_depth_index, _outputDescr, depth_index);
+  out_mat.c = output_depth;
+  out_mat.w = output_width;
+  out_mat.h = output_height;
+  out_mat.n = batches;
+  out_mat.data = _outputData.f;
+
+  const int outch = _kernelDescr.dimensions[kernel_output_depth_index];
+  const int inch = _kernelDescr.dimensions[kernel_input_depth_index];
+  const int ker_height = _kernelDescr.dimensions[height_index];
+  const int ker_width = _kernelDescr.dimensions[width_index];
+  kernel_mat.c = input_depth;
+  kernel_mat.w = ker_width;
+  kernel_mat.h = ker_height;
+  kernel_mat.n = output_depth;
+  kernel_mat.data = _kernelData.f;
+
+  in_param.kernel_w = ker_width;
+  in_param.kernel_h = ker_height;
+  in_param.stride_w = _strideWidth;
+  in_param.stride_h = _strideHeight;
+  in_param.padding = _paddingType;
+  in_param.pad_w = _paddingLeft;
+  in_param.pad_h = _paddingTop;
+  in_param.dilation_w = 1;
+  in_param.dilation_h = 1;
+
+  nnfw::srcn::winogradParams_t winograd_param;
+  winograd_param.kernel_w = ker_width;
+  winograd_param.kernel_h = ker_height;
+  winograd_param.stride_w = _strideWidth;
+  winograd_param.stride_h = _strideHeight;
+  winograd_param.dilation_w = 1;
+  winograd_param.dilation_h = 1;
+  winograd_param.batch = batches;
+  winograd_param.w = ker_width;
+  winograd_param.h = ker_height;
+  winograd_param.inch = inch;
+  winograd_param.outch = outch;
+  winograd_param.num_threads = 4;
+
+  winograd_param.conv_type = _layout;
+  winograd_param.weight_data = _kernelData.f;
+
+  // Without winograd
+  if (nnfw::srcn::check_winograd(winograd_param))
+  {
+    _winograd_weights = nnfw::srcn::trans_weight2winograd(winograd_param, nullptr);
+  }
+  _sparse_weights = nnfw::srcn::trans_weight2sparse(kernel_mat);
+
+  nnfw::srcn::srcn_convolution2D(in_mat, kernel_mat, out_mat, in_param, _winograd_weights, 4,
+                                 _layout);
+
+  // Add biases
+  if (_biasData.f == nullptr)
+  {
+    return;
+  }
+  // TODO Optimize
+  uint32_t strides[4] = {
+      _outputDescr.dimensions[1] * _outputDescr.dimensions[2] * _outputDescr.dimensions[3],
+      _outputDescr.dimensions[2] * _outputDescr.dimensions[3], _outputDescr.dimensions[3], 1};
+  if (_layout == nnfw::srcn::convType_t::col_major)
+  {
+    for (uint32_t c = 0; c < _outputDescr.dimensions[3]; ++c)
+    {
+      if (_biasData.f[c] != 0)
+      {
+        for (uint32_t b = 0; b < _outputDescr.dimensions[0]; ++b)
+        {
+          for (uint32_t h = 0; h < _outputDescr.dimensions[1]; ++h)
+          {
+            for (uint32_t w = 0; w < _outputDescr.dimensions[2]; ++w)
+            {
+              _outputData.f[b * strides[0] + h * strides[1] + w * strides[2] + c * strides[3]] +=
+                  _biasData.f[c];
+            }
+          }
+        }
+      }
+    }
+  }
+  else if (_layout == nnfw::srcn::convType_t::row_major)
+  {
+    for (uint32_t c = 0; c < _outputDescr.dimensions[1]; ++c)
+    {
+      if (_biasData.f[c] != 0)
+      {
+        for (uint32_t b = 0; b < _outputDescr.dimensions[0]; ++b)
+        {
+          for (uint32_t h = 0; h < _outputDescr.dimensions[2]; ++h)
+          {
+            for (uint32_t w = 0; w < _outputDescr.dimensions[3]; ++w)
+            {
+              _outputData.f[b * strides[0] + c * strides[1] + h * strides[2] + w * strides[3]] +=
+                  _biasData.f[c];
+            }
+          }
+        }
+      }
+    }
+  }
+  else
+  {
+    throw std::runtime_error("Wrong Layout");
+  }
+}
+
+void ConvolutionLayer::configure(uint8_t *inputData, const TensorDescriptor inputDescr,
+                                 uint8_t *kernelData, const TensorDescriptor kernelDescr,
+                                 uint8_t *biasData, const TensorDescriptor biasDescr,
+                                 const uint32_t paddingType, const uint32_t paddingLeft,
+                                 const uint32_t paddingRight, const uint32_t paddingTop,
+                                 const uint32_t paddingBottom, const uint32_t strideWidth,
+                                 const uint32_t strideHeight, uint8_t *outputData,
+                                 const TensorDescriptor outputDescr, ir::Layout layout)
+{
+  assert(inputDescr.dimensions.size() == 4);
+  assert(kernelDescr.dimensions.size() == 4);
+  assert(biasDescr.dimensions.size() == 1);
+  assert(outputDescr.dimensions.size() == 4);
+  assert(inputDescr.type == kernelDescr.type && inputDescr.type == outputDescr.type);
+  // TODO Add assertions validating height and width with padding
+  _layout = convertLayout(layout);
+  _inputData.u8 = inputData;
+  _inputDescr = inputDescr;
+  _inputType = inputDescr.type;
+  _kernelData.u8 = kernelData;
+  _kernelDescr = kernelDescr;
+  _biasData.u8 = biasData;
+  _biasDescr = biasDescr;
+  _paddingType = paddingType;
+  _paddingLeft = paddingLeft;
+  _paddingRight = paddingRight;
+  _paddingTop = paddingTop;
+  _paddingBottom = paddingBottom;
+  _strideWidth = strideWidth;
+  _strideHeight = strideHeight;
+  _outputData.u8 = outputData;
+  _outputDescr = outputDescr;
+}
+
+void ConvolutionLayer::run()
+{
+  if (_inputType == OperandType::FLOAT32)
+  {
+    convFloat32();
+  }
+  else if (_inputType == OperandType::QUANT8_ASYMM)
+  {
+    throw std::runtime_error("NYI");
+  }
+}
+
+} // namespace kernel
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/srcn/kernel/ConvolutionLayer.h b/runtime/neurun/backend/srcn/kernel/ConvolutionLayer.h
new file mode 100644
index 000000000..4edafaa87
--- /dev/null
+++ b/runtime/neurun/backend/srcn/kernel/ConvolutionLayer.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_SRCN_KERNEL_CONVOLUTION_LAYER_H__
+#define __NEURUN_BACKEND_SRCN_KERNEL_CONVOLUTION_LAYER_H__
+
+#include <exec/IFunction.h>
+#include <ncnn/srcn/conv_type.h>
+
+#include "OperationUtils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+namespace kernel
+{
+
+class ConvolutionLayer : public ::neurun::exec::IFunction
+{
+public:
+  ConvolutionLayer();
+  ~ConvolutionLayer();
+
+public:
+  void convFloat32();
+  void configure(uint8_t *inputData, const TensorDescriptor inputDescr, uint8_t *kernelData,
+                 const TensorDescriptor kernelDescr, uint8_t *biasData,
+                 const TensorDescriptor biasDescr, const uint32_t paddingType,
+                 const uint32_t paddingLeft, const uint32_t paddingRight, const uint32_t paddingTop,
+                 const uint32_t paddingBottom, const uint32_t strideW, const uint32_t strideH,
+                 uint8_t *outputData, const TensorDescriptor outputDescr, ir::Layout layout);
+
+  void run();
+  void runSync()
+  {
+    // this abstract method is used just for profiling and called for
+    // backend::acl_common::AclFunction
+    run();
+  }
+
+private:
+  DataPtr _inputData;
+  DataPtr _kernelData;
+  DataPtr _biasData;
+  DataPtr _outputData;
+
+  TensorDescriptor _inputDescr;
+  TensorDescriptor _kernelDescr;
+  TensorDescriptor _biasDescr;
+  TensorDescriptor _outputDescr;
+
+  uint32_t _paddingType;
+  uint32_t _paddingLeft;
+  uint32_t _paddingTop;
+  uint32_t _paddingRight;
+  uint32_t _paddingBottom;
+
+  uint32_t _strideWidth;
+  uint32_t _strideHeight;
+
+  OperandType _inputType;
+  nnfw::srcn::convType_t _layout;
+
+  float *_winograd_weights;
+  void *_sparse_weights;
+};
+
+} // namespace kernel
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_SRCN_KERNEL_CONVOLUTION_LAYER_H__
diff --git a/runtime/neurun/backend/srcn/kernel/DepthwiseConvolutionLayer.cc b/runtime/neurun/backend/srcn/kernel/DepthwiseConvolutionLayer.cc
new file mode 100644
index 000000000..a1718c500
--- /dev/null
+++ b/runtime/neurun/backend/srcn/kernel/DepthwiseConvolutionLayer.cc
@@ -0,0 +1,212 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "DepthwiseConvolutionLayer.h"
+
+#include <ncnn/srcn/srcn_conv.h>
+#include "OperationUtils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+namespace kernel
+{
+
+DepthwiseConvolutionLayer::DepthwiseConvolutionLayer()
+    : _inputData(), _kernelData(), _biasData(), _outputData(), _inputDescr(), _kernelDescr(),
+      _biasDescr(), _outputDescr(), _paddingType(0), _paddingLeft(0), _paddingTop(0),
+      _paddingRight(0), _paddingBottom(0), _strideWidth(0), _strideHeight(0),
+      _inputType(OperandType::FLOAT32), _layout(nnfw::srcn::col_major)
+{
+  // DO NOTHING
+}
+
+void DepthwiseConvolutionLayer::convFloat32()
+{
+  nnfw::srcn::convMat_t in_mat, out_mat, kernel_mat, bias_mat;
+  nnfw::srcn::convParams_t in_param;
+
+  assert(_layout == nnfw::srcn::col_major || _layout == nnfw::srcn::row_major);
+  size_t height_index = _layout == nnfw::srcn::col_major ? 1 : 2;
+  size_t width_index = _layout == nnfw::srcn::col_major ? 2 : 3;
+  size_t depth_index = _layout == nnfw::srcn::col_major ? 3 : 1;
+
+  const int batches = MatchingDim(_inputDescr, 0, _outputDescr, 0);
+  const int input_height = _inputDescr.dimensions[height_index];
+  const int input_width = _inputDescr.dimensions[width_index];
+  const int input_depth = _inputDescr.dimensions[depth_index];
+  in_mat.c = input_depth;
+  in_mat.w = input_width;
+  in_mat.h = input_height;
+  in_mat.n = batches;
+  in_mat.data = _inputData.f;
+
+  const int output_height = _outputDescr.dimensions[height_index];
+  const int output_width = _outputDescr.dimensions[width_index];
+  const int output_depth = MatchingDim(_kernelDescr, depth_index, _outputDescr, depth_index);
+  out_mat.c = output_depth;
+  out_mat.w = output_width;
+  out_mat.h = output_height;
+  out_mat.n = batches;
+  out_mat.data = _outputData.f;
+
+  const int ker_height = _kernelDescr.dimensions[height_index];
+  const int ker_width = _kernelDescr.dimensions[width_index];
+  kernel_mat.c = MatchingDim(_kernelDescr, depth_index, _outputDescr, depth_index);
+  kernel_mat.w = ker_width;
+  kernel_mat.h = ker_height;
+  kernel_mat.n = 1;
+  kernel_mat.data = _kernelData.f;
+
+  const int bias_depth = MatchingDim(_biasDescr, 0, _outputDescr, depth_index);
+  bias_mat.c = bias_depth;
+  bias_mat.data = _biasData.f;
+
+  in_param.kernel_w = ker_width;
+  in_param.kernel_h = ker_height;
+  in_param.stride_w = _strideWidth;
+  in_param.stride_h = _strideHeight;
+  in_param.padding = _paddingType;
+  in_param.pad_w = _paddingLeft;
+  in_param.pad_h = _paddingTop;
+  in_param.dilation_w = 1;
+  in_param.dilation_h = 1;
+
+  nnfw::srcn::srcn_depthwise_conv(in_mat, kernel_mat, out_mat, bias_mat, in_param, 4, _layout);
+
+  // Add biases
+  if (_biasData.f == nullptr)
+  {
+    return;
+  }
+  // TODO Optimize
+  uint32_t strides[4] = {
+      _outputDescr.dimensions[1] * _outputDescr.dimensions[2] * _outputDescr.dimensions[3],
+      _outputDescr.dimensions[2] * _outputDescr.dimensions[3], _outputDescr.dimensions[3], 1};
+  if (_layout == nnfw::srcn::convType_t::col_major)
+  {
+    for (uint32_t c = 0; c < _outputDescr.dimensions[3]; ++c)
+    {
+      if (_biasData.f[c] != 0)
+      {
+        for (uint32_t b = 0; b < _outputDescr.dimensions[0]; ++b)
+        {
+          for (uint32_t h = 0; h < _outputDescr.dimensions[1]; ++h)
+          {
+            for (uint32_t w = 0; w < _outputDescr.dimensions[2]; ++w)
+            {
+              _outputData.f[b * strides[0] + h * strides[1] + w * strides[2] + c * strides[3]] +=
+                  _biasData.f[c];
+            }
+          }
+        }
+      }
+    }
+  }
+  else if (_layout == nnfw::srcn::convType_t::row_major)
+  {
+    for (uint32_t c = 0; c < _outputDescr.dimensions[1]; ++c)
+    {
+      if (_biasData.f[c] != 0)
+      {
+        for (uint32_t b = 0; b < _outputDescr.dimensions[0]; ++b)
+        {
+          for (uint32_t h = 0; h < _outputDescr.dimensions[2]; ++h)
+          {
+            for (uint32_t w = 0; w < _outputDescr.dimensions[3]; ++w)
+            {
+              _outputData.f[b * strides[0] + c * strides[1] + h * strides[2] + w * strides[3]] +=
+                  _biasData.f[c];
+            }
+          }
+        }
+      }
+    }
+  }
+  else
+  {
+    throw std::runtime_error("Wrong Layout");
+  }
+}
+
+void DepthwiseConvolutionLayer::configure(uint8_t *inputData, const TensorDescriptor inputDescr,
+                                          uint8_t *kernelData, const TensorDescriptor kernelDescr,
+                                          uint8_t *biasData, const TensorDescriptor biasDescr,
+                                          const uint32_t paddingType, const uint32_t paddingLeft,
+                                          const uint32_t paddingRight, const uint32_t paddingTop,
+                                          const uint32_t paddingBottom, const uint32_t strideWidth,
+                                          const uint32_t strideHeight, uint8_t *outputData,
+                                          const TensorDescriptor outputDescr, ir::Layout layout)
+{
+  assert(layout == ir::Layout::NHWC || layout == ir::Layout::NCHW);
+
+  const auto height_index = layout == ir::Layout::NHWC ? 1 : 2;
+  const auto width_index = layout == ir::Layout::NHWC ? 2 : 3;
+
+  if (layout == ir::Layout::NHWC)
+  {
+    throw std::runtime_error("DepthwiseConv of ncnn does not support layout yet in NHWC");
+  }
+
+  if (kernelDescr.dimensions[height_index] != 3 || kernelDescr.dimensions[width_index] != 3)
+  {
+    throw std::runtime_error("DepthwiseConv of ncnn supports only 3x3 kernel now");
+  }
+
+  assert(inputDescr.dimensions.size() == 4);
+  assert(kernelDescr.dimensions.size() == 4);
+  assert(biasDescr.dimensions.size() == 1);
+  assert(outputDescr.dimensions.size() == 4);
+  assert(inputDescr.type == kernelDescr.type && inputDescr.type == outputDescr.type);
+  // TODO Add assertions validating height and width with padding
+  _layout = convertLayout(layout);
+  _inputData.u8 = inputData;
+  _inputDescr = inputDescr;
+  _inputType = inputDescr.type;
+  _kernelData.u8 = kernelData;
+  _kernelDescr = kernelDescr;
+  _biasData.u8 = biasData;
+  _biasDescr = biasDescr;
+  _paddingType = paddingType;
+  _paddingLeft = paddingLeft;
+  _paddingRight = paddingRight;
+  _paddingTop = paddingTop;
+  _paddingBottom = paddingBottom;
+  _strideWidth = strideWidth;
+  _strideHeight = strideHeight;
+  _outputData.u8 = outputData;
+  _outputDescr = outputDescr;
+}
+
+void DepthwiseConvolutionLayer::run()
+{
+  if (_inputType == OperandType::FLOAT32)
+  {
+    convFloat32();
+  }
+  else if (_inputType == OperandType::QUANT8_ASYMM)
+  {
+    throw std::runtime_error("NYI");
+  }
+}
+
+} // namespace kernel
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/srcn/kernel/DepthwiseConvolutionLayer.h b/runtime/neurun/backend/srcn/kernel/DepthwiseConvolutionLayer.h
new file mode 100644
index 000000000..e94acff08
--- /dev/null
+++ b/runtime/neurun/backend/srcn/kernel/DepthwiseConvolutionLayer.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_SRCN_KERNEL_DEPTHWISE_CONVOLUTION_LAYER_H__
+#define __NEURUN_BACKEND_SRCN_KERNEL_DEPTHWISE_CONVOLUTION_LAYER_H__
+
+#include <exec/IFunction.h>
+#include <ncnn/srcn/conv_type.h>
+
+#include "OperationUtils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+namespace kernel
+{
+
+class DepthwiseConvolutionLayer : public ::neurun::exec::IFunction
+{
+public:
+  DepthwiseConvolutionLayer();
+
+public:
+  void convFloat32();
+  void configure(uint8_t *inputData, const TensorDescriptor inputDescr, uint8_t *kernelData,
+                 const TensorDescriptor kernelDescr, uint8_t *biasData,
+                 const TensorDescriptor biasDescr, const uint32_t paddingType,
+                 const uint32_t paddingLeft, const uint32_t paddingRight, const uint32_t paddingTop,
+                 const uint32_t paddingBottom, const uint32_t strideW, const uint32_t strideH,
+                 uint8_t *outputData, const TensorDescriptor outputDescr, ir::Layout layout);
+
+  void run();
+  void runSync()
+  {
+    // this abstract method is used just for profiling and called for
+    // backend::acl_common::AclFunction
+    run();
+  }
+
+private:
+  DataPtr _inputData;
+  DataPtr _kernelData;
+  DataPtr _biasData;
+  DataPtr _outputData;
+
+  TensorDescriptor _inputDescr;
+  TensorDescriptor _kernelDescr;
+  TensorDescriptor _biasDescr;
+  TensorDescriptor _outputDescr;
+
+  uint32_t _paddingType;
+  uint32_t _paddingLeft;
+  uint32_t _paddingTop;
+  uint32_t _paddingRight;
+  uint32_t _paddingBottom;
+
+  uint32_t _strideWidth;
+  uint32_t _strideHeight;
+
+  OperandType _inputType;
+  nnfw::srcn::convType_t _layout;
+};
+
+} // namespace kernel
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_SRCN_KERNEL_DEPTHWISE_CONVOLUTION_LAYER_H__
diff --git a/runtime/neurun/backend/srcn/kernel/InstanceNormLayer.cc b/runtime/neurun/backend/srcn/kernel/InstanceNormLayer.cc
new file mode 100644
index 000000000..c83fe6d67
--- /dev/null
+++ b/runtime/neurun/backend/srcn/kernel/InstanceNormLayer.cc
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "InstanceNormLayer.h"
+
+#include "OperationUtils.h"
+#include "ncnn/layer/instance_norm.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+namespace kernel
+{
+
+InstanceNormLayer::InstanceNormLayer()
+    : _inputData(), _gammaData(), _betaData(), _outputData(), _inputDescr(), _gammaDescr(),
+      _betaDescr(), _outputDescr(), _epsilon(1e-5), _activation(ir::Activation::NONE),
+      _inputType(OperandType::FLOAT32), _backendLayout(ir::Layout::UNKNOWN)
+{
+  // DO NOTHING
+}
+
+void InstanceNormLayer::instanceNormFloat32()
+{
+  // Call kernel for NCHW data layout
+  if (_backendLayout == ir::Layout::NCHW)
+  {
+    // Supports single batch only
+    assert(_inputDescr.dimensions[0] == 1);
+    const int input_channels = _inputDescr.dimensions[1];
+    const int input_height = _inputDescr.dimensions[2];
+    const int input_width = _inputDescr.dimensions[3];
+    nnfw::ncnn::Mat in_mat(input_width, input_height, input_channels, _inputData.f);
+
+    const int gamma_channels = _gammaDescr.dimensions[0];
+    nnfw::ncnn::Mat gamma_mat(gamma_channels, _gammaData.f);
+
+    const int beta_channels = _betaDescr.dimensions[0];
+    nnfw::ncnn::Mat beta_mat(beta_channels, _betaData.f);
+
+    assert(_outputDescr.dimensions[0] == 1);
+    const int output_channels = _outputDescr.dimensions[1];
+    const int output_height = _outputDescr.dimensions[2];
+    const int output_width = _outputDescr.dimensions[3];
+    nnfw::ncnn::Mat out_mat(output_width, output_height, output_channels, _outputData.f);
+
+    if (_activation == ir::Activation::NONE)
+    {
+      nnfw::ncnn::ncnn_instance_norm_rowmajor(in_mat, out_mat, gamma_mat, beta_mat, input_channels,
+                                              _epsilon);
+    }
+    else if (_activation == ir::Activation::RELU)
+    {
+      nnfw::ncnn::ncnn_instance_norm_with_relu_rowmajor(in_mat, out_mat, gamma_mat, beta_mat,
+                                                        input_channels, _epsilon, 0.f);
+    }
+    else
+    {
+      std::runtime_error("Unsupported activation type");
+    }
+  }
+  // Call kernel for NHWC data layout
+  else if (_backendLayout == ir::Layout::NHWC)
+  {
+    // Supports single batch only
+    assert(_inputDescr.dimensions[0] == 1);
+    const int input_height = _inputDescr.dimensions[1];
+    const int input_width = _inputDescr.dimensions[2];
+    const int input_channels = _inputDescr.dimensions[3];
+    nnfw::ncnn::Mat in_mat(input_channels, input_width, input_height, _inputData.f);
+
+    const int gamma_channels = _gammaDescr.dimensions[0];
+    nnfw::ncnn::Mat gamma_mat(gamma_channels, _gammaData.f);
+
+    const int beta_channels = _betaDescr.dimensions[0];
+    nnfw::ncnn::Mat beta_mat(beta_channels, _betaData.f);
+
+    assert(_outputDescr.dimensions[0] == 1);
+    const int output_height = _outputDescr.dimensions[1];
+    const int output_width = _outputDescr.dimensions[2];
+    const int output_channels = _outputDescr.dimensions[3];
+    nnfw::ncnn::Mat out_mat(output_channels, output_width, output_height, _outputData.f);
+
+    if (_activation == ir::Activation::NONE)
+    {
+      nnfw::ncnn::ncnn_instance_norm_colmajor(in_mat, out_mat, gamma_mat, beta_mat, input_channels,
+                                              _epsilon);
+    }
+    else if (_activation == ir::Activation::RELU)
+    {
+      nnfw::ncnn::ncnn_instance_norm_with_relu_colmajor(in_mat, out_mat, gamma_mat, beta_mat,
+                                                        input_channels, _epsilon, 0.f);
+    }
+    {
+      std::runtime_error("Unsupported activation type");
+    }
+  }
+  else
+  {
+    std::runtime_error("Unsupported backend layout");
+  }
+}
+
+void InstanceNormLayer::configure(uint8_t *inputData, const TensorDescriptor inputDescr,
+                                  uint8_t *gammaData, const TensorDescriptor gammaDescr,
+                                  uint8_t *betaData, const TensorDescriptor betaDescr,
+                                  uint8_t *outputData, const TensorDescriptor outputDescr,
+                                  float epsilon, ir::Activation activation,
+                                  ir::Layout backendLayout)
+{
+  _inputData.u8 = inputData;
+  _inputDescr = inputDescr;
+  _gammaData.u8 = gammaData;
+  _gammaDescr = gammaDescr;
+  _betaData.u8 = betaData;
+  _betaDescr = betaDescr;
+  _outputData.u8 = outputData;
+  _outputDescr = outputDescr;
+  _epsilon = epsilon;
+  _activation = activation;
+  _backendLayout = backendLayout;
+}
+
+void InstanceNormLayer::run()
+{
+  if (_inputType == OperandType::FLOAT32)
+  {
+    instanceNormFloat32();
+  }
+  else if (_inputType == OperandType::QUANT8_ASYMM)
+  {
+    throw std::runtime_error("NYI");
+  }
+}
+
+} // namespace kernel
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/srcn/kernel/InstanceNormLayer.h b/runtime/neurun/backend/srcn/kernel/InstanceNormLayer.h
new file mode 100644
index 000000000..0ac0cef3f
--- /dev/null
+++ b/runtime/neurun/backend/srcn/kernel/InstanceNormLayer.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_SRCN_KERNEL_INSTANCENORM_LAYER_H__
+#define __NEURUN_BACKEND_SRCN_KERNEL_INSTANCENORM_LAYER_H__
+
+#include <exec/IFunction.h>
+
+#include "OperationUtils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+namespace kernel
+{
+
+class InstanceNormLayer : public ::neurun::exec::IFunction
+{
+public:
+  InstanceNormLayer();
+
+public:
+  void instanceNormFloat32();
+  void configure(uint8_t *inputData, const TensorDescriptor inputDescr, uint8_t *gammaData,
+                 const TensorDescriptor gammaDescr, uint8_t *betaData,
+                 const TensorDescriptor betaDescr, uint8_t *outputData,
+                 const TensorDescriptor outputDescr, float epsilon, ir::Activation activation,
+                 ir::Layout backendLayout);
+
+  void run();
+  void runSync()
+  {
+    // this abstract method is used just for profiling and called for
+    // backend::acl_common::AclFunction
+    run();
+  }
+
+private:
+  DataPtr _inputData;
+  DataPtr _gammaData;
+  DataPtr _betaData;
+  DataPtr _outputData;
+
+  TensorDescriptor _inputDescr;
+  TensorDescriptor _gammaDescr;
+  TensorDescriptor _betaDescr;
+  TensorDescriptor _outputDescr;
+
+  float _epsilon;
+  ir::Activation _activation;
+
+  OperandType _inputType;
+  ir::Layout _backendLayout;
+};
+
+} // namespace kernel
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_SRCN_KERNEL_INSTANCENORM_LAYER_H__
diff --git a/runtime/neurun/backend/srcn/kernel/OperationUtils.cc b/runtime/neurun/backend/srcn/kernel/OperationUtils.cc
new file mode 100644
index 000000000..684573a51
--- /dev/null
+++ b/runtime/neurun/backend/srcn/kernel/OperationUtils.cc
@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "OperationUtils.h"
+
+#include <cmath>
+#include <algorithm>
+#include <cassert>
+#include <map>
+
+#include "util/Utils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+namespace kernel
+{
+
+uint32_t MatchingDim(const TensorDescriptor &descr1, int index1, const TensorDescriptor &descr2,
+                     int index2)
+{
+  UNUSED_RELEASE(descr2);
+  UNUSED_RELEASE(index2);
+  assert(descr1.dimensions[index1] == descr2.dimensions[index2]);
+  return descr1.dimensions[index1];
+}
+
+std::vector<int32_t> getFilterPermutation(FilterLayout from_layout, FilterLayout to_layout)
+{
+  static std::map<std::pair<FilterLayout, FilterLayout>, std::vector<int32_t>> filter_permutation =
+      {{std::make_pair(FilterLayout::OHWI, FilterLayout::HWOI), {1, 2, 0, 3}},
+       {std::make_pair(FilterLayout::OHWI, FilterLayout::HWIO), {1, 2, 3, 0}},
+       {std::make_pair(FilterLayout::OHWI, FilterLayout::OIHW), {0, 3, 1, 2}},
+       {std::make_pair(FilterLayout::OHWI, FilterLayout::IOHW), {3, 0, 1, 2}},
+       {std::make_pair(FilterLayout::OIHW, FilterLayout::HWOI), {2, 3, 0, 1}},
+       {std::make_pair(FilterLayout::OIHW, FilterLayout::HWIO), {2, 3, 1, 0}},
+       {std::make_pair(FilterLayout::OIHW, FilterLayout::OHWI), {0, 2, 3, 1}},
+       {std::make_pair(FilterLayout::OIHW, FilterLayout::IOHW), {1, 0, 2, 3}}};
+
+  const auto pair = std::make_pair(from_layout, to_layout);
+  const auto it = filter_permutation.find(pair);
+  if (it == filter_permutation.end())
+  {
+    return std::vector<int32_t>{};
+  }
+  return it->second;
+}
+
+Coordinates convertCoordinates(const Coordinates &coordinates, FilterLayout from_layout,
+                               FilterLayout to_layout)
+{
+  assert(coordinates.size() == 4);
+  if (from_layout == to_layout)
+  {
+    return coordinates;
+  }
+
+  const auto permutation = getFilterPermutation(from_layout, to_layout);
+  if (permutation.size() == 0)
+  {
+    throw std::runtime_error("Not supported FilterLayout");
+  }
+  return Coordinates{coordinates[permutation[0]], coordinates[permutation[1]],
+                     coordinates[permutation[2]], coordinates[permutation[3]]};
+}
+
+nnfw::srcn::convType_t convertLayout(ir::Layout layout)
+{
+  if (layout == ir::Layout::NHWC)
+  {
+    return nnfw::srcn::col_major;
+  }
+  else if (layout == ir::Layout::NCHW)
+  {
+    return nnfw::srcn::row_major;
+  }
+  else
+  {
+    throw std::runtime_error("Not supported layout");
+  }
+}
+
+TensorDescriptor getTensorDescriptor(const ir::Operand &o, ir::Layout frontend_layout,
+                                     ir::Layout backend_layout)
+{
+  TensorDescriptor descriptor;
+
+  auto dims = o.shape().dims();
+  if (frontend_layout == ir::Layout::NHWC && backend_layout == ir::Layout::NCHW &&
+      o.shape().rank() == 4)
+  {
+    // NHWC -> NCHW
+    uint32_t permutation[4] = {0, 3, 1, 2};
+    for (int i = 0; i < o.shape().rank(); ++i)
+    {
+      dims.at(i) = o.shape().dim(permutation[i]);
+    }
+  }
+  else if (frontend_layout == ir::Layout::NCHW && backend_layout == ir::Layout::NHWC &&
+           o.shape().rank() == 4)
+  {
+    // NCHW -> NHWC
+    uint32_t permutation[4] = {0, 2, 3, 1};
+    for (int i = 0; i < o.shape().rank(); ++i)
+    {
+      dims.at(i) = o.shape().dim(permutation[i]);
+    }
+  }
+  descriptor.dimensions = std::vector<uint32_t>(dims.begin(), dims.end());
+  descriptor.type = static_cast<OperandType>(static_cast<int32_t>(o.typeInfo().type()));
+  descriptor.scale = o.typeInfo().scale();
+  descriptor.offset = o.typeInfo().offset();
+
+  // CPU backend assume that neurun internal descriptor's rank is always same or less than 4
+  assert(descriptor.dimensions.size() <= 4);
+
+  return descriptor;
+}
+
+} // namespace kernel
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/srcn/kernel/OperationUtils.h b/runtime/neurun/backend/srcn/kernel/OperationUtils.h
new file mode 100644
index 000000000..aa163a1f3
--- /dev/null
+++ b/runtime/neurun/backend/srcn/kernel/OperationUtils.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_SRCN_OPERATION_UTILS_H__
+#define __NEURUN_BACKEND_SRCN_OPERATION_UTILS_H__
+
+#include <iostream>
+#include <limits>
+#include <vector>
+
+#include "ir/Operand.h"
+#include "ir/DataType.h"
+#include <ir/InternalType.h>
+#include <ncnn/srcn/conv_type.h>
+
+using OperandType = neurun::ir::DataType;
+using neurun::util::Coordinates;
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+namespace kernel
+{
+
+struct TensorDescriptor
+{
+  OperandType type;
+  std::vector<uint32_t> dimensions;
+  float scale;
+  int32_t offset;
+};
+
+union DataPtr {
+  uint8_t *u8;
+  int8_t *i8;
+  int32_t *i32;
+  float *f;
+  void *v;
+};
+
+enum FilterLayout
+{
+  OHWI = 0, // TfLite Kernel Layout when using NHWC image layout
+  HWOI,     // SRCN Transpose Conv Kernel Layout when using NHWC image layout
+  OIHW,     // SRCN Conv Kernel Layout when using NCHW image layout
+  HWIO,     // SRCN Conv Kernel Layout when using NHWC image layout
+  IOHW,     // SRCN Transpose Conv Kernel Layout when using NCHW image layout
+};
+
+uint32_t MatchingDim(const TensorDescriptor &shape1, int index1, const TensorDescriptor &shape2,
+                     int index2);
+
+std::vector<int32_t> getFilterPermutation(FilterLayout from_layout, FilterLayout to_layout);
+
+Coordinates convertCoordinates(const Coordinates &from_coordinates, FilterLayout from_layout,
+                               FilterLayout to_layout);
+
+nnfw::srcn::convType_t convertLayout(ir::Layout layout);
+
+TensorDescriptor getTensorDescriptor(const ir::Operand &o, ir::Layout frontend_layout,
+                                     ir::Layout backend_layout);
+
+} // namespace kernel
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_SRCN_OPERATION_UTILS_H__
diff --git a/runtime/neurun/backend/srcn/kernel/TransposeConvLayer.cc b/runtime/neurun/backend/srcn/kernel/TransposeConvLayer.cc
new file mode 100644
index 000000000..26469f728
--- /dev/null
+++ b/runtime/neurun/backend/srcn/kernel/TransposeConvLayer.cc
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "TransposeConvLayer.h"
+
+#include <cstring>
+#include "OperationUtils.h"
+#include "ncnn/srcn/srcn_conv.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+namespace kernel
+{
+
+TransposeConvLayer::TransposeConvLayer()
+    : _inputData(), _kernelData(), _outputData(), _inputDescr(), _kernelDescr(), _outputDescr(),
+      _paddingType(0), _paddingLeft(0), _paddingTop(0), _paddingRight(0), _paddingBottom(0),
+      _strideWidth(0), _strideHeight(0), _inputType(OperandType::FLOAT32),
+      _layout(nnfw::srcn::col_major)
+{
+  // DO NOTHING
+}
+
+void TransposeConvLayer::convFloat32()
+{
+  nnfw::srcn::convMat_t in_mat, out_mat, kernel_mat;
+  nnfw::srcn::convParams_t in_param;
+
+  assert(_layout == nnfw::srcn::col_major || _layout == nnfw::srcn::row_major);
+  size_t height_index = _layout == nnfw::srcn::col_major ? 1 : 2;
+  size_t width_index = _layout == nnfw::srcn::col_major ? 2 : 3;
+  size_t depth_index = _layout == nnfw::srcn::col_major ? 3 : 1;
+  size_t kernel_input_depth_index = _layout == nnfw::srcn::col_major ? 3 : 1;
+  size_t kernel_output_depth_index = 0;
+  const int batches = MatchingDim(_inputDescr, 0, _outputDescr, 0);
+  const int input_height = _inputDescr.dimensions[height_index];
+  const int input_width = _inputDescr.dimensions[width_index];
+  const int input_depth =
+      MatchingDim(_inputDescr, depth_index, _kernelDescr, kernel_input_depth_index);
+  in_mat.c = input_depth;
+  in_mat.w = input_width;
+  in_mat.h = input_height;
+  in_mat.n = batches;
+  in_mat.data = _inputData.f;
+
+  const int output_height = _outputDescr.dimensions[height_index];
+  const int output_width = _outputDescr.dimensions[width_index];
+  const int output_depth =
+      MatchingDim(_kernelDescr, kernel_output_depth_index, _outputDescr, depth_index);
+  out_mat.c = output_depth;
+  out_mat.w = output_width;
+  out_mat.h = output_height;
+  out_mat.n = batches;
+  out_mat.data = _outputData.f;
+
+  const int ker_height = _kernelDescr.dimensions[height_index];
+  const int ker_width = _kernelDescr.dimensions[width_index];
+  kernel_mat.c = input_depth;
+  kernel_mat.w = ker_width;
+  kernel_mat.h = ker_height;
+  kernel_mat.n = output_depth;
+  kernel_mat.data = _kernelData.f;
+
+  in_param.kernel_w = ker_width;
+  in_param.kernel_h = ker_height;
+  in_param.stride_w = _strideWidth;
+  in_param.stride_h = _strideHeight;
+  in_param.padding = _paddingType;
+  in_param.pad_w = _paddingLeft;
+  in_param.pad_h = _paddingTop;
+  in_param.dilation_w = 1;
+  in_param.dilation_h = 1;
+
+  memset(_outputData.f, 0, out_mat.n * out_mat.h * out_mat.w * out_mat.c * sizeof(float));
+
+  nnfw::srcn::srcn_deconvolution2D(in_mat, kernel_mat, out_mat, in_param, 4, _layout);
+}
+
+void TransposeConvLayer::configure(uint8_t *inputData, const TensorDescriptor inputDescr,
+                                   uint8_t *kernelData, const TensorDescriptor kernelDescr,
+                                   const uint32_t paddingType, const uint32_t paddingLeft,
+                                   const uint32_t paddingRight, const uint32_t paddingTop,
+                                   const uint32_t paddingBottom, const uint32_t strideWidth,
+                                   const uint32_t strideHeight, uint8_t *outputData,
+                                   const TensorDescriptor outputDescr, ir::Layout layout)
+{
+  _layout = convertLayout(layout);
+  _inputData.u8 = inputData;
+  _inputDescr = inputDescr;
+  _inputType = inputDescr.type;
+  _kernelData.u8 = kernelData;
+  _kernelDescr = kernelDescr;
+  _paddingType = paddingType;
+  _paddingLeft = paddingLeft;
+  _paddingRight = paddingRight;
+  _paddingTop = paddingTop;
+  _paddingBottom = paddingBottom;
+  _strideWidth = strideWidth;
+  _strideHeight = strideHeight;
+  _outputData.u8 = outputData;
+  _outputDescr = outputDescr;
+}
+
+void TransposeConvLayer::run()
+{
+  if (_inputType == OperandType::FLOAT32)
+  {
+    convFloat32();
+  }
+  else if (_inputType == OperandType::QUANT8_ASYMM)
+  {
+    throw std::runtime_error("NYI");
+  }
+}
+
+} // namespace kernel
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/srcn/kernel/TransposeConvLayer.h b/runtime/neurun/backend/srcn/kernel/TransposeConvLayer.h
new file mode 100644
index 000000000..cd88d4127
--- /dev/null
+++ b/runtime/neurun/backend/srcn/kernel/TransposeConvLayer.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_SRCN_KERNEL_TRANSPOSECONV_LAYER_H__
+#define __NEURUN_BACKEND_SRCN_KERNEL_TRANSPOSECONV_LAYER_H__
+
+#include <exec/IFunction.h>
+#include <ncnn/srcn/conv_type.h>
+
+#include "OperationUtils.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+namespace kernel
+{
+
+class TransposeConvLayer : public ::neurun::exec::IFunction
+{
+public:
+  TransposeConvLayer();
+
+public:
+  void convFloat32();
+  void configure(uint8_t *inputData, const TensorDescriptor inputDescr, uint8_t *kernelData,
+                 const TensorDescriptor kernelDescr, const uint32_t paddingType,
+                 const uint32_t paddingLeft, const uint32_t paddingRight, const uint32_t paddingTop,
+                 const uint32_t paddingBottom, const uint32_t strideW, const uint32_t strideH,
+                 uint8_t *outputData, const TensorDescriptor outputDescr,
+                 ir::Layout backend_layout);
+
+  void run();
+  void runSync()
+  {
+    // this abstract method is used just for profiling and called for
+    // backend::acl_common::AclFunction
+    run();
+  }
+
+private:
+  DataPtr _inputData;
+  DataPtr _kernelData;
+  DataPtr _outputData;
+
+  TensorDescriptor _inputDescr;
+  TensorDescriptor _kernelDescr;
+  TensorDescriptor _outputDescr;
+
+  uint32_t _paddingType;
+  uint32_t _paddingLeft;
+  uint32_t _paddingTop;
+  uint32_t _paddingRight;
+  uint32_t _paddingBottom;
+
+  uint32_t _strideWidth;
+  uint32_t _strideHeight;
+
+  OperandType _inputType;
+  nnfw::srcn::convType_t _layout;
+};
+
+} // namespace kernel
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_SRCN_KERNEL_TRANSPOSECONV_LAYER_H__
diff --git a/runtime/neurun/backend/srcn/operand/Tensor.cc b/runtime/neurun/backend/srcn/operand/Tensor.cc
new file mode 100644
index 000000000..8a53f97c5
--- /dev/null
+++ b/runtime/neurun/backend/srcn/operand/Tensor.cc
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "Tensor.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+namespace operand
+{
+
+size_t Tensor::calcOffset(const neurun::util::Coordinates &coords) const
+{
+  size_t rank = num_dimensions();
+  size_t offset = 0;
+  for (size_t i = 0; i < rank; ++i)
+  {
+    offset = offset * dimension(i) + coords[i];
+  }
+  offset *= sizeOfDataType(data_type());
+  return offset;
+}
+
+void Tensor::access(const std::function<void(ITensor &)> &fn) { fn(*this); }
+
+} // namespace operand
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/backend/srcn/operand/Tensor.h b/runtime/neurun/backend/srcn/operand/Tensor.h
new file mode 100644
index 000000000..e16234a81
--- /dev/null
+++ b/runtime/neurun/backend/srcn/operand/Tensor.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_SRCN_OPERAND_TENSOR_H__
+#define __NEURUN_BACKEND_SRCN_OPERAND_TENSOR_H__
+
+#include <backend/operand/ITensor.h>
+#include <ir/Layout.h>
+#include "ir/OperandInfo.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace srcn
+{
+namespace operand
+{
+
+class Tensor : public ::neurun::backend::operand::ITensor
+{
+public:
+  Tensor() = delete;
+
+public:
+  Tensor(const ir::OperandInfo &info, ir::Layout layout) : _info(info), _layout(layout)
+  {
+    // DO NOTHING
+  }
+
+public:
+  void setBuffer(uint8_t *buffer) { _buffer = buffer; }
+  ir::DataType data_type() const { return _info.typeInfo().type(); }
+
+public:
+  uint8_t *buffer() const override { return _buffer; }
+  /**
+   * @brief Get dimension by index
+   *
+   * @param index Index to get diemension
+   * @return size_t Dimension at index
+   * @note N : dimension(0)
+   *       H : dimension(1)
+   *       W : dimension(2)
+   *       C : dimension(3)
+   */
+  size_t dimension(size_t index) const override { return _info.shape().dim(index); }
+  size_t num_dimensions() const override { return _info.shape().rank(); }
+  size_t total_size() const override { return _info.total_size(); }
+  size_t calcOffset(const neurun::util::Coordinates &coords) const override;
+  ir::Layout layout() const override { return _layout; }
+  bool has_padding() const override { return false; }
+  void access(const std::function<void(ITensor &tensor)> &fn) final;
+
+private:
+  ir::OperandInfo _info;
+  uint8_t *_buffer = nullptr;
+  ir::Layout _layout;
+};
+
+} // namespace operand
+} // namespace srcn
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_SRCN_OPERAND_TENSOR_H__
diff --git a/runtime/neurun/core/CMakeLists.txt b/runtime/neurun/core/CMakeLists.txt
new file mode 100644
index 000000000..422d292bb
--- /dev/null
+++ b/runtime/neurun/core/CMakeLists.txt
@@ -0,0 +1,18 @@
+file(GLOB_RECURSE SOURCES "src/*.cc")
+
+add_library(neurun_core SHARED ${SOURCES})
+set_target_properties(neurun_core PROPERTIES POSITION_INDEPENDENT_CODE ON)
+target_include_directories(neurun_core PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/include)
+target_include_directories(neurun_core PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/src)
+target_link_libraries(neurun_core PUBLIC nnfw_lib_misc)
+target_link_libraries(neurun_core PUBLIC nnfw_lib_cpp14)
+target_link_libraries(neurun_core PRIVATE nnfw_lib_cker)
+target_link_libraries(neurun_core PRIVATE nnfw_common)
+target_link_libraries(neurun_core PRIVATE nnfw_coverage)
+target_link_libraries(neurun_core PRIVATE dl ${LIB_PTHREAD})
+
+if(ENVVAR_NEURUN_CONFIG)
+  target_compile_definitions(neurun_core PRIVATE ENVVAR_FOR_DEFAULT_CONFIG)
+endif(ENVVAR_NEURUN_CONFIG)
+
+install(TARGETS neurun_core DESTINATION lib)
diff --git a/runtime/neurun/core/include/backend/Backend.h b/runtime/neurun/core/include/backend/Backend.h
new file mode 100644
index 000000000..9c4484fca
--- /dev/null
+++ b/runtime/neurun/core/include/backend/Backend.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_BACKEND_H__
+#define __NEURUN_BACKEND_BACKEND_H__
+
+#include <memory>
+
+#include "ir/Operands.h"
+
+namespace neurun
+{
+namespace backend
+{
+
+namespace custom
+{
+class IKernelBuilder;
+}
+
+class Backend;
+struct IConfig;
+class IConstantInitializer;
+class IKernelGenerator;
+class IShapeFixer;
+class ITensorRegister;
+struct ITensorBuilder;
+
+class BackendContext
+{
+public:
+  const Backend *backend;
+  std::shared_ptr<ITensorBuilder> tensor_builder;
+  std::shared_ptr<IConstantInitializer> constant_initializer;
+  std::shared_ptr<IKernelGenerator> kernel_gen;
+  std::shared_ptr<IShapeFixer> shape_fixer;
+  std::shared_ptr<ITensorRegister> tensor_register;
+};
+
+class Backend
+{
+public:
+  virtual ~Backend() = default;
+  virtual std::shared_ptr<neurun::backend::IConfig> config() const = 0;
+
+  virtual std::unique_ptr<BackendContext>
+  newContext(const ir::Operands &operands,
+             const std::shared_ptr<backend::custom::IKernelBuilder> &kb) const = 0;
+};
+
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_BACKEND_H__
diff --git a/runtime/neurun/core/include/backend/CustomKernelBuilder.h b/runtime/neurun/core/include/backend/CustomKernelBuilder.h
new file mode 100644
index 000000000..848ebd595
--- /dev/null
+++ b/runtime/neurun/core/include/backend/CustomKernelBuilder.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_CUSTOM_KERNEL_BUILDER_H__
+#define __NEURUN_BACKEND_CUSTOM_KERNEL_BUILDER_H__
+
+#include "exec/IFunction.h"
+
+#include "misc/tensor/Shape.h"
+#include "ir/DataType.h"
+
+#include <vector>
+#include <memory>
+
+namespace neurun
+{
+namespace backend
+{
+namespace custom
+{
+
+using Shape = nnfw::misc::tensor::Shape;
+
+struct TypeInfo
+{
+  Shape shape;
+  ir::DataType dtype;
+};
+
+struct CustomKernelConfigParams
+{
+  std::vector<void *> input_allocations;
+  std::vector<TypeInfo> input_types;
+
+  std::vector<void *> output_allocations;
+  std::vector<TypeInfo> output_types;
+
+  char *userdata;
+  size_t userdata_size;
+};
+
+class IKernelBuilder
+{
+public:
+  virtual ~IKernelBuilder() = default;
+  virtual std::unique_ptr<exec::IFunction> buildKernel(const std::string &id,
+                                                       CustomKernelConfigParams &&params) const = 0;
+};
+
+} // namespace custom
+
+} // namespace backend
+
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_CUSTOM_KERNEL_BUILDER_H__
diff --git a/runtime/neurun/core/include/backend/ExecTime.h b/runtime/neurun/core/include/backend/ExecTime.h
new file mode 100644
index 000000000..4eaf49fab
--- /dev/null
+++ b/runtime/neurun/core/include/backend/ExecTime.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_EXEC_TIME_H__
+#define __NEURUN_BACKEND_EXEC_TIME_H__
+
+#include "backend/Backend.h"
+#include "backend/IConfig.h"
+#include "JSONExecTime.h"
+#include <memory>
+#include <limits>
+#include <map>
+#include <unordered_map>
+#include <vector>
+
+namespace neurun
+{
+namespace backend
+{
+class ExecTime
+{
+public:
+  explicit ExecTime(const std::vector<const Backend *> &backends) : _json(backends, _measurements)
+  {
+  }
+
+public:
+  /**
+   * @brief Get exec time of an operation with input size
+   *        or linearly interpolated value based on size if there is no record for given size
+   *
+   * @param[in] backend id of a backend
+   * @param[in] operation name of an operation
+   * @param[in] quant if input type quantized
+   * @param[in] op_size sum of operation's flattened sizes of inputs and outputs
+   * @return execution time for given input sizes
+   *         -1 if there are no records for given parameters (backend, op, quantization).
+   */
+  int64_t getOperationExecTime(const Backend *backend, const std::string &operation, bool quant,
+                               uint32_t op_size) const;
+  /**
+   * @brief Update exec time of the operation on a backend with given input size or
+   *        add new entity if there is no one.
+   *
+   * @param[in] backend id of a backend
+   * @param[in] operation name of an operation
+   * @param[in] quant if input type quantized
+   * @param[in] op_size sum of operation's flattened sizes of inputs and outputs
+   * @param[in] time real measured value
+   */
+  void updateOperationExecTime(const Backend *backend, const std::string &operation, bool quant,
+                               uint32_t op_size, int64_t time);
+  /**
+   * @brief Get the permute time from one backend to another
+   *
+   * @param[in] from_backend
+   * @param[in] to_backend
+   * @param[in] quant if input type quantized
+   * @param[in] op_size sum of operation's flattened sizes of inputs and outputs
+   * @return permutation time for operation size
+   */
+  int64_t getPermuteTime(const Backend *from_backend, const Backend *to_backend, bool quant,
+                         uint32_t op_size) const;
+  /**
+   * @brief Update permute time from one backend to another
+   *
+   * @param[in] from_backend
+   * @param[in] to_backend
+   * @param[in] quant if input type quantized
+   * @param[in] time measured permutation time
+   * @param[in] op_size sum of operation's flattened sizes of inputs and outputs
+   */
+  void updatePermuteTime(const Backend *from_backend, const Backend *to_backend, bool quant,
+                         uint32_t op_size, int64_t time);
+  /**
+   * @brief Get the max value of int32_t in int64_t
+   * @return max value
+   */
+  static int64_t getMax() { return _MAX; }
+  /**
+   * @brief Update metrics file with new data.
+   */
+  void uploadOperationsExecTime() const { _json.uploadOperationsExecTime(); }
+  static const int64_t NOT_FOUND = -1;
+
+private:
+  /// @brief Measurement data, which is shared with serializer
+  MeasurementData _measurements;
+  // int64_t::max may cause integer overflow
+  static const int64_t _MAX = std::numeric_limits<int32_t>::max();
+  /// @brief Serializer
+  JSON _json;
+};
+
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_EXEC_TIME_H__
diff --git a/runtime/neurun/core/include/backend/IConfig.h b/runtime/neurun/core/include/backend/IConfig.h
new file mode 100644
index 000000000..855f31ef9
--- /dev/null
+++ b/runtime/neurun/core/include/backend/IConfig.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ICONFIG_H__
+#define __NEURUN_BACKEND_ICONFIG_H__
+
+#include "util/ITimer.h"
+#include <memory>
+#include <string>
+
+namespace neurun
+{
+namespace backend
+{
+
+struct IConfig
+{
+  virtual ~IConfig() = default;
+
+  virtual std::string id() = 0;
+  virtual bool initialize() = 0;
+  // Support permute kernel
+  virtual bool SupportPermutation() = 0;
+  // Support subtensor allocation
+  virtual bool SupportSubTensorAlloc() = 0;
+
+  // Timer is used for backend profiling. In case of default (nullptr) timer profiler won't work.
+  virtual std::unique_ptr<util::ITimer> timer() { return nullptr; }
+};
+
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ICONFIG_H__
diff --git a/runtime/neurun/core/include/backend/IConstantInitializer.h b/runtime/neurun/core/include/backend/IConstantInitializer.h
new file mode 100644
index 000000000..3cc770b29
--- /dev/null
+++ b/runtime/neurun/core/include/backend/IConstantInitializer.h
@@ -0,0 +1,288 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ICONSTANT_INITIALIZER_H__
+#define __NEURUN_BACKEND_ICONSTANT_INITIALIZER_H__
+
+#include <unordered_map>
+#include <functional>
+
+#include "ITensorBuilder.h"
+#include "ir/Layout.h"
+#include "ir/Operand.h"
+#include "ir/Operands.h"
+#include "ir/OperationVisitor.h"
+#include "ir/OpSequence.h"
+#include "util/logging.h"
+#include "util/Utils.h"
+
+namespace
+{
+template <typename T>
+static void Init(const neurun::ir::Operand &model_obj, neurun::backend::operand::ITensor &obj,
+                 const bool copy,
+                 const neurun::ir::Layout frontend_layout = neurun::ir::Layout::UNKNOWN)
+{
+  const auto shape = model_obj.shape();
+  auto base = reinterpret_cast<const T *>(model_obj.data().base());
+
+  obj.access([&](::neurun::backend::operand::ITensor &tensor) {
+    switch (shape.rank())
+    {
+      case 0:
+      {
+        assert(model_obj.data().size() == sizeof(T));
+        const auto value = *reinterpret_cast<const T *>(base);
+        T *into = reinterpret_cast<T *>(tensor.buffer());
+        *into = value;
+        break;
+      }
+      case 1:
+      {
+        auto vec_size = shape.dim(0);
+        for (int32_t n = 0; n < vec_size; ++n)
+        {
+          const T *from = reinterpret_cast<const T *>(base) + n;
+          const auto value = *from;
+
+          T *into = reinterpret_cast<T *>(tensor.buffer()) + n;
+
+          *into = value;
+        }
+        break;
+      }
+      case 2:
+      {
+        const int32_t copy_len = shape.dim(1);
+
+        for (auto i = 0; i < shape.dim(0); ++i)
+        {
+          neurun::util::Coordinates coords{i, 0};
+          memcpy(tensor.buffer() + tensor.calcOffset(coords), base + i * copy_len,
+                 copy_len * sizeof(T));
+        }
+        break;
+      }
+      case 3:
+      {
+        const int32_t width = shape.dim(1);
+        const int32_t copy_len = shape.dim(2);
+
+        for (auto i = 0; i < shape.dim(0); ++i)
+        {
+          for (auto j = 0; j < shape.dim(1); ++j)
+          {
+            neurun::util::Coordinates coords{i, j, 0};
+            memcpy(tensor.buffer() + tensor.calcOffset(coords),
+                   base + i * width * copy_len + j * copy_len, copy_len * sizeof(T));
+          }
+        }
+        break;
+      }
+      case 4:
+      {
+        const int32_t height = shape.dim(1);
+        const int32_t width = shape.dim(2);
+        const int32_t copy_len = shape.dim(3);
+        for (auto i = 0; i < shape.dim(0); ++i)
+        {
+          for (auto j = 0; j < shape.dim(1); ++j)
+          {
+            for (auto k = 0; k < shape.dim(2); ++k)
+            {
+              if (copy)
+              {
+                neurun::util::Coordinates coords{i, j, k, 0};
+                memcpy(tensor.buffer() + tensor.calcOffset(coords),
+                       base + i * height * width * copy_len + j * width * copy_len + k * copy_len,
+                       copy_len * sizeof(T));
+              }
+              else
+              {
+                for (auto l = 0; l < shape.dim(3); ++l)
+                {
+                  const auto coords = neurun::util::convertCoordinates(
+                      {i, j, k, l}, frontend_layout, tensor.layout());
+                  T *into = reinterpret_cast<T *>(tensor.buffer() + tensor.calcOffset(coords));
+                  T value = *(base + i * height * width * copy_len + j * width * copy_len +
+                              k * copy_len + l);
+                  *into = value;
+                }
+              }
+            }
+          }
+        }
+        break;
+      }
+      default:
+        throw std::runtime_error{"Not yet supported"};
+    }
+  });
+}
+
+template <typename T>
+void copyInit(const neurun::ir::Operand &model_obj, neurun::backend::operand::ITensor &obj)
+{
+  Init<T>(model_obj, obj, true);
+}
+
+template <typename T>
+void permuteInit(const neurun::ir::Operand &model_obj, neurun::backend::operand::ITensor &obj,
+                 const neurun::ir::Layout frontend_layout)
+{
+  const bool copy = frontend_layout == obj.layout();
+  Init<T>(model_obj, obj, copy, frontend_layout);
+}
+
+} // namespace
+
+namespace neurun
+{
+namespace backend
+{
+
+class IConstantInitializer : ir::OperationVisitor
+{
+public:
+  virtual ~IConstantInitializer() = default;
+
+public:
+  void run()
+  {
+    assert(tensor_builder().get());
+    for (const auto &it : _init_map)
+    {
+      const auto &ind = it.first;
+      const auto &fn = it.second;
+
+      const auto &model_obj = operands().at(ind);
+      auto tensor_obj = tensor_builder()->tensorAt(ind);
+      fn(model_obj, *tensor_obj);
+      VERBOSE(FillOperandData) << "Fill data for operand " << ind.value() << std::endl;
+    }
+    _init_map.clear();
+  }
+
+public:
+  using Initializer = std::function<void(const ir::Operand &, backend::operand::ITensor &)>;
+
+  void generate(const ir::OpSequence &subg, const ir::Operands &operands)
+  {
+    _current_subg_layout = subg.getLayout();
+    subg.accept(*this);
+    for (const auto &e : subg.operations())
+    {
+      for (const auto &ind : e.node->getInputs())
+      {
+        const auto &obj = operands.at(ind);
+        if (obj.isConstant() && !exist(ind))
+        {
+          registerPermuteInitializer(ind, obj);
+        }
+      }
+    }
+  }
+
+protected:
+  using OperationVisitor::visit;
+
+protected:
+  virtual const ir::Operands &operands() const = 0;
+  virtual std::shared_ptr<ITensorBuilder> tensor_builder() const = 0;
+
+protected:
+  void registerCopyInitializer(const ir::OperandIndex &index, const ir::Operand &obj)
+  {
+    // For only CONSTANTS
+    // TODO Add to check if tensor has been allocated
+    if (!obj.isConstant())
+      return;
+
+    const auto type = obj.typeInfo().type();
+    using ir::DataType;
+
+    switch (type)
+    {
+      case DataType::FLOAT32:
+        _init_map[index] = copyInit<float>;
+        break;
+      case DataType::INT32:
+        _init_map[index] = copyInit<int32_t>;
+        break;
+      case DataType::UINT32:
+        _init_map[index] = copyInit<uint32_t>;
+        break;
+      case DataType::BOOL8:
+      case DataType::QUANT8_ASYMM:
+        _init_map[index] = copyInit<uint8_t>;
+        break;
+      case DataType::QUANT8_SYMM:
+        _init_map[index] = copyInit<int8_t>;
+        break;
+      default:
+        throw std::runtime_error("Not supported, yet");
+        break;
+    }
+  }
+
+protected:
+  void registerPermuteInitializer(const ir::OperandIndex &index, const ir::Operand &obj)
+  {
+    // For only CONSTANTS
+    // TODO Add to check if tensor has been allocated
+    if (!obj.isConstant())
+      return;
+
+    const auto type = obj.typeInfo().type();
+    using ir::DataType;
+    using namespace std::placeholders;
+
+    switch (type)
+    {
+      case DataType::FLOAT32:
+        _init_map[index] = std::bind(permuteInit<float>, _1, _2, _current_subg_layout);
+        break;
+      case DataType::INT32:
+        _init_map[index] = std::bind(permuteInit<int32_t>, _1, _2, _current_subg_layout);
+        break;
+      case DataType::UINT32:
+        _init_map[index] = std::bind(permuteInit<uint32_t>, _1, _2, _current_subg_layout);
+        break;
+      case DataType::BOOL8:
+      case DataType::QUANT8_ASYMM:
+        _init_map[index] = std::bind(permuteInit<uint8_t>, _1, _2, _current_subg_layout);
+        break;
+      case DataType::QUANT8_SYMM:
+        _init_map[index] = std::bind(permuteInit<int8_t>, _1, _2, _current_subg_layout);
+        break;
+      default:
+        throw std::runtime_error("Not supported, yet");
+        break;
+    }
+  }
+
+private:
+  bool exist(const ir::OperandIndex &ind) { return _init_map.find(ind) != _init_map.end(); }
+
+protected:
+  std::unordered_map<ir::OperandIndex, Initializer> _init_map;
+  ir::Layout _current_subg_layout;
+};
+
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ICONSTANT_INITIALIZER_H__
diff --git a/runtime/neurun/core/include/backend/IKernelGenerator.h b/runtime/neurun/core/include/backend/IKernelGenerator.h
new file mode 100644
index 000000000..4540e81d2
--- /dev/null
+++ b/runtime/neurun/core/include/backend/IKernelGenerator.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_IKERNEL_GENERATOR_H__
+#define __NEURUN_BACKEND_IKERNEL_GENERATOR_H__
+
+#include <memory>
+#include <functional>
+
+#include "ITensorBuilder.h"
+#include "compiler/IExecutionBuilder.h"
+#include "ir/OperationVisitor.h"
+#include "ir/OpSequence.h"
+#include "cpp14/memory.h"
+
+namespace neurun
+{
+namespace backend
+{
+
+class IKernelGenerator : public ir::OperationVisitor
+{
+public:
+  virtual ~IKernelGenerator() = default;
+
+  void generate(const ir::OpSequence &subg, neurun::compiler::IExecutionBuilder *executionBuilder)
+  {
+    _execution_builder = executionBuilder;
+    subg.accept(*this);
+  }
+
+protected:
+  using OperationVisitor::visit;
+
+#define OP(InternalName)                                                                \
+  void visit(const ir::operation::InternalName &) override                              \
+  {                                                                                     \
+    throw std::runtime_error("KernelGenerator: NYI for operation '" #InternalName "'"); \
+  }
+#include "ir/Operations.lst"
+#undef OP
+
+protected:
+  neurun::compiler::IExecutionBuilder *_execution_builder;
+};
+
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_IKERNEL_GENERATOR_H__
diff --git a/runtime/neurun/core/include/backend/IMemoryManager.h b/runtime/neurun/core/include/backend/IMemoryManager.h
new file mode 100644
index 000000000..b06bab872
--- /dev/null
+++ b/runtime/neurun/core/include/backend/IMemoryManager.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_IMEMORY_MANAGER_H__
+#define __NEURUN_BACKEND_IMEMORY_MANAGER_H__
+
+namespace neurun
+{
+namespace backend
+{
+
+struct IMemoryManager
+{
+  virtual ~IMemoryManager() = default;
+
+  virtual void allocate(void) = 0;
+  virtual void deallocate(void) = 0;
+};
+
+} // namespace backend
+} // namespace neurun
+
+#include <unordered_set>
+#include <memory>
+
+namespace neurun
+{
+namespace backend
+{
+
+using MemoryManagerSet = std::unordered_set<std::unique_ptr<backend::IMemoryManager>>;
+
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_IMEMORY_MANAGER_H__
diff --git a/runtime/neurun/core/include/backend/IShapeFixer.h b/runtime/neurun/core/include/backend/IShapeFixer.h
new file mode 100644
index 000000000..8168e2a11
--- /dev/null
+++ b/runtime/neurun/core/include/backend/IShapeFixer.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ISHAPE_FIXER_H__
+#define __NEURUN_BACKEND_ISHAPE_FIXER_H__
+
+#include <memory>
+#include <functional>
+
+#include "ir/LowerInfoMap.h"
+#include "ITensorBuilder.h"
+#include "ir/OperationVisitor.h"
+#include "ir/OpSequence.h"
+#include "cpp14/memory.h"
+
+namespace neurun
+{
+namespace backend
+{
+
+class IShapeFixer : public ir::OperationVisitor
+{
+public:
+  virtual ~IShapeFixer() = default;
+
+protected:
+#define OP(InternalName)                                                           \
+  void visit(const ir::operation::InternalName &) override                         \
+  {                                                                                \
+    throw std::runtime_error("ShapeFixer: NYI for operation '" #InternalName "'"); \
+  }
+#include "ir/Operations.lst"
+#undef OP
+
+public:
+  void fix(const ir::OpSequence &op_seq) { op_seq.accept(*this); };
+};
+
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ISHAPE_FIXER_H__
diff --git a/runtime/neurun/core/include/backend/ITensorBuilder.h b/runtime/neurun/core/include/backend/ITensorBuilder.h
new file mode 100644
index 000000000..5eb4ab2d8
--- /dev/null
+++ b/runtime/neurun/core/include/backend/ITensorBuilder.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ITENSOR_BUILDER_H__
+#define __NEURUN_BACKEND_ITENSOR_BUILDER_H__
+
+#include <map>
+
+#include "ir/Index.h"
+#include "ir/OperandInfo.h"
+#include "ir/Operation.h"
+#include "ir/Layout.h"
+#include "operand/ITensor.h"
+#include "compiler/SubTensorInfo.h"
+#include "ITensorManager.h"
+
+namespace neurun
+{
+namespace backend
+{
+
+struct ITensorBuilder
+{
+  using IterateFunction = std::function<void(const ir::OperandIndex &)>;
+
+  virtual ~ITensorBuilder(void) = default;
+
+  // TODO Merge registerTensorInfo and registerSubTensorInfo using abstraction by internal class
+  /**
+   * @brief Register tensor information to allocate on backend
+   */
+  virtual void registerTensorInfo(const ir::OperandIndex &, const ir::OperandInfo &,
+                                  ir::Layout backend_layout, bool as_const) = 0;
+  /**
+   * @brief     Register subtensor information to allocate on backend
+   */
+  virtual void registerSubTensorInfo(const ir::OperandIndex &, const compiler::SubTensorInfo &) = 0;
+
+  virtual void notifyFirstUse(const ir::OperandIndex &) = 0;
+  virtual void notifyLastUse(const ir::OperandIndex &) = 0;
+
+  virtual bool isRegistered(const ir::OperandIndex &) const = 0;
+
+  virtual void prepare(void) = 0;
+  virtual void allocateConsts() = 0;
+  virtual void allocateNonconsts() = 0;
+  virtual void postFunctionPrepare() = 0;
+  virtual void finalize() = 0;
+
+  virtual std::shared_ptr<::neurun::backend::operand::ITensor>
+  tensorAt(const ir::OperandIndex &ind) = 0;
+  virtual void iterate(const IterateFunction &fn) = 0;
+
+  virtual void preVisit(const ir::Operation &) = 0;
+  virtual void postVisit(const ir::Operation &) = 0;
+
+  virtual std::unique_ptr<ITensorManager> releaseTensorManager(void) = 0;
+};
+
+} // namespace backend
+} // namespace neurun
+
+#include <unordered_set>
+#include <memory>
+
+namespace neurun
+{
+namespace backend
+{
+
+using TensorBuilderSet = std::unordered_set<std::shared_ptr<backend::ITensorBuilder>>;
+
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ITENSOR_BUILDER_H__
diff --git a/runtime/neurun/core/include/backend/ITensorManager.h b/runtime/neurun/core/include/backend/ITensorManager.h
new file mode 100644
index 000000000..74506ef59
--- /dev/null
+++ b/runtime/neurun/core/include/backend/ITensorManager.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ITENSOR_MANAGER_H__
+#define __NEURUN_BACKEND_ITENSOR_MANAGER_H__
+
+namespace neurun
+{
+namespace backend
+{
+
+// NOTE This name ITensorManager has been discussed whether or not the name is proper.
+// Anyone can argue with any better name.
+/**
+ * @brief Interface as an abstract tensor manager which has MemoryManager
+ */
+struct ITensorManager
+{
+  virtual ~ITensorManager() = default;
+
+  virtual void allocateConsts(void) = 0;
+  virtual void allocateNonconsts(void) = 0;
+  virtual void deallocateConsts(void) = 0;
+  virtual void deallocateNonconsts(void) = 0;
+};
+
+} // namespace backend
+} // namespace neurun
+
+#include <unordered_set>
+#include <memory>
+
+namespace neurun
+{
+namespace backend
+{
+
+using TensorManagerSet = std::unordered_set<std::unique_ptr<backend::ITensorManager>>;
+
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ITENSOR_MANAGER_H__
diff --git a/runtime/neurun/core/include/backend/ITensorRegister.h b/runtime/neurun/core/include/backend/ITensorRegister.h
new file mode 100644
index 000000000..9e554ab77
--- /dev/null
+++ b/runtime/neurun/core/include/backend/ITensorRegister.h
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ITENSOR_REGISTER_H__
+#define __NEURUN_BACKEND_ITENSOR_REGISTER_H__
+
+#include "compiler/SubTensorInfo.h"
+#include "ir/LowerInfoMap.h"
+#include "ir/operand/ParentInfo.h"
+#include "ITensorBuilder.h"
+#include "ir/Layout.h"
+#include "ir/OperandIndexSequence.h"
+#include "ir/OperandInfo.h"
+#include "ir/Operands.h"
+#include "ir/OperationVisitor.h"
+
+namespace
+{
+
+neurun::ir::Shape permuteTensorShape(const neurun::ir::Shape &shape,
+                                     neurun::ir::Layout frontend_layout,
+                                     neurun::ir::Layout backend_layout)
+{
+  assert(shape.rank() <= 4);
+  neurun::ir::Shape backend_shape{shape};
+  if (shape.rank() == 4 && frontend_layout == neurun::ir::Layout::NHWC &&
+      backend_layout == neurun::ir::Layout::NCHW)
+  {
+    backend_shape.dim(1) = shape.dim(3);
+    backend_shape.dim(2) = shape.dim(1);
+    backend_shape.dim(3) = shape.dim(2);
+  }
+  else if (shape.rank() == 4 && frontend_layout == neurun::ir::Layout::NCHW &&
+           backend_layout == neurun::ir::Layout::NHWC)
+  {
+    backend_shape.dim(1) = shape.dim(2);
+    backend_shape.dim(2) = shape.dim(3);
+    backend_shape.dim(3) = shape.dim(1);
+  }
+  return backend_shape;
+}
+} // namespace
+
+namespace neurun
+{
+namespace backend
+{
+
+class ITensorRegister : public ir::OperationVisitor
+{
+public:
+  virtual ~ITensorRegister() = default;
+
+public:
+  void registerTensors(const ir::OpSequence &subg, const ir::LowerInfoMap *lower_info_map)
+  {
+    _current_subg_layout = subg.getLayout();
+    _lower_info_map = lower_info_map;
+    assert(_lower_info_map != nullptr);
+    assert(tensor_builder().get() != nullptr);
+    subg.accept(*this);
+  }
+
+protected:
+  virtual const ir::Operands &operands() const = 0;
+  virtual std::shared_ptr<ITensorBuilder> tensor_builder() const = 0;
+  virtual bool supportSubTensor() const = 0;
+
+protected:
+#define OP(InternalName)                                       \
+  void visit(const ir::operation::InternalName &node) override \
+  {                                                            \
+    ir::OperandIndexSequence indices{node.getInputs()};        \
+    indices.append(node.getOutputs());                         \
+    for (const auto &index : indices)                          \
+    {                                                          \
+      defaultRegisterTensorInfo(index);                        \
+    }                                                          \
+  }
+#include "ir/Operations.lst"
+#undef OP
+
+protected:
+  void defaultRegisterTensorInfo(const ir::OperandIndex &index) const
+  {
+    if (tensor_builder()->isRegistered(index))
+    {
+      return;
+    }
+
+    const auto &obj = operands().at(index);
+    const auto frontend_layout = frontendLayout();
+    const auto backend_layout = backendLayout(index);
+    if (supportSubTensor() && obj.parent_info() != nullptr)
+    {
+      tensor_builder()->registerSubTensorInfo(
+          index, generateSubTensorInfo(obj, frontend_layout, backend_layout));
+    }
+    else
+    {
+      ir::OperandInfo backend_info{permuteTensorShape(obj.shape(), frontend_layout, backend_layout),
+                                   obj.typeInfo()};
+      tensor_builder()->registerTensorInfo(index, backend_info, backend_layout, obj.isConstant());
+    }
+  }
+
+protected:
+  ir::Layout frontendLayout() const { return _current_subg_layout; }
+  ir::Layout backendLayout(const ir::OperandIndex &index) const
+  {
+    assert(_lower_info_map != nullptr);
+    const auto lower_info = _lower_info_map->operand.at(index).get();
+    return lower_info->def_factors().getOnlyElement().layout();
+  }
+
+private:
+  compiler::SubTensorInfo generateSubTensorInfo(const ir::Operand &obj, ir::Layout frontend_layout,
+                                                ir::Layout backend_layout) const
+  {
+    assert(obj.shape().rank() <= 4);
+    const auto parent_index = obj.parent_info()->parent();
+    auto shape = obj.shape();
+    auto offset = obj.parent_info()->offset();
+    if (operands().at(parent_index).shape().rank() == 4 && frontend_layout == ir::Layout::NHWC &&
+        backend_layout == ir::Layout::NCHW)
+    {
+      shape.extendRank(4);
+      offset = {offset[0], offset[3], offset[1], offset[2]};
+    }
+    else if (operands().at(parent_index).shape().rank() == 4 &&
+             frontend_layout == ir::Layout::NHWC && backend_layout == ir::Layout::NCHW)
+    {
+      shape.extendRank(4);
+      offset = {offset[0], offset[2], offset[3], offset[1]};
+    }
+    ir::Operand subtensor_obj{permuteTensorShape(shape, frontend_layout, backend_layout),
+                              obj.typeInfo()};
+    subtensor_obj.parent_info(
+        nnfw::cpp14::make_unique<ir::operand::ParentInfo>(parent_index, offset));
+    return compiler::SubTensorInfo{subtensor_obj};
+  }
+
+private:
+  ir::Layout _current_subg_layout;
+  const ir::LowerInfoMap *_lower_info_map{nullptr};
+};
+
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ITENSOR_REGISTER_H__
diff --git a/runtime/neurun/core/include/backend/JSONExecTime.h b/runtime/neurun/core/include/backend/JSONExecTime.h
new file mode 100644
index 000000000..84505e10f
--- /dev/null
+++ b/runtime/neurun/core/include/backend/JSONExecTime.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_JSON_EXEC_TIME_H__
+#define __NEURUN_BACKEND_JSON_EXEC_TIME_H__
+
+#include <fstream>
+#include <unordered_map>
+#include <map>
+#include <vector>
+#include "backend/Backend.h"
+#include "backend/IConfig.h"
+
+namespace neurun
+{
+namespace backend
+{
+
+/**
+ * @brief table, that contains execution time of an operation on some backend for different input
+ * sizes and transfer time from one backend to another for various input sizes (permutation time)
+ *
+ *               backend ->  op ->  quant->  size   --> time
+ * _measurements[Backend*]["string"][bool][uint32_t] = int64_t
+ */
+using MeasurementData = std::unordered_map<
+    const Backend *,
+    std::unordered_map<std::string, std::unordered_map<bool, std::map<uint32_t, int64_t>>>>;
+
+class JSON
+{
+public:
+  explicit JSON(const std::vector<const Backend *> &backends, MeasurementData &measurements)
+      : _measurement_file("exec_time.json"), _backends(), _measurements(measurements)
+  {
+    for (const auto b : backends)
+    {
+      _backends.emplace(b->config()->id(), b);
+    }
+    loadOperationsExecTime();
+  };
+  /**
+   * @brief Update _operations_exec_time_file with new data.
+   */
+  void uploadOperationsExecTime() const;
+
+private:
+  ///@brief file containing measurements
+  std::string _measurement_file;
+  std::unordered_map<std::string, const Backend *> _backends;
+  std::unordered_map<
+      const Backend *,
+      std::unordered_map<std::string, std::unordered_map<bool, std::map<uint32_t, int64_t>>>>
+      &_measurements;
+  /**
+   * @brief Helper function for inserting data to OperationExecTimes
+   *
+   * @param backend String name of backend
+   * @param operation String name of operation
+   * @param quant if input type quantized
+   * @param stream File stream
+   */
+  void readOperation(const std::string &backend, const std::string &operation, bool quant,
+                     std::ifstream &stream);
+
+  /**
+   * @brief Helper function for writing OperationExecTimes to stream
+   *
+   * @param operation_info Map of operations execution information
+   * @param stream File stream
+   */
+  void printOperation(const std::map<uint32_t, int64_t> &operation_info,
+                      std::ofstream &stream) const;
+  /**
+   * @brief Parse and load operations_exec_time from _operations_exec_time_file.
+   */
+  void loadOperationsExecTime();
+};
+
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_JSON_EXEC_TIME_H__
diff --git a/runtime/neurun/core/include/backend/operand/ITensor.h b/runtime/neurun/core/include/backend/operand/ITensor.h
new file mode 100644
index 000000000..c278b01a0
--- /dev/null
+++ b/runtime/neurun/core/include/backend/operand/ITensor.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_OPERAND_I_TENSOR_H__
+#define __NEURUN_BACKEND_OPERAND_I_TENSOR_H__
+
+#include <cstring>
+#include <cstdint>
+#include <functional>
+
+#include "ir/Layout.h"
+#include "util/Coordinates.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace operand
+{
+
+class ITensor
+{
+public:
+  virtual ~ITensor() = default;
+
+public:
+  virtual uint8_t *buffer() const = 0;
+  virtual size_t total_size() const = 0;
+  virtual size_t dimension(size_t index) const = 0;
+  virtual size_t num_dimensions() const = 0;
+  virtual size_t calcOffset(const neurun::util::Coordinates &coords) const = 0;
+  virtual ir::Layout layout() const = 0;
+  virtual bool has_padding() const = 0;
+  virtual void access(const std::function<void(ITensor &tensor)> &fn) = 0;
+};
+
+} // namespace operand
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_OPERAND_I_TENSOR_H__
diff --git a/runtime/neurun/core/include/compiler/Compiler.h b/runtime/neurun/core/include/compiler/Compiler.h
new file mode 100644
index 000000000..797fc77ad
--- /dev/null
+++ b/runtime/neurun/core/include/compiler/Compiler.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file  Compiler.h
+ * @brief This file contains Compiler class to define and run compilation phase
+ */
+
+#ifndef __NEURUN_COMPILER_COMPILE_H_
+#define __NEURUN_COMPILER_COMPILE_H_
+
+#include "ir/Graph.h"
+#include "exec/IExecutor.h"
+
+namespace neurun
+{
+
+namespace compiler
+{
+
+enum class State
+{
+  CREATED, // Before compilation
+  STARTED, // Compile is started
+  LOWERED, // Backend is decided
+  COMPILED // Success compilation
+};
+
+/**
+ * @brief Class to compile graph model
+ */
+class Compiler
+{
+public:
+  /**
+   * @brief     Construct a new Compiler object
+   * @param[in] model Graph model
+   */
+  Compiler(const std::shared_ptr<ir::Graph> &graph)
+      : _graph{graph}, _executor{nullptr}, _state{State::CREATED}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief   Run compilation. Compilation result will be saved in _plan
+   */
+  void compile(void);
+  /**
+   * @brief       Pass plan reference
+   * @param[out]  plan  Plan reference to return\n
+   *                    Set nullptr if compile is not run yet
+   */
+  void release(std::shared_ptr<exec::IExecutor> &executor) { executor = _executor; }
+
+  void state(State state) { _state = state; }
+  State state(void) const { return _state; }
+
+  /**
+   * @brief   Check if model can compile
+   * @return  @c true if model can compile, otherwise @c false
+   * @note    This method don't check model correctness,\n
+   *          so model verification should be done before calling this method
+   */
+  bool checkCompilable();
+
+private:
+  std::shared_ptr<ir::Graph> _graph;
+  std::shared_ptr<exec::IExecutor> _executor;
+  State _state;
+};
+
+} // namespace compiler
+
+} // namespace neurun
+
+#endif // __NEURUN_COMPILER_COMPILE_H_
diff --git a/runtime/neurun/core/include/compiler/IExecutionBuilder.h b/runtime/neurun/core/include/compiler/IExecutionBuilder.h
new file mode 100644
index 000000000..c5a06fec0
--- /dev/null
+++ b/runtime/neurun/core/include/compiler/IExecutionBuilder.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_COMPILER_I_EXECUTION_BUILDER_H__
+#define __NEURUN_COMPILER_I_EXECUTION_BUILDER_H__
+
+#include <memory>
+
+#include "exec/IFunction.h"
+
+namespace neurun
+{
+namespace compiler
+{
+
+struct IExecutionBuilder
+{
+  virtual ~IExecutionBuilder() = default;
+
+  virtual void append(std::unique_ptr<::neurun::exec::IFunction> &&f) = 0;
+};
+
+} // namespace compiler
+} // namespace neurun
+
+#endif // __NEURUN_COMPILER_I_EXECUTION_BUILDER_H__
diff --git a/runtime/neurun/core/include/compiler/SubTensorInfo.h b/runtime/neurun/core/include/compiler/SubTensorInfo.h
new file mode 100644
index 000000000..18cab466b
--- /dev/null
+++ b/runtime/neurun/core/include/compiler/SubTensorInfo.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file  SubTensorInfo.h
+ * @brief This file contains SubTensorInfo to represent subsumption between tensors
+ *        for backend tensor allocation
+ */
+#ifndef __NEURUN_COMPILER_SUBTENSOR_INFO_H__
+#define __NEURUN_COMPILER_SUBTENSOR_INFO_H__
+
+#include "ir/Operand.h"
+
+namespace neurun
+{
+namespace compiler
+{
+
+/**
+ * @brief Class to represent information of subtensor
+ */
+class SubTensorInfo
+{
+public:
+  SubTensorInfo() = delete;
+
+  /**
+   * @brief     Construct a new SubTensorInfo object
+   * @param[in] obj SubTensor object
+   */
+  SubTensorInfo(const ir::Operand &obj)
+      : _parent{obj.parent_info()->parent()}, _shape{obj.shape()}, _type{obj.typeInfo()},
+        _offset{obj.parent_info()->offset()}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief   Return parent tensor index
+   * @return  Parent tensor index
+   */
+  const ir::OperandIndex parent(void) const { return _parent; }
+  /**
+   * @brief   Return tensor shape
+   * @return  Tensor shape
+   */
+  const ir::Shape &shape(void) const { return _shape; }
+  /**
+   * @brief   Return tensor type
+   * @return  Tensor type
+   */
+  const ir::TypeInfo &type(void) const { return _type; }
+  /**
+   * @brief   Return tensor's offset in parent tensor
+   * @return  Tensor offset
+   */
+  const neurun::util::Coordinates offset(void) const { return _offset; }
+
+private:
+  const ir::OperandIndex _parent;
+  const ir::Shape _shape;
+  const ir::TypeInfo _type;
+  const neurun::util::Coordinates _offset;
+};
+
+} // compiler
+} // neurun
+
+#endif // __NEURUN_COMPILER_SUBTENSOR_INFO_H__
diff --git a/runtime/neurun/core/include/exec/Execution.h b/runtime/neurun/core/include/exec/Execution.h
new file mode 100644
index 000000000..7304f8aab
--- /dev/null
+++ b/runtime/neurun/core/include/exec/Execution.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file  Execution.h
+ * @brief This file defines execution
+ */
+#ifndef __NEURUN_EXEC_EXECUTION_H__
+#define __NEURUN_EXEC_EXECUTION_H__
+
+#include "ir/Layout.h"
+#include "exec/IExecutor.h"
+#include "IODescription.h"
+
+#include <thread>
+
+namespace neurun
+{
+namespace exec
+{
+
+/**
+ * @brief Class to define execution instance to collect input/output information for inference
+ *        and prepare executor run (TODO)
+ */
+class Execution
+{
+
+public:
+  /**
+   * @brief     Construct a new Execution object
+   * @param[in] executor  Model executor
+   */
+  Execution(const std::shared_ptr<IExecutor> &executor);
+
+public:
+  /**
+   * @brief   Returns graph object
+   * @return  Graph object
+   */
+  const ir::Graph &graph() const { return _executor->graph(); }
+  /**
+   * @brief     Set input data's information
+   * @param[in] index   Input index
+   * @param[in] buffer  Input data's buffer pointer
+   * @param[in] length  Input data's length
+   * @param[in] layout  Input data's data format
+   */
+  void setInput(const ir::IOIndex &index, const void *buffer, size_t length,
+                ir::Layout layout = ir::Layout::NHWC);
+  /**
+   * @brief     Set input data's information, especially to specify unknown dimensions on model
+   * build time.
+   * @param[in] index   Input index
+   * @param[in] type    Input data's type info
+   * @param[in] shape   Input data's shape
+   * @param[in] buffer  Input data's buffer pointer
+   * @param[in] length  Input data's length
+   * @param[in] layout  Input data's data format
+   */
+  void setInput(const ir::IOIndex &index, const ir::TypeInfo &type, const ir::Shape &shape,
+                const void *buffer, size_t length, ir::Layout layout = ir::Layout::NHWC);
+  /**
+   * @brief     Set output data's information
+   * @param[in] index   Output index
+   * @param[in] buffer  Output data's buffer pointer
+   * @param[in] length  Output data's length
+   * @param[in] layout  Output data's data format
+   */
+  void setOutput(const ir::IOIndex &index, void *buffer, size_t length,
+                 ir::Layout layout = ir::Layout::NHWC);
+  /**
+   * @brief     Set output data's information, especially to specify unknown dimensions on model
+   * build time.
+   * @param[in] index   Output index
+   * @param[in] type    Output data's type info
+   * @param[in] shape   Output data's shape
+   * @param[in] buffer  Output data's buffer pointer
+   * @param[in] length  Output data's length
+   * @param[in] layout  Output data's data format
+   */
+  void setOutput(const ir::IOIndex &index, const ir::TypeInfo &type, const ir::Shape &shape,
+                 void *buffer, size_t length, ir::Layout layout = ir::Layout::NHWC);
+  /**
+   * @brief     Set input data's data format
+   * @param[in] index   Input index
+   * @param[in] layout  Input data's data format
+   */
+  void setInputLayout(const ir::IOIndex &index, ir::Layout layout);
+  /**
+   * @brief     Set output data's data format
+   * @param[in] index   Output index
+   * @param[in] layout  Output data's data format
+   */
+  void setOutputLayout(const ir::IOIndex &index, ir::Layout layout);
+  /**
+   * @brief  Execution
+   * @note   It should be called after setting input and output buffer
+   */
+  void execute();
+
+  /**
+   * @brief Start asynchronous execution
+   * @note  It returns after execution thread is started
+   *        It should be called after setting input and output buffer
+   */
+  void startExecute(void);
+
+  /**
+   * @brief Return when execution is finished
+   * @note  It waits until execution is finished
+   */
+  void waitFinish(void);
+
+  /**
+   * @brief   Check execution is finished
+   * @return  @c true if execution is finished, otherwise @c false
+   */
+  bool isFinished(void) const;
+
+private:
+  const std::shared_ptr<IExecutor> _executor;
+  IODescription _io_desc;
+  std::unique_ptr<std::thread> _exec_thread;
+  bool finished{false};
+};
+
+} // namespace exec
+} // namespace neurun
+
+#endif // __NEURUN_EXEC_EXECUTION_H__
diff --git a/runtime/neurun/core/include/exec/ExecutionObservers.h b/runtime/neurun/core/include/exec/ExecutionObservers.h
new file mode 100644
index 000000000..ca658c706
--- /dev/null
+++ b/runtime/neurun/core/include/exec/ExecutionObservers.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_EXEC_OBSREVERS_H__
+#define __NEURUN_EXEC_OBSREVERS_H__
+
+#include "exec/IFunction.h"
+#include "ir/OpSequence.h"
+#include "backend/ExecTime.h"
+#include "util/ITimer.h"
+#include "IExecutor.h"
+#include "misc/EventCollector.h"
+#include "misc/EventRecorder.h"
+
+namespace neurun
+{
+namespace exec
+{
+class IExecutionObserver
+{
+public:
+  /// @brief Invoked just before model (not individual operation) execution begins
+  virtual void handleBegin(IExecutor *) { return; }
+
+  virtual void handleBegin(IExecutor *, const ir::OpSequence *, const backend::Backend *) = 0;
+  virtual void handleEnd(IExecutor *, const ir::OpSequence *, const backend::Backend *) = 0;
+
+  /// @brief Invoked just after model (not individual operation) execution ends
+  virtual void handleEnd(IExecutor *) { return; }
+
+  virtual ~IExecutionObserver() = default;
+};
+
+class ProfileObserver : public IExecutionObserver
+{
+public:
+  explicit ProfileObserver(std::shared_ptr<backend::ExecTime> et) : _et(std::move(et)) {}
+  void handleBegin(IExecutor *, const ir::OpSequence *, const backend::Backend *) override;
+  void handleEnd(IExecutor *, const ir::OpSequence *, const backend::Backend *) override;
+
+  void handleEnd(IExecutor *) override { _et->uploadOperationsExecTime(); }
+
+private:
+  std::unique_ptr<util::ITimer> _timer;
+  std::shared_ptr<backend::ExecTime> _et;
+};
+
+class ChromeTracingObserver : public IExecutionObserver
+{
+public:
+  ChromeTracingObserver(const std::string &filepath);
+  ~ChromeTracingObserver();
+  void handleBegin(IExecutor *) override;
+  void handleBegin(IExecutor *, const ir::OpSequence *, const backend::Backend *) override;
+  void handleEnd(IExecutor *, const ir::OpSequence *, const backend::Backend *) override;
+  void handleEnd(IExecutor *) override;
+
+private:
+  static std::string subgraphTag(const ir::OpSequence *op_seq);
+
+private:
+  std::ofstream _ofs;
+  EventRecorder _recorder;
+  EventCollector _collector;
+};
+
+} // namespace exec
+} // namespace neurun
+
+#endif // __NEURUN_EXEC_OBSREVERS_H__
diff --git a/runtime/neurun/core/include/exec/IExecutor.h b/runtime/neurun/core/include/exec/IExecutor.h
new file mode 100644
index 000000000..de3291388
--- /dev/null
+++ b/runtime/neurun/core/include/exec/IExecutor.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file  IExecutor.h
+ * @brief This file defines interface of Executor
+ */
+#ifndef __NEURUN_EXEC_I_EXECUTOR_H_
+#define __NEURUN_EXEC_I_EXECUTOR_H_
+
+#include "ir/Graph.h"
+#include "IFunction.h"
+#include "IODescription.h"
+#include "ir/OperationIndexMap.h"
+
+namespace neurun
+{
+namespace exec
+{
+class IExecutionObserver;
+/**
+ * @brief Struct to define interface of Executor
+ */
+struct IExecutor
+{
+  /**
+   * @brief Construct a new IExecutor object
+   */
+  IExecutor() = default;
+  /**
+   * @brief Destroy the IExecutor object
+   */
+  virtual ~IExecutor() = default;
+
+  /**
+   * @brief Returns graph object
+   *
+   * @return Graph object
+   */
+  virtual const ir::Graph &graph() = 0;
+
+  /**
+   * @brief     Set an ordering on operations
+   * @param[in] ranks   The table encoding the ordering
+   */
+  virtual void setIndexedRanks(std::shared_ptr<ir::OperationIndexMap<int64_t>>) = 0;
+
+  /**
+   * @brief     Start execution
+   * @param[in] desc Input and output description
+   * @note      This method should be thread-safe
+   */
+  virtual void execute(const IODescription &desc) = 0;
+};
+
+} // namespace exec
+} // namespace neurun
+
+#endif // __NEURUN_EXEC_I_EXECUTOR_H_
diff --git a/runtime/neurun/core/include/exec/IFunction.h b/runtime/neurun/core/include/exec/IFunction.h
new file mode 100644
index 000000000..5cc29ea75
--- /dev/null
+++ b/runtime/neurun/core/include/exec/IFunction.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_EXEC_I_FUNCTION_H__
+#define __NEURUN_EXEC_I_FUNCTION_H__
+
+namespace neurun
+{
+namespace exec
+{
+
+class IFunction
+{
+public:
+  virtual ~IFunction() = default;
+  virtual void run() = 0;
+  virtual void runSync() = 0;
+  virtual void prepare() {}
+};
+
+} // namespace exec
+} // namespace neurun
+
+#endif // __NEURUN_EXEC_I_FUNCTION_H__
diff --git a/runtime/neurun/core/include/exec/IODescription.h b/runtime/neurun/core/include/exec/IODescription.h
new file mode 100644
index 000000000..bdcc78176
--- /dev/null
+++ b/runtime/neurun/core/include/exec/IODescription.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_EXEC_IO_DESCRIPTION_H__
+#define __NEURUN_EXEC_IO_DESCRIPTION_H__
+
+#include <vector>
+
+#include "ir/OperandInfo.h"
+
+namespace neurun
+{
+namespace exec
+{
+
+struct InputDesc
+{
+  const ir::OperandInfo info;
+  const void *buffer;
+  const size_t size;
+  const ir::Layout layout;
+
+  InputDesc(void) = delete;
+  InputDesc(const ir::OperandInfo &info, const void *buffer, const size_t size, ir::Layout layout)
+      : info(info), buffer(buffer), size(size), layout(layout)
+  {
+  }
+};
+
+struct OutputDesc
+{
+  const ir::OperandInfo info;
+  void *buffer;
+  const size_t size;
+  const ir::Layout layout;
+
+  OutputDesc(void) = delete;
+  OutputDesc(const ir::OperandInfo &info, void *buffer, const size_t size, ir::Layout layout)
+      : info(info), buffer(buffer), size(size), layout(layout)
+  {
+  }
+};
+
+struct IODescription
+{
+  std::vector<std::unique_ptr<InputDesc>> inputs;
+  std::vector<std::unique_ptr<OutputDesc>> outputs;
+};
+
+} // namespace exec
+} // namespace neurun
+
+#endif // __NEURUN_EXEC_IO_DESCRIPTION_H__
diff --git a/runtime/neurun/core/include/exec/NopFunction.h b/runtime/neurun/core/include/exec/NopFunction.h
new file mode 100644
index 000000000..5cbd7e5ce
--- /dev/null
+++ b/runtime/neurun/core/include/exec/NopFunction.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file  NopFunction.h
+ * @brief This file defines NopFunction
+ */
+#ifndef __NEURUN_EXEC_NOP_FUNCTION_H_
+#define __NEURUN_EXEC_NOP_FUNCTION_H_
+
+#include "IFunction.h"
+
+namespace neurun
+{
+namespace exec
+{
+
+/**
+ * @brief A derivative of IFunction tha does nothing
+ *
+ */
+class NopFunction : public IFunction
+{
+public:
+  NopFunction() = default;
+  void run() override
+  {
+    // DO NOTHING
+  }
+  void runSync() override
+  {
+    // this abstract method is used just for profiling and called for
+    // backend::acl_common::AclFunction
+    run();
+  }
+};
+
+} // namespace exec
+} // namespace neurun
+
+#endif // __NEURUN_EXEC_NOP_FUNCTION_H_
diff --git a/runtime/neurun/core/include/ir/BackendSet.h b/runtime/neurun/core/include/ir/BackendSet.h
new file mode 100644
index 000000000..4979286df
--- /dev/null
+++ b/runtime/neurun/core/include/ir/BackendSet.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_BACKEND_SET_H__
+#define __NEURUN_IR_BACKEND_SET_H__
+
+#include "util/Set.h"
+
+namespace neurun
+{
+namespace backend
+{
+class Backend;
+} // namespace backend
+} // namespace neurun
+
+namespace neurun
+{
+namespace ir
+{
+
+using BackendSet = util::Set<const backend::Backend *>;
+
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_BACKEND_SET_H__
diff --git a/runtime/neurun/core/include/ir/Data.h b/runtime/neurun/core/include/ir/Data.h
new file mode 100644
index 000000000..a0a489553
--- /dev/null
+++ b/runtime/neurun/core/include/ir/Data.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_DATA_H__
+#define __NEURUN_IR_DATA_H__
+
+#include <algorithm>
+
+namespace neurun
+{
+namespace ir
+{
+
+struct Data
+{
+  virtual ~Data() = default;
+
+  virtual size_t size(void) const = 0;
+  virtual const uint8_t *base(void) const = 0;
+};
+
+class CachedData final : public Data
+{
+public:
+  CachedData(const uint8_t *base, size_t size) : _base{new uint8_t[size]}, _size{size}
+  {
+    std::copy(base, base + size, _base);
+  }
+
+public:
+  ~CachedData() { delete[] _base; }
+
+public:
+  size_t size(void) const override { return _size; }
+  const uint8_t *base(void) const override { return _base; }
+
+private:
+  uint8_t *_base;
+  size_t _size;
+};
+
+class ExternalData final : public Data
+{
+public:
+  ExternalData(const uint8_t *base, size_t size) : _base{base}, _size{size}
+  {
+    // DO NOTHING
+  }
+
+public:
+  size_t size(void) const override { return _size; }
+  const uint8_t *base(void) const override { return _base; }
+
+private:
+  const uint8_t *_base;
+  const size_t _size;
+};
+
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_DATA_H__
diff --git a/runtime/neurun/core/include/ir/DataType.h b/runtime/neurun/core/include/ir/DataType.h
new file mode 100644
index 000000000..6eca6eb27
--- /dev/null
+++ b/runtime/neurun/core/include/ir/DataType.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_DATATYPE_H__
+#define __NEURUN_IR_DATATYPE_H__
+
+#include <stdexcept>
+
+namespace neurun
+{
+namespace ir
+{
+
+enum class DataType
+{
+  FLOAT32 = 0,
+  INT32 = 1,
+  UINT32 = 2,
+  QUANT8_ASYMM = 3,
+  BOOL8 = 4,
+  UINT8 = 5,
+  QUANT8_SYMM = 6,
+};
+
+inline size_t sizeOfDataType(DataType data_type)
+{
+  switch (data_type)
+  {
+    case DataType::FLOAT32:
+      return sizeof(float);
+    case DataType::INT32:
+      return sizeof(int32_t);
+    case DataType::UINT32:
+      return sizeof(uint32_t);
+    case DataType::BOOL8:
+    case DataType::QUANT8_ASYMM:
+    case DataType::UINT8:
+      return sizeof(uint8_t);
+    case DataType::QUANT8_SYMM:
+      return sizeof(int8_t);
+    default:
+      throw std::runtime_error{"Unsupported type size"};
+  }
+}
+
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_DATATYPE_H__
diff --git a/runtime/neurun/core/include/ir/Graph.h b/runtime/neurun/core/include/ir/Graph.h
new file mode 100644
index 000000000..5105c3a42
--- /dev/null
+++ b/runtime/neurun/core/include/ir/Graph.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_GRAPH_H__
+#define __NEURUN_IR_GRAPH_H__
+
+#include <functional>
+
+#include "ir/Operands.h"
+#include "ir/Operations.h"
+#include "ir/LowerInfoMap.h"
+#include "ir/OpSequence.h"
+#include "ir/Subgraphs.h"
+
+namespace neurun
+{
+namespace compiler
+{
+class BackendResolver;
+} // namespace compiler
+} // namespace neurun
+
+namespace neurun
+{
+namespace backend
+{
+namespace custom
+{
+class IKernelBuilder;
+} // namespace custom
+} // namespace backend
+} // namespace neurun
+
+namespace neurun
+{
+namespace ir
+{
+
+class Graph
+{
+private:
+  enum class Phase
+  {
+    BUILDING,
+    MODEL
+  };
+
+public:
+  Graph(void);
+  ~Graph(void);
+
+  // Graph Building
+public:
+  OperandIndex addOperand(const Shape &shape, const TypeInfo &type);
+  OperationIndex addOperation(std::unique_ptr<Operation> &&node);
+  void setOperandValue(const OperandIndex &ind, std::unique_ptr<Data> &&data);
+  void addInput(const OperandIndex &ind);
+  void addOutput(const OperandIndex &ind);
+  void finishBuilding(void);
+  void lower(void);
+  void removeOperand(const OperandIndex &ind) { _operands.remove(ind); }
+  bool isBuildingPhase(void) const { return _phase == Phase::BUILDING; }
+
+private:
+  void initializeUseDef();
+
+  // Custom operations support
+public:
+  void
+  bindKernelBuilder(const std::shared_ptr<neurun::backend::custom::IKernelBuilder> &kernel_builder)
+  {
+    _kernel_builder = kernel_builder;
+  }
+
+  const std::shared_ptr<backend::custom::IKernelBuilder> &getKernelBuilder() const
+  {
+    return _kernel_builder;
+  }
+
+private:
+  std::shared_ptr<backend::custom::IKernelBuilder> _kernel_builder;
+
+  // Accessors
+public:
+  const OperandIndexSequence &getInputs() const { return _inputs; }
+  OperandIndexSequence &getInputs() { return _inputs; }
+  const OperandIndexSequence &getOutputs() const { return _outputs; }
+  OperandIndexSequence &getOutputs() { return _outputs; }
+  const Operands &operands() const { return _operands; }
+  Operands &operands() { return _operands; } // TODO Remove this non-const accessor
+  const Operations &operations() const { return _operations; }
+  Operations &operations() { return _operations; }
+  const compiler::BackendResolver *backend_resolver() const { return _backend_resolver.get(); }
+
+private:
+  Phase _phase{Phase::BUILDING};
+  Operations _operations;
+  Operands _operands;
+  OperandIndexSequence _inputs;
+  OperandIndexSequence _outputs;
+
+  // For LOWERED phase
+public:
+  const LowerInfoMap *getLowerInfo() const { return _lower_info_map.get(); }
+  const operation::LowerInfo *getLowerInfo(const SubgraphIndex &subg_index) const;
+  void setLowerInfo(const SubgraphIndex &subg_index,
+                    std::unique_ptr<operation::LowerInfo> &&lower_info);
+  void removeLowerInfo(const SubgraphIndex &subg_index);
+  const operand::LowerInfo *getLowerInfo(const OperandIndex &index) const;
+  operand::LowerInfo *getLowerInfo(const OperandIndex &index);
+  void setLowerInfo(const OperandIndex &index, std::unique_ptr<operand::LowerInfo> &&lower_info);
+  void removeLowerInfo(const OperandIndex &index);
+  Subgraphs &subgraphs()
+  {
+    assert(_op_seqs);
+    return *_op_seqs;
+  }
+  const Subgraphs *subgraphs() const { return _op_seqs.get(); }
+  void setBackendResolver(std::unique_ptr<compiler::BackendResolver> &&br);
+
+private:
+  void makeSubgraphs(OperandIndexMap<std::unique_ptr<operand::LowerInfo>> &operands_lower_info);
+  void
+  manipulateLowerInfo(OperandIndexMap<std::unique_ptr<operand::LowerInfo>> &operands_lower_info);
+  void dumpLowerInfo();
+  bool mergeable(const SubgraphIndex &subg_index, const OperationIndex &node_index, Layout layout);
+  SubgraphIndex appendFreshSingleOpSubgraph(const OperationIndex &node_index, const Operation &node,
+                                            Layout layout);
+
+private:
+  std::unique_ptr<compiler::BackendResolver> _backend_resolver;
+  std::unique_ptr<LowerInfoMap> _lower_info_map;
+  // Pass(for Perm) can accept only graph so that Graph has Subgraphs as a member
+  std::unique_ptr<Subgraphs> _op_seqs;
+};
+
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_GRAPH_H__
diff --git a/runtime/neurun/core/include/ir/Index.h b/runtime/neurun/core/include/ir/Index.h
new file mode 100644
index 000000000..aebc64dcd
--- /dev/null
+++ b/runtime/neurun/core/include/ir/Index.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERAND_INDEX_H__
+#define __NEURUN_IR_OPERAND_INDEX_H__
+
+#include "util/Index.h"
+
+namespace neurun
+{
+namespace ir
+{
+
+struct OperationIndexTag;
+using OperationIndex = ::neurun::util::Index<uint32_t, OperationIndexTag>;
+
+struct OperandIndexTag;
+using OperandIndex = ::neurun::util::Index<uint32_t, OperandIndexTag>;
+
+struct IOIndexTag;
+using IOIndex = ::neurun::util::Index<uint32_t, IOIndexTag>;
+
+struct SubgraphIndexTag;
+using SubgraphIndex = ::neurun::util::Index<uint32_t, SubgraphIndexTag>;
+
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERAND_INDEX_H__
diff --git a/runtime/neurun/core/include/ir/InternalType.h b/runtime/neurun/core/include/ir/InternalType.h
new file mode 100644
index 000000000..91085f2f3
--- /dev/null
+++ b/runtime/neurun/core/include/ir/InternalType.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_INTERNAL_TYPE_H__
+#define __NEURUN_IR_INTERNAL_TYPE_H__
+
+#include <cstdint>
+
+namespace neurun
+{
+namespace ir
+{
+
+enum class Activation
+{
+  NONE = 0,
+  RELU = 1,
+  RELU1 = 2,
+  RELU6 = 3,
+  TANH = 4,
+  SIGMOID = 5
+};
+
+enum class PaddingType
+{
+  EXPLICIT = 0,
+  SAME = 1,
+  VALID = 2
+};
+
+struct ExplicitPadding
+{
+  uint32_t left;
+  uint32_t right;
+  uint32_t top;
+  uint32_t bottom;
+};
+
+// TODO Resolve explicit padding param at frontend and save in value field
+struct Padding
+{
+  PaddingType type;
+  ExplicitPadding param;
+};
+
+struct Stride
+{
+  uint32_t vertical;
+  uint32_t horizontal;
+};
+
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_INTERNAL_TYPE_H__
diff --git a/runtime/neurun/core/include/ir/Layout.h b/runtime/neurun/core/include/ir/Layout.h
new file mode 100644
index 000000000..c4edb70db
--- /dev/null
+++ b/runtime/neurun/core/include/ir/Layout.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_LAYOUT_H__
+#define __NEURUN_IR_LAYOUT_H__
+
+#include <functional>
+#include <string>
+
+namespace neurun
+{
+namespace ir
+{
+
+enum class Layout
+{
+  UNKNOWN = 0,
+  NHWC,
+  NCHW
+};
+
+inline std::string to_string(Layout layout)
+{
+  switch (layout)
+  {
+    case Layout::NHWC:
+      return std::string{"NHWC"};
+    case Layout::NCHW:
+      return std::string{"NCHW"};
+    case Layout::UNKNOWN:
+      return std::string{"UNKNOWN"};
+    default:
+      throw std::runtime_error("WRONG LAYOUT");
+  }
+}
+
+} // namespace ir
+} // namespace neurun
+
+namespace std
+{
+
+template <> struct hash<neurun::ir::Layout>
+{
+  size_t operator()(neurun::ir::Layout value) const noexcept
+  {
+    using type = typename std::underlying_type<neurun::ir::Layout>::type;
+    return hash<type>()(static_cast<type>(value));
+  }
+};
+
+} // namespace std
+
+#endif // __NEURUN_IR_LAYOUT_H__
diff --git a/runtime/neurun/core/include/ir/LowerInfoMap.h b/runtime/neurun/core/include/ir/LowerInfoMap.h
new file mode 100644
index 000000000..a8fd818b8
--- /dev/null
+++ b/runtime/neurun/core/include/ir/LowerInfoMap.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_LOWER_INFO_MAP_H__
+#define __NEURUN_IR_LOWER_INFO_MAP_H__
+
+#include <memory>
+#include <unordered_map>
+
+#include "ir/operand/LowerInfo.h"
+#include "ir/operation/LowerInfo.h"
+#include "ir/OperandIndexMap.h"
+#include "ir/Index.h"
+
+namespace neurun
+{
+namespace ir
+{
+
+struct LowerInfoMap
+{
+  std::unordered_map<SubgraphIndex, std::unique_ptr<operation::LowerInfo>> operation;
+  OperandIndexMap<std::unique_ptr<operand::LowerInfo>> operand;
+};
+
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_LOWER_INFO_MAP_H__
diff --git a/runtime/neurun/core/include/ir/OpCode.h b/runtime/neurun/core/include/ir/OpCode.h
new file mode 100644
index 000000000..2b466a212
--- /dev/null
+++ b/runtime/neurun/core/include/ir/OpCode.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OP_CODE_H__
+#define __NEURUN_IR_OP_CODE_H__
+
+#include <functional>
+#include <stdint.h>
+
+namespace neurun
+{
+namespace ir
+{
+
+enum class OpCode
+{
+  Invalid,             //< Unused
+#define OP(Name) Name, //< All operations
+#include "ir/Operations.lst"
+#undef OP
+  COUNT
+};
+
+const char *toString(OpCode opcode);
+
+} // namespace ir
+} // namespace neurun
+
+namespace std
+{
+
+template <> struct hash<neurun::ir::OpCode>
+{
+  size_t operator()(neurun::ir::OpCode value) const noexcept
+  {
+    using type = typename std::underlying_type<neurun::ir::OpCode>::type;
+    return hash<type>()(static_cast<type>(value));
+  }
+};
+
+} // namespace std
+
+#endif // __NEURUN_IR_OP_CODE_H__
diff --git a/runtime/neurun/core/include/ir/OpSequence.h b/runtime/neurun/core/include/ir/OpSequence.h
new file mode 100644
index 000000000..68632e589
--- /dev/null
+++ b/runtime/neurun/core/include/ir/OpSequence.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OP_SEQUENCE_H__
+#define __NEURUN_IR_OP_SEQUENCE_H__
+
+#include <vector>
+#include <string>
+#include <memory>
+
+#include "ir/Layout.h"
+#include "ir/Index.h"
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+
+// To support ValueSwappable, Element doesn't have members which are classes
+// as value(or can have members which are classes as value and the classes
+// support Swappable)
+struct Element
+{
+  OperationIndex index;
+  const Operation *node;
+
+  Element(const OperationIndex *i, const Operation *n) : index{*i}, node{n}
+  {
+    // DO NOTHING
+  }
+};
+
+class OpSequence
+{
+public:
+  explicit OpSequence(Layout layout);
+  OpSequence(const OpSequence &) = delete;
+
+public:
+  void accept(OperationVisitor &v) const;
+
+public:
+  const OperandIndexSequence &getInputs() const { return _inputs; }
+  const OperandIndexSequence &getOutputs() const { return _outputs; }
+  void setInputs(const OperandIndexSequence &indexes) { _inputs = indexes; }
+  void setOutputs(const OperandIndexSequence &indexes) { _outputs = indexes; }
+  void replaceInput(const OperandIndex &from, const OperandIndex &to) { _inputs.replace(from, to); }
+  void replaceOutput(const OperandIndex &from, const OperandIndex &to)
+  {
+    _outputs.replace(from, to);
+  }
+
+  void appendOperation(const OperationIndex &index, const Operation &node)
+  {
+    _operations.emplace_back(&index, &node);
+  }
+
+  std::vector<Element> &operations(void) { return _operations; }
+
+  const std::vector<Element> &operations(void) const { return _operations; }
+
+  uint32_t size(void) const { return _operations.size(); }
+
+  // TODO: Impl Dumper instead of this method
+  std::string getStr(void) const;
+
+public:
+  void remove(const OperationIndex &index);
+
+public:
+  Layout getLayout() const { return _layout; }
+
+public:
+  std::vector<Element>::const_iterator begin() const { return _operations.begin(); }
+  std::vector<Element>::const_iterator end() const { return _operations.end(); }
+
+private:
+  bool exist(const OperationIndex &index) const;
+
+private:
+  OperandIndexSequence _inputs;
+  OperandIndexSequence _outputs;
+  std::vector<Element> _operations;
+
+private:
+  Layout _layout;
+};
+
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OP_SEQUENCE_H__
diff --git a/runtime/neurun/core/include/ir/Operand.h b/runtime/neurun/core/include/ir/Operand.h
new file mode 100644
index 000000000..b1f28de48
--- /dev/null
+++ b/runtime/neurun/core/include/ir/Operand.h
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERAND_H__
+#define __NEURUN_IR_OPERAND_H__
+
+#include <cassert>
+#include <cstdint>
+#include <cpp14/memory.h>
+#include <algorithm>
+
+#include "ir/Data.h"
+#include "ir/DataType.h"
+#include "ir/OperandInfo.h"
+#include "ir/operand/ParentInfo.h" // TODO Remove this dependency
+#include "ir/OperationIndexList.h"
+
+namespace neurun
+{
+namespace ir
+{
+
+class Operand
+{
+public:
+  explicit Operand(const Shape &shape, const TypeInfo &type) : _info{shape, type}
+  {
+    // DO NOTHING
+  }
+
+public:
+  const Shape &shape(void) const { return _info.shape(); }
+  const TypeInfo &typeInfo(void) const { return _info.typeInfo(); }
+  const OperandInfo &info(void) const { return _info; }
+  size_t operandSize(void) const;
+
+  const OperationIndexList &getUses() const { return _uses; }
+  const OperationIndexList &getDef() const { return _def; }
+  void appendUse(const OperationIndex &idx);
+  void removeUse(const OperationIndex &idx);
+  void appendDef(const OperationIndex &idx);
+  void removeDef(const OperationIndex &idx);
+
+public:
+  void type(const DataType type) { _info.type(type); };
+
+public:
+  void data(std::unique_ptr<Data> &&data) { _data = std::move(data); }
+  const Data &data(void) const
+  {
+    assert(_data);
+    return *_data;
+  }
+
+  /**
+   * @brief Get true if Operand has data, otherwise @c false
+   a @return @c true if Operand has data, otherwise @c false
+   */
+  bool isConstant(void) const { return _data != nullptr; }
+
+public:
+  template <typename T, typename... Args> void data(Args &&... args)
+  {
+    data(nnfw::cpp14::make_unique<T>(std::forward<Args>(args)...));
+  }
+
+public:
+  template <typename T> T asScalar(void) const
+  {
+    assert((shape().rank() == 0) || ((shape().rank() == 1) && (shape().dim(0) == 1)));
+    assert(_data != nullptr);
+    assert((_data->base() != nullptr) && (_data->size() == sizeof(T)));
+
+    return *(reinterpret_cast<const T *>(_data->base()));
+  }
+
+  template <typename T> std::vector<T> asVector() const
+  {
+    assert(isConstant());
+    assert(_data->size() % sizeof(T) == 0);
+
+    const auto *base = reinterpret_cast<const T *>(_data->base());
+    const std::size_t size = _data->size() / sizeof(T);
+    return std::vector<T>(base, base + size);
+  }
+
+public:
+  /**
+   * @brief     Set parent information
+   * @param[in] parent_info Parent information
+   */
+  void parent_info(std::unique_ptr<operand::ParentInfo> &&parent_info);
+  /**
+   * @brief   Return parent information pointer as constant
+   * @return  Parent information pointer
+   */
+  const operand::ParentInfo *parent_info() const;
+  /**
+   * @brief   Return parent information pointer
+   * @return  Perent information pointer
+   */
+  operand::ParentInfo *parent_info();
+
+private:
+  OperandInfo _info;
+  std::shared_ptr<Data> _data;
+
+  OperationIndexList _uses;
+  OperationIndexList _def; // size is 0 (constant) or 1 (from def operation)
+
+  std::shared_ptr<operand::ParentInfo> _parent_info;
+};
+
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERAND_H__
diff --git a/runtime/neurun/core/include/ir/OperandConstraint.h b/runtime/neurun/core/include/ir/OperandConstraint.h
new file mode 100644
index 000000000..de6f21634
--- /dev/null
+++ b/runtime/neurun/core/include/ir/OperandConstraint.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_MODEL_OPERAND_CONSTRAINT_H__
+#define __NEURUN_MODEL_OPERAND_CONSTRAINT_H__
+
+#include <stdint.h>
+#include <limits>
+#include <set>
+
+namespace neurun
+{
+namespace ir
+{
+
+class OperandConstraint
+{
+private:
+  static const uint32_t INF = std::numeric_limits<uint32_t>::max();
+
+public:
+  static OperandConstraint createAny() { return OperandConstraint{0u, INF}; }
+  static OperandConstraint createExact(uint32_t exact) { return OperandConstraint{exact, exact}; }
+  static OperandConstraint createAtMost(uint32_t end) { return OperandConstraint{0u, end}; }
+  static OperandConstraint createAtLeast(uint32_t begin) { return OperandConstraint{begin, INF}; }
+  static OperandConstraint createInRange(uint32_t begin, uint32_t end)
+  {
+    return OperandConstraint{begin, end};
+  }
+
+private:
+  OperandConstraint(uint32_t begin, uint32_t end) : _begin{begin}, _end{end} {}
+
+public:
+  bool check(uint32_t ind) const { return _begin <= ind && ind <= _end; }
+
+private:
+  uint32_t _begin;
+  uint32_t _end;
+};
+
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_MODEL_OPERAND_CONSTRAINT_H__
diff --git a/runtime/neurun/core/include/ir/OperandIndexMap.h b/runtime/neurun/core/include/ir/OperandIndexMap.h
new file mode 100644
index 000000000..c9234128e
--- /dev/null
+++ b/runtime/neurun/core/include/ir/OperandIndexMap.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERAND_INDEX_MAP_H__
+#define __NEURUN_IR_OPERAND_INDEX_MAP_H__
+
+#include <unordered_map>
+
+#include "ir/Index.h"
+
+namespace neurun
+{
+namespace ir
+{
+
+template <typename T> using OperandIndexMap = std::unordered_map<OperandIndex, T>;
+
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERAND_INDEX_MAP_H__
diff --git a/runtime/neurun/core/include/ir/OperandIndexSequence.h b/runtime/neurun/core/include/ir/OperandIndexSequence.h
new file mode 100644
index 000000000..7f8cec844
--- /dev/null
+++ b/runtime/neurun/core/include/ir/OperandIndexSequence.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_MODEL_OPERAND_INDEX_SEQUENCE_H__
+#define __NEURUN_MODEL_OPERAND_INDEX_SEQUENCE_H__
+
+#include <initializer_list>
+#include <vector>
+
+#include "ir/Index.h"
+
+namespace neurun
+{
+namespace ir
+{
+
+class OperandIndexSequence
+{
+public:
+  OperandIndexSequence(void) = default;
+  OperandIndexSequence(std::initializer_list<OperandIndex> list);
+  OperandIndexSequence(std::initializer_list<int32_t> list);
+  OperandIndexSequence(std::initializer_list<uint32_t> list);
+
+public:
+  void append(const OperandIndex &index) { _set.emplace_back(index); }
+  void append(const OperandIndexSequence &l) { _set.insert(_set.end(), l.begin(), l.end()); }
+
+public:
+  uint32_t size() const { return static_cast<uint32_t>(_set.size()); }
+  const OperandIndex &at(IOIndex set_index) const { return _set.at(set_index.value()); }
+  const OperandIndex &at(uint32_t index) const { return _set.at(index); }
+  bool contains(const OperandIndex &index) const;
+  void replace(const OperandIndex &from, const OperandIndex &to);
+
+public:
+  std::vector<OperandIndex>::const_iterator begin(void) const { return _set.begin(); }
+  std::vector<OperandIndex>::const_iterator end(void) const { return _set.end(); }
+
+private:
+  std::vector<OperandIndex> _set;
+};
+
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_MODEL_OPERAND_INDEX_SET_H__
diff --git a/runtime/neurun/core/include/ir/OperandInfo.h b/runtime/neurun/core/include/ir/OperandInfo.h
new file mode 100644
index 000000000..82ad7ef0f
--- /dev/null
+++ b/runtime/neurun/core/include/ir/OperandInfo.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file  OperandInfo.h
+ * @brief This file contains OperandInfo class
+ */
+#ifndef __NEURUN_IR_OPERAND_INFO_H__
+#define __NEURUN_IR_OPERAND_INFO_H__
+
+#include "ir/Shape.h"
+#include "ir/TypeInfo.h"
+#include "ir/Layout.h"
+
+namespace neurun
+{
+namespace ir
+{
+
+/**
+ * @brief Class to save tensor's shape and type
+ */
+class OperandInfo
+{
+public:
+  /**
+   * @brief Construct a new OperandInfo object (deleted)
+   */
+  OperandInfo() = delete;
+  /**
+   * @brief     Construct a new OperandInfo object
+   * @param[in] shape     Tensor shape
+   * @param[in] typeInfo  Tensor data type
+   */
+  OperandInfo(const Shape &shape, const TypeInfo &typeInfo) : _shape(shape), _typeInfo(typeInfo)
+  {
+    // DO NOTHING
+  }
+  /**
+   * @brief     Construct a new OperandInfo object
+   * @param[in] origin info for copy
+   */
+  OperandInfo(const OperandInfo &origin) : _shape(origin.shape()), _typeInfo(origin.typeInfo())
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief   Return tensor shape
+   * @return  Tensor shape
+   */
+  const Shape &shape() const { return _shape; }
+  /**
+   * @brief   Return tensor data type info
+   * @return  Tensor data type
+   */
+  const TypeInfo &typeInfo() const { return _typeInfo; }
+  /**
+   * @brief   Set tensor data type
+   */
+  void type(const DataType type) { _typeInfo.type(type); }
+  /**
+   * @brief   Return size of tensor (bytes)
+   * @return  Tensor size
+   */
+  size_t total_size() const { return _shape.num_elements() * sizeOfDataType(_typeInfo.type()); }
+
+private:
+  Shape _shape;
+  TypeInfo _typeInfo;
+};
+
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERAND_INFO_H__
diff --git a/runtime/neurun/core/include/ir/Operands.h b/runtime/neurun/core/include/ir/Operands.h
new file mode 100644
index 000000000..c8d68c088
--- /dev/null
+++ b/runtime/neurun/core/include/ir/Operands.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERANDS_H__
+#define __NEURUN_IR_OPERANDS_H__
+
+#include <memory>
+#include <unordered_map>
+
+#include "ir/Operand.h"
+#include "ir/Index.h"
+#include "util/ObjectManager.h"
+
+namespace neurun
+{
+namespace ir
+{
+
+class Operands : public util::ObjectManager<OperandIndex, Operand>
+{
+};
+
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_MODEL_OPERAND_SET_H__
diff --git a/runtime/neurun/core/include/ir/Operation.h b/runtime/neurun/core/include/ir/Operation.h
new file mode 100644
index 000000000..a02f980a5
--- /dev/null
+++ b/runtime/neurun/core/include/ir/Operation.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_H__
+#define __NEURUN_IR_OPERATION_H__
+
+#include <memory>
+
+#include "ir/OpCode.h"
+#include "ir/Operand.h"
+#include "ir/OperandIndexSequence.h"
+#include "ir/OperandConstraint.h"
+
+namespace neurun
+{
+namespace ir
+{
+
+struct OperationVisitor;
+
+class Operation
+{
+public:
+  Operation(OperandConstraint input_constr, const OperandIndexSequence &inputs,
+            const OperandIndexSequence &outputs);
+  explicit Operation(OperandConstraint input_constr);
+
+  Operation(const Operation &) = delete;
+  Operation(Operation &&) = default;
+  Operation &operator=(const Operation &) = delete;
+  Operation &operator=(Operation &&) = default;
+
+  virtual ~Operation();
+
+public:
+  virtual void accept(OperationVisitor &v) const = 0;
+  virtual std::string name() const { return std::string{toString(opcode())}; }
+  virtual OpCode opcode() const = 0;
+
+public:
+  void replaceInput(const OperandIndex &from, const OperandIndex &to);
+  void replaceOutput(const OperandIndex &from, const OperandIndex &to);
+  const OperandIndexSequence &getInputs() const { return _inputs; }
+  const OperandIndexSequence &getOutputs() const { return _outputs; }
+  // It's for only input/output tensors but const data.
+  void setInputs(const OperandIndexSequence &indexes);
+  void setOutputs(const OperandIndexSequence &indexes);
+
+private:
+  OperandConstraint _input_constr;
+  OperandIndexSequence _inputs;
+  OperandIndexSequence _outputs;
+};
+
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_H__
diff --git a/runtime/neurun/core/include/ir/OperationIndexList.h b/runtime/neurun/core/include/ir/OperationIndexList.h
new file mode 100644
index 000000000..bf3ea3d6b
--- /dev/null
+++ b/runtime/neurun/core/include/ir/OperationIndexList.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_MODEL_OPERATION_INDEX_LIST_H__
+#define __NEURUN_MODEL_OPERATION_INDEX_LIST_H__
+
+#include <algorithm>
+#include <cassert>
+#include <initializer_list>
+#include <list>
+
+#include "ir/Index.h"
+
+namespace neurun
+{
+namespace ir
+{
+
+class OperationIndexList
+{
+public:
+  OperationIndexList(void) = default;
+  OperationIndexList(std::initializer_list<OperationIndex> list);
+
+public:
+  void append(const OperationIndex &index) { _list.push_back(index); }
+  void remove(const OperationIndex &index)
+  {
+    auto itr = std::find(_list.begin(), _list.end(), index);
+    assert(itr != _list.end());
+    _list.erase(itr);
+  }
+
+public:
+  uint32_t size() const { return static_cast<uint32_t>(_list.size()); }
+  const std::list<OperationIndex> &list() const { return _list; }
+  bool contains(const OperationIndex &index) const;
+
+private:
+  std::list<OperationIndex> _list;
+};
+
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_MODEL_OPERATION_INDEX_LIST_H__
diff --git a/runtime/neurun/core/include/ir/OperationIndexMap.h b/runtime/neurun/core/include/ir/OperationIndexMap.h
new file mode 100644
index 000000000..50b1db527
--- /dev/null
+++ b/runtime/neurun/core/include/ir/OperationIndexMap.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_INDEX_MAP_H__
+#define __NEURUN_IR_OPERATION_INDEX_MAP_H__
+
+#include <unordered_map>
+
+#include "ir/Index.h"
+
+namespace neurun
+{
+namespace ir
+{
+
+template <typename T> using OperationIndexMap = std::unordered_map<OperationIndex, T>;
+
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_INDEX_MAP_H__
diff --git a/runtime/neurun/core/include/ir/OperationVisitor.h b/runtime/neurun/core/include/ir/OperationVisitor.h
new file mode 100644
index 000000000..0eb6de2d3
--- /dev/null
+++ b/runtime/neurun/core/include/ir/OperationVisitor.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_VISITOR_H__
+#define __NEURUN_IR_OPERATION_VISITOR_H__
+
+#include "ir/Operations.Include.h"
+#include "ir/OpSequence.h"
+
+namespace neurun
+{
+namespace ir
+{
+
+struct OperationVisitor
+{
+  virtual ~OperationVisitor() = default;
+
+#define OP(InternalName) \
+  virtual void visit(const operation::InternalName &) {}
+#include "ir/Operations.lst"
+#undef OP
+
+  // This OpSequence node should be handled specially so that
+  // Op.lst doesn't have OpSequence
+  // TODO Remove by pushing it down to derived classes.
+  virtual void visit(const OpSequence &op_seq)
+  {
+    for (const auto &e : op_seq.operations())
+    {
+      e.node->accept(*this);
+    }
+  }
+};
+
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_VISITOR_H__
diff --git a/runtime/neurun/core/include/ir/Operations.Include.h b/runtime/neurun/core/include/ir/Operations.Include.h
new file mode 100644
index 000000000..e14e18cc1
--- /dev/null
+++ b/runtime/neurun/core/include/ir/Operations.Include.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+// This file has no ifdef guard intentionally
+
+#include "ir/operation/BatchToSpaceND.h"
+#include "ir/operation/Conv2D.h"
+#include "ir/operation/MaxPool2D.h"
+#include "ir/operation/AvgPool2D.h"
+#include "ir/operation/Concat.h"
+#include "ir/operation/Reshape.h"
+#include "ir/operation/FullyConnected.h"
+#include "ir/operation/Softmax.h"
+#include "ir/operation/Transpose.h"
+#include "ir/operation/Permute.h"
+#include "ir/operation/ReduceSum.h"
+#include "ir/operation/Add.h"
+#include "ir/operation/Sub.h"
+#include "ir/operation/DepthwiseConv2D.h"
+#include "ir/operation/Slice.h"
+#include "ir/operation/StridedSlice.h"
+#include "ir/operation/Mul.h"
+#include "ir/operation/Squeeze.h"
+#include "ir/operation/Tanh.h"
+#include "ir/operation/Logistic.h"
+#include "ir/operation/Cast.h"
+#include "ir/operation/Div.h"
+#include "ir/operation/Exp.h"
+#include "ir/operation/ReduceMax.h"
+#include "ir/operation/Comparison.h"
+#include "ir/operation/LogicalAnd.h"
+#include "ir/operation/LogicalOr.h"
+#include "ir/operation/LogicalNot.h"
+#include "ir/operation/LSTM.h"
+#include "ir/operation/RSQRT.h"
+#include "ir/operation/ReLU.h"
+#include "ir/operation/ResizeBilinear.h"
+#include "ir/operation/ReLU1.h"
+#include "ir/operation/ReLU6.h"
+#include "ir/operation/RNN.h"
+#include "ir/operation/Floor.h"
+#include "ir/operation/SpaceToBatchND.h"
+#include "ir/operation/SpaceToDepth.h"
+#include "ir/operation/L2Pool2D.h"
+#include "ir/operation/EmbeddingLookup.h"
+#include "ir/operation/L2Normalization.h"
+#include "ir/operation/HashtableLookup.h"
+#include "ir/operation/InstanceNorm.h"
+#include "ir/operation/PReLU.h"
+#include "ir/operation/TransposeConv.h"
+#include "ir/operation/SQRT.h"
+#include "ir/operation/SquaredDifference.h"
+#include "ir/operation/TopKV2.h"
+#include "ir/operation/Gather.h"
+#include "ir/operation/Neg.h"
+#include "ir/operation/Abs.h"
+#include "ir/operation/ArgMax.h"
+#include "ir/operation/Dequantize.h"
+#include "ir/operation/Mean.h"
+#include "ir/operation/LocalResponseNormalization.h"
+#include "ir/operation/DepthToSpace.h"
+#include "ir/operation/Pack.h"
+#include "ir/operation/ReduceMin.h"
+#include "ir/operation/Split.h"
+#include "ir/operation/Unpack.h"
+#include "ir/operation/Pad.h"
+#include "ir/operation/Min.h"
+#include "ir/operation/Max.h"
+#include "ir/operation/Custom.h"
+#include "ir/operation/OneHot.h"
diff --git a/runtime/neurun/core/include/ir/Operations.h b/runtime/neurun/core/include/ir/Operations.h
new file mode 100644
index 000000000..9e2aecb43
--- /dev/null
+++ b/runtime/neurun/core/include/ir/Operations.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATIONS_H__
+#define __NEURUN_IR_OPERATIONS_H__
+
+#include "ir/Index.h"
+#include "ir/Operation.h"
+#include "util/ObjectManager.h"
+
+namespace neurun
+{
+namespace ir
+{
+
+class Operations : public util::ObjectManager<OperationIndex, Operation>
+{
+};
+
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_MODEL_OPERATION_MANAGER_H__
diff --git a/runtime/neurun/core/include/ir/Operations.lst b/runtime/neurun/core/include/ir/Operations.lst
new file mode 100644
index 000000000..8c02857d9
--- /dev/null
+++ b/runtime/neurun/core/include/ir/Operations.lst
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef OP
+#error Define OP before including this file
+#endif
+
+// Internal Name
+OP(Add)
+OP(Sub)
+OP(BatchToSpaceND)
+OP(Cast)
+OP(Conv2D)
+OP(DepthwiseConv2D)
+OP(AvgPool2D)
+OP(MaxPool2D)
+OP(Concat)
+OP(FullyConnected)
+OP(ReduceSum)
+OP(Reshape)
+OP(Mul)
+OP(Softmax)
+OP(Squeeze)
+OP(Slice)
+OP(StridedSlice)
+OP(Tanh)
+OP(Logistic)
+OP(Div)
+OP(Transpose)
+OP(Exp)
+OP(ReduceMax)
+OP(Comparison)
+OP(LogicalAnd)
+OP(LogicalOr)
+OP(LogicalNot)
+OP(LSTM)
+OP(RSQRT)
+OP(ReLU)
+OP(ResizeBilinear)
+OP(ReLU1)
+OP(ReLU6)
+OP(RNN)
+OP(Floor)
+OP(SpaceToBatchND)
+OP(SpaceToDepth)
+OP(L2Pool2D)
+OP(EmbeddingLookup)
+OP(L2Normalization)
+OP(HashtableLookup)
+OP(InstanceNorm)
+OP(PReLU)
+OP(TransposeConv)
+OP(SQRT)
+OP(SquaredDifference)
+OP(TopKV2)
+OP(Gather)
+OP(Neg)
+OP(Abs)
+OP(ArgMax)
+OP(Dequantize)
+OP(Mean)
+OP(LocalResponseNormalization)
+OP(DepthToSpace)
+OP(Pack)
+OP(ReduceMin)
+OP(Split)
+OP(Unpack)
+OP(Pad)
+OP(Custom)
+OP(Permute)
+OP(Min)
+OP(Max)
+OP(OneHot)
diff --git a/runtime/neurun/core/include/ir/Shape.h b/runtime/neurun/core/include/ir/Shape.h
new file mode 100644
index 000000000..a58af38ad
--- /dev/null
+++ b/runtime/neurun/core/include/ir/Shape.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_SHAPE_H__
+#define __NEURUN_IR_SHAPE_H__
+
+#include "ir/Layout.h"
+#include "misc/feature/Shape.h"
+
+#include <cstdint>
+#include <vector>
+
+namespace neurun
+{
+namespace ir
+{
+
+// TODO Remove this dependency.
+using FeatureShape = nnfw::misc::feature::Shape;
+
+struct Shape
+{
+public:
+  Shape() = default;
+
+  explicit Shape(int rank) : _dimensions(rank) {}
+
+  Shape(std::initializer_list<int32_t> dimensions) : _dimensions(dimensions) {}
+
+  int rank() const { return _dimensions.size(); }
+
+  const std::vector<int32_t> &dims() const { return _dimensions; }
+
+  int32_t dim(int i) const { return _dimensions.at(i); }
+
+  int32_t &dim(int i) { return _dimensions.at(i); }
+
+  uint64_t num_elements() const;
+
+public:
+  FeatureShape asFeature(Layout layout) const;
+
+  /**
+   * @brief Add dimension to the beginning
+   * @param[in] d dimension to add to the beginning
+   */
+  void prepend(int32_t d) { _dimensions.insert(_dimensions.cbegin(), d); }
+
+  /**
+   * @brief Add dimension to the end
+   * @param[in] d dimension to add to the end
+   */
+  void append(int32_t d) { _dimensions.emplace_back(d); }
+
+  /**
+   * @brief Extend rank of Shape object for operand with param.
+   * @param[in] to_rank The rank value to be extended to
+   */
+  void extendRank(int to_rank);
+
+private:
+  std::vector<int32_t> _dimensions;
+};
+
+inline bool operator==(const Shape &lhs, const Shape &rhs) { return lhs.dims() == rhs.dims(); }
+inline bool operator!=(const Shape &lhs, const Shape &rhs) { return lhs.dims() != rhs.dims(); }
+
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_SHAPE_H__
diff --git a/runtime/neurun/core/include/ir/Subgraphs.h b/runtime/neurun/core/include/ir/Subgraphs.h
new file mode 100644
index 000000000..716f09bcf
--- /dev/null
+++ b/runtime/neurun/core/include/ir/Subgraphs.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_SUBGRAPHS_H__
+#define __NEURUN_IR_SUBGRAPHS_H__
+
+#include "ir/Index.h"
+#include "ir/OpSequence.h"
+#include "util/ObjectManager.h"
+
+namespace neurun
+{
+namespace ir
+{
+
+/**
+ * @brief Class that manages OpSequence objects
+ */
+class Subgraphs : public util::ObjectManager<SubgraphIndex, OpSequence>
+{
+public:
+  /**
+   * @brief Create an instance of OpSequence with given op and push it to objects
+   *
+   * @param[in] op_idx Operation index that is emplaced
+   * @param[in] op Operation that is emplaced
+   * @param[in] layout OpSequence's layout
+   * @return SubgraphIndex
+   */
+  SubgraphIndex emplace(const OperationIndex &op_index, const Operation &op, Layout layout);
+
+  /**
+   * @brief Push an instance of OpSequence to objects
+   *
+   * @param[in] subg An instance of OpSequence
+   * @return SubgraphIndex
+   */
+  SubgraphIndex emplace(std::unique_ptr<OpSequence> &&subg);
+
+  /**
+   * @brief Check if an operation does exist in any subgraphs
+   *
+   * @param operation_index Operation index to find
+   * @return true If such operation exists in any subgraphs otherwise false
+   */
+  bool containsOperation(const OperationIndex &operation_index) const;
+  /**
+   * @brief Find an operation from all subgraphs
+   *
+   * @param operation_index Operation index to find
+   * @return SubgraphIndex Index of OpSequence that contains given operation index
+   */
+  SubgraphIndex getOperation(const OperationIndex &operation_index) const;
+  /**
+   * @brief Dump subgraphs
+   *
+   * @param msg Message that will be displayed
+   */
+  void dump(const std::string &msg) const;
+  /**
+   * @brief Remove an operation from OpSequence
+   *
+   * @param operation_index Operation index to be removed
+   */
+  void removeFromSubgraph(const OperationIndex &operation_index);
+
+private:
+  SubgraphIndex findOperation(const OperationIndex &operation_index) const;
+};
+
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_SUBGRAPHS_H__
diff --git a/runtime/neurun/core/include/ir/TypeInfo.h b/runtime/neurun/core/include/ir/TypeInfo.h
new file mode 100644
index 000000000..5b35046bb
--- /dev/null
+++ b/runtime/neurun/core/include/ir/TypeInfo.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_TYPEINFO_H__
+#define __NEURUN_IR_TYPEINFO_H__
+
+#include <cstdint>
+
+#include "ir/DataType.h"
+
+namespace neurun
+{
+namespace ir
+{
+
+class TypeInfo
+{
+public:
+  TypeInfo() = delete;
+
+  explicit TypeInfo(DataType type, float scale = 0, int32_t offset = 0)
+      : _type(type), _scale(scale), _offset(offset)
+  {
+  }
+
+public:
+  DataType type() const { return _type; }
+  float scale() const { return _scale; }
+  int32_t offset() const { return _offset; }
+
+public:
+  void type(const DataType type) { _type = type; }
+
+private:
+  DataType _type;
+  float _scale;
+  int32_t _offset;
+};
+
+bool operator==(const TypeInfo &lhs, const TypeInfo &rhs);
+bool operator!=(const TypeInfo &lhs, const TypeInfo &rhs);
+
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_TYPEINFO_H__
diff --git a/runtime/neurun/core/include/ir/operand/LowerInfo.h b/runtime/neurun/core/include/ir/operand/LowerInfo.h
new file mode 100644
index 000000000..e0fb2c5c8
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operand/LowerInfo.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERAND_LOWER_INFO_H__
+#define __NEURUN_IR_OPERAND_LOWER_INFO_H__
+
+#include <functional>
+#include <stdint.h>
+
+#include "ir/operand/PermuteFactor.h"
+#include "util/Set.h"
+
+namespace neurun
+{
+namespace backend
+{
+class Backend;
+} // namespace backend
+} // namespace neurun
+
+namespace neurun
+{
+namespace ir
+{
+namespace operand
+{
+using PermuteFactorSet = util::Set<PermuteFactor>;
+
+class LowerInfo
+{
+public:
+  class Shape4D
+  {
+  public:
+    Shape4D(uint32_t n, uint32_t h, uint32_t w, uint32_t c) : _n{n}, _h{h}, _w{w}, _c{c}
+    {
+      // DO NOTHING
+    }
+
+  public:
+    uint32_t n(void) const { return _n; }
+    uint32_t h(void) const { return _h; }
+    uint32_t w(void) const { return _w; }
+    uint32_t c(void) const { return _c; }
+
+  private:
+    uint32_t _n;
+    uint32_t _h;
+    uint32_t _w;
+    uint32_t _c;
+  };
+
+public:
+  LowerInfo(const Shape4D &shape) : _shape{shape}
+  {
+    // DO NOTHING
+  }
+
+public:
+  const Shape4D &shape(void) const { return _shape; }
+  const PermuteFactorSet &def_factors(void) const { return _def_factors; }
+  const PermuteFactorSet &use_factors(void) const { return _use_factors; }
+
+public:
+  void addDefPermuteFactor(const PermuteFactor &factor) { _def_factors.add(factor); }
+  void addUsePermuteFactor(const PermuteFactor &factor) { _use_factors.add(factor); }
+  void removeDefPermuteFactor(const PermuteFactor &factor) { _def_factors.remove(factor); }
+  void removeUsePermuteFactor(const PermuteFactor &factor) { _use_factors.remove(factor); }
+
+private:
+  Shape4D _shape;
+  PermuteFactorSet _def_factors;
+  PermuteFactorSet _use_factors;
+};
+
+} // namespace operand
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERAND_LOWER_INFO_H__
diff --git a/runtime/neurun/core/include/ir/operand/ParentInfo.h b/runtime/neurun/core/include/ir/operand/ParentInfo.h
new file mode 100644
index 000000000..92dac2b63
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operand/ParentInfo.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file  ParentInfo.h
+ * @brief This file contains ParentInfo class and internal Coordinate4D class
+ *        to represent subsumption between operand
+ */
+
+#ifndef __NEURUN_IR_OPERAND_PARENT_INFO_H__
+#define __NEURUN_IR_OPERAND_PARENT_INFO_H__
+
+#include <stdint.h>
+
+#include "ir/Index.h"
+#include "util/Coordinates.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operand
+{
+
+/**
+ * @brief	Class to represent parent operand in child operand
+ */
+class ParentInfo
+{
+public:
+  /**
+   * @brief     Construct a new ParentInfo object
+   * @param[in] parent      Index of parent operand
+   * @param[in] coordinate  Offset of child operand in parent operand
+   * @return
+   */
+  ParentInfo(const OperandIndex parent, const util::Coordinates &coordinate)
+      : _parent{parent}, _coordinate{coordinate}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief   Return parent index
+   * @return  Parent index
+   */
+  OperandIndex parent(void) const { return _parent; }
+  /**
+   * @brief   Retern offset in parent
+   * @return  Offset
+   */
+  util::Coordinates offset(void) const { return _coordinate; }
+
+private:
+  OperandIndex _parent;
+  util::Coordinates _coordinate;
+};
+
+} // namespace operand
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERAND_PARENT_INFO_H__
diff --git a/runtime/neurun/core/include/ir/operand/PermuteFactor.h b/runtime/neurun/core/include/ir/operand/PermuteFactor.h
new file mode 100644
index 000000000..60d926b2d
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operand/PermuteFactor.h
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     PermuteFactor.h
+ * @brief    This file contains neurun::ir::operand::PermuteFactor class
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NEURUN_IR_OPERAND_PERMUTE_FACTOR_H__
+#define __NEURUN_IR_OPERAND_PERMUTE_FACTOR_H__
+
+#include <functional>
+
+#include "ir/Layout.h"
+
+namespace neurun
+{
+namespace backend
+{
+class Backend;
+} // namespace backend
+} // namespace neurun
+
+namespace neurun
+{
+namespace ir
+{
+namespace operand
+{
+
+/**
+ * @brief Class that has factors of permutation
+ */
+class PermuteFactor
+{
+public:
+  /**
+   * @brief Construct PermuteFactor object.
+   * @param backend  The backend factor
+   * @param backend  The layout factor
+   */
+  PermuteFactor(const backend::Backend *backend, Layout layout) : _backend{backend}, _layout{layout}
+  {
+    // DO NOTHING
+  }
+  /**
+   * @brief Construct PermuteFactor object by copy semantics.
+   */
+  PermuteFactor(const PermuteFactor &f) : _backend{f._backend}, _layout{f._layout}
+  {
+    // DO NOTHING
+  }
+  /**
+   * @brief Construct PermuteFactor object by move semantics.
+   */
+  PermuteFactor(PermuteFactor &&) = default;
+
+public:
+  /**
+   * @brief Get backend
+   *
+   * @return Backend factor
+   */
+  const backend::Backend *backend() const { return _backend; }
+  /**
+   * @brief Get layout
+   *
+   * @return Layout factor
+   */
+  Layout layout() const { return _layout; }
+
+public:
+  /**
+   * @brief operator overloading function for `==`
+   *
+   * @return Whether two PermuteFactor are the same
+   */
+  bool operator==(const PermuteFactor &other) const
+  {
+    return _backend == other.backend() && _layout == other.layout();
+  }
+  /**
+   * @brief operator overloading function for `!=`
+   *
+   * @return Whether two PermuteFactor are differenct
+   */
+  bool operator!=(const PermuteFactor &other) const { return !(*this == other); }
+
+private:
+  const backend::Backend *_backend{nullptr};
+  Layout _layout{Layout::UNKNOWN};
+};
+
+} // namespace operand
+} // namespace ir
+} // namespace neurun
+
+namespace std
+{
+
+/**
+ * @brief Structure that provides hash value of PermuteFactor
+ */
+template <> struct hash<neurun::ir::operand::PermuteFactor>
+{
+  size_t operator()(const neurun::ir::operand::PermuteFactor &factor) const noexcept
+  {
+    hash<const neurun::backend::Backend *> b_hash{};
+    hash<neurun::ir::Layout> l_hash{};
+    return b_hash(factor.backend()) ^ (l_hash(factor.layout()) << 1);
+  }
+};
+
+} // namespace std
+
+#endif // __NEURUN_IR_OPERAND_PERMUTE_FACTOR_H__
diff --git a/runtime/neurun/core/include/ir/operation/Abs.h b/runtime/neurun/core/include/ir/operation/Abs.h
new file mode 100644
index 000000000..97293823b
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/Abs.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_ABS_H__
+#define __NEURUN_IR_OPERATION_ABS_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class Abs : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0
+  };
+
+public:
+  Abs(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::Abs; }
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_ABS_H__
diff --git a/runtime/neurun/core/include/ir/operation/Add.h b/runtime/neurun/core/include/ir/operation/Add.h
new file mode 100644
index 000000000..fc4d6a7e7
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/Add.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_ADD_H__
+#define __NEURUN_IR_OPERATION_ADD_H__
+
+#include "ir/Operation.h"
+#include "ir/InternalType.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class Add : public Operation
+{
+public:
+  enum Input
+  {
+    LHS = 0,
+    RHS
+  };
+
+  struct Param
+  {
+    Activation activation;
+  };
+
+public:
+  Add(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs, const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::Add; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_ADD_H__
diff --git a/runtime/neurun/core/include/ir/operation/ArgMax.h b/runtime/neurun/core/include/ir/operation/ArgMax.h
new file mode 100644
index 000000000..23f52710f
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/ArgMax.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_ARG_MAX_H__
+#define __NEURUN_IR_OPERATION_ARG_MAX_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class ArgMax : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT
+  };
+
+  struct Param
+  {
+    int axis;
+    int rank;
+  };
+
+public:
+  ArgMax(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+         const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::ArgMax; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_ARG_MAX_H__
diff --git a/runtime/neurun/core/include/ir/operation/AvgPool2D.h b/runtime/neurun/core/include/ir/operation/AvgPool2D.h
new file mode 100644
index 000000000..a03628184
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/AvgPool2D.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_AVGPOOL2D_H__
+#define __NEURUN_IR_OPERATION_AVGPOOL2D_H__
+
+#include <memory>
+
+#include "ir/Operation.h"
+#include "ir/InternalType.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class AvgPool2D : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0
+  };
+
+  struct Param
+  {
+    uint32_t kh;
+    uint32_t kw;
+
+    Stride stride;
+    Padding padding;
+    Activation activation;
+  };
+
+public:
+  AvgPool2D(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+            const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::AvgPool2D; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_AVGPOOL2D_H__
diff --git a/runtime/neurun/core/include/ir/operation/BatchToSpaceND.h b/runtime/neurun/core/include/ir/operation/BatchToSpaceND.h
new file mode 100644
index 000000000..b90d2871d
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/BatchToSpaceND.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_BATCH_TO_SPACE_ND_H__
+#define __NEURUN_IR_OPERATION_BATCH_TO_SPACE_ND_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class BatchToSpaceND : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0,
+    BLOCK_SIZE = 1
+  };
+
+public:
+  BatchToSpaceND(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::BatchToSpaceND; }
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_BATCH_TO_SPACE_ND_H__
diff --git a/runtime/neurun/core/include/ir/operation/Cast.h b/runtime/neurun/core/include/ir/operation/Cast.h
new file mode 100644
index 000000000..a71087dd0
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/Cast.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_CAST_H__
+#define __NEURUN_IR_OPERATION_CAST_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class Cast : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0
+  };
+
+public:
+  Cast(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::Cast; }
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_CAST_H__
diff --git a/runtime/neurun/core/include/ir/operation/Comparison.h b/runtime/neurun/core/include/ir/operation/Comparison.h
new file mode 100644
index 000000000..23c775c42
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/Comparison.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_COMPARISON_H__
+#define __NEURUN_IR_OPERATION_COMPARISON_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class Comparison : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT0 = 0,
+    INPUT1
+  };
+
+  enum class ComparisonType
+  {
+    Equal,
+    NotEqual,
+    Greater,
+    GreaterEqual,
+    Less,
+    LessEqual
+  };
+
+  struct Param
+  {
+    ComparisonType comparison_type;
+  };
+
+public:
+  Comparison(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+             const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::Comparison; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_COMPARISON_H__
diff --git a/runtime/neurun/core/include/ir/operation/Concat.h b/runtime/neurun/core/include/ir/operation/Concat.h
new file mode 100644
index 000000000..8628ed398
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/Concat.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_CONCAT_H__
+#define __NEURUN_IR_OPERATION_CONCAT_H__
+
+#include <memory>
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class Concat : public Operation
+{
+public:
+  struct Param
+  {
+    int32_t axis;
+    int32_t rank;
+  };
+
+public:
+  Concat(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+         const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::Concat; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_CONCAT_H__
diff --git a/runtime/neurun/core/include/ir/operation/Conv2D.h b/runtime/neurun/core/include/ir/operation/Conv2D.h
new file mode 100644
index 000000000..1215666e9
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/Conv2D.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_CONV2D_H__
+#define __NEURUN_IR_OPERATION_CONV2D_H__
+
+#include <memory>
+
+#include "ir/Operation.h"
+#include "ir/InternalType.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class Conv2D : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0,
+    KERNEL,
+    BIAS
+  };
+
+  struct Param
+  {
+    Stride stride;
+    Padding padding;
+    Activation activation;
+  };
+
+public:
+  Conv2D(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+         const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::Conv2D; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_CONV2D_H__
diff --git a/runtime/neurun/core/include/ir/operation/Custom.h b/runtime/neurun/core/include/ir/operation/Custom.h
new file mode 100644
index 000000000..03501e8ef
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/Custom.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __NEURUN_IR_OPERATION_CUSTOM_H__
+#define __NEURUN_IR_OPERATION_CUSTOM_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class Custom : public Operation
+{
+public:
+  struct Userdata
+  {
+    char *data;
+    size_t size;
+  };
+
+  Custom(OperandConstraint input_constr, const OperandIndexSequence &inputs,
+         const OperandIndexSequence &outputs, std::string id, const Userdata &userdata);
+
+  void accept(OperationVisitor &v) const override;
+
+public:
+  /**
+   * @return unique operation identifier
+   */
+  const std::string &id() const;
+
+  std::string name() const override;
+  OpCode opcode() const final { return OpCode::Custom; }
+
+  /**
+   * @return user-provided data
+   */
+  const Userdata &userdata() const;
+
+  ~Custom() override;
+
+private:
+  std::string _id;
+  Userdata _userdata;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+#endif // __NEURUN_IR_OPERATION_CUSTOM_H__
diff --git a/runtime/neurun/core/include/ir/operation/DepthToSpace.h b/runtime/neurun/core/include/ir/operation/DepthToSpace.h
new file mode 100644
index 000000000..6e7aaf249
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/DepthToSpace.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_DEPTH_TO_SPACE_H__
+#define __NEURUN_IR_OPERATION_DEPTH_TO_SPACE_H__
+
+#include <memory>
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class DepthToSpace : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0
+  };
+
+  struct Param
+  {
+    std::int32_t block_size;
+  };
+
+public:
+  DepthToSpace(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+               const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::DepthToSpace; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_DEPTH_TO_SPACE_H__
diff --git a/runtime/neurun/core/include/ir/operation/DepthwiseConv2D.h b/runtime/neurun/core/include/ir/operation/DepthwiseConv2D.h
new file mode 100644
index 000000000..1f0926fa8
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/DepthwiseConv2D.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_DEPTHWISECONV2D_H__
+#define __NEURUN_IR_OPERATION_DEPTHWISECONV2D_H__
+
+#include <memory>
+
+#include "ir/Operation.h"
+#include "ir/InternalType.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class DepthwiseConv2D : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0,
+    KERNEL,
+    BIAS
+  };
+
+  struct Param
+  {
+    Stride stride;
+    Padding padding;
+    uint32_t multiplier;
+    Activation activation;
+  };
+
+public:
+  DepthwiseConv2D(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+                  const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::DepthwiseConv2D; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_DEPTHWISECONV2D_H__
diff --git a/runtime/neurun/core/include/ir/operation/Dequantize.h b/runtime/neurun/core/include/ir/operation/Dequantize.h
new file mode 100644
index 000000000..dfca278cd
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/Dequantize.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_DEQUANTIZE_H__
+#define __NEURUN_IR_OPERATION_DEQUANTIZE_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class Dequantize : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0
+  };
+
+public:
+  Dequantize(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::Dequantize; }
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_DEQUANTIZE_H__
diff --git a/runtime/neurun/core/include/ir/operation/Div.h b/runtime/neurun/core/include/ir/operation/Div.h
new file mode 100644
index 000000000..d3e744472
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/Div.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_DIV_H__
+#define __NEURUN_IR_OPERATION_DIV_H__
+
+#include "ir/Operation.h"
+#include "ir/InternalType.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class Div : public Operation
+{
+public:
+  enum Input
+  {
+    LHS = 0,
+    RHS
+  };
+
+  struct Param
+  {
+    Activation activation;
+  };
+
+public:
+  Div(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs, const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::Div; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_DIV_H__
diff --git a/runtime/neurun/core/include/ir/operation/EmbeddingLookup.h b/runtime/neurun/core/include/ir/operation/EmbeddingLookup.h
new file mode 100644
index 000000000..968b7b35a
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/EmbeddingLookup.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_EMBEDDING_LOOKUP_H__
+#define __NEURUN_IR_OPERATION_EMBEDDING_LOOKUP_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class EmbeddingLookup : public Operation
+{
+public:
+  enum Input
+  {
+    LOOKUPS = 0,
+    VALUES = 1
+  };
+
+public:
+  EmbeddingLookup(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::EmbeddingLookup; }
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_EMBEDDING_LOOKUP_H__
diff --git a/runtime/neurun/core/include/ir/operation/Exp.h b/runtime/neurun/core/include/ir/operation/Exp.h
new file mode 100644
index 000000000..8e04f3f7f
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/Exp.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_EXP_H__
+#define __NEURUN_IR_OPERATION_EXP_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class Exp : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0
+  };
+
+public:
+  Exp(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::Exp; }
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_EXP_H__
diff --git a/runtime/neurun/core/include/ir/operation/Floor.h b/runtime/neurun/core/include/ir/operation/Floor.h
new file mode 100644
index 000000000..ca4cf9881
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/Floor.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_FLOOR_H__
+#define __NEURUN_IR_OPERATION_FLOOR_H__
+
+#include <memory>
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class Floor : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0
+  };
+
+public:
+  Floor(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::Floor; }
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_FLOOR_H__
diff --git a/runtime/neurun/core/include/ir/operation/FullyConnected.h b/runtime/neurun/core/include/ir/operation/FullyConnected.h
new file mode 100644
index 000000000..1ffa1318d
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/FullyConnected.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_FULLYCONNECTED_H__
+#define __NEURUN_IR_OPERATION_FULLYCONNECTED_H__
+
+#include <memory>
+
+#include "ir/Operation.h"
+#include "ir/InternalType.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class FullyConnected : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0,
+    WEIGHT,
+    BIAS
+  };
+
+  struct Param
+  {
+    Activation activation;
+  };
+
+public:
+  FullyConnected(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+                 const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::FullyConnected; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_FULLYCONNECTED_H__
diff --git a/runtime/neurun/core/include/ir/operation/Gather.h b/runtime/neurun/core/include/ir/operation/Gather.h
new file mode 100644
index 000000000..13540d413
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/Gather.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_GATHER_H__
+#define __NEURUN_IR_OPERATION_GATHER_H__
+
+#include <memory>
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class Gather : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0,
+    INDICES,
+  };
+
+  struct Param
+  {
+    int32_t axis;
+    int32_t rank;
+  };
+
+public:
+  Gather(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+         const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::Gather; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_GATHER_H__
diff --git a/runtime/neurun/core/include/ir/operation/HashtableLookup.h b/runtime/neurun/core/include/ir/operation/HashtableLookup.h
new file mode 100644
index 000000000..fb6c97607
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/HashtableLookup.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_HASHTABLE_LOOKUP_H__
+#define __NEURUN_IR_OPERATION_HASHTABLE_LOOKUP_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class HashtableLookup : public Operation
+{
+public:
+  enum Input
+  {
+    LOOKUPS = 0,
+    KEYS = 1,
+    VALUES = 2
+  };
+
+  enum Output
+  {
+    OUTPUT = 0,
+    HITS = 1
+  };
+
+public:
+  HashtableLookup(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::HashtableLookup; }
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_HASHTABLE_LOOKUP_H__
diff --git a/runtime/neurun/core/include/ir/operation/InstanceNorm.h b/runtime/neurun/core/include/ir/operation/InstanceNorm.h
new file mode 100644
index 000000000..cbd03ad1f
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/InstanceNorm.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_INSTANCE_NORM_H__
+#define __NEURUN_IR_OPERATION_INSTANCE_NORM_H__
+
+#include "ir/Operation.h"
+#include "ir/InternalType.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class InstanceNorm : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0,
+    GAMMA,
+    BETA
+  };
+
+  struct Param
+  {
+    Activation activation;
+    float epsilon;
+  };
+
+public:
+  InstanceNorm(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+               const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::InstanceNorm; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_INSTANCE_NORM_H__
diff --git a/runtime/neurun/core/include/ir/operation/L2Normalization.h b/runtime/neurun/core/include/ir/operation/L2Normalization.h
new file mode 100644
index 000000000..e2c1f4eee
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/L2Normalization.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_L2_NORMALIZATION_H__
+#define __NEURUN_IR_OPERATION_L2_NORMALIZATION_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class L2Normalization : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0
+  };
+
+public:
+  struct Param
+  {
+    int32_t rank;
+  };
+
+public:
+  L2Normalization(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+                  const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::L2Normalization; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_L2_NORMALIZATION_H__
diff --git a/runtime/neurun/core/include/ir/operation/L2Pool2D.h b/runtime/neurun/core/include/ir/operation/L2Pool2D.h
new file mode 100644
index 000000000..6d4d72ee2
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/L2Pool2D.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_L2_POOL_2D_H__
+#define __NEURUN_IR_OPERATION_L2_POOL_2D_H__
+
+#include <memory>
+
+#include "ir/Operation.h"
+#include "ir/InternalType.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class L2Pool2D : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0,
+  };
+
+  struct Param
+  {
+    Padding padding;
+    Stride stride;
+    uint32_t kw;
+    uint32_t kh;
+    Activation activation;
+  };
+
+public:
+  L2Pool2D(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+           const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::L2Pool2D; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_L2_POOL_2D_H__
diff --git a/runtime/neurun/core/include/ir/operation/LSTM.h b/runtime/neurun/core/include/ir/operation/LSTM.h
new file mode 100644
index 000000000..2ea09b1b7
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/LSTM.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __NEURUN_IR_OPERATION_LSTM_H__
+#define __NEURUN_IR_OPERATION_LSTM_H__
+
+#include "ir/InternalType.h"
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class LSTM : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0,
+    INPUT_TO_INPUT_WEIGHTS = 1,
+    INPUT_TO_FORGET_WEIGHTS = 2,
+    INPUT_TO_CELL_WEIGHTS = 3,
+    INPUT_TO_OUTPUT_WEIGHTS = 4,
+    RECURRENT_TO_INPUT_WEIGHTS = 5,
+    RECURRENT_TO_FORGET_WEIGHTS = 6,
+    RECURRENT_TO_CELL_WEIGHTS = 7,
+    RECURRENT_TO_OUTPUT_WEIGHTS = 8,
+    CELL_TO_INPUT_WEIGHTS = 9,
+    CELL_TO_FORGET_WEIGHTS = 10,
+    CELL_TO_OUTPUT_WEIGHTS = 11,
+    INPUT_GATE_BIAS = 12,
+    FORGET_GATE_BIAS = 13,
+    CELL_BIAS = 14,
+    OUTPUT_GATE_BIAS = 15,
+    PROJECTION_WEIGHTS = 16,
+    PROJECTION_BIAS = 17,
+    OUTPUT_STATE_IN = 18,
+    CELL_STATE_IN = 19,
+  };
+
+  enum Output
+  {
+    SCRATCH_BUFFER = 0,
+    OUTPUT_STATE_OUT = 1,
+    CELL_STATE_OUT = 2,
+    OUTPUT = 3
+  };
+
+  struct Param
+  {
+    Activation activation;
+    float cell_threshold;
+    float projection_threshold;
+  };
+
+public:
+  LSTM(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs, const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::LSTM; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_LSTM_H__
diff --git a/runtime/neurun/core/include/ir/operation/LocalResponseNormalization.h b/runtime/neurun/core/include/ir/operation/LocalResponseNormalization.h
new file mode 100644
index 000000000..3fbf2e4ae
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/LocalResponseNormalization.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_LOCAL_RESPONSE_NORMALIZATION_H__
+#define __NEURUN_IR_OPERATION_LOCAL_RESPONSE_NORMALIZATION_H__
+
+#include <memory>
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class LocalResponseNormalization : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0
+  };
+
+  struct Param
+  {
+    int radius;
+    float bias;
+    float alpha;
+    float beta;
+  };
+
+public:
+  LocalResponseNormalization(const OperandIndexSequence &inputs,
+                             const OperandIndexSequence &outputs, const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::LocalResponseNormalization; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_LOCAL_RESPONSE_NORMALIZATION_H__
diff --git a/runtime/neurun/core/include/ir/operation/LogicalAnd.h b/runtime/neurun/core/include/ir/operation/LogicalAnd.h
new file mode 100644
index 000000000..f7b03d62d
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/LogicalAnd.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_LOGICAL_AND_H__
+#define __NEURUN_IR_OPERATION_LOGICAL_AND_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class LogicalAnd : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT0 = 0,
+    INPUT1 = 1,
+  };
+
+public:
+  LogicalAnd(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::LogicalAnd; }
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_LOGICAL_AND_H__
diff --git a/runtime/neurun/core/include/ir/operation/LogicalNot.h b/runtime/neurun/core/include/ir/operation/LogicalNot.h
new file mode 100644
index 000000000..e689d57b2
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/LogicalNot.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_LOGICAL_NOT_H__
+#define __NEURUN_IR_OPERATION_LOGICAL_NOT_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class LogicalNot : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0,
+  };
+
+public:
+  LogicalNot(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::LogicalNot; }
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_LOGICAL_NOT_H__
diff --git a/runtime/neurun/core/include/ir/operation/LogicalOr.h b/runtime/neurun/core/include/ir/operation/LogicalOr.h
new file mode 100644
index 000000000..fda6b20d7
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/LogicalOr.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_LOGICAL_OR_H__
+#define __NEURUN_IR_OPERATION_LOGICAL_OR_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class LogicalOr : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT0 = 0,
+    INPUT1 = 1,
+  };
+
+public:
+  LogicalOr(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::LogicalOr; }
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_LOGICAL_OR_H__
diff --git a/runtime/neurun/core/include/ir/operation/Logistic.h b/runtime/neurun/core/include/ir/operation/Logistic.h
new file mode 100644
index 000000000..b23e7ef3f
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/Logistic.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_LOGISTIC_H__
+#define __NEURUN_IR_OPERATION_LOGISTIC_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class Logistic : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0
+  };
+
+public:
+  Logistic(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::Logistic; }
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_LOGISTIC_H__
diff --git a/runtime/neurun/core/include/ir/operation/LowerInfo.h b/runtime/neurun/core/include/ir/operation/LowerInfo.h
new file mode 100644
index 000000000..856976a0c
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/LowerInfo.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_LOWER_INFO_H__
+#define __NEURUN_IR_OPERATION_LOWER_INFO_H__
+
+#include <string>
+
+#include <ir/operand/PermuteFactor.h>
+
+namespace neurun
+{
+namespace backend
+{
+class Backend;
+} // namespace backend
+} // namespace neurun
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class LowerInfo
+{
+public:
+  LowerInfo(const backend::Backend *backend, Layout layout);
+  const backend::Backend *backend() const { return _permute_factor.backend(); }
+  Layout layout() const { return _permute_factor.layout(); }
+
+private:
+  operand::PermuteFactor _permute_factor;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_LOWER_INFO_H__
diff --git a/runtime/neurun/core/include/ir/operation/Max.h b/runtime/neurun/core/include/ir/operation/Max.h
new file mode 100644
index 000000000..1675f9f72
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/Max.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_MAX_H__
+#define __NEURUN_IR_OPERATION_MAX_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class Max : public Operation
+{
+public:
+  enum Input
+  {
+    LHS = 0,
+    RHS
+  };
+
+public:
+  Max(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::Max; }
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_MAX_H__
diff --git a/runtime/neurun/core/include/ir/operation/MaxPool2D.h b/runtime/neurun/core/include/ir/operation/MaxPool2D.h
new file mode 100644
index 000000000..c0f0939aa
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/MaxPool2D.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_MAXPOOL2D_H__
+#define __NEURUN_IR_OPERATION_MAXPOOL2D_H__
+
+#include <memory>
+
+#include "ir/Operation.h"
+#include "ir/InternalType.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class MaxPool2D : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0
+  };
+
+  struct Param
+  {
+    uint32_t kh;
+    uint32_t kw;
+    Stride stride;
+    Padding padding;
+    Activation activation;
+  };
+
+public:
+  MaxPool2D(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+            const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::MaxPool2D; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_MAXPOOL2D_H__
diff --git a/runtime/neurun/core/include/ir/operation/Mean.h b/runtime/neurun/core/include/ir/operation/Mean.h
new file mode 100644
index 000000000..cce8de377
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/Mean.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_MEAN_H__
+#define __NEURUN_IR_OPERATION_MEAN_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class Mean : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT
+  };
+
+  struct Param
+  {
+    std::vector<int> axes;
+    bool keep_dims;
+    int32_t rank;
+  };
+
+public:
+  Mean(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs, const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::Mean; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_MEAN_H__
diff --git a/runtime/neurun/core/include/ir/operation/Min.h b/runtime/neurun/core/include/ir/operation/Min.h
new file mode 100644
index 000000000..fac901f21
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/Min.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_MIN_H__
+#define __NEURUN_IR_OPERATION_MIN_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class Min : public Operation
+{
+public:
+  enum Input
+  {
+    LHS = 0,
+    RHS
+  };
+
+public:
+  Min(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::Min; }
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_MIN_H__
diff --git a/runtime/neurun/core/include/ir/operation/Mul.h b/runtime/neurun/core/include/ir/operation/Mul.h
new file mode 100644
index 000000000..f6cfe2afb
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/Mul.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_MUL_H__
+#define __NEURUN_IR_OPERATION_MUL_H__
+
+#include "ir/Operation.h"
+#include "ir/InternalType.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class Mul : public Operation
+{
+public:
+  enum Input
+  {
+    LHS = 0,
+    RHS
+  };
+
+  struct Param
+  {
+    Activation activation;
+  };
+
+public:
+  Mul(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs, const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::Mul; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_MUL_H__
diff --git a/runtime/neurun/core/include/ir/operation/Neg.h b/runtime/neurun/core/include/ir/operation/Neg.h
new file mode 100644
index 000000000..ec364f8ad
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/Neg.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_NEG_H__
+#define __NEURUN_IR_OPERATION_NEG_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class Neg : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0
+  };
+
+public:
+  Neg(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::Neg; }
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_NEG_H__
diff --git a/runtime/neurun/core/include/ir/operation/OneHot.h b/runtime/neurun/core/include/ir/operation/OneHot.h
new file mode 100644
index 000000000..5fbc5d45f
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/OneHot.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_ONEHOT_H__
+#define __NEURUN_IR_OPERATION_ONEHOT_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class OneHot : public Operation
+{
+public:
+  enum Input
+  {
+    INDICES = 0,
+    DEPTH = 1,
+    ON_VALUE = 2,
+    OFF_VALUE = 3,
+  };
+
+  struct Param
+  {
+    int axis;
+  };
+
+public:
+  OneHot(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+         const Param &param);
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::OneHot; }
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_ONEHOT_H__
diff --git a/runtime/neurun/core/include/ir/operation/PReLU.h b/runtime/neurun/core/include/ir/operation/PReLU.h
new file mode 100644
index 000000000..8c00c46fd
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/PReLU.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_PRELU_H__
+#define __NEURUN_IR_OPERATION_PRELU_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class PReLU : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0,
+    ALPHA = 1
+  };
+
+public:
+  PReLU(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::PReLU; }
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_PRELU_H__
diff --git a/runtime/neurun/core/include/ir/operation/Pack.h b/runtime/neurun/core/include/ir/operation/Pack.h
new file mode 100644
index 000000000..ccf73fe5c
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/Pack.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __NEURUN_IR_OPERATION_PACK_H__
+#define __NEURUN_IR_OPERATION_PACK_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+class Pack : public Operation
+{
+public:
+  struct Param
+  {
+    int32_t num;
+    int32_t axis;
+    int32_t rank;
+  };
+
+public:
+  Pack(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs, const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::Pack; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+#endif // __NEURUN_IR_OPERATION_PACK_H__
diff --git a/runtime/neurun/core/include/ir/operation/Pad.h b/runtime/neurun/core/include/ir/operation/Pad.h
new file mode 100644
index 000000000..8e8304fae
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/Pad.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_PAD_H__
+#define __NEURUN_IR_OPERATION_PAD_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class Pad : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0,
+    PAD = 1,
+    // VALUE = 2 Not allow padding value operand yet
+  };
+
+public:
+  struct Param
+  {
+    int32_t rank;
+  };
+
+public:
+  Pad(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs, const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::Pad; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_PAD_H__
diff --git a/runtime/neurun/core/include/ir/operation/Permute.h b/runtime/neurun/core/include/ir/operation/Permute.h
new file mode 100644
index 000000000..f91f9571b
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/Permute.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_PERMUTE_H__
+#define __NEURUN_IR_OPERATION_PERMUTE_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace backend
+{
+class BackendContext;
+} // namespace backend
+} // namespace neurun
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class Permute : public Operation
+{
+public:
+  enum class Type
+  {
+    NHWC_TO_NCHW,
+    NCHW_TO_NHWC,
+    COPY
+  };
+
+  struct Param
+  {
+    const backend::BackendContext *input_backend_ctx;
+    const backend::BackendContext *output_backend_ctx;
+  };
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::Permute; }
+
+public:
+  Permute(const OperandIndex &input, const OperandIndex &output,
+          const backend::BackendContext *input_backend_ctx,
+          const backend::BackendContext *output_backend_ctx, Type type,
+          DataType data_type = DataType::FLOAT32);
+
+public:
+  const Param &param() const { return _param; }
+  DataType getDataType() const { return _dataType; }
+  Type getPermuteType() const { return _type; }
+
+private:
+  Param _param;
+  Type _type;
+  DataType _dataType;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_PERMUTE_H__
diff --git a/runtime/neurun/core/include/ir/operation/RNN.h b/runtime/neurun/core/include/ir/operation/RNN.h
new file mode 100644
index 000000000..d812a6fc3
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/RNN.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __NEURUN_IR_OPERATION_RNN_H__
+#define __NEURUN_IR_OPERATION_RNN_H__
+
+#include "ir/InternalType.h"
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class RNN : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0,
+    WEIGHTS = 1,
+    RECURRENT_WEIGHTS = 2,
+    BIAS = 3,
+    HIDDEN_STATE_IN = 4
+  };
+
+  enum Output
+  {
+    OUTPUT = 0,
+    HIDDEN_STATE_OUT = 1
+  };
+
+  struct Param
+  {
+    Activation activation;
+  };
+
+public:
+  RNN(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs, const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::RNN; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_RNN_H__
diff --git a/runtime/neurun/core/include/ir/operation/RSQRT.h b/runtime/neurun/core/include/ir/operation/RSQRT.h
new file mode 100644
index 000000000..33648555a
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/RSQRT.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_RSQRT_H__
+#define __NEURUN_IR_OPERATION_RSQRT_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class RSQRT : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0
+  };
+
+public:
+  RSQRT(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::RSQRT; }
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_RSQRT_H__
diff --git a/runtime/neurun/core/include/ir/operation/ReLU.h b/runtime/neurun/core/include/ir/operation/ReLU.h
new file mode 100644
index 000000000..b6c7fdf01
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/ReLU.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_RELU_H__
+#define __NEURUN_IR_OPERATION_RELU_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class ReLU : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0
+  };
+
+public:
+  ReLU(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::ReLU; }
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_RELU_H__
diff --git a/runtime/neurun/core/include/ir/operation/ReLU1.h b/runtime/neurun/core/include/ir/operation/ReLU1.h
new file mode 100644
index 000000000..ac45fda05
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/ReLU1.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_ReLU1_H__
+#define __NEURUN_IR_OPERATION_ReLU1_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class ReLU1 : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0
+  };
+
+public:
+  ReLU1(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::ReLU1; }
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_ReLU1_H__
diff --git a/runtime/neurun/core/include/ir/operation/ReLU6.h b/runtime/neurun/core/include/ir/operation/ReLU6.h
new file mode 100644
index 000000000..4d98dad55
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/ReLU6.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_ReLU6_H__
+#define __NEURUN_IR_OPERATION_ReLU6_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class ReLU6 : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0
+  };
+
+public:
+  ReLU6(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::ReLU6; }
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_ReLU6_H__
diff --git a/runtime/neurun/core/include/ir/operation/ReduceMax.h b/runtime/neurun/core/include/ir/operation/ReduceMax.h
new file mode 100644
index 000000000..da4d7c4cc
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/ReduceMax.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_REDUCEMAX_H__
+#define __NEURUN_IR_OPERATION_REDUCEMAX_H__
+
+#include <memory>
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class ReduceMax : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0
+  };
+
+  struct Param
+  {
+    std::vector<int> axes;
+    bool keep_dims;
+    int32_t rank;
+  };
+
+public:
+  ReduceMax(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+            const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::ReduceMax; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_REDUCEMAX_H__
diff --git a/runtime/neurun/core/include/ir/operation/ReduceMin.h b/runtime/neurun/core/include/ir/operation/ReduceMin.h
new file mode 100644
index 000000000..f79fdeaea
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/ReduceMin.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_REDUCEMIN_H__
+#define __NEURUN_IR_OPERATION_REDUCEMIN_H__
+
+#include <memory>
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class ReduceMin : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0
+  };
+
+  struct Param
+  {
+    std::vector<int> axes;
+    bool keep_dims;
+    int32_t rank;
+  };
+
+public:
+  ReduceMin(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+            const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::ReduceMin; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_REDUCEMIN_H__
diff --git a/runtime/neurun/core/include/ir/operation/ReduceSum.h b/runtime/neurun/core/include/ir/operation/ReduceSum.h
new file mode 100644
index 000000000..b5ab8ee75
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/ReduceSum.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_REDUCE_SUM_H__
+#define __NEURUN_IR_OPERATION_REDUCE_SUM_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class ReduceSum : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0
+  };
+
+  struct Param
+  {
+    std::vector<int> axes;
+    bool keep_dims;
+    int32_t rank;
+  };
+
+public:
+  ReduceSum(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+            const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::ReduceSum; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_REDUCE_SUM_H__
diff --git a/runtime/neurun/core/include/ir/operation/Reshape.h b/runtime/neurun/core/include/ir/operation/Reshape.h
new file mode 100644
index 000000000..e476d7fe1
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/Reshape.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_RESHAPE_H__
+#define __NEURUN_IR_OPERATION_RESHAPE_H__
+
+#include <memory>
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class Reshape : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0
+  };
+
+public:
+  Reshape(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::Reshape; }
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_RESHAPE_H__
diff --git a/runtime/neurun/core/include/ir/operation/ResizeBilinear.h b/runtime/neurun/core/include/ir/operation/ResizeBilinear.h
new file mode 100644
index 000000000..d937da00c
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/ResizeBilinear.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_RESIZE_BILINEAR_H__
+#define __NEURUN_IR_OPERATION_RESIZE_BILINEAR_H__
+
+#include <memory>
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class ResizeBilinear : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0
+  };
+
+  struct Param
+  {
+    int32_t height_out;
+    int32_t width_out;
+  };
+
+public:
+  ResizeBilinear(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+                 const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::ResizeBilinear; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_RESIZE_BILINEAR_H__
diff --git a/runtime/neurun/core/include/ir/operation/SQRT.h b/runtime/neurun/core/include/ir/operation/SQRT.h
new file mode 100644
index 000000000..5e21315b4
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/SQRT.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_SQRT_H__
+#define __NEURUN_IR_OPERATION_SQRT_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class SQRT : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0
+  };
+
+public:
+  SQRT(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::SQRT; }
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_SQRT_H__
diff --git a/runtime/neurun/core/include/ir/operation/Slice.h b/runtime/neurun/core/include/ir/operation/Slice.h
new file mode 100644
index 000000000..4b79f42a6
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/Slice.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_SLICE_H__
+#define __NEURUN_IR_OPERATION_SLICE_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class Slice : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0,
+    BEGINS = 1,
+    SIZES = 2,
+  };
+
+public:
+  struct Param
+  {
+    int32_t rank;
+  };
+
+public:
+  Slice(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+        const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::Slice; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_SLICE_H__
diff --git a/runtime/neurun/core/include/ir/operation/Softmax.h b/runtime/neurun/core/include/ir/operation/Softmax.h
new file mode 100644
index 000000000..a3e896fed
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/Softmax.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_SOFTMAX_H__
+#define __NEURUN_IR_OPERATION_SOFTMAX_H__
+
+#include <memory>
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class Softmax : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0
+  };
+
+  struct Param
+  {
+    float beta;
+  };
+
+public:
+  Softmax(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+          const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::Softmax; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_SOFTMAX_H__
diff --git a/runtime/neurun/core/include/ir/operation/SpaceToBatchND.h b/runtime/neurun/core/include/ir/operation/SpaceToBatchND.h
new file mode 100644
index 000000000..4ca0978b0
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/SpaceToBatchND.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_SPACE_TO_BATCH_ND_H__
+#define __NEURUN_IR_OPERATION_SPACE_TO_BATCH_ND_H__
+
+#include <memory>
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class SpaceToBatchND : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0,
+    BLOCK_SIZE = 1,
+    PADDINGS = 2
+  };
+
+public:
+  SpaceToBatchND(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::SpaceToBatchND; }
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_SPACE_TO_BATCH_ND_H__
diff --git a/runtime/neurun/core/include/ir/operation/SpaceToDepth.h b/runtime/neurun/core/include/ir/operation/SpaceToDepth.h
new file mode 100644
index 000000000..9e77bdae0
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/SpaceToDepth.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_SPACE_TO_DEPTH_H__
+#define __NEURUN_IR_OPERATION_SPACE_TO_DEPTH_H__
+
+#include <memory>
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class SpaceToDepth : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0
+  };
+
+  struct Param
+  {
+    std::int32_t block_size;
+  };
+
+public:
+  SpaceToDepth(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+               const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::SpaceToDepth; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_SPACE_TO_DEPTH_H__
diff --git a/runtime/neurun/core/include/ir/operation/Split.h b/runtime/neurun/core/include/ir/operation/Split.h
new file mode 100644
index 000000000..7a2749e84
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/Split.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __NEURUN_IR_OPERATION_SPLIT_H__
+#define __NEURUN_IR_OPERATION_SPLIT_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+class Split : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0
+  };
+
+  struct Param
+  {
+    int axis;
+    int num_splits;
+    int rank;
+  };
+
+public:
+  Split(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+        const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::Split; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+#endif // __NEURUN_IR_OPERATION_SPLIT_H__
diff --git a/runtime/neurun/core/include/ir/operation/SquaredDifference.h b/runtime/neurun/core/include/ir/operation/SquaredDifference.h
new file mode 100644
index 000000000..46df419f5
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/SquaredDifference.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_SQUARED_DIFFERENCE_H__
+#define __NEURUN_IR_OPERATION_SQUARED_DIFFERENCE_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class SquaredDifference : public Operation
+{
+public:
+  enum Input
+  {
+    LHS = 0,
+    RHS
+  };
+
+public:
+  SquaredDifference(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::SquaredDifference; }
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_SQUARED_DIFFERENCE_H__
diff --git a/runtime/neurun/core/include/ir/operation/Squeeze.h b/runtime/neurun/core/include/ir/operation/Squeeze.h
new file mode 100644
index 000000000..d27b315b5
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/Squeeze.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_SQUEEZE_H__
+#define __NEURUN_IR_OPERATION_SQUEEZE_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class Squeeze : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0
+  };
+
+  struct Param
+  {
+    // Please see tensorflow/lite/c/builtin_op_data.h and squeeze.cc.
+    // tensorflow lite supports only for ndim <= 8.
+    int dims[8];
+    int ndim;
+  };
+
+public:
+  Squeeze(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+          const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::Squeeze; }
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_SQUEEZE_H__
diff --git a/runtime/neurun/core/include/ir/operation/StridedSlice.h b/runtime/neurun/core/include/ir/operation/StridedSlice.h
new file mode 100644
index 000000000..868bda72c
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/StridedSlice.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_STRIDED_SLICE_H__
+#define __NEURUN_IR_OPERATION_STRIDED_SLICE_H__
+
+#include <memory>
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class StridedSlice : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0,
+    STARTS = 1,
+    ENDS = 2,
+    STRIDES = 3
+  };
+
+  struct Param
+  {
+    std::int32_t begin_mask;
+    std::int32_t end_mask;
+    std::int32_t shrink_axis_mask;
+    int32_t rank;
+  };
+
+public:
+  StridedSlice(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+               const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::StridedSlice; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_STRIDED_SLICE_H__
diff --git a/runtime/neurun/core/include/ir/operation/Sub.h b/runtime/neurun/core/include/ir/operation/Sub.h
new file mode 100644
index 000000000..e5850af8c
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/Sub.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_SUB_H__
+#define __NEURUN_IR_OPERATION_SUB_H__
+
+#include "ir/Operation.h"
+#include "ir/InternalType.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class Sub : public Operation
+{
+public:
+  enum Input
+  {
+    LHS = 0,
+    RHS
+  };
+
+  struct Param
+  {
+    Activation activation;
+  };
+
+public:
+  Sub(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs, const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::Sub; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_SUB_H__
diff --git a/runtime/neurun/core/include/ir/operation/Tanh.h b/runtime/neurun/core/include/ir/operation/Tanh.h
new file mode 100644
index 000000000..814ceec5a
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/Tanh.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_TANH_H__
+#define __NEURUN_IR_OPERATION_TANH_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class Tanh : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0
+  };
+
+public:
+  Tanh(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::Tanh; }
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_TANH_H__
diff --git a/runtime/neurun/core/include/ir/operation/TopKV2.h b/runtime/neurun/core/include/ir/operation/TopKV2.h
new file mode 100644
index 000000000..a6971e843
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/TopKV2.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_TOPK_V2_H__
+#define __NEURUN_IR_OPERATION_TOPK_V2_H__
+
+#include <memory>
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class TopKV2 : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT
+  };
+
+  enum Output
+  {
+    OUTPUT_VALUES = 0,
+    OUTPUT_INDICES,
+  };
+
+  struct Param
+  {
+    std::int32_t k;
+  };
+
+public:
+  TopKV2(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+         const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::TopKV2; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_TOPK_V2_H__
diff --git a/runtime/neurun/core/include/ir/operation/Transpose.h b/runtime/neurun/core/include/ir/operation/Transpose.h
new file mode 100644
index 000000000..b1e08a506
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/Transpose.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_TRANSPOSE_H__
+#define __NEURUN_IR_OPERATION_TRANSPOSE_H__
+
+#include "ir/Operation.h"
+
+#include <utility>
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class Transpose : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0, // for an n-D tensor, specifying the tensor to be transposed.
+  };
+
+  struct Param
+  {
+    std::vector<int> perm;
+    int32_t rank;
+  };
+
+public:
+  Transpose(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+            const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::Transpose; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_TRANSPOSE_H__
diff --git a/runtime/neurun/core/include/ir/operation/TransposeConv.h b/runtime/neurun/core/include/ir/operation/TransposeConv.h
new file mode 100644
index 000000000..a561db4e4
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/TransposeConv.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_OPERATION_TRANSPOSE_CONV_H__
+#define __NEURUN_IR_OPERATION_TRANSPOSE_CONV_H__
+
+#include <memory>
+
+#include "ir/Operation.h"
+#include "ir/InternalType.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+class TransposeConv : public Operation
+{
+public:
+  enum Input
+  {
+    OUTPUT_SHAPE = 0,
+    KERNEL,
+    INPUT
+  };
+
+  struct Param
+  {
+    Padding padding;
+    Stride stride;
+  };
+
+public:
+  TransposeConv(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+                const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::TransposeConv; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_OPERATION_TRANSPOSE_CONV_H__
diff --git a/runtime/neurun/core/include/ir/operation/Unpack.h b/runtime/neurun/core/include/ir/operation/Unpack.h
new file mode 100644
index 000000000..fa698d3af
--- /dev/null
+++ b/runtime/neurun/core/include/ir/operation/Unpack.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __NEURUN_IR_OPERATION_UNPACK_H__
+#define __NEURUN_IR_OPERATION_UNPACK_H__
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+class Unpack : public Operation
+{
+public:
+  enum Input
+  {
+    INPUT = 0
+  };
+
+  struct Param
+  {
+    int32_t num;
+    int32_t axis;
+    int32_t rank;
+  };
+
+public:
+  Unpack(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+         const Param &param);
+
+public:
+  void accept(OperationVisitor &v) const override;
+  OpCode opcode() const final { return OpCode::Unpack; }
+
+public:
+  const Param &param() const { return _param; }
+
+private:
+  Param _param;
+};
+} // namespace operation
+} // namespace ir
+} // namespace neurun
+#endif // __NEURUN_IR_OPERATION_UNPACK_H__
diff --git a/runtime/neurun/core/include/util/Config.lst b/runtime/neurun/core/include/util/Config.lst
new file mode 100644
index 000000000..046a0c4a8
--- /dev/null
+++ b/runtime/neurun/core/include/util/Config.lst
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef CONFIG
+#error  Define CONFIG before including this file
+#endif
+
+//     Name                    | Type         | Default
+CONFIG(GRAPH_DOT_DUMP          , int          , "0")
+CONFIG(BACKENDS                , std::string  , "acl_cl;acl_neon;cpu;srcn")
+CONFIG(OP_BACKEND_ALLOPS       , std::string  , "")
+CONFIG(OP_BACKEND_MAP          , std::string  , "")
+CONFIG(DISABLE_COMPILE         , bool         , "0")
+CONFIG(NEURUN_LOG_ENABLE       , bool         , "0")
+CONFIG(CPU_MEMORY_PLANNER      , std::string  , "WIC")
+CONFIG(EXECUTOR                , std::string  , "Linear")
+CONFIG(ACL_LAYOUT              , std::string  , "none")
+CONFIG(NCNN_LAYOUT             , std::string  , "NCHW")
+CONFIG(PROFILING_MODE          , bool         , "0")
+CONFIG(USE_SCHEDULER           , bool         , "0")
+CONFIG(SUBG_MAX_NODE           , int          , "0")
+CONFIG(TRACE_FILEPATH          , std::string  , "")
+
+// Auto-generate all operations
+
+#define OP(InternalName) \
+    CONFIG(OP_BACKEND_ ## InternalName, std::string, "")
+#include "ir/Operations.lst"
+#undef OP
+
diff --git a/runtime/neurun/core/include/util/ConfigSource.h b/runtime/neurun/core/include/util/ConfigSource.h
new file mode 100644
index 000000000..b1fa9a87d
--- /dev/null
+++ b/runtime/neurun/core/include/util/ConfigSource.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_UTIL_CONFIG_SOURCE_H__
+#define __NEURUN_UTIL_CONFIG_SOURCE_H__
+
+#include <memory>
+
+#include "IConfigSource.h"
+
+namespace neurun
+{
+namespace util
+{
+
+void config_source(std::unique_ptr<IConfigSource> &&source);
+
+bool getConfigBool(const std::string &key);
+int getConfigInt(const std::string &key);
+std::string getConfigString(const std::string &key);
+
+} // namespace util
+} // namespace neurun
+
+namespace neurun
+{
+namespace util
+{
+namespace config
+{
+
+#define CONFIG(Name, Type, Default) extern const char *Name;
+
+#include "Config.lst"
+
+#undef CONFIG
+
+} // namespace config
+} // namespace util
+} // namespace neurun
+
+#endif // __NEURUN_UTIL_CONFIG_SOURCE_H__
diff --git a/runtime/neurun/core/include/util/Coordinates.h b/runtime/neurun/core/include/util/Coordinates.h
new file mode 100644
index 000000000..67947138f
--- /dev/null
+++ b/runtime/neurun/core/include/util/Coordinates.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_UTIL_COORDINATES_H__
+#define __NEURUN_UTIL_COORDINATES_H__
+
+#include <cassert>
+#include <stdint.h>
+#include <vector>
+
+namespace neurun
+{
+namespace util
+{
+
+/**
+ * @brief Class to represent position(offset) of tensor.\n
+ *        Assume that the front is higher dimensional.
+ *        i.g. N: 0, C: 1, H: 2, W: 3 for NCHW layout
+ */
+class Coordinates final
+{
+public:
+  static constexpr size_t num_max_dimensions = 4;
+
+public:
+  /**
+   * @brief     Construct a new Coordinates object
+   * @param[in] init The initialzer_list with coordinates
+   * @return
+   */
+  Coordinates(std::initializer_list<int32_t> init) : _coordinates{init}
+  {
+    assert(init.size() <= num_max_dimensions);
+  }
+
+public:
+  /**
+   * @brief  Set the coordinate of one of the coordinates.
+   *
+   * @param[in] dimension  Dimension for which the coordinate is set.
+   * @param[in] Coordinate Coordinate to be set for the dimension.
+   */
+  void set(size_t dimension, int32_t coordinate)
+  {
+    assert(dimension < num_max_dimensions);
+    if (dimension >= _coordinates.size())
+    {
+      _coordinates.resize(dimension + 1, 0);
+    }
+    _coordinates[dimension] = coordinate;
+  }
+
+public:
+  /**
+   * @brief Return size of coordinates
+   *
+   * @return size of coordinates
+   */
+  size_t size() const { return _coordinates.size(); }
+
+public:
+  int32_t operator[](size_t dimension) const
+  {
+    assert(dimension < _coordinates.size());
+    return _coordinates[dimension];
+  }
+
+public:
+  /**
+   * @brief begin() of const_iterator for this class
+   *
+   * @return The first iterator of the coordinates
+   */
+  std::vector<int32_t>::const_iterator begin() const { return _coordinates.begin(); }
+  /**
+   * @brief end() of const_iterator for this class
+   *
+   * @return The last iterator of the coordinates
+   */
+  std::vector<int32_t>::const_iterator end() const { return _coordinates.end(); }
+
+private:
+  std::vector<int32_t> _coordinates;
+};
+
+} // namespace util
+} // namespace neurun
+
+#endif // __NEURUN_UTIL_COORDINATES_H__
diff --git a/runtime/neurun/core/include/util/EnvConfigSource.h b/runtime/neurun/core/include/util/EnvConfigSource.h
new file mode 100644
index 000000000..77be15c4e
--- /dev/null
+++ b/runtime/neurun/core/include/util/EnvConfigSource.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_UTIL_ENV_CONFIG_SOURCE_H__
+#define __NEURUN_UTIL_ENV_CONFIG_SOURCE_H__
+
+#include <unordered_map>
+
+#include "util/GeneralConfigSource.h"
+
+namespace neurun
+{
+namespace util
+{
+
+class EnvConfigSource final : public GeneralConfigSource
+{
+public:
+  std::string get(const std::string &key) const override;
+
+private:
+  std::unordered_map<std::string, std::string> _default_attributes;
+};
+
+} // namespace util
+} // namespace neurun
+
+#endif // __NEURUN_UTIL_ENV_CONFIG_SOURCE_H__
diff --git a/runtime/neurun/core/include/util/EventCollectorGlobal.h b/runtime/neurun/core/include/util/EventCollectorGlobal.h
new file mode 100644
index 000000000..15e40844e
--- /dev/null
+++ b/runtime/neurun/core/include/util/EventCollectorGlobal.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_UTIL_EVENT_COLLECTOR_GLOBAL_H__
+#define __NEURUN_UTIL_EVENT_COLLECTOR_GLOBAL_H__
+
+#include "misc/EventRecorder.h"
+#include "misc/EventCollector.h"
+
+namespace neurun
+{
+namespace util
+{
+
+/**
+ * @brief Singleton class for event collection from anywhere in code
+ *
+ */
+class EventCollectorGlobal
+{
+public:
+  /**
+   * @brief Get the singleton object of this class
+   *
+   * @return EventCollectorGlobal& Singleton object
+   */
+  static EventCollectorGlobal &get();
+
+public:
+  /**
+   * @brief Getter for event collector object
+   *
+   * @return EventCollector& Collector object
+   */
+  EventCollector &collector() { return _collector; }
+
+private:
+  EventCollectorGlobal();
+  ~EventCollectorGlobal();
+
+private:
+  EventRecorder _recorder;
+  EventCollector _collector;
+};
+
+/**
+ * @brief Helper class for emitting duration event which is handled automatically with ctor/dtor
+ *
+ */
+class EventDurationBlock
+{
+public:
+  /**
+   * @brief Raise a duration event with type of BEGIN
+   *
+   * @param tag A label for the duration event
+   */
+  EventDurationBlock(const std::string &tag);
+  /**
+   * @brief Raise a duration event with type of END
+   *
+   */
+  ~EventDurationBlock();
+
+private:
+  std::string _tag;
+};
+
+/**
+ * @brief Helper class for emitting duration event which is handled manually
+ *
+ *        Usage:
+ *        {
+ *          ...
+ *          EventDurationManual duration("some tag");
+ *          duration.begin();
+ *          ...
+ *          ... // Code for duration
+ *          ...
+ *          duration.end();
+ *        }
+ *
+ */
+class EventDurationManual
+{
+public:
+  /**
+   * @brief Construct a new Event Duration Manual object
+   *
+   * @param tag A label for the duration object
+   */
+  EventDurationManual(const std::string &tag);
+  /**
+   * @brief Destroy the Event Duration Manual object
+   *
+   */
+  ~EventDurationManual();
+
+  /**
+   * @brief Raise a duration event with type of BEGIN
+   *
+   */
+  void begin();
+  /**
+   * @brief Raise a duration event with type of END
+   *
+   */
+  void end();
+
+private:
+  std::string _tag;
+  bool _pair;
+};
+
+} // namespace util
+} // namespace neurun
+
+/**
+ * Helper Macro Definitions
+ *
+ * HOW TO USE
+ *
+ * void f(args)
+ * {
+ *   EVENT_DURATION_FUNCTION();
+ *   ...
+ *   if(cond)
+ *   {
+ *     EVENT_DURATION_REGION("if branch");
+ *     ...
+ *   }
+ *   ...
+ * }
+ */
+
+#define EVENT_DURATION_FUNCTION() \
+  ::neurun::util::EventDurationBlock __event_duration__##__LINE__ { __FUNCTION__ }
+
+#define EVENT_DURATION_REGION(tag) \
+  ::neurun::util::EventDurationBlock __event_duration__##__LINE__ { tag }
+
+#endif // __NEURUN_UTIL_EVENT_COLLECTOR_GLOBAL_H__
diff --git a/runtime/neurun/core/include/util/GeneralConfigSource.h b/runtime/neurun/core/include/util/GeneralConfigSource.h
new file mode 100644
index 000000000..04e3332b3
--- /dev/null
+++ b/runtime/neurun/core/include/util/GeneralConfigSource.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_UTIL_GLOBAL_CONFIG_SOURCE_H__
+#define __NEURUN_UTIL_GLOBAL_CONFIG_SOURCE_H__
+
+#include <unordered_map>
+
+#include "util/IConfigSource.h"
+
+namespace neurun
+{
+namespace util
+{
+
+class GeneralConfigSource : public IConfigSource
+{
+public:
+  GeneralConfigSource() = default;
+
+  std::string get(const std::string &key) const override;
+  void set(const std::string &key, const std::string &val);
+
+private:
+  std::unordered_map<std::string, std::string> _map;
+};
+
+} // namespace util
+} // namespace neurun
+
+#endif // __NEURUN_UTIL_GLOBAL_CONFIG_SOURCE_H__
diff --git a/runtime/neurun/core/include/util/IConfigSource.h b/runtime/neurun/core/include/util/IConfigSource.h
new file mode 100644
index 000000000..a52d87097
--- /dev/null
+++ b/runtime/neurun/core/include/util/IConfigSource.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_UTIL_I_CONFIG_SOURCE_H__
+#define __NEURUN_UTIL_I_CONFIG_SOURCE_H__
+
+#include <string>
+
+namespace neurun
+{
+namespace util
+{
+
+struct IConfigSource
+{
+  /**
+   * @brief Destroy the IConfigSource object
+   */
+  virtual ~IConfigSource() = default;
+
+  /**
+   * @brief get the value for the matching key
+   *
+   * @param key string key to search
+   * @return string value associated with the key
+   */
+  virtual std::string get(const std::string &key) const = 0;
+};
+
+} // namespace util
+} // namespace neurun
+
+#endif // __NEURUN_UTIL_I_CONFIG_SOURCE_H__
diff --git a/runtime/neurun/core/include/util/ITimer.h b/runtime/neurun/core/include/util/ITimer.h
new file mode 100644
index 000000000..79ecdd0ca
--- /dev/null
+++ b/runtime/neurun/core/include/util/ITimer.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_UTIL_ITIMER_H__
+#define __NEURUN_UTIL_ITIMER_H__
+
+#include <chrono>
+
+namespace neurun
+{
+namespace util
+{
+
+class ITimer
+{
+public:
+  virtual void handleBegin() = 0;
+  virtual void handleEnd() = 0;
+  int getTime() { return _timer_res; };
+
+  virtual ~ITimer() = default;
+
+protected:
+  int _timer_res{0};
+};
+
+class CPUTimer : public ITimer
+{
+public:
+  void handleBegin() override { _start_time = std::chrono::steady_clock::now(); };
+
+  void handleEnd() override
+  {
+    const auto end_time = std::chrono::steady_clock::now();
+    _timer_res =
+        std::chrono::duration_cast<std::chrono::microseconds>(end_time - _start_time).count();
+  };
+
+private:
+  std::chrono::steady_clock::time_point _start_time; // in microseconds
+};
+
+} // namespace util
+} // namespace neurun
+
+#endif // __NEURUN_UTIL_ITIMER_H__
diff --git a/runtime/neurun/core/include/util/Index.h b/runtime/neurun/core/include/util/Index.h
new file mode 100644
index 000000000..bd8eeb38c
--- /dev/null
+++ b/runtime/neurun/core/include/util/Index.h
@@ -0,0 +1,154 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_UTIL_INDEX_H__
+#define __NEURUN_UTIL_INDEX_H__
+
+#include <functional>
+#include <limits>
+#include <stdint.h>
+
+namespace neurun
+{
+namespace util
+{
+
+/**
+ * @brief A wrapper class for unsigned integral Index
+ *        NOTE : Max value of the underlying type is used as the invalid value
+ *
+ * @tparam T Underlying type. Must be unsigned integral type otherwise its behavior is undefined.
+ * @tparam DummyTag Dummy type to distinguish types with a same underlying type. Using an opaque
+ * type is recommended.
+ */
+template <typename T, typename DummyTag> class Index
+{
+private:
+  static const T UNDEFINED = std::numeric_limits<T>::max();
+
+public:
+  /**
+   * @brief Construct a new Index object
+   */
+  explicit Index(void) : _index{UNDEFINED} {}
+  /**
+   * @brief Construct a new Index object with a value in the underlying type
+   *
+   * @param o Value in the underlying type
+   */
+  explicit Index(const T o) : _index{o} {}
+  /**
+   * @brief Copy Constructor
+   *
+   * @param o Object to be copied
+   */
+  Index(const Index &o) = default;
+
+  /**
+   * @brief Assign a value in the underlying time
+   *
+   * @param o Value in the underlying type
+   * @return Index& Reference of this pointer
+   */
+  Index &operator=(const T o)
+  {
+    _index = o;
+    return *this;
+  }
+
+  /**
+   * @brief Copy assignment operator
+   *
+   * @param o Object to be copied
+   * @return Index& Reference of this pointer
+   */
+  Index &operator=(const Index &o) = default;
+
+  /**
+   * @brief Equality operator
+   *
+   * @param o The other value in the underlying type to compare
+   * @return true if underlying value is the same, false otherwise
+   */
+  bool operator==(T o) const { return _index == o; }
+  /**
+   * @brief Equality operator
+   *
+   * @param o The other object to compare
+   * @return true if underlying value is the same, false otherwise
+   */
+  bool operator==(const Index &o) const { return _index == o._index; }
+  /**
+   * @brief Inquality operator
+   *
+   * @param o The other value in the underlying type to compare
+   * @return true if underlying value is different, false otherwise
+   */
+  bool operator!=(T o) const { return !(*this == o); }
+  /**
+   * @brief Inquality operator
+   *
+   * @param o The other object to compare
+   * @return true if underlying value is different, false otherwise
+   */
+  bool operator!=(const Index &o) const { return !(*this == o); }
+
+  /**
+   * @brief Post increment operator
+   *
+   * @return Index Index before increment
+   */
+  Index operator++(int)
+  {
+    Index temp = *this;
+    _index++;
+    return temp;
+  }
+
+  /**
+   * @brief Check whether the value is valid or not
+   *
+   * @return true if valid, false otherwise
+   */
+  bool valid() const { return _index != UNDEFINED; }
+  /**
+   * @brief Return underlying value
+   *
+   * @return T Underlying value
+   */
+  T value() const { return _index; }
+
+private:
+  T _index;
+};
+
+} // namespace util
+} // namespace neurun
+
+namespace std
+{
+
+template <typename T, typename Tag> struct hash<::neurun::util::Index<T, Tag>>
+{
+  size_t operator()(const ::neurun::util::Index<T, Tag> &index) const noexcept
+  {
+    return hash<T>()(index.value());
+  }
+};
+
+} // namespace std
+
+#endif // __NEURUN_UTIL_INDEX_H__
diff --git a/runtime/neurun/core/include/util/ObjectManager.h b/runtime/neurun/core/include/util/ObjectManager.h
new file mode 100644
index 000000000..fd2c3f295
--- /dev/null
+++ b/runtime/neurun/core/include/util/ObjectManager.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_UTIL_OBJECT_MANAGER_H__
+#define __NEURUN_UTIL_OBJECT_MANAGER_H__
+
+#include <unordered_map>
+#include <memory>
+
+namespace neurun
+{
+namespace util
+{
+
+/**
+ * @brief Class that owns objects and maps them with indices as a handle for them
+ *
+ */
+template <typename Index, typename Object> class ObjectManager
+{
+public:
+  ObjectManager() : _index_count{0u} {}
+
+public:
+  /**
+   * @brief Create an object with args and put it in the container with a new Index for that
+   *
+   * @param[in] args Arguments for creating Operand object
+   * @return Created index that is associated to the object
+   */
+  template <class... Args> Index emplace(Args &&... args)
+  {
+    auto index = generateIndex();
+    _objects.emplace(index, nnfw::cpp14::make_unique<Object>(std::forward<Args>(args)...));
+    return index;
+  }
+
+  /**
+   * @brief Put object in the container with a new Index for that
+   *
+   * @param[in] object Object to be pushed
+   * @return Created index that is associated to the object
+   */
+  Index push(std::unique_ptr<Object> &&object)
+  {
+    auto index = generateIndex();
+    _objects.emplace(index, std::move(object));
+    return index;
+  }
+
+  /**
+   * @brief Remove the object that is associated with the given index
+   *
+   * @param[in] index Index of the object to be removed
+   * @return N/A
+   */
+  void remove(const Index &index) { _objects.erase(index); };
+
+  /**
+   * @brief Get the object that is associated with the given index
+   *
+   * @param[in] index Index of the object to be returned
+   * @return Object
+   */
+  const Object &at(const Index &index) const { return *(_objects.at(index)); }
+  /**
+   * @brief Get the object that is associated with the given index
+   *
+   * @param[in] index Index of the object to be returned
+   * @return Object
+   */
+  Object &at(const Index &index) { return *(_objects.at(index)); }
+  /**
+   * @brief Get the object that is associated with the given index
+   *
+   * @param[in] index Index of the object to be returned
+   * @return true if such entry exists otherwise false
+   */
+  bool exist(const Index &index) const
+  {
+    auto it = _objects.find(index);
+    return it != _objects.end();
+  }
+  /**
+   * @brief Iterate over the container with given function
+   *
+   * @param[in] fn Function to be run for every container entry
+   * @return N/A
+   */
+  void iterate(const std::function<void(const Index &, const Object &)> &fn) const
+  {
+    for (const auto &e : _objects)
+    {
+      fn(e.first, *e.second);
+    }
+  }
+  /**
+   * @brief Iterate over the container with given function
+   *
+   * @param[in] fn Function to be run for every container entry
+   * @return N/A
+   */
+  void iterate(const std::function<void(const Index &, Object &)> &fn)
+  {
+    // TODO Remove this workaround
+    // This implementation is a workaround in case of adding operands while iteration
+    std::list<Index> l;
+
+    for (auto &e : _objects)
+    {
+      l.push_back(e.first);
+    }
+
+    for (auto index : l)
+    {
+      fn(index, *_objects[index]);
+    }
+  }
+
+private:
+  Index generateIndex() { return Index{_index_count++}; }
+
+private:
+  std::unordered_map<Index, std::unique_ptr<Object>> _objects;
+  uint32_t _index_count;
+};
+
+} // namespace util
+} // namespace neurun
+
+#endif // __NEURUN_UTIL_OBJECT_MANAGER_H__
diff --git a/runtime/neurun/core/include/util/Padding.h b/runtime/neurun/core/include/util/Padding.h
new file mode 100644
index 000000000..3c707b873
--- /dev/null
+++ b/runtime/neurun/core/include/util/Padding.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_UTIL_PADDING_H__
+#define __NEURUN_UTIL_PADDING_H__
+
+#include <stdint.h>
+
+#include "ir/Shape.h"
+#include "ir/InternalType.h"
+
+namespace neurun
+{
+namespace util
+{
+
+ir::ExplicitPadding validPadding(void);
+ir::ExplicitPadding samePadding(const ir::FeatureShape &ifm_shape,
+                                const ir::FeatureShape &ofm_shape, const ir::Stride &stride,
+                                uint32_t kw, uint32_t kh);
+ir::ExplicitPadding calculatePadding(const ir::Padding &padding, const ir::FeatureShape &ifm_shape,
+                                     const ir::FeatureShape &ofm_shape, const ir::Stride &stride,
+                                     uint32_t kw, uint32_t kh);
+
+} // namespace util
+} // namespace neurun
+
+#endif // __NEURUN_UTIL_PADDING_H__
diff --git a/runtime/neurun/core/include/util/Set.h b/runtime/neurun/core/include/util/Set.h
new file mode 100644
index 000000000..13213511d
--- /dev/null
+++ b/runtime/neurun/core/include/util/Set.h
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     Set.h
+ * @brief    This file contains neurun::util::Set class
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NEURUN_UTIL_SET_H__
+#define __NEURUN_UTIL_SET_H__
+
+#include <cassert>
+#include <unordered_set>
+
+namespace neurun
+{
+namespace util
+{
+
+/**
+ * @brief Class for set of custom element
+ & @tparam Element  Key type of Set
+ */
+template <typename Element> class Set
+{
+public:
+  /**
+   * @brief Construct default Set object.
+   */
+  Set() = default;
+  /**
+   * @brief Construct Set object by copy semantics.
+   */
+  Set(const Set<Element> &) = default;
+  /**
+   * @brief Construct move Set object by move semantics.
+   */
+  Set(Set<Element> &&) = default;
+
+public:
+  /**
+   * @brief Add a given element to the set
+   *
+   * @param e Element added
+   */
+  void add(const Element &e) { _set.insert(e); }
+  /**
+   * @brief remove a given element from the set
+   *
+   * @param e Element removed
+   */
+  void remove(const Element &e) { _set.erase(e); }
+  /**
+   * @brief Get size of the set
+   *
+   * @return The size of the set
+   */
+  uint32_t size() const { return static_cast<uint32_t>(_set.size()); }
+  /**
+   * @brief Get whether the set is empty
+   *
+   * @return Whether the set is empty
+   */
+  bool empty() const { return _set.empty(); }
+  /**
+   * @brief Get whether a given element exists in the set
+   *
+   * @param e A given element
+   *
+   * @return Whether a given element exists in the set
+   */
+  bool contains(const Element &e) const { return _set.find(e) != _set.end(); }
+  /**
+   * @brief Get first element of the set
+   *
+   * @return first element of the set
+   */
+  const Element &getOnlyElement() const
+  {
+    assert(_set.size() == 1u);
+    return *_set.begin();
+  }
+
+public:
+  /**
+   * @brief operator overloading function for `|`
+   *
+   * @return A set with two sets combined
+   */
+  Set<Element> operator|(const Set<Element> &other) const // Union
+  {
+    auto ret = *this;
+    for (auto e : other)
+    {
+      ret.add(e);
+    }
+    return ret;
+  }
+  /**
+   * @brief operator overloading function for `&`
+   *
+   * @return A set of elements that overlap in two sets
+   */
+  Set<Element> operator&(const Set<Element> &other) const // Intersect
+  {
+    Set<Element> ret;
+    for (auto e : other)
+    {
+      if (contains(e))
+      {
+        ret.add(e);
+      }
+    }
+    return ret;
+  }
+  /**
+   * @brief operator overloading function for `-`
+   *
+   * @return A set of subtracted from another set
+   */
+  Set<Element> operator-(const Set<Element> &other) const // Minus
+  {
+    auto ret = *this;
+    for (auto e : other)
+    {
+      ret.remove(e);
+    }
+    return ret;
+  }
+
+public:
+  /**
+   * @brief begin() of const_iterator for this class
+   *
+   * @return The first iterator of the set
+   */
+  typename std::unordered_set<Element>::const_iterator begin() const { return _set.begin(); }
+  /**
+   * @brief end() of const_iterator for this class
+   *
+   * @return The last iterator of the set
+   */
+  typename std::unordered_set<Element>::const_iterator end() const { return _set.end(); }
+
+private:
+  std::unordered_set<Element> _set;
+};
+
+} // namespace util
+} // namespace neurun
+
+#endif // __NEURUN_UTIL_SET_H__
diff --git a/runtime/neurun/core/include/util/ShapeInference.h b/runtime/neurun/core/include/util/ShapeInference.h
new file mode 100644
index 000000000..097d61643
--- /dev/null
+++ b/runtime/neurun/core/include/util/ShapeInference.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_GRAPH_SHAPE_INFERENCE_H__
+#define __NEURUN_GRAPH_SHAPE_INFERENCE_H__
+
+#include "ir/operation/AvgPool2D.h"
+#include "ir/operation/Concat.h"
+#include "ir/operation/MaxPool2D.h"
+#include "ir/operation/Conv2D.h"
+#include "ir/operation/DepthwiseConv2D.h"
+#include "ir/Operands.h"
+#include "ir/Index.h"
+#include "ir/Layout.h"
+
+namespace neurun
+{
+namespace shape_inference
+{
+
+using Shapes = std::vector<ir::Shape>;
+
+Shapes inferEltwiseShape(const ir::Shape &lhs_shape, const ir::Shape &rhs_shape);
+
+Shapes inferAvgPoolShape(const ir::Shape &in_shape, const ir::operation::AvgPool2D::Param &param,
+                         ir::Layout layout = ir::Layout::NHWC);
+
+Shapes inferConcatShape(const Shapes &in_shapes, const ir::operation::Concat::Param &param);
+
+Shapes inferMaxPoolShape(const ir::Shape &in_shape, const ir::operation::MaxPool2D::Param &param,
+                         ir::Layout layout = ir::Layout::NHWC);
+
+Shapes inferConv2DShape(const ir::Shape &in_shape, const ir::Shape &ker_shape,
+                        const ir::operation::Conv2D::Param &param,
+                        ir::Layout layout = ir::Layout::NHWC);
+
+Shapes inferDepthwiseConv2DShape(const ir::Shape &in_shape, const ir::Shape &ker_shape,
+                                 const ir::operation::DepthwiseConv2D::Param &param,
+                                 ir::Layout layout = ir::Layout::NHWC);
+
+Shapes inferFullyConnectedShape(const ir::Shape &in_shape, const ir::Shape &ker_shape);
+
+} // namespace shape_inference
+} // namespace neurun
+
+#endif // __NEURUN_GRAPH_SHAPE_INFERENCE_H__
diff --git a/runtime/neurun/core/include/util/Utils.h b/runtime/neurun/core/include/util/Utils.h
new file mode 100644
index 000000000..e7468dabd
--- /dev/null
+++ b/runtime/neurun/core/include/util/Utils.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     Utils.h
+ * @brief    This file contains utility functions
+ * @ingroup  COM_AI_RUNTIME
+ */
+
+#ifndef __NEURUN_UTIL_UTILS_H__
+#define __NEURUN_UTIL_UTILS_H__
+
+#include "ir/InternalType.h"
+#include "ir/Layout.h"
+#include "ir/Operand.h"
+#include "util/Coordinates.h"
+
+#define UNUSED_RELEASE(a) (void)(a)
+
+namespace neurun
+{
+namespace util
+{
+
+/**
+ * @brief Converts a internal padding type to const char*
+ * @param[in] type Padding type to be converted
+ * @return A string holding the converted value
+ */
+const char *to_string(ir::PaddingType type);
+
+Coordinates convertCoordinates(const Coordinates &from_coordinates, ir::Layout from_layout,
+                               ir::Layout to_layout);
+
+} // namespace util
+} // namespace neurun
+
+#endif // __NEURUN_UTIL_UTILS_H__
diff --git a/runtime/neurun/core/include/util/feature/Coordinate4D.h b/runtime/neurun/core/include/util/feature/Coordinate4D.h
new file mode 100644
index 000000000..b020ed239
--- /dev/null
+++ b/runtime/neurun/core/include/util/feature/Coordinate4D.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_UTIL_FEATURE_COORDINATE_4D_H__
+#define __NEURUN_UTIL_FEATURE_COORDINATE_4D_H__
+
+#include <stdint.h>
+
+namespace neurun
+{
+namespace util
+{
+namespace feature
+{
+
+/**
+ * @brief Class to represent position(offset) of subtensor.\n
+ *        Assume that parent and child are already lowered (can get Shape4D).
+ */
+class Coordinate4D
+{
+public:
+  /**
+   * @brief Construct a new Coordinate4D object
+   */
+  Coordinate4D(void) : _n{0}, _h{0}, _w{0}, _c{0}
+  {
+    // DO NOTHING
+  }
+  /**
+   * @brief     Construct a new Coordinate4D object
+   * @param[in] n Batch offset
+   * @param[in] h Height offset
+   * @param[in] w Width offset
+   * @param[in] c Channel offset
+   * @return
+   */
+  Coordinate4D(int32_t n, int32_t h, int32_t w, int32_t c) : _n{n}, _h{h}, _w{w}, _c{c}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief   Set batch offset
+   * @param[in] n Batch offset
+   */
+  void n(int32_t n) { _n = n; }
+  /**
+   * @brief   Set height offset
+   * @param[in] h Height offset
+   */
+  void h(int32_t h) { _h = h; }
+  /**
+   * @brief   Set width offset
+   * @param[in] w Width offset
+   */
+  void w(int32_t w) { _w = w; }
+  /**
+   * @brief   Set channel offset
+   * @param[in] c Channel offset
+   */
+  void c(int32_t c) { _c = c; }
+
+public:
+  /**
+   * @brief   Return batch offset
+   * @return  Batch offset
+   */
+  int32_t n(void) const { return _n; }
+  /**
+   * @brief   Return height offset
+   * @return  Height offset
+   */
+  int32_t h(void) const { return _h; }
+  /**
+   * @brief   Return width offset
+   * @return  Width offset
+   */
+  int32_t w(void) const { return _w; }
+  /**
+   * @brief   Return channel offset
+   * @return  Channel offset
+   */
+  int32_t c(void) const { return _c; }
+
+private:
+  int32_t _n;
+  int32_t _h;
+  int32_t _w;
+  int32_t _c;
+};
+
+} // namespace feature
+} // namespace util
+} // namespace neurun
+
+#endif // __NEURUN_UTIL_FEATURE_COORDINATE_4D_H__
diff --git a/runtime/neurun/core/include/util/feature/nchw/Reader.h b/runtime/neurun/core/include/util/feature/nchw/Reader.h
new file mode 100644
index 000000000..0305bdf69
--- /dev/null
+++ b/runtime/neurun/core/include/util/feature/nchw/Reader.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_UTIL_FEATURE_NCHW_READER_H__
+#define __NEURUN_UTIL_FEATURE_NCHW_READER_H__
+
+#include <cassert>
+
+#include "backend/operand/ITensor.h"
+#include "misc/feature/Reader.h"
+#include "misc/feature/Shape.h"
+#include "util/Coordinates.h"
+#include "util/Utils.h"
+
+namespace neurun
+{
+namespace util
+{
+namespace feature
+{
+namespace nchw
+{
+
+template <typename T> class Reader final : public nnfw::misc::feature::Reader<T>
+{
+public:
+  // Construct for buffer of model inputs
+  Reader(const ::nnfw::misc::feature::Shape &shape, const T *ptr, size_t len)
+      : _shape{shape}, _ptr{reinterpret_cast<const uint8_t *>(ptr)}, _len{len}
+  {
+    assert(shape.N * shape.C * shape.H * shape.W * sizeof(T) == len);
+
+    // No padding
+    _strides.W = sizeof(T);
+    _strides.H = shape.W * sizeof(T);
+    _strides.C = shape.W * shape.H * sizeof(T);
+    _strides.N = shape.W * shape.H * shape.C * sizeof(T);
+  }
+
+  // Construct for backend tensor
+  Reader(backend::operand::ITensor *tensor)
+      : _ptr{tensor->buffer() + tensor->calcOffset({0, 0, 0, 0})}, _len{tensor->total_size()}
+  {
+    assert(tensor->layout() == ir::Layout::NCHW);
+
+    const auto start_offset = tensor->calcOffset({0, 0, 0, 0});
+    _strides.W = tensor->dimension(3) == 1 ? 0 : tensor->calcOffset({0, 0, 0, 1}) - start_offset;
+    _strides.H = tensor->dimension(2) == 1 ? 0 : tensor->calcOffset({0, 0, 1, 0}) - start_offset;
+    _strides.C = tensor->dimension(1) == 1 ? 0 : tensor->calcOffset({0, 1, 0, 0}) - start_offset;
+    _strides.N = tensor->dimension(0) == 1 ? 0 : tensor->calcOffset({1, 0, 0, 0}) - start_offset;
+
+    _shape.W = tensor->dimension(3);
+    _shape.H = tensor->dimension(2);
+    _shape.C = tensor->dimension(1);
+    _shape.N = tensor->dimension(0);
+  }
+
+public:
+  T at(uint32_t ch, uint32_t row, uint32_t col) const override
+  {
+    const auto offset = feature_index_to_byte_offset(0, ch, row, col);
+
+    const T *ptr = reinterpret_cast<const T *>(_ptr + offset);
+
+    return *ptr;
+  }
+  T at(uint32_t batch, uint32_t ch, uint32_t row, uint32_t col) const override
+  {
+    const auto offset = feature_index_to_byte_offset(batch, ch, row, col);
+
+    const T *ptr = reinterpret_cast<const T *>(_ptr + offset);
+
+    return *ptr;
+  }
+
+private:
+  size_t feature_index_to_byte_offset(uint32_t batch, uint32_t ch, uint32_t row, uint32_t col) const
+  {
+    assert(1u * _shape.N > batch); // shape.N > batch
+    assert(1u * _shape.C > ch);    // shape.C > ch
+    assert(1u * _shape.H > row);   // shape.H > row
+    assert(1u * _shape.W > col);   // shape.W > col
+
+    uint32_t res = 0;
+    res += batch * _strides.N;
+    res += ch * _strides.C;
+    res += row * _strides.H;
+    res += col * _strides.W;
+
+    return res;
+  }
+
+private:
+  // TODO Remove _shape
+  nnfw::misc::feature::Shape _shape;
+  using Strides = nnfw::misc::feature::Shape;
+  Strides _strides;
+  const uint8_t *_ptr;
+  size_t _len;
+};
+
+} // namespace nchw
+} // namespace feature
+} // namespace util
+} // namespace neurun
+
+#endif // __NEURUN_UTIL_FEATURE_NCHW_READER_H__
diff --git a/runtime/neurun/core/include/util/feature/nchw/View.h b/runtime/neurun/core/include/util/feature/nchw/View.h
new file mode 100644
index 000000000..d747937ee
--- /dev/null
+++ b/runtime/neurun/core/include/util/feature/nchw/View.h
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_UTIL_FEATURE_NCHW_VIEW_H__
+#define __NEURUN_UTIL_FEATURE_NCHW_VIEW_H__
+
+#include "misc/feature/Reader.h"
+#include "misc/feature/Shape.h"
+
+#include "backend/operand/ITensor.h"
+#include "util/Coordinates.h"
+#include "util/Utils.h"
+
+#include <cassert>
+
+namespace neurun
+{
+namespace util
+{
+namespace feature
+{
+namespace nchw
+{
+
+template <typename T> class View final : public nnfw::misc::feature::Reader<T>
+{
+public:
+  // Construct for buffer of model inputs
+  View(const ::nnfw::misc::feature::Shape &shape, T *ptr, size_t len)
+      : _shape{shape}, _ptr{reinterpret_cast<uint8_t *>(ptr)}, _len{len}
+  {
+    assert(shape.N * shape.C * shape.H * shape.W * sizeof(T) == len);
+
+    _strides.W = sizeof(T);
+    _strides.H = shape.W * sizeof(T);
+    _strides.C = shape.W * shape.H * sizeof(T);
+    _strides.N = shape.W * shape.H * shape.C * sizeof(T);
+  }
+
+  // Construct for backend tensor
+  View(::neurun::backend::operand::ITensor *tensor)
+      : _ptr{tensor->buffer() + tensor->calcOffset({0, 0, 0, 0})}, _len{tensor->total_size()}
+  {
+    assert(tensor->layout() == ir::Layout::NCHW);
+
+    const auto start_offset = tensor->calcOffset({0, 0, 0, 0});
+    _strides.W = tensor->dimension(3) == 1 ? 0 : tensor->calcOffset({0, 0, 0, 1}) - start_offset;
+    _strides.H = tensor->dimension(2) == 1 ? 0 : tensor->calcOffset({0, 0, 1, 0}) - start_offset;
+    _strides.C = tensor->dimension(1) == 1 ? 0 : tensor->calcOffset({0, 1, 0, 0}) - start_offset;
+    _strides.N = tensor->dimension(0) == 1 ? 0 : tensor->calcOffset({1, 0, 0, 0}) - start_offset;
+
+    _shape.W = tensor->dimension(3);
+    _shape.H = tensor->dimension(2);
+    _shape.C = tensor->dimension(1);
+    _shape.N = tensor->dimension(0);
+  }
+
+public:
+  T at(uint32_t ch, uint32_t row, uint32_t col) const override
+  {
+    const auto offset = feature_index_to_byte_offset(0, ch, row, col);
+
+    T *ptr = reinterpret_cast<T *>(_ptr + offset);
+
+    return *ptr;
+  }
+  T at(uint32_t batch, uint32_t ch, uint32_t row, uint32_t col) const override
+  {
+    const auto offset = feature_index_to_byte_offset(batch, ch, row, col);
+
+    T *ptr = reinterpret_cast<T *>(_ptr + offset);
+
+    return *ptr;
+  }
+
+public:
+  T &at(uint32_t ch, uint32_t row, uint32_t col)
+  {
+    const auto offset = feature_index_to_byte_offset(0, ch, row, col);
+
+    T *ptr = reinterpret_cast<T *>(_ptr + offset);
+
+    return *ptr;
+  }
+  T &at(uint32_t batch, uint32_t ch, uint32_t row, uint32_t col)
+  {
+    const auto offset = feature_index_to_byte_offset(batch, ch, row, col);
+
+    T *ptr = reinterpret_cast<T *>(_ptr + offset);
+
+    return *ptr;
+  }
+
+private:
+  size_t feature_index_to_byte_offset(uint32_t batch, uint32_t ch, uint32_t row, uint32_t col) const
+  {
+    assert(1u * _shape.N > batch); // shape.N > batch
+    assert(1u * _shape.C > ch);    // shape.C > ch
+    assert(1u * _shape.H > row);   // shape.H > row
+    assert(1u * _shape.W > col);   // shape.W > col
+
+    uint32_t res = 0;
+    res += batch * _strides.N;
+    res += ch * _strides.C;
+    res += row * _strides.H;
+    res += col * _strides.W;
+
+    return res;
+  }
+
+private:
+  // TODO Remove _shape
+  nnfw::misc::feature::Shape _shape;
+  using Strides = nnfw::misc::feature::Shape;
+  Strides _strides;
+  uint8_t *_ptr;
+  size_t _len;
+};
+
+} // namespace nchw
+} // namespace feature
+} // namespace util
+} // namespace neurun
+
+#endif // __NEURUN_UTIL_FEATURE_NCHW_VIEW_H__
diff --git a/runtime/neurun/core/include/util/feature/nhwc/Reader.h b/runtime/neurun/core/include/util/feature/nhwc/Reader.h
new file mode 100644
index 000000000..0df7be4be
--- /dev/null
+++ b/runtime/neurun/core/include/util/feature/nhwc/Reader.h
@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_UTIL_FEATURE_NHWC_READER_H__
+#define __NEURUN_UTIL_FEATURE_NHWC_READER_H__
+
+#include <cassert>
+
+#include "backend/operand/ITensor.h"
+#include "misc/feature/Reader.h"
+#include "misc/feature/Shape.h"
+#include "util/Coordinates.h"
+#include "util/Utils.h"
+
+namespace neurun
+{
+namespace util
+{
+namespace feature
+{
+namespace nhwc
+{
+
+template <typename T> class Reader final : public nnfw::misc::feature::Reader<T>
+{
+public:
+  // Construct for buffer of model inputs
+  Reader(const ::nnfw::misc::feature::Shape &shape, const T *ptr, size_t len)
+      : _shape{shape}, _ptr{reinterpret_cast<const uint8_t *>(ptr)}, _len{len}
+  {
+    UNUSED_RELEASE(len); // Workaround for unused variable in release mode
+    assert(shape.N * shape.C * shape.H * shape.W * sizeof(T) == len);
+
+    // No padding
+    _strides.C = sizeof(T);
+    _strides.W = shape.C * sizeof(T);
+    _strides.H = shape.C * shape.W * sizeof(T);
+    _strides.N = shape.C * shape.W * shape.H * sizeof(T);
+  }
+
+  // Construct for backend tensor
+  Reader(const backend::operand::ITensor *tensor)
+      : _ptr{tensor->buffer() + tensor->calcOffset({0, 0, 0, 0})}, _len{tensor->total_size()}
+  {
+    assert(tensor->layout() == ir::Layout::NHWC);
+
+    const auto start_offset = tensor->calcOffset({0, 0, 0, 0});
+    _strides.C = tensor->dimension(3) == 1 ? 0 : tensor->calcOffset({0, 0, 0, 1}) - start_offset;
+    _strides.W = tensor->dimension(2) == 1 ? 0 : tensor->calcOffset({0, 0, 1, 0}) - start_offset;
+    _strides.H = tensor->dimension(1) == 1 ? 0 : tensor->calcOffset({0, 1, 0, 0}) - start_offset;
+    _strides.N = tensor->dimension(0) == 1 ? 0 : tensor->calcOffset({1, 0, 0, 0}) - start_offset;
+
+    _shape.C = tensor->dimension(3);
+    _shape.W = tensor->dimension(2);
+    _shape.H = tensor->dimension(1);
+    _shape.N = tensor->dimension(0);
+  }
+
+public:
+  T at(uint32_t row, uint32_t col, uint32_t ch) const override
+  {
+    const auto offset = feature_index_to_byte_offset(0, row, col, ch);
+
+    const T *ptr = reinterpret_cast<const T *>(_ptr + offset);
+
+    return *ptr;
+  }
+  T at(uint32_t batch, uint32_t row, uint32_t col, uint32_t ch) const override
+  {
+    const auto offset = feature_index_to_byte_offset(batch, row, col, ch);
+
+    const T *ptr = reinterpret_cast<const T *>(_ptr + offset);
+
+    return *ptr;
+  }
+
+private:
+  size_t feature_index_to_byte_offset(uint32_t batch, uint32_t row, uint32_t col, uint32_t ch) const
+  {
+    assert(1u * _shape.N > batch); // shape.N > batch
+    assert(1u * _shape.H > row);   // shape.H > row
+    assert(1u * _shape.W > col);   // shape.W > col
+    assert(1u * _shape.C > ch);    // shape.C > ch
+
+    uint32_t res = 0;
+    res += batch * _strides.N;
+    res += row * _strides.H;
+    res += col * _strides.W;
+    res += ch * _strides.C;
+
+    return res;
+  }
+
+private:
+  // TODO Remove _shape
+  nnfw::misc::feature::Shape _shape;
+  using Strides = nnfw::misc::feature::Shape;
+  Strides _strides;
+  const uint8_t *_ptr;
+  size_t _len;
+};
+
+} // namespace nhwc
+} // namespace feature
+} // namespace util
+} // namespace neurun
+
+#endif // __NEURUN_UTIL_FEATURE_NHWC_READER_H__
diff --git a/runtime/neurun/core/include/util/feature/nhwc/View.h b/runtime/neurun/core/include/util/feature/nhwc/View.h
new file mode 100644
index 000000000..b9d98e9fa
--- /dev/null
+++ b/runtime/neurun/core/include/util/feature/nhwc/View.h
@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_UTIL_FEATURE_NHWC_VIEW_H__
+#define __NEURUN_UTIL_FEATURE_NHWC_VIEW_H__
+
+#include <cassert>
+#include <cstddef>
+
+#include "backend/operand/ITensor.h"
+#include "misc/feature/Reader.h"
+#include "misc/feature/Shape.h"
+#include "util/Coordinates.h"
+#include "util/Utils.h"
+
+namespace neurun
+{
+namespace util
+{
+namespace feature
+{
+namespace nhwc
+{
+
+template <typename T> class View final : public nnfw::misc::feature::Reader<T>
+{
+public:
+  // Construct for buffer of model inputs
+  View(const ::nnfw::misc::feature::Shape &shape, T *ptr, size_t len)
+      : _shape{shape}, _ptr{reinterpret_cast<uint8_t *>(ptr)}, _len{len}
+  {
+    UNUSED_RELEASE(len); // Workaround for unused variable in release mode
+    assert(shape.N * shape.H * shape.W * shape.C * sizeof(T) == len);
+
+    // No padding
+    _strides.C = sizeof(T);
+    _strides.W = shape.C * sizeof(T);
+    _strides.H = shape.C * shape.W * sizeof(T);
+    _strides.N = shape.C * shape.W * shape.H * sizeof(T);
+  }
+
+  // Construct for backend tensor
+  View(backend::operand::ITensor *tensor)
+      : _ptr{tensor->buffer() + tensor->calcOffset({0, 0, 0, 0})}, _len{tensor->total_size()}
+  {
+    assert(tensor->layout() == ir::Layout::NHWC);
+
+    const auto start_offset = tensor->calcOffset({0, 0, 0, 0});
+    _strides.C = tensor->dimension(3) == 1 ? 0 : tensor->calcOffset({0, 0, 0, 1}) - start_offset;
+    _strides.W = tensor->dimension(2) == 1 ? 0 : tensor->calcOffset({0, 0, 1, 0}) - start_offset;
+    _strides.H = tensor->dimension(1) == 1 ? 0 : tensor->calcOffset({0, 1, 0, 0}) - start_offset;
+    _strides.N = tensor->dimension(0) == 1 ? 0 : tensor->calcOffset({1, 0, 0, 0}) - start_offset;
+
+    _shape.C = tensor->dimension(3);
+    _shape.W = tensor->dimension(2);
+    _shape.H = tensor->dimension(1);
+    _shape.N = tensor->dimension(0);
+  }
+
+public:
+  T at(uint32_t row, uint32_t col, uint32_t ch) const override
+  {
+    const auto offset = feature_index_to_byte_offset(0, row, col, ch);
+
+    const T *ptr = reinterpret_cast<const T *>(_ptr + offset);
+
+    return *ptr;
+  }
+  T at(uint32_t batch, uint32_t row, uint32_t col, uint32_t ch) const override
+  {
+    const auto offset = feature_index_to_byte_offset(batch, row, col, ch);
+
+    const T *ptr = reinterpret_cast<const T *>(_ptr + offset);
+
+    return *ptr;
+  }
+
+  T &at(uint32_t row, uint32_t col, uint32_t ch)
+  {
+    const auto offset = feature_index_to_byte_offset(0, row, col, ch);
+
+    T *ptr = reinterpret_cast<T *>(_ptr + offset);
+
+    return *ptr;
+  }
+
+  T &at(uint32_t batch, uint32_t row, uint32_t col, uint32_t ch)
+  {
+    const auto offset = feature_index_to_byte_offset(batch, row, col, ch);
+
+    T *ptr = reinterpret_cast<T *>(_ptr + offset);
+
+    return *ptr;
+  }
+
+private:
+  size_t feature_index_to_byte_offset(uint32_t batch, uint32_t row, uint32_t col, uint32_t ch) const
+  {
+    assert(1u * _shape.N > batch); // shape.N > batch
+    assert(1u * _shape.H > row);   // shape.H > row
+    assert(1u * _shape.W > col);   // shape.W > col
+    assert(1u * _shape.C > ch);    // shape.C > ch
+
+    uint32_t res = 0;
+    res += batch * _strides.N;
+    res += row * _strides.H;
+    res += col * _strides.W;
+    res += ch * _strides.C;
+
+    return res;
+  }
+
+private:
+  // TODO Remove _shape
+  nnfw::misc::feature::Shape _shape;
+  using Strides = nnfw::misc::feature::Shape;
+  Strides _strides;
+  uint8_t *_ptr;
+  size_t _len;
+};
+
+} // namespace nhwc
+} // namespace feature
+} // namespace util
+} // namespace neurun
+
+#endif // __NEURUN_UTIL_FEATURE_NHWC_VIEW_H__
diff --git a/runtime/neurun/core/include/util/logging.h b/runtime/neurun/core/include/util/logging.h
new file mode 100644
index 000000000..8ecd0ac12
--- /dev/null
+++ b/runtime/neurun/core/include/util/logging.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_UTIL_LOGGING_H__
+#define __NEURUN_UTIL_LOGGING_H__
+
+#include <iostream>
+
+#include "util/ConfigSource.h"
+
+namespace neurun
+{
+namespace util
+{
+namespace logging
+{
+
+class Context
+{
+public:
+  Context() noexcept : _enabled{false}
+  {
+    const auto env = util::getConfigBool(util::config::NEURUN_LOG_ENABLE);
+
+    if (env)
+    {
+      _enabled = true;
+    }
+  }
+
+  static Context &get() noexcept;
+
+public:
+  bool enabled(void) const { return _enabled; }
+
+private:
+  bool _enabled;
+};
+
+static Context &ctx = Context::get();
+
+} // namespace logging
+} // namespace util
+} // namespace neurun
+
+#define VERBOSE(name)                         \
+  if (::neurun::util::logging::ctx.enabled()) \
+  std::cout << "[" << #name << "] "
+
+#endif // __NEURUN_UTIL_LOGGING_H__
diff --git a/runtime/neurun/core/src/backend/Backend.cc b/runtime/neurun/core/src/backend/Backend.cc
new file mode 100644
index 000000000..c2f745f8f
--- /dev/null
+++ b/runtime/neurun/core/src/backend/Backend.cc
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "backend/Backend.h"
+
+#include "backend/IConfig.h"
+#include "backend/ITensorBuilder.h"
+#include "backend/IKernelGenerator.h"
+#include "backend/IShapeFixer.h"
+
+namespace neurun
+{
+namespace backend
+{
+
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/core/src/backend/BackendManager.cc b/runtime/neurun/core/src/backend/BackendManager.cc
new file mode 100644
index 000000000..32086e8b6
--- /dev/null
+++ b/runtime/neurun/core/src/backend/BackendManager.cc
@@ -0,0 +1,150 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <memory>
+#include <dlfcn.h>
+#include "BackendManager.h"
+
+#include "backend/Backend.h"
+#include "backend/IConfig.h"
+#include "util/logging.h"
+#include "util/ConfigSource.h"
+#include "misc/string_helpers.h"
+
+namespace neurun
+{
+namespace backend
+{
+
+BackendManager &BackendManager::get()
+{
+  static BackendManager object;
+  return object;
+}
+
+template <typename T, class... Types>
+void BackendManager::loadObjectFromPlugin(std::shared_ptr<T> &object_of_plugin_class,
+                                          const std::string obj_creator_func_name, void *handle,
+                                          Types &&... args)
+{
+  T *(*allocate_obj)(Types && ... Args);
+  // load object creator function
+  allocate_obj = (T * (*)(Types && ... Args))dlsym(handle, obj_creator_func_name.c_str());
+  if (allocate_obj == nullptr)
+  {
+    fprintf(stderr, "BackendManager: unable to open function %s: %s\n",
+            obj_creator_func_name.c_str(), dlerror());
+    abort();
+  }
+
+  object_of_plugin_class.reset(allocate_obj(args...));
+}
+
+void BackendManager::loadBackend(const std::string &backend)
+{
+  const std::string backend_plugin = "libbackend_" + backend + ".so";
+  void *handle = dlopen(backend_plugin.c_str(), RTLD_LAZY | RTLD_LOCAL);
+  if (handle == nullptr)
+  {
+    VERBOSE(BackendManager::loadBackend) << "loadBackend failed to load plugin of "
+                                         << backend.c_str() << " backend: " << dlerror()
+                                         << std::endl;
+    return;
+  }
+
+  VERBOSE(BackendManager::loadBackend) << "loaded " << backend_plugin << " as a plugin of "
+                                       << backend << " backend\n";
+
+  {
+    // load object creator function
+    auto backend_create = (backend_create_t)dlsym(handle, "neurun_backend_create");
+    if (backend_create == nullptr)
+    {
+      fprintf(stderr, "BackendManager: unable to open function neurun_backend_create : %s\n",
+              dlerror());
+      abort();
+    }
+
+    // load object creator function
+    auto backend_destroy = (backend_destroy_t)dlsym(handle, "neurun_backend_destroy");
+    if (backend_destroy == nullptr)
+    {
+      fprintf(stderr, "BackendManager: unable to open function neurun_backend_destroy : %s\n",
+              dlerror());
+      abort();
+    }
+
+    auto backend_object =
+        std::unique_ptr<backend::Backend, backend_destroy_t>(backend_create(), backend_destroy);
+    auto backend_object_raw = backend_object.get();
+    bool initialized = backend_object->config()->initialize(); // Call initialize here?
+    if (!initialized)
+    {
+      VERBOSE(BackendManager::loadBackend)
+          << backend.c_str() << " backend initialization failed. Don't use this backend"
+          << std::endl;
+      dlclose(handle);
+      return;
+    }
+    _gen_map.emplace(backend_object->config()->id(), std::move(backend_object));
+    _available_backends.push_back(backend_object_raw);
+  }
+
+  // Save backend handle (avoid warning by handle lost without dlclose())
+  auto u_handle = std::unique_ptr<void, dlhandle_destroy_t>{handle, [](void *h) { dlclose(h); }};
+  _handle_map.emplace(backend, std::move(u_handle));
+}
+
+BackendManager::BackendManager()
+{
+  const auto backends = util::getConfigString(util::config::BACKENDS);
+  for (auto &backend_id : nnfw::misc::split(backends, ';'))
+  {
+    loadBackend(backend_id);
+  }
+
+  // No loaded backend
+  if (_available_backends.empty())
+  {
+    VERBOSE(BackendManager::loadBackend) << "There is no loaded backend\n";
+    abort();
+  }
+}
+
+Backend *BackendManager::get(const std::string &key)
+{
+  if (_gen_map.find(key) != _gen_map.end())
+  {
+    return _gen_map.at(key).get();
+  }
+
+  return nullptr;
+}
+
+const Backend *BackendManager::get(const std::string &key) const
+{
+  if (_gen_map.find(key) != _gen_map.end())
+  {
+    return _gen_map.at(key).get();
+  }
+
+  return nullptr;
+}
+
+const Backend *BackendManager::getDefault() const { return get("cpu"); }
+
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/core/src/backend/BackendManager.h b/runtime/neurun/core/src/backend/BackendManager.h
new file mode 100644
index 000000000..9c6483f9d
--- /dev/null
+++ b/runtime/neurun/core/src/backend/BackendManager.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_BACKEND_MANAGER_H__
+#define __NEURUN_BACKEND_BACKEND_MANAGER_H__
+
+#include <memory>
+#include <map>
+
+#include "ir/Operands.h"
+#include "backend/Backend.h"
+
+namespace neurun
+{
+namespace backend
+{
+
+class BackendManager
+{
+public:
+  using backend_create_t = Backend *(*)();
+  using backend_destroy_t = void (*)(Backend *);
+  using dlhandle_destroy_t = void (*)(void *);
+
+  static BackendManager &get();
+
+public:
+  Backend *get(const std::string &key);
+  const Backend *get(const std::string &key) const;
+  const Backend *getDefault() const;
+  const std::vector<const Backend *> &getAll() const { return _available_backends; };
+
+private:
+  BackendManager();
+
+private:
+  std::vector<const Backend *> _available_backends;
+  std::map<std::string, std::unique_ptr<void, dlhandle_destroy_t>> _handle_map;
+  std::map<std::string, std::unique_ptr<Backend, backend_destroy_t>> _gen_map;
+  /**
+   * @brief Allocate an object of a class of a plugin by loading a plugin function, that does
+   * allocation, and calling it
+   *
+   * @param object_of_plugin_class target object
+   * @param obj_creator_func_name name of the plugin function, that allocates an object
+   * @param handle handle of the plugin
+   * @param args arguments to pass to constructor of the plugin class
+   *
+   * @return
+   */
+  template <typename T, class... Types>
+  void loadObjectFromPlugin(std::shared_ptr<T> &object_of_plugin_class,
+                            const std::string obj_creator_func_name, void *handle,
+                            Types &&... args);
+
+  /**
+   * @brief load backend plugin
+   *
+   * @param backend backend to be loaded
+   *
+   * @return
+   */
+  void loadBackend(const std::string &backend);
+};
+
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_BACKEND_MANAGER_H__
diff --git a/runtime/neurun/core/src/backend/ExecTime.cc b/runtime/neurun/core/src/backend/ExecTime.cc
new file mode 100644
index 000000000..d5aa679d7
--- /dev/null
+++ b/runtime/neurun/core/src/backend/ExecTime.cc
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "backend/ExecTime.h"
+
+#include <fstream>
+#include <cassert>
+#include <limits>
+#include <algorithm>
+
+namespace neurun
+{
+namespace backend
+{
+
+int64_t ExecTime::getOperationExecTime(const Backend *backend, const std::string &operation,
+                                       bool quant, uint32_t op_size) const
+{
+  auto found_backend = _measurements.find(backend);
+  if (found_backend == _measurements.end())
+    return NOT_FOUND; // no execution time for this backend
+
+  auto found_operation_with_type = found_backend->second.find(operation);
+  if (found_operation_with_type == found_backend->second.end())
+    // no execution time for this operation
+    return NOT_FOUND;
+
+  auto found_operation = found_operation_with_type->second.find(quant);
+  if (found_operation == found_operation_with_type->second.end())
+    // no execution time for this operation
+    return NOT_FOUND;
+
+  auto found_size = found_operation->second.find(op_size);
+  if (found_size != found_operation->second.end())
+    return found_size->second; // found execution time
+
+  // Try to interpolate
+  if (found_operation->second.size() < 2)
+    // not possible to do linear interpolation
+    return found_operation->second.begin()->second;
+
+  // if we reach here, then this means, that there is no record, that is equal to op_size
+  auto upper_bound = found_operation->second.upper_bound(op_size); // > op_size
+  auto lower_bound = upper_bound;
+
+  if (upper_bound == found_operation->second.end()) // all values <= op_size
+  {
+    upper_bound--;
+    lower_bound = upper_bound;
+    lower_bound--;
+  }
+  else if (upper_bound == found_operation->second.begin()) // all values > op_size
+  {
+    upper_bound++;
+  }
+  else // op_size between
+  {
+    lower_bound--;
+  }
+
+  // Linear interpolation
+  const auto x0 = static_cast<int64_t>(lower_bound->first); // size
+  const auto x1 = static_cast<int64_t>(upper_bound->first); // size
+  const int64_t y0 = lower_bound->second;                   // time
+  const int64_t y1 = upper_bound->second;                   // time
+  const auto x = static_cast<int64_t>(op_size);
+
+  int64_t interpolated_value = y0 + (x - x0) * (y1 - y0) / (x1 - x0);
+
+  // In some cases ops with smaller inputs is executed slower than the one
+  // with larger inputs, more likely because of a backend's load difference
+  if (interpolated_value < 0 && x > x1)
+  {
+    return y0;
+  }
+  // It must be non-positive ONLY if it's lesser than both of them
+  assert(interpolated_value > 0 || x < x0);
+
+  // execution time must be non-negative
+  return std::max<int64_t>(interpolated_value, 1);
+}
+
+void ExecTime::updateOperationExecTime(const Backend *backend, const std::string &operation,
+                                       bool quant, uint32_t op_size, int64_t time)
+{
+  // If the op is not implemented for some input, it should not be scheduled
+  const auto &recs = _measurements[backend][operation][quant];
+  if (time == getMax() ||
+      std::any_of(recs.begin(), recs.end(),
+                  [](std::pair<const uint32_t, const int64_t> p) { return p.second == getMax(); }))
+  {
+    _measurements[backend][operation][quant].clear();
+    _measurements[backend][operation][quant].emplace(op_size, getMax());
+  }
+  else
+  {
+    auto it = _measurements[backend][operation][quant].emplace(op_size, time);
+    if (!it.second)
+    {
+      // affect of the last measurement is bigger than the previous ones:
+      //   this prefers new metrics than older once, so will adapt backend changes
+      it.first->second = (it.first->second + time) / 2;
+    }
+  }
+}
+
+void ExecTime::updatePermuteTime(const Backend *from_backend, const Backend *to_backend, bool quant,
+                                 uint32_t op_size, int64_t time)
+{
+  updateOperationExecTime(from_backend, to_backend->config()->id(), quant, op_size, time);
+}
+
+int64_t ExecTime::getPermuteTime(const Backend *from_backend, const Backend *to_backend, bool quant,
+                                 uint32_t op_size) const
+{
+  return getOperationExecTime(from_backend, to_backend->config()->id(), quant, op_size);
+}
+
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/core/src/backend/JSONExecTime.cc b/runtime/neurun/core/src/backend/JSONExecTime.cc
new file mode 100644
index 000000000..e2404b2c8
--- /dev/null
+++ b/runtime/neurun/core/src/backend/JSONExecTime.cc
@@ -0,0 +1,231 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "backend/JSONExecTime.h"
+#include "backend/IConfig.h"
+#include <fstream>
+
+namespace neurun
+{
+namespace backend
+{
+/**
+ * @brief Helper function for reading string from stream
+ *
+ * @param str Output string
+ * @param stream File stream
+ */
+void readString(std::string &str, std::ifstream &stream)
+{
+  str.clear();
+  char buf;
+  while (stream.good())
+  {
+    stream.get(buf);
+    if (buf == '"')
+      break;
+    str.push_back(buf);
+  }
+}
+
+/**
+ * @brief Helper function for reading bool from stream
+ *
+ * @param quant Output bool
+ * @param stream File stream
+ */
+void readBool(bool &quant, std::ifstream &stream)
+{
+  char buf;
+  stream.get(buf);
+  quant = (buf == '1');
+  stream.get(buf);
+}
+
+void printString(const std::string &str, std::ofstream &stream) { stream << "\"" << str << "\""; }
+
+void printBool(bool quant, std::ofstream &stream) { stream << "\"" << quant << "\""; }
+
+void JSON::readOperation(const std::string &backend, const std::string &operation, bool quant,
+                         std::ifstream &stream)
+{
+  uint32_t size = 0;
+  int64_t time = 0;
+
+  std::string int_buf;
+  char buf;
+  int number_of_closed_braces = 0;
+  int number_of_commas = 0;
+
+  while (stream.good())
+  {
+    stream.get(buf);
+
+    switch (buf)
+    {
+      case ']':
+      {
+        number_of_closed_braces++;
+        break;
+      }
+      case '[':
+      {
+        number_of_closed_braces--;
+        break;
+      }
+      default:
+      {
+        if (std::isdigit(buf))
+        {
+          int_buf.push_back(buf);
+        }
+        break;
+      }
+    }
+
+    if (number_of_closed_braces == 1)
+      break;
+
+    if ((buf == ']' && number_of_closed_braces == 0) ||
+        (buf == ',' && number_of_closed_braces == -1))
+    {
+      switch (number_of_commas % 2)
+      {
+        case 0:
+        {
+          size = static_cast<uint32_t>(std::atoi(int_buf.c_str()));
+          break;
+        }
+        case 1:
+        {
+          time = static_cast<int64_t>(std::atol(int_buf.c_str()));
+          auto bf = _backends.find(backend);
+          if (bf != _backends.end())
+          {
+            _measurements[bf->second][operation][quant][size] = time;
+          } // we ignore the records for unsupported backends
+          break;
+        }
+      }
+      number_of_commas++;
+      int_buf.clear();
+    }
+  }
+}
+void JSON::printOperation(const std::map<uint32_t, int64_t> &operation_info,
+                          std::ofstream &stream) const
+{
+  for (const auto &items : operation_info)
+  {
+    stream << "[" << items.first << ", " << items.second << "], ";
+  }
+  stream.seekp(-2, std::ofstream::end);
+}
+
+void JSON::uploadOperationsExecTime() const
+{
+  std::ofstream stream(_measurement_file);
+  if (!stream.is_open())
+  {
+    throw std::runtime_error("Failed to save backend config file");
+  }
+  else
+  {
+    stream << "{";
+    for (const auto &backend : _measurements)
+    {
+      printString(backend.first->config()->id(), stream);
+      stream << ": {";
+      for (const auto &operation : backend.second)
+      {
+        printString(operation.first, stream);
+        stream << ": {";
+        for (const auto &type : operation.second)
+        {
+          printBool(type.first, stream);
+          stream << ": [";
+          printOperation(type.second, stream);
+          stream << "], ";
+        }
+        stream.seekp(-2, std::ofstream::end);
+        stream << "}, ";
+      }
+      stream.seekp(-2, std::ofstream::end);
+      stream << "}, ";
+    }
+    stream.seekp(-2, std::ofstream::end);
+    stream << "}";
+    stream.close();
+  }
+}
+
+void JSON::loadOperationsExecTime()
+{
+  std::ifstream stream(_measurement_file);
+  if (stream.is_open())
+  {
+    std::string backend;
+    std::string operation;
+    bool quant = false;
+    char buf;
+    int number_of_open_braces = 0;
+
+    while (stream.good())
+    {
+      stream.get(buf);
+      switch (buf)
+      {
+        case '{':
+          number_of_open_braces++;
+          break;
+        case '}':
+          number_of_open_braces--;
+          break;
+        case '"':
+        {
+          if (number_of_open_braces == 1)
+          {
+            // read backend string
+            readString(backend, stream);
+          }
+          if (number_of_open_braces == 2)
+          {
+            // read operation string
+            readString(operation, stream);
+          }
+          if (number_of_open_braces == 3)
+          {
+            // read operation string
+            readBool(quant, stream);
+          }
+          break;
+        }
+        case '[':
+        {
+          // reading and creating all info for operation
+          readOperation(backend, operation, quant, stream);
+          break;
+        }
+        default:
+          break;
+      }
+    }
+    stream.close();
+  }
+}
+
+} // namespace backend
+} // namespace neurun
diff --git a/runtime/neurun/core/src/compiler/BackendResolver.cc b/runtime/neurun/core/src/compiler/BackendResolver.cc
new file mode 100644
index 000000000..0c544190c
--- /dev/null
+++ b/runtime/neurun/core/src/compiler/BackendResolver.cc
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "BackendResolver.h"
+
+namespace neurun
+{
+namespace compiler
+{
+
+BackendResolver::BackendResolver(const BackendResolver &obj)
+    : _context_manager{}, _gen_map{obj._gen_map}
+{
+  for (const auto &e : obj._context_manager)
+  {
+    _context_manager.emplace(e.first, nnfw::cpp14::make_unique<backend::BackendContext>(*e.second));
+  }
+}
+
+BackendResolver &BackendResolver::operator=(const BackendResolver &obj)
+{
+  _gen_map = obj._gen_map;
+
+  _context_manager.clear();
+  for (const auto &e : obj._context_manager)
+  {
+    _context_manager.emplace(e.first, nnfw::cpp14::make_unique<backend::BackendContext>(*e.second));
+  }
+
+  return *this;
+}
+
+} // namespace compiler
+} // namespace neurun
diff --git a/runtime/neurun/core/src/compiler/BackendResolver.h b/runtime/neurun/core/src/compiler/BackendResolver.h
new file mode 100644
index 000000000..ddcae793a
--- /dev/null
+++ b/runtime/neurun/core/src/compiler/BackendResolver.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_COMPILER_BACKEND_RESOLVER_H__
+#define __NEURUN_COMPILER_BACKEND_RESOLVER_H__
+
+#include <unordered_map>
+#include <typeindex>
+
+#include "util/logging.h"
+#include "backend/Backend.h"
+#include "backend/BackendManager.h"
+#include "backend/ITensorBuilder.h"
+#include "ir/OperationIndexMap.h"
+
+namespace neurun
+{
+namespace compiler
+{
+
+class BackendResolver
+{
+public:
+  BackendResolver(const ir::Operands &operands,
+                  const std::vector<const backend::Backend *> &backends,
+                  const std::shared_ptr<backend::custom::IKernelBuilder> &kb)
+  {
+    for (const auto backend : backends)
+    {
+      _context_manager.emplace(backend, backend->newContext(operands, kb));
+    }
+  }
+
+  ~BackendResolver() = default;
+  BackendResolver(const BackendResolver &obj);
+  BackendResolver(BackendResolver &&obj) = default;
+  BackendResolver &operator=(const BackendResolver &obj);
+  BackendResolver &operator=(BackendResolver &&obj) = default;
+
+public:
+  const backend::BackendContext *getBackendContext(const ir::OperationIndex &index) const
+  {
+    return _context_manager.at(_gen_map.at(index)).get();
+  }
+
+  const backend::BackendContext *getBackendContext(const backend::Backend *backend) const
+  {
+    return _context_manager.at(backend).get();
+  }
+
+  backend::TensorBuilderSet tensor_builders() const
+  {
+    backend::TensorBuilderSet ret;
+    for (const auto &e : _context_manager)
+    {
+      ret.insert(e.second->tensor_builder);
+    }
+    return ret;
+  }
+
+  const backend::Backend *getBackend(const ir::OperationIndex &index) const
+  {
+    return getBackendContext(index)->backend;
+  }
+
+  void setBackend(const ir::OperationIndex &index, const backend::Backend *backend)
+  {
+    _gen_map[index] = backend;
+  }
+
+  void iterate(const std::function<void(const ir::OperationIndex &,
+                                        const backend::BackendContext &)> &fn) const
+  {
+    for (const auto &e : _gen_map)
+    {
+      fn(e.first, *_context_manager.at(e.second));
+    }
+  }
+
+private:
+  std::unordered_map<const backend::Backend *, std::unique_ptr<backend::BackendContext>>
+      _context_manager;
+  ir::OperationIndexMap<const backend::Backend *> _gen_map;
+};
+
+} // namespace compiler
+} // namespace neurun
+
+#endif // __NEURUN_COMPILER_BACKEND_RESOLVER_H__
diff --git a/runtime/neurun/core/src/compiler/CodeWithInfo.h b/runtime/neurun/core/src/compiler/CodeWithInfo.h
new file mode 100644
index 000000000..73dd1055b
--- /dev/null
+++ b/runtime/neurun/core/src/compiler/CodeWithInfo.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_COMPILER_CODE_WITH_INFO_H__
+#define __NEURUN_COMPILER_CODE_WITH_INFO_H__
+
+#include <memory>
+
+#include "compiler/Linear.h"
+#include "exec/IFunction.h"
+
+namespace neurun
+{
+namespace compiler
+{
+
+struct CodeWithInfo
+{
+  Linear::Element elem;
+  std::unique_ptr<exec::IFunction> fn;
+
+  CodeWithInfo(const Linear::Element &elem, std::unique_ptr<exec::IFunction> &&fn)
+      : elem{elem}, fn{std::move(fn)}
+  {
+  }
+};
+
+} // namespace compiler
+} // namespace neurun
+
+#endif // __NEURUN_COMPILER_CODE_WITH_INFO_H__
diff --git a/runtime/neurun/core/src/compiler/Compiler.cc b/runtime/neurun/core/src/compiler/Compiler.cc
new file mode 100644
index 000000000..d5ee39d85
--- /dev/null
+++ b/runtime/neurun/core/src/compiler/Compiler.cc
@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "compiler/Compiler.h"
+
+#include "BackendResolver.h"
+#include "ParamChecker.h"
+#include "ExecutorFactory.h"
+#include "OperationValidator.h"
+
+#include "compiler/IScheduler.h"
+#include "compiler/ManualScheduler.h"
+#include "compiler/HEScheduler.h"
+#include "backend/ExecTime.h"
+#include "ir/operation/LowerInfo.h"
+#include "dumper/dot/DotDumper.h"
+#include "compiler/Linear.h"
+#include "exec/interp/ExecManager.h"
+#include "backend/ExecTime.h"
+#include "util/ConfigSource.h"
+
+namespace neurun
+{
+
+namespace compiler
+{
+
+static void checkProfilerConditions()
+{
+  if (!util::getConfigBool(util::config::USE_SCHEDULER))
+    throw std::runtime_error("Heterogeneous scheduler must be enabled during profiling.");
+
+  if (util::getConfigString(util::config::EXECUTOR) != "Dataflow")
+    throw std::runtime_error("Profiling mode works only with 'Dataflow' executor");
+}
+
+void Compiler::compile(void)
+{
+  _state = State::STARTED;
+
+  /***************************************************
+   * Prepare compilation phase
+   ***************************************************/
+
+  // Operation validation check
+  OperationValidator{*_graph}();
+
+  // Compilable check
+  if (!checkCompilable())
+  {
+    _executor = std::make_shared<exec::interp::ExecManager>(*_graph);
+    return;
+  }
+
+  // Mode check
+  if (util::getConfigBool(util::config::PROFILING_MODE))
+    checkProfilerConditions();
+
+  /***************************************************
+   * Backend independent analysis & optimization phase
+   ***************************************************/
+  // Schedule
+  std::unique_ptr<BackendResolver> br;
+  std::shared_ptr<ir::OperationIndexMap<int64_t>> indexed_ranks;
+  if (util::getConfigBool(util::config::USE_SCHEDULER))
+  {
+    auto scheduler = compiler::HEScheduler(
+        _graph->operands(), backend::BackendManager::get().getAll(), _graph->getKernelBuilder());
+    br = scheduler.schedule(*_graph);
+    indexed_ranks = scheduler.getIndexedRanks();
+  }
+  else
+  {
+    auto scheduler = compiler::ManualScheduler();
+    br = scheduler.schedule(*_graph);
+  }
+  _graph->setBackendResolver(std::move(br));
+  /*************************************************************
+   *  Backend independent analysis & optimization phase finished
+   *************************************************************/
+
+  // dump graph to .dot
+  auto dump_level =
+      static_cast<dumper::dot::DotDumper::Level>(util::getConfigInt(util::config::GRAPH_DOT_DUMP));
+  neurun::dumper::dot::DotDumper dot_dumper(*_graph, dump_level);
+  dot_dumper.dump("before_lower");
+
+  // Lower: decide backend
+  _graph->lower();
+  _state = State::LOWERED;
+
+  dot_dumper.dump("after_lower");
+
+  const std::string executor_str = util::getConfigString(util::config::EXECUTOR);
+
+  _executor =
+      std::shared_ptr<exec::IExecutor>{ExecutorFactory::get().create(executor_str, *_graph)};
+  _executor->setIndexedRanks(indexed_ranks);
+  /********************************
+   * Code generation phase finished
+   ********************************/
+  _state = State::COMPILED;
+}
+
+bool Compiler::checkCompilable()
+{
+  // Disable compile phase
+  // When ready to use interpreter backend, remove this config and use backend setting
+  const auto env_disable_compile = util::getConfigBool(util::config::DISABLE_COMPILE);
+  if (env_disable_compile)
+  {
+    return false;
+  }
+
+  // TODO check unspecified operand shape
+
+  // Check compilable parameter
+  ParamChecker paramChecker{_graph};
+  paramChecker();
+  if (paramChecker.haveNoneConstParam())
+  {
+    return false;
+  }
+
+  return true;
+}
+
+} // namespace compiler
+
+} // namespace neurun
diff --git a/runtime/neurun/core/src/compiler/ExecutorFactory.cc b/runtime/neurun/core/src/compiler/ExecutorFactory.cc
new file mode 100644
index 000000000..59de6c4a4
--- /dev/null
+++ b/runtime/neurun/core/src/compiler/ExecutorFactory.cc
@@ -0,0 +1,379 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ExecutorFactory.h"
+
+#include <functional>
+#include "exec/ExecutionObservers.h"
+#include "exec/LinearExecutor.h"
+#include "exec/DataflowExecutor.h"
+#include "exec/ParallelExecutor.h"
+#include "compiler/BackendResolver.h"
+#include "backend/ExecTime.h"
+#include "compiler/Linear.h"
+#include "ir/dumper/Dumper.h"
+#include "SubTensorAnalyzer.h"
+#include "backend/IConstantInitializer.h"
+#include "backend/IKernelGenerator.h"
+#include "backend/IShapeFixer.h"
+#include "backend/ITensorRegister.h"
+#include "cpp14/memory.h"
+#include "CodeWithInfo.h"
+
+namespace neurun
+{
+namespace compiler
+{
+
+ExecutorFactory &ExecutorFactory::get()
+{
+  static ExecutorFactory singleton;
+  return singleton;
+}
+
+ExecutorFactory::ExecutorFactory()
+{
+  _map["Linear"] = createLinearExecutor;
+  _map["Dataflow"] = std::bind(createDataflowExecutor, std::placeholders::_1, false);
+  _map["Parallel"] = std::bind(createDataflowExecutor, std::placeholders::_1, true);
+}
+
+exec::IExecutor *ExecutorFactory::create(const std::string &id, ir::Graph &graph)
+{
+  return _map.at(id)(graph);
+}
+
+exec::IExecutor *ExecutorFactory::createLinearExecutor(ir::Graph &graph)
+{
+  auto operand_context = std::make_shared<OperandContext>();
+
+  // linearize
+  assert(!graph.isBuildingPhase());
+  auto linear = nnfw::cpp14::make_unique<Linear>(graph);
+
+  // Dump ops
+  linear->accept(ir::dumper::Dumper{});
+
+  /*************************************************
+   * Backend dependent analysis & optimization phase
+   *************************************************/
+
+  // SubTensorInfo should be generated after lower, before shape correction and finalize
+  // because SubTensorAnalyzer assume that insert permutation is already finished
+  //    lower: decide backend and insert permutation
+  //    fix shapes: prepare codegen to optimization
+  //    generate tensor objects: generate tensor using subtensor info
+  //    generate kernels
+  //    allocate tesor memory
+  //    constant intialization: fill the constants with values
+  // Generated SubTensorInfo is in operand(Object)
+  // for easy pass SubTensorInfo to plan builder and tensor builder
+  linear->accept(SubTensorAnalyzer{graph});
+
+  /**********************************************************
+   * Backend dependent analysis & optimization phase finished
+   **********************************************************/
+
+  /***********************
+   * Code generation phase
+   ***********************/
+
+  // Fix shapes
+  linear->iterate([&](const compiler::Linear::Element &element) {
+    auto backend = element.lower_info->backend();
+    auto shape_fixer = graph.backend_resolver()->getBackendContext(backend)->shape_fixer;
+    shape_fixer->fix(*element.op_seq);
+  });
+
+  linear->planTensors();
+
+  auto tensor_builders = graph.backend_resolver()->tensor_builders();
+
+  // Prepare tensors
+  for (auto &tensor_builder : tensor_builders)
+  {
+    tensor_builder->prepare();
+  }
+
+  // Generate initializers
+  linear->generateConstantInitializers();
+
+  class ExecutionBuilder final : public IExecutionBuilder
+  {
+  public:
+    void append(std::unique_ptr<exec::IFunction> &&f) override
+    {
+      _code.emplace_back(_next_elem, std::move(f));
+    }
+
+    void setNextElem(const compiler::Linear::Element &next_elem) { _next_elem = next_elem; }
+    std::vector<CodeWithInfo> releaseCode() { return std::move(_code); }
+
+  private:
+    compiler::Linear::Element _next_elem;
+    std::vector<CodeWithInfo> _code;
+  };
+
+  ExecutionBuilder builder;
+
+  // Generate kernels
+  linear->iterate([&](const compiler::Linear::Element &element) {
+    auto backend = element.lower_info->backend();
+    builder.setNextElem(element);
+    auto kernel_gen = graph.backend_resolver()->getBackendContext(backend)->kernel_gen;
+    kernel_gen->generate(*element.op_seq, &builder);
+  });
+
+  auto code = builder.releaseCode();
+
+  for (auto &tensor_builder : tensor_builders)
+  {
+    tensor_builder->allocateConsts();
+  }
+
+  // TODO Add optimization passes
+
+  // Initialize constant tensors
+  for (const auto backend : backend::BackendManager::get().getAll())
+  {
+    graph.backend_resolver()->getBackendContext(backend)->constant_initializer->run();
+  }
+
+  for (auto &&e : code)
+  {
+    e.fn->prepare();
+    auto backend = e.elem.lower_info->backend();
+    auto tensor_builder = graph.backend_resolver()->getBackendContext(backend)->tensor_builder;
+    tensor_builder->postFunctionPrepare();
+  }
+
+  for (auto &tensor_builder : tensor_builders)
+  {
+    tensor_builder->allocateNonconsts();
+  }
+
+  for (auto &tensor_builder : tensor_builders)
+  {
+    tensor_builder->finalize();
+  }
+
+  // Wrap tensors as Object and store them to plan
+  for (auto &tensor_builder : tensor_builders)
+  {
+    tensor_builder->iterate([&](const ir::OperandIndex &index) {
+      auto object = tensor_builder->tensorAt(index);
+      operand_context->set(index, object);
+    });
+  }
+
+  // Prepare each TensorManager on each backend
+  auto tensor_mgrs = nnfw::cpp14::make_unique<backend::TensorManagerSet>();
+  for (auto &tensor_builder : tensor_builders)
+  {
+    tensor_mgrs->insert(tensor_builder->releaseTensorManager());
+  }
+
+  auto exec =
+      new exec::LinearExecutor{graph, operand_context, std::move(tensor_mgrs), std::move(code)};
+
+  const std::string trace_filepath = util::getConfigString(util::config::TRACE_FILEPATH);
+  if (!trace_filepath.empty())
+  {
+    std::unique_ptr<exec::IExecutionObserver> ctp =
+        nnfw::cpp14::make_unique<exec::ChromeTracingObserver>(trace_filepath);
+    exec->addObserver(std::move(ctp));
+  }
+
+  return exec;
+}
+
+exec::IExecutor *ExecutorFactory::createDataflowExecutor(ir::Graph &graph, bool parallel)
+{
+  auto operand_context = std::make_shared<OperandContext>();
+
+  graph.subgraphs().iterate([&](const ir::SubgraphIndex &, const ir::OpSequence &subg) {
+    auto subtensor_analyzer = SubTensorAnalyzer{graph};
+    subg.accept(subtensor_analyzer);
+  });
+
+  // Fix shapes and register tensors
+  graph.subgraphs().iterate([&](const ir::SubgraphIndex &subg_index, const ir::OpSequence &subg) {
+    auto backend = graph.getLowerInfo(subg_index)->backend();
+    auto shape_fixer = graph.backend_resolver()->getBackendContext(backend)->shape_fixer;
+    shape_fixer->fix(subg);
+    const auto tensor_register =
+        graph.backend_resolver()->getBackendContext(backend)->tensor_register;
+    tensor_register->registerTensors(subg, graph.getLowerInfo());
+  });
+
+  graph.operands().iterate([&](const ir::OperandIndex &ind, const ir::Operand &obj) {
+    const auto lower_info = graph.getLowerInfo(ind);
+    for (auto factor : lower_info->def_factors())
+    {
+      auto backend = factor.backend();
+      auto tensor_builder = graph.backend_resolver()->getBackendContext(backend)->tensor_builder;
+
+      if (!tensor_builder->isRegistered(ind))
+      {
+        // These tensors do not exist in any op_seq (No use and def)
+        // These tensors cannot be a SubTensor
+        assert(obj.parent_info() == nullptr);
+
+        const auto info = obj.info();
+        const auto backend_layout = lower_info->def_factors().getOnlyElement().layout();
+        // TODO Change tensor info to have permuted shape
+        tensor_builder->registerTensorInfo(ind, info, backend_layout, obj.isConstant());
+      }
+
+      // Is not SubTensor?
+      if (!backend->config()->SupportSubTensorAlloc() || obj.parent_info() == nullptr)
+      {
+        // To make this never be deallocated, this is a workaround to use static memory planner
+        tensor_builder->notifyFirstUse(ind);
+      }
+    }
+  });
+
+  auto tensor_builders = graph.backend_resolver()->tensor_builders();
+
+  for (auto &tensor_builder : tensor_builders)
+  {
+    tensor_builder->prepare();
+  }
+
+  class ExecutionBuilder : public IExecutionBuilder
+  {
+  public:
+    void append(std::unique_ptr<exec::IFunction> &&fn) override
+    {
+      auto itr = _code_map.find(_next_index);
+      if (itr == _code_map.end())
+      {
+        _code_map[_next_index] = nnfw::cpp14::make_unique<exec::FunctionSequence>();
+      }
+      _code_map[_next_index]->append(std::move(fn));
+    };
+
+    // TODO Remove this method and make `append` to get index value as an argument
+    void setNextIndex(const ir::SubgraphIndex next_index) { _next_index = next_index; }
+
+    exec::DataflowExecutor::CodeMap &&releaseCodeMap() { return std::move(_code_map); }
+
+  private:
+    ir::SubgraphIndex _next_index;
+    exec::DataflowExecutor::CodeMap _code_map;
+  };
+
+  auto execution_builder = nnfw::cpp14::make_unique<ExecutionBuilder>();
+
+  // Generate kernels
+  graph.subgraphs().iterate([&](const ir::SubgraphIndex &subg_index, const ir::OpSequence &subg) {
+    auto backend = graph.getLowerInfo(subg_index)->backend();
+    auto constant_initializer =
+        graph.backend_resolver()->getBackendContext(backend)->constant_initializer;
+    constant_initializer->generate(subg, graph.operands());
+    // TODO This approach is temporal. See declaration of `setNextIndex`.
+    execution_builder->setNextIndex(subg_index);
+    auto kernel_gen = graph.backend_resolver()->getBackendContext(backend)->kernel_gen;
+    kernel_gen->generate(subg, execution_builder.get());
+  });
+
+  for (const auto &tensor_builder : tensor_builders)
+  {
+    tensor_builder->allocateConsts();
+  }
+
+  // Initialize constant tensors
+  for (const auto backend : backend::BackendManager::get().getAll())
+  {
+    graph.backend_resolver()->getBackendContext(backend)->constant_initializer->run();
+  }
+
+  exec::DataflowExecutor::CodeMap code_map = execution_builder->releaseCodeMap();
+
+  for (auto &it : code_map)
+  {
+    auto subg_index = it.first;
+    auto &function_sequence = *(it.second);
+
+    function_sequence.iterate([&](exec::IFunction &ifunc) {
+      // NOTE. It may need avoiding prepare() for some operations
+      // Ref: https://github.sec.samsung.net/STAR/nnfw/issues/7326
+      ifunc.prepare();
+      auto backend = graph.getLowerInfo(subg_index)->backend();
+      auto tensor_builder = graph.backend_resolver()->getBackendContext(backend)->tensor_builder;
+      tensor_builder->postFunctionPrepare();
+    });
+  }
+
+  for (const auto &tensor_builder : tensor_builders)
+  {
+    tensor_builder->allocateNonconsts();
+  }
+
+  for (auto &tensor_builder : tensor_builders)
+  {
+    tensor_builder->finalize();
+  }
+
+  // Wrap tensors as Object and store them to plan
+  for (auto &tensor_builder : tensor_builders)
+  {
+    tensor_builder->iterate([&](const ir::OperandIndex &index) {
+      auto object = tensor_builder->tensorAt(index);
+      operand_context->set(index, object);
+    });
+  }
+
+  // Prepare each TensorManager on each backend
+  auto tensor_mgrs = nnfw::cpp14::make_unique<backend::TensorManagerSet>();
+  for (auto &tensor_builder : tensor_builders)
+  {
+    tensor_mgrs->insert(tensor_builder->releaseTensorManager());
+  }
+
+  exec::ExecutorBase *exec = nullptr;
+  if (parallel)
+  {
+    exec = new exec::ParallelExecutor{graph, operand_context, std::move(tensor_mgrs),
+                                      std::move(code_map)};
+  }
+  else
+  {
+    exec = new exec::DataflowExecutor{graph, operand_context, std::move(tensor_mgrs),
+                                      std::move(code_map)};
+    if (util::getConfigBool(util::config::PROFILING_MODE))
+    {
+      auto et = std::make_shared<backend::ExecTime>(backend::BackendManager::get().getAll());
+      std::unique_ptr<exec::IExecutionObserver> obs =
+          nnfw::cpp14::make_unique<exec::ProfileObserver>(et);
+      exec->addObserver(std::move(obs));
+    }
+  }
+
+  const std::string trace_filepath = util::getConfigString(util::config::TRACE_FILEPATH);
+  if (!trace_filepath.empty())
+  {
+    std::unique_ptr<exec::IExecutionObserver> ctp =
+        nnfw::cpp14::make_unique<exec::ChromeTracingObserver>(trace_filepath);
+    exec->addObserver(std::move(ctp));
+  }
+
+  return exec;
+}
+
+} // namespace compiler
+} // namespace neurun
diff --git a/runtime/neurun/core/src/compiler/ExecutorFactory.h b/runtime/neurun/core/src/compiler/ExecutorFactory.h
new file mode 100644
index 000000000..6da4ffc5e
--- /dev/null
+++ b/runtime/neurun/core/src/compiler/ExecutorFactory.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_COMPILER_EXECUTOR_FACTORY_H__
+#define __NEURUN_COMPILER_EXECUTOR_FACTORY_H__
+
+#include <unordered_map>
+
+#include "exec/IExecutor.h"
+#include "ir/Graph.h"
+
+namespace neurun
+{
+namespace compiler
+{
+
+class ExecutorFactory
+{
+public:
+  static ExecutorFactory &get();
+
+public:
+  exec::IExecutor *create(const std::string &id, ir::Graph &graph);
+
+private:
+  ExecutorFactory();
+
+private:
+  static exec::IExecutor *createLinearExecutor(ir::Graph &graph);
+  static exec::IExecutor *createDataflowExecutor(ir::Graph &graph, bool parallel);
+
+private:
+  std::unordered_map<std::string, std::function<exec::IExecutor *(ir::Graph &)>> _map;
+};
+
+} // namespace compiler
+} // namespace neurun
+
+#endif // __NEURUN_COMPILER_EXECUTOR_FACTORY_H__
diff --git a/runtime/neurun/core/src/compiler/HEScheduler.cc b/runtime/neurun/core/src/compiler/HEScheduler.cc
new file mode 100644
index 000000000..aec68d655
--- /dev/null
+++ b/runtime/neurun/core/src/compiler/HEScheduler.cc
@@ -0,0 +1,628 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/Operand.h"
+#include "compiler/HEScheduler.h"
+#include "ir/Graph.h"
+#include "util/ConfigSource.h"
+#include "compiler/IExecutionBuilder.h"
+#include "compiler/BackendResolver.h"
+#include "backend/IShapeFixer.h"
+#include "util/logging.h"
+#include "util/Utils.h"
+#include "exec/FunctionSequence.h"
+#include <cassert>
+#include <cmath>
+#include <chrono>
+
+namespace neurun
+{
+
+namespace compiler
+{
+static uint32_t getOperationsFlattenedIOSize(const ir::Graph &graph, const ir::Operation &node)
+{
+  uint32_t size = 0;
+  for (const auto &input : node.getInputs())
+  {
+    size += graph.operands().at(input).info().total_size();
+  }
+  for (const auto &output : node.getOutputs())
+  {
+    size += graph.operands().at(output).info().total_size();
+  }
+  return size;
+}
+
+static bool isQuant(const ir::Graph &graph, const ir::Operation &node)
+{
+  for (const auto &input : node.getInputs())
+  {
+    const auto &obj = graph.operands().at(input);
+    if (obj.typeInfo().type() == ir::DataType::QUANT8_ASYMM)
+    {
+      return true;
+    }
+  }
+  return false;
+}
+
+static bool isWorkaroundSkip(const ir::Graph &graph, const backend::Backend *backend,
+                             const ir::Operation &node, bool quant)
+{
+  /* TODO: this is workaround, come up with better solution if have.
+      Adding exception in stage doesn't help. Because if there is a record for add without
+      broadcast, scheduling will select it since it doesn't distinguish broadcast and
+      non-broadcast like it does for quant non-quantized*/
+  if (backend->config()->id() == "cpu" &&
+      (node.opcode() == ir::OpCode::Add || node.opcode() == ir::OpCode::Sub ||
+       node.opcode() == ir::OpCode::Mul))
+  {
+    const auto lhs_index{node.getInputs().at(ir::operation::Add::Input::LHS)};
+    const auto rhs_index{node.getInputs().at(ir::operation::Add::Input::RHS)};
+    /*Broadcasting isn't supported on CPU: no way to differ the existing exec_time record with and
+     * without broadcasting*/
+    if (!(graph.operands().at(lhs_index).shape() == graph.operands().at(rhs_index).shape()))
+    {
+      return true;
+    }
+  }
+  /* TODO: this is workaround, come up with better solution if have.
+          Adding exception in stage doesn't help. Because if there is a record for Mul without
+          broadcast, scheduling will select it since it doesn't distinguish broadcast and
+          non-broadcast like it does for quant non-quantized*/
+  else if (backend->config()->id() == "acl_neon" && node.opcode() == ir::OpCode::Mul)
+  {
+    const auto lhs_index{node.getInputs().at(ir::operation::Mul::Input::LHS)};
+    const auto rhs_index{node.getInputs().at(ir::operation::Mul::Input::RHS)};
+
+    // Nontrivial broadcasting isn't supported yet
+    if (quant ||
+        !(graph.operands().at(lhs_index).shape() == graph.operands().at(rhs_index).shape()))
+    {
+      return true;
+    }
+  }
+  return false;
+}
+
+// if a node can be merged into op_seq
+static bool isMergeable(const ir::Graph &graph, const ir::Operation &node)
+{
+  size_t prev_op_cnt = 0;
+  for (const auto &input : node.getInputs())
+  {
+    // only valid_inputs
+    const auto &operand = graph.operands().at(input);
+    if (operand.isConstant())
+      continue;
+
+    // This operand is output of operation, not weight or bias
+    if (operand.getDef().list().size() > 0)
+      ++prev_op_cnt;
+
+    // Current node has multiple inputs as concat or at the beginning of the separated branch
+    if (prev_op_cnt > 1 || operand.getUses().list().size() > 1)
+    {
+      return false;
+    }
+  }
+  return true;
+}
+
+void HEScheduler::scheduleShufflingBackends()
+{
+  VERBOSE(HEScheduler::schedule)
+      << "Started task scheduling: uses all backends to get more metrics for data transfer"
+      << std::endl;
+  size_t backend_ind = 0;
+  for (const auto &rank : _rank_to_op)
+  {
+    VERBOSE(HEScheduler::schedule) << "scheduling (" << rank.second.value() << ")" << std::endl;
+    const auto &node = _graph->operations().at(rank.second);
+    const bool quant = isQuant(*_graph, node);
+    const auto size = getOperationsFlattenedIOSize(*_graph, node);
+    for (size_t i = 0;; ++i)
+    {
+      if (i == _all_backends.size())
+      {
+        // wasn't able to find backend
+        assert(false);
+        break;
+      }
+      if (backend_ind == _all_backends.size())
+      {
+        backend_ind = 0;
+      }
+      if (isWorkaroundSkip(*_graph, _all_backends[backend_ind], node, quant))
+      {
+        ++backend_ind;
+        continue;
+      }
+      const auto exec_time =
+          _exec_time->getOperationExecTime(_all_backends[backend_ind], node.name(), quant, size);
+      // Scheduling to measure data transfer must be done after measuring all backends separately
+      assert(exec_time != _exec_time->NOT_FOUND);
+      if (exec_time == _exec_time->getMax())
+      {
+        ++backend_ind;
+        continue;
+      }
+      _backend_resolver->setBackend(rank.second, _all_backends[backend_ind]);
+      VERBOSE(HEScheduler::schedule) << "backend for " << node.name() << " is "
+                                     << _all_backends[backend_ind]->config()->id() << std::endl;
+      ++backend_ind;
+      break;
+    }
+  }
+}
+
+bool HEScheduler::isNodeProfiled(const ir::Operation &node)
+{
+  const bool quant = isQuant(*_graph, node);
+  const auto size = getOperationsFlattenedIOSize(*_graph, node);
+  for (const auto *backend : _all_backends)
+  {
+    const auto exec_time = _exec_time->getOperationExecTime(backend, node.name(), quant, size);
+    if (exec_time == _exec_time->NOT_FOUND)
+      return false;
+  }
+  return true;
+}
+
+void HEScheduler::scheduleBranch(const ir::OperationIndex &index,
+                                 ir::OperationIndexMap<bool> &scheduled)
+{
+  auto loc_index = index;
+  const backend::Backend *parent_backend = nullptr;
+  while (true)
+  {
+    if (scheduled[loc_index])
+    {
+      return;
+    }
+    if (!schedule(loc_index, parent_backend))
+    {
+      return;
+    }
+    scheduled[loc_index] = true;
+    parent_backend = _backend_resolver->getBackend(loc_index);
+
+    const auto &node = _graph->operations().at(loc_index);
+    /* get the only output operand, that is input of the next single operation
+     *   and just this nodes output.*/
+    if (node.getOutputs().size() != 1)
+    {
+      return;
+    }
+    const auto &only_out_operand = _graph->operands().at(*node.getOutputs().begin());
+    loc_index = only_out_operand.getUses().list().front();
+    /* verify, that next node is neither beginning nor ending node of a branch*/
+    const auto &next_node = _graph->operations().at(loc_index);
+    if (!isMergeable(*_graph, next_node))
+    {
+      return;
+    }
+  }
+}
+
+std::unique_ptr<compiler::BackendResolver> HEScheduler::schedule(const ir::Graph &graph)
+{
+  _graph = &graph;
+  VERBOSE(HEScheduler::schedule) << "task scheduling started" << std::endl;
+  // Make ranks and save in descending order
+  makeRank();
+
+  for (const auto *backend : _all_backends)
+  {
+    _backends_avail_time.emplace(backend, std::map<int64_t, int64_t>{{0, 0}});
+  }
+
+  const bool is_profiling = util::getConfigBool(util::config::PROFILING_MODE);
+  if (is_profiling)
+  {
+    // Check if profiling info about all backend/node pairs already exists
+    bool all_nodes_are_profiled = true;
+    _graph->operations().iterate([&](const ir::OperationIndex &, const ir::Operation &op) {
+      if (all_nodes_are_profiled)
+        all_nodes_are_profiled = isNodeProfiled(op);
+    });
+
+    // If all nodes are already profiled - schedule backends in such order, so more profiling
+    // information about between-backends data transfer could be collected
+    if (all_nodes_are_profiled)
+    {
+      scheduleShufflingBackends();
+      VERBOSE(HEScheduler::schedule) << "task scheduling finished" << std::endl;
+      return std::move(_backend_resolver);
+    }
+  }
+
+  ir::OperationIndexMap<bool> visited;
+  graph.operations().iterate(
+      [&](const ir::OperationIndex &index, const ir::Operation &) { visited[index] = false; });
+  // for each task select the backend with the smallest earliest finishing time(eft)
+  for (const auto &rank : _rank_to_op)
+  {
+    scheduleBranch(rank.second, visited);
+  }
+  VERBOSE(HEScheduler::schedule) << "task scheduling finished" << std::endl;
+  return std::move(_backend_resolver);
+}
+
+int64_t HEScheduler::getOpTime(const backend::Backend *backend, const std::string &operation,
+                               bool quant, uint32_t size)
+{
+  const auto time = _exec_time->getOperationExecTime(backend, operation, quant, size);
+  if (time != _exec_time->NOT_FOUND)
+    return time;
+
+  return _is_supported.at(backend).at(operation) ? 1 : _exec_time->getMax();
+}
+
+int64_t HEScheduler::getPermuteTime(const backend::Backend *src_backend,
+                                    const backend::Backend *dst_backend, bool quant, uint32_t size)
+{
+  const auto time = _exec_time->getPermuteTime(src_backend, dst_backend, quant, size);
+  if (time != _exec_time->NOT_FOUND)
+    return time;
+
+  // Makes the scheduler prefer keeping computations on one backend
+  return size / 200;
+}
+
+int64_t HEScheduler::tryBackend(const ir::Operation &node, const backend::Backend *backend)
+{
+  // if there is no profiling info don't use this backend during scheduling
+  if (!util::getConfigBool(util::config::PROFILING_MODE))
+  {
+    VERBOSE(HEScheduler::tryBackend)
+        << "Trying to HE schedule while there is no profiling info for " << node.name()
+        << " on backend " << backend->config()->id() << ". So this backend won't be used. "
+        << std::endl;
+    _is_supported[backend][node.name()] = false;
+    return _exec_time->getMax();
+  }
+  auto iter = _is_supported.find(backend);
+  if (iter != _is_supported.end())
+  {
+    auto it2 = iter->second.find(node.name());
+    if (it2 != iter->second.end())
+    {
+      return _is_supported[backend][node.name()] ? 1 : _exec_time->getMax();
+    }
+  }
+  try
+  {
+    node.accept(*_backend_resolver->getBackendContext(backend)->shape_fixer);
+
+    _is_supported[backend][node.name()] = true;
+  }
+  catch (std::runtime_error &e)
+  {
+    _is_supported[backend][node.name()] = false;
+  }
+  return _is_supported[backend][node.name()] ? 1 : _exec_time->getMax();
+}
+
+void HEScheduler::makeRank()
+{
+  VERBOSE(HEScheduler::makeRank) << "task prioritizing" << std::endl;
+
+  _graph->operations().iterate(
+      [&](const ir::OperationIndex &index, const ir::Operation &) { DFSMaxRank(index); });
+
+  // Check that ranks are calculated for all operations(nodes)
+  _graph->operations().iterate([&](const ir::OperationIndex &index, const ir::Operation &) {
+    UNUSED_RELEASE(index);
+    assert(_op_to_rank->find(index) != _op_to_rank->end());
+  });
+  VERBOSE(HEScheduler::makeRank) << "task prioritizing finished" << std::endl;
+}
+
+int64_t HEScheduler::DFSMaxRank(const ir::OperationIndex &index)
+{
+  auto op_to_rank_it = _op_to_rank->find(index);
+  if (op_to_rank_it != _op_to_rank->end())
+    return op_to_rank_it->second;
+
+  const auto &node = _graph->operations().at(index);
+  int64_t rank = 0;
+  const bool quant = isQuant(*_graph, node);
+  const auto size = getOperationsFlattenedIOSize(*_graph, node);
+  auto supported_backends_quantity = static_cast<int64_t>(_all_backends.size());
+
+  const auto max_child_rank = DFSChildrenMaxRank(index);
+
+  // get average exec time of this op
+  for (const auto &backend : _all_backends)
+  {
+    auto exec_time = _exec_time->getOperationExecTime(backend, node.name(), quant, size);
+    if (exec_time == _exec_time->NOT_FOUND)
+    {
+      exec_time = tryBackend(node, backend);
+    }
+    if (exec_time < _exec_time->getMax())
+    {
+      rank += exec_time;
+    }
+    else
+    {
+      // this operation isn't supported in this backend
+      --supported_backends_quantity;
+    }
+  }
+  if (supported_backends_quantity == 0)
+  {
+    throw std::runtime_error{"Encountered unsupported op: " + node.name()};
+  }
+  rank /= supported_backends_quantity;
+
+  // get standard deviation
+  int64_t std = 0;
+  for (const auto backend : _all_backends)
+  {
+    const auto exec_time = getOpTime(backend, node.name(), quant, size);
+    if (exec_time < _exec_time->getMax())
+    {
+      std += (exec_time - rank) * (exec_time - rank);
+    }
+  }
+  std /= supported_backends_quantity;
+  if (std > 0)
+  {
+    std = static_cast<int>(std::sqrt(std));
+    rank *= std;
+  }
+  rank += max_child_rank;
+
+  assert(rank >= 0);
+  _rank_to_op.emplace(rank, index);
+  _op_to_rank->emplace(index, rank);
+  VERBOSE(HEScheduler::DFSMaxRank) << "rank of operation (" << index.value() << ")" << node.name()
+                                   << " is " << rank << std::endl;
+
+  return rank;
+}
+
+int64_t HEScheduler::DFSChildrenMaxRank(const ir::OperationIndex &index)
+{
+  const auto &node = _graph->operations().at(index);
+  int64_t max_child_rank = 0;
+  for (const auto &output : node.getOutputs())
+  {
+    const auto &operand = _graph->operands().at(output);
+    const bool quant = operand.typeInfo().type() == ir::DataType::QUANT8_ASYMM;
+    // average data transfer cost of this operand's data
+    int64_t avg_transfer_cost = 1;
+    for (const auto *backend : _all_backends)
+    {
+      for (const auto *other_backend : _all_backends)
+      {
+        if (backend == other_backend)
+        {
+          continue;
+        }
+        auto transfer_cost =
+            _exec_time->getPermuteTime(backend, other_backend, quant, operand.info().total_size());
+        if (transfer_cost == _exec_time->NOT_FOUND)
+        {
+          // Makes the scheduler prefer keeping computations on one backend
+          transfer_cost = operand.info().total_size() / 100;
+        }
+        avg_transfer_cost += transfer_cost;
+      }
+    }
+    avg_transfer_cost /= _all_backends.size();
+    for (const auto &use : operand.getUses().list())
+    {
+      const auto cur_child_rank = DFSMaxRank(use);
+      max_child_rank = std::max(max_child_rank, cur_child_rank + avg_transfer_cost);
+    }
+  }
+  return max_child_rank;
+}
+
+int64_t HEScheduler::backendAvailableTime(const backend::Backend *backend,
+                                          const int64_t &starting_time, const int64_t &time_amount)
+{
+  const auto backend_times = _backends_avail_time.at(backend);
+  // finishing and starting times of an op, that will come after current op
+  auto next_op_fst = backend_times.upper_bound(starting_time);
+  // finishing time of an op, that will come before current op
+  auto prev_op_ft = starting_time;
+  // until reach the "hole/gap", that is enough to run this op
+  while (next_op_fst != backend_times.end() && next_op_fst->second - prev_op_ft <= time_amount)
+  {
+    prev_op_ft = next_op_fst->first + 1;
+    ++next_op_fst;
+  }
+  return prev_op_ft;
+}
+
+bool HEScheduler::schedule(const ir::OperationIndex &index, const backend::Backend *parent_backend)
+{
+  VERBOSE(HEScheduler::schedule) << "scheduling (" << index.value() << ")" << std::endl;
+  int64_t eft = std::numeric_limits<int64_t>::max(), selected_exec_time = 0;
+  const auto &node = _graph->operations().at(index);
+
+  std::multimap<int64_t, int64_t> selected_transfer_st_exec_time;
+  // select the backend with the smallest eft of this task
+  const backend::Backend *chosen_backend = nullptr;
+  for (const auto *backend : _all_backends)
+  {
+    std::multimap<int64_t, int64_t> transfer_st_exec_time;
+    const auto est_and_et = ESTAndExecTime(backend, index, transfer_st_exec_time);
+
+    if (eft > est_and_et.first + est_and_et.second)
+    {
+      eft = est_and_et.first + est_and_et.second;
+      selected_exec_time = est_and_et.second;
+      chosen_backend = backend;
+      selected_transfer_st_exec_time = transfer_st_exec_time;
+    }
+  }
+
+  if (chosen_backend == nullptr)
+  {
+    throw std::runtime_error{"Fail to choose backend on scheduler"};
+  }
+
+  // this is part of a branch and it is assigned another backend
+  if (parent_backend && parent_backend != chosen_backend)
+  {
+    return false;
+  }
+  for (const auto &it : selected_transfer_st_exec_time)
+  {
+    auto prev_op_ft = backendAvailableTime(_cpu_backend, it.first, it.second);
+    _backends_avail_time[_cpu_backend].insert({prev_op_ft + it.second, prev_op_ft});
+  }
+
+  _ops_eft[index] = eft;
+  _backends_avail_time[chosen_backend].emplace(eft, eft - selected_exec_time);
+  _backend_resolver->setBackend(index, chosen_backend);
+
+  VERBOSE(HEScheduler::schedule) << "backend for " << node.name() << " is "
+                                 << chosen_backend->config()->id() << ". Its eft: " << eft
+                                 << std::endl;
+  return true;
+}
+
+std::pair<int64_t, int64_t>
+HEScheduler::ESTAndExecTime(const backend::Backend *backend, const ir::OperationIndex &index,
+                            std::multimap<int64_t, int64_t> &transfer_st_exec_time)
+{
+  const bool is_linear_exec = "Linear" == util::getConfigString(util::config::EXECUTOR);
+  const bool is_parallel_exec = "Parallel" == util::getConfigString(util::config::EXECUTOR);
+  // Permutation will cause creating a separate op_seq that contains just this permutation node.
+  // This isn't needed for Linear executor since it doesn't use subgraphs
+  // Number 1 ms is picked experimentally
+  int64_t permute_fine = 1000;
+  // Multiply cpu operations' exec time by 2 because in parallel executor it might be busy with
+  // permutation on other branches or non-nnfw specific tasks and have to wait for it.
+  // Number 2 is picked experimentally
+  const int64_t CPU_DELAY = 2;
+  const auto &node = _graph->operations().at(index);
+  const bool quant = isQuant(*_graph, node);
+  const auto size = getOperationsFlattenedIOSize(*_graph, node);
+  // if this node can be part of a op_seq, then assigning different backend will cause creating
+  // another op_seq
+  if (isMergeable(*_graph, node))
+  {
+    permute_fine *= 2;
+  }
+  if (isWorkaroundSkip(*_graph, backend, node, quant))
+  {
+    return {_exec_time->getMax(), _exec_time->getMax()};
+  }
+  // get average exec time of the op on this backend
+  auto exec_time = getOpTime(backend, node.name(), quant, size);
+  if (backend->config()->id() == "cpu" && is_parallel_exec)
+  {
+    exec_time *= CPU_DELAY;
+  }
+
+  // get max eft of direct (one level above) predecessors
+  auto max_pred_eft = predMaxEFT(backend, node, transfer_st_exec_time);
+
+  int64_t total_transfer_cost = 0;
+  std::vector<std::multimap<int64_t, int64_t>::iterator> inserted_permutations;
+  // Find free time for data transferring and insert it into backend taskset. This is needed:
+  //  1. Time for multiple permutations for this node's input is found correctly
+  //  2. If backend==cpu, then free time for this node must come after permutations
+  for (auto &it : transfer_st_exec_time)
+  {
+    if (is_parallel_exec)
+    {
+      it.second *= CPU_DELAY;
+    }
+    if (!is_linear_exec)
+    {
+      it.second += permute_fine;
+    }
+    total_transfer_cost += it.second;
+
+    const auto prev_op_ft = backendAvailableTime(_cpu_backend, it.first, it.second);
+
+    max_pred_eft = std::max(max_pred_eft, prev_op_ft + it.second);
+
+    const auto tmp = _backends_avail_time[_cpu_backend].emplace(prev_op_ft + it.second, prev_op_ft);
+    inserted_permutations.push_back(tmp.first);
+  }
+  // find the hole/gap, where this op can be put or the finishing time of the last assigned op
+  auto prev_op_ft = backendAvailableTime(backend, max_pred_eft, exec_time);
+
+  // Remove inserted permutation from cpu's task set
+  for (const auto &it : inserted_permutations)
+  {
+    _backends_avail_time[_cpu_backend].erase(it);
+  }
+
+  /* In case non-parallel executor measure just exec time and data transfer time
+   * because EFT(prev_op_ft) is the same for all backends. Since two operations
+   * can't be run simultaneously, finish of running operation must be waited for.
+   * When an operation starts, all backends are free. So, they need time just for
+   * data transfer.*/
+  if (!is_parallel_exec)
+  {
+    VERBOSE(HEScheduler::ESTAndExecTime)
+        << "exec_time of (" << index.value() << ") " << node.name() << " quant==" << quant << " on "
+        << backend->config()->id() << " is " << exec_time
+        << " microseconds. Data transfer cost: " << total_transfer_cost << std::endl;
+
+    return {total_transfer_cost, exec_time};
+  }
+  VERBOSE(HEScheduler::ESTAndExecTime)
+      << "exec_time of (" << index.value() << ") " << node.name() << " quant==" << quant << " on "
+      << backend->config()->id() << ": " << exec_time
+      << " microseconds. Backend available time: " << prev_op_ft
+      << " Parent's max eft: " << max_pred_eft - total_transfer_cost
+      << " data transfer cost: " << total_transfer_cost << std::endl;
+
+  return {prev_op_ft, exec_time};
+}
+
+int64_t HEScheduler::predMaxEFT(const backend::Backend *backend, const ir::Operation &node,
+                                std::multimap<int64_t, int64_t> &transfer_st_exec_time)
+{
+  int64_t max_pred_eft = 0;
+  for (const auto &input_operand_idx : node.getInputs())
+  {
+    const auto &input_operand = _graph->operands().at(input_operand_idx);
+    const bool quant = input_operand.typeInfo().type() == ir::DataType::QUANT8_ASYMM;
+
+    for (const auto &input_node_idx : input_operand.getDef().list())
+    {
+      // Data transfer cost from parent's node backend to current node's backend:
+      auto parent_backend = _backend_resolver->getBackend(input_node_idx);
+
+      max_pred_eft = std::max(max_pred_eft, _ops_eft.at(input_node_idx));
+      if (parent_backend != backend)
+      {
+        // Multiply operand size by 2 because size must describe input+output size
+        int64_t transfer_cost =
+            getPermuteTime(parent_backend, backend, quant, input_operand.info().total_size() * 2);
+        transfer_st_exec_time.emplace(_ops_eft.at(input_node_idx), transfer_cost);
+      }
+    }
+  }
+  return max_pred_eft;
+}
+
+} // namespace compiler
+
+} // namespace neurun
diff --git a/runtime/neurun/core/src/compiler/HEScheduler.h b/runtime/neurun/core/src/compiler/HEScheduler.h
new file mode 100644
index 000000000..538427065
--- /dev/null
+++ b/runtime/neurun/core/src/compiler/HEScheduler.h
@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file  HEScheduler.h
+ * @brief This file contains HEScheduler class to define and run task Heterogeneous Execution
+ * Scheduler
+ */
+
+#ifndef __NEURUN_COMPILER_H_E_SCHEDULER_H_
+#define __NEURUN_COMPILER_H_E_SCHEDULER_H_
+
+#include "compiler/IScheduler.h"
+#include "ir/Graph.h"
+#include "backend/ExecTime.h"
+#include "backend/Backend.h"
+#include "cpp14/memory.h"
+#include "ir/OperationIndexMap.h"
+#include <map>
+#include <memory>
+
+namespace neurun
+{
+
+namespace compiler
+{
+/**
+ * @brief Class to schedule tasks
+ */
+class HEScheduler : IScheduler
+{
+public:
+  /**
+   * @brief     Construct a new Heterogeneous Execution Scheduler object
+   * @param[in] model Graph model
+   * @param[in] backend_resolver backend resolver
+   */
+  HEScheduler(const ir::Operands &operands, std::vector<const backend::Backend *> backends,
+              const std::shared_ptr<backend::custom::IKernelBuilder> &kb)
+      : _is_supported{}, _backends_avail_time{}, _ops_eft{},
+        _op_to_rank{std::make_shared<ir::OperationIndexMap<int64_t>>()},
+        _all_backends(std::move(backends))
+  {
+    _backend_resolver =
+        nnfw::cpp14::make_unique<compiler::BackendResolver>(operands, _all_backends, kb);
+    _exec_time = nnfw::cpp14::make_unique<backend::ExecTime>(_all_backends);
+
+    // Find cpu backend
+    auto cpu_backend_it = std::find_if(
+        _all_backends.begin(), _all_backends.end(),
+        [](const backend::Backend *backend) { return backend->config()->id() == "cpu"; });
+    if (cpu_backend_it == _all_backends.end())
+      throw std::runtime_error("HEScheduler could be used only if 'cpu' backend is available");
+    _cpu_backend = *cpu_backend_it;
+  }
+
+public:
+  /**
+   * @brief   Task scheduling
+   *
+   * @note    The main idea is taken from HSIP algo:
+   *          https://www.hindawi.com/journals/sp/2016/3676149/
+   */
+  std::unique_ptr<compiler::BackendResolver> schedule(const ir::Graph &graph) final;
+  std::shared_ptr<ir::OperationIndexMap<int64_t>> getIndexedRanks() { return _op_to_rank; }
+
+private:
+  bool isNodeProfiled(const ir::Operation &);
+
+  bool schedule(const ir::OperationIndex &, const backend::Backend *parent_backend);
+  /**
+   * @brief   Get earliest starting time and execution time of an operation on a backend.
+   *
+   * @note  Returns a time when operation's inputs are ready and backend is available
+   *        It also returns exec time. If this is "cpu" backend, then exec_time*CPU_DELAY
+   *
+   * @param[in] backend: backend, for which to return the time
+   * @param[in] index: index of an operation
+   * @param[out] transfer_st_exec_time: est and exec time of data transfer operation
+   *
+   * @return earliest starting time and execution time
+   */
+  std::pair<int64_t, int64_t>
+  ESTAndExecTime(const backend::Backend *backend, const ir::OperationIndex &index,
+                 std::multimap<int64_t, int64_t> &transfer_st_exec_time);
+  /**
+   * @brief   Returns the latest finishing time of parents of a node.
+   *
+   * @param[in] backend: backend, for which to return the time
+   * @param[in] node: node to get eft of parents
+   * @param[out] transfer_st_exec_time: est and exec time of data transfer operation
+   *
+   * @return earliest finishing time of parent nodes
+   */
+  int64_t predMaxEFT(const backend::Backend *backend, const ir::Operation &node,
+                     std::multimap<int64_t, int64_t> &transfer_st_exec_time);
+
+  void makeRank();
+
+  int64_t DFSMaxRank(const ir::OperationIndex &index);
+
+  int64_t DFSChildrenMaxRank(const ir::OperationIndex &index);
+  /**
+   * @brief   Returns the time, when backend is available for at least given amount of time.
+   *
+   * @note  Returns either hole/gap between two performing two already scheduled operations,
+   *        or the finishing time of the last scheduled operation
+   *
+   * @param[in] backend backend, for which to return the time
+   * @param[in] starting_time time, starting which to look for gap
+   * @param[in] time_amount amount of the time, for which to look gap
+   *
+   * @return time, when backend has at least time_amount free time
+   */
+  int64_t backendAvailableTime(const backend::Backend *backend, const int64_t &starting_time,
+                               const int64_t &time_amount);
+
+  int64_t getOpTime(const backend::Backend *backend, const std::string &operation, bool quant,
+                    uint32_t size);
+
+  int64_t getPermuteTime(const backend::Backend *src_backend, const backend::Backend *dst_backend,
+                         bool quant, uint32_t size);
+
+  void scheduleShufflingBackends();
+
+  int64_t tryBackend(const ir::Operation &node, const backend::Backend *backend);
+
+  /**
+   * @brief   Schedule a node and its successor until:
+   *            1. there is no branching or connection of multiple branches
+   *            2. for subsequent nodes: other than predecessor's backend is prefered
+   *
+   * @param[in] index: index of an operation
+   * @param[in] scheduled: a map to check if this node has already been scheduled
+   *
+   * @return N/A
+   */
+  void scheduleBranch(const ir::OperationIndex &index, ir::OperationIndexMap<bool> &scheduled);
+
+private:
+  // This variable stores backend/node pairs with unknown execution time, and hints scheduler
+  // whether it should assign these backends to these nodes:
+  // * It stores false for unsupported nodes
+  // * During rank calculation with enabled profiling mode it stores true for supported nodes
+  std::unordered_map<const backend::Backend *, std::unordered_map<std::string, bool>> _is_supported;
+  // Finishing and starting time of each backend
+  std::unordered_map<const backend::Backend *, std::map<int64_t, int64_t>> _backends_avail_time;
+  ir::OperationIndexMap<int64_t> _ops_eft;
+  std::multimap<int64_t, ir::OperationIndex, std::greater<int64_t>> _rank_to_op;
+  std::shared_ptr<ir::OperationIndexMap<int64_t>> _op_to_rank;
+  std::unique_ptr<compiler::BackendResolver> _backend_resolver;
+  std::unique_ptr<backend::ExecTime> _exec_time;
+  const ir::Graph *_graph{nullptr};
+  const std::vector<const backend::Backend *> _all_backends;
+  const backend::Backend *_cpu_backend{nullptr};
+};
+
+} // namespace compiler
+
+} // namespace neurun
+
+#endif // __NEURUN_COMPILER_H_E_SCHEDULER_H_
diff --git a/runtime/neurun/core/src/compiler/IScheduler.h b/runtime/neurun/core/src/compiler/IScheduler.h
new file mode 100644
index 000000000..dc1373ff9
--- /dev/null
+++ b/runtime/neurun/core/src/compiler/IScheduler.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_CORE_COMPILER_I_SCHEDULER_H__
+#define __NEURUN_CORE_COMPILER_I_SCHEDULER_H__
+
+#include "BackendResolver.h"
+#include "ir/Graph.h"
+
+namespace neurun
+{
+namespace compiler
+{
+
+struct IScheduler
+{
+  virtual ~IScheduler() = default;
+
+  virtual std::unique_ptr<BackendResolver> schedule(const ir::Graph &graph) = 0;
+};
+
+} // namespace compiler
+} // namespace neurun
+
+#endif // __NEURUN_CORE_COMPILER_I_SCHEDULER_H__
diff --git a/runtime/neurun/core/src/compiler/Linear.cc b/runtime/neurun/core/src/compiler/Linear.cc
new file mode 100644
index 000000000..b18dcea02
--- /dev/null
+++ b/runtime/neurun/core/src/compiler/Linear.cc
@@ -0,0 +1,317 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <algorithm>
+
+#include "Linear.h"
+
+#include "backend/IShapeFixer.h"
+#include "backend/IConfig.h"
+#include "backend/IConstantInitializer.h"
+#include "backend/ITensorRegister.h"
+#include "backend/Backend.h"
+#include "compiler/SubTensorInfo.h"
+
+#include "util/logging.h"
+
+namespace neurun
+{
+namespace compiler
+{
+
+Linear::Linear(ir::Graph &graph) : _graph(graph)
+{
+  // Get SubgraphSequence by topological sorting
+  {
+    ir::Subgraphs &subgraphs = _graph.subgraphs();
+    ir::Operands &operands = _graph.operands();
+    // subgraphs can't access a op_seq by an operand so that input_to_subgs can offer it
+    std::unordered_map<ir::OperandIndex, std::list<ir::SubgraphIndex>> input_to_subgs;
+
+    // Get the relations between input/op_seq to be used for dfs-post-iter
+    //
+    //      [0]             # input -> _input_to_op_seqes[0] = {SUBG0}
+    //       |
+    //     [SUBG0]
+    //       |
+    //      [1]-----.       # input -> _input_to_op_seqes[1] = {SUBG1, SUBG2}
+    //       |      |
+    //     [SUBG1] [SUBG2]
+    //       |      |
+    //      [2]    [3]      # input -> _input_to_op_seqes[2] = {SUBG3}
+    //       \      /       # input -> _input_to_op_seqes[3] = {SUBG3}
+    //       [SUBG3]
+    //         |
+    //        [4]
+    subgraphs.iterate([&](const ir::SubgraphIndex &subg_idx, ir::OpSequence &subg) {
+      for (auto input : subg.getInputs())
+      {
+        // only valid_inputs
+        const auto &operand = operands.at(input);
+        if (operand.isConstant())
+          continue;
+
+        auto it = input_to_subgs.find(input);
+        if (it == input_to_subgs.end())
+        {
+          std::list<ir::SubgraphIndex> list{subg_idx};
+          input_to_subgs[input] = list;
+        }
+        else
+        {
+          it->second.push_back(subg_idx);
+        }
+      }
+    });
+
+    std::unordered_map<ir::SubgraphIndex, bool> visited;
+    subgraphs.iterate(
+        [&](const ir::SubgraphIndex &index, const ir::OpSequence &) { visited[index] = false; });
+
+    std::function<void(const ir::SubgraphIndex &, ir::OpSequence &)> dfs_recursive =
+        [&](const ir::SubgraphIndex &index, ir::OpSequence &subg) -> void {
+      if (visited[index])
+        return;
+      visited[index] = true;
+
+      // The outputs should be not constants
+      for (auto output : subg.getOutputs())
+      {
+        const auto it = input_to_subgs.find(output);
+        if (it != input_to_subgs.end())
+        {
+          const auto &subg_index_list = it->second;
+          for (const auto &index : subg_index_list)
+          {
+            auto &subg = subgraphs.at(index);
+            dfs_recursive(index, subg);
+          }
+        }
+      }
+
+      _elements.emplace_back(&subgraphs.at(index), _graph.getLowerInfo(index));
+    };
+
+    subgraphs.iterate(dfs_recursive);
+
+    // All of the nodes must have been visited.
+    assert(std::all_of(visited.begin(), visited.end(),
+                       [](const std::pair<const ir::SubgraphIndex, bool> &v) { return v.second; }));
+
+    // NOTE. Now these op_seq are on the reverse order
+    std::reverse(_elements.begin(), _elements.end());
+  }
+
+  {
+    const auto &backendToString = [](const neurun::backend::Backend *backend) {
+      assert(backend);
+      std::string str;
+      str += backend->config()->id();
+      str += " ";
+      return "{ " + str + "}";
+    };
+
+    VERBOSE(Linear) << "Final SubgraphSequence" << std::endl;
+    for (const auto &element : _elements)
+    {
+      const auto subg = element.op_seq;
+      const auto lower_info = element.lower_info;
+      VERBOSE(Linear) << "* SUBG"
+                      << " " << backendToString(lower_info->backend()) << " " << subg->getStr()
+                      << std::endl;
+    }
+  }
+}
+
+void Linear::accept(ir::OperationVisitor &&visitor) const
+{
+  for (const auto &e : _elements)
+  {
+    e.op_seq->accept(visitor);
+  }
+}
+
+void Linear::planTensors()
+{
+  ir::OperandIndexMap<std::shared_ptr<backend::ITensorBuilder>> tensor_builder_map;
+
+  // NOTE
+  // While current ITensorBuilder exposes registerSubTensorInfo for subtensor,
+  // this stage uses registerSubTensorInfo() and notify{First|Last}Use()
+  // but handling subtensor should be processed on each backend. See #5726.
+  ir::OperandIndexMap<uint32_t> uses_map;
+  ir::OperandIndexMap<uint32_t> def_map;
+  ir::OperandIndexSequence constants;
+
+  iterate([&](const neurun::compiler::Linear::Element &element) {
+    const auto backend = element.lower_info->backend();
+    const auto tensor_register =
+        _graph.backend_resolver()->getBackendContext(backend)->tensor_register;
+    tensor_register->registerTensors(*element.op_seq, _graph.getLowerInfo());
+  });
+
+  // Prepare scanning
+  _graph.operands().iterate([&](const ir::OperandIndex &ind, const ir::Operand &obj) {
+    const auto lower_info = _graph.getLowerInfo(ind);
+    // TODO Remove if neurun doesn't support anymore such as
+    // GeneratedTests.reshape_quant8_weights_as_inputs
+    if (lower_info->def_factors().size() == 0 && lower_info->use_factors().size() == 0 &&
+        !_graph.getInputs().contains(ind))
+    {
+      VERBOSE(LINEAR) << "Operand #" << ind.value() << " will be not used. no more process."
+                      << std::endl;
+      return;
+    }
+
+    uses_map[ind] = obj.getUses().size();
+    def_map[ind] = obj.getDef().size(); // should be 1 or 0
+
+    bool is_const = obj.isConstant();
+    if (is_const)
+    {
+      constants.append(ind);
+    }
+
+    for (auto factor : lower_info->def_factors())
+    {
+      auto backend = factor.backend();
+      auto tensor_builder = _graph.backend_resolver()->getBackendContext(backend)->tensor_builder;
+
+      if (!tensor_builder->isRegistered(ind))
+      {
+        // These tensors do not exist in any op_seq (No use and def)
+        // These tensors cannot be a SubTensor
+        assert(obj.parent_info() == nullptr);
+
+        const auto info = obj.info();
+        const auto backend_layout = lower_info->def_factors().getOnlyElement().layout();
+        // TODO Change tensor info to have permuted shape
+        tensor_builder->registerTensorInfo(ind, info, backend_layout, is_const);
+      }
+
+      tensor_builder_map[ind] = tensor_builder;
+    }
+  });
+
+  // If a tensor is model output, increase the use of the tensor.
+  // This aim is same to above one.
+  for (const auto &ind : _graph.getOutputs())
+  {
+    uses_map[ind]++;
+  }
+
+  // Start scanning to do notify{First|Last}Use for each tensor
+
+  // If a tensor is a constant, increase the use of the tensor.
+  // It makes the tensor not be dealloced. It means these will be deallocated last.
+  // And allocate constant operands first
+  VERBOSE(LINEAR) << "TENSORS as CONSTANT" << std::endl;
+  for (const auto &ind : constants)
+  {
+    uses_map[ind]++;
+    tensor_builder_map[ind]->notifyFirstUse(ind);
+  }
+
+  // Allocate Model's inputs
+  VERBOSE(LINEAR) << "TENSORS as MODEL INPUT" << std::endl;
+  for (const auto &ind : _graph.getInputs())
+  {
+    auto tensor_builder = tensor_builder_map[ind];
+    if (!tensor_builder) // for GeneratedTests.xxx_weights_as_inputs
+      continue;
+    tensor_builder->notifyFirstUse(ind);
+  }
+
+  // At each operation,
+  // 1. Scan DEF of outputs. If the DEF, allocate it
+  // 2. Scan USE of inputs. Decrease the USE and deallocate if the USE is 0
+  VERBOSE(LINEAR) << "TENSORS" << std::endl;
+  for (const auto &e : _elements)
+  {
+    for (const auto &op : e.op_seq->operations())
+    {
+      for (const auto &ind : op.node->getOutputs())
+      {
+        assert(def_map.find(ind) != def_map.end());
+        if (def_map[ind])
+        {
+          def_map[ind] = 0;
+          tensor_builder_map[ind]->notifyFirstUse(ind);
+        }
+      }
+
+      for (const auto &ind : op.node->getInputs())
+      {
+        assert(uses_map.find(ind) != uses_map.end());
+        assert(uses_map[ind] > 0);
+        uses_map[ind]--;
+        if (uses_map[ind] == 0)
+        {
+          tensor_builder_map[ind]->notifyLastUse(ind);
+        }
+      }
+    }
+  }
+
+  // Dispose and validate
+  for (const auto &ind : _graph.getOutputs())
+  {
+    --uses_map[ind];
+    if (uses_map[ind] == 0) // To prevent notifyLastUse from being called twice
+    {
+      tensor_builder_map[ind]->notifyLastUse(ind);
+    }
+  }
+
+  for (const auto &ind : constants)
+  {
+    --uses_map[ind];
+    if (uses_map[ind] == 0) // To prevent notifyLastUse from being called twice
+    {
+      tensor_builder_map[ind]->notifyLastUse(ind);
+    }
+  }
+
+  assert(
+      std::all_of(uses_map.begin(), uses_map.end(),
+                  [](std::pair<const ir::OperandIndex, uint32_t> it) { return it.second == 0; }));
+
+  assert(
+      std::all_of(def_map.begin(), def_map.end(),
+                  [](std::pair<const ir::OperandIndex, uint32_t> it) { return it.second == 0; }));
+}
+
+void Linear::iterate(const std::function<void(const Element &element)> &fn) const
+{
+  for (const auto &e : _elements)
+  {
+    fn(e);
+  }
+}
+
+void Linear::generateConstantInitializers(void) const
+{
+  iterate([&](const compiler::Linear::Element &element) {
+    auto backend = element.lower_info->backend();
+
+    auto constant_initializer =
+        _graph.backend_resolver()->getBackendContext(backend)->constant_initializer;
+    constant_initializer->generate(*element.op_seq, _graph.operands());
+  });
+}
+
+} // namespace compiler
+} // namespace neurun
diff --git a/runtime/neurun/core/src/compiler/Linear.h b/runtime/neurun/core/src/compiler/Linear.h
new file mode 100644
index 000000000..e10d03695
--- /dev/null
+++ b/runtime/neurun/core/src/compiler/Linear.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_COMPILER_LINEAR_H__
+#define __NEURUN_COMPILER_LINEAR_H__
+
+#include <vector>
+#include <memory>
+
+#include "ir/Subgraphs.h"
+#include "backend/ITensorBuilder.h"
+#include "ir/Graph.h"
+#include "compiler/BackendResolver.h"
+
+namespace neurun
+{
+namespace ir
+{
+struct OperationVisitor;
+} // namespace ir
+} // namespace neurun
+
+namespace neurun
+{
+namespace compiler
+{
+
+class Linear
+{
+public:
+  struct Element
+  {
+    const ir::OpSequence *op_seq;
+    const ir::operation::LowerInfo *lower_info;
+
+    Element() : op_seq{nullptr}, lower_info{nullptr} {}
+
+    Element(const ir::OpSequence *op_seq, const ir::operation::LowerInfo *lower_info)
+        : op_seq{op_seq}, lower_info{lower_info}
+    {
+      // DO NOTHING
+    }
+  };
+
+public:
+  Linear(ir::Graph &graph);
+
+public:
+  Linear(const Linear &linear) = delete;
+
+public:
+  void accept(ir::OperationVisitor &&visitor) const;
+
+  void planTensors();
+
+  void iterate(const std::function<void(const Element &element)> &fn) const;
+
+  void generateConstantInitializers(void) const;
+
+private:
+  ir::Graph &_graph;
+  std::vector<Element> _elements;
+};
+
+} // namespace compiler
+} // namespace neurun
+
+#endif // __NEURUN_COMPILER_LINEAR_H__
diff --git a/runtime/neurun/core/src/compiler/ManualScheduler.cc b/runtime/neurun/core/src/compiler/ManualScheduler.cc
new file mode 100644
index 000000000..1fb9d3759
--- /dev/null
+++ b/runtime/neurun/core/src/compiler/ManualScheduler.cc
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ManualScheduler.h"
+#include "ir/OpCode.h"
+#include "ir/Operations.Include.h"
+#include "backend/Backend.h"
+#include "backend/BackendManager.h"
+#include "backend/IConfig.h"
+#include "util/ConfigSource.h"
+#include "misc/string_helpers.h"
+
+namespace neurun
+{
+namespace compiler
+{
+
+std::unique_ptr<BackendResolver> ManualScheduler::schedule(const ir::Graph &graph)
+{
+  auto backend_resolver = nnfw::cpp14::make_unique<compiler::BackendResolver>(
+      graph.operands(), backend::BackendManager::get().getAll(), graph.getKernelBuilder());
+
+  // 1. Backend for All operations
+  auto backend_all_str = util::getConfigString(util::config::OP_BACKEND_ALLOPS);
+  backend::Backend *backend_all = nullptr;
+
+  if (backend_all_str.empty())
+  {
+    const auto backends_str = util::getConfigString(util::config::BACKENDS);
+    size_t prev_pos = 0;
+    auto pos = backends_str.find(";");
+    while (pos != std::string::npos)
+    {
+      backend_all_str = backends_str.substr(prev_pos, pos - prev_pos);
+      backend_all = backend::BackendManager::get().get(backend_all_str);
+      if (backend_all != nullptr)
+        break;
+
+      prev_pos = pos + 1;
+      pos = backends_str.find(";", prev_pos);
+    }
+    // if backends doesn't terminate with ";"
+    if (backend_all == nullptr && prev_pos < backends_str.size())
+    {
+      backend_all_str = backends_str.substr(prev_pos);
+      backend_all = backend::BackendManager::get().get(backend_all_str);
+    }
+  }
+  else
+  {
+    backend_all = backend::BackendManager::get().get(backend_all_str);
+  }
+
+  VERBOSE(ManualScheduler) << "Default backend for all ops: " << backend_all_str << std::endl;
+
+  graph.operations().iterate([&](const ir::OperationIndex &index, const ir::Operation &) {
+    backend_resolver->setBackend(index, backend_all);
+  });
+
+  // 2. Backend per operation type
+  std::unordered_map<ir::OpCode, backend::Backend *> op_type_map;
+  // By default, Custom uses cpu backend
+  op_type_map[ir::OpCode::Custom] = backend::BackendManager::get().get("cpu");
+
+#define OP(InternalName)                                                                      \
+  {                                                                                           \
+    const auto &backend_str = util::getConfigString(util::config::OP_BACKEND_##InternalName); \
+    if (!backend_str.empty())                                                                 \
+    {                                                                                         \
+      auto backend = backend::BackendManager::get().get(backend_str);                         \
+      VERBOSE(Lower) << "backend for " << #InternalName << ": " << backend_str << std::endl;  \
+      op_type_map[ir::OpCode::InternalName] = backend;                                        \
+    }                                                                                         \
+  }
+#include "ir/Operations.lst"
+#undef OP
+
+  graph.operations().iterate([&](const ir::OperationIndex &index, const ir::Operation &operation) {
+    auto itr = op_type_map.find(operation.opcode());
+    if (itr != op_type_map.end())
+    {
+      backend_resolver->setBackend(index, itr->second);
+    }
+  });
+
+  // 3. Backend per operation
+  try
+  {
+    auto map_str = util::getConfigString(util::config::OP_BACKEND_MAP);
+    auto key_val_list = nnfw::misc::split(map_str, ';');
+    for (const auto &key_val_str : key_val_list)
+    {
+      if (key_val_str.empty())
+      {
+        continue;
+      }
+
+      auto key_val = nnfw::misc::split(key_val_str, '=');
+      const auto &key_str = key_val.at(0);
+      const auto &val = key_val.at(1);
+      auto key = static_cast<uint32_t>(std::stoi(key_str));
+
+      graph.operations().at(ir::OperationIndex{key}); // Check if exist, or this wil throw
+      backend_resolver->setBackend(ir::OperationIndex{key},
+                                   backend::BackendManager::get().get(val));
+    }
+  }
+  catch (...)
+  {
+    VERBOSE(ManualScheduler) << "Invalid value from " << util::config::OP_BACKEND_MAP
+                             << ". Some of the given values are ignored" << std::endl;
+  }
+
+  // 4. Operations that are specially handled
+  //    All configuration above will be ignored(overwritten)
+  op_type_map[ir::OpCode::Permute] = backend::BackendManager::get().get("cpu");
+
+  // Dump final assignment
+  backend_resolver->iterate(
+      [&](const ir::OperationIndex &index, const backend::BackendContext &backend_ctx) {
+        VERBOSE(ManualScheduler) << "backend for operation #" << index.value() << ": "
+                                 << backend_ctx.backend->config()->id() << std::endl;
+      });
+
+  return backend_resolver;
+}
+
+} // namespace compiler
+} // namespace neurun
diff --git a/runtime/neurun/core/src/compiler/ManualScheduler.h b/runtime/neurun/core/src/compiler/ManualScheduler.h
new file mode 100644
index 000000000..a442cec08
--- /dev/null
+++ b/runtime/neurun/core/src/compiler/ManualScheduler.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_CORE_COMPILER_MANUAL_SCHEDULER_H__
+#define __NEURUN_CORE_COMPILER_MANUAL_SCHEDULER_H__
+
+#include "IScheduler.h"
+
+namespace neurun
+{
+namespace compiler
+{
+
+class ManualScheduler : public IScheduler
+{
+public:
+  std::unique_ptr<BackendResolver> schedule(const ir::Graph &graph) override;
+};
+
+} // namespace compiler
+} // namespace neurun
+
+#endif // __NEURUN_CORE_COMPILER_MANUAL_SCHEDULER_H__
diff --git a/runtime/neurun/core/src/compiler/OperandContext.cc b/runtime/neurun/core/src/compiler/OperandContext.cc
new file mode 100644
index 000000000..c06f6157b
--- /dev/null
+++ b/runtime/neurun/core/src/compiler/OperandContext.cc
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "OperandContext.h"
+
+#include <cassert>
+
+namespace neurun
+{
+namespace compiler
+{
+
+OperandContext &OperandContext::set(const ir::OperandIndex &id,
+                                    const std::shared_ptr<backend::operand::ITensor> &tensor)
+{
+  // Only one tensor for an id
+  assert(_tensors.find(id) == _tensors.end());
+  _tensors[id] = tensor;
+  return (*this);
+}
+
+void OperandContext::iterate(
+    const std::function<void(const ir::OperandIndex &, backend::operand::ITensor &)> &fn)
+{
+  for (auto &e : _tensors)
+  {
+    fn(e.first, *e.second);
+  }
+}
+
+} // namespace compiler
+} // namespace neurun
diff --git a/runtime/neurun/core/src/compiler/OperandContext.h b/runtime/neurun/core/src/compiler/OperandContext.h
new file mode 100644
index 000000000..da1a51bb9
--- /dev/null
+++ b/runtime/neurun/core/src/compiler/OperandContext.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_COMPILER_OPERAND_CONTEXT_H__
+#define __NEURUN_COMPILER_OPERAND_CONTEXT_H__
+
+#include "backend/operand/ITensor.h"
+#include "ir/OperandIndexMap.h"
+#include <unordered_map>
+#include <memory>
+
+namespace neurun
+{
+namespace compiler
+{
+
+class OperandContext
+{
+public:
+  OperandContext &set(const ir::OperandIndex &ind,
+                      const std::shared_ptr<backend::operand::ITensor> &tensor);
+
+public:
+  bool exist(const ir::OperandIndex &ind) const { return _tensors.find(ind) != _tensors.end(); }
+
+public:
+  std::shared_ptr<backend::operand::ITensor> at(const ir::OperandIndex &ind) const
+  {
+    return _tensors.at(ind);
+  }
+
+  std::shared_ptr<backend::operand::ITensor> &at(const ir::OperandIndex &ind)
+  {
+    return _tensors.at(ind);
+  }
+
+  void
+  iterate(const std::function<void(const ir::OperandIndex &, backend::operand::ITensor &)> &fn);
+
+private:
+  ir::OperandIndexMap<std::shared_ptr<backend::operand::ITensor>> _tensors;
+};
+
+} // namespace compiler
+} // namespace neurun
+
+#endif // __NEURUN_COMPILER_OPERAND_CONTEXT_H__
diff --git a/runtime/neurun/core/src/compiler/OperationValidator.cc b/runtime/neurun/core/src/compiler/OperationValidator.cc
new file mode 100644
index 000000000..74f76bdbe
--- /dev/null
+++ b/runtime/neurun/core/src/compiler/OperationValidator.cc
@@ -0,0 +1,985 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "OperationValidator.h"
+
+#include <typeinfo>
+
+#include "ir/Graph.h"
+#include "ir/operation/LowerInfo.h"
+
+#include "util/logging.h"
+#include "util/Utils.h"
+
+namespace neurun
+{
+namespace compiler
+{
+
+OperationValidator::OperationValidator(const ir::Graph &graph)
+    : _graph{graph}, _ctx{graph.operands()}, _current_subg_layout{ir::Layout::UNKNOWN}
+{
+}
+
+void OperationValidator::operator()()
+{
+  // TODO Get frontend layout from graph
+  _current_subg_layout = ir::Layout::NHWC;
+
+  _graph.operations().iterate(
+      [&](const ir::OperationIndex &, const ir::Operation &node) { node.accept(*this); });
+}
+
+void OperationValidator::visit(const ir::operation::BatchToSpaceND &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::BatchToSpaceND::Input::INPUT)};
+  const auto block_size_index{
+      node.getInputs().at(ir::operation::BatchToSpaceND::Input::BLOCK_SIZE)};
+
+  const auto frontend_layout = _current_subg_layout;
+  const auto input_shape = _ctx.at(ifm_index).shape().asFeature(frontend_layout);
+  const auto output_shape = _ctx.at(ofm_index).shape().asFeature(frontend_layout);
+
+  UNUSED_RELEASE(input_shape);
+  UNUSED_RELEASE(output_shape);
+
+  // All assertions as per NNAPI specification.
+  assert(_ctx.at(ifm_index).shape().rank() == 4);
+  assert(_ctx.at(ofm_index).shape().rank() == 4);
+  assert(_ctx.at(block_size_index).shape().rank() == 1);
+
+  assert(_ctx.at(block_size_index).shape().dim(0) == 2);
+
+  assert(_ctx.at(block_size_index).isConstant());
+
+  assert(input_shape.C == output_shape.C);
+}
+
+void OperationValidator::visit(const ir::operation::Cast &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(0)};
+
+  UNUSED_RELEASE(output_index);
+  UNUSED_RELEASE(input_index);
+
+  assert(_ctx.at(output_index).shape() == _ctx.at(input_index).shape());
+}
+
+void OperationValidator::visit(const ir::operation::Comparison &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto lhs_index{node.getInputs().at(ir::operation::Comparison::Input::INPUT0)};
+  const auto rhs_index{node.getInputs().at(ir::operation::Comparison::Input::INPUT1)};
+
+  UNUSED_RELEASE(output_index);
+  UNUSED_RELEASE(lhs_index);
+  UNUSED_RELEASE(rhs_index);
+
+  assert(_ctx.at(lhs_index).typeInfo().type() == _ctx.at(rhs_index).typeInfo().type());
+  assert(_ctx.at(output_index).typeInfo().type() == ir::DataType::BOOL8);
+}
+
+void OperationValidator::visit(const ir::operation::Softmax &node)
+{
+  VERBOSE(Softmax) << "Configure SOFTMAX operation" << std::endl;
+
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(0)};
+
+  UNUSED_RELEASE(output_index);
+  UNUSED_RELEASE(input_index);
+
+  assert(_ctx.at(output_index).shape().rank() == _ctx.at(input_index).shape().rank());
+}
+
+void OperationValidator::visit(const ir::operation::InstanceNorm &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::InstanceNorm::Input::INPUT)};
+  const auto gamma_index{node.getInputs().at(ir::operation::InstanceNorm::Input::GAMMA)};
+  const auto beta_index{node.getInputs().at(ir::operation::InstanceNorm::Input::BETA)};
+
+  UNUSED_RELEASE(ofm_index);
+  UNUSED_RELEASE(ifm_index);
+  UNUSED_RELEASE(gamma_index);
+  UNUSED_RELEASE(beta_index);
+
+  assert(_ctx.at(ifm_index).shape().rank() == 4);
+  assert(_ctx.at(ifm_index).shape() == _ctx.at(ofm_index).shape());
+  assert(_ctx.at(gamma_index).shape().rank() == 1);
+  assert(_ctx.at(beta_index).shape().rank() == 1);
+}
+
+void OperationValidator::visit(const ir::operation::Permute &node)
+{
+  VERBOSE(Permute) << "Configure Permute operation" << std::endl;
+
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(0)};
+
+  UNUSED_RELEASE(output_index);
+  UNUSED_RELEASE(input_index);
+
+  assert(_ctx.at(output_index).shape().rank() == _ctx.at(input_index).shape().rank());
+}
+
+void OperationValidator::visit(const ir::operation::ReduceSum &node)
+{
+  VERBOSE(Permute) << "Configure ReduceSum operation" << std::endl;
+
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::ReduceSum::Input::INPUT)};
+  const auto &axes = node.param().axes;
+
+  UNUSED_RELEASE(output_index);
+  UNUSED_RELEASE(input_index);
+  UNUSED_RELEASE(axes);
+
+  const auto input_shape = _ctx.at(input_index).shape();
+  const auto output_shape = _ctx.at(output_index).shape();
+
+  UNUSED_RELEASE(output_shape);
+  UNUSED_RELEASE(input_shape);
+
+  assert(input_shape.rank() <= 4);
+  assert(output_shape.rank() <= input_shape.rank());
+
+  // NOTE For the 4-dimensions, if the rank of input and output are different, this runtime only
+  // supports cases reducing height and width or reducing depth.
+  // TODO We have to support all cases of dimensions up to 4.
+  // For correct permuting, we have to set output's shape to be equal in dimension position of the
+  // input. But the positions of the same dimensions in the input and output may be set differently.
+  // For example {2,3,4,5}(input's shape) can be reduced to {3,5}(output's shape). The original
+  // output shape should be {1,3,1,5}, but real output shape may be {3,5}. If you simply try to
+  // extend it in 4 dimensions, it should be {1,1,3,5}.
+  // Even if output shape is changed to {1,3,1,5}, there is another problem. It is that shape of
+  // output tensor used at next operation is changed to {1,3,1,5} after this operation even if the
+  // next operation is not desired.
+  if (input_shape.rank() == 4 && input_shape.rank() != output_shape.rank())
+  {
+    if (output_shape.rank() == 2)
+    {
+      // Reducing HW
+      assert(input_shape.dim(0) == output_shape.dim(0) &&
+             input_shape.dim(3) == output_shape.dim(1));
+    }
+    else if (output_shape.rank() == 3)
+    {
+      // Reducing C or
+      // (Reducing H and C(input and output) == 1) or (Reducing W and C(input and output) == 1)
+      assert((input_shape.dim(0) == output_shape.dim(0) &&
+              input_shape.dim(1) == output_shape.dim(1) &&
+              input_shape.dim(2) == output_shape.dim(2)) ||
+             (input_shape.dim(0) == output_shape.dim(0) &&
+              (input_shape.dim(1) == output_shape.dim(1) ||
+               input_shape.dim(2) == output_shape.dim(1)) &&
+              input_shape.dim(3) == 1 && output_shape.dim(2) == 1));
+    }
+  }
+}
+
+void OperationValidator::visit(const ir::operation::Transpose &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::Transpose::Input::INPUT)};
+  const auto &perm{node.param().perm};
+
+  const auto &output_shape = _ctx.at(output_index).shape();
+  const auto &input_shape = _ctx.at(input_index).shape();
+
+  UNUSED_RELEASE(output_shape);
+  UNUSED_RELEASE(input_shape);
+  UNUSED_RELEASE(perm);
+
+  assert(input_shape.rank() == static_cast<int>(perm.size()));
+  assert(input_shape.rank() == output_shape.rank());
+}
+
+void OperationValidator::visit(const ir::operation::ReduceMax &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::ReduceMax::Input::INPUT)};
+  const auto &axes = node.param().axes;
+
+  auto output_shape = _ctx.at(output_index).shape();
+  auto input_shape = _ctx.at(input_index).shape();
+
+  UNUSED_RELEASE(output_shape);
+  UNUSED_RELEASE(input_shape);
+  UNUSED_RELEASE(axes);
+
+  assert(input_shape.rank() <= 4);
+  assert(output_shape.rank() <= input_shape.rank());
+
+  // NOTE For the 4-dimensions, if the rank of input and output are different, this runtime only
+  // supports cases reducing height and width or reducing depth.
+  // TODO We have to support all cases of dimensions up to 4.
+  // For correct permuting, we have to set output's shape to be equal in dimension position of the
+  // input. But the positions of the same dimensions in the input and output may be set differently.
+  // For example {2,3,4,5}(input's shape) can be reduced to {3,5}(output's shape). The original
+  // output shape should be {1,3,1,5}, but real output shape may be {3,5}. If you simply try to
+  // extend it in 4 dimensions, it should be {1,1,3,5}.
+  // Even if output shape is changed to {1,3,1,5}, there is another problem. It is that shape of
+  // output tensor used at next operation is changed to {1,3,1,5} after this operation even if the
+  // next operation is not desired.
+  if (input_shape.rank() == 4 && input_shape.rank() != output_shape.rank())
+  {
+    if (output_shape.rank() == 2)
+    {
+      // Reducing HW
+      assert(input_shape.dim(0) == output_shape.dim(0) &&
+             input_shape.dim(3) == output_shape.dim(1));
+    }
+    else if (output_shape.rank() == 3)
+    {
+      // Reducing C or
+      // (Reducing H and C(ifm and ofm) == 1) or (Reducing W and C(ifm and ofm) == 1)
+      assert((input_shape.dim(0) == output_shape.dim(0) &&
+              input_shape.dim(1) == output_shape.dim(1) &&
+              input_shape.dim(2) == output_shape.dim(2)) ||
+             (input_shape.dim(0) == output_shape.dim(0) &&
+              (input_shape.dim(1) == output_shape.dim(1) ||
+               input_shape.dim(2) == output_shape.dim(1)) &&
+              input_shape.dim(3) == 1 && output_shape.dim(2) == 1));
+    }
+  }
+}
+
+void OperationValidator::visit(const ir::operation::RNN &node)
+{
+  // NOTE This validation is for static rnn(non-dynamic shape), but not for dynamic rnn
+  // TODO Support dynamic rnn
+  const auto output_index{node.getOutputs().at(ir::operation::RNN::Output::OUTPUT)};
+  const auto hidden_state_out_index{
+      node.getOutputs().at(ir::operation::RNN::Output::HIDDEN_STATE_OUT)};
+
+  const auto input_index{node.getInputs().at(ir::operation::RNN::Input::INPUT)};
+  const auto weights_index{node.getInputs().at(ir::operation::RNN::Input::WEIGHTS)};
+  const auto recurrent_weights_index{
+      node.getInputs().at(ir::operation::RNN::Input::RECURRENT_WEIGHTS)};
+  const auto bias_index{node.getInputs().at(ir::operation::RNN::Input::BIAS)};
+  const auto hidden_state_in_index{node.getInputs().at(ir::operation::RNN::Input::HIDDEN_STATE_IN)};
+
+  const auto batch_size = _ctx.at(output_index).shape().dim(0);
+  const auto num_units = _ctx.at(output_index).shape().dim(1);
+
+  UNUSED_RELEASE(output_index);
+  UNUSED_RELEASE(hidden_state_out_index);
+  UNUSED_RELEASE(input_index);
+  UNUSED_RELEASE(weights_index);
+  UNUSED_RELEASE(recurrent_weights_index);
+  UNUSED_RELEASE(bias_index);
+  UNUSED_RELEASE(hidden_state_in_index);
+  UNUSED_RELEASE(batch_size);
+  UNUSED_RELEASE(num_units);
+
+  assert(_ctx.at(output_index).shape().rank() == 2 &&
+         _ctx.at(hidden_state_out_index).shape().rank() == 2 &&
+         _ctx.at(input_index).shape().rank() == 2 && _ctx.at(weights_index).shape().rank() == 2 &&
+         _ctx.at(recurrent_weights_index).shape().rank() == 2 &&
+         _ctx.at(hidden_state_in_index).shape().rank() == 2);
+  assert(_ctx.at(bias_index).shape().rank() == 1);
+
+  assert(batch_size == _ctx.at(input_index).shape().dim(0) &&
+         batch_size == _ctx.at(hidden_state_in_index).shape().dim(0) &&
+         batch_size == _ctx.at(hidden_state_out_index).shape().dim(0));
+  assert(_ctx.at(input_index).shape().dim(1) == _ctx.at(weights_index).shape().dim(1));
+
+  assert(num_units == _ctx.at(weights_index).shape().dim(0) &&
+         num_units == _ctx.at(recurrent_weights_index).shape().dim(0) &&
+         num_units == _ctx.at(bias_index).shape().dim(0));
+  assert(num_units == _ctx.at(output_index).shape().dim(1) &&
+         num_units == _ctx.at(recurrent_weights_index).shape().dim(1) &&
+         num_units == _ctx.at(hidden_state_in_index).shape().dim(1) &&
+         num_units == _ctx.at(hidden_state_out_index).shape().dim(1));
+}
+
+void OperationValidator::visit(const ir::operation::SpaceToBatchND &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::SpaceToBatchND::Input::INPUT)};
+  const auto block_size_index{
+      node.getInputs().at(ir::operation::SpaceToBatchND::Input::BLOCK_SIZE)};
+  const auto paddings_index{node.getInputs().at(ir::operation::SpaceToBatchND::Input::PADDINGS)};
+
+  const auto frontend_layout = _current_subg_layout;
+  const auto input_shape = _ctx.at(ifm_index).shape().asFeature(frontend_layout);
+  const auto output_shape = _ctx.at(ofm_index).shape().asFeature(frontend_layout);
+
+  UNUSED_RELEASE(input_shape);
+  UNUSED_RELEASE(output_shape);
+
+  // All assertions as per NNAPI specification.
+  assert(_ctx.at(ifm_index).shape().rank() == 4);
+  assert(_ctx.at(ofm_index).shape().rank() == 4);
+  assert(_ctx.at(block_size_index).shape().rank() == 1);
+  assert(_ctx.at(paddings_index).shape().rank() == 2);
+
+  assert(_ctx.at(block_size_index).shape().dim(0) == 2);
+  assert(_ctx.at(paddings_index).shape().dim(0) == 2);
+  assert(_ctx.at(paddings_index).shape().dim(1) == 2);
+
+  assert(_ctx.at(block_size_index).isConstant());
+  assert(_ctx.at(paddings_index).isConstant());
+
+  assert(input_shape.C == output_shape.C);
+}
+
+void OperationValidator::visit(const ir::operation::SpaceToDepth &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::SpaceToDepth::Input::INPUT)};
+
+  const auto frontend_layout = _current_subg_layout;
+  const auto input_shape = _ctx.at(ifm_index).shape().asFeature(frontend_layout);
+  const auto output_shape = _ctx.at(ofm_index).shape().asFeature(frontend_layout);
+  const auto block_size = node.param().block_size;
+
+  UNUSED_RELEASE(input_shape);
+  UNUSED_RELEASE(output_shape);
+  UNUSED_RELEASE(block_size);
+
+  // All assertions as per NNAPI specification.
+  assert(_ctx.at(ifm_index).shape().rank() == 4);
+  assert(_ctx.at(ofm_index).shape().rank() == 4);
+  assert((block_size >= 1) && (input_shape.H % block_size == 0) &&
+         (input_shape.W % block_size == 0));
+  assert(input_shape.N == output_shape.N);
+  assert(input_shape.C * block_size * block_size == output_shape.C);
+}
+
+void OperationValidator::visit(const ir::operation::EmbeddingLookup &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto lookups_index{node.getInputs().at(ir::operation::EmbeddingLookup::Input::LOOKUPS)};
+  const auto values_index{node.getInputs().at(ir::operation::EmbeddingLookup::Input::VALUES)};
+
+  const auto &output_obj = _ctx.at(output_index);
+  const auto &lookups_obj = _ctx.at(lookups_index);
+  const auto &values_obj = _ctx.at(values_index);
+
+  UNUSED_RELEASE(output_obj);
+  UNUSED_RELEASE(lookups_obj);
+  UNUSED_RELEASE(values_obj);
+
+  // Verify operand here, not at SimpleEmbeddingLookup::configure() to avoid acl's modifying
+  // TensorShape sometimes(Issue: https://github.sec.samsung.net/STAR/nnfw/issues/729)
+  {
+    assert(lookups_obj.typeInfo().type() == ir::DataType::INT32);
+
+    const auto &output_shape = output_obj.shape();
+    const auto &lookups_shape = lookups_obj.shape();
+    const auto &values_shape = values_obj.shape();
+
+    UNUSED_RELEASE(output_shape);
+    UNUSED_RELEASE(lookups_shape);
+    UNUSED_RELEASE(values_shape);
+
+    assert(lookups_shape.rank() == 1);
+    assert(values_shape.rank() >= 2);
+
+    // output should be a n-D tensor with the same rank and shape as the values tensor, except for
+    // the first dimension which has the same size as lookups' only dimension.
+    assert(output_shape.rank() == values_shape.rank());
+    assert(output_shape.dim(0) == lookups_shape.dim(0));
+    for (int n = 1; n < output_shape.rank(); ++n)
+    {
+      assert(output_shape.dim(n) == values_shape.dim(n));
+    }
+  }
+}
+
+void OperationValidator::visit(const ir::operation::Exp &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::Exp::Input::INPUT)};
+
+  UNUSED_RELEASE(output_index);
+  UNUSED_RELEASE(input_index);
+
+  assert(_ctx.at(output_index).shape() == _ctx.at(input_index).shape());
+  assert(_ctx.at(output_index).typeInfo().type() == _ctx.at(input_index).typeInfo().type());
+}
+
+void OperationValidator::visit(const ir::operation::Floor &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::Floor::Input::INPUT)};
+
+  UNUSED_RELEASE(output_index);
+  UNUSED_RELEASE(input_index);
+
+  assert(_ctx.at(output_index).shape() == _ctx.at(input_index).shape());
+  assert(_ctx.at(output_index).typeInfo().type() == _ctx.at(input_index).typeInfo().type());
+}
+
+void OperationValidator::visit(const ir::operation::HashtableLookup &node)
+{
+  const auto output_index{node.getOutputs().at(ir::operation::HashtableLookup::Output::OUTPUT)};
+  const auto hits_index{node.getOutputs().at(ir::operation::HashtableLookup::Output::HITS)};
+
+  const auto lookups_index{node.getInputs().at(ir::operation::HashtableLookup::Input::LOOKUPS)};
+  const auto keys_index{node.getInputs().at(ir::operation::HashtableLookup::Input::KEYS)};
+  const auto values_index{node.getInputs().at(ir::operation::HashtableLookup::Input::VALUES)};
+
+  const auto &output_obj = _ctx.at(output_index);
+  const auto &hits_obj = _ctx.at(hits_index);
+
+  const auto &lookups_obj = _ctx.at(lookups_index);
+  const auto &keys_obj = _ctx.at(keys_index);
+  const auto &values_obj = _ctx.at(values_index);
+
+  assert(lookups_obj.typeInfo().type() == ir::DataType::INT32);
+  assert(keys_obj.typeInfo().type() == ir::DataType::INT32);
+  assert(hits_obj.typeInfo().type() == ir::DataType::QUANT8_ASYMM);
+
+  const auto &output_shape = output_obj.shape();
+  const auto &hits_shape = hits_obj.shape();
+
+  const auto &lookups_shape = lookups_obj.shape();
+  const auto &keys_shape = keys_obj.shape();
+  const auto &values_shape = values_obj.shape();
+
+  UNUSED_RELEASE(output_shape);
+  UNUSED_RELEASE(hits_shape);
+  UNUSED_RELEASE(lookups_shape);
+  UNUSED_RELEASE(keys_shape);
+  UNUSED_RELEASE(values_shape);
+
+  assert(values_shape.rank() == output_shape.rank());
+  assert(lookups_shape.rank() == 1);
+  assert(keys_shape.rank() == 1);
+  assert(values_shape.dim(0) == keys_shape.dim(0));
+  assert(lookups_shape.dim(0) == output_shape.dim(0));
+}
+
+void OperationValidator::visit(const ir::operation::TransposeConv &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::TransposeConv::Input::INPUT)};
+  const auto ker_index{node.getInputs().at(ir::operation::TransposeConv::Input::KERNEL)};
+
+  // Only 4D tensors are supported
+  assert(_ctx.at(ofm_index).shape().rank() == 4);
+  assert(_ctx.at(ofm_index).shape().rank() == _ctx.at(ifm_index).shape().rank());
+  assert(_ctx.at(ofm_index).shape().rank() == _ctx.at(ker_index).shape().rank());
+
+  const auto frontend_layout = _current_subg_layout;
+  const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature(frontend_layout);
+  const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature(frontend_layout);
+  // The kernel has only IHWO layout on frontend
+  // So ker_shape is treated here below
+  // I -> N
+  // H -> H
+  // W -> W
+  // O -> C
+  const auto ker_shape = _ctx.at(ker_index).shape().asFeature(ir::Layout::NHWC);
+
+  UNUSED_RELEASE(ofm_shape);
+  UNUSED_RELEASE(ifm_shape);
+  UNUSED_RELEASE(ker_shape);
+
+  assert((node.param().padding.type == ir::PaddingType::SAME) ||
+         (node.param().padding.type == ir::PaddingType::VALID));
+  assert(ifm_shape.N == ofm_shape.N);
+  assert(ifm_shape.C == ker_shape.C);
+  assert(ker_shape.N == ofm_shape.C);
+}
+
+void OperationValidator::visit(const ir::operation::Gather &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+
+  const auto ifm_index{node.getInputs().at(ir::operation::Gather::Input::INPUT)};
+  const auto indices_index{node.getInputs().at(ir::operation::Gather::Input::INDICES)};
+
+  const auto axis = node.param().axis;
+
+  const auto ifm_shape = _ctx.at(ifm_index).shape();
+  const auto indices_shape = _ctx.at(indices_index).shape();
+  const auto ofm_shape = _ctx.at(ofm_index).shape();
+
+  UNUSED_RELEASE(ifm_shape);
+  UNUSED_RELEASE(indices_shape);
+  UNUSED_RELEASE(ofm_shape);
+  UNUSED_RELEASE(axis);
+
+  assert(ifm_shape.rank() <= 4);
+  assert(indices_shape.rank() <= 3);
+  assert(ofm_shape.rank() <= 4);
+}
+
+void OperationValidator::visit(const ir::operation::Dequantize &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::Dequantize::Input::INPUT)};
+
+  UNUSED_RELEASE(output_index);
+  UNUSED_RELEASE(input_index);
+
+  assert(_ctx.at(input_index).shape().rank() <= 4);
+  assert(_ctx.at(input_index).shape() == _ctx.at(output_index).shape());
+  assert(_ctx.at(input_index).typeInfo().type() == ir::DataType::QUANT8_ASYMM);
+  assert(_ctx.at(output_index).typeInfo().type() == ir::DataType::FLOAT32);
+}
+
+void OperationValidator::visit(const ir::operation::Mean &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::Mean::Input::INPUT)};
+
+  const auto ifm_shape = _ctx.at(ifm_index).shape();
+  const auto ofm_shape = _ctx.at(ofm_index).shape();
+
+  // NOTE For the 4-dimensions, if the rank of input and output are different, this runtime only
+  // supports cases reducing height and width or reducing depth.
+  // TODO We have to support all cases of dimensions up to 4.
+  // For correct permuting, we have to set output's shape to be equal in dimension position of the
+  // input. But the positions of the same dimensions in the input and output may be set differently.
+  // For example {2,3,4,5}(input's shape) can be reduced to {3,5}(output's shape). The original
+  // output shape should be {1,3,1,5}, but real output shape may be {3,5}. If you simply try to
+  // extend it in 4 dimensions, it should be {1,1,3,5}.
+  // Even if output shape is changed to {1,3,1,5}, there is another problem. It is that shape of
+  // output tensor used at next operation is changed to {1,3,1,5} after this operation even if the
+  // next operation is not desired.
+  if (ifm_shape.rank() == 4 && ifm_shape.rank() != ofm_shape.rank())
+  {
+    if (ofm_shape.rank() == 2)
+    {
+      // Reducing HW
+      assert(ifm_shape.dim(0) == ofm_shape.dim(0) && ifm_shape.dim(3) == ofm_shape.dim(1));
+    }
+    else if (ofm_shape.rank() == 3)
+    {
+      // Reducing C or
+      // (Reducing H and C(ifm and ofm) == 1) or (Reducing W and C(ifm and ofm) == 1)
+      assert((ifm_shape.dim(0) == ofm_shape.dim(0) && ifm_shape.dim(1) == ofm_shape.dim(1) &&
+              ifm_shape.dim(2) == ofm_shape.dim(2)) ||
+             (ifm_shape.dim(0) == ofm_shape.dim(0) &&
+              (ifm_shape.dim(1) == ofm_shape.dim(1) || ifm_shape.dim(2) == ofm_shape.dim(1)) &&
+              ifm_shape.dim(3) == 1 && ofm_shape.dim(2) == 1));
+    }
+  }
+}
+
+void OperationValidator::visit(const ir::operation::DepthToSpace &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto input_index{node.getInputs().at(ir::operation::DepthToSpace::Input::INPUT)};
+
+  const auto frontend_layout = _current_subg_layout;
+  const auto output_shape = _ctx.at(output_index).shape().asFeature(frontend_layout);
+  const auto input_shape = _ctx.at(input_index).shape().asFeature(frontend_layout);
+
+  UNUSED_RELEASE(output_shape);
+  UNUSED_RELEASE(input_shape);
+
+  assert(_ctx.at(input_index).shape().rank() == 4);
+  assert(_ctx.at(output_index).shape().rank() == 4);
+
+  int32_t block_size = node.param().block_size;
+
+  UNUSED_RELEASE(block_size);
+
+  assert(block_size > 0);
+
+  { // assertions block
+    assert(output_shape.N == input_shape.N);
+    assert(output_shape.H == input_shape.H * block_size);
+    assert(output_shape.W == input_shape.W * block_size);
+    assert(input_shape.C % (block_size * block_size) == 0);
+    assert(output_shape.C == input_shape.C / (block_size * block_size));
+  }
+}
+
+void OperationValidator::visit(const ir::operation::Pack &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto num{node.param().num};
+  const auto axis{node.param().axis};
+
+  const auto &output_shape = _ctx.at(output_index).shape();
+  const auto output_rank = static_cast<int32_t>(output_shape.rank());
+
+  const auto input1_index{node.getInputs().at(0)};
+  const auto input_shape = _ctx.at(input1_index).shape();
+
+  UNUSED_RELEASE(num);
+  UNUSED_RELEASE(axis);
+  UNUSED_RELEASE(output_rank);
+
+  assert(num == static_cast<int32_t>(node.getInputs().size()));
+  assert(axis >= -output_rank && axis < output_rank);
+  for (const auto &index : node.getInputs())
+  {
+    UNUSED_RELEASE(index);
+    assert(input_shape == _ctx.at(index).shape());
+  }
+}
+
+void OperationValidator::visit(const ir::operation::ReduceMin &node)
+{
+  const auto ofm_index{node.getOutputs().at(0)};
+  const auto ifm_index{node.getInputs().at(ir::operation::ReduceMin::Input::INPUT)};
+  const auto &axes = node.param().axes;
+
+  auto ifm_shape = _ctx.at(ifm_index).shape();
+  auto ofm_shape = _ctx.at(ofm_index).shape();
+
+  UNUSED_RELEASE(ifm_shape);
+  UNUSED_RELEASE(ofm_shape);
+  UNUSED_RELEASE(axes);
+
+  assert(ifm_shape.rank() <= 4);
+  assert(ofm_shape.rank() <= ifm_shape.rank());
+
+  // NOTE For the 4-dimensions, if the rank of input and output are different, this runtime only
+  // supports cases reducing height and width or reducing depth.
+  // TODO We have to support all cases of dimensions up to 4.
+  // For correct permuting, we have to set output's shape to be equal in dimension position of the
+  // input. But the positions of the same dimensions in the input and output may be set differently.
+  // For example {2,3,4,5}(input's shape) can be reduced to {3,5}(output's shape). The original
+  // output shape should be {1,3,1,5}, but real output shape may be {3,5}. If you simply try to
+  // extend it in 4 dimensions, it should be {1,1,3,5}.
+  // Even if output shape is changed to {1,3,1,5}, there is another problem. It is that shape of
+  // output tensor used at next operation is changed to {1,3,1,5} after this operation even if the
+  // next operation is not desired.
+  if (ifm_shape.rank() == 4 && ifm_shape.rank() != ofm_shape.rank())
+  {
+    if (ofm_shape.rank() == 2)
+    {
+      // Reducing HW
+      assert(ifm_shape.dim(0) == ofm_shape.dim(0) && ifm_shape.dim(3) == ofm_shape.dim(1));
+    }
+    else if (ofm_shape.rank() == 3)
+    {
+      // Reducing C or
+      // (Reducing H and C(ifm and ofm) == 1) or (Reducing W and C(ifm and ofm) == 1)
+      assert((ifm_shape.dim(0) == ofm_shape.dim(0) && ifm_shape.dim(1) == ofm_shape.dim(1) &&
+              ifm_shape.dim(2) == ofm_shape.dim(2)) ||
+             (ifm_shape.dim(0) == ofm_shape.dim(0) &&
+              (ifm_shape.dim(1) == ofm_shape.dim(1) || ifm_shape.dim(2) == ofm_shape.dim(1)) &&
+              ifm_shape.dim(3) == 1 && ofm_shape.dim(2) == 1));
+    }
+  }
+}
+
+void OperationValidator::visit(const ir::operation::LSTM &node)
+{
+  // NOTE This validation is for static rnn(non-dynamic shape), but not for dynamic rnn
+  // TODO Support dynamic rnn
+  const auto scratch_buffer_index{
+      node.getOutputs().at(ir::operation::LSTM::Output::SCRATCH_BUFFER)};
+  const auto output_state_out_index{
+      node.getOutputs().at(ir::operation::LSTM::Output::OUTPUT_STATE_OUT)};
+  const auto cell_state_out_index{
+      node.getOutputs().at(ir::operation::LSTM::Output::CELL_STATE_OUT)};
+  const auto output_index{node.getOutputs().at(ir::operation::LSTM::Output::OUTPUT)};
+
+  const auto input_index{node.getInputs().at(ir::operation::LSTM::Input::INPUT)};
+  const auto input_to_input_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::INPUT_TO_INPUT_WEIGHTS)};
+  const auto input_to_forget_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::INPUT_TO_FORGET_WEIGHTS)};
+  const auto input_to_cell_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::INPUT_TO_CELL_WEIGHTS)};
+  const auto input_to_output_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::INPUT_TO_OUTPUT_WEIGHTS)};
+  const auto recurrent_to_input_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::RECURRENT_TO_INPUT_WEIGHTS)};
+  const auto recurrent_to_forget_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::RECURRENT_TO_FORGET_WEIGHTS)};
+  const auto recurrent_to_cell_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::RECURRENT_TO_CELL_WEIGHTS)};
+  const auto recurrent_to_output_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::RECURRENT_TO_OUTPUT_WEIGHTS)};
+  const auto cell_to_input_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::CELL_TO_INPUT_WEIGHTS)};
+  const auto cell_to_forget_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::CELL_TO_FORGET_WEIGHTS)};
+  const auto cell_to_output_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::CELL_TO_OUTPUT_WEIGHTS)};
+  const auto input_gate_bias_index{
+      node.getInputs().at(ir::operation::LSTM::Input::INPUT_GATE_BIAS)};
+  const auto forget_gate_bias_index{
+      node.getInputs().at(ir::operation::LSTM::Input::FORGET_GATE_BIAS)};
+  const auto cell_bias_index{node.getInputs().at(ir::operation::LSTM::Input::CELL_BIAS)};
+  const auto output_gate_bias_index{
+      node.getInputs().at(ir::operation::LSTM::Input::OUTPUT_GATE_BIAS)};
+  const auto projection_weights_index{
+      node.getInputs().at(ir::operation::LSTM::Input::PROJECTION_WEIGHTS)};
+  const auto projection_bias_index{
+      node.getInputs().at(ir::operation::LSTM::Input::PROJECTION_BIAS)};
+  const auto output_state_in_index{
+      node.getInputs().at(ir::operation::LSTM::Input::OUTPUT_STATE_IN)};
+  const auto cell_state_in_index{node.getInputs().at(ir::operation::LSTM::Input::CELL_STATE_IN)};
+
+  UNUSED_RELEASE(scratch_buffer_index);
+  UNUSED_RELEASE(output_state_out_index);
+  UNUSED_RELEASE(cell_state_out_index);
+  UNUSED_RELEASE(output_index);
+
+  UNUSED_RELEASE(input_index);
+  UNUSED_RELEASE(input_to_input_weights_index);
+  UNUSED_RELEASE(input_to_forget_weights_index);
+  UNUSED_RELEASE(input_to_cell_weights_index);
+  UNUSED_RELEASE(input_to_output_weights_index);
+  UNUSED_RELEASE(recurrent_to_input_weights_index);
+  UNUSED_RELEASE(recurrent_to_forget_weights_index);
+  UNUSED_RELEASE(recurrent_to_cell_weights_index);
+  UNUSED_RELEASE(recurrent_to_output_weights_index);
+  UNUSED_RELEASE(cell_to_input_weights_index);
+  UNUSED_RELEASE(cell_to_forget_weights_index);
+  UNUSED_RELEASE(cell_to_output_weights_index);
+  UNUSED_RELEASE(input_gate_bias_index);
+  UNUSED_RELEASE(forget_gate_bias_index);
+  UNUSED_RELEASE(cell_bias_index);
+  UNUSED_RELEASE(output_gate_bias_index);
+  UNUSED_RELEASE(projection_weights_index);
+  UNUSED_RELEASE(projection_bias_index);
+  UNUSED_RELEASE(output_state_in_index);
+  UNUSED_RELEASE(cell_state_in_index);
+
+  assert(_ctx.at(scratch_buffer_index).shape().rank() == 2 &&
+         _ctx.at(output_state_out_index).shape().rank() == 2 &&
+         _ctx.at(cell_state_out_index).shape().rank() == 2 &&
+         _ctx.at(output_index).shape().rank() == 2 && _ctx.at(input_index).shape().rank() == 2 &&
+         _ctx.at(input_to_input_weights_index).shape().rank() == 2 &&
+         _ctx.at(input_to_forget_weights_index).shape().rank() == 2 &&
+         _ctx.at(input_to_cell_weights_index).shape().rank() == 2 &&
+         _ctx.at(input_to_output_weights_index).shape().rank() == 2 &&
+         _ctx.at(recurrent_to_input_weights_index).shape().rank() == 2 &&
+         _ctx.at(recurrent_to_forget_weights_index).shape().rank() == 2 &&
+         _ctx.at(recurrent_to_cell_weights_index).shape().rank() == 2 &&
+         _ctx.at(recurrent_to_output_weights_index).shape().rank() == 2 &&
+         _ctx.at(projection_weights_index).shape().rank() == 2 &&
+         _ctx.at(output_state_in_index).shape().rank() == 2 &&
+         _ctx.at(cell_state_in_index).shape().rank() == 2);
+
+  assert(_ctx.at(cell_to_input_weights_index).shape().rank() == 1 &&
+         _ctx.at(cell_to_forget_weights_index).shape().rank() == 1 &&
+         _ctx.at(cell_to_output_weights_index).shape().rank() == 1 &&
+         _ctx.at(input_gate_bias_index).shape().rank() == 1 &&
+         _ctx.at(forget_gate_bias_index).shape().rank() == 1 &&
+         _ctx.at(cell_bias_index).shape().rank() == 1 &&
+         _ctx.at(output_gate_bias_index).shape().rank() == 1 &&
+         _ctx.at(projection_bias_index).shape().rank() == 1);
+
+  // CIFG assertion
+  assert((_ctx.at(input_to_input_weights_index).shape().dim(0) == 0 &&
+          _ctx.at(input_to_input_weights_index).shape().dim(1) == 0 &&
+          _ctx.at(recurrent_to_input_weights_index).shape().dim(0) == 0 &&
+          _ctx.at(recurrent_to_input_weights_index).shape().dim(1) == 0 &&
+          _ctx.at(input_gate_bias_index).shape().dim(0) == 0 &&
+          _ctx.at(cell_to_input_weights_index).shape().dim(0) == 0) ||
+         (_ctx.at(input_to_input_weights_index).shape().dim(0) != 0 &&
+          _ctx.at(input_to_input_weights_index).shape().dim(1) != 0 &&
+          _ctx.at(recurrent_to_input_weights_index).shape().dim(0) != 0 &&
+          _ctx.at(recurrent_to_input_weights_index).shape().dim(1) != 0 &&
+          _ctx.at(input_gate_bias_index).shape().dim(0) != 0));
+
+  // Peephole assertion
+  assert((_ctx.at(cell_to_forget_weights_index).shape().dim(0) == 0 &&
+          _ctx.at(cell_to_output_weights_index).shape().dim(0) == 0) ||
+         (_ctx.at(cell_to_forget_weights_index).shape().dim(0) != 0 &&
+          _ctx.at(cell_to_output_weights_index).shape().dim(0) != 0));
+
+  bool has_input_to_input_weights = _ctx.at(input_to_input_weights_index).shape().dim(0) != 0 &&
+                                    _ctx.at(input_to_input_weights_index).shape().dim(1) != 0;
+  bool has_recurrent_to_input_weights =
+      _ctx.at(recurrent_to_input_weights_index).shape().dim(0) != 0 &&
+      _ctx.at(recurrent_to_input_weights_index).shape().dim(1) != 0;
+  bool has_input_gate_bias = _ctx.at(input_gate_bias_index).shape().dim(0) != 0;
+  bool has_cell_to_input_weights = _ctx.at(cell_to_input_weights_index).shape().dim(0) != 0;
+  bool has_cell_to_forget_weights = _ctx.at(cell_to_forget_weights_index).shape().dim(0) != 0;
+  bool has_cell_to_output_weights = _ctx.at(cell_to_output_weights_index).shape().dim(0) != 0;
+  bool has_projection_weights = _ctx.at(projection_weights_index).shape().dim(0) != 0 &&
+                                _ctx.at(projection_weights_index).shape().dim(1) != 0;
+  bool has_projection_bias = _ctx.at(projection_bias_index).shape().dim(0);
+
+  // NOTE The cell_to_input_weights do not exist in non-peephole although regular LSTM(non-CIFG).
+  // true: no CIFG
+  // false: CIFG
+  bool has_cifg_param = has_input_to_input_weights && has_recurrent_to_input_weights;
+
+  // NOTE The cell_to_input_weights do not exist in regular CIFG although peephole.
+  // true: peephole
+  // false: no peephole
+  bool has_peephole_param = has_cell_to_forget_weights && has_cell_to_output_weights;
+
+  // NOTE The projection weights may have data but the projection bias may not.
+  bool has_projection_param = has_projection_weights;
+
+  UNUSED_RELEASE(has_input_to_input_weights);
+  UNUSED_RELEASE(has_recurrent_to_input_weights);
+  UNUSED_RELEASE(has_input_gate_bias);
+  UNUSED_RELEASE(has_cell_to_input_weights);
+  UNUSED_RELEASE(has_cell_to_forget_weights);
+  UNUSED_RELEASE(has_cell_to_output_weights);
+  UNUSED_RELEASE(has_projection_weights);
+  UNUSED_RELEASE(has_projection_bias);
+  UNUSED_RELEASE(has_cifg_param);
+  UNUSED_RELEASE(has_peephole_param);
+  UNUSED_RELEASE(has_projection_param);
+
+  const auto batch_size = _ctx.at(input_index).shape().dim(0);
+  UNUSED_RELEASE(batch_size);
+  assert(batch_size == _ctx.at(output_state_in_index).shape().dim(0) &&
+         batch_size == _ctx.at(cell_state_in_index).shape().dim(0) &&
+         batch_size == _ctx.at(scratch_buffer_index).shape().dim(0) &&
+         batch_size == _ctx.at(output_state_out_index).shape().dim(0) &&
+         batch_size == _ctx.at(cell_state_out_index).shape().dim(0) &&
+         batch_size == _ctx.at(output_index).shape().dim(0));
+
+  const auto input_size = _ctx.at(input_index).shape().dim(1);
+  UNUSED_RELEASE(input_size);
+  assert(input_size == _ctx.at(input_to_forget_weights_index).shape().dim(1) &&
+         input_size == _ctx.at(input_to_cell_weights_index).shape().dim(1) &&
+         input_size == _ctx.at(input_to_output_weights_index).shape().dim(1));
+
+  const auto num_units = _ctx.at(cell_state_out_index).shape().dim(1);
+  UNUSED_RELEASE(num_units);
+  assert(num_units == _ctx.at(input_to_forget_weights_index).shape().dim(0) &&
+         num_units == _ctx.at(input_to_cell_weights_index).shape().dim(0) &&
+         num_units == _ctx.at(input_to_output_weights_index).shape().dim(0) &&
+         num_units == _ctx.at(recurrent_to_forget_weights_index).shape().dim(0) &&
+         num_units == _ctx.at(recurrent_to_cell_weights_index).shape().dim(0) &&
+         num_units == _ctx.at(recurrent_to_output_weights_index).shape().dim(0) &&
+         num_units == _ctx.at(forget_gate_bias_index).shape().dim(0) &&
+         num_units == _ctx.at(cell_bias_index).shape().dim(0) &&
+         num_units == _ctx.at(output_gate_bias_index).shape().dim(0) &&
+         num_units == _ctx.at(cell_state_in_index).shape().dim(1) &&
+         (((num_units * 3) == _ctx.at(scratch_buffer_index).shape().dim(1)) ||
+          ((num_units * 4) == _ctx.at(scratch_buffer_index).shape().dim(1))));
+
+  const auto output_size = _ctx.at(output_index).shape().dim(1);
+  UNUSED_RELEASE(output_size);
+  assert(output_size == _ctx.at(recurrent_to_forget_weights_index).shape().dim(1) &&
+         output_size == _ctx.at(recurrent_to_cell_weights_index).shape().dim(1) &&
+         output_size == _ctx.at(recurrent_to_output_weights_index).shape().dim(1) &&
+         output_size == _ctx.at(output_state_in_index).shape().dim(1) &&
+         output_size == _ctx.at(output_state_out_index).shape().dim(1));
+
+  if (has_cifg_param)
+  {
+    assert(input_size == _ctx.at(input_to_input_weights_index).shape().dim(1));
+    assert(num_units == _ctx.at(input_to_input_weights_index).shape().dim(0) &&
+           num_units == _ctx.at(recurrent_to_input_weights_index).shape().dim(0) &&
+           (num_units == _ctx.at(cell_to_input_weights_index).shape().dim(0) ||
+            _ctx.at(cell_to_input_weights_index).shape().dim(0) == 0 /* non-peephole */) &&
+           num_units == _ctx.at(input_gate_bias_index).shape().dim(0));
+    assert(output_size == _ctx.at(recurrent_to_input_weights_index).shape().dim(1));
+    assert(has_input_to_input_weights && has_recurrent_to_input_weights && has_input_gate_bias);
+    if (has_cell_to_input_weights)
+    {
+      // NOTE The cell_to_input_weights exist only in case of non-CIFG and peephole.
+      assert(has_peephole_param);
+    }
+    assert(_ctx.at(scratch_buffer_index).shape().dim(1) == num_units * 4);
+  }
+  else
+  {
+    assert(_ctx.at(scratch_buffer_index).shape().dim(1) == num_units * 3);
+  }
+
+  if (has_peephole_param)
+  {
+    assert(num_units == _ctx.at(cell_to_forget_weights_index).shape().dim(0) &&
+           num_units == _ctx.at(cell_to_output_weights_index).shape().dim(0) &&
+           (num_units == _ctx.at(cell_to_input_weights_index).shape().dim(0) ||
+            _ctx.at(cell_to_input_weights_index).shape().dim(0) == 0 /* CIFG */));
+  }
+
+  if (has_projection_param)
+  {
+    assert(num_units == _ctx.at(projection_weights_index).shape().dim(1));
+    assert(output_size == _ctx.at(projection_weights_index).shape().dim(0));
+    if (has_projection_bias)
+    {
+      assert(output_size == _ctx.at(projection_bias_index).shape().dim(0));
+    }
+  }
+}
+
+void OperationValidator::visit(const ir::operation::Unpack &node)
+{
+  const auto input_index{node.getInputs().at(ir::operation::Unpack::Input::INPUT)};
+  const auto num{node.param().num};
+  const auto axis{node.param().axis};
+
+  const auto &input_shape = _ctx.at(input_index).shape();
+  const auto input_rank = static_cast<int32_t>(input_shape.rank());
+
+  UNUSED_RELEASE(num);
+  UNUSED_RELEASE(axis);
+  UNUSED_RELEASE(input_rank);
+
+  assert(num == static_cast<int32_t>(node.getOutputs().size()));
+  assert(axis >= -input_rank && axis < input_rank);
+}
+
+void OperationValidator::visit(const ir::operation::Pad &node)
+{
+  const auto input_index{node.getInputs().at(ir::operation::Pad::Input::INPUT)};
+  const auto pad_index{node.getInputs().at(ir::operation::Pad::Input::PAD)};
+  const auto output_index{node.getInputs().at(0)};
+
+  const auto &pad_shape = _ctx.at(pad_index).shape();
+  const auto input_rank = static_cast<int32_t>(_ctx.at(input_index).shape().rank());
+
+  UNUSED_RELEASE(pad_shape);
+  UNUSED_RELEASE(input_rank);
+  UNUSED_RELEASE(output_index);
+
+  assert(pad_shape.rank() == 2);
+  assert(pad_shape.dim(0) == input_rank);
+  assert(pad_shape.dim(1) == 2);
+  assert(_ctx.at(pad_index).typeInfo().type() == ir::DataType::INT32);
+  assert(_ctx.at(input_index).shape().rank() == _ctx.at(output_index).shape().rank());
+}
+
+void OperationValidator::visit(const ir::operation::Min &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto lhs_index{node.getInputs().at(ir::operation::Min::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::Min::Input::RHS)};
+
+  UNUSED_RELEASE(output_index);
+  UNUSED_RELEASE(lhs_index);
+  UNUSED_RELEASE(rhs_index);
+
+  assert(_ctx.at(lhs_index).typeInfo().type() == _ctx.at(rhs_index).typeInfo().type());
+  assert(_ctx.at(lhs_index).typeInfo().type() == _ctx.at(output_index).typeInfo().type());
+}
+
+void OperationValidator::visit(const ir::operation::Max &node)
+{
+  const auto output_index{node.getOutputs().at(0)};
+  const auto lhs_index{node.getInputs().at(ir::operation::Max::Input::LHS)};
+  const auto rhs_index{node.getInputs().at(ir::operation::Max::Input::RHS)};
+
+  UNUSED_RELEASE(output_index);
+  UNUSED_RELEASE(lhs_index);
+  UNUSED_RELEASE(rhs_index);
+
+  assert(_ctx.at(lhs_index).typeInfo().type() == _ctx.at(rhs_index).typeInfo().type());
+  assert(_ctx.at(lhs_index).typeInfo().type() == _ctx.at(output_index).typeInfo().type());
+}
+
+} // namespace compiler
+} // namespace neurun
diff --git a/runtime/neurun/core/src/compiler/OperationValidator.h b/runtime/neurun/core/src/compiler/OperationValidator.h
new file mode 100644
index 000000000..6ff3c7815
--- /dev/null
+++ b/runtime/neurun/core/src/compiler/OperationValidator.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_COMPILER_OPERATION_VALIDATOR_H__
+#define __NEURUN_COMPILER_OPERATION_VALIDATOR_H__
+
+#include "ir/Layout.h"
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+class Graph;
+class Operands;
+} // namespace ir
+} // namespace neurun
+
+namespace neurun
+{
+namespace compiler
+{
+
+class OperationValidator : public ir::OperationVisitor
+{
+public:
+  OperationValidator(void) = delete;
+  OperationValidator(const ir::Graph &graph);
+
+public:
+  void operator()();
+
+public:
+  void visit(const ir::operation::BatchToSpaceND &node) override;
+  void visit(const ir::operation::Cast &node) override;
+  void visit(const ir::operation::Comparison &node) override;
+  void visit(const ir::operation::Softmax &node) override;
+  void visit(const ir::operation::InstanceNorm &node) override;
+  void visit(const ir::operation::Permute &node) override;
+  void visit(const ir::operation::ReduceSum &node) override;
+  void visit(const ir::operation::Transpose &node) override;
+  void visit(const ir::operation::ReduceMax &node) override;
+  void visit(const ir::operation::RNN &node) override;
+  void visit(const ir::operation::SpaceToBatchND &node) override;
+  void visit(const ir::operation::SpaceToDepth &node) override;
+  void visit(const ir::operation::EmbeddingLookup &node) override;
+  void visit(const ir::operation::Exp &node) override;
+  void visit(const ir::operation::Floor &node) override;
+  void visit(const ir::operation::HashtableLookup &node) override;
+  void visit(const ir::operation::TransposeConv &node) override;
+  void visit(const ir::operation::Gather &node) override;
+  void visit(const ir::operation::Dequantize &node) override;
+  void visit(const ir::operation::Mean &node) override;
+  void visit(const ir::operation::DepthToSpace &node) override;
+  void visit(const ir::operation::Pack &node) override;
+  void visit(const ir::operation::ReduceMin &node) override;
+  void visit(const ir::operation::LSTM &node) override;
+  void visit(const ir::operation::Unpack &node) override;
+  void visit(const ir::operation::Pad &node) override;
+  void visit(const ir::operation::Min &node) override;
+  void visit(const ir::operation::Max &node) override;
+
+private:
+  // TODO Remove _ctx field
+  const ir::Graph &_graph;
+  const ir::Operands &_ctx;
+  ir::Layout _current_subg_layout;
+};
+
+} // namespace compiler
+} // namespace neurun
+
+#endif // __NEURUN_COMPILER_OPERATION_VALIDATOR_H__
diff --git a/runtime/neurun/core/src/compiler/ParamChecker.cc b/runtime/neurun/core/src/compiler/ParamChecker.cc
new file mode 100644
index 000000000..bf172b53f
--- /dev/null
+++ b/runtime/neurun/core/src/compiler/ParamChecker.cc
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ParamChecker.h"
+
+#include "ir/Graph.h"
+
+namespace neurun
+{
+namespace compiler
+{
+
+void ParamChecker::operator()()
+{
+  _model->operations().iterate(
+      [&](const ir::OperationIndex &, const ir::Operation &node) { node.accept(*this); });
+}
+
+} // namespace compiler
+} // namespace neurun
diff --git a/runtime/neurun/core/src/compiler/ParamChecker.h b/runtime/neurun/core/src/compiler/ParamChecker.h
new file mode 100644
index 000000000..7e88ff185
--- /dev/null
+++ b/runtime/neurun/core/src/compiler/ParamChecker.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file ParamChecker.h
+ * @brief This file contains ParamChecker to check\n
+ *        operations' parameters are compilable at machine independent phase\n
+ *        ex) Check param is constant
+ */
+#ifndef __NEURUN_COMPILER_PARAM_CHECKER_H__
+#define __NEURUN_COMPILER_PARAM_CHECKER_H__
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+class Graph;
+} // namespace ir
+} // namespace neurun
+
+namespace neurun
+{
+namespace compiler
+{
+
+class ParamChecker : public ir::OperationVisitor
+{
+public:
+  /**
+   * @brief Construct a new Param Checker object (deleted)
+   */
+  ParamChecker(void) = delete;
+  /**
+   * @brief Construct a new Param Checker object
+   * @param[in] model Graph model to check
+   */
+  ParamChecker(std::shared_ptr<ir::Graph> model) : _model{model} {}
+
+public:
+  /**
+   * @brief Run parameter analysis
+   */
+  void operator()();
+  /**
+   * @brief   Return analysis result if model have non-const parameter
+   * @return  @c true if there is non-const parameter, otherwise @c false
+   */
+  bool haveNoneConstParam(void) { return _nonConstParam; }
+
+private:
+  const std::shared_ptr<ir::Graph> _model;
+  bool _nonConstParam{false};
+};
+
+} // namespace compiler
+} // namespace neurun
+
+#endif // __NEURUN_COMPILER_OPERATION_VALIDATOR_H__
diff --git a/runtime/neurun/core/src/compiler/SubTensorAnalyzer.cc b/runtime/neurun/core/src/compiler/SubTensorAnalyzer.cc
new file mode 100644
index 000000000..dae1a74ff
--- /dev/null
+++ b/runtime/neurun/core/src/compiler/SubTensorAnalyzer.cc
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "SubTensorAnalyzer.h"
+
+#include <typeinfo>
+
+#include "cpp14/memory.h"
+#include "ir/OperandIndexSequence.h"
+#include "util/logging.h"
+#include "util/Coordinates.h"
+
+namespace neurun
+{
+namespace compiler
+{
+
+void SubTensorAnalyzer::visit(const ir::operation::Concat &node)
+{
+  //  If operator is concat (or other operators related with subsumption), fill subsumption info
+  //  TODO: if one tensor is subset of many parents or model input
+  //        Solution 1. Handle 1st parent only, ignore others (need to invert for other children)
+  //        Solution 2. Insert copy operation for other parents
+  int32_t axis_raw = node.param().axis;
+
+  const auto &output_index = node.getOutputs().at(0);
+  const auto &inputs = node.getInputs();
+
+  int32_t axis_point = 0;
+  const auto rank = _graph.operands().at(output_index).shape().rank();
+  int32_t axis = axis_raw < 0 ? (axis_raw + rank) : axis_raw;
+  assert(rank > axis);
+
+  for (const auto &input_index : inputs)
+  {
+    // NOTE Not support multiple parent tensor yet
+    //
+    // Let us consider the following example (where OP_i is not a CONCAT):
+    //
+    //   %0 = OP_0
+    //   %1 = OP_1
+    //   %2 = OP_2
+    //   %3 = CONCAT(%0, %1)
+    //   %4 = CONCAT(%0, %2)
+    //
+    // %0 and %1 SHOULD be consecutive in order to eliminate the former CONCAT operation,
+    // which makes it impossible to eliminate the latter CONCAT operation.
+    // - Note that %0 and %2 cannot be consecutive.
+    if (_graph.operands().at(input_index).parent_info() != nullptr)
+    {
+      return;
+    }
+
+    // NOTE Not support the case that concat's input is a constant or a input of model
+    if (_graph.operands().at(input_index).isConstant() || _graph.getInputs().contains(input_index))
+    {
+      return;
+    }
+  }
+
+  for (const auto &input_index : inputs)
+  {
+    auto input_shape = _graph.operands().at(input_index).shape();
+    assert(rank == input_shape.rank());
+
+    neurun::util::Coordinates coordinate_info{};
+    for (int i = 0; i < rank; i++)
+    {
+      coordinate_info.set(i, 0);
+    }
+    coordinate_info.set(axis, axis_point);
+
+    auto parentInfo =
+        nnfw::cpp14::make_unique<ir::operand::ParentInfo>(output_index, coordinate_info);
+
+    _graph.operands().at(input_index).parent_info(std::move(parentInfo));
+
+    axis_point += input_shape.dim(axis);
+  }
+}
+
+} // namespace compiler
+} // namespace neurun
diff --git a/runtime/neurun/core/src/compiler/SubTensorAnalyzer.h b/runtime/neurun/core/src/compiler/SubTensorAnalyzer.h
new file mode 100644
index 000000000..54d41e460
--- /dev/null
+++ b/runtime/neurun/core/src/compiler/SubTensorAnalyzer.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file  SubTensorAnalyzer.h
+ * @brief This file contains SubTensorAnalyzer to analyze tensor subsumption
+ *        using operation visitor
+ */
+
+#ifndef __NEURUN_COMPILER_SUBTENSOR_ANALYZER_H__
+#define __NEURUN_COMPILER_SUBTENSOR_ANALYZER_H__
+
+#include "ir/OperationVisitor.h"
+#include "ir/Graph.h"
+
+namespace neurun
+{
+namespace compiler
+{
+
+/**
+ * @brief Class to analyze tensor subsumption
+ */
+class SubTensorAnalyzer : public ir::OperationVisitor
+{
+public:
+  /**
+   * @brief     Construct a new SubTensorAnalyzer object
+   * @param[in] ctx Graph operand set
+   */
+  SubTensorAnalyzer(ir::Graph &graph) : _graph{graph}
+  {
+    // DO NOTHING
+  }
+
+public:
+  void visit(const ir::operation::Concat &) override;
+
+private:
+  ir::Graph &_graph; // TODO Refactor : Do not update Operands
+};
+
+} // namespace compiler
+} // namespace neurun
+
+#endif // __NEURUN_COMPILER_SUBTENSOR_ANALYZER_H__
diff --git a/runtime/neurun/core/src/dumper/dot/DotBuilder.cc b/runtime/neurun/core/src/dumper/dot/DotBuilder.cc
new file mode 100644
index 000000000..4c7089a9c
--- /dev/null
+++ b/runtime/neurun/core/src/dumper/dot/DotBuilder.cc
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "DotBuilder.h"
+
+namespace neurun
+{
+namespace dumper
+{
+namespace dot
+{
+
+// DotDumper
+DotBuilder::DotBuilder() {}
+
+void DotBuilder::update(const Node &node_info)
+{
+  add(node_info);
+  for (auto edge : node_info.edges())
+  {
+    addEdge(node_info, *edge);
+  }
+}
+
+void DotBuilder::addSubgraph(const DotSubgraphInfo &subgraph_info)
+{
+  _dot << "op_seq cluster_" << subgraph_info.index().value() << " {\n";
+  _dot << "  label=\"" << subgraph_info.label() << "\";\n";
+  _dot << "  style=filled;\n";
+  _dot << "  color=lightgrey;\n";
+  _dot << "  ";
+  for (auto op : subgraph_info.operations())
+  {
+    _dot << "operation" << op.value() << "; ";
+  }
+  for (auto op : subgraph_info.operands())
+  {
+    _dot << "operand" << op.value() << "; ";
+  }
+  _dot << "\n";
+  _dot << "}\n";
+}
+
+void DotBuilder::writeDot(std::ostream &os)
+{
+  os << "digraph D {\n"
+     << _dot.str() << "\n"
+     << "}\n";
+}
+
+void DotBuilder::add(const Node &node)
+{
+  _dot << node.id();
+  std::stringstream ss;
+  _dot << "[";
+  for (auto attr : node.attributes())
+  {
+    _dot << attr.first << "=\"" << attr.second << "\" ";
+  }
+  _dot << "];\n";
+}
+
+void DotBuilder::addEdge(const Node &node1, const Node &node2)
+{
+  _dot << node1.id() << " -> " << node2.id() << ";\n";
+}
+
+} // namespace dot
+} // namespace dumper
+} // namespace neurun
diff --git a/runtime/neurun/core/src/dumper/dot/DotBuilder.h b/runtime/neurun/core/src/dumper/dot/DotBuilder.h
new file mode 100644
index 000000000..c04f6bc52
--- /dev/null
+++ b/runtime/neurun/core/src/dumper/dot/DotBuilder.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_DUMPER_DOT_DOT_BUILDER_H__
+#define __NEURUN_DUMPER_DOT_DOT_BUILDER_H__
+
+#include <sstream>
+
+#include "ir/Index.h"
+#include "ir/Operation.h"
+#include "ir/Operand.h"
+
+#include "OperationNode.h"
+#include "OperandNode.h"
+#include "DotSubgraphInfo.h"
+
+using Operation = neurun::ir::Operation;
+using Object = neurun::ir::Operand;
+
+namespace neurun
+{
+namespace dumper
+{
+namespace dot
+{
+
+class DotBuilder
+{
+public:
+  DotBuilder();
+
+public:
+  void update(const Node &dotinfo);
+  void addSubgraph(const DotSubgraphInfo &subgraph_info);
+
+  void writeDot(std::ostream &os);
+
+private:
+  void add(const Node &dotinfo);
+  void addEdge(const Node &dotinfo1, const Node &dotinfo2);
+
+  std::stringstream _dot;
+};
+
+} // namespace dot
+} // namespace dumper
+} // namespace neurun
+
+#endif // __NEURUN_DUMPER_DOT_DOT_BUILDER_H__
diff --git a/runtime/neurun/core/src/dumper/dot/DotDumper.cc b/runtime/neurun/core/src/dumper/dot/DotDumper.cc
new file mode 100644
index 000000000..44313a657
--- /dev/null
+++ b/runtime/neurun/core/src/dumper/dot/DotDumper.cc
@@ -0,0 +1,199 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <fstream>
+#include <unordered_map>
+
+#include "DotDumper.h"
+#include "DotBuilder.h"
+#include "DotSubgraphInfo.h"
+#include "ir/OpSequence.h"
+#include "ir/OperationIndexMap.h"
+#include "backend/Backend.h"
+#include "backend/BackendManager.h"
+#include "backend/IConfig.h"
+
+namespace neurun
+{
+namespace dumper
+{
+namespace dot
+{
+
+void DotDumper::dump(const std::string &tag)
+{
+  if (_level == Level::OFF)
+  {
+    return;
+  }
+
+  neurun::dumper::dot::DotBuilder dot_builder;
+
+  auto &operations = _graph.operations();
+  auto &operands = _graph.operands();
+
+  ir::OperationIndexMap<std::unique_ptr<Operation>> operation_nodes;
+  std::unordered_map<ir::OperandIndex, std::unique_ptr<Operand>> operand_nodes;
+
+  operations.iterate([&](const ir::OperationIndex &index, const ir::Operation &op) {
+    auto node = nnfw::cpp14::make_unique<Operation>(index, op);
+
+    for (auto output : op.getOutputs())
+    {
+      using neurun::dumper::dot::Operand;
+      auto child = std::make_shared<Operand>(output, Operand::Type::MODEL_OUTPUT);
+      node->addEdge(child);
+    }
+
+    operation_nodes.emplace(index, std::move(node));
+  });
+
+  auto backend_to_fillcolor = [](const backend::Backend *backend) {
+    static const auto map = []() {
+      std::unordered_map<const backend::Backend *, std::string> ret;
+      uint32_t index = 1; // Start from 1 to avoid 0(red) which is too dark :(
+      for (const auto backend : backend::BackendManager::get().getAll())
+      {
+        ret.emplace(backend, Node::BG_COLORS[index]);
+        index = (index + 1) % (sizeof(Node::BG_COLORS) / sizeof(Node::BG_COLORS[0]));
+      }
+      return ret;
+    }();
+
+    auto itr = map.find(backend);
+    if (itr == map.end())
+    {
+      return Node::DEFAULT_FILLCOLOR;
+    }
+    else
+    {
+      return itr->second;
+    }
+  };
+
+  util::Set<ir::OperandIndex> shown_operand_set;
+
+  operands.iterate([&](const ir::OperandIndex &index, const ir::Operand &object) {
+    bool showing_cond = false;
+    if (_level == Level::ALL)
+    {
+      showing_cond = true;
+    }
+    else
+    {
+      showing_cond = !object.isConstant();
+    }
+    if (object.isConstant() || _graph.getInputs().contains(index))
+    {
+      showing_cond = showing_cond && (object.getUses().size() > 0);
+    }
+    if (showing_cond)
+    {
+      shown_operand_set.add(index);
+
+      auto type = [&]() {
+        using neurun::dumper::dot::Operand;
+        if (_graph.getInputs().contains(index))
+          return Operand::Type::MODEL_INPUT;
+        if (_graph.getOutputs().contains(index))
+          return Operand::Type::MODEL_OUTPUT;
+        return Operand::Type::INTERNAL;
+      }();
+
+      auto lower_info = _graph.getLowerInfo(index);
+      auto node = nnfw::cpp14::make_unique<Operand>(index, type);
+
+      {
+        // Display LowerInfo attributes
+        std::string label = std::to_string(index.value());
+        std::string fillcolor = "";
+        if (lower_info)
+        {
+          const auto &def_factors = lower_info->def_factors();
+          if (def_factors.size() > 0)
+          {
+            label += "\\n[";
+            label += def_factors.getOnlyElement().backend()->config()->id();
+            label += "]";
+
+            fillcolor = backend_to_fillcolor(lower_info->def_factors().getOnlyElement().backend());
+          }
+        }
+        node->setAttribute("label", label);
+        node->setAttribute("fillcolor", fillcolor);
+      }
+
+      for (auto operation_index : object.getUses().list())
+      {
+        auto &operation = operations.at(operation_index);
+        auto child = std::make_shared<Operation>(operation_index, operation);
+        node->addEdge(child);
+      }
+
+      operand_nodes.emplace(index, std::move(node));
+    }
+  });
+
+  const auto subgraphs = _graph.subgraphs();
+  if (subgraphs)
+  {
+    subgraphs->iterate([&](const ir::SubgraphIndex &index, const ir::OpSequence &op_seq) {
+      const auto lower_info = _graph.getLowerInfo(index);
+      auto fillcolor = backend_to_fillcolor(lower_info->backend());
+      std::string label =
+          std::to_string(index.value()) + " [" + lower_info->backend()->config()->id() + "]";
+      DotSubgraphInfo subgraph_info{index, op_seq, shown_operand_set};
+      subgraph_info.label(label);
+      subgraph_info.fillcolor(fillcolor);
+      dot_builder.addSubgraph(subgraph_info);
+
+      // Set fillcolor of all operations in the op_seq
+      for (const auto &op : op_seq.operations())
+      {
+        auto found = operation_nodes.find(op.index);
+        if (found != operation_nodes.end())
+        {
+          auto &&op = found->second;
+          op->setAttribute("fillcolor", fillcolor);
+        }
+      }
+    });
+  }
+
+  for (const auto &e : operation_nodes)
+    dot_builder.update(*e.second);
+  for (const auto &e : operand_nodes)
+    dot_builder.update(*e.second);
+
+  // Dump to file
+  {
+    std::string file_name;
+    file_name += tag;
+    file_name += ".dot";
+    std::filebuf fb;
+
+    fb.open(file_name, std::ios::out);
+    std::ostream os(&fb);
+
+    dot_builder.writeDot(os);
+
+    fb.close();
+  }
+}
+
+} // namespace dot
+} // namespace dumper
+} // namespace neurun
diff --git a/runtime/neurun/core/src/dumper/dot/DotDumper.h b/runtime/neurun/core/src/dumper/dot/DotDumper.h
new file mode 100644
index 000000000..ec4d2b967
--- /dev/null
+++ b/runtime/neurun/core/src/dumper/dot/DotDumper.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/Graph.h"
+
+#ifndef __NEURUN_DUMPER_DOT_DOT_DUMPER_H__
+#define __NEURUN_DUMPER_DOT_DOT_DUMPER_H__
+
+namespace neurun
+{
+namespace dumper
+{
+namespace dot
+{
+
+class DotDumper
+{
+public:
+  enum Level
+  {
+    OFF = 0,               //< Do not dump
+    ALL_BUT_CONSTANTS = 1, //< Emit all operations and operands but constants
+    ALL = 2                //< Emit all operations and operands
+  };
+
+public:
+  DotDumper(const ir::Graph &graph, Level level) : _graph(graph), _level{level} {}
+
+public:
+  /**
+   * @brief Dump to dot file as tag name if "GRAPH_DOT_DUMP" is set
+   *
+   * @param[in] tag    The name of dot file that would be created
+   * @return N/A
+   */
+  void dump(const std::string &tag);
+
+private:
+  const ir::Graph &_graph;
+  Level _level;
+};
+
+} // namespace dot
+} // namespace dumper
+} // namespace neurun
+
+#endif // __NEURUN_DUMPER_DOT_DOT_DUMPER_H__
diff --git a/runtime/neurun/core/src/dumper/dot/DotSubgraphInfo.cc b/runtime/neurun/core/src/dumper/dot/DotSubgraphInfo.cc
new file mode 100644
index 000000000..8cfe35900
--- /dev/null
+++ b/runtime/neurun/core/src/dumper/dot/DotSubgraphInfo.cc
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "DotSubgraphInfo.h"
+
+#include <sstream>
+
+namespace neurun
+{
+namespace dumper
+{
+namespace dot
+{
+
+DotSubgraphInfo::DotSubgraphInfo(const ir::SubgraphIndex &index, const ir::OpSequence &op_seq,
+                                 const util::Set<ir::OperandIndex> &shown_operands)
+    : _index{index}
+{
+  for (const auto &element : op_seq.operations())
+  {
+    _operations.insert(element.index);
+    for (auto o : element.node->getInputs())
+    {
+      // Must be a shown operand, not op_seq's inputs
+      if (shown_operands.contains(o) && !op_seq.getInputs().contains(o))
+      {
+        _operands.insert(o);
+      }
+    }
+    for (auto o : element.node->getOutputs())
+    {
+      // Must be a shown operand, not op_seq's inputs
+      if (shown_operands.contains(o) && !op_seq.getOutputs().contains(o))
+      {
+        _operands.insert(o);
+      }
+    }
+  }
+}
+
+} // namespace dot
+} // namespace dumper
+} // namespace neurun
diff --git a/runtime/neurun/core/src/dumper/dot/DotSubgraphInfo.h b/runtime/neurun/core/src/dumper/dot/DotSubgraphInfo.h
new file mode 100644
index 000000000..0aa7c6ddf
--- /dev/null
+++ b/runtime/neurun/core/src/dumper/dot/DotSubgraphInfo.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_CORE_DUMPER_DOT_DOT_SUBGRAPH_INFO_H__
+#define __NEURUN_CORE_DUMPER_DOT_DOT_SUBGRAPH_INFO_H__
+
+#include <unordered_set>
+
+#include "ir/Index.h"
+#include "ir/OpSequence.h"
+#include "util/Set.h"
+
+namespace neurun
+{
+namespace dumper
+{
+namespace dot
+{
+
+class DotSubgraphInfo
+{
+public:
+  DotSubgraphInfo(const ir::SubgraphIndex &index, const ir::OpSequence &op_seq,
+                  const util::Set<ir::OperandIndex> &shown_operands);
+
+  ir::SubgraphIndex index() const { return _index; }
+  std::string label() const { return _label; }
+  void label(const std::string &val) { _label = val; }
+  std::string fillcolor() const { return _fillcolor; }
+  void fillcolor(const std::string &val) { _fillcolor = val; }
+  const std::unordered_set<ir::OperationIndex> &operations() const { return _operations; }
+  const std::unordered_set<ir::OperandIndex> &operands() const { return _operands; }
+
+private:
+  ir::SubgraphIndex _index;
+  std::string _label;
+  std::string _fillcolor;
+  std::unordered_set<ir::OperationIndex> _operations;
+  std::unordered_set<ir::OperandIndex> _operands;
+};
+
+} // namespace dot
+} // namespace dumper
+} // namespace neurun
+
+#endif // __NEURUN_CORE_DUMPER_DOT_DOT_SUBGRAPH_INFO_H__
diff --git a/runtime/neurun/core/src/dumper/dot/Node.cc b/runtime/neurun/core/src/dumper/dot/Node.cc
new file mode 100644
index 000000000..166f0f40f
--- /dev/null
+++ b/runtime/neurun/core/src/dumper/dot/Node.cc
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "Node.h"
+
+namespace neurun
+{
+namespace dumper
+{
+namespace dot
+{
+
+const std::string Node::DEFAULT_COLORSCHEME = "x11";
+const std::string Node::DEFAULT_FILLCOLOR = "white";
+// RED, BLUE, GREEN, PURPLE, ORANGE, YELLOW, BROWN, PINK
+const std::string Node::BG_COLORS[8] = {"1", "2", "3", "4", "5", "6", "7", "8"};
+
+Node::Node(const std::string &id) : _id{id}
+{
+  // Set default values
+  _attributes["style"] = "filled";
+  _attributes["colorscheme"] = DEFAULT_COLORSCHEME;
+  _attributes["fillcolor"] = DEFAULT_FILLCOLOR;
+}
+
+void Node::setAttribute(const std::string &key, const std::string &val) { _attributes[key] = val; }
+
+std::string Node::getAttribute(const std::string &key)
+{
+  auto itr = _attributes.find(key);
+  if (itr == _attributes.end())
+  {
+    return "";
+  }
+  else
+  {
+    return itr->second;
+  }
+}
+
+} // namespace dot
+} // namespace dumper
+} // namespace neurun
diff --git a/runtime/neurun/core/src/dumper/dot/Node.h b/runtime/neurun/core/src/dumper/dot/Node.h
new file mode 100644
index 000000000..364cb08a4
--- /dev/null
+++ b/runtime/neurun/core/src/dumper/dot/Node.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Node.h
+ * @brief    This file contains Node class
+ * @ingroup  COM_AI_RUNTIME
+ *
+ */
+
+#ifndef __NEURUN_DUMPER_DOT_NODE_H__
+#define __NEURUN_DUMPER_DOT_NODE_H__
+
+#include <string>
+#include <memory>
+#include <vector>
+#include <unordered_map>
+
+namespace neurun
+{
+namespace dumper
+{
+namespace dot
+{
+
+enum BGCOLORS : int
+{
+  RED,
+  BLUE,
+  GREEN,
+  PUPLE,
+  ORANGE,
+  YELLOW,
+  BROWN,
+  PINK
+};
+
+/**
+ * @brief Class that represents a Node in "dot" format
+ *
+*/
+class Node
+{
+public:
+  const static std::string DEFAULT_FILLCOLOR;
+  const static std::string DEFAULT_COLORSCHEME;
+  const static std::string BG_COLORS[8];
+
+public:
+  /**
+   * @brief Destroy the Node object
+   *
+  */
+  virtual ~Node() = default;
+
+  /**
+   * @brief Construct a new Node object
+   *
+   * @param id
+  */
+  Node(const std::string &id);
+
+  /**
+   * @brief return id
+   *
+   * @return id
+  */
+  std::string id() const { return _id; }
+
+  /**
+   * @brief return attributes
+   *
+   * @return const reference of attributes object
+  */
+  const std::unordered_map<std::string, std::string> &attributes() const { return _attributes; }
+  /**
+   * @brief Store an attribute with key-value pair
+   *
+   * @param[in] key attribute's key
+   * @param[in] val attribute's value that is associated with the key
+  */
+  void setAttribute(const std::string &key, const std::string &val);
+  /**
+   * @brief Get the attributte value that is associated with key
+   *
+   * @param[in] key key of the attribute
+   * @return value that is associated with the key
+  */
+  std::string getAttribute(const std::string &key);
+
+  /**
+   * @brief Add an edge in the graph, which is an outgoing edge
+   *
+   * @param[in] dotinfo A node that the new edge will be connected to
+  */
+  void addEdge(std::shared_ptr<Node> dotinfo) { _children.emplace_back(dotinfo); }
+  /**
+   * @brief Return list of edges
+   *
+   * @return Edges
+  */
+  const std::vector<std::shared_ptr<Node>> &edges() const { return _children; }
+
+private:
+  std::string _id;
+  std::unordered_map<std::string, std::string> _attributes;
+  std::vector<std::shared_ptr<Node>> _children;
+};
+
+} // namespace dot
+} // namespace dumper
+} // namespace neurun
+
+#endif // __NEURUN_DUMPER_DOT_NODE_H__
diff --git a/runtime/neurun/core/src/dumper/dot/OperandNode.cc b/runtime/neurun/core/src/dumper/dot/OperandNode.cc
new file mode 100644
index 000000000..76d2c704c
--- /dev/null
+++ b/runtime/neurun/core/src/dumper/dot/OperandNode.cc
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <sstream>
+
+#include "OperandNode.h"
+#include "ir/Graph.h"
+#include "ir/operand/LowerInfo.h"
+
+namespace neurun
+{
+namespace dumper
+{
+namespace dot
+{
+
+const std::string Operand::INPUT_SHAPE = "doublecircle";
+const std::string Operand::OUTPUT_SHAPE = "doublecircle";
+const std::string Operand::OPERAND_SHAPE = "ellipse";
+const std::string Operand::BG_COLOR_SCHEME = "set18";
+
+Operand::Operand(const ir::OperandIndex &index, Type type)
+    : Node{"operand" + std::to_string(index.value())}
+{
+  {
+    auto type_to_shape = [](Type type) {
+      switch (type)
+      {
+        case Type::MODEL_INPUT:
+          return INPUT_SHAPE;
+        case Type::MODEL_OUTPUT:
+          return OUTPUT_SHAPE;
+        case Type::UNDEFINED:
+        case Type::INTERNAL:
+        default:
+          return OPERAND_SHAPE;
+      }
+    };
+    setAttribute("shape", type_to_shape(type));
+  }
+
+  setAttribute("colorscheme", BG_COLOR_SCHEME);
+}
+
+} // namespace dot
+} // namespace dumper
+} // namespace neurun
diff --git a/runtime/neurun/core/src/dumper/dot/OperandNode.h b/runtime/neurun/core/src/dumper/dot/OperandNode.h
new file mode 100644
index 000000000..5ebd651b6
--- /dev/null
+++ b/runtime/neurun/core/src/dumper/dot/OperandNode.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Operand.h
+ * @brief    This file contains Operand
+ * @ingroup  COM_AI_RUNTIME
+ *
+ */
+
+#ifndef __NEURUN_DUMPER_DOT_DOT_OPERAND_INFO_H__
+#define __NEURUN_DUMPER_DOT_DOT_OPERAND_INFO_H__
+
+#include <vector>
+
+#include "Node.h"
+#include "ir/Operand.h"
+#include "ir/Index.h"
+
+namespace neurun
+{
+namespace dumper
+{
+namespace dot
+{
+
+/**
+ * @brief Class that represents an Operand
+ *
+ */
+class Operand : public Node
+{
+public:
+  enum class Type
+  {
+    UNDEFINED,
+    MODEL_INPUT,
+    MODEL_OUTPUT,
+    INTERNAL
+  };
+
+public:
+  static const std::string INPUT_SHAPE;
+  static const std::string OUTPUT_SHAPE;
+  static const std::string OPERAND_SHAPE;
+  static const std::string BG_COLOR_SCHEME;
+
+public:
+  /**
+   * @brief Construct a new Operand Node object
+   *
+   * @param[in] index Operand index
+   * @param[in] type Operand type
+   * @param[in] lower_info Operand LowerInfo
+   */
+  Operand(const ir::OperandIndex &index, Type type);
+
+private:
+  void addBackendLabel();
+};
+
+} // namespace dot
+} // namespace dumper
+} // namespace neurun
+
+#endif // __NEURUN_DUMPER_DOT_DOT_OPERAND_INFO_H__
diff --git a/runtime/neurun/core/src/dumper/dot/OperationNode.cc b/runtime/neurun/core/src/dumper/dot/OperationNode.cc
new file mode 100644
index 000000000..ca870ba05
--- /dev/null
+++ b/runtime/neurun/core/src/dumper/dot/OperationNode.cc
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <sstream>
+
+#include "OperationNode.h"
+#include "ir/Graph.h"
+#include "ir/operation/LowerInfo.h"
+#include "backend/IConfig.h"
+#include "backend/Backend.h"
+
+namespace neurun
+{
+namespace dumper
+{
+namespace dot
+{
+
+const std::string Operation::OPERATION_SHAPE = "rect";
+const std::string Operation::BG_COLOR_SCHEME = "pastel18";
+
+Operation::Operation(const ir::OperationIndex &index, const ir::Operation &node)
+    : Node{"operation" + std::to_string(index.value())}
+{
+  setAttribute("label", std::to_string(index.value()) + " : " + node.name());
+  setAttribute("shape", OPERATION_SHAPE);
+  setAttribute("colorscheme", BG_COLOR_SCHEME);
+  setAttribute("fillcolor", DEFAULT_FILLCOLOR);
+}
+
+} // namespace dot
+} // namespace dumper
+} // namespace neurun
diff --git a/runtime/neurun/core/src/dumper/dot/OperationNode.h b/runtime/neurun/core/src/dumper/dot/OperationNode.h
new file mode 100644
index 000000000..ba0713790
--- /dev/null
+++ b/runtime/neurun/core/src/dumper/dot/OperationNode.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Operation.h
+ * @brief    This file contains Operation
+ * @ingroup  COM_AI_RUNTIME
+ *
+ */
+
+#ifndef __NEURUN_DUMPER_DOT_DOT_NODE_INFO_H__
+#define __NEURUN_DUMPER_DOT_DOT_NODE_INFO_H__
+
+#include "Node.h"
+#include "ir/Operation.h"
+#include "ir/Index.h"
+
+namespace neurun
+{
+namespace dumper
+{
+namespace dot
+{
+
+/**
+ * @brief Class that represents an Operation
+ *
+ */
+class Operation : public Node
+{
+public:
+  static const std::string OPERATION_SHAPE;
+  static const std::string BG_COLOR_SCHEME;
+
+public:
+  /**
+   * @brief Construct a new Operation Node object
+   *
+   * @param[in] index operation index
+   * @param[in] node operation object
+  */
+  Operation(const ir::OperationIndex &index, const ir::Operation &node);
+};
+
+} // namespace dot
+} // namespace dumper
+} // namespace neurun
+
+#endif // __NEURUN_DUMPER_DOT_DOT_NODE_INFO_H__
diff --git a/runtime/neurun/core/src/exec/DataflowExecutor.cc b/runtime/neurun/core/src/exec/DataflowExecutor.cc
new file mode 100644
index 000000000..e22d41031
--- /dev/null
+++ b/runtime/neurun/core/src/exec/DataflowExecutor.cc
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "DataflowExecutor.h"
+
+#include <cassert>
+
+#include "util/logging.h"
+
+namespace neurun
+{
+namespace exec
+{
+
+int64_t DataflowExecutor::calculateRank(const std::vector<ir::Element> &operations)
+{
+  int64_t rank = 0;
+  if (!_indexed_ranks)
+  {
+    return rank;
+  }
+  for (const auto &element : operations)
+  {
+    auto it = _indexed_ranks->find(element.index);
+    if (it == _indexed_ranks->end())
+    {
+      assert(element.node->opcode() == ir::OpCode::Permute);
+      // assign int32_t::max to prevent integer overflow
+      rank += std::numeric_limits<int32_t>::max();
+    }
+    else
+    {
+      rank += it->second;
+    }
+  }
+  return rank;
+}
+
+void DataflowExecutor::emplaceToReadyJobs(const uint32_t &id)
+{
+  auto &job = _waiting_jobs[id];
+  assert(job != nullptr);
+  auto &subg = _graph.subgraphs()->at(_job_to_op_seq[job->index()]);
+  auto rank = calculateRank(subg.operations());
+  _ready_jobs.emplace(rank, std::move(job));
+}
+
+void DataflowExecutor::notify(uint32_t finished_job_id)
+{
+  for (auto id : _output_info[finished_job_id])
+  {
+    assert(_input_info[id] > 0);
+    auto count = --_input_info[id];
+    if (count == 0) // No dependent jobs left, ready for execution
+    {
+      emplaceToReadyJobs(id);
+    }
+  }
+}
+bool DataflowExecutor::noWaitingJobs()
+{
+  return std::all_of(_waiting_jobs.begin(), _waiting_jobs.end(),
+                     [](const std::unique_ptr<Job> &job) { return job == nullptr; });
+}
+
+DataflowExecutor::DataflowExecutor(const ir::Graph &graph,
+                                   const std::shared_ptr<compiler::OperandContext> &operand_context,
+                                   std::unique_ptr<backend::TensorManagerSet> tensor_mgrs,
+                                   CodeMap &&code_map)
+    : ExecutorBase{graph, operand_context, std::move(tensor_mgrs)}, _code_map{std::move(code_map)}
+{
+  VERBOSE(DataflowExecutor) << "Constructing Dataflow Executor" << std::endl;
+
+  const ir::Subgraphs *subgraphs = _graph.subgraphs();
+  // Assign jobs convert SubgraphIndex to job index(uint32_t)
+  uint32_t next_job_index = 0;
+  std::unordered_map<ir::SubgraphIndex, uint32_t> subgraph_to_job;
+  subgraphs->iterate([&](const ir::SubgraphIndex &subg_index, const ir::OpSequence &) {
+    VERBOSE(DataflowExecutor) << "Create a job #" << next_job_index << " with SubgraphIndex "
+                              << subg_index.value() << std::endl;
+    _finished_jobs.emplace_back(
+        nnfw::cpp14::make_unique<Job>(next_job_index, _code_map.at(subg_index).get()));
+    subgraph_to_job[subg_index] = next_job_index++;
+  });
+
+  _waiting_jobs.resize(next_job_index);
+  _output_info.resize(next_job_index);
+  _initial_input_info.resize(next_job_index, 0);
+
+  subgraphs->iterate([&](const ir::SubgraphIndex &subg_index, const ir::OpSequence &subg) {
+    auto job_index = subgraph_to_job[subg_index];
+    for (auto output : subg.getOutputs())
+    {
+      // Update output and input info
+      subgraphs->iterate(
+          [&](const ir::SubgraphIndex &subg_cur_index, const ir::OpSequence &subg_cur) {
+            if (subg_cur.getInputs().contains(output))
+            {
+              auto dep_index = subgraph_to_job[subg_cur_index];
+              ++_initial_input_info[dep_index];
+              _output_info[job_index].push_back(dep_index);
+            }
+          });
+    }
+  });
+  for (const auto &s : subgraph_to_job)
+    _job_to_op_seq.emplace(s.second, s.first);
+
+  _input_info = _initial_input_info;
+}
+
+void DataflowExecutor::executeImpl()
+{
+  assert(noWaitingJobs());
+
+  // Execution setup
+  _waiting_jobs.swap(_finished_jobs); // Move finished jobs to waiting jobs
+
+  for (uint32_t i = 0; i < _waiting_jobs.size(); ++i)
+  {
+    if (_input_info[i] == 0)
+    {
+      emplaceToReadyJobs(i);
+    }
+  }
+  assert(!_ready_jobs.empty()); // Cannot begin if there is no initial jobs
+  bool is_profiling = util::getConfigBool(util::config::PROFILING_MODE);
+
+  _subject.notifyModelBegin(this);
+
+  while (!_ready_jobs.empty())
+  {
+    auto job = std::move((_ready_jobs.begin())->second);
+    _ready_jobs.erase(_ready_jobs.begin());
+    auto job_index = job->index();
+    VERBOSE(DataflowExecutor) << "Run job #" << job_index << std::endl;
+
+    auto subgraph_index = _job_to_op_seq[job_index];
+    auto op_seq = &_graph.subgraphs()->at(subgraph_index);
+    const backend::Backend *backend =
+        _graph.getLowerInfo()->operation.at(subgraph_index)->backend();
+
+    _subject.notifyJobBegin(this, op_seq, backend);
+
+    if (is_profiling)
+      job->fn()->runSync();
+    else
+      job->run();
+
+    _subject.notifyJobEnd(this, op_seq, backend);
+    notify(job_index);
+    _finished_jobs[job_index] = std::move(job);
+  }
+  assert(noWaitingJobs());
+
+  _subject.notifyModelEnd(this);
+
+  // Reset input info for the next execution
+  _input_info = _initial_input_info;
+}
+
+} // namespace exec
+} // namespace neurun
diff --git a/runtime/neurun/core/src/exec/DataflowExecutor.h b/runtime/neurun/core/src/exec/DataflowExecutor.h
new file mode 100644
index 000000000..6c12093fd
--- /dev/null
+++ b/runtime/neurun/core/src/exec/DataflowExecutor.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_EXEC_DATAFLOW_EXECUTOR_H__
+#define __NEURUN_EXEC_DATAFLOW_EXECUTOR_H__
+
+#include <list>
+#include <map>
+#include <unordered_map>
+
+#include "FunctionSequence.h"
+#include "Job.h"
+#include "ir/OperandIndexSequence.h"
+#include "ir/Index.h"
+#include "cpp14/memory.h"
+#include "exec/ExecutorBase.h"
+
+namespace neurun
+{
+namespace exec
+{
+
+class DataflowExecutor : public ExecutorBase
+{
+public:
+  using CodeMap = std::unordered_map<ir::SubgraphIndex, std::unique_ptr<FunctionSequence>>;
+
+protected:
+  virtual void notify(uint32_t finished_job_id);
+  bool noWaitingJobs();
+
+public:
+  /**
+   * @brief Constructs a DataflowExecutor object
+   *
+   * @param graph Graph object
+   * @param operand_context (Only for input/output operand data access)
+   * @param code_map Compiled code map
+   * @param ranks Operation ranks for ordering execution
+   */
+  DataflowExecutor(const ir::Graph &graph,
+                   const std::shared_ptr<compiler::OperandContext> &operand_context,
+                   std::unique_ptr<backend::TensorManagerSet> tensor_mgrs, CodeMap &&code_map);
+
+  void executeImpl() override;
+
+protected:
+  int64_t calculateRank(const std::vector<ir::Element> &operations);
+  void emplaceToReadyJobs(const uint32_t &id);
+
+protected:
+  CodeMap _code_map;
+  /**
+   * @brief A vector of finished jobs for current execution
+   *        After a run it has all the jobs of this execution for the next run
+   */
+  std::vector<std::unique_ptr<Job>> _finished_jobs;
+  /**
+   * @brief A vector of waiting jobs for current execution
+   *        All the jobs are moved from #_finished_jobs to it when start a run
+   */
+  std::vector<std::unique_ptr<Job>> _waiting_jobs;
+  /**
+   * @brief Jobs' output info
+   *        Used for notifying after finishing a job
+   */
+  std::vector<std::list<uint32_t>> _output_info;
+  std::vector<uint32_t> _initial_input_info;
+  std::vector<uint32_t> _input_info;
+  /**
+   * @brief A collection of jobs that are ready for execution
+   *        Jobs in it are ready to be scheduled.
+   *        Ordered by priority from `_indexed_ranks`
+   */
+  std::multimap<int64_t, std::unique_ptr<Job>, std::greater<int64_t>> _ready_jobs;
+
+  /// @brief Which job runs which op and function.
+  std::unordered_map<uint32_t, ir::SubgraphIndex> _job_to_op_seq;
+};
+
+} // namespace exec
+} // namespace neurun
+
+#endif // __NEURUN_EXEC_DATAFLOW_EXECUTOR_H__
diff --git a/runtime/neurun/core/src/exec/Execution.cc b/runtime/neurun/core/src/exec/Execution.cc
new file mode 100644
index 000000000..bc7bbd160
--- /dev/null
+++ b/runtime/neurun/core/src/exec/Execution.cc
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "exec/Execution.h"
+
+#include "util/logging.h"
+
+namespace neurun
+{
+namespace exec
+{
+
+Execution::Execution(const std::shared_ptr<IExecutor> &executor) : _executor{executor}
+{
+  _io_desc.inputs.resize(_executor->graph().getInputs().size());
+  _io_desc.outputs.resize(_executor->graph().getOutputs().size());
+}
+
+// TODO Remove default parameter
+void Execution::setInput(const ir::IOIndex &index, const void *buffer, size_t length,
+                         ir::Layout layout)
+{
+  const auto input_index = graph().getInputs().at(index);
+  const auto info = graph().operands().at(input_index).info();
+
+  if (length < info.total_size())
+  {
+    throw std::runtime_error{"Too small length"};
+  }
+
+  _io_desc.inputs.at(index.value()) =
+      nnfw::cpp14::make_unique<InputDesc>(info, buffer, length, layout);
+}
+
+// TODO Remove default parameter
+void Execution::setInput(const ir::IOIndex &index, const ir::TypeInfo &type, const ir::Shape &shape,
+                         const void *buffer, size_t length, ir::Layout layout)
+{
+  const ir::OperandInfo info{shape, type};
+
+  if (length < info.total_size())
+  {
+    throw std::runtime_error{"Too small length"};
+  }
+
+  _io_desc.inputs.at(index.value()) =
+      nnfw::cpp14::make_unique<InputDesc>(info, buffer, length, layout);
+}
+
+// TODO Remove default parameter
+void Execution::setOutput(const ir::IOIndex &index, void *buffer, size_t length, ir::Layout layout)
+{
+  const auto output_index = graph().getOutputs().at(index);
+  const auto info = graph().operands().at(output_index).info();
+
+  if (length < info.total_size())
+  {
+    throw std::runtime_error{"Too small length"};
+  }
+
+  _io_desc.outputs.at(index.value()) =
+      nnfw::cpp14::make_unique<OutputDesc>(info, buffer, length, layout);
+}
+
+// TODO Remove default parameter
+void Execution::setOutput(const ir::IOIndex &index, const ir::TypeInfo &type,
+                          const ir::Shape &shape, void *buffer, size_t length, ir::Layout layout)
+{
+  const ir::OperandInfo info{shape, type};
+
+  if (length < info.total_size())
+  {
+    throw std::runtime_error{"Too small length"};
+  }
+
+  _io_desc.outputs.at(index.value()) =
+      nnfw::cpp14::make_unique<OutputDesc>(info, buffer, length, layout);
+}
+
+void Execution::setInputLayout(const ir::IOIndex &index, ir::Layout layout)
+{
+  const auto &input_desc = _io_desc.inputs.at(index.value());
+  _io_desc.inputs.at(index.value()) = nnfw::cpp14::make_unique<InputDesc>(
+      input_desc->info, input_desc->buffer, input_desc->size, layout);
+}
+
+void Execution::setOutputLayout(const ir::IOIndex &index, ir::Layout layout)
+{
+  const auto &output_desc = _io_desc.outputs.at(index.value());
+  _io_desc.outputs.at(index.value()) = nnfw::cpp14::make_unique<OutputDesc>(
+      output_desc->info, output_desc->buffer, output_desc->size, layout);
+}
+
+void Execution::execute()
+{
+  VERBOSE(Execution) << "Start execution" << std::endl;
+
+  _executor->execute(_io_desc);
+  finished = true;
+
+  VERBOSE(Execution) << "Execution finished" << std::endl;
+}
+
+void Execution::startExecute()
+{
+  VERBOSE(Execution) << "Create asynchronous execution thread" << std::endl;
+
+  _exec_thread = nnfw::cpp14::make_unique<std::thread>(&Execution::execute, this);
+}
+
+void Execution::waitFinish()
+{
+  VERBOSE(Execution) << "Wait to finish execution" << std::endl;
+
+  _exec_thread->join();
+  finished = true;
+}
+
+bool Execution::isFinished(void) const { return finished; }
+
+} // namespace exec
+} // namespace neurun
diff --git a/runtime/neurun/core/src/exec/ExecutionObservee.cc b/runtime/neurun/core/src/exec/ExecutionObservee.cc
new file mode 100644
index 000000000..3b342d703
--- /dev/null
+++ b/runtime/neurun/core/src/exec/ExecutionObservee.cc
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ExecutionObservee.h"
+
+namespace neurun
+{
+namespace exec
+{
+
+void ExecutionObservee::add(std::unique_ptr<IExecutionObserver> observer)
+{
+  _observers.emplace_back(std::move(observer));
+}
+
+void ExecutionObservee::notifyModelBegin(IExecutor *executor)
+{
+  for (auto &o : _observers)
+  {
+    o->handleBegin(executor);
+  }
+}
+
+void ExecutionObservee::notifyModelEnd(IExecutor *executor)
+{
+  for (auto &o : _observers)
+  {
+    o->handleEnd(executor);
+  }
+}
+
+void ExecutionObservee::notifyJobBegin(IExecutor *executor, const ir::OpSequence *op_seq,
+                                       const backend::Backend *backend)
+{
+  for (auto &o : _observers)
+  {
+    o->handleBegin(executor, op_seq, backend);
+  }
+}
+
+void ExecutionObservee::notifyJobEnd(IExecutor *executor, const ir::OpSequence *op_seq,
+                                     const backend::Backend *backend)
+{
+  for (auto &o : _observers)
+  {
+    o->handleEnd(executor, op_seq, backend);
+  }
+}
+
+} // namespace exec
+} // namespace neurun
diff --git a/runtime/neurun/core/src/exec/ExecutionObservee.h b/runtime/neurun/core/src/exec/ExecutionObservee.h
new file mode 100644
index 000000000..dafeef55b
--- /dev/null
+++ b/runtime/neurun/core/src/exec/ExecutionObservee.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_EXEC_EXECUTION_OBSERVEE_H__
+#define __NEURUN_EXEC_EXECUTION_OBSERVEE_H__
+
+#include <list>
+
+#include "exec/ExecutionObservers.h"
+
+namespace neurun
+{
+namespace exec
+{
+
+/**
+ * @brief Class that
+ *
+ */
+class ExecutionObservee
+{
+public:
+  /**
+   * @brief Register an observer
+   *
+   * @param observer Observer to be added
+   */
+  void add(std::unique_ptr<IExecutionObserver> observer);
+  void notifyModelBegin(IExecutor *executor);
+  void notifyModelEnd(IExecutor *executor);
+  void notifyJobBegin(IExecutor *executor, const ir::OpSequence *op_seq,
+                      const backend::Backend *backend);
+  void notifyJobEnd(IExecutor *executor, const ir::OpSequence *op_seq,
+                    const backend::Backend *backend);
+
+private:
+  std::list<std::unique_ptr<IExecutionObserver>> _observers;
+};
+
+} // namespace exec
+} // namespace neurun
+
+#endif // __NEURUN_EXEC_EXECUTION_OBSERVEE__
diff --git a/runtime/neurun/core/src/exec/ExecutionObservers.cc b/runtime/neurun/core/src/exec/ExecutionObservers.cc
new file mode 100644
index 000000000..071a9e228
--- /dev/null
+++ b/runtime/neurun/core/src/exec/ExecutionObservers.cc
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "exec/ExecutionObservers.h"
+
+#include <string>
+
+#include "util/logging.h"
+#include "ir/operation/Permute.h"
+#include "exec/IExecutor.h"
+#include "misc/polymorphic_downcast.h"
+#include "ir/OpSequence.h"
+
+namespace neurun
+{
+
+namespace exec
+{
+
+void ProfileObserver::handleBegin(neurun::exec::IExecutor *, const ir::OpSequence *,
+                                  const neurun::backend::Backend *backend)
+{
+  _timer = backend->config()->timer();
+  if (_timer == nullptr)
+    throw std::runtime_error("To profile backend timer() method must be implemented");
+  _timer->handleBegin();
+}
+
+void ProfileObserver::handleEnd(IExecutor *exec, const ir::OpSequence *op_seq,
+                                const backend::Backend *backend)
+{
+  _timer->handleEnd();
+  const auto timer_res = _timer->getTime();
+
+  // NOTE This assumes there is just one operation in a op_seq
+  auto node = op_seq->operations().at(0).node;
+  auto node_name = node->name();
+  VERBOSE(ProfileInfo) << "Time for " << node_name << " : " << timer_res << std::endl;
+
+  // fill ExecTime:
+  bool is_quantized = exec->graph().operands().at(node->getInputs().at(0)).typeInfo().type() ==
+                      ir::DataType::QUANT8_ASYMM;
+
+  uint32_t size = 0;
+  for (const auto &input : node->getInputs())
+  {
+    size += exec->graph().operands().at(input).info().total_size();
+  }
+  for (const auto &output : node->getOutputs())
+  {
+    size += exec->graph().operands().at(output).info().total_size();
+  }
+  if (node_name == "Permute")
+  {
+    auto *permute_node = nnfw::misc::polymorphic_downcast<const ir::operation::Permute *>(node);
+    assert(permute_node != nullptr);
+    _et->updatePermuteTime(permute_node->param().input_backend_ctx->backend,
+                           permute_node->param().output_backend_ctx->backend, is_quantized, size,
+                           timer_res);
+  }
+  else
+  {
+    _et->updateOperationExecTime(backend, node_name, is_quantized, size, timer_res);
+  }
+};
+
+ChromeTracingObserver::ChromeTracingObserver(const std::string &filepath)
+    : _ofs{filepath, std::ofstream::out}, _recorder{}, _collector{&_recorder}
+{
+}
+
+ChromeTracingObserver::~ChromeTracingObserver() { _recorder.writeToFile(_ofs); }
+
+void ChromeTracingObserver::handleBegin(IExecutor *)
+{
+  _collector.onEvent(EventCollector::Event{EventCollector::Edge::BEGIN, "runtime", "Graph"});
+}
+
+void ChromeTracingObserver::handleBegin(IExecutor *, const ir::OpSequence *op_seq,
+                                        const backend::Backend *backend)
+{
+  std::string backend_id = backend->config()->id();
+  _collector.onEvent(
+      EventCollector::Event{EventCollector::Edge::BEGIN, backend_id, subgraphTag(op_seq)});
+}
+
+void ChromeTracingObserver::handleEnd(IExecutor *, const ir::OpSequence *op_seq,
+                                      const backend::Backend *backend)
+{
+  std::string backend_id = backend->config()->id();
+  _collector.onEvent(
+      EventCollector::Event{EventCollector::Edge::END, backend_id, subgraphTag(op_seq)});
+}
+
+void ChromeTracingObserver::handleEnd(IExecutor *)
+{
+  _collector.onEvent(EventCollector::Event{EventCollector::Edge::END, "runtime", "Graph"});
+}
+
+std::string ChromeTracingObserver::subgraphTag(const ir::OpSequence *op_seq)
+{
+  if (op_seq->size() == 0)
+    return "Empty OpSequence";
+
+  auto first_op = op_seq->operations().at(0);
+  std::string tag = "$" + std::to_string(first_op.index.value());
+  tag += " " + first_op.node->name();
+  if (op_seq->size() > 1)
+  {
+    tag += " (+" + std::to_string(op_seq->size() - 1) + ")";
+  }
+  return tag;
+}
+
+} // namespace exec
+
+} // namespace neurun
diff --git a/runtime/neurun/core/src/exec/ExecutorBase.cc b/runtime/neurun/core/src/exec/ExecutorBase.cc
new file mode 100644
index 000000000..9692c2ba7
--- /dev/null
+++ b/runtime/neurun/core/src/exec/ExecutorBase.cc
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ExecutorBase.h"
+#include "util/logging.h"
+namespace neurun
+{
+namespace exec
+{
+
+ExecutorBase::ExecutorBase(const ir::Graph &graph,
+                           const std::shared_ptr<compiler::OperandContext> &operand_context,
+                           std::unique_ptr<backend::TensorManagerSet> tensor_mgrs)
+    : _graph{graph}, _operand_context{operand_context}, _tensor_mgrs{std::move(tensor_mgrs)},
+      _mutex()
+{
+  // DO NOTHING
+}
+
+std::unique_ptr<ISource> ExecutorBase::source(const ir::IOIndex &index, const ir::TypeInfo &type,
+                                              const void *buffer, size_t length,
+                                              ir::Layout io_layout)
+{
+  using ir::DataType;
+  switch (type.type())
+  {
+    case DataType::FLOAT32:
+      return source<float>(index, buffer, length, io_layout);
+    case DataType::INT32:
+      return source<int32_t>(index, buffer, length, io_layout);
+    case DataType::UINT32:
+      return source<uint32_t>(index, buffer, length, io_layout);
+    case DataType::BOOL8:
+    case DataType::QUANT8_ASYMM:
+    case DataType::UINT8:
+      return source<uint8_t>(index, buffer, length, io_layout);
+    case DataType::QUANT8_SYMM:
+      return source<int8_t>(index, buffer, length, io_layout);
+    default:
+      throw std::runtime_error("Not supported yet");
+  }
+}
+
+std::unique_ptr<ISink> ExecutorBase::sink(const ir::IOIndex &index, const ir::TypeInfo &type,
+                                          void *buffer, size_t length, ir::Layout io_layout)
+{
+  using ir::DataType;
+  switch (type.type())
+  {
+    case DataType::FLOAT32:
+      return sink<float>(index, buffer, length, io_layout);
+    case DataType::INT32:
+      return sink<int32_t>(index, buffer, length, io_layout);
+    case DataType::UINT32:
+      return sink<uint32_t>(index, buffer, length, io_layout);
+    case DataType::BOOL8:
+    case DataType::QUANT8_ASYMM:
+    case DataType::UINT8:
+      return sink<uint8_t>(index, buffer, length, io_layout);
+    case DataType::QUANT8_SYMM:
+      return sink<int8_t>(index, buffer, length, io_layout);
+    default:
+      throw std::runtime_error("Not supported yet");
+  }
+}
+
+void ExecutorBase::execute(const IODescription &desc)
+{
+  // For thread-safe, use mutex
+  // TODO: if all used backends on this executor are thread-safe,
+  //       do not need to use mutex (otherwise, use mutex)
+  std::lock_guard<std::mutex> lock(_mutex);
+
+  std::vector<std::unique_ptr<ISource>> sources{_graph.getInputs().size()};
+  std::vector<std::unique_ptr<ISink>> sinks{_graph.getOutputs().size()};
+
+  // Set input(s)
+  for (uint32_t n = 0; n < _graph.getInputs().size(); ++n)
+  {
+    ir::IOIndex input_index{n};
+    ir::OperandIndex index{_graph.getInputs().at(input_index)};
+
+    if (desc.inputs.at(n) == nullptr)
+    {
+      // Optional input
+      continue;
+    }
+
+    const auto operand_li = _graph.getLowerInfo()->operand.at(index).get();
+    if (operand_li->def_factors().empty())
+    {
+      // This input is not used (i.e. constant, EX. reshape's axis)
+      continue;
+    }
+
+    const auto &input = *desc.inputs.at(n);
+    sources.at(n) =
+        source(input_index, input.info.typeInfo(), input.buffer, input.size, input.layout);
+
+    auto setter = [&](::neurun::backend::operand::ITensor &tensor) { sources.at(n)->push(tensor); };
+
+    auto object = _operand_context->at(index);
+
+    object->access(setter);
+  }
+
+  executeImpl();
+
+  // Get output(s)
+  for (uint32_t n = 0; n < _graph.getOutputs().size(); ++n)
+  {
+    ir::IOIndex output_index{n};
+    // Optional output
+    if (desc.outputs.at(n) == nullptr)
+    {
+      continue;
+    }
+    const auto &output = *desc.outputs.at(n);
+    sinks.at(n) =
+        sink(output_index, output.info.typeInfo(), output.buffer, output.size, output.layout);
+
+    auto getter = [&](::neurun::backend::operand::ITensor &tensor) { sinks.at(n)->pull(tensor); };
+
+    ir::OperandIndex index{_graph.getOutputs().at(output_index)};
+    auto object = _operand_context->at(index);
+
+    object->access(getter);
+  }
+}
+
+} // namespace exec
+} // namespace neurun
diff --git a/runtime/neurun/core/src/exec/ExecutorBase.h b/runtime/neurun/core/src/exec/ExecutorBase.h
new file mode 100644
index 000000000..a93e036a5
--- /dev/null
+++ b/runtime/neurun/core/src/exec/ExecutorBase.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_EXEC_EXECUTOR_BASE_H__
+#define __NEURUN_EXEC_EXECUTOR_BASE_H__
+
+#include <mutex>
+
+#include "Source.h"
+#include "exec/ExecutionObservers.h"
+#include "Sink.h"
+#include "exec/IExecutor.h"
+#include "ir/Graph.h"
+#include "ir/LowerInfoMap.h"
+#include "backend/IConfig.h"
+#include "backend/Backend.h"
+#include "compiler/OperandContext.h"
+#include "backend/ExecTime.h"
+#include "exec/IFunction.h"
+#include "backend/ITensorManager.h"
+#include "exec/ExecutionObservee.h"
+#include <list>
+
+namespace neurun
+{
+namespace exec
+{
+
+class ExecutorBase : public IExecutor
+{
+public:
+  ExecutorBase(const ir::Graph &graph,
+               const std::shared_ptr<compiler::OperandContext> &operand_context,
+               std::unique_ptr<backend::TensorManagerSet> tensor_mgrs);
+
+  virtual ~ExecutorBase() = default;
+
+  const ir::Graph &graph() final { return _graph; }
+
+  void execute(const IODescription &desc) final;
+
+  // Used only in Dataflow and Parallel Executors
+  void setIndexedRanks(std::shared_ptr<ir::OperationIndexMap<int64_t>> ranks) final
+  {
+    _indexed_ranks = std::move(ranks);
+  };
+
+  virtual void executeImpl(void) = 0;
+
+  void addObserver(std::unique_ptr<IExecutionObserver> ref) { _subject.add(std::move(ref)); };
+
+private:
+  std::unique_ptr<ISource> source(const ir::IOIndex &index, const ir::TypeInfo &type,
+                                  const void *buffer, size_t length, ir::Layout io_layout);
+  std::unique_ptr<ISink> sink(const ir::IOIndex &index, const ir::TypeInfo &type, void *buffer,
+                              size_t length, ir::Layout io_layout);
+
+  template <typename T>
+  std::unique_ptr<ISource> source(const ir::IOIndex &index, const void *buffer, size_t length,
+                                  ir::Layout io_layout)
+  {
+    const auto operand_index = _graph.getInputs().at(index);
+    const auto &operand = _graph.operands().at(operand_index);
+
+    const auto tensor = _operand_context->at(operand_index);
+    const auto tensor_layout = tensor->layout();
+
+    if (((io_layout == ir::Layout::NHWC) && (tensor_layout == ir::Layout::NCHW)) ||
+        ((io_layout == ir::Layout::NCHW) && (tensor_layout == ir::Layout::NHWC)))
+    {
+      return nnfw::cpp14::make_unique<PermutateSource<T>>(buffer, length, operand.shape(),
+                                                          io_layout);
+    }
+    // TODO Change this to return error
+    assert(io_layout != ir::Layout::UNKNOWN ||
+           (tensor_layout != ir::Layout::NCHW && tensor_layout != ir::Layout::NCHW));
+
+    return nnfw::cpp14::make_unique<CopySource<T>>(buffer, length, operand.shape());
+  }
+
+  template <typename T>
+  std::unique_ptr<ISink> sink(const ir::IOIndex &index, void *buffer, size_t length,
+                              ir::Layout io_layout)
+  {
+    const auto operand_index = _graph.getOutputs().at(index);
+    const auto &operand = _graph.operands().at(operand_index);
+    const auto tensor = _operand_context->at(operand_index);
+    const auto tensor_layout = tensor->layout();
+
+    if (((tensor_layout == ir::Layout::NCHW) && (io_layout == ir::Layout::NHWC)) ||
+        ((tensor_layout == ir::Layout::NHWC) && (io_layout == ir::Layout::NCHW)))
+    {
+      return nnfw::cpp14::make_unique<PermutateSink<T>>(buffer, length, operand.shape(), io_layout);
+    }
+    // TODO Change this to return error
+    assert(io_layout != ir::Layout::UNKNOWN ||
+           (tensor_layout != ir::Layout::NCHW && tensor_layout != ir::Layout::NCHW));
+
+    return nnfw::cpp14::make_unique<CopySink<T>>(buffer, length, operand.shape());
+  }
+
+protected:
+  ExecutionObservee _subject;
+  std::shared_ptr<ir::OperationIndexMap<int64_t>> _indexed_ranks;
+  const ir::Graph &_graph;
+  std::shared_ptr<compiler::OperandContext> _operand_context;
+  std::unique_ptr<backend::TensorManagerSet> _tensor_mgrs;
+  std::mutex _mutex;
+};
+
+} // namespace exec
+} // namespace neurun
+
+#endif // __NEURUN_EXEC_EXECUTOR_BASE_H__
diff --git a/runtime/neurun/core/src/exec/FunctionSequence.cc b/runtime/neurun/core/src/exec/FunctionSequence.cc
new file mode 100644
index 000000000..00214fcfa
--- /dev/null
+++ b/runtime/neurun/core/src/exec/FunctionSequence.cc
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "FunctionSequence.h"
+
+namespace neurun
+{
+namespace exec
+{
+
+void FunctionSequence::run()
+{
+  for (const auto &function : _functions)
+  {
+    function->run();
+  }
+}
+
+void FunctionSequence::runSync()
+{
+  for (const auto &function : _functions)
+  {
+    function->runSync();
+  }
+}
+
+void FunctionSequence::prepare()
+{
+  for (const auto &function : _functions)
+  {
+    function->prepare();
+  }
+}
+
+void FunctionSequence::append(std::unique_ptr<IFunction> &&function)
+{
+  _functions.push_back(std::move(function));
+}
+
+void FunctionSequence::iterate(const std::function<void(IFunction &)> &fn)
+{
+  for (const auto &func : _functions)
+  {
+    fn(*func);
+  }
+}
+
+} // namespace exec
+} // namespace neurun
diff --git a/runtime/neurun/core/src/exec/FunctionSequence.h b/runtime/neurun/core/src/exec/FunctionSequence.h
new file mode 100644
index 000000000..2ba5c0b08
--- /dev/null
+++ b/runtime/neurun/core/src/exec/FunctionSequence.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_EXEC_FUNCTION_SEQUENCE_H__
+#define __NEURUN_EXEC_FUNCTION_SEQUENCE_H__
+
+#include <memory>
+#include <vector>
+#include <functional>
+
+#include "exec/IFunction.h"
+
+namespace neurun
+{
+namespace exec
+{
+
+class FunctionSequence : public IFunction
+{
+public:
+  virtual ~FunctionSequence() = default;
+
+  void run() override;
+  void runSync() override;
+  void prepare() override;
+
+  /**
+   * @brief Appends an IFunction object to the function sequence
+   *
+   * @param function IFunction object to be appended
+   */
+  void append(std::unique_ptr<IFunction> &&function);
+
+  void iterate(const std::function<void(IFunction &)> &fn);
+
+private:
+  std::vector<std::unique_ptr<IFunction>> _functions;
+};
+
+} // namespace exec
+} // namespace neurun
+
+#endif // __NEURUN_EXEC_FUNCTION_SEQUENCE_H__
diff --git a/runtime/neurun/core/src/exec/Job.cc b/runtime/neurun/core/src/exec/Job.cc
new file mode 100644
index 000000000..ba02daf30
--- /dev/null
+++ b/runtime/neurun/core/src/exec/Job.cc
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "Job.h"
+
+#include <cassert>
+
+#include "util/logging.h"
+
+namespace neurun
+{
+namespace exec
+{
+
+Job::Job(uint32_t index, IFunction *fn) : _index{index}, _fn{fn} {}
+
+void Job::run() { _fn->run(); }
+
+} // namespace exec
+} // namespace neurun
diff --git a/runtime/neurun/core/src/exec/Job.h b/runtime/neurun/core/src/exec/Job.h
new file mode 100644
index 000000000..1516b9281
--- /dev/null
+++ b/runtime/neurun/core/src/exec/Job.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_EXEC_JOB_H__
+#define __NEURUN_EXEC_JOB_H__
+
+#include <unordered_set>
+
+#include "exec/IFunction.h"
+#include "ir/Index.h"
+#include "ir/OperandIndexSequence.h"
+#include "backend/Backend.h"
+
+namespace neurun
+{
+namespace exec
+{
+
+class Job
+{
+public:
+  /**
+   * @brief Constructs a Job object
+   *
+   * @param index Operation index for this job
+   * @param fn compiled code to run this job
+   * @param inputs Input operand list
+   * @param outputs Output operand list
+   */
+  Job(uint32_t index, IFunction *fn);
+  /**
+   * @brief Execute the compiled code
+   */
+  void run();
+  /**
+   * @brief Return job index
+   *
+   * @return Job index
+   */
+  uint32_t index() const { return _index; }
+  /**
+   * @brief Return the function to be executed
+   *
+   * @return Pointer of the function
+   */
+  IFunction *fn() { return _fn; }
+
+private:
+  uint32_t _index;
+  IFunction *_fn;
+};
+
+} // namespace exec
+} // namespace neurun
+
+#endif // __NEURUN_EXEC_JOB_H__
diff --git a/runtime/neurun/core/src/exec/LinearExecutor.cc b/runtime/neurun/core/src/exec/LinearExecutor.cc
new file mode 100644
index 000000000..d41dba880
--- /dev/null
+++ b/runtime/neurun/core/src/exec/LinearExecutor.cc
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "LinearExecutor.h"
+
+namespace neurun
+{
+namespace exec
+{
+
+void LinearExecutor::executeImpl()
+{
+  _subject.notifyModelBegin(this);
+  for (auto &&code : _code)
+  {
+    const auto op_seq = code.elem.op_seq;
+    const auto backend = code.elem.lower_info->backend();
+    _subject.notifyJobBegin(this, op_seq, backend);
+    code.fn->run();
+    _subject.notifyJobEnd(this, op_seq, backend);
+  }
+  _subject.notifyModelEnd(this);
+}
+
+} // namespace exec
+} // namespace neurun
diff --git a/runtime/neurun/core/src/exec/LinearExecutor.h b/runtime/neurun/core/src/exec/LinearExecutor.h
new file mode 100644
index 000000000..baf063a12
--- /dev/null
+++ b/runtime/neurun/core/src/exec/LinearExecutor.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file  LinearExecutor.h
+ * @brief This file contains LinearExecutor class to define and run execution phase
+ */
+
+#ifndef __NEURUN_EXEC_EXECUTOR_H_
+#define __NEURUN_EXEC_EXECUTOR_H_
+
+#include "ExecutorBase.h"
+#include "compiler/Linear.h"
+#include "exec/FunctionSequence.h"
+#include "compiler/CodeWithInfo.h"
+
+namespace neurun
+{
+namespace exec
+{
+
+/**
+ * @brief Class to handle execution phase. Simple run the sequence of operations that is sorted in
+ *        topological order
+ */
+class LinearExecutor final : public ExecutorBase
+{
+public:
+  /**
+   * @brief Construct a new LinearExecutor object
+   * @param[in] plan  Execution plan generated by compiled result
+   */
+  LinearExecutor(const ir::Graph &graph,
+                 const std::shared_ptr<compiler::OperandContext> &operand_context,
+                 std::unique_ptr<backend::TensorManagerSet> tensor_mgrs,
+                 std::vector<compiler::CodeWithInfo> &&code)
+      : ExecutorBase{graph, operand_context, std::move(tensor_mgrs)}, _code{std::move(code)}
+  {
+  }
+
+public:
+  void executeImpl(void) override;
+
+private:
+  std::vector<compiler::CodeWithInfo> _code;
+};
+
+} // namespace exec
+} // namespace neurun
+
+#endif // __NEURUN_EXEC_EXECUTOR_H_
diff --git a/runtime/neurun/core/src/exec/ParallelExecutor.cc b/runtime/neurun/core/src/exec/ParallelExecutor.cc
new file mode 100644
index 000000000..c73c353d3
--- /dev/null
+++ b/runtime/neurun/core/src/exec/ParallelExecutor.cc
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ParallelExecutor.h"
+
+#include <cassert>
+
+#include "util/logging.h"
+#include "exec/IFunction.h"
+
+namespace neurun
+{
+namespace exec
+{
+
+class HookFunction : public IFunction
+{
+public:
+  HookFunction(IFunction *fn, const std::function<void()> &setup,
+               const std::function<void()> &teardown)
+      : _fn{fn}, _setup{setup}, _teardown{teardown}
+  {
+  }
+
+public:
+  void run() override
+  {
+    _setup();
+    _fn->run();
+    _teardown();
+  }
+  void runSync() override { throw("runSync is needed just for profiling in Dataflow executor"); }
+
+private:
+  IFunction *_fn;
+  std::function<void()> _setup;
+  std::function<void()> _teardown;
+};
+
+void ParallelExecutor::notify(uint32_t finished_job_id)
+{
+  std::unique_lock<std::mutex> lock{_mu_jobs};
+
+  DataflowExecutor::notify(finished_job_id);
+
+  lock.unlock();
+  _cv_jobs.notify_all();
+}
+
+ParallelExecutor::ParallelExecutor(const ir::Graph &graph,
+                                   const std::shared_ptr<compiler::OperandContext> &operand_context,
+                                   std::unique_ptr<backend::TensorManagerSet> tensor_mgrs,
+                                   CodeMap &&code_map)
+    : DataflowExecutor{graph, operand_context, std::move(tensor_mgrs), std::move(code_map)}
+{
+  VERBOSE(ParallelExecutor) << "Constructing Parallel Executor" << std::endl;
+}
+
+void ParallelExecutor::executeImpl()
+{
+  // Init scheduler
+  // TODO Consider to have distinct backend set in LowerInfoMap
+  ir::BackendSet backends;
+  for (auto &itr : _graph.getLowerInfo()->operation)
+  {
+    backends.add(itr.second->backend());
+  }
+  _scheduler = nnfw::cpp14::make_unique<ParallelScheduler>(backends);
+
+  assert(noWaitingJobs());
+
+  // Execution setup
+  _waiting_jobs.swap(_finished_jobs); // Move finished jobs to waiting jobs
+
+  for (uint32_t i = 0; i < _waiting_jobs.size(); ++i)
+  {
+    VERBOSE(ParallelExecutor) << i << ": " << _input_info[i] << std::endl;
+    if (_input_info[i] == 0)
+    {
+      emplaceToReadyJobs(i);
+    }
+  }
+  assert(!_ready_jobs.empty()); // Cannot begin if there is no initial jobs
+
+  VERBOSE(ParallelExecutor) << "INITIAL JOBS : " << _ready_jobs.size() << std::endl;
+
+  _subject.notifyModelBegin(this);
+  while (true)
+  {
+    std::unique_lock<std::mutex> lock{_mu_jobs};
+
+    if (_ready_jobs.empty())
+    {
+      _cv_jobs.wait(lock, [this] { return !_ready_jobs.empty() || noWaitingJobs(); });
+      // Check finish condition
+      if (_ready_jobs.empty() && noWaitingJobs())
+      {
+        break;
+      }
+    }
+
+    auto job = std::move(_ready_jobs.begin()->second);
+    _ready_jobs.erase(_ready_jobs.begin());
+
+    lock.unlock();
+
+    VERBOSE(ParallelExecutor) << "Assigning fn #" << job->index() << std::endl;
+
+    auto job_index = job->index();
+    auto subgraph_index = _job_to_op_seq[job_index];
+    auto op_seq = &_graph.subgraphs()->at(subgraph_index);
+    auto backend = _graph.getLowerInfo()->operation.at(subgraph_index)->backend();
+    auto setup = [&, op_seq, backend]() { _subject.notifyJobBegin(this, op_seq, backend); };
+    auto teardown = [&, job_index, op_seq, backend]() {
+      _subject.notifyJobEnd(this, op_seq, backend);
+      notify(job_index);
+    };
+
+    _scheduler->assign(nnfw::cpp14::make_unique<HookFunction>(job->fn(), setup, teardown), backend);
+    _finished_jobs[job_index] = std::move(job);
+  }
+
+  assert(noWaitingJobs());
+
+  // Wait for all the jobs done
+  _scheduler->finish();
+  _subject.notifyModelEnd(this);
+
+  // Reset input info for the next execution
+  _input_info = _initial_input_info;
+}
+
+} // namespace exec
+} // namespace neurun
diff --git a/runtime/neurun/core/src/exec/ParallelExecutor.h b/runtime/neurun/core/src/exec/ParallelExecutor.h
new file mode 100644
index 000000000..54377fd9e
--- /dev/null
+++ b/runtime/neurun/core/src/exec/ParallelExecutor.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_EXEC_PARALLEL_EXECUTOR_H__
+#define __NEURUN_EXEC_PARALLEL_EXECUTOR_H__
+
+#include <list>
+#include <queue>
+#include <unordered_map>
+
+#include "FunctionSequence.h"
+#include "Job.h"
+#include "ir/OperandIndexSequence.h"
+#include "ir/Index.h"
+#include "cpp14/memory.h"
+#include "exec/DataflowExecutor.h"
+#include "ParallelScheduler.h"
+
+namespace neurun
+{
+namespace exec
+{
+
+/**
+ * @brief Class to execute Graph in parallel
+ */
+class ParallelExecutor : public DataflowExecutor
+{
+protected:
+  void notify(uint32_t finished_job_id) override;
+
+public:
+  /**
+   * @brief Constructs a ParallelExecutor object
+   *
+   * @param graph Graph object
+   * @param operand_context (Only for input/output operand data access)
+   * @param code_map Compiled code map
+   * @param ranks Operation ranks for ordering execution
+   */
+  ParallelExecutor(const ir::Graph &graph,
+                   const std::shared_ptr<compiler::OperandContext> &operand_context,
+                   std::unique_ptr<backend::TensorManagerSet> tensor_mgrs, CodeMap &&code_map);
+
+  void executeImpl() override;
+
+private:
+  std::condition_variable _cv_jobs;
+  std::mutex _mu_jobs;
+  std::unique_ptr<ParallelScheduler> _scheduler;
+};
+
+} // namespace exec
+} // namespace neurun
+
+#endif // __NEURUN_EXEC_PARALLEL_EXECUTOR_H__
diff --git a/runtime/neurun/core/src/exec/ParallelScheduler.cc b/runtime/neurun/core/src/exec/ParallelScheduler.cc
new file mode 100644
index 000000000..5f9e9e013
--- /dev/null
+++ b/runtime/neurun/core/src/exec/ParallelScheduler.cc
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ParallelScheduler.h"
+
+#include <cassert>
+
+#include "cpp14/memory.h"
+#include "util/logging.h"
+
+namespace neurun
+{
+namespace exec
+{
+
+ParallelScheduler::ParallelScheduler(const ir::BackendSet &backends)
+{
+  assert(!backends.empty());
+
+  for (auto backend : backends)
+  {
+    _thread_pools[backend] = nnfw::cpp14::make_unique<ThreadPool>();
+  }
+}
+
+void ParallelScheduler::assign(std::unique_ptr<IFunction> &&fn, const backend::Backend *backend)
+{
+  assert(!_thread_pools.empty());
+
+  _thread_pools.at(backend)->enqueue(std::move(fn));
+}
+
+void ParallelScheduler::finish()
+{
+  for (auto &itr : _thread_pools)
+  {
+    itr.second->finish();
+  }
+}
+
+} // namespace exec
+} // namespace neurun
diff --git a/runtime/neurun/core/src/exec/ParallelScheduler.h b/runtime/neurun/core/src/exec/ParallelScheduler.h
new file mode 100644
index 000000000..af1103750
--- /dev/null
+++ b/runtime/neurun/core/src/exec/ParallelScheduler.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_EXEC_PARALLEL_SCHEDULER_H__
+#define __NEURUN_EXEC_PARALLEL_SCHEDULER_H__
+
+#include <unordered_map>
+#include <memory>
+
+#include "exec/IFunction.h"
+#include "ir/BackendSet.h"
+#include "ThreadPool.h"
+
+namespace neurun
+{
+namespace exec
+{
+
+class ParallelScheduler
+{
+public:
+  /**
+   * @brief Constructs ParallelScheduler object
+   *
+   * @param backends Backend set
+   */
+  ParallelScheduler(const ir::BackendSet &backends);
+  /**
+   * @brief Assign a task to the given backend
+   *
+   * @param[in] fn Function to be assigned
+   * @param[in] fn Target backend
+   */
+  void assign(std::unique_ptr<IFunction> &&fn, const backend::Backend *backend);
+  /**
+   * @brief Block until all jobs are finished
+   */
+  void finish();
+
+private:
+  std::unordered_map<const backend::Backend *, std::unique_ptr<ThreadPool>> _thread_pools;
+};
+
+} // namespace exec
+} // namespace neurun
+
+#endif // __NEURUN_EXEC_PARALLEL_SCHEDULER_H__
diff --git a/runtime/neurun/core/src/exec/Sink.h b/runtime/neurun/core/src/exec/Sink.h
new file mode 100644
index 000000000..bb2a6c58a
--- /dev/null
+++ b/runtime/neurun/core/src/exec/Sink.h
@@ -0,0 +1,205 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_EXEC_SINK_H__
+#define __NEURUN_EXEC_SINK_H__
+
+#include <cassert>
+
+#include "cpp14/memory.h"
+#include "util/feature/nchw/Reader.h"
+#include "util/feature/nchw/View.h"
+#include "util/feature/nhwc/Reader.h"
+#include "util/feature/nhwc/View.h"
+#include "util/Utils.h"
+#include <misc/feature/IndexIterator.h>
+
+namespace neurun
+{
+namespace exec
+{
+struct ISink
+{
+  virtual ~ISink() = default;
+
+  virtual void pull(::neurun::backend::operand::ITensor &tensor) const = 0;
+};
+
+// Create second lever inheritance: the first lever is used as a reference type in use-case places
+template <typename T> class ITemplSink : public ISink
+{
+public:
+  ITemplSink(void *output_buffer, const size_t &output_size, const ir::Shape &shape,
+             const bool copy, ir::Layout io_layout)
+      : _output_buffer{reinterpret_cast<T *>(output_buffer)}, _output_size{output_size},
+        _shape{shape}, _copy{copy}, _io_layout{io_layout}
+  {
+  }
+
+protected:
+  void pullUnif(neurun::backend::operand::ITensor &tensor) const
+  {
+    assert(((_io_layout == ir::Layout::NHWC && tensor.layout() == ir::Layout::NCHW) ||
+            (_io_layout == ir::Layout::NCHW && tensor.layout() == ir::Layout::NHWC)) ||
+           _copy);
+    auto input_buffer = tensor.buffer();
+    auto rank = _shape.rank();
+
+    if (!tensor.has_padding() && rank < 4 + _copy)
+    {
+      memcpy(_output_buffer, input_buffer, _output_size);
+      return;
+    }
+
+    switch (rank)
+    {
+      case 0:
+      case 1:
+      {
+        memcpy(_output_buffer, input_buffer, _output_size);
+        break;
+      }
+      case 2:
+      {
+        const int32_t copy_len = _shape.dim(1);
+
+        for (auto i = 0; i < _shape.dim(0); ++i)
+        {
+          neurun::util::Coordinates coords{i, 0};
+          memcpy(_output_buffer + i * copy_len, input_buffer + tensor.calcOffset(coords),
+                 copy_len * sizeof(T));
+        }
+        break;
+      }
+      case 3:
+      {
+        const int32_t dim1 = _shape.dim(1);
+        const int32_t dim2 = _shape.dim(2);
+
+        for (auto i = 0; i < _shape.dim(0); ++i)
+        {
+          for (auto j = 0; j < _shape.dim(1); ++j)
+          {
+            neurun::util::Coordinates coords{i, j, 0};
+            memcpy(_output_buffer + i * dim1 * dim2 + j * dim2,
+                   input_buffer + tensor.calcOffset(coords), dim2 * sizeof(T));
+          }
+        }
+        break;
+      }
+      case 4:
+      {
+        if (_copy)
+        {
+          const int32_t dim1 = _shape.dim(1);
+          const int32_t dim2 = _shape.dim(2);
+          const int32_t dim3 = _shape.dim(3);
+
+          for (auto i = 0; i < _shape.dim(0); ++i)
+          {
+            for (auto j = 0; j < _shape.dim(1); ++j)
+            {
+              for (auto k = 0; k < _shape.dim(2); ++k)
+              {
+                neurun::util::Coordinates coords{i, j, k, 0};
+                memcpy(_output_buffer + i * dim1 * dim2 * dim3 + j * dim2 * dim3 + k * dim3,
+                       input_buffer + tensor.calcOffset(coords), dim3 * sizeof(T));
+              }
+            }
+          }
+        }
+        else
+        {
+          const auto shape = _shape.asFeature(_io_layout);
+
+          if (_io_layout == ir::Layout::NHWC)
+          {
+            const util::feature::nchw::Reader<T> from(&tensor);
+            util::feature::nhwc::View<T> into(shape, _output_buffer, _output_size);
+            ::nnfw::misc::feature::iterate(shape)
+                << [&](uint32_t batch, uint32_t ch, uint32_t row, uint32_t col) {
+                     const auto value = from.at(batch, ch, row, col);
+                     into.at(batch, row, col, ch) = value;
+                   };
+          }
+          else if (_io_layout == ir::Layout::NCHW)
+          {
+            const util::feature::nhwc::Reader<T> from(&tensor);
+            util::feature::nchw::View<T> into(shape, _output_buffer, _output_size);
+            ::nnfw::misc::feature::iterate(shape)
+                << [&](uint32_t batch, uint32_t ch, uint32_t row, uint32_t col) {
+                     const auto value = from.at(batch, row, col, ch);
+                     into.at(batch, ch, row, col) = value;
+                   };
+          }
+          else
+          {
+            throw std::runtime_error("Wrong Layout");
+          }
+        }
+        break;
+      }
+      default:
+        throw std::runtime_error("NYI");
+        break;
+    }
+  }
+
+private:
+  T *_output_buffer;
+  const size_t _output_size;
+  const ir::Shape _shape;
+  const bool _copy;
+  const ir::Layout _io_layout;
+};
+
+template <typename T> class PermutateSink final : public ITemplSink<T>
+{
+public:
+  PermutateSink(void *output_buffer, const size_t &output_size, const ir::Shape &shape,
+                ir::Layout io_layout)
+      : ITemplSink<T>(output_buffer, output_size, shape, false, io_layout)
+  {
+  }
+
+public:
+  void pull(neurun::backend::operand::ITensor &tensor) const override
+  {
+    ITemplSink<T>::pullUnif(tensor);
+  }
+};
+
+// Only supports NHWC format front-end(NNAPI) now
+template <typename T> class CopySink final : public ITemplSink<T>
+{
+public:
+  CopySink(void *output_buffer, const size_t &output_size, const ir::Shape &shape,
+           ir::Layout io_layout = ir::Layout::UNKNOWN)
+      : ITemplSink<T>(output_buffer, output_size, shape, true, io_layout)
+  {
+  }
+
+public:
+  void pull(neurun::backend::operand::ITensor &tensor) const override
+  {
+    ITemplSink<T>::pullUnif(tensor);
+  }
+};
+
+} // namespace exec
+} // namespace neurun
+
+#endif // __NEURUN_EXEC_SINK_H__
diff --git a/runtime/neurun/core/src/exec/Source.h b/runtime/neurun/core/src/exec/Source.h
new file mode 100644
index 000000000..fd52dd546
--- /dev/null
+++ b/runtime/neurun/core/src/exec/Source.h
@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_EXEC_SOURCE_H__
+#define __NEURUN_EXEC_SOURCE_H__
+
+#include <cassert>
+
+#include "cpp14/memory.h"
+#include "util/feature/nchw/Reader.h"
+#include "util/feature/nchw/View.h"
+#include "util/feature/nhwc/Reader.h"
+#include "util/feature/nhwc/View.h"
+#include "util/Utils.h"
+#include <misc/feature/IndexIterator.h>
+#include <ir/Layout.h>
+#include "ir/Shape.h"
+
+namespace neurun
+{
+namespace exec
+{
+
+struct ISource
+{
+  virtual ~ISource() = default;
+
+  virtual void push(::neurun::backend::operand::ITensor &tensor) const = 0;
+};
+
+// Create second lever inheritance: the first lever is used as a reference type in use-case places
+template <typename T> class ITemplSource : public ISource
+{
+public:
+  ITemplSource(const void *input_buffer, const size_t &input_size, const ir::Shape &shape,
+               const bool copy, ir::Layout io_layout)
+      : _input_buffer{reinterpret_cast<const T *>(input_buffer)}, _input_size{input_size},
+        _shape{shape}, _copy(copy), _io_layout{io_layout}
+  {
+  }
+
+  virtual void push(::neurun::backend::operand::ITensor &tensor) const = 0;
+
+protected:
+  void pushUnif(neurun::backend::operand::ITensor &tensor) const
+  {
+    assert(((_io_layout == ir::Layout::NHWC && tensor.layout() == ir::Layout::NCHW) ||
+            (_io_layout == ir::Layout::NCHW && tensor.layout() == ir::Layout::NHWC)) ||
+           _copy);
+    auto output_buffer = tensor.buffer();
+    auto rank = _shape.rank();
+
+    if (!tensor.has_padding() && rank < 4 + _copy)
+    {
+      memcpy(output_buffer, _input_buffer, _input_size);
+      return;
+    }
+
+    switch (rank)
+    {
+      case 0:
+      case 1:
+      {
+        memcpy(output_buffer, _input_buffer, _input_size);
+        break;
+      }
+      case 2:
+      {
+        const int32_t copy_len = _shape.dim(1);
+
+        for (auto i = 0; i < _shape.dim(0); ++i)
+        {
+          neurun::util::Coordinates coords{i, 0};
+          memcpy(output_buffer + tensor.calcOffset(coords), _input_buffer + i * copy_len,
+                 copy_len * sizeof(T));
+        }
+        break;
+      }
+      case 3:
+      {
+        const int32_t dim1 = _shape.dim(1);
+        const int32_t dim2 = _shape.dim(2);
+
+        for (auto i = 0; i < _shape.dim(0); ++i)
+        {
+          for (auto j = 0; j < _shape.dim(1); ++j)
+          {
+            neurun::util::Coordinates coords{i, j, 0};
+            memcpy(output_buffer + tensor.calcOffset(coords),
+                   _input_buffer + i * dim1 * dim2 + j * dim2, dim2 * sizeof(T));
+          }
+        }
+        break;
+      }
+      case 4:
+      {
+        if (_copy)
+        {
+          const int32_t dim1 = _shape.dim(1);
+          const int32_t dim2 = _shape.dim(2);
+          const int32_t dim3 = _shape.dim(3);
+          for (auto i = 0; i < _shape.dim(0); ++i)
+          {
+            for (auto j = 0; j < _shape.dim(1); ++j)
+            {
+              for (auto k = 0; k < _shape.dim(2); ++k)
+              {
+                neurun::util::Coordinates coords{i, j, k, 0};
+                memcpy(output_buffer + tensor.calcOffset(coords),
+                       _input_buffer + i * dim1 * dim2 * dim3 + j * dim2 * dim3 + k * dim3,
+                       dim3 * sizeof(T));
+              }
+            }
+          }
+        }
+        else
+        {
+          const auto shape = _shape.asFeature(_io_layout);
+
+          if (_io_layout == ir::Layout::NCHW)
+          {
+            const util::feature::nchw::Reader<T> from(shape, _input_buffer, _input_size);
+            util::feature::nhwc::View<T> into(&tensor);
+            ::nnfw::misc::feature::iterate(shape)
+                << [&](uint32_t batch, uint32_t ch, uint32_t row, uint32_t col) {
+                     const auto value = from.at(batch, ch, row, col);
+                     into.at(batch, row, col, ch) = value;
+                   };
+          }
+          else if (_io_layout == ir::Layout::NHWC)
+          {
+            const util::feature::nhwc::Reader<T> from(shape, _input_buffer, _input_size);
+            util::feature::nchw::View<T> into(&tensor);
+            ::nnfw::misc::feature::iterate(shape)
+                << [&](uint32_t batch, uint32_t ch, uint32_t row, uint32_t col) {
+                     const auto value = from.at(batch, row, col, ch);
+                     into.at(batch, ch, row, col) = value;
+                   };
+          }
+          else
+          {
+            throw std::runtime_error("Wrong Layout");
+          }
+        }
+
+        break;
+      }
+      default:
+        throw std::runtime_error("NYI");
+        break;
+    }
+  }
+
+private:
+  const T *_input_buffer;
+  const size_t _input_size;
+  const ir::Shape _shape;
+  const bool _copy;
+  const ir::Layout _io_layout;
+};
+
+template <typename T> class PermutateSource final : public ITemplSource<T>
+{
+public:
+  PermutateSource(const void *input_buffer, const size_t &input_size, const ir::Shape &shape,
+                  ir::Layout io_layout)
+      : ITemplSource<T>(input_buffer, input_size, shape, false, io_layout)
+  {
+  }
+
+public:
+  void push(neurun::backend::operand::ITensor &tensor) const override
+  {
+    // do NHWC_TO_NCHW or NCHW_TO_NHWC permutation
+    ITemplSource<T>::pushUnif(tensor);
+  }
+};
+
+template <typename T> class CopySource final : public ITemplSource<T>
+{
+public:
+  CopySource(const void *input_buffer, const size_t &input_size, const ir::Shape &shape,
+             ir::Layout io_layout = ir::Layout::UNKNOWN)
+      : ITemplSource<T>(input_buffer, input_size, shape, true, io_layout)
+  {
+  }
+
+public:
+  void push(neurun::backend::operand::ITensor &tensor) const override
+  {
+    ITemplSource<T>::pushUnif(tensor);
+  }
+};
+
+} // namespace exec
+} // namespace neurun
+
+#endif // __NEURUN_EXEC_SOURCE_H__
diff --git a/runtime/neurun/core/src/exec/ThreadPool.cc b/runtime/neurun/core/src/exec/ThreadPool.cc
new file mode 100644
index 000000000..d8c706e30
--- /dev/null
+++ b/runtime/neurun/core/src/exec/ThreadPool.cc
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ThreadPool.h"
+
+#include <cassert>
+
+namespace neurun
+{
+namespace exec
+{
+
+ThreadPool::ThreadPool(uint32_t num_threads)
+{
+  assert(num_threads >= 1);
+
+  for (uint32_t i = 0; i < num_threads; i++)
+  {
+    _threads.emplace_back(std::ref(_worker));
+  }
+}
+
+ThreadPool::~ThreadPool()
+{
+  if (!_threads.empty())
+  {
+    _worker.terminate();
+    join();
+  }
+}
+
+void ThreadPool::enqueue(std::unique_ptr<IFunction> &&fn) { _worker.enqueue(std::move(fn)); }
+
+uint32_t ThreadPool::numJobsInQueue() { return _worker.numJobsInQueue(); }
+
+void ThreadPool::join()
+{
+  for (auto &thread : _threads)
+  {
+    thread.join();
+  }
+  _threads.clear();
+}
+
+void ThreadPool::finish()
+{
+  _worker.finish();
+  join();
+}
+
+} // namespace exec
+} // namespace neurun
diff --git a/runtime/neurun/core/src/exec/ThreadPool.h b/runtime/neurun/core/src/exec/ThreadPool.h
new file mode 100644
index 000000000..a1a027617
--- /dev/null
+++ b/runtime/neurun/core/src/exec/ThreadPool.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_EXEC_THREAD_POOL_H__
+#define __NEURUN_EXEC_THREAD_POOL_H__
+
+#include <thread>
+#include <memory>
+#include <vector>
+
+#include "WorkQueue.h"
+
+namespace neurun
+{
+namespace exec
+{
+
+class ThreadPool
+{
+public:
+  /**
+   * @brief Coustruct ThreadPool object
+   *
+   * @param num_threads Number of threads
+   */
+  ThreadPool(uint32_t num_threads = 1);
+  /**
+   * @brief Destroy ThreadPool object
+   */
+  ~ThreadPool();
+  /**
+   * @brief Enqueue a function
+   *
+   * @param fn A function to be queued
+   */
+  void enqueue(std::unique_ptr<IFunction> &&fn);
+  /**
+   * @brief Get number of jobs in worker's queue
+   *
+   * @return Number of jobs
+   */
+  uint32_t numJobsInQueue();
+
+  /**
+   * @brief Block until all jobs are finished
+   */
+  void finish();
+
+private:
+  void join();
+
+private:
+  WorkQueue _worker;
+  std::vector<std::thread> _threads;
+};
+
+} // namespace exec
+} // namespace neurun
+
+#endif // __NEURUN_EXEC_THREAD_POOL_H__
diff --git a/runtime/neurun/core/src/exec/WorkQueue.cc b/runtime/neurun/core/src/exec/WorkQueue.cc
new file mode 100644
index 000000000..6712554ac
--- /dev/null
+++ b/runtime/neurun/core/src/exec/WorkQueue.cc
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "WorkQueue.h"
+
+#include <cassert>
+
+namespace neurun
+{
+namespace exec
+{
+
+WorkQueue::~WorkQueue()
+{
+  {
+    std::unique_lock<std::mutex> lock(_mu);
+    _state = State::FORCE_FINISHING;
+  }
+  _cv.notify_all();
+}
+
+void WorkQueue::operator()()
+{
+  while (true)
+  {
+    std::unique_ptr<IFunction> fn = nullptr;
+
+    {
+      std::unique_lock<std::mutex> lock{_mu};
+      _cv.wait(lock, [this] {
+        return (_state == State::FORCE_FINISHING) || (_state == State::FINISHING) ||
+               (_state == State::ONLINE && !_functions.empty());
+      });
+
+      if (_state == State::FORCE_FINISHING)
+      {
+        assert(_functions.empty() && "Terminating with unfinished jobs");
+        return;
+      }
+      else if (_state == State::FINISHING && _functions.empty())
+      {
+        return;
+      }
+      else
+      {
+        assert(((_state == State::FINISHING) || (_state == State::ONLINE)) && !_functions.empty());
+        fn = std::move(_functions.front());
+        _functions.pop();
+      }
+    }
+
+    assert(fn);
+    fn->run();
+  }
+}
+
+void WorkQueue::enqueue(std::unique_ptr<IFunction> &&fn)
+{
+  {
+    std::unique_lock<std::mutex> lock{_mu};
+    _functions.emplace(std::move(fn));
+  }
+  _cv.notify_one();
+}
+
+void WorkQueue::terminate()
+{
+  {
+    std::unique_lock<std::mutex> lock{_mu};
+    _state = State::FORCE_FINISHING;
+  }
+  _cv.notify_all();
+}
+
+void WorkQueue::finish()
+{
+  {
+    std::unique_lock<std::mutex> lock{_mu};
+    _state = State::FINISHING;
+  }
+  _cv.notify_all();
+}
+
+uint32_t WorkQueue::numJobsInQueue()
+{
+  std::unique_lock<std::mutex> lock{_mu};
+  return _functions.size();
+}
+
+} // namespace exec
+} // namespace neurun
diff --git a/runtime/neurun/core/src/exec/WorkQueue.h b/runtime/neurun/core/src/exec/WorkQueue.h
new file mode 100644
index 000000000..cdbadfb8f
--- /dev/null
+++ b/runtime/neurun/core/src/exec/WorkQueue.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_EXEC_WORK_QUEUE_H__
+#define __NEURUN_EXEC_WORK_QUEUE_H__
+
+#include <condition_variable>
+#include <memory>
+#include <mutex>
+#include <queue>
+
+#include "exec/IFunction.h"
+
+namespace neurun
+{
+namespace exec
+{
+
+class WorkQueue
+{
+public:
+  enum class State
+  {
+    ONLINE,
+    FINISHING,
+    FORCE_FINISHING
+  };
+
+public:
+  /**
+   * @brief Create WorkQueue object
+   */
+  WorkQueue() = default;
+  /**
+   * @brief Destroy WorkQueue object
+   */
+  ~WorkQueue();
+  /**
+   * @brief Thread entry function
+   */
+  void operator()();
+  /**
+   * @brief Push the given Task to the job queue
+   *
+   * @param fn Function to be executed(a job)
+   */
+  void enqueue(std::unique_ptr<IFunction> &&fn);
+  /**
+   * @brief Flag as terminating so all the worker threads can terminate
+   */
+  void terminate();
+  /**
+   * @brief Flag as terminating so all the worker threads can terminate
+   */
+  void finish();
+  /**
+   * @brief Check if it has pending jobs. Even if this returns fals, WorkQueue threads may be still
+   * running
+   *
+   * @return true if the job queue not empty otherwise false
+   */
+  uint32_t numJobsInQueue();
+
+private:
+  State _state{State::ONLINE};
+  std::queue<std::unique_ptr<IFunction>> _functions;
+  std::mutex _mu;
+  std::condition_variable _cv;
+};
+
+} // namespace exec
+} // namespace neurun
+
+#endif // __NEURUN_EXEC_WORK_QUEUE_H__
diff --git a/runtime/neurun/core/src/exec/interp/Buffer.h b/runtime/neurun/core/src/exec/interp/Buffer.h
new file mode 100644
index 000000000..d60b59a2f
--- /dev/null
+++ b/runtime/neurun/core/src/exec/interp/Buffer.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file  Buffer.h
+ * @brief This file contains Buffer interface and InternalBuffer, ExternalBuffer class
+ */
+#ifndef __NEURUN_EXEC_INTERP_BUFFER_H__
+#define __NEURUN_EXEC_INTERP_BUFFER_H__
+
+#include <cpp14/memory.h>
+
+#include "ir/Data.h"
+
+namespace neurun
+{
+namespace exec
+{
+namespace interp
+{
+
+/**
+ * @brief Interface for writable data area
+ */
+class Buffer : public ir::Data
+{
+public:
+  /**
+   * @brief   Return writable pointer for data area
+   * @return  Writable pointer
+   */
+  virtual uint8_t *baseWritable(void) const = 0;
+};
+
+/**
+ * @brief Class for internally allocated data area
+ */
+class InternalBuffer final : public Buffer
+{
+public:
+  InternalBuffer(size_t size) : _base{nnfw::cpp14::make_unique<uint8_t[]>(size)}, _size{size}
+  {
+    // DO NOTHING
+  }
+
+public:
+  size_t size(void) const override { return _size; }
+  const uint8_t *base(void) const override { return _base.get(); }
+  uint8_t *baseWritable(void) const override { return _base.get(); }
+
+private:
+  std::unique_ptr<uint8_t[]> _base;
+  size_t _size;
+};
+
+/**
+ * @brief Class for data area from outside
+ */
+class ExternalBuffer final : public Buffer
+{
+public:
+  ExternalBuffer(uint8_t *base, size_t size) : _base{base}, _size{size}
+  {
+    // DO NOTHING
+  }
+
+public:
+  size_t size(void) const override { return _size; }
+  const uint8_t *base(void) const override { return _base; }
+  uint8_t *baseWritable(void) const override { return _base; }
+
+private:
+  uint8_t *_base;
+  size_t _size;
+};
+
+} // namespace interp
+} // namespace exec
+} // namespace neurun
+
+#endif // __NEURUN_EXEC_INTERP_BUFFER_H__
diff --git a/runtime/neurun/core/src/exec/interp/ExecEnv.h b/runtime/neurun/core/src/exec/interp/ExecEnv.h
new file mode 100644
index 000000000..0f7d45e2a
--- /dev/null
+++ b/runtime/neurun/core/src/exec/interp/ExecEnv.h
@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file  ExecEnv.h
+ * @brief This file contains ExecEnv to access interpreter tensor and execution status
+ */
+#ifndef __NEURUN_EXEC_INTERP_EXEC_ENV_H_
+#define __NEURUN_EXEC_INTERP_EXEC_ENV_H_
+
+#include <unordered_set>
+
+#include "ir/Graph.h"
+#include "Tensor.h"
+
+namespace neurun
+{
+namespace exec
+{
+namespace interp
+{
+
+/**
+ * @brief Class to gather interpreter execution environment
+ *        Each interpreter instance own execution environment
+ */
+class ExecEnv
+{
+public:
+  /**
+   * @brief Construct a new Exec Env object (deleted)
+   */
+  ExecEnv(void) = delete;
+  /**
+   * @brief Construct a new ExecEnv object
+   * @param[in] graph Graph to execute by interpreter
+   */
+  explicit ExecEnv(const ir::Graph &graph) : _graph(graph)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief   Return graph to execute
+   * @return  Graph
+   */
+  const ir::Graph &graph(void) const { return _graph; }
+  /**
+   * @brief     Assign tensor to environment which have allocated or assigned buffer
+   * @param[in] index   Tensor index
+   * @param[in] tensor  Tensor
+   */
+  void assignTensor(const ir::OperandIndex index, std::shared_ptr<ITensor> tensor)
+  {
+    assert(tensor->bufferRO() != nullptr);
+    _tensors.emplace(index, tensor);
+  }
+
+  /**
+   * @brief     Return tensor pointer in environment
+   * @param[in] index Tensor index
+   * @return    Tensor pointer
+   */
+  const ITensor *tensorAt(const ir::OperandIndex index) const { return _tensors.at(index).get(); }
+
+  /**
+   * @brief     Check environment contains tensor
+   * @param[in] index Tensor index
+   * @return    @c true if environment contain tensor, otherwise @c false
+   */
+  bool contains(const ir::OperandIndex index) const
+  {
+    return (_tensors.find(index) != _tensors.end());
+  }
+
+  /**
+   * @brief     Allocate tensor using operand info
+   * @param[in] index     Tensor index
+   * @param[in] info      Operand info
+   * @note      If already allocated, just return
+   * @TODO      More smart allocation policy
+   */
+  void allocateIfNeeded(const ir::OperandIndex index, const ir::OperandInfo &info)
+  {
+    // already allocated, or constant
+    if (contains(index))
+    {
+      return;
+    }
+
+    auto tensor = std::make_shared<Tensor>(info);
+    tensor->setBuffer(std::make_shared<InternalBuffer>(tensor->total_size()));
+    assignTensor(index, tensor);
+    _buffers.insert(index);
+  }
+
+  /**
+   * @brief     Allocate read-only tensor and share data with other tensor
+   * @param[in] index           Tensor index
+   * @param[in] info            Operand info
+   * @param[in] index_to_share  Tensor index that have data to share
+   */
+  void allocateAndShareIfNeeded(const ir::OperandIndex index, const ir::OperandInfo &info,
+                                const ir::OperandIndex index_to_share)
+  {
+    if (!contains(index_to_share))
+    {
+      throw std::runtime_error{"Cannot find tensor to share data"};
+    }
+
+    // already allocated
+    if (contains(index))
+    {
+      return;
+    }
+    else
+    {
+      auto tensor = std::make_shared<ROTensor>(info);
+      tensor->setData(tensorAt(index_to_share)->shareData());
+      assignTensor(index, tensor);
+      _buffers.insert(index);
+    }
+  }
+
+  /**
+   * @brief     Free buffer if allocated by allocateIfNeed
+   * @param[in] index Tensor index
+   * @note      If allocated by outside, just return
+   */
+  void freeIfAllocated(const ir::OperandIndex index)
+  {
+    if (_buffers.find(index) != _buffers.end())
+    {
+      _tensors.at(index)->releaseData();
+    }
+  }
+
+private:
+  const ir::Graph &_graph;
+  // Tensor map to use in interpreter
+  // It should map tensors that have allocated or assigned buffer pointer
+  std::unordered_map<ir::OperandIndex, std::shared_ptr<ITensor>> _tensors;
+  // Tensors allocated by allocateIfNeed (buffer)
+  std::unordered_set<ir::OperandIndex> _buffers;
+};
+
+} // namespace interp
+} // namespace exec
+} // namespace neurun
+
+#endif // __NEURUN_EXEC_INTERP_EXEC_ENV_H_
diff --git a/runtime/neurun/core/src/exec/interp/ExecManager.cc b/runtime/neurun/core/src/exec/interp/ExecManager.cc
new file mode 100644
index 000000000..92f182c06
--- /dev/null
+++ b/runtime/neurun/core/src/exec/interp/ExecManager.cc
@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ExecManager.h"
+#include "ExecEnv.h"
+#include "Interpreter.h"
+
+#include "util/logging.h"
+
+#include <cpp14/memory.h>
+
+namespace neurun
+{
+namespace exec
+{
+namespace interp
+{
+
+void ExecManager::execute(const IODescription &desc)
+{
+  /************************************************************************
+   * Prepare execution model (submodel)
+     It may execute divided model
+     but now consider model inference is done at interpreter
+   ***********************************************************************/
+  ir::OperandIndexMap<std::shared_ptr<ITensor>> tensor_map;
+
+  for (uint32_t n = 0; n < _graph.getInputs().size(); n++)
+  {
+    ir::IOIndex index{n};
+    const auto input_index = _graph.getInputs().at(index);
+    const auto &input = *desc.inputs.at(n);
+
+    auto input_tensor = std::make_shared<ROTensor>(input.info);
+    input_tensor->setData(std::make_shared<const ir::ExternalData>(
+        reinterpret_cast<const uint8_t *>(input.buffer), input.size));
+    tensor_map[input_index] = input_tensor;
+  }
+
+  for (uint32_t n = 0; n < _graph.getOutputs().size(); n++)
+  {
+    ir::IOIndex index{n};
+    const auto output_index = _graph.getOutputs().at(index);
+    const auto &output = *desc.outputs.at(n);
+
+    auto output_tensor = std::make_shared<Tensor>(output.info);
+    output_tensor->setBuffer(
+        std::make_shared<ExternalBuffer>(reinterpret_cast<uint8_t *>(output.buffer), output.size));
+    tensor_map[output_index] = output_tensor;
+  }
+
+  /************************************************************************
+   * Prepare execution environment
+     Execution environment will be assigned to invoked interpreter instance
+   ***********************************************************************/
+
+  std::unique_ptr<ExecEnv> interp_env = nnfw::cpp14::make_unique<ExecEnv>(_graph);
+
+  // Assign input tensor into interpreter execution environment
+  for (auto index : _graph.getInputs())
+  {
+    if (tensor_map.find(index) != tensor_map.end())
+    {
+      VERBOSE(INTERPRETER) << "Assign input tensor. operand index:" << index.value() << std::endl;
+      interp_env->assignTensor(index, tensor_map.at(index));
+    }
+  }
+
+  // Assign output tensor into interpreter execution environment
+  for (auto index : _graph.getOutputs())
+  {
+    if (tensor_map.find(index) != tensor_map.end())
+    {
+      VERBOSE(INTERPRETER) << "Assign output tensor. operand index: " << index.value() << std::endl;
+      interp_env->assignTensor(index, tensor_map.at(index));
+    }
+  }
+
+  // Allocate constant tensor
+  _graph.operands().iterate([&](const ir::OperandIndex &ind, const ir::Operand &obj) {
+    if (obj.isConstant())
+    {
+      VERBOSE(INTERPRETER) << "Allocate and assign constant tensor. operand index:" << ind.value()
+                           << std::endl;
+
+      auto const_tensor = std::make_shared<ROTensor>(obj.info());
+      // Assume that interpreter's tensor layout is same with model (NHWC)
+      const_tensor->setData(
+          std::make_shared<ir::ExternalData>(obj.data().base(), obj.info().total_size()));
+      interp_env->assignTensor(ind, const_tensor);
+    }
+  });
+
+  /*****************************************************************************
+   * Invoke interpreter
+   ****************************************************************************/
+
+  Interpreter interp(std::move(interp_env));
+  interp.run();
+
+  /*****************************************************************************
+   * Invoked interpreter run is finished
+   ****************************************************************************/
+
+  // If interpreter execute submodel
+  //  1. Get tensor output of submodel into tensor_map to save result
+  //  2. Generate new ExecEnv for next interpretation
+}
+
+} // namespace interp
+} // namespace exec
+} // namespace neurun
diff --git a/runtime/neurun/core/src/exec/interp/ExecManager.h b/runtime/neurun/core/src/exec/interp/ExecManager.h
new file mode 100644
index 000000000..f952abf02
--- /dev/null
+++ b/runtime/neurun/core/src/exec/interp/ExecManager.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file  ExecManager.h
+ * @brief This file contains ExecManager class\n
+ *        to manage interpreter execution and environment
+ */
+#ifndef __NEURUN_EXEC_INTERP_EXEC_MANAGER_H_
+#define __NEURUN_EXEC_INTERP_EXEC_MANAGER_H_
+
+#include "ir/Graph.h"
+#include "exec/IExecutor.h"
+#include "Tensor.h"
+
+namespace neurun
+{
+namespace exec
+{
+namespace interp
+{
+
+/**
+ * @brief Class to execute model using interpreter
+ */
+class ExecManager final : public IExecutor
+{
+public:
+  explicit ExecManager(const ir::Graph &graph) : _graph(graph)
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief   Return graph object
+   * @return  Graph object
+   */
+  const ir::Graph &graph() final { return _graph; }
+  void setIndexedRanks(std::shared_ptr<ir::OperationIndexMap<int64_t>>) override{
+      // Not implemented
+  };
+  /**
+   * @brief  Start execution
+   * @note   It should be called after setting input and output buffer
+   */
+  void execute(const IODescription &desc) final;
+
+private:
+  const ir::Graph &_graph;
+  ir::OperandIndexMap<std::shared_ptr<ITensor>> _tensor_map;
+};
+
+} // namespace interp
+} // namespace exec
+} // namespace neurun
+
+#endif // __NEURUN_EXEC_INTERP_EXEC_MANAGER_H_
diff --git a/runtime/neurun/core/src/exec/interp/Interpreter.cc b/runtime/neurun/core/src/exec/interp/Interpreter.cc
new file mode 100644
index 000000000..8373419f6
--- /dev/null
+++ b/runtime/neurun/core/src/exec/interp/Interpreter.cc
@@ -0,0 +1,210 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "Interpreter.h"
+
+#include <stack>
+#include <unordered_set>
+
+#include "Registration.h"
+
+#include "ir/OperandIndexMap.h"
+#include "util/logging.h"
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace exec
+{
+namespace interp
+{
+
+// TODO more structured execution kernel implementation
+// TODO use cker for execution
+// TODO divide tensor prepare and execution
+// TODO introduce memory manager (buffer allocate and free)
+class OperationExecutor : ir::OperationVisitor
+{
+public:
+  OperationExecutor(ExecEnv *env) : _env{env}
+  {
+    _kernels[ir::OpCode::Add] = getAdd();
+    _kernels[ir::OpCode::Sub] = getSub();
+    _kernels[ir::OpCode::Mul] = getMul();
+    _kernels[ir::OpCode::Conv2D] = getConv2D();
+    _kernels[ir::OpCode::MaxPool2D] = getMaxPool2D();
+    _kernels[ir::OpCode::Concat] = getConcat();
+    _kernels[ir::OpCode::Gather] = getGather();
+    _kernels[ir::OpCode::AvgPool2D] = getAvgPool2D();
+    _kernels[ir::OpCode::FullyConnected] = getFullyConnected();
+    _kernels[ir::OpCode::InstanceNorm] = getInstanceNorm();
+    _kernels[ir::OpCode::Softmax] = getSoftMax();
+    _kernels[ir::OpCode::Reshape] = getReshape();
+    _kernels[ir::OpCode::DepthwiseConv2D] = getDepthwiseConv();
+    _kernels[ir::OpCode::TransposeConv] = getTransposeConv();
+    _kernels[ir::OpCode::Logistic] = getLogistic();
+    _kernels[ir::OpCode::Pad] = getPad();
+    _kernels[ir::OpCode::ReLU] = getReLU();
+    _kernels[ir::OpCode::ReLU1] = getReLU1();
+    _kernels[ir::OpCode::ReLU6] = getReLU6();
+    _kernels[ir::OpCode::Tanh] = getTanh();
+  }
+
+  void execute(const ir::OperationIndex &idx)
+  {
+    const auto nodeName = _env->graph().operations().at(idx).name();
+    VERBOSE(INTERPRETER) << "Prepare output operands and execute " << nodeName
+                         << " operation (id: " << idx.value() << ")" << std::endl;
+    _env->graph().operations().at(idx).accept(*this);
+  }
+
+private:
+#define OP(InternalName)                                        \
+  void visit(const ir::operation::InternalName &node) override  \
+  {                                                             \
+    if (_kernels[ir::OpCode::InternalName]->prepare != nullptr) \
+    {                                                           \
+      _kernels[ir::OpCode::InternalName]->prepare(_env, node);  \
+    }                                                           \
+    _kernels[ir::OpCode::InternalName]->invoke(_env, node);     \
+  }
+#include "ir/Operations.lst"
+#undef OP
+
+private:
+  ExecEnv *_env;
+  std::unordered_map<ir::OpCode, OpKernel *> _kernels;
+};
+
+void Interpreter::run()
+{
+  VERBOSE(INTERPRETER) << "Interpreter is invoked " << std::endl;
+
+  // operand_stack: save operands prepared to use
+  std::stack<ir::OperandIndex> operand_stack;
+
+  // Note: We should push input first, then constant.
+  //       We use use-def for find operators ready to execution,
+  //       but Use-Def cannot handle parameters (maybe constant, but not always)
+  // Note: If all model inputs are constant, it may not work (depend on tensors' order).
+  //       But that scenario may not exist
+  for (auto ind : _env->graph().getInputs())
+  {
+    VERBOSE(INTERPRETER) << "Input: Push to operand stack " << ind.value() << std::endl;
+
+    operand_stack.push(ind);
+  }
+
+  _env->graph().operands().iterate([&](const ir::OperandIndex &ind, const ir::Operand &obj) {
+    if (obj.isConstant())
+    {
+      VERBOSE(INTERPRETER) << "Constant: Push to operand stack " << ind.value() << std::endl;
+
+      operand_stack.push(ind);
+    }
+  });
+
+  // Execution
+  std::unordered_set<ir::OperandIndex> ready_check;
+  std::unordered_set<ir::OperationIndex> executed;
+  OperationExecutor executor{_env.get()};
+  while (!operand_stack.empty())
+  {
+    const auto current_operand_index = operand_stack.top();
+    operand_stack.pop();
+    VERBOSE(INTERPRETER) << "Poped operand " << current_operand_index.value()
+                         << " is checked ready to use" << std::endl;
+
+    assert(ready_check.find(current_operand_index) == ready_check.end());
+    ready_check.insert(current_operand_index);
+
+    // Find prepared operations by scan use of current operand
+    std::stack<ir::OperationIndex> operation_stack;
+    auto use_operators = std::list<ir::OperationIndex>(
+        _env->graph().operands().at(current_operand_index).getUses().list());
+    // Remove operation index duplication
+    // If one operation uses same operand tensor for multiple input,
+    // use-list have duplicated operation index
+    use_operators.unique();
+    for (auto use_operator : use_operators)
+    {
+      // Assumption: all parameters are ready to use
+      bool operator_ready = true;
+      for (auto input_index : _env->graph().operations().at(use_operator).getInputs())
+      {
+        if (ready_check.find(input_index) == ready_check.end())
+        {
+          operator_ready = false;
+          break;
+        }
+      }
+
+      if (operator_ready)
+      {
+        VERBOSE(INTERPRETER) << "Ready to execute operation " << use_operator.value() << std::endl;
+        operation_stack.push(use_operator);
+      }
+    }
+
+    while (!operation_stack.empty())
+    {
+      const auto current_operation_index = operation_stack.top();
+      operation_stack.pop();
+      VERBOSE(INTERPRETER) << "Poped operation: " << current_operation_index.value() << "("
+                           << _env->graph().operations().at(current_operation_index).name() << ")"
+                           << std::endl;
+
+      // execution
+      // 1. Prepare output tensor
+      // 2. Call operation kernel
+      executor.execute(current_operation_index);
+      executed.insert(current_operation_index);
+
+      // 3. Push each output into operand stack
+      const auto def_operands = _env->graph().operations().at(current_operation_index).getOutputs();
+      for (auto def_operand : def_operands)
+      {
+        VERBOSE(INTERPRETER) << "Buffer: Push to operand stack " << def_operand.value()
+                             << std::endl;
+        operand_stack.push(def_operand);
+      }
+
+      // 4. Free if lifetime of buffer operands used by input is finished
+      for (auto input_index : _env->graph().operations().at(current_operation_index).getInputs())
+      {
+        const auto use_operators = _env->graph().operands().at(input_index).getUses();
+        bool dead_buffer = true;
+        for (auto use_operator : use_operators.list())
+        {
+          if (executed.find(use_operator) == executed.end())
+          {
+            dead_buffer = false;
+            break;
+          }
+        }
+
+        if (dead_buffer)
+        {
+          _env->freeIfAllocated(input_index);
+        }
+      }
+    }
+  }
+}
+
+} // namespace interp
+} // namespace exec
+} // namespace neurun
diff --git a/runtime/neurun/core/src/exec/interp/Interpreter.h b/runtime/neurun/core/src/exec/interp/Interpreter.h
new file mode 100644
index 000000000..1b73592b3
--- /dev/null
+++ b/runtime/neurun/core/src/exec/interp/Interpreter.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file  Interpreter.h
+ * @brief This file contains Interpreter class for interpretation
+ */
+#ifndef __NEURUN_EXEC_INTERP_INTERPRETER_H__
+#define __NEURUN_EXEC_INTERP_INTERPRETER_H__
+
+#include "ExecEnv.h"
+
+namespace neurun
+{
+namespace exec
+{
+namespace interp
+{
+
+/**
+ * @brief Class for interpretation
+ */
+class Interpreter
+{
+
+public:
+  /**
+   * @brief Construct a new Interpreter object (deleted)
+   */
+  Interpreter() = delete;
+  /**
+   * @brief     Construct a new Interpreter object
+   * @param[in] env Execution environment variable for interpreter object
+   */
+  Interpreter(std::unique_ptr<ExecEnv> env) : _env{std::move(env)}
+  {
+    // DO NOTHING
+  }
+
+public:
+  /**
+   * @brief Run interpreter until there is no operation to execute
+   */
+  void run();
+
+private:
+  std::unique_ptr<ExecEnv> _env;
+};
+
+} // namespace interp
+} // namespace exec
+} // namespace neurun
+
+#endif // __NEURUN_EXEC_INTERP_INTERPRETER_H__
diff --git a/runtime/neurun/core/src/exec/interp/Registration.h b/runtime/neurun/core/src/exec/interp/Registration.h
new file mode 100644
index 000000000..3ebe3bc9f
--- /dev/null
+++ b/runtime/neurun/core/src/exec/interp/Registration.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_EXEC_INTERP_REGISTRATION_H__
+#define __NEURUN_EXEC_INTERP_REGISTRATION_H__
+
+#include "ExecEnv.h"
+
+#include "ir/Operation.h"
+
+namespace neurun
+{
+namespace exec
+{
+namespace interp
+{
+
+struct OpKernel
+{
+  std::function<void(ExecEnv *, const ir::Operation &)> prepare;
+  std::function<void(const ExecEnv *, const ir::Operation &)> invoke;
+};
+
+// Defined in operations/ directory
+OpKernel *getAdd();
+OpKernel *getSub();
+OpKernel *getMul();
+OpKernel *getConv2D();
+OpKernel *getMaxPool2D();
+OpKernel *getConcat();
+OpKernel *getGather();
+OpKernel *getAvgPool2D();
+OpKernel *getFullyConnected();
+OpKernel *getInstanceNorm();
+OpKernel *getSoftMax();
+OpKernel *getDepthwiseConv();
+OpKernel *getReshape();
+OpKernel *getTransposeConv();
+OpKernel *getLogistic();
+OpKernel *getPad();
+OpKernel *getReLU();
+OpKernel *getReLU1();
+OpKernel *getReLU6();
+OpKernel *getTanh();
+
+} // namespace interp
+} // namespace exec
+} // namespace neurun
+
+#endif // __NEURUN_EXEC_INTERP_REGISTRATION_H__
diff --git a/runtime/neurun/core/src/exec/interp/Tensor.cc b/runtime/neurun/core/src/exec/interp/Tensor.cc
new file mode 100644
index 000000000..5c1da3587
--- /dev/null
+++ b/runtime/neurun/core/src/exec/interp/Tensor.cc
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "Tensor.h"
+
+#define NO_USE(a) (void)(a)
+
+namespace neurun
+{
+namespace exec
+{
+namespace interp
+{
+
+void ITensor::access(const std::function<void(backend::operand::ITensor &tensor)> &fn)
+{
+  fn(*this);
+}
+
+size_t ROTensor::calcOffset(const neurun::util::Coordinates &coords) const
+{
+  NO_USE(coords);
+  throw std::runtime_error("offset_element_in_bytes is not supported for cpu::Tensor now.");
+}
+
+size_t Tensor::calcOffset(const neurun::util::Coordinates &coords) const
+{
+  NO_USE(coords);
+  throw std::runtime_error("offset_element_in_bytes is not supported for cpu::Tensor now.");
+}
+
+ir::Layout ROTensor::layout() const
+{
+  // TODO Changes to return frontend layout
+  return ir::Layout::NHWC;
+}
+
+ir::Layout Tensor::layout() const
+{
+  // TODO Changes to return frontend layout
+  return ir::Layout::NHWC;
+}
+
+} // namespace interp
+} // namespace exec
+} // namespace neurun
diff --git a/runtime/neurun/core/src/exec/interp/Tensor.h b/runtime/neurun/core/src/exec/interp/Tensor.h
new file mode 100644
index 000000000..c53fd46a6
--- /dev/null
+++ b/runtime/neurun/core/src/exec/interp/Tensor.h
@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file  Tensor.h
+ * @brief This file contains ITensor interface, ROTensor class, and Tensor class
+ */
+#ifndef __NEURUN_EXEC_INTERP_TENSOR_H__
+#define __NEURUN_EXEC_INTERP_TENSOR_H__
+
+#include "Buffer.h"
+
+#include "ir/OperandInfo.h"
+#include "backend/operand/ITensor.h"
+#include "ir/Layout.h"
+
+namespace neurun
+{
+namespace exec
+{
+namespace interp
+{
+
+/**
+ * @brief Interface to handle Tensor in interpreter
+ */
+class ITensor : public backend::operand::ITensor
+{
+public:
+  virtual ~ITensor() = default;
+
+public:
+  virtual uint8_t *buffer() const = 0;
+  /**
+   * @brief   Return shared pointer for buffer
+   * @return  Buffer shared pointer
+   */
+  virtual std::shared_ptr<const Buffer> shareBuffer() const = 0;
+  /**
+   * @brief   Return read-only buffer pointer
+   * @return  Read-only buffer pointer
+   */
+  virtual const uint8_t *bufferRO() const = 0;
+  /**
+   * @brief   Return shared pointer for data
+   * @return  Data shared pointer
+   */
+  virtual std::shared_ptr<const ir::Data> shareData() const = 0;
+  /**
+   * @brief     Set internal/external buffer
+   * @param[in] buffer  Buffer pointer
+   */
+  virtual void setBuffer(std::shared_ptr<const Buffer> buffer) = 0;
+  /**
+   * @brief     Set data reference (including constant, input)
+   * @param[in] data  Data pointer
+   */
+  virtual void setData(std::shared_ptr<const ir::Data> data) = 0;
+  virtual void releaseData() = 0;
+
+  virtual size_t total_size() const = 0;
+  virtual size_t dimension(size_t index) const = 0;
+  virtual size_t num_dimensions() const = 0;
+  virtual size_t calcOffset(const util::Coordinates &coords) const = 0;
+
+  virtual bool has_padding() const = 0;
+  /**
+   * @brief   Return data type of tensor
+   * @return  Data type of tensor
+   */
+  virtual ir::DataType data_type() const = 0;
+  /**
+   * @brief   Return TensorInfo
+   * @return  TensorInfo
+   */
+  virtual const ir::OperandInfo &tensorInfo() const = 0;
+  /**
+   * @brief   Return number of elements
+   * @return  Number of elements
+   */
+  virtual uint64_t num_elements() const = 0;
+  void access(const std::function<void(backend::operand::ITensor &tensor)> &fn) final;
+};
+
+/**
+ * @brief Class to handle tensor in interpreter as read-only
+ */
+class ROTensor final : public ITensor
+{
+public:
+  ROTensor() = delete;
+  ROTensor(const ir::OperandInfo &info) : _info(info)
+  {
+    // DO NOTHING
+  }
+
+public:
+  uint8_t *buffer() const override { throw std::runtime_error{"Read only tensor"}; }
+  std::shared_ptr<const Buffer> shareBuffer() const override
+  {
+    throw std::runtime_error{"Read only tensor"};
+  }
+  const uint8_t *bufferRO() const override { return _data->base(); }
+  std::shared_ptr<const ir::Data> shareData() const override { return _data; }
+  void setBuffer(std::shared_ptr<const Buffer> buffer) override { _data = buffer; }
+  void setData(std::shared_ptr<const ir::Data> data) override { _data = data; }
+  void releaseData() override { _data = nullptr; }
+
+  size_t total_size() const override { return _info.total_size(); }
+  size_t dimension(size_t index) const override { return _info.shape().dim(index); }
+  size_t num_dimensions() const override { return _info.shape().rank(); }
+  size_t calcOffset(const util::Coordinates &coords) const override;
+  ir::Layout layout() const override;
+  bool has_padding() const override { return false; }
+  ir::DataType data_type() const override { return _info.typeInfo().type(); }
+  const ir::OperandInfo &tensorInfo() const override { return _info; }
+  uint64_t num_elements() const override { return _info.shape().num_elements(); };
+
+private:
+  const ir::OperandInfo _info;
+  std::shared_ptr<const ir::Data> _data{nullptr};
+};
+
+/**
+ * @brief Class to handle tensor in interpreter as writable
+ */
+class Tensor final : public ITensor
+{
+public:
+  Tensor() = delete;
+  Tensor(const ir::OperandInfo &info) : _info(info)
+  {
+    // DO NOTHING
+  }
+
+public:
+  uint8_t *buffer() const override { return _buffer->baseWritable(); }
+  std::shared_ptr<const Buffer> shareBuffer() const override { return _buffer; };
+  const uint8_t *bufferRO() const override { return _buffer->base(); }
+  std::shared_ptr<const ir::Data> shareData() const override { return _buffer; }
+  void setBuffer(std::shared_ptr<const Buffer> buffer) override { _buffer = buffer; }
+  void setData(std::shared_ptr<const ir::Data>) override
+  {
+    throw std::runtime_error{"Passed data may read-only"};
+  }
+  void releaseData() override { _buffer = nullptr; }
+
+  size_t total_size() const override { return _info.total_size(); }
+  size_t dimension(size_t index) const override { return _info.shape().dim(index); }
+  size_t num_dimensions() const override { return _info.shape().rank(); }
+  size_t calcOffset(const util::Coordinates &coords) const override;
+  ir::Layout layout() const override;
+  bool has_padding() const override { return false; }
+  ir::DataType data_type() const override { return _info.typeInfo().type(); }
+  const ir::OperandInfo &tensorInfo() const override { return _info; }
+  uint64_t num_elements() const override { return _info.shape().num_elements(); };
+
+private:
+  const ir::OperandInfo _info;
+  std::shared_ptr<const Buffer> _buffer{nullptr};
+};
+
+} // namespace interp
+} // namespace exec
+} // namespace neurun
+
+#endif // __NEURUN_EXEC_INTERP_TENSOR_H__
diff --git a/runtime/neurun/core/src/exec/interp/operations/AvgPool2D.cc b/runtime/neurun/core/src/exec/interp/operations/AvgPool2D.cc
new file mode 100644
index 000000000..bd396491f
--- /dev/null
+++ b/runtime/neurun/core/src/exec/interp/operations/AvgPool2D.cc
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <cker/operation/AveragePool.h>
+
+#include "OperationUtil.h"
+
+#include "exec/interp/Registration.h"
+#include "ir/operation/AvgPool2D.h"
+#include "util/Utils.h"
+#include "util/Padding.h"
+#include "util/ShapeInference.h"
+#include "misc/polymorphic_downcast.h"
+
+namespace neurun
+{
+namespace exec
+{
+namespace interp
+{
+namespace avgpool2d
+{
+
+void prepareAvgPool2D(ExecEnv *env, const ir::Operation &node)
+{
+  const auto in_index = node.getInputs().at(0);
+  const auto out_index = node.getOutputs().at(0);
+
+  const auto in_tensor = env->tensorAt(in_index);
+  UNUSED_RELEASE(in_tensor);
+
+  assert(in_tensor->num_dimensions() == 4);
+
+  const auto output_info = env->graph().operands().at(out_index).info();
+  if (output_info.total_size() == 0)
+  {
+    // Handle unspecified output shape
+    const auto &avgpool_node =
+        nnfw::misc::polymorphic_downcast<const ir::operation::AvgPool2D &>(node);
+    const auto infered_output_shapes =
+        shape_inference::inferAvgPoolShape(in_tensor->tensorInfo().shape(), avgpool_node.param());
+    env->allocateIfNeeded(out_index, {infered_output_shapes[0], output_info.typeInfo()});
+  }
+  else
+  {
+    env->allocateIfNeeded(out_index, output_info);
+  }
+
+  auto out_tensor = env->tensorAt(out_index);
+  UNUSED_RELEASE(out_tensor);
+
+  // Handle same ifm & ofm data type only
+  assert(in_tensor->data_type() == out_tensor->data_type());
+  assert(out_tensor->num_dimensions() == 4);
+}
+
+void invoke(const ITensor *in_tensor, const ITensor *out_tensor,
+            const ir::operation::AvgPool2D::Param &param)
+{
+  // TODO Support NCHW frontend
+  const auto ifm_shape = in_tensor->tensorInfo().shape().asFeature(ir::Layout::NHWC);
+  const auto ofm_shape = out_tensor->tensorInfo().shape().asFeature(ir::Layout::NHWC);
+  const auto padding = neurun::util::calculatePadding(param.padding, ifm_shape, ofm_shape,
+                                                      param.stride, param.kw, param.kh);
+  // Calculate
+  nnfw::cker::PoolParams cker_param;
+  calculateActivationRange(param.activation, &cker_param.float_activation_min,
+                           &cker_param.float_activation_max);
+  cker_param.filter_width = param.kw;
+  cker_param.filter_height = param.kh;
+  cker_param.padding_values.width = padding.left;
+  cker_param.padding_values.height = padding.top;
+  cker_param.stride_width = param.stride.horizontal;
+  cker_param.stride_height = param.stride.vertical;
+
+  const auto in_shape = convertShape(in_tensor->tensorInfo().shape());
+  const auto out_shape = convertShape(out_tensor->tensorInfo().shape());
+  const float *in_ptr = reinterpret_cast<const float *>(in_tensor->bufferRO());
+  float *out_ptr = reinterpret_cast<float *>(out_tensor->buffer());
+
+  nnfw::cker::AveragePool(cker_param, in_shape, in_ptr, out_shape, out_ptr);
+}
+
+void invokeAvgPool2D(const ExecEnv *env, const ir::Operation &node)
+{
+  const auto &avgpool_node =
+      nnfw::misc::polymorphic_downcast<const ir::operation::AvgPool2D &>(node);
+
+  const auto in_index = node.getInputs().at(0);
+  const auto out_index = node.getOutputs().at(0);
+
+  // Check lhs shape is same with rhs (with broadcast)
+  const auto in_tensor = env->tensorAt(in_index);
+  const auto out_tensor = env->tensorAt(out_index);
+
+  const auto data_type = in_tensor->data_type();
+  if (data_type == ir::DataType::FLOAT32)
+  {
+    invoke(in_tensor, out_tensor, avgpool_node.param());
+  }
+  else
+  {
+    throw std::runtime_error{"NYI: Support float only"};
+  }
+}
+} // namespace avgpool2d
+
+OpKernel *getAvgPool2D()
+{
+  static OpKernel kernel = {avgpool2d::prepareAvgPool2D, avgpool2d::invokeAvgPool2D};
+  return &kernel;
+}
+
+} // namespace interp
+} // namespace exec
+} // namespace neurun
diff --git a/runtime/neurun/core/src/exec/interp/operations/BinaryArithmeticOps.cc b/runtime/neurun/core/src/exec/interp/operations/BinaryArithmeticOps.cc
new file mode 100644
index 000000000..16469b9db
--- /dev/null
+++ b/runtime/neurun/core/src/exec/interp/operations/BinaryArithmeticOps.cc
@@ -0,0 +1,202 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <cker/operation/BinaryArithmeticOps.h>
+
+#include "OperationUtil.h"
+
+#include "exec/interp/Registration.h"
+#include "ir/operation/Add.h"
+#include "ir/operation/Sub.h"
+#include "ir/operation/Mul.h"
+#include "misc/polymorphic_downcast.h"
+
+namespace neurun
+{
+namespace exec
+{
+namespace interp
+{
+namespace
+{
+
+enum class OpType
+{
+  ADD,
+  SUB,
+  MUL
+};
+
+template <typename node_type> void prepareAdd(ExecEnv *env, const ir::Operation &node)
+{
+  const auto &add_node = nnfw::misc::polymorphic_downcast<const node_type &>(node);
+
+  const auto lhs_index = node.getInputs().at(add_node.LHS);
+  const auto rhs_index = node.getInputs().at(add_node.RHS);
+  const auto out_index = node.getOutputs().at(0);
+
+  const auto lhs_tensor = env->tensorAt(lhs_index);
+  const auto rhs_tensor = env->tensorAt(rhs_index);
+
+  // Check shape and type lhs is same with rhs
+  // TODO Util function to compare TensorInfo
+  if (lhs_tensor->data_type() != rhs_tensor->data_type())
+  {
+    throw std::runtime_error{"Interp(Add): Different input types"};
+  }
+
+  bool try_broadcast = (lhs_tensor->tensorInfo().shape() != rhs_tensor->tensorInfo().shape());
+  if (try_broadcast)
+  {
+    bool success = true;
+    auto out_shape = calcBroadcastShape(lhs_tensor->tensorInfo().shape(),
+                                        rhs_tensor->tensorInfo().shape(), success);
+    if (!success)
+    {
+      throw std::runtime_error{"Interp(Add): Fail to brodcasting"};
+    }
+
+    auto output_info = ir::OperandInfo(out_shape, lhs_tensor->tensorInfo().typeInfo());
+    // We can handle already allocated (ex. model output)
+    env->allocateIfNeeded(out_index, output_info);
+  }
+  else
+  {
+    // Output's shape and type is same with input
+    auto output_info = lhs_tensor->tensorInfo();
+    // We can handle already allocated (ex. model output)
+    env->allocateIfNeeded(out_index, output_info);
+  }
+
+  auto out_tensor = env->tensorAt(out_index);
+  // Check shape and type lhs is same with output
+  // TODO Util function to compare TensorInfo
+  if (lhs_tensor->data_type() != out_tensor->data_type())
+  {
+    throw std::runtime_error{"Interp(Add): Invalid output type"};
+  }
+}
+
+inline void setActivationParams(float min, float max, nnfw::cker::BinaryArithmeticOpParam *params)
+{
+  params->float_activation_min = min;
+  params->float_activation_max = max;
+}
+
+inline void setActivationParams(int32_t min, int32_t max,
+                                nnfw::cker::BinaryArithmeticOpParam *params)
+{
+  params->quantized_activation_min = min;
+  params->quantized_activation_max = max;
+}
+
+template <typename raw_type, typename param_type, OpType op_type>
+void invoke(const ITensor *lhs_tensor, const ITensor *rhs_tensor, const ITensor *out_tensor,
+            const param_type &param)
+{
+  const auto lhs_buffer = lhs_tensor->bufferRO();
+  const auto rhs_buffer = rhs_tensor->bufferRO();
+  auto out_buffer = out_tensor->buffer();
+
+  nnfw::cker::BinaryArithmeticOpParam cker_param;
+  raw_type activation_min, activation_max;
+  calculateActivationRange(param.activation, &activation_min, &activation_max);
+  setActivationParams(activation_min, activation_max, &cker_param);
+  const raw_type *lhs_ptr = reinterpret_cast<const raw_type *>(lhs_buffer);
+  const raw_type *rhs_ptr = reinterpret_cast<const raw_type *>(rhs_buffer);
+  raw_type *out_ptr = reinterpret_cast<raw_type *>(out_buffer);
+
+  // Calculate
+  const std::function<raw_type(const raw_type &, const raw_type &)> fn_add =
+      [](const raw_type &a, const raw_type &b) { return a + b; };
+  const std::function<raw_type(const raw_type &, const raw_type &)> fn_sub =
+      [](const raw_type &a, const raw_type &b) { return a - b; };
+  const std::function<raw_type(const raw_type &, const raw_type &)> fn_mul =
+      [](const raw_type &a, const raw_type &b) { return a * b; };
+
+  const std::function<raw_type(const raw_type &, const raw_type &)> fn =
+      (op_type == OpType::ADD) ? fn_add : ((op_type == OpType::SUB) ? fn_sub : fn_mul);
+
+  if (lhs_tensor->tensorInfo().shape() != rhs_tensor->tensorInfo().shape())
+  {
+    const auto lhs_shape = convertExtendShape(lhs_tensor->tensorInfo().shape());
+    const auto rhs_shape = convertExtendShape(rhs_tensor->tensorInfo().shape());
+    const auto out_shape = convertExtendShape(out_tensor->tensorInfo().shape());
+    nnfw::cker::BroadcastBinaryArithmeticOpSlow(cker_param, lhs_shape, lhs_ptr, rhs_shape, rhs_ptr,
+                                                out_shape, out_ptr, fn);
+    return;
+  }
+
+  const auto lhs_shape = convertShape(lhs_tensor->tensorInfo().shape());
+  const auto rhs_shape = convertShape(rhs_tensor->tensorInfo().shape());
+  const auto out_shape = convertShape(out_tensor->tensorInfo().shape());
+  nnfw::cker::BinaryArithmeticOp(cker_param, lhs_shape, lhs_ptr, rhs_shape, rhs_ptr, out_shape,
+                                 out_ptr, fn);
+}
+
+template <typename node_type, typename param_type, OpType op_type>
+void invokeAdd(const ExecEnv *env, const ir::Operation &node)
+{
+  const auto &arithmetic_node = nnfw::misc::polymorphic_downcast<const node_type &>(node);
+
+  const auto lhs_index = node.getInputs().at(arithmetic_node.LHS);
+  const auto rhs_index = node.getInputs().at(arithmetic_node.RHS);
+  const auto out_index = node.getOutputs().at(0);
+  const auto lhs_tensor = env->tensorAt(lhs_index);
+  const auto rhs_tensor = env->tensorAt(rhs_index);
+  const auto out_tensor = env->tensorAt(out_index);
+  const auto data_type = lhs_tensor->data_type();
+
+  if (data_type == ir::DataType::INT32)
+  {
+    invoke<int32_t, param_type, op_type>(lhs_tensor, rhs_tensor, out_tensor,
+                                         arithmetic_node.param());
+  }
+  else if (data_type == ir::DataType::FLOAT32)
+  {
+    invoke<float, param_type, op_type>(lhs_tensor, rhs_tensor, out_tensor, arithmetic_node.param());
+  }
+  else
+  {
+    throw std::runtime_error{"NYI: Unsupported data type"};
+  }
+}
+} // namespace add
+
+OpKernel *getAdd()
+{
+  static OpKernel kernel = {prepareAdd<ir::operation::Add>,
+                            invokeAdd<ir::operation::Add, ir::operation::Add::Param, OpType::ADD>};
+  return &kernel;
+}
+
+OpKernel *getSub()
+{
+  static OpKernel kernel = {prepareAdd<ir::operation::Sub>,
+                            invokeAdd<ir::operation::Sub, ir::operation::Sub::Param, OpType::SUB>};
+  return &kernel;
+}
+
+OpKernel *getMul()
+{
+  static OpKernel kernel = {prepareAdd<ir::operation::Mul>,
+                            invokeAdd<ir::operation::Mul, ir::operation::Mul::Param, OpType::MUL>};
+  return &kernel;
+}
+
+} // namespace interp
+} // namespace exec
+} // namespace neurun
diff --git a/runtime/neurun/core/src/exec/interp/operations/Concat.cc b/runtime/neurun/core/src/exec/interp/operations/Concat.cc
new file mode 100644
index 000000000..a127e5f30
--- /dev/null
+++ b/runtime/neurun/core/src/exec/interp/operations/Concat.cc
@@ -0,0 +1,150 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <cker/operation/Concatenation.h>
+
+#include "OperationUtil.h"
+
+#include "exec/interp/Registration.h"
+#include "ir/operation/Concat.h"
+#include "misc/polymorphic_downcast.h"
+
+namespace neurun
+{
+namespace exec
+{
+namespace interp
+{
+namespace concat
+{
+
+void prepareConcat(ExecEnv *env, const ir::Operation &node)
+{
+  const auto &concat_node = nnfw::misc::polymorphic_downcast<const ir::operation::Concat &>(node);
+
+  const auto first_index = node.getInputs().at(0);
+  const auto out_index = node.getOutputs().at(0);
+
+  const auto first_tensor = env->tensorAt(first_index);
+  uint32_t out_axis_dimension = 0;
+  const int32_t axis_raw = concat_node.param().axis;
+  const uint32_t axis = (axis_raw < 0) ? (axis_raw + first_tensor->num_dimensions()) : axis_raw;
+
+  // All inputs shape should be same except axis dimension
+  // All inputs type should be same
+  for (auto input : node.getInputs())
+  {
+    assert(first_tensor->num_dimensions() == env->tensorAt(input)->num_dimensions());
+    assert(first_tensor->data_type() == env->tensorAt(input)->data_type());
+    for (uint32_t i = 0; i < first_tensor->num_dimensions(); i++)
+    {
+      if (i == axis)
+      {
+        out_axis_dimension += env->tensorAt(input)->dimension(i);
+        continue;
+      }
+      assert(first_tensor->dimension(i) == env->tensorAt(input)->dimension(i));
+    }
+  }
+
+  // Make output tensor info using first input tensor info, and accumulated axis dimension value
+  auto out_shape = first_tensor->tensorInfo().shape();
+  out_shape.dim(axis) = out_axis_dimension;
+  env->allocateIfNeeded(out_index,
+                        ir::OperandInfo{out_shape, first_tensor->tensorInfo().typeInfo()});
+
+  auto out_tensor = env->tensorAt(out_index);
+  UNUSED_RELEASE(out_tensor);
+
+  // Output shape should be same with input except axis dimension
+  // Output type should be same with input
+  assert(first_tensor->data_type() == out_tensor->data_type());
+  for (uint32_t i = 0; i < first_tensor->num_dimensions(); i++)
+  {
+    if (i == axis)
+    {
+      continue;
+    }
+    assert(first_tensor->dimension(i) == out_tensor->dimension(i));
+  }
+}
+
+void invoke(const std::vector<const ITensor *> in_tensors, const ITensor *out_tensor, uint32_t axis)
+{
+  const uint32_t count = in_tensors.size();
+
+  // Calculate
+  nnfw::cker::ConcatenationParams cker_param;
+  cker_param.axis = (int8_t)axis;
+  cker_param.inputs_count = count;
+
+  const auto out_shape = convertShape(out_tensor->tensorInfo().shape());
+
+  std::vector<nnfw::cker::Shape> in_shapes;
+  std::vector<const nnfw::cker::Shape *> in_shape_ptrs;
+  in_shapes.reserve(count);
+  in_shape_ptrs.reserve(count);
+  std::vector<const float *> in_ptrs;
+  for (uint32_t i = 0; i < count; i++)
+  {
+    in_shapes.push_back(convertShape(in_tensors[i]->tensorInfo().shape()));
+    in_shape_ptrs.push_back(&in_shapes[i]);
+    in_ptrs.push_back(reinterpret_cast<const float *>(in_tensors[i]->bufferRO()));
+  }
+
+  auto out_buffer = out_tensor->buffer();
+  float *out_ptr = reinterpret_cast<float *>(out_buffer);
+
+  nnfw::cker::Concatenation<float>(cker_param, in_shape_ptrs.data(), in_ptrs.data(), out_shape,
+                                   out_ptr);
+}
+
+void invokeConcat(const ExecEnv *env, const ir::Operation &node)
+{
+  const auto &concat_node = nnfw::misc::polymorphic_downcast<const ir::operation::Concat &>(node);
+  const int32_t axis_raw = concat_node.param().axis;
+
+  std::vector<const ITensor *> in_tensors;
+  for (const auto &e : concat_node.getInputs())
+  {
+    in_tensors.emplace_back(env->tensorAt(e));
+  }
+
+  const auto out_index = node.getOutputs().at(0);
+  const auto out_tensor = env->tensorAt(out_index);
+  const uint32_t axis = (axis_raw < 0) ? (axis_raw + out_tensor->num_dimensions()) : axis_raw;
+
+  const auto data_type = in_tensors[0]->data_type();
+  if (data_type == ir::DataType::FLOAT32)
+  {
+    invoke(in_tensors, out_tensor, axis);
+  }
+  else
+  {
+    throw std::runtime_error{"NYI: Support float32 only"};
+  }
+}
+} // namespace concat
+
+OpKernel *getConcat()
+{
+  static OpKernel kernel = {concat::prepareConcat, concat::invokeConcat};
+  return &kernel;
+}
+
+} // namespace interp
+} // namespace exec
+} // namespace neurun
diff --git a/runtime/neurun/core/src/exec/interp/operations/Conv2D.cc b/runtime/neurun/core/src/exec/interp/operations/Conv2D.cc
new file mode 100644
index 000000000..5242247a4
--- /dev/null
+++ b/runtime/neurun/core/src/exec/interp/operations/Conv2D.cc
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <cker/operation/Conv.h>
+
+#include "OperationUtil.h"
+
+#include "exec/interp/Registration.h"
+#include "ir/operation/Conv2D.h"
+#include "util/Utils.h"
+#include "util/Padding.h"
+#include "util/ShapeInference.h"
+#include "misc/polymorphic_downcast.h"
+
+namespace neurun
+{
+namespace exec
+{
+namespace interp
+{
+namespace conv2d
+{
+
+void prepareConv2D(ExecEnv *env, const ir::Operation &node)
+{
+  const auto in_index = node.getInputs().at(ir::operation::Conv2D::INPUT);
+  const auto kernel_index = node.getInputs().at(ir::operation::Conv2D::KERNEL);
+  const auto bias_index = node.getInputs().at(ir::operation::Conv2D::BIAS);
+  const auto out_index = node.getOutputs().at(0);
+
+  const auto in_tensor = env->tensorAt(in_index);
+  const auto kernel_tensor = env->tensorAt(kernel_index);
+  const auto bias_tensor = env->tensorAt(bias_index);
+
+  assert(in_tensor->num_dimensions() == 4);
+  assert(kernel_tensor->num_dimensions() == 4);
+  assert(bias_tensor->num_dimensions() == 1);
+
+  UNUSED_RELEASE(in_tensor);
+  UNUSED_RELEASE(kernel_tensor);
+  UNUSED_RELEASE(bias_tensor);
+
+  const auto output_info = env->graph().operands().at(out_index).info();
+  if (output_info.total_size() == 0)
+  {
+    // Handle unspecified output shape
+    const auto &conv_node = nnfw::misc::polymorphic_downcast<const ir::operation::Conv2D &>(node);
+    const auto infered_output_shapes = shape_inference::inferConv2DShape(
+        in_tensor->tensorInfo().shape(), kernel_tensor->tensorInfo().shape(), conv_node.param());
+    env->allocateIfNeeded(out_index, {infered_output_shapes[0], output_info.typeInfo()});
+  }
+  else
+  {
+    env->allocateIfNeeded(out_index, output_info);
+  }
+
+  auto out_tensor = env->tensorAt(out_index);
+  UNUSED_RELEASE(out_tensor);
+
+  // Handle same ifm & ofm data type only
+  assert(in_tensor->data_type() == out_tensor->data_type());
+  assert(out_tensor->num_dimensions() == 4);
+}
+
+void invoke(const ITensor *ifm_tensor, const ITensor *ker_tensor, const ITensor *bias_tensor,
+            const ITensor *ofm_tensor, const ir::operation::Conv2D::Param &param)
+{
+  // TODO Support NCHW frontned
+  const auto ifm_shape = ifm_tensor->tensorInfo().shape().asFeature(ir::Layout::NHWC);
+  const auto ofm_shape = ofm_tensor->tensorInfo().shape().asFeature(ir::Layout::NHWC);
+  // Kernel format is [depth_out, kernel_height, kernel_width, depth_in].
+  const auto &ker_shape = ker_tensor->tensorInfo().shape();
+  const auto ker_height = ker_shape.dim(1);
+  const auto ker_width = ker_shape.dim(2);
+  const auto padding = neurun::util::calculatePadding(param.padding, ifm_shape, ofm_shape,
+                                                      param.stride, ker_width, ker_height);
+
+  // Calculate
+  float activation_min, activation_max;
+  calculateActivationRange(param.activation, &activation_min, &activation_max);
+
+  nnfw::cker::ConvParams cker_param;
+  cker_param.padding_values.width = padding.left;
+  cker_param.padding_values.height = padding.top;
+  cker_param.stride_width = param.stride.horizontal;
+  cker_param.stride_height = param.stride.vertical;
+  cker_param.dilation_width_factor = 1;
+  cker_param.dilation_height_factor = 1;
+  cker_param.float_activation_min = activation_min;
+  cker_param.float_activation_max = activation_max;
+
+  const auto cker_ifm_shape = convertShape(ifm_tensor->tensorInfo().shape());
+  const auto cker_ker_shape = convertShape(ker_tensor->tensorInfo().shape());
+  const auto cker_bias_shape = convertShape(bias_tensor->tensorInfo().shape());
+  const auto cker_ofm_shape = convertShape(ofm_tensor->tensorInfo().shape());
+  const float *ifm_ptr = reinterpret_cast<const float *>(ifm_tensor->bufferRO());
+  const float *ker_ptr = reinterpret_cast<const float *>(ker_tensor->bufferRO());
+  const float *bias_ptr = reinterpret_cast<const float *>(bias_tensor->bufferRO());
+  float *ofm_ptr = reinterpret_cast<float *>(ofm_tensor->buffer());
+
+  nnfw::cker::Conv(cker_param, cker_ifm_shape, ifm_ptr, cker_ker_shape, ker_ptr, cker_bias_shape,
+                   bias_ptr, cker_ofm_shape, ofm_ptr);
+}
+
+void invokeConv2D(const ExecEnv *env, const ir::Operation &node)
+{
+  const auto &conv_node = nnfw::misc::polymorphic_downcast<const ir::operation::Conv2D &>(node);
+
+  const auto ifm_index = node.getInputs().at(ir::operation::Conv2D::INPUT);
+  const auto ker_index = node.getInputs().at(ir::operation::Conv2D::KERNEL);
+  const auto bias_index = node.getInputs().at(ir::operation::Conv2D::BIAS);
+  const auto ofm_index = node.getOutputs().at(0);
+
+  const auto ifm_tensor = env->tensorAt(ifm_index);
+  const auto ker_tensor = env->tensorAt(ker_index);
+  const auto bias_tensor = env->tensorAt(bias_index);
+  const auto ofm_tensor = env->tensorAt(ofm_index);
+
+  const auto data_type = ifm_tensor->data_type();
+  if (data_type == ir::DataType::FLOAT32)
+  {
+    invoke(ifm_tensor, ker_tensor, bias_tensor, ofm_tensor, conv_node.param());
+  }
+  else
+  {
+    throw std::runtime_error{"NYI: Support float32 only"};
+  }
+}
+} // namespace conv2d
+
+OpKernel *getConv2D()
+{
+  static OpKernel kernel = {conv2d::prepareConv2D, conv2d::invokeConv2D};
+  return &kernel;
+}
+
+} // namespace interp
+} // namespace exec
+} // namespace neurun
diff --git a/runtime/neurun/core/src/exec/interp/operations/DepthwiseConv.cc b/runtime/neurun/core/src/exec/interp/operations/DepthwiseConv.cc
new file mode 100644
index 000000000..1d3649f48
--- /dev/null
+++ b/runtime/neurun/core/src/exec/interp/operations/DepthwiseConv.cc
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <cker/operation/DepthwiseConv.h>
+#include <misc/polymorphic_downcast.h>
+
+#include "OperationUtil.h"
+
+#include "exec/interp/Registration.h"
+#include "ir/operation/DepthwiseConv2D.h"
+#include "util/Padding.h"
+#include "util/Utils.h"
+#include "util/ShapeInference.h"
+
+namespace neurun
+{
+namespace exec
+{
+namespace interp
+{
+
+namespace
+{
+
+void prepareDepthwiseConv(ExecEnv *env, const ir::Operation &node)
+{
+  const auto in_index = node.getInputs().at(ir::operation::DepthwiseConv2D::INPUT);
+  const auto kernel_index = node.getInputs().at(ir::operation::DepthwiseConv2D::KERNEL);
+  const auto bias_index = node.getInputs().at(ir::operation::DepthwiseConv2D::BIAS);
+  const auto out_index = node.getOutputs().at(0);
+
+  const auto in_tensor = env->tensorAt(in_index);
+  const auto kernel_tensor = env->tensorAt(kernel_index);
+  const auto bias_tensor = env->tensorAt(bias_index);
+
+  assert(in_tensor->num_dimensions() == 4);
+  assert(kernel_tensor->num_dimensions() == 4);
+  assert(bias_tensor->num_dimensions() == 1);
+
+  UNUSED_RELEASE(in_tensor);
+  UNUSED_RELEASE(kernel_tensor);
+  UNUSED_RELEASE(bias_tensor);
+
+  // TODO handle unspecified output shape:
+  //      calculate output shape using ifm shape, kernel shape, padding, stride
+  const auto output_info = env->graph().operands().at(out_index).info();
+  if (output_info.total_size() == 0)
+  {
+    // Handle unspecified output shape
+    const auto &depth_conv_node =
+        nnfw::misc::polymorphic_downcast<const ir::operation::DepthwiseConv2D &>(node);
+    const auto infered_output_shapes = shape_inference::inferDepthwiseConv2DShape(
+        in_tensor->tensorInfo().shape(), kernel_tensor->tensorInfo().shape(),
+        depth_conv_node.param());
+    env->allocateIfNeeded(out_index, {infered_output_shapes[0], output_info.typeInfo()});
+  }
+  else
+  {
+    env->allocateIfNeeded(out_index, output_info);
+  }
+
+  auto out_tensor = env->tensorAt(out_index);
+  UNUSED_RELEASE(out_tensor);
+
+  // Handle same ifm & ofm data type only
+  assert(in_tensor->data_type() == out_tensor->data_type());
+  assert(out_tensor->num_dimensions() == 4);
+}
+
+void invoke(const ITensor *ifm_tensor, const ITensor *ker_tensor, const ITensor *bias_tensor,
+            const ITensor *ofm_tensor, const ir::operation::DepthwiseConv2D::Param &param)
+{
+  // TODO Support NCHW frontend
+  const auto ifm_shape = ifm_tensor->tensorInfo().shape().asFeature(ir::Layout::NHWC);
+  const auto ofm_shape = ofm_tensor->tensorInfo().shape().asFeature(ir::Layout::NHWC);
+  // Kernel format is [1, kernel_height, kernel_width, depth_out].
+  const auto &ker_shape = ker_tensor->tensorInfo().shape();
+  const auto ker_height = ker_shape.dim(1);
+  const auto ker_width = ker_shape.dim(2);
+  const auto padding = neurun::util::calculatePadding(param.padding, ifm_shape, ofm_shape,
+                                                      param.stride, ker_width, ker_height);
+
+  // Calculate
+  float activation_min, activation_max;
+  calculateActivationRange(param.activation, &activation_min, &activation_max);
+
+  nnfw::cker::DepthwiseConvParams cker_param;
+  cker_param.padding_values.width = padding.left;
+  cker_param.padding_values.height = padding.top;
+  cker_param.depth_multiplier = param.multiplier;
+  cker_param.stride_width = param.stride.horizontal;
+  cker_param.stride_height = param.stride.vertical;
+  cker_param.dilation_width_factor = 1;
+  cker_param.dilation_height_factor = 1;
+  cker_param.float_activation_min = activation_min;
+  cker_param.float_activation_max = activation_max;
+
+  const auto cker_ifm_shape = convertShape(ifm_tensor->tensorInfo().shape());
+  const auto cker_ker_shape = convertShape(ker_tensor->tensorInfo().shape());
+  const auto cker_bias_shape = convertShape(bias_tensor->tensorInfo().shape());
+  const auto cker_ofm_shape = convertShape(ofm_tensor->tensorInfo().shape());
+  const float *ifm_ptr = reinterpret_cast<const float *>(ifm_tensor->bufferRO());
+  const float *ker_ptr = reinterpret_cast<const float *>(ker_tensor->bufferRO());
+  const float *bias_ptr = reinterpret_cast<const float *>(bias_tensor->bufferRO());
+  float *ofm_ptr = reinterpret_cast<float *>(ofm_tensor->buffer());
+
+  nnfw::cker::DepthwiseConv(cker_param, cker_ifm_shape, ifm_ptr, cker_ker_shape, ker_ptr,
+                            cker_bias_shape, bias_ptr, cker_ofm_shape, ofm_ptr);
+}
+
+void invokeDepthwiseConv(const ExecEnv *env, const ir::Operation &node)
+{
+  const auto &conv_node = static_cast<const ir::operation::DepthwiseConv2D &>(node);
+
+  const auto ifm_index = node.getInputs().at(ir::operation::DepthwiseConv2D::INPUT);
+  const auto ker_index = node.getInputs().at(ir::operation::DepthwiseConv2D::KERNEL);
+  const auto bias_index = node.getInputs().at(ir::operation::DepthwiseConv2D::BIAS);
+  const auto ofm_index = node.getOutputs().at(0);
+
+  const auto ifm_tensor = env->tensorAt(ifm_index);
+  const auto ker_tensor = env->tensorAt(ker_index);
+  const auto bias_tensor = env->tensorAt(bias_index);
+  const auto ofm_tensor = env->tensorAt(ofm_index);
+
+  const auto data_type = ifm_tensor->data_type();
+  if (data_type == ir::DataType::FLOAT32)
+  {
+    invoke(ifm_tensor, ker_tensor, bias_tensor, ofm_tensor, conv_node.param());
+  }
+  else
+  {
+    throw std::runtime_error{"NYI: Support float32 only"};
+  }
+}
+
+} // namespace
+
+OpKernel *getDepthwiseConv()
+{
+  static OpKernel kernel = {prepareDepthwiseConv, invokeDepthwiseConv};
+  return &kernel;
+}
+
+} // namespace interp
+} // namespace exec
+} // namespace neurun
diff --git a/runtime/neurun/core/src/exec/interp/operations/FullyConnected.cc b/runtime/neurun/core/src/exec/interp/operations/FullyConnected.cc
new file mode 100644
index 000000000..9c1c5d4e2
--- /dev/null
+++ b/runtime/neurun/core/src/exec/interp/operations/FullyConnected.cc
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <cker/operation/FullyConnected.h>
+
+#include "OperationUtil.h"
+
+#include "exec/interp/Registration.h"
+#include "ir/operation/FullyConnected.h"
+#include "misc/polymorphic_downcast.h"
+
+namespace neurun
+{
+namespace exec
+{
+namespace interp
+{
+namespace fc
+{
+
+void prepareFC(ExecEnv *env, const ir::Operation &node)
+{
+  const auto in_index = node.getInputs().at(ir::operation::FullyConnected::INPUT);
+  const auto kernel_index = node.getInputs().at(ir::operation::FullyConnected::WEIGHT);
+  const auto bias_index = node.getInputs().at(ir::operation::FullyConnected::BIAS);
+  const auto out_index = node.getOutputs().at(0);
+
+  const auto in_tensor = env->tensorAt(in_index);
+  const auto kernel_tensor = env->tensorAt(kernel_index);
+  const auto bias_tensor = env->tensorAt(bias_index);
+
+  UNUSED_RELEASE(in_tensor);
+  UNUSED_RELEASE(kernel_tensor);
+  UNUSED_RELEASE(bias_tensor);
+
+  assert(in_tensor->num_dimensions() >= 2);
+  assert(kernel_tensor->num_dimensions() == 2);
+  assert(bias_tensor->num_dimensions() == 1);
+
+  const auto input_size_with_batch = in_tensor->num_elements();
+  const auto num_units = kernel_tensor->dimension(0);
+  const auto input_size = kernel_tensor->dimension(1);
+  const auto batch_size = input_size_with_batch / input_size;
+  assert(input_size_with_batch % input_size == 0);
+  assert(num_units == bias_tensor->dimension(0));
+
+  // Make output tensor info
+  ir::Shape output_shape(2);
+  output_shape.dim(0) = batch_size;
+  output_shape.dim(1) = num_units;
+  const ir::OperandInfo out_info{output_shape, in_tensor->tensorInfo().typeInfo()};
+  env->allocateIfNeeded(out_index, out_info);
+
+  auto out_tensor = env->tensorAt(out_index);
+  UNUSED_RELEASE(out_tensor);
+
+  // Handle same ifm & ofm data type only
+  assert(in_tensor->data_type() == out_tensor->data_type());
+  assert(out_tensor->num_dimensions() == 2);
+  assert(out_tensor->dimension(0) == batch_size);
+  assert(out_tensor->dimension(1) == num_units);
+}
+
+void invoke(const ITensor *ifm_tensor, const ITensor *ker_tensor, const ITensor *bias_tensor,
+            const ITensor *ofm_tensor, const ir::operation::FullyConnected::Param &param)
+{
+  const auto ifm_buffer = ifm_tensor->bufferRO();
+  const auto ker_buffer = ker_tensor->bufferRO();
+  const auto bias_buffer = bias_tensor->bufferRO();
+  auto ofm_buffer = ofm_tensor->buffer();
+
+  // Calculate
+  nnfw::cker::FullyConnectedParams cker_param;
+  calculateActivationRange(param.activation, &cker_param.float_activation_min,
+                           &cker_param.float_activation_max);
+  const auto cker_ifm_shape = convertExtendShape(ifm_tensor->tensorInfo().shape());
+  const auto cker_ker_shape = convertExtendShape(ker_tensor->tensorInfo().shape());
+  const auto cker_bias_shape = convertExtendShape(bias_tensor->tensorInfo().shape());
+  const auto cker_ofm_shape = convertExtendShape(ofm_tensor->tensorInfo().shape());
+  const float *ifm_ptr = reinterpret_cast<const float *>(ifm_buffer);
+  const float *ker_ptr = reinterpret_cast<const float *>(ker_buffer);
+  const float *bias_ptr = reinterpret_cast<const float *>(bias_buffer);
+  float *ofm_ptr = reinterpret_cast<float *>(ofm_buffer);
+
+  nnfw::cker::FullyConnected(cker_param, cker_ifm_shape, ifm_ptr, cker_ker_shape, ker_ptr,
+                             cker_bias_shape, bias_ptr, cker_ofm_shape, ofm_ptr);
+}
+
+void invokeFC(const ExecEnv *env, const ir::Operation &node)
+{
+  const auto &conv_node =
+      nnfw::misc::polymorphic_downcast<const ir::operation::FullyConnected &>(node);
+
+  const auto ifm_index = node.getInputs().at(ir::operation::FullyConnected::INPUT);
+  const auto ker_index = node.getInputs().at(ir::operation::FullyConnected::WEIGHT);
+  const auto bias_index = node.getInputs().at(ir::operation::FullyConnected::BIAS);
+  const auto ofm_index = node.getOutputs().at(0);
+
+  const auto ifm_tensor = env->tensorAt(ifm_index);
+  const auto ker_tensor = env->tensorAt(ker_index);
+  const auto bias_tensor = env->tensorAt(bias_index);
+  const auto ofm_tensor = env->tensorAt(ofm_index);
+
+  const auto data_type = ifm_tensor->data_type();
+  if (data_type == ir::DataType::FLOAT32)
+  {
+    invoke(ifm_tensor, ker_tensor, bias_tensor, ofm_tensor, conv_node.param());
+  }
+  else
+  {
+    throw std::runtime_error{"NYI: Support float only"};
+  }
+}
+} // namespace fc
+
+OpKernel *getFullyConnected()
+{
+  static OpKernel kernel = {fc::prepareFC, fc::invokeFC};
+  return &kernel;
+}
+
+} // namespace interp
+} // namespace exec
+} // namespace neurun
diff --git a/runtime/neurun/core/src/exec/interp/operations/Gather.cc b/runtime/neurun/core/src/exec/interp/operations/Gather.cc
new file mode 100644
index 000000000..8b64d1937
--- /dev/null
+++ b/runtime/neurun/core/src/exec/interp/operations/Gather.cc
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <cker/operation/Gather.h>
+
+#include "OperationUtil.h"
+
+#include "exec/interp/Registration.h"
+#include "ir/operation/Gather.h"
+#include "misc/polymorphic_downcast.h"
+
+namespace neurun
+{
+namespace exec
+{
+namespace interp
+{
+namespace
+{
+
+void prepareGather(ExecEnv *env, const ir::Operation &node)
+{
+  const auto input_index = node.getInputs().at(ir::operation::Gather::INPUT);
+  const auto indices_index = node.getInputs().at(ir::operation::Gather::INDICES);
+  const auto output_index = node.getOutputs().at(0);
+
+  const auto input_tensor = env->tensorAt(input_index);
+  const auto indices_tensor = env->tensorAt(indices_index);
+
+  // TODO handle unspecified output shape:
+  //      calculate output shape using ifm shape, kernel shape, padding, stride
+  const auto output_info = env->graph().operands().at(output_index).info();
+  if (output_info.total_size() == 0)
+  {
+    throw std::runtime_error{"Interp(Gather): NYI for unspecified output shape"};
+  }
+  else
+  {
+    env->allocateIfNeeded(output_index, output_info);
+  }
+
+  if (indices_tensor->data_type() != ir::DataType::INT32)
+  {
+    throw std::runtime_error{"Interp(Gather): Invalid indices data type"};
+  }
+
+  auto output_tensor = env->tensorAt(output_index);
+  auto output_rank = input_tensor->num_dimensions() + indices_tensor->num_dimensions() - 1;
+
+  if (output_rank != output_tensor->num_dimensions())
+  {
+    throw std::runtime_error{"Interp(Gather): Invalid output rank"};
+  }
+  if (output_tensor->data_type() != input_tensor->data_type())
+  {
+    throw std::runtime_error{"Interp(Gather): Invalid output data type"};
+  }
+
+  if (input_tensor->data_type() == ir::DataType::QUANT8_ASYMM &&
+      input_tensor->tensorInfo().typeInfo() != output_tensor->tensorInfo().typeInfo())
+  {
+    throw std::runtime_error{
+        "Interp(Gather): Cannot handle different I/O QUANT8_ASYMM scale/offset"};
+  }
+}
+
+template <typename raw_type>
+void invoke(const ITensor *input_tensors, const ITensor *indices_tensors,
+            const ITensor *output_tensor, uint32_t axis)
+{
+  // Calculate
+  nnfw::cker::GatherParams cker_param;
+  cker_param.axis = (int8_t)axis;
+
+  const auto cker_input_shapes = convertShape(input_tensors->tensorInfo().shape());
+  const auto cker_indices_shape = convertShape(indices_tensors->tensorInfo().shape());
+  const auto cker_output_shape = convertShape(output_tensor->tensorInfo().shape());
+  const raw_type *input_ptr = reinterpret_cast<const raw_type *>(input_tensors->bufferRO());
+  const int32_t *indices_ptr = reinterpret_cast<const int32_t *>(indices_tensors->bufferRO());
+  raw_type *output_ptr = reinterpret_cast<raw_type *>(output_tensor->buffer());
+
+  nnfw::cker::Gather<raw_type>(cker_param, cker_input_shapes, input_ptr, cker_indices_shape,
+                               indices_ptr, cker_output_shape, output_ptr);
+}
+
+void invokeGather(const ExecEnv *env, const ir::Operation &node)
+{
+  const auto &gather_node = nnfw::misc::polymorphic_downcast<const ir::operation::Gather &>(node);
+  const int32_t axis_raw = gather_node.param().axis;
+
+  const auto input_index = node.getInputs().at(ir::operation::Gather::INPUT);
+  const auto indices_index = node.getInputs().at(ir::operation::Gather::INDICES);
+  const auto output_index = node.getOutputs().at(0);
+
+  const auto input_tensor = env->tensorAt(input_index);
+  const auto indices_tensor = env->tensorAt(indices_index);
+  const auto output_tensor = env->tensorAt(output_index);
+  const uint32_t axis = (axis_raw < 0) ? (axis_raw + input_tensor->num_dimensions()) : axis_raw;
+
+  const auto data_type = input_tensor->data_type();
+
+  switch (data_type)
+  {
+    case ir::DataType::FLOAT32:
+      invoke<float>(input_tensor, indices_tensor, output_tensor, axis);
+      break;
+    case ir::DataType::INT32:
+      invoke<int32_t>(input_tensor, indices_tensor, output_tensor, axis);
+      break;
+    case ir::DataType::QUANT8_ASYMM:
+      invoke<uint8_t>(input_tensor, indices_tensor, output_tensor, axis);
+      break;
+    default:
+      throw std::runtime_error{"Interp(Gather): NYI - Not supported type"};
+  }
+}
+
+} // namespace concat
+
+OpKernel *getGather()
+{
+  static OpKernel kernel = {prepareGather, invokeGather};
+  return &kernel;
+}
+
+} // namespace interp
+} // namespace exec
+} // namespace neurun
diff --git a/runtime/neurun/core/src/exec/interp/operations/InstanceNorm.cc b/runtime/neurun/core/src/exec/interp/operations/InstanceNorm.cc
new file mode 100644
index 000000000..d1623d53c
--- /dev/null
+++ b/runtime/neurun/core/src/exec/interp/operations/InstanceNorm.cc
@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2020 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <cker/operation/InstanceNorm.h>
+
+#include "OperationUtil.h"
+
+#include "exec/interp/Registration.h"
+#include "ir/operation/InstanceNorm.h"
+#include "misc/polymorphic_downcast.h"
+
+namespace neurun
+{
+namespace exec
+{
+namespace interp
+{
+namespace instancenorm
+{
+
+void prepareInstanceNorm(ExecEnv *env, const ir::Operation &node)
+{
+  const auto &instancenorm_node =
+      nnfw::misc::polymorphic_downcast<const ir::operation::InstanceNorm &>(node);
+
+  const auto input_index = node.getInputs().at(instancenorm_node.INPUT);
+  const auto output_index = node.getOutputs().at(0);
+  const auto input_tensor = env->tensorAt(input_index);
+
+  if (input_tensor->num_dimensions() != 4)
+  {
+    throw std::runtime_error{"Interp(InstanceNorm): Input should be 4D-tensor"};
+  }
+
+  // Output shape should be same with input
+  env->allocateIfNeeded(output_index, input_tensor->tensorInfo());
+
+  auto output_tensor = env->tensorAt(output_index);
+  UNUSED_RELEASE(output_tensor);
+
+  // Handle same ifm & ofm data type only
+  assert(input_tensor->data_type() == output_tensor->data_type());
+  assert(input_tensor->tensorInfo().shape() == output_tensor->tensorInfo().shape());
+}
+
+inline void setActivationParams(float min, float max, nnfw::cker::InstanceNormParams *params)
+{
+  params->float_activation_min = min;
+  params->float_activation_max = max;
+}
+
+void invoke(const ITensor *input_tensor, const ITensor *gamma_tensor, const ITensor *beta_tensor,
+            const ITensor *output_tensor, const ir::operation::InstanceNorm::Param &param)
+{
+  // Calculate
+  float activation_min, activation_max;
+  calculateActivationRange(param.activation, &activation_min, &activation_max);
+
+  nnfw::cker::InstanceNormParams cker_param;
+  cker_param.epsilon = param.epsilon;
+  cker_param.float_activation_min = activation_min;
+  cker_param.float_activation_max = activation_max;
+
+  const auto cker_input_shape = convertShape(input_tensor->tensorInfo().shape());
+  const auto cker_gamma_shape = convertShape(gamma_tensor->tensorInfo().shape());
+  const auto cker_beta_shape = convertShape(beta_tensor->tensorInfo().shape());
+  const auto cker_output_shape = convertShape(output_tensor->tensorInfo().shape());
+  const float *input_ptr = reinterpret_cast<const float *>(input_tensor->bufferRO());
+  const float *gamma_ptr = reinterpret_cast<const float *>(gamma_tensor->bufferRO());
+  const float *beta_ptr = reinterpret_cast<const float *>(beta_tensor->bufferRO());
+  float *output_ptr = reinterpret_cast<float *>(output_tensor->buffer());
+
+  nnfw::cker::InstanceNorm(cker_param, cker_input_shape, input_ptr, cker_gamma_shape, gamma_ptr,
+                           cker_beta_shape, beta_ptr, cker_output_shape, output_ptr);
+}
+
+void invokeInstanceNorm(const ExecEnv *env, const ir::Operation &node)
+{
+  const auto &instancenorm_node =
+      nnfw::misc::polymorphic_downcast<const ir::operation::InstanceNorm &>(node);
+
+  const auto input_index = node.getInputs().at(instancenorm_node.INPUT);
+  const auto gamma_index = node.getInputs().at(instancenorm_node.GAMMA);
+  const auto beta_index = node.getInputs().at(instancenorm_node.BETA);
+  const auto out_index = node.getOutputs().at(0);
+  const auto input_tensor = env->tensorAt(input_index);
+  const auto gamma_tensor = env->tensorAt(gamma_index);
+  const auto beta_tensor = env->tensorAt(beta_index);
+  const auto out_tensor = env->tensorAt(out_index);
+  const auto data_type = input_tensor->data_type();
+
+  if (data_type == ir::DataType::FLOAT32)
+  {
+    invoke(input_tensor, gamma_tensor, beta_tensor, out_tensor, instancenorm_node.param());
+  }
+  else
+  {
+    throw std::runtime_error{"NYI: Unsupported data type"};
+  }
+}
+} // namespace instancenorm
+
+OpKernel *getInstanceNorm()
+{
+  static OpKernel kernel = {instancenorm::prepareInstanceNorm, instancenorm::invokeInstanceNorm};
+  return &kernel;
+}
+
+} // namespace interp
+} // namespace exec
+} // namespace neurun
diff --git a/runtime/neurun/core/src/exec/interp/operations/Logistic.cc b/runtime/neurun/core/src/exec/interp/operations/Logistic.cc
new file mode 100644
index 000000000..2fc68ffd2
--- /dev/null
+++ b/runtime/neurun/core/src/exec/interp/operations/Logistic.cc
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <cker/operation/Logistic.h>
+
+#include "OperationUtil.h"
+
+#include "exec/interp/Registration.h"
+#include "ir/operation/Logistic.h"
+
+namespace neurun
+{
+namespace exec
+{
+namespace interp
+{
+namespace
+{
+
+void prepareLogistic(ExecEnv *env, const ir::Operation &node)
+{
+  const auto input_index = node.getInputs().at(0);
+  const auto output_index = node.getOutputs().at(0);
+
+  const auto input_tensor = env->tensorAt(input_index);
+
+  const auto output_info = env->graph().operands().at(output_index).info();
+
+  // Check shape and type lhs is same with rhs
+  // TODO Util function to compare TensorInfo
+  if (output_info.total_size() == 0)
+  {
+    throw std::runtime_error{"Interp(TConv): NYI unspecified output shape"};
+  }
+  else
+  {
+    env->allocateIfNeeded(output_index, output_info);
+  }
+
+  const auto output_tensor = env->tensorAt(output_index);
+  if (input_tensor->data_type() != output_tensor->data_type())
+  {
+    throw std::runtime_error{"Interp(Logistic): Invalid output type"};
+  }
+}
+
+void invoke(const ITensor *input_tensor, const ITensor *output_tensor)
+{
+  const auto input_buffer = input_tensor->bufferRO();
+  auto output_buffer = output_tensor->buffer();
+
+  const auto cker_input_shape = convertShape(input_tensor->tensorInfo().shape());
+  const auto cker_output_shape = convertShape(output_tensor->tensorInfo().shape());
+  const float *input_ptr = reinterpret_cast<const float *>(input_buffer);
+  float *output_ptr = reinterpret_cast<float *>(output_buffer);
+
+  nnfw::cker::Logistic(cker_input_shape, input_ptr, cker_output_shape, output_ptr);
+}
+
+void invokeLogistic(const ExecEnv *env, const ir::Operation &node)
+{
+  const auto input_index = node.getInputs().at(0);
+  const auto output_index = node.getOutputs().at(0);
+
+  const auto input_tensor = env->tensorAt(input_index);
+  const auto output_tensor = env->tensorAt(output_index);
+
+  const auto data_type = input_tensor->data_type();
+
+  if (data_type == ir::DataType::FLOAT32)
+  {
+    invoke(input_tensor, output_tensor);
+  }
+  else
+  {
+    throw std::runtime_error{"Interp(Logistic): NYI - Unsupported data type"};
+  }
+}
+} // namespace
+
+OpKernel *getLogistic()
+{
+  static OpKernel kernel = {prepareLogistic, invokeLogistic};
+  return &kernel;
+}
+
+} // namespace interp
+} // namespace exec
+} // namespace neurun
diff --git a/runtime/neurun/core/src/exec/interp/operations/MaxPool2D.cc b/runtime/neurun/core/src/exec/interp/operations/MaxPool2D.cc
new file mode 100644
index 000000000..3e1711d8e
--- /dev/null
+++ b/runtime/neurun/core/src/exec/interp/operations/MaxPool2D.cc
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <cker/operation/MaxPool.h>
+
+#include "OperationUtil.h"
+
+#include "exec/interp/Registration.h"
+#include "ir/operation/MaxPool2D.h"
+#include "util/Utils.h"
+#include "util/Padding.h"
+#include "util/ShapeInference.h"
+#include "misc/polymorphic_downcast.h"
+
+namespace neurun
+{
+namespace exec
+{
+namespace interp
+{
+namespace
+{
+
+void prepareMaxPool2D(ExecEnv *env, const ir::Operation &node)
+{
+  const auto in_index = node.getInputs().at(0);
+  const auto out_index = node.getOutputs().at(0);
+
+  const auto in_tensor = env->tensorAt(in_index);
+
+  assert(in_tensor->num_dimensions() == 4);
+  UNUSED_RELEASE(in_tensor);
+
+  const auto output_info = env->graph().operands().at(out_index).info();
+  if (output_info.total_size() == 0)
+  {
+    // Handle unspecified output shape
+    const auto &maxpool_node =
+        nnfw::misc::polymorphic_downcast<const ir::operation::MaxPool2D &>(node);
+    const auto infered_output_shapes =
+        shape_inference::inferMaxPoolShape(in_tensor->tensorInfo().shape(), maxpool_node.param());
+    env->allocateIfNeeded(out_index, {infered_output_shapes[0], output_info.typeInfo()});
+  }
+  else
+  {
+    env->allocateIfNeeded(out_index, output_info);
+  }
+
+  auto out_tensor = env->tensorAt(out_index);
+  UNUSED_RELEASE(out_tensor);
+
+  // Handle same ifm & ofm data type only
+  assert(in_tensor->data_type() == out_tensor->data_type());
+  assert(out_tensor->num_dimensions() == 4);
+}
+
+void invoke(const ITensor *in_tensor, const ITensor *out_tensor,
+            const ir::operation::MaxPool2D::Param &param)
+{
+  // TODO support NCHW frontend
+  const auto ifm_shape = in_tensor->tensorInfo().shape().asFeature(ir::Layout::NHWC);
+  const auto ofm_shape = out_tensor->tensorInfo().shape().asFeature(ir::Layout::NHWC);
+  const auto padding = neurun::util::calculatePadding(param.padding, ifm_shape, ofm_shape,
+                                                      param.stride, param.kw, param.kh);
+  // Calculate
+  nnfw::cker::PoolParams cker_param;
+  calculateActivationRange(param.activation, &cker_param.float_activation_min,
+                           &cker_param.float_activation_max);
+  cker_param.filter_width = param.kw;
+  cker_param.filter_height = param.kh;
+  cker_param.padding_values.width = padding.left;
+  cker_param.padding_values.height = padding.top;
+  cker_param.stride_width = param.stride.horizontal;
+  cker_param.stride_height = param.stride.vertical;
+
+  const auto in_shape = convertShape(in_tensor->tensorInfo().shape());
+  const auto out_shape = convertShape(out_tensor->tensorInfo().shape());
+  const float *in_ptr = reinterpret_cast<const float *>(in_tensor->bufferRO());
+  float *out_ptr = reinterpret_cast<float *>(out_tensor->buffer());
+
+  nnfw::cker::MaxPool(cker_param, in_shape, in_ptr, out_shape, out_ptr);
+}
+
+void invokeMaxPool2D(const ExecEnv *env, const ir::Operation &node)
+{
+  const auto &maxpool_node =
+      nnfw::misc::polymorphic_downcast<const ir::operation::MaxPool2D &>(node);
+
+  const auto in_index = node.getInputs().at(0);
+  const auto out_index = node.getOutputs().at(0);
+
+  const auto in_tensor = env->tensorAt(in_index);
+  const auto out_tensor = env->tensorAt(out_index);
+
+  const auto data_type = in_tensor->data_type();
+  if (data_type == ir::DataType::FLOAT32)
+  {
+    invoke(in_tensor, out_tensor, maxpool_node.param());
+  }
+  else
+  {
+    throw std::runtime_error{"NYI: Support float32 only"};
+  }
+}
+} // namespace
+
+OpKernel *getMaxPool2D()
+{
+  static OpKernel kernel = {prepareMaxPool2D, invokeMaxPool2D};
+  return &kernel;
+}
+
+} // namespace interp
+} // namespace exec
+} // namespace neurun
diff --git a/runtime/neurun/core/src/exec/interp/operations/OperationUtil.h b/runtime/neurun/core/src/exec/interp/operations/OperationUtil.h
new file mode 100644
index 000000000..5f4146bb8
--- /dev/null
+++ b/runtime/neurun/core/src/exec/interp/operations/OperationUtil.h
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_EXEC_INTERP_OPERATIONS_OPERATION_UTILS_H_
+#define __NEURUN_EXEC_INTERP_OPERATIONS_OPERATION_UTILS_H_
+
+#include "ir/Shape.h"
+#include "ir/InternalType.h"
+
+#include <cker/Shape.h>
+
+namespace neurun
+{
+namespace exec
+{
+namespace interp
+{
+
+inline nnfw::cker::Shape convertShape(const ir::Shape &shape)
+{
+  auto dimensions = std::vector<uint32_t>(shape.dims().begin(), shape.dims().end());
+
+  std::vector<int32_t> raw_shape;
+  raw_shape.resize(4);
+
+  for (uint32_t i = 0; i < 4; ++i)
+  {
+    if (i >= dimensions.size())
+    {
+      raw_shape[i] = 1;
+    }
+    else
+    {
+      raw_shape[i] = dimensions[i];
+    }
+  }
+
+  return nnfw::cker::GetShape(raw_shape);
+}
+
+inline nnfw::cker::Shape convertExtendShape(const ir::Shape &shape)
+{
+  auto dimensions = std::vector<uint32_t>(shape.dims().begin(), shape.dims().end());
+
+  std::vector<int32_t> raw_shape;
+  raw_shape.resize(4);
+  uint32_t start = 4 - dimensions.size();
+
+  for (uint32_t i = 0; i < 4; ++i)
+  {
+    if (i < start)
+    {
+      raw_shape[i] = 1;
+    }
+    else
+    {
+      raw_shape[i] = dimensions[i - start];
+    }
+  }
+
+  return nnfw::cker::GetShape(raw_shape);
+}
+
+template <typename T>
+void calculateActivationRange(ir::Activation activation, T *activation_min, T *activation_max)
+{
+  if (activation == ir::Activation::RELU)
+  {
+    *activation_min = 0;
+    *activation_max = std::numeric_limits<T>::max();
+  }
+  else if (activation == ir::Activation::RELU6)
+  {
+    *activation_min = 0;
+    *activation_max = 6;
+  }
+  else if (activation == ir::Activation::RELU1)
+  {
+    *activation_min = -1;
+    *activation_max = 1;
+  }
+  else if (activation == ir::Activation::NONE)
+  {
+    *activation_min = std::numeric_limits<T>::lowest();
+    *activation_max = std::numeric_limits<T>::max();
+  }
+  else
+  {
+    throw std::runtime_error{"Unsupported activation type"};
+  }
+}
+
+inline ir::Shape calcBroadcastShape(const ir::Shape &lhs, const ir::Shape &rhs, bool &success)
+{
+  int lhs_rank = lhs.rank();
+  int rhs_rank = rhs.rank();
+
+  int out_rank = (lhs_rank > rhs_rank ? lhs_rank : rhs_rank);
+  ir::Shape out_shape(out_rank);
+
+  int lhs_idim = lhs_rank - 1;
+  int rhs_idim = rhs_rank - 1;
+  success = true;
+  for (int out_idim = out_rank - 1; out_idim >= 0; out_idim--)
+  {
+    if (lhs_idim == -1 && rhs_idim == -1)
+    {
+      // invalid result
+      success = false;
+      break;
+    }
+
+    if (lhs_idim == -1)
+    {
+      out_shape.dim(out_idim) = rhs.dim(rhs_idim);
+      rhs_idim--;
+    }
+    else if (rhs_idim == -1)
+    {
+      out_shape.dim(out_idim) = lhs.dim(lhs_idim);
+      lhs_idim--;
+    }
+    else
+    {
+      if (lhs.dim(lhs_idim) == rhs.dim(rhs_idim))
+      {
+        out_shape.dim(out_idim) = lhs.dim(lhs_idim);
+        lhs_idim--;
+        rhs_idim--;
+      }
+      else if (lhs.dim(lhs_idim) == 1)
+      {
+        out_shape.dim(out_idim) = rhs.dim(rhs_idim);
+        lhs_idim--;
+        rhs_idim--;
+      }
+      else if (rhs.dim(rhs_idim) == 1)
+      {
+        out_shape.dim(out_idim) = lhs.dim(lhs_idim);
+        lhs_idim--;
+        rhs_idim--;
+      }
+      else
+      {
+        // invalid result
+        success = false;
+        break;
+      }
+    }
+  }
+
+  if (lhs_idim != -1 || rhs_idim != -1)
+  {
+    // invalid result
+    success = false;
+  }
+  return out_shape;
+}
+
+} // namespace interp
+} // namespace exec
+} // namespace neurun
+
+#endif // __NEURUN_EXEC_INTERP_OPERATIONS_OPERATION_UTILS_H_
diff --git a/runtime/neurun/core/src/exec/interp/operations/Pad.cc b/runtime/neurun/core/src/exec/interp/operations/Pad.cc
new file mode 100644
index 000000000..0c8267a90
--- /dev/null
+++ b/runtime/neurun/core/src/exec/interp/operations/Pad.cc
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <cker/operation/Pad.h>
+
+#include "OperationUtil.h"
+
+#include "exec/interp/Registration.h"
+#include "ir/operation/Pad.h"
+
+namespace neurun
+{
+namespace exec
+{
+namespace interp
+{
+namespace
+{
+
+void preparePad(ExecEnv *env, const ir::Operation &node)
+{
+  const auto input_index = node.getInputs().at(ir::operation::Pad::INPUT);
+  const auto output_index = node.getOutputs().at(0);
+
+  const auto input_tensor = env->tensorAt(input_index);
+
+  const auto output_info = env->graph().operands().at(output_index).info();
+
+  // Check shape and type lhs is same with rhs
+  // TODO Util function to compare TensorInfo
+  if (output_info.total_size() == 0)
+  {
+    throw std::runtime_error{"Interp(Pad): NYI unspecified output shape"};
+  }
+  else
+  {
+    env->allocateIfNeeded(output_index, output_info);
+  }
+
+  const auto output_tensor = env->tensorAt(output_index);
+  if (input_tensor->data_type() != output_tensor->data_type())
+  {
+    throw std::runtime_error{"Interp(Pad): Invalid output type"};
+  }
+}
+
+void invoke(const ITensor *input_tensor, const ITensor *pad_tensor, const ITensor *output_tensor)
+{
+  const auto input_buffer = input_tensor->bufferRO();
+  const auto pad_buffer = pad_tensor->bufferRO();
+  auto output_buffer = output_tensor->buffer();
+
+  int32_t pad_rank = pad_tensor->dimension(0);
+
+  const auto cker_input_shape = convertShape(input_tensor->tensorInfo().shape());
+  const auto cker_output_shape = convertShape(output_tensor->tensorInfo().shape());
+  const float *input_ptr = reinterpret_cast<const float *>(input_buffer);
+  const int32_t *pad_ptr = reinterpret_cast<const int32_t *>(pad_buffer);
+  float *output_ptr = reinterpret_cast<float *>(output_buffer);
+
+  nnfw::cker::Pad(pad_ptr, pad_rank, cker_input_shape, input_ptr, cker_output_shape, output_ptr,
+                  nullptr);
+}
+
+void invokePad(const ExecEnv *env, const ir::Operation &node)
+{
+  const auto input_index = node.getInputs().at(ir::operation::Pad::INPUT);
+  const auto pad_index = node.getInputs().at(ir::operation::Pad::PAD);
+  const auto output_index = node.getOutputs().at(0);
+
+  const auto input_tensor = env->tensorAt(input_index);
+  const auto pad_tensor = env->tensorAt(pad_index);
+  const auto output_tensor = env->tensorAt(output_index);
+
+  const auto data_type = input_tensor->data_type();
+
+  if (data_type == ir::DataType::FLOAT32)
+  {
+    invoke(input_tensor, pad_tensor, output_tensor);
+  }
+  else
+  {
+    throw std::runtime_error{"Interp(Pad): NYI - Unsupported data type"};
+  }
+}
+} // namespace
+
+OpKernel *getPad()
+{
+  static OpKernel kernel = {preparePad, invokePad};
+  return &kernel;
+}
+
+} // namespace interp
+} // namespace exec
+} // namespace neurun
diff --git a/runtime/neurun/core/src/exec/interp/operations/Reshape.cc b/runtime/neurun/core/src/exec/interp/operations/Reshape.cc
new file mode 100644
index 000000000..a160232de
--- /dev/null
+++ b/runtime/neurun/core/src/exec/interp/operations/Reshape.cc
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "exec/interp/Registration.h"
+
+namespace neurun
+{
+namespace exec
+{
+namespace interp
+{
+namespace
+{
+
+void prepare(ExecEnv *env, const ir::Operation &node)
+{
+  const auto in_index = node.getInputs().at(0);
+  const auto out_index = node.getOutputs().at(0);
+
+  // Unspecified shape is not supported in operation node spec now
+  const auto output_info = env->graph().operands().at(out_index).info();
+  env->allocateAndShareIfNeeded(out_index, output_info, in_index);
+
+  assert(output_info.total_size() == env->graph().operands().at(in_index).info().total_size());
+}
+
+void invoke(const ExecEnv *env, const ir::Operation &node)
+{
+  const auto in_index = node.getInputs().at(0);
+  const auto out_index = node.getOutputs().at(0);
+
+  if (env->tensorAt(in_index)->bufferRO() == env->tensorAt(out_index)->bufferRO())
+  {
+    // Same data
+    return;
+  }
+
+  const auto output_info = env->graph().operands().at(out_index).info();
+  memcpy(env->tensorAt(out_index)->buffer(), env->tensorAt(in_index)->bufferRO(),
+         output_info.total_size());
+}
+
+} // namespace {anonymous}
+
+OpKernel *getReshape()
+{
+  static OpKernel kernel = {prepare, invoke};
+  return &kernel;
+}
+
+} // namespace interp
+} // namespace exec
+} // namespace neurun
diff --git a/runtime/neurun/core/src/exec/interp/operations/SoftMax.cc b/runtime/neurun/core/src/exec/interp/operations/SoftMax.cc
new file mode 100644
index 000000000..91d98889f
--- /dev/null
+++ b/runtime/neurun/core/src/exec/interp/operations/SoftMax.cc
@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <cker/operation/SoftMax.h>
+
+#include "OperationUtil.h"
+
+#include "exec/interp/Registration.h"
+#include "ir/operation/Softmax.h"
+#include "misc/polymorphic_downcast.h"
+
+namespace neurun
+{
+namespace exec
+{
+namespace interp
+{
+namespace
+{
+
+void Softmax2D(const float *in, const int input_size, const int batch_size, const float beta,
+               float *out)
+{
+  assert(input_size > 0);
+
+  // For each batch
+  for (int b = 0; b < batch_size; b++)
+  {
+    // Find the max coeff.
+    float max_coeff = in[0];
+    for (int i = 1; i < input_size; i++)
+    {
+      if (in[i] > max_coeff)
+        max_coeff = in[i];
+    }
+
+    // Compute the normalized sum of exps.
+    float exp_sum = 0.0;
+    for (int i = 0; i < input_size; i++)
+    {
+      out[i] = std::exp((in[i] - max_coeff) * beta);
+      exp_sum += out[i];
+    }
+
+    // Divide by the sum of exps.
+    float reciprocal_sum_exp = 1.f / exp_sum;
+    for (int i = 0; i < input_size; i++)
+    {
+      out[i] *= reciprocal_sum_exp;
+    }
+
+    // Advance in and out pointers for the next batch.
+    in += input_size;
+    out += input_size;
+  }
+}
+
+void prepareSoftMax(ExecEnv *env, const ir::Operation &node)
+{
+  const auto in_index = node.getInputs().at(0);
+  const auto out_index = node.getOutputs().at(0);
+
+  const auto in_tensor = env->tensorAt(in_index);
+  UNUSED_RELEASE(in_tensor);
+
+  assert((in_tensor->num_dimensions() == 4) || (in_tensor->num_dimensions() == 2));
+
+  // Output shape should be same with input
+  // Output type is pre-defined in model
+  const auto output_shape = env->graph().operands().at(in_index).info().shape();
+  const auto output_type = env->graph().operands().at(out_index).info().typeInfo();
+
+  const ir::OperandInfo output_info{output_shape, output_type};
+  env->allocateIfNeeded(out_index, output_info);
+
+  auto out_tensor = env->tensorAt(out_index);
+  UNUSED_RELEASE(out_tensor);
+
+  // Check output shape is same with input
+  assert(out_tensor->num_dimensions() == out_tensor->num_dimensions());
+  for (uint32_t i = 0; i < in_tensor->num_dimensions(); i++)
+  {
+    assert(in_tensor->dimension(i) == out_tensor->dimension(i));
+  }
+}
+
+void invoke(const ITensor *in_tensor, const ITensor *out_tensor,
+            const ir::operation::Softmax::Param &param)
+{
+  const float *in_ptr = reinterpret_cast<const float *>(in_tensor->bufferRO());
+  float *out_ptr = reinterpret_cast<float *>(out_tensor->buffer());
+
+  float beta = param.beta;
+
+  if (in_tensor->num_dimensions() == 2)
+  {
+    uint32_t batch_size = in_tensor->dimension(0);
+    uint32_t input_size = in_tensor->dimension(1);
+
+    Softmax2D(in_ptr, input_size, batch_size, beta, out_ptr);
+  }
+  else if (in_tensor->num_dimensions() == 4)
+  {
+    const auto in_shape = convertShape(in_tensor->tensorInfo().shape());
+    const auto out_shape = convertShape(out_tensor->tensorInfo().shape());
+
+    nnfw::cker::SoftmaxParams cker_param;
+    cker_param.beta = beta;
+
+    nnfw::cker::Softmax(cker_param, in_shape, in_ptr, out_shape, out_ptr);
+  }
+  else
+  {
+    throw std::runtime_error{"Unsuported input dimension: support 2D or 4D"};
+  }
+}
+
+void invokeSoftMax(const ExecEnv *env, const ir::Operation &node)
+{
+  const auto &softmax_node = nnfw::misc::polymorphic_downcast<const ir::operation::Softmax &>(node);
+
+  const auto in_index = node.getInputs().at(0);
+  const auto out_index = node.getOutputs().at(0);
+
+  const auto in_tensor = env->tensorAt(in_index);
+  const auto out_tensor = env->tensorAt(out_index);
+
+  const auto in_data_type = in_tensor->data_type();
+  const auto out_data_type = out_tensor->data_type();
+  if ((in_data_type == ir::DataType::FLOAT32) && (out_data_type == ir::DataType::FLOAT32))
+  {
+    invoke(in_tensor, out_tensor, softmax_node.param());
+  }
+  else
+  {
+    throw std::runtime_error{"NYI: Support float32 only"};
+  }
+}
+
+} // namespace
+
+OpKernel *getSoftMax()
+{
+  static OpKernel kernel = {prepareSoftMax, invokeSoftMax};
+  return &kernel;
+}
+
+} // namespace interp
+} // namespace exec
+} // namespace neurun
diff --git a/runtime/neurun/core/src/exec/interp/operations/TransposeConv.cc b/runtime/neurun/core/src/exec/interp/operations/TransposeConv.cc
new file mode 100644
index 000000000..70b72c88d
--- /dev/null
+++ b/runtime/neurun/core/src/exec/interp/operations/TransposeConv.cc
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <cker/operation/TransposeConv.h>
+#include <misc/polymorphic_downcast.h>
+
+#include "OperationUtil.h"
+
+#include "exec/interp/Registration.h"
+#include "ir/operation/TransposeConv.h"
+#include "util/Padding.h"
+
+namespace neurun
+{
+namespace exec
+{
+namespace interp
+{
+namespace
+{
+
+void prepareTransposeConv(ExecEnv *env, const ir::Operation &node)
+{
+  const auto ifm_index = node.getInputs().at(ir::operation::TransposeConv::INPUT);
+  const auto ker_index = node.getInputs().at(ir::operation::TransposeConv::KERNEL);
+  const auto ofm_shape_index = node.getInputs().at(ir::operation::TransposeConv::OUTPUT_SHAPE);
+  const auto ofm_index = node.getOutputs().at(0);
+
+  const auto ifm_tensor = env->tensorAt(ifm_index);
+  const auto ker_tensor = env->tensorAt(ker_index);
+  const auto ofm_shape_tensor = env->tensorAt(ofm_shape_index);
+
+  assert(ifm_tensor->num_dimensions() == 4);
+  assert(ker_tensor->num_dimensions() == 4);
+  assert(ofm_shape_tensor->num_dimensions() == 1);
+
+  UNUSED_RELEASE(ifm_tensor);
+  UNUSED_RELEASE(ker_tensor);
+  UNUSED_RELEASE(ofm_shape_tensor);
+
+  const auto output_info = env->graph().operands().at(ofm_index).info();
+  if (output_info.total_size() == 0)
+  {
+    // TODO: Handle unspecified output shape
+    throw std::runtime_error{"Interp(TConv): NYI unspecified output shape"};
+  }
+  else
+  {
+    env->allocateIfNeeded(ofm_index, output_info);
+  }
+
+  auto ofm_tensor = env->tensorAt(ofm_index);
+  UNUSED_RELEASE(ofm_tensor);
+
+  // Handle same ifm & ofm data type only
+  if (ifm_tensor->data_type() != ofm_tensor->data_type())
+  {
+    throw std::runtime_error{"Interp(TConv): Different I/O data dype"};
+  }
+
+  if (ofm_tensor->num_dimensions() != 4)
+  {
+    throw std::runtime_error{"Interp(TConv): Invalid output rank"};
+  }
+}
+
+void invoke(const ITensor *ifm_tensor, const ITensor *ker_tensor, const ITensor *ofm_tensor,
+            const ir::operation::TransposeConv::Param &param)
+{
+  const auto ifm_shape = ifm_tensor->tensorInfo().shape().asFeature(ir::Layout::NHWC);
+  const auto ofm_shape = ofm_tensor->tensorInfo().shape().asFeature(ir::Layout::NHWC);
+  // Kernel format is [depth_out, kernel_height, kernel_width, depth_in].
+  const auto ker_shape = ker_tensor->tensorInfo().shape();
+  const auto ker_height = ker_shape.dim(1);
+  const auto ker_width = ker_shape.dim(2);
+  const auto padding = neurun::util::calculatePadding(param.padding, ofm_shape, ifm_shape,
+                                                      param.stride, ker_width, ker_height);
+
+  nnfw::cker::TransposeConvParams cker_param;
+  cker_param.padding_values.width = padding.left;
+  cker_param.padding_values.height = padding.top;
+  cker_param.stride_width = param.stride.horizontal;
+  cker_param.stride_height = param.stride.vertical;
+  cker_param.dilation_width_factor = 1;
+  cker_param.dilation_height_factor = 1;
+
+  const auto cker_ifm_shape = convertShape(ifm_tensor->tensorInfo().shape());
+  const auto cker_ker_shape = convertShape(ker_tensor->tensorInfo().shape());
+  const auto cker_ofm_shape = convertShape(ofm_tensor->tensorInfo().shape());
+  const float *ifm_ptr = reinterpret_cast<const float *>(ifm_tensor->bufferRO());
+  const float *ker_ptr = reinterpret_cast<const float *>(ker_tensor->bufferRO());
+  float *ofm_ptr = reinterpret_cast<float *>(ofm_tensor->buffer());
+
+  nnfw::cker::TransposeConv(cker_param, cker_ifm_shape, ifm_ptr, cker_ker_shape, ker_ptr,
+                            cker_ofm_shape, ofm_ptr);
+}
+
+void invokeTransposeConv(const ExecEnv *env, const ir::Operation &node)
+{
+  const auto &tconv_node =
+      nnfw::misc::polymorphic_downcast<const ir::operation::TransposeConv &>(node);
+
+  const auto ifm_index = node.getInputs().at(ir::operation::TransposeConv::INPUT);
+  const auto ker_index = node.getInputs().at(ir::operation::TransposeConv::KERNEL);
+  const auto ofm_index = node.getOutputs().at(0);
+
+  const auto ifm_tensor = env->tensorAt(ifm_index);
+  const auto ker_tensor = env->tensorAt(ker_index);
+  const auto ofm_tensor = env->tensorAt(ofm_index);
+
+  const auto data_type = ifm_tensor->data_type();
+  if (data_type == ir::DataType::FLOAT32)
+  {
+    invoke(ifm_tensor, ker_tensor, ofm_tensor, tconv_node.param());
+  }
+  else
+  {
+    throw std::runtime_error{"Interp(TConv): Support float32 only"};
+  }
+}
+
+} // namespace transposeconv
+
+OpKernel *getTransposeConv()
+{
+  static OpKernel kernel = {prepareTransposeConv, invokeTransposeConv};
+  return &kernel;
+}
+
+} // namespace interp
+} // namespace exec
+} // namespace neurun
diff --git a/runtime/neurun/core/src/exec/interp/operations/UnaryActivations.cc b/runtime/neurun/core/src/exec/interp/operations/UnaryActivations.cc
new file mode 100644
index 000000000..116806fc4
--- /dev/null
+++ b/runtime/neurun/core/src/exec/interp/operations/UnaryActivations.cc
@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) 2020 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <cmath>
+
+#include "OperationUtil.h"
+
+#include "exec/interp/Registration.h"
+
+#include "ir/operation/ReLU.h"
+#include "ir/operation/ReLU1.h"
+#include "ir/operation/ReLU6.h"
+#include "ir/operation/Tanh.h"
+
+namespace neurun
+{
+namespace exec
+{
+namespace interp
+{
+namespace
+{
+
+enum class ActivationType
+{
+  ReLU,
+  ReLU1,
+  ReLU6,
+  Tanh
+};
+
+void prepare(ExecEnv *env, const ir::Operation &node)
+{
+  const auto input_index = node.getInputs().at(0);
+  const auto output_index = node.getOutputs().at(0);
+
+  const auto input_tensor = env->tensorAt(input_index);
+
+  const auto output_info = env->graph().operands().at(output_index).info();
+  if (output_info.total_size() == 0)
+  {
+    // Output's shape and type is same with input
+    auto input_info = input_tensor->tensorInfo();
+    // We can handle already allocated (ex. model output)
+    env->allocateIfNeeded(output_index, input_info);
+  }
+  else
+  {
+    env->allocateIfNeeded(output_index, output_info);
+  }
+
+  const auto output_tensor = env->tensorAt(output_index);
+  // Check shape and type lhs is same with output
+  // TODO Util function to compare TensorInfo
+  if (input_tensor->data_type() != output_tensor->data_type())
+  {
+    throw std::runtime_error{"Interp(Activations): Invalid output type"};
+  }
+}
+
+template <ActivationType act_type>
+void evalFloat(const float *input_ptr, float *output_ptr, uint64_t num_elements)
+{
+  std::function<float(const float &)> fn = [](const float &) { return std::nanf(""); };
+  switch (act_type)
+  {
+    case ActivationType::ReLU:
+      fn = [](const float &in) { return std::max(0.f, in); };
+      break;
+    case ActivationType::ReLU1:
+      fn = [](const float &in) { return std::min(std::max(-1.f, in), 1.f); };
+      break;
+    case ActivationType::ReLU6:
+      fn = [](const float &in) { return std::min(std::max(0.f, in), 6.f); };
+      break;
+    case ActivationType::Tanh:
+      fn = [](const float &in) { return std::tanh(in); };
+      break;
+    default:
+      throw std::runtime_error{"Interp(Activations): NYI - Unsupported activation"};
+      break;
+  }
+
+  const float *input_end = input_ptr + num_elements;
+  for (; input_ptr < input_end; input_ptr++, output_ptr++)
+  {
+    *output_ptr = fn(*input_ptr);
+  }
+}
+
+template <ActivationType act_type> void invoke(const ExecEnv *env, const ir::Operation &node)
+{
+  const auto input_index = node.getInputs().at(0);
+  const auto output_index = node.getOutputs().at(0);
+
+  // Check lhs shape is same with rhs (with broadcast)
+  const auto input_tensor = env->tensorAt(input_index);
+  const auto output_tensor = env->tensorAt(output_index);
+
+  const auto data_type = input_tensor->data_type();
+  if (data_type == ir::DataType::FLOAT32)
+  {
+    uint64_t elements = input_tensor->num_elements();
+    const float *input_start = reinterpret_cast<const float *>(input_tensor->bufferRO());
+    float *out = reinterpret_cast<float *>(output_tensor->buffer());
+
+    evalFloat<act_type>(input_start, out, elements);
+  }
+  else
+  {
+    throw std::runtime_error{"Interp(ReLU6): NYI - Support float only"};
+  }
+}
+
+} // namespace
+
+OpKernel *getReLU()
+{
+  static OpKernel kernel = {prepare, invoke<ActivationType::ReLU>};
+  return &kernel;
+}
+
+OpKernel *getReLU1()
+{
+  static OpKernel kernel = {prepare, invoke<ActivationType::ReLU1>};
+  return &kernel;
+}
+
+OpKernel *getReLU6()
+{
+  static OpKernel kernel = {prepare, invoke<ActivationType::ReLU6>};
+  return &kernel;
+}
+
+OpKernel *getTanh()
+{
+  static OpKernel kernel = {prepare, invoke<ActivationType::Tanh>};
+  return &kernel;
+}
+
+} // namespace interp
+} // namespace exec
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/Graph.cc b/runtime/neurun/core/src/ir/Graph.cc
new file mode 100644
index 000000000..a84ebb68b
--- /dev/null
+++ b/runtime/neurun/core/src/ir/Graph.cc
@@ -0,0 +1,551 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/Graph.h"
+
+#include <algorithm>
+#include <bitset>
+#include <sstream>
+
+#include "util/logging.h"
+#include "verifier/Verifier.h"
+#include "cpp14/memory.h"
+#include "ir/operation/LowerInfo.h"
+#include "ir/operand/LowerInfo.h"
+#include "ir/operand/PermuteFactor.h"
+#include "ir/GraphIterator.h"
+#include "operand/Shape4DConvert.h"
+#include "compiler/BackendResolver.h"
+#include "backend/IConfig.h"
+#include "pass/ConstantInsertionPass.h"
+#include "pass/PermutationInsertionPass.h"
+#include "pass/PermutationEliminationPass.h"
+#include "pass/PermutationOperationPass.h"
+
+namespace neurun
+{
+namespace ir
+{
+
+Graph::Graph() = default;
+
+Graph::~Graph(void) = default;
+
+OperandIndex Graph::addOperand(const Shape &shape, const TypeInfo &type)
+{
+  return _operands.emplace(shape, type);
+}
+
+OperationIndex Graph::addOperation(std::unique_ptr<Operation> &&node)
+{
+  assert(isBuildingPhase());
+  return _operations.push(std::move(node));
+}
+
+void Graph::setOperandValue(const OperandIndex &ind, std::unique_ptr<Data> &&data)
+{
+  assert(isBuildingPhase());
+  assert(_operands.exist(ind));
+  _operands.at(ind).data(std::move(data));
+}
+
+void Graph::addInput(const OperandIndex &ind)
+{
+  assert(isBuildingPhase());
+  _inputs.append(ind);
+}
+
+void Graph::addOutput(const OperandIndex &ind)
+{
+  assert(isBuildingPhase());
+  _outputs.append(ind);
+}
+
+void Graph::finishBuilding(void)
+{
+  assert(isBuildingPhase());
+  _phase = Phase::MODEL;
+
+  // Initialize operand use-def
+  initializeUseDef();
+
+  // Call graph verifications for the MODEL phase
+  {
+    assert(verifier::DAGChecker().verify(*this));
+    assert(verifier::EdgeConsistencyChecker().verify(*this));
+  }
+}
+
+void Graph::lower(void)
+{
+  assert(_phase == Phase::MODEL);
+
+  _op_seqs = nnfw::cpp14::make_unique<Subgraphs>();
+
+  // Lower
+  {
+    // operand::LowerInfo holder
+    OperandIndexMap<std::unique_ptr<operand::LowerInfo>> operands_lower_info;
+
+    _operands.iterate([&](const OperandIndex &index, const Operand &object) {
+      operands_lower_info[index] =
+          nnfw::cpp14::make_unique<operand::LowerInfo>(operand::asShape4D(object.shape()));
+    });
+
+    _lower_info_map = nnfw::cpp14::make_unique<LowerInfoMap>();
+
+    // Make subgraphs while checking whether a node can be merged into a op_seq.
+    makeSubgraphs(operands_lower_info);
+
+    _op_seqs->iterate([&](const SubgraphIndex &, OpSequence &subg) {
+      assert(subg.operations().size() > 0);
+      std::reverse(std::begin(subg.operations()), std::end(subg.operations()));
+    });
+
+    _op_seqs->dump("merged and sorted operations without permutation");
+
+    pass::ConstantInsertionPass ci_pass(*this);
+    ci_pass.run();
+
+    // Set LowerInfo for each operand from the operand::LowerInfo holder
+    manipulateLowerInfo(operands_lower_info);
+
+    dumpLowerInfo();
+  }
+
+  // Run Permutation Passes
+  {
+    pass::PermutationOperationPass po_pass(*this);
+    po_pass.run();
+
+    pass::PermutationInsertionPass pi_pass(*this);
+    pi_pass.run();
+    // Implemented code no longer works.
+    // pass::PermutationEliminationPass pe_pass(*this);
+    // pe_pass.run();
+
+    // TODO merge perm subgraphs if possible
+    _op_seqs->dump("merged and sorted operations with permutation");
+  }
+
+  // Graph verifications for the LOWERED phase
+  {
+    assert(verifier::DAGChecker().verify(*this));
+    assert(verifier::EdgeConsistencyChecker().verify(*this));
+  }
+}
+
+void Graph::initializeUseDef()
+{
+  operations().iterate([&](const OperationIndex &index, const Operation &node) -> void {
+    auto outputs = node.getOutputs();
+    for (auto output : outputs)
+    {
+      operands().at(output).appendDef(index);
+    }
+
+    auto inputs = node.getInputs();
+    for (auto input : inputs)
+    {
+      operands().at(input).appendUse(index);
+    }
+  });
+}
+
+const operation::LowerInfo *Graph::getLowerInfo(const SubgraphIndex &subg_index) const
+{
+  if (!_lower_info_map)
+    return nullptr;
+  auto itr = _lower_info_map->operation.find(subg_index);
+  if (itr == _lower_info_map->operation.end())
+    return nullptr;
+  return itr->second.get();
+}
+
+void Graph::setLowerInfo(const SubgraphIndex &subg_index,
+                         std::unique_ptr<operation::LowerInfo> &&lower_info)
+{
+  assert(_lower_info_map);
+  _lower_info_map->operation.insert(std::make_pair(subg_index, std::move(lower_info)));
+}
+
+void Graph::removeLowerInfo(const SubgraphIndex &subg_index)
+{
+  auto &subg_lower_info = _lower_info_map->operation;
+  assert(subg_lower_info.find(subg_index) != subg_lower_info.end());
+  for (auto it = subg_lower_info.begin(); it != subg_lower_info.end(); ++it)
+  {
+    if (it->first == subg_index)
+    {
+      subg_lower_info.erase(it);
+      break;
+    }
+  }
+}
+
+const operand::LowerInfo *Graph::getLowerInfo(const OperandIndex &index) const
+{
+  if (!_lower_info_map)
+    return nullptr;
+  auto itr = _lower_info_map->operand.find(index);
+  if (itr == _lower_info_map->operand.end())
+    return nullptr;
+  return itr->second.get();
+}
+
+operand::LowerInfo *Graph::getLowerInfo(const OperandIndex &index)
+{
+  if (!_lower_info_map)
+    return nullptr;
+  auto itr = _lower_info_map->operand.find(index);
+  if (itr == _lower_info_map->operand.end())
+    return nullptr;
+  return itr->second.get();
+}
+
+void Graph::setLowerInfo(const OperandIndex &index,
+                         std::unique_ptr<operand::LowerInfo> &&lower_info)
+{
+  assert(_lower_info_map);
+  _lower_info_map->operand.insert(std::make_pair(index, std::move(lower_info)));
+}
+
+void Graph::removeLowerInfo(const OperandIndex &index) { _lower_info_map->operand.erase(index); }
+
+void Graph::makeSubgraphs(OperandIndexMap<std::unique_ptr<operand::LowerInfo>> &operands_lower_info)
+{
+  // if SUBG_MAX_NODE == 0, no limit on nodes of a op_seq
+  const int subg_max_node = util::getConfigInt(util::config::SUBG_MAX_NODE);
+  assert(subg_max_node >= 0);
+
+  bool is_profiling = util::getConfigBool(util::config::PROFILING_MODE);
+  OpSequence *subg = nullptr;
+  SubgraphIndex subg_index;
+
+  // NOTE: The below method appends nodes while making one op_seq if needed. If something better
+  // ways, happy to update this code.
+  PostDfsConstIterator{}.iterate(*this, [&](const OperationIndex &node_index,
+                                            const Operation &node) {
+    // LowerInfo for in/output operands
+    auto backend = _backend_resolver->getBackend(node_index);
+
+    // TODO How to get frontend layout of this node from IR
+    auto frontend_layout = Layout::NHWC;
+    auto backend_layout = frontend_layout;
+
+    // The layout of each backend should be set at another place
+    // TODO Change setting layout of each backend at another place
+    // TODO Remove getting id of backend
+    if (backend->config()->id() == "acl_cl" || backend->config()->id() == "acl_neon")
+    {
+      const std::string acl_layout_str = util::getConfigString(util::config::ACL_LAYOUT);
+      if (acl_layout_str == "NHWC")
+      {
+        backend_layout = Layout::NHWC;
+      }
+      else if (acl_layout_str == "NCHW")
+      {
+        backend_layout = Layout::NCHW;
+      }
+    }
+    else if (backend->config()->id() == "srcn")
+    {
+      const std::string ncnn_layout_str = util::getConfigString(util::config::NCNN_LAYOUT);
+      if (ncnn_layout_str == "NHWC")
+      {
+        backend_layout = Layout::NHWC;
+      }
+      else if (ncnn_layout_str == "NCHW")
+      {
+        backend_layout = Layout::NCHW;
+      }
+    }
+    else if (backend->config()->id() == "cpu")
+    {
+      backend_layout = Layout::NHWC;
+    }
+
+    for (auto operand : node.getInputs())
+    {
+      auto &&lower_info = operands_lower_info.at(operand);
+      lower_info->addUsePermuteFactor(operand::PermuteFactor{backend, backend_layout});
+    }
+    for (auto operand : node.getOutputs())
+    {
+      auto &&lower_info = operands_lower_info.at(operand);
+      lower_info->addDefPermuteFactor(operand::PermuteFactor{backend, backend_layout});
+    }
+
+    bool new_subg =
+        (subg == nullptr ||
+         (subg_max_node != 0 && subg->operations().size() >= static_cast<size_t>(subg_max_node)));
+
+    // for profiling each op_seq must contain just one node,
+    // so that we can measure a node separately
+    if (new_subg || is_profiling || !mergeable(subg_index, node_index, backend_layout))
+    {
+      auto new_subg_index = appendFreshSingleOpSubgraph(node_index, node, frontend_layout);
+
+      // OpSequence LowerInfo
+      setLowerInfo(new_subg_index,
+                   nnfw::cpp14::make_unique<operation::LowerInfo>(backend, backend_layout));
+
+      subg_index = new_subg_index;
+      subg = &(_op_seqs->at(new_subg_index));
+
+      VERBOSE(Lower) << "SUBG#" << subg_index.value() << " is created for "
+                     << "NODE#" << node_index.value() << "(" << node.name() << ")" << std::endl;
+    }
+    else
+    {
+      subg->appendOperation(node_index, node);
+      subg->setInputs(node.getInputs());
+
+      VERBOSE(Lower) << "SUBG#" << subg_index.value() << " merges "
+                     << "NODE#" << node_index.value() << "(" << node.name() << ")" << std::endl;
+    }
+  });
+}
+
+void Graph::manipulateLowerInfo(
+    OperandIndexMap<std::unique_ptr<operand::LowerInfo>> &operands_lower_info)
+{
+  const auto default_backend = backend::BackendManager::get().getDefault();
+  for (auto index : _inputs)
+  {
+    // Pick just any one from the uses, here the first one is chosen
+    // For the other uses, Permute operations will be inserted later
+    auto &&lower_info = operands_lower_info.at(index);
+    assert(lower_info->use_factors().size() > 0);
+    lower_info->addDefPermuteFactor(*lower_info->use_factors().begin());
+  }
+  for (auto index : _outputs)
+  {
+    auto &&lower_info = operands_lower_info.at(index);
+    if (_operands.at(index).isConstant())
+    {
+      lower_info->addDefPermuteFactor(operand::PermuteFactor{
+          default_backend,
+          Layout::NHWC // TODO Get frontend layout of this node from IR
+      });
+    }
+  }
+
+  // Set LowerInfo for each operand from the operand::LowerInfo holder
+  _operands.iterate([&](const OperandIndex &index, Operand &) {
+    setLowerInfo(index, std::move(operands_lower_info[index]));
+  });
+}
+
+void Graph::dumpLowerInfo()
+{
+  if (::neurun::util::logging::ctx.enabled() == false)
+    return;
+
+  std::map<uint32_t, std::string> dumps;
+
+  _operands.iterate([&](const OperandIndex &index, Operand &object) {
+    std::stringstream sstream;
+    if (!getLowerInfo(index)->def_factors().empty() || !getLowerInfo(index)->use_factors().empty())
+    {
+      auto factors_to_string = [](const operand::PermuteFactorSet &factors) {
+        std::string str;
+        for (auto factor : factors)
+        {
+          str += factor.backend()->config()->id();
+          str += "(" + to_string(factor.layout()) + ")";
+          str += " ";
+        }
+        return "{ " + str + "}";
+      };
+
+      auto operation_index_to_string = [](const OperationIndexList &operations) {
+        std::string str;
+        for (auto op : operations.list())
+        {
+          str += std::to_string(op.value());
+          str += " ";
+        }
+        return "{ " + str + "}";
+      };
+
+      const auto lower_info = getLowerInfo(index);
+      const auto &shape = object.shape();
+      const auto &lower_shape = lower_info->shape();
+      std::string def_ops = operation_index_to_string(object.getDef());
+      std::string use_ops = operation_index_to_string(object.getUses());
+      std::string def_layouts = factors_to_string(lower_info->def_factors());
+      std::string use_layouts = factors_to_string(lower_info->use_factors());
+      sstream << "Operand #" << index.value() << " LowerInfo" << std::endl;
+      sstream << "  - Shape           : { " << (shape.rank() > 0 ? shape.dim(0) : 0) << " "
+              << (shape.rank() > 1 ? shape.dim(1) : 0) << " "
+              << (shape.rank() > 2 ? shape.dim(2) : 0) << " "
+              << (shape.rank() > 3 ? shape.dim(3) : 0) << " "
+              << "}" << std::endl;
+      sstream << "  - Def Operations  : " << def_ops << std::endl;
+      sstream << "  - Use Operations  : " << use_ops << std::endl;
+      sstream << "  - Lower Info" << std::endl;
+      sstream << "    - 4D Shape (NHWC) : { " << lower_shape.n() << " " << lower_shape.h() << " "
+              << lower_shape.w() << " " << lower_shape.c() << " "
+              << "}" << std::endl;
+      sstream << "    - Def Backends    : " << def_layouts << std::endl;
+      sstream << "    - Use Backends    : " << use_layouts << std::endl;
+    }
+    dumps.emplace(index.value(), sstream.str());
+  });
+
+  for (const auto &e : dumps)
+  {
+    if (!e.second.empty())
+    {
+      VERBOSE(Lower) << e.second;
+    }
+  }
+}
+
+bool Graph::mergeable(const SubgraphIndex &subg_index, const OperationIndex &node_index,
+                      Layout layout)
+{
+  // Are they mergeable?
+  // 1. the same backend id and layout?
+  // 2. Is op_seq or node branched?
+  // 3. if 1 is true, the subg and a node are connected?
+  const auto &subg = _op_seqs->at(subg_index);
+  const auto &node = _operations.at(node_index);
+
+  // The same backend id and layout?
+  {
+    const auto subg_backend_layout = getLowerInfo(subg_index)->layout();
+    const auto &subg_backend_id = getLowerInfo(subg_index)->backend()->config()->id();
+    const auto &node_backend_id = _backend_resolver->getBackend(node_index)->config()->id();
+    VERBOSE(Lower) << "SUBG#" << subg_index.value() << " { " << subg_backend_id << "("
+                   << to_string(subg_backend_layout) << ") } "
+                   << " NODE#" << node_index.value() << " (" << node.name() << ") { "
+                   << node_backend_id << "(" << to_string(layout) << ") } " << std::endl;
+    if (subg_backend_id != node_backend_id || subg_backend_layout != layout)
+      return false;
+  }
+
+  // Branched?
+  {
+    std::unordered_set<OperationIndex> branched_set;
+
+    // Check for branching up
+    const auto &inputs = subg.getInputs();
+    for (const auto &input : inputs)
+    {
+      const auto &input_obj = _operands.at(input);
+      for (const auto &def : input_obj.getDef().list())
+      {
+        branched_set.insert(def);
+        if (branched_set.size() > 1)
+        {
+          return false;
+        }
+      }
+    }
+    branched_set.clear();
+
+    // Check for branching down
+    const auto &outputs = node.getOutputs();
+    for (const auto &output : outputs)
+    {
+      const auto &output_obj = _operands.at(output);
+      for (const auto &use : output_obj.getUses().list())
+      {
+        branched_set.insert(use);
+        if (branched_set.size() > 1)
+        {
+          return false;
+        }
+      }
+    }
+  }
+
+  // Connected?
+  // an input of one node is an output of the other node? or vice-versa?
+  {
+    const auto &node_inputs = node.getInputs();
+    const auto &node_outputs = node.getOutputs();
+
+    // subg's operations are in order so that we just check the first and the last
+    std::vector<Element> subg_ops{subg.operations()[0]};
+    if (subg.operations().size() > 1)
+      subg_ops.emplace_back(subg.operations()[subg.operations().size() - 1]);
+
+    for (const auto &elem : subg_ops)
+    {
+      const auto &n_index = elem.index;
+      const auto &n = *elem.node;
+
+      // node's output == subg's input?
+      const auto &n_inputs = n.getInputs();
+      for (auto input : n_inputs)
+      {
+        if (node_outputs.contains(input))
+        {
+          VERBOSE(Lower) << "SUBG#" << subg_index.value() << " 's NODE#" << n_index.value() << "("
+                         << n.name() << ") is connected to NODE#" << node_index.value() << "("
+                         << node.name() << ")" << std::endl;
+          return true;
+        }
+      }
+
+      // node's input == subg's output?
+      const auto &n_outputs = n.getOutputs();
+      for (auto output : n_outputs)
+      {
+        if (node_inputs.contains(output))
+        {
+          VERBOSE(Lower) << "SUBG#" << subg_index.value() << " 's NODE#" << n_index.value() << " ("
+                         << n.name() << ") is connected to NODE#" << node_index.value()
+                         << std::endl;
+          return true;
+        }
+      }
+    }
+
+    VERBOSE(Lower) << "SUBG#" << subg_index.value() << " is not connected to NODE#"
+                   << node_index.value() << "(" << node.name() << ")" << std::endl;
+  }
+
+  return false;
+}
+
+SubgraphIndex Graph::appendFreshSingleOpSubgraph(const OperationIndex &node_index,
+                                                 const Operation &node, Layout layout)
+{
+  // Create a fresh op_seq with one operation, and append it to subgraphs
+  // Create a fresh op_seq
+  auto subg = nnfw::cpp14::make_unique<OpSequence>(layout);
+
+  // Add an operation
+  subg->appendOperation(node_index, node);
+
+  // Update input/output
+  subg->setOutputs(node.getOutputs());
+  subg->setInputs(node.getInputs());
+
+  return _op_seqs->emplace(std::move(subg));
+}
+
+void Graph::setBackendResolver(std::unique_ptr<compiler::BackendResolver> &&br)
+{
+  _backend_resolver = std::move(br);
+}
+
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/GraphIterator.cc b/runtime/neurun/core/src/ir/GraphIterator.cc
new file mode 100644
index 000000000..ce20787ae
--- /dev/null
+++ b/runtime/neurun/core/src/ir/GraphIterator.cc
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2020 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "GraphIterator.h"
+
+#include "ir/OperationIndexMap.h"
+#include "ir/Graph.h"
+
+namespace neurun
+{
+namespace ir
+{
+
+// Explicit instantiations to have implementation in the source file.
+
+template class DefaultIterator<true>;
+template class DefaultIterator<false>;
+
+template class PostDfsIterator<true>;
+template class PostDfsIterator<false>;
+
+//
+// Graph::DefaultIterator
+//
+
+template <bool is_const>
+void DefaultIterator<is_const>::iterate(GraphRef graph, const IterFn &fn) const
+{
+  graph.operations().iterate(
+      [&](const OperationIndex &index, NodeRef node) -> void { fn(index, node); });
+}
+
+//
+// Graph::PostDfsIterator
+//
+
+template <bool is_const>
+void PostDfsIterator<is_const>::iterate(GraphRef graph, const IterFn &fn) const
+{
+  assert(!graph.isBuildingPhase()); // Restrict iteration condition
+
+  OperationIndexMap<bool> visited;
+  graph.operations().iterate([&](const OperationIndex &index, NodeRef) { visited[index] = false; });
+
+  std::function<void(const OperationIndex &, NodeRef)> dfs_recursive =
+      [&](const OperationIndex &index, NodeRef node) -> void {
+    if (visited[index])
+      return;
+    visited[index] = true;
+
+    for (auto output : node.getOutputs())
+    {
+      const auto &operand = graph.operands().at(output);
+      for (const auto &use : operand.getUses().list())
+      {
+        dfs_recursive(use, graph.operations().at(use));
+      }
+    }
+
+    fn(index, node);
+  };
+
+  graph.operations().iterate(dfs_recursive);
+
+  // All of the operations(nodes) must have been visited.
+  assert(std::all_of(visited.begin(), visited.end(),
+                     [](const std::pair<const OperationIndex, bool> &v) { return v.second; }));
+}
+
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/GraphIterator.h b/runtime/neurun/core/src/ir/GraphIterator.h
new file mode 100644
index 000000000..a5bf1c323
--- /dev/null
+++ b/runtime/neurun/core/src/ir/GraphIterator.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2020 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_GRAPH_ITERATOR_H__
+#define __NEURUN_IR_GRAPH_ITERATOR_H__
+
+#include <type_traits>
+
+#include "ir/Index.h"
+
+namespace neurun
+{
+namespace ir
+{
+
+class Graph;
+class Operation;
+
+template <bool is_const> class Iterator
+{
+public:
+  using GraphRef = typename std::conditional<is_const, const Graph &, Graph &>::type;
+  using IndexRef = const OperationIndex &;
+  using NodeRef = typename std::conditional<is_const, const Operation &, Operation &>::type;
+  using IterFn = std::function<void(IndexRef, NodeRef)>;
+
+public:
+  virtual ~Iterator() = default;
+  virtual void iterate(GraphRef graph, const IterFn &fn) const = 0;
+};
+
+template <bool is_const = false> class DefaultIterator final : public Iterator<is_const>
+{
+public:
+  using GraphRef = typename Iterator<is_const>::GraphRef;
+  using IndexRef = typename Iterator<is_const>::IndexRef;
+  using NodeRef = typename Iterator<is_const>::NodeRef;
+  using IterFn = typename Iterator<is_const>::IterFn;
+
+public:
+  void iterate(GraphRef graph, const IterFn &fn) const;
+};
+using DefaultConstIterator = DefaultIterator<true>;
+
+template <bool is_const = false> class PostDfsIterator final : public Iterator<is_const>
+{
+public:
+  using GraphRef = typename Iterator<is_const>::GraphRef;
+  using IndexRef = typename Iterator<is_const>::IndexRef;
+  using NodeRef = typename Iterator<is_const>::NodeRef;
+  using IterFn = typename Iterator<is_const>::IterFn;
+
+public:
+  void iterate(GraphRef graph, const IterFn &fn) const;
+};
+using PostDfsConstIterator = PostDfsIterator<true>;
+
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_GRAPH_ITERATOR_H__
diff --git a/runtime/neurun/core/src/ir/LayoutSet.cc b/runtime/neurun/core/src/ir/LayoutSet.cc
new file mode 100644
index 000000000..025ba45dc
--- /dev/null
+++ b/runtime/neurun/core/src/ir/LayoutSet.cc
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "LayoutSet.h"
+
+namespace neurun
+{
+namespace ir
+{
+
+LayoutSet::LayoutSet(std::initializer_list<Layout> layouts)
+{
+  for (auto layout : layouts)
+  {
+    _set.insert(layout);
+  }
+}
+
+LayoutSet LayoutSet::operator|(const LayoutSet &other) const
+{
+  auto ret = *this;
+  for (auto layout : other)
+  {
+    ret.add(layout);
+  }
+  return ret;
+}
+
+LayoutSet LayoutSet::operator&(const LayoutSet &other) const
+{
+  LayoutSet ret;
+  for (auto layout : other)
+  {
+    if (contains(layout))
+    {
+      ret.add(layout);
+    }
+  }
+  return ret;
+}
+
+LayoutSet LayoutSet::operator-(const LayoutSet &other) const
+{
+  auto ret = *this;
+  for (auto layout : other)
+  {
+    ret.remove(layout);
+  }
+  return ret;
+}
+
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/LayoutSet.h b/runtime/neurun/core/src/ir/LayoutSet.h
new file mode 100644
index 000000000..e38ef3ce2
--- /dev/null
+++ b/runtime/neurun/core/src/ir/LayoutSet.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_IR_LAYOUT_SET_H__
+#define __NEURUN_IR_LAYOUT_SET_H__
+
+#include <initializer_list>
+#include <unordered_set>
+
+#include "ir/Layout.h"
+
+namespace neurun
+{
+namespace ir
+{
+
+class LayoutSet
+{
+public:
+  LayoutSet() = default;
+  LayoutSet(std::initializer_list<Layout> layouts);
+
+public:
+  void add(const Layout &layout) { _set.insert(layout); }
+  void remove(const Layout &layout) { _set.erase(layout); }
+  uint32_t size() const { return static_cast<uint32_t>(_set.size()); }
+  bool contains(const Layout &layout) const { return _set.find(layout) != _set.end(); }
+
+public:
+  LayoutSet operator|(const LayoutSet &other) const; // Union
+  LayoutSet operator&(const LayoutSet &other) const; // Intersect
+  LayoutSet operator-(const LayoutSet &other) const; // Minus
+
+public:
+  std::unordered_set<Layout>::const_iterator begin() const { return _set.begin(); }
+  std::unordered_set<Layout>::const_iterator end() const { return _set.end(); }
+
+private:
+  std::unordered_set<Layout> _set;
+};
+
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_IR_LAYOUT_SET_H__
diff --git a/runtime/neurun/core/src/ir/OpCode.cc b/runtime/neurun/core/src/ir/OpCode.cc
new file mode 100644
index 000000000..e6552a275
--- /dev/null
+++ b/runtime/neurun/core/src/ir/OpCode.cc
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/OpCode.h"
+
+#include <unordered_map>
+
+namespace neurun
+{
+namespace ir
+{
+
+const char *toString(OpCode opcode)
+{
+  static const std::unordered_map<OpCode, const char *> map{{OpCode::Invalid, "Invalid"},
+#define OP(Name) {OpCode::Name, #Name},
+#include "ir/Operations.lst"
+#undef OP
+                                                            {OpCode::COUNT, "COUNT"}};
+  return map.at(opcode);
+}
+
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/OpSequence.cc b/runtime/neurun/core/src/ir/OpSequence.cc
new file mode 100644
index 000000000..13a6cbe27
--- /dev/null
+++ b/runtime/neurun/core/src/ir/OpSequence.cc
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/OpSequence.h"
+#include "ir/OperationVisitor.h"
+#include <sstream>
+
+namespace neurun
+{
+namespace ir
+{
+
+OpSequence::OpSequence(Layout layout) : _layout{layout}
+{
+  // DO NOTHING
+}
+
+void OpSequence::accept(OperationVisitor &v) const { v.visit(*this); }
+
+// TODO: Impl Dumper instead of this method
+std::string OpSequence::getStr() const
+{
+  // "  OpSequence IN(xx,xx,xx) -> { op0, op1, op2 } -> OUT(yy,yy,yy)"
+  std::stringstream ss;
+  ss << "  OpSequence IN(";
+  for (const auto &index : getInputs())
+  {
+    ss << " " << index.value();
+  }
+  ss << " ) -> {";
+  for (const auto &elem : _operations)
+  {
+    ss << " " << elem.index.value() << "(" << elem.node->name() << ")";
+  }
+  ss << " } -> OUT(";
+  for (const auto &index : getOutputs())
+  {
+    ss << " " << index.value();
+  }
+  ss << " )";
+  return ss.str();
+}
+
+void OpSequence::remove(const OperationIndex &index)
+{
+  assert(exist(index));
+  for (auto it = _operations.cbegin(); it != _operations.cend(); ++it)
+  {
+    if (it->index == index)
+    {
+      _operations.erase(it);
+      break;
+    }
+  }
+}
+
+bool OpSequence::exist(const OperationIndex &index) const
+{
+  for (const auto &element : _operations)
+  {
+    if (element.index == index)
+    {
+      return true;
+    }
+  }
+  return false;
+}
+
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/Operand.cc b/runtime/neurun/core/src/ir/Operand.cc
new file mode 100644
index 000000000..335dd17b9
--- /dev/null
+++ b/runtime/neurun/core/src/ir/Operand.cc
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/Operand.h"
+
+namespace neurun
+{
+namespace ir
+{
+
+size_t Operand::operandSize(void) const
+{
+  const uint32_t ranks = shape().rank();
+  int32_t elements = 1;
+
+  for (uint32_t rank = 0; rank < ranks; rank++)
+  {
+    elements *= shape().dim(rank);
+  }
+
+  DataType type = typeInfo().type();
+  size_t element_size = sizeOfDataType(type);
+
+  // Value of type is matched with OperandCode enum in NeuralNetworks.h
+  return element_size * elements;
+}
+
+void Operand::appendUse(const OperationIndex &idx) { _uses.append(idx); }
+
+void Operand::removeUse(const OperationIndex &idx) { _uses.remove(idx); }
+
+void Operand::appendDef(const OperationIndex &idx)
+{
+  assert(!isConstant());
+  assert(_def.size() == 0);
+
+  _def.append(idx);
+}
+
+void Operand::removeDef(const OperationIndex &idx)
+{
+  assert(_def.contains(idx));
+
+  _def.remove(idx);
+}
+
+void Operand::parent_info(std::unique_ptr<operand::ParentInfo> &&parent_info)
+{
+  _parent_info = std::move(parent_info);
+}
+
+const operand::ParentInfo *Operand::parent_info() const { return _parent_info.get(); }
+
+operand::ParentInfo *Operand::parent_info() { return _parent_info.get(); }
+
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/OperandIndexSequence.cc b/runtime/neurun/core/src/ir/OperandIndexSequence.cc
new file mode 100644
index 000000000..302444125
--- /dev/null
+++ b/runtime/neurun/core/src/ir/OperandIndexSequence.cc
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/OperandIndexSequence.h"
+
+#include <algorithm>
+
+namespace neurun
+{
+namespace ir
+{
+
+OperandIndexSequence::OperandIndexSequence(std::initializer_list<OperandIndex> list) : _set(list)
+{
+  // DO NOTHING
+}
+
+OperandIndexSequence::OperandIndexSequence(std::initializer_list<int32_t> list)
+{
+  for (auto val : list)
+  {
+    _set.emplace_back(static_cast<uint32_t>(val));
+  }
+}
+
+OperandIndexSequence::OperandIndexSequence(std::initializer_list<uint32_t> list)
+{
+  for (auto val : list)
+  {
+    _set.emplace_back(val);
+  }
+}
+
+bool OperandIndexSequence::contains(const OperandIndex &index) const
+{
+  return std::find(_set.begin(), _set.end(), index) != _set.end();
+}
+
+void OperandIndexSequence::replace(const OperandIndex &from, const OperandIndex &to)
+{
+  std::replace(_set.begin(), _set.end(), from, to);
+}
+
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/Operation.cc b/runtime/neurun/core/src/ir/Operation.cc
new file mode 100644
index 000000000..3e4b606f2
--- /dev/null
+++ b/runtime/neurun/core/src/ir/Operation.cc
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/Operation.h"
+
+#include <cassert>
+
+namespace neurun
+{
+namespace ir
+{
+
+Operation::Operation(OperandConstraint input_constr, const OperandIndexSequence &inputs,
+                     const OperandIndexSequence &outputs)
+    : _input_constr{input_constr}, _inputs{inputs}, _outputs{outputs}
+{
+}
+
+Operation::Operation(OperandConstraint input_constr) : _input_constr{input_constr} {}
+
+Operation::~Operation() = default;
+
+void Operation::setInputs(const OperandIndexSequence &indexes)
+{
+  assert(_input_constr.check(indexes.size()));
+  _inputs = indexes;
+}
+
+void Operation::setOutputs(const OperandIndexSequence &indexes) { _outputs = indexes; }
+
+void Operation::replaceInput(const OperandIndex &from, const OperandIndex &to)
+{
+  _inputs.replace(from, to);
+}
+
+void Operation::replaceOutput(const OperandIndex &from, const OperandIndex &to)
+{
+  _outputs.replace(from, to);
+}
+
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/OperationIndexList.cc b/runtime/neurun/core/src/ir/OperationIndexList.cc
new file mode 100644
index 000000000..261cc5ce6
--- /dev/null
+++ b/runtime/neurun/core/src/ir/OperationIndexList.cc
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/OperationIndexList.h"
+
+#include <algorithm>
+
+namespace neurun
+{
+namespace ir
+{
+
+OperationIndexList::OperationIndexList(std::initializer_list<OperationIndex> list) : _list(list)
+{
+  // DO NOTHING
+}
+
+bool OperationIndexList::contains(const OperationIndex &index) const
+{
+  return std::find(_list.begin(), _list.end(), index) != _list.end();
+}
+
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/Shape.cc b/runtime/neurun/core/src/ir/Shape.cc
new file mode 100644
index 000000000..2679f83c6
--- /dev/null
+++ b/runtime/neurun/core/src/ir/Shape.cc
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/Shape.h"
+#include "util/Utils.h"
+
+#include <cassert>
+#include <functional>
+#include <numeric>
+
+namespace neurun
+{
+namespace ir
+{
+
+FeatureShape Shape::asFeature(Layout layout) const
+{
+  assert(rank() == 4);
+
+  if (layout == Layout::NHWC)
+  {
+    // Feature Map in NHWC layout
+    //  - Dimension(0) -> Batch
+    //  - Dimension(1) -> Height
+    //  - Dimension(2) -> Width
+    //  - Dimension(3) -> Depth
+    const auto batch = dim(0);
+    const auto depth = dim(3);
+    const auto height = dim(1);
+    const auto width = dim(2);
+
+    return {batch, depth, height, width};
+  }
+  else if (layout == Layout::NCHW)
+  {
+    // Feature Map in NHWC layout
+    //  - Dimension(0) -> Batch
+    //  - Dimension(1) -> Depth
+    //  - Dimension(2) -> Height
+    //  - Dimension(3) -> Width
+    const auto batch = dim(0);
+    const auto depth = dim(1);
+    const auto height = dim(2);
+    const auto width = dim(3);
+
+    return {batch, depth, height, width};
+  }
+  else
+  {
+    throw std::runtime_error("Wrong Layout");
+  }
+}
+
+// Extended dimension is filled with 1.
+void Shape::extendRank(int to_rank)
+{
+  assert(to_rank - rank() >= 0);
+  _dimensions.insert(_dimensions.cbegin(), to_rank - rank(), 1);
+}
+
+uint64_t Shape::num_elements() const
+{
+  // All of the nodes must have non-negative dimension
+  assert(std::all_of(_dimensions.begin(), _dimensions.end(),
+                     [](const int32_t &v) { return (v >= 0); }));
+
+  return std::accumulate(_dimensions.cbegin(), _dimensions.cend(), UINT64_C(1),
+                         std::multiplies<uint64_t>());
+}
+
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/Subgraphs.cc b/runtime/neurun/core/src/ir/Subgraphs.cc
new file mode 100644
index 000000000..780fc8c28
--- /dev/null
+++ b/runtime/neurun/core/src/ir/Subgraphs.cc
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/Subgraphs.h"
+#include "util/logging.h"
+#include "cpp14/memory.h"
+
+#include <cassert>
+#include <string>
+
+namespace neurun
+{
+namespace ir
+{
+
+SubgraphIndex Subgraphs::emplace(const OperationIndex &index, const Operation &node, Layout layout)
+{
+  std::unique_ptr<OpSequence> subg = nnfw::cpp14::make_unique<OpSequence>(layout);
+  subg->appendOperation(index, node);
+  return push(std::move(subg));
+}
+
+SubgraphIndex Subgraphs::emplace(std::unique_ptr<OpSequence> &&subg)
+{
+  return push(std::move(subg));
+}
+
+bool Subgraphs::containsOperation(const OperationIndex &operation_index) const
+{
+  return findOperation(operation_index).valid();
+}
+
+SubgraphIndex Subgraphs::getOperation(const OperationIndex &operation_index) const
+{
+  SubgraphIndex ret = findOperation(operation_index);
+  assert(ret.valid());
+  return ret;
+}
+
+// TODO: Extract this into external helper function
+void Subgraphs::dump(const std::string &msg) const
+{
+  VERBOSE(Subgraphs) << "Subgraphs(" << msg << ")" << std::endl;
+  iterate([&](const SubgraphIndex &idx, const OpSequence &subg) {
+    VERBOSE(Subgraphs) << idx.value() << "] " << subg.getStr() << std::endl;
+  });
+}
+
+void Subgraphs::removeFromSubgraph(const OperationIndex &operation_index)
+{
+  const auto subg_index = findOperation(operation_index);
+  auto &subg = at(subg_index);
+  subg.remove(operation_index);
+  if (subg.size() == 0)
+  {
+    remove(subg_index);
+  }
+}
+
+SubgraphIndex Subgraphs::findOperation(const OperationIndex &operation_index) const
+{
+  SubgraphIndex ret;
+  iterate([&](const SubgraphIndex &index, const OpSequence &object) {
+    for (const auto &elem : object.operations())
+    {
+      if (elem.index == operation_index)
+        ret = index;
+    }
+  });
+  return ret;
+}
+
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/TypeInfo.cc b/runtime/neurun/core/src/ir/TypeInfo.cc
new file mode 100644
index 000000000..280146b51
--- /dev/null
+++ b/runtime/neurun/core/src/ir/TypeInfo.cc
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/TypeInfo.h"
+
+namespace neurun
+{
+namespace ir
+{
+
+bool operator==(const TypeInfo &lhs, const TypeInfo &rhs)
+{
+  if (lhs.type() != rhs.type())
+  {
+    return false;
+  }
+
+  if (lhs.offset() != rhs.offset())
+  {
+    return false;
+  }
+
+  if (lhs.scale() != rhs.scale())
+  {
+    return false;
+  }
+
+  return true;
+}
+
+bool operator!=(const TypeInfo &lhs, const TypeInfo &rhs) { return !(lhs == rhs); }
+
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/dumper/Dumper.cc b/runtime/neurun/core/src/ir/dumper/Dumper.cc
new file mode 100644
index 000000000..ddfd1a47a
--- /dev/null
+++ b/runtime/neurun/core/src/ir/dumper/Dumper.cc
@@ -0,0 +1,633 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "Dumper.h"
+
+#include <string>
+
+#include "util/logging.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace dumper
+{
+
+using namespace operation;
+
+void Dumper::visit(const Abs &node)
+{
+  VERBOSE(LIR) << "* Abs" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(Abs::Input::INPUT).value() << ")"
+               << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const Add &node)
+{
+  VERBOSE(LIR) << "* Add" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(Add::Input::LHS).value() << ", "
+               << node.getInputs().at(Add::Input::RHS).value() << ")" << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const ArgMax &node)
+{
+  VERBOSE(LIR) << "* ArgMax" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(ArgMax::Input::INPUT).value() << ")"
+               << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const AvgPool2D &node)
+{
+  VERBOSE(LIR) << "* AvgPool2D(Implicit)" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : IFM(" << node.getInputs().at(AvgPool2D::Input::INPUT).value() << ")"
+               << std::endl;
+  VERBOSE(LIR) << "  - Output : OFM(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const Cast &node)
+{
+  VERBOSE(LIR) << "* Cast" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(Cast::Input::INPUT).value() << ")"
+               << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const Comparison &node)
+{
+  VERBOSE(LIR) << "* Comparison" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(Comparison::Input::INPUT0).value()
+               << ", " << node.getInputs().at(Comparison::Input::INPUT1).value() << ")"
+               << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const Concat &node)
+{
+  VERBOSE(LIR) << "* Concat" << std::endl;
+  std::string inputs;
+  for (auto i : node.getInputs())
+  {
+    inputs += std::to_string(i.value()) + ",";
+  }
+  VERBOSE(LIR) << "  - Inputs : IFM(" << inputs << ")" << std::endl;
+  VERBOSE(LIR) << "  - Output : OFM(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const Conv2D &node)
+{
+  std::string padding_type =
+      node.param().padding.type == PaddingType::EXPLICIT ? "Explicit" : "Implicit";
+  VERBOSE(LIR) << "* Conv2D(" << padding_type << ")" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : IFM(" << node.getInputs().at(Conv2D::Input::INPUT).value()
+               << ") Kernel(" << node.getInputs().at(Conv2D::Input::KERNEL).value() << ") Bias("
+               << node.getInputs().at(Conv2D::Input::BIAS).value() << ")" << std::endl;
+  VERBOSE(LIR) << "  - Output : OFM(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const DepthToSpace &node)
+{
+  VERBOSE(LIR) << "* DepthToSpace" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(DepthToSpace::Input::INPUT).value()
+               << ")" << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const DepthwiseConv2D &node)
+{
+  std::string padding_type =
+      node.param().padding.type == PaddingType::EXPLICIT ? "Explicit" : "Implicit";
+  VERBOSE(LIR) << "* DepthwiseConv2D(" << padding_type << ")" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : IFM(" << node.getInputs().at(DepthwiseConv2D::Input::INPUT).value()
+               << ") Kernel(" << node.getInputs().at(DepthwiseConv2D::Input::KERNEL).value()
+               << ") Bias(" << node.getInputs().at(DepthwiseConv2D::Input::BIAS).value() << ")"
+               << std::endl;
+  VERBOSE(LIR) << "  - Output : OFM(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const Dequantize &node)
+{
+  VERBOSE(LIR) << "* Dequantize" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(Dequantize::Input::INPUT).value()
+               << ")" << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const Div &node)
+{
+  VERBOSE(LIR) << "* Div" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(Div::Input::LHS).value() << ", "
+               << node.getInputs().at(Div::Input::RHS).value() << ")" << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const EmbeddingLookup &node)
+{
+  VERBOSE(LIR) << "* EmbeddingLookup" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Lookups("
+               << node.getInputs().at(EmbeddingLookup::Input::LOOKUPS).value() << ") VALUES("
+               << node.getInputs().at(EmbeddingLookup::Input::VALUES).value() << ")" << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const Exp &node)
+{
+  VERBOSE(LIR) << "* Exp" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(Exp::Input::INPUT).value() << ")"
+               << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const Floor &node)
+{
+  VERBOSE(LIR) << "* Floor" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(Floor::Input::INPUT).value() << ")"
+               << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const FullyConnected &node)
+{
+  VERBOSE(LIR) << "* FullyConnected" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : IFM(" << node.getInputs().at(FullyConnected::Input::INPUT).value()
+               << ") Weight(" << node.getInputs().at(FullyConnected::Input::WEIGHT).value()
+               << ") Bias(" << node.getInputs().at(FullyConnected::Input::BIAS).value() << ")"
+               << std::endl;
+  VERBOSE(LIR) << "  - Output : OFM(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const Gather &node)
+{
+  VERBOSE(LIR) << "* Gather" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(Gather::Input::INPUT).value()
+               << ") Indices(" << node.getInputs().at(Gather::Input::INDICES).value() << ")"
+               << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const HashtableLookup &node)
+{
+  VERBOSE(LIR) << "* HashTableLookup" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Lookups("
+               << node.getInputs().at(HashtableLookup::Input::LOOKUPS).value() << ") Keys("
+               << node.getInputs().at(HashtableLookup::Input::KEYS).value() << ") Values("
+               << node.getInputs().at(HashtableLookup::Input::VALUES).value() << ")" << std::endl;
+  VERBOSE(LIR) << "  - Outputs : Output("
+               << node.getInputs().at(HashtableLookup::Output::OUTPUT).value() << ") Hits("
+               << node.getInputs().at(HashtableLookup::Output::HITS).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const InstanceNorm &node)
+{
+  VERBOSE(LIR) << "* InstanceNorm" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : IFM(" << node.getInputs().at(InstanceNorm::Input::INPUT).value()
+               << ") Gamma(" << node.getInputs().at(InstanceNorm::Input::GAMMA).value() << ") Beta("
+               << node.getInputs().at(InstanceNorm::Input::BETA).value() << ") Epsilon("
+               << node.param().epsilon << ")" << std::endl;
+  VERBOSE(LIR) << "  - Output : OFM(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const L2Normalization &node)
+{
+  VERBOSE(LIR) << "* L2Normalization" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input("
+               << node.getInputs().at(L2Normalization::Input::INPUT).value() << ")" << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const L2Pool2D &node)
+{
+  VERBOSE(LIR) << "* L2Pool2D" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(L2Pool2D::Input::INPUT).value()
+               << ")" << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const LocalResponseNormalization &node)
+{
+  VERBOSE(LIR) << "* LocalResponseNormalization" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input("
+               << node.getInputs().at(LocalResponseNormalization::Input::INPUT).value() << ")"
+               << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const LSTM &node)
+{
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(LSTM::Input::INPUT).value()
+               << ") Input To Input Weights("
+               << node.getInputs().at(LSTM::Input::INPUT_TO_INPUT_WEIGHTS).value()
+               << ") Input To Forget Weights("
+               << node.getInputs().at(LSTM::Input::INPUT_TO_FORGET_WEIGHTS).value()
+               << ") Input To Cell Weights("
+               << node.getInputs().at(LSTM::Input::INPUT_TO_CELL_WEIGHTS).value()
+               << ") Input To Output Weights("
+               << node.getInputs().at(LSTM::Input::INPUT_TO_OUTPUT_WEIGHTS).value()
+               << ") Recurrent To Input Weights("
+               << node.getInputs().at(LSTM::Input::RECURRENT_TO_INPUT_WEIGHTS).value()
+               << ") Recurrent To Forget Weights("
+               << node.getInputs().at(LSTM::Input::RECURRENT_TO_FORGET_WEIGHTS).value()
+               << ") Recurrent To Cell Weights("
+               << node.getInputs().at(LSTM::Input::RECURRENT_TO_CELL_WEIGHTS).value()
+               << ") Recurrent To Output Weights("
+               << node.getInputs().at(LSTM::Input::RECURRENT_TO_OUTPUT_WEIGHTS).value()
+               << ") Cell To Input Weights("
+               << node.getInputs().at(LSTM::Input::CELL_TO_INPUT_WEIGHTS).value()
+               << ") Cell To Forget Weights("
+               << node.getInputs().at(LSTM::Input::CELL_TO_FORGET_WEIGHTS).value()
+               << ") Cell To OUTPUT Weights("
+               << node.getInputs().at(LSTM::Input::CELL_TO_OUTPUT_WEIGHTS).value()
+               << ") Input Gate Bias(" << node.getInputs().at(LSTM::Input::INPUT_GATE_BIAS).value()
+               << ") Forget Gate Bias("
+               << node.getInputs().at(LSTM::Input::FORGET_GATE_BIAS).value() << ") Cell Bias("
+               << node.getInputs().at(LSTM::Input::CELL_BIAS).value() << ") Output Gate Bias("
+               << node.getInputs().at(LSTM::Input::OUTPUT_GATE_BIAS).value()
+               << ") Projection Weights("
+               << node.getInputs().at(LSTM::Input::PROJECTION_WEIGHTS).value()
+               << ") Projection Bias(" << node.getInputs().at(LSTM::Input::PROJECTION_BIAS).value()
+               << ") Output State In(" << node.getInputs().at(LSTM::Input::OUTPUT_STATE_IN).value()
+               << ") Cell State In(" << node.getInputs().at(LSTM::Input::CELL_STATE_IN).value()
+               << ")" << std::endl;
+  VERBOSE(LIR) << "  - Output : Scratch Buffer("
+               << node.getOutputs().at(LSTM::Output::SCRATCH_BUFFER).value()
+               << ") Output State Out("
+               << node.getInputs().at(LSTM::Output::OUTPUT_STATE_OUT).value() << ") Cell State Out("
+               << node.getInputs().at(LSTM::Output::CELL_STATE_OUT).value() << ") Output("
+               << node.getInputs().at(LSTM::Output::OUTPUT).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const LogicalAnd &node)
+{
+  VERBOSE(LIR) << "* LogicalAnd" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(LogicalAnd::Input::INPUT0).value()
+               << ", " << node.getInputs().at(LogicalAnd::Input::INPUT1).value() << ")"
+               << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const LogicalNot &node)
+{
+  VERBOSE(LIR) << "* LogicalNot" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(LogicalNot::Input::INPUT).value()
+               << ")" << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const LogicalOr &node)
+{
+  VERBOSE(LIR) << "* LogicalOr" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(LogicalOr::Input::INPUT0).value()
+               << ", " << node.getInputs().at(LogicalOr::Input::INPUT1).value() << ")" << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const Logistic &node)
+{
+  VERBOSE(LIR) << "* Logistic" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(Logistic::Input::INPUT).value()
+               << ")" << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const MaxPool2D &node)
+{
+  std::string padding_type =
+      node.param().padding.type == PaddingType::EXPLICIT ? "Explicit" : "Implicit";
+  VERBOSE(LIR) << "* MaxPool2D(" << padding_type << ")" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : IFM(" << node.getInputs().at(MaxPool2D::Input::INPUT).value() << ")"
+               << std::endl;
+  VERBOSE(LIR) << "  - Output : OFM(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const Mean &node)
+{
+  VERBOSE(LIR) << "* Mean" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(Mean::Input::INPUT).value() << ")"
+               << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const Mul &node)
+{
+  VERBOSE(LIR) << "* Mul" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(Mul::Input::LHS).value() << ", "
+               << node.getInputs().at(Mul::Input::RHS).value() << ")" << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const Neg &node)
+{
+  VERBOSE(LIR) << "* Neg" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(Neg::Input::INPUT).value() << ")"
+               << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const Pack &node)
+{
+  VERBOSE(LIR) << "* Pack" << std::endl;
+  std::string inputs;
+  const auto &input_indices = node.getInputs();
+  for (auto it = std::begin(input_indices); it != std::end(input_indices); ++it)
+  {
+    inputs += std::to_string(it->value());
+    if (std::next(it) != std::end(input_indices))
+      inputs += ", ";
+  }
+  VERBOSE(LIR) << "  - Inputs : Inputs(" << inputs << ")" << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const Permute &node)
+{
+  std::string permute_type = "Unknown";
+  switch (node.getPermuteType())
+  {
+    case Permute::Type::COPY:
+      permute_type = "Copy";
+      break;
+    case Permute::Type::NHWC_TO_NCHW:
+      permute_type = "NHWC to NCHW";
+      break;
+    case Permute::Type::NCHW_TO_NHWC:
+      permute_type = "NCHW to NHWC";
+      break;
+  }
+
+  VERBOSE(LIR) << "* Permute(" + permute_type + ")" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(0).value() << ")" << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const PReLU &node)
+{
+  VERBOSE(LIR) << "* PReLU" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(PReLU::Input::INPUT).value()
+               << ") Alpha(" << node.getInputs().at(PReLU::Input::ALPHA).value() << ")"
+               << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const ReduceMax &node)
+{
+  VERBOSE(LIR) << "* ReduceMax" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(ReduceMax::Input::INPUT).value()
+               << ")" << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const ReduceMin &node)
+{
+  VERBOSE(LIR) << "* ReduceMin" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(ReduceMin::Input::INPUT).value()
+               << ")" << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const ReduceSum &node)
+{
+  VERBOSE(LIR) << "* ReduceSum" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(ReduceSum::Input::INPUT).value()
+               << ")" << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const ReLU &node)
+{
+  VERBOSE(LIR) << "* ReLU" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(ReLU::Input::INPUT).value() << ")"
+               << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const ReLU1 &node)
+{
+  VERBOSE(LIR) << "* ReLU1" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(ReLU1::Input::INPUT).value() << ")"
+               << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const ReLU6 &node)
+{
+  VERBOSE(LIR) << "* ReLU6" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(ReLU6::Input::INPUT).value() << ")"
+               << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const Reshape &node)
+{
+  VERBOSE(LIR) << "* Reshape" << std::endl;
+  // TODO The shape index should be "node.getInputs().at(1).value()" but not valid for now
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(Reshape::Input::INPUT).value()
+               << ") Shape("
+               << "?"
+               << ")" << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const ResizeBilinear &node)
+{
+  VERBOSE(LIR) << "* ResizeBilinear" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(ResizeBilinear::Input::INPUT).value()
+               << ")" << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const RNN &node)
+{
+  VERBOSE(LIR) << "* RNN" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(RNN::Input::INPUT).value()
+               << ") Weights" << node.getInputs().at(RNN::Input::WEIGHTS).value()
+               << ") Recurrent Weights"
+               << node.getInputs().at(RNN::Input::RECURRENT_WEIGHTS).value() << ") Bias"
+               << node.getInputs().at(RNN::Input::BIAS).value() << ") Hidden State"
+               << node.getInputs().at(RNN::Input::HIDDEN_STATE_IN).value() << ")" << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(RNN::Output::OUTPUT).value()
+               << ") Hidden State" << node.getInputs().at(RNN::Output::HIDDEN_STATE_OUT).value()
+               << ")" << std::endl;
+}
+
+void Dumper::visit(const RSQRT &node)
+{
+  VERBOSE(LIR) << "* RSQRT" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(RSQRT::Input::INPUT).value() << ")"
+               << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const Softmax &node)
+{
+  VERBOSE(LIR) << "* Softmax" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(Softmax::Input::INPUT).value() << ")"
+               << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const SpaceToDepth &node)
+{
+  VERBOSE(LIR) << "* SpaceToDepth" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(SpaceToDepth::Input::INPUT).value()
+               << ")" << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const Split &node)
+{
+  VERBOSE(LIR) << "* Split" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(Split::Input::INPUT).value() << ")"
+               << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const SQRT &node)
+{
+  VERBOSE(LIR) << "* SQRT" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(SQRT::Input::INPUT).value() << ")"
+               << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const SquaredDifference &node)
+{
+  VERBOSE(LIR) << "* SquaredDifference" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input("
+               << node.getInputs().at(SquaredDifference::Input::LHS).value() << ", "
+               << node.getInputs().at(SquaredDifference::Input::RHS).value() << ")" << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const Squeeze &node)
+{
+  VERBOSE(LIR) << "* Squeeze" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(Squeeze::Input::INPUT).value() << ")"
+               << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const Slice &node)
+{
+  VERBOSE(LIR) << "* Slice" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(Slice::Input::INPUT).value() << ")"
+               << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const StridedSlice &node)
+{
+  VERBOSE(LIR) << "* StridedSlice" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(StridedSlice::Input::INPUT).value()
+               << ")" << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const Sub &node)
+{
+  VERBOSE(LIR) << "* Sub" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(Sub::Input::LHS).value() << ", "
+               << node.getInputs().at(Sub::Input::RHS).value() << ")" << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const Tanh &node)
+{
+  VERBOSE(LIR) << "* TanH" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(Tanh::Input::INPUT).value() << ")"
+               << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const TopKV2 &node)
+{
+  VERBOSE(LIR) << "* TopKV2" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(TopKV2::Input::INPUT).value() << ")"
+               << std::endl;
+  VERBOSE(LIR) << "  - Outputs : Values("
+               << node.getOutputs().at(TopKV2::Output::OUTPUT_VALUES).value() << ") Indices("
+               << node.getOutputs().at(TopKV2::Output::OUTPUT_INDICES).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const TransposeConv &node)
+{
+  std::string padding_type =
+      node.param().padding.type == PaddingType::EXPLICIT ? "Explicit" : "Implicit";
+  VERBOSE(LIR) << "* TransposeConv(" << padding_type << ")" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Output Shape("
+               << node.getInputs().at(TransposeConv::Input::OUTPUT_SHAPE).value() << ") KERNEL("
+               << node.getInputs().at(TransposeConv::Input::KERNEL).value() << ") IFM("
+               << node.getInputs().at(TransposeConv::Input::INPUT).value() << ")" << std::endl;
+  VERBOSE(LIR) << "  - Output : OFM(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const Transpose &node)
+{
+  VERBOSE(LIR) << "* Transpose" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(Transpose::Input::INPUT).value()
+               << ")" << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const Unpack &node)
+{
+  VERBOSE(LIR) << "* Unpack" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(Unpack::Input::INPUT).value() << ")"
+               << std::endl;
+  std::string outputs;
+  const auto &output_indices = node.getOutputs();
+  for (auto it = std::begin(output_indices); it != std::end(output_indices); ++it)
+  {
+    outputs += std::to_string(it->value());
+    if (std::next(it) != std::end(output_indices))
+      outputs += ", ";
+  }
+  VERBOSE(LIR) << "  - Outputs : Outputs(" << outputs << ")" << std::endl;
+}
+
+void Dumper::visit(const Min &node)
+{
+  VERBOSE(LIR) << "* Min" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(Min::Input::LHS).value() << ", "
+               << node.getInputs().at(Min::Input::RHS).value() << ")" << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const Max &node)
+{
+  VERBOSE(LIR) << "* Max" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : Input(" << node.getInputs().at(Max::Input::LHS).value() << ", "
+               << node.getInputs().at(Max::Input::RHS).value() << ")" << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+void Dumper::visit(const OneHot &node)
+{
+  VERBOSE(LIR) << "* OneHot" << std::endl;
+  VERBOSE(LIR) << "  - Inputs : "
+               << "Indices(" << node.getInputs().at(OneHot::Input::INDICES).value() << ") "
+               << "Depth(" << node.getInputs().at(OneHot::Input::DEPTH).value() << ") "
+               << "OnValue(" << node.getInputs().at(OneHot::Input::ON_VALUE).value() << ") "
+               << "OffValue(" << node.getInputs().at(OneHot::Input::OFF_VALUE).value() << ") "
+               << "Axis(" << node.param().axis << ") " << std::endl;
+  VERBOSE(LIR) << "  - Output : Output(" << node.getOutputs().at(0).value() << ")" << std::endl;
+}
+
+} // namespace dumper
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/dumper/Dumper.h b/runtime/neurun/core/src/ir/dumper/Dumper.h
new file mode 100644
index 000000000..458f1c81f
--- /dev/null
+++ b/runtime/neurun/core/src/ir/dumper/Dumper.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_GRAPH_DUMPER_H__
+#define __NEURUN_GRAPH_DUMPER_H__
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace dumper
+{
+
+class Dumper : public OperationVisitor
+{
+public:
+  Dumper() = default;
+
+public:
+  void visit(const operation::Abs &) override;
+  void visit(const operation::Add &node) override;
+  void visit(const operation::ArgMax &) override;
+  void visit(const operation::AvgPool2D &node) override;
+  void visit(const operation::Cast &) override;
+  void visit(const operation::Comparison &) override;
+  void visit(const operation::Concat &node) override;
+  void visit(const operation::Conv2D &node) override;
+  void visit(const operation::DepthToSpace &) override;
+  void visit(const operation::DepthwiseConv2D &node) override;
+  void visit(const operation::Dequantize &) override;
+  void visit(const operation::Div &) override;
+  void visit(const operation::EmbeddingLookup &) override;
+  void visit(const operation::Exp &) override;
+  void visit(const operation::Floor &) override;
+  void visit(const operation::FullyConnected &node) override;
+  void visit(const operation::Gather &) override;
+  void visit(const operation::HashtableLookup &) override;
+  void visit(const operation::InstanceNorm &) override;
+  void visit(const operation::L2Normalization &) override;
+  void visit(const operation::L2Pool2D &) override;
+  void visit(const operation::LocalResponseNormalization &) override;
+  void visit(const operation::LogicalAnd &) override;
+  void visit(const operation::LogicalNot &) override;
+  void visit(const operation::LogicalOr &) override;
+  void visit(const operation::Logistic &) override;
+  void visit(const operation::LSTM &) override;
+  void visit(const operation::MaxPool2D &node) override;
+  void visit(const operation::Mean &) override;
+  void visit(const operation::Mul &) override;
+  void visit(const operation::Neg &) override;
+  void visit(const operation::Pack &) override;
+  void visit(const operation::Permute &node) override;
+  void visit(const operation::PReLU &) override;
+  void visit(const operation::ReduceMax &) override;
+  void visit(const operation::ReduceMin &) override;
+  void visit(const operation::ReduceSum &) override;
+  void visit(const operation::ReLU &) override;
+  void visit(const operation::ReLU1 &) override;
+  void visit(const operation::ReLU6 &) override;
+  void visit(const operation::Reshape &node) override;
+  void visit(const operation::ResizeBilinear &) override;
+  void visit(const operation::RNN &) override;
+  void visit(const operation::RSQRT &) override;
+  void visit(const operation::Softmax &node) override;
+  void visit(const operation::SpaceToDepth &) override;
+  void visit(const operation::Split &) override;
+  void visit(const operation::SQRT &) override;
+  void visit(const operation::SquaredDifference &) override;
+  void visit(const operation::Squeeze &) override;
+  void visit(const operation::Slice &) override;
+  void visit(const operation::StridedSlice &) override;
+  void visit(const operation::Sub &) override;
+  void visit(const operation::Tanh &) override;
+  void visit(const operation::TopKV2 &) override;
+  void visit(const operation::TransposeConv &) override;
+  void visit(const operation::Transpose &) override;
+  void visit(const operation::Unpack &) override;
+  void visit(const operation::Min &) override;
+  void visit(const operation::Max &) override;
+  void visit(const operation::OneHot &) override;
+};
+
+} // namespace dumper
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_GRAPH_DUMPER_H__
diff --git a/runtime/neurun/core/src/ir/operand/Shape4DConvert.h b/runtime/neurun/core/src/ir/operand/Shape4DConvert.h
new file mode 100644
index 000000000..feffee89f
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operand/Shape4DConvert.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_GRAPH_OPERAND_SHAPE4D_CONVERT_H__
+#define __NEURUN_GRAPH_OPERAND_SHAPE4D_CONVERT_H__
+
+#include "ir/operand/LowerInfo.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operand
+{
+
+inline LowerInfo::Shape4D asShape4D(const Shape &shape)
+{
+  switch (shape.rank())
+  {
+    case 0u:
+      return LowerInfo::Shape4D(1, 1, 1, 1);
+
+    case 1u:
+      return LowerInfo::Shape4D(1, 1, 1, shape.dim(0));
+
+    case 2u:
+      return LowerInfo::Shape4D(1, 1, shape.dim(0), shape.dim(1));
+
+    case 3u:
+      return LowerInfo::Shape4D(1, shape.dim(0), shape.dim(1), shape.dim(2));
+
+    case 4u:
+      return LowerInfo::Shape4D(shape.dim(0), shape.dim(1), shape.dim(2), shape.dim(3));
+
+    default:
+      throw "Unsupported rank > 4";
+  }
+}
+
+} // namespace operand
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_GRAPH_OPERAND_SHAPE4D_CONVERT_H__
diff --git a/runtime/neurun/core/src/ir/operation/Abs.cc b/runtime/neurun/core/src/ir/operation/Abs.cc
new file mode 100644
index 000000000..9506f83d2
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/Abs.cc
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/Abs.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void Abs::accept(OperationVisitor &v) const { v.visit(*this); }
+
+Abs::Abs(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/Add.cc b/runtime/neurun/core/src/ir/operation/Add.cc
new file mode 100644
index 000000000..a7c40c37a
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/Add.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/Add.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void Add::accept(OperationVisitor &v) const { v.visit(*this); }
+
+Add::Add(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+         const Param &param)
+    : Operation{OperandConstraint::createExact(2u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/ArgMax.cc b/runtime/neurun/core/src/ir/operation/ArgMax.cc
new file mode 100644
index 000000000..200abc7dd
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/ArgMax.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/ArgMax.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void ArgMax::accept(OperationVisitor &v) const { v.visit(*this); }
+
+ArgMax::ArgMax(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+               const Param &param)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/AvgPool2D.cc b/runtime/neurun/core/src/ir/operation/AvgPool2D.cc
new file mode 100644
index 000000000..21ec052eb
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/AvgPool2D.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/AvgPool2D.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void AvgPool2D::accept(OperationVisitor &v) const { v.visit(*this); }
+
+AvgPool2D::AvgPool2D(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+                     const Param &param)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/BatchToSpaceND.cc b/runtime/neurun/core/src/ir/operation/BatchToSpaceND.cc
new file mode 100644
index 000000000..042144c12
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/BatchToSpaceND.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/BatchToSpaceND.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void BatchToSpaceND::accept(OperationVisitor &v) const { v.visit(*this); }
+
+BatchToSpaceND::BatchToSpaceND(const OperandIndexSequence &inputs,
+                               const OperandIndexSequence &outputs)
+    : Operation{OperandConstraint::createExact(2u), inputs, outputs}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/Cast.cc b/runtime/neurun/core/src/ir/operation/Cast.cc
new file mode 100644
index 000000000..095225eca
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/Cast.cc
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/Cast.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void Cast::accept(OperationVisitor &v) const { v.visit(*this); }
+
+Cast::Cast(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/Comparison.cc b/runtime/neurun/core/src/ir/operation/Comparison.cc
new file mode 100644
index 000000000..995d56764
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/Comparison.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/Comparison.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void Comparison::accept(OperationVisitor &v) const { v.visit(*this); }
+
+Comparison::Comparison(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+                       const Param &param)
+    : Operation{OperandConstraint::createExact(2u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/Concat.cc b/runtime/neurun/core/src/ir/operation/Concat.cc
new file mode 100644
index 000000000..1772da1fc
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/Concat.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/Concat.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void Concat::accept(OperationVisitor &v) const { v.visit(*this); }
+
+Concat::Concat(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+               const Param &param)
+    : Operation{OperandConstraint::createAtLeast(1u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/Conv2D.cc b/runtime/neurun/core/src/ir/operation/Conv2D.cc
new file mode 100644
index 000000000..505e916a9
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/Conv2D.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/Conv2D.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void Conv2D::accept(OperationVisitor &v) const { v.visit(*this); }
+
+Conv2D::Conv2D(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+               const Param &param)
+    : Operation{OperandConstraint::createExact(3u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/Custom.cc b/runtime/neurun/core/src/ir/operation/Custom.cc
new file mode 100644
index 000000000..67f36d588
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/Custom.cc
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/Custom.h"
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void Custom::accept(OperationVisitor &v) const { v.visit(*this); }
+
+Custom::Custom(OperandConstraint input_constr, const OperandIndexSequence &inputs,
+               const OperandIndexSequence &outputs, std::string id, const Userdata &userdata)
+    : Operation{input_constr, inputs, outputs}, _id(std::move(id)), _userdata(userdata)
+{
+}
+
+const std::string &Custom::id() const { return _id; }
+
+const Custom::Userdata &Custom::userdata() const { return _userdata; }
+
+Custom::~Custom() { delete[] _userdata.data; }
+
+std::string Custom::name() const { return id(); }
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/DepthToSpace.cc b/runtime/neurun/core/src/ir/operation/DepthToSpace.cc
new file mode 100644
index 000000000..fd1d1f1aa
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/DepthToSpace.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/DepthToSpace.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void DepthToSpace::accept(OperationVisitor &v) const { v.visit(*this); }
+
+DepthToSpace::DepthToSpace(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+                           const Param &param)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/DepthwiseConv2D.cc b/runtime/neurun/core/src/ir/operation/DepthwiseConv2D.cc
new file mode 100644
index 000000000..ed76594a3
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/DepthwiseConv2D.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/DepthwiseConv2D.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void DepthwiseConv2D::accept(OperationVisitor &v) const { v.visit(*this); }
+
+DepthwiseConv2D::DepthwiseConv2D(const OperandIndexSequence &inputs,
+                                 const OperandIndexSequence &outputs, const Param &param)
+    : Operation{OperandConstraint::createExact(3u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/Dequantize.cc b/runtime/neurun/core/src/ir/operation/Dequantize.cc
new file mode 100644
index 000000000..e99a59cb7
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/Dequantize.cc
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/Dequantize.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void Dequantize::accept(OperationVisitor &v) const { v.visit(*this); }
+
+Dequantize::Dequantize(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/Div.cc b/runtime/neurun/core/src/ir/operation/Div.cc
new file mode 100644
index 000000000..484406ff3
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/Div.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/Div.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void Div::accept(OperationVisitor &v) const { v.visit(*this); }
+
+Div::Div(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+         const Param &param)
+    : Operation{OperandConstraint::createExact(2u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/EmbeddingLookup.cc b/runtime/neurun/core/src/ir/operation/EmbeddingLookup.cc
new file mode 100644
index 000000000..206e6bfaa
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/EmbeddingLookup.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/EmbeddingLookup.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void EmbeddingLookup::accept(OperationVisitor &v) const { v.visit(*this); }
+
+EmbeddingLookup::EmbeddingLookup(const OperandIndexSequence &inputs,
+                                 const OperandIndexSequence &outputs)
+    : Operation{OperandConstraint::createExact(2u), inputs, outputs}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/Exp.cc b/runtime/neurun/core/src/ir/operation/Exp.cc
new file mode 100644
index 000000000..3c0e0cf9b
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/Exp.cc
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/Exp.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void Exp::accept(OperationVisitor &v) const { v.visit(*this); }
+
+Exp::Exp(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/Floor.cc b/runtime/neurun/core/src/ir/operation/Floor.cc
new file mode 100644
index 000000000..75373cd41
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/Floor.cc
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/Floor.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void Floor::accept(OperationVisitor &v) const { v.visit(*this); }
+
+Floor::Floor(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/FullyConnected.cc b/runtime/neurun/core/src/ir/operation/FullyConnected.cc
new file mode 100644
index 000000000..9560c0593
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/FullyConnected.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/FullyConnected.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void FullyConnected::accept(OperationVisitor &v) const { v.visit(*this); }
+
+FullyConnected::FullyConnected(const OperandIndexSequence &inputs,
+                               const OperandIndexSequence &outputs, const Param &param)
+    : Operation{OperandConstraint::createExact(3u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/Gather.cc b/runtime/neurun/core/src/ir/operation/Gather.cc
new file mode 100644
index 000000000..f98cef9ae
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/Gather.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/Gather.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void Gather::accept(OperationVisitor &v) const { v.visit(*this); }
+
+Gather::Gather(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+               const Param &param)
+    : Operation{OperandConstraint::createExact(2u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/HashtableLookup.cc b/runtime/neurun/core/src/ir/operation/HashtableLookup.cc
new file mode 100644
index 000000000..ecb9d3195
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/HashtableLookup.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/HashtableLookup.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void HashtableLookup::accept(OperationVisitor &v) const { v.visit(*this); }
+
+HashtableLookup::HashtableLookup(const OperandIndexSequence &inputs,
+                                 const OperandIndexSequence &outputs)
+    : Operation{OperandConstraint::createExact(3u), inputs, outputs}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/InstanceNorm.cc b/runtime/neurun/core/src/ir/operation/InstanceNorm.cc
new file mode 100644
index 000000000..69e47abd4
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/InstanceNorm.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/InstanceNorm.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void InstanceNorm::accept(OperationVisitor &v) const { v.visit(*this); }
+
+InstanceNorm::InstanceNorm(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+                           const Param &param)
+    : Operation{OperandConstraint::createExact(3u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/L2Normalization.cc b/runtime/neurun/core/src/ir/operation/L2Normalization.cc
new file mode 100644
index 000000000..67085989e
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/L2Normalization.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/L2Normalization.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void L2Normalization::accept(OperationVisitor &v) const { v.visit(*this); }
+
+L2Normalization::L2Normalization(const OperandIndexSequence &inputs,
+                                 const OperandIndexSequence &outputs, const Param &param)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/L2Pool2D.cc b/runtime/neurun/core/src/ir/operation/L2Pool2D.cc
new file mode 100644
index 000000000..0815cb5ab
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/L2Pool2D.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/L2Pool2D.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void L2Pool2D::accept(OperationVisitor &v) const { v.visit(*this); }
+
+L2Pool2D::L2Pool2D(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+                   const Param &param)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/LSTM.cc b/runtime/neurun/core/src/ir/operation/LSTM.cc
new file mode 100644
index 000000000..58e2aa32e
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/LSTM.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/LSTM.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void LSTM::accept(OperationVisitor &v) const { v.visit(*this); }
+
+LSTM::LSTM(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+           const Param &param)
+    : Operation{OperandConstraint::createExact(23u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/LocalResponseNormalization.cc b/runtime/neurun/core/src/ir/operation/LocalResponseNormalization.cc
new file mode 100644
index 000000000..dcba7f1cb
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/LocalResponseNormalization.cc
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/LocalResponseNormalization.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void LocalResponseNormalization::accept(OperationVisitor &v) const { v.visit(*this); }
+
+LocalResponseNormalization::LocalResponseNormalization(const OperandIndexSequence &inputs,
+                                                       const OperandIndexSequence &outputs,
+                                                       const Param &param)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/LogicalAnd.cc b/runtime/neurun/core/src/ir/operation/LogicalAnd.cc
new file mode 100644
index 000000000..51f4f0ee0
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/LogicalAnd.cc
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/LogicalAnd.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void LogicalAnd::accept(OperationVisitor &v) const { v.visit(*this); }
+
+LogicalAnd::LogicalAnd(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs)
+    : Operation{OperandConstraint::createExact(2u), inputs, outputs}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/LogicalNot.cc b/runtime/neurun/core/src/ir/operation/LogicalNot.cc
new file mode 100644
index 000000000..48c25142a
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/LogicalNot.cc
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/LogicalNot.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void LogicalNot::accept(OperationVisitor &v) const { v.visit(*this); }
+
+LogicalNot::LogicalNot(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/LogicalOr.cc b/runtime/neurun/core/src/ir/operation/LogicalOr.cc
new file mode 100644
index 000000000..663b7deb5
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/LogicalOr.cc
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/LogicalOr.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void LogicalOr::accept(OperationVisitor &v) const { v.visit(*this); }
+
+LogicalOr::LogicalOr(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs)
+    : Operation{OperandConstraint::createExact(2u), inputs, outputs}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/Logistic.cc b/runtime/neurun/core/src/ir/operation/Logistic.cc
new file mode 100644
index 000000000..3ed2f3453
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/Logistic.cc
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/Logistic.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void Logistic::accept(OperationVisitor &v) const { v.visit(*this); }
+
+Logistic::Logistic(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/LowerInfo.cc b/runtime/neurun/core/src/ir/operation/LowerInfo.cc
new file mode 100644
index 000000000..6133be3f8
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/LowerInfo.cc
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/LowerInfo.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+LowerInfo::LowerInfo(const backend::Backend *backend, Layout layout)
+    : _permute_factor{backend, layout}
+{
+  // DO NOTHING
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/Max.cc b/runtime/neurun/core/src/ir/operation/Max.cc
new file mode 100644
index 000000000..be4bdd365
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/Max.cc
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/Max.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void Max::accept(OperationVisitor &v) const { v.visit(*this); }
+
+Max::Max(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs)
+    : Operation{OperandConstraint::createExact(2u), inputs, outputs}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/MaxPool2D.cc b/runtime/neurun/core/src/ir/operation/MaxPool2D.cc
new file mode 100644
index 000000000..8f1b70cd6
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/MaxPool2D.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/MaxPool2D.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void MaxPool2D::accept(OperationVisitor &v) const { v.visit(*this); }
+
+MaxPool2D::MaxPool2D(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+                     const Param &param)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/Mean.cc b/runtime/neurun/core/src/ir/operation/Mean.cc
new file mode 100644
index 000000000..016b5dd85
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/Mean.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/Mean.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void Mean::accept(OperationVisitor &v) const { v.visit(*this); }
+
+Mean::Mean(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+           const Param &param)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/Min.cc b/runtime/neurun/core/src/ir/operation/Min.cc
new file mode 100644
index 000000000..a864405dc
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/Min.cc
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/Min.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void Min::accept(OperationVisitor &v) const { v.visit(*this); }
+
+Min::Min(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs)
+    : Operation{OperandConstraint::createExact(2u), inputs, outputs}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/Mul.cc b/runtime/neurun/core/src/ir/operation/Mul.cc
new file mode 100644
index 000000000..0b2d67a9d
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/Mul.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/Mul.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void Mul::accept(OperationVisitor &v) const { v.visit(*this); }
+
+Mul::Mul(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+         const Param &param)
+    : Operation{OperandConstraint::createExact(2u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/Neg.cc b/runtime/neurun/core/src/ir/operation/Neg.cc
new file mode 100644
index 000000000..65922d57c
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/Neg.cc
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/Neg.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void Neg::accept(OperationVisitor &v) const { v.visit(*this); }
+
+Neg::Neg(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/OneHot.cc b/runtime/neurun/core/src/ir/operation/OneHot.cc
new file mode 100644
index 000000000..0ba3c9d60
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/OneHot.cc
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/OneHot.h"
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void OneHot::accept(OperationVisitor &v) const { v.visit(*this); }
+
+OneHot::OneHot(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+               const Param &param)
+    : Operation{OperandConstraint::createExact(4u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/PReLU.cc b/runtime/neurun/core/src/ir/operation/PReLU.cc
new file mode 100644
index 000000000..b8555ccbd
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/PReLU.cc
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/PReLU.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void PReLU::accept(OperationVisitor &v) const { v.visit(*this); }
+
+PReLU::PReLU(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs)
+    : Operation{OperandConstraint::createExact(2u), inputs, outputs}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/Pack.cc b/runtime/neurun/core/src/ir/operation/Pack.cc
new file mode 100644
index 000000000..412c744ea
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/Pack.cc
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "ir/operation/Pack.h"
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+void Pack::accept(OperationVisitor &v) const { v.visit(*this); }
+Pack::Pack(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+           const Param &param)
+    : Operation{OperandConstraint::createAtLeast(3u), inputs, outputs}, _param{param}
+{
+}
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/Pad.cc b/runtime/neurun/core/src/ir/operation/Pad.cc
new file mode 100644
index 000000000..a08be12a6
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/Pad.cc
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/Pad.h"
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void Pad::accept(OperationVisitor &v) const { v.visit(*this); }
+
+Pad::Pad(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+         const Param &param)
+    : Operation{OperandConstraint::createExact(2u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/Permute.cc b/runtime/neurun/core/src/ir/operation/Permute.cc
new file mode 100644
index 000000000..ec3d969c8
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/Permute.cc
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/Permute.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void Permute::accept(OperationVisitor &v) const { v.visit(*this); }
+
+Permute::Permute(const OperandIndex &input, const OperandIndex &output,
+                 const backend::BackendContext *input_backend_ctx,
+                 const backend::BackendContext *output_backend_ctx, Type type, DataType data_type)
+    : Operation{OperandConstraint::createExact(1u)}, _param{input_backend_ctx, output_backend_ctx},
+      _type{type}, _dataType{data_type}
+{
+  setInputs({input});
+  setOutputs({output});
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/RNN.cc b/runtime/neurun/core/src/ir/operation/RNN.cc
new file mode 100644
index 000000000..8db5cbceb
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/RNN.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/RNN.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void RNN::accept(OperationVisitor &v) const { v.visit(*this); }
+
+RNN::RNN(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+         const Param &param)
+    : Operation{OperandConstraint::createExact(5u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/RSQRT.cc b/runtime/neurun/core/src/ir/operation/RSQRT.cc
new file mode 100644
index 000000000..ec13b20ec
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/RSQRT.cc
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/RSQRT.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void RSQRT::accept(OperationVisitor &v) const { v.visit(*this); }
+
+RSQRT::RSQRT(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/ReLU.cc b/runtime/neurun/core/src/ir/operation/ReLU.cc
new file mode 100644
index 000000000..6b3f7e72d
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/ReLU.cc
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/ReLU.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void ReLU::accept(OperationVisitor &v) const { v.visit(*this); }
+
+ReLU::ReLU(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/ReLU1.cc b/runtime/neurun/core/src/ir/operation/ReLU1.cc
new file mode 100644
index 000000000..d7b4e1b11
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/ReLU1.cc
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/ReLU1.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void ReLU1::accept(OperationVisitor &v) const { v.visit(*this); }
+
+ReLU1::ReLU1(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/ReLU6.cc b/runtime/neurun/core/src/ir/operation/ReLU6.cc
new file mode 100644
index 000000000..245eb923f
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/ReLU6.cc
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/ReLU6.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void ReLU6::accept(OperationVisitor &v) const { v.visit(*this); }
+
+ReLU6::ReLU6(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/ReduceMax.cc b/runtime/neurun/core/src/ir/operation/ReduceMax.cc
new file mode 100644
index 000000000..b7ef2c5a9
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/ReduceMax.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/ReduceMax.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void ReduceMax::accept(OperationVisitor &v) const { v.visit(*this); }
+
+ReduceMax::ReduceMax(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+                     const Param &param)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/ReduceMin.cc b/runtime/neurun/core/src/ir/operation/ReduceMin.cc
new file mode 100644
index 000000000..84d7e0cc5
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/ReduceMin.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/ReduceMin.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void ReduceMin::accept(OperationVisitor &v) const { v.visit(*this); }
+
+ReduceMin::ReduceMin(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+                     const Param &param)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/ReduceSum.cc b/runtime/neurun/core/src/ir/operation/ReduceSum.cc
new file mode 100644
index 000000000..7e3b19bd6
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/ReduceSum.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/ReduceSum.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void ReduceSum::accept(OperationVisitor &v) const { v.visit(*this); }
+
+ReduceSum::ReduceSum(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+                     const Param &param)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/Reshape.cc b/runtime/neurun/core/src/ir/operation/Reshape.cc
new file mode 100644
index 000000000..bae37e12f
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/Reshape.cc
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/Reshape.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void Reshape::accept(OperationVisitor &v) const { v.visit(*this); }
+
+Reshape::Reshape(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/ResizeBilinear.cc b/runtime/neurun/core/src/ir/operation/ResizeBilinear.cc
new file mode 100644
index 000000000..55ae4815d
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/ResizeBilinear.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/ResizeBilinear.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void ResizeBilinear::accept(OperationVisitor &v) const { v.visit(*this); }
+
+ResizeBilinear::ResizeBilinear(const OperandIndexSequence &inputs,
+                               const OperandIndexSequence &outputs, const Param &param)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/SQRT.cc b/runtime/neurun/core/src/ir/operation/SQRT.cc
new file mode 100644
index 000000000..6c6daa3a0
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/SQRT.cc
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/SQRT.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void SQRT::accept(OperationVisitor &v) const { v.visit(*this); }
+
+SQRT::SQRT(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/Slice.cc b/runtime/neurun/core/src/ir/operation/Slice.cc
new file mode 100644
index 000000000..88014d1e4
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/Slice.cc
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/Slice.h"
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void Slice::accept(OperationVisitor &v) const { v.visit(*this); }
+
+Slice::Slice(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+             const Param &param)
+    : Operation{OperandConstraint::createExact(3u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/Softmax.cc b/runtime/neurun/core/src/ir/operation/Softmax.cc
new file mode 100644
index 000000000..6b3a6b164
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/Softmax.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/Softmax.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void Softmax::accept(OperationVisitor &v) const { v.visit(*this); }
+
+Softmax::Softmax(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+                 const Param &param)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/SpaceToBatchND.cc b/runtime/neurun/core/src/ir/operation/SpaceToBatchND.cc
new file mode 100644
index 000000000..a07453504
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/SpaceToBatchND.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/SpaceToBatchND.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void SpaceToBatchND::accept(OperationVisitor &v) const { v.visit(*this); }
+
+SpaceToBatchND::SpaceToBatchND(const OperandIndexSequence &inputs,
+                               const OperandIndexSequence &outputs)
+    : Operation{OperandConstraint::createExact(3u), inputs, outputs}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/SpaceToDepth.cc b/runtime/neurun/core/src/ir/operation/SpaceToDepth.cc
new file mode 100644
index 000000000..ca16bd92f
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/SpaceToDepth.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/SpaceToDepth.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void SpaceToDepth::accept(OperationVisitor &v) const { v.visit(*this); }
+
+SpaceToDepth::SpaceToDepth(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+                           const Param &param)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/Split.cc b/runtime/neurun/core/src/ir/operation/Split.cc
new file mode 100644
index 000000000..a4b15a9b2
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/Split.cc
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "ir/operation/Split.h"
+#include <cassert>
+#include "ir/OperationVisitor.h"
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+void Split::accept(OperationVisitor &v) const { v.visit(*this); }
+Split::Split(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+             const Param &param)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}, _param{param}
+{
+}
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/SquaredDifference.cc b/runtime/neurun/core/src/ir/operation/SquaredDifference.cc
new file mode 100644
index 000000000..141fb7560
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/SquaredDifference.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/SquaredDifference.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void SquaredDifference::accept(OperationVisitor &v) const { v.visit(*this); }
+
+SquaredDifference::SquaredDifference(const OperandIndexSequence &inputs,
+                                     const OperandIndexSequence &outputs)
+    : Operation{OperandConstraint::createExact(2u), inputs, outputs}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/Squeeze.cc b/runtime/neurun/core/src/ir/operation/Squeeze.cc
new file mode 100644
index 000000000..22ee5763d
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/Squeeze.cc
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/Squeeze.h"
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void Squeeze::accept(OperationVisitor &v) const { v.visit(*this); }
+
+Squeeze::Squeeze(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+                 const Param &param)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}, _param(param)
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/StridedSlice.cc b/runtime/neurun/core/src/ir/operation/StridedSlice.cc
new file mode 100644
index 000000000..f764dccc0
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/StridedSlice.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/StridedSlice.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void StridedSlice::accept(OperationVisitor &v) const { v.visit(*this); }
+
+StridedSlice::StridedSlice(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+                           const Param &param)
+    : Operation{OperandConstraint::createExact(3u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/Sub.cc b/runtime/neurun/core/src/ir/operation/Sub.cc
new file mode 100644
index 000000000..7d83e3d74
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/Sub.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/Sub.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void Sub::accept(OperationVisitor &v) const { v.visit(*this); }
+
+Sub::Sub(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+         const Param &param)
+    : Operation{OperandConstraint::createExact(2u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/Tanh.cc b/runtime/neurun/core/src/ir/operation/Tanh.cc
new file mode 100644
index 000000000..a3125e947
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/Tanh.cc
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/Tanh.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void Tanh::accept(OperationVisitor &v) const { v.visit(*this); }
+
+Tanh::Tanh(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/TopKV2.cc b/runtime/neurun/core/src/ir/operation/TopKV2.cc
new file mode 100644
index 000000000..6fabd34a3
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/TopKV2.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/TopKV2.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void TopKV2::accept(OperationVisitor &v) const { v.visit(*this); }
+
+TopKV2::TopKV2(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+               const Param &param)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/Transpose.cc b/runtime/neurun/core/src/ir/operation/Transpose.cc
new file mode 100644
index 000000000..74239b0f6
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/Transpose.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/Transpose.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void Transpose::accept(OperationVisitor &v) const { v.visit(*this); }
+
+Transpose::Transpose(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+                     const Param &param)
+    : Operation{OperandConstraint::createExact(2u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/TransposeConv.cc b/runtime/neurun/core/src/ir/operation/TransposeConv.cc
new file mode 100644
index 000000000..30664e974
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/TransposeConv.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ir/operation/TransposeConv.h"
+
+#include <cassert>
+
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+
+void TransposeConv::accept(OperationVisitor &v) const { v.visit(*this); }
+
+TransposeConv::TransposeConv(const OperandIndexSequence &inputs,
+                             const OperandIndexSequence &outputs, const Param &param)
+    : Operation{OperandConstraint::createExact(3u), inputs, outputs}, _param{param}
+{
+}
+
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/operation/Unpack.cc b/runtime/neurun/core/src/ir/operation/Unpack.cc
new file mode 100644
index 000000000..7c2c24892
--- /dev/null
+++ b/runtime/neurun/core/src/ir/operation/Unpack.cc
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "ir/operation/Unpack.h"
+#include "ir/OperationVisitor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace operation
+{
+void Unpack::accept(OperationVisitor &v) const { v.visit(*this); }
+Unpack::Unpack(const OperandIndexSequence &inputs, const OperandIndexSequence &outputs,
+               const Param &param)
+    : Operation{OperandConstraint::createExact(1u), inputs, outputs}, _param{param}
+{
+}
+} // namespace operation
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/pass/ConstantInsertionPass.cc b/runtime/neurun/core/src/ir/pass/ConstantInsertionPass.cc
new file mode 100644
index 000000000..8f8ebff1b
--- /dev/null
+++ b/runtime/neurun/core/src/ir/pass/ConstantInsertionPass.cc
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ConstantInsertionPass.h"
+
+#include "backend/Backend.h"
+#include <ir/Graph.h>
+#include "ir/operand/Shape4DConvert.h"
+#include <util/Utils.h>
+
+namespace neurun
+{
+namespace ir
+{
+namespace pass
+{
+
+void ConstantInsertionPass::callback(const OperationIndex &node_index, Operation &node)
+{
+  const auto &subgraph_index = _graph.subgraphs().getOperation(node_index);
+  const auto subg_lower_info = _graph.getLowerInfo(subgraph_index);
+  const auto backend = subg_lower_info->backend();
+  const auto layout = subg_lower_info->layout();
+  const auto factor = operand::PermuteFactor{backend, layout};
+
+  for (const auto input : node.getInputs())
+  {
+    auto &object = _graph.operands().at(input);
+
+    if (object.isConstant())
+    {
+      const auto key = ReplaceKey{input, factor};
+      if (_replace_operands_map.count(key) == 0)
+      {
+        auto new_object = object;
+        // TODO Remove const_case
+        const_cast<std::list<OperationIndex> &>(new_object.getDef().list()).clear();
+        const_cast<std::list<OperationIndex> &>(new_object.getUses().list()).clear();
+        const auto new_index = _graph.operands().emplace(new_object);
+        _replace_operands_map[key] = new_index;
+
+        _graph.setLowerInfo(new_index, nnfw::cpp14::make_unique<operand::LowerInfo>(
+                                           operand::asShape4D(new_object.shape())));
+        _graph.getLowerInfo(new_index)->addDefPermuteFactor(factor);
+      }
+
+      const auto replaced_input = _replace_operands_map[key];
+      // Update op_seq
+      if (_graph.subgraphs().at(subgraph_index).getInputs().contains(input))
+      {
+        _graph.subgraphs().at(subgraph_index).replaceInput(input, replaced_input);
+      }
+
+      // Update node
+      node.replaceInput(input, replaced_input);
+
+      // Update operand
+      auto &replaced_object = _graph.operands().at(replaced_input);
+      replaced_object.appendUse(node_index);
+
+      // Update lower_info
+      auto replaced_lower_info = _graph.getLowerInfo(replaced_input);
+      replaced_lower_info->addUsePermuteFactor(factor);
+
+      // Remove this node from def and uses of origin operand
+      if (object.getDef().contains(node_index))
+      {
+        object.removeDef(node_index);
+      }
+      object.removeUse(node_index);
+
+      // Remove origin operand
+      if (object.getDef().size() == 0 && object.getUses().size() == 0)
+      {
+        _graph.removeOperand(input);
+        _graph.removeLowerInfo(input);
+      }
+    }
+  }
+
+  // Now this runtime does not support the node making output as constant
+  for (const auto &output : node.getOutputs())
+  {
+    UNUSED_RELEASE(output);
+    assert(!_graph.operands().at(output).isConstant());
+  }
+}
+
+} // namespace pass
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/pass/ConstantInsertionPass.h b/runtime/neurun/core/src/ir/pass/ConstantInsertionPass.h
new file mode 100644
index 000000000..40476b20e
--- /dev/null
+++ b/runtime/neurun/core/src/ir/pass/ConstantInsertionPass.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_GRAPH_PASS_CONSTANT_INSERTION_PASS_H__
+#define __NEURUN_GRAPH_PASS_CONSTANT_INSERTION_PASS_H__
+
+#include <ir/operand/PermuteFactor.h>
+#include <ir/Index.h>
+#include "OperationPass.h"
+#include <unordered_map>
+#include <utility>
+
+namespace neurun
+{
+namespace ir
+{
+namespace pass
+{
+
+class ConstantInsertionPass : public OperationPass
+{
+public:
+  using OperationPass::OperationPass;
+
+public:
+  std::string id() final { return "ConstantInsertionPass"; }
+
+public:
+  void callback(const OperationIndex &index, Operation &node) final;
+
+private:
+  struct ReplaceKey
+  {
+    OperandIndex index;
+    operand::PermuteFactor factor;
+
+    bool operator==(const ReplaceKey &other) const
+    {
+      return index == other.index && factor == other.factor;
+    }
+  };
+
+  /**
+   * @brief Structure that provides hash function of ReplaceKey
+   */
+  struct KeyHasher
+  {
+    std::size_t operator()(const ReplaceKey &key) const noexcept
+    {
+      using std::hash;
+      return hash<OperandIndex>()(key.index) ^ (hash<operand::PermuteFactor>()(key.factor) << 1);
+    }
+  };
+
+  std::unordered_map<ReplaceKey, OperandIndex, KeyHasher> _replace_operands_map;
+};
+
+} // namespace pass
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_GRAPH_PASS_CONSTANT_INSERTION_PASS_H__
diff --git a/runtime/neurun/core/src/ir/pass/OperandPass.cc b/runtime/neurun/core/src/ir/pass/OperandPass.cc
new file mode 100644
index 000000000..f31d0d850
--- /dev/null
+++ b/runtime/neurun/core/src/ir/pass/OperandPass.cc
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "OperandPass.h"
+
+#include "ir/Graph.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace pass
+{
+
+void OperandPass::run()
+{
+  _graph.operands().iterate(
+      [&](const OperandIndex &index, Operand &object) { callback(index, object); });
+}
+
+} // namespace pass
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/pass/OperandPass.h b/runtime/neurun/core/src/ir/pass/OperandPass.h
new file mode 100644
index 000000000..c9fbf541d
--- /dev/null
+++ b/runtime/neurun/core/src/ir/pass/OperandPass.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_GRAPH_PASS_OPERAND_PASS_H__
+#define __NEURUN_GRAPH_PASS_OPERAND_PASS_H__
+
+#include "Pass.h"
+#include "ir/Index.h"
+
+namespace neurun
+{
+namespace ir
+{
+class Operand;
+} // namespace ir
+} // namespace neurun
+
+namespace neurun
+{
+namespace ir
+{
+namespace pass
+{
+
+class OperandPass : public Pass
+{
+public:
+  using Pass::Pass;
+
+public:
+  std::string id() override = 0;
+  void run() override final;
+  virtual void callback(const OperandIndex &i, Operand &o) = 0;
+};
+
+} // namespace pass
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_GRAPH_PASS_OPERAND_PASS_H__
diff --git a/runtime/neurun/core/src/ir/pass/OperationPass.cc b/runtime/neurun/core/src/ir/pass/OperationPass.cc
new file mode 100644
index 000000000..c9438ee39
--- /dev/null
+++ b/runtime/neurun/core/src/ir/pass/OperationPass.cc
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "OperationPass.h"
+
+#include "ir/Index.h"
+#include "ir/Operation.h"
+#include "ir/Graph.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace pass
+{
+
+void OperationPass::run()
+{
+  _graph.operations().iterate(
+      [&](const OperationIndex &index, Operation &node) { callback(index, node); });
+}
+
+} // namespace pass
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/pass/OperationPass.h b/runtime/neurun/core/src/ir/pass/OperationPass.h
new file mode 100644
index 000000000..4b7de7109
--- /dev/null
+++ b/runtime/neurun/core/src/ir/pass/OperationPass.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file  OperationPass.h
+ * @brief This file contains OperationPass class
+ */
+
+#ifndef __NEURUN_GRAPH_PASS_OPERATION_PASS_H__
+#define __NEURUN_GRAPH_PASS_OPERATION_PASS_H__
+
+#include "Pass.h"
+#include "ir/Index.h"
+
+namespace neurun
+{
+namespace ir
+{
+class Operation;
+} // namespace ir
+} // namespace neurun
+
+namespace neurun
+{
+namespace ir
+{
+namespace pass
+{
+
+/**
+ * @brief  Class to iterate over operations and calls callback() method
+ */
+class OperationPass : public Pass
+{
+public:
+  using Pass::Pass;
+
+public:
+  /**
+   * @brief Returns string id for this pass. Same with class name.
+   *
+   * @return string id
+   */
+  std::string id() override = 0;
+
+  /**
+   * @brief Be called for all nodes of graph.
+   * @param index is the index of a node in graph
+   * @param node is the node in graph
+   */
+  virtual void callback(const OperationIndex &index, Operation &node) = 0;
+
+  /**
+   * @brief Run the pass
+   */
+  void run() final;
+};
+
+} // namespace pass
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_GRAPH_PASS_OPERATION_PASS_H__
diff --git a/runtime/neurun/core/src/ir/pass/Pass.h b/runtime/neurun/core/src/ir/pass/Pass.h
new file mode 100644
index 000000000..0aa0f36a6
--- /dev/null
+++ b/runtime/neurun/core/src/ir/pass/Pass.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_GRAPH_PASS_PASS_H__
+#define __NEURUN_GRAPH_PASS_PASS_H__
+
+#include <string>
+
+namespace neurun
+{
+namespace ir
+{
+class Graph;
+} // namespace ir
+} // namespace neurun
+
+namespace neurun
+{
+namespace ir
+{
+namespace pass
+{
+
+class Pass
+{
+public:
+  Pass(Graph &graph) : _graph{graph} {}
+  virtual ~Pass() = default;
+
+public:
+  virtual std::string id() = 0;
+  virtual void run() = 0;
+
+protected:
+  Graph &_graph;
+};
+
+} // namespace pass
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_GRAPH_PASS_PASS_H__
diff --git a/runtime/neurun/core/src/ir/pass/PermutationEliminationPass.cc b/runtime/neurun/core/src/ir/pass/PermutationEliminationPass.cc
new file mode 100644
index 000000000..71f3d7e82
--- /dev/null
+++ b/runtime/neurun/core/src/ir/pass/PermutationEliminationPass.cc
@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "PermutationEliminationPass.h"
+
+#include "ir/Operand.h"
+#include "ir/operand/LowerInfo.h"
+#include "ir/Graph.h"
+#include "backend/IConfig.h"
+#include "util/logging.h"
+#include "compiler/BackendResolver.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace pass
+{
+void PermutationEliminationPass::callback(const OperandIndex &inp_index, Operand &object)
+{
+  if (_graph.getInputs().contains(inp_index))
+  {
+    eliminateInput(inp_index, object);
+  }
+  else if (_graph.getOutputs().contains(inp_index))
+  {
+    eliminateOutput(inp_index, object);
+  }
+}
+
+void PermutationEliminationPass::eliminateInput(const OperandIndex &inp_index, Operand &object)
+{
+  auto &model_inputs = _graph.getInputs();
+
+  // get uses of the model's given input
+  auto uses = object.getUses();
+
+  // input must be used just by permutation
+  if (uses.size() != 1)
+  {
+    return;
+  }
+
+  for (auto input_use : uses.list())
+  {
+    auto &perm_operation = _graph.operations().at(input_use);
+    auto perm_inputs = perm_operation.getInputs();
+
+    auto perm_outputs = perm_operation.getOutputs();
+
+    if (!isPermuteLayerToEliminate(perm_inputs, perm_outputs, true))
+    {
+      return;
+    }
+
+    assert(perm_inputs.at(0) == inp_index);
+
+    VERBOSE(PermutationEliminationPass::EliminateInput) << "remove NHWC_TO_NCHW permutation\n";
+
+    // set model's new input, which was output of permutation
+    model_inputs.replace(inp_index, perm_outputs.at(0));
+
+    // remove model's input, which is also input of permutation
+    _graph.removeOperand(inp_index);
+
+    // remove permutation operation
+    assert(_graph.subgraphs().containsOperation(input_use));
+    auto subg_idx = _graph.subgraphs().getOperation(input_use);
+    _graph.subgraphs().remove(subg_idx);
+    _graph.operations().remove(input_use);
+
+    VERBOSE(PermutationEliminationPass::EliminateInput)
+        << inp_index.value() << " is model's input and is removed. New input is "
+        << perm_outputs.at(0).value() << "\n"
+        << input_use.value() << " is removed permutation operation\n";
+  }
+}
+
+void PermutationEliminationPass::eliminateOutput(const OperandIndex &out_index, Operand &object)
+{
+  auto &model_outputs = _graph.getOutputs();
+
+  // get defs of the model's given output
+  auto defs = object.getDef();
+
+  // output must use just permutation
+  if (defs.size() != 1)
+  {
+    return;
+  }
+
+  for (auto output_def : defs.list())
+  {
+    auto &perm_operation = _graph.operations().at(output_def);
+    auto perm_outputs = perm_operation.getOutputs();
+
+    auto perm_inputs = perm_operation.getInputs();
+    if (!isPermuteLayerToEliminate(perm_inputs, perm_outputs, false))
+    {
+      return;
+    }
+
+    assert(perm_outputs.at(0) == out_index);
+
+    VERBOSE(PermutationEliminationPass::EliminateOutput) << "remove NCHW_TO_NHWC permutation\n";
+
+    // Update operations' output that is used by permute operand
+    for (auto perm_input_index : perm_inputs)
+    {
+      auto &perm_input_operand = _graph.operands().at(perm_input_index);
+      perm_input_operand.removeUse(output_def);
+    }
+
+    // set model's new output, which was input of permutation
+    model_outputs.replace(out_index, perm_inputs.at(0));
+
+    // remove model's output, which is also output of permutation
+    _graph.removeOperand(out_index);
+
+    // remove permutation operation
+    assert(_graph.subgraphs().containsOperation(output_def));
+    auto subg_idx = _graph.subgraphs().getOperation(output_def);
+    _graph.subgraphs().remove(subg_idx);
+    _graph.operations().remove(output_def);
+
+    VERBOSE(PermutationEliminationPass::EliminateOutput)
+        << out_index.value() << " is model's output and is removed. New output is "
+        << perm_inputs.at(0).value() << "\n"
+        << output_def.value() << " is removed permutation operation\n";
+  }
+}
+
+bool PermutationEliminationPass::isPermuteLayerToEliminate(const OperandIndexSequence &inp_indexes,
+                                                           const OperandIndexSequence &out_indexes,
+                                                           bool is_for_model_input)
+{
+  auto input_def_factors = _graph.getLowerInfo(inp_indexes.at(0))->def_factors();
+  auto output_def_factors = _graph.getLowerInfo(out_indexes.at(0))->def_factors();
+
+  auto input_layout = input_def_factors.getOnlyElement().layout();
+  auto output_layout = output_def_factors.getOnlyElement().layout();
+
+  if (input_def_factors.size() != 1 || output_def_factors.size() != 1)
+  {
+    return false;
+  }
+
+  // all operands' factor must be the same
+  for (auto index : inp_indexes)
+  {
+    auto op_factor_set = _graph.getLowerInfo(index)->def_factors();
+    if (op_factor_set.size() != 1 ||
+        input_layout != _graph.getLowerInfo(index)->def_factors().getOnlyElement().layout())
+    {
+      return false;
+    }
+  }
+  // all operands' factor must be the same
+  for (auto index : out_indexes)
+  {
+    auto op_factor_set = _graph.getLowerInfo(index)->def_factors();
+    if (op_factor_set.size() != 1 ||
+        output_layout != _graph.getLowerInfo(index)->def_factors().getOnlyElement().layout())
+    {
+      return false;
+    }
+  }
+
+  if (is_for_model_input)
+  {
+    // check if this is NHWC_TO_NCHW permutation: must have single input, which is model's input
+    return (inp_indexes.size() == 1 && input_layout == Layout::NHWC &&
+            output_layout == Layout::NCHW);
+  }
+
+  // check if this is NCHW_TO_NHWC permutation: must have single output, which is model's output
+  return (out_indexes.size() == 1 && input_layout == Layout::NCHW && output_layout == Layout::NHWC);
+}
+
+} // namespace pass
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/pass/PermutationEliminationPass.h b/runtime/neurun/core/src/ir/pass/PermutationEliminationPass.h
new file mode 100644
index 000000000..4431eabbc
--- /dev/null
+++ b/runtime/neurun/core/src/ir/pass/PermutationEliminationPass.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_GRAPH_PASS_PERMUTATION_ELIMINATION_PASS_H__
+#define __NEURUN_GRAPH_PASS_PERMUTATION_ELIMINATION_PASS_H__
+
+#include "OperandPass.h"
+#include "ir/Operand.h"
+#include "ir/OperandIndexSequence.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace pass
+{
+
+class PermutationEliminationPass : public OperandPass
+{
+public:
+  using OperandPass::OperandPass;
+
+public:
+  std::string id() override { return "PermutationEliminationPass"; }
+
+  void callback(const OperandIndex &index, Operand &object) override;
+
+private:
+  /**
+   * @brief Remove Permute operation that permutates input
+   *
+   * Note: This function aslo removes model's input and
+   * sets output of permutation as model's new input
+   *
+   * @param inp_index is the target operand index for the elimination
+   * @param object is the target operand object for the elimination
+   *
+   * @return
+   */
+  void eliminateInput(const OperandIndex &inp_index, Operand &object);
+
+  /**
+   * @brief Remove Permute operation that permutates output of a model
+   *
+   * Note: This function aslo removes model's output and
+   * sets input of permutation as model's new output
+   *
+   * @param out_index is the target operand index for the elimination
+   * @param object is the target operand object for the elimination
+   *
+   * @return
+   */
+  void eliminateOutput(const OperandIndex &out_index, Operand &object);
+
+  /**
+   * @brief Determine if passed operands are permute layer's input and output, that must be
+   * eliminated
+   *
+   * @param inp_index indexes of the input operand to operation
+   * @param out_index indexes of the output operand to operation
+   * @param is_for_model_input checking for model's input or output
+   *
+   * @return if it is permutation layer
+   */
+  bool isPermuteLayerToEliminate(const OperandIndexSequence &inp_indexes,
+                                 const OperandIndexSequence &out_indexes, bool is_for_model_input);
+};
+
+} // namespace pass
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_GRAPH_PASS_PERMUTATION_ELIMINATION_PASS_H__
diff --git a/runtime/neurun/core/src/ir/pass/PermutationInsertionPass.cc b/runtime/neurun/core/src/ir/pass/PermutationInsertionPass.cc
new file mode 100644
index 000000000..052e3026a
--- /dev/null
+++ b/runtime/neurun/core/src/ir/pass/PermutationInsertionPass.cc
@@ -0,0 +1,209 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "PermutationInsertionPass.h"
+
+#include <cassert>
+#include <utility>
+#include <unordered_map>
+
+#include "ir/Operand.h"
+#include "ir/operation/LowerInfo.h"
+#include "ir/Graph.h"
+#include "backend/IConfig.h"
+#include "util/logging.h"
+#include "cpp14/memory.h"
+#include "ir/operation/Permute.h"
+#include "ir/operand/Shape4DConvert.h"
+#include "compiler/BackendResolver.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace pass
+{
+
+void PermutationInsertionPass::callback(const OperandIndex &index, Operand &object)
+{
+  auto &&operand_li = _graph.getLowerInfo(index);
+  assert(operand_li);
+
+  // NOTE Later, constants also will have Def
+  // Ignore constants
+  if (operand_li->def_factors().size() == 0)
+  {
+    return;
+  }
+
+  std::list<OperationIndex> permute_indexes;
+
+  // Build a map for all necessary type of operands
+  std::unordered_map<operand::PermuteFactor, OperandIndex> factor_to_index;
+  {
+    assert(operand_li->def_factors().size() == 1);
+    for (auto factor : operand_li->def_factors())
+    {
+      factor_to_index.emplace(factor, index);
+    }
+
+    auto insert_set = operand_li->use_factors() - operand_li->def_factors();
+    for (auto factor : insert_set)
+    {
+      const auto permute_operation_index = insertPermute(index, factor);
+      permute_indexes.push_back(permute_operation_index);
+      VERBOSE(PermutationInsertionPass) << "Insert 'Permute' operation for operand "
+                                        << index.value() << std::endl;
+      const auto &permute_operation = _graph.operations().at(permute_operation_index);
+      const auto permuted_operand_index = permute_operation.getOutputs().at(0);
+      factor_to_index.emplace(factor, permuted_operand_index);
+    }
+  }
+
+  // Update operations' input that uses this operand
+  {
+    std::list<OperationIndex> remove_list;
+
+    auto uses = object.getUses();
+    for (auto use : uses.list())
+    {
+      // If permute operation, ignore it
+      if (std::find(permute_indexes.begin(), permute_indexes.end(), use) != permute_indexes.end())
+        continue;
+
+      auto &operation = _graph.operations().at(use);
+      assert(_graph.subgraphs().containsOperation(use));
+      auto subg_index = _graph.subgraphs().getOperation(use);
+      auto subg_li = _graph.getLowerInfo(subg_index);
+      assert(subg_li);
+      const auto subg_layout = subg_li->layout();
+      const backend::Backend *backend = subg_li->backend();
+      assert(backend);
+      auto use_node_inputs = operation.getInputs();
+      assert(use_node_inputs.contains(index));
+
+      auto new_index = factor_to_index.at({backend, subg_layout});
+      if (index != new_index)
+      {
+        // Update from op_seq
+        _graph.subgraphs().at(subg_index).replaceInput(index, new_index);
+
+        // Update from operation
+        operation.replaceInput(index, new_index);
+
+        // Update from operand
+        remove_list.push_back(
+            use); // Removal should be done in another loop since we are in the loop
+        _graph.operands().at(new_index).appendUse(use);
+      }
+    }
+
+    for (auto &operation : remove_list)
+    {
+      object.removeUse(operation);
+    }
+  }
+}
+
+OperationIndex PermutationInsertionPass::insertPermute(const OperandIndex &operand_index,
+                                                       const operand::PermuteFactor &factor)
+{
+  assert(!_graph.isBuildingPhase());
+
+  auto &operand = _graph.operands().at(operand_index);
+
+  // Generate output operand and permute operation
+  auto out_operand_index = _graph.addOperand(operand.shape(), operand.typeInfo());
+  // change model output if operand_index is model output index
+  auto &model_outputs = _graph.getOutputs();
+  if (model_outputs.contains(operand_index))
+  {
+    model_outputs.replace(operand_index, out_operand_index);
+  }
+
+  // Find Permute information
+  auto input_backend = _graph.getLowerInfo(operand_index)->def_factors().getOnlyElement().backend();
+  auto output_backend = factor.backend();
+  // NOTE Permute may not have specific layout because the layout of input and output may be
+  // different.
+  const auto permute_node_layout = Layout::UNKNOWN;
+  const auto permute_node_backend = backend::BackendManager::get().getDefault();
+  const operand::PermuteFactor permute_node_factor{permute_node_backend, permute_node_layout};
+
+  // Update LowerInfo of input operand
+  auto operand_lower_info = _graph.getLowerInfo(operand_index);
+  operand_lower_info->removeUsePermuteFactor(factor);
+  operand_lower_info->addUsePermuteFactor(permute_node_factor);
+
+  // Update LowerInfo of output operand
+  auto out_operand_li =
+      nnfw::cpp14::make_unique<operand::LowerInfo>(operand::asShape4D(operand.shape()));
+
+  // The input and output factors of all nodes will be the same except Permute. So Tensor's
+  // allocators allocates memory using only the information of def permutation factor now.
+  // TODO Change param to permute_node_factor
+  out_operand_li->addDefPermuteFactor(factor);
+  out_operand_li->addUsePermuteFactor(factor);
+  _graph.setLowerInfo(out_operand_index, std::move(out_operand_li));
+
+  auto input_backend_ctx = _graph.backend_resolver()->getBackendContext(input_backend);
+  auto output_backend_ctx = _graph.backend_resolver()->getBackendContext(output_backend);
+
+  // Insert permute operation to the graph
+  const auto input_layout =
+      _graph.getLowerInfo(operand_index)->def_factors().getOnlyElement().layout();
+  const auto output_layout = factor.layout();
+  using Permute = operation::Permute;
+  const auto permute_type = [&]() {
+    if (input_layout == Layout::NHWC && output_layout == Layout::NCHW)
+    {
+      return Permute::Type::NHWC_TO_NCHW;
+    }
+    else if (input_layout == Layout::NCHW && output_layout == Layout::NHWC)
+    {
+      return Permute::Type::NCHW_TO_NHWC;
+    }
+    else
+    {
+      return Permute::Type::COPY;
+    }
+  }();
+  auto insert_node = nnfw::cpp14::make_unique<Permute>(
+      operand_index, out_operand_index, input_backend_ctx, output_backend_ctx, permute_type);
+
+  auto node_index = _graph.operations().push(std::move(insert_node));
+  const auto &node = _graph.operations().at(node_index);
+
+  // OpSequence
+  {
+    auto subg_index = _graph.subgraphs().emplace(node_index, node, permute_node_layout);
+    auto &subg = _graph.subgraphs().at(subg_index);
+    subg.setInputs(node.getInputs());
+    subg.setOutputs(node.getOutputs());
+    _graph.setLowerInfo(subg_index, nnfw::cpp14::make_unique<operation::LowerInfo>(
+                                        permute_node_backend, permute_node_layout));
+  }
+
+  // Update Use/Def info
+  {
+    _graph.operands().at(operand_index).appendUse(node_index);
+    _graph.operands().at(out_operand_index).appendDef(node_index);
+  }
+  return node_index;
+}
+} // namespace pass
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/pass/PermutationInsertionPass.h b/runtime/neurun/core/src/ir/pass/PermutationInsertionPass.h
new file mode 100644
index 000000000..4065fc6ac
--- /dev/null
+++ b/runtime/neurun/core/src/ir/pass/PermutationInsertionPass.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_GRAPH_PASS_PERMUTATION_INSERTION_PASS_H__
+#define __NEURUN_GRAPH_PASS_PERMUTATION_INSERTION_PASS_H__
+
+#include "OperandPass.h"
+#include "ir/Operand.h" //for OperationIndex
+#include "backend/BackendManager.h"
+#include "ir/operand/PermuteFactor.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace pass
+{
+
+class PermutationInsertionPass : public OperandPass
+{
+public:
+  using OperandPass::OperandPass;
+
+public:
+  std::string id() override { return "PermutationInsertionPass"; }
+  void callback(const OperandIndex &index, Operand &object) override;
+
+  /**
+   * @brief Insert Permute operation that has given operand as input
+   *
+   * @param operand_index is the target operand index for the insertion
+   * @param factor is the output operand's backend type and layout
+   *
+   * @return OperationIndex
+   */
+  OperationIndex insertPermute(const OperandIndex &operand_index,
+                               const operand::PermuteFactor &factor);
+
+private:
+};
+
+} // namespace pass
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_GRAPH_PASS_PERMUTATION_INSERTION_PASS_H__
diff --git a/runtime/neurun/core/src/ir/pass/PermutationOperationPass.cc b/runtime/neurun/core/src/ir/pass/PermutationOperationPass.cc
new file mode 100644
index 000000000..41a1ad903
--- /dev/null
+++ b/runtime/neurun/core/src/ir/pass/PermutationOperationPass.cc
@@ -0,0 +1,230 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "PermutationOperationPass.h"
+
+#include "backend/Backend.h"
+#include "backend/IConfig.h"
+#include "ir/Graph.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace pass
+{
+
+void PermutationOperationPass::callback(const OperationIndex &, Operation &node)
+{
+  node.accept(*this);
+};
+
+void PermutationOperationPass::changeToKeepLayout(const Operation &node)
+{
+  const auto &output_ind = node.getOutputs().at(0);
+  const auto &output_obj = _graph.operands().at(output_ind);
+
+  assert(output_obj.getDef().size() == 1);
+  const auto &node_index = output_obj.getDef().list().front();
+  const auto &subg_index = _graph.subgraphs().getOperation(node_index);
+
+  const auto frontend_layout = _graph.subgraphs().at(subg_index).getLayout();
+  const auto backend_layout = _graph.getLowerInfo(subg_index)->layout();
+
+  if (frontend_layout == backend_layout)
+  {
+    return;
+  }
+
+  // CPU supports only NHWC now
+  if (_graph.getLowerInfo(subg_index)->backend()->config()->id() != "cpu")
+  {
+    // TODO Change backend of this node
+    assert(frontend_layout == Layout::NHWC || backend_layout == Layout::UNKNOWN);
+  }
+
+  // Divide op_seq based on target operation
+  {
+    auto &above_subg = _graph.subgraphs().at(subg_index);
+
+    // Create new op_seq and move information from existing op_seq to new op_seq if target
+    // node is the end of op_seq
+    auto it = above_subg.begin();
+    // Find iterator of target node in op_seq
+    while ((it++)->index != node_index)
+      ;
+    if (it != above_subg.end())
+    {
+      const auto &below_subg_index =
+          _graph.subgraphs().emplace(it->index, *it->node, above_subg.getLayout());
+      auto &below_subg = _graph.subgraphs().at(below_subg_index);
+      below_subg.setInputs(it->node->getInputs());
+      below_subg.setOutputs(it->node->getOutputs());
+
+      std::vector<OperationIndex> remove_list;
+      remove_list.emplace_back(it->index);
+      while (++it != above_subg.end())
+      {
+        below_subg.appendOperation(it->index, *it->node);
+        below_subg.setOutputs(it->node->getOutputs());
+        remove_list.emplace_back(it->index);
+      }
+
+      above_subg.setOutputs(node.getOutputs());
+      for (const auto &index : remove_list)
+      {
+        above_subg.remove(index);
+      }
+
+      const auto subg_li = _graph.getLowerInfo(subg_index);
+      _graph.setLowerInfo(below_subg_index, nnfw::cpp14::make_unique<operation::LowerInfo>(
+                                                subg_li->backend(), subg_li->layout()));
+    }
+  }
+
+  // Remove target operation from op_seq and insert the target operation to new op_seq
+  {
+    const auto backend = _graph.getLowerInfo(subg_index)->backend();
+
+    // Remove target operation from subraph
+    _graph.subgraphs().removeFromSubgraph(node_index);
+
+    if (!_graph.subgraphs().exist(subg_index))
+    {
+      // Remove lowerinfo for op_seq of target operation if the op_seq does not exist
+      _graph.removeLowerInfo(subg_index);
+    }
+    else
+    {
+      // Update op_seq of target operation if the op_seq exists
+      auto &above_subg = _graph.subgraphs().at(subg_index);
+      const auto last_node = (--above_subg.end())->node;
+      above_subg.setOutputs(last_node->getOutputs());
+    }
+
+    // Create new op_seq and set information to the op_seq
+    auto new_subg_index = _graph.subgraphs().emplace(node_index, node, frontend_layout);
+    auto &new_subg = _graph.subgraphs().at(new_subg_index);
+    new_subg.setInputs(node.getInputs());
+    new_subg.setOutputs(node.getOutputs());
+    _graph.setLowerInfo(new_subg_index,
+                        nnfw::cpp14::make_unique<operation::LowerInfo>(backend, frontend_layout));
+  }
+
+  // Change PermuteFactors of operands of target node
+  {
+    const auto &subg_index = _graph.subgraphs().getOperation(node_index);
+    const auto subg_li = _graph.getLowerInfo(subg_index);
+    const auto backend = subg_li->backend();
+    const operand::PermuteFactor removed_factor{backend, backend_layout};
+    const operand::PermuteFactor new_factor{backend, frontend_layout};
+    for (const auto &input : node.getInputs())
+    {
+      bool canRemove = true;
+      for (const auto &use : _graph.operands().at(input).getUses().list())
+      {
+        if (use != node_index)
+        {
+          const auto &use_subg_index = _graph.subgraphs().getOperation(use);
+          auto use_subg_li = _graph.getLowerInfo(use_subg_index);
+          if (use_subg_li->backend() == backend && use_subg_li->layout() == backend_layout)
+          {
+            canRemove = false;
+            break;
+          }
+        }
+      }
+
+      auto lower_info = _graph.getLowerInfo(input);
+      if (canRemove)
+      {
+        lower_info->removeUsePermuteFactor(removed_factor);
+      }
+      lower_info->addUsePermuteFactor(new_factor);
+
+      // Whether if node's input is an input of model or a constant
+      if (_graph.operands().at(input).getDef().size() == 0)
+      {
+        assert(_graph.getInputs().contains(input) || _graph.operands().at(input).isConstant());
+        lower_info->removeDefPermuteFactor(removed_factor);
+        lower_info->addDefPermuteFactor(new_factor);
+      }
+    }
+
+    for (const auto &output : node.getOutputs())
+    {
+      auto lower_info = _graph.getLowerInfo(output);
+      lower_info->removeDefPermuteFactor(removed_factor);
+      lower_info->addDefPermuteFactor(new_factor);
+
+      // Whether if node's output is an output of model
+      if (_graph.operands().at(output).getUses().size() == 0)
+      {
+        assert(_graph.getOutputs().contains(output));
+        lower_info->removeUsePermuteFactor(removed_factor);
+        lower_info->addUsePermuteFactor(new_factor);
+      }
+    }
+  }
+}
+
+void PermutationOperationPass::visit(const operation::FullyConnected &node)
+{
+  const auto &input_ind = node.getInputs().at(operation::FullyConnected::Input::INPUT);
+  const auto &input_obj = _graph.operands().at(input_ind);
+  const auto &input_shape = input_obj.shape();
+
+  if (input_shape.rank() == 4)
+  {
+    changeToKeepLayout(node);
+  }
+}
+
+void PermutationOperationPass::visit(const operation::Gather &node)
+{
+  const auto &input_ind = node.getInputs().at(operation::Gather::Input::INPUT);
+  const auto &input_obj = _graph.operands().at(input_ind);
+  const auto &input_shape = input_obj.shape();
+
+  const auto &output_ind = node.getOutputs().at(0);
+  const auto &output_obj = _graph.operands().at(output_ind);
+  const auto &output_shape = output_obj.shape();
+
+  if (input_shape.rank() >= 4 || output_shape.rank() >= 4)
+  {
+    changeToKeepLayout(node);
+  }
+}
+
+void PermutationOperationPass::visit(const operation::Reshape &node)
+{
+  const auto &input_ind = node.getInputs().at(operation::Reshape::Input::INPUT);
+  const auto &input_obj = _graph.operands().at(input_ind);
+  const auto &input_shape = input_obj.shape();
+
+  const auto &output_ind = node.getOutputs().at(0);
+  const auto &output_obj = _graph.operands().at(output_ind);
+  const auto &output_shape = output_obj.shape();
+
+  if (input_shape.rank() >= 4 || output_shape.rank() >= 4)
+  {
+    changeToKeepLayout(node);
+  }
+}
+
+} // namespace pass
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/pass/PermutationOperationPass.h b/runtime/neurun/core/src/ir/pass/PermutationOperationPass.h
new file mode 100644
index 000000000..896e0176a
--- /dev/null
+++ b/runtime/neurun/core/src/ir/pass/PermutationOperationPass.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_GRAPH_PASS_PERMUTATION_OPERATION_PASS_H__
+#define __NEURUN_GRAPH_PASS_PERMUTATION_OPERATION_PASS_H__
+
+#include "ir/OperationVisitor.h"
+#include "OperationPass.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace pass
+{
+
+class PermutationOperationPass : public OperationPass, public OperationVisitor
+{
+public:
+  using OperationPass::OperationPass;
+
+public:
+  std::string id() final { return "PermutationOperationPass"; }
+
+public:
+  void callback(const OperationIndex &i, Operation &n) final;
+
+public:
+  void visit(const operation::FullyConnected &) final;
+  void visit(const operation::Gather &) final;
+  void visit(const operation::Reshape &) final;
+
+private:
+  void changeToKeepLayout(const Operation &);
+};
+
+} // namespace pass
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_GRAPH_PASS_PERMUTATION_OPERATION_PASS_H__
diff --git a/runtime/neurun/core/src/ir/verifier/Verifier.cc b/runtime/neurun/core/src/ir/verifier/Verifier.cc
new file mode 100644
index 000000000..7bd8ac512
--- /dev/null
+++ b/runtime/neurun/core/src/ir/verifier/Verifier.cc
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "Verifier.h"
+
+#include "ir/Graph.h"
+#include "ir/OperationIndexMap.h"
+
+#include "util/logging.h"
+
+namespace neurun
+{
+namespace ir
+{
+namespace verifier
+{
+
+//
+// DAGChecker
+//
+
+bool DAGChecker::verify(const Graph &graph) const
+{
+  auto &operations = graph.operations();
+  bool cyclic = false;
+
+  OperationIndexMap<bool> visited;
+  operations.iterate(
+      [&](const OperationIndex &index, const Operation &) { visited[index] = false; });
+  OperationIndexMap<bool> on_stack = visited; // Copy from visited
+
+  std::function<void(const OperationIndex &index, const Operation &)> dfs_recursive =
+      [&](const OperationIndex &index, const Operation &node) -> void {
+    if (on_stack[index])
+      cyclic = true;
+    if (visited[index])
+      return;
+    visited[index] = true;
+    on_stack[index] = true;
+
+    for (auto output : node.getOutputs())
+    {
+      const auto &operand = graph.operands().at(output);
+      for (const auto &use : operand.getUses().list())
+      {
+        dfs_recursive(use, graph.operations().at(use));
+      }
+    }
+
+    on_stack[index] = false;
+  };
+
+  operations.iterate(dfs_recursive);
+
+  return !cyclic;
+}
+
+//
+// EdgeConsistencyVerifier
+//
+
+bool EdgeConsistencyChecker::verify(const Graph &graph) const
+{
+  auto &operations = graph.operations();
+  uint32_t mismatches = 0;
+  operations.iterate([&](const OperationIndex &index, const Operation &node) {
+    for (auto operand_index : node.getInputs())
+    {
+      auto &operand = graph.operands().at(operand_index);
+      mismatches += (operand.getUses().contains(index) ? 0 : 1);
+    }
+    for (auto operand_index : node.getOutputs())
+    {
+      auto &operand = graph.operands().at(operand_index);
+      mismatches += (operand.getDef().contains(index) ? 0 : 1);
+    }
+  });
+  return mismatches == 0;
+}
+
+} // namespace verifier
+} // namespace ir
+} // namespace neurun
diff --git a/runtime/neurun/core/src/ir/verifier/Verifier.h b/runtime/neurun/core/src/ir/verifier/Verifier.h
new file mode 100644
index 000000000..0993a239e
--- /dev/null
+++ b/runtime/neurun/core/src/ir/verifier/Verifier.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_GRAPH_VERIFIER_VERIFIER_H__
+#define __NEURUN_GRAPH_VERIFIER_VERIFIER_H__
+
+namespace neurun
+{
+namespace ir
+{
+class Graph;
+} // namespace ir
+} // namespace neurun
+
+namespace neurun
+{
+namespace ir
+{
+namespace verifier
+{
+
+struct IVerifier
+{
+  virtual ~IVerifier() = default;
+  virtual bool verify(const Graph &graph) const = 0;
+};
+
+} // namespace verifier
+} // namespace ir
+} // namespace neurun
+
+namespace neurun
+{
+namespace ir
+{
+namespace verifier
+{
+
+class DAGChecker : public IVerifier
+{
+public:
+  bool verify(const Graph &graph) const override;
+};
+
+class EdgeConsistencyChecker : public IVerifier
+{
+public:
+  bool verify(const Graph &graph) const override;
+};
+
+} // namespace verifier
+} // namespace ir
+} // namespace neurun
+
+#endif // __NEURUN_GRAPH_VERIFIER_VERIFIER_H__
diff --git a/runtime/neurun/core/src/library_info.cc b/runtime/neurun/core/src/library_info.cc
new file mode 100644
index 000000000..601d09185
--- /dev/null
+++ b/runtime/neurun/core/src/library_info.cc
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+volatile const char info[] = "library information : runtime=neurun";
diff --git a/runtime/neurun/core/src/util/ConfigSource.cc b/runtime/neurun/core/src/util/ConfigSource.cc
new file mode 100644
index 000000000..7d57ec178
--- /dev/null
+++ b/runtime/neurun/core/src/util/ConfigSource.cc
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "util/ConfigSource.h"
+#include "util/GeneralConfigSource.h"
+#include "util/EnvConfigSource.h"
+
+#include <array>
+#include <algorithm>
+#include <cassert>
+
+#include "cpp14/memory.h"
+
+namespace neurun
+{
+namespace util
+{
+
+static std::unique_ptr<IConfigSource> _source;
+
+void config_source(std::unique_ptr<IConfigSource> &&source) { _source = std::move(source); }
+
+static IConfigSource *config_source()
+{
+  if (!_source)
+  {
+#ifdef ENVVAR_FOR_DEFAULT_CONFIG
+    // Default ConfigSource is EnvConfigSource
+    _source = nnfw::cpp14::make_unique<EnvConfigSource>();
+#else
+    _source = nnfw::cpp14::make_unique<GeneralConfigSource>();
+#endif // ENVVAR_FOR_DEFAULT_CONFIG
+  }
+  return _source.get();
+}
+
+static std::string getConfigOrDefault(const std::string &key)
+{
+  static std::unordered_map<std::string, std::string> defaults;
+  if (defaults.empty())
+  {
+#define CONFIG(Name, Type, Default)               \
+  {                                               \
+    auto name = std::string{#Name};               \
+    defaults.emplace(name, std::string{Default}); \
+  }
+
+#include "util/Config.lst"
+
+#undef CONFIG
+  }
+
+  // Treat empty string and absence of the value to be the same
+  auto ret = config_source()->get(key);
+  if (ret.empty())
+  {
+    auto itr = defaults.find(key);
+    if (itr != defaults.end())
+    {
+      // Return the default value if exists
+      ret = itr->second;
+    }
+  }
+
+  return ret;
+}
+
+bool getConfigBool(const std::string &key)
+{
+  auto raw = getConfigOrDefault(key);
+  static const std::array<std::string, 5> false_list{"0", "OFF", "FALSE", "N", "NO"};
+  auto false_found = std::find(false_list.begin(), false_list.end(), raw);
+
+  return (false_found == false_list.end());
+}
+
+int getConfigInt(const std::string &key)
+{
+  auto raw = getConfigOrDefault(key);
+  return std::stoi(raw);
+}
+
+std::string getConfigString(const std::string &key) { return getConfigOrDefault(key); }
+
+} // namespace util
+} // namespace neurun
+
+namespace neurun
+{
+namespace util
+{
+namespace config
+{
+
+#define CONFIG(Name, Type, Default) const char *Name = #Name;
+
+#include "util/Config.lst"
+
+#undef CONFIG
+
+} // namespace config
+} // namespace util
+} // namespace neurun
diff --git a/runtime/neurun/core/src/util/EnvConfigSource.cc b/runtime/neurun/core/src/util/EnvConfigSource.cc
new file mode 100644
index 000000000..52a6bf2a4
--- /dev/null
+++ b/runtime/neurun/core/src/util/EnvConfigSource.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "util/EnvConfigSource.h"
+
+#include <cstdlib>
+
+namespace neurun
+{
+namespace util
+{
+
+std::string EnvConfigSource::get(const std::string &key) const
+{
+  const char *value = std::getenv(key.c_str());
+  if (value != nullptr)
+  {
+    return value;
+  }
+  else
+  {
+    return GeneralConfigSource::get(key);
+  }
+}
+
+} // namespace util
+} // namespace neurun
diff --git a/runtime/neurun/core/src/util/EventCollectorGlobal.cc b/runtime/neurun/core/src/util/EventCollectorGlobal.cc
new file mode 100644
index 000000000..6c3594f5f
--- /dev/null
+++ b/runtime/neurun/core/src/util/EventCollectorGlobal.cc
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "util/EventCollectorGlobal.h"
+
+#include <cassert>
+#include <fstream>
+
+#include "util/ConfigSource.h"
+
+namespace neurun
+{
+namespace util
+{
+
+EventCollectorGlobal::EventCollectorGlobal() : _recorder{}, _collector{&_recorder}
+{
+  // DO NOTHING
+}
+
+EventCollectorGlobal::~EventCollectorGlobal()
+{
+  auto path = util::getConfigString(util::config::TRACE_FILEPATH);
+  if (!path.empty())
+  {
+    // TODO Need better way for saved file path than just appending ".global" to the trace file path
+    std::ofstream ofs{path + ".global"};
+    _recorder.writeToFile(ofs);
+  }
+}
+
+EventCollectorGlobal &EventCollectorGlobal::get()
+{
+  static EventCollectorGlobal instance;
+  return instance;
+}
+
+EventDurationBlock::EventDurationBlock(const std::string &tag) : _tag{tag}
+{
+  auto &glob = EventCollectorGlobal::get();
+  glob.collector().onEvent(EventCollector::Event{EventCollector::Edge::BEGIN, "0", _tag});
+}
+EventDurationBlock::~EventDurationBlock()
+{
+  auto &glob = EventCollectorGlobal::get();
+  glob.collector().onEvent(EventCollector::Event{EventCollector::Edge::END, "0", _tag});
+}
+
+EventDurationManual::EventDurationManual(const std::string &tag) : _tag{tag}, _pair{true} {}
+
+EventDurationManual::~EventDurationManual()
+{
+  // Check if it has called begin-end pair
+  assert(_pair);
+}
+
+void EventDurationManual::begin()
+{
+  _pair = false;
+  auto &glob = EventCollectorGlobal::get();
+  glob.collector().onEvent(EventCollector::Event{EventCollector::Edge::BEGIN, "0", _tag});
+}
+
+void EventDurationManual::end()
+{
+  assert(!_pair);
+  _pair = true;
+  auto &glob = EventCollectorGlobal::get();
+  glob.collector().onEvent(EventCollector::Event{EventCollector::Edge::END, "0", _tag});
+}
+
+} // namespace util
+} // namespace neurun
diff --git a/runtime/neurun/core/src/util/GeneralConfigSource.cc b/runtime/neurun/core/src/util/GeneralConfigSource.cc
new file mode 100644
index 000000000..084e4c109
--- /dev/null
+++ b/runtime/neurun/core/src/util/GeneralConfigSource.cc
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "util/GeneralConfigSource.h"
+#include "util/logging.h"
+
+namespace neurun
+{
+namespace util
+{
+
+std::string GeneralConfigSource::get(const std::string &key) const
+{
+  auto itr = _map.find(key);
+  if (itr == _map.end())
+  {
+    return "";
+  }
+  else
+  {
+    return itr->second;
+  }
+}
+
+void GeneralConfigSource::set(const std::string &key, const std::string &val)
+{
+  VERBOSE(GeneralConfigSource) << key << " : " << val << std::endl;
+  _map[key] = val;
+}
+
+} // namespace util
+} // namespace neurun
diff --git a/runtime/neurun/core/src/util/Padding.cc b/runtime/neurun/core/src/util/Padding.cc
new file mode 100644
index 000000000..2e2202b58
--- /dev/null
+++ b/runtime/neurun/core/src/util/Padding.cc
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "util/Padding.h"
+#include "util/Utils.h"
+
+#include <algorithm>
+#include <stdexcept>
+
+namespace neurun
+{
+namespace util
+{
+
+ir::ExplicitPadding validPadding(void)
+{
+  //
+  // ANEURALNETWORKS_PADDING_VALID
+  //
+  // VALID padding. No padding.
+  //
+  // When the input size is not evenly divisible by the filter size,
+  // the input at the end that could not fill the whole filter tile
+  // will simply be ignored.
+  //
+  ir::ExplicitPadding padding;
+
+  padding.top = 0;
+  padding.bottom = 0;
+  padding.left = 0;
+  padding.right = 0;
+
+  return padding;
+}
+
+ir::ExplicitPadding samePaddingUsingIFM(const ir::FeatureShape &ifm_shape, const ir::Stride &stride,
+                                        uint32_t kw, uint32_t kh)
+{
+  ir::ExplicitPadding padding;
+
+  // ANEURALNETWORKS_PADDING_SAME (from NNAPI spec)
+  //
+  // SAME padding. Padding on both ends are the "same":
+  //
+  // padding_to_beginning = total_padding / 2
+  // padding_to_end = (total_padding + 1)/2.
+  //
+  const int32_t vertical_expected_output = (ifm_shape.H + stride.vertical - 1) / stride.vertical;
+  const int32_t horizontal_expected_output =
+      (ifm_shape.W + stride.horizontal - 1) / stride.horizontal;
+
+  const int32_t vertical_needed_input = (vertical_expected_output - 1) * stride.vertical + kh;
+  const int32_t vertical_total_padding = std::max(0, vertical_needed_input - ifm_shape.H);
+
+  const int32_t horizontal_needed_input = (horizontal_expected_output - 1) * stride.horizontal + kw;
+  const int32_t horizontal_total_padding = std::max(0, horizontal_needed_input - ifm_shape.W);
+
+  padding.top = vertical_total_padding / 2;
+  padding.bottom = (vertical_total_padding + 1) / 2;
+  padding.left = horizontal_total_padding / 2;
+  padding.right = (horizontal_total_padding + 1) / 2;
+
+  return padding;
+}
+
+ir::ExplicitPadding samePadding(const ir::FeatureShape &ifm_shape,
+                                const ir::FeatureShape &ofm_shape, const ir::Stride &stride,
+                                uint32_t kw, uint32_t kh)
+{
+  const int32_t vertical_expected_output = (ifm_shape.H + stride.vertical - 1) / stride.vertical;
+  const int32_t horizontal_expected_output =
+      (ifm_shape.W + stride.horizontal - 1) / stride.horizontal;
+  assert(vertical_expected_output == ofm_shape.H);
+  assert(horizontal_expected_output == ofm_shape.W);
+
+  UNUSED_RELEASE(ofm_shape);
+  UNUSED_RELEASE(vertical_expected_output);
+  UNUSED_RELEASE(horizontal_expected_output);
+
+  return samePaddingUsingIFM(ifm_shape, stride, kw, kh);
+}
+
+ir::ExplicitPadding calculatePadding(const ir::Padding &padding, const ir::FeatureShape &ifm_shape,
+                                     const ir::FeatureShape &ofm_shape, const ir::Stride &stride,
+                                     uint32_t kw, uint32_t kh)
+{
+  if (padding.type == ir::PaddingType::EXPLICIT)
+  {
+    return padding.param;
+  }
+  else if (padding.type == ir::PaddingType::SAME)
+  {
+    return samePadding(ifm_shape, ofm_shape, stride, kw, kh);
+  }
+  else if (padding.type == ir::PaddingType::VALID)
+  {
+    return validPadding();
+  }
+  else
+  {
+    throw std::runtime_error{"Cannot handle padding type"};
+  }
+}
+
+} // namespace util
+} // namespace neurun
diff --git a/runtime/neurun/core/src/util/ShapeInference.cc b/runtime/neurun/core/src/util/ShapeInference.cc
new file mode 100644
index 000000000..6fa29e7d8
--- /dev/null
+++ b/runtime/neurun/core/src/util/ShapeInference.cc
@@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "util/Utils.h"
+#include "ir/InternalType.h"
+#include "ir/Shape.h"
+#include "ir/operation/AvgPool2D.h"
+#include "ir/operation/MaxPool2D.h"
+#include "util/ShapeInference.h"
+
+namespace neurun
+{
+namespace shape_inference
+{
+
+//
+// Helper functions
+//
+
+namespace
+{
+
+template <typename T, typename U>
+typename std::enable_if<std::is_integral<T>::value && std::is_integral<U>::value,
+                        typename std::common_type<T, U>::type>::type
+ceil_div(T dividend, U divisor)
+{
+  assert(dividend > 0 && divisor > 0 && "this implementations is for positive numbers only");
+  return (dividend + divisor - 1) / divisor;
+}
+
+// Calculate the result of broadcast of two shapes
+ir::Shape broadcastShapes(const ir::Shape &lhs_shape, const ir::Shape &rhs_shape)
+{
+  ir::Shape out_shape;
+  auto max_rank = std::max(lhs_shape.rank(), rhs_shape.rank());
+
+  for (int idx = 0; idx < max_rank; ++idx)
+  {
+    // Go over operands dimensions from right to left
+    int lhs_idx = lhs_shape.rank() - idx - 1;
+    int rhs_idx = rhs_shape.rank() - idx - 1;
+
+    int32_t lhs_dim = lhs_idx >= 0 ? lhs_shape.dim(lhs_idx) : 1;
+    int32_t rhs_dim = rhs_idx >= 0 ? rhs_shape.dim(rhs_idx) : 1;
+
+    if (lhs_dim != 1 && rhs_dim != 1 && lhs_dim != rhs_dim)
+      throw std::runtime_error("Incompatible shapes for broadcast");
+
+    out_shape.prepend(std::max(lhs_dim, rhs_dim));
+  }
+
+  return out_shape;
+}
+
+// Calculate output height and width of convolution-like operation
+std::pair<int, int> calcConvLikeHeightAndWidth(const int in_h, const int in_w, const int ker_h,
+                                               const int ker_w, const ir::Padding pad,
+                                               const ir::Stride stride)
+{
+  int32_t out_h = 0, out_w = 0;
+
+  switch (pad.type)
+  {
+    case ir::PaddingType::SAME:
+      out_h = ceil_div(in_h, stride.vertical);
+      out_w = ceil_div(in_w, stride.horizontal);
+      break;
+    case ir::PaddingType::VALID:
+      out_h = ceil_div(in_h - ker_h + 1, stride.vertical);
+      out_w = ceil_div(in_w - ker_w + 1, stride.horizontal);
+      break;
+    case ir::PaddingType::EXPLICIT:
+      out_h = (in_h + pad.param.top + pad.param.bottom - ker_h) / stride.vertical + 1;
+      out_w = (in_w + pad.param.left + pad.param.right - ker_w) / stride.horizontal + 1;
+      break;
+    default:
+      assert(false);
+  }
+
+  return {out_h, out_w};
+}
+
+} // namespace
+
+//
+// Shape inference
+//
+
+Shapes inferEltwiseShape(const ir::Shape &lhs_shape, const ir::Shape &rhs_shape)
+{
+  return {broadcastShapes(lhs_shape, rhs_shape)};
+}
+
+Shapes inferAvgPoolShape(const ir::Shape &in_shape, const ir::operation::AvgPool2D::Param &param,
+                         const ir::Layout layout)
+{
+  assert(layout == ir::Layout::NHWC);
+  auto ifm_shape = in_shape.asFeature(layout);
+  const auto out_h_w = calcConvLikeHeightAndWidth(ifm_shape.H, ifm_shape.W, param.kh, param.kw,
+                                                  param.padding, param.stride);
+  // Pooling don't change number of channels and batch size
+  return {ir::Shape{ifm_shape.N, out_h_w.first, out_h_w.second, ifm_shape.C}};
+}
+
+Shapes inferConcatShape(const Shapes &in_shapes, const ir::operation::Concat::Param &param)
+{
+  const int32_t concat_axis = param.axis;
+  const auto &first_in_shape = in_shapes[0];
+
+  // Check that all shapes are equal except for concat axis dimension
+  for (const auto &in_shape : in_shapes)
+  {
+    assert(in_shape.rank() == first_in_shape.rank());
+    for (int64_t dim_idx = 0; dim_idx < in_shape.rank(); ++dim_idx)
+      assert(dim_idx == concat_axis || in_shape.dim(dim_idx) == first_in_shape.dim(dim_idx));
+  }
+
+  // Calculate output shape
+  ir::Shape out_shape(first_in_shape);
+  out_shape.dim(concat_axis) = 0;
+  for (const auto &in_shape : in_shapes)
+    out_shape.dim(concat_axis) += in_shape.dim(concat_axis);
+  return {out_shape};
+}
+
+Shapes inferMaxPoolShape(const ir::Shape &in_shape, const ir::operation::MaxPool2D::Param &param,
+                         const ir::Layout layout)
+{
+  assert(layout == ir::Layout::NHWC);
+  auto ifm_shape = in_shape.asFeature(layout);
+  const auto out_h_w = calcConvLikeHeightAndWidth(ifm_shape.H, ifm_shape.W, param.kh, param.kw,
+                                                  param.padding, param.stride);
+  // Pooling don't change number of channels and batch size
+  return {ir::Shape{ifm_shape.N, out_h_w.first, out_h_w.second, ifm_shape.C}};
+}
+
+Shapes inferConv2DShape(const ir::Shape &in_shape, const ir::Shape &ker_shape,
+                        const ir::operation::Conv2D::Param &param, ir::Layout layout)
+{
+  assert(layout == ir::Layout::NHWC);
+  auto ifm_shape = in_shape.asFeature(layout);
+
+  // Kernel format is [depth_out, kernel_height, kernel_width, depth_in]
+  auto kf_shape = ker_shape.asFeature(layout);
+  assert(ifm_shape.C == kf_shape.C);
+
+  const auto out_h_w = calcConvLikeHeightAndWidth(ifm_shape.H, ifm_shape.W, kf_shape.H, kf_shape.W,
+                                                  param.padding, param.stride);
+
+  return {ir::Shape{ifm_shape.N, out_h_w.first, out_h_w.second, kf_shape.N}};
+}
+
+Shapes inferDepthwiseConv2DShape(const ir::Shape &in_shape, const ir::Shape &ker_shape,
+                                 const ir::operation::DepthwiseConv2D::Param &param,
+                                 ir::Layout layout)
+{
+  assert(layout == ir::Layout::NHWC);
+  auto ifm_shape = in_shape.asFeature(layout);
+
+  // Kernel format is [1, kernel_height, kernel_width, depth_out]
+  auto kf_shape = ker_shape.asFeature(layout);
+  assert(kf_shape.C == static_cast<int32_t>(ifm_shape.C * param.multiplier));
+  assert(kf_shape.N == 1);
+
+  const auto out_h_w = calcConvLikeHeightAndWidth(ifm_shape.H, ifm_shape.W, kf_shape.H, kf_shape.W,
+                                                  param.padding, param.stride);
+
+  return {ir::Shape{ifm_shape.N, out_h_w.first, out_h_w.second, kf_shape.C}};
+}
+
+Shapes inferFullyConnectedShape(const ir::Shape &in_shape, const ir::Shape &ker_shape)
+{
+  assert(in_shape.rank() >= 2);
+  assert(ker_shape.rank() == 2);
+
+  const auto input_size_with_batch = in_shape.num_elements();
+  const auto num_units = ker_shape.dim(0);
+  const auto input_size = ker_shape.dim(1);
+  const auto batch_size = input_size_with_batch / input_size;
+  assert(input_size_with_batch % input_size == 0);
+
+  return {{ir::Shape({static_cast<int32_t>(batch_size), num_units})}};
+}
+
+} // namespace shape_inference
+} // namespace neurun
diff --git a/runtime/neurun/core/src/util/Utils.cc b/runtime/neurun/core/src/util/Utils.cc
new file mode 100644
index 000000000..1e24e28d4
--- /dev/null
+++ b/runtime/neurun/core/src/util/Utils.cc
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "util/Utils.h"
+
+#include <cassert>
+
+namespace neurun
+{
+namespace util
+{
+
+const char *to_string(const ir::PaddingType type)
+{
+  assert((type == ir::PaddingType::EXPLICIT) || (type == ir::PaddingType::SAME) ||
+         (type == ir::PaddingType::VALID));
+
+  switch (type)
+  {
+    case ir::PaddingType::EXPLICIT:
+      return "Padding::EXPLICIT";
+    case ir::PaddingType::SAME:
+      return "Padding::SAME";
+    case ir::PaddingType::VALID:
+      return "Padding::VALID";
+  }
+
+  return nullptr;
+}
+
+Coordinates convertCoordinates(const Coordinates &from_coordinates, ir::Layout from_layout,
+                               ir::Layout to_layout)
+{
+  assert(from_coordinates.size() == 4);
+  Coordinates to{from_coordinates};
+  if (from_layout == ir::Layout::NHWC && to_layout == ir::Layout::NCHW)
+  {
+    to.set(0, from_coordinates[0]);
+    to.set(1, from_coordinates[3]);
+    to.set(2, from_coordinates[1]);
+    to.set(3, from_coordinates[2]);
+  }
+  else if (from_layout == ir::Layout::NCHW && to_layout == ir::Layout::NHWC)
+  {
+    to.set(0, from_coordinates[0]);
+    to.set(1, from_coordinates[2]);
+    to.set(2, from_coordinates[3]);
+    to.set(3, from_coordinates[1]);
+  }
+
+  return to;
+}
+
+} // namespace util
+} // namespace neurun
diff --git a/runtime/neurun/core/src/util/logging.cc b/runtime/neurun/core/src/util/logging.cc
new file mode 100644
index 000000000..c23e2b53c
--- /dev/null
+++ b/runtime/neurun/core/src/util/logging.cc
@@ -0,0 +1,7 @@
+#include "util/logging.h"
+
+neurun::util::logging::Context &neurun::util::logging::Context::get() noexcept
+{
+  static Context ctx;
+  return ctx;
+}
diff --git a/runtime/neurun/frontend/CMakeLists.txt b/runtime/neurun/frontend/CMakeLists.txt
new file mode 100644
index 000000000..5ea6cdadd
--- /dev/null
+++ b/runtime/neurun/frontend/CMakeLists.txt
@@ -0,0 +1 @@
+add_subdirectories()
diff --git a/runtime/neurun/frontend/base_loader/CMakeLists.txt b/runtime/neurun/frontend/base_loader/CMakeLists.txt
new file mode 100644
index 000000000..358fc2646
--- /dev/null
+++ b/runtime/neurun/frontend/base_loader/CMakeLists.txt
@@ -0,0 +1,7 @@
+if(NOT BUILD_TFLITE_LOADER AND NOT BUILD_CIRCLE_LOADER)
+  return()
+endif(NOT BUILD_TFLITE_LOADER AND NOT BUILD_CIRCLE_LOADER)
+
+add_library(base_loader INTERFACE)
+target_include_directories(base_loader INTERFACE ${CMAKE_CURRENT_SOURCE_DIR}/include)
+target_link_libraries(base_loader INTERFACE neurun_core nnfw_lib_cpp14)
diff --git a/runtime/neurun/frontend/base_loader/include/base_loader.h b/runtime/neurun/frontend/base_loader/include/base_loader.h
new file mode 100644
index 000000000..ae1562f6c
--- /dev/null
+++ b/runtime/neurun/frontend/base_loader/include/base_loader.h
@@ -0,0 +1,1278 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __BASE_LOADER_BASE_LOADER_H__
+#define __BASE_LOADER_BASE_LOADER_H__
+
+#include "ir/Graph.h"
+#include "ir/Operations.Include.h"
+
+#include <map>
+#include <cpp14/memory.h>
+#include <fstream>
+#include <limits>
+
+namespace neurun
+{
+namespace base_loader
+{
+
+template <typename LoaderDomain, typename SpecificLoader> class BaseLoader
+{
+  using Verifier = typename LoaderDomain::Verifier;
+  using ActivationFunctionType = typename LoaderDomain::ActivationFunctionType;
+  using Buffer = typename LoaderDomain::Buffer;
+  using BuiltinOperator = typename LoaderDomain::BuiltinOperator;
+  using CustomOptionsFormat = typename LoaderDomain::CustomOptionsFormat;
+  using Model = typename LoaderDomain::Model;
+  using Operator = typename LoaderDomain::Operator;
+  using Padding = typename LoaderDomain::Padding;
+  using Pool2DOptions = typename LoaderDomain::Pool2DOptions;
+  using SubGraph = typename LoaderDomain::SubGraph;
+  using Tensor = typename LoaderDomain::Tensor;
+  using TensorType = typename LoaderDomain::TensorType;
+
+public:
+  /**
+   * @brief Construct a new Loader object
+   *
+   * @param graph reference on graph
+   */
+  explicit BaseLoader(ir::Graph &graph) : _graph(graph), _model{nullptr} {}
+
+  /**
+   * @brief Load a model from file
+   *
+   * @param file_path
+   */
+  void loadFromFile(const char *file_path);
+
+protected:
+  ~BaseLoader() = default;
+
+  void loadModel();
+
+  // Helper functions
+  ir::Activation convertActivation(ActivationFunctionType type);
+  ir::DataType tensorTypeToDataType(TensorType type);
+
+  // Create operands form tflite::Tensor
+  ir::OperandIndex loadOperand(const Tensor *tensor);
+  void loadOperationIO(const Operator *op, ir::OperandIndexSequence &inputs,
+                       ir::OperandIndexSequence &outputs);
+  // Create operations from Operator
+  void loadOperation(const Operator *op);
+  // Load Strides and Paddings from options to param
+  template <typename Param, typename OptionsType>
+  void loadStridesAndPaddings(Param &param, const OptionsType *options);
+  // Load Pool2D param
+  template <typename Param> void loadPool2D(Param &param, const Pool2DOptions *options);
+
+  // Operations
+  void loadConv2D(const Operator *op);
+  void loadDepthwiseConv2D(const Operator *op);
+  void loadTransposeConv(const Operator *op);
+  void loadAvgPool2D(const Operator *op);
+  void loadReshape(const Operator *op);
+  void loadSoftmax(const Operator *op);
+  void loadMaxPool2D(const Operator *op);
+  void loadConcatenation(const Operator *op);
+  void loadInstanceNorm(const Operator *op);
+  void loadFC(const Operator *op);
+  void loadAdd(const Operator *op);
+  void loadSub(const Operator *op);
+  void loadMul(const Operator *op);
+  void loadDiv(const Operator *op);
+  void loadPack(const Operator *op);
+  void loadRelu(const Operator *op);
+  void loadRelu6(const Operator *op);
+  void loadResizeBilinear(const Operator *op);
+  void loadRsqrt(const Operator *op);
+  void loadSqrt(const Operator *op);
+  void loadSquaredDifference(const Operator *op);
+  void loadTanh(const Operator *op);
+  void loadTranspose(const Operator *op);
+  void loadMean(const Operator *op);
+  void loadReduceMax(const Operator *op);
+  void loadPad(const Operator *op);
+  void loadLogistic(const Operator *op);
+  void loadExp(const Operator *op);
+  void loadGather(const Operator *op);
+  void loadCustom(const Operator *op);
+  void loadSpaceToBatchND(const Operator *op);
+  void loadBatchToSpaceND(const Operator *op);
+  void loadReduceSum(const Operator *op);
+  void loadSqueeze(const Operator *op);
+  void loadPrelu(const Operator *op);
+  void loadSplit(const Operator *op);
+  void loadSlice(const Operator *op);
+  void loadStridedSlice(const Operator *op);
+  void loadUnpack(const Operator *op);
+  void loadMinimum(const Operator *op);
+  void loadMaximum(const Operator *op);
+  void loadCast(const Operator *op);
+  void loadComparison(const Operator *op);
+  void loadOneHot(const Operator *op);
+
+protected:
+  // Buffer for loading (if needed)
+  std::vector<char> _buffer;
+  // Reference on loadable Graph
+  ir::Graph &_graph;
+  const Model *_model;
+  // Maps Tensor indices to neurun Operands.
+  std::vector<ir::OperandIndex> _tensor_to_operand;
+  // Verifier
+  std::unique_ptr<Verifier> _verifier;
+};
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::BaseLoader::loadFromFile(const char *file_path)
+{
+  std::ifstream stream(file_path, std::fstream::in | std::fstream::binary);
+
+  if (!stream)
+  {
+    std::string msg = "Failed to open file `";
+    msg += file_path;
+    msg += "`";
+    throw std::runtime_error{msg};
+  }
+
+  stream.seekg(0, stream.end);
+  auto size = stream.tellg();
+  stream.seekg(0, stream.beg);
+
+  _buffer.resize(size);
+  stream.read(_buffer.data(), size);
+
+  stream.close();
+
+  // Prepare verifier
+  _verifier = nnfw::cpp14::make_unique<Verifier>(
+      reinterpret_cast<const std::uint8_t *>(_buffer.data()), _buffer.size());
+
+  loadModel();
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+ir::Activation BaseLoader<LoaderDomain, SpecificLoader>::BaseLoader::convertActivation(
+    const ActivationFunctionType type)
+{
+  switch (type)
+  {
+    case ActivationFunctionType::ActivationFunctionType_NONE:
+      return ir::Activation::NONE;
+    case ActivationFunctionType::ActivationFunctionType_RELU:
+      return ir::Activation::RELU;
+    case ActivationFunctionType::ActivationFunctionType_RELU_N1_TO_1:
+      return ir::Activation::RELU1;
+    case ActivationFunctionType::ActivationFunctionType_RELU6:
+      return ir::Activation::RELU6;
+    case ActivationFunctionType::ActivationFunctionType_TANH:
+      return ir::Activation::TANH;
+    default:
+      throw std::runtime_error(std::string("Unsupported activation type: ")
+                                   .append(EnumNameActivationFunctionType(type)));
+  }
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+ir::DataType
+BaseLoader<LoaderDomain, SpecificLoader>::BaseLoader::tensorTypeToDataType(const TensorType type)
+{
+  switch (type)
+  {
+    case TensorType::TensorType_FLOAT32:
+      return ir::DataType::FLOAT32;
+    case TensorType::TensorType_INT32:
+      return ir::DataType::INT32;
+    case TensorType::TensorType_BOOL:
+      return ir::DataType::BOOL8;
+    case TensorType::TensorType_UINT8:
+      return ir::DataType::UINT8;
+    default:
+      throw std::runtime_error(
+          std::string("Unsupported tensor type: ").append(EnumNameTensorType(type)));
+  }
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+ir::OperandIndex BaseLoader<LoaderDomain, SpecificLoader>::loadOperand(const Tensor *tensor)
+{
+  ir::Shape shape;
+  // Shape
+  const auto *tensor_shape = tensor->shape();
+  for (const auto &dim : *tensor_shape)
+  {
+    shape.append(dim);
+  }
+  // Type
+  ir::DataType data_type = tensorTypeToDataType(tensor->type());
+  // Quantization
+  auto q_params = tensor->quantization();
+  float scale = 0.0;
+  long zero_point = 0;
+  if (q_params != nullptr)
+  {
+    if (q_params->scale())
+    {
+      if (q_params->scale()->size() != 1)
+      {
+        throw std::runtime_error("Only 1 scale for a tensor is supported.");
+      }
+      scale = q_params->scale()->Get(0);
+    }
+
+    if (q_params->zero_point())
+    {
+      if (q_params->zero_point()->size() != 1)
+      {
+        throw std::runtime_error("Only 1 zero_point value for a tensor is supported.");
+      }
+      zero_point = q_params->zero_point()->Get(0);
+      // zero_point is long while TypeInfo.zero_point is defined as int32_t.
+      assert(zero_point >= std::numeric_limits<int32_t>::min());
+      assert(zero_point <= std::numeric_limits<int32_t>::max());
+    }
+    auto details = q_params->details_as_CustomQuantization();
+    if (details != nullptr)
+      throw std::runtime_error("Custom Quantization is not supported");
+
+    if (q_params->scale() && q_params->zero_point())
+    {
+      data_type = ir::DataType::QUANT8_ASYMM;
+    }
+  }
+  // Create TypeInfo
+  ir::TypeInfo type_info(data_type, scale, zero_point);
+  // Create operand
+  const auto operand_index = _graph.addOperand(shape, type_info);
+
+  // Constant tensors are indicated by non-empty data.
+  const auto *data = _model->buffers()->Get(tensor->buffer())->data();
+  if (data != nullptr)
+  {
+    auto ptr = nnfw::cpp14::make_unique<ir::CachedData>(data->data(), data->size());
+    _graph.setOperandValue(operand_index, std::move(ptr));
+  }
+
+  // Name unused
+  // auto name = tensor->name();
+  // Variablie
+  if (tensor->is_variable())
+    throw std::runtime_error("Variable tensor not supported!");
+
+  return operand_index;
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadOperationIO(const Operator *op,
+                                                               ir::OperandIndexSequence &inputs,
+                                                               ir::OperandIndexSequence &outputs)
+{
+  for (const std::int32_t idx : *op->inputs())
+  {
+    inputs.append(_tensor_to_operand[idx]);
+  }
+
+  for (const std::int32_t idx : *op->outputs())
+  {
+    outputs.append(_tensor_to_operand[idx]);
+  }
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+template <typename Param, typename OptionsType>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadStridesAndPaddings(Param &param,
+                                                                      const OptionsType *options)
+{
+  // Strides
+  param.stride.vertical = options->stride_w();
+  param.stride.horizontal = options->stride_h();
+  // Paddings
+  if (options->padding() == Padding::Padding_SAME)
+    param.padding.type = ir::PaddingType::SAME;
+  if (options->padding() == Padding::Padding_VALID)
+    param.padding.type = ir::PaddingType::VALID;
+  // param paddings indexes unused
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+template <typename Param>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadPool2D(Param &param,
+                                                          const Pool2DOptions *options)
+{
+  // Strides and Paddings
+  loadStridesAndPaddings(param, options);
+  // Filter width and height
+  // Strides
+  param.kw = options->filter_width();
+  param.kh = options->filter_height();
+  // Activation
+  param.activation = convertActivation(options->fused_activation_function());
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadConv2D(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  ir::operation::Conv2D::Param param;
+  const auto *options = op->builtin_options_as_Conv2DOptions();
+  param.activation = convertActivation(options->fused_activation_function());
+  loadStridesAndPaddings(param, options);
+  // Dilation h/w factor unused
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::Conv2D(inputs, outputs, param));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadDepthwiseConv2D(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  ir::operation::DepthwiseConv2D::Param param;
+  const auto *options = op->builtin_options_as_DepthwiseConv2DOptions();
+  param.activation = convertActivation(options->fused_activation_function());
+  loadStridesAndPaddings(param, options);
+  // Multiplier
+  param.multiplier = options->depth_multiplier();
+  // Dilation h/w factor unused
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::DepthwiseConv2D(inputs, outputs, param));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadTransposeConv(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  ir::operation::TransposeConv::Param param;
+  const auto *options = op->builtin_options_as_TransposeConvOptions();
+  loadStridesAndPaddings(param, options);
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::TransposeConv(inputs, outputs, param));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadAvgPool2D(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  ir::operation::AvgPool2D::Param param;
+  const auto *options = op->builtin_options_as_Pool2DOptions();
+
+  loadPool2D(param, options);
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::AvgPool2D(inputs, outputs, param));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadReshape(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  // const auto *options = op->builtin_options_as_ReshapeOptions();
+  // No params
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::Reshape(inputs, outputs));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadSoftmax(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  ir::operation::Softmax::Param param;
+  const auto *options = op->builtin_options_as_SoftmaxOptions();
+  // Beta
+  param.beta = options->beta();
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::Softmax(inputs, outputs, param));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadMaxPool2D(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  ir::operation::MaxPool2D::Param param;
+  const auto *options = op->builtin_options_as_Pool2DOptions();
+
+  loadPool2D(param, options);
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::MaxPool2D(inputs, outputs, param));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadConcatenation(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  ir::operation::Concat::Param param;
+  const auto *options = op->builtin_options_as_ConcatenationOptions();
+  // Axis
+  param.axis = options->axis();
+  param.rank = _graph.operands().at(outputs.at(0)).shape().rank();
+  // activation unused
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::Concat(inputs, outputs, param));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadInstanceNorm(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  ir::operation::InstanceNorm::Param param;
+  const auto *options = op->builtin_options_as_InstanceNormOptions();
+
+  param.activation = convertActivation(options->fused_activation_function());
+  // Use default value 1e-5 if value of epsilon is zero
+  param.epsilon = options->epsilon() == 0.f ? 1e-5 : options->epsilon();
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::InstanceNorm(inputs, outputs, param));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadFC(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  const auto &input_operand = _graph.operands().at(inputs.at(ir::operation::FullyConnected::INPUT));
+  auto &weights_operand = _graph.operands().at(inputs.at(ir::operation::FullyConnected::WEIGHT));
+  if (input_operand.typeInfo().type() == ir::DataType::FLOAT32 &&
+      weights_operand.typeInfo().type() == ir::DataType::QUANT8_ASYMM)
+  {
+    weights_operand.type(ir::DataType::QUANT8_SYMM);
+  }
+
+  ir::operation::FullyConnected::Param param;
+  const auto *options = op->builtin_options_as_FullyConnectedOptions();
+
+  param.activation = convertActivation(options->fused_activation_function());
+  // weights_format unused
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::FullyConnected(inputs, outputs, param));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadAdd(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  ir::operation::Add::Param param;
+  const auto *options = op->builtin_options_as_AddOptions();
+
+  param.activation = convertActivation(options->fused_activation_function());
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::Add(inputs, outputs, param));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadSub(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  ir::operation::Sub::Param param;
+  const auto *options = op->builtin_options_as_SubOptions();
+
+  param.activation = convertActivation(options->fused_activation_function());
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::Sub(inputs, outputs, param));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadMul(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  ir::operation::Mul::Param param;
+  const auto *options = op->builtin_options_as_MulOptions();
+
+  param.activation = convertActivation(options->fused_activation_function());
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::Mul(inputs, outputs, param));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadDiv(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  ir::operation::Div::Param param;
+  const auto *options = op->builtin_options_as_DivOptions();
+
+  param.activation = convertActivation(options->fused_activation_function());
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::Div(inputs, outputs, param));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadPack(const Operator *op)
+{
+  // This runtime_error will be removed if the one of backend supports this operation
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  ir::operation::Pack::Param param;
+  const auto *options = op->builtin_options_as_PackOptions();
+  param.num = options->values_count();
+  param.axis = options->axis();
+  param.rank = _graph.operands().at(outputs.at(0)).shape().rank();
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::Pack(inputs, outputs, param));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadRelu(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::ReLU(inputs, outputs));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadRelu6(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::ReLU6(inputs, outputs));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadResizeBilinear(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+  auto input = inputs.at(0);
+  auto size = inputs.at(1);
+
+  // FIXME Handle ResizeBilinearOptions.
+  if (!_graph.operands().at(size).isConstant())
+    throw std::runtime_error("ResizeBilinear: non-constant 'size' is not supported.");
+
+  std::vector<std::int32_t> size_v = _graph.operands().at(size).template asVector<std::int32_t>();
+
+  ir::operation::ResizeBilinear::Param param;
+  param.height_out = size_v[0];
+  param.width_out = size_v[1];
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::ResizeBilinear({input}, outputs, param));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadRsqrt(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::RSQRT(inputs, outputs));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadSqrt(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::SQRT(inputs, outputs));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadSquaredDifference(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::SquaredDifference(inputs, outputs));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadTanh(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::Tanh(inputs, outputs));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadTranspose(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+  auto input = inputs.at(0);
+  auto perm = inputs.at(1);
+
+  if (!_graph.operands().at(perm).isConstant())
+    throw std::runtime_error("Transpose: non-constant 'perm' is not supported.");
+
+  ir::operation::Transpose::Param param;
+  param.perm = _graph.operands().at(perm).template asVector<int>();
+  param.rank = _graph.operands().at(inputs.at(0)).shape().rank();
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::Transpose({input}, outputs, param));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadMean(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+  auto input = inputs.at(0);
+  auto axes = inputs.at(1);
+
+  if (!_graph.operands().at(axes).isConstant())
+    throw std::runtime_error("Mean: non-constant 'axes' is not supported.");
+
+  ir::operation::Mean::Param param;
+  param.axes = _graph.operands().at(axes).template asVector<int>();
+  param.keep_dims = op->builtin_options_as_ReducerOptions()->keep_dims();
+  param.rank = _graph.operands().at(inputs.at(0)).shape().rank();
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::Mean({input}, outputs, param));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadReduceMax(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+  auto input = inputs.at(0);
+  auto axes = inputs.at(1);
+
+  // FIXME Handle ReducerOptions.
+  if (!_graph.operands().at(axes).isConstant())
+    throw std::runtime_error("ReduceSum: non-constant 'axes' is not supported.");
+
+  ir::operation::ReduceMax::Param param;
+  param.axes = _graph.operands().at(axes).template asVector<int>();
+  param.keep_dims = op->builtin_options_as_ReducerOptions()->keep_dims();
+  param.rank = _graph.operands().at(inputs.at(0)).shape().rank();
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::ReduceMax({input}, outputs, param));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadPad(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  ir::operation::Pad::Param param;
+  param.rank = _graph.operands().at(inputs.at(0)).shape().rank();
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::Pad(inputs, outputs, param));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadLogistic(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::Logistic(inputs, outputs));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadExp(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::Exp(inputs, outputs));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadGather(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+  ir::operation::Gather::Param param;
+  param.axis = op->builtin_options_as_GatherOptions()->axis();
+  param.rank = _graph.operands().at(inputs.at(0)).shape().rank();
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::Gather(inputs, outputs, param));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadSpaceToBatchND(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  std::unique_ptr<ir::Operation> new_op{new ir::operation::SpaceToBatchND{inputs, outputs}};
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadBatchToSpaceND(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+  auto input = inputs.at(0);
+  auto block_shape = inputs.at(1);
+  auto crops = inputs.at(2);
+
+  if (!_graph.operands().at(crops).isConstant())
+    throw std::runtime_error("BatchToSpaceND: non-constant 'crops' is not supported.");
+
+  std::vector<std::int32_t> crops_v = _graph.operands().at(crops).template asVector<std::int32_t>();
+  assert(crops_v.size() == 4);
+  if (crops_v != std::vector<std::int32_t>{0, 0, 0, 0})
+    throw std::runtime_error("BatchToSpaceND: 'crops' other than {0, 0, 0, 0} is not supported.");
+
+  std::unique_ptr<ir::Operation> new_op{
+      new ir::operation::BatchToSpaceND{{input, block_shape}, outputs}};
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadReduceSum(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+  auto input = inputs.at(0);
+  auto axes = inputs.at(1);
+
+  // FIXME Handle ReducerOptions.
+  if (!_graph.operands().at(axes).isConstant())
+    throw std::runtime_error("ReduceSum: non-constant 'axes' is not supported.");
+
+  ir::operation::ReduceSum::Param param;
+  param.axes = _graph.operands().at(axes).template asVector<int>();
+  param.keep_dims = op->builtin_options_as_ReducerOptions()->keep_dims();
+  param.rank = _graph.operands().at(inputs.at(0)).shape().rank();
+
+  std::unique_ptr<ir::Operation> new_op{new ir::operation::ReduceSum{{input}, outputs, param}};
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadCustom(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  auto *op_code = _model->operator_codes()->Get(op->opcode_index());
+  auto custom_op_id = op_code->custom_code()->str();
+
+  auto constraint = ir::OperandConstraint::createExact(inputs.size());
+
+  assert(op->custom_options_format() == CustomOptionsFormat::CustomOptionsFormat_FLEXBUFFERS &&
+         "Unsupported custom operation options format");
+
+  size_t custom_op_data_size = op->custom_options()->size();
+  auto custom_op_data = new char[custom_op_data_size];
+  std::copy(op->custom_options()->begin(), op->custom_options()->end(), custom_op_data);
+
+  ir::operation::Custom::Userdata userdata{};
+  userdata.data = custom_op_data;
+  userdata.size = custom_op_data_size;
+
+  auto new_op = nnfw::cpp14::make_unique<ir::operation::Custom>(constraint, inputs, outputs,
+                                                                custom_op_id, userdata);
+
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadSqueeze(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  ir::operation::Squeeze::Param param{};
+  const auto *options = op->builtin_options_as_SqueezeOptions();
+  const auto *dims = options->squeeze_dims();
+  if (dims)
+  {
+    if (dims->Length() > sizeof(param.dims) / sizeof(param.dims[0]))
+      throw std::runtime_error("Squeeze: 'param.ndims' is out of range.");
+    param.ndim = dims->Length();
+    for (int i = 0; i < param.ndim; ++i)
+      param.dims[i] = dims->Get(i);
+  }
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::Squeeze(inputs, outputs, param));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadPrelu(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::PReLU(inputs, outputs));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadSplit(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+  // Notice : input order is strange for tflite split
+  auto input = inputs.at(1);
+  auto axis = inputs.at(0);
+
+  // FIXME Handle SplitOptions.
+  if (!_graph.operands().at(axis).isConstant())
+    throw std::runtime_error("Split: non-constant 'axis' is not supported.");
+
+  ir::operation::Split::Param param{};
+  param.axis = _graph.operands().at(axis).template asScalar<int>();
+  const auto *options = op->builtin_options_as_SplitOptions();
+  param.num_splits = options->num_splits();
+  param.rank = _graph.operands().at(inputs.at(0)).shape().rank();
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::Split({input}, outputs, param));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadSlice(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  ir::operation::Slice::Param param;
+  param.rank = _graph.operands().at(inputs.at(0)).shape().rank();
+
+  std::unique_ptr<ir::Operation> new_op{new ir::operation::Slice{inputs, outputs, param}};
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadStridedSlice(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  ir::operation::StridedSlice::Param param;
+
+  const auto *options = op->builtin_options_as_StridedSliceOptions();
+  param.begin_mask = options->begin_mask();
+  param.end_mask = options->end_mask();
+  param.shrink_axis_mask = options->shrink_axis_mask();
+  param.rank = _graph.operands().at(inputs.at(0)).shape().rank();
+
+  std::unique_ptr<ir::Operation> new_op{new ir::operation::StridedSlice{inputs, outputs, param}};
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadUnpack(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  ir::operation::Unpack::Param param;
+  const auto *options = op->builtin_options_as_UnpackOptions();
+  param.num = options->num();
+  param.axis = options->axis();
+  param.rank = _graph.operands().at(inputs.at(0)).shape().rank();
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::Unpack(inputs, outputs, param));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadMinimum(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::Min(inputs, outputs));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadMaximum(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::Max(inputs, outputs));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadCast(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::Cast(inputs, outputs));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadComparison(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  ir::operation::Comparison::Param param;
+
+  const auto builtin_op = _model->operator_codes()->Get(op->opcode_index())->builtin_code();
+
+  switch (builtin_op)
+  {
+    case BuiltinOperator::BuiltinOperator_EQUAL:
+      param.comparison_type = ir::operation::Comparison::ComparisonType::Equal;
+      break;
+    case BuiltinOperator::BuiltinOperator_GREATER_EQUAL:
+      param.comparison_type = ir::operation::Comparison::ComparisonType::GreaterEqual;
+      break;
+    case BuiltinOperator::BuiltinOperator_GREATER:
+      param.comparison_type = ir::operation::Comparison::ComparisonType::Greater;
+      break;
+    case BuiltinOperator::BuiltinOperator_LESS_EQUAL:
+      param.comparison_type = ir::operation::Comparison::ComparisonType::LessEqual;
+      break;
+    case BuiltinOperator::BuiltinOperator_LESS:
+      param.comparison_type = ir::operation::Comparison::ComparisonType::Less;
+      break;
+    default:
+      throw std::runtime_error(
+          std::string("Unsupported operation: ").append(EnumNameBuiltinOperator(builtin_op)));
+  }
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::Comparison(inputs, outputs, param));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadOneHot(const Operator *op)
+{
+  ir::OperandIndexSequence inputs;
+  ir::OperandIndexSequence outputs;
+
+  loadOperationIO(op, inputs, outputs);
+
+  ir::operation::OneHot::Param param{};
+  const auto *options = op->builtin_options_as_OneHotOptions();
+  const auto axis = options->axis();
+  const auto &indices = _graph.operands().at(inputs.at(ir::operation::OneHot::INDICES));
+  auto indices_dims = indices.shape().rank();
+  param.axis = (axis == -1) ? indices_dims : axis;
+
+  std::unique_ptr<ir::Operation> new_op(new ir::operation::OneHot(inputs, outputs, param));
+  _graph.addOperation(std::move(new_op));
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadOperation(const Operator *op)
+{
+  const auto builtin_op = _model->operator_codes()->Get(op->opcode_index())->builtin_code();
+
+  switch (builtin_op)
+  {
+    case BuiltinOperator::BuiltinOperator_CONV_2D:
+      loadConv2D(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_AVERAGE_POOL_2D:
+      loadAvgPool2D(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_DEPTHWISE_CONV_2D:
+      loadDepthwiseConv2D(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_TRANSPOSE_CONV:
+      loadTransposeConv(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_RESHAPE:
+      loadReshape(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_SOFTMAX:
+      loadSoftmax(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_MAX_POOL_2D:
+      loadMaxPool2D(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_CONCATENATION:
+      loadConcatenation(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_FULLY_CONNECTED:
+      loadFC(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_ADD:
+      loadAdd(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_SUB:
+      loadSub(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_MUL:
+      loadMul(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_DIV:
+      loadDiv(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_PACK:
+      loadPack(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_RELU:
+      loadRelu(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_RELU6:
+      loadRelu6(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_RESIZE_BILINEAR:
+      loadResizeBilinear(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_RSQRT:
+      loadRsqrt(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_SQRT:
+      loadSqrt(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_SQUARED_DIFFERENCE:
+      loadSquaredDifference(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_TANH:
+      loadTanh(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_TRANSPOSE:
+      loadTranspose(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_MEAN:
+      loadMean(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_REDUCE_MAX:
+      loadReduceMax(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_PAD:
+      loadPad(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_LOGISTIC:
+      loadLogistic(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_EXP:
+      loadExp(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_GATHER:
+      loadGather(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_SPACE_TO_BATCH_ND:
+      loadSpaceToBatchND(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_BATCH_TO_SPACE_ND:
+      loadBatchToSpaceND(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_SUM:
+      loadReduceSum(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_CUSTOM:
+      loadCustom(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_SQUEEZE:
+      loadSqueeze(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_PRELU:
+      loadPrelu(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_SPLIT:
+      loadSplit(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_SLICE:
+      loadSlice(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_STRIDED_SLICE:
+      loadStridedSlice(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_UNPACK:
+      loadUnpack(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_MINIMUM:
+      loadMinimum(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_MAXIMUM:
+      loadMaximum(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_CAST:
+      loadCast(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_EQUAL:
+    case BuiltinOperator::BuiltinOperator_GREATER_EQUAL:
+    case BuiltinOperator::BuiltinOperator_GREATER:
+    case BuiltinOperator::BuiltinOperator_LESS_EQUAL:
+    case BuiltinOperator::BuiltinOperator_LESS:
+      loadComparison(op);
+      return;
+    case BuiltinOperator::BuiltinOperator_ONE_HOT:
+      loadOneHot(op);
+      return;
+    default:
+      throw std::runtime_error(
+          std::string("Unsupported operation: ").append(EnumNameBuiltinOperator(builtin_op)));
+  }
+}
+
+template <typename LoaderDomain, typename SpecificLoader>
+void BaseLoader<LoaderDomain, SpecificLoader>::loadModel()
+{
+  LoaderDomain::VerifyModelBuffer(*_verifier.get());
+  _model = LoaderDomain::GetModel(_buffer.data());
+  // Version unused
+  // const auto version = _model->version();
+  // Description unused
+  // const auto *description = _model->description();
+  // Metabuffer unsued
+  // const auto *metadata_buffer = _model->metadata_buffer();
+  // Load subgraphs and mapping from op to subgraph
+  for (const auto *subgraph : *_model->subgraphs())
+  {
+    static_cast<SpecificLoader *>(this)->loadSubgraph(subgraph);
+  }
+
+  _graph.finishBuilding();
+}
+
+} // namespace base_loader
+} // namespace neurun
+
+#endif //__BASE_LOADER_BASE_LOADER_H__
diff --git a/runtime/neurun/frontend/circle/CMakeLists.txt b/runtime/neurun/frontend/circle/CMakeLists.txt
new file mode 100644
index 000000000..fea9725c2
--- /dev/null
+++ b/runtime/neurun/frontend/circle/CMakeLists.txt
@@ -0,0 +1,17 @@
+if (NOT BUILD_CIRCLE_LOADER)
+    return()
+endif ()
+
+nnfw_find_package(FlatBuffersSource REQUIRED)
+
+set(CIRCLE_LOADER_SOURCES src/circle_loader.cc)
+
+add_library(circle_loader SHARED ${CIRCLE_LOADER_SOURCES})
+
+target_include_directories(circle_loader PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/include)
+target_include_directories(circle_loader PRIVATE ${FlatBuffersSource_DIR}/include)
+
+target_link_libraries(circle_loader PUBLIC neurun_core)
+target_link_libraries(circle_loader PRIVATE base_loader nnfw_lib_cpp14 nnfw_common nnfw_coverage)
+
+install(TARGETS circle_loader DESTINATION lib)
diff --git a/runtime/neurun/frontend/circle/include/circle_loader.h b/runtime/neurun/frontend/circle/include/circle_loader.h
new file mode 100644
index 000000000..898bd32b1
--- /dev/null
+++ b/runtime/neurun/frontend/circle/include/circle_loader.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CIRCLE_CIRCLE_LOADER_H__
+#define __CIRCLE_CIRCLE_LOADER_H__
+
+#include "ir/Graph.h"
+
+#include <memory>
+
+namespace neurun
+{
+namespace circle_loader
+{
+std::unique_ptr<ir::Graph> loadModel(const char *filename);
+} // namespace circle_loader
+} // namespace neurun
+
+#endif // __CIRCLE_CIRCLE_LOADER_H__
diff --git a/runtime/neurun/frontend/circle/src/circle_loader.cc b/runtime/neurun/frontend/circle/src/circle_loader.cc
new file mode 100644
index 000000000..cc48a793d
--- /dev/null
+++ b/runtime/neurun/frontend/circle/src/circle_loader.cc
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "circle_loader.h"
+#include "base_loader.h"
+#include "circle_schema_generated.h"
+
+namespace neurun
+{
+namespace circle_loader
+{
+
+namespace
+{
+
+struct LoaderDomain
+{
+  using Verifier = flatbuffers::Verifier;
+  using ActivationFunctionType = circle::ActivationFunctionType;
+  using Buffer = circle::Buffer;
+  using BuiltinOperator = circle::BuiltinOperator;
+  using CustomOptionsFormat = circle::CustomOptionsFormat;
+  using Model = circle::Model;
+  using Operator = circle::Operator;
+  using Padding = circle::Padding;
+  using Pool2DOptions = circle::Pool2DOptions;
+  using Tensor = circle::Tensor;
+  using TensorType = circle::TensorType;
+  using SubGraph = circle::SubGraph;
+
+  static const char *EnumNameBuiltinOperator(BuiltinOperator e)
+  {
+    return circle::EnumNameBuiltinOperator(e);
+  }
+  static const char *EnumNameActivationFunctionType(ActivationFunctionType e)
+  {
+    return circle::EnumNameActivationFunctionType(e);
+  }
+  static const char *EnumNameTensorType(TensorType e) { return circle::EnumNameTensorType(e); }
+  static const Model *GetModel(const void *buf) { return circle::GetModel(buf); }
+  static bool VerifyModelBuffer(Verifier &verifier) { return circle::VerifyModelBuffer(verifier); }
+};
+
+class CircleLoader final : public base_loader::BaseLoader<LoaderDomain, CircleLoader>
+{
+public:
+  using BaseLoader::BaseLoader;
+
+  void loadSubgraph(const circle::SubGraph *subgraph)
+  {
+    // Load tensors
+    _tensor_to_operand.resize(subgraph->tensors()->size());
+    for (flatbuffers::uoffset_t i = 0; i < subgraph->tensors()->size(); ++i)
+    {
+      _tensor_to_operand[i] = loadOperand(subgraph->tensors()->Get(i));
+    }
+    // Set inputs
+    for (const std::int32_t input_ind : *subgraph->inputs())
+    {
+      _graph.addInput(_tensor_to_operand[input_ind]);
+    }
+    // Set outputs
+    for (const std::int32_t output_ind : *subgraph->outputs())
+    {
+      _graph.addOutput(_tensor_to_operand[output_ind]);
+    }
+    // Create operations
+    for (const auto *op : *subgraph->operators())
+    {
+      CircleLoader::loadOperation(op);
+    }
+
+    (void)subgraph->data_format();
+  }
+
+  void loadOperation(const circle::Operator *op)
+  {
+    const auto builtin_op = _model->operator_codes()->Get(op->opcode_index())->builtin_code();
+
+    switch (builtin_op)
+    {
+      case circle::BuiltinOperator::BuiltinOperator_INSTANCE_NORM:
+        loadInstanceNorm(op);
+        return;
+      default:
+        BaseLoader::loadOperation(op);
+        return;
+    }
+  }
+};
+
+} // namespace
+
+std::unique_ptr<ir::Graph> loadModel(const char *filename)
+{
+  auto graph = nnfw::cpp14::make_unique<ir::Graph>();
+  CircleLoader loader(*graph);
+  loader.loadFromFile(filename);
+  return graph;
+}
+
+} // namespace circle_loader
+} // namespace neurun
diff --git a/runtime/neurun/frontend/circle/src/circle_schema_generated.h b/runtime/neurun/frontend/circle/src/circle_schema_generated.h
new file mode 100644
index 000000000..5f7aad462
--- /dev/null
+++ b/runtime/neurun/frontend/circle/src/circle_schema_generated.h
@@ -0,0 +1,7546 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+// automatically generated by the FlatBuffers compiler, do not modify
+
+#ifndef FLATBUFFERS_GENERATED_CIRCLESCHEMA_CIRCLE_H_
+#define FLATBUFFERS_GENERATED_CIRCLESCHEMA_CIRCLE_H_
+
+#include "flatbuffers/flatbuffers.h"
+
+namespace circle
+{
+
+struct CustomQuantization;
+
+struct QuantizationParameters;
+
+struct Tensor;
+
+struct Conv2DOptions;
+
+struct Pool2DOptions;
+
+struct DepthwiseConv2DOptions;
+
+struct ConcatEmbeddingsOptions;
+
+struct LSHProjectionOptions;
+
+struct SVDFOptions;
+
+struct RNNOptions;
+
+struct SequenceRNNOptions;
+
+struct BidirectionalSequenceRNNOptions;
+
+struct FullyConnectedOptions;
+
+struct SoftmaxOptions;
+
+struct ConcatenationOptions;
+
+struct AddOptions;
+
+struct MulOptions;
+
+struct L2NormOptions;
+
+struct LocalResponseNormalizationOptions;
+
+struct LSTMOptions;
+
+struct UnidirectionalSequenceLSTMOptions;
+
+struct BidirectionalSequenceLSTMOptions;
+
+struct ResizeBilinearOptions;
+
+struct ResizeNearestNeighborOptions;
+
+struct CallOptions;
+
+struct PadOptions;
+
+struct PadV2Options;
+
+struct ReshapeOptions;
+
+struct SpaceToBatchNDOptions;
+
+struct BatchToSpaceNDOptions;
+
+struct SkipGramOptions;
+
+struct SpaceToDepthOptions;
+
+struct SubOptions;
+
+struct DivOptions;
+
+struct TopKV2Options;
+
+struct EmbeddingLookupSparseOptions;
+
+struct GatherOptions;
+
+struct TransposeOptions;
+
+struct ExpOptions;
+
+struct ReducerOptions;
+
+struct SqueezeOptions;
+
+struct SplitOptions;
+
+struct SplitVOptions;
+
+struct StridedSliceOptions;
+
+struct LogSoftmaxOptions;
+
+struct CastOptions;
+
+struct DequantizeOptions;
+
+struct MaximumMinimumOptions;
+
+struct TileOptions;
+
+struct ArgMaxOptions;
+
+struct ArgMinOptions;
+
+struct GreaterOptions;
+
+struct GreaterEqualOptions;
+
+struct LessOptions;
+
+struct LessEqualOptions;
+
+struct NegOptions;
+
+struct SelectOptions;
+
+struct SliceOptions;
+
+struct TransposeConvOptions;
+
+struct ExpandDimsOptions;
+
+struct SparseToDenseOptions;
+
+struct EqualOptions;
+
+struct NotEqualOptions;
+
+struct ShapeOptions;
+
+struct PowOptions;
+
+struct FakeQuantOptions;
+
+struct PackOptions;
+
+struct LogicalOrOptions;
+
+struct OneHotOptions;
+
+struct AbsOptions;
+
+struct LogicalAndOptions;
+
+struct LogicalNotOptions;
+
+struct UnpackOptions;
+
+struct FloorDivOptions;
+
+struct SquareOptions;
+
+struct ZerosLikeOptions;
+
+struct FillOptions;
+
+struct FloorModOptions;
+
+struct RangeOptions;
+
+struct LeakyReluOptions;
+
+struct SquaredDifferenceOptions;
+
+struct MirrorPadOptions;
+
+struct InstanceNormOptions;
+
+struct OperatorCode;
+
+struct Operator;
+
+struct SubGraph;
+
+struct Buffer;
+
+struct Model;
+
+enum TensorType
+{
+  TensorType_FLOAT32 = 0,
+  TensorType_FLOAT16 = 1,
+  TensorType_INT32 = 2,
+  TensorType_UINT8 = 3,
+  TensorType_INT64 = 4,
+  TensorType_STRING = 5,
+  TensorType_BOOL = 6,
+  TensorType_INT16 = 7,
+  TensorType_COMPLEX64 = 8,
+  TensorType_INT8 = 9,
+  TensorType_MIN = TensorType_FLOAT32,
+  TensorType_MAX = TensorType_INT8
+};
+
+inline const TensorType (&EnumValuesTensorType())[10]
+{
+  static const TensorType values[] = {TensorType_FLOAT32, TensorType_FLOAT16, TensorType_INT32,
+                                      TensorType_UINT8,   TensorType_INT64,   TensorType_STRING,
+                                      TensorType_BOOL,    TensorType_INT16,   TensorType_COMPLEX64,
+                                      TensorType_INT8};
+  return values;
+}
+
+inline const char *const *EnumNamesTensorType()
+{
+  static const char *const names[] = {"FLOAT32", "FLOAT16", "INT32",     "UINT8", "INT64", "STRING",
+                                      "BOOL",    "INT16",   "COMPLEX64", "INT8",  nullptr};
+  return names;
+}
+
+inline const char *EnumNameTensorType(TensorType e)
+{
+  const size_t index = static_cast<int>(e);
+  return EnumNamesTensorType()[index];
+}
+
+enum QuantizationDetails
+{
+  QuantizationDetails_NONE = 0,
+  QuantizationDetails_CustomQuantization = 1,
+  QuantizationDetails_MIN = QuantizationDetails_NONE,
+  QuantizationDetails_MAX = QuantizationDetails_CustomQuantization
+};
+
+inline const QuantizationDetails (&EnumValuesQuantizationDetails())[2]
+{
+  static const QuantizationDetails values[] = {QuantizationDetails_NONE,
+                                               QuantizationDetails_CustomQuantization};
+  return values;
+}
+
+inline const char *const *EnumNamesQuantizationDetails()
+{
+  static const char *const names[] = {"NONE", "CustomQuantization", nullptr};
+  return names;
+}
+
+inline const char *EnumNameQuantizationDetails(QuantizationDetails e)
+{
+  const size_t index = static_cast<int>(e);
+  return EnumNamesQuantizationDetails()[index];
+}
+
+template <typename T> struct QuantizationDetailsTraits
+{
+  static const QuantizationDetails enum_value = QuantizationDetails_NONE;
+};
+
+template <> struct QuantizationDetailsTraits<CustomQuantization>
+{
+  static const QuantizationDetails enum_value = QuantizationDetails_CustomQuantization;
+};
+
+bool VerifyQuantizationDetails(flatbuffers::Verifier &verifier, const void *obj,
+                               QuantizationDetails type);
+bool VerifyQuantizationDetailsVector(flatbuffers::Verifier &verifier,
+                                     const flatbuffers::Vector<flatbuffers::Offset<void>> *values,
+                                     const flatbuffers::Vector<uint8_t> *types);
+
+enum BuiltinOperator
+{
+  BuiltinOperator_ADD = 0,
+  BuiltinOperator_AVERAGE_POOL_2D = 1,
+  BuiltinOperator_CONCATENATION = 2,
+  BuiltinOperator_CONV_2D = 3,
+  BuiltinOperator_DEPTHWISE_CONV_2D = 4,
+  BuiltinOperator_DEQUANTIZE = 6,
+  BuiltinOperator_EMBEDDING_LOOKUP = 7,
+  BuiltinOperator_FLOOR = 8,
+  BuiltinOperator_FULLY_CONNECTED = 9,
+  BuiltinOperator_HASHTABLE_LOOKUP = 10,
+  BuiltinOperator_L2_NORMALIZATION = 11,
+  BuiltinOperator_L2_POOL_2D = 12,
+  BuiltinOperator_LOCAL_RESPONSE_NORMALIZATION = 13,
+  BuiltinOperator_LOGISTIC = 14,
+  BuiltinOperator_LSH_PROJECTION = 15,
+  BuiltinOperator_LSTM = 16,
+  BuiltinOperator_MAX_POOL_2D = 17,
+  BuiltinOperator_MUL = 18,
+  BuiltinOperator_RELU = 19,
+  BuiltinOperator_RELU_N1_TO_1 = 20,
+  BuiltinOperator_RELU6 = 21,
+  BuiltinOperator_RESHAPE = 22,
+  BuiltinOperator_RESIZE_BILINEAR = 23,
+  BuiltinOperator_RNN = 24,
+  BuiltinOperator_SOFTMAX = 25,
+  BuiltinOperator_SPACE_TO_DEPTH = 26,
+  BuiltinOperator_SVDF = 27,
+  BuiltinOperator_TANH = 28,
+  BuiltinOperator_CONCAT_EMBEDDINGS = 29,
+  BuiltinOperator_SKIP_GRAM = 30,
+  BuiltinOperator_CALL = 31,
+  BuiltinOperator_CUSTOM = 32,
+  BuiltinOperator_EMBEDDING_LOOKUP_SPARSE = 33,
+  BuiltinOperator_PAD = 34,
+  BuiltinOperator_UNIDIRECTIONAL_SEQUENCE_RNN = 35,
+  BuiltinOperator_GATHER = 36,
+  BuiltinOperator_BATCH_TO_SPACE_ND = 37,
+  BuiltinOperator_SPACE_TO_BATCH_ND = 38,
+  BuiltinOperator_TRANSPOSE = 39,
+  BuiltinOperator_MEAN = 40,
+  BuiltinOperator_SUB = 41,
+  BuiltinOperator_DIV = 42,
+  BuiltinOperator_SQUEEZE = 43,
+  BuiltinOperator_UNIDIRECTIONAL_SEQUENCE_LSTM = 44,
+  BuiltinOperator_STRIDED_SLICE = 45,
+  BuiltinOperator_BIDIRECTIONAL_SEQUENCE_RNN = 46,
+  BuiltinOperator_EXP = 47,
+  BuiltinOperator_TOPK_V2 = 48,
+  BuiltinOperator_SPLIT = 49,
+  BuiltinOperator_LOG_SOFTMAX = 50,
+  BuiltinOperator_DELEGATE = 51,
+  BuiltinOperator_BIDIRECTIONAL_SEQUENCE_LSTM = 52,
+  BuiltinOperator_CAST = 53,
+  BuiltinOperator_PRELU = 54,
+  BuiltinOperator_MAXIMUM = 55,
+  BuiltinOperator_ARG_MAX = 56,
+  BuiltinOperator_MINIMUM = 57,
+  BuiltinOperator_LESS = 58,
+  BuiltinOperator_NEG = 59,
+  BuiltinOperator_PADV2 = 60,
+  BuiltinOperator_GREATER = 61,
+  BuiltinOperator_GREATER_EQUAL = 62,
+  BuiltinOperator_LESS_EQUAL = 63,
+  BuiltinOperator_SELECT = 64,
+  BuiltinOperator_SLICE = 65,
+  BuiltinOperator_SIN = 66,
+  BuiltinOperator_TRANSPOSE_CONV = 67,
+  BuiltinOperator_SPARSE_TO_DENSE = 68,
+  BuiltinOperator_TILE = 69,
+  BuiltinOperator_EXPAND_DIMS = 70,
+  BuiltinOperator_EQUAL = 71,
+  BuiltinOperator_NOT_EQUAL = 72,
+  BuiltinOperator_LOG = 73,
+  BuiltinOperator_SUM = 74,
+  BuiltinOperator_SQRT = 75,
+  BuiltinOperator_RSQRT = 76,
+  BuiltinOperator_SHAPE = 77,
+  BuiltinOperator_POW = 78,
+  BuiltinOperator_ARG_MIN = 79,
+  BuiltinOperator_FAKE_QUANT = 80,
+  BuiltinOperator_REDUCE_PROD = 81,
+  BuiltinOperator_REDUCE_MAX = 82,
+  BuiltinOperator_PACK = 83,
+  BuiltinOperator_LOGICAL_OR = 84,
+  BuiltinOperator_ONE_HOT = 85,
+  BuiltinOperator_LOGICAL_AND = 86,
+  BuiltinOperator_LOGICAL_NOT = 87,
+  BuiltinOperator_UNPACK = 88,
+  BuiltinOperator_REDUCE_MIN = 89,
+  BuiltinOperator_FLOOR_DIV = 90,
+  BuiltinOperator_REDUCE_ANY = 91,
+  BuiltinOperator_SQUARE = 92,
+  BuiltinOperator_ZEROS_LIKE = 93,
+  BuiltinOperator_FILL = 94,
+  BuiltinOperator_FLOOR_MOD = 95,
+  BuiltinOperator_RANGE = 96,
+  BuiltinOperator_RESIZE_NEAREST_NEIGHBOR = 97,
+  BuiltinOperator_LEAKY_RELU = 98,
+  BuiltinOperator_SQUARED_DIFFERENCE = 99,
+  BuiltinOperator_MIRROR_PAD = 100,
+  BuiltinOperator_ABS = 101,
+  BuiltinOperator_SPLIT_V = 102,
+  BuiltinOperator_INSTANCE_NORM = 254,
+  BuiltinOperator_MIN = BuiltinOperator_ADD,
+  BuiltinOperator_MAX = BuiltinOperator_INSTANCE_NORM
+};
+
+inline const BuiltinOperator (&EnumValuesBuiltinOperator())[103]
+{
+  static const BuiltinOperator values[] = {BuiltinOperator_ADD,
+                                           BuiltinOperator_AVERAGE_POOL_2D,
+                                           BuiltinOperator_CONCATENATION,
+                                           BuiltinOperator_CONV_2D,
+                                           BuiltinOperator_DEPTHWISE_CONV_2D,
+                                           BuiltinOperator_DEQUANTIZE,
+                                           BuiltinOperator_EMBEDDING_LOOKUP,
+                                           BuiltinOperator_FLOOR,
+                                           BuiltinOperator_FULLY_CONNECTED,
+                                           BuiltinOperator_HASHTABLE_LOOKUP,
+                                           BuiltinOperator_L2_NORMALIZATION,
+                                           BuiltinOperator_L2_POOL_2D,
+                                           BuiltinOperator_LOCAL_RESPONSE_NORMALIZATION,
+                                           BuiltinOperator_LOGISTIC,
+                                           BuiltinOperator_LSH_PROJECTION,
+                                           BuiltinOperator_LSTM,
+                                           BuiltinOperator_MAX_POOL_2D,
+                                           BuiltinOperator_MUL,
+                                           BuiltinOperator_RELU,
+                                           BuiltinOperator_RELU_N1_TO_1,
+                                           BuiltinOperator_RELU6,
+                                           BuiltinOperator_RESHAPE,
+                                           BuiltinOperator_RESIZE_BILINEAR,
+                                           BuiltinOperator_RNN,
+                                           BuiltinOperator_SOFTMAX,
+                                           BuiltinOperator_SPACE_TO_DEPTH,
+                                           BuiltinOperator_SVDF,
+                                           BuiltinOperator_TANH,
+                                           BuiltinOperator_CONCAT_EMBEDDINGS,
+                                           BuiltinOperator_SKIP_GRAM,
+                                           BuiltinOperator_CALL,
+                                           BuiltinOperator_CUSTOM,
+                                           BuiltinOperator_EMBEDDING_LOOKUP_SPARSE,
+                                           BuiltinOperator_PAD,
+                                           BuiltinOperator_UNIDIRECTIONAL_SEQUENCE_RNN,
+                                           BuiltinOperator_GATHER,
+                                           BuiltinOperator_BATCH_TO_SPACE_ND,
+                                           BuiltinOperator_SPACE_TO_BATCH_ND,
+                                           BuiltinOperator_TRANSPOSE,
+                                           BuiltinOperator_MEAN,
+                                           BuiltinOperator_SUB,
+                                           BuiltinOperator_DIV,
+                                           BuiltinOperator_SQUEEZE,
+                                           BuiltinOperator_UNIDIRECTIONAL_SEQUENCE_LSTM,
+                                           BuiltinOperator_STRIDED_SLICE,
+                                           BuiltinOperator_BIDIRECTIONAL_SEQUENCE_RNN,
+                                           BuiltinOperator_EXP,
+                                           BuiltinOperator_TOPK_V2,
+                                           BuiltinOperator_SPLIT,
+                                           BuiltinOperator_LOG_SOFTMAX,
+                                           BuiltinOperator_DELEGATE,
+                                           BuiltinOperator_BIDIRECTIONAL_SEQUENCE_LSTM,
+                                           BuiltinOperator_CAST,
+                                           BuiltinOperator_PRELU,
+                                           BuiltinOperator_MAXIMUM,
+                                           BuiltinOperator_ARG_MAX,
+                                           BuiltinOperator_MINIMUM,
+                                           BuiltinOperator_LESS,
+                                           BuiltinOperator_NEG,
+                                           BuiltinOperator_PADV2,
+                                           BuiltinOperator_GREATER,
+                                           BuiltinOperator_GREATER_EQUAL,
+                                           BuiltinOperator_LESS_EQUAL,
+                                           BuiltinOperator_SELECT,
+                                           BuiltinOperator_SLICE,
+                                           BuiltinOperator_SIN,
+                                           BuiltinOperator_TRANSPOSE_CONV,
+                                           BuiltinOperator_SPARSE_TO_DENSE,
+                                           BuiltinOperator_TILE,
+                                           BuiltinOperator_EXPAND_DIMS,
+                                           BuiltinOperator_EQUAL,
+                                           BuiltinOperator_NOT_EQUAL,
+                                           BuiltinOperator_LOG,
+                                           BuiltinOperator_SUM,
+                                           BuiltinOperator_SQRT,
+                                           BuiltinOperator_RSQRT,
+                                           BuiltinOperator_SHAPE,
+                                           BuiltinOperator_POW,
+                                           BuiltinOperator_ARG_MIN,
+                                           BuiltinOperator_FAKE_QUANT,
+                                           BuiltinOperator_REDUCE_PROD,
+                                           BuiltinOperator_REDUCE_MAX,
+                                           BuiltinOperator_PACK,
+                                           BuiltinOperator_LOGICAL_OR,
+                                           BuiltinOperator_ONE_HOT,
+                                           BuiltinOperator_LOGICAL_AND,
+                                           BuiltinOperator_LOGICAL_NOT,
+                                           BuiltinOperator_UNPACK,
+                                           BuiltinOperator_REDUCE_MIN,
+                                           BuiltinOperator_FLOOR_DIV,
+                                           BuiltinOperator_REDUCE_ANY,
+                                           BuiltinOperator_SQUARE,
+                                           BuiltinOperator_ZEROS_LIKE,
+                                           BuiltinOperator_FILL,
+                                           BuiltinOperator_FLOOR_MOD,
+                                           BuiltinOperator_RANGE,
+                                           BuiltinOperator_RESIZE_NEAREST_NEIGHBOR,
+                                           BuiltinOperator_LEAKY_RELU,
+                                           BuiltinOperator_SQUARED_DIFFERENCE,
+                                           BuiltinOperator_MIRROR_PAD,
+                                           BuiltinOperator_ABS,
+                                           BuiltinOperator_SPLIT_V,
+                                           BuiltinOperator_INSTANCE_NORM};
+  return values;
+}
+
+inline const char *const *EnumNamesBuiltinOperator()
+{
+  static const char *const names[] = {"ADD",
+                                      "AVERAGE_POOL_2D",
+                                      "CONCATENATION",
+                                      "CONV_2D",
+                                      "DEPTHWISE_CONV_2D",
+                                      "",
+                                      "DEQUANTIZE",
+                                      "EMBEDDING_LOOKUP",
+                                      "FLOOR",
+                                      "FULLY_CONNECTED",
+                                      "HASHTABLE_LOOKUP",
+                                      "L2_NORMALIZATION",
+                                      "L2_POOL_2D",
+                                      "LOCAL_RESPONSE_NORMALIZATION",
+                                      "LOGISTIC",
+                                      "LSH_PROJECTION",
+                                      "LSTM",
+                                      "MAX_POOL_2D",
+                                      "MUL",
+                                      "RELU",
+                                      "RELU_N1_TO_1",
+                                      "RELU6",
+                                      "RESHAPE",
+                                      "RESIZE_BILINEAR",
+                                      "RNN",
+                                      "SOFTMAX",
+                                      "SPACE_TO_DEPTH",
+                                      "SVDF",
+                                      "TANH",
+                                      "CONCAT_EMBEDDINGS",
+                                      "SKIP_GRAM",
+                                      "CALL",
+                                      "CUSTOM",
+                                      "EMBEDDING_LOOKUP_SPARSE",
+                                      "PAD",
+                                      "UNIDIRECTIONAL_SEQUENCE_RNN",
+                                      "GATHER",
+                                      "BATCH_TO_SPACE_ND",
+                                      "SPACE_TO_BATCH_ND",
+                                      "TRANSPOSE",
+                                      "MEAN",
+                                      "SUB",
+                                      "DIV",
+                                      "SQUEEZE",
+                                      "UNIDIRECTIONAL_SEQUENCE_LSTM",
+                                      "STRIDED_SLICE",
+                                      "BIDIRECTIONAL_SEQUENCE_RNN",
+                                      "EXP",
+                                      "TOPK_V2",
+                                      "SPLIT",
+                                      "LOG_SOFTMAX",
+                                      "DELEGATE",
+                                      "BIDIRECTIONAL_SEQUENCE_LSTM",
+                                      "CAST",
+                                      "PRELU",
+                                      "MAXIMUM",
+                                      "ARG_MAX",
+                                      "MINIMUM",
+                                      "LESS",
+                                      "NEG",
+                                      "PADV2",
+                                      "GREATER",
+                                      "GREATER_EQUAL",
+                                      "LESS_EQUAL",
+                                      "SELECT",
+                                      "SLICE",
+                                      "SIN",
+                                      "TRANSPOSE_CONV",
+                                      "SPARSE_TO_DENSE",
+                                      "TILE",
+                                      "EXPAND_DIMS",
+                                      "EQUAL",
+                                      "NOT_EQUAL",
+                                      "LOG",
+                                      "SUM",
+                                      "SQRT",
+                                      "RSQRT",
+                                      "SHAPE",
+                                      "POW",
+                                      "ARG_MIN",
+                                      "FAKE_QUANT",
+                                      "REDUCE_PROD",
+                                      "REDUCE_MAX",
+                                      "PACK",
+                                      "LOGICAL_OR",
+                                      "ONE_HOT",
+                                      "LOGICAL_AND",
+                                      "LOGICAL_NOT",
+                                      "UNPACK",
+                                      "REDUCE_MIN",
+                                      "FLOOR_DIV",
+                                      "REDUCE_ANY",
+                                      "SQUARE",
+                                      "ZEROS_LIKE",
+                                      "FILL",
+                                      "FLOOR_MOD",
+                                      "RANGE",
+                                      "RESIZE_NEAREST_NEIGHBOR",
+                                      "LEAKY_RELU",
+                                      "SQUARED_DIFFERENCE",
+                                      "MIRROR_PAD",
+                                      "ABS",
+                                      "SPLIT_V",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "",
+                                      "INSTANCE_NORM",
+                                      nullptr};
+  return names;
+}
+
+inline const char *EnumNameBuiltinOperator(BuiltinOperator e)
+{
+  const size_t index = static_cast<int>(e);
+  return EnumNamesBuiltinOperator()[index];
+}
+
+enum BuiltinOptions
+{
+  BuiltinOptions_NONE = 0,
+  BuiltinOptions_Conv2DOptions = 1,
+  BuiltinOptions_DepthwiseConv2DOptions = 2,
+  BuiltinOptions_ConcatEmbeddingsOptions = 3,
+  BuiltinOptions_LSHProjectionOptions = 4,
+  BuiltinOptions_Pool2DOptions = 5,
+  BuiltinOptions_SVDFOptions = 6,
+  BuiltinOptions_RNNOptions = 7,
+  BuiltinOptions_FullyConnectedOptions = 8,
+  BuiltinOptions_SoftmaxOptions = 9,
+  BuiltinOptions_ConcatenationOptions = 10,
+  BuiltinOptions_AddOptions = 11,
+  BuiltinOptions_L2NormOptions = 12,
+  BuiltinOptions_LocalResponseNormalizationOptions = 13,
+  BuiltinOptions_LSTMOptions = 14,
+  BuiltinOptions_ResizeBilinearOptions = 15,
+  BuiltinOptions_CallOptions = 16,
+  BuiltinOptions_ReshapeOptions = 17,
+  BuiltinOptions_SkipGramOptions = 18,
+  BuiltinOptions_SpaceToDepthOptions = 19,
+  BuiltinOptions_EmbeddingLookupSparseOptions = 20,
+  BuiltinOptions_MulOptions = 21,
+  BuiltinOptions_PadOptions = 22,
+  BuiltinOptions_GatherOptions = 23,
+  BuiltinOptions_BatchToSpaceNDOptions = 24,
+  BuiltinOptions_SpaceToBatchNDOptions = 25,
+  BuiltinOptions_TransposeOptions = 26,
+  BuiltinOptions_ReducerOptions = 27,
+  BuiltinOptions_SubOptions = 28,
+  BuiltinOptions_DivOptions = 29,
+  BuiltinOptions_SqueezeOptions = 30,
+  BuiltinOptions_SequenceRNNOptions = 31,
+  BuiltinOptions_StridedSliceOptions = 32,
+  BuiltinOptions_ExpOptions = 33,
+  BuiltinOptions_TopKV2Options = 34,
+  BuiltinOptions_SplitOptions = 35,
+  BuiltinOptions_LogSoftmaxOptions = 36,
+  BuiltinOptions_CastOptions = 37,
+  BuiltinOptions_DequantizeOptions = 38,
+  BuiltinOptions_MaximumMinimumOptions = 39,
+  BuiltinOptions_ArgMaxOptions = 40,
+  BuiltinOptions_LessOptions = 41,
+  BuiltinOptions_NegOptions = 42,
+  BuiltinOptions_PadV2Options = 43,
+  BuiltinOptions_GreaterOptions = 44,
+  BuiltinOptions_GreaterEqualOptions = 45,
+  BuiltinOptions_LessEqualOptions = 46,
+  BuiltinOptions_SelectOptions = 47,
+  BuiltinOptions_SliceOptions = 48,
+  BuiltinOptions_TransposeConvOptions = 49,
+  BuiltinOptions_SparseToDenseOptions = 50,
+  BuiltinOptions_TileOptions = 51,
+  BuiltinOptions_ExpandDimsOptions = 52,
+  BuiltinOptions_EqualOptions = 53,
+  BuiltinOptions_NotEqualOptions = 54,
+  BuiltinOptions_ShapeOptions = 55,
+  BuiltinOptions_PowOptions = 56,
+  BuiltinOptions_ArgMinOptions = 57,
+  BuiltinOptions_FakeQuantOptions = 58,
+  BuiltinOptions_PackOptions = 59,
+  BuiltinOptions_LogicalOrOptions = 60,
+  BuiltinOptions_OneHotOptions = 61,
+  BuiltinOptions_LogicalAndOptions = 62,
+  BuiltinOptions_LogicalNotOptions = 63,
+  BuiltinOptions_UnpackOptions = 64,
+  BuiltinOptions_FloorDivOptions = 65,
+  BuiltinOptions_SquareOptions = 66,
+  BuiltinOptions_ZerosLikeOptions = 67,
+  BuiltinOptions_FillOptions = 68,
+  BuiltinOptions_BidirectionalSequenceLSTMOptions = 69,
+  BuiltinOptions_BidirectionalSequenceRNNOptions = 70,
+  BuiltinOptions_UnidirectionalSequenceLSTMOptions = 71,
+  BuiltinOptions_FloorModOptions = 72,
+  BuiltinOptions_RangeOptions = 73,
+  BuiltinOptions_ResizeNearestNeighborOptions = 74,
+  BuiltinOptions_LeakyReluOptions = 75,
+  BuiltinOptions_SquaredDifferenceOptions = 76,
+  BuiltinOptions_MirrorPadOptions = 77,
+  BuiltinOptions_AbsOptions = 78,
+  BuiltinOptions_SplitVOptions = 79,
+  BuiltinOptions_InstanceNormOptions = 80,
+  BuiltinOptions_MIN = BuiltinOptions_NONE,
+  BuiltinOptions_MAX = BuiltinOptions_InstanceNormOptions
+};
+
+inline const BuiltinOptions (&EnumValuesBuiltinOptions())[81]
+{
+  static const BuiltinOptions values[] = {BuiltinOptions_NONE,
+                                          BuiltinOptions_Conv2DOptions,
+                                          BuiltinOptions_DepthwiseConv2DOptions,
+                                          BuiltinOptions_ConcatEmbeddingsOptions,
+                                          BuiltinOptions_LSHProjectionOptions,
+                                          BuiltinOptions_Pool2DOptions,
+                                          BuiltinOptions_SVDFOptions,
+                                          BuiltinOptions_RNNOptions,
+                                          BuiltinOptions_FullyConnectedOptions,
+                                          BuiltinOptions_SoftmaxOptions,
+                                          BuiltinOptions_ConcatenationOptions,
+                                          BuiltinOptions_AddOptions,
+                                          BuiltinOptions_L2NormOptions,
+                                          BuiltinOptions_LocalResponseNormalizationOptions,
+                                          BuiltinOptions_LSTMOptions,
+                                          BuiltinOptions_ResizeBilinearOptions,
+                                          BuiltinOptions_CallOptions,
+                                          BuiltinOptions_ReshapeOptions,
+                                          BuiltinOptions_SkipGramOptions,
+                                          BuiltinOptions_SpaceToDepthOptions,
+                                          BuiltinOptions_EmbeddingLookupSparseOptions,
+                                          BuiltinOptions_MulOptions,
+                                          BuiltinOptions_PadOptions,
+                                          BuiltinOptions_GatherOptions,
+                                          BuiltinOptions_BatchToSpaceNDOptions,
+                                          BuiltinOptions_SpaceToBatchNDOptions,
+                                          BuiltinOptions_TransposeOptions,
+                                          BuiltinOptions_ReducerOptions,
+                                          BuiltinOptions_SubOptions,
+                                          BuiltinOptions_DivOptions,
+                                          BuiltinOptions_SqueezeOptions,
+                                          BuiltinOptions_SequenceRNNOptions,
+                                          BuiltinOptions_StridedSliceOptions,
+                                          BuiltinOptions_ExpOptions,
+                                          BuiltinOptions_TopKV2Options,
+                                          BuiltinOptions_SplitOptions,
+                                          BuiltinOptions_LogSoftmaxOptions,
+                                          BuiltinOptions_CastOptions,
+                                          BuiltinOptions_DequantizeOptions,
+                                          BuiltinOptions_MaximumMinimumOptions,
+                                          BuiltinOptions_ArgMaxOptions,
+                                          BuiltinOptions_LessOptions,
+                                          BuiltinOptions_NegOptions,
+                                          BuiltinOptions_PadV2Options,
+                                          BuiltinOptions_GreaterOptions,
+                                          BuiltinOptions_GreaterEqualOptions,
+                                          BuiltinOptions_LessEqualOptions,
+                                          BuiltinOptions_SelectOptions,
+                                          BuiltinOptions_SliceOptions,
+                                          BuiltinOptions_TransposeConvOptions,
+                                          BuiltinOptions_SparseToDenseOptions,
+                                          BuiltinOptions_TileOptions,
+                                          BuiltinOptions_ExpandDimsOptions,
+                                          BuiltinOptions_EqualOptions,
+                                          BuiltinOptions_NotEqualOptions,
+                                          BuiltinOptions_ShapeOptions,
+                                          BuiltinOptions_PowOptions,
+                                          BuiltinOptions_ArgMinOptions,
+                                          BuiltinOptions_FakeQuantOptions,
+                                          BuiltinOptions_PackOptions,
+                                          BuiltinOptions_LogicalOrOptions,
+                                          BuiltinOptions_OneHotOptions,
+                                          BuiltinOptions_LogicalAndOptions,
+                                          BuiltinOptions_LogicalNotOptions,
+                                          BuiltinOptions_UnpackOptions,
+                                          BuiltinOptions_FloorDivOptions,
+                                          BuiltinOptions_SquareOptions,
+                                          BuiltinOptions_ZerosLikeOptions,
+                                          BuiltinOptions_FillOptions,
+                                          BuiltinOptions_BidirectionalSequenceLSTMOptions,
+                                          BuiltinOptions_BidirectionalSequenceRNNOptions,
+                                          BuiltinOptions_UnidirectionalSequenceLSTMOptions,
+                                          BuiltinOptions_FloorModOptions,
+                                          BuiltinOptions_RangeOptions,
+                                          BuiltinOptions_ResizeNearestNeighborOptions,
+                                          BuiltinOptions_LeakyReluOptions,
+                                          BuiltinOptions_SquaredDifferenceOptions,
+                                          BuiltinOptions_MirrorPadOptions,
+                                          BuiltinOptions_AbsOptions,
+                                          BuiltinOptions_SplitVOptions,
+                                          BuiltinOptions_InstanceNormOptions};
+  return values;
+}
+
+inline const char *const *EnumNamesBuiltinOptions()
+{
+  static const char *const names[] = {"NONE",
+                                      "Conv2DOptions",
+                                      "DepthwiseConv2DOptions",
+                                      "ConcatEmbeddingsOptions",
+                                      "LSHProjectionOptions",
+                                      "Pool2DOptions",
+                                      "SVDFOptions",
+                                      "RNNOptions",
+                                      "FullyConnectedOptions",
+                                      "SoftmaxOptions",
+                                      "ConcatenationOptions",
+                                      "AddOptions",
+                                      "L2NormOptions",
+                                      "LocalResponseNormalizationOptions",
+                                      "LSTMOptions",
+                                      "ResizeBilinearOptions",
+                                      "CallOptions",
+                                      "ReshapeOptions",
+                                      "SkipGramOptions",
+                                      "SpaceToDepthOptions",
+                                      "EmbeddingLookupSparseOptions",
+                                      "MulOptions",
+                                      "PadOptions",
+                                      "GatherOptions",
+                                      "BatchToSpaceNDOptions",
+                                      "SpaceToBatchNDOptions",
+                                      "TransposeOptions",
+                                      "ReducerOptions",
+                                      "SubOptions",
+                                      "DivOptions",
+                                      "SqueezeOptions",
+                                      "SequenceRNNOptions",
+                                      "StridedSliceOptions",
+                                      "ExpOptions",
+                                      "TopKV2Options",
+                                      "SplitOptions",
+                                      "LogSoftmaxOptions",
+                                      "CastOptions",
+                                      "DequantizeOptions",
+                                      "MaximumMinimumOptions",
+                                      "ArgMaxOptions",
+                                      "LessOptions",
+                                      "NegOptions",
+                                      "PadV2Options",
+                                      "GreaterOptions",
+                                      "GreaterEqualOptions",
+                                      "LessEqualOptions",
+                                      "SelectOptions",
+                                      "SliceOptions",
+                                      "TransposeConvOptions",
+                                      "SparseToDenseOptions",
+                                      "TileOptions",
+                                      "ExpandDimsOptions",
+                                      "EqualOptions",
+                                      "NotEqualOptions",
+                                      "ShapeOptions",
+                                      "PowOptions",
+                                      "ArgMinOptions",
+                                      "FakeQuantOptions",
+                                      "PackOptions",
+                                      "LogicalOrOptions",
+                                      "OneHotOptions",
+                                      "LogicalAndOptions",
+                                      "LogicalNotOptions",
+                                      "UnpackOptions",
+                                      "FloorDivOptions",
+                                      "SquareOptions",
+                                      "ZerosLikeOptions",
+                                      "FillOptions",
+                                      "BidirectionalSequenceLSTMOptions",
+                                      "BidirectionalSequenceRNNOptions",
+                                      "UnidirectionalSequenceLSTMOptions",
+                                      "FloorModOptions",
+                                      "RangeOptions",
+                                      "ResizeNearestNeighborOptions",
+                                      "LeakyReluOptions",
+                                      "SquaredDifferenceOptions",
+                                      "MirrorPadOptions",
+                                      "AbsOptions",
+                                      "SplitVOptions",
+                                      "InstanceNormOptions",
+                                      nullptr};
+  return names;
+}
+
+inline const char *EnumNameBuiltinOptions(BuiltinOptions e)
+{
+  const size_t index = static_cast<int>(e);
+  return EnumNamesBuiltinOptions()[index];
+}
+
+template <typename T> struct BuiltinOptionsTraits
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_NONE;
+};
+
+template <> struct BuiltinOptionsTraits<Conv2DOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_Conv2DOptions;
+};
+
+template <> struct BuiltinOptionsTraits<DepthwiseConv2DOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_DepthwiseConv2DOptions;
+};
+
+template <> struct BuiltinOptionsTraits<ConcatEmbeddingsOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_ConcatEmbeddingsOptions;
+};
+
+template <> struct BuiltinOptionsTraits<LSHProjectionOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_LSHProjectionOptions;
+};
+
+template <> struct BuiltinOptionsTraits<Pool2DOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_Pool2DOptions;
+};
+
+template <> struct BuiltinOptionsTraits<SVDFOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_SVDFOptions;
+};
+
+template <> struct BuiltinOptionsTraits<RNNOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_RNNOptions;
+};
+
+template <> struct BuiltinOptionsTraits<FullyConnectedOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_FullyConnectedOptions;
+};
+
+template <> struct BuiltinOptionsTraits<SoftmaxOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_SoftmaxOptions;
+};
+
+template <> struct BuiltinOptionsTraits<ConcatenationOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_ConcatenationOptions;
+};
+
+template <> struct BuiltinOptionsTraits<AddOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_AddOptions;
+};
+
+template <> struct BuiltinOptionsTraits<L2NormOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_L2NormOptions;
+};
+
+template <> struct BuiltinOptionsTraits<LocalResponseNormalizationOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_LocalResponseNormalizationOptions;
+};
+
+template <> struct BuiltinOptionsTraits<LSTMOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_LSTMOptions;
+};
+
+template <> struct BuiltinOptionsTraits<ResizeBilinearOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_ResizeBilinearOptions;
+};
+
+template <> struct BuiltinOptionsTraits<CallOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_CallOptions;
+};
+
+template <> struct BuiltinOptionsTraits<ReshapeOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_ReshapeOptions;
+};
+
+template <> struct BuiltinOptionsTraits<SkipGramOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_SkipGramOptions;
+};
+
+template <> struct BuiltinOptionsTraits<SpaceToDepthOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_SpaceToDepthOptions;
+};
+
+template <> struct BuiltinOptionsTraits<EmbeddingLookupSparseOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_EmbeddingLookupSparseOptions;
+};
+
+template <> struct BuiltinOptionsTraits<MulOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_MulOptions;
+};
+
+template <> struct BuiltinOptionsTraits<PadOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_PadOptions;
+};
+
+template <> struct BuiltinOptionsTraits<GatherOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_GatherOptions;
+};
+
+template <> struct BuiltinOptionsTraits<BatchToSpaceNDOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_BatchToSpaceNDOptions;
+};
+
+template <> struct BuiltinOptionsTraits<SpaceToBatchNDOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_SpaceToBatchNDOptions;
+};
+
+template <> struct BuiltinOptionsTraits<TransposeOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_TransposeOptions;
+};
+
+template <> struct BuiltinOptionsTraits<ReducerOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_ReducerOptions;
+};
+
+template <> struct BuiltinOptionsTraits<SubOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_SubOptions;
+};
+
+template <> struct BuiltinOptionsTraits<DivOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_DivOptions;
+};
+
+template <> struct BuiltinOptionsTraits<SqueezeOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_SqueezeOptions;
+};
+
+template <> struct BuiltinOptionsTraits<SequenceRNNOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_SequenceRNNOptions;
+};
+
+template <> struct BuiltinOptionsTraits<StridedSliceOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_StridedSliceOptions;
+};
+
+template <> struct BuiltinOptionsTraits<ExpOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_ExpOptions;
+};
+
+template <> struct BuiltinOptionsTraits<TopKV2Options>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_TopKV2Options;
+};
+
+template <> struct BuiltinOptionsTraits<SplitOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_SplitOptions;
+};
+
+template <> struct BuiltinOptionsTraits<LogSoftmaxOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_LogSoftmaxOptions;
+};
+
+template <> struct BuiltinOptionsTraits<CastOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_CastOptions;
+};
+
+template <> struct BuiltinOptionsTraits<DequantizeOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_DequantizeOptions;
+};
+
+template <> struct BuiltinOptionsTraits<MaximumMinimumOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_MaximumMinimumOptions;
+};
+
+template <> struct BuiltinOptionsTraits<ArgMaxOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_ArgMaxOptions;
+};
+
+template <> struct BuiltinOptionsTraits<LessOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_LessOptions;
+};
+
+template <> struct BuiltinOptionsTraits<NegOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_NegOptions;
+};
+
+template <> struct BuiltinOptionsTraits<PadV2Options>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_PadV2Options;
+};
+
+template <> struct BuiltinOptionsTraits<GreaterOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_GreaterOptions;
+};
+
+template <> struct BuiltinOptionsTraits<GreaterEqualOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_GreaterEqualOptions;
+};
+
+template <> struct BuiltinOptionsTraits<LessEqualOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_LessEqualOptions;
+};
+
+template <> struct BuiltinOptionsTraits<SelectOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_SelectOptions;
+};
+
+template <> struct BuiltinOptionsTraits<SliceOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_SliceOptions;
+};
+
+template <> struct BuiltinOptionsTraits<TransposeConvOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_TransposeConvOptions;
+};
+
+template <> struct BuiltinOptionsTraits<SparseToDenseOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_SparseToDenseOptions;
+};
+
+template <> struct BuiltinOptionsTraits<TileOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_TileOptions;
+};
+
+template <> struct BuiltinOptionsTraits<ExpandDimsOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_ExpandDimsOptions;
+};
+
+template <> struct BuiltinOptionsTraits<EqualOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_EqualOptions;
+};
+
+template <> struct BuiltinOptionsTraits<NotEqualOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_NotEqualOptions;
+};
+
+template <> struct BuiltinOptionsTraits<ShapeOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_ShapeOptions;
+};
+
+template <> struct BuiltinOptionsTraits<PowOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_PowOptions;
+};
+
+template <> struct BuiltinOptionsTraits<ArgMinOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_ArgMinOptions;
+};
+
+template <> struct BuiltinOptionsTraits<FakeQuantOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_FakeQuantOptions;
+};
+
+template <> struct BuiltinOptionsTraits<PackOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_PackOptions;
+};
+
+template <> struct BuiltinOptionsTraits<LogicalOrOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_LogicalOrOptions;
+};
+
+template <> struct BuiltinOptionsTraits<OneHotOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_OneHotOptions;
+};
+
+template <> struct BuiltinOptionsTraits<LogicalAndOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_LogicalAndOptions;
+};
+
+template <> struct BuiltinOptionsTraits<LogicalNotOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_LogicalNotOptions;
+};
+
+template <> struct BuiltinOptionsTraits<UnpackOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_UnpackOptions;
+};
+
+template <> struct BuiltinOptionsTraits<FloorDivOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_FloorDivOptions;
+};
+
+template <> struct BuiltinOptionsTraits<SquareOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_SquareOptions;
+};
+
+template <> struct BuiltinOptionsTraits<ZerosLikeOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_ZerosLikeOptions;
+};
+
+template <> struct BuiltinOptionsTraits<FillOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_FillOptions;
+};
+
+template <> struct BuiltinOptionsTraits<BidirectionalSequenceLSTMOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_BidirectionalSequenceLSTMOptions;
+};
+
+template <> struct BuiltinOptionsTraits<BidirectionalSequenceRNNOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_BidirectionalSequenceRNNOptions;
+};
+
+template <> struct BuiltinOptionsTraits<UnidirectionalSequenceLSTMOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_UnidirectionalSequenceLSTMOptions;
+};
+
+template <> struct BuiltinOptionsTraits<FloorModOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_FloorModOptions;
+};
+
+template <> struct BuiltinOptionsTraits<RangeOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_RangeOptions;
+};
+
+template <> struct BuiltinOptionsTraits<ResizeNearestNeighborOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_ResizeNearestNeighborOptions;
+};
+
+template <> struct BuiltinOptionsTraits<LeakyReluOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_LeakyReluOptions;
+};
+
+template <> struct BuiltinOptionsTraits<SquaredDifferenceOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_SquaredDifferenceOptions;
+};
+
+template <> struct BuiltinOptionsTraits<MirrorPadOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_MirrorPadOptions;
+};
+
+template <> struct BuiltinOptionsTraits<AbsOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_AbsOptions;
+};
+
+template <> struct BuiltinOptionsTraits<SplitVOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_SplitVOptions;
+};
+
+template <> struct BuiltinOptionsTraits<InstanceNormOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_InstanceNormOptions;
+};
+
+bool VerifyBuiltinOptions(flatbuffers::Verifier &verifier, const void *obj, BuiltinOptions type);
+bool VerifyBuiltinOptionsVector(flatbuffers::Verifier &verifier,
+                                const flatbuffers::Vector<flatbuffers::Offset<void>> *values,
+                                const flatbuffers::Vector<uint8_t> *types);
+
+enum Padding
+{
+  Padding_SAME = 0,
+  Padding_VALID = 1,
+  Padding_MIN = Padding_SAME,
+  Padding_MAX = Padding_VALID
+};
+
+inline const Padding (&EnumValuesPadding())[2]
+{
+  static const Padding values[] = {Padding_SAME, Padding_VALID};
+  return values;
+}
+
+inline const char *const *EnumNamesPadding()
+{
+  static const char *const names[] = {"SAME", "VALID", nullptr};
+  return names;
+}
+
+inline const char *EnumNamePadding(Padding e)
+{
+  const size_t index = static_cast<int>(e);
+  return EnumNamesPadding()[index];
+}
+
+enum ActivationFunctionType
+{
+  ActivationFunctionType_NONE = 0,
+  ActivationFunctionType_RELU = 1,
+  ActivationFunctionType_RELU_N1_TO_1 = 2,
+  ActivationFunctionType_RELU6 = 3,
+  ActivationFunctionType_TANH = 4,
+  ActivationFunctionType_SIGN_BIT = 5,
+  ActivationFunctionType_MIN = ActivationFunctionType_NONE,
+  ActivationFunctionType_MAX = ActivationFunctionType_SIGN_BIT
+};
+
+inline const ActivationFunctionType (&EnumValuesActivationFunctionType())[6]
+{
+  static const ActivationFunctionType values[] = {
+      ActivationFunctionType_NONE,         ActivationFunctionType_RELU,
+      ActivationFunctionType_RELU_N1_TO_1, ActivationFunctionType_RELU6,
+      ActivationFunctionType_TANH,         ActivationFunctionType_SIGN_BIT};
+  return values;
+}
+
+inline const char *const *EnumNamesActivationFunctionType()
+{
+  static const char *const names[] = {"NONE", "RELU",     "RELU_N1_TO_1", "RELU6",
+                                      "TANH", "SIGN_BIT", nullptr};
+  return names;
+}
+
+inline const char *EnumNameActivationFunctionType(ActivationFunctionType e)
+{
+  const size_t index = static_cast<int>(e);
+  return EnumNamesActivationFunctionType()[index];
+}
+
+enum LSHProjectionType
+{
+  LSHProjectionType_UNKNOWN = 0,
+  LSHProjectionType_SPARSE = 1,
+  LSHProjectionType_DENSE = 2,
+  LSHProjectionType_MIN = LSHProjectionType_UNKNOWN,
+  LSHProjectionType_MAX = LSHProjectionType_DENSE
+};
+
+inline const LSHProjectionType (&EnumValuesLSHProjectionType())[3]
+{
+  static const LSHProjectionType values[] = {LSHProjectionType_UNKNOWN, LSHProjectionType_SPARSE,
+                                             LSHProjectionType_DENSE};
+  return values;
+}
+
+inline const char *const *EnumNamesLSHProjectionType()
+{
+  static const char *const names[] = {"UNKNOWN", "SPARSE", "DENSE", nullptr};
+  return names;
+}
+
+inline const char *EnumNameLSHProjectionType(LSHProjectionType e)
+{
+  const size_t index = static_cast<int>(e);
+  return EnumNamesLSHProjectionType()[index];
+}
+
+enum FullyConnectedOptionsWeightsFormat
+{
+  FullyConnectedOptionsWeightsFormat_DEFAULT = 0,
+  FullyConnectedOptionsWeightsFormat_SHUFFLED4x16INT8 = 1,
+  FullyConnectedOptionsWeightsFormat_MIN = FullyConnectedOptionsWeightsFormat_DEFAULT,
+  FullyConnectedOptionsWeightsFormat_MAX = FullyConnectedOptionsWeightsFormat_SHUFFLED4x16INT8
+};
+
+inline const FullyConnectedOptionsWeightsFormat (&EnumValuesFullyConnectedOptionsWeightsFormat())[2]
+{
+  static const FullyConnectedOptionsWeightsFormat values[] = {
+      FullyConnectedOptionsWeightsFormat_DEFAULT,
+      FullyConnectedOptionsWeightsFormat_SHUFFLED4x16INT8};
+  return values;
+}
+
+inline const char *const *EnumNamesFullyConnectedOptionsWeightsFormat()
+{
+  static const char *const names[] = {"DEFAULT", "SHUFFLED4x16INT8", nullptr};
+  return names;
+}
+
+inline const char *EnumNameFullyConnectedOptionsWeightsFormat(FullyConnectedOptionsWeightsFormat e)
+{
+  const size_t index = static_cast<int>(e);
+  return EnumNamesFullyConnectedOptionsWeightsFormat()[index];
+}
+
+enum LSTMKernelType
+{
+  LSTMKernelType_FULL = 0,
+  LSTMKernelType_BASIC = 1,
+  LSTMKernelType_MIN = LSTMKernelType_FULL,
+  LSTMKernelType_MAX = LSTMKernelType_BASIC
+};
+
+inline const LSTMKernelType (&EnumValuesLSTMKernelType())[2]
+{
+  static const LSTMKernelType values[] = {LSTMKernelType_FULL, LSTMKernelType_BASIC};
+  return values;
+}
+
+inline const char *const *EnumNamesLSTMKernelType()
+{
+  static const char *const names[] = {"FULL", "BASIC", nullptr};
+  return names;
+}
+
+inline const char *EnumNameLSTMKernelType(LSTMKernelType e)
+{
+  const size_t index = static_cast<int>(e);
+  return EnumNamesLSTMKernelType()[index];
+}
+
+enum CombinerType
+{
+  CombinerType_SUM = 0,
+  CombinerType_MEAN = 1,
+  CombinerType_SQRTN = 2,
+  CombinerType_MIN = CombinerType_SUM,
+  CombinerType_MAX = CombinerType_SQRTN
+};
+
+inline const CombinerType (&EnumValuesCombinerType())[3]
+{
+  static const CombinerType values[] = {CombinerType_SUM, CombinerType_MEAN, CombinerType_SQRTN};
+  return values;
+}
+
+inline const char *const *EnumNamesCombinerType()
+{
+  static const char *const names[] = {"SUM", "MEAN", "SQRTN", nullptr};
+  return names;
+}
+
+inline const char *EnumNameCombinerType(CombinerType e)
+{
+  const size_t index = static_cast<int>(e);
+  return EnumNamesCombinerType()[index];
+}
+
+enum MirrorPadMode
+{
+  MirrorPadMode_REFLECT = 0,
+  MirrorPadMode_SYMMETRIC = 1,
+  MirrorPadMode_MIN = MirrorPadMode_REFLECT,
+  MirrorPadMode_MAX = MirrorPadMode_SYMMETRIC
+};
+
+inline const MirrorPadMode (&EnumValuesMirrorPadMode())[2]
+{
+  static const MirrorPadMode values[] = {MirrorPadMode_REFLECT, MirrorPadMode_SYMMETRIC};
+  return values;
+}
+
+inline const char *const *EnumNamesMirrorPadMode()
+{
+  static const char *const names[] = {"REFLECT", "SYMMETRIC", nullptr};
+  return names;
+}
+
+inline const char *EnumNameMirrorPadMode(MirrorPadMode e)
+{
+  const size_t index = static_cast<int>(e);
+  return EnumNamesMirrorPadMode()[index];
+}
+
+enum CustomOptionsFormat
+{
+  CustomOptionsFormat_FLEXBUFFERS = 0,
+  CustomOptionsFormat_MIN = CustomOptionsFormat_FLEXBUFFERS,
+  CustomOptionsFormat_MAX = CustomOptionsFormat_FLEXBUFFERS
+};
+
+inline const CustomOptionsFormat (&EnumValuesCustomOptionsFormat())[1]
+{
+  static const CustomOptionsFormat values[] = {CustomOptionsFormat_FLEXBUFFERS};
+  return values;
+}
+
+inline const char *const *EnumNamesCustomOptionsFormat()
+{
+  static const char *const names[] = {"FLEXBUFFERS", nullptr};
+  return names;
+}
+
+inline const char *EnumNameCustomOptionsFormat(CustomOptionsFormat e)
+{
+  const size_t index = static_cast<int>(e);
+  return EnumNamesCustomOptionsFormat()[index];
+}
+
+enum DataFormat
+{
+  DataFormat_CHANNELS_LAST = 0,
+  DataFormat_CHANNELS_FIRST = 1,
+  DataFormat_MIN = DataFormat_CHANNELS_LAST,
+  DataFormat_MAX = DataFormat_CHANNELS_FIRST
+};
+
+inline const DataFormat (&EnumValuesDataFormat())[2]
+{
+  static const DataFormat values[] = {DataFormat_CHANNELS_LAST, DataFormat_CHANNELS_FIRST};
+  return values;
+}
+
+inline const char *const *EnumNamesDataFormat()
+{
+  static const char *const names[] = {"CHANNELS_LAST", "CHANNELS_FIRST", nullptr};
+  return names;
+}
+
+inline const char *EnumNameDataFormat(DataFormat e)
+{
+  const size_t index = static_cast<int>(e);
+  return EnumNamesDataFormat()[index];
+}
+
+struct CustomQuantization FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_CUSTOM = 4
+  };
+  const flatbuffers::Vector<uint8_t> *custom() const
+  {
+    return GetPointer<const flatbuffers::Vector<uint8_t> *>(VT_CUSTOM);
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyOffset(verifier, VT_CUSTOM) &&
+           verifier.VerifyVector(custom()) && verifier.EndTable();
+  }
+};
+
+struct CustomQuantizationBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_custom(flatbuffers::Offset<flatbuffers::Vector<uint8_t>> custom)
+  {
+    fbb_.AddOffset(CustomQuantization::VT_CUSTOM, custom);
+  }
+  explicit CustomQuantizationBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  CustomQuantizationBuilder &operator=(const CustomQuantizationBuilder &);
+  flatbuffers::Offset<CustomQuantization> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<CustomQuantization>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<CustomQuantization>
+CreateCustomQuantization(flatbuffers::FlatBufferBuilder &_fbb,
+                         flatbuffers::Offset<flatbuffers::Vector<uint8_t>> custom = 0)
+{
+  CustomQuantizationBuilder builder_(_fbb);
+  builder_.add_custom(custom);
+  return builder_.Finish();
+}
+
+inline flatbuffers::Offset<CustomQuantization>
+CreateCustomQuantizationDirect(flatbuffers::FlatBufferBuilder &_fbb,
+                               const std::vector<uint8_t> *custom = nullptr)
+{
+  return circle::CreateCustomQuantization(_fbb, custom ? _fbb.CreateVector<uint8_t>(*custom) : 0);
+}
+
+struct QuantizationParameters FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_MIN = 4,
+    VT_MAX = 6,
+    VT_SCALE = 8,
+    VT_ZERO_POINT = 10,
+    VT_DETAILS_TYPE = 12,
+    VT_DETAILS = 14
+  };
+  const flatbuffers::Vector<float> *min() const
+  {
+    return GetPointer<const flatbuffers::Vector<float> *>(VT_MIN);
+  }
+  const flatbuffers::Vector<float> *max() const
+  {
+    return GetPointer<const flatbuffers::Vector<float> *>(VT_MAX);
+  }
+  const flatbuffers::Vector<float> *scale() const
+  {
+    return GetPointer<const flatbuffers::Vector<float> *>(VT_SCALE);
+  }
+  const flatbuffers::Vector<int64_t> *zero_point() const
+  {
+    return GetPointer<const flatbuffers::Vector<int64_t> *>(VT_ZERO_POINT);
+  }
+  QuantizationDetails details_type() const
+  {
+    return static_cast<QuantizationDetails>(GetField<uint8_t>(VT_DETAILS_TYPE, 0));
+  }
+  const void *details() const { return GetPointer<const void *>(VT_DETAILS); }
+  template <typename T> const T *details_as() const;
+  const CustomQuantization *details_as_CustomQuantization() const
+  {
+    return details_type() == QuantizationDetails_CustomQuantization
+               ? static_cast<const CustomQuantization *>(details())
+               : nullptr;
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyOffset(verifier, VT_MIN) &&
+           verifier.VerifyVector(min()) && VerifyOffset(verifier, VT_MAX) &&
+           verifier.VerifyVector(max()) && VerifyOffset(verifier, VT_SCALE) &&
+           verifier.VerifyVector(scale()) && VerifyOffset(verifier, VT_ZERO_POINT) &&
+           verifier.VerifyVector(zero_point()) && VerifyField<uint8_t>(verifier, VT_DETAILS_TYPE) &&
+           VerifyOffset(verifier, VT_DETAILS) &&
+           VerifyQuantizationDetails(verifier, details(), details_type()) && verifier.EndTable();
+  }
+};
+
+template <>
+inline const CustomQuantization *QuantizationParameters::details_as<CustomQuantization>() const
+{
+  return details_as_CustomQuantization();
+}
+
+struct QuantizationParametersBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_min(flatbuffers::Offset<flatbuffers::Vector<float>> min)
+  {
+    fbb_.AddOffset(QuantizationParameters::VT_MIN, min);
+  }
+  void add_max(flatbuffers::Offset<flatbuffers::Vector<float>> max)
+  {
+    fbb_.AddOffset(QuantizationParameters::VT_MAX, max);
+  }
+  void add_scale(flatbuffers::Offset<flatbuffers::Vector<float>> scale)
+  {
+    fbb_.AddOffset(QuantizationParameters::VT_SCALE, scale);
+  }
+  void add_zero_point(flatbuffers::Offset<flatbuffers::Vector<int64_t>> zero_point)
+  {
+    fbb_.AddOffset(QuantizationParameters::VT_ZERO_POINT, zero_point);
+  }
+  void add_details_type(QuantizationDetails details_type)
+  {
+    fbb_.AddElement<uint8_t>(QuantizationParameters::VT_DETAILS_TYPE,
+                             static_cast<uint8_t>(details_type), 0);
+  }
+  void add_details(flatbuffers::Offset<void> details)
+  {
+    fbb_.AddOffset(QuantizationParameters::VT_DETAILS, details);
+  }
+  explicit QuantizationParametersBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  QuantizationParametersBuilder &operator=(const QuantizationParametersBuilder &);
+  flatbuffers::Offset<QuantizationParameters> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<QuantizationParameters>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<QuantizationParameters>
+CreateQuantizationParameters(flatbuffers::FlatBufferBuilder &_fbb,
+                             flatbuffers::Offset<flatbuffers::Vector<float>> min = 0,
+                             flatbuffers::Offset<flatbuffers::Vector<float>> max = 0,
+                             flatbuffers::Offset<flatbuffers::Vector<float>> scale = 0,
+                             flatbuffers::Offset<flatbuffers::Vector<int64_t>> zero_point = 0,
+                             QuantizationDetails details_type = QuantizationDetails_NONE,
+                             flatbuffers::Offset<void> details = 0)
+{
+  QuantizationParametersBuilder builder_(_fbb);
+  builder_.add_details(details);
+  builder_.add_zero_point(zero_point);
+  builder_.add_scale(scale);
+  builder_.add_max(max);
+  builder_.add_min(min);
+  builder_.add_details_type(details_type);
+  return builder_.Finish();
+}
+
+inline flatbuffers::Offset<QuantizationParameters> CreateQuantizationParametersDirect(
+    flatbuffers::FlatBufferBuilder &_fbb, const std::vector<float> *min = nullptr,
+    const std::vector<float> *max = nullptr, const std::vector<float> *scale = nullptr,
+    const std::vector<int64_t> *zero_point = nullptr,
+    QuantizationDetails details_type = QuantizationDetails_NONE,
+    flatbuffers::Offset<void> details = 0)
+{
+  return circle::CreateQuantizationParameters(
+      _fbb, min ? _fbb.CreateVector<float>(*min) : 0, max ? _fbb.CreateVector<float>(*max) : 0,
+      scale ? _fbb.CreateVector<float>(*scale) : 0,
+      zero_point ? _fbb.CreateVector<int64_t>(*zero_point) : 0, details_type, details);
+}
+
+struct Tensor FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_SHAPE = 4,
+    VT_TYPE = 6,
+    VT_BUFFER = 8,
+    VT_NAME = 10,
+    VT_QUANTIZATION = 12,
+    VT_IS_VARIABLE = 14
+  };
+  const flatbuffers::Vector<int32_t> *shape() const
+  {
+    return GetPointer<const flatbuffers::Vector<int32_t> *>(VT_SHAPE);
+  }
+  TensorType type() const { return static_cast<TensorType>(GetField<int8_t>(VT_TYPE, 0)); }
+  uint32_t buffer() const { return GetField<uint32_t>(VT_BUFFER, 0); }
+  const flatbuffers::String *name() const
+  {
+    return GetPointer<const flatbuffers::String *>(VT_NAME);
+  }
+  const QuantizationParameters *quantization() const
+  {
+    return GetPointer<const QuantizationParameters *>(VT_QUANTIZATION);
+  }
+  bool is_variable() const { return GetField<uint8_t>(VT_IS_VARIABLE, 0) != 0; }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyOffset(verifier, VT_SHAPE) &&
+           verifier.VerifyVector(shape()) && VerifyField<int8_t>(verifier, VT_TYPE) &&
+           VerifyField<uint32_t>(verifier, VT_BUFFER) && VerifyOffset(verifier, VT_NAME) &&
+           verifier.VerifyString(name()) && VerifyOffset(verifier, VT_QUANTIZATION) &&
+           verifier.VerifyTable(quantization()) && VerifyField<uint8_t>(verifier, VT_IS_VARIABLE) &&
+           verifier.EndTable();
+  }
+};
+
+struct TensorBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_shape(flatbuffers::Offset<flatbuffers::Vector<int32_t>> shape)
+  {
+    fbb_.AddOffset(Tensor::VT_SHAPE, shape);
+  }
+  void add_type(TensorType type)
+  {
+    fbb_.AddElement<int8_t>(Tensor::VT_TYPE, static_cast<int8_t>(type), 0);
+  }
+  void add_buffer(uint32_t buffer) { fbb_.AddElement<uint32_t>(Tensor::VT_BUFFER, buffer, 0); }
+  void add_name(flatbuffers::Offset<flatbuffers::String> name)
+  {
+    fbb_.AddOffset(Tensor::VT_NAME, name);
+  }
+  void add_quantization(flatbuffers::Offset<QuantizationParameters> quantization)
+  {
+    fbb_.AddOffset(Tensor::VT_QUANTIZATION, quantization);
+  }
+  void add_is_variable(bool is_variable)
+  {
+    fbb_.AddElement<uint8_t>(Tensor::VT_IS_VARIABLE, static_cast<uint8_t>(is_variable), 0);
+  }
+  explicit TensorBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  TensorBuilder &operator=(const TensorBuilder &);
+  flatbuffers::Offset<Tensor> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<Tensor>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<Tensor>
+CreateTensor(flatbuffers::FlatBufferBuilder &_fbb,
+             flatbuffers::Offset<flatbuffers::Vector<int32_t>> shape = 0,
+             TensorType type = TensorType_FLOAT32, uint32_t buffer = 0,
+             flatbuffers::Offset<flatbuffers::String> name = 0,
+             flatbuffers::Offset<QuantizationParameters> quantization = 0, bool is_variable = false)
+{
+  TensorBuilder builder_(_fbb);
+  builder_.add_quantization(quantization);
+  builder_.add_name(name);
+  builder_.add_buffer(buffer);
+  builder_.add_shape(shape);
+  builder_.add_is_variable(is_variable);
+  builder_.add_type(type);
+  return builder_.Finish();
+}
+
+inline flatbuffers::Offset<Tensor> CreateTensorDirect(
+    flatbuffers::FlatBufferBuilder &_fbb, const std::vector<int32_t> *shape = nullptr,
+    TensorType type = TensorType_FLOAT32, uint32_t buffer = 0, const char *name = nullptr,
+    flatbuffers::Offset<QuantizationParameters> quantization = 0, bool is_variable = false)
+{
+  return circle::CreateTensor(_fbb, shape ? _fbb.CreateVector<int32_t>(*shape) : 0, type, buffer,
+                              name ? _fbb.CreateString(name) : 0, quantization, is_variable);
+}
+
+struct Conv2DOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_PADDING = 4,
+    VT_STRIDE_W = 6,
+    VT_STRIDE_H = 8,
+    VT_FUSED_ACTIVATION_FUNCTION = 10,
+    VT_DILATION_W_FACTOR = 12,
+    VT_DILATION_H_FACTOR = 14
+  };
+  Padding padding() const { return static_cast<Padding>(GetField<int8_t>(VT_PADDING, 0)); }
+  int32_t stride_w() const { return GetField<int32_t>(VT_STRIDE_W, 0); }
+  int32_t stride_h() const { return GetField<int32_t>(VT_STRIDE_H, 0); }
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  int32_t dilation_w_factor() const { return GetField<int32_t>(VT_DILATION_W_FACTOR, 1); }
+  int32_t dilation_h_factor() const { return GetField<int32_t>(VT_DILATION_H_FACTOR, 1); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int8_t>(verifier, VT_PADDING) &&
+           VerifyField<int32_t>(verifier, VT_STRIDE_W) &&
+           VerifyField<int32_t>(verifier, VT_STRIDE_H) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) &&
+           VerifyField<int32_t>(verifier, VT_DILATION_W_FACTOR) &&
+           VerifyField<int32_t>(verifier, VT_DILATION_H_FACTOR) && verifier.EndTable();
+  }
+};
+
+struct Conv2DOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_padding(Padding padding)
+  {
+    fbb_.AddElement<int8_t>(Conv2DOptions::VT_PADDING, static_cast<int8_t>(padding), 0);
+  }
+  void add_stride_w(int32_t stride_w)
+  {
+    fbb_.AddElement<int32_t>(Conv2DOptions::VT_STRIDE_W, stride_w, 0);
+  }
+  void add_stride_h(int32_t stride_h)
+  {
+    fbb_.AddElement<int32_t>(Conv2DOptions::VT_STRIDE_H, stride_h, 0);
+  }
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(Conv2DOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  void add_dilation_w_factor(int32_t dilation_w_factor)
+  {
+    fbb_.AddElement<int32_t>(Conv2DOptions::VT_DILATION_W_FACTOR, dilation_w_factor, 1);
+  }
+  void add_dilation_h_factor(int32_t dilation_h_factor)
+  {
+    fbb_.AddElement<int32_t>(Conv2DOptions::VT_DILATION_H_FACTOR, dilation_h_factor, 1);
+  }
+  explicit Conv2DOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  Conv2DOptionsBuilder &operator=(const Conv2DOptionsBuilder &);
+  flatbuffers::Offset<Conv2DOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<Conv2DOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<Conv2DOptions>
+CreateConv2DOptions(flatbuffers::FlatBufferBuilder &_fbb, Padding padding = Padding_SAME,
+                    int32_t stride_w = 0, int32_t stride_h = 0,
+                    ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE,
+                    int32_t dilation_w_factor = 1, int32_t dilation_h_factor = 1)
+{
+  Conv2DOptionsBuilder builder_(_fbb);
+  builder_.add_dilation_h_factor(dilation_h_factor);
+  builder_.add_dilation_w_factor(dilation_w_factor);
+  builder_.add_stride_h(stride_h);
+  builder_.add_stride_w(stride_w);
+  builder_.add_fused_activation_function(fused_activation_function);
+  builder_.add_padding(padding);
+  return builder_.Finish();
+}
+
+struct Pool2DOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_PADDING = 4,
+    VT_STRIDE_W = 6,
+    VT_STRIDE_H = 8,
+    VT_FILTER_WIDTH = 10,
+    VT_FILTER_HEIGHT = 12,
+    VT_FUSED_ACTIVATION_FUNCTION = 14
+  };
+  Padding padding() const { return static_cast<Padding>(GetField<int8_t>(VT_PADDING, 0)); }
+  int32_t stride_w() const { return GetField<int32_t>(VT_STRIDE_W, 0); }
+  int32_t stride_h() const { return GetField<int32_t>(VT_STRIDE_H, 0); }
+  int32_t filter_width() const { return GetField<int32_t>(VT_FILTER_WIDTH, 0); }
+  int32_t filter_height() const { return GetField<int32_t>(VT_FILTER_HEIGHT, 0); }
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int8_t>(verifier, VT_PADDING) &&
+           VerifyField<int32_t>(verifier, VT_STRIDE_W) &&
+           VerifyField<int32_t>(verifier, VT_STRIDE_H) &&
+           VerifyField<int32_t>(verifier, VT_FILTER_WIDTH) &&
+           VerifyField<int32_t>(verifier, VT_FILTER_HEIGHT) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) && verifier.EndTable();
+  }
+};
+
+struct Pool2DOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_padding(Padding padding)
+  {
+    fbb_.AddElement<int8_t>(Pool2DOptions::VT_PADDING, static_cast<int8_t>(padding), 0);
+  }
+  void add_stride_w(int32_t stride_w)
+  {
+    fbb_.AddElement<int32_t>(Pool2DOptions::VT_STRIDE_W, stride_w, 0);
+  }
+  void add_stride_h(int32_t stride_h)
+  {
+    fbb_.AddElement<int32_t>(Pool2DOptions::VT_STRIDE_H, stride_h, 0);
+  }
+  void add_filter_width(int32_t filter_width)
+  {
+    fbb_.AddElement<int32_t>(Pool2DOptions::VT_FILTER_WIDTH, filter_width, 0);
+  }
+  void add_filter_height(int32_t filter_height)
+  {
+    fbb_.AddElement<int32_t>(Pool2DOptions::VT_FILTER_HEIGHT, filter_height, 0);
+  }
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(Pool2DOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  explicit Pool2DOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  Pool2DOptionsBuilder &operator=(const Pool2DOptionsBuilder &);
+  flatbuffers::Offset<Pool2DOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<Pool2DOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<Pool2DOptions>
+CreatePool2DOptions(flatbuffers::FlatBufferBuilder &_fbb, Padding padding = Padding_SAME,
+                    int32_t stride_w = 0, int32_t stride_h = 0, int32_t filter_width = 0,
+                    int32_t filter_height = 0,
+                    ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE)
+{
+  Pool2DOptionsBuilder builder_(_fbb);
+  builder_.add_filter_height(filter_height);
+  builder_.add_filter_width(filter_width);
+  builder_.add_stride_h(stride_h);
+  builder_.add_stride_w(stride_w);
+  builder_.add_fused_activation_function(fused_activation_function);
+  builder_.add_padding(padding);
+  return builder_.Finish();
+}
+
+struct DepthwiseConv2DOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_PADDING = 4,
+    VT_STRIDE_W = 6,
+    VT_STRIDE_H = 8,
+    VT_DEPTH_MULTIPLIER = 10,
+    VT_FUSED_ACTIVATION_FUNCTION = 12,
+    VT_DILATION_W_FACTOR = 14,
+    VT_DILATION_H_FACTOR = 16
+  };
+  Padding padding() const { return static_cast<Padding>(GetField<int8_t>(VT_PADDING, 0)); }
+  int32_t stride_w() const { return GetField<int32_t>(VT_STRIDE_W, 0); }
+  int32_t stride_h() const { return GetField<int32_t>(VT_STRIDE_H, 0); }
+  int32_t depth_multiplier() const { return GetField<int32_t>(VT_DEPTH_MULTIPLIER, 0); }
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  int32_t dilation_w_factor() const { return GetField<int32_t>(VT_DILATION_W_FACTOR, 1); }
+  int32_t dilation_h_factor() const { return GetField<int32_t>(VT_DILATION_H_FACTOR, 1); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int8_t>(verifier, VT_PADDING) &&
+           VerifyField<int32_t>(verifier, VT_STRIDE_W) &&
+           VerifyField<int32_t>(verifier, VT_STRIDE_H) &&
+           VerifyField<int32_t>(verifier, VT_DEPTH_MULTIPLIER) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) &&
+           VerifyField<int32_t>(verifier, VT_DILATION_W_FACTOR) &&
+           VerifyField<int32_t>(verifier, VT_DILATION_H_FACTOR) && verifier.EndTable();
+  }
+};
+
+struct DepthwiseConv2DOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_padding(Padding padding)
+  {
+    fbb_.AddElement<int8_t>(DepthwiseConv2DOptions::VT_PADDING, static_cast<int8_t>(padding), 0);
+  }
+  void add_stride_w(int32_t stride_w)
+  {
+    fbb_.AddElement<int32_t>(DepthwiseConv2DOptions::VT_STRIDE_W, stride_w, 0);
+  }
+  void add_stride_h(int32_t stride_h)
+  {
+    fbb_.AddElement<int32_t>(DepthwiseConv2DOptions::VT_STRIDE_H, stride_h, 0);
+  }
+  void add_depth_multiplier(int32_t depth_multiplier)
+  {
+    fbb_.AddElement<int32_t>(DepthwiseConv2DOptions::VT_DEPTH_MULTIPLIER, depth_multiplier, 0);
+  }
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(DepthwiseConv2DOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  void add_dilation_w_factor(int32_t dilation_w_factor)
+  {
+    fbb_.AddElement<int32_t>(DepthwiseConv2DOptions::VT_DILATION_W_FACTOR, dilation_w_factor, 1);
+  }
+  void add_dilation_h_factor(int32_t dilation_h_factor)
+  {
+    fbb_.AddElement<int32_t>(DepthwiseConv2DOptions::VT_DILATION_H_FACTOR, dilation_h_factor, 1);
+  }
+  explicit DepthwiseConv2DOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  DepthwiseConv2DOptionsBuilder &operator=(const DepthwiseConv2DOptionsBuilder &);
+  flatbuffers::Offset<DepthwiseConv2DOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<DepthwiseConv2DOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<DepthwiseConv2DOptions> CreateDepthwiseConv2DOptions(
+    flatbuffers::FlatBufferBuilder &_fbb, Padding padding = Padding_SAME, int32_t stride_w = 0,
+    int32_t stride_h = 0, int32_t depth_multiplier = 0,
+    ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE,
+    int32_t dilation_w_factor = 1, int32_t dilation_h_factor = 1)
+{
+  DepthwiseConv2DOptionsBuilder builder_(_fbb);
+  builder_.add_dilation_h_factor(dilation_h_factor);
+  builder_.add_dilation_w_factor(dilation_w_factor);
+  builder_.add_depth_multiplier(depth_multiplier);
+  builder_.add_stride_h(stride_h);
+  builder_.add_stride_w(stride_w);
+  builder_.add_fused_activation_function(fused_activation_function);
+  builder_.add_padding(padding);
+  return builder_.Finish();
+}
+
+struct ConcatEmbeddingsOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_NUM_CHANNELS = 4,
+    VT_NUM_COLUMNS_PER_CHANNEL = 6,
+    VT_EMBEDDING_DIM_PER_CHANNEL = 8
+  };
+  int32_t num_channels() const { return GetField<int32_t>(VT_NUM_CHANNELS, 0); }
+  const flatbuffers::Vector<int32_t> *num_columns_per_channel() const
+  {
+    return GetPointer<const flatbuffers::Vector<int32_t> *>(VT_NUM_COLUMNS_PER_CHANNEL);
+  }
+  const flatbuffers::Vector<int32_t> *embedding_dim_per_channel() const
+  {
+    return GetPointer<const flatbuffers::Vector<int32_t> *>(VT_EMBEDDING_DIM_PER_CHANNEL);
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int32_t>(verifier, VT_NUM_CHANNELS) &&
+           VerifyOffset(verifier, VT_NUM_COLUMNS_PER_CHANNEL) &&
+           verifier.VerifyVector(num_columns_per_channel()) &&
+           VerifyOffset(verifier, VT_EMBEDDING_DIM_PER_CHANNEL) &&
+           verifier.VerifyVector(embedding_dim_per_channel()) && verifier.EndTable();
+  }
+};
+
+struct ConcatEmbeddingsOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_num_channels(int32_t num_channels)
+  {
+    fbb_.AddElement<int32_t>(ConcatEmbeddingsOptions::VT_NUM_CHANNELS, num_channels, 0);
+  }
+  void add_num_columns_per_channel(
+      flatbuffers::Offset<flatbuffers::Vector<int32_t>> num_columns_per_channel)
+  {
+    fbb_.AddOffset(ConcatEmbeddingsOptions::VT_NUM_COLUMNS_PER_CHANNEL, num_columns_per_channel);
+  }
+  void add_embedding_dim_per_channel(
+      flatbuffers::Offset<flatbuffers::Vector<int32_t>> embedding_dim_per_channel)
+  {
+    fbb_.AddOffset(ConcatEmbeddingsOptions::VT_EMBEDDING_DIM_PER_CHANNEL,
+                   embedding_dim_per_channel);
+  }
+  explicit ConcatEmbeddingsOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  ConcatEmbeddingsOptionsBuilder &operator=(const ConcatEmbeddingsOptionsBuilder &);
+  flatbuffers::Offset<ConcatEmbeddingsOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<ConcatEmbeddingsOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<ConcatEmbeddingsOptions> CreateConcatEmbeddingsOptions(
+    flatbuffers::FlatBufferBuilder &_fbb, int32_t num_channels = 0,
+    flatbuffers::Offset<flatbuffers::Vector<int32_t>> num_columns_per_channel = 0,
+    flatbuffers::Offset<flatbuffers::Vector<int32_t>> embedding_dim_per_channel = 0)
+{
+  ConcatEmbeddingsOptionsBuilder builder_(_fbb);
+  builder_.add_embedding_dim_per_channel(embedding_dim_per_channel);
+  builder_.add_num_columns_per_channel(num_columns_per_channel);
+  builder_.add_num_channels(num_channels);
+  return builder_.Finish();
+}
+
+inline flatbuffers::Offset<ConcatEmbeddingsOptions>
+CreateConcatEmbeddingsOptionsDirect(flatbuffers::FlatBufferBuilder &_fbb, int32_t num_channels = 0,
+                                    const std::vector<int32_t> *num_columns_per_channel = nullptr,
+                                    const std::vector<int32_t> *embedding_dim_per_channel = nullptr)
+{
+  return circle::CreateConcatEmbeddingsOptions(
+      _fbb, num_channels,
+      num_columns_per_channel ? _fbb.CreateVector<int32_t>(*num_columns_per_channel) : 0,
+      embedding_dim_per_channel ? _fbb.CreateVector<int32_t>(*embedding_dim_per_channel) : 0);
+}
+
+struct LSHProjectionOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_TYPE = 4
+  };
+  LSHProjectionType type() const
+  {
+    return static_cast<LSHProjectionType>(GetField<int8_t>(VT_TYPE, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int8_t>(verifier, VT_TYPE) &&
+           verifier.EndTable();
+  }
+};
+
+struct LSHProjectionOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_type(LSHProjectionType type)
+  {
+    fbb_.AddElement<int8_t>(LSHProjectionOptions::VT_TYPE, static_cast<int8_t>(type), 0);
+  }
+  explicit LSHProjectionOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  LSHProjectionOptionsBuilder &operator=(const LSHProjectionOptionsBuilder &);
+  flatbuffers::Offset<LSHProjectionOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<LSHProjectionOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<LSHProjectionOptions>
+CreateLSHProjectionOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                           LSHProjectionType type = LSHProjectionType_UNKNOWN)
+{
+  LSHProjectionOptionsBuilder builder_(_fbb);
+  builder_.add_type(type);
+  return builder_.Finish();
+}
+
+struct SVDFOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_RANK = 4,
+    VT_FUSED_ACTIVATION_FUNCTION = 6
+  };
+  int32_t rank() const { return GetField<int32_t>(VT_RANK, 0); }
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int32_t>(verifier, VT_RANK) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) && verifier.EndTable();
+  }
+};
+
+struct SVDFOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_rank(int32_t rank) { fbb_.AddElement<int32_t>(SVDFOptions::VT_RANK, rank, 0); }
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(SVDFOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  explicit SVDFOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  SVDFOptionsBuilder &operator=(const SVDFOptionsBuilder &);
+  flatbuffers::Offset<SVDFOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<SVDFOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<SVDFOptions>
+CreateSVDFOptions(flatbuffers::FlatBufferBuilder &_fbb, int32_t rank = 0,
+                  ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE)
+{
+  SVDFOptionsBuilder builder_(_fbb);
+  builder_.add_rank(rank);
+  builder_.add_fused_activation_function(fused_activation_function);
+  return builder_.Finish();
+}
+
+struct RNNOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_FUSED_ACTIVATION_FUNCTION = 4
+  };
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) && verifier.EndTable();
+  }
+};
+
+struct RNNOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(RNNOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  explicit RNNOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  RNNOptionsBuilder &operator=(const RNNOptionsBuilder &);
+  flatbuffers::Offset<RNNOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<RNNOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<RNNOptions>
+CreateRNNOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                 ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE)
+{
+  RNNOptionsBuilder builder_(_fbb);
+  builder_.add_fused_activation_function(fused_activation_function);
+  return builder_.Finish();
+}
+
+struct SequenceRNNOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_TIME_MAJOR = 4,
+    VT_FUSED_ACTIVATION_FUNCTION = 6
+  };
+  bool time_major() const { return GetField<uint8_t>(VT_TIME_MAJOR, 0) != 0; }
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<uint8_t>(verifier, VT_TIME_MAJOR) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) && verifier.EndTable();
+  }
+};
+
+struct SequenceRNNOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_time_major(bool time_major)
+  {
+    fbb_.AddElement<uint8_t>(SequenceRNNOptions::VT_TIME_MAJOR, static_cast<uint8_t>(time_major),
+                             0);
+  }
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(SequenceRNNOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  explicit SequenceRNNOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  SequenceRNNOptionsBuilder &operator=(const SequenceRNNOptionsBuilder &);
+  flatbuffers::Offset<SequenceRNNOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<SequenceRNNOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<SequenceRNNOptions> CreateSequenceRNNOptions(
+    flatbuffers::FlatBufferBuilder &_fbb, bool time_major = false,
+    ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE)
+{
+  SequenceRNNOptionsBuilder builder_(_fbb);
+  builder_.add_fused_activation_function(fused_activation_function);
+  builder_.add_time_major(time_major);
+  return builder_.Finish();
+}
+
+struct BidirectionalSequenceRNNOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_TIME_MAJOR = 4,
+    VT_FUSED_ACTIVATION_FUNCTION = 6,
+    VT_MERGE_OUTPUTS = 8
+  };
+  bool time_major() const { return GetField<uint8_t>(VT_TIME_MAJOR, 0) != 0; }
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  bool merge_outputs() const { return GetField<uint8_t>(VT_MERGE_OUTPUTS, 0) != 0; }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<uint8_t>(verifier, VT_TIME_MAJOR) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) &&
+           VerifyField<uint8_t>(verifier, VT_MERGE_OUTPUTS) && verifier.EndTable();
+  }
+};
+
+struct BidirectionalSequenceRNNOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_time_major(bool time_major)
+  {
+    fbb_.AddElement<uint8_t>(BidirectionalSequenceRNNOptions::VT_TIME_MAJOR,
+                             static_cast<uint8_t>(time_major), 0);
+  }
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(BidirectionalSequenceRNNOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  void add_merge_outputs(bool merge_outputs)
+  {
+    fbb_.AddElement<uint8_t>(BidirectionalSequenceRNNOptions::VT_MERGE_OUTPUTS,
+                             static_cast<uint8_t>(merge_outputs), 0);
+  }
+  explicit BidirectionalSequenceRNNOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  BidirectionalSequenceRNNOptionsBuilder &operator=(const BidirectionalSequenceRNNOptionsBuilder &);
+  flatbuffers::Offset<BidirectionalSequenceRNNOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<BidirectionalSequenceRNNOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<BidirectionalSequenceRNNOptions> CreateBidirectionalSequenceRNNOptions(
+    flatbuffers::FlatBufferBuilder &_fbb, bool time_major = false,
+    ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE,
+    bool merge_outputs = false)
+{
+  BidirectionalSequenceRNNOptionsBuilder builder_(_fbb);
+  builder_.add_merge_outputs(merge_outputs);
+  builder_.add_fused_activation_function(fused_activation_function);
+  builder_.add_time_major(time_major);
+  return builder_.Finish();
+}
+
+struct FullyConnectedOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_FUSED_ACTIVATION_FUNCTION = 4,
+    VT_WEIGHTS_FORMAT = 6
+  };
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  FullyConnectedOptionsWeightsFormat weights_format() const
+  {
+    return static_cast<FullyConnectedOptionsWeightsFormat>(GetField<int8_t>(VT_WEIGHTS_FORMAT, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) &&
+           VerifyField<int8_t>(verifier, VT_WEIGHTS_FORMAT) && verifier.EndTable();
+  }
+};
+
+struct FullyConnectedOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(FullyConnectedOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  void add_weights_format(FullyConnectedOptionsWeightsFormat weights_format)
+  {
+    fbb_.AddElement<int8_t>(FullyConnectedOptions::VT_WEIGHTS_FORMAT,
+                            static_cast<int8_t>(weights_format), 0);
+  }
+  explicit FullyConnectedOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  FullyConnectedOptionsBuilder &operator=(const FullyConnectedOptionsBuilder &);
+  flatbuffers::Offset<FullyConnectedOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<FullyConnectedOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<FullyConnectedOptions> CreateFullyConnectedOptions(
+    flatbuffers::FlatBufferBuilder &_fbb,
+    ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE,
+    FullyConnectedOptionsWeightsFormat weights_format = FullyConnectedOptionsWeightsFormat_DEFAULT)
+{
+  FullyConnectedOptionsBuilder builder_(_fbb);
+  builder_.add_weights_format(weights_format);
+  builder_.add_fused_activation_function(fused_activation_function);
+  return builder_.Finish();
+}
+
+struct SoftmaxOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_BETA = 4
+  };
+  float beta() const { return GetField<float>(VT_BETA, 0.0f); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<float>(verifier, VT_BETA) &&
+           verifier.EndTable();
+  }
+};
+
+struct SoftmaxOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_beta(float beta) { fbb_.AddElement<float>(SoftmaxOptions::VT_BETA, beta, 0.0f); }
+  explicit SoftmaxOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  SoftmaxOptionsBuilder &operator=(const SoftmaxOptionsBuilder &);
+  flatbuffers::Offset<SoftmaxOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<SoftmaxOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<SoftmaxOptions>
+CreateSoftmaxOptions(flatbuffers::FlatBufferBuilder &_fbb, float beta = 0.0f)
+{
+  SoftmaxOptionsBuilder builder_(_fbb);
+  builder_.add_beta(beta);
+  return builder_.Finish();
+}
+
+struct ConcatenationOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_AXIS = 4,
+    VT_FUSED_ACTIVATION_FUNCTION = 6
+  };
+  int32_t axis() const { return GetField<int32_t>(VT_AXIS, 0); }
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int32_t>(verifier, VT_AXIS) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) && verifier.EndTable();
+  }
+};
+
+struct ConcatenationOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_axis(int32_t axis) { fbb_.AddElement<int32_t>(ConcatenationOptions::VT_AXIS, axis, 0); }
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(ConcatenationOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  explicit ConcatenationOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  ConcatenationOptionsBuilder &operator=(const ConcatenationOptionsBuilder &);
+  flatbuffers::Offset<ConcatenationOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<ConcatenationOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<ConcatenationOptions> CreateConcatenationOptions(
+    flatbuffers::FlatBufferBuilder &_fbb, int32_t axis = 0,
+    ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE)
+{
+  ConcatenationOptionsBuilder builder_(_fbb);
+  builder_.add_axis(axis);
+  builder_.add_fused_activation_function(fused_activation_function);
+  return builder_.Finish();
+}
+
+struct AddOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_FUSED_ACTIVATION_FUNCTION = 4
+  };
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) && verifier.EndTable();
+  }
+};
+
+struct AddOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(AddOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  explicit AddOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  AddOptionsBuilder &operator=(const AddOptionsBuilder &);
+  flatbuffers::Offset<AddOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<AddOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<AddOptions>
+CreateAddOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                 ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE)
+{
+  AddOptionsBuilder builder_(_fbb);
+  builder_.add_fused_activation_function(fused_activation_function);
+  return builder_.Finish();
+}
+
+struct MulOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_FUSED_ACTIVATION_FUNCTION = 4
+  };
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) && verifier.EndTable();
+  }
+};
+
+struct MulOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(MulOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  explicit MulOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  MulOptionsBuilder &operator=(const MulOptionsBuilder &);
+  flatbuffers::Offset<MulOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<MulOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<MulOptions>
+CreateMulOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                 ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE)
+{
+  MulOptionsBuilder builder_(_fbb);
+  builder_.add_fused_activation_function(fused_activation_function);
+  return builder_.Finish();
+}
+
+struct L2NormOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_FUSED_ACTIVATION_FUNCTION = 4
+  };
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) && verifier.EndTable();
+  }
+};
+
+struct L2NormOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(L2NormOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  explicit L2NormOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  L2NormOptionsBuilder &operator=(const L2NormOptionsBuilder &);
+  flatbuffers::Offset<L2NormOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<L2NormOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<L2NormOptions>
+CreateL2NormOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                    ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE)
+{
+  L2NormOptionsBuilder builder_(_fbb);
+  builder_.add_fused_activation_function(fused_activation_function);
+  return builder_.Finish();
+}
+
+struct LocalResponseNormalizationOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_RADIUS = 4,
+    VT_BIAS = 6,
+    VT_ALPHA = 8,
+    VT_BETA = 10
+  };
+  int32_t radius() const { return GetField<int32_t>(VT_RADIUS, 0); }
+  float bias() const { return GetField<float>(VT_BIAS, 0.0f); }
+  float alpha() const { return GetField<float>(VT_ALPHA, 0.0f); }
+  float beta() const { return GetField<float>(VT_BETA, 0.0f); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int32_t>(verifier, VT_RADIUS) &&
+           VerifyField<float>(verifier, VT_BIAS) && VerifyField<float>(verifier, VT_ALPHA) &&
+           VerifyField<float>(verifier, VT_BETA) && verifier.EndTable();
+  }
+};
+
+struct LocalResponseNormalizationOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_radius(int32_t radius)
+  {
+    fbb_.AddElement<int32_t>(LocalResponseNormalizationOptions::VT_RADIUS, radius, 0);
+  }
+  void add_bias(float bias)
+  {
+    fbb_.AddElement<float>(LocalResponseNormalizationOptions::VT_BIAS, bias, 0.0f);
+  }
+  void add_alpha(float alpha)
+  {
+    fbb_.AddElement<float>(LocalResponseNormalizationOptions::VT_ALPHA, alpha, 0.0f);
+  }
+  void add_beta(float beta)
+  {
+    fbb_.AddElement<float>(LocalResponseNormalizationOptions::VT_BETA, beta, 0.0f);
+  }
+  explicit LocalResponseNormalizationOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb)
+      : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  LocalResponseNormalizationOptionsBuilder &
+  operator=(const LocalResponseNormalizationOptionsBuilder &);
+  flatbuffers::Offset<LocalResponseNormalizationOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<LocalResponseNormalizationOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<LocalResponseNormalizationOptions>
+CreateLocalResponseNormalizationOptions(flatbuffers::FlatBufferBuilder &_fbb, int32_t radius = 0,
+                                        float bias = 0.0f, float alpha = 0.0f, float beta = 0.0f)
+{
+  LocalResponseNormalizationOptionsBuilder builder_(_fbb);
+  builder_.add_beta(beta);
+  builder_.add_alpha(alpha);
+  builder_.add_bias(bias);
+  builder_.add_radius(radius);
+  return builder_.Finish();
+}
+
+struct LSTMOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_FUSED_ACTIVATION_FUNCTION = 4,
+    VT_CELL_CLIP = 6,
+    VT_PROJ_CLIP = 8,
+    VT_KERNEL_TYPE = 10
+  };
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  float cell_clip() const { return GetField<float>(VT_CELL_CLIP, 0.0f); }
+  float proj_clip() const { return GetField<float>(VT_PROJ_CLIP, 0.0f); }
+  LSTMKernelType kernel_type() const
+  {
+    return static_cast<LSTMKernelType>(GetField<int8_t>(VT_KERNEL_TYPE, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) &&
+           VerifyField<float>(verifier, VT_CELL_CLIP) &&
+           VerifyField<float>(verifier, VT_PROJ_CLIP) &&
+           VerifyField<int8_t>(verifier, VT_KERNEL_TYPE) && verifier.EndTable();
+  }
+};
+
+struct LSTMOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(LSTMOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  void add_cell_clip(float cell_clip)
+  {
+    fbb_.AddElement<float>(LSTMOptions::VT_CELL_CLIP, cell_clip, 0.0f);
+  }
+  void add_proj_clip(float proj_clip)
+  {
+    fbb_.AddElement<float>(LSTMOptions::VT_PROJ_CLIP, proj_clip, 0.0f);
+  }
+  void add_kernel_type(LSTMKernelType kernel_type)
+  {
+    fbb_.AddElement<int8_t>(LSTMOptions::VT_KERNEL_TYPE, static_cast<int8_t>(kernel_type), 0);
+  }
+  explicit LSTMOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  LSTMOptionsBuilder &operator=(const LSTMOptionsBuilder &);
+  flatbuffers::Offset<LSTMOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<LSTMOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<LSTMOptions>
+CreateLSTMOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                  ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE,
+                  float cell_clip = 0.0f, float proj_clip = 0.0f,
+                  LSTMKernelType kernel_type = LSTMKernelType_FULL)
+{
+  LSTMOptionsBuilder builder_(_fbb);
+  builder_.add_proj_clip(proj_clip);
+  builder_.add_cell_clip(cell_clip);
+  builder_.add_kernel_type(kernel_type);
+  builder_.add_fused_activation_function(fused_activation_function);
+  return builder_.Finish();
+}
+
+struct UnidirectionalSequenceLSTMOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_FUSED_ACTIVATION_FUNCTION = 4,
+    VT_CELL_CLIP = 6,
+    VT_PROJ_CLIP = 8,
+    VT_TIME_MAJOR = 10
+  };
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  float cell_clip() const { return GetField<float>(VT_CELL_CLIP, 0.0f); }
+  float proj_clip() const { return GetField<float>(VT_PROJ_CLIP, 0.0f); }
+  bool time_major() const { return GetField<uint8_t>(VT_TIME_MAJOR, 0) != 0; }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) &&
+           VerifyField<float>(verifier, VT_CELL_CLIP) &&
+           VerifyField<float>(verifier, VT_PROJ_CLIP) &&
+           VerifyField<uint8_t>(verifier, VT_TIME_MAJOR) && verifier.EndTable();
+  }
+};
+
+struct UnidirectionalSequenceLSTMOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(UnidirectionalSequenceLSTMOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  void add_cell_clip(float cell_clip)
+  {
+    fbb_.AddElement<float>(UnidirectionalSequenceLSTMOptions::VT_CELL_CLIP, cell_clip, 0.0f);
+  }
+  void add_proj_clip(float proj_clip)
+  {
+    fbb_.AddElement<float>(UnidirectionalSequenceLSTMOptions::VT_PROJ_CLIP, proj_clip, 0.0f);
+  }
+  void add_time_major(bool time_major)
+  {
+    fbb_.AddElement<uint8_t>(UnidirectionalSequenceLSTMOptions::VT_TIME_MAJOR,
+                             static_cast<uint8_t>(time_major), 0);
+  }
+  explicit UnidirectionalSequenceLSTMOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb)
+      : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  UnidirectionalSequenceLSTMOptionsBuilder &
+  operator=(const UnidirectionalSequenceLSTMOptionsBuilder &);
+  flatbuffers::Offset<UnidirectionalSequenceLSTMOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<UnidirectionalSequenceLSTMOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<UnidirectionalSequenceLSTMOptions>
+CreateUnidirectionalSequenceLSTMOptions(
+    flatbuffers::FlatBufferBuilder &_fbb,
+    ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE,
+    float cell_clip = 0.0f, float proj_clip = 0.0f, bool time_major = false)
+{
+  UnidirectionalSequenceLSTMOptionsBuilder builder_(_fbb);
+  builder_.add_proj_clip(proj_clip);
+  builder_.add_cell_clip(cell_clip);
+  builder_.add_time_major(time_major);
+  builder_.add_fused_activation_function(fused_activation_function);
+  return builder_.Finish();
+}
+
+struct BidirectionalSequenceLSTMOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_FUSED_ACTIVATION_FUNCTION = 4,
+    VT_CELL_CLIP = 6,
+    VT_PROJ_CLIP = 8,
+    VT_MERGE_OUTPUTS = 10
+  };
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  float cell_clip() const { return GetField<float>(VT_CELL_CLIP, 0.0f); }
+  float proj_clip() const { return GetField<float>(VT_PROJ_CLIP, 0.0f); }
+  bool merge_outputs() const { return GetField<uint8_t>(VT_MERGE_OUTPUTS, 0) != 0; }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) &&
+           VerifyField<float>(verifier, VT_CELL_CLIP) &&
+           VerifyField<float>(verifier, VT_PROJ_CLIP) &&
+           VerifyField<uint8_t>(verifier, VT_MERGE_OUTPUTS) && verifier.EndTable();
+  }
+};
+
+struct BidirectionalSequenceLSTMOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(BidirectionalSequenceLSTMOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  void add_cell_clip(float cell_clip)
+  {
+    fbb_.AddElement<float>(BidirectionalSequenceLSTMOptions::VT_CELL_CLIP, cell_clip, 0.0f);
+  }
+  void add_proj_clip(float proj_clip)
+  {
+    fbb_.AddElement<float>(BidirectionalSequenceLSTMOptions::VT_PROJ_CLIP, proj_clip, 0.0f);
+  }
+  void add_merge_outputs(bool merge_outputs)
+  {
+    fbb_.AddElement<uint8_t>(BidirectionalSequenceLSTMOptions::VT_MERGE_OUTPUTS,
+                             static_cast<uint8_t>(merge_outputs), 0);
+  }
+  explicit BidirectionalSequenceLSTMOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb)
+      : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  BidirectionalSequenceLSTMOptionsBuilder &
+  operator=(const BidirectionalSequenceLSTMOptionsBuilder &);
+  flatbuffers::Offset<BidirectionalSequenceLSTMOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<BidirectionalSequenceLSTMOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<BidirectionalSequenceLSTMOptions> CreateBidirectionalSequenceLSTMOptions(
+    flatbuffers::FlatBufferBuilder &_fbb,
+    ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE,
+    float cell_clip = 0.0f, float proj_clip = 0.0f, bool merge_outputs = false)
+{
+  BidirectionalSequenceLSTMOptionsBuilder builder_(_fbb);
+  builder_.add_proj_clip(proj_clip);
+  builder_.add_cell_clip(cell_clip);
+  builder_.add_merge_outputs(merge_outputs);
+  builder_.add_fused_activation_function(fused_activation_function);
+  return builder_.Finish();
+}
+
+struct ResizeBilinearOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_ALIGN_CORNERS = 8
+  };
+  bool align_corners() const { return GetField<uint8_t>(VT_ALIGN_CORNERS, 0) != 0; }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<uint8_t>(verifier, VT_ALIGN_CORNERS) &&
+           verifier.EndTable();
+  }
+};
+
+struct ResizeBilinearOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_align_corners(bool align_corners)
+  {
+    fbb_.AddElement<uint8_t>(ResizeBilinearOptions::VT_ALIGN_CORNERS,
+                             static_cast<uint8_t>(align_corners), 0);
+  }
+  explicit ResizeBilinearOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  ResizeBilinearOptionsBuilder &operator=(const ResizeBilinearOptionsBuilder &);
+  flatbuffers::Offset<ResizeBilinearOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<ResizeBilinearOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<ResizeBilinearOptions>
+CreateResizeBilinearOptions(flatbuffers::FlatBufferBuilder &_fbb, bool align_corners = false)
+{
+  ResizeBilinearOptionsBuilder builder_(_fbb);
+  builder_.add_align_corners(align_corners);
+  return builder_.Finish();
+}
+
+struct ResizeNearestNeighborOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_ALIGN_CORNERS = 4
+  };
+  bool align_corners() const { return GetField<uint8_t>(VT_ALIGN_CORNERS, 0) != 0; }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<uint8_t>(verifier, VT_ALIGN_CORNERS) &&
+           verifier.EndTable();
+  }
+};
+
+struct ResizeNearestNeighborOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_align_corners(bool align_corners)
+  {
+    fbb_.AddElement<uint8_t>(ResizeNearestNeighborOptions::VT_ALIGN_CORNERS,
+                             static_cast<uint8_t>(align_corners), 0);
+  }
+  explicit ResizeNearestNeighborOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  ResizeNearestNeighborOptionsBuilder &operator=(const ResizeNearestNeighborOptionsBuilder &);
+  flatbuffers::Offset<ResizeNearestNeighborOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<ResizeNearestNeighborOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<ResizeNearestNeighborOptions>
+CreateResizeNearestNeighborOptions(flatbuffers::FlatBufferBuilder &_fbb, bool align_corners = false)
+{
+  ResizeNearestNeighborOptionsBuilder builder_(_fbb);
+  builder_.add_align_corners(align_corners);
+  return builder_.Finish();
+}
+
+struct CallOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_SUBGRAPH = 4
+  };
+  uint32_t subgraph() const { return GetField<uint32_t>(VT_SUBGRAPH, 0); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<uint32_t>(verifier, VT_SUBGRAPH) &&
+           verifier.EndTable();
+  }
+};
+
+struct CallOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_subgraph(uint32_t subgraph)
+  {
+    fbb_.AddElement<uint32_t>(CallOptions::VT_SUBGRAPH, subgraph, 0);
+  }
+  explicit CallOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  CallOptionsBuilder &operator=(const CallOptionsBuilder &);
+  flatbuffers::Offset<CallOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<CallOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<CallOptions> CreateCallOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                                                          uint32_t subgraph = 0)
+{
+  CallOptionsBuilder builder_(_fbb);
+  builder_.add_subgraph(subgraph);
+  return builder_.Finish();
+}
+
+struct PadOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct PadOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit PadOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  PadOptionsBuilder &operator=(const PadOptionsBuilder &);
+  flatbuffers::Offset<PadOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<PadOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<PadOptions> CreatePadOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  PadOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct PadV2Options FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct PadV2OptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit PadV2OptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  PadV2OptionsBuilder &operator=(const PadV2OptionsBuilder &);
+  flatbuffers::Offset<PadV2Options> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<PadV2Options>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<PadV2Options> CreatePadV2Options(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  PadV2OptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct ReshapeOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_NEW_SHAPE = 4
+  };
+  const flatbuffers::Vector<int32_t> *new_shape() const
+  {
+    return GetPointer<const flatbuffers::Vector<int32_t> *>(VT_NEW_SHAPE);
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyOffset(verifier, VT_NEW_SHAPE) &&
+           verifier.VerifyVector(new_shape()) && verifier.EndTable();
+  }
+};
+
+struct ReshapeOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_new_shape(flatbuffers::Offset<flatbuffers::Vector<int32_t>> new_shape)
+  {
+    fbb_.AddOffset(ReshapeOptions::VT_NEW_SHAPE, new_shape);
+  }
+  explicit ReshapeOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  ReshapeOptionsBuilder &operator=(const ReshapeOptionsBuilder &);
+  flatbuffers::Offset<ReshapeOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<ReshapeOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<ReshapeOptions>
+CreateReshapeOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                     flatbuffers::Offset<flatbuffers::Vector<int32_t>> new_shape = 0)
+{
+  ReshapeOptionsBuilder builder_(_fbb);
+  builder_.add_new_shape(new_shape);
+  return builder_.Finish();
+}
+
+inline flatbuffers::Offset<ReshapeOptions>
+CreateReshapeOptionsDirect(flatbuffers::FlatBufferBuilder &_fbb,
+                           const std::vector<int32_t> *new_shape = nullptr)
+{
+  return circle::CreateReshapeOptions(_fbb, new_shape ? _fbb.CreateVector<int32_t>(*new_shape) : 0);
+}
+
+struct SpaceToBatchNDOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct SpaceToBatchNDOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit SpaceToBatchNDOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  SpaceToBatchNDOptionsBuilder &operator=(const SpaceToBatchNDOptionsBuilder &);
+  flatbuffers::Offset<SpaceToBatchNDOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<SpaceToBatchNDOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<SpaceToBatchNDOptions>
+CreateSpaceToBatchNDOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  SpaceToBatchNDOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct BatchToSpaceNDOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct BatchToSpaceNDOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit BatchToSpaceNDOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  BatchToSpaceNDOptionsBuilder &operator=(const BatchToSpaceNDOptionsBuilder &);
+  flatbuffers::Offset<BatchToSpaceNDOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<BatchToSpaceNDOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<BatchToSpaceNDOptions>
+CreateBatchToSpaceNDOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  BatchToSpaceNDOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct SkipGramOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_NGRAM_SIZE = 4,
+    VT_MAX_SKIP_SIZE = 6,
+    VT_INCLUDE_ALL_NGRAMS = 8
+  };
+  int32_t ngram_size() const { return GetField<int32_t>(VT_NGRAM_SIZE, 0); }
+  int32_t max_skip_size() const { return GetField<int32_t>(VT_MAX_SKIP_SIZE, 0); }
+  bool include_all_ngrams() const { return GetField<uint8_t>(VT_INCLUDE_ALL_NGRAMS, 0) != 0; }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int32_t>(verifier, VT_NGRAM_SIZE) &&
+           VerifyField<int32_t>(verifier, VT_MAX_SKIP_SIZE) &&
+           VerifyField<uint8_t>(verifier, VT_INCLUDE_ALL_NGRAMS) && verifier.EndTable();
+  }
+};
+
+struct SkipGramOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_ngram_size(int32_t ngram_size)
+  {
+    fbb_.AddElement<int32_t>(SkipGramOptions::VT_NGRAM_SIZE, ngram_size, 0);
+  }
+  void add_max_skip_size(int32_t max_skip_size)
+  {
+    fbb_.AddElement<int32_t>(SkipGramOptions::VT_MAX_SKIP_SIZE, max_skip_size, 0);
+  }
+  void add_include_all_ngrams(bool include_all_ngrams)
+  {
+    fbb_.AddElement<uint8_t>(SkipGramOptions::VT_INCLUDE_ALL_NGRAMS,
+                             static_cast<uint8_t>(include_all_ngrams), 0);
+  }
+  explicit SkipGramOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  SkipGramOptionsBuilder &operator=(const SkipGramOptionsBuilder &);
+  flatbuffers::Offset<SkipGramOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<SkipGramOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<SkipGramOptions>
+CreateSkipGramOptions(flatbuffers::FlatBufferBuilder &_fbb, int32_t ngram_size = 0,
+                      int32_t max_skip_size = 0, bool include_all_ngrams = false)
+{
+  SkipGramOptionsBuilder builder_(_fbb);
+  builder_.add_max_skip_size(max_skip_size);
+  builder_.add_ngram_size(ngram_size);
+  builder_.add_include_all_ngrams(include_all_ngrams);
+  return builder_.Finish();
+}
+
+struct SpaceToDepthOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_BLOCK_SIZE = 4
+  };
+  int32_t block_size() const { return GetField<int32_t>(VT_BLOCK_SIZE, 0); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int32_t>(verifier, VT_BLOCK_SIZE) &&
+           verifier.EndTable();
+  }
+};
+
+struct SpaceToDepthOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_block_size(int32_t block_size)
+  {
+    fbb_.AddElement<int32_t>(SpaceToDepthOptions::VT_BLOCK_SIZE, block_size, 0);
+  }
+  explicit SpaceToDepthOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  SpaceToDepthOptionsBuilder &operator=(const SpaceToDepthOptionsBuilder &);
+  flatbuffers::Offset<SpaceToDepthOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<SpaceToDepthOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<SpaceToDepthOptions>
+CreateSpaceToDepthOptions(flatbuffers::FlatBufferBuilder &_fbb, int32_t block_size = 0)
+{
+  SpaceToDepthOptionsBuilder builder_(_fbb);
+  builder_.add_block_size(block_size);
+  return builder_.Finish();
+}
+
+struct SubOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_FUSED_ACTIVATION_FUNCTION = 4
+  };
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) && verifier.EndTable();
+  }
+};
+
+struct SubOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(SubOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  explicit SubOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  SubOptionsBuilder &operator=(const SubOptionsBuilder &);
+  flatbuffers::Offset<SubOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<SubOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<SubOptions>
+CreateSubOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                 ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE)
+{
+  SubOptionsBuilder builder_(_fbb);
+  builder_.add_fused_activation_function(fused_activation_function);
+  return builder_.Finish();
+}
+
+struct DivOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_FUSED_ACTIVATION_FUNCTION = 4
+  };
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) && verifier.EndTable();
+  }
+};
+
+struct DivOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(DivOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  explicit DivOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  DivOptionsBuilder &operator=(const DivOptionsBuilder &);
+  flatbuffers::Offset<DivOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<DivOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<DivOptions>
+CreateDivOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                 ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE)
+{
+  DivOptionsBuilder builder_(_fbb);
+  builder_.add_fused_activation_function(fused_activation_function);
+  return builder_.Finish();
+}
+
+struct TopKV2Options FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct TopKV2OptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit TopKV2OptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  TopKV2OptionsBuilder &operator=(const TopKV2OptionsBuilder &);
+  flatbuffers::Offset<TopKV2Options> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<TopKV2Options>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<TopKV2Options> CreateTopKV2Options(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  TopKV2OptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct EmbeddingLookupSparseOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_COMBINER = 4
+  };
+  CombinerType combiner() const
+  {
+    return static_cast<CombinerType>(GetField<int8_t>(VT_COMBINER, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int8_t>(verifier, VT_COMBINER) &&
+           verifier.EndTable();
+  }
+};
+
+struct EmbeddingLookupSparseOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_combiner(CombinerType combiner)
+  {
+    fbb_.AddElement<int8_t>(EmbeddingLookupSparseOptions::VT_COMBINER,
+                            static_cast<int8_t>(combiner), 0);
+  }
+  explicit EmbeddingLookupSparseOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  EmbeddingLookupSparseOptionsBuilder &operator=(const EmbeddingLookupSparseOptionsBuilder &);
+  flatbuffers::Offset<EmbeddingLookupSparseOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<EmbeddingLookupSparseOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<EmbeddingLookupSparseOptions>
+CreateEmbeddingLookupSparseOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                                   CombinerType combiner = CombinerType_SUM)
+{
+  EmbeddingLookupSparseOptionsBuilder builder_(_fbb);
+  builder_.add_combiner(combiner);
+  return builder_.Finish();
+}
+
+struct GatherOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_AXIS = 4
+  };
+  int32_t axis() const { return GetField<int32_t>(VT_AXIS, 0); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int32_t>(verifier, VT_AXIS) &&
+           verifier.EndTable();
+  }
+};
+
+struct GatherOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_axis(int32_t axis) { fbb_.AddElement<int32_t>(GatherOptions::VT_AXIS, axis, 0); }
+  explicit GatherOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  GatherOptionsBuilder &operator=(const GatherOptionsBuilder &);
+  flatbuffers::Offset<GatherOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<GatherOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<GatherOptions> CreateGatherOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                                                              int32_t axis = 0)
+{
+  GatherOptionsBuilder builder_(_fbb);
+  builder_.add_axis(axis);
+  return builder_.Finish();
+}
+
+struct TransposeOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct TransposeOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit TransposeOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  TransposeOptionsBuilder &operator=(const TransposeOptionsBuilder &);
+  flatbuffers::Offset<TransposeOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<TransposeOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<TransposeOptions>
+CreateTransposeOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  TransposeOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct ExpOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct ExpOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit ExpOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  ExpOptionsBuilder &operator=(const ExpOptionsBuilder &);
+  flatbuffers::Offset<ExpOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<ExpOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<ExpOptions> CreateExpOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  ExpOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct ReducerOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_KEEP_DIMS = 4
+  };
+  bool keep_dims() const { return GetField<uint8_t>(VT_KEEP_DIMS, 0) != 0; }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<uint8_t>(verifier, VT_KEEP_DIMS) &&
+           verifier.EndTable();
+  }
+};
+
+struct ReducerOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_keep_dims(bool keep_dims)
+  {
+    fbb_.AddElement<uint8_t>(ReducerOptions::VT_KEEP_DIMS, static_cast<uint8_t>(keep_dims), 0);
+  }
+  explicit ReducerOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  ReducerOptionsBuilder &operator=(const ReducerOptionsBuilder &);
+  flatbuffers::Offset<ReducerOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<ReducerOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<ReducerOptions>
+CreateReducerOptions(flatbuffers::FlatBufferBuilder &_fbb, bool keep_dims = false)
+{
+  ReducerOptionsBuilder builder_(_fbb);
+  builder_.add_keep_dims(keep_dims);
+  return builder_.Finish();
+}
+
+struct SqueezeOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_SQUEEZE_DIMS = 4
+  };
+  const flatbuffers::Vector<int32_t> *squeeze_dims() const
+  {
+    return GetPointer<const flatbuffers::Vector<int32_t> *>(VT_SQUEEZE_DIMS);
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyOffset(verifier, VT_SQUEEZE_DIMS) &&
+           verifier.VerifyVector(squeeze_dims()) && verifier.EndTable();
+  }
+};
+
+struct SqueezeOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_squeeze_dims(flatbuffers::Offset<flatbuffers::Vector<int32_t>> squeeze_dims)
+  {
+    fbb_.AddOffset(SqueezeOptions::VT_SQUEEZE_DIMS, squeeze_dims);
+  }
+  explicit SqueezeOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  SqueezeOptionsBuilder &operator=(const SqueezeOptionsBuilder &);
+  flatbuffers::Offset<SqueezeOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<SqueezeOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<SqueezeOptions>
+CreateSqueezeOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                     flatbuffers::Offset<flatbuffers::Vector<int32_t>> squeeze_dims = 0)
+{
+  SqueezeOptionsBuilder builder_(_fbb);
+  builder_.add_squeeze_dims(squeeze_dims);
+  return builder_.Finish();
+}
+
+inline flatbuffers::Offset<SqueezeOptions>
+CreateSqueezeOptionsDirect(flatbuffers::FlatBufferBuilder &_fbb,
+                           const std::vector<int32_t> *squeeze_dims = nullptr)
+{
+  return circle::CreateSqueezeOptions(_fbb,
+                                      squeeze_dims ? _fbb.CreateVector<int32_t>(*squeeze_dims) : 0);
+}
+
+struct SplitOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_NUM_SPLITS = 4
+  };
+  int32_t num_splits() const { return GetField<int32_t>(VT_NUM_SPLITS, 0); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int32_t>(verifier, VT_NUM_SPLITS) &&
+           verifier.EndTable();
+  }
+};
+
+struct SplitOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_num_splits(int32_t num_splits)
+  {
+    fbb_.AddElement<int32_t>(SplitOptions::VT_NUM_SPLITS, num_splits, 0);
+  }
+  explicit SplitOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  SplitOptionsBuilder &operator=(const SplitOptionsBuilder &);
+  flatbuffers::Offset<SplitOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<SplitOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<SplitOptions> CreateSplitOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                                                            int32_t num_splits = 0)
+{
+  SplitOptionsBuilder builder_(_fbb);
+  builder_.add_num_splits(num_splits);
+  return builder_.Finish();
+}
+
+struct SplitVOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_NUM_SPLITS = 4
+  };
+  int32_t num_splits() const { return GetField<int32_t>(VT_NUM_SPLITS, 0); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int32_t>(verifier, VT_NUM_SPLITS) &&
+           verifier.EndTable();
+  }
+};
+
+struct SplitVOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_num_splits(int32_t num_splits)
+  {
+    fbb_.AddElement<int32_t>(SplitVOptions::VT_NUM_SPLITS, num_splits, 0);
+  }
+  explicit SplitVOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  SplitVOptionsBuilder &operator=(const SplitVOptionsBuilder &);
+  flatbuffers::Offset<SplitVOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<SplitVOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<SplitVOptions> CreateSplitVOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                                                              int32_t num_splits = 0)
+{
+  SplitVOptionsBuilder builder_(_fbb);
+  builder_.add_num_splits(num_splits);
+  return builder_.Finish();
+}
+
+struct StridedSliceOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_BEGIN_MASK = 4,
+    VT_END_MASK = 6,
+    VT_ELLIPSIS_MASK = 8,
+    VT_NEW_AXIS_MASK = 10,
+    VT_SHRINK_AXIS_MASK = 12
+  };
+  int32_t begin_mask() const { return GetField<int32_t>(VT_BEGIN_MASK, 0); }
+  int32_t end_mask() const { return GetField<int32_t>(VT_END_MASK, 0); }
+  int32_t ellipsis_mask() const { return GetField<int32_t>(VT_ELLIPSIS_MASK, 0); }
+  int32_t new_axis_mask() const { return GetField<int32_t>(VT_NEW_AXIS_MASK, 0); }
+  int32_t shrink_axis_mask() const { return GetField<int32_t>(VT_SHRINK_AXIS_MASK, 0); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int32_t>(verifier, VT_BEGIN_MASK) &&
+           VerifyField<int32_t>(verifier, VT_END_MASK) &&
+           VerifyField<int32_t>(verifier, VT_ELLIPSIS_MASK) &&
+           VerifyField<int32_t>(verifier, VT_NEW_AXIS_MASK) &&
+           VerifyField<int32_t>(verifier, VT_SHRINK_AXIS_MASK) && verifier.EndTable();
+  }
+};
+
+struct StridedSliceOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_begin_mask(int32_t begin_mask)
+  {
+    fbb_.AddElement<int32_t>(StridedSliceOptions::VT_BEGIN_MASK, begin_mask, 0);
+  }
+  void add_end_mask(int32_t end_mask)
+  {
+    fbb_.AddElement<int32_t>(StridedSliceOptions::VT_END_MASK, end_mask, 0);
+  }
+  void add_ellipsis_mask(int32_t ellipsis_mask)
+  {
+    fbb_.AddElement<int32_t>(StridedSliceOptions::VT_ELLIPSIS_MASK, ellipsis_mask, 0);
+  }
+  void add_new_axis_mask(int32_t new_axis_mask)
+  {
+    fbb_.AddElement<int32_t>(StridedSliceOptions::VT_NEW_AXIS_MASK, new_axis_mask, 0);
+  }
+  void add_shrink_axis_mask(int32_t shrink_axis_mask)
+  {
+    fbb_.AddElement<int32_t>(StridedSliceOptions::VT_SHRINK_AXIS_MASK, shrink_axis_mask, 0);
+  }
+  explicit StridedSliceOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  StridedSliceOptionsBuilder &operator=(const StridedSliceOptionsBuilder &);
+  flatbuffers::Offset<StridedSliceOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<StridedSliceOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<StridedSliceOptions>
+CreateStridedSliceOptions(flatbuffers::FlatBufferBuilder &_fbb, int32_t begin_mask = 0,
+                          int32_t end_mask = 0, int32_t ellipsis_mask = 0,
+                          int32_t new_axis_mask = 0, int32_t shrink_axis_mask = 0)
+{
+  StridedSliceOptionsBuilder builder_(_fbb);
+  builder_.add_shrink_axis_mask(shrink_axis_mask);
+  builder_.add_new_axis_mask(new_axis_mask);
+  builder_.add_ellipsis_mask(ellipsis_mask);
+  builder_.add_end_mask(end_mask);
+  builder_.add_begin_mask(begin_mask);
+  return builder_.Finish();
+}
+
+struct LogSoftmaxOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct LogSoftmaxOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit LogSoftmaxOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  LogSoftmaxOptionsBuilder &operator=(const LogSoftmaxOptionsBuilder &);
+  flatbuffers::Offset<LogSoftmaxOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<LogSoftmaxOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<LogSoftmaxOptions>
+CreateLogSoftmaxOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  LogSoftmaxOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct CastOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_IN_DATA_TYPE = 4,
+    VT_OUT_DATA_TYPE = 6
+  };
+  TensorType in_data_type() const
+  {
+    return static_cast<TensorType>(GetField<int8_t>(VT_IN_DATA_TYPE, 0));
+  }
+  TensorType out_data_type() const
+  {
+    return static_cast<TensorType>(GetField<int8_t>(VT_OUT_DATA_TYPE, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int8_t>(verifier, VT_IN_DATA_TYPE) &&
+           VerifyField<int8_t>(verifier, VT_OUT_DATA_TYPE) && verifier.EndTable();
+  }
+};
+
+struct CastOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_in_data_type(TensorType in_data_type)
+  {
+    fbb_.AddElement<int8_t>(CastOptions::VT_IN_DATA_TYPE, static_cast<int8_t>(in_data_type), 0);
+  }
+  void add_out_data_type(TensorType out_data_type)
+  {
+    fbb_.AddElement<int8_t>(CastOptions::VT_OUT_DATA_TYPE, static_cast<int8_t>(out_data_type), 0);
+  }
+  explicit CastOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  CastOptionsBuilder &operator=(const CastOptionsBuilder &);
+  flatbuffers::Offset<CastOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<CastOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<CastOptions>
+CreateCastOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                  TensorType in_data_type = TensorType_FLOAT32,
+                  TensorType out_data_type = TensorType_FLOAT32)
+{
+  CastOptionsBuilder builder_(_fbb);
+  builder_.add_out_data_type(out_data_type);
+  builder_.add_in_data_type(in_data_type);
+  return builder_.Finish();
+}
+
+struct DequantizeOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct DequantizeOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit DequantizeOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  DequantizeOptionsBuilder &operator=(const DequantizeOptionsBuilder &);
+  flatbuffers::Offset<DequantizeOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<DequantizeOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<DequantizeOptions>
+CreateDequantizeOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  DequantizeOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct MaximumMinimumOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct MaximumMinimumOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit MaximumMinimumOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  MaximumMinimumOptionsBuilder &operator=(const MaximumMinimumOptionsBuilder &);
+  flatbuffers::Offset<MaximumMinimumOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<MaximumMinimumOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<MaximumMinimumOptions>
+CreateMaximumMinimumOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  MaximumMinimumOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct TileOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct TileOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit TileOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  TileOptionsBuilder &operator=(const TileOptionsBuilder &);
+  flatbuffers::Offset<TileOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<TileOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<TileOptions> CreateTileOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  TileOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct ArgMaxOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_OUTPUT_TYPE = 4
+  };
+  TensorType output_type() const
+  {
+    return static_cast<TensorType>(GetField<int8_t>(VT_OUTPUT_TYPE, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int8_t>(verifier, VT_OUTPUT_TYPE) &&
+           verifier.EndTable();
+  }
+};
+
+struct ArgMaxOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_output_type(TensorType output_type)
+  {
+    fbb_.AddElement<int8_t>(ArgMaxOptions::VT_OUTPUT_TYPE, static_cast<int8_t>(output_type), 0);
+  }
+  explicit ArgMaxOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  ArgMaxOptionsBuilder &operator=(const ArgMaxOptionsBuilder &);
+  flatbuffers::Offset<ArgMaxOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<ArgMaxOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<ArgMaxOptions>
+CreateArgMaxOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                    TensorType output_type = TensorType_FLOAT32)
+{
+  ArgMaxOptionsBuilder builder_(_fbb);
+  builder_.add_output_type(output_type);
+  return builder_.Finish();
+}
+
+struct ArgMinOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_OUTPUT_TYPE = 4
+  };
+  TensorType output_type() const
+  {
+    return static_cast<TensorType>(GetField<int8_t>(VT_OUTPUT_TYPE, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int8_t>(verifier, VT_OUTPUT_TYPE) &&
+           verifier.EndTable();
+  }
+};
+
+struct ArgMinOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_output_type(TensorType output_type)
+  {
+    fbb_.AddElement<int8_t>(ArgMinOptions::VT_OUTPUT_TYPE, static_cast<int8_t>(output_type), 0);
+  }
+  explicit ArgMinOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  ArgMinOptionsBuilder &operator=(const ArgMinOptionsBuilder &);
+  flatbuffers::Offset<ArgMinOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<ArgMinOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<ArgMinOptions>
+CreateArgMinOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                    TensorType output_type = TensorType_FLOAT32)
+{
+  ArgMinOptionsBuilder builder_(_fbb);
+  builder_.add_output_type(output_type);
+  return builder_.Finish();
+}
+
+struct GreaterOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct GreaterOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit GreaterOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  GreaterOptionsBuilder &operator=(const GreaterOptionsBuilder &);
+  flatbuffers::Offset<GreaterOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<GreaterOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<GreaterOptions>
+CreateGreaterOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  GreaterOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct GreaterEqualOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct GreaterEqualOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit GreaterEqualOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  GreaterEqualOptionsBuilder &operator=(const GreaterEqualOptionsBuilder &);
+  flatbuffers::Offset<GreaterEqualOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<GreaterEqualOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<GreaterEqualOptions>
+CreateGreaterEqualOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  GreaterEqualOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct LessOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct LessOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit LessOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  LessOptionsBuilder &operator=(const LessOptionsBuilder &);
+  flatbuffers::Offset<LessOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<LessOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<LessOptions> CreateLessOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  LessOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct LessEqualOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct LessEqualOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit LessEqualOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  LessEqualOptionsBuilder &operator=(const LessEqualOptionsBuilder &);
+  flatbuffers::Offset<LessEqualOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<LessEqualOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<LessEqualOptions>
+CreateLessEqualOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  LessEqualOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct NegOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct NegOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit NegOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  NegOptionsBuilder &operator=(const NegOptionsBuilder &);
+  flatbuffers::Offset<NegOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<NegOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<NegOptions> CreateNegOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  NegOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct SelectOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct SelectOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit SelectOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  SelectOptionsBuilder &operator=(const SelectOptionsBuilder &);
+  flatbuffers::Offset<SelectOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<SelectOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<SelectOptions> CreateSelectOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  SelectOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct SliceOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct SliceOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit SliceOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  SliceOptionsBuilder &operator=(const SliceOptionsBuilder &);
+  flatbuffers::Offset<SliceOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<SliceOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<SliceOptions> CreateSliceOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  SliceOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct TransposeConvOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_PADDING = 4,
+    VT_STRIDE_W = 6,
+    VT_STRIDE_H = 8
+  };
+  Padding padding() const { return static_cast<Padding>(GetField<int8_t>(VT_PADDING, 0)); }
+  int32_t stride_w() const { return GetField<int32_t>(VT_STRIDE_W, 0); }
+  int32_t stride_h() const { return GetField<int32_t>(VT_STRIDE_H, 0); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int8_t>(verifier, VT_PADDING) &&
+           VerifyField<int32_t>(verifier, VT_STRIDE_W) &&
+           VerifyField<int32_t>(verifier, VT_STRIDE_H) && verifier.EndTable();
+  }
+};
+
+struct TransposeConvOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_padding(Padding padding)
+  {
+    fbb_.AddElement<int8_t>(TransposeConvOptions::VT_PADDING, static_cast<int8_t>(padding), 0);
+  }
+  void add_stride_w(int32_t stride_w)
+  {
+    fbb_.AddElement<int32_t>(TransposeConvOptions::VT_STRIDE_W, stride_w, 0);
+  }
+  void add_stride_h(int32_t stride_h)
+  {
+    fbb_.AddElement<int32_t>(TransposeConvOptions::VT_STRIDE_H, stride_h, 0);
+  }
+  explicit TransposeConvOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  TransposeConvOptionsBuilder &operator=(const TransposeConvOptionsBuilder &);
+  flatbuffers::Offset<TransposeConvOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<TransposeConvOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<TransposeConvOptions>
+CreateTransposeConvOptions(flatbuffers::FlatBufferBuilder &_fbb, Padding padding = Padding_SAME,
+                           int32_t stride_w = 0, int32_t stride_h = 0)
+{
+  TransposeConvOptionsBuilder builder_(_fbb);
+  builder_.add_stride_h(stride_h);
+  builder_.add_stride_w(stride_w);
+  builder_.add_padding(padding);
+  return builder_.Finish();
+}
+
+struct ExpandDimsOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct ExpandDimsOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit ExpandDimsOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  ExpandDimsOptionsBuilder &operator=(const ExpandDimsOptionsBuilder &);
+  flatbuffers::Offset<ExpandDimsOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<ExpandDimsOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<ExpandDimsOptions>
+CreateExpandDimsOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  ExpandDimsOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct SparseToDenseOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_VALIDATE_INDICES = 4
+  };
+  bool validate_indices() const { return GetField<uint8_t>(VT_VALIDATE_INDICES, 0) != 0; }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<uint8_t>(verifier, VT_VALIDATE_INDICES) &&
+           verifier.EndTable();
+  }
+};
+
+struct SparseToDenseOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_validate_indices(bool validate_indices)
+  {
+    fbb_.AddElement<uint8_t>(SparseToDenseOptions::VT_VALIDATE_INDICES,
+                             static_cast<uint8_t>(validate_indices), 0);
+  }
+  explicit SparseToDenseOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  SparseToDenseOptionsBuilder &operator=(const SparseToDenseOptionsBuilder &);
+  flatbuffers::Offset<SparseToDenseOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<SparseToDenseOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<SparseToDenseOptions>
+CreateSparseToDenseOptions(flatbuffers::FlatBufferBuilder &_fbb, bool validate_indices = false)
+{
+  SparseToDenseOptionsBuilder builder_(_fbb);
+  builder_.add_validate_indices(validate_indices);
+  return builder_.Finish();
+}
+
+struct EqualOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct EqualOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit EqualOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  EqualOptionsBuilder &operator=(const EqualOptionsBuilder &);
+  flatbuffers::Offset<EqualOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<EqualOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<EqualOptions> CreateEqualOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  EqualOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct NotEqualOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct NotEqualOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit NotEqualOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  NotEqualOptionsBuilder &operator=(const NotEqualOptionsBuilder &);
+  flatbuffers::Offset<NotEqualOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<NotEqualOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<NotEqualOptions>
+CreateNotEqualOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  NotEqualOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct ShapeOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_OUT_TYPE = 4
+  };
+  TensorType out_type() const { return static_cast<TensorType>(GetField<int8_t>(VT_OUT_TYPE, 0)); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int8_t>(verifier, VT_OUT_TYPE) &&
+           verifier.EndTable();
+  }
+};
+
+struct ShapeOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_out_type(TensorType out_type)
+  {
+    fbb_.AddElement<int8_t>(ShapeOptions::VT_OUT_TYPE, static_cast<int8_t>(out_type), 0);
+  }
+  explicit ShapeOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  ShapeOptionsBuilder &operator=(const ShapeOptionsBuilder &);
+  flatbuffers::Offset<ShapeOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<ShapeOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<ShapeOptions>
+CreateShapeOptions(flatbuffers::FlatBufferBuilder &_fbb, TensorType out_type = TensorType_FLOAT32)
+{
+  ShapeOptionsBuilder builder_(_fbb);
+  builder_.add_out_type(out_type);
+  return builder_.Finish();
+}
+
+struct PowOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct PowOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit PowOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  PowOptionsBuilder &operator=(const PowOptionsBuilder &);
+  flatbuffers::Offset<PowOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<PowOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<PowOptions> CreatePowOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  PowOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct FakeQuantOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_MIN = 4,
+    VT_MAX = 6,
+    VT_NUM_BITS = 8,
+    VT_NARROW_RANGE = 10
+  };
+  float min() const { return GetField<float>(VT_MIN, 0.0f); }
+  float max() const { return GetField<float>(VT_MAX, 0.0f); }
+  int32_t num_bits() const { return GetField<int32_t>(VT_NUM_BITS, 0); }
+  bool narrow_range() const { return GetField<uint8_t>(VT_NARROW_RANGE, 0) != 0; }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<float>(verifier, VT_MIN) &&
+           VerifyField<float>(verifier, VT_MAX) && VerifyField<int32_t>(verifier, VT_NUM_BITS) &&
+           VerifyField<uint8_t>(verifier, VT_NARROW_RANGE) && verifier.EndTable();
+  }
+};
+
+struct FakeQuantOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_min(float min) { fbb_.AddElement<float>(FakeQuantOptions::VT_MIN, min, 0.0f); }
+  void add_max(float max) { fbb_.AddElement<float>(FakeQuantOptions::VT_MAX, max, 0.0f); }
+  void add_num_bits(int32_t num_bits)
+  {
+    fbb_.AddElement<int32_t>(FakeQuantOptions::VT_NUM_BITS, num_bits, 0);
+  }
+  void add_narrow_range(bool narrow_range)
+  {
+    fbb_.AddElement<uint8_t>(FakeQuantOptions::VT_NARROW_RANGE, static_cast<uint8_t>(narrow_range),
+                             0);
+  }
+  explicit FakeQuantOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  FakeQuantOptionsBuilder &operator=(const FakeQuantOptionsBuilder &);
+  flatbuffers::Offset<FakeQuantOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<FakeQuantOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<FakeQuantOptions>
+CreateFakeQuantOptions(flatbuffers::FlatBufferBuilder &_fbb, float min = 0.0f, float max = 0.0f,
+                       int32_t num_bits = 0, bool narrow_range = false)
+{
+  FakeQuantOptionsBuilder builder_(_fbb);
+  builder_.add_num_bits(num_bits);
+  builder_.add_max(max);
+  builder_.add_min(min);
+  builder_.add_narrow_range(narrow_range);
+  return builder_.Finish();
+}
+
+struct PackOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_VALUES_COUNT = 4,
+    VT_AXIS = 6
+  };
+  int32_t values_count() const { return GetField<int32_t>(VT_VALUES_COUNT, 0); }
+  int32_t axis() const { return GetField<int32_t>(VT_AXIS, 0); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int32_t>(verifier, VT_VALUES_COUNT) &&
+           VerifyField<int32_t>(verifier, VT_AXIS) && verifier.EndTable();
+  }
+};
+
+struct PackOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_values_count(int32_t values_count)
+  {
+    fbb_.AddElement<int32_t>(PackOptions::VT_VALUES_COUNT, values_count, 0);
+  }
+  void add_axis(int32_t axis) { fbb_.AddElement<int32_t>(PackOptions::VT_AXIS, axis, 0); }
+  explicit PackOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  PackOptionsBuilder &operator=(const PackOptionsBuilder &);
+  flatbuffers::Offset<PackOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<PackOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<PackOptions>
+CreatePackOptions(flatbuffers::FlatBufferBuilder &_fbb, int32_t values_count = 0, int32_t axis = 0)
+{
+  PackOptionsBuilder builder_(_fbb);
+  builder_.add_axis(axis);
+  builder_.add_values_count(values_count);
+  return builder_.Finish();
+}
+
+struct LogicalOrOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct LogicalOrOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit LogicalOrOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  LogicalOrOptionsBuilder &operator=(const LogicalOrOptionsBuilder &);
+  flatbuffers::Offset<LogicalOrOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<LogicalOrOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<LogicalOrOptions>
+CreateLogicalOrOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  LogicalOrOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct OneHotOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_AXIS = 4
+  };
+  int32_t axis() const { return GetField<int32_t>(VT_AXIS, 0); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int32_t>(verifier, VT_AXIS) &&
+           verifier.EndTable();
+  }
+};
+
+struct OneHotOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_axis(int32_t axis) { fbb_.AddElement<int32_t>(OneHotOptions::VT_AXIS, axis, 0); }
+  explicit OneHotOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  OneHotOptionsBuilder &operator=(const OneHotOptionsBuilder &);
+  flatbuffers::Offset<OneHotOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<OneHotOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<OneHotOptions> CreateOneHotOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                                                              int32_t axis = 0)
+{
+  OneHotOptionsBuilder builder_(_fbb);
+  builder_.add_axis(axis);
+  return builder_.Finish();
+}
+
+struct AbsOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct AbsOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit AbsOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  AbsOptionsBuilder &operator=(const AbsOptionsBuilder &);
+  flatbuffers::Offset<AbsOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<AbsOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<AbsOptions> CreateAbsOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  AbsOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct LogicalAndOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct LogicalAndOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit LogicalAndOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  LogicalAndOptionsBuilder &operator=(const LogicalAndOptionsBuilder &);
+  flatbuffers::Offset<LogicalAndOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<LogicalAndOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<LogicalAndOptions>
+CreateLogicalAndOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  LogicalAndOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct LogicalNotOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct LogicalNotOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit LogicalNotOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  LogicalNotOptionsBuilder &operator=(const LogicalNotOptionsBuilder &);
+  flatbuffers::Offset<LogicalNotOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<LogicalNotOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<LogicalNotOptions>
+CreateLogicalNotOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  LogicalNotOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct UnpackOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_NUM = 4,
+    VT_AXIS = 6
+  };
+  int32_t num() const { return GetField<int32_t>(VT_NUM, 0); }
+  int32_t axis() const { return GetField<int32_t>(VT_AXIS, 0); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int32_t>(verifier, VT_NUM) &&
+           VerifyField<int32_t>(verifier, VT_AXIS) && verifier.EndTable();
+  }
+};
+
+struct UnpackOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_num(int32_t num) { fbb_.AddElement<int32_t>(UnpackOptions::VT_NUM, num, 0); }
+  void add_axis(int32_t axis) { fbb_.AddElement<int32_t>(UnpackOptions::VT_AXIS, axis, 0); }
+  explicit UnpackOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  UnpackOptionsBuilder &operator=(const UnpackOptionsBuilder &);
+  flatbuffers::Offset<UnpackOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<UnpackOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<UnpackOptions> CreateUnpackOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                                                              int32_t num = 0, int32_t axis = 0)
+{
+  UnpackOptionsBuilder builder_(_fbb);
+  builder_.add_axis(axis);
+  builder_.add_num(num);
+  return builder_.Finish();
+}
+
+struct FloorDivOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct FloorDivOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit FloorDivOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  FloorDivOptionsBuilder &operator=(const FloorDivOptionsBuilder &);
+  flatbuffers::Offset<FloorDivOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<FloorDivOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<FloorDivOptions>
+CreateFloorDivOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  FloorDivOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct SquareOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct SquareOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit SquareOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  SquareOptionsBuilder &operator=(const SquareOptionsBuilder &);
+  flatbuffers::Offset<SquareOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<SquareOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<SquareOptions> CreateSquareOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  SquareOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct ZerosLikeOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct ZerosLikeOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit ZerosLikeOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  ZerosLikeOptionsBuilder &operator=(const ZerosLikeOptionsBuilder &);
+  flatbuffers::Offset<ZerosLikeOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<ZerosLikeOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<ZerosLikeOptions>
+CreateZerosLikeOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  ZerosLikeOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct FillOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct FillOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit FillOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  FillOptionsBuilder &operator=(const FillOptionsBuilder &);
+  flatbuffers::Offset<FillOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<FillOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<FillOptions> CreateFillOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  FillOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct FloorModOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct FloorModOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit FloorModOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  FloorModOptionsBuilder &operator=(const FloorModOptionsBuilder &);
+  flatbuffers::Offset<FloorModOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<FloorModOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<FloorModOptions>
+CreateFloorModOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  FloorModOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct RangeOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct RangeOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit RangeOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  RangeOptionsBuilder &operator=(const RangeOptionsBuilder &);
+  flatbuffers::Offset<RangeOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<RangeOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<RangeOptions> CreateRangeOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  RangeOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct LeakyReluOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_ALPHA = 4
+  };
+  float alpha() const { return GetField<float>(VT_ALPHA, 0.0f); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<float>(verifier, VT_ALPHA) &&
+           verifier.EndTable();
+  }
+};
+
+struct LeakyReluOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_alpha(float alpha) { fbb_.AddElement<float>(LeakyReluOptions::VT_ALPHA, alpha, 0.0f); }
+  explicit LeakyReluOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  LeakyReluOptionsBuilder &operator=(const LeakyReluOptionsBuilder &);
+  flatbuffers::Offset<LeakyReluOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<LeakyReluOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<LeakyReluOptions>
+CreateLeakyReluOptions(flatbuffers::FlatBufferBuilder &_fbb, float alpha = 0.0f)
+{
+  LeakyReluOptionsBuilder builder_(_fbb);
+  builder_.add_alpha(alpha);
+  return builder_.Finish();
+}
+
+struct SquaredDifferenceOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct SquaredDifferenceOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit SquaredDifferenceOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  SquaredDifferenceOptionsBuilder &operator=(const SquaredDifferenceOptionsBuilder &);
+  flatbuffers::Offset<SquaredDifferenceOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<SquaredDifferenceOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<SquaredDifferenceOptions>
+CreateSquaredDifferenceOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  SquaredDifferenceOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct MirrorPadOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_MODE = 4
+  };
+  MirrorPadMode mode() const { return static_cast<MirrorPadMode>(GetField<int8_t>(VT_MODE, 0)); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int8_t>(verifier, VT_MODE) &&
+           verifier.EndTable();
+  }
+};
+
+struct MirrorPadOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_mode(MirrorPadMode mode)
+  {
+    fbb_.AddElement<int8_t>(MirrorPadOptions::VT_MODE, static_cast<int8_t>(mode), 0);
+  }
+  explicit MirrorPadOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  MirrorPadOptionsBuilder &operator=(const MirrorPadOptionsBuilder &);
+  flatbuffers::Offset<MirrorPadOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<MirrorPadOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<MirrorPadOptions>
+CreateMirrorPadOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                       MirrorPadMode mode = MirrorPadMode_REFLECT)
+{
+  MirrorPadOptionsBuilder builder_(_fbb);
+  builder_.add_mode(mode);
+  return builder_.Finish();
+}
+
+struct InstanceNormOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_EPSILON = 4,
+    VT_FUSED_ACTIVATION_FUNCTION = 6
+  };
+  float epsilon() const { return GetField<float>(VT_EPSILON, 0.0f); }
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<float>(verifier, VT_EPSILON) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) && verifier.EndTable();
+  }
+};
+
+struct InstanceNormOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_epsilon(float epsilon)
+  {
+    fbb_.AddElement<float>(InstanceNormOptions::VT_EPSILON, epsilon, 0.0f);
+  }
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(InstanceNormOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  explicit InstanceNormOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  InstanceNormOptionsBuilder &operator=(const InstanceNormOptionsBuilder &);
+  flatbuffers::Offset<InstanceNormOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<InstanceNormOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<InstanceNormOptions> CreateInstanceNormOptions(
+    flatbuffers::FlatBufferBuilder &_fbb, float epsilon = 0.0f,
+    ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE)
+{
+  InstanceNormOptionsBuilder builder_(_fbb);
+  builder_.add_epsilon(epsilon);
+  builder_.add_fused_activation_function(fused_activation_function);
+  return builder_.Finish();
+}
+
+struct OperatorCode FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_BUILTIN_CODE = 4,
+    VT_CUSTOM_CODE = 6,
+    VT_VERSION = 8
+  };
+  BuiltinOperator builtin_code() const
+  {
+    return static_cast<BuiltinOperator>(GetField<uint8_t>(VT_BUILTIN_CODE, 0));
+  }
+  const flatbuffers::String *custom_code() const
+  {
+    return GetPointer<const flatbuffers::String *>(VT_CUSTOM_CODE);
+  }
+  int32_t version() const { return GetField<int32_t>(VT_VERSION, 1); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<uint8_t>(verifier, VT_BUILTIN_CODE) &&
+           VerifyOffset(verifier, VT_CUSTOM_CODE) && verifier.VerifyString(custom_code()) &&
+           VerifyField<int32_t>(verifier, VT_VERSION) && verifier.EndTable();
+  }
+};
+
+struct OperatorCodeBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_builtin_code(BuiltinOperator builtin_code)
+  {
+    fbb_.AddElement<uint8_t>(OperatorCode::VT_BUILTIN_CODE, static_cast<uint8_t>(builtin_code), 0);
+  }
+  void add_custom_code(flatbuffers::Offset<flatbuffers::String> custom_code)
+  {
+    fbb_.AddOffset(OperatorCode::VT_CUSTOM_CODE, custom_code);
+  }
+  void add_version(int32_t version)
+  {
+    fbb_.AddElement<int32_t>(OperatorCode::VT_VERSION, version, 1);
+  }
+  explicit OperatorCodeBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  OperatorCodeBuilder &operator=(const OperatorCodeBuilder &);
+  flatbuffers::Offset<OperatorCode> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<OperatorCode>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<OperatorCode>
+CreateOperatorCode(flatbuffers::FlatBufferBuilder &_fbb,
+                   BuiltinOperator builtin_code = BuiltinOperator_ADD,
+                   flatbuffers::Offset<flatbuffers::String> custom_code = 0, int32_t version = 1)
+{
+  OperatorCodeBuilder builder_(_fbb);
+  builder_.add_version(version);
+  builder_.add_custom_code(custom_code);
+  builder_.add_builtin_code(builtin_code);
+  return builder_.Finish();
+}
+
+inline flatbuffers::Offset<OperatorCode>
+CreateOperatorCodeDirect(flatbuffers::FlatBufferBuilder &_fbb,
+                         BuiltinOperator builtin_code = BuiltinOperator_ADD,
+                         const char *custom_code = nullptr, int32_t version = 1)
+{
+  return circle::CreateOperatorCode(_fbb, builtin_code,
+                                    custom_code ? _fbb.CreateString(custom_code) : 0, version);
+}
+
+struct Operator FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_OPCODE_INDEX = 4,
+    VT_INPUTS = 6,
+    VT_OUTPUTS = 8,
+    VT_BUILTIN_OPTIONS_TYPE = 10,
+    VT_BUILTIN_OPTIONS = 12,
+    VT_CUSTOM_OPTIONS = 14,
+    VT_CUSTOM_OPTIONS_FORMAT = 16,
+    VT_MUTATING_VARIABLE_INPUTS = 18
+  };
+  uint32_t opcode_index() const { return GetField<uint32_t>(VT_OPCODE_INDEX, 0); }
+  const flatbuffers::Vector<int32_t> *inputs() const
+  {
+    return GetPointer<const flatbuffers::Vector<int32_t> *>(VT_INPUTS);
+  }
+  const flatbuffers::Vector<int32_t> *outputs() const
+  {
+    return GetPointer<const flatbuffers::Vector<int32_t> *>(VT_OUTPUTS);
+  }
+  BuiltinOptions builtin_options_type() const
+  {
+    return static_cast<BuiltinOptions>(GetField<uint8_t>(VT_BUILTIN_OPTIONS_TYPE, 0));
+  }
+  const void *builtin_options() const { return GetPointer<const void *>(VT_BUILTIN_OPTIONS); }
+  template <typename T> const T *builtin_options_as() const;
+  const Conv2DOptions *builtin_options_as_Conv2DOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_Conv2DOptions
+               ? static_cast<const Conv2DOptions *>(builtin_options())
+               : nullptr;
+  }
+  const DepthwiseConv2DOptions *builtin_options_as_DepthwiseConv2DOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_DepthwiseConv2DOptions
+               ? static_cast<const DepthwiseConv2DOptions *>(builtin_options())
+               : nullptr;
+  }
+  const ConcatEmbeddingsOptions *builtin_options_as_ConcatEmbeddingsOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_ConcatEmbeddingsOptions
+               ? static_cast<const ConcatEmbeddingsOptions *>(builtin_options())
+               : nullptr;
+  }
+  const LSHProjectionOptions *builtin_options_as_LSHProjectionOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_LSHProjectionOptions
+               ? static_cast<const LSHProjectionOptions *>(builtin_options())
+               : nullptr;
+  }
+  const Pool2DOptions *builtin_options_as_Pool2DOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_Pool2DOptions
+               ? static_cast<const Pool2DOptions *>(builtin_options())
+               : nullptr;
+  }
+  const SVDFOptions *builtin_options_as_SVDFOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_SVDFOptions
+               ? static_cast<const SVDFOptions *>(builtin_options())
+               : nullptr;
+  }
+  const RNNOptions *builtin_options_as_RNNOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_RNNOptions
+               ? static_cast<const RNNOptions *>(builtin_options())
+               : nullptr;
+  }
+  const FullyConnectedOptions *builtin_options_as_FullyConnectedOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_FullyConnectedOptions
+               ? static_cast<const FullyConnectedOptions *>(builtin_options())
+               : nullptr;
+  }
+  const SoftmaxOptions *builtin_options_as_SoftmaxOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_SoftmaxOptions
+               ? static_cast<const SoftmaxOptions *>(builtin_options())
+               : nullptr;
+  }
+  const ConcatenationOptions *builtin_options_as_ConcatenationOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_ConcatenationOptions
+               ? static_cast<const ConcatenationOptions *>(builtin_options())
+               : nullptr;
+  }
+  const AddOptions *builtin_options_as_AddOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_AddOptions
+               ? static_cast<const AddOptions *>(builtin_options())
+               : nullptr;
+  }
+  const L2NormOptions *builtin_options_as_L2NormOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_L2NormOptions
+               ? static_cast<const L2NormOptions *>(builtin_options())
+               : nullptr;
+  }
+  const LocalResponseNormalizationOptions *
+  builtin_options_as_LocalResponseNormalizationOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_LocalResponseNormalizationOptions
+               ? static_cast<const LocalResponseNormalizationOptions *>(builtin_options())
+               : nullptr;
+  }
+  const LSTMOptions *builtin_options_as_LSTMOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_LSTMOptions
+               ? static_cast<const LSTMOptions *>(builtin_options())
+               : nullptr;
+  }
+  const ResizeBilinearOptions *builtin_options_as_ResizeBilinearOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_ResizeBilinearOptions
+               ? static_cast<const ResizeBilinearOptions *>(builtin_options())
+               : nullptr;
+  }
+  const CallOptions *builtin_options_as_CallOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_CallOptions
+               ? static_cast<const CallOptions *>(builtin_options())
+               : nullptr;
+  }
+  const ReshapeOptions *builtin_options_as_ReshapeOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_ReshapeOptions
+               ? static_cast<const ReshapeOptions *>(builtin_options())
+               : nullptr;
+  }
+  const SkipGramOptions *builtin_options_as_SkipGramOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_SkipGramOptions
+               ? static_cast<const SkipGramOptions *>(builtin_options())
+               : nullptr;
+  }
+  const SpaceToDepthOptions *builtin_options_as_SpaceToDepthOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_SpaceToDepthOptions
+               ? static_cast<const SpaceToDepthOptions *>(builtin_options())
+               : nullptr;
+  }
+  const EmbeddingLookupSparseOptions *builtin_options_as_EmbeddingLookupSparseOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_EmbeddingLookupSparseOptions
+               ? static_cast<const EmbeddingLookupSparseOptions *>(builtin_options())
+               : nullptr;
+  }
+  const MulOptions *builtin_options_as_MulOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_MulOptions
+               ? static_cast<const MulOptions *>(builtin_options())
+               : nullptr;
+  }
+  const PadOptions *builtin_options_as_PadOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_PadOptions
+               ? static_cast<const PadOptions *>(builtin_options())
+               : nullptr;
+  }
+  const GatherOptions *builtin_options_as_GatherOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_GatherOptions
+               ? static_cast<const GatherOptions *>(builtin_options())
+               : nullptr;
+  }
+  const BatchToSpaceNDOptions *builtin_options_as_BatchToSpaceNDOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_BatchToSpaceNDOptions
+               ? static_cast<const BatchToSpaceNDOptions *>(builtin_options())
+               : nullptr;
+  }
+  const SpaceToBatchNDOptions *builtin_options_as_SpaceToBatchNDOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_SpaceToBatchNDOptions
+               ? static_cast<const SpaceToBatchNDOptions *>(builtin_options())
+               : nullptr;
+  }
+  const TransposeOptions *builtin_options_as_TransposeOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_TransposeOptions
+               ? static_cast<const TransposeOptions *>(builtin_options())
+               : nullptr;
+  }
+  const ReducerOptions *builtin_options_as_ReducerOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_ReducerOptions
+               ? static_cast<const ReducerOptions *>(builtin_options())
+               : nullptr;
+  }
+  const SubOptions *builtin_options_as_SubOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_SubOptions
+               ? static_cast<const SubOptions *>(builtin_options())
+               : nullptr;
+  }
+  const DivOptions *builtin_options_as_DivOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_DivOptions
+               ? static_cast<const DivOptions *>(builtin_options())
+               : nullptr;
+  }
+  const SqueezeOptions *builtin_options_as_SqueezeOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_SqueezeOptions
+               ? static_cast<const SqueezeOptions *>(builtin_options())
+               : nullptr;
+  }
+  const SequenceRNNOptions *builtin_options_as_SequenceRNNOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_SequenceRNNOptions
+               ? static_cast<const SequenceRNNOptions *>(builtin_options())
+               : nullptr;
+  }
+  const StridedSliceOptions *builtin_options_as_StridedSliceOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_StridedSliceOptions
+               ? static_cast<const StridedSliceOptions *>(builtin_options())
+               : nullptr;
+  }
+  const ExpOptions *builtin_options_as_ExpOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_ExpOptions
+               ? static_cast<const ExpOptions *>(builtin_options())
+               : nullptr;
+  }
+  const TopKV2Options *builtin_options_as_TopKV2Options() const
+  {
+    return builtin_options_type() == BuiltinOptions_TopKV2Options
+               ? static_cast<const TopKV2Options *>(builtin_options())
+               : nullptr;
+  }
+  const SplitOptions *builtin_options_as_SplitOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_SplitOptions
+               ? static_cast<const SplitOptions *>(builtin_options())
+               : nullptr;
+  }
+  const LogSoftmaxOptions *builtin_options_as_LogSoftmaxOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_LogSoftmaxOptions
+               ? static_cast<const LogSoftmaxOptions *>(builtin_options())
+               : nullptr;
+  }
+  const CastOptions *builtin_options_as_CastOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_CastOptions
+               ? static_cast<const CastOptions *>(builtin_options())
+               : nullptr;
+  }
+  const DequantizeOptions *builtin_options_as_DequantizeOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_DequantizeOptions
+               ? static_cast<const DequantizeOptions *>(builtin_options())
+               : nullptr;
+  }
+  const MaximumMinimumOptions *builtin_options_as_MaximumMinimumOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_MaximumMinimumOptions
+               ? static_cast<const MaximumMinimumOptions *>(builtin_options())
+               : nullptr;
+  }
+  const ArgMaxOptions *builtin_options_as_ArgMaxOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_ArgMaxOptions
+               ? static_cast<const ArgMaxOptions *>(builtin_options())
+               : nullptr;
+  }
+  const LessOptions *builtin_options_as_LessOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_LessOptions
+               ? static_cast<const LessOptions *>(builtin_options())
+               : nullptr;
+  }
+  const NegOptions *builtin_options_as_NegOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_NegOptions
+               ? static_cast<const NegOptions *>(builtin_options())
+               : nullptr;
+  }
+  const PadV2Options *builtin_options_as_PadV2Options() const
+  {
+    return builtin_options_type() == BuiltinOptions_PadV2Options
+               ? static_cast<const PadV2Options *>(builtin_options())
+               : nullptr;
+  }
+  const GreaterOptions *builtin_options_as_GreaterOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_GreaterOptions
+               ? static_cast<const GreaterOptions *>(builtin_options())
+               : nullptr;
+  }
+  const GreaterEqualOptions *builtin_options_as_GreaterEqualOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_GreaterEqualOptions
+               ? static_cast<const GreaterEqualOptions *>(builtin_options())
+               : nullptr;
+  }
+  const LessEqualOptions *builtin_options_as_LessEqualOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_LessEqualOptions
+               ? static_cast<const LessEqualOptions *>(builtin_options())
+               : nullptr;
+  }
+  const SelectOptions *builtin_options_as_SelectOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_SelectOptions
+               ? static_cast<const SelectOptions *>(builtin_options())
+               : nullptr;
+  }
+  const SliceOptions *builtin_options_as_SliceOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_SliceOptions
+               ? static_cast<const SliceOptions *>(builtin_options())
+               : nullptr;
+  }
+  const TransposeConvOptions *builtin_options_as_TransposeConvOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_TransposeConvOptions
+               ? static_cast<const TransposeConvOptions *>(builtin_options())
+               : nullptr;
+  }
+  const SparseToDenseOptions *builtin_options_as_SparseToDenseOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_SparseToDenseOptions
+               ? static_cast<const SparseToDenseOptions *>(builtin_options())
+               : nullptr;
+  }
+  const TileOptions *builtin_options_as_TileOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_TileOptions
+               ? static_cast<const TileOptions *>(builtin_options())
+               : nullptr;
+  }
+  const ExpandDimsOptions *builtin_options_as_ExpandDimsOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_ExpandDimsOptions
+               ? static_cast<const ExpandDimsOptions *>(builtin_options())
+               : nullptr;
+  }
+  const EqualOptions *builtin_options_as_EqualOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_EqualOptions
+               ? static_cast<const EqualOptions *>(builtin_options())
+               : nullptr;
+  }
+  const NotEqualOptions *builtin_options_as_NotEqualOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_NotEqualOptions
+               ? static_cast<const NotEqualOptions *>(builtin_options())
+               : nullptr;
+  }
+  const ShapeOptions *builtin_options_as_ShapeOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_ShapeOptions
+               ? static_cast<const ShapeOptions *>(builtin_options())
+               : nullptr;
+  }
+  const PowOptions *builtin_options_as_PowOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_PowOptions
+               ? static_cast<const PowOptions *>(builtin_options())
+               : nullptr;
+  }
+  const ArgMinOptions *builtin_options_as_ArgMinOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_ArgMinOptions
+               ? static_cast<const ArgMinOptions *>(builtin_options())
+               : nullptr;
+  }
+  const FakeQuantOptions *builtin_options_as_FakeQuantOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_FakeQuantOptions
+               ? static_cast<const FakeQuantOptions *>(builtin_options())
+               : nullptr;
+  }
+  const PackOptions *builtin_options_as_PackOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_PackOptions
+               ? static_cast<const PackOptions *>(builtin_options())
+               : nullptr;
+  }
+  const LogicalOrOptions *builtin_options_as_LogicalOrOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_LogicalOrOptions
+               ? static_cast<const LogicalOrOptions *>(builtin_options())
+               : nullptr;
+  }
+  const OneHotOptions *builtin_options_as_OneHotOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_OneHotOptions
+               ? static_cast<const OneHotOptions *>(builtin_options())
+               : nullptr;
+  }
+  const LogicalAndOptions *builtin_options_as_LogicalAndOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_LogicalAndOptions
+               ? static_cast<const LogicalAndOptions *>(builtin_options())
+               : nullptr;
+  }
+  const LogicalNotOptions *builtin_options_as_LogicalNotOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_LogicalNotOptions
+               ? static_cast<const LogicalNotOptions *>(builtin_options())
+               : nullptr;
+  }
+  const UnpackOptions *builtin_options_as_UnpackOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_UnpackOptions
+               ? static_cast<const UnpackOptions *>(builtin_options())
+               : nullptr;
+  }
+  const FloorDivOptions *builtin_options_as_FloorDivOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_FloorDivOptions
+               ? static_cast<const FloorDivOptions *>(builtin_options())
+               : nullptr;
+  }
+  const SquareOptions *builtin_options_as_SquareOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_SquareOptions
+               ? static_cast<const SquareOptions *>(builtin_options())
+               : nullptr;
+  }
+  const ZerosLikeOptions *builtin_options_as_ZerosLikeOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_ZerosLikeOptions
+               ? static_cast<const ZerosLikeOptions *>(builtin_options())
+               : nullptr;
+  }
+  const FillOptions *builtin_options_as_FillOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_FillOptions
+               ? static_cast<const FillOptions *>(builtin_options())
+               : nullptr;
+  }
+  const BidirectionalSequenceLSTMOptions *
+  builtin_options_as_BidirectionalSequenceLSTMOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_BidirectionalSequenceLSTMOptions
+               ? static_cast<const BidirectionalSequenceLSTMOptions *>(builtin_options())
+               : nullptr;
+  }
+  const BidirectionalSequenceRNNOptions *builtin_options_as_BidirectionalSequenceRNNOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_BidirectionalSequenceRNNOptions
+               ? static_cast<const BidirectionalSequenceRNNOptions *>(builtin_options())
+               : nullptr;
+  }
+  const UnidirectionalSequenceLSTMOptions *
+  builtin_options_as_UnidirectionalSequenceLSTMOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_UnidirectionalSequenceLSTMOptions
+               ? static_cast<const UnidirectionalSequenceLSTMOptions *>(builtin_options())
+               : nullptr;
+  }
+  const FloorModOptions *builtin_options_as_FloorModOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_FloorModOptions
+               ? static_cast<const FloorModOptions *>(builtin_options())
+               : nullptr;
+  }
+  const RangeOptions *builtin_options_as_RangeOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_RangeOptions
+               ? static_cast<const RangeOptions *>(builtin_options())
+               : nullptr;
+  }
+  const ResizeNearestNeighborOptions *builtin_options_as_ResizeNearestNeighborOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_ResizeNearestNeighborOptions
+               ? static_cast<const ResizeNearestNeighborOptions *>(builtin_options())
+               : nullptr;
+  }
+  const LeakyReluOptions *builtin_options_as_LeakyReluOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_LeakyReluOptions
+               ? static_cast<const LeakyReluOptions *>(builtin_options())
+               : nullptr;
+  }
+  const SquaredDifferenceOptions *builtin_options_as_SquaredDifferenceOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_SquaredDifferenceOptions
+               ? static_cast<const SquaredDifferenceOptions *>(builtin_options())
+               : nullptr;
+  }
+  const MirrorPadOptions *builtin_options_as_MirrorPadOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_MirrorPadOptions
+               ? static_cast<const MirrorPadOptions *>(builtin_options())
+               : nullptr;
+  }
+  const AbsOptions *builtin_options_as_AbsOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_AbsOptions
+               ? static_cast<const AbsOptions *>(builtin_options())
+               : nullptr;
+  }
+  const SplitVOptions *builtin_options_as_SplitVOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_SplitVOptions
+               ? static_cast<const SplitVOptions *>(builtin_options())
+               : nullptr;
+  }
+  const InstanceNormOptions *builtin_options_as_InstanceNormOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_InstanceNormOptions
+               ? static_cast<const InstanceNormOptions *>(builtin_options())
+               : nullptr;
+  }
+  const flatbuffers::Vector<uint8_t> *custom_options() const
+  {
+    return GetPointer<const flatbuffers::Vector<uint8_t> *>(VT_CUSTOM_OPTIONS);
+  }
+  CustomOptionsFormat custom_options_format() const
+  {
+    return static_cast<CustomOptionsFormat>(GetField<int8_t>(VT_CUSTOM_OPTIONS_FORMAT, 0));
+  }
+  const flatbuffers::Vector<uint8_t> *mutating_variable_inputs() const
+  {
+    return GetPointer<const flatbuffers::Vector<uint8_t> *>(VT_MUTATING_VARIABLE_INPUTS);
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<uint32_t>(verifier, VT_OPCODE_INDEX) &&
+           VerifyOffset(verifier, VT_INPUTS) && verifier.VerifyVector(inputs()) &&
+           VerifyOffset(verifier, VT_OUTPUTS) && verifier.VerifyVector(outputs()) &&
+           VerifyField<uint8_t>(verifier, VT_BUILTIN_OPTIONS_TYPE) &&
+           VerifyOffset(verifier, VT_BUILTIN_OPTIONS) &&
+           VerifyBuiltinOptions(verifier, builtin_options(), builtin_options_type()) &&
+           VerifyOffset(verifier, VT_CUSTOM_OPTIONS) && verifier.VerifyVector(custom_options()) &&
+           VerifyField<int8_t>(verifier, VT_CUSTOM_OPTIONS_FORMAT) &&
+           VerifyOffset(verifier, VT_MUTATING_VARIABLE_INPUTS) &&
+           verifier.VerifyVector(mutating_variable_inputs()) && verifier.EndTable();
+  }
+};
+
+template <> inline const Conv2DOptions *Operator::builtin_options_as<Conv2DOptions>() const
+{
+  return builtin_options_as_Conv2DOptions();
+}
+
+template <>
+inline const DepthwiseConv2DOptions *Operator::builtin_options_as<DepthwiseConv2DOptions>() const
+{
+  return builtin_options_as_DepthwiseConv2DOptions();
+}
+
+template <>
+inline const ConcatEmbeddingsOptions *Operator::builtin_options_as<ConcatEmbeddingsOptions>() const
+{
+  return builtin_options_as_ConcatEmbeddingsOptions();
+}
+
+template <>
+inline const LSHProjectionOptions *Operator::builtin_options_as<LSHProjectionOptions>() const
+{
+  return builtin_options_as_LSHProjectionOptions();
+}
+
+template <> inline const Pool2DOptions *Operator::builtin_options_as<Pool2DOptions>() const
+{
+  return builtin_options_as_Pool2DOptions();
+}
+
+template <> inline const SVDFOptions *Operator::builtin_options_as<SVDFOptions>() const
+{
+  return builtin_options_as_SVDFOptions();
+}
+
+template <> inline const RNNOptions *Operator::builtin_options_as<RNNOptions>() const
+{
+  return builtin_options_as_RNNOptions();
+}
+
+template <>
+inline const FullyConnectedOptions *Operator::builtin_options_as<FullyConnectedOptions>() const
+{
+  return builtin_options_as_FullyConnectedOptions();
+}
+
+template <> inline const SoftmaxOptions *Operator::builtin_options_as<SoftmaxOptions>() const
+{
+  return builtin_options_as_SoftmaxOptions();
+}
+
+template <>
+inline const ConcatenationOptions *Operator::builtin_options_as<ConcatenationOptions>() const
+{
+  return builtin_options_as_ConcatenationOptions();
+}
+
+template <> inline const AddOptions *Operator::builtin_options_as<AddOptions>() const
+{
+  return builtin_options_as_AddOptions();
+}
+
+template <> inline const L2NormOptions *Operator::builtin_options_as<L2NormOptions>() const
+{
+  return builtin_options_as_L2NormOptions();
+}
+
+template <>
+inline const LocalResponseNormalizationOptions *
+Operator::builtin_options_as<LocalResponseNormalizationOptions>() const
+{
+  return builtin_options_as_LocalResponseNormalizationOptions();
+}
+
+template <> inline const LSTMOptions *Operator::builtin_options_as<LSTMOptions>() const
+{
+  return builtin_options_as_LSTMOptions();
+}
+
+template <>
+inline const ResizeBilinearOptions *Operator::builtin_options_as<ResizeBilinearOptions>() const
+{
+  return builtin_options_as_ResizeBilinearOptions();
+}
+
+template <> inline const CallOptions *Operator::builtin_options_as<CallOptions>() const
+{
+  return builtin_options_as_CallOptions();
+}
+
+template <> inline const ReshapeOptions *Operator::builtin_options_as<ReshapeOptions>() const
+{
+  return builtin_options_as_ReshapeOptions();
+}
+
+template <> inline const SkipGramOptions *Operator::builtin_options_as<SkipGramOptions>() const
+{
+  return builtin_options_as_SkipGramOptions();
+}
+
+template <>
+inline const SpaceToDepthOptions *Operator::builtin_options_as<SpaceToDepthOptions>() const
+{
+  return builtin_options_as_SpaceToDepthOptions();
+}
+
+template <>
+inline const EmbeddingLookupSparseOptions *
+Operator::builtin_options_as<EmbeddingLookupSparseOptions>() const
+{
+  return builtin_options_as_EmbeddingLookupSparseOptions();
+}
+
+template <> inline const MulOptions *Operator::builtin_options_as<MulOptions>() const
+{
+  return builtin_options_as_MulOptions();
+}
+
+template <> inline const PadOptions *Operator::builtin_options_as<PadOptions>() const
+{
+  return builtin_options_as_PadOptions();
+}
+
+template <> inline const GatherOptions *Operator::builtin_options_as<GatherOptions>() const
+{
+  return builtin_options_as_GatherOptions();
+}
+
+template <>
+inline const BatchToSpaceNDOptions *Operator::builtin_options_as<BatchToSpaceNDOptions>() const
+{
+  return builtin_options_as_BatchToSpaceNDOptions();
+}
+
+template <>
+inline const SpaceToBatchNDOptions *Operator::builtin_options_as<SpaceToBatchNDOptions>() const
+{
+  return builtin_options_as_SpaceToBatchNDOptions();
+}
+
+template <> inline const TransposeOptions *Operator::builtin_options_as<TransposeOptions>() const
+{
+  return builtin_options_as_TransposeOptions();
+}
+
+template <> inline const ReducerOptions *Operator::builtin_options_as<ReducerOptions>() const
+{
+  return builtin_options_as_ReducerOptions();
+}
+
+template <> inline const SubOptions *Operator::builtin_options_as<SubOptions>() const
+{
+  return builtin_options_as_SubOptions();
+}
+
+template <> inline const DivOptions *Operator::builtin_options_as<DivOptions>() const
+{
+  return builtin_options_as_DivOptions();
+}
+
+template <> inline const SqueezeOptions *Operator::builtin_options_as<SqueezeOptions>() const
+{
+  return builtin_options_as_SqueezeOptions();
+}
+
+template <>
+inline const SequenceRNNOptions *Operator::builtin_options_as<SequenceRNNOptions>() const
+{
+  return builtin_options_as_SequenceRNNOptions();
+}
+
+template <>
+inline const StridedSliceOptions *Operator::builtin_options_as<StridedSliceOptions>() const
+{
+  return builtin_options_as_StridedSliceOptions();
+}
+
+template <> inline const ExpOptions *Operator::builtin_options_as<ExpOptions>() const
+{
+  return builtin_options_as_ExpOptions();
+}
+
+template <> inline const TopKV2Options *Operator::builtin_options_as<TopKV2Options>() const
+{
+  return builtin_options_as_TopKV2Options();
+}
+
+template <> inline const SplitOptions *Operator::builtin_options_as<SplitOptions>() const
+{
+  return builtin_options_as_SplitOptions();
+}
+
+template <> inline const LogSoftmaxOptions *Operator::builtin_options_as<LogSoftmaxOptions>() const
+{
+  return builtin_options_as_LogSoftmaxOptions();
+}
+
+template <> inline const CastOptions *Operator::builtin_options_as<CastOptions>() const
+{
+  return builtin_options_as_CastOptions();
+}
+
+template <> inline const DequantizeOptions *Operator::builtin_options_as<DequantizeOptions>() const
+{
+  return builtin_options_as_DequantizeOptions();
+}
+
+template <>
+inline const MaximumMinimumOptions *Operator::builtin_options_as<MaximumMinimumOptions>() const
+{
+  return builtin_options_as_MaximumMinimumOptions();
+}
+
+template <> inline const ArgMaxOptions *Operator::builtin_options_as<ArgMaxOptions>() const
+{
+  return builtin_options_as_ArgMaxOptions();
+}
+
+template <> inline const LessOptions *Operator::builtin_options_as<LessOptions>() const
+{
+  return builtin_options_as_LessOptions();
+}
+
+template <> inline const NegOptions *Operator::builtin_options_as<NegOptions>() const
+{
+  return builtin_options_as_NegOptions();
+}
+
+template <> inline const PadV2Options *Operator::builtin_options_as<PadV2Options>() const
+{
+  return builtin_options_as_PadV2Options();
+}
+
+template <> inline const GreaterOptions *Operator::builtin_options_as<GreaterOptions>() const
+{
+  return builtin_options_as_GreaterOptions();
+}
+
+template <>
+inline const GreaterEqualOptions *Operator::builtin_options_as<GreaterEqualOptions>() const
+{
+  return builtin_options_as_GreaterEqualOptions();
+}
+
+template <> inline const LessEqualOptions *Operator::builtin_options_as<LessEqualOptions>() const
+{
+  return builtin_options_as_LessEqualOptions();
+}
+
+template <> inline const SelectOptions *Operator::builtin_options_as<SelectOptions>() const
+{
+  return builtin_options_as_SelectOptions();
+}
+
+template <> inline const SliceOptions *Operator::builtin_options_as<SliceOptions>() const
+{
+  return builtin_options_as_SliceOptions();
+}
+
+template <>
+inline const TransposeConvOptions *Operator::builtin_options_as<TransposeConvOptions>() const
+{
+  return builtin_options_as_TransposeConvOptions();
+}
+
+template <>
+inline const SparseToDenseOptions *Operator::builtin_options_as<SparseToDenseOptions>() const
+{
+  return builtin_options_as_SparseToDenseOptions();
+}
+
+template <> inline const TileOptions *Operator::builtin_options_as<TileOptions>() const
+{
+  return builtin_options_as_TileOptions();
+}
+
+template <> inline const ExpandDimsOptions *Operator::builtin_options_as<ExpandDimsOptions>() const
+{
+  return builtin_options_as_ExpandDimsOptions();
+}
+
+template <> inline const EqualOptions *Operator::builtin_options_as<EqualOptions>() const
+{
+  return builtin_options_as_EqualOptions();
+}
+
+template <> inline const NotEqualOptions *Operator::builtin_options_as<NotEqualOptions>() const
+{
+  return builtin_options_as_NotEqualOptions();
+}
+
+template <> inline const ShapeOptions *Operator::builtin_options_as<ShapeOptions>() const
+{
+  return builtin_options_as_ShapeOptions();
+}
+
+template <> inline const PowOptions *Operator::builtin_options_as<PowOptions>() const
+{
+  return builtin_options_as_PowOptions();
+}
+
+template <> inline const ArgMinOptions *Operator::builtin_options_as<ArgMinOptions>() const
+{
+  return builtin_options_as_ArgMinOptions();
+}
+
+template <> inline const FakeQuantOptions *Operator::builtin_options_as<FakeQuantOptions>() const
+{
+  return builtin_options_as_FakeQuantOptions();
+}
+
+template <> inline const PackOptions *Operator::builtin_options_as<PackOptions>() const
+{
+  return builtin_options_as_PackOptions();
+}
+
+template <> inline const LogicalOrOptions *Operator::builtin_options_as<LogicalOrOptions>() const
+{
+  return builtin_options_as_LogicalOrOptions();
+}
+
+template <> inline const OneHotOptions *Operator::builtin_options_as<OneHotOptions>() const
+{
+  return builtin_options_as_OneHotOptions();
+}
+
+template <> inline const LogicalAndOptions *Operator::builtin_options_as<LogicalAndOptions>() const
+{
+  return builtin_options_as_LogicalAndOptions();
+}
+
+template <> inline const LogicalNotOptions *Operator::builtin_options_as<LogicalNotOptions>() const
+{
+  return builtin_options_as_LogicalNotOptions();
+}
+
+template <> inline const UnpackOptions *Operator::builtin_options_as<UnpackOptions>() const
+{
+  return builtin_options_as_UnpackOptions();
+}
+
+template <> inline const FloorDivOptions *Operator::builtin_options_as<FloorDivOptions>() const
+{
+  return builtin_options_as_FloorDivOptions();
+}
+
+template <> inline const SquareOptions *Operator::builtin_options_as<SquareOptions>() const
+{
+  return builtin_options_as_SquareOptions();
+}
+
+template <> inline const ZerosLikeOptions *Operator::builtin_options_as<ZerosLikeOptions>() const
+{
+  return builtin_options_as_ZerosLikeOptions();
+}
+
+template <> inline const FillOptions *Operator::builtin_options_as<FillOptions>() const
+{
+  return builtin_options_as_FillOptions();
+}
+
+template <>
+inline const BidirectionalSequenceLSTMOptions *
+Operator::builtin_options_as<BidirectionalSequenceLSTMOptions>() const
+{
+  return builtin_options_as_BidirectionalSequenceLSTMOptions();
+}
+
+template <>
+inline const BidirectionalSequenceRNNOptions *
+Operator::builtin_options_as<BidirectionalSequenceRNNOptions>() const
+{
+  return builtin_options_as_BidirectionalSequenceRNNOptions();
+}
+
+template <>
+inline const UnidirectionalSequenceLSTMOptions *
+Operator::builtin_options_as<UnidirectionalSequenceLSTMOptions>() const
+{
+  return builtin_options_as_UnidirectionalSequenceLSTMOptions();
+}
+
+template <> inline const FloorModOptions *Operator::builtin_options_as<FloorModOptions>() const
+{
+  return builtin_options_as_FloorModOptions();
+}
+
+template <> inline const RangeOptions *Operator::builtin_options_as<RangeOptions>() const
+{
+  return builtin_options_as_RangeOptions();
+}
+
+template <>
+inline const ResizeNearestNeighborOptions *
+Operator::builtin_options_as<ResizeNearestNeighborOptions>() const
+{
+  return builtin_options_as_ResizeNearestNeighborOptions();
+}
+
+template <> inline const LeakyReluOptions *Operator::builtin_options_as<LeakyReluOptions>() const
+{
+  return builtin_options_as_LeakyReluOptions();
+}
+
+template <>
+inline const SquaredDifferenceOptions *
+Operator::builtin_options_as<SquaredDifferenceOptions>() const
+{
+  return builtin_options_as_SquaredDifferenceOptions();
+}
+
+template <> inline const MirrorPadOptions *Operator::builtin_options_as<MirrorPadOptions>() const
+{
+  return builtin_options_as_MirrorPadOptions();
+}
+
+template <> inline const AbsOptions *Operator::builtin_options_as<AbsOptions>() const
+{
+  return builtin_options_as_AbsOptions();
+}
+
+template <> inline const SplitVOptions *Operator::builtin_options_as<SplitVOptions>() const
+{
+  return builtin_options_as_SplitVOptions();
+}
+
+template <>
+inline const InstanceNormOptions *Operator::builtin_options_as<InstanceNormOptions>() const
+{
+  return builtin_options_as_InstanceNormOptions();
+}
+
+struct OperatorBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_opcode_index(uint32_t opcode_index)
+  {
+    fbb_.AddElement<uint32_t>(Operator::VT_OPCODE_INDEX, opcode_index, 0);
+  }
+  void add_inputs(flatbuffers::Offset<flatbuffers::Vector<int32_t>> inputs)
+  {
+    fbb_.AddOffset(Operator::VT_INPUTS, inputs);
+  }
+  void add_outputs(flatbuffers::Offset<flatbuffers::Vector<int32_t>> outputs)
+  {
+    fbb_.AddOffset(Operator::VT_OUTPUTS, outputs);
+  }
+  void add_builtin_options_type(BuiltinOptions builtin_options_type)
+  {
+    fbb_.AddElement<uint8_t>(Operator::VT_BUILTIN_OPTIONS_TYPE,
+                             static_cast<uint8_t>(builtin_options_type), 0);
+  }
+  void add_builtin_options(flatbuffers::Offset<void> builtin_options)
+  {
+    fbb_.AddOffset(Operator::VT_BUILTIN_OPTIONS, builtin_options);
+  }
+  void add_custom_options(flatbuffers::Offset<flatbuffers::Vector<uint8_t>> custom_options)
+  {
+    fbb_.AddOffset(Operator::VT_CUSTOM_OPTIONS, custom_options);
+  }
+  void add_custom_options_format(CustomOptionsFormat custom_options_format)
+  {
+    fbb_.AddElement<int8_t>(Operator::VT_CUSTOM_OPTIONS_FORMAT,
+                            static_cast<int8_t>(custom_options_format), 0);
+  }
+  void add_mutating_variable_inputs(
+      flatbuffers::Offset<flatbuffers::Vector<uint8_t>> mutating_variable_inputs)
+  {
+    fbb_.AddOffset(Operator::VT_MUTATING_VARIABLE_INPUTS, mutating_variable_inputs);
+  }
+  explicit OperatorBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  OperatorBuilder &operator=(const OperatorBuilder &);
+  flatbuffers::Offset<Operator> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<Operator>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<Operator>
+CreateOperator(flatbuffers::FlatBufferBuilder &_fbb, uint32_t opcode_index = 0,
+               flatbuffers::Offset<flatbuffers::Vector<int32_t>> inputs = 0,
+               flatbuffers::Offset<flatbuffers::Vector<int32_t>> outputs = 0,
+               BuiltinOptions builtin_options_type = BuiltinOptions_NONE,
+               flatbuffers::Offset<void> builtin_options = 0,
+               flatbuffers::Offset<flatbuffers::Vector<uint8_t>> custom_options = 0,
+               CustomOptionsFormat custom_options_format = CustomOptionsFormat_FLEXBUFFERS,
+               flatbuffers::Offset<flatbuffers::Vector<uint8_t>> mutating_variable_inputs = 0)
+{
+  OperatorBuilder builder_(_fbb);
+  builder_.add_mutating_variable_inputs(mutating_variable_inputs);
+  builder_.add_custom_options(custom_options);
+  builder_.add_builtin_options(builtin_options);
+  builder_.add_outputs(outputs);
+  builder_.add_inputs(inputs);
+  builder_.add_opcode_index(opcode_index);
+  builder_.add_custom_options_format(custom_options_format);
+  builder_.add_builtin_options_type(builtin_options_type);
+  return builder_.Finish();
+}
+
+inline flatbuffers::Offset<Operator>
+CreateOperatorDirect(flatbuffers::FlatBufferBuilder &_fbb, uint32_t opcode_index = 0,
+                     const std::vector<int32_t> *inputs = nullptr,
+                     const std::vector<int32_t> *outputs = nullptr,
+                     BuiltinOptions builtin_options_type = BuiltinOptions_NONE,
+                     flatbuffers::Offset<void> builtin_options = 0,
+                     const std::vector<uint8_t> *custom_options = nullptr,
+                     CustomOptionsFormat custom_options_format = CustomOptionsFormat_FLEXBUFFERS,
+                     const std::vector<uint8_t> *mutating_variable_inputs = nullptr)
+{
+  return circle::CreateOperator(
+      _fbb, opcode_index, inputs ? _fbb.CreateVector<int32_t>(*inputs) : 0,
+      outputs ? _fbb.CreateVector<int32_t>(*outputs) : 0, builtin_options_type, builtin_options,
+      custom_options ? _fbb.CreateVector<uint8_t>(*custom_options) : 0, custom_options_format,
+      mutating_variable_inputs ? _fbb.CreateVector<uint8_t>(*mutating_variable_inputs) : 0);
+}
+
+struct SubGraph FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_TENSORS = 4,
+    VT_INPUTS = 6,
+    VT_OUTPUTS = 8,
+    VT_OPERATORS = 10,
+    VT_NAME = 12,
+    VT_DATA_FORMAT = 14
+  };
+  const flatbuffers::Vector<flatbuffers::Offset<Tensor>> *tensors() const
+  {
+    return GetPointer<const flatbuffers::Vector<flatbuffers::Offset<Tensor>> *>(VT_TENSORS);
+  }
+  const flatbuffers::Vector<int32_t> *inputs() const
+  {
+    return GetPointer<const flatbuffers::Vector<int32_t> *>(VT_INPUTS);
+  }
+  const flatbuffers::Vector<int32_t> *outputs() const
+  {
+    return GetPointer<const flatbuffers::Vector<int32_t> *>(VT_OUTPUTS);
+  }
+  const flatbuffers::Vector<flatbuffers::Offset<Operator>> *operators() const
+  {
+    return GetPointer<const flatbuffers::Vector<flatbuffers::Offset<Operator>> *>(VT_OPERATORS);
+  }
+  const flatbuffers::String *name() const
+  {
+    return GetPointer<const flatbuffers::String *>(VT_NAME);
+  }
+  DataFormat data_format() const
+  {
+    return static_cast<DataFormat>(GetField<int8_t>(VT_DATA_FORMAT, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyOffset(verifier, VT_TENSORS) &&
+           verifier.VerifyVector(tensors()) && verifier.VerifyVectorOfTables(tensors()) &&
+           VerifyOffset(verifier, VT_INPUTS) && verifier.VerifyVector(inputs()) &&
+           VerifyOffset(verifier, VT_OUTPUTS) && verifier.VerifyVector(outputs()) &&
+           VerifyOffset(verifier, VT_OPERATORS) && verifier.VerifyVector(operators()) &&
+           verifier.VerifyVectorOfTables(operators()) && VerifyOffset(verifier, VT_NAME) &&
+           verifier.VerifyString(name()) && VerifyField<int8_t>(verifier, VT_DATA_FORMAT) &&
+           verifier.EndTable();
+  }
+};
+
+struct SubGraphBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_tensors(flatbuffers::Offset<flatbuffers::Vector<flatbuffers::Offset<Tensor>>> tensors)
+  {
+    fbb_.AddOffset(SubGraph::VT_TENSORS, tensors);
+  }
+  void add_inputs(flatbuffers::Offset<flatbuffers::Vector<int32_t>> inputs)
+  {
+    fbb_.AddOffset(SubGraph::VT_INPUTS, inputs);
+  }
+  void add_outputs(flatbuffers::Offset<flatbuffers::Vector<int32_t>> outputs)
+  {
+    fbb_.AddOffset(SubGraph::VT_OUTPUTS, outputs);
+  }
+  void
+  add_operators(flatbuffers::Offset<flatbuffers::Vector<flatbuffers::Offset<Operator>>> operators)
+  {
+    fbb_.AddOffset(SubGraph::VT_OPERATORS, operators);
+  }
+  void add_name(flatbuffers::Offset<flatbuffers::String> name)
+  {
+    fbb_.AddOffset(SubGraph::VT_NAME, name);
+  }
+  void add_data_format(DataFormat data_format)
+  {
+    fbb_.AddElement<int8_t>(SubGraph::VT_DATA_FORMAT, static_cast<int8_t>(data_format), 0);
+  }
+  explicit SubGraphBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  SubGraphBuilder &operator=(const SubGraphBuilder &);
+  flatbuffers::Offset<SubGraph> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<SubGraph>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<SubGraph> CreateSubGraph(
+    flatbuffers::FlatBufferBuilder &_fbb,
+    flatbuffers::Offset<flatbuffers::Vector<flatbuffers::Offset<Tensor>>> tensors = 0,
+    flatbuffers::Offset<flatbuffers::Vector<int32_t>> inputs = 0,
+    flatbuffers::Offset<flatbuffers::Vector<int32_t>> outputs = 0,
+    flatbuffers::Offset<flatbuffers::Vector<flatbuffers::Offset<Operator>>> operators = 0,
+    flatbuffers::Offset<flatbuffers::String> name = 0,
+    DataFormat data_format = DataFormat_CHANNELS_LAST)
+{
+  SubGraphBuilder builder_(_fbb);
+  builder_.add_name(name);
+  builder_.add_operators(operators);
+  builder_.add_outputs(outputs);
+  builder_.add_inputs(inputs);
+  builder_.add_tensors(tensors);
+  builder_.add_data_format(data_format);
+  return builder_.Finish();
+}
+
+inline flatbuffers::Offset<SubGraph>
+CreateSubGraphDirect(flatbuffers::FlatBufferBuilder &_fbb,
+                     const std::vector<flatbuffers::Offset<Tensor>> *tensors = nullptr,
+                     const std::vector<int32_t> *inputs = nullptr,
+                     const std::vector<int32_t> *outputs = nullptr,
+                     const std::vector<flatbuffers::Offset<Operator>> *operators = nullptr,
+                     const char *name = nullptr, DataFormat data_format = DataFormat_CHANNELS_LAST)
+{
+  return circle::CreateSubGraph(
+      _fbb, tensors ? _fbb.CreateVector<flatbuffers::Offset<Tensor>>(*tensors) : 0,
+      inputs ? _fbb.CreateVector<int32_t>(*inputs) : 0,
+      outputs ? _fbb.CreateVector<int32_t>(*outputs) : 0,
+      operators ? _fbb.CreateVector<flatbuffers::Offset<Operator>>(*operators) : 0,
+      name ? _fbb.CreateString(name) : 0, data_format);
+}
+
+struct Buffer FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_DATA = 4
+  };
+  const flatbuffers::Vector<uint8_t> *data() const
+  {
+    return GetPointer<const flatbuffers::Vector<uint8_t> *>(VT_DATA);
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyOffset(verifier, VT_DATA) &&
+           verifier.VerifyVector(data()) && verifier.EndTable();
+  }
+};
+
+struct BufferBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_data(flatbuffers::Offset<flatbuffers::Vector<uint8_t>> data)
+  {
+    fbb_.AddOffset(Buffer::VT_DATA, data);
+  }
+  explicit BufferBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  BufferBuilder &operator=(const BufferBuilder &);
+  flatbuffers::Offset<Buffer> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<Buffer>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<Buffer>
+CreateBuffer(flatbuffers::FlatBufferBuilder &_fbb,
+             flatbuffers::Offset<flatbuffers::Vector<uint8_t>> data = 0)
+{
+  BufferBuilder builder_(_fbb);
+  builder_.add_data(data);
+  return builder_.Finish();
+}
+
+inline flatbuffers::Offset<Buffer> CreateBufferDirect(flatbuffers::FlatBufferBuilder &_fbb,
+                                                      const std::vector<uint8_t> *data = nullptr)
+{
+  return circle::CreateBuffer(_fbb, data ? _fbb.CreateVector<uint8_t>(*data) : 0);
+}
+
+struct Model FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_VERSION = 4,
+    VT_OPERATOR_CODES = 6,
+    VT_SUBGRAPHS = 8,
+    VT_DESCRIPTION = 10,
+    VT_BUFFERS = 12,
+    VT_METADATA_BUFFER = 14
+  };
+  uint32_t version() const { return GetField<uint32_t>(VT_VERSION, 0); }
+  const flatbuffers::Vector<flatbuffers::Offset<OperatorCode>> *operator_codes() const
+  {
+    return GetPointer<const flatbuffers::Vector<flatbuffers::Offset<OperatorCode>> *>(
+        VT_OPERATOR_CODES);
+  }
+  const flatbuffers::Vector<flatbuffers::Offset<SubGraph>> *subgraphs() const
+  {
+    return GetPointer<const flatbuffers::Vector<flatbuffers::Offset<SubGraph>> *>(VT_SUBGRAPHS);
+  }
+  const flatbuffers::String *description() const
+  {
+    return GetPointer<const flatbuffers::String *>(VT_DESCRIPTION);
+  }
+  const flatbuffers::Vector<flatbuffers::Offset<Buffer>> *buffers() const
+  {
+    return GetPointer<const flatbuffers::Vector<flatbuffers::Offset<Buffer>> *>(VT_BUFFERS);
+  }
+  const flatbuffers::Vector<int32_t> *metadata_buffer() const
+  {
+    return GetPointer<const flatbuffers::Vector<int32_t> *>(VT_METADATA_BUFFER);
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<uint32_t>(verifier, VT_VERSION) &&
+           VerifyOffset(verifier, VT_OPERATOR_CODES) && verifier.VerifyVector(operator_codes()) &&
+           verifier.VerifyVectorOfTables(operator_codes()) &&
+           VerifyOffset(verifier, VT_SUBGRAPHS) && verifier.VerifyVector(subgraphs()) &&
+           verifier.VerifyVectorOfTables(subgraphs()) && VerifyOffset(verifier, VT_DESCRIPTION) &&
+           verifier.VerifyString(description()) && VerifyOffset(verifier, VT_BUFFERS) &&
+           verifier.VerifyVector(buffers()) && verifier.VerifyVectorOfTables(buffers()) &&
+           VerifyOffset(verifier, VT_METADATA_BUFFER) && verifier.VerifyVector(metadata_buffer()) &&
+           verifier.EndTable();
+  }
+};
+
+struct ModelBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_version(uint32_t version) { fbb_.AddElement<uint32_t>(Model::VT_VERSION, version, 0); }
+  void add_operator_codes(
+      flatbuffers::Offset<flatbuffers::Vector<flatbuffers::Offset<OperatorCode>>> operator_codes)
+  {
+    fbb_.AddOffset(Model::VT_OPERATOR_CODES, operator_codes);
+  }
+  void
+  add_subgraphs(flatbuffers::Offset<flatbuffers::Vector<flatbuffers::Offset<SubGraph>>> subgraphs)
+  {
+    fbb_.AddOffset(Model::VT_SUBGRAPHS, subgraphs);
+  }
+  void add_description(flatbuffers::Offset<flatbuffers::String> description)
+  {
+    fbb_.AddOffset(Model::VT_DESCRIPTION, description);
+  }
+  void add_buffers(flatbuffers::Offset<flatbuffers::Vector<flatbuffers::Offset<Buffer>>> buffers)
+  {
+    fbb_.AddOffset(Model::VT_BUFFERS, buffers);
+  }
+  void add_metadata_buffer(flatbuffers::Offset<flatbuffers::Vector<int32_t>> metadata_buffer)
+  {
+    fbb_.AddOffset(Model::VT_METADATA_BUFFER, metadata_buffer);
+  }
+  explicit ModelBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  ModelBuilder &operator=(const ModelBuilder &);
+  flatbuffers::Offset<Model> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<Model>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<Model> CreateModel(
+    flatbuffers::FlatBufferBuilder &_fbb, uint32_t version = 0,
+    flatbuffers::Offset<flatbuffers::Vector<flatbuffers::Offset<OperatorCode>>> operator_codes = 0,
+    flatbuffers::Offset<flatbuffers::Vector<flatbuffers::Offset<SubGraph>>> subgraphs = 0,
+    flatbuffers::Offset<flatbuffers::String> description = 0,
+    flatbuffers::Offset<flatbuffers::Vector<flatbuffers::Offset<Buffer>>> buffers = 0,
+    flatbuffers::Offset<flatbuffers::Vector<int32_t>> metadata_buffer = 0)
+{
+  ModelBuilder builder_(_fbb);
+  builder_.add_metadata_buffer(metadata_buffer);
+  builder_.add_buffers(buffers);
+  builder_.add_description(description);
+  builder_.add_subgraphs(subgraphs);
+  builder_.add_operator_codes(operator_codes);
+  builder_.add_version(version);
+  return builder_.Finish();
+}
+
+inline flatbuffers::Offset<Model>
+CreateModelDirect(flatbuffers::FlatBufferBuilder &_fbb, uint32_t version = 0,
+                  const std::vector<flatbuffers::Offset<OperatorCode>> *operator_codes = nullptr,
+                  const std::vector<flatbuffers::Offset<SubGraph>> *subgraphs = nullptr,
+                  const char *description = nullptr,
+                  const std::vector<flatbuffers::Offset<Buffer>> *buffers = nullptr,
+                  const std::vector<int32_t> *metadata_buffer = nullptr)
+{
+  return circle::CreateModel(
+      _fbb, version,
+      operator_codes ? _fbb.CreateVector<flatbuffers::Offset<OperatorCode>>(*operator_codes) : 0,
+      subgraphs ? _fbb.CreateVector<flatbuffers::Offset<SubGraph>>(*subgraphs) : 0,
+      description ? _fbb.CreateString(description) : 0,
+      buffers ? _fbb.CreateVector<flatbuffers::Offset<Buffer>>(*buffers) : 0,
+      metadata_buffer ? _fbb.CreateVector<int32_t>(*metadata_buffer) : 0);
+}
+
+inline bool VerifyQuantizationDetails(flatbuffers::Verifier &verifier, const void *obj,
+                                      QuantizationDetails type)
+{
+  switch (type)
+  {
+    case QuantizationDetails_NONE:
+    {
+      return true;
+    }
+    case QuantizationDetails_CustomQuantization:
+    {
+      auto ptr = reinterpret_cast<const CustomQuantization *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    default:
+      return false;
+  }
+}
+
+inline bool
+VerifyQuantizationDetailsVector(flatbuffers::Verifier &verifier,
+                                const flatbuffers::Vector<flatbuffers::Offset<void>> *values,
+                                const flatbuffers::Vector<uint8_t> *types)
+{
+  if (!values || !types)
+    return !values && !types;
+  if (values->size() != types->size())
+    return false;
+  for (flatbuffers::uoffset_t i = 0; i < values->size(); ++i)
+  {
+    if (!VerifyQuantizationDetails(verifier, values->Get(i),
+                                   types->GetEnum<QuantizationDetails>(i)))
+    {
+      return false;
+    }
+  }
+  return true;
+}
+
+inline bool VerifyBuiltinOptions(flatbuffers::Verifier &verifier, const void *obj,
+                                 BuiltinOptions type)
+{
+  switch (type)
+  {
+    case BuiltinOptions_NONE:
+    {
+      return true;
+    }
+    case BuiltinOptions_Conv2DOptions:
+    {
+      auto ptr = reinterpret_cast<const Conv2DOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_DepthwiseConv2DOptions:
+    {
+      auto ptr = reinterpret_cast<const DepthwiseConv2DOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_ConcatEmbeddingsOptions:
+    {
+      auto ptr = reinterpret_cast<const ConcatEmbeddingsOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_LSHProjectionOptions:
+    {
+      auto ptr = reinterpret_cast<const LSHProjectionOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_Pool2DOptions:
+    {
+      auto ptr = reinterpret_cast<const Pool2DOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_SVDFOptions:
+    {
+      auto ptr = reinterpret_cast<const SVDFOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_RNNOptions:
+    {
+      auto ptr = reinterpret_cast<const RNNOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_FullyConnectedOptions:
+    {
+      auto ptr = reinterpret_cast<const FullyConnectedOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_SoftmaxOptions:
+    {
+      auto ptr = reinterpret_cast<const SoftmaxOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_ConcatenationOptions:
+    {
+      auto ptr = reinterpret_cast<const ConcatenationOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_AddOptions:
+    {
+      auto ptr = reinterpret_cast<const AddOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_L2NormOptions:
+    {
+      auto ptr = reinterpret_cast<const L2NormOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_LocalResponseNormalizationOptions:
+    {
+      auto ptr = reinterpret_cast<const LocalResponseNormalizationOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_LSTMOptions:
+    {
+      auto ptr = reinterpret_cast<const LSTMOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_ResizeBilinearOptions:
+    {
+      auto ptr = reinterpret_cast<const ResizeBilinearOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_CallOptions:
+    {
+      auto ptr = reinterpret_cast<const CallOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_ReshapeOptions:
+    {
+      auto ptr = reinterpret_cast<const ReshapeOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_SkipGramOptions:
+    {
+      auto ptr = reinterpret_cast<const SkipGramOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_SpaceToDepthOptions:
+    {
+      auto ptr = reinterpret_cast<const SpaceToDepthOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_EmbeddingLookupSparseOptions:
+    {
+      auto ptr = reinterpret_cast<const EmbeddingLookupSparseOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_MulOptions:
+    {
+      auto ptr = reinterpret_cast<const MulOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_PadOptions:
+    {
+      auto ptr = reinterpret_cast<const PadOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_GatherOptions:
+    {
+      auto ptr = reinterpret_cast<const GatherOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_BatchToSpaceNDOptions:
+    {
+      auto ptr = reinterpret_cast<const BatchToSpaceNDOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_SpaceToBatchNDOptions:
+    {
+      auto ptr = reinterpret_cast<const SpaceToBatchNDOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_TransposeOptions:
+    {
+      auto ptr = reinterpret_cast<const TransposeOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_ReducerOptions:
+    {
+      auto ptr = reinterpret_cast<const ReducerOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_SubOptions:
+    {
+      auto ptr = reinterpret_cast<const SubOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_DivOptions:
+    {
+      auto ptr = reinterpret_cast<const DivOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_SqueezeOptions:
+    {
+      auto ptr = reinterpret_cast<const SqueezeOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_SequenceRNNOptions:
+    {
+      auto ptr = reinterpret_cast<const SequenceRNNOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_StridedSliceOptions:
+    {
+      auto ptr = reinterpret_cast<const StridedSliceOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_ExpOptions:
+    {
+      auto ptr = reinterpret_cast<const ExpOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_TopKV2Options:
+    {
+      auto ptr = reinterpret_cast<const TopKV2Options *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_SplitOptions:
+    {
+      auto ptr = reinterpret_cast<const SplitOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_LogSoftmaxOptions:
+    {
+      auto ptr = reinterpret_cast<const LogSoftmaxOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_CastOptions:
+    {
+      auto ptr = reinterpret_cast<const CastOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_DequantizeOptions:
+    {
+      auto ptr = reinterpret_cast<const DequantizeOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_MaximumMinimumOptions:
+    {
+      auto ptr = reinterpret_cast<const MaximumMinimumOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_ArgMaxOptions:
+    {
+      auto ptr = reinterpret_cast<const ArgMaxOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_LessOptions:
+    {
+      auto ptr = reinterpret_cast<const LessOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_NegOptions:
+    {
+      auto ptr = reinterpret_cast<const NegOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_PadV2Options:
+    {
+      auto ptr = reinterpret_cast<const PadV2Options *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_GreaterOptions:
+    {
+      auto ptr = reinterpret_cast<const GreaterOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_GreaterEqualOptions:
+    {
+      auto ptr = reinterpret_cast<const GreaterEqualOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_LessEqualOptions:
+    {
+      auto ptr = reinterpret_cast<const LessEqualOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_SelectOptions:
+    {
+      auto ptr = reinterpret_cast<const SelectOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_SliceOptions:
+    {
+      auto ptr = reinterpret_cast<const SliceOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_TransposeConvOptions:
+    {
+      auto ptr = reinterpret_cast<const TransposeConvOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_SparseToDenseOptions:
+    {
+      auto ptr = reinterpret_cast<const SparseToDenseOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_TileOptions:
+    {
+      auto ptr = reinterpret_cast<const TileOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_ExpandDimsOptions:
+    {
+      auto ptr = reinterpret_cast<const ExpandDimsOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_EqualOptions:
+    {
+      auto ptr = reinterpret_cast<const EqualOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_NotEqualOptions:
+    {
+      auto ptr = reinterpret_cast<const NotEqualOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_ShapeOptions:
+    {
+      auto ptr = reinterpret_cast<const ShapeOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_PowOptions:
+    {
+      auto ptr = reinterpret_cast<const PowOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_ArgMinOptions:
+    {
+      auto ptr = reinterpret_cast<const ArgMinOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_FakeQuantOptions:
+    {
+      auto ptr = reinterpret_cast<const FakeQuantOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_PackOptions:
+    {
+      auto ptr = reinterpret_cast<const PackOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_LogicalOrOptions:
+    {
+      auto ptr = reinterpret_cast<const LogicalOrOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_OneHotOptions:
+    {
+      auto ptr = reinterpret_cast<const OneHotOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_LogicalAndOptions:
+    {
+      auto ptr = reinterpret_cast<const LogicalAndOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_LogicalNotOptions:
+    {
+      auto ptr = reinterpret_cast<const LogicalNotOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_UnpackOptions:
+    {
+      auto ptr = reinterpret_cast<const UnpackOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_FloorDivOptions:
+    {
+      auto ptr = reinterpret_cast<const FloorDivOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_SquareOptions:
+    {
+      auto ptr = reinterpret_cast<const SquareOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_ZerosLikeOptions:
+    {
+      auto ptr = reinterpret_cast<const ZerosLikeOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_FillOptions:
+    {
+      auto ptr = reinterpret_cast<const FillOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_BidirectionalSequenceLSTMOptions:
+    {
+      auto ptr = reinterpret_cast<const BidirectionalSequenceLSTMOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_BidirectionalSequenceRNNOptions:
+    {
+      auto ptr = reinterpret_cast<const BidirectionalSequenceRNNOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_UnidirectionalSequenceLSTMOptions:
+    {
+      auto ptr = reinterpret_cast<const UnidirectionalSequenceLSTMOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_FloorModOptions:
+    {
+      auto ptr = reinterpret_cast<const FloorModOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_RangeOptions:
+    {
+      auto ptr = reinterpret_cast<const RangeOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_ResizeNearestNeighborOptions:
+    {
+      auto ptr = reinterpret_cast<const ResizeNearestNeighborOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_LeakyReluOptions:
+    {
+      auto ptr = reinterpret_cast<const LeakyReluOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_SquaredDifferenceOptions:
+    {
+      auto ptr = reinterpret_cast<const SquaredDifferenceOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_MirrorPadOptions:
+    {
+      auto ptr = reinterpret_cast<const MirrorPadOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_AbsOptions:
+    {
+      auto ptr = reinterpret_cast<const AbsOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_SplitVOptions:
+    {
+      auto ptr = reinterpret_cast<const SplitVOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_InstanceNormOptions:
+    {
+      auto ptr = reinterpret_cast<const InstanceNormOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    default:
+      return false;
+  }
+}
+
+inline bool VerifyBuiltinOptionsVector(flatbuffers::Verifier &verifier,
+                                       const flatbuffers::Vector<flatbuffers::Offset<void>> *values,
+                                       const flatbuffers::Vector<uint8_t> *types)
+{
+  if (!values || !types)
+    return !values && !types;
+  if (values->size() != types->size())
+    return false;
+  for (flatbuffers::uoffset_t i = 0; i < values->size(); ++i)
+  {
+    if (!VerifyBuiltinOptions(verifier, values->Get(i), types->GetEnum<BuiltinOptions>(i)))
+    {
+      return false;
+    }
+  }
+  return true;
+}
+
+inline const circle::Model *GetModel(const void *buf)
+{
+  return flatbuffers::GetRoot<circle::Model>(buf);
+}
+
+inline const circle::Model *GetSizePrefixedModel(const void *buf)
+{
+  return flatbuffers::GetSizePrefixedRoot<circle::Model>(buf);
+}
+
+inline const char *ModelIdentifier() { return "CIR0"; }
+
+inline bool ModelBufferHasIdentifier(const void *buf)
+{
+  return flatbuffers::BufferHasIdentifier(buf, ModelIdentifier());
+}
+
+inline bool VerifyModelBuffer(flatbuffers::Verifier &verifier)
+{
+  return verifier.VerifyBuffer<circle::Model>(ModelIdentifier());
+}
+
+inline bool VerifySizePrefixedModelBuffer(flatbuffers::Verifier &verifier)
+{
+  return verifier.VerifySizePrefixedBuffer<circle::Model>(ModelIdentifier());
+}
+
+inline const char *ModelExtension() { return "circle"; }
+
+inline void FinishModelBuffer(flatbuffers::FlatBufferBuilder &fbb,
+                              flatbuffers::Offset<circle::Model> root)
+{
+  fbb.Finish(root, ModelIdentifier());
+}
+
+inline void FinishSizePrefixedModelBuffer(flatbuffers::FlatBufferBuilder &fbb,
+                                          flatbuffers::Offset<circle::Model> root)
+{
+  fbb.FinishSizePrefixed(root, ModelIdentifier());
+}
+
+} // namespace circle
+
+#endif // FLATBUFFERS_GENERATED_CIRCLESCHEMA_CIRCLE_H_
diff --git a/runtime/neurun/frontend/nnapi/ANeuralNetworksModel.test.cc b/runtime/neurun/frontend/nnapi/ANeuralNetworksModel.test.cc
new file mode 100644
index 000000000..15a279a7e
--- /dev/null
+++ b/runtime/neurun/frontend/nnapi/ANeuralNetworksModel.test.cc
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <gtest/gtest.h>
+
+#include "wrapper/ANeuralNetworksModel.h"
+
+TEST(MODEL, model_build)
+{
+  ANeuralNetworksModel model;
+  ASSERT_EQ(model.isFinished(), false);
+}
diff --git a/runtime/neurun/frontend/nnapi/CMakeLists.txt b/runtime/neurun/frontend/nnapi/CMakeLists.txt
new file mode 100644
index 000000000..3c3411e05
--- /dev/null
+++ b/runtime/neurun/frontend/nnapi/CMakeLists.txt
@@ -0,0 +1,23 @@
+file(GLOB_RECURSE SOURCES_FRONTEND "*.cc")
+file(GLOB_RECURSE TESTS_FRONTEND "*.test.cc")
+list(REMOVE_ITEM SOURCES_FRONTEND ${TESTS_FRONTEND})
+
+set(LIB_NEURUN neurun)
+
+add_library(${LIB_NEURUN} SHARED ${SOURCES_FRONTEND})
+target_link_libraries(${LIB_NEURUN} PUBLIC nnfw-nnapi-header)
+target_link_libraries(${LIB_NEURUN} PUBLIC neurun_core) # TODO Link PRIVATE neurun_core
+target_link_libraries(${LIB_NEURUN} PRIVATE nnfw_common)
+target_link_libraries(${LIB_NEURUN} PRIVATE nnfw_coverage)
+
+set_target_properties(${LIB_NEURUN} PROPERTIES OUTPUT_NAME neuralnetworks)
+
+install(TARGETS ${LIB_NEURUN} DESTINATION lib)
+
+add_executable(test_neurun_frontend_nnapi ${TESTS_FRONTEND})
+
+target_link_libraries(test_neurun_frontend_nnapi PRIVATE ${LIB_NEURUN} dl)
+target_link_libraries(test_neurun_frontend_nnapi PRIVATE gtest)
+target_link_libraries(test_neurun_frontend_nnapi PRIVATE gtest_main)
+
+install(TARGETS test_neurun_frontend_nnapi DESTINATION unittest)
diff --git a/runtime/neurun/frontend/nnapi/compilation.cc b/runtime/neurun/frontend/nnapi/compilation.cc
new file mode 100644
index 000000000..164158f19
--- /dev/null
+++ b/runtime/neurun/frontend/nnapi/compilation.cc
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <NeuralNetworks.h>
+
+#include <new>
+
+#include "wrapper/ANeuralNetworksModel.h"
+#include "wrapper/ANeuralNetworksCompilation.h"
+#include "util/logging.h"
+
+//
+// NNAPI Implementation
+//
+int ANeuralNetworksCompilation_create(ANeuralNetworksModel *model,
+                                      ANeuralNetworksCompilation **compilation)
+{
+  if ((model == nullptr) || (compilation == nullptr))
+  {
+    VERBOSE(NNAPI::Compilation) << "create: Incorrect null pointer parameter(s)" << std::endl;
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  if (!model->isFinished())
+  {
+    VERBOSE(NNAPI::Compilation) << "create: Model define is not finished" << std::endl;
+    return ANEURALNETWORKS_BAD_STATE;
+  }
+
+  std::shared_ptr<neurun::ir::Graph> internal;
+
+  model->release(internal);
+
+  *compilation = new (std::nothrow) ANeuralNetworksCompilation(internal);
+  if (*compilation == nullptr)
+  {
+    VERBOSE(NNAPI::Compilation) << "create: ail to create compilation object" << std::endl;
+    return ANEURALNETWORKS_OUT_OF_MEMORY;
+  }
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksCompilation_finish(ANeuralNetworksCompilation *compilation)
+{
+  if (compilation == nullptr)
+  {
+    VERBOSE(NNAPI::Compilation) << "finish: Incorrect null pointer parameter" << std::endl;
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  if (compilation->state() != ::neurun::compiler::State::CREATED)
+  {
+    VERBOSE(NNAPI::Compilation) << "finish: Already finished" << std::endl;
+    return ANEURALNETWORKS_BAD_STATE;
+  }
+
+  if (!compilation->finish())
+  {
+    VERBOSE(NNAPI::Compilation) << "finish: Fail to compile" << std::endl;
+    return ANEURALNETWORKS_BAD_STATE;
+  }
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+void ANeuralNetworksCompilation_free(ANeuralNetworksCompilation *compilation)
+{
+  delete compilation;
+}
+
+int ANeuralNetworksCompilation_setPreference(ANeuralNetworksCompilation *compilation,
+                                             int32_t preference)
+{
+  if (compilation == nullptr)
+  {
+    VERBOSE(NNAPI::Compilation) << "setPreference: Incorrect null pointer parameter" << std::endl;
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  if (compilation->state() != ::neurun::compiler::State::CREATED)
+  {
+    VERBOSE(NNAPI::Compilation) << "setPreference: Already finished" << std::endl;
+    return ANEURALNETWORKS_BAD_STATE;
+  }
+
+  const PreferenceCode FIRST_PREFERENCE_CODE = ANEURALNETWORKS_PREFER_LOW_POWER;
+  const PreferenceCode LAST_PREFERENCE_CODE = ANEURALNETWORKS_PREFER_SUSTAINED_SPEED;
+  if ((preference < FIRST_PREFERENCE_CODE) || (preference > LAST_PREFERENCE_CODE))
+  {
+    VERBOSE(NNAPI::Compilation) << "setPreference: Incorrect preference code" << std::endl;
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  // NYI: nothing to set
+  return ANEURALNETWORKS_NO_ERROR;
+}
diff --git a/runtime/neurun/frontend/nnapi/event.cc b/runtime/neurun/frontend/nnapi/event.cc
new file mode 100644
index 000000000..593b74e90
--- /dev/null
+++ b/runtime/neurun/frontend/nnapi/event.cc
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <NeuralNetworks.h>
+
+#include "wrapper/ANeuralNetworksEvent.h"
+
+int ANeuralNetworksEvent_wait(ANeuralNetworksEvent *event)
+{
+  if (event == nullptr)
+  {
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  if (!event->waitFinish())
+  {
+    return ANEURALNETWORKS_BAD_STATE;
+  }
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+void ANeuralNetworksEvent_free(ANeuralNetworksEvent *event) { delete event; }
diff --git a/runtime/neurun/frontend/nnapi/execution.cc b/runtime/neurun/frontend/nnapi/execution.cc
new file mode 100644
index 000000000..08f2df4c2
--- /dev/null
+++ b/runtime/neurun/frontend/nnapi/execution.cc
@@ -0,0 +1,480 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <NeuralNetworks.h>
+
+#include <new>
+
+#include "wrapper/ANeuralNetworksCompilation.h"
+#include "wrapper/ANeuralNetworksExecution.h"
+#include "wrapper/ANeuralNetworksMemory.h"
+#include "wrapper/ANeuralNetworksEvent.h"
+#include "wrapper/NNAPIConvert.h"
+#include "util/logging.h"
+
+//
+// NNAPI Implementation
+//
+int ANeuralNetworksExecution_create(ANeuralNetworksCompilation *compilation,
+                                    ANeuralNetworksExecution **execution)
+{
+  if ((compilation == nullptr) || (execution == nullptr))
+  {
+    VERBOSE(NNAPI::Execution) << "create: Incorrect null pointer parameter(s)" << std::endl;
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  std::shared_ptr<neurun::exec::IExecutor> executor;
+
+  compilation->publish(executor);
+
+  if (executor == nullptr)
+  {
+    VERBOSE(NNAPI::Execution) << "create: Never compiled yet" << std::endl;
+    return ANEURALNETWORKS_BAD_STATE;
+  }
+
+  *execution = new (std::nothrow) ANeuralNetworksExecution{executor};
+  if (*execution == nullptr)
+  {
+    VERBOSE(NNAPI::Execution) << "create: Fail to create execution object" << std::endl;
+    return ANEURALNETWORKS_OUT_OF_MEMORY;
+  }
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+// NOTE Handle optional input
+//  Unspecified shape on model build
+//    Optional and omitted input on execution: skip input setting (workaround for LSTM)
+//    Optional but not omitted input on execution: cannot handle
+//    Normal input on execution: cannot handle
+//  Fully specified shape on model build
+//    Optional input on execution: cannot handle
+//    Normal input: handle normally
+int ANeuralNetworksExecution_setInput(ANeuralNetworksExecution *execution, int32_t index,
+                                      const ANeuralNetworksOperandType *type, const void *buffer,
+                                      size_t length)
+{
+  // Don't check type
+  // Comment about ANeuralNetworksOperandType in NeuralNetworks.h:
+  //  If the input or output is optional and omitted then it need not have a fully specified tensor
+  //  operand type
+  if ((execution == nullptr) || ((buffer == nullptr) && (length != 0)))
+  {
+    VERBOSE(NNAPI::Execution) << "setInput: Incorrect null pointer parameter(s)" << std::endl;
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  if ((buffer != nullptr) && (length == 0))
+  {
+    VERBOSE(NNAPI::Execution) << "setInput: Zero length input" << std::endl;
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  const auto operand_index = execution->getInputOperandIndex(index);
+  if (!operand_index.valid())
+  {
+    VERBOSE(NNAPI::Execution) << "setInput: Invalid input index" << std::endl;
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  // Omitted optional input
+  // LSTM operation's some inputs can be optional input
+  if ((buffer == nullptr) && (length == 0))
+  {
+    if (execution->haveUnspecifiedDims(operand_index))
+    {
+      return ANEURALNETWORKS_NO_ERROR;
+    }
+    else
+    {
+      VERBOSE(NNAPI::Execution) << "setInput: Cannot handle fully-specified shape on model build "
+                                   "but omitted input on execution"
+                                << std::endl;
+      return ANEURALNETWORKS_BAD_DATA;
+    }
+  }
+
+  if (type != nullptr)
+  {
+    if (!execution->compareDataType(type, operand_index))
+    {
+      VERBOSE(NNAPI::Execution) << "setInput: Data type mismatch" << std::endl;
+      return ANEURALNETWORKS_BAD_DATA;
+    }
+
+    if (!execution->compareShape(type, operand_index))
+    {
+      VERBOSE(NNAPI::Execution) << "setInput: Shape mismatch" << std::endl;
+      return ANEURALNETWORKS_BAD_DATA;
+    }
+
+    if (NNAPIConvert::calculateSizeFromType(type) != length)
+    {
+      VERBOSE(NNAPI::Execution) << "setInput: Invalid length" << std::endl;
+      return ANEURALNETWORKS_BAD_DATA;
+    }
+  }
+  else
+  {
+    if (execution->haveUnspecifiedDims(operand_index))
+    {
+      VERBOSE(NNAPI::Execution) << "setInput: Unspecified dimension value" << std::endl;
+      return ANEURALNETWORKS_BAD_DATA;
+    }
+
+    if (execution->getOperandSize(operand_index) != length)
+    {
+      VERBOSE(NNAPI::Execution) << "setInput: Invalid length" << std::endl;
+      return ANEURALNETWORKS_BAD_DATA;
+    }
+  }
+
+  if (!execution->setInput(index, type, buffer, length))
+  {
+    VERBOSE(NNAPI::Execution) << "setInput: Fail to set input" << std::endl;
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksExecution_setOutput(ANeuralNetworksExecution *execution, int32_t index,
+                                       const ANeuralNetworksOperandType *type, void *buffer,
+                                       size_t length)
+{
+  // Don't check type
+  // Comment about ANeuralNetworksOperandType in NeuralNetworks.h:
+  //  If the input or output is optional and omitted then it need not have a fully specified tensor
+  //  operand type
+  if ((execution == nullptr) || ((buffer == nullptr) && (length != 0)))
+  {
+    VERBOSE(NNAPI::Execution) << "setOutput: Incorrect null pointer parameter(s)" << std::endl;
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  if ((buffer != nullptr) && (length == 0))
+  {
+    VERBOSE(NNAPI::Execution) << "setOutput: Zero length output" << std::endl;
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  // Handle optional output
+  if (buffer == nullptr)
+  {
+    return ANEURALNETWORKS_NO_ERROR;
+  }
+
+  const auto operand_index = execution->getOutputOperandIndex(index);
+  if (!operand_index.valid())
+  {
+    VERBOSE(NNAPI::Execution) << "setOutput: Invalid output index" << std::endl;
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  if (type != nullptr)
+  {
+    if (!execution->compareDataType(type, operand_index))
+    {
+      VERBOSE(NNAPI::Execution) << "setOutput: Data type mismatch" << std::endl;
+      return ANEURALNETWORKS_BAD_DATA;
+    }
+
+    if (!execution->compareShape(type, operand_index))
+    {
+      VERBOSE(NNAPI::Execution) << "setOutput: Shape mismatch" << std::endl;
+      return ANEURALNETWORKS_BAD_DATA;
+    }
+
+    if (NNAPIConvert::calculateSizeFromType(type) != length)
+    {
+      VERBOSE(NNAPI::Execution) << "setOutput: Invalid length" << std::endl;
+      return ANEURALNETWORKS_BAD_DATA;
+    }
+  }
+  else
+  {
+    if (execution->haveUnspecifiedDims(operand_index))
+    {
+      VERBOSE(NNAPI::Execution) << "setOutput: Unspecified dimension value" << std::endl;
+      return ANEURALNETWORKS_BAD_DATA;
+    }
+
+    if (execution->getOperandSize(operand_index) != length)
+    {
+      VERBOSE(NNAPI::Execution) << "setInput: Invalid length" << std::endl;
+      return ANEURALNETWORKS_BAD_DATA;
+    }
+  }
+
+  if (!execution->setOutput(index, type, buffer, length))
+  {
+    VERBOSE(NNAPI::Execution) << "setOutput: Fail to set output" << std::endl;
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksExecution_startCompute(ANeuralNetworksExecution *execution,
+                                          ANeuralNetworksEvent **event)
+{
+  if ((execution == nullptr) || (event == nullptr))
+  {
+    VERBOSE(NNAPI::Execution) << "startCompute: Incorrect null pointer parameter(s)" << std::endl;
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  // TODO: Handle event
+  auto instance = execution->instance();
+  *event = new (std::nothrow) ANeuralNetworksEvent{instance};
+  if (*event == nullptr)
+  {
+    VERBOSE(NNAPI::Execution) << "startCompute: Fail to create event" << std::endl;
+    return ANEURALNETWORKS_OUT_OF_MEMORY;
+  }
+
+  if (!execution->startExecute())
+  {
+    VERBOSE(NNAPI::Execution) << "startCompute: Fail to start execution" << std::endl;
+    return ANEURALNETWORKS_BAD_STATE;
+  }
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksExecution_compute(ANeuralNetworksExecution *execution)
+{
+  if (execution == nullptr)
+  {
+    VERBOSE(NNAPI::Execution) << "Compute: Incorrect null pointer parameter" << std::endl;
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  if (!execution->execute())
+  {
+    VERBOSE(NNAPI::Execution) << "Compute: Fail to execution" << std::endl;
+    return ANEURALNETWORKS_BAD_STATE;
+  }
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+void ANeuralNetworksExecution_free(ANeuralNetworksExecution *execution) { delete execution; }
+
+int ANeuralNetworksExecution_setInputFromMemory(ANeuralNetworksExecution *execution, int32_t index,
+                                                const ANeuralNetworksOperandType *type,
+                                                const ANeuralNetworksMemory *memory, size_t offset,
+                                                size_t length)
+{
+  if ((execution == nullptr) || (memory == nullptr))
+  {
+    VERBOSE(NNAPI::Execution) << "setInputFromMemory: Incorrect null pointer parameter(s)"
+                              << std::endl;
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  if (length == 0)
+  {
+    VERBOSE(NNAPI::Execution) << "setInputFromMemory: Zero length input" << std::endl;
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  const auto operand_index = execution->getInputOperandIndex(index);
+  if (!operand_index.valid())
+  {
+    VERBOSE(NNAPI::Execution) << "setInputFromMemory: Invalid input index" << std::endl;
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  if (type != nullptr)
+  {
+    if (!execution->compareDataType(type, operand_index))
+    {
+      VERBOSE(NNAPI::Execution) << "setInputFromMemory: Data type mismatch" << std::endl;
+      return ANEURALNETWORKS_BAD_DATA;
+    }
+
+    if (!execution->compareShape(type, operand_index))
+    {
+      VERBOSE(NNAPI::Execution) << "setInputFromMemory: Shape mismatch" << std::endl;
+      return ANEURALNETWORKS_BAD_DATA;
+    }
+
+    if (NNAPIConvert::calculateSizeFromType(type) != length)
+    {
+      VERBOSE(NNAPI::Execution) << "setInputFromMemory: Invalid length" << std::endl;
+      return ANEURALNETWORKS_BAD_DATA;
+    }
+  }
+  else
+  {
+    if (execution->haveUnspecifiedDims(operand_index))
+    {
+      VERBOSE(NNAPI::Execution) << "setInputFromMemory: Unspecified dimension value" << std::endl;
+      return ANEURALNETWORKS_BAD_DATA;
+    }
+
+    if (execution->getOperandSize(operand_index) != length)
+    {
+      VERBOSE(NNAPI::Execution) << "setInputFromMemory: Invalid length" << std::endl;
+      return ANEURALNETWORKS_BAD_DATA;
+    }
+  }
+
+  if (!memory->vaildAccess(offset, length))
+  {
+    VERBOSE(NNAPI::Execution) << "setInputFromMemory: Invalid memory access" << std::endl;
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  if (!execution->setInput(index, type, reinterpret_cast<const void *>(memory->base() + offset),
+                           length))
+  {
+    VERBOSE(NNAPI::Execution) << "setInputFromMemory: Fail to set input" << std::endl;
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksExecution_setOutputFromMemory(ANeuralNetworksExecution *execution, int32_t index,
+                                                 const ANeuralNetworksOperandType *type,
+                                                 const ANeuralNetworksMemory *memory, size_t offset,
+                                                 size_t length)
+{
+  if ((execution == nullptr) || (memory == nullptr))
+  {
+    VERBOSE(NNAPI::Execution) << "setOutputFromMemory: Incorrect null pointer parameter(s)"
+                              << std::endl;
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  if (length == 0)
+  {
+    VERBOSE(NNAPI::Execution) << "setOutputFromMemory: Zero length input" << std::endl;
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  const auto operand_index = execution->getOutputOperandIndex(index);
+  if (!operand_index.valid())
+  {
+    VERBOSE(NNAPI::Execution) << "setOutputFromMemory: Invalid output index" << std::endl;
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  if (type != nullptr)
+  {
+    if (!execution->compareDataType(type, operand_index))
+    {
+      VERBOSE(NNAPI::Execution) << "setOutputFromMemory: Data type mismatch" << std::endl;
+      return ANEURALNETWORKS_BAD_DATA;
+    }
+
+    if (!execution->compareShape(type, operand_index))
+    {
+      VERBOSE(NNAPI::Execution) << "setOutputFromMemory: Shape mismatch" << std::endl;
+      return ANEURALNETWORKS_BAD_DATA;
+    }
+
+    if (NNAPIConvert::calculateSizeFromType(type) != length)
+    {
+      VERBOSE(NNAPI::Execution) << "setOutputFromMemory: Invalid length" << std::endl;
+      return ANEURALNETWORKS_BAD_DATA;
+    }
+  }
+  else
+  {
+    if (execution->haveUnspecifiedDims(operand_index))
+    {
+      VERBOSE(NNAPI::Execution) << "setOutputFromMemory: Unspecified dimension value" << std::endl;
+      return ANEURALNETWORKS_BAD_DATA;
+    }
+
+    if (execution->getOperandSize(operand_index) != length)
+    {
+      VERBOSE(NNAPI::Execution) << "setOutputFromMemory: Invalid length" << std::endl;
+      return ANEURALNETWORKS_BAD_DATA;
+    }
+  }
+
+  if (!memory->vaildAccess(offset, length))
+  {
+    VERBOSE(NNAPI::Execution) << "setOutputFromMemory: Invalid memory access" << std::endl;
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  if (!execution->setOutput(index, type, reinterpret_cast<void *>(memory->base() + offset), length))
+  {
+    VERBOSE(NNAPI::Execution) << "setOutputFromMemory: Fail to set input" << std::endl;
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksExecution_getOutputOperandRank(ANeuralNetworksExecution *execution,
+                                                  int32_t index, uint32_t *rank)
+{
+  if ((execution == nullptr) || (rank == nullptr))
+  {
+    VERBOSE(NNAPI::Execution) << "getOutputOperandRank: Incorrect null pointer parameter(s)"
+                              << std::endl;
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  const auto operand_index = execution->getOutputOperandIndex(index);
+  if (!operand_index.valid())
+  {
+    VERBOSE(NNAPI::Execution) << "getOutputOperandRank: Invalid output index" << std::endl;
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  if (!execution->getOutputOperandRank(index, rank))
+  {
+    VERBOSE(NNAPI::Execution) << "getOutputOperandRank: Fail to get rank" << std::endl;
+    return ANEURALNETWORKS_BAD_STATE;
+  }
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksExecution_getOutputOperandDimensions(ANeuralNetworksExecution *execution,
+                                                        int32_t index, uint32_t *dimensions)
+{
+  if ((execution == nullptr) || (dimensions == nullptr))
+  {
+    VERBOSE(NNAPI::Execution) << "getOutputOperandDimensions: Incorrect null pointer parameter(s)"
+                              << std::endl;
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  const auto operand_index = execution->getOutputOperandIndex(index);
+  if (!operand_index.valid())
+  {
+    VERBOSE(NNAPI::Execution) << "getOutputOperandDimensions: Invalid output index" << std::endl;
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  if (!execution->getOutputOperandDimensions(index, dimensions))
+  {
+    VERBOSE(NNAPI::Execution) << "getOutputOperandDimensions: Fail to get rank" << std::endl;
+    return ANEURALNETWORKS_BAD_STATE;
+  }
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
diff --git a/runtime/neurun/frontend/nnapi/memory.cc b/runtime/neurun/frontend/nnapi/memory.cc
new file mode 100644
index 000000000..fbe1a48e8
--- /dev/null
+++ b/runtime/neurun/frontend/nnapi/memory.cc
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <NeuralNetworks.h>
+#include <sys/mman.h>
+#include <new>
+#include <memory>
+
+#include "cpp14/memory.h"
+#include "wrapper/ANeuralNetworksMemory.h"
+
+int ANeuralNetworksMemory_createFromFd(size_t size, int protect, int fd, size_t offset,
+                                       ANeuralNetworksMemory **memory)
+{
+  if (memory == nullptr)
+  {
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  *memory = new (std::nothrow) ANeuralNetworksMemory{size, protect, fd, offset};
+  if (*memory == nullptr)
+  {
+    return ANEURALNETWORKS_OUT_OF_MEMORY;
+  }
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+void ANeuralNetworksMemory_free(ANeuralNetworksMemory *memory) { delete memory; }
diff --git a/runtime/neurun/frontend/nnapi/model.cc b/runtime/neurun/frontend/nnapi/model.cc
new file mode 100644
index 000000000..72a66e630
--- /dev/null
+++ b/runtime/neurun/frontend/nnapi/model.cc
@@ -0,0 +1,411 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <NeuralNetworks.h>
+#include <NeuralNetworksEx.h>
+
+#include <new>
+
+#include "wrapper/ANeuralNetworksModel.h"
+#include "wrapper/ANeuralNetworksMemory.h"
+#include "util/logging.h"
+
+int ANeuralNetworksModel_create(ANeuralNetworksModel **model)
+{
+  if (model == nullptr)
+  {
+    VERBOSE(NNAPI::Model) << "create: Incorrect null pointer parameter" << std::endl;
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  *model = new (std::nothrow) ANeuralNetworksModel{};
+  if (*model == nullptr)
+  {
+    VERBOSE(NNAPI::Model) << "create: Fail to create model object" << std::endl;
+    return ANEURALNETWORKS_OUT_OF_MEMORY;
+  }
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+void ANeuralNetworksModel_free(ANeuralNetworksModel *model) { delete model; }
+
+int ANeuralNetworksModel_addOperand(ANeuralNetworksModel *model,
+                                    const ANeuralNetworksOperandType *type)
+{
+  if ((model == nullptr) || (type == nullptr))
+  {
+    VERBOSE(NNAPI::Model) << "addOperand: Incorrect null pointer parameter(s)" << std::endl;
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  if (model->isFinished())
+  {
+    VERBOSE(NNAPI::Model) << "addOperand: Already finished" << std::endl;
+    return ANEURALNETWORKS_BAD_STATE;
+  }
+
+  // scale and zeroPoint should be zero for scalars and non-fixed point tensors
+  // Quantized:
+  //  scale: a 32 bit floating point value greater than zero
+  //  zeroPoint: a 32 bit integer, in range [0, 255]
+  if (type->type == ANEURALNETWORKS_TENSOR_QUANT8_ASYMM)
+  {
+    if (!(type->scale > 0.0f))
+    {
+      VERBOSE(NNAPI::Model) << "addOperand: Incorrect scale value for quantization" << std::endl;
+      return ANEURALNETWORKS_BAD_DATA;
+    }
+
+    if ((type->zeroPoint < 0) || (type->zeroPoint > 255))
+    {
+      VERBOSE(NNAPI::Model) << "addOperand: Incorrect zeroPoint value for quantization"
+                            << std::endl;
+      return ANEURALNETWORKS_BAD_DATA;
+    }
+  }
+  // NOTE Validation of scale and zeroPoint would be skipped for a while.
+  //      We do not know whether scalar type can have scale and zeroPoint.
+  //      To pass ValidationTest and GeneratedTest, this validation code
+  //      would not be implemented until we can define this issue clearly.
+  //
+  // scale and zeroPoint should be zero for scalars and non-fixed point tensors
+  // else if ((type->scale != 0.0f) || (type->zeroPoint != 0))
+  // {
+  //   return ANEURALNETWORKS_BAD_DATA;
+  // }
+
+  // dimensionCount should be zero for scalars
+  if ((type->dimensionCount != 0) &&
+      ((type->type == ANEURALNETWORKS_FLOAT32) || (type->type == ANEURALNETWORKS_INT32) ||
+       (type->type == ANEURALNETWORKS_UINT32)))
+  {
+    VERBOSE(NNAPI::Model) << "addOperand: Incorrect data type" << std::endl;
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  if (!model->addOperand(type))
+  {
+    VERBOSE(NNAPI::Model) << "addOperand: Fail to add operand" << std::endl;
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksModel_setOperandValue(ANeuralNetworksModel *model, int32_t index,
+                                         const void *buffer, size_t length)
+{
+  const bool optional_operand = ((buffer == nullptr) && (length == 0));
+
+  if ((model == nullptr) || ((buffer == nullptr) && (length != 0)))
+  {
+    VERBOSE(NNAPI::Model) << "setOperandValue: Incorrect null pointer parameter(s)" << std::endl;
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  if (model->isFinished())
+  {
+    VERBOSE(NNAPI::Model) << "setOperandValue: Already finished" << std::endl;
+    return ANEURALNETWORKS_BAD_STATE;
+  }
+
+  // Negative index value is not allowed
+  if (index < 0)
+  {
+    VERBOSE(NNAPI::Model) << "setOperandValue: Invalid index value (negative)" << std::endl;
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+  // NOTE OperandIndex uses uint32_t as its underlying type as various NNAPI
+  //      functions such as ANeuralNetworksModel_addOperation use uint32_t to represent operand
+  //      index
+  //      ANeuralNetworksModel_setOperandValue, however, uses int32_t to represent operand index.
+  //
+  //      Below, static_cast<uint32_t>(...) is introduced to eliminate compiler warning.
+  uint32_t ind = static_cast<uint32_t>(index);
+
+  if (!model->isExistOperand(ind))
+  {
+    VERBOSE(NNAPI::Model) << "setOperandValue: Invalid index value (not exist)" << std::endl;
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  if (!optional_operand && (model->operandSize(ind) != length))
+  {
+    VERBOSE(NNAPI::Model) << "setOperandValue: Invalid data length" << std::endl;
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  if (model->isUsageSet(ind))
+  {
+    VERBOSE(NNAPI::Model) << "setOperandValue: Already set operand" << std::endl;
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  // NNAPI spec in NeuralNetworks.h
+  // For values of length greater than ANEURALNETWORKS_MAX_SIZE_OF_IMMEDIATELY_COPIED_VALUES,
+  // the application is responsible for not changing the content of this region
+  // until all executions using this model have completed
+  bool copy_value = false;
+  if (length <= ANEURALNETWORKS_MAX_SIZE_OF_IMMEDIATELY_COPIED_VALUES)
+  {
+    copy_value = true;
+  }
+
+  if (!model->setOperandValue(ind, buffer, length, optional_operand, copy_value))
+  {
+    VERBOSE(NNAPI::Model) << "setOperandValue: Fail to set operand value" << std::endl;
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksModel_setOperandValueFromMemory(ANeuralNetworksModel *model, int32_t index,
+                                                   const ANeuralNetworksMemory *memory,
+                                                   size_t offset, size_t length)
+{
+  if ((model == nullptr) || (memory == nullptr))
+  {
+    VERBOSE(NNAPI::Model) << "setOperandValueFromMemory: Incorrect null pointer parameter(s)"
+                          << std::endl;
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  if (model->isFinished())
+  {
+    VERBOSE(NNAPI::Model) << "setOperandValueFromMemory: Already finished" << std::endl;
+    return ANEURALNETWORKS_BAD_STATE;
+  }
+
+  // Negative index value is not allowed
+  if (index < 0)
+  {
+    VERBOSE(NNAPI::Model) << "setOperandValueFromMemory: Invalid index value (negative)"
+                          << std::endl;
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+  // NOTE OperandIndex uses uint32_t as its underlying type as various NNAPI
+  //      functions such as ANeuralNetworksModel_addOperation use uint32_t to represent operand
+  //      index
+  //      ANeuralNetworksModel_setOperandValue, however, uses int32_t to represent operand index.
+  //
+  //      Below, static_cast<uint32_t>(...) is introduced to eliminate compiler warning.
+  uint32_t ind = static_cast<uint32_t>(index);
+
+  if (!model->isExistOperand(ind))
+  {
+    VERBOSE(NNAPI::Model) << "setOperandValueFromMemory: Invalid index value (not exist)"
+                          << std::endl;
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  if ((model->operandSize(ind) != length) || (memory->size() < (offset + length)))
+  {
+    VERBOSE(NNAPI::Model) << "setOperandValueFromMemory: Invalid data length" << std::endl;
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  if (model->isUsageSet(ind))
+  {
+    VERBOSE(NNAPI::Model) << "setOperandValueFromMemory: Already set operand" << std::endl;
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  if (!model->setOperandValue(ind, memory->base() + offset, length))
+  {
+    VERBOSE(NNAPI::Model) << "setOperandValueFromMemory: Fail to set operand value" << std::endl;
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksModel_addOperation(ANeuralNetworksModel *model,
+                                      ANeuralNetworksOperationType type, uint32_t inputCount,
+                                      const uint32_t *inputs, uint32_t outputCount,
+                                      const uint32_t *outputs)
+{
+  if ((model == nullptr) || (inputs == nullptr) || (outputs == nullptr))
+  {
+    VERBOSE(NNAPI::Model) << "addOperation: Incorrect null pointer parameter(s)" << std::endl;
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  if (model->isFinished())
+  {
+    VERBOSE(NNAPI::Model) << "addOperation: Already finished" << std::endl;
+    return ANEURALNETWORKS_BAD_STATE;
+  }
+
+  const ANeuralNetworksOperationType FIRST_OPERATION = ANEURALNETWORKS_ADD;
+  const ANeuralNetworksOperationType LAST_OPERATION = ANEURALNETWORKS_RESIZE_NEAREST_NEIGHBOR;
+  if ((type < FIRST_OPERATION) || (type > LAST_OPERATION))
+  {
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  for (uint32_t i = 0; i < outputCount; i++)
+  {
+    if (model->isUsageSet(outputs[i]))
+    {
+      VERBOSE(NNAPI::Model) << "addOperation: Already set output operand" << std::endl;
+      return ANEURALNETWORKS_BAD_DATA;
+    }
+  }
+
+  if (!model->addOperation(type, inputCount, inputs, outputCount, outputs))
+  {
+    VERBOSE(NNAPI::Model) << "addOperation: Fail to add operation" << std::endl;
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksModel_addOperationEx(ANeuralNetworksModel *model,
+                                        ANeuralNetworksOperationTypeEx type, uint32_t inputCount,
+                                        const uint32_t *inputs, uint32_t outputCount,
+                                        const uint32_t *outputs)
+{
+  if ((model == nullptr) || (inputs == nullptr) || (outputs == nullptr))
+  {
+    VERBOSE(NNAPI::Model) << "addOperation: Incorrect null pointer parameter(s)" << std::endl;
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  if (model->isFinished())
+  {
+    VERBOSE(NNAPI::Model) << "addOperation: Already finished" << std::endl;
+    return ANEURALNETWORKS_BAD_STATE;
+  }
+
+  const ANeuralNetworksOperationTypeEx FIRST_OPERATION = ANEURALNETWORKS_CAST_EX;
+  const ANeuralNetworksOperationTypeEx LAST_OPERATION = ANEURALNETWORKS_LESS_EX;
+  if ((type < FIRST_OPERATION) || (type > LAST_OPERATION))
+  {
+    VERBOSE(NNAPI::Model) << "addOperation: Invalid operation type" << std::endl;
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  for (uint32_t i = 0; i < outputCount; i++)
+  {
+    if (model->isUsageSet(outputs[i]))
+    {
+      VERBOSE(NNAPI::Model) << "addOperation: Already set output operand" << std::endl;
+      return ANEURALNETWORKS_BAD_DATA;
+    }
+  }
+
+  if (!model->addOperationEx(type, inputCount, inputs, outputCount, outputs))
+  {
+    VERBOSE(NNAPI::Model) << "addOperation: Fail to add operation" << std::endl;
+    return ANEURALNETWORKS_BAD_DATA;
+  }
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksModel_identifyInputsAndOutputs(ANeuralNetworksModel *model, uint32_t inputCount,
+                                                  const uint32_t *inputs, uint32_t outputCount,
+                                                  const uint32_t *outputs)
+{
+  if ((model == nullptr) || (inputs == nullptr) || (outputs == nullptr))
+  {
+    VERBOSE(NNAPI::Model) << "identifyInputsAndOutputs: Incorrect null pointer parameter(s)"
+                          << std::endl;
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  if (model->isFinished())
+  {
+    VERBOSE(NNAPI::Model) << "identifyInputsAndOutputs: Already finished" << std::endl;
+    return ANEURALNETWORKS_BAD_STATE;
+  }
+
+  for (uint32_t n = 0; n < inputCount; ++n)
+  {
+    uint32_t ind = inputs[n];
+    if (model->isUsageSet(ind))
+    {
+      VERBOSE(NNAPI::Model) << "identifyInputsAndOutputs: Already set input operand" << std::endl;
+      return ANEURALNETWORKS_BAD_DATA;
+    }
+
+    if (!model->addModelInput(ind))
+    {
+      VERBOSE(NNAPI::Model) << "identifyInputsAndOutputs: Fail to add input" << std::endl;
+      return ANEURALNETWORKS_BAD_DATA;
+    }
+  }
+
+  for (uint32_t n = 0; n < outputCount; ++n)
+  {
+    uint32_t ind = outputs[n];
+
+    if (!model->isOperationOutput(ind))
+    {
+      VERBOSE(NNAPI::Model) << "identifyInputsAndOutputs: Need to set output operand" << std::endl;
+      return ANEURALNETWORKS_BAD_DATA;
+    }
+
+    if (!model->addModelOutput(ind))
+    {
+      VERBOSE(NNAPI::Model) << "identifyInputsAndOutputs: Fail to add output" << std::endl;
+      return ANEURALNETWORKS_BAD_DATA;
+    }
+  }
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksModel_finish(ANeuralNetworksModel *model)
+{
+  if (model == nullptr)
+  {
+    VERBOSE(NNAPI::Model) << "finish: Incorrect null pointer parameter" << std::endl;
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  if (model->isFinished())
+  {
+    VERBOSE(NNAPI::Model) << "finish: Already finished" << std::endl;
+    return ANEURALNETWORKS_BAD_STATE;
+  }
+
+  if (!model->finish())
+  {
+    VERBOSE(NNAPI::Model) << "finish: Fail to generate internal graph" << std::endl;
+    return ANEURALNETWORKS_BAD_STATE;
+  }
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
+
+int ANeuralNetworksModel_relaxComputationFloat32toFloat16(ANeuralNetworksModel *model, bool)
+{
+  if (model == nullptr)
+  {
+    VERBOSE(NNAPI::Model) << "relaxComputationFloat32toFloat16: Incorrect null pointer parameter"
+                          << std::endl;
+    return ANEURALNETWORKS_UNEXPECTED_NULL;
+  }
+
+  // NYI: nothing to set
+  VERBOSE(NNAPI::Model) << "relaxComputationFloat32toFloat16: Do nothing yet" << std::endl;
+
+  return ANEURALNETWORKS_NO_ERROR;
+}
diff --git a/runtime/neurun/frontend/nnapi/wrapper/ANeuralNetworksCompilation.cc b/runtime/neurun/frontend/nnapi/wrapper/ANeuralNetworksCompilation.cc
new file mode 100644
index 000000000..1aa1583aa
--- /dev/null
+++ b/runtime/neurun/frontend/nnapi/wrapper/ANeuralNetworksCompilation.cc
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ANeuralNetworksCompilation.h"
+
+#include "util/logging.h"
+
+ANeuralNetworksCompilation::ANeuralNetworksCompilation(
+    const std::shared_ptr<neurun::ir::Graph> &model) noexcept
+    : _compiler{new neurun::compiler::Compiler{model}}
+{
+  // DO NOTHING
+}
+
+bool ANeuralNetworksCompilation::finish() noexcept
+{
+  try
+  {
+    _compiler->compile();
+  }
+  catch (const std::exception &e)
+  {
+    VERBOSE(EXCEPTION) << e.what() << std::endl;
+
+    return false;
+  }
+
+  return true;
+}
diff --git a/runtime/neurun/frontend/nnapi/wrapper/ANeuralNetworksCompilation.h b/runtime/neurun/frontend/nnapi/wrapper/ANeuralNetworksCompilation.h
new file mode 100644
index 000000000..56b402d16
--- /dev/null
+++ b/runtime/neurun/frontend/nnapi/wrapper/ANeuralNetworksCompilation.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __COMPILATION_H__
+#define __COMPILATION_H__
+
+#include "compiler/Compiler.h"
+#include "ir/Graph.h"
+#include "exec/IExecutor.h"
+
+struct ANeuralNetworksCompilation
+{
+public:
+  ANeuralNetworksCompilation(const std::shared_ptr<neurun::ir::Graph> &graph) noexcept;
+
+public:
+  bool finish() noexcept;
+
+  neurun::compiler::State state(void) noexcept { return _compiler->state(); }
+  void publish(std::shared_ptr<neurun::exec::IExecutor> &executor) noexcept
+  {
+    _compiler->release(executor);
+  }
+
+private:
+  std::shared_ptr<neurun::compiler::Compiler> _compiler;
+};
+
+#endif
diff --git a/runtime/neurun/frontend/nnapi/wrapper/ANeuralNetworksEvent.cc b/runtime/neurun/frontend/nnapi/wrapper/ANeuralNetworksEvent.cc
new file mode 100644
index 000000000..b09f9abe6
--- /dev/null
+++ b/runtime/neurun/frontend/nnapi/wrapper/ANeuralNetworksEvent.cc
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ANeuralNetworksEvent.h"
+
+#include "exec/Execution.h"
+#include "util/logging.h"
+
+ANeuralNetworksEvent::ANeuralNetworksEvent(
+    const std::shared_ptr<neurun::exec::Execution> &execution)
+    : _execution{execution}
+{
+  // DO NOTHING
+}
+
+bool ANeuralNetworksEvent::waitFinish(void) noexcept
+{
+  try
+  {
+    _execution->waitFinish();
+  }
+  catch (const std::exception &e)
+  {
+    VERBOSE(EXCEPTION) << e.what() << std::endl;
+
+    return false;
+  }
+
+  return true;
+}
diff --git a/runtime/neurun/frontend/nnapi/wrapper/ANeuralNetworksEvent.h b/runtime/neurun/frontend/nnapi/wrapper/ANeuralNetworksEvent.h
new file mode 100644
index 000000000..e499bab77
--- /dev/null
+++ b/runtime/neurun/frontend/nnapi/wrapper/ANeuralNetworksEvent.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __EVENT_H__
+#define __EVENT_H__
+
+#include <NeuralNetworks.h>
+
+#include <memory>
+
+namespace neurun
+{
+namespace exec
+{
+class Execution;
+} // namespace exec
+} // namespace neurun
+
+struct ANeuralNetworksEvent
+{
+public:
+  ANeuralNetworksEvent(const std::shared_ptr<neurun::exec::Execution> &execution);
+
+public:
+  bool waitFinish(void) noexcept;
+
+private:
+  const std::shared_ptr<neurun::exec::Execution> _execution;
+};
+
+#endif
diff --git a/runtime/neurun/frontend/nnapi/wrapper/ANeuralNetworksExecution.cc b/runtime/neurun/frontend/nnapi/wrapper/ANeuralNetworksExecution.cc
new file mode 100644
index 000000000..b8e43a691
--- /dev/null
+++ b/runtime/neurun/frontend/nnapi/wrapper/ANeuralNetworksExecution.cc
@@ -0,0 +1,289 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ANeuralNetworksExecution.h"
+#include "NNAPIConvert.h"
+#include "util/logging.h"
+
+const neurun::ir::OperandIndex
+ANeuralNetworksExecution::getInputOperandIndex(int32_t index) noexcept
+{
+  if (index < 0)
+  {
+    // Negative index: return invalid index
+    return neurun::ir::OperandIndex{};
+  }
+
+  uint32_t cast_index = static_cast<uint32_t>(index);
+  if (cast_index >= _execution->graph().getInputs().size())
+  {
+    // Return invalid index
+    return neurun::ir::OperandIndex{};
+  }
+
+  neurun::ir::IOIndex input_index{cast_index};
+  const auto operand_index = _execution->graph().getInputs().at(input_index);
+  return operand_index;
+}
+
+const neurun::ir::OperandIndex
+ANeuralNetworksExecution::getOutputOperandIndex(int32_t index) noexcept
+{
+  if (index < 0)
+  {
+    // Negative index: return invalid index
+    return neurun::ir::OperandIndex{};
+  }
+
+  uint32_t cast_index = static_cast<uint32_t>(index);
+  if (cast_index >= _execution->graph().getOutputs().size())
+  {
+    // Return invalid index
+    return neurun::ir::OperandIndex{};
+  }
+
+  neurun::ir::IOIndex output_index{cast_index};
+  const auto operand_index = _execution->graph().getOutputs().at(output_index);
+  return operand_index;
+}
+
+bool ANeuralNetworksExecution::compareDataType(const ANeuralNetworksOperandType *type,
+                                               const neurun::ir::OperandIndex index) noexcept
+{
+  try
+  {
+    const auto operand_type = _execution->graph().operands().at(index).typeInfo();
+    const auto typeInfo = NNAPIConvert::getTypeInfo(type);
+
+    if (operand_type != typeInfo)
+    {
+      // Data type mismatch
+      return false;
+    }
+  }
+  catch (const std::exception &e)
+  {
+    VERBOSE(EXCEPTION) << e.what() << std::endl;
+
+    return false;
+  }
+
+  return true;
+}
+
+bool ANeuralNetworksExecution::compareShape(const ANeuralNetworksOperandType *type,
+                                            const neurun::ir::OperandIndex index) noexcept
+{
+  // Passed shape should be specified
+  if (haveUnspecifiedDims(index))
+  {
+    return false;
+  }
+
+  const auto &operand_shape = _execution->graph().operands().at(index).shape();
+  const auto &shape_from_type = NNAPIConvert::getShape(type);
+
+  return operand_shape == shape_from_type;
+}
+
+bool ANeuralNetworksExecution::haveUnspecifiedDims(const neurun::ir::OperandIndex index) noexcept
+{
+  const auto operand_shape = _execution->graph().operands().at(index).shape();
+
+  return operand_shape.num_elements() == 0;
+}
+
+size_t ANeuralNetworksExecution::getOperandSize(const neurun::ir::OperandIndex index) noexcept
+{
+  try
+  {
+    return _execution->graph().operands().at(index).operandSize();
+  }
+  catch (const std::exception &e)
+  {
+    VERBOSE(EXCEPTION) << e.what() << std::endl;
+
+    return 0;
+  }
+}
+
+bool ANeuralNetworksExecution::setInput(uint32_t index, const ANeuralNetworksOperandType *type,
+                                        const void *buffer, size_t length) noexcept
+{
+  try
+  {
+    neurun::ir::IOIndex input_index{index};
+    const auto operand_index = getInputOperandIndex(index);
+
+    const auto type_info = _execution->graph().operands().at(operand_index).typeInfo();
+    const auto shape = (type != nullptr) ? NNAPIConvert::getShape(type)
+                                         : _execution->graph().operands().at(operand_index).shape();
+
+    // NOTE The nnapi does not provide setting io_layout and not support changing layout. In other
+    // words, we can assume that io_layout from nnapi always is the same as layout of the used
+    // model.
+    // TODO Set layout of model
+    _execution->setInput(input_index, type_info, shape, buffer, length, neurun::ir::Layout::NHWC);
+  }
+  catch (const std::exception &e)
+  {
+    VERBOSE(EXCEPTION) << e.what() << std::endl;
+
+    return false;
+  }
+
+  return true;
+}
+
+bool ANeuralNetworksExecution::setOutput(uint32_t index, const ANeuralNetworksOperandType *type,
+                                         void *buffer, size_t length) noexcept
+{
+  try
+  {
+    neurun::ir::IOIndex output_index{index};
+    const auto operand_index = getOutputOperandIndex(index);
+
+    const auto type_info = _execution->graph().operands().at(operand_index).typeInfo();
+    const auto shape = (type != nullptr) ? NNAPIConvert::getShape(type)
+                                         : _execution->graph().operands().at(operand_index).shape();
+
+    // NOTE The nnapi does not provide setting io_layout and not support changing layout. In other
+    // words, we can assume that io_layout from nnapi always is the same as layout of the used
+    // model.
+    // TODO Set layout of model
+    _execution->setOutput(output_index, type_info, shape, buffer, length, neurun::ir::Layout::NHWC);
+  }
+  catch (const std::exception &e)
+  {
+    VERBOSE(EXCEPTION) << e.what() << std::endl;
+
+    return false;
+  }
+
+  return true;
+}
+
+bool ANeuralNetworksExecution::startExecute(void) noexcept
+{
+  try
+  {
+    _execution->startExecute();
+  }
+  catch (const std::exception &e)
+  {
+    VERBOSE(EXCEPTION) << e.what() << std::endl;
+
+    return false;
+  }
+
+  return true;
+}
+
+bool ANeuralNetworksExecution::execute(void) noexcept
+{
+  try
+  {
+    _execution->execute();
+  }
+  catch (const std::exception &e)
+  {
+    VERBOSE(EXCEPTION) << e.what() << std::endl;
+
+    return false;
+  }
+
+  return true;
+}
+
+const std::shared_ptr<neurun::exec::Execution> ANeuralNetworksExecution::instance(void) noexcept
+{
+  return _execution;
+}
+
+bool ANeuralNetworksExecution::getOutputOperandRank(uint32_t index, uint32_t *rank) noexcept
+{
+  try
+  {
+    neurun::ir::IOIndex output_index{index};
+    const auto operand_index = getOutputOperandIndex(index);
+    bool unspecified = haveUnspecifiedDims(operand_index);
+
+    // TODO Get unspecified output operand's rank
+    if (unspecified)
+    {
+      throw std::runtime_error{"Unsupport feature"};
+    }
+
+    // Check execution is finished
+    // Output rank and shape may be decided after execution if output is unspecified operand
+    if (!_execution->isFinished())
+    {
+      return false;
+    }
+
+    *rank = _execution->graph().operands().at(operand_index).shape().rank();
+  }
+  catch (const std::exception &e)
+  {
+    VERBOSE(EXCEPTION) << e.what() << std::endl;
+
+    return false;
+  }
+
+  return true;
+}
+
+bool ANeuralNetworksExecution::getOutputOperandDimensions(uint32_t index, uint32_t *dimensions)
+{
+  try
+  {
+    neurun::ir::IOIndex output_index{index};
+    const auto operand_index = getOutputOperandIndex(index);
+    bool unspecified = haveUnspecifiedDims(operand_index);
+    if (unspecified)
+    {
+      throw std::runtime_error{"NYI: Models with unspecified output dimensions"};
+    }
+
+    // Check execution is finished
+    // Output rank and shape may be decided after execution if output is unspecified operand
+    if (!_execution->isFinished())
+    {
+      return false;
+    }
+
+    auto shape = _execution->graph().operands().at(operand_index).shape();
+    for (int i = 0; i < shape.rank(); i++)
+    {
+      auto dim = shape.dim(i);
+
+      if (dim <= 0)
+      {
+        throw std::runtime_error{"Invalid dimension value"};
+      }
+
+      dimensions[i] = static_cast<uint32_t>(dim);
+    }
+  }
+  catch (const std::exception &e)
+  {
+    VERBOSE(EXCEPTION) << e.what() << std::endl;
+
+    return false;
+  }
+
+  return true;
+}
diff --git a/runtime/neurun/frontend/nnapi/wrapper/ANeuralNetworksExecution.h b/runtime/neurun/frontend/nnapi/wrapper/ANeuralNetworksExecution.h
new file mode 100644
index 000000000..ecffedc0a
--- /dev/null
+++ b/runtime/neurun/frontend/nnapi/wrapper/ANeuralNetworksExecution.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __EXECUTION_H__
+#define __EXECUTION_H__
+
+#include <NeuralNetworks.h>
+
+#include <memory>
+
+#include "exec/Execution.h"
+
+struct ANeuralNetworksExecution
+{
+public:
+  ANeuralNetworksExecution(const std::shared_ptr<neurun::exec::IExecutor> &executor)
+      : _execution{std::make_shared<neurun::exec::Execution>(executor)}
+  {
+    // DO NOTHING
+  }
+
+public:
+  bool setInput(uint32_t index, const ANeuralNetworksOperandType *type, const void *buffer,
+                size_t length) noexcept;
+  bool setOutput(uint32_t index, const ANeuralNetworksOperandType *type, void *buffer,
+                 size_t length) noexcept;
+  bool startExecute(void) noexcept;
+  bool execute(void) noexcept;
+
+  const neurun::ir::OperandIndex getInputOperandIndex(int32_t index) noexcept;
+  const neurun::ir::OperandIndex getOutputOperandIndex(int32_t index) noexcept;
+  bool compareDataType(const ANeuralNetworksOperandType *type,
+                       const neurun::ir::OperandIndex index) noexcept;
+  bool compareShape(const ANeuralNetworksOperandType *type,
+                    const neurun::ir::OperandIndex index) noexcept;
+  bool haveUnspecifiedDims(const neurun::ir::OperandIndex index) noexcept;
+  size_t getOperandSize(const neurun::ir::OperandIndex index) noexcept;
+  const std::shared_ptr<neurun::exec::Execution> instance(void) noexcept;
+
+  /**
+   * @brief       Get output operand's rank
+   * @param[in]   index Output index
+   * @param[out]  rank  Output operand's rank
+   * @return      @c true if success to get rank, otherwise @c false
+   */
+  bool getOutputOperandRank(uint32_t index, uint32_t *rank) noexcept;
+  /**
+   * @brief       Get dimensions of the output operand
+   * @param[in]   index Output index
+   * @param[out]  dimensions  Output operand's dimensions
+   * @return      @c true if success to get rank, otherwise @c false
+   * @note        This must be called after execution is finished to get resolved output shape
+   *              unspecified in model
+   */
+  bool getOutputOperandDimensions(uint32_t index, uint32_t *dimensions);
+
+private:
+  std::shared_ptr<neurun::exec::Execution> _execution;
+};
+
+#endif
diff --git a/runtime/neurun/frontend/nnapi/wrapper/ANeuralNetworksMemory.cc b/runtime/neurun/frontend/nnapi/wrapper/ANeuralNetworksMemory.cc
new file mode 100644
index 000000000..9cc100585
--- /dev/null
+++ b/runtime/neurun/frontend/nnapi/wrapper/ANeuralNetworksMemory.cc
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <NeuralNetworks.h>
+#include <sys/mman.h>
+
+#include "ANeuralNetworksMemory.h"
+
+//
+// ANeuralNetworksMemory
+//
+ANeuralNetworksMemory::ANeuralNetworksMemory(size_t size, int protect, int fd, size_t offset)
+{
+  _base = reinterpret_cast<uint8_t *>(mmap(nullptr, size, protect, MAP_PRIVATE, fd, offset));
+  _size = size;
+}
+
+ANeuralNetworksMemory::~ANeuralNetworksMemory() { munmap(reinterpret_cast<void *>(_base), _size); }
+
+bool ANeuralNetworksMemory::vaildAccess(size_t offset, size_t length) const
+{
+  if ((offset >= _size) || (length > _size))
+  {
+    return false;
+  }
+
+  if ((offset + length) >= _size)
+  {
+    return false;
+  }
+
+  return true;
+}
diff --git a/runtime/neurun/frontend/nnapi/wrapper/ANeuralNetworksMemory.h b/runtime/neurun/frontend/nnapi/wrapper/ANeuralNetworksMemory.h
new file mode 100644
index 000000000..48a1bc5fc
--- /dev/null
+++ b/runtime/neurun/frontend/nnapi/wrapper/ANeuralNetworksMemory.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MEMORY_H__
+#define __MEMORY_H__
+
+#include <cstdint>
+
+struct ANeuralNetworksMemory
+{
+public:
+  ANeuralNetworksMemory(size_t size, int protect, int fd, size_t offset);
+  ~ANeuralNetworksMemory();
+
+public:
+  size_t size(void) const { return _size; }
+  uint8_t *base(void) { return _base; }
+  uint8_t *base(void) const { return _base; }
+  bool vaildAccess(size_t offset, size_t length) const;
+
+private:
+  size_t _size;
+  uint8_t *_base;
+};
+
+#endif // __MEMORY_H__
diff --git a/runtime/neurun/frontend/nnapi/wrapper/ANeuralNetworksModel.cc b/runtime/neurun/frontend/nnapi/wrapper/ANeuralNetworksModel.cc
new file mode 100644
index 000000000..5542a2e83
--- /dev/null
+++ b/runtime/neurun/frontend/nnapi/wrapper/ANeuralNetworksModel.cc
@@ -0,0 +1,268 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ANeuralNetworksModel.h"
+#include "OperationFactory.h"
+#include "NNAPIConvert.h"
+
+#include "ir/Operations.Include.h"
+#include "util/logging.h"
+
+#include "cpp14/memory.h"
+
+//
+// ANeuralNetworksModel
+//
+ANeuralNetworksModel::ANeuralNetworksModel() noexcept : _optional_operands{}, _operand_usages{}
+{
+  _graph = std::make_shared<neurun::ir::Graph>();
+}
+
+bool ANeuralNetworksModel::addOperand(const ANeuralNetworksOperandType *type) noexcept
+{
+  try
+  {
+    const auto shape = NNAPIConvert::getShape(type);
+    const auto typeInfo = NNAPIConvert::getTypeInfo(type);
+    _graph->addOperand(shape, typeInfo);
+    _operand_usages.emplace_back(OperandUsage::NOT_DEFINED);
+  }
+  catch (const std::exception &e)
+  {
+    VERBOSE(EXCEPTION) << e.what() << std::endl;
+
+    return false;
+  }
+
+  return true;
+}
+
+bool ANeuralNetworksModel::setOperandValue(uint32_t index, const void *buffer, size_t length,
+                                           bool optional, bool copy) noexcept
+{
+  const neurun::ir::OperandIndex ind{index};
+
+  try
+  {
+    _operand_usages[index] = OperandUsage::CONSTANT;
+
+    // Remain operands.at(ind).data()->base() as nullptr for optional operand
+    // This will be filled when model finished
+    if (optional)
+    {
+      setOptionalOperand(ind);
+    }
+
+    using neurun::ir::CachedData;
+    using neurun::ir::ExternalData;
+    if (copy)
+    {
+      _graph->operands().at(ind).data(
+          nnfw::cpp14::make_unique<CachedData>(reinterpret_cast<const uint8_t *>(buffer), length));
+    }
+    else
+    {
+      _graph->operands().at(ind).data(nnfw::cpp14::make_unique<ExternalData>(
+          reinterpret_cast<const uint8_t *>(buffer), length));
+    }
+  }
+  catch (const std::exception &e)
+  {
+    VERBOSE(EXCEPTION) << e.what() << std::endl;
+
+    return false;
+  }
+
+  return true;
+}
+
+bool ANeuralNetworksModel::addOperation(ANeuralNetworksOperationType type, uint32_t inputCount,
+                                        const uint32_t *inputs, uint32_t outputCount,
+                                        const uint32_t *outputs) noexcept
+{
+  try
+  {
+    for (uint32_t i = 0; i < outputCount; i++)
+    {
+      _operand_usages[outputs[i]] = OperandUsage::OPERATION_OUTPUT;
+    }
+
+    auto &factory = OperationFactory::get();
+    OperationFactory::Param param{inputCount, inputs, outputCount, outputs};
+
+    auto node = factory.create(type, param, _graph->operands());
+    _graph->addOperation(std::unique_ptr<neurun::ir::Operation>{node});
+
+    // TODO Move these codes to delegate.cpp
+    if (type == ANEURALNETWORKS_FULLY_CONNECTED)
+    {
+      const auto &input_operand =
+          _graph->operands().at(node->getInputs().at(neurun::ir::operation::FullyConnected::INPUT));
+      auto &weights_operand = _graph->operands().at(
+          node->getInputs().at(neurun::ir::operation::FullyConnected::WEIGHT));
+      if (input_operand.typeInfo().type() == neurun::ir::DataType::FLOAT32 &&
+          weights_operand.typeInfo().type() == neurun::ir::DataType::QUANT8_ASYMM)
+      {
+        weights_operand.type(neurun::ir::DataType::QUANT8_SYMM);
+      }
+    }
+  }
+  catch (const std::exception &e)
+  {
+    VERBOSE(EXCEPTION) << e.what() << std::endl;
+
+    return false;
+  }
+
+  return true;
+}
+
+bool ANeuralNetworksModel::addOperationEx(ANeuralNetworksOperationTypeEx type, uint32_t inputCount,
+                                          const uint32_t *inputs, uint32_t outputCount,
+                                          const uint32_t *outputs) noexcept
+{
+  try
+  {
+    for (uint32_t i = 0; i < outputCount; i++)
+    {
+      _operand_usages[outputs[i]] = OperandUsage::OPERATION_OUTPUT;
+    }
+
+    auto &factory = OperationFactory::get();
+    OperationFactory::Param param{inputCount, inputs, outputCount, outputs};
+
+    auto node = factory.create(type, param, _graph->operands());
+    _graph->addOperation(std::unique_ptr<neurun::ir::Operation>{node});
+  }
+  catch (const std::exception &e)
+  {
+    return false;
+  }
+  return true;
+}
+
+bool ANeuralNetworksModel::addModelInput(uint32_t index) noexcept
+{
+  try
+  {
+    _operand_usages[index] = OperandUsage::MODEL_INPUT;
+
+    const neurun::ir::OperandIndex ind{index};
+    _graph->addInput(ind);
+  }
+  catch (const std::exception &e)
+  {
+    VERBOSE(EXCEPTION) << e.what() << std::endl;
+
+    return false;
+  }
+
+  return true;
+}
+bool ANeuralNetworksModel::addModelOutput(uint32_t index) noexcept
+{
+  try
+  {
+    const neurun::ir::OperandIndex ind{index};
+
+    // Duplicated output is not allowed
+    if (_graph->getOutputs().contains(ind))
+    {
+      return false;
+    }
+
+    _graph->addOutput(ind);
+  }
+  catch (const std::exception &e)
+  {
+    VERBOSE(EXCEPTION) << e.what() << std::endl;
+
+    return false;
+  }
+
+  return true;
+}
+
+bool ANeuralNetworksModel::finish() noexcept
+{
+  try
+  {
+    fillOptionalOperand();
+
+    _graph->finishBuilding();
+
+    _operand_usages.clear();
+  }
+  catch (const std::exception &e)
+  {
+    VERBOSE(EXCEPTION) << e.what() << '\n';
+
+    return false;
+  }
+
+  return true;
+}
+
+bool ANeuralNetworksModel::isFinished() noexcept { return !_graph->isBuildingPhase(); }
+
+bool ANeuralNetworksModel::isExistOperand(uint32_t index) noexcept
+{
+  return _graph->operands().exist(neurun::ir::OperandIndex{index});
+}
+
+size_t ANeuralNetworksModel::operandSize(uint32_t index) noexcept
+{
+  try
+  {
+    return _graph->operands().at(neurun::ir::OperandIndex{index}).operandSize();
+  }
+  catch (const std::exception &e)
+  {
+    VERBOSE(EXCEPTION) << e.what() << '\n';
+
+    return 0;
+  }
+}
+
+bool ANeuralNetworksModel::isUsageSet(uint32_t index) noexcept
+{
+  return (_operand_usages[index] != OperandUsage::NOT_DEFINED);
+}
+
+bool ANeuralNetworksModel::isOperationOutput(uint32_t index) noexcept
+{
+  return (_operand_usages[index] == OperandUsage::OPERATION_OUTPUT);
+}
+
+void ANeuralNetworksModel::setOptionalOperand(const neurun::ir::OperandIndex idx)
+{
+  _optional_operands.insert(idx);
+}
+
+void ANeuralNetworksModel::fillOptionalOperand(void)
+{
+  _graph->operations().iterate(
+      [&](const neurun::ir::OperationIndex &, neurun::ir::Operation &node) {
+        for (auto input : node.getInputs())
+        {
+          // TODO fill default value for optional operands
+          if (_optional_operands.find(input) != _optional_operands.end())
+          {
+            throw std::runtime_error{"Optional operand is not supported yet"};
+          }
+        }
+      });
+}
diff --git a/runtime/neurun/frontend/nnapi/wrapper/ANeuralNetworksModel.h b/runtime/neurun/frontend/nnapi/wrapper/ANeuralNetworksModel.h
new file mode 100644
index 000000000..d364ee39e
--- /dev/null
+++ b/runtime/neurun/frontend/nnapi/wrapper/ANeuralNetworksModel.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MODEL_H__
+#define __MODEL_H__
+
+#include <unordered_set>
+#include <NeuralNetworks.h>
+#include <NeuralNetworksEx.h>
+
+#include "ir/Graph.h"
+
+struct ANeuralNetworksModel
+{
+public:
+  enum class OperandUsage
+  {
+    NOT_DEFINED = 0,
+    MODEL_INPUT,
+    CONSTANT,
+    OPERATION_OUTPUT,
+  };
+
+public:
+  ANeuralNetworksModel() noexcept;
+
+public:
+  bool addOperand(const ANeuralNetworksOperandType *type) noexcept;
+  bool setOperandValue(uint32_t index, const void *buffer, size_t length, bool optional = false,
+                       bool copy = false) noexcept;
+  bool addOperation(ANeuralNetworksOperationType type, uint32_t inputCount, const uint32_t *inputs,
+                    uint32_t outputCount, const uint32_t *outputs) noexcept;
+  bool addOperationEx(ANeuralNetworksOperationTypeEx type, uint32_t inputCount,
+                      const uint32_t *inputs, uint32_t outputCount,
+                      const uint32_t *outputs) noexcept;
+  bool addModelInput(uint32_t index) noexcept;
+  bool addModelOutput(uint32_t index) noexcept;
+  bool finish() noexcept;
+
+  neurun::ir::Graph &deref(void) { return *_graph; }
+  bool isFinished() noexcept;
+  bool isExistOperand(uint32_t index) noexcept;
+  size_t operandSize(uint32_t index) noexcept;
+  bool isUsageSet(uint32_t index) noexcept;
+  bool isOperationOutput(uint32_t index) noexcept;
+  void release(std::shared_ptr<neurun::ir::Graph> &graph) { graph = _graph; }
+
+private:
+  void setOptionalOperand(const neurun::ir::OperandIndex idx);
+  void fillOptionalOperand(void);
+
+private:
+  std::shared_ptr<neurun::ir::Graph> _graph;
+  std::unordered_set<neurun::ir::OperandIndex> _optional_operands;
+  std::vector<OperandUsage> _operand_usages;
+};
+
+#endif // __MODEL_H__
diff --git a/runtime/neurun/frontend/nnapi/wrapper/NNAPIConvert.cc b/runtime/neurun/frontend/nnapi/wrapper/NNAPIConvert.cc
new file mode 100644
index 000000000..79589be75
--- /dev/null
+++ b/runtime/neurun/frontend/nnapi/wrapper/NNAPIConvert.cc
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "NNAPIConvert.h"
+
+#include <numeric>
+
+using namespace neurun::ir;
+
+DataType NNAPIConvert::getDataType(OperandCode type)
+{
+  switch (type)
+  {
+    case ANEURALNETWORKS_FLOAT32:
+    case ANEURALNETWORKS_TENSOR_FLOAT32:
+      return DataType::FLOAT32;
+    case ANEURALNETWORKS_INT32:
+    case ANEURALNETWORKS_TENSOR_INT32:
+      return DataType::INT32;
+    case ANEURALNETWORKS_UINT32:
+      return DataType::UINT32;
+    case ANEURALNETWORKS_TENSOR_QUANT8_ASYMM:
+      return DataType::QUANT8_ASYMM;
+    case ANEURALNETWORKS_TENSOR_QUANT8_SYMM:
+      return DataType::QUANT8_SYMM;
+    case ANEURALNETWORKS_BOOL:
+    case ANEURALNETWORKS_TENSOR_BOOL8:
+      return DataType::BOOL8;
+    default:
+      throw std::runtime_error("Unsupported type");
+  }
+}
+
+TypeInfo NNAPIConvert::getTypeInfo(const ANeuralNetworksOperandType *type)
+{
+  return TypeInfo(getDataType((OperandCode)(type->type)), type->scale, type->zeroPoint);
+}
+
+Shape NNAPIConvert::getShape(const ANeuralNetworksOperandType *type)
+{
+  Shape shape(type->dimensionCount);
+
+  for (uint32_t axis = 0; axis < type->dimensionCount; ++axis)
+  {
+    shape.dim(axis) = type->dimensions[axis];
+  }
+
+  return shape;
+}
+
+size_t NNAPIConvert::calculateSizeFromType(const ANeuralNetworksOperandType *type)
+{
+  auto shape = getShape(type);
+  auto data_type = getDataType((OperandCode)(type->type));
+
+  return shape.num_elements() * sizeOfDataType(data_type);
+}
+
+Activation NNAPIConvert::getFusedActivation(FuseCode act)
+{
+  switch (act)
+  {
+    case ANEURALNETWORKS_FUSED_NONE:
+      return Activation::NONE;
+    case ANEURALNETWORKS_FUSED_RELU:
+      return Activation::RELU;
+    case ANEURALNETWORKS_FUSED_RELU1:
+      return Activation::RELU1;
+    case ANEURALNETWORKS_FUSED_RELU6:
+      return Activation::RELU6;
+    default:
+      throw std::runtime_error("Unsupported activation type");
+  }
+}
+
+PaddingType NNAPIConvert::getPaddingType(PaddingCode type)
+{
+  switch (type)
+  {
+    case ANEURALNETWORKS_PADDING_SAME:
+      return PaddingType::SAME;
+    case ANEURALNETWORKS_PADDING_VALID:
+      return PaddingType::VALID;
+    default:
+      throw std::runtime_error("Unsupported type");
+  }
+}
diff --git a/runtime/neurun/frontend/nnapi/wrapper/NNAPIConvert.h b/runtime/neurun/frontend/nnapi/wrapper/NNAPIConvert.h
new file mode 100644
index 000000000..91f84b983
--- /dev/null
+++ b/runtime/neurun/frontend/nnapi/wrapper/NNAPIConvert.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file  NNAPIConvert.h
+ * @brief This file contains convereter(s)\n
+ *        from NNAPI frontend's struct to neurun's internal struct
+ */
+#ifndef __NEURUN_NNAPI_CONVERT_H__
+#define __NEURUN_NNAPI_CONVERT_H__
+
+#include <NeuralNetworks.h>
+
+#include <ir/TypeInfo.h>
+#include <ir/Shape.h>
+#include <ir/InternalType.h>
+
+class NNAPIConvert
+{
+
+public:
+  /**
+   * @brief     Convert data type from NNAPI to internal data type
+   * @param[in] type  NNAPI's data type
+   * @return    neurun's internal data type
+   */
+  static neurun::ir::DataType getDataType(OperandCode type);
+
+  /**
+   * @brief     Convert operand type info from NNAPI to interanl operand type info
+   * @param[in] type  NNAPI's operand type
+   * @return    neurun's internal operand type info
+   */
+  static neurun::ir::TypeInfo getTypeInfo(const ANeuralNetworksOperandType *type);
+
+  /**
+   * @brief     Convert operand shape info from NNAPI to internal operand shape
+   * @param[in] type  NNAPI's operand type
+   * @return    neurun's internal operand shape
+   */
+  static neurun::ir::Shape getShape(const ANeuralNetworksOperandType *type);
+
+  /**
+   * @brief     Calcaulate operand size from NNAPI type
+   * @param[in] type  NNAPI's operand type
+   * @return    Operand size
+   */
+  static size_t calculateSizeFromType(const ANeuralNetworksOperandType *type);
+
+  /**
+   * @brief     Convert NNAPI FuseCode to internal activation type
+   * @param[in] act NNAPI's FuseCode type
+   * @return    neurun's internal activation type
+   */
+  static neurun::ir::Activation getFusedActivation(FuseCode act);
+
+  /**
+   * @brief     Convert NNAPI PaddingCode to internal padding type
+   * @param[in] type NNAPI's PaddingCode type
+   * @return    neurun's internal padding type
+   */
+  static neurun::ir::PaddingType getPaddingType(PaddingCode type);
+};
+
+#endif // __NEURUN_NNAPI_CONVERT_H__
diff --git a/runtime/neurun/frontend/nnapi/wrapper/OperationFactory.cc b/runtime/neurun/frontend/nnapi/wrapper/OperationFactory.cc
new file mode 100644
index 000000000..84f876e86
--- /dev/null
+++ b/runtime/neurun/frontend/nnapi/wrapper/OperationFactory.cc
@@ -0,0 +1,1680 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "OperationFactory.h"
+#include "NNAPIConvert.h"
+
+#include <ir/Operations.Include.h>
+#include <string.h>
+
+namespace
+{
+using namespace neurun::ir;
+
+void replaceDataType(Operands &operands, const OperandIndex &index, const DataType type)
+{
+  assert(operands.exist(index));
+  operands.at(index).type(type);
+}
+
+ExplicitPadding makeExplicitPadding(Operands &operands, const OperandIndex &left_index,
+                                    const OperandIndex &right_index, const OperandIndex &top_index,
+                                    const OperandIndex &bottom_index)
+{
+  auto left = operands.at(left_index).asScalar<int32_t>();
+  auto right = operands.at(right_index).asScalar<int32_t>();
+  auto top = operands.at(top_index).asScalar<int32_t>();
+  auto bottom = operands.at(bottom_index).asScalar<int32_t>();
+
+  if (left < 0 || right < 0 || top < 0 || bottom < 0)
+  {
+    throw std::runtime_error{"Cannot handle negative explicit padding value"};
+  }
+
+  ExplicitPadding param;
+  param.left = static_cast<uint32_t>(left);
+  param.right = static_cast<uint32_t>(right);
+  param.top = static_cast<uint32_t>(top);
+  param.bottom = static_cast<uint32_t>(bottom);
+
+  return param;
+}
+
+Stride makeStride(Operands &operands, const OperandIndex &horizontal_index,
+                  const OperandIndex &vertical_index)
+{
+  auto horizontal = operands.at(horizontal_index).asScalar<int32_t>();
+  auto vertical = operands.at(vertical_index).asScalar<int32_t>();
+
+  if (vertical < 0 || horizontal < 0)
+  {
+    throw std::runtime_error{"Cannot handle negative stride value"};
+  }
+
+  Stride stride;
+  stride.horizontal = static_cast<uint32_t>(horizontal);
+  stride.vertical = static_cast<uint32_t>(vertical);
+
+  return stride;
+}
+
+uint32_t getUint32Scalar(Operands &operands, const OperandIndex index)
+{
+  auto int32_value = operands.at(index).asScalar<int32_t>();
+  if (int32_value < 0)
+  {
+    throw std::runtime_error{"Cannot handle negative value"};
+  }
+
+  return static_cast<uint32_t>(int32_value);
+}
+
+} // namespace
+
+OperationFactory &OperationFactory::get()
+{
+  static OperationFactory factory;
+  return factory;
+}
+
+OperationFactory::OperationFactory()
+{
+  _map[ANEURALNETWORKS_BATCH_TO_SPACE_ND] = [](const OperationFactory::Param &init_param,
+                                               Operands &) {
+    assert(init_param.input_count == 2 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> Input Tensor Index
+    //  1 -> Block size Index
+    OperandIndexSequence inputs{init_param.inputs[0], init_param.inputs[1]};
+
+    return new operation::BatchToSpaceND{inputs, outputs};
+  };
+
+  _map[ANEURALNETWORKS_DEPTHWISE_CONV_2D] = [](const OperationFactory::Param &init_param,
+                                               Operands &operands) {
+    assert((init_param.input_count == 8 || init_param.input_count == 11) &&
+           init_param.output_count == 1);
+
+    // In common
+    // 0 -> IFM Tensor Index
+    // 1 -> Kernel Tensor Index
+    // 2 -> Bias Tensor Index
+    OperandIndexSequence inputs{init_param.inputs[0], init_param.inputs[1], init_param.inputs[2]};
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    operation::DepthwiseConv2D::Param param;
+    if (init_param.input_count == 8)
+    {
+      // Imlicit Padding case
+      // Each input should be interpreted as follows:
+      //
+      // 3 -> Padding Code (ANEURALNETWORKS_PADDING_SAME or ANEURALNETWORKS_PADDING_VALID) Index
+      // 4 -> Stride (width) Index
+      // 5 -> Stride (height) INdex
+      // 6 -> Depthwise multiplier
+      // 7 -> Activation Index
+
+      const auto padding_index = OperandIndex{init_param.inputs[3]};
+      const auto hstride_index = OperandIndex{init_param.inputs[4]};
+      const auto vstride_index = OperandIndex{init_param.inputs[5]};
+      const auto multiplier_index = OperandIndex{init_param.inputs[6]};
+      const auto activation_index = OperandIndex{init_param.inputs[7]};
+
+      param.padding.type =
+          NNAPIConvert::getPaddingType(operands.at(padding_index).asScalar<PaddingCode>());
+      param.stride = makeStride(operands, hstride_index, vstride_index);
+      param.multiplier = getUint32Scalar(operands, multiplier_index);
+      param.activation =
+          NNAPIConvert::getFusedActivation(operands.at(activation_index).asScalar<FuseCode>());
+    }
+    else
+    {
+      // Explicit Padding case
+      // Each input should be interpreted as follows:
+      //
+      // 3 -> Padding On the Left
+      // 4 -> Padding On the Right
+      // 5 -> Padding On the Top
+      // 6 -> Padding On the Bottom
+      // 7 -> Stride (width) Index
+      // 8 -> Stride (height) Index
+      // 9 -> Depthwise multiplier
+      // 10-> Activation Index
+
+      const auto padding_left_index = OperandIndex{init_param.inputs[3]};
+      const auto padding_right_index = OperandIndex{init_param.inputs[4]};
+      const auto padding_top_index = OperandIndex{init_param.inputs[5]};
+      const auto padding_bottom_index = OperandIndex{init_param.inputs[6]};
+      const auto hstride_index = OperandIndex{init_param.inputs[7]};
+      const auto vstride_index = OperandIndex{init_param.inputs[8]};
+      const auto multiplier_index = OperandIndex{init_param.inputs[9]};
+      const auto activation_index = OperandIndex{init_param.inputs[10]};
+
+      param.padding.type = PaddingType::EXPLICIT;
+      param.padding.param = makeExplicitPadding(operands, padding_left_index, padding_right_index,
+                                                padding_top_index, padding_bottom_index);
+      param.stride = makeStride(operands, hstride_index, vstride_index);
+      param.multiplier = getUint32Scalar(operands, multiplier_index);
+      param.activation =
+          NNAPIConvert::getFusedActivation(operands.at(activation_index).asScalar<FuseCode>());
+    }
+
+    return new operation::DepthwiseConv2D{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_MAX_POOL_2D] = [](const OperationFactory::Param &init_param,
+                                         Operands &operands) {
+    assert(init_param.input_count == 7 || init_param.input_count == 10);
+    assert(init_param.output_count == 1);
+
+    // In common
+    //  0 -> IFM Tensor Index
+    OperandIndexSequence inputs{init_param.inputs[0]};
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    operation::MaxPool2D::Param param;
+    if (init_param.input_count == 7) // support implicit padding
+    {
+      // Each input should be interpreted as follows:
+      //
+      //  1 -> Padding Code (ANEURALNETWORKS_PADDING_SAME or ANEURALNETWORKS_PADDING_VALID) Index
+      //  2 -> Horizontal (over width) Stride Index
+      //  3 -> Vertial (over height) Stride Index
+      //  4 -> Filter Width Index
+      //  5 -> Filter Height Index
+      //  6 -> FuseCode (activation) Index
+
+      const auto padding_index = OperandIndex{init_param.inputs[1]};
+      const auto hstride_index = OperandIndex{init_param.inputs[2]};
+      const auto vstride_index = OperandIndex{init_param.inputs[3]};
+      const auto kw_index = OperandIndex{init_param.inputs[4]};
+      const auto kh_index = OperandIndex{init_param.inputs[5]};
+      const auto activation_index = OperandIndex{init_param.inputs[6]};
+
+      param.padding.type =
+          NNAPIConvert::getPaddingType(operands.at(padding_index).asScalar<PaddingCode>());
+      param.stride = makeStride(operands, hstride_index, vstride_index);
+      param.kw = getUint32Scalar(operands, kw_index);
+      param.kh = operands.at(kh_index).asScalar<uint32_t>();
+      param.activation =
+          NNAPIConvert::getFusedActivation(operands.at(activation_index).asScalar<FuseCode>());
+    }
+    else if (init_param.input_count == 10) // support explicit padding
+    {
+      // Each input should be interpreted as follows:
+      //
+      //  1 -> Padding_left index
+      //  2 -> Padding_right index
+      //  3 -> Padding_top index
+      //  4 -> Padding_bottom index
+      //  5 -> Horizontal (over width) Stride Index
+      //  6 -> Vertial (over height) Stride Index
+      //  7 -> Filter Width Index
+      //  8 -> Filter Height Index
+      //  9 -> FuseCode (activation) Index
+
+      const auto padding_left_index = OperandIndex{init_param.inputs[1]};
+      const auto padding_right_index = OperandIndex{init_param.inputs[2]};
+      const auto padding_top_index = OperandIndex{init_param.inputs[3]};
+      const auto padding_bottom_index = OperandIndex{init_param.inputs[4]};
+      const auto hstride_index = OperandIndex{init_param.inputs[5]};
+      const auto vstride_index = OperandIndex{init_param.inputs[6]};
+      const auto kw_index = OperandIndex{init_param.inputs[7]};
+      const auto kh_index = OperandIndex{init_param.inputs[8]};
+      const auto activation_index = OperandIndex{init_param.inputs[9]};
+
+      param.padding.type = PaddingType::EXPLICIT;
+      param.padding.param = makeExplicitPadding(operands, padding_left_index, padding_right_index,
+                                                padding_top_index, padding_bottom_index);
+      param.stride = makeStride(operands, hstride_index, vstride_index);
+      param.kw = getUint32Scalar(operands, kw_index);
+      param.kh = getUint32Scalar(operands, kh_index);
+      param.activation =
+          NNAPIConvert::getFusedActivation(operands.at(activation_index).asScalar<FuseCode>());
+    }
+    return new operation::MaxPool2D{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_AVERAGE_POOL_2D] = [](const OperationFactory::Param &init_param,
+                                             Operands &operands) {
+    // TODO We may reuse code here for MAX_POOL_2D. Seems like these two are identical
+    assert(init_param.input_count == 7 || init_param.input_count == 10);
+    assert(init_param.output_count == 1);
+
+    // In common
+    //  0 -> IFM Tensor Index
+    OperandIndexSequence inputs{init_param.inputs[0]};
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    operation::AvgPool2D::Param param;
+    if (init_param.input_count == 7) // support implicit padding
+    {
+      // Each input should be interpreted as follows:
+      //
+      //  1 -> Padding Code (ANEURALNETWORKS_PADDING_SAME or ANEURALNETWORKS_PADDING_VALID) Index
+      //  2 -> Horizontal (over width) Stride Index
+      //  3 -> Vertial (over height) Stride Index
+      //  4 -> Filter Width Index
+      //  5 -> Filter Height Index
+      //  6 -> FuseCode (activation) Index
+
+      const auto padding_index = OperandIndex{init_param.inputs[1]};
+      const auto hstride_index = OperandIndex{init_param.inputs[2]};
+      const auto vstride_index = OperandIndex{init_param.inputs[3]};
+      const auto kw_index = OperandIndex{init_param.inputs[4]};
+      const auto kh_index = OperandIndex{init_param.inputs[5]};
+      const auto activation_index = OperandIndex{init_param.inputs[6]};
+
+      param.padding.type =
+          NNAPIConvert::getPaddingType(operands.at(padding_index).asScalar<PaddingCode>());
+      param.stride = makeStride(operands, hstride_index, vstride_index);
+      param.kw = getUint32Scalar(operands, kw_index);
+      param.kh = getUint32Scalar(operands, kh_index);
+      param.activation =
+          NNAPIConvert::getFusedActivation(operands.at(activation_index).asScalar<FuseCode>());
+    }
+    else if (init_param.input_count == 10) // support explicit padding
+    {
+      // Each input should be interpreted as follows:
+      //
+      //  1 -> Padding_left index
+      //  2 -> Padding_right index
+      //  3 -> Padding_top index
+      //  4 -> Padding_bottom index
+      //  5 -> Horizontal (over width) Stride Index
+      //  6 -> Vertial (over height) Stride Index
+      //  7 -> Filter Width Index
+      //  8 -> Filter Height Index
+      //  9 -> FuseCode (activation) Index
+
+      const auto padding_left_index = OperandIndex{init_param.inputs[1]};
+      const auto padding_right_index = OperandIndex{init_param.inputs[2]};
+      const auto padding_top_index = OperandIndex{init_param.inputs[3]};
+      const auto padding_bottom_index = OperandIndex{init_param.inputs[4]};
+      const auto hstride_index = OperandIndex{init_param.inputs[5]};
+      const auto vstride_index = OperandIndex{init_param.inputs[6]};
+      const auto kw_index = OperandIndex{init_param.inputs[7]};
+      const auto kh_index = OperandIndex{init_param.inputs[8]};
+      const auto activation_index = OperandIndex{init_param.inputs[9]};
+
+      param.padding.type = PaddingType::EXPLICIT;
+      param.padding.param = makeExplicitPadding(operands, padding_left_index, padding_right_index,
+                                                padding_top_index, padding_bottom_index);
+      param.stride = makeStride(operands, hstride_index, vstride_index);
+      param.kw = getUint32Scalar(operands, kw_index);
+      param.kh = getUint32Scalar(operands, kh_index);
+      param.activation =
+          NNAPIConvert::getFusedActivation(operands.at(activation_index).asScalar<FuseCode>());
+    }
+
+    return new operation::AvgPool2D{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_CONCATENATION] = [](const OperationFactory::Param &init_param,
+                                           Operands &operands) {
+    assert(init_param.input_count >= 2); // At least one one input tensor and axis
+    assert(init_param.output_count == 1);
+
+    // When there are N + 1 inputs, each input should be interpreted as follows:
+    //
+    //  [0, N) -> Input tensors
+    //  N -> Axis
+    //
+
+    OperandIndexSequence inputs;
+    for (uint32_t n = 0; n < init_param.input_count - 1; ++n)
+    {
+      inputs.append(OperandIndex{init_param.inputs[n]});
+    }
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    operation::Concat::Param param;
+    const OperandIndex axis_index{init_param.inputs[init_param.input_count - 1]};
+    param.axis = operands.at(axis_index).asScalar<int32_t>();
+    param.rank = operands.at(outputs.at(0)).shape().rank();
+
+    return new operation::Concat{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_RESHAPE] = [](const OperationFactory::Param &init_param, Operands &) {
+    assert(init_param.input_count == 2 && init_param.output_count == 1);
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> A tensor, specifying the tensor to be reshaped.
+    //  1 -> A 1-D tensor of type ANEURALNETWORKS_TENSOR_INT32, defining the shape of the output
+    //  tensor
+
+    // TODO Second input should be shape tensor (init_param.inputs[1])
+    //      Currently unused since assume that it is same with output tensor size
+    OperandIndexSequence inputs{init_param.inputs[0] /* , init_param.inputs[1] */};
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    return new operation::Reshape{inputs, outputs};
+  };
+
+  _map[ANEURALNETWORKS_FULLY_CONNECTED] = [](const OperationFactory::Param &init_param,
+                                             Operands &operands) {
+    assert(init_param.input_count == 4 && init_param.output_count == 1);
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> A tensor, specifying the input.
+    //  1 -> A 2-D tensor, specifying the weights
+    //  2 -> A 1-D tensor, specifying the bias
+    //  3 -> An INT32 value, and has to be one of the FuseCode values
+
+    OperandIndexSequence inputs{init_param.inputs[0], init_param.inputs[1], init_param.inputs[2]};
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    operation::FullyConnected::Param param;
+    const auto activation_index = OperandIndex{init_param.inputs[3]};
+    param.activation =
+        NNAPIConvert::getFusedActivation(operands.at(activation_index).asScalar<FuseCode>());
+
+    return new operation::FullyConnected{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_SOFTMAX] = [](const OperationFactory::Param &init_param,
+                                     Operands &operands) {
+    assert(init_param.input_count == 2 && init_param.output_count == 1);
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> A 2-D or 4-D tensor, specifying the tensor to be reshaped.
+    //  1 ->  FLOAT32 value, specifying the positive scaling factor for the exponent, beta.
+
+    OperandIndexSequence inputs{init_param.inputs[0]};
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    const auto beta_index = OperandIndex{init_param.inputs[1]};
+
+    operation::Softmax::Param param;
+    param.beta = operands.at(beta_index).asScalar<float>();
+
+    return new operation::Softmax{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_CAST] = [](const OperationFactory::Param &init_param, Operands &operands) {
+    assert(init_param.input_count == 1 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //  0 -> input Tensor Index
+    OperandIndexSequence inputs{init_param.inputs[0]};
+
+    // NNAPI uses QUANT8_ASYMM to represent UINT8 type for ANEURALNETWORKS_CAST's input/output
+    if (operands.at(inputs.at(0)).typeInfo().type() == DataType::QUANT8_ASYMM)
+    {
+      replaceDataType(operands, inputs.at(0), DataType::UINT8);
+    }
+    if (operands.at(outputs.at(0)).typeInfo().type() == DataType::QUANT8_ASYMM)
+    {
+      replaceDataType(operands, outputs.at(0), DataType::UINT8);
+    }
+
+    return new operation::Cast{inputs, outputs};
+  };
+
+  // ANEURALNETWORKS_CAST_EX is deprecated
+  // TODO Remove ANEURALNETWORKS_CAST_EX
+  _map[ANEURALNETWORKS_CAST_EX] = _map[ANEURALNETWORKS_CAST];
+
+  _map[ANEURALNETWORKS_CONV_2D] = [](const OperationFactory::Param &init_param,
+                                     Operands &operands) {
+    using operation::Conv2D;
+
+    // inputCount is either 7 or 10 acccording to NN API specification.
+    //  - Padding is implicit when inputCount is 7
+    //  - Padding is explicit when inputCount is 10
+    assert(init_param.input_count == 7 || init_param.input_count == 10);
+    assert(init_param.output_count == 1);
+
+    //  0 -> IFM Tensor Index
+    //  1 -> Kernel Tensor Index
+    //  2 -> Bias Tensor Index
+
+    OperandIndexSequence inputs{init_param.inputs[0], init_param.inputs[1], init_param.inputs[2]};
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    Conv2D::Param param;
+
+    if (init_param.input_count == 7) // support implicit padding
+    {
+      // Each input should be interpreted as follows:
+      //
+      //  3 -> Padding Code (ANEURALNETWORKS_PADDING_SAME or ANEURALNETWORKS_PADDING_VALID) Index
+      //  4 -> Stride (width) Index
+      //  5 -> Stride (height) INdex
+      //  6 -> Activation Index
+
+      const auto padding_index = OperandIndex{init_param.inputs[3]};
+      const auto hstride_index = OperandIndex{init_param.inputs[4]};
+      const auto vstride_index = OperandIndex{init_param.inputs[5]};
+      const auto activation_index = OperandIndex{init_param.inputs[6]};
+
+      param.padding.type =
+          NNAPIConvert::getPaddingType(operands.at(padding_index).asScalar<PaddingCode>());
+      param.stride = makeStride(operands, hstride_index, vstride_index);
+      param.activation =
+          NNAPIConvert::getFusedActivation(operands.at(activation_index).asScalar<FuseCode>());
+    }
+    else if (init_param.input_count == 10) // support explicit padding
+    {
+      // Each input should be interpreted as follows:
+      //
+      //  3 -> Padding_left index
+      //  4 -> Padding_right index
+      //  5 -> Padding_top index
+      //  6 -> Padding_bottom index
+      //  7 -> Stride (width) Index
+      //  8 -> Stride (height) INdex
+      //  9 -> Activation Index
+
+      const auto padding_left_index = OperandIndex{init_param.inputs[3]};
+      const auto padding_right_index = OperandIndex{init_param.inputs[4]};
+      const auto padding_top_index = OperandIndex{init_param.inputs[5]};
+      const auto padding_bottom_index = OperandIndex{init_param.inputs[6]};
+      const auto hstride_index = OperandIndex{init_param.inputs[7]};
+      const auto vstride_index = OperandIndex{init_param.inputs[8]};
+      const auto activation_index = OperandIndex{init_param.inputs[9]};
+
+      param.padding.type = PaddingType::EXPLICIT;
+      param.padding.param = makeExplicitPadding(operands, padding_left_index, padding_right_index,
+                                                padding_top_index, padding_bottom_index);
+      param.stride = makeStride(operands, hstride_index, vstride_index);
+      param.activation =
+          NNAPIConvert::getFusedActivation(operands.at(activation_index).asScalar<FuseCode>());
+    }
+
+    return new Conv2D{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_ADD] = [](const OperationFactory::Param &init_param, Operands &operands) {
+    assert(init_param.input_count == 3);
+    assert(init_param.output_count == 1);
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> Lefthand side operand
+    //  1 -> Righthand side operand
+
+    OperandIndexSequence inputs{init_param.inputs[0], init_param.inputs[1]};
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    operation::Add::Param param;
+
+    const auto activation_index = OperandIndex{init_param.inputs[2]};
+    param.activation =
+        NNAPIConvert::getFusedActivation(operands.at(activation_index).asScalar<FuseCode>());
+
+    return new operation::Add{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_REDUCE_SUM_EX] = [](const OperationFactory::Param &init_param,
+                                           Operands &operands) {
+    assert(init_param.input_count == 3);
+    assert(init_param.output_count == 1);
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> Input Tensor Index
+    //  1 -> Reduced Axes Tensor Index
+    //  2 -> keep_dims Index
+
+    OperandIndexSequence inputs{init_param.inputs[0]};
+    OperandIndexSequence outputs{init_param.outputs[0]};
+    std::vector<std::int32_t> axes =
+        operands.at(OperandIndex{init_param.inputs[1]}).asVector<std::int32_t>();
+
+    operation::ReduceSum::Param param;
+    param.axes.assign(axes.cbegin(), axes.cend());
+    param.keep_dims = operands.at(OperandIndex{init_param.inputs[2]}).asScalar<int32_t>() != 0;
+    param.rank = operands.at(inputs.at(0)).shape().rank();
+
+    return new operation::ReduceSum{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_SUB] = [](const OperationFactory::Param &init_param, Operands &operands) {
+    assert(init_param.input_count == 3);
+    assert(init_param.output_count == 1);
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> Lefthand side operand
+    //  1 -> Righthand side operand
+
+    OperandIndexSequence inputs{init_param.inputs[0], init_param.inputs[1]};
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    operation::Sub::Param param;
+
+    const auto activation_index = OperandIndex{init_param.inputs[2]};
+    param.activation =
+        NNAPIConvert::getFusedActivation(operands.at(activation_index).asScalar<FuseCode>());
+
+    return new operation::Sub{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_SLICE] = [](const OperationFactory::Param &init_param, Operands &operands) {
+    assert(init_param.input_count == 3 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> Input Tensor Index
+    //  1 -> Begins Tensor Index
+    //  2 -> Sizes Tensor Index
+    OperandIndexSequence inputs{init_param.inputs[0], init_param.inputs[1], init_param.inputs[2]};
+
+    operation::Slice::Param param;
+    param.rank = operands.at(inputs.at(0)).shape().rank();
+
+    return new operation::Slice{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_STRIDED_SLICE] = [](const OperationFactory::Param &init_param,
+                                           Operands &operands) {
+    assert(init_param.input_count == 7 && init_param.output_count == 1);
+
+    OperandIndexSequence inputs{init_param.inputs[0], init_param.inputs[1], init_param.inputs[2],
+                                init_param.inputs[3]};
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  1 -> A 1-D Tensor of {@link ANEURALNETWORKS_TENSOR_INT32}, the starts of
+    //       the dimensions of the input tensor to be sliced. The length must be
+    //       of rank(input0).
+    //  2 -> A 1-D Tensor of {@link ANEURALNETWORKS_TENSOR_INT32}, the ends of
+    //       the dimensions of the input tensor to be sliced. The length must be
+    //       of rank(input0).
+    //  3 -> A 1-D Tensor of {@link ANEURALNETWORKS_TENSOR_INT32}, the strides of
+    //       the dimensions of the input tensor to be sliced. The length must be
+    //       of rank(input0).
+    //  4 -> An {@link ANEURALNETWORKS_INT32} scalar, begin_mask. If the ith bit
+    //       of begin_mask is set, begin[i] is ignored and the fullest possible
+    //       range in that dimension is used instead.
+    //  5 -> An {@link ANEURALNETWORKS_INT32} scalar, end_mask. If the ith bit of
+    //       end_mask is set, end[i] is ignored and the fullest possible range in
+    //       that dimension is used instead.
+    //  6 -> An {@link ANEURALNETWORKS_INT32} scalar, shrink_axis_mask. An int32
+    //       mask. If the ith bit of shrink_axis_mask is set, it implies that the
+    //       ith specification shrinks the dimensionality by 1. A slice of size 1
+    //       starting from begin[i] in the dimension must be preserved.
+
+    operation::StridedSlice::Param param;
+
+    param.begin_mask = operands.at(OperandIndex{init_param.inputs[4]}).asScalar<std::int32_t>();
+    param.end_mask = operands.at(OperandIndex{init_param.inputs[5]}).asScalar<std::int32_t>();
+    param.shrink_axis_mask =
+        operands.at(OperandIndex{init_param.inputs[6]}).asScalar<std::int32_t>();
+    param.rank = operands.at(inputs.at(0)).shape().rank();
+
+    return new operation::StridedSlice{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_TRANSPOSE] = [](const OperationFactory::Param &init_param,
+                                       Operands &operands) {
+    // TODO make this work with init_param.input_count == 1 (when permutation vector is optional)
+
+    // Inputs
+    // 0: An n-D tensor, specifying the tensor to be transposed.
+    // 1: An optional 1-D Tensor of {@link ANEURALNETWORKS_TENSOR_INT32},
+    //    the permutation of the dimensions of the input tensor.
+    //    The returned tensor's dimension i corresponds to the input dimension
+    //    perm[i]. If perm is not given, it is set to (n-1...0), where n is the
+    //    rank of the input tensor. Hence by default, this operation performs a
+    //    regular matrix transpose on 2-D input Tensors.
+    assert(init_param.input_count == 2);
+    assert(init_param.output_count == 1);
+
+    OperandIndexSequence inputs{init_param.inputs[0]};
+    OperandIndexSequence outputs{init_param.outputs[0]};
+    std::vector<std::int32_t> perm =
+        operands.at(OperandIndex{init_param.inputs[1]}).asVector<std::int32_t>();
+
+    operation::Transpose::Param param;
+    param.perm.assign(perm.cbegin(), perm.cend());
+    param.rank = operands.at(inputs.at(0)).shape().rank();
+
+    return new operation::Transpose{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_MUL] = [](const OperationFactory::Param &init_param, Operands &operands) {
+    assert(init_param.input_count == 3 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> LHS Tensor Index
+    //  1 -> RHS Tensor Index
+    //  2 -> Activation Index
+
+    OperandIndexSequence inputs{init_param.inputs[0], init_param.inputs[1]};
+
+    operation::Mul::Param param;
+
+    const auto activation_index = OperandIndex{init_param.inputs[2]};
+    param.activation =
+        NNAPIConvert::getFusedActivation(operands.at(activation_index).asScalar<FuseCode>());
+
+    return new operation::Mul{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_SQUEEZE] = [](const OperationFactory::Param &init_param,
+                                     Operands &operands) {
+    assert(init_param.input_count == 1 || init_param.input_count == 2);
+    assert(init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    // 0 -> An n-D tensor, the tensor to be squeezed.
+    // 1 -> An optional 1-D tensor of ANEURALNETWORKS_TENSOR_INT32. The dimensions to squeeze.
+    //      If specified only squeezes the dimensions listed. Otherwise, squeezes all dimensions.
+    //      The dimension index starts at 0. An error must be reported if squeezing a dimension that
+    //      is not 1.
+
+    // Add mandatory input index
+    OperandIndexSequence inputs{init_param.inputs[0]};
+
+    // Add dims index if specified
+    operation::Squeeze::Param param{};
+    if (init_param.input_count == 2)
+    {
+      auto squeeze_dims_idx = OperandIndex{init_param.inputs[1]};
+      assert(operands.at(squeeze_dims_idx).shape().rank() == 1);
+      assert(operands.at(squeeze_dims_idx).shape().dim(0) >= 0);
+      assert(static_cast<uint32_t>(operands.at(squeeze_dims_idx).shape().dim(0)) <=
+             sizeof(param.dims));
+      param.ndim = operands.at(squeeze_dims_idx).shape().dim(0);
+      if (param.ndim > 0)
+        memcpy(param.dims, operands.at(squeeze_dims_idx).data().base(),
+               param.ndim * sizeof(param.dims[0]));
+    }
+
+    return new operation::Squeeze{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_TANH] = [](const OperationFactory::Param &init_param, Operands &) {
+    assert(init_param.input_count == 1 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> Input Tensor Index
+    OperandIndexSequence inputs{init_param.inputs[0]};
+
+    return new operation::Tanh{inputs, outputs};
+  };
+
+  _map[ANEURALNETWORKS_LOGISTIC] = [](const OperationFactory::Param &init_param, Operands &) {
+    assert(init_param.input_count == 1 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> Input Tensor Index
+    OperandIndexSequence inputs{init_param.inputs[0]};
+
+    return new operation::Logistic{inputs, outputs};
+  };
+
+  _map[ANEURALNETWORKS_DIV] = [](const OperationFactory::Param &init_param, Operands &operands) {
+    assert(init_param.input_count == 3 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> LHS Tensor Index
+    //  1 -> RHS Tensor Index
+    //  2 -> Activation Index
+    OperandIndexSequence inputs{init_param.inputs[0], init_param.inputs[1]};
+
+    operation::Div::Param param;
+
+    const auto activation_index = OperandIndex{init_param.inputs[2]};
+    param.activation =
+        NNAPIConvert::getFusedActivation(operands.at(activation_index).asScalar<FuseCode>());
+
+    return new operation::Div{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_EXP] = [](const OperationFactory::Param &init_param, Operands &) {
+    assert(init_param.input_count == 1 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> Input Tensor Index
+    OperandIndexSequence inputs{init_param.inputs[0]};
+
+    return new operation::Exp{inputs, outputs};
+  };
+
+  // ANEURALNETWORKS_EXP_EX is deprecated
+  // TODO Remove ANEURALNETWORKS_EXP_EX
+  _map[ANEURALNETWORKS_EXP_EX] = _map[ANEURALNETWORKS_EXP];
+
+  _map[ANEURALNETWORKS_GREATER_EQUAL_EX] = [](const OperationFactory::Param &init_param,
+                                              Operands &operands) {
+    assert(init_param.input_count == 2 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> input0 Tensor Index
+    //  1 -> input1 Tensor Index
+    OperandIndexSequence inputs{init_param.inputs[0], init_param.inputs[1]};
+
+    operation::Comparison::Param param;
+    param.comparison_type = operation::Comparison::ComparisonType::GreaterEqual;
+
+    // Output operand type must be boolean
+    replaceDataType(operands, outputs.at(0), DataType::BOOL8);
+
+    return new operation::Comparison{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_LESS_EX] = [](const OperationFactory::Param &init_param,
+                                     Operands &operands) {
+    assert(init_param.input_count == 2 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> input0 Tensor Index
+    //  1 -> input1 Tensor Index
+    OperandIndexSequence inputs{init_param.inputs[0], init_param.inputs[1]};
+
+    operation::Comparison::Param param;
+    param.comparison_type = operation::Comparison::ComparisonType::Less;
+
+    // Output operand type must be boolean
+    replaceDataType(operands, outputs.at(0), DataType::BOOL8);
+
+    return new operation::Comparison{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_REDUCE_MAX] = [](const OperationFactory::Param &init_param,
+                                        Operands &operands) {
+    assert(init_param.input_count == 3 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> Input Tensor Index
+    //  1 -> Axis Tensor Index
+    //  2 -> keep_dims Index
+    OperandIndexSequence inputs{init_param.inputs[0]};
+    std::vector<std::int32_t> axes =
+        operands.at(OperandIndex{init_param.inputs[1]}).asVector<std::int32_t>();
+
+    operation::ReduceMax::Param param;
+    param.axes.assign(axes.cbegin(), axes.cend());
+    param.keep_dims = operands.at(OperandIndex{init_param.inputs[2]}).asScalar<int8_t>() != 0;
+    param.rank = operands.at(inputs.at(0)).shape().rank();
+
+    return new operation::ReduceMax{inputs, outputs, param};
+  };
+
+  // ANEURALNETWORKS_REDUCE_MAX_EX is deprecated
+  // TODO Remove ANEURALNETWORKS_REDUCE_MAX_EX
+  _map[ANEURALNETWORKS_REDUCE_MAX_EX] = _map[ANEURALNETWORKS_REDUCE_MAX];
+
+  _map[ANEURALNETWORKS_NOT_EQUAL_EX] = [](const OperationFactory::Param &init_param,
+                                          Operands &operands) {
+    assert(init_param.input_count == 2 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> input1 Tensor Index
+    //  1 -> input2 Tensor Index
+    OperandIndexSequence inputs{init_param.inputs[0], init_param.inputs[1]};
+
+    operation::Comparison::Param param;
+    param.comparison_type = operation::Comparison::ComparisonType::NotEqual;
+
+    // Output operand type must be boolean
+    replaceDataType(operands, outputs.at(0), DataType::BOOL8);
+
+    return new operation::Comparison{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_LOGICAL_AND_EX] = [](const OperationFactory::Param &init_param,
+                                            Operands &operands) {
+    assert(init_param.input_count == 2 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> input0 Tensor Index
+    //  1 -> input1 Tensor Index
+    OperandIndexSequence inputs{init_param.inputs[0], init_param.inputs[1]};
+
+    // This operation's operands must be boolean type.
+    replaceDataType(operands, inputs.at(0), DataType::BOOL8);
+    replaceDataType(operands, inputs.at(1), DataType::BOOL8);
+    replaceDataType(operands, outputs.at(0), DataType::BOOL8);
+
+    return new operation::LogicalAnd{inputs, outputs};
+  };
+
+  _map[ANEURALNETWORKS_RSQRT] = [](const OperationFactory::Param &init_param, Operands &) {
+    assert(init_param.input_count == 1 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> Input Tensor Index
+    OperandIndexSequence inputs{init_param.inputs[0]};
+
+    return new operation::RSQRT{inputs, outputs};
+  };
+
+  // ANEURALNETWORKS_RSQRT_EX is deprecated
+  // TODO Remove ANEURALNETWORKS_RSQRT_EX
+  _map[ANEURALNETWORKS_RSQRT_EX] = _map[ANEURALNETWORKS_RSQRT];
+
+  _map[ANEURALNETWORKS_RELU] = [](const OperationFactory::Param &init_param, Operands &) {
+    assert(init_param.input_count == 1 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> Input Tensor Index
+    OperandIndexSequence inputs{init_param.inputs[0]};
+
+    return new operation::ReLU{inputs, outputs};
+  };
+
+  _map[ANEURALNETWORKS_RESIZE_BILINEAR] = [](const OperationFactory::Param &init_param,
+                                             Operands &operands) {
+    assert(init_param.input_count == 3 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> IFM Index
+    //  1 -> Height Index
+    //  2 -> Width Index
+    OperandIndexSequence inputs{init_param.inputs[0]};
+
+    operation::ResizeBilinear::Param param;
+    param.height_out = operands.at(OperandIndex{init_param.inputs[1]}).asScalar<int32_t>();
+    param.width_out = operands.at(OperandIndex{init_param.inputs[2]}).asScalar<int32_t>();
+
+    return new operation::ResizeBilinear{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_RELU1] = [](const OperationFactory::Param &init_param, Operands &) {
+    assert(init_param.input_count == 1 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> input Tensor Index
+    OperandIndexSequence inputs{init_param.inputs[0]};
+
+    return new operation::ReLU1{inputs, outputs};
+  };
+
+  _map[ANEURALNETWORKS_RELU6] = [](const OperationFactory::Param &init_param, Operands &) {
+    assert(init_param.input_count == 1 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> input Tensor Index
+    OperandIndexSequence inputs{init_param.inputs[0]};
+
+    return new operation::ReLU6{inputs, outputs};
+  };
+
+  _map[ANEURALNETWORKS_RNN] = [](const OperationFactory::Param &init_param, Operands &operands) {
+    assert(init_param.input_count == 6 && init_param.output_count == 2);
+
+    // Each input should be interpreted as follows:
+    //
+    // 0 -> Input Tensor Index
+    // 1 -> Weights Tensor Index
+    // 2 -> Recurrent Weights Tensor Index
+    // 3 -> Bias Tensor Index
+    // 4 -> Hidden state (in) Index
+    // 5 -> Activation Index
+
+    OperandIndexSequence inputs;
+    for (uint32_t n = 0; n < init_param.input_count - 1; ++n)
+    {
+      inputs.append(OperandIndex{init_param.inputs[n]});
+    }
+    OperandIndexSequence outputs;
+    for (uint32_t n = 0; n < init_param.output_count; ++n)
+    {
+      outputs.append(OperandIndex{init_param.outputs[n]});
+    }
+
+    operation::RNN::Param param;
+    const auto activation_index = OperandIndex{init_param.inputs[5]};
+    param.activation =
+        NNAPIConvert::getFusedActivation(operands.at(activation_index).asScalar<FuseCode>());
+
+    return new operation::RNN{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_FLOOR] = [](const OperationFactory::Param &init_param, Operands &) {
+    assert(init_param.input_count == 1 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //  0 -> input Tensor Index
+    OperandIndexSequence inputs{init_param.inputs[0]};
+
+    return new operation::Floor{inputs, outputs};
+  };
+
+  _map[ANEURALNETWORKS_SPACE_TO_BATCH_ND] = [](const OperationFactory::Param &init_param,
+                                               Operands &) {
+    assert(init_param.input_count == 3 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> Input Tensor Index
+    //  1 -> Block size Index
+    //  2 -> Paddings Index
+    OperandIndexSequence inputs;
+    for (uint32_t n = 0; n < init_param.input_count; ++n)
+    {
+      inputs.append(OperandIndex{init_param.inputs[n]});
+    }
+
+    return new operation::SpaceToBatchND{inputs, outputs};
+  };
+
+  _map[ANEURALNETWORKS_SPACE_TO_DEPTH] = [](const OperationFactory::Param &init_param,
+                                            Operands &operands) {
+    assert(init_param.input_count == 2 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> Input Tensor Index
+    //  1 -> Block size Index
+    OperandIndexSequence inputs{init_param.inputs[0]};
+
+    operation::SpaceToDepth::Param param;
+    param.block_size = operands.at(OperandIndex{init_param.inputs[1]}).asScalar<std::int32_t>();
+
+    return new operation::SpaceToDepth{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_L2_POOL_2D] = [](const OperationFactory::Param &init_param,
+                                        Operands &operands) {
+    assert(init_param.input_count == 10 || init_param.input_count == 7);
+    assert(init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> IFM Tensor Index
+    OperandIndexSequence inputs{init_param.inputs[0]};
+
+    operation::L2Pool2D::Param param;
+
+    if (init_param.input_count == 7) // Imlicit Padding case
+    {
+      //  1 -> Padding Code (ANEURALNETWORKS_PADDING_SAME or ANEURALNETWORKS_PADDING_VALID) Index
+      //  2 -> Horizontal (over width) Stride Index
+      //  3 -> Vertial (over height) Stride Index
+      //  4 -> Filter Width Index
+      //  5 -> Filter Height Index
+      //  6 -> FuseCode (activation) Index
+      const auto padding_index = OperandIndex{init_param.inputs[1]};
+      const auto hstride_index = OperandIndex{init_param.inputs[2]};
+      const auto vstride_index = OperandIndex{init_param.inputs[3]};
+      const auto kw_index = OperandIndex{init_param.inputs[4]};
+      const auto kh_index = OperandIndex{init_param.inputs[5]};
+      const auto activation_index = OperandIndex{init_param.inputs[6]};
+
+      param.padding.type =
+          NNAPIConvert::getPaddingType(operands.at(padding_index).asScalar<PaddingCode>());
+      param.stride = makeStride(operands, hstride_index, vstride_index);
+      param.kw = getUint32Scalar(operands, kw_index);
+      param.kh = getUint32Scalar(operands, kh_index);
+      param.activation =
+          NNAPIConvert::getFusedActivation(operands.at(activation_index).asScalar<FuseCode>());
+    }
+    else // Explicit Padding case
+    {
+      //  1 -> Padding_left index
+      //  2 -> Padding_right index
+      //  3 -> Padding_top index
+      //  4 -> Padding_bottom index
+      //  5 -> Horizontal (over width) Stride Index
+      //  6 -> Vertial (over height) Stride Index
+      //  7 -> Filter Width Index
+      //  8 -> Filter Height Index
+      //  9 -> FuseCode (activation) Index
+      const auto padding_left_index = OperandIndex{init_param.inputs[1]};
+      const auto padding_right_index = OperandIndex{init_param.inputs[2]};
+      const auto padding_top_index = OperandIndex{init_param.inputs[3]};
+      const auto padding_bottom_index = OperandIndex{init_param.inputs[4]};
+      const auto hstride_index = OperandIndex{init_param.inputs[5]};
+      const auto vstride_index = OperandIndex{init_param.inputs[6]};
+      const auto kw_index = OperandIndex{init_param.inputs[7]};
+      const auto kh_index = OperandIndex{init_param.inputs[8]};
+      const auto activation_index = OperandIndex{init_param.inputs[9]};
+
+      param.padding.type = PaddingType::EXPLICIT;
+      param.padding.param = makeExplicitPadding(operands, padding_left_index, padding_right_index,
+                                                padding_top_index, padding_bottom_index);
+      param.stride = makeStride(operands, hstride_index, vstride_index);
+      param.kw = getUint32Scalar(operands, kw_index);
+      param.kh = getUint32Scalar(operands, kh_index);
+      param.activation =
+          NNAPIConvert::getFusedActivation(operands.at(activation_index).asScalar<FuseCode>());
+    }
+
+    return new operation::L2Pool2D{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_EMBEDDING_LOOKUP] = [](const OperationFactory::Param &init_param,
+                                              Operands &) {
+    assert(init_param.input_count == 2 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> Lookups Index
+    //  1 -> Values Index
+    OperandIndexSequence inputs{init_param.inputs[0], init_param.inputs[1]};
+
+    return new operation::EmbeddingLookup{inputs, outputs};
+  };
+
+  _map[ANEURALNETWORKS_L2_NORMALIZATION] = [](const OperationFactory::Param &init_param,
+                                              Operands &operands) {
+    assert(init_param.input_count == 1 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //  0 -> input Tensor Index
+    OperandIndexSequence inputs{init_param.inputs[0]};
+
+    operation::L2Normalization::Param param;
+    param.rank = operands.at(inputs.at(0)).shape().rank();
+
+    return new operation::L2Normalization{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_HASHTABLE_LOOKUP] = [](const OperationFactory::Param &init_param,
+                                              Operands &) {
+    assert(init_param.input_count == 3 && init_param.output_count == 2);
+
+    // Each output should be interpreted as follows:
+    //
+    //  0 -> Output Index
+    //  1 -> Hits Index
+    OperandIndexSequence outputs{init_param.outputs[0], init_param.outputs[1]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> Lookups Index
+    //  1 -> Keys Index
+    //  2 -> Values Index
+    OperandIndexSequence inputs{init_param.inputs[0], init_param.inputs[1], init_param.inputs[2]};
+
+    return new operation::HashtableLookup{inputs, outputs};
+  };
+
+  _map[ANEURALNETWORKS_PRELU_EX] = [](const OperationFactory::Param &init_param, Operands &) {
+    assert(init_param.input_count == 2 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> input Tensor Index
+    //  1 -> alpha Tensor Index
+    OperandIndexSequence inputs{init_param.inputs[0], init_param.inputs[1]};
+
+    return new operation::PReLU{inputs, outputs};
+  };
+
+  _map[ANEURALNETWORKS_TRANSPOSE_CONV_EX] = [](const OperationFactory::Param &init_param,
+                                               Operands &operands) {
+    assert(init_param.input_count == 6 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> Output Shape Index
+    //  1 -> Weights Index
+    //  2 -> Input Tensor Index
+    //  3 -> Padding Type
+    //  4 -> Stride width
+    //  5 -> Stride height
+
+    OperandIndexSequence inputs{init_param.inputs[0], init_param.inputs[1], init_param.inputs[2]};
+
+    operation::TransposeConv::Param param;
+
+    const auto padding_index = OperandIndex{init_param.inputs[3]};
+    const auto hstride_index = OperandIndex{init_param.inputs[4]};
+    const auto vstride_index = OperandIndex{init_param.inputs[5]};
+
+    param.padding.type =
+        NNAPIConvert::getPaddingType(operands.at(padding_index).asScalar<PaddingCode>());
+    param.stride = makeStride(operands, hstride_index, vstride_index);
+
+    return new operation::TransposeConv{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_SQRT] = [](const OperationFactory::Param &init_param, Operands &) {
+    assert(init_param.input_count == 1 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //  0 -> input Tensor Index
+
+    OperandIndexSequence inputs{init_param.inputs[0]};
+    return new operation::SQRT{inputs, outputs};
+  };
+
+  // ANEURALNETWORKS_SQRT_EX is deprecated
+  // TODO Remove ANEURALNETWORKS_SQRT_EX
+  _map[ANEURALNETWORKS_SQRT_EX] = _map[ANEURALNETWORKS_SQRT];
+
+  _map[ANEURALNETWORKS_LOGICAL_OR_EX] = [](const OperationFactory::Param &init_param,
+                                           Operands &operands) {
+    assert(init_param.input_count == 2 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> input0 Tensor Index
+    //  1 -> input1 Tensor Index
+    OperandIndexSequence inputs{init_param.inputs[0], init_param.inputs[1]};
+
+    // This operation's operands must be boolean type.
+    replaceDataType(operands, inputs.at(0), DataType::BOOL8);
+    replaceDataType(operands, inputs.at(1), DataType::BOOL8);
+    replaceDataType(operands, outputs.at(0), DataType::BOOL8);
+
+    return new operation::LogicalOr{inputs, outputs};
+  };
+
+  _map[ANEURALNETWORKS_LOGICAL_NOT_EX] = [](const OperationFactory::Param &init_param,
+                                            Operands &operands) {
+    assert(init_param.input_count == 1 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> input Tensor Index
+    OperandIndexSequence inputs{init_param.inputs[0]};
+
+    // This operation's operands must be boolean type.
+    replaceDataType(operands, inputs.at(0), DataType::BOOL8);
+    replaceDataType(operands, outputs.at(0), DataType::BOOL8);
+
+    return new operation::LogicalNot{inputs, outputs};
+  };
+
+  _map[ANEURALNETWORKS_LSTM] = [](const OperationFactory::Param &init_param, Operands &operands) {
+    assert(init_param.input_count == 23 && init_param.output_count == 4);
+
+    // Each input should be interpreted as follows:
+    //
+    // 0 -> Input Tensor Index
+    // 1 -> Input to Input Tensor Index
+    // 2 -> Input to Forget Tensor Index
+    // 3 -> Input to Cell Tensor Index
+    // 4 -> Input to Output Tensor Index
+    // 5 -> Recurrent to Input Weights Tensor Index
+    // 6 -> Recurrent to Forget Weights Tensor Index
+    // 7 -> Recurrent to Cell Weights Tensor Index
+    // 8 -> Recurrent to Output Weights Tensor Index
+    // 9 -> Cell to Input Weights Tensor Index
+    // 10 -> Cell to Forget Weights Tensor Index
+    // 11 -> Cell to Output Weights Tensor Index
+    // 12 -> Input Gate Bias Tensor Index
+    // 13 -> Forget Gate Bias Tensor Index
+    // 14 -> Cell Bias Tensor Index
+    // 15 -> Output Gate Bias Tensor Index
+    // 16 -> Projection Weights Tensor Index
+    // 17 -> Projection Bias Tensor Index
+    // 18 -> Output State In Tensor Index
+    // 19 -> Cell State In Tensor Index
+    OperandIndexSequence inputs;
+    for (uint32_t n = 0; n < init_param.input_count - 3; ++n)
+    {
+      inputs.append(OperandIndex{init_param.inputs[n]});
+    }
+
+    // Each output should be interpreted as follows:
+    //
+    // 0 -> Scratch Buffer Tensor Index
+    // 1 -> Output State Out Tensor Index
+    // 2 -> Cell State Out Tensor Index
+    // 3 -> Output Tensor Index
+    OperandIndexSequence outputs;
+    for (uint32_t n = 0; n < init_param.output_count; ++n)
+    {
+      outputs.append(OperandIndex{init_param.outputs[n]});
+    }
+
+    operation::LSTM::Param param;
+    const auto activation_index = OperandIndex{init_param.inputs[20]};
+    switch (operands.at(activation_index).asScalar<int32_t>())
+    {
+      case 0:
+        param.activation = Activation::NONE;
+        break;
+      case 1:
+        param.activation = Activation::RELU;
+        break;
+      case 2:
+        param.activation = Activation::RELU1;
+        break;
+      case 3:
+        param.activation = Activation::RELU6;
+        break;
+      case 4:
+        param.activation = Activation::TANH;
+        break;
+      case 6:
+        param.activation = Activation::SIGMOID;
+        break;
+      default:
+        throw std::runtime_error("Unsupported activation type");
+        break;
+    }
+    param.cell_threshold = operands.at(OperandIndex{init_param.inputs[21]}).asScalar<float>();
+    param.projection_threshold = operands.at(OperandIndex{init_param.inputs[22]}).asScalar<float>();
+
+    return new operation::LSTM{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_EQUAL_EX] = [](const OperationFactory::Param &init_param,
+                                      Operands &operands) {
+    assert(init_param.input_count == 2 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> input0 Tensor Index
+    //  1 -> input1 Tensor Index
+    OperandIndexSequence inputs{init_param.inputs[0], init_param.inputs[1]};
+
+    operation::Comparison::Param param;
+    param.comparison_type = operation::Comparison::ComparisonType::Equal;
+
+    // Output operand type must be boolean
+    replaceDataType(operands, outputs.at(0), DataType::BOOL8);
+
+    return new operation::Comparison{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_SQUARED_DIFFERENCE_EX] = [](const OperationFactory::Param &init_param,
+                                                   Operands &) {
+    assert(init_param.input_count == 2 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> LHS Tensor Index
+    //  1 -> RHS Tensor Index
+    OperandIndexSequence inputs{init_param.inputs[0], init_param.inputs[1]};
+
+    return new operation::SquaredDifference{inputs, outputs};
+  };
+
+  _map[ANEURALNETWORKS_TOPK_V2] = [](const OperationFactory::Param &init_param,
+                                     Operands &operands) {
+    assert(init_param.input_count == 2 && init_param.output_count == 2);
+
+    // Each output should be interpreted as follows:
+    //
+    //  0 -> Index for Output Values
+    //  1 -> Index for Output Indices
+    OperandIndexSequence outputs{init_param.outputs[0], init_param.outputs[1]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> Index for Input Data
+    //  1 -> Index for K
+    OperandIndexSequence inputs{init_param.inputs[0]};
+
+    operation::TopKV2::Param param;
+    param.k = operands.at(OperandIndex{init_param.inputs[1]}).asScalar<std::int32_t>();
+
+    return new operation::TopKV2{inputs, outputs, param};
+  };
+
+  // ANEURALNETWORKS_CAST_EX is deprecated
+  // TODO Remove ANEURALNETWORKS_CAST_EX
+  _map[ANEURALNETWORKS_TOPK_V2_EX] = _map[ANEURALNETWORKS_TOPK_V2];
+
+  _map[ANEURALNETWORKS_GATHER] = [](const OperationFactory::Param &init_param, Operands &operands) {
+    assert(init_param.input_count == 3 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> input Tensor Index
+    //  1 -> axis Index
+    //  2 -> indices Tensor Index
+    OperandIndexSequence inputs{init_param.inputs[0], init_param.inputs[2]};
+
+    operation::Gather::Param param;
+    param.axis = operands.at(OperandIndex{init_param.inputs[1]}).asScalar<int32_t>();
+    param.rank = operands.at(inputs.at(0)).shape().rank();
+
+    return new operation::Gather{inputs, outputs, param};
+  };
+
+  // ANEURALNETWORKS_GATHER_EX is deprecated
+  // TODO Remove ANEURALNETWORKS_GATHER_EX
+  _map[ANEURALNETWORKS_GATHER_EX] = _map[ANEURALNETWORKS_GATHER];
+
+  _map[ANEURALNETWORKS_NEG] = [](const OperationFactory::Param &init_param, Operands &) {
+    assert(init_param.input_count == 1 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> Input Tensor Index
+    OperandIndexSequence inputs{init_param.inputs[0]};
+
+    return new operation::Neg{inputs, outputs};
+  };
+
+  // ANEURALNETWORKS_NEG_EX is deprecated
+  // TODO Remove ANEURALNETWORKS_NEG_EX
+  _map[ANEURALNETWORKS_NEG_EX] = _map[ANEURALNETWORKS_NEG];
+
+  _map[ANEURALNETWORKS_ABS] = [](const OperationFactory::Param &init_param, Operands &) {
+    assert(init_param.input_count == 1 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> Input Tensor Index
+    OperandIndexSequence inputs{init_param.inputs[0]};
+
+    return new operation::Abs{inputs, outputs};
+  };
+
+  // ANEURALNETWORKS_ABS_EX is deprecated
+  // TODO Remove ANEURALNETWORKS_ABS_EX
+  _map[ANEURALNETWORKS_ABS_EX] = _map[ANEURALNETWORKS_ABS];
+
+  _map[ANEURALNETWORKS_ARGMAX_EX] = [](const OperationFactory::Param &init_param,
+                                       Operands &operands) {
+    assert(init_param.input_count == 2 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> Input Tensor Index
+    //  1 -> Axis Tensor Index
+    OperandIndexSequence inputs{init_param.inputs[0]};
+
+    operation::ArgMax::Param param;
+    param.axis = operands.at(OperandIndex{init_param.inputs[1]}).asScalar<std::int32_t>();
+    param.rank = operands.at(inputs.at(0)).shape().rank();
+
+    return new operation::ArgMax{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_DEQUANTIZE] = [](const OperationFactory::Param &init_param, Operands &) {
+    assert(init_param.input_count == 1 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> Input Tensor Index
+    OperandIndexSequence inputs{init_param.inputs[0]};
+
+    return new operation::Dequantize{inputs, outputs};
+  };
+
+  _map[ANEURALNETWORKS_MEAN] = [](const OperationFactory::Param &init_param, Operands &operands) {
+    assert(init_param.input_count == 3 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> ifm Tensor Index
+    //  1 -> axis Tensor Index
+    //  2 -> keep_dims Index
+    OperandIndexSequence inputs{init_param.inputs[0]};
+    std::vector<std::int32_t> axes =
+        operands.at(OperandIndex{init_param.inputs[1]}).asVector<std::int32_t>();
+
+    operation::Mean::Param param;
+    param.axes.assign(axes.cbegin(), axes.cend());
+    param.keep_dims = operands.at(OperandIndex{init_param.inputs[2]}).asScalar<int32_t>() != 0;
+    param.rank = operands.at(inputs.at(0)).shape().rank();
+
+    return new operation::Mean{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_LOCAL_RESPONSE_NORMALIZATION] = [](const OperationFactory::Param &init_param,
+                                                          Operands &operands) {
+    assert(init_param.input_count == 5 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    OperandIndexSequence inputs{init_param.inputs[0]};
+
+    operation::LocalResponseNormalization::Param param;
+    param.radius = operands.at(OperandIndex{init_param.inputs[1]}).asScalar<std::int32_t>();
+    param.bias = operands.at(OperandIndex{init_param.inputs[2]}).asScalar<float>();
+    param.alpha = operands.at(OperandIndex{init_param.inputs[3]}).asScalar<float>();
+    param.beta = operands.at(OperandIndex{init_param.inputs[4]}).asScalar<float>();
+
+    return new operation::LocalResponseNormalization{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_DEPTH_TO_SPACE] = [](const OperationFactory::Param &init_param,
+                                            Operands &operands) {
+    assert(init_param.input_count == 2 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> Input Tensor Index
+    //  1 -> Block size Index
+    OperandIndexSequence inputs{init_param.inputs[0]};
+
+    operation::DepthToSpace::Param param;
+    param.block_size = operands.at(OperandIndex{init_param.inputs[1]}).asScalar<std::int32_t>();
+
+    return new operation::DepthToSpace{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_PACK_EX] = [](const OperationFactory::Param &init_param,
+                                     Operands &operands) {
+    assert(init_param.input_count >= 3 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+    OperandIndexSequence inputs;
+    for (uint32_t n = 0; n < init_param.input_count - 2; ++n)
+    {
+      inputs.append(OperandIndex{init_param.inputs[n]});
+    }
+
+    operation::Pack::Param param;
+    const auto num_index = OperandIndex{init_param.inputs[init_param.input_count - 2]};
+    const auto axis_index = OperandIndex{init_param.inputs[init_param.input_count - 1]};
+    param.num = operands.at(num_index).asScalar<int32_t>();
+    param.axis = operands.at(axis_index).asScalar<int32_t>();
+    param.rank = operands.at(outputs.at(0)).shape().rank();
+
+    return new operation::Pack{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_REDUCE_MIN_EX] = [](const OperationFactory::Param &init_param,
+                                           Operands &operands) {
+    assert(init_param.input_count == 3 && init_param.output_count == 1);
+
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    // Each input should be interpreted as follows:
+    //
+    //  0 -> Input Tensor Index
+    //  1 -> Axis Tensor Index
+    //  2 -> keep_dims Index
+    OperandIndexSequence inputs{init_param.inputs[0]};
+    std::vector<std::int32_t> axes =
+        operands.at(OperandIndex{init_param.inputs[1]}).asVector<std::int32_t>();
+
+    operation::ReduceMin::Param param;
+    param.axes.assign(axes.cbegin(), axes.cend());
+    param.keep_dims = operands.at(OperandIndex{init_param.inputs[2]}).asScalar<int32_t>() != 0;
+    param.rank = operands.at(inputs.at(0)).shape().rank();
+
+    return new operation::ReduceMin{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_SPLIT_EX] = [](const OperationFactory::Param &init_param,
+                                      Operands &operands) {
+    assert(init_param.input_count == 3);
+    assert(init_param.output_count >= 1); // At least one output tensor and axis
+
+    OperandIndexSequence inputs{init_param.inputs[0]};
+    OperandIndexSequence outputs;
+    for (uint32_t n = 0; n < init_param.output_count; ++n)
+    {
+      outputs.append(OperandIndex{init_param.outputs[n]});
+    }
+
+    operation::Split::Param param;
+    param.axis = operands.at(OperandIndex{init_param.inputs[1]}).asScalar<std::int32_t>();
+    param.num_splits = operands.at(OperandIndex{init_param.inputs[2]}).asScalar<std::int32_t>();
+    param.rank = operands.at(inputs.at(0)).shape().rank();
+
+    return new operation::Split{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_UNPACK_EX] = [](const OperationFactory::Param &init_param,
+                                       Operands &operands) {
+    assert(init_param.input_count == 3 && init_param.output_count >= 1);
+
+    OperandIndexSequence inputs{init_param.inputs[0]};
+    OperandIndexSequence outputs;
+    for (uint32_t n = 0; n < init_param.output_count; ++n)
+    {
+      outputs.append(OperandIndex{init_param.outputs[n]});
+    }
+
+    operation::Unpack::Param param;
+    const auto num_index = OperandIndex{init_param.inputs[1]};
+    const auto axis_index = OperandIndex{init_param.inputs[2]};
+    param.num = operands.at(num_index).asScalar<int32_t>();
+    param.axis = operands.at(axis_index).asScalar<int32_t>();
+    param.rank = operands.at(inputs.at(0)).shape().rank();
+
+    return new operation::Unpack{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_PAD] = [](const OperationFactory::Param &init_param, Operands &operands) {
+    assert(init_param.input_count == 2 && init_param.output_count >= 1);
+
+    OperandIndexSequence inputs{init_param.inputs[0], init_param.inputs[1]};
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    operation::Pad::Param param;
+    param.rank = operands.at(inputs.at(0)).shape().rank();
+
+    return new operation::Pad{inputs, outputs, param};
+  };
+
+  _map[ANEURALNETWORKS_MINIMUM] = [](const OperationFactory::Param &init_param, Operands &) {
+    assert(init_param.input_count == 2 && init_param.output_count == 1);
+
+    OperandIndexSequence inputs{init_param.inputs[0], init_param.inputs[1]};
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    return new operation::Min{inputs, outputs};
+  };
+
+  _map[ANEURALNETWORKS_MAXIMUM] = [](const OperationFactory::Param &init_param, Operands &) {
+    assert(init_param.input_count == 2 && init_param.output_count == 1);
+
+    OperandIndexSequence inputs{init_param.inputs[0], init_param.inputs[1]};
+    OperandIndexSequence outputs{init_param.outputs[0]};
+
+    return new operation::Max{inputs, outputs};
+  };
+}
+
+Operation *OperationFactory::create(ANeuralNetworksOperationType type,
+                                    const OperationFactory::Param &param, Operands &operands)
+{
+  auto it = _map.find(type);
+  if (it == _map.end())
+  {
+    throw std::runtime_error("Unsupported operation type: " + std::to_string(type));
+  }
+  return it->second(param, operands);
+}
diff --git a/runtime/neurun/frontend/nnapi/wrapper/OperationFactory.h b/runtime/neurun/frontend/nnapi/wrapper/OperationFactory.h
new file mode 100644
index 000000000..003e4eb7a
--- /dev/null
+++ b/runtime/neurun/frontend/nnapi/wrapper/OperationFactory.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __OPERATION_FACTORY_H__
+#define __OPERATION_FACTORY_H__
+
+#include <unordered_map>
+
+#include "ir/Operands.h"
+#include "ir/Operation.h"
+#include "NeuralNetworks.h"
+#include "NeuralNetworksEx.h"
+
+/**
+ * @brief A class to create a neurun operation object from NN API input parameters
+ */
+class OperationFactory
+{
+public:
+  struct Param
+  {
+    uint32_t input_count;
+    const uint32_t *inputs;
+    uint32_t output_count;
+    const uint32_t *outputs;
+  };
+
+public:
+  using Generator = std::function<neurun::ir::Operation *(const OperationFactory::Param &,
+                                                          neurun::ir::Operands &)>;
+
+public:
+  static OperationFactory &get();
+
+private:
+  OperationFactory();
+
+public:
+  neurun::ir::Operation *create(ANeuralNetworksOperationType, const OperationFactory::Param &param,
+                                neurun::ir::Operands &operands);
+  // TODO add "register" method for separating registration, possibly supporting custom-ops
+
+private:
+  std::unordered_map<ANeuralNetworksOperationType, Generator> _map;
+};
+
+#endif // __OPERATION_FACTORY_H__
diff --git a/runtime/neurun/frontend/tflite/CMakeLists.txt b/runtime/neurun/frontend/tflite/CMakeLists.txt
new file mode 100644
index 000000000..5157869f3
--- /dev/null
+++ b/runtime/neurun/frontend/tflite/CMakeLists.txt
@@ -0,0 +1,17 @@
+if(NOT BUILD_TFLITE_LOADER)
+  return()
+endif(NOT BUILD_TFLITE_LOADER)
+
+nnfw_find_package(FlatBuffersSource REQUIRED)
+
+set(TFLITE_LOADER_SOURCES src/tflite_loader.cc)
+
+add_library(tflite_loader SHARED ${TFLITE_LOADER_SOURCES})
+
+target_include_directories(tflite_loader PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/include)
+target_include_directories(tflite_loader PRIVATE ${FlatBuffersSource_DIR}/include)
+
+target_link_libraries(tflite_loader PUBLIC neurun_core)
+target_link_libraries(tflite_loader PRIVATE base_loader nnfw_lib_cpp14 nnfw_common nnfw_coverage)
+
+install(TARGETS tflite_loader DESTINATION lib)
diff --git a/runtime/neurun/frontend/tflite/include/tflite_loader.h b/runtime/neurun/frontend/tflite/include/tflite_loader.h
new file mode 100644
index 000000000..033230b4b
--- /dev/null
+++ b/runtime/neurun/frontend/tflite/include/tflite_loader.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __TFLITE_TFLITE_LOADER_H__
+#define __TFLITE_TFLITE_LOADER_H__
+
+#include "ir/Graph.h"
+
+#include <memory>
+
+namespace neurun
+{
+namespace tflite_loader
+{
+
+std::unique_ptr<ir::Graph> loadModel(const char *filename);
+
+} // namespace tflite_loader
+} // namespace neurun
+
+#endif // __TFLITE_TFLITE_LOADER_H__
diff --git a/runtime/neurun/frontend/tflite/src/tflite_loader.cc b/runtime/neurun/frontend/tflite/src/tflite_loader.cc
new file mode 100644
index 000000000..10a4fc095
--- /dev/null
+++ b/runtime/neurun/frontend/tflite/src/tflite_loader.cc
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "tflite_loader.h"
+#include "base_loader.h"
+#include "tflite_schema_generated.h"
+
+namespace neurun
+{
+namespace tflite_loader
+{
+
+namespace
+{
+
+struct LoaderDomain
+{
+  using Verifier = flatbuffers::Verifier;
+  using ActivationFunctionType = neurun_tflite::ActivationFunctionType;
+  using Buffer = neurun_tflite::Buffer;
+  using BuiltinOperator = neurun_tflite::BuiltinOperator;
+  using CustomOptionsFormat = neurun_tflite::CustomOptionsFormat;
+  using Model = neurun_tflite::Model;
+  using Operator = neurun_tflite::Operator;
+  using Padding = neurun_tflite::Padding;
+  using Pool2DOptions = neurun_tflite::Pool2DOptions;
+  using Tensor = neurun_tflite::Tensor;
+  using TensorType = neurun_tflite::TensorType;
+  using SubGraph = neurun_tflite::SubGraph;
+
+  static const char *EnumNameBuiltinOperator(BuiltinOperator e)
+  {
+    return neurun_tflite::EnumNameBuiltinOperator(e);
+  }
+  static const char *EnumNameActivationFunctionType(ActivationFunctionType e)
+  {
+    return neurun_tflite::EnumNameActivationFunctionType(e);
+  }
+  static const char *EnumNameTensorType(TensorType e)
+  {
+    return neurun_tflite::EnumNameTensorType(e);
+  }
+  static const Model *GetModel(const void *buf) { return neurun_tflite::GetModel(buf); }
+  static bool VerifyModelBuffer(Verifier &verifier)
+  {
+    return neurun_tflite::VerifyModelBuffer(verifier);
+  }
+};
+
+class TFLiteLoader final : public base_loader::BaseLoader<LoaderDomain, TFLiteLoader>
+{
+public:
+  using BaseLoader::BaseLoader;
+
+  void loadSubgraph(const neurun_tflite::SubGraph *subgraph)
+  {
+    // Load tensors
+    _tensor_to_operand.resize(subgraph->tensors()->size());
+    for (flatbuffers::uoffset_t i = 0; i < subgraph->tensors()->size(); ++i)
+    {
+      _tensor_to_operand[i] = loadOperand(subgraph->tensors()->Get(i));
+    }
+    // Set inputs
+    for (const std::int32_t input_ind : *subgraph->inputs())
+    {
+      _graph.addInput(_tensor_to_operand[input_ind]);
+    }
+    // Set outputs
+    for (const std::int32_t output_ind : *subgraph->outputs())
+    {
+      _graph.addOutput(_tensor_to_operand[output_ind]);
+    }
+    // Create operations
+    for (const auto *op : *subgraph->operators())
+    {
+      loadOperation(op);
+    }
+  }
+};
+
+} // namespace
+
+std::unique_ptr<ir::Graph> loadModel(const char *filename)
+{
+  auto graph = nnfw::cpp14::make_unique<ir::Graph>();
+  TFLiteLoader loader(*graph);
+  loader.loadFromFile(filename);
+  return graph;
+}
+
+} // namespace tflite_loader
+} // namespace neurun
diff --git a/runtime/neurun/frontend/tflite/src/tflite_schema_generated.h b/runtime/neurun/frontend/tflite/src/tflite_schema_generated.h
new file mode 100644
index 000000000..21669e2ff
--- /dev/null
+++ b/runtime/neurun/frontend/tflite/src/tflite_schema_generated.h
@@ -0,0 +1,7275 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+// automatically generated by the FlatBuffers compiler, do not modify
+
+#ifndef FLATBUFFERS_GENERATED_SCHEMA_NEURUN_TFLITE_H_
+#define FLATBUFFERS_GENERATED_SCHEMA_NEURUN_TFLITE_H_
+
+#include "flatbuffers/flatbuffers.h"
+
+namespace neurun_tflite
+{
+
+struct CustomQuantization;
+
+struct QuantizationParameters;
+
+struct Tensor;
+
+struct Conv2DOptions;
+
+struct Pool2DOptions;
+
+struct DepthwiseConv2DOptions;
+
+struct ConcatEmbeddingsOptions;
+
+struct LSHProjectionOptions;
+
+struct SVDFOptions;
+
+struct RNNOptions;
+
+struct SequenceRNNOptions;
+
+struct BidirectionalSequenceRNNOptions;
+
+struct FullyConnectedOptions;
+
+struct SoftmaxOptions;
+
+struct ConcatenationOptions;
+
+struct AddOptions;
+
+struct MulOptions;
+
+struct L2NormOptions;
+
+struct LocalResponseNormalizationOptions;
+
+struct LSTMOptions;
+
+struct UnidirectionalSequenceLSTMOptions;
+
+struct BidirectionalSequenceLSTMOptions;
+
+struct ResizeBilinearOptions;
+
+struct ResizeNearestNeighborOptions;
+
+struct CallOptions;
+
+struct PadOptions;
+
+struct PadV2Options;
+
+struct ReshapeOptions;
+
+struct SpaceToBatchNDOptions;
+
+struct BatchToSpaceNDOptions;
+
+struct SkipGramOptions;
+
+struct SpaceToDepthOptions;
+
+struct SubOptions;
+
+struct DivOptions;
+
+struct TopKV2Options;
+
+struct EmbeddingLookupSparseOptions;
+
+struct GatherOptions;
+
+struct TransposeOptions;
+
+struct ExpOptions;
+
+struct ReducerOptions;
+
+struct SqueezeOptions;
+
+struct SplitOptions;
+
+struct SplitVOptions;
+
+struct StridedSliceOptions;
+
+struct LogSoftmaxOptions;
+
+struct CastOptions;
+
+struct DequantizeOptions;
+
+struct MaximumMinimumOptions;
+
+struct TileOptions;
+
+struct ArgMaxOptions;
+
+struct ArgMinOptions;
+
+struct GreaterOptions;
+
+struct GreaterEqualOptions;
+
+struct LessOptions;
+
+struct LessEqualOptions;
+
+struct NegOptions;
+
+struct SelectOptions;
+
+struct SliceOptions;
+
+struct TransposeConvOptions;
+
+struct ExpandDimsOptions;
+
+struct SparseToDenseOptions;
+
+struct EqualOptions;
+
+struct NotEqualOptions;
+
+struct ShapeOptions;
+
+struct PowOptions;
+
+struct FakeQuantOptions;
+
+struct PackOptions;
+
+struct LogicalOrOptions;
+
+struct OneHotOptions;
+
+struct AbsOptions;
+
+struct LogicalAndOptions;
+
+struct LogicalNotOptions;
+
+struct UnpackOptions;
+
+struct FloorDivOptions;
+
+struct SquareOptions;
+
+struct ZerosLikeOptions;
+
+struct FillOptions;
+
+struct FloorModOptions;
+
+struct RangeOptions;
+
+struct LeakyReluOptions;
+
+struct SquaredDifferenceOptions;
+
+struct MirrorPadOptions;
+
+struct OperatorCode;
+
+struct Operator;
+
+struct SubGraph;
+
+struct Buffer;
+
+struct Model;
+
+enum TensorType
+{
+  TensorType_FLOAT32 = 0,
+  TensorType_FLOAT16 = 1,
+  TensorType_INT32 = 2,
+  TensorType_UINT8 = 3,
+  TensorType_INT64 = 4,
+  TensorType_STRING = 5,
+  TensorType_BOOL = 6,
+  TensorType_INT16 = 7,
+  TensorType_COMPLEX64 = 8,
+  TensorType_INT8 = 9,
+  TensorType_MIN = TensorType_FLOAT32,
+  TensorType_MAX = TensorType_INT8
+};
+
+inline const TensorType (&EnumValuesTensorType())[10]
+{
+  static const TensorType values[] = {TensorType_FLOAT32, TensorType_FLOAT16, TensorType_INT32,
+                                      TensorType_UINT8,   TensorType_INT64,   TensorType_STRING,
+                                      TensorType_BOOL,    TensorType_INT16,   TensorType_COMPLEX64,
+                                      TensorType_INT8};
+  return values;
+}
+
+inline const char *const *EnumNamesTensorType()
+{
+  static const char *const names[] = {"FLOAT32", "FLOAT16", "INT32",     "UINT8", "INT64", "STRING",
+                                      "BOOL",    "INT16",   "COMPLEX64", "INT8",  nullptr};
+  return names;
+}
+
+inline const char *EnumNameTensorType(TensorType e)
+{
+  const size_t index = static_cast<int>(e);
+  return EnumNamesTensorType()[index];
+}
+
+enum QuantizationDetails
+{
+  QuantizationDetails_NONE = 0,
+  QuantizationDetails_CustomQuantization = 1,
+  QuantizationDetails_MIN = QuantizationDetails_NONE,
+  QuantizationDetails_MAX = QuantizationDetails_CustomQuantization
+};
+
+inline const QuantizationDetails (&EnumValuesQuantizationDetails())[2]
+{
+  static const QuantizationDetails values[] = {QuantizationDetails_NONE,
+                                               QuantizationDetails_CustomQuantization};
+  return values;
+}
+
+inline const char *const *EnumNamesQuantizationDetails()
+{
+  static const char *const names[] = {"NONE", "CustomQuantization", nullptr};
+  return names;
+}
+
+inline const char *EnumNameQuantizationDetails(QuantizationDetails e)
+{
+  const size_t index = static_cast<int>(e);
+  return EnumNamesQuantizationDetails()[index];
+}
+
+template <typename T> struct QuantizationDetailsTraits
+{
+  static const QuantizationDetails enum_value = QuantizationDetails_NONE;
+};
+
+template <> struct QuantizationDetailsTraits<CustomQuantization>
+{
+  static const QuantizationDetails enum_value = QuantizationDetails_CustomQuantization;
+};
+
+bool VerifyQuantizationDetails(flatbuffers::Verifier &verifier, const void *obj,
+                               QuantizationDetails type);
+bool VerifyQuantizationDetailsVector(flatbuffers::Verifier &verifier,
+                                     const flatbuffers::Vector<flatbuffers::Offset<void>> *values,
+                                     const flatbuffers::Vector<uint8_t> *types);
+
+enum BuiltinOperator
+{
+  BuiltinOperator_ADD = 0,
+  BuiltinOperator_AVERAGE_POOL_2D = 1,
+  BuiltinOperator_CONCATENATION = 2,
+  BuiltinOperator_CONV_2D = 3,
+  BuiltinOperator_DEPTHWISE_CONV_2D = 4,
+  BuiltinOperator_DEQUANTIZE = 6,
+  BuiltinOperator_EMBEDDING_LOOKUP = 7,
+  BuiltinOperator_FLOOR = 8,
+  BuiltinOperator_FULLY_CONNECTED = 9,
+  BuiltinOperator_HASHTABLE_LOOKUP = 10,
+  BuiltinOperator_L2_NORMALIZATION = 11,
+  BuiltinOperator_L2_POOL_2D = 12,
+  BuiltinOperator_LOCAL_RESPONSE_NORMALIZATION = 13,
+  BuiltinOperator_LOGISTIC = 14,
+  BuiltinOperator_LSH_PROJECTION = 15,
+  BuiltinOperator_LSTM = 16,
+  BuiltinOperator_MAX_POOL_2D = 17,
+  BuiltinOperator_MUL = 18,
+  BuiltinOperator_RELU = 19,
+  BuiltinOperator_RELU_N1_TO_1 = 20,
+  BuiltinOperator_RELU6 = 21,
+  BuiltinOperator_RESHAPE = 22,
+  BuiltinOperator_RESIZE_BILINEAR = 23,
+  BuiltinOperator_RNN = 24,
+  BuiltinOperator_SOFTMAX = 25,
+  BuiltinOperator_SPACE_TO_DEPTH = 26,
+  BuiltinOperator_SVDF = 27,
+  BuiltinOperator_TANH = 28,
+  BuiltinOperator_CONCAT_EMBEDDINGS = 29,
+  BuiltinOperator_SKIP_GRAM = 30,
+  BuiltinOperator_CALL = 31,
+  BuiltinOperator_CUSTOM = 32,
+  BuiltinOperator_EMBEDDING_LOOKUP_SPARSE = 33,
+  BuiltinOperator_PAD = 34,
+  BuiltinOperator_UNIDIRECTIONAL_SEQUENCE_RNN = 35,
+  BuiltinOperator_GATHER = 36,
+  BuiltinOperator_BATCH_TO_SPACE_ND = 37,
+  BuiltinOperator_SPACE_TO_BATCH_ND = 38,
+  BuiltinOperator_TRANSPOSE = 39,
+  BuiltinOperator_MEAN = 40,
+  BuiltinOperator_SUB = 41,
+  BuiltinOperator_DIV = 42,
+  BuiltinOperator_SQUEEZE = 43,
+  BuiltinOperator_UNIDIRECTIONAL_SEQUENCE_LSTM = 44,
+  BuiltinOperator_STRIDED_SLICE = 45,
+  BuiltinOperator_BIDIRECTIONAL_SEQUENCE_RNN = 46,
+  BuiltinOperator_EXP = 47,
+  BuiltinOperator_TOPK_V2 = 48,
+  BuiltinOperator_SPLIT = 49,
+  BuiltinOperator_LOG_SOFTMAX = 50,
+  BuiltinOperator_DELEGATE = 51,
+  BuiltinOperator_BIDIRECTIONAL_SEQUENCE_LSTM = 52,
+  BuiltinOperator_CAST = 53,
+  BuiltinOperator_PRELU = 54,
+  BuiltinOperator_MAXIMUM = 55,
+  BuiltinOperator_ARG_MAX = 56,
+  BuiltinOperator_MINIMUM = 57,
+  BuiltinOperator_LESS = 58,
+  BuiltinOperator_NEG = 59,
+  BuiltinOperator_PADV2 = 60,
+  BuiltinOperator_GREATER = 61,
+  BuiltinOperator_GREATER_EQUAL = 62,
+  BuiltinOperator_LESS_EQUAL = 63,
+  BuiltinOperator_SELECT = 64,
+  BuiltinOperator_SLICE = 65,
+  BuiltinOperator_SIN = 66,
+  BuiltinOperator_TRANSPOSE_CONV = 67,
+  BuiltinOperator_SPARSE_TO_DENSE = 68,
+  BuiltinOperator_TILE = 69,
+  BuiltinOperator_EXPAND_DIMS = 70,
+  BuiltinOperator_EQUAL = 71,
+  BuiltinOperator_NOT_EQUAL = 72,
+  BuiltinOperator_LOG = 73,
+  BuiltinOperator_SUM = 74,
+  BuiltinOperator_SQRT = 75,
+  BuiltinOperator_RSQRT = 76,
+  BuiltinOperator_SHAPE = 77,
+  BuiltinOperator_POW = 78,
+  BuiltinOperator_ARG_MIN = 79,
+  BuiltinOperator_FAKE_QUANT = 80,
+  BuiltinOperator_REDUCE_PROD = 81,
+  BuiltinOperator_REDUCE_MAX = 82,
+  BuiltinOperator_PACK = 83,
+  BuiltinOperator_LOGICAL_OR = 84,
+  BuiltinOperator_ONE_HOT = 85,
+  BuiltinOperator_LOGICAL_AND = 86,
+  BuiltinOperator_LOGICAL_NOT = 87,
+  BuiltinOperator_UNPACK = 88,
+  BuiltinOperator_REDUCE_MIN = 89,
+  BuiltinOperator_FLOOR_DIV = 90,
+  BuiltinOperator_REDUCE_ANY = 91,
+  BuiltinOperator_SQUARE = 92,
+  BuiltinOperator_ZEROS_LIKE = 93,
+  BuiltinOperator_FILL = 94,
+  BuiltinOperator_FLOOR_MOD = 95,
+  BuiltinOperator_RANGE = 96,
+  BuiltinOperator_RESIZE_NEAREST_NEIGHBOR = 97,
+  BuiltinOperator_LEAKY_RELU = 98,
+  BuiltinOperator_SQUARED_DIFFERENCE = 99,
+  BuiltinOperator_MIRROR_PAD = 100,
+  BuiltinOperator_ABS = 101,
+  BuiltinOperator_SPLIT_V = 102,
+  BuiltinOperator_MIN = BuiltinOperator_ADD,
+  BuiltinOperator_MAX = BuiltinOperator_SPLIT_V
+};
+
+inline const BuiltinOperator (&EnumValuesBuiltinOperator())[102]
+{
+  static const BuiltinOperator values[] = {BuiltinOperator_ADD,
+                                           BuiltinOperator_AVERAGE_POOL_2D,
+                                           BuiltinOperator_CONCATENATION,
+                                           BuiltinOperator_CONV_2D,
+                                           BuiltinOperator_DEPTHWISE_CONV_2D,
+                                           BuiltinOperator_DEQUANTIZE,
+                                           BuiltinOperator_EMBEDDING_LOOKUP,
+                                           BuiltinOperator_FLOOR,
+                                           BuiltinOperator_FULLY_CONNECTED,
+                                           BuiltinOperator_HASHTABLE_LOOKUP,
+                                           BuiltinOperator_L2_NORMALIZATION,
+                                           BuiltinOperator_L2_POOL_2D,
+                                           BuiltinOperator_LOCAL_RESPONSE_NORMALIZATION,
+                                           BuiltinOperator_LOGISTIC,
+                                           BuiltinOperator_LSH_PROJECTION,
+                                           BuiltinOperator_LSTM,
+                                           BuiltinOperator_MAX_POOL_2D,
+                                           BuiltinOperator_MUL,
+                                           BuiltinOperator_RELU,
+                                           BuiltinOperator_RELU_N1_TO_1,
+                                           BuiltinOperator_RELU6,
+                                           BuiltinOperator_RESHAPE,
+                                           BuiltinOperator_RESIZE_BILINEAR,
+                                           BuiltinOperator_RNN,
+                                           BuiltinOperator_SOFTMAX,
+                                           BuiltinOperator_SPACE_TO_DEPTH,
+                                           BuiltinOperator_SVDF,
+                                           BuiltinOperator_TANH,
+                                           BuiltinOperator_CONCAT_EMBEDDINGS,
+                                           BuiltinOperator_SKIP_GRAM,
+                                           BuiltinOperator_CALL,
+                                           BuiltinOperator_CUSTOM,
+                                           BuiltinOperator_EMBEDDING_LOOKUP_SPARSE,
+                                           BuiltinOperator_PAD,
+                                           BuiltinOperator_UNIDIRECTIONAL_SEQUENCE_RNN,
+                                           BuiltinOperator_GATHER,
+                                           BuiltinOperator_BATCH_TO_SPACE_ND,
+                                           BuiltinOperator_SPACE_TO_BATCH_ND,
+                                           BuiltinOperator_TRANSPOSE,
+                                           BuiltinOperator_MEAN,
+                                           BuiltinOperator_SUB,
+                                           BuiltinOperator_DIV,
+                                           BuiltinOperator_SQUEEZE,
+                                           BuiltinOperator_UNIDIRECTIONAL_SEQUENCE_LSTM,
+                                           BuiltinOperator_STRIDED_SLICE,
+                                           BuiltinOperator_BIDIRECTIONAL_SEQUENCE_RNN,
+                                           BuiltinOperator_EXP,
+                                           BuiltinOperator_TOPK_V2,
+                                           BuiltinOperator_SPLIT,
+                                           BuiltinOperator_LOG_SOFTMAX,
+                                           BuiltinOperator_DELEGATE,
+                                           BuiltinOperator_BIDIRECTIONAL_SEQUENCE_LSTM,
+                                           BuiltinOperator_CAST,
+                                           BuiltinOperator_PRELU,
+                                           BuiltinOperator_MAXIMUM,
+                                           BuiltinOperator_ARG_MAX,
+                                           BuiltinOperator_MINIMUM,
+                                           BuiltinOperator_LESS,
+                                           BuiltinOperator_NEG,
+                                           BuiltinOperator_PADV2,
+                                           BuiltinOperator_GREATER,
+                                           BuiltinOperator_GREATER_EQUAL,
+                                           BuiltinOperator_LESS_EQUAL,
+                                           BuiltinOperator_SELECT,
+                                           BuiltinOperator_SLICE,
+                                           BuiltinOperator_SIN,
+                                           BuiltinOperator_TRANSPOSE_CONV,
+                                           BuiltinOperator_SPARSE_TO_DENSE,
+                                           BuiltinOperator_TILE,
+                                           BuiltinOperator_EXPAND_DIMS,
+                                           BuiltinOperator_EQUAL,
+                                           BuiltinOperator_NOT_EQUAL,
+                                           BuiltinOperator_LOG,
+                                           BuiltinOperator_SUM,
+                                           BuiltinOperator_SQRT,
+                                           BuiltinOperator_RSQRT,
+                                           BuiltinOperator_SHAPE,
+                                           BuiltinOperator_POW,
+                                           BuiltinOperator_ARG_MIN,
+                                           BuiltinOperator_FAKE_QUANT,
+                                           BuiltinOperator_REDUCE_PROD,
+                                           BuiltinOperator_REDUCE_MAX,
+                                           BuiltinOperator_PACK,
+                                           BuiltinOperator_LOGICAL_OR,
+                                           BuiltinOperator_ONE_HOT,
+                                           BuiltinOperator_LOGICAL_AND,
+                                           BuiltinOperator_LOGICAL_NOT,
+                                           BuiltinOperator_UNPACK,
+                                           BuiltinOperator_REDUCE_MIN,
+                                           BuiltinOperator_FLOOR_DIV,
+                                           BuiltinOperator_REDUCE_ANY,
+                                           BuiltinOperator_SQUARE,
+                                           BuiltinOperator_ZEROS_LIKE,
+                                           BuiltinOperator_FILL,
+                                           BuiltinOperator_FLOOR_MOD,
+                                           BuiltinOperator_RANGE,
+                                           BuiltinOperator_RESIZE_NEAREST_NEIGHBOR,
+                                           BuiltinOperator_LEAKY_RELU,
+                                           BuiltinOperator_SQUARED_DIFFERENCE,
+                                           BuiltinOperator_MIRROR_PAD,
+                                           BuiltinOperator_ABS,
+                                           BuiltinOperator_SPLIT_V};
+  return values;
+}
+
+inline const char *const *EnumNamesBuiltinOperator()
+{
+  static const char *const names[] = {"ADD",
+                                      "AVERAGE_POOL_2D",
+                                      "CONCATENATION",
+                                      "CONV_2D",
+                                      "DEPTHWISE_CONV_2D",
+                                      "",
+                                      "DEQUANTIZE",
+                                      "EMBEDDING_LOOKUP",
+                                      "FLOOR",
+                                      "FULLY_CONNECTED",
+                                      "HASHTABLE_LOOKUP",
+                                      "L2_NORMALIZATION",
+                                      "L2_POOL_2D",
+                                      "LOCAL_RESPONSE_NORMALIZATION",
+                                      "LOGISTIC",
+                                      "LSH_PROJECTION",
+                                      "LSTM",
+                                      "MAX_POOL_2D",
+                                      "MUL",
+                                      "RELU",
+                                      "RELU_N1_TO_1",
+                                      "RELU6",
+                                      "RESHAPE",
+                                      "RESIZE_BILINEAR",
+                                      "RNN",
+                                      "SOFTMAX",
+                                      "SPACE_TO_DEPTH",
+                                      "SVDF",
+                                      "TANH",
+                                      "CONCAT_EMBEDDINGS",
+                                      "SKIP_GRAM",
+                                      "CALL",
+                                      "CUSTOM",
+                                      "EMBEDDING_LOOKUP_SPARSE",
+                                      "PAD",
+                                      "UNIDIRECTIONAL_SEQUENCE_RNN",
+                                      "GATHER",
+                                      "BATCH_TO_SPACE_ND",
+                                      "SPACE_TO_BATCH_ND",
+                                      "TRANSPOSE",
+                                      "MEAN",
+                                      "SUB",
+                                      "DIV",
+                                      "SQUEEZE",
+                                      "UNIDIRECTIONAL_SEQUENCE_LSTM",
+                                      "STRIDED_SLICE",
+                                      "BIDIRECTIONAL_SEQUENCE_RNN",
+                                      "EXP",
+                                      "TOPK_V2",
+                                      "SPLIT",
+                                      "LOG_SOFTMAX",
+                                      "DELEGATE",
+                                      "BIDIRECTIONAL_SEQUENCE_LSTM",
+                                      "CAST",
+                                      "PRELU",
+                                      "MAXIMUM",
+                                      "ARG_MAX",
+                                      "MINIMUM",
+                                      "LESS",
+                                      "NEG",
+                                      "PADV2",
+                                      "GREATER",
+                                      "GREATER_EQUAL",
+                                      "LESS_EQUAL",
+                                      "SELECT",
+                                      "SLICE",
+                                      "SIN",
+                                      "TRANSPOSE_CONV",
+                                      "SPARSE_TO_DENSE",
+                                      "TILE",
+                                      "EXPAND_DIMS",
+                                      "EQUAL",
+                                      "NOT_EQUAL",
+                                      "LOG",
+                                      "SUM",
+                                      "SQRT",
+                                      "RSQRT",
+                                      "SHAPE",
+                                      "POW",
+                                      "ARG_MIN",
+                                      "FAKE_QUANT",
+                                      "REDUCE_PROD",
+                                      "REDUCE_MAX",
+                                      "PACK",
+                                      "LOGICAL_OR",
+                                      "ONE_HOT",
+                                      "LOGICAL_AND",
+                                      "LOGICAL_NOT",
+                                      "UNPACK",
+                                      "REDUCE_MIN",
+                                      "FLOOR_DIV",
+                                      "REDUCE_ANY",
+                                      "SQUARE",
+                                      "ZEROS_LIKE",
+                                      "FILL",
+                                      "FLOOR_MOD",
+                                      "RANGE",
+                                      "RESIZE_NEAREST_NEIGHBOR",
+                                      "LEAKY_RELU",
+                                      "SQUARED_DIFFERENCE",
+                                      "MIRROR_PAD",
+                                      "ABS",
+                                      "SPLIT_V",
+                                      nullptr};
+  return names;
+}
+
+inline const char *EnumNameBuiltinOperator(BuiltinOperator e)
+{
+  const size_t index = static_cast<int>(e);
+  return EnumNamesBuiltinOperator()[index];
+}
+
+enum BuiltinOptions
+{
+  BuiltinOptions_NONE = 0,
+  BuiltinOptions_Conv2DOptions = 1,
+  BuiltinOptions_DepthwiseConv2DOptions = 2,
+  BuiltinOptions_ConcatEmbeddingsOptions = 3,
+  BuiltinOptions_LSHProjectionOptions = 4,
+  BuiltinOptions_Pool2DOptions = 5,
+  BuiltinOptions_SVDFOptions = 6,
+  BuiltinOptions_RNNOptions = 7,
+  BuiltinOptions_FullyConnectedOptions = 8,
+  BuiltinOptions_SoftmaxOptions = 9,
+  BuiltinOptions_ConcatenationOptions = 10,
+  BuiltinOptions_AddOptions = 11,
+  BuiltinOptions_L2NormOptions = 12,
+  BuiltinOptions_LocalResponseNormalizationOptions = 13,
+  BuiltinOptions_LSTMOptions = 14,
+  BuiltinOptions_ResizeBilinearOptions = 15,
+  BuiltinOptions_CallOptions = 16,
+  BuiltinOptions_ReshapeOptions = 17,
+  BuiltinOptions_SkipGramOptions = 18,
+  BuiltinOptions_SpaceToDepthOptions = 19,
+  BuiltinOptions_EmbeddingLookupSparseOptions = 20,
+  BuiltinOptions_MulOptions = 21,
+  BuiltinOptions_PadOptions = 22,
+  BuiltinOptions_GatherOptions = 23,
+  BuiltinOptions_BatchToSpaceNDOptions = 24,
+  BuiltinOptions_SpaceToBatchNDOptions = 25,
+  BuiltinOptions_TransposeOptions = 26,
+  BuiltinOptions_ReducerOptions = 27,
+  BuiltinOptions_SubOptions = 28,
+  BuiltinOptions_DivOptions = 29,
+  BuiltinOptions_SqueezeOptions = 30,
+  BuiltinOptions_SequenceRNNOptions = 31,
+  BuiltinOptions_StridedSliceOptions = 32,
+  BuiltinOptions_ExpOptions = 33,
+  BuiltinOptions_TopKV2Options = 34,
+  BuiltinOptions_SplitOptions = 35,
+  BuiltinOptions_LogSoftmaxOptions = 36,
+  BuiltinOptions_CastOptions = 37,
+  BuiltinOptions_DequantizeOptions = 38,
+  BuiltinOptions_MaximumMinimumOptions = 39,
+  BuiltinOptions_ArgMaxOptions = 40,
+  BuiltinOptions_LessOptions = 41,
+  BuiltinOptions_NegOptions = 42,
+  BuiltinOptions_PadV2Options = 43,
+  BuiltinOptions_GreaterOptions = 44,
+  BuiltinOptions_GreaterEqualOptions = 45,
+  BuiltinOptions_LessEqualOptions = 46,
+  BuiltinOptions_SelectOptions = 47,
+  BuiltinOptions_SliceOptions = 48,
+  BuiltinOptions_TransposeConvOptions = 49,
+  BuiltinOptions_SparseToDenseOptions = 50,
+  BuiltinOptions_TileOptions = 51,
+  BuiltinOptions_ExpandDimsOptions = 52,
+  BuiltinOptions_EqualOptions = 53,
+  BuiltinOptions_NotEqualOptions = 54,
+  BuiltinOptions_ShapeOptions = 55,
+  BuiltinOptions_PowOptions = 56,
+  BuiltinOptions_ArgMinOptions = 57,
+  BuiltinOptions_FakeQuantOptions = 58,
+  BuiltinOptions_PackOptions = 59,
+  BuiltinOptions_LogicalOrOptions = 60,
+  BuiltinOptions_OneHotOptions = 61,
+  BuiltinOptions_LogicalAndOptions = 62,
+  BuiltinOptions_LogicalNotOptions = 63,
+  BuiltinOptions_UnpackOptions = 64,
+  BuiltinOptions_FloorDivOptions = 65,
+  BuiltinOptions_SquareOptions = 66,
+  BuiltinOptions_ZerosLikeOptions = 67,
+  BuiltinOptions_FillOptions = 68,
+  BuiltinOptions_BidirectionalSequenceLSTMOptions = 69,
+  BuiltinOptions_BidirectionalSequenceRNNOptions = 70,
+  BuiltinOptions_UnidirectionalSequenceLSTMOptions = 71,
+  BuiltinOptions_FloorModOptions = 72,
+  BuiltinOptions_RangeOptions = 73,
+  BuiltinOptions_ResizeNearestNeighborOptions = 74,
+  BuiltinOptions_LeakyReluOptions = 75,
+  BuiltinOptions_SquaredDifferenceOptions = 76,
+  BuiltinOptions_MirrorPadOptions = 77,
+  BuiltinOptions_AbsOptions = 78,
+  BuiltinOptions_SplitVOptions = 79,
+  BuiltinOptions_MIN = BuiltinOptions_NONE,
+  BuiltinOptions_MAX = BuiltinOptions_SplitVOptions
+};
+
+inline const BuiltinOptions (&EnumValuesBuiltinOptions())[80]
+{
+  static const BuiltinOptions values[] = {BuiltinOptions_NONE,
+                                          BuiltinOptions_Conv2DOptions,
+                                          BuiltinOptions_DepthwiseConv2DOptions,
+                                          BuiltinOptions_ConcatEmbeddingsOptions,
+                                          BuiltinOptions_LSHProjectionOptions,
+                                          BuiltinOptions_Pool2DOptions,
+                                          BuiltinOptions_SVDFOptions,
+                                          BuiltinOptions_RNNOptions,
+                                          BuiltinOptions_FullyConnectedOptions,
+                                          BuiltinOptions_SoftmaxOptions,
+                                          BuiltinOptions_ConcatenationOptions,
+                                          BuiltinOptions_AddOptions,
+                                          BuiltinOptions_L2NormOptions,
+                                          BuiltinOptions_LocalResponseNormalizationOptions,
+                                          BuiltinOptions_LSTMOptions,
+                                          BuiltinOptions_ResizeBilinearOptions,
+                                          BuiltinOptions_CallOptions,
+                                          BuiltinOptions_ReshapeOptions,
+                                          BuiltinOptions_SkipGramOptions,
+                                          BuiltinOptions_SpaceToDepthOptions,
+                                          BuiltinOptions_EmbeddingLookupSparseOptions,
+                                          BuiltinOptions_MulOptions,
+                                          BuiltinOptions_PadOptions,
+                                          BuiltinOptions_GatherOptions,
+                                          BuiltinOptions_BatchToSpaceNDOptions,
+                                          BuiltinOptions_SpaceToBatchNDOptions,
+                                          BuiltinOptions_TransposeOptions,
+                                          BuiltinOptions_ReducerOptions,
+                                          BuiltinOptions_SubOptions,
+                                          BuiltinOptions_DivOptions,
+                                          BuiltinOptions_SqueezeOptions,
+                                          BuiltinOptions_SequenceRNNOptions,
+                                          BuiltinOptions_StridedSliceOptions,
+                                          BuiltinOptions_ExpOptions,
+                                          BuiltinOptions_TopKV2Options,
+                                          BuiltinOptions_SplitOptions,
+                                          BuiltinOptions_LogSoftmaxOptions,
+                                          BuiltinOptions_CastOptions,
+                                          BuiltinOptions_DequantizeOptions,
+                                          BuiltinOptions_MaximumMinimumOptions,
+                                          BuiltinOptions_ArgMaxOptions,
+                                          BuiltinOptions_LessOptions,
+                                          BuiltinOptions_NegOptions,
+                                          BuiltinOptions_PadV2Options,
+                                          BuiltinOptions_GreaterOptions,
+                                          BuiltinOptions_GreaterEqualOptions,
+                                          BuiltinOptions_LessEqualOptions,
+                                          BuiltinOptions_SelectOptions,
+                                          BuiltinOptions_SliceOptions,
+                                          BuiltinOptions_TransposeConvOptions,
+                                          BuiltinOptions_SparseToDenseOptions,
+                                          BuiltinOptions_TileOptions,
+                                          BuiltinOptions_ExpandDimsOptions,
+                                          BuiltinOptions_EqualOptions,
+                                          BuiltinOptions_NotEqualOptions,
+                                          BuiltinOptions_ShapeOptions,
+                                          BuiltinOptions_PowOptions,
+                                          BuiltinOptions_ArgMinOptions,
+                                          BuiltinOptions_FakeQuantOptions,
+                                          BuiltinOptions_PackOptions,
+                                          BuiltinOptions_LogicalOrOptions,
+                                          BuiltinOptions_OneHotOptions,
+                                          BuiltinOptions_LogicalAndOptions,
+                                          BuiltinOptions_LogicalNotOptions,
+                                          BuiltinOptions_UnpackOptions,
+                                          BuiltinOptions_FloorDivOptions,
+                                          BuiltinOptions_SquareOptions,
+                                          BuiltinOptions_ZerosLikeOptions,
+                                          BuiltinOptions_FillOptions,
+                                          BuiltinOptions_BidirectionalSequenceLSTMOptions,
+                                          BuiltinOptions_BidirectionalSequenceRNNOptions,
+                                          BuiltinOptions_UnidirectionalSequenceLSTMOptions,
+                                          BuiltinOptions_FloorModOptions,
+                                          BuiltinOptions_RangeOptions,
+                                          BuiltinOptions_ResizeNearestNeighborOptions,
+                                          BuiltinOptions_LeakyReluOptions,
+                                          BuiltinOptions_SquaredDifferenceOptions,
+                                          BuiltinOptions_MirrorPadOptions,
+                                          BuiltinOptions_AbsOptions,
+                                          BuiltinOptions_SplitVOptions};
+  return values;
+}
+
+inline const char *const *EnumNamesBuiltinOptions()
+{
+  static const char *const names[] = {"NONE",
+                                      "Conv2DOptions",
+                                      "DepthwiseConv2DOptions",
+                                      "ConcatEmbeddingsOptions",
+                                      "LSHProjectionOptions",
+                                      "Pool2DOptions",
+                                      "SVDFOptions",
+                                      "RNNOptions",
+                                      "FullyConnectedOptions",
+                                      "SoftmaxOptions",
+                                      "ConcatenationOptions",
+                                      "AddOptions",
+                                      "L2NormOptions",
+                                      "LocalResponseNormalizationOptions",
+                                      "LSTMOptions",
+                                      "ResizeBilinearOptions",
+                                      "CallOptions",
+                                      "ReshapeOptions",
+                                      "SkipGramOptions",
+                                      "SpaceToDepthOptions",
+                                      "EmbeddingLookupSparseOptions",
+                                      "MulOptions",
+                                      "PadOptions",
+                                      "GatherOptions",
+                                      "BatchToSpaceNDOptions",
+                                      "SpaceToBatchNDOptions",
+                                      "TransposeOptions",
+                                      "ReducerOptions",
+                                      "SubOptions",
+                                      "DivOptions",
+                                      "SqueezeOptions",
+                                      "SequenceRNNOptions",
+                                      "StridedSliceOptions",
+                                      "ExpOptions",
+                                      "TopKV2Options",
+                                      "SplitOptions",
+                                      "LogSoftmaxOptions",
+                                      "CastOptions",
+                                      "DequantizeOptions",
+                                      "MaximumMinimumOptions",
+                                      "ArgMaxOptions",
+                                      "LessOptions",
+                                      "NegOptions",
+                                      "PadV2Options",
+                                      "GreaterOptions",
+                                      "GreaterEqualOptions",
+                                      "LessEqualOptions",
+                                      "SelectOptions",
+                                      "SliceOptions",
+                                      "TransposeConvOptions",
+                                      "SparseToDenseOptions",
+                                      "TileOptions",
+                                      "ExpandDimsOptions",
+                                      "EqualOptions",
+                                      "NotEqualOptions",
+                                      "ShapeOptions",
+                                      "PowOptions",
+                                      "ArgMinOptions",
+                                      "FakeQuantOptions",
+                                      "PackOptions",
+                                      "LogicalOrOptions",
+                                      "OneHotOptions",
+                                      "LogicalAndOptions",
+                                      "LogicalNotOptions",
+                                      "UnpackOptions",
+                                      "FloorDivOptions",
+                                      "SquareOptions",
+                                      "ZerosLikeOptions",
+                                      "FillOptions",
+                                      "BidirectionalSequenceLSTMOptions",
+                                      "BidirectionalSequenceRNNOptions",
+                                      "UnidirectionalSequenceLSTMOptions",
+                                      "FloorModOptions",
+                                      "RangeOptions",
+                                      "ResizeNearestNeighborOptions",
+                                      "LeakyReluOptions",
+                                      "SquaredDifferenceOptions",
+                                      "MirrorPadOptions",
+                                      "AbsOptions",
+                                      "SplitVOptions",
+                                      nullptr};
+  return names;
+}
+
+inline const char *EnumNameBuiltinOptions(BuiltinOptions e)
+{
+  const size_t index = static_cast<int>(e);
+  return EnumNamesBuiltinOptions()[index];
+}
+
+template <typename T> struct BuiltinOptionsTraits
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_NONE;
+};
+
+template <> struct BuiltinOptionsTraits<Conv2DOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_Conv2DOptions;
+};
+
+template <> struct BuiltinOptionsTraits<DepthwiseConv2DOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_DepthwiseConv2DOptions;
+};
+
+template <> struct BuiltinOptionsTraits<ConcatEmbeddingsOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_ConcatEmbeddingsOptions;
+};
+
+template <> struct BuiltinOptionsTraits<LSHProjectionOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_LSHProjectionOptions;
+};
+
+template <> struct BuiltinOptionsTraits<Pool2DOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_Pool2DOptions;
+};
+
+template <> struct BuiltinOptionsTraits<SVDFOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_SVDFOptions;
+};
+
+template <> struct BuiltinOptionsTraits<RNNOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_RNNOptions;
+};
+
+template <> struct BuiltinOptionsTraits<FullyConnectedOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_FullyConnectedOptions;
+};
+
+template <> struct BuiltinOptionsTraits<SoftmaxOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_SoftmaxOptions;
+};
+
+template <> struct BuiltinOptionsTraits<ConcatenationOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_ConcatenationOptions;
+};
+
+template <> struct BuiltinOptionsTraits<AddOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_AddOptions;
+};
+
+template <> struct BuiltinOptionsTraits<L2NormOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_L2NormOptions;
+};
+
+template <> struct BuiltinOptionsTraits<LocalResponseNormalizationOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_LocalResponseNormalizationOptions;
+};
+
+template <> struct BuiltinOptionsTraits<LSTMOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_LSTMOptions;
+};
+
+template <> struct BuiltinOptionsTraits<ResizeBilinearOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_ResizeBilinearOptions;
+};
+
+template <> struct BuiltinOptionsTraits<CallOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_CallOptions;
+};
+
+template <> struct BuiltinOptionsTraits<ReshapeOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_ReshapeOptions;
+};
+
+template <> struct BuiltinOptionsTraits<SkipGramOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_SkipGramOptions;
+};
+
+template <> struct BuiltinOptionsTraits<SpaceToDepthOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_SpaceToDepthOptions;
+};
+
+template <> struct BuiltinOptionsTraits<EmbeddingLookupSparseOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_EmbeddingLookupSparseOptions;
+};
+
+template <> struct BuiltinOptionsTraits<MulOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_MulOptions;
+};
+
+template <> struct BuiltinOptionsTraits<PadOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_PadOptions;
+};
+
+template <> struct BuiltinOptionsTraits<GatherOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_GatherOptions;
+};
+
+template <> struct BuiltinOptionsTraits<BatchToSpaceNDOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_BatchToSpaceNDOptions;
+};
+
+template <> struct BuiltinOptionsTraits<SpaceToBatchNDOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_SpaceToBatchNDOptions;
+};
+
+template <> struct BuiltinOptionsTraits<TransposeOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_TransposeOptions;
+};
+
+template <> struct BuiltinOptionsTraits<ReducerOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_ReducerOptions;
+};
+
+template <> struct BuiltinOptionsTraits<SubOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_SubOptions;
+};
+
+template <> struct BuiltinOptionsTraits<DivOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_DivOptions;
+};
+
+template <> struct BuiltinOptionsTraits<SqueezeOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_SqueezeOptions;
+};
+
+template <> struct BuiltinOptionsTraits<SequenceRNNOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_SequenceRNNOptions;
+};
+
+template <> struct BuiltinOptionsTraits<StridedSliceOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_StridedSliceOptions;
+};
+
+template <> struct BuiltinOptionsTraits<ExpOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_ExpOptions;
+};
+
+template <> struct BuiltinOptionsTraits<TopKV2Options>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_TopKV2Options;
+};
+
+template <> struct BuiltinOptionsTraits<SplitOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_SplitOptions;
+};
+
+template <> struct BuiltinOptionsTraits<LogSoftmaxOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_LogSoftmaxOptions;
+};
+
+template <> struct BuiltinOptionsTraits<CastOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_CastOptions;
+};
+
+template <> struct BuiltinOptionsTraits<DequantizeOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_DequantizeOptions;
+};
+
+template <> struct BuiltinOptionsTraits<MaximumMinimumOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_MaximumMinimumOptions;
+};
+
+template <> struct BuiltinOptionsTraits<ArgMaxOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_ArgMaxOptions;
+};
+
+template <> struct BuiltinOptionsTraits<LessOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_LessOptions;
+};
+
+template <> struct BuiltinOptionsTraits<NegOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_NegOptions;
+};
+
+template <> struct BuiltinOptionsTraits<PadV2Options>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_PadV2Options;
+};
+
+template <> struct BuiltinOptionsTraits<GreaterOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_GreaterOptions;
+};
+
+template <> struct BuiltinOptionsTraits<GreaterEqualOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_GreaterEqualOptions;
+};
+
+template <> struct BuiltinOptionsTraits<LessEqualOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_LessEqualOptions;
+};
+
+template <> struct BuiltinOptionsTraits<SelectOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_SelectOptions;
+};
+
+template <> struct BuiltinOptionsTraits<SliceOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_SliceOptions;
+};
+
+template <> struct BuiltinOptionsTraits<TransposeConvOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_TransposeConvOptions;
+};
+
+template <> struct BuiltinOptionsTraits<SparseToDenseOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_SparseToDenseOptions;
+};
+
+template <> struct BuiltinOptionsTraits<TileOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_TileOptions;
+};
+
+template <> struct BuiltinOptionsTraits<ExpandDimsOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_ExpandDimsOptions;
+};
+
+template <> struct BuiltinOptionsTraits<EqualOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_EqualOptions;
+};
+
+template <> struct BuiltinOptionsTraits<NotEqualOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_NotEqualOptions;
+};
+
+template <> struct BuiltinOptionsTraits<ShapeOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_ShapeOptions;
+};
+
+template <> struct BuiltinOptionsTraits<PowOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_PowOptions;
+};
+
+template <> struct BuiltinOptionsTraits<ArgMinOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_ArgMinOptions;
+};
+
+template <> struct BuiltinOptionsTraits<FakeQuantOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_FakeQuantOptions;
+};
+
+template <> struct BuiltinOptionsTraits<PackOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_PackOptions;
+};
+
+template <> struct BuiltinOptionsTraits<LogicalOrOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_LogicalOrOptions;
+};
+
+template <> struct BuiltinOptionsTraits<OneHotOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_OneHotOptions;
+};
+
+template <> struct BuiltinOptionsTraits<LogicalAndOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_LogicalAndOptions;
+};
+
+template <> struct BuiltinOptionsTraits<LogicalNotOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_LogicalNotOptions;
+};
+
+template <> struct BuiltinOptionsTraits<UnpackOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_UnpackOptions;
+};
+
+template <> struct BuiltinOptionsTraits<FloorDivOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_FloorDivOptions;
+};
+
+template <> struct BuiltinOptionsTraits<SquareOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_SquareOptions;
+};
+
+template <> struct BuiltinOptionsTraits<ZerosLikeOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_ZerosLikeOptions;
+};
+
+template <> struct BuiltinOptionsTraits<FillOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_FillOptions;
+};
+
+template <> struct BuiltinOptionsTraits<BidirectionalSequenceLSTMOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_BidirectionalSequenceLSTMOptions;
+};
+
+template <> struct BuiltinOptionsTraits<BidirectionalSequenceRNNOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_BidirectionalSequenceRNNOptions;
+};
+
+template <> struct BuiltinOptionsTraits<UnidirectionalSequenceLSTMOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_UnidirectionalSequenceLSTMOptions;
+};
+
+template <> struct BuiltinOptionsTraits<FloorModOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_FloorModOptions;
+};
+
+template <> struct BuiltinOptionsTraits<RangeOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_RangeOptions;
+};
+
+template <> struct BuiltinOptionsTraits<ResizeNearestNeighborOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_ResizeNearestNeighborOptions;
+};
+
+template <> struct BuiltinOptionsTraits<LeakyReluOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_LeakyReluOptions;
+};
+
+template <> struct BuiltinOptionsTraits<SquaredDifferenceOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_SquaredDifferenceOptions;
+};
+
+template <> struct BuiltinOptionsTraits<MirrorPadOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_MirrorPadOptions;
+};
+
+template <> struct BuiltinOptionsTraits<AbsOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_AbsOptions;
+};
+
+template <> struct BuiltinOptionsTraits<SplitVOptions>
+{
+  static const BuiltinOptions enum_value = BuiltinOptions_SplitVOptions;
+};
+
+bool VerifyBuiltinOptions(flatbuffers::Verifier &verifier, const void *obj, BuiltinOptions type);
+bool VerifyBuiltinOptionsVector(flatbuffers::Verifier &verifier,
+                                const flatbuffers::Vector<flatbuffers::Offset<void>> *values,
+                                const flatbuffers::Vector<uint8_t> *types);
+
+enum Padding
+{
+  Padding_SAME = 0,
+  Padding_VALID = 1,
+  Padding_MIN = Padding_SAME,
+  Padding_MAX = Padding_VALID
+};
+
+inline const Padding (&EnumValuesPadding())[2]
+{
+  static const Padding values[] = {Padding_SAME, Padding_VALID};
+  return values;
+}
+
+inline const char *const *EnumNamesPadding()
+{
+  static const char *const names[] = {"SAME", "VALID", nullptr};
+  return names;
+}
+
+inline const char *EnumNamePadding(Padding e)
+{
+  const size_t index = static_cast<int>(e);
+  return EnumNamesPadding()[index];
+}
+
+enum ActivationFunctionType
+{
+  ActivationFunctionType_NONE = 0,
+  ActivationFunctionType_RELU = 1,
+  ActivationFunctionType_RELU_N1_TO_1 = 2,
+  ActivationFunctionType_RELU6 = 3,
+  ActivationFunctionType_TANH = 4,
+  ActivationFunctionType_SIGN_BIT = 5,
+  ActivationFunctionType_MIN = ActivationFunctionType_NONE,
+  ActivationFunctionType_MAX = ActivationFunctionType_SIGN_BIT
+};
+
+inline const ActivationFunctionType (&EnumValuesActivationFunctionType())[6]
+{
+  static const ActivationFunctionType values[] = {
+      ActivationFunctionType_NONE,         ActivationFunctionType_RELU,
+      ActivationFunctionType_RELU_N1_TO_1, ActivationFunctionType_RELU6,
+      ActivationFunctionType_TANH,         ActivationFunctionType_SIGN_BIT};
+  return values;
+}
+
+inline const char *const *EnumNamesActivationFunctionType()
+{
+  static const char *const names[] = {"NONE", "RELU",     "RELU_N1_TO_1", "RELU6",
+                                      "TANH", "SIGN_BIT", nullptr};
+  return names;
+}
+
+inline const char *EnumNameActivationFunctionType(ActivationFunctionType e)
+{
+  const size_t index = static_cast<int>(e);
+  return EnumNamesActivationFunctionType()[index];
+}
+
+enum LSHProjectionType
+{
+  LSHProjectionType_UNKNOWN = 0,
+  LSHProjectionType_SPARSE = 1,
+  LSHProjectionType_DENSE = 2,
+  LSHProjectionType_MIN = LSHProjectionType_UNKNOWN,
+  LSHProjectionType_MAX = LSHProjectionType_DENSE
+};
+
+inline const LSHProjectionType (&EnumValuesLSHProjectionType())[3]
+{
+  static const LSHProjectionType values[] = {LSHProjectionType_UNKNOWN, LSHProjectionType_SPARSE,
+                                             LSHProjectionType_DENSE};
+  return values;
+}
+
+inline const char *const *EnumNamesLSHProjectionType()
+{
+  static const char *const names[] = {"UNKNOWN", "SPARSE", "DENSE", nullptr};
+  return names;
+}
+
+inline const char *EnumNameLSHProjectionType(LSHProjectionType e)
+{
+  const size_t index = static_cast<int>(e);
+  return EnumNamesLSHProjectionType()[index];
+}
+
+enum FullyConnectedOptionsWeightsFormat
+{
+  FullyConnectedOptionsWeightsFormat_DEFAULT = 0,
+  FullyConnectedOptionsWeightsFormat_SHUFFLED4x16INT8 = 1,
+  FullyConnectedOptionsWeightsFormat_MIN = FullyConnectedOptionsWeightsFormat_DEFAULT,
+  FullyConnectedOptionsWeightsFormat_MAX = FullyConnectedOptionsWeightsFormat_SHUFFLED4x16INT8
+};
+
+inline const FullyConnectedOptionsWeightsFormat (&EnumValuesFullyConnectedOptionsWeightsFormat())[2]
+{
+  static const FullyConnectedOptionsWeightsFormat values[] = {
+      FullyConnectedOptionsWeightsFormat_DEFAULT,
+      FullyConnectedOptionsWeightsFormat_SHUFFLED4x16INT8};
+  return values;
+}
+
+inline const char *const *EnumNamesFullyConnectedOptionsWeightsFormat()
+{
+  static const char *const names[] = {"DEFAULT", "SHUFFLED4x16INT8", nullptr};
+  return names;
+}
+
+inline const char *EnumNameFullyConnectedOptionsWeightsFormat(FullyConnectedOptionsWeightsFormat e)
+{
+  const size_t index = static_cast<int>(e);
+  return EnumNamesFullyConnectedOptionsWeightsFormat()[index];
+}
+
+enum LSTMKernelType
+{
+  LSTMKernelType_FULL = 0,
+  LSTMKernelType_BASIC = 1,
+  LSTMKernelType_MIN = LSTMKernelType_FULL,
+  LSTMKernelType_MAX = LSTMKernelType_BASIC
+};
+
+inline const LSTMKernelType (&EnumValuesLSTMKernelType())[2]
+{
+  static const LSTMKernelType values[] = {LSTMKernelType_FULL, LSTMKernelType_BASIC};
+  return values;
+}
+
+inline const char *const *EnumNamesLSTMKernelType()
+{
+  static const char *const names[] = {"FULL", "BASIC", nullptr};
+  return names;
+}
+
+inline const char *EnumNameLSTMKernelType(LSTMKernelType e)
+{
+  const size_t index = static_cast<int>(e);
+  return EnumNamesLSTMKernelType()[index];
+}
+
+enum CombinerType
+{
+  CombinerType_SUM = 0,
+  CombinerType_MEAN = 1,
+  CombinerType_SQRTN = 2,
+  CombinerType_MIN = CombinerType_SUM,
+  CombinerType_MAX = CombinerType_SQRTN
+};
+
+inline const CombinerType (&EnumValuesCombinerType())[3]
+{
+  static const CombinerType values[] = {CombinerType_SUM, CombinerType_MEAN, CombinerType_SQRTN};
+  return values;
+}
+
+inline const char *const *EnumNamesCombinerType()
+{
+  static const char *const names[] = {"SUM", "MEAN", "SQRTN", nullptr};
+  return names;
+}
+
+inline const char *EnumNameCombinerType(CombinerType e)
+{
+  const size_t index = static_cast<int>(e);
+  return EnumNamesCombinerType()[index];
+}
+
+enum MirrorPadMode
+{
+  MirrorPadMode_REFLECT = 0,
+  MirrorPadMode_SYMMETRIC = 1,
+  MirrorPadMode_MIN = MirrorPadMode_REFLECT,
+  MirrorPadMode_MAX = MirrorPadMode_SYMMETRIC
+};
+
+inline const MirrorPadMode (&EnumValuesMirrorPadMode())[2]
+{
+  static const MirrorPadMode values[] = {MirrorPadMode_REFLECT, MirrorPadMode_SYMMETRIC};
+  return values;
+}
+
+inline const char *const *EnumNamesMirrorPadMode()
+{
+  static const char *const names[] = {"REFLECT", "SYMMETRIC", nullptr};
+  return names;
+}
+
+inline const char *EnumNameMirrorPadMode(MirrorPadMode e)
+{
+  const size_t index = static_cast<int>(e);
+  return EnumNamesMirrorPadMode()[index];
+}
+
+enum CustomOptionsFormat
+{
+  CustomOptionsFormat_FLEXBUFFERS = 0,
+  CustomOptionsFormat_MIN = CustomOptionsFormat_FLEXBUFFERS,
+  CustomOptionsFormat_MAX = CustomOptionsFormat_FLEXBUFFERS
+};
+
+inline const CustomOptionsFormat (&EnumValuesCustomOptionsFormat())[1]
+{
+  static const CustomOptionsFormat values[] = {CustomOptionsFormat_FLEXBUFFERS};
+  return values;
+}
+
+inline const char *const *EnumNamesCustomOptionsFormat()
+{
+  static const char *const names[] = {"FLEXBUFFERS", nullptr};
+  return names;
+}
+
+inline const char *EnumNameCustomOptionsFormat(CustomOptionsFormat e)
+{
+  const size_t index = static_cast<int>(e);
+  return EnumNamesCustomOptionsFormat()[index];
+}
+
+struct CustomQuantization FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_CUSTOM = 4
+  };
+  const flatbuffers::Vector<uint8_t> *custom() const
+  {
+    return GetPointer<const flatbuffers::Vector<uint8_t> *>(VT_CUSTOM);
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyOffset(verifier, VT_CUSTOM) &&
+           verifier.VerifyVector(custom()) && verifier.EndTable();
+  }
+};
+
+struct CustomQuantizationBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_custom(flatbuffers::Offset<flatbuffers::Vector<uint8_t>> custom)
+  {
+    fbb_.AddOffset(CustomQuantization::VT_CUSTOM, custom);
+  }
+  explicit CustomQuantizationBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  CustomQuantizationBuilder &operator=(const CustomQuantizationBuilder &);
+  flatbuffers::Offset<CustomQuantization> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<CustomQuantization>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<CustomQuantization>
+CreateCustomQuantization(flatbuffers::FlatBufferBuilder &_fbb,
+                         flatbuffers::Offset<flatbuffers::Vector<uint8_t>> custom = 0)
+{
+  CustomQuantizationBuilder builder_(_fbb);
+  builder_.add_custom(custom);
+  return builder_.Finish();
+}
+
+inline flatbuffers::Offset<CustomQuantization>
+CreateCustomQuantizationDirect(flatbuffers::FlatBufferBuilder &_fbb,
+                               const std::vector<uint8_t> *custom = nullptr)
+{
+  return neurun_tflite::CreateCustomQuantization(_fbb,
+                                                 custom ? _fbb.CreateVector<uint8_t>(*custom) : 0);
+}
+
+struct QuantizationParameters FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_MIN = 4,
+    VT_MAX = 6,
+    VT_SCALE = 8,
+    VT_ZERO_POINT = 10,
+    VT_DETAILS_TYPE = 12,
+    VT_DETAILS = 14
+  };
+  const flatbuffers::Vector<float> *min() const
+  {
+    return GetPointer<const flatbuffers::Vector<float> *>(VT_MIN);
+  }
+  const flatbuffers::Vector<float> *max() const
+  {
+    return GetPointer<const flatbuffers::Vector<float> *>(VT_MAX);
+  }
+  const flatbuffers::Vector<float> *scale() const
+  {
+    return GetPointer<const flatbuffers::Vector<float> *>(VT_SCALE);
+  }
+  const flatbuffers::Vector<int64_t> *zero_point() const
+  {
+    return GetPointer<const flatbuffers::Vector<int64_t> *>(VT_ZERO_POINT);
+  }
+  QuantizationDetails details_type() const
+  {
+    return static_cast<QuantizationDetails>(GetField<uint8_t>(VT_DETAILS_TYPE, 0));
+  }
+  const void *details() const { return GetPointer<const void *>(VT_DETAILS); }
+  template <typename T> const T *details_as() const;
+  const CustomQuantization *details_as_CustomQuantization() const
+  {
+    return details_type() == QuantizationDetails_CustomQuantization
+               ? static_cast<const CustomQuantization *>(details())
+               : nullptr;
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyOffset(verifier, VT_MIN) &&
+           verifier.VerifyVector(min()) && VerifyOffset(verifier, VT_MAX) &&
+           verifier.VerifyVector(max()) && VerifyOffset(verifier, VT_SCALE) &&
+           verifier.VerifyVector(scale()) && VerifyOffset(verifier, VT_ZERO_POINT) &&
+           verifier.VerifyVector(zero_point()) && VerifyField<uint8_t>(verifier, VT_DETAILS_TYPE) &&
+           VerifyOffset(verifier, VT_DETAILS) &&
+           VerifyQuantizationDetails(verifier, details(), details_type()) && verifier.EndTable();
+  }
+};
+
+template <>
+inline const CustomQuantization *QuantizationParameters::details_as<CustomQuantization>() const
+{
+  return details_as_CustomQuantization();
+}
+
+struct QuantizationParametersBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_min(flatbuffers::Offset<flatbuffers::Vector<float>> min)
+  {
+    fbb_.AddOffset(QuantizationParameters::VT_MIN, min);
+  }
+  void add_max(flatbuffers::Offset<flatbuffers::Vector<float>> max)
+  {
+    fbb_.AddOffset(QuantizationParameters::VT_MAX, max);
+  }
+  void add_scale(flatbuffers::Offset<flatbuffers::Vector<float>> scale)
+  {
+    fbb_.AddOffset(QuantizationParameters::VT_SCALE, scale);
+  }
+  void add_zero_point(flatbuffers::Offset<flatbuffers::Vector<int64_t>> zero_point)
+  {
+    fbb_.AddOffset(QuantizationParameters::VT_ZERO_POINT, zero_point);
+  }
+  void add_details_type(QuantizationDetails details_type)
+  {
+    fbb_.AddElement<uint8_t>(QuantizationParameters::VT_DETAILS_TYPE,
+                             static_cast<uint8_t>(details_type), 0);
+  }
+  void add_details(flatbuffers::Offset<void> details)
+  {
+    fbb_.AddOffset(QuantizationParameters::VT_DETAILS, details);
+  }
+  explicit QuantizationParametersBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  QuantizationParametersBuilder &operator=(const QuantizationParametersBuilder &);
+  flatbuffers::Offset<QuantizationParameters> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<QuantizationParameters>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<QuantizationParameters>
+CreateQuantizationParameters(flatbuffers::FlatBufferBuilder &_fbb,
+                             flatbuffers::Offset<flatbuffers::Vector<float>> min = 0,
+                             flatbuffers::Offset<flatbuffers::Vector<float>> max = 0,
+                             flatbuffers::Offset<flatbuffers::Vector<float>> scale = 0,
+                             flatbuffers::Offset<flatbuffers::Vector<int64_t>> zero_point = 0,
+                             QuantizationDetails details_type = QuantizationDetails_NONE,
+                             flatbuffers::Offset<void> details = 0)
+{
+  QuantizationParametersBuilder builder_(_fbb);
+  builder_.add_details(details);
+  builder_.add_zero_point(zero_point);
+  builder_.add_scale(scale);
+  builder_.add_max(max);
+  builder_.add_min(min);
+  builder_.add_details_type(details_type);
+  return builder_.Finish();
+}
+
+inline flatbuffers::Offset<QuantizationParameters> CreateQuantizationParametersDirect(
+    flatbuffers::FlatBufferBuilder &_fbb, const std::vector<float> *min = nullptr,
+    const std::vector<float> *max = nullptr, const std::vector<float> *scale = nullptr,
+    const std::vector<int64_t> *zero_point = nullptr,
+    QuantizationDetails details_type = QuantizationDetails_NONE,
+    flatbuffers::Offset<void> details = 0)
+{
+  return neurun_tflite::CreateQuantizationParameters(
+      _fbb, min ? _fbb.CreateVector<float>(*min) : 0, max ? _fbb.CreateVector<float>(*max) : 0,
+      scale ? _fbb.CreateVector<float>(*scale) : 0,
+      zero_point ? _fbb.CreateVector<int64_t>(*zero_point) : 0, details_type, details);
+}
+
+struct Tensor FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_SHAPE = 4,
+    VT_TYPE = 6,
+    VT_BUFFER = 8,
+    VT_NAME = 10,
+    VT_QUANTIZATION = 12,
+    VT_IS_VARIABLE = 14
+  };
+  const flatbuffers::Vector<int32_t> *shape() const
+  {
+    return GetPointer<const flatbuffers::Vector<int32_t> *>(VT_SHAPE);
+  }
+  TensorType type() const { return static_cast<TensorType>(GetField<int8_t>(VT_TYPE, 0)); }
+  uint32_t buffer() const { return GetField<uint32_t>(VT_BUFFER, 0); }
+  const flatbuffers::String *name() const
+  {
+    return GetPointer<const flatbuffers::String *>(VT_NAME);
+  }
+  const QuantizationParameters *quantization() const
+  {
+    return GetPointer<const QuantizationParameters *>(VT_QUANTIZATION);
+  }
+  bool is_variable() const { return GetField<uint8_t>(VT_IS_VARIABLE, 0) != 0; }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyOffset(verifier, VT_SHAPE) &&
+           verifier.VerifyVector(shape()) && VerifyField<int8_t>(verifier, VT_TYPE) &&
+           VerifyField<uint32_t>(verifier, VT_BUFFER) && VerifyOffset(verifier, VT_NAME) &&
+           verifier.VerifyString(name()) && VerifyOffset(verifier, VT_QUANTIZATION) &&
+           verifier.VerifyTable(quantization()) && VerifyField<uint8_t>(verifier, VT_IS_VARIABLE) &&
+           verifier.EndTable();
+  }
+};
+
+struct TensorBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_shape(flatbuffers::Offset<flatbuffers::Vector<int32_t>> shape)
+  {
+    fbb_.AddOffset(Tensor::VT_SHAPE, shape);
+  }
+  void add_type(TensorType type)
+  {
+    fbb_.AddElement<int8_t>(Tensor::VT_TYPE, static_cast<int8_t>(type), 0);
+  }
+  void add_buffer(uint32_t buffer) { fbb_.AddElement<uint32_t>(Tensor::VT_BUFFER, buffer, 0); }
+  void add_name(flatbuffers::Offset<flatbuffers::String> name)
+  {
+    fbb_.AddOffset(Tensor::VT_NAME, name);
+  }
+  void add_quantization(flatbuffers::Offset<QuantizationParameters> quantization)
+  {
+    fbb_.AddOffset(Tensor::VT_QUANTIZATION, quantization);
+  }
+  void add_is_variable(bool is_variable)
+  {
+    fbb_.AddElement<uint8_t>(Tensor::VT_IS_VARIABLE, static_cast<uint8_t>(is_variable), 0);
+  }
+  explicit TensorBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  TensorBuilder &operator=(const TensorBuilder &);
+  flatbuffers::Offset<Tensor> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<Tensor>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<Tensor>
+CreateTensor(flatbuffers::FlatBufferBuilder &_fbb,
+             flatbuffers::Offset<flatbuffers::Vector<int32_t>> shape = 0,
+             TensorType type = TensorType_FLOAT32, uint32_t buffer = 0,
+             flatbuffers::Offset<flatbuffers::String> name = 0,
+             flatbuffers::Offset<QuantizationParameters> quantization = 0, bool is_variable = false)
+{
+  TensorBuilder builder_(_fbb);
+  builder_.add_quantization(quantization);
+  builder_.add_name(name);
+  builder_.add_buffer(buffer);
+  builder_.add_shape(shape);
+  builder_.add_is_variable(is_variable);
+  builder_.add_type(type);
+  return builder_.Finish();
+}
+
+inline flatbuffers::Offset<Tensor> CreateTensorDirect(
+    flatbuffers::FlatBufferBuilder &_fbb, const std::vector<int32_t> *shape = nullptr,
+    TensorType type = TensorType_FLOAT32, uint32_t buffer = 0, const char *name = nullptr,
+    flatbuffers::Offset<QuantizationParameters> quantization = 0, bool is_variable = false)
+{
+  return neurun_tflite::CreateTensor(_fbb, shape ? _fbb.CreateVector<int32_t>(*shape) : 0, type,
+                                     buffer, name ? _fbb.CreateString(name) : 0, quantization,
+                                     is_variable);
+}
+
+struct Conv2DOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_PADDING = 4,
+    VT_STRIDE_W = 6,
+    VT_STRIDE_H = 8,
+    VT_FUSED_ACTIVATION_FUNCTION = 10,
+    VT_DILATION_W_FACTOR = 12,
+    VT_DILATION_H_FACTOR = 14
+  };
+  Padding padding() const { return static_cast<Padding>(GetField<int8_t>(VT_PADDING, 0)); }
+  int32_t stride_w() const { return GetField<int32_t>(VT_STRIDE_W, 0); }
+  int32_t stride_h() const { return GetField<int32_t>(VT_STRIDE_H, 0); }
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  int32_t dilation_w_factor() const { return GetField<int32_t>(VT_DILATION_W_FACTOR, 1); }
+  int32_t dilation_h_factor() const { return GetField<int32_t>(VT_DILATION_H_FACTOR, 1); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int8_t>(verifier, VT_PADDING) &&
+           VerifyField<int32_t>(verifier, VT_STRIDE_W) &&
+           VerifyField<int32_t>(verifier, VT_STRIDE_H) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) &&
+           VerifyField<int32_t>(verifier, VT_DILATION_W_FACTOR) &&
+           VerifyField<int32_t>(verifier, VT_DILATION_H_FACTOR) && verifier.EndTable();
+  }
+};
+
+struct Conv2DOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_padding(Padding padding)
+  {
+    fbb_.AddElement<int8_t>(Conv2DOptions::VT_PADDING, static_cast<int8_t>(padding), 0);
+  }
+  void add_stride_w(int32_t stride_w)
+  {
+    fbb_.AddElement<int32_t>(Conv2DOptions::VT_STRIDE_W, stride_w, 0);
+  }
+  void add_stride_h(int32_t stride_h)
+  {
+    fbb_.AddElement<int32_t>(Conv2DOptions::VT_STRIDE_H, stride_h, 0);
+  }
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(Conv2DOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  void add_dilation_w_factor(int32_t dilation_w_factor)
+  {
+    fbb_.AddElement<int32_t>(Conv2DOptions::VT_DILATION_W_FACTOR, dilation_w_factor, 1);
+  }
+  void add_dilation_h_factor(int32_t dilation_h_factor)
+  {
+    fbb_.AddElement<int32_t>(Conv2DOptions::VT_DILATION_H_FACTOR, dilation_h_factor, 1);
+  }
+  explicit Conv2DOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  Conv2DOptionsBuilder &operator=(const Conv2DOptionsBuilder &);
+  flatbuffers::Offset<Conv2DOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<Conv2DOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<Conv2DOptions>
+CreateConv2DOptions(flatbuffers::FlatBufferBuilder &_fbb, Padding padding = Padding_SAME,
+                    int32_t stride_w = 0, int32_t stride_h = 0,
+                    ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE,
+                    int32_t dilation_w_factor = 1, int32_t dilation_h_factor = 1)
+{
+  Conv2DOptionsBuilder builder_(_fbb);
+  builder_.add_dilation_h_factor(dilation_h_factor);
+  builder_.add_dilation_w_factor(dilation_w_factor);
+  builder_.add_stride_h(stride_h);
+  builder_.add_stride_w(stride_w);
+  builder_.add_fused_activation_function(fused_activation_function);
+  builder_.add_padding(padding);
+  return builder_.Finish();
+}
+
+struct Pool2DOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_PADDING = 4,
+    VT_STRIDE_W = 6,
+    VT_STRIDE_H = 8,
+    VT_FILTER_WIDTH = 10,
+    VT_FILTER_HEIGHT = 12,
+    VT_FUSED_ACTIVATION_FUNCTION = 14
+  };
+  Padding padding() const { return static_cast<Padding>(GetField<int8_t>(VT_PADDING, 0)); }
+  int32_t stride_w() const { return GetField<int32_t>(VT_STRIDE_W, 0); }
+  int32_t stride_h() const { return GetField<int32_t>(VT_STRIDE_H, 0); }
+  int32_t filter_width() const { return GetField<int32_t>(VT_FILTER_WIDTH, 0); }
+  int32_t filter_height() const { return GetField<int32_t>(VT_FILTER_HEIGHT, 0); }
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int8_t>(verifier, VT_PADDING) &&
+           VerifyField<int32_t>(verifier, VT_STRIDE_W) &&
+           VerifyField<int32_t>(verifier, VT_STRIDE_H) &&
+           VerifyField<int32_t>(verifier, VT_FILTER_WIDTH) &&
+           VerifyField<int32_t>(verifier, VT_FILTER_HEIGHT) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) && verifier.EndTable();
+  }
+};
+
+struct Pool2DOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_padding(Padding padding)
+  {
+    fbb_.AddElement<int8_t>(Pool2DOptions::VT_PADDING, static_cast<int8_t>(padding), 0);
+  }
+  void add_stride_w(int32_t stride_w)
+  {
+    fbb_.AddElement<int32_t>(Pool2DOptions::VT_STRIDE_W, stride_w, 0);
+  }
+  void add_stride_h(int32_t stride_h)
+  {
+    fbb_.AddElement<int32_t>(Pool2DOptions::VT_STRIDE_H, stride_h, 0);
+  }
+  void add_filter_width(int32_t filter_width)
+  {
+    fbb_.AddElement<int32_t>(Pool2DOptions::VT_FILTER_WIDTH, filter_width, 0);
+  }
+  void add_filter_height(int32_t filter_height)
+  {
+    fbb_.AddElement<int32_t>(Pool2DOptions::VT_FILTER_HEIGHT, filter_height, 0);
+  }
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(Pool2DOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  explicit Pool2DOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  Pool2DOptionsBuilder &operator=(const Pool2DOptionsBuilder &);
+  flatbuffers::Offset<Pool2DOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<Pool2DOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<Pool2DOptions>
+CreatePool2DOptions(flatbuffers::FlatBufferBuilder &_fbb, Padding padding = Padding_SAME,
+                    int32_t stride_w = 0, int32_t stride_h = 0, int32_t filter_width = 0,
+                    int32_t filter_height = 0,
+                    ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE)
+{
+  Pool2DOptionsBuilder builder_(_fbb);
+  builder_.add_filter_height(filter_height);
+  builder_.add_filter_width(filter_width);
+  builder_.add_stride_h(stride_h);
+  builder_.add_stride_w(stride_w);
+  builder_.add_fused_activation_function(fused_activation_function);
+  builder_.add_padding(padding);
+  return builder_.Finish();
+}
+
+struct DepthwiseConv2DOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_PADDING = 4,
+    VT_STRIDE_W = 6,
+    VT_STRIDE_H = 8,
+    VT_DEPTH_MULTIPLIER = 10,
+    VT_FUSED_ACTIVATION_FUNCTION = 12,
+    VT_DILATION_W_FACTOR = 14,
+    VT_DILATION_H_FACTOR = 16
+  };
+  Padding padding() const { return static_cast<Padding>(GetField<int8_t>(VT_PADDING, 0)); }
+  int32_t stride_w() const { return GetField<int32_t>(VT_STRIDE_W, 0); }
+  int32_t stride_h() const { return GetField<int32_t>(VT_STRIDE_H, 0); }
+  int32_t depth_multiplier() const { return GetField<int32_t>(VT_DEPTH_MULTIPLIER, 0); }
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  int32_t dilation_w_factor() const { return GetField<int32_t>(VT_DILATION_W_FACTOR, 1); }
+  int32_t dilation_h_factor() const { return GetField<int32_t>(VT_DILATION_H_FACTOR, 1); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int8_t>(verifier, VT_PADDING) &&
+           VerifyField<int32_t>(verifier, VT_STRIDE_W) &&
+           VerifyField<int32_t>(verifier, VT_STRIDE_H) &&
+           VerifyField<int32_t>(verifier, VT_DEPTH_MULTIPLIER) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) &&
+           VerifyField<int32_t>(verifier, VT_DILATION_W_FACTOR) &&
+           VerifyField<int32_t>(verifier, VT_DILATION_H_FACTOR) && verifier.EndTable();
+  }
+};
+
+struct DepthwiseConv2DOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_padding(Padding padding)
+  {
+    fbb_.AddElement<int8_t>(DepthwiseConv2DOptions::VT_PADDING, static_cast<int8_t>(padding), 0);
+  }
+  void add_stride_w(int32_t stride_w)
+  {
+    fbb_.AddElement<int32_t>(DepthwiseConv2DOptions::VT_STRIDE_W, stride_w, 0);
+  }
+  void add_stride_h(int32_t stride_h)
+  {
+    fbb_.AddElement<int32_t>(DepthwiseConv2DOptions::VT_STRIDE_H, stride_h, 0);
+  }
+  void add_depth_multiplier(int32_t depth_multiplier)
+  {
+    fbb_.AddElement<int32_t>(DepthwiseConv2DOptions::VT_DEPTH_MULTIPLIER, depth_multiplier, 0);
+  }
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(DepthwiseConv2DOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  void add_dilation_w_factor(int32_t dilation_w_factor)
+  {
+    fbb_.AddElement<int32_t>(DepthwiseConv2DOptions::VT_DILATION_W_FACTOR, dilation_w_factor, 1);
+  }
+  void add_dilation_h_factor(int32_t dilation_h_factor)
+  {
+    fbb_.AddElement<int32_t>(DepthwiseConv2DOptions::VT_DILATION_H_FACTOR, dilation_h_factor, 1);
+  }
+  explicit DepthwiseConv2DOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  DepthwiseConv2DOptionsBuilder &operator=(const DepthwiseConv2DOptionsBuilder &);
+  flatbuffers::Offset<DepthwiseConv2DOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<DepthwiseConv2DOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<DepthwiseConv2DOptions> CreateDepthwiseConv2DOptions(
+    flatbuffers::FlatBufferBuilder &_fbb, Padding padding = Padding_SAME, int32_t stride_w = 0,
+    int32_t stride_h = 0, int32_t depth_multiplier = 0,
+    ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE,
+    int32_t dilation_w_factor = 1, int32_t dilation_h_factor = 1)
+{
+  DepthwiseConv2DOptionsBuilder builder_(_fbb);
+  builder_.add_dilation_h_factor(dilation_h_factor);
+  builder_.add_dilation_w_factor(dilation_w_factor);
+  builder_.add_depth_multiplier(depth_multiplier);
+  builder_.add_stride_h(stride_h);
+  builder_.add_stride_w(stride_w);
+  builder_.add_fused_activation_function(fused_activation_function);
+  builder_.add_padding(padding);
+  return builder_.Finish();
+}
+
+struct ConcatEmbeddingsOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_NUM_CHANNELS = 4,
+    VT_NUM_COLUMNS_PER_CHANNEL = 6,
+    VT_EMBEDDING_DIM_PER_CHANNEL = 8
+  };
+  int32_t num_channels() const { return GetField<int32_t>(VT_NUM_CHANNELS, 0); }
+  const flatbuffers::Vector<int32_t> *num_columns_per_channel() const
+  {
+    return GetPointer<const flatbuffers::Vector<int32_t> *>(VT_NUM_COLUMNS_PER_CHANNEL);
+  }
+  const flatbuffers::Vector<int32_t> *embedding_dim_per_channel() const
+  {
+    return GetPointer<const flatbuffers::Vector<int32_t> *>(VT_EMBEDDING_DIM_PER_CHANNEL);
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int32_t>(verifier, VT_NUM_CHANNELS) &&
+           VerifyOffset(verifier, VT_NUM_COLUMNS_PER_CHANNEL) &&
+           verifier.VerifyVector(num_columns_per_channel()) &&
+           VerifyOffset(verifier, VT_EMBEDDING_DIM_PER_CHANNEL) &&
+           verifier.VerifyVector(embedding_dim_per_channel()) && verifier.EndTable();
+  }
+};
+
+struct ConcatEmbeddingsOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_num_channels(int32_t num_channels)
+  {
+    fbb_.AddElement<int32_t>(ConcatEmbeddingsOptions::VT_NUM_CHANNELS, num_channels, 0);
+  }
+  void add_num_columns_per_channel(
+      flatbuffers::Offset<flatbuffers::Vector<int32_t>> num_columns_per_channel)
+  {
+    fbb_.AddOffset(ConcatEmbeddingsOptions::VT_NUM_COLUMNS_PER_CHANNEL, num_columns_per_channel);
+  }
+  void add_embedding_dim_per_channel(
+      flatbuffers::Offset<flatbuffers::Vector<int32_t>> embedding_dim_per_channel)
+  {
+    fbb_.AddOffset(ConcatEmbeddingsOptions::VT_EMBEDDING_DIM_PER_CHANNEL,
+                   embedding_dim_per_channel);
+  }
+  explicit ConcatEmbeddingsOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  ConcatEmbeddingsOptionsBuilder &operator=(const ConcatEmbeddingsOptionsBuilder &);
+  flatbuffers::Offset<ConcatEmbeddingsOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<ConcatEmbeddingsOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<ConcatEmbeddingsOptions> CreateConcatEmbeddingsOptions(
+    flatbuffers::FlatBufferBuilder &_fbb, int32_t num_channels = 0,
+    flatbuffers::Offset<flatbuffers::Vector<int32_t>> num_columns_per_channel = 0,
+    flatbuffers::Offset<flatbuffers::Vector<int32_t>> embedding_dim_per_channel = 0)
+{
+  ConcatEmbeddingsOptionsBuilder builder_(_fbb);
+  builder_.add_embedding_dim_per_channel(embedding_dim_per_channel);
+  builder_.add_num_columns_per_channel(num_columns_per_channel);
+  builder_.add_num_channels(num_channels);
+  return builder_.Finish();
+}
+
+inline flatbuffers::Offset<ConcatEmbeddingsOptions>
+CreateConcatEmbeddingsOptionsDirect(flatbuffers::FlatBufferBuilder &_fbb, int32_t num_channels = 0,
+                                    const std::vector<int32_t> *num_columns_per_channel = nullptr,
+                                    const std::vector<int32_t> *embedding_dim_per_channel = nullptr)
+{
+  return neurun_tflite::CreateConcatEmbeddingsOptions(
+      _fbb, num_channels,
+      num_columns_per_channel ? _fbb.CreateVector<int32_t>(*num_columns_per_channel) : 0,
+      embedding_dim_per_channel ? _fbb.CreateVector<int32_t>(*embedding_dim_per_channel) : 0);
+}
+
+struct LSHProjectionOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_TYPE = 4
+  };
+  LSHProjectionType type() const
+  {
+    return static_cast<LSHProjectionType>(GetField<int8_t>(VT_TYPE, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int8_t>(verifier, VT_TYPE) &&
+           verifier.EndTable();
+  }
+};
+
+struct LSHProjectionOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_type(LSHProjectionType type)
+  {
+    fbb_.AddElement<int8_t>(LSHProjectionOptions::VT_TYPE, static_cast<int8_t>(type), 0);
+  }
+  explicit LSHProjectionOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  LSHProjectionOptionsBuilder &operator=(const LSHProjectionOptionsBuilder &);
+  flatbuffers::Offset<LSHProjectionOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<LSHProjectionOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<LSHProjectionOptions>
+CreateLSHProjectionOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                           LSHProjectionType type = LSHProjectionType_UNKNOWN)
+{
+  LSHProjectionOptionsBuilder builder_(_fbb);
+  builder_.add_type(type);
+  return builder_.Finish();
+}
+
+struct SVDFOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_RANK = 4,
+    VT_FUSED_ACTIVATION_FUNCTION = 6
+  };
+  int32_t rank() const { return GetField<int32_t>(VT_RANK, 0); }
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int32_t>(verifier, VT_RANK) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) && verifier.EndTable();
+  }
+};
+
+struct SVDFOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_rank(int32_t rank) { fbb_.AddElement<int32_t>(SVDFOptions::VT_RANK, rank, 0); }
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(SVDFOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  explicit SVDFOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  SVDFOptionsBuilder &operator=(const SVDFOptionsBuilder &);
+  flatbuffers::Offset<SVDFOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<SVDFOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<SVDFOptions>
+CreateSVDFOptions(flatbuffers::FlatBufferBuilder &_fbb, int32_t rank = 0,
+                  ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE)
+{
+  SVDFOptionsBuilder builder_(_fbb);
+  builder_.add_rank(rank);
+  builder_.add_fused_activation_function(fused_activation_function);
+  return builder_.Finish();
+}
+
+struct RNNOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_FUSED_ACTIVATION_FUNCTION = 4
+  };
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) && verifier.EndTable();
+  }
+};
+
+struct RNNOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(RNNOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  explicit RNNOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  RNNOptionsBuilder &operator=(const RNNOptionsBuilder &);
+  flatbuffers::Offset<RNNOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<RNNOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<RNNOptions>
+CreateRNNOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                 ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE)
+{
+  RNNOptionsBuilder builder_(_fbb);
+  builder_.add_fused_activation_function(fused_activation_function);
+  return builder_.Finish();
+}
+
+struct SequenceRNNOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_TIME_MAJOR = 4,
+    VT_FUSED_ACTIVATION_FUNCTION = 6
+  };
+  bool time_major() const { return GetField<uint8_t>(VT_TIME_MAJOR, 0) != 0; }
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<uint8_t>(verifier, VT_TIME_MAJOR) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) && verifier.EndTable();
+  }
+};
+
+struct SequenceRNNOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_time_major(bool time_major)
+  {
+    fbb_.AddElement<uint8_t>(SequenceRNNOptions::VT_TIME_MAJOR, static_cast<uint8_t>(time_major),
+                             0);
+  }
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(SequenceRNNOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  explicit SequenceRNNOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  SequenceRNNOptionsBuilder &operator=(const SequenceRNNOptionsBuilder &);
+  flatbuffers::Offset<SequenceRNNOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<SequenceRNNOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<SequenceRNNOptions> CreateSequenceRNNOptions(
+    flatbuffers::FlatBufferBuilder &_fbb, bool time_major = false,
+    ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE)
+{
+  SequenceRNNOptionsBuilder builder_(_fbb);
+  builder_.add_fused_activation_function(fused_activation_function);
+  builder_.add_time_major(time_major);
+  return builder_.Finish();
+}
+
+struct BidirectionalSequenceRNNOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_TIME_MAJOR = 4,
+    VT_FUSED_ACTIVATION_FUNCTION = 6,
+    VT_MERGE_OUTPUTS = 8
+  };
+  bool time_major() const { return GetField<uint8_t>(VT_TIME_MAJOR, 0) != 0; }
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  bool merge_outputs() const { return GetField<uint8_t>(VT_MERGE_OUTPUTS, 0) != 0; }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<uint8_t>(verifier, VT_TIME_MAJOR) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) &&
+           VerifyField<uint8_t>(verifier, VT_MERGE_OUTPUTS) && verifier.EndTable();
+  }
+};
+
+struct BidirectionalSequenceRNNOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_time_major(bool time_major)
+  {
+    fbb_.AddElement<uint8_t>(BidirectionalSequenceRNNOptions::VT_TIME_MAJOR,
+                             static_cast<uint8_t>(time_major), 0);
+  }
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(BidirectionalSequenceRNNOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  void add_merge_outputs(bool merge_outputs)
+  {
+    fbb_.AddElement<uint8_t>(BidirectionalSequenceRNNOptions::VT_MERGE_OUTPUTS,
+                             static_cast<uint8_t>(merge_outputs), 0);
+  }
+  explicit BidirectionalSequenceRNNOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  BidirectionalSequenceRNNOptionsBuilder &operator=(const BidirectionalSequenceRNNOptionsBuilder &);
+  flatbuffers::Offset<BidirectionalSequenceRNNOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<BidirectionalSequenceRNNOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<BidirectionalSequenceRNNOptions> CreateBidirectionalSequenceRNNOptions(
+    flatbuffers::FlatBufferBuilder &_fbb, bool time_major = false,
+    ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE,
+    bool merge_outputs = false)
+{
+  BidirectionalSequenceRNNOptionsBuilder builder_(_fbb);
+  builder_.add_merge_outputs(merge_outputs);
+  builder_.add_fused_activation_function(fused_activation_function);
+  builder_.add_time_major(time_major);
+  return builder_.Finish();
+}
+
+struct FullyConnectedOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_FUSED_ACTIVATION_FUNCTION = 4,
+    VT_WEIGHTS_FORMAT = 6
+  };
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  FullyConnectedOptionsWeightsFormat weights_format() const
+  {
+    return static_cast<FullyConnectedOptionsWeightsFormat>(GetField<int8_t>(VT_WEIGHTS_FORMAT, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) &&
+           VerifyField<int8_t>(verifier, VT_WEIGHTS_FORMAT) && verifier.EndTable();
+  }
+};
+
+struct FullyConnectedOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(FullyConnectedOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  void add_weights_format(FullyConnectedOptionsWeightsFormat weights_format)
+  {
+    fbb_.AddElement<int8_t>(FullyConnectedOptions::VT_WEIGHTS_FORMAT,
+                            static_cast<int8_t>(weights_format), 0);
+  }
+  explicit FullyConnectedOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  FullyConnectedOptionsBuilder &operator=(const FullyConnectedOptionsBuilder &);
+  flatbuffers::Offset<FullyConnectedOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<FullyConnectedOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<FullyConnectedOptions> CreateFullyConnectedOptions(
+    flatbuffers::FlatBufferBuilder &_fbb,
+    ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE,
+    FullyConnectedOptionsWeightsFormat weights_format = FullyConnectedOptionsWeightsFormat_DEFAULT)
+{
+  FullyConnectedOptionsBuilder builder_(_fbb);
+  builder_.add_weights_format(weights_format);
+  builder_.add_fused_activation_function(fused_activation_function);
+  return builder_.Finish();
+}
+
+struct SoftmaxOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_BETA = 4
+  };
+  float beta() const { return GetField<float>(VT_BETA, 0.0f); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<float>(verifier, VT_BETA) &&
+           verifier.EndTable();
+  }
+};
+
+struct SoftmaxOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_beta(float beta) { fbb_.AddElement<float>(SoftmaxOptions::VT_BETA, beta, 0.0f); }
+  explicit SoftmaxOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  SoftmaxOptionsBuilder &operator=(const SoftmaxOptionsBuilder &);
+  flatbuffers::Offset<SoftmaxOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<SoftmaxOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<SoftmaxOptions>
+CreateSoftmaxOptions(flatbuffers::FlatBufferBuilder &_fbb, float beta = 0.0f)
+{
+  SoftmaxOptionsBuilder builder_(_fbb);
+  builder_.add_beta(beta);
+  return builder_.Finish();
+}
+
+struct ConcatenationOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_AXIS = 4,
+    VT_FUSED_ACTIVATION_FUNCTION = 6
+  };
+  int32_t axis() const { return GetField<int32_t>(VT_AXIS, 0); }
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int32_t>(verifier, VT_AXIS) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) && verifier.EndTable();
+  }
+};
+
+struct ConcatenationOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_axis(int32_t axis) { fbb_.AddElement<int32_t>(ConcatenationOptions::VT_AXIS, axis, 0); }
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(ConcatenationOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  explicit ConcatenationOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  ConcatenationOptionsBuilder &operator=(const ConcatenationOptionsBuilder &);
+  flatbuffers::Offset<ConcatenationOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<ConcatenationOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<ConcatenationOptions> CreateConcatenationOptions(
+    flatbuffers::FlatBufferBuilder &_fbb, int32_t axis = 0,
+    ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE)
+{
+  ConcatenationOptionsBuilder builder_(_fbb);
+  builder_.add_axis(axis);
+  builder_.add_fused_activation_function(fused_activation_function);
+  return builder_.Finish();
+}
+
+struct AddOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_FUSED_ACTIVATION_FUNCTION = 4
+  };
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) && verifier.EndTable();
+  }
+};
+
+struct AddOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(AddOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  explicit AddOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  AddOptionsBuilder &operator=(const AddOptionsBuilder &);
+  flatbuffers::Offset<AddOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<AddOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<AddOptions>
+CreateAddOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                 ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE)
+{
+  AddOptionsBuilder builder_(_fbb);
+  builder_.add_fused_activation_function(fused_activation_function);
+  return builder_.Finish();
+}
+
+struct MulOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_FUSED_ACTIVATION_FUNCTION = 4
+  };
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) && verifier.EndTable();
+  }
+};
+
+struct MulOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(MulOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  explicit MulOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  MulOptionsBuilder &operator=(const MulOptionsBuilder &);
+  flatbuffers::Offset<MulOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<MulOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<MulOptions>
+CreateMulOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                 ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE)
+{
+  MulOptionsBuilder builder_(_fbb);
+  builder_.add_fused_activation_function(fused_activation_function);
+  return builder_.Finish();
+}
+
+struct L2NormOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_FUSED_ACTIVATION_FUNCTION = 4
+  };
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) && verifier.EndTable();
+  }
+};
+
+struct L2NormOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(L2NormOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  explicit L2NormOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  L2NormOptionsBuilder &operator=(const L2NormOptionsBuilder &);
+  flatbuffers::Offset<L2NormOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<L2NormOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<L2NormOptions>
+CreateL2NormOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                    ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE)
+{
+  L2NormOptionsBuilder builder_(_fbb);
+  builder_.add_fused_activation_function(fused_activation_function);
+  return builder_.Finish();
+}
+
+struct LocalResponseNormalizationOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_RADIUS = 4,
+    VT_BIAS = 6,
+    VT_ALPHA = 8,
+    VT_BETA = 10
+  };
+  int32_t radius() const { return GetField<int32_t>(VT_RADIUS, 0); }
+  float bias() const { return GetField<float>(VT_BIAS, 0.0f); }
+  float alpha() const { return GetField<float>(VT_ALPHA, 0.0f); }
+  float beta() const { return GetField<float>(VT_BETA, 0.0f); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int32_t>(verifier, VT_RADIUS) &&
+           VerifyField<float>(verifier, VT_BIAS) && VerifyField<float>(verifier, VT_ALPHA) &&
+           VerifyField<float>(verifier, VT_BETA) && verifier.EndTable();
+  }
+};
+
+struct LocalResponseNormalizationOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_radius(int32_t radius)
+  {
+    fbb_.AddElement<int32_t>(LocalResponseNormalizationOptions::VT_RADIUS, radius, 0);
+  }
+  void add_bias(float bias)
+  {
+    fbb_.AddElement<float>(LocalResponseNormalizationOptions::VT_BIAS, bias, 0.0f);
+  }
+  void add_alpha(float alpha)
+  {
+    fbb_.AddElement<float>(LocalResponseNormalizationOptions::VT_ALPHA, alpha, 0.0f);
+  }
+  void add_beta(float beta)
+  {
+    fbb_.AddElement<float>(LocalResponseNormalizationOptions::VT_BETA, beta, 0.0f);
+  }
+  explicit LocalResponseNormalizationOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb)
+      : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  LocalResponseNormalizationOptionsBuilder &
+  operator=(const LocalResponseNormalizationOptionsBuilder &);
+  flatbuffers::Offset<LocalResponseNormalizationOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<LocalResponseNormalizationOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<LocalResponseNormalizationOptions>
+CreateLocalResponseNormalizationOptions(flatbuffers::FlatBufferBuilder &_fbb, int32_t radius = 0,
+                                        float bias = 0.0f, float alpha = 0.0f, float beta = 0.0f)
+{
+  LocalResponseNormalizationOptionsBuilder builder_(_fbb);
+  builder_.add_beta(beta);
+  builder_.add_alpha(alpha);
+  builder_.add_bias(bias);
+  builder_.add_radius(radius);
+  return builder_.Finish();
+}
+
+struct LSTMOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_FUSED_ACTIVATION_FUNCTION = 4,
+    VT_CELL_CLIP = 6,
+    VT_PROJ_CLIP = 8,
+    VT_KERNEL_TYPE = 10
+  };
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  float cell_clip() const { return GetField<float>(VT_CELL_CLIP, 0.0f); }
+  float proj_clip() const { return GetField<float>(VT_PROJ_CLIP, 0.0f); }
+  LSTMKernelType kernel_type() const
+  {
+    return static_cast<LSTMKernelType>(GetField<int8_t>(VT_KERNEL_TYPE, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) &&
+           VerifyField<float>(verifier, VT_CELL_CLIP) &&
+           VerifyField<float>(verifier, VT_PROJ_CLIP) &&
+           VerifyField<int8_t>(verifier, VT_KERNEL_TYPE) && verifier.EndTable();
+  }
+};
+
+struct LSTMOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(LSTMOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  void add_cell_clip(float cell_clip)
+  {
+    fbb_.AddElement<float>(LSTMOptions::VT_CELL_CLIP, cell_clip, 0.0f);
+  }
+  void add_proj_clip(float proj_clip)
+  {
+    fbb_.AddElement<float>(LSTMOptions::VT_PROJ_CLIP, proj_clip, 0.0f);
+  }
+  void add_kernel_type(LSTMKernelType kernel_type)
+  {
+    fbb_.AddElement<int8_t>(LSTMOptions::VT_KERNEL_TYPE, static_cast<int8_t>(kernel_type), 0);
+  }
+  explicit LSTMOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  LSTMOptionsBuilder &operator=(const LSTMOptionsBuilder &);
+  flatbuffers::Offset<LSTMOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<LSTMOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<LSTMOptions>
+CreateLSTMOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                  ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE,
+                  float cell_clip = 0.0f, float proj_clip = 0.0f,
+                  LSTMKernelType kernel_type = LSTMKernelType_FULL)
+{
+  LSTMOptionsBuilder builder_(_fbb);
+  builder_.add_proj_clip(proj_clip);
+  builder_.add_cell_clip(cell_clip);
+  builder_.add_kernel_type(kernel_type);
+  builder_.add_fused_activation_function(fused_activation_function);
+  return builder_.Finish();
+}
+
+struct UnidirectionalSequenceLSTMOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_FUSED_ACTIVATION_FUNCTION = 4,
+    VT_CELL_CLIP = 6,
+    VT_PROJ_CLIP = 8,
+    VT_TIME_MAJOR = 10
+  };
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  float cell_clip() const { return GetField<float>(VT_CELL_CLIP, 0.0f); }
+  float proj_clip() const { return GetField<float>(VT_PROJ_CLIP, 0.0f); }
+  bool time_major() const { return GetField<uint8_t>(VT_TIME_MAJOR, 0) != 0; }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) &&
+           VerifyField<float>(verifier, VT_CELL_CLIP) &&
+           VerifyField<float>(verifier, VT_PROJ_CLIP) &&
+           VerifyField<uint8_t>(verifier, VT_TIME_MAJOR) && verifier.EndTable();
+  }
+};
+
+struct UnidirectionalSequenceLSTMOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(UnidirectionalSequenceLSTMOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  void add_cell_clip(float cell_clip)
+  {
+    fbb_.AddElement<float>(UnidirectionalSequenceLSTMOptions::VT_CELL_CLIP, cell_clip, 0.0f);
+  }
+  void add_proj_clip(float proj_clip)
+  {
+    fbb_.AddElement<float>(UnidirectionalSequenceLSTMOptions::VT_PROJ_CLIP, proj_clip, 0.0f);
+  }
+  void add_time_major(bool time_major)
+  {
+    fbb_.AddElement<uint8_t>(UnidirectionalSequenceLSTMOptions::VT_TIME_MAJOR,
+                             static_cast<uint8_t>(time_major), 0);
+  }
+  explicit UnidirectionalSequenceLSTMOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb)
+      : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  UnidirectionalSequenceLSTMOptionsBuilder &
+  operator=(const UnidirectionalSequenceLSTMOptionsBuilder &);
+  flatbuffers::Offset<UnidirectionalSequenceLSTMOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<UnidirectionalSequenceLSTMOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<UnidirectionalSequenceLSTMOptions>
+CreateUnidirectionalSequenceLSTMOptions(
+    flatbuffers::FlatBufferBuilder &_fbb,
+    ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE,
+    float cell_clip = 0.0f, float proj_clip = 0.0f, bool time_major = false)
+{
+  UnidirectionalSequenceLSTMOptionsBuilder builder_(_fbb);
+  builder_.add_proj_clip(proj_clip);
+  builder_.add_cell_clip(cell_clip);
+  builder_.add_time_major(time_major);
+  builder_.add_fused_activation_function(fused_activation_function);
+  return builder_.Finish();
+}
+
+struct BidirectionalSequenceLSTMOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_FUSED_ACTIVATION_FUNCTION = 4,
+    VT_CELL_CLIP = 6,
+    VT_PROJ_CLIP = 8,
+    VT_MERGE_OUTPUTS = 10
+  };
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  float cell_clip() const { return GetField<float>(VT_CELL_CLIP, 0.0f); }
+  float proj_clip() const { return GetField<float>(VT_PROJ_CLIP, 0.0f); }
+  bool merge_outputs() const { return GetField<uint8_t>(VT_MERGE_OUTPUTS, 0) != 0; }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) &&
+           VerifyField<float>(verifier, VT_CELL_CLIP) &&
+           VerifyField<float>(verifier, VT_PROJ_CLIP) &&
+           VerifyField<uint8_t>(verifier, VT_MERGE_OUTPUTS) && verifier.EndTable();
+  }
+};
+
+struct BidirectionalSequenceLSTMOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(BidirectionalSequenceLSTMOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  void add_cell_clip(float cell_clip)
+  {
+    fbb_.AddElement<float>(BidirectionalSequenceLSTMOptions::VT_CELL_CLIP, cell_clip, 0.0f);
+  }
+  void add_proj_clip(float proj_clip)
+  {
+    fbb_.AddElement<float>(BidirectionalSequenceLSTMOptions::VT_PROJ_CLIP, proj_clip, 0.0f);
+  }
+  void add_merge_outputs(bool merge_outputs)
+  {
+    fbb_.AddElement<uint8_t>(BidirectionalSequenceLSTMOptions::VT_MERGE_OUTPUTS,
+                             static_cast<uint8_t>(merge_outputs), 0);
+  }
+  explicit BidirectionalSequenceLSTMOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb)
+      : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  BidirectionalSequenceLSTMOptionsBuilder &
+  operator=(const BidirectionalSequenceLSTMOptionsBuilder &);
+  flatbuffers::Offset<BidirectionalSequenceLSTMOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<BidirectionalSequenceLSTMOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<BidirectionalSequenceLSTMOptions> CreateBidirectionalSequenceLSTMOptions(
+    flatbuffers::FlatBufferBuilder &_fbb,
+    ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE,
+    float cell_clip = 0.0f, float proj_clip = 0.0f, bool merge_outputs = false)
+{
+  BidirectionalSequenceLSTMOptionsBuilder builder_(_fbb);
+  builder_.add_proj_clip(proj_clip);
+  builder_.add_cell_clip(cell_clip);
+  builder_.add_merge_outputs(merge_outputs);
+  builder_.add_fused_activation_function(fused_activation_function);
+  return builder_.Finish();
+}
+
+struct ResizeBilinearOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_ALIGN_CORNERS = 8
+  };
+  bool align_corners() const { return GetField<uint8_t>(VT_ALIGN_CORNERS, 0) != 0; }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<uint8_t>(verifier, VT_ALIGN_CORNERS) &&
+           verifier.EndTable();
+  }
+};
+
+struct ResizeBilinearOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_align_corners(bool align_corners)
+  {
+    fbb_.AddElement<uint8_t>(ResizeBilinearOptions::VT_ALIGN_CORNERS,
+                             static_cast<uint8_t>(align_corners), 0);
+  }
+  explicit ResizeBilinearOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  ResizeBilinearOptionsBuilder &operator=(const ResizeBilinearOptionsBuilder &);
+  flatbuffers::Offset<ResizeBilinearOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<ResizeBilinearOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<ResizeBilinearOptions>
+CreateResizeBilinearOptions(flatbuffers::FlatBufferBuilder &_fbb, bool align_corners = false)
+{
+  ResizeBilinearOptionsBuilder builder_(_fbb);
+  builder_.add_align_corners(align_corners);
+  return builder_.Finish();
+}
+
+struct ResizeNearestNeighborOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_ALIGN_CORNERS = 4
+  };
+  bool align_corners() const { return GetField<uint8_t>(VT_ALIGN_CORNERS, 0) != 0; }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<uint8_t>(verifier, VT_ALIGN_CORNERS) &&
+           verifier.EndTable();
+  }
+};
+
+struct ResizeNearestNeighborOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_align_corners(bool align_corners)
+  {
+    fbb_.AddElement<uint8_t>(ResizeNearestNeighborOptions::VT_ALIGN_CORNERS,
+                             static_cast<uint8_t>(align_corners), 0);
+  }
+  explicit ResizeNearestNeighborOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  ResizeNearestNeighborOptionsBuilder &operator=(const ResizeNearestNeighborOptionsBuilder &);
+  flatbuffers::Offset<ResizeNearestNeighborOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<ResizeNearestNeighborOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<ResizeNearestNeighborOptions>
+CreateResizeNearestNeighborOptions(flatbuffers::FlatBufferBuilder &_fbb, bool align_corners = false)
+{
+  ResizeNearestNeighborOptionsBuilder builder_(_fbb);
+  builder_.add_align_corners(align_corners);
+  return builder_.Finish();
+}
+
+struct CallOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_SUBGRAPH = 4
+  };
+  uint32_t subgraph() const { return GetField<uint32_t>(VT_SUBGRAPH, 0); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<uint32_t>(verifier, VT_SUBGRAPH) &&
+           verifier.EndTable();
+  }
+};
+
+struct CallOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_subgraph(uint32_t subgraph)
+  {
+    fbb_.AddElement<uint32_t>(CallOptions::VT_SUBGRAPH, subgraph, 0);
+  }
+  explicit CallOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  CallOptionsBuilder &operator=(const CallOptionsBuilder &);
+  flatbuffers::Offset<CallOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<CallOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<CallOptions> CreateCallOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                                                          uint32_t subgraph = 0)
+{
+  CallOptionsBuilder builder_(_fbb);
+  builder_.add_subgraph(subgraph);
+  return builder_.Finish();
+}
+
+struct PadOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct PadOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit PadOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  PadOptionsBuilder &operator=(const PadOptionsBuilder &);
+  flatbuffers::Offset<PadOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<PadOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<PadOptions> CreatePadOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  PadOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct PadV2Options FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct PadV2OptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit PadV2OptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  PadV2OptionsBuilder &operator=(const PadV2OptionsBuilder &);
+  flatbuffers::Offset<PadV2Options> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<PadV2Options>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<PadV2Options> CreatePadV2Options(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  PadV2OptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct ReshapeOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_NEW_SHAPE = 4
+  };
+  const flatbuffers::Vector<int32_t> *new_shape() const
+  {
+    return GetPointer<const flatbuffers::Vector<int32_t> *>(VT_NEW_SHAPE);
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyOffset(verifier, VT_NEW_SHAPE) &&
+           verifier.VerifyVector(new_shape()) && verifier.EndTable();
+  }
+};
+
+struct ReshapeOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_new_shape(flatbuffers::Offset<flatbuffers::Vector<int32_t>> new_shape)
+  {
+    fbb_.AddOffset(ReshapeOptions::VT_NEW_SHAPE, new_shape);
+  }
+  explicit ReshapeOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  ReshapeOptionsBuilder &operator=(const ReshapeOptionsBuilder &);
+  flatbuffers::Offset<ReshapeOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<ReshapeOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<ReshapeOptions>
+CreateReshapeOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                     flatbuffers::Offset<flatbuffers::Vector<int32_t>> new_shape = 0)
+{
+  ReshapeOptionsBuilder builder_(_fbb);
+  builder_.add_new_shape(new_shape);
+  return builder_.Finish();
+}
+
+inline flatbuffers::Offset<ReshapeOptions>
+CreateReshapeOptionsDirect(flatbuffers::FlatBufferBuilder &_fbb,
+                           const std::vector<int32_t> *new_shape = nullptr)
+{
+  return neurun_tflite::CreateReshapeOptions(
+      _fbb, new_shape ? _fbb.CreateVector<int32_t>(*new_shape) : 0);
+}
+
+struct SpaceToBatchNDOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct SpaceToBatchNDOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit SpaceToBatchNDOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  SpaceToBatchNDOptionsBuilder &operator=(const SpaceToBatchNDOptionsBuilder &);
+  flatbuffers::Offset<SpaceToBatchNDOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<SpaceToBatchNDOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<SpaceToBatchNDOptions>
+CreateSpaceToBatchNDOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  SpaceToBatchNDOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct BatchToSpaceNDOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct BatchToSpaceNDOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit BatchToSpaceNDOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  BatchToSpaceNDOptionsBuilder &operator=(const BatchToSpaceNDOptionsBuilder &);
+  flatbuffers::Offset<BatchToSpaceNDOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<BatchToSpaceNDOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<BatchToSpaceNDOptions>
+CreateBatchToSpaceNDOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  BatchToSpaceNDOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct SkipGramOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_NGRAM_SIZE = 4,
+    VT_MAX_SKIP_SIZE = 6,
+    VT_INCLUDE_ALL_NGRAMS = 8
+  };
+  int32_t ngram_size() const { return GetField<int32_t>(VT_NGRAM_SIZE, 0); }
+  int32_t max_skip_size() const { return GetField<int32_t>(VT_MAX_SKIP_SIZE, 0); }
+  bool include_all_ngrams() const { return GetField<uint8_t>(VT_INCLUDE_ALL_NGRAMS, 0) != 0; }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int32_t>(verifier, VT_NGRAM_SIZE) &&
+           VerifyField<int32_t>(verifier, VT_MAX_SKIP_SIZE) &&
+           VerifyField<uint8_t>(verifier, VT_INCLUDE_ALL_NGRAMS) && verifier.EndTable();
+  }
+};
+
+struct SkipGramOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_ngram_size(int32_t ngram_size)
+  {
+    fbb_.AddElement<int32_t>(SkipGramOptions::VT_NGRAM_SIZE, ngram_size, 0);
+  }
+  void add_max_skip_size(int32_t max_skip_size)
+  {
+    fbb_.AddElement<int32_t>(SkipGramOptions::VT_MAX_SKIP_SIZE, max_skip_size, 0);
+  }
+  void add_include_all_ngrams(bool include_all_ngrams)
+  {
+    fbb_.AddElement<uint8_t>(SkipGramOptions::VT_INCLUDE_ALL_NGRAMS,
+                             static_cast<uint8_t>(include_all_ngrams), 0);
+  }
+  explicit SkipGramOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  SkipGramOptionsBuilder &operator=(const SkipGramOptionsBuilder &);
+  flatbuffers::Offset<SkipGramOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<SkipGramOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<SkipGramOptions>
+CreateSkipGramOptions(flatbuffers::FlatBufferBuilder &_fbb, int32_t ngram_size = 0,
+                      int32_t max_skip_size = 0, bool include_all_ngrams = false)
+{
+  SkipGramOptionsBuilder builder_(_fbb);
+  builder_.add_max_skip_size(max_skip_size);
+  builder_.add_ngram_size(ngram_size);
+  builder_.add_include_all_ngrams(include_all_ngrams);
+  return builder_.Finish();
+}
+
+struct SpaceToDepthOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_BLOCK_SIZE = 4
+  };
+  int32_t block_size() const { return GetField<int32_t>(VT_BLOCK_SIZE, 0); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int32_t>(verifier, VT_BLOCK_SIZE) &&
+           verifier.EndTable();
+  }
+};
+
+struct SpaceToDepthOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_block_size(int32_t block_size)
+  {
+    fbb_.AddElement<int32_t>(SpaceToDepthOptions::VT_BLOCK_SIZE, block_size, 0);
+  }
+  explicit SpaceToDepthOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  SpaceToDepthOptionsBuilder &operator=(const SpaceToDepthOptionsBuilder &);
+  flatbuffers::Offset<SpaceToDepthOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<SpaceToDepthOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<SpaceToDepthOptions>
+CreateSpaceToDepthOptions(flatbuffers::FlatBufferBuilder &_fbb, int32_t block_size = 0)
+{
+  SpaceToDepthOptionsBuilder builder_(_fbb);
+  builder_.add_block_size(block_size);
+  return builder_.Finish();
+}
+
+struct SubOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_FUSED_ACTIVATION_FUNCTION = 4
+  };
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) && verifier.EndTable();
+  }
+};
+
+struct SubOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(SubOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  explicit SubOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  SubOptionsBuilder &operator=(const SubOptionsBuilder &);
+  flatbuffers::Offset<SubOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<SubOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<SubOptions>
+CreateSubOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                 ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE)
+{
+  SubOptionsBuilder builder_(_fbb);
+  builder_.add_fused_activation_function(fused_activation_function);
+  return builder_.Finish();
+}
+
+struct DivOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_FUSED_ACTIVATION_FUNCTION = 4
+  };
+  ActivationFunctionType fused_activation_function() const
+  {
+    return static_cast<ActivationFunctionType>(GetField<int8_t>(VT_FUSED_ACTIVATION_FUNCTION, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) &&
+           VerifyField<int8_t>(verifier, VT_FUSED_ACTIVATION_FUNCTION) && verifier.EndTable();
+  }
+};
+
+struct DivOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_fused_activation_function(ActivationFunctionType fused_activation_function)
+  {
+    fbb_.AddElement<int8_t>(DivOptions::VT_FUSED_ACTIVATION_FUNCTION,
+                            static_cast<int8_t>(fused_activation_function), 0);
+  }
+  explicit DivOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  DivOptionsBuilder &operator=(const DivOptionsBuilder &);
+  flatbuffers::Offset<DivOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<DivOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<DivOptions>
+CreateDivOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                 ActivationFunctionType fused_activation_function = ActivationFunctionType_NONE)
+{
+  DivOptionsBuilder builder_(_fbb);
+  builder_.add_fused_activation_function(fused_activation_function);
+  return builder_.Finish();
+}
+
+struct TopKV2Options FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct TopKV2OptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit TopKV2OptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  TopKV2OptionsBuilder &operator=(const TopKV2OptionsBuilder &);
+  flatbuffers::Offset<TopKV2Options> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<TopKV2Options>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<TopKV2Options> CreateTopKV2Options(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  TopKV2OptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct EmbeddingLookupSparseOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_COMBINER = 4
+  };
+  CombinerType combiner() const
+  {
+    return static_cast<CombinerType>(GetField<int8_t>(VT_COMBINER, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int8_t>(verifier, VT_COMBINER) &&
+           verifier.EndTable();
+  }
+};
+
+struct EmbeddingLookupSparseOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_combiner(CombinerType combiner)
+  {
+    fbb_.AddElement<int8_t>(EmbeddingLookupSparseOptions::VT_COMBINER,
+                            static_cast<int8_t>(combiner), 0);
+  }
+  explicit EmbeddingLookupSparseOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  EmbeddingLookupSparseOptionsBuilder &operator=(const EmbeddingLookupSparseOptionsBuilder &);
+  flatbuffers::Offset<EmbeddingLookupSparseOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<EmbeddingLookupSparseOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<EmbeddingLookupSparseOptions>
+CreateEmbeddingLookupSparseOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                                   CombinerType combiner = CombinerType_SUM)
+{
+  EmbeddingLookupSparseOptionsBuilder builder_(_fbb);
+  builder_.add_combiner(combiner);
+  return builder_.Finish();
+}
+
+struct GatherOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_AXIS = 4
+  };
+  int32_t axis() const { return GetField<int32_t>(VT_AXIS, 0); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int32_t>(verifier, VT_AXIS) &&
+           verifier.EndTable();
+  }
+};
+
+struct GatherOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_axis(int32_t axis) { fbb_.AddElement<int32_t>(GatherOptions::VT_AXIS, axis, 0); }
+  explicit GatherOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  GatherOptionsBuilder &operator=(const GatherOptionsBuilder &);
+  flatbuffers::Offset<GatherOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<GatherOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<GatherOptions> CreateGatherOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                                                              int32_t axis = 0)
+{
+  GatherOptionsBuilder builder_(_fbb);
+  builder_.add_axis(axis);
+  return builder_.Finish();
+}
+
+struct TransposeOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct TransposeOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit TransposeOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  TransposeOptionsBuilder &operator=(const TransposeOptionsBuilder &);
+  flatbuffers::Offset<TransposeOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<TransposeOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<TransposeOptions>
+CreateTransposeOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  TransposeOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct ExpOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct ExpOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit ExpOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  ExpOptionsBuilder &operator=(const ExpOptionsBuilder &);
+  flatbuffers::Offset<ExpOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<ExpOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<ExpOptions> CreateExpOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  ExpOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct ReducerOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_KEEP_DIMS = 4
+  };
+  bool keep_dims() const { return GetField<uint8_t>(VT_KEEP_DIMS, 0) != 0; }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<uint8_t>(verifier, VT_KEEP_DIMS) &&
+           verifier.EndTable();
+  }
+};
+
+struct ReducerOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_keep_dims(bool keep_dims)
+  {
+    fbb_.AddElement<uint8_t>(ReducerOptions::VT_KEEP_DIMS, static_cast<uint8_t>(keep_dims), 0);
+  }
+  explicit ReducerOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  ReducerOptionsBuilder &operator=(const ReducerOptionsBuilder &);
+  flatbuffers::Offset<ReducerOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<ReducerOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<ReducerOptions>
+CreateReducerOptions(flatbuffers::FlatBufferBuilder &_fbb, bool keep_dims = false)
+{
+  ReducerOptionsBuilder builder_(_fbb);
+  builder_.add_keep_dims(keep_dims);
+  return builder_.Finish();
+}
+
+struct SqueezeOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_SQUEEZE_DIMS = 4
+  };
+  const flatbuffers::Vector<int32_t> *squeeze_dims() const
+  {
+    return GetPointer<const flatbuffers::Vector<int32_t> *>(VT_SQUEEZE_DIMS);
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyOffset(verifier, VT_SQUEEZE_DIMS) &&
+           verifier.VerifyVector(squeeze_dims()) && verifier.EndTable();
+  }
+};
+
+struct SqueezeOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_squeeze_dims(flatbuffers::Offset<flatbuffers::Vector<int32_t>> squeeze_dims)
+  {
+    fbb_.AddOffset(SqueezeOptions::VT_SQUEEZE_DIMS, squeeze_dims);
+  }
+  explicit SqueezeOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  SqueezeOptionsBuilder &operator=(const SqueezeOptionsBuilder &);
+  flatbuffers::Offset<SqueezeOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<SqueezeOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<SqueezeOptions>
+CreateSqueezeOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                     flatbuffers::Offset<flatbuffers::Vector<int32_t>> squeeze_dims = 0)
+{
+  SqueezeOptionsBuilder builder_(_fbb);
+  builder_.add_squeeze_dims(squeeze_dims);
+  return builder_.Finish();
+}
+
+inline flatbuffers::Offset<SqueezeOptions>
+CreateSqueezeOptionsDirect(flatbuffers::FlatBufferBuilder &_fbb,
+                           const std::vector<int32_t> *squeeze_dims = nullptr)
+{
+  return neurun_tflite::CreateSqueezeOptions(
+      _fbb, squeeze_dims ? _fbb.CreateVector<int32_t>(*squeeze_dims) : 0);
+}
+
+struct SplitOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_NUM_SPLITS = 4
+  };
+  int32_t num_splits() const { return GetField<int32_t>(VT_NUM_SPLITS, 0); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int32_t>(verifier, VT_NUM_SPLITS) &&
+           verifier.EndTable();
+  }
+};
+
+struct SplitOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_num_splits(int32_t num_splits)
+  {
+    fbb_.AddElement<int32_t>(SplitOptions::VT_NUM_SPLITS, num_splits, 0);
+  }
+  explicit SplitOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  SplitOptionsBuilder &operator=(const SplitOptionsBuilder &);
+  flatbuffers::Offset<SplitOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<SplitOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<SplitOptions> CreateSplitOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                                                            int32_t num_splits = 0)
+{
+  SplitOptionsBuilder builder_(_fbb);
+  builder_.add_num_splits(num_splits);
+  return builder_.Finish();
+}
+
+struct SplitVOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_NUM_SPLITS = 4
+  };
+  int32_t num_splits() const { return GetField<int32_t>(VT_NUM_SPLITS, 0); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int32_t>(verifier, VT_NUM_SPLITS) &&
+           verifier.EndTable();
+  }
+};
+
+struct SplitVOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_num_splits(int32_t num_splits)
+  {
+    fbb_.AddElement<int32_t>(SplitVOptions::VT_NUM_SPLITS, num_splits, 0);
+  }
+  explicit SplitVOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  SplitVOptionsBuilder &operator=(const SplitVOptionsBuilder &);
+  flatbuffers::Offset<SplitVOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<SplitVOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<SplitVOptions> CreateSplitVOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                                                              int32_t num_splits = 0)
+{
+  SplitVOptionsBuilder builder_(_fbb);
+  builder_.add_num_splits(num_splits);
+  return builder_.Finish();
+}
+
+struct StridedSliceOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_BEGIN_MASK = 4,
+    VT_END_MASK = 6,
+    VT_ELLIPSIS_MASK = 8,
+    VT_NEW_AXIS_MASK = 10,
+    VT_SHRINK_AXIS_MASK = 12
+  };
+  int32_t begin_mask() const { return GetField<int32_t>(VT_BEGIN_MASK, 0); }
+  int32_t end_mask() const { return GetField<int32_t>(VT_END_MASK, 0); }
+  int32_t ellipsis_mask() const { return GetField<int32_t>(VT_ELLIPSIS_MASK, 0); }
+  int32_t new_axis_mask() const { return GetField<int32_t>(VT_NEW_AXIS_MASK, 0); }
+  int32_t shrink_axis_mask() const { return GetField<int32_t>(VT_SHRINK_AXIS_MASK, 0); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int32_t>(verifier, VT_BEGIN_MASK) &&
+           VerifyField<int32_t>(verifier, VT_END_MASK) &&
+           VerifyField<int32_t>(verifier, VT_ELLIPSIS_MASK) &&
+           VerifyField<int32_t>(verifier, VT_NEW_AXIS_MASK) &&
+           VerifyField<int32_t>(verifier, VT_SHRINK_AXIS_MASK) && verifier.EndTable();
+  }
+};
+
+struct StridedSliceOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_begin_mask(int32_t begin_mask)
+  {
+    fbb_.AddElement<int32_t>(StridedSliceOptions::VT_BEGIN_MASK, begin_mask, 0);
+  }
+  void add_end_mask(int32_t end_mask)
+  {
+    fbb_.AddElement<int32_t>(StridedSliceOptions::VT_END_MASK, end_mask, 0);
+  }
+  void add_ellipsis_mask(int32_t ellipsis_mask)
+  {
+    fbb_.AddElement<int32_t>(StridedSliceOptions::VT_ELLIPSIS_MASK, ellipsis_mask, 0);
+  }
+  void add_new_axis_mask(int32_t new_axis_mask)
+  {
+    fbb_.AddElement<int32_t>(StridedSliceOptions::VT_NEW_AXIS_MASK, new_axis_mask, 0);
+  }
+  void add_shrink_axis_mask(int32_t shrink_axis_mask)
+  {
+    fbb_.AddElement<int32_t>(StridedSliceOptions::VT_SHRINK_AXIS_MASK, shrink_axis_mask, 0);
+  }
+  explicit StridedSliceOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  StridedSliceOptionsBuilder &operator=(const StridedSliceOptionsBuilder &);
+  flatbuffers::Offset<StridedSliceOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<StridedSliceOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<StridedSliceOptions>
+CreateStridedSliceOptions(flatbuffers::FlatBufferBuilder &_fbb, int32_t begin_mask = 0,
+                          int32_t end_mask = 0, int32_t ellipsis_mask = 0,
+                          int32_t new_axis_mask = 0, int32_t shrink_axis_mask = 0)
+{
+  StridedSliceOptionsBuilder builder_(_fbb);
+  builder_.add_shrink_axis_mask(shrink_axis_mask);
+  builder_.add_new_axis_mask(new_axis_mask);
+  builder_.add_ellipsis_mask(ellipsis_mask);
+  builder_.add_end_mask(end_mask);
+  builder_.add_begin_mask(begin_mask);
+  return builder_.Finish();
+}
+
+struct LogSoftmaxOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct LogSoftmaxOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit LogSoftmaxOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  LogSoftmaxOptionsBuilder &operator=(const LogSoftmaxOptionsBuilder &);
+  flatbuffers::Offset<LogSoftmaxOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<LogSoftmaxOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<LogSoftmaxOptions>
+CreateLogSoftmaxOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  LogSoftmaxOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct CastOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_IN_DATA_TYPE = 4,
+    VT_OUT_DATA_TYPE = 6
+  };
+  TensorType in_data_type() const
+  {
+    return static_cast<TensorType>(GetField<int8_t>(VT_IN_DATA_TYPE, 0));
+  }
+  TensorType out_data_type() const
+  {
+    return static_cast<TensorType>(GetField<int8_t>(VT_OUT_DATA_TYPE, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int8_t>(verifier, VT_IN_DATA_TYPE) &&
+           VerifyField<int8_t>(verifier, VT_OUT_DATA_TYPE) && verifier.EndTable();
+  }
+};
+
+struct CastOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_in_data_type(TensorType in_data_type)
+  {
+    fbb_.AddElement<int8_t>(CastOptions::VT_IN_DATA_TYPE, static_cast<int8_t>(in_data_type), 0);
+  }
+  void add_out_data_type(TensorType out_data_type)
+  {
+    fbb_.AddElement<int8_t>(CastOptions::VT_OUT_DATA_TYPE, static_cast<int8_t>(out_data_type), 0);
+  }
+  explicit CastOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  CastOptionsBuilder &operator=(const CastOptionsBuilder &);
+  flatbuffers::Offset<CastOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<CastOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<CastOptions>
+CreateCastOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                  TensorType in_data_type = TensorType_FLOAT32,
+                  TensorType out_data_type = TensorType_FLOAT32)
+{
+  CastOptionsBuilder builder_(_fbb);
+  builder_.add_out_data_type(out_data_type);
+  builder_.add_in_data_type(in_data_type);
+  return builder_.Finish();
+}
+
+struct DequantizeOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct DequantizeOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit DequantizeOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  DequantizeOptionsBuilder &operator=(const DequantizeOptionsBuilder &);
+  flatbuffers::Offset<DequantizeOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<DequantizeOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<DequantizeOptions>
+CreateDequantizeOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  DequantizeOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct MaximumMinimumOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct MaximumMinimumOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit MaximumMinimumOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  MaximumMinimumOptionsBuilder &operator=(const MaximumMinimumOptionsBuilder &);
+  flatbuffers::Offset<MaximumMinimumOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<MaximumMinimumOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<MaximumMinimumOptions>
+CreateMaximumMinimumOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  MaximumMinimumOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct TileOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct TileOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit TileOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  TileOptionsBuilder &operator=(const TileOptionsBuilder &);
+  flatbuffers::Offset<TileOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<TileOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<TileOptions> CreateTileOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  TileOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct ArgMaxOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_OUTPUT_TYPE = 4
+  };
+  TensorType output_type() const
+  {
+    return static_cast<TensorType>(GetField<int8_t>(VT_OUTPUT_TYPE, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int8_t>(verifier, VT_OUTPUT_TYPE) &&
+           verifier.EndTable();
+  }
+};
+
+struct ArgMaxOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_output_type(TensorType output_type)
+  {
+    fbb_.AddElement<int8_t>(ArgMaxOptions::VT_OUTPUT_TYPE, static_cast<int8_t>(output_type), 0);
+  }
+  explicit ArgMaxOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  ArgMaxOptionsBuilder &operator=(const ArgMaxOptionsBuilder &);
+  flatbuffers::Offset<ArgMaxOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<ArgMaxOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<ArgMaxOptions>
+CreateArgMaxOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                    TensorType output_type = TensorType_FLOAT32)
+{
+  ArgMaxOptionsBuilder builder_(_fbb);
+  builder_.add_output_type(output_type);
+  return builder_.Finish();
+}
+
+struct ArgMinOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_OUTPUT_TYPE = 4
+  };
+  TensorType output_type() const
+  {
+    return static_cast<TensorType>(GetField<int8_t>(VT_OUTPUT_TYPE, 0));
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int8_t>(verifier, VT_OUTPUT_TYPE) &&
+           verifier.EndTable();
+  }
+};
+
+struct ArgMinOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_output_type(TensorType output_type)
+  {
+    fbb_.AddElement<int8_t>(ArgMinOptions::VT_OUTPUT_TYPE, static_cast<int8_t>(output_type), 0);
+  }
+  explicit ArgMinOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  ArgMinOptionsBuilder &operator=(const ArgMinOptionsBuilder &);
+  flatbuffers::Offset<ArgMinOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<ArgMinOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<ArgMinOptions>
+CreateArgMinOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                    TensorType output_type = TensorType_FLOAT32)
+{
+  ArgMinOptionsBuilder builder_(_fbb);
+  builder_.add_output_type(output_type);
+  return builder_.Finish();
+}
+
+struct GreaterOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct GreaterOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit GreaterOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  GreaterOptionsBuilder &operator=(const GreaterOptionsBuilder &);
+  flatbuffers::Offset<GreaterOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<GreaterOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<GreaterOptions>
+CreateGreaterOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  GreaterOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct GreaterEqualOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct GreaterEqualOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit GreaterEqualOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  GreaterEqualOptionsBuilder &operator=(const GreaterEqualOptionsBuilder &);
+  flatbuffers::Offset<GreaterEqualOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<GreaterEqualOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<GreaterEqualOptions>
+CreateGreaterEqualOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  GreaterEqualOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct LessOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct LessOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit LessOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  LessOptionsBuilder &operator=(const LessOptionsBuilder &);
+  flatbuffers::Offset<LessOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<LessOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<LessOptions> CreateLessOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  LessOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct LessEqualOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct LessEqualOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit LessEqualOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  LessEqualOptionsBuilder &operator=(const LessEqualOptionsBuilder &);
+  flatbuffers::Offset<LessEqualOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<LessEqualOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<LessEqualOptions>
+CreateLessEqualOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  LessEqualOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct NegOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct NegOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit NegOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  NegOptionsBuilder &operator=(const NegOptionsBuilder &);
+  flatbuffers::Offset<NegOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<NegOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<NegOptions> CreateNegOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  NegOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct SelectOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct SelectOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit SelectOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  SelectOptionsBuilder &operator=(const SelectOptionsBuilder &);
+  flatbuffers::Offset<SelectOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<SelectOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<SelectOptions> CreateSelectOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  SelectOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct SliceOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct SliceOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit SliceOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  SliceOptionsBuilder &operator=(const SliceOptionsBuilder &);
+  flatbuffers::Offset<SliceOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<SliceOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<SliceOptions> CreateSliceOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  SliceOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct TransposeConvOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_PADDING = 4,
+    VT_STRIDE_W = 6,
+    VT_STRIDE_H = 8
+  };
+  Padding padding() const { return static_cast<Padding>(GetField<int8_t>(VT_PADDING, 0)); }
+  int32_t stride_w() const { return GetField<int32_t>(VT_STRIDE_W, 0); }
+  int32_t stride_h() const { return GetField<int32_t>(VT_STRIDE_H, 0); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int8_t>(verifier, VT_PADDING) &&
+           VerifyField<int32_t>(verifier, VT_STRIDE_W) &&
+           VerifyField<int32_t>(verifier, VT_STRIDE_H) && verifier.EndTable();
+  }
+};
+
+struct TransposeConvOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_padding(Padding padding)
+  {
+    fbb_.AddElement<int8_t>(TransposeConvOptions::VT_PADDING, static_cast<int8_t>(padding), 0);
+  }
+  void add_stride_w(int32_t stride_w)
+  {
+    fbb_.AddElement<int32_t>(TransposeConvOptions::VT_STRIDE_W, stride_w, 0);
+  }
+  void add_stride_h(int32_t stride_h)
+  {
+    fbb_.AddElement<int32_t>(TransposeConvOptions::VT_STRIDE_H, stride_h, 0);
+  }
+  explicit TransposeConvOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  TransposeConvOptionsBuilder &operator=(const TransposeConvOptionsBuilder &);
+  flatbuffers::Offset<TransposeConvOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<TransposeConvOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<TransposeConvOptions>
+CreateTransposeConvOptions(flatbuffers::FlatBufferBuilder &_fbb, Padding padding = Padding_SAME,
+                           int32_t stride_w = 0, int32_t stride_h = 0)
+{
+  TransposeConvOptionsBuilder builder_(_fbb);
+  builder_.add_stride_h(stride_h);
+  builder_.add_stride_w(stride_w);
+  builder_.add_padding(padding);
+  return builder_.Finish();
+}
+
+struct ExpandDimsOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct ExpandDimsOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit ExpandDimsOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  ExpandDimsOptionsBuilder &operator=(const ExpandDimsOptionsBuilder &);
+  flatbuffers::Offset<ExpandDimsOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<ExpandDimsOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<ExpandDimsOptions>
+CreateExpandDimsOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  ExpandDimsOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct SparseToDenseOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_VALIDATE_INDICES = 4
+  };
+  bool validate_indices() const { return GetField<uint8_t>(VT_VALIDATE_INDICES, 0) != 0; }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<uint8_t>(verifier, VT_VALIDATE_INDICES) &&
+           verifier.EndTable();
+  }
+};
+
+struct SparseToDenseOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_validate_indices(bool validate_indices)
+  {
+    fbb_.AddElement<uint8_t>(SparseToDenseOptions::VT_VALIDATE_INDICES,
+                             static_cast<uint8_t>(validate_indices), 0);
+  }
+  explicit SparseToDenseOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  SparseToDenseOptionsBuilder &operator=(const SparseToDenseOptionsBuilder &);
+  flatbuffers::Offset<SparseToDenseOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<SparseToDenseOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<SparseToDenseOptions>
+CreateSparseToDenseOptions(flatbuffers::FlatBufferBuilder &_fbb, bool validate_indices = false)
+{
+  SparseToDenseOptionsBuilder builder_(_fbb);
+  builder_.add_validate_indices(validate_indices);
+  return builder_.Finish();
+}
+
+struct EqualOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct EqualOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit EqualOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  EqualOptionsBuilder &operator=(const EqualOptionsBuilder &);
+  flatbuffers::Offset<EqualOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<EqualOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<EqualOptions> CreateEqualOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  EqualOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct NotEqualOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct NotEqualOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit NotEqualOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  NotEqualOptionsBuilder &operator=(const NotEqualOptionsBuilder &);
+  flatbuffers::Offset<NotEqualOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<NotEqualOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<NotEqualOptions>
+CreateNotEqualOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  NotEqualOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct ShapeOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_OUT_TYPE = 4
+  };
+  TensorType out_type() const { return static_cast<TensorType>(GetField<int8_t>(VT_OUT_TYPE, 0)); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int8_t>(verifier, VT_OUT_TYPE) &&
+           verifier.EndTable();
+  }
+};
+
+struct ShapeOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_out_type(TensorType out_type)
+  {
+    fbb_.AddElement<int8_t>(ShapeOptions::VT_OUT_TYPE, static_cast<int8_t>(out_type), 0);
+  }
+  explicit ShapeOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  ShapeOptionsBuilder &operator=(const ShapeOptionsBuilder &);
+  flatbuffers::Offset<ShapeOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<ShapeOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<ShapeOptions>
+CreateShapeOptions(flatbuffers::FlatBufferBuilder &_fbb, TensorType out_type = TensorType_FLOAT32)
+{
+  ShapeOptionsBuilder builder_(_fbb);
+  builder_.add_out_type(out_type);
+  return builder_.Finish();
+}
+
+struct PowOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct PowOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit PowOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  PowOptionsBuilder &operator=(const PowOptionsBuilder &);
+  flatbuffers::Offset<PowOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<PowOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<PowOptions> CreatePowOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  PowOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct FakeQuantOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_MIN = 4,
+    VT_MAX = 6,
+    VT_NUM_BITS = 8,
+    VT_NARROW_RANGE = 10
+  };
+  float min() const { return GetField<float>(VT_MIN, 0.0f); }
+  float max() const { return GetField<float>(VT_MAX, 0.0f); }
+  int32_t num_bits() const { return GetField<int32_t>(VT_NUM_BITS, 0); }
+  bool narrow_range() const { return GetField<uint8_t>(VT_NARROW_RANGE, 0) != 0; }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<float>(verifier, VT_MIN) &&
+           VerifyField<float>(verifier, VT_MAX) && VerifyField<int32_t>(verifier, VT_NUM_BITS) &&
+           VerifyField<uint8_t>(verifier, VT_NARROW_RANGE) && verifier.EndTable();
+  }
+};
+
+struct FakeQuantOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_min(float min) { fbb_.AddElement<float>(FakeQuantOptions::VT_MIN, min, 0.0f); }
+  void add_max(float max) { fbb_.AddElement<float>(FakeQuantOptions::VT_MAX, max, 0.0f); }
+  void add_num_bits(int32_t num_bits)
+  {
+    fbb_.AddElement<int32_t>(FakeQuantOptions::VT_NUM_BITS, num_bits, 0);
+  }
+  void add_narrow_range(bool narrow_range)
+  {
+    fbb_.AddElement<uint8_t>(FakeQuantOptions::VT_NARROW_RANGE, static_cast<uint8_t>(narrow_range),
+                             0);
+  }
+  explicit FakeQuantOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  FakeQuantOptionsBuilder &operator=(const FakeQuantOptionsBuilder &);
+  flatbuffers::Offset<FakeQuantOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<FakeQuantOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<FakeQuantOptions>
+CreateFakeQuantOptions(flatbuffers::FlatBufferBuilder &_fbb, float min = 0.0f, float max = 0.0f,
+                       int32_t num_bits = 0, bool narrow_range = false)
+{
+  FakeQuantOptionsBuilder builder_(_fbb);
+  builder_.add_num_bits(num_bits);
+  builder_.add_max(max);
+  builder_.add_min(min);
+  builder_.add_narrow_range(narrow_range);
+  return builder_.Finish();
+}
+
+struct PackOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_VALUES_COUNT = 4,
+    VT_AXIS = 6
+  };
+  int32_t values_count() const { return GetField<int32_t>(VT_VALUES_COUNT, 0); }
+  int32_t axis() const { return GetField<int32_t>(VT_AXIS, 0); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int32_t>(verifier, VT_VALUES_COUNT) &&
+           VerifyField<int32_t>(verifier, VT_AXIS) && verifier.EndTable();
+  }
+};
+
+struct PackOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_values_count(int32_t values_count)
+  {
+    fbb_.AddElement<int32_t>(PackOptions::VT_VALUES_COUNT, values_count, 0);
+  }
+  void add_axis(int32_t axis) { fbb_.AddElement<int32_t>(PackOptions::VT_AXIS, axis, 0); }
+  explicit PackOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  PackOptionsBuilder &operator=(const PackOptionsBuilder &);
+  flatbuffers::Offset<PackOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<PackOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<PackOptions>
+CreatePackOptions(flatbuffers::FlatBufferBuilder &_fbb, int32_t values_count = 0, int32_t axis = 0)
+{
+  PackOptionsBuilder builder_(_fbb);
+  builder_.add_axis(axis);
+  builder_.add_values_count(values_count);
+  return builder_.Finish();
+}
+
+struct LogicalOrOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct LogicalOrOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit LogicalOrOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  LogicalOrOptionsBuilder &operator=(const LogicalOrOptionsBuilder &);
+  flatbuffers::Offset<LogicalOrOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<LogicalOrOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<LogicalOrOptions>
+CreateLogicalOrOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  LogicalOrOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct OneHotOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_AXIS = 4
+  };
+  int32_t axis() const { return GetField<int32_t>(VT_AXIS, 0); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int32_t>(verifier, VT_AXIS) &&
+           verifier.EndTable();
+  }
+};
+
+struct OneHotOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_axis(int32_t axis) { fbb_.AddElement<int32_t>(OneHotOptions::VT_AXIS, axis, 0); }
+  explicit OneHotOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  OneHotOptionsBuilder &operator=(const OneHotOptionsBuilder &);
+  flatbuffers::Offset<OneHotOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<OneHotOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<OneHotOptions> CreateOneHotOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                                                              int32_t axis = 0)
+{
+  OneHotOptionsBuilder builder_(_fbb);
+  builder_.add_axis(axis);
+  return builder_.Finish();
+}
+
+struct AbsOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct AbsOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit AbsOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  AbsOptionsBuilder &operator=(const AbsOptionsBuilder &);
+  flatbuffers::Offset<AbsOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<AbsOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<AbsOptions> CreateAbsOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  AbsOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct LogicalAndOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct LogicalAndOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit LogicalAndOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  LogicalAndOptionsBuilder &operator=(const LogicalAndOptionsBuilder &);
+  flatbuffers::Offset<LogicalAndOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<LogicalAndOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<LogicalAndOptions>
+CreateLogicalAndOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  LogicalAndOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct LogicalNotOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct LogicalNotOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit LogicalNotOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  LogicalNotOptionsBuilder &operator=(const LogicalNotOptionsBuilder &);
+  flatbuffers::Offset<LogicalNotOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<LogicalNotOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<LogicalNotOptions>
+CreateLogicalNotOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  LogicalNotOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct UnpackOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_NUM = 4,
+    VT_AXIS = 6
+  };
+  int32_t num() const { return GetField<int32_t>(VT_NUM, 0); }
+  int32_t axis() const { return GetField<int32_t>(VT_AXIS, 0); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int32_t>(verifier, VT_NUM) &&
+           VerifyField<int32_t>(verifier, VT_AXIS) && verifier.EndTable();
+  }
+};
+
+struct UnpackOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_num(int32_t num) { fbb_.AddElement<int32_t>(UnpackOptions::VT_NUM, num, 0); }
+  void add_axis(int32_t axis) { fbb_.AddElement<int32_t>(UnpackOptions::VT_AXIS, axis, 0); }
+  explicit UnpackOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  UnpackOptionsBuilder &operator=(const UnpackOptionsBuilder &);
+  flatbuffers::Offset<UnpackOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<UnpackOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<UnpackOptions> CreateUnpackOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                                                              int32_t num = 0, int32_t axis = 0)
+{
+  UnpackOptionsBuilder builder_(_fbb);
+  builder_.add_axis(axis);
+  builder_.add_num(num);
+  return builder_.Finish();
+}
+
+struct FloorDivOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct FloorDivOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit FloorDivOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  FloorDivOptionsBuilder &operator=(const FloorDivOptionsBuilder &);
+  flatbuffers::Offset<FloorDivOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<FloorDivOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<FloorDivOptions>
+CreateFloorDivOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  FloorDivOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct SquareOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct SquareOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit SquareOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  SquareOptionsBuilder &operator=(const SquareOptionsBuilder &);
+  flatbuffers::Offset<SquareOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<SquareOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<SquareOptions> CreateSquareOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  SquareOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct ZerosLikeOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct ZerosLikeOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit ZerosLikeOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  ZerosLikeOptionsBuilder &operator=(const ZerosLikeOptionsBuilder &);
+  flatbuffers::Offset<ZerosLikeOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<ZerosLikeOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<ZerosLikeOptions>
+CreateZerosLikeOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  ZerosLikeOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct FillOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct FillOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit FillOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  FillOptionsBuilder &operator=(const FillOptionsBuilder &);
+  flatbuffers::Offset<FillOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<FillOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<FillOptions> CreateFillOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  FillOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct FloorModOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct FloorModOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit FloorModOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  FloorModOptionsBuilder &operator=(const FloorModOptionsBuilder &);
+  flatbuffers::Offset<FloorModOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<FloorModOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<FloorModOptions>
+CreateFloorModOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  FloorModOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct RangeOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct RangeOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit RangeOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  RangeOptionsBuilder &operator=(const RangeOptionsBuilder &);
+  flatbuffers::Offset<RangeOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<RangeOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<RangeOptions> CreateRangeOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  RangeOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct LeakyReluOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_ALPHA = 4
+  };
+  float alpha() const { return GetField<float>(VT_ALPHA, 0.0f); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<float>(verifier, VT_ALPHA) &&
+           verifier.EndTable();
+  }
+};
+
+struct LeakyReluOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_alpha(float alpha) { fbb_.AddElement<float>(LeakyReluOptions::VT_ALPHA, alpha, 0.0f); }
+  explicit LeakyReluOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  LeakyReluOptionsBuilder &operator=(const LeakyReluOptionsBuilder &);
+  flatbuffers::Offset<LeakyReluOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<LeakyReluOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<LeakyReluOptions>
+CreateLeakyReluOptions(flatbuffers::FlatBufferBuilder &_fbb, float alpha = 0.0f)
+{
+  LeakyReluOptionsBuilder builder_(_fbb);
+  builder_.add_alpha(alpha);
+  return builder_.Finish();
+}
+
+struct SquaredDifferenceOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && verifier.EndTable();
+  }
+};
+
+struct SquaredDifferenceOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  explicit SquaredDifferenceOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  SquaredDifferenceOptionsBuilder &operator=(const SquaredDifferenceOptionsBuilder &);
+  flatbuffers::Offset<SquaredDifferenceOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<SquaredDifferenceOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<SquaredDifferenceOptions>
+CreateSquaredDifferenceOptions(flatbuffers::FlatBufferBuilder &_fbb)
+{
+  SquaredDifferenceOptionsBuilder builder_(_fbb);
+  return builder_.Finish();
+}
+
+struct MirrorPadOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_MODE = 4
+  };
+  MirrorPadMode mode() const { return static_cast<MirrorPadMode>(GetField<int8_t>(VT_MODE, 0)); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int8_t>(verifier, VT_MODE) &&
+           verifier.EndTable();
+  }
+};
+
+struct MirrorPadOptionsBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_mode(MirrorPadMode mode)
+  {
+    fbb_.AddElement<int8_t>(MirrorPadOptions::VT_MODE, static_cast<int8_t>(mode), 0);
+  }
+  explicit MirrorPadOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  MirrorPadOptionsBuilder &operator=(const MirrorPadOptionsBuilder &);
+  flatbuffers::Offset<MirrorPadOptions> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<MirrorPadOptions>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<MirrorPadOptions>
+CreateMirrorPadOptions(flatbuffers::FlatBufferBuilder &_fbb,
+                       MirrorPadMode mode = MirrorPadMode_REFLECT)
+{
+  MirrorPadOptionsBuilder builder_(_fbb);
+  builder_.add_mode(mode);
+  return builder_.Finish();
+}
+
+struct OperatorCode FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_BUILTIN_CODE = 4,
+    VT_CUSTOM_CODE = 6,
+    VT_VERSION = 8
+  };
+  BuiltinOperator builtin_code() const
+  {
+    return static_cast<BuiltinOperator>(GetField<int8_t>(VT_BUILTIN_CODE, 0));
+  }
+  const flatbuffers::String *custom_code() const
+  {
+    return GetPointer<const flatbuffers::String *>(VT_CUSTOM_CODE);
+  }
+  int32_t version() const { return GetField<int32_t>(VT_VERSION, 1); }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<int8_t>(verifier, VT_BUILTIN_CODE) &&
+           VerifyOffset(verifier, VT_CUSTOM_CODE) && verifier.VerifyString(custom_code()) &&
+           VerifyField<int32_t>(verifier, VT_VERSION) && verifier.EndTable();
+  }
+};
+
+struct OperatorCodeBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_builtin_code(BuiltinOperator builtin_code)
+  {
+    fbb_.AddElement<int8_t>(OperatorCode::VT_BUILTIN_CODE, static_cast<int8_t>(builtin_code), 0);
+  }
+  void add_custom_code(flatbuffers::Offset<flatbuffers::String> custom_code)
+  {
+    fbb_.AddOffset(OperatorCode::VT_CUSTOM_CODE, custom_code);
+  }
+  void add_version(int32_t version)
+  {
+    fbb_.AddElement<int32_t>(OperatorCode::VT_VERSION, version, 1);
+  }
+  explicit OperatorCodeBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  OperatorCodeBuilder &operator=(const OperatorCodeBuilder &);
+  flatbuffers::Offset<OperatorCode> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<OperatorCode>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<OperatorCode>
+CreateOperatorCode(flatbuffers::FlatBufferBuilder &_fbb,
+                   BuiltinOperator builtin_code = BuiltinOperator_ADD,
+                   flatbuffers::Offset<flatbuffers::String> custom_code = 0, int32_t version = 1)
+{
+  OperatorCodeBuilder builder_(_fbb);
+  builder_.add_version(version);
+  builder_.add_custom_code(custom_code);
+  builder_.add_builtin_code(builtin_code);
+  return builder_.Finish();
+}
+
+inline flatbuffers::Offset<OperatorCode>
+CreateOperatorCodeDirect(flatbuffers::FlatBufferBuilder &_fbb,
+                         BuiltinOperator builtin_code = BuiltinOperator_ADD,
+                         const char *custom_code = nullptr, int32_t version = 1)
+{
+  return neurun_tflite::CreateOperatorCode(
+      _fbb, builtin_code, custom_code ? _fbb.CreateString(custom_code) : 0, version);
+}
+
+struct Operator FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_OPCODE_INDEX = 4,
+    VT_INPUTS = 6,
+    VT_OUTPUTS = 8,
+    VT_BUILTIN_OPTIONS_TYPE = 10,
+    VT_BUILTIN_OPTIONS = 12,
+    VT_CUSTOM_OPTIONS = 14,
+    VT_CUSTOM_OPTIONS_FORMAT = 16,
+    VT_MUTATING_VARIABLE_INPUTS = 18
+  };
+  uint32_t opcode_index() const { return GetField<uint32_t>(VT_OPCODE_INDEX, 0); }
+  const flatbuffers::Vector<int32_t> *inputs() const
+  {
+    return GetPointer<const flatbuffers::Vector<int32_t> *>(VT_INPUTS);
+  }
+  const flatbuffers::Vector<int32_t> *outputs() const
+  {
+    return GetPointer<const flatbuffers::Vector<int32_t> *>(VT_OUTPUTS);
+  }
+  BuiltinOptions builtin_options_type() const
+  {
+    return static_cast<BuiltinOptions>(GetField<uint8_t>(VT_BUILTIN_OPTIONS_TYPE, 0));
+  }
+  const void *builtin_options() const { return GetPointer<const void *>(VT_BUILTIN_OPTIONS); }
+  template <typename T> const T *builtin_options_as() const;
+  const Conv2DOptions *builtin_options_as_Conv2DOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_Conv2DOptions
+               ? static_cast<const Conv2DOptions *>(builtin_options())
+               : nullptr;
+  }
+  const DepthwiseConv2DOptions *builtin_options_as_DepthwiseConv2DOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_DepthwiseConv2DOptions
+               ? static_cast<const DepthwiseConv2DOptions *>(builtin_options())
+               : nullptr;
+  }
+  const ConcatEmbeddingsOptions *builtin_options_as_ConcatEmbeddingsOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_ConcatEmbeddingsOptions
+               ? static_cast<const ConcatEmbeddingsOptions *>(builtin_options())
+               : nullptr;
+  }
+  const LSHProjectionOptions *builtin_options_as_LSHProjectionOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_LSHProjectionOptions
+               ? static_cast<const LSHProjectionOptions *>(builtin_options())
+               : nullptr;
+  }
+  const Pool2DOptions *builtin_options_as_Pool2DOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_Pool2DOptions
+               ? static_cast<const Pool2DOptions *>(builtin_options())
+               : nullptr;
+  }
+  const SVDFOptions *builtin_options_as_SVDFOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_SVDFOptions
+               ? static_cast<const SVDFOptions *>(builtin_options())
+               : nullptr;
+  }
+  const RNNOptions *builtin_options_as_RNNOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_RNNOptions
+               ? static_cast<const RNNOptions *>(builtin_options())
+               : nullptr;
+  }
+  const FullyConnectedOptions *builtin_options_as_FullyConnectedOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_FullyConnectedOptions
+               ? static_cast<const FullyConnectedOptions *>(builtin_options())
+               : nullptr;
+  }
+  const SoftmaxOptions *builtin_options_as_SoftmaxOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_SoftmaxOptions
+               ? static_cast<const SoftmaxOptions *>(builtin_options())
+               : nullptr;
+  }
+  const ConcatenationOptions *builtin_options_as_ConcatenationOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_ConcatenationOptions
+               ? static_cast<const ConcatenationOptions *>(builtin_options())
+               : nullptr;
+  }
+  const AddOptions *builtin_options_as_AddOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_AddOptions
+               ? static_cast<const AddOptions *>(builtin_options())
+               : nullptr;
+  }
+  const L2NormOptions *builtin_options_as_L2NormOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_L2NormOptions
+               ? static_cast<const L2NormOptions *>(builtin_options())
+               : nullptr;
+  }
+  const LocalResponseNormalizationOptions *
+  builtin_options_as_LocalResponseNormalizationOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_LocalResponseNormalizationOptions
+               ? static_cast<const LocalResponseNormalizationOptions *>(builtin_options())
+               : nullptr;
+  }
+  const LSTMOptions *builtin_options_as_LSTMOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_LSTMOptions
+               ? static_cast<const LSTMOptions *>(builtin_options())
+               : nullptr;
+  }
+  const ResizeBilinearOptions *builtin_options_as_ResizeBilinearOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_ResizeBilinearOptions
+               ? static_cast<const ResizeBilinearOptions *>(builtin_options())
+               : nullptr;
+  }
+  const CallOptions *builtin_options_as_CallOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_CallOptions
+               ? static_cast<const CallOptions *>(builtin_options())
+               : nullptr;
+  }
+  const ReshapeOptions *builtin_options_as_ReshapeOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_ReshapeOptions
+               ? static_cast<const ReshapeOptions *>(builtin_options())
+               : nullptr;
+  }
+  const SkipGramOptions *builtin_options_as_SkipGramOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_SkipGramOptions
+               ? static_cast<const SkipGramOptions *>(builtin_options())
+               : nullptr;
+  }
+  const SpaceToDepthOptions *builtin_options_as_SpaceToDepthOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_SpaceToDepthOptions
+               ? static_cast<const SpaceToDepthOptions *>(builtin_options())
+               : nullptr;
+  }
+  const EmbeddingLookupSparseOptions *builtin_options_as_EmbeddingLookupSparseOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_EmbeddingLookupSparseOptions
+               ? static_cast<const EmbeddingLookupSparseOptions *>(builtin_options())
+               : nullptr;
+  }
+  const MulOptions *builtin_options_as_MulOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_MulOptions
+               ? static_cast<const MulOptions *>(builtin_options())
+               : nullptr;
+  }
+  const PadOptions *builtin_options_as_PadOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_PadOptions
+               ? static_cast<const PadOptions *>(builtin_options())
+               : nullptr;
+  }
+  const GatherOptions *builtin_options_as_GatherOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_GatherOptions
+               ? static_cast<const GatherOptions *>(builtin_options())
+               : nullptr;
+  }
+  const BatchToSpaceNDOptions *builtin_options_as_BatchToSpaceNDOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_BatchToSpaceNDOptions
+               ? static_cast<const BatchToSpaceNDOptions *>(builtin_options())
+               : nullptr;
+  }
+  const SpaceToBatchNDOptions *builtin_options_as_SpaceToBatchNDOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_SpaceToBatchNDOptions
+               ? static_cast<const SpaceToBatchNDOptions *>(builtin_options())
+               : nullptr;
+  }
+  const TransposeOptions *builtin_options_as_TransposeOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_TransposeOptions
+               ? static_cast<const TransposeOptions *>(builtin_options())
+               : nullptr;
+  }
+  const ReducerOptions *builtin_options_as_ReducerOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_ReducerOptions
+               ? static_cast<const ReducerOptions *>(builtin_options())
+               : nullptr;
+  }
+  const SubOptions *builtin_options_as_SubOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_SubOptions
+               ? static_cast<const SubOptions *>(builtin_options())
+               : nullptr;
+  }
+  const DivOptions *builtin_options_as_DivOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_DivOptions
+               ? static_cast<const DivOptions *>(builtin_options())
+               : nullptr;
+  }
+  const SqueezeOptions *builtin_options_as_SqueezeOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_SqueezeOptions
+               ? static_cast<const SqueezeOptions *>(builtin_options())
+               : nullptr;
+  }
+  const SequenceRNNOptions *builtin_options_as_SequenceRNNOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_SequenceRNNOptions
+               ? static_cast<const SequenceRNNOptions *>(builtin_options())
+               : nullptr;
+  }
+  const StridedSliceOptions *builtin_options_as_StridedSliceOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_StridedSliceOptions
+               ? static_cast<const StridedSliceOptions *>(builtin_options())
+               : nullptr;
+  }
+  const ExpOptions *builtin_options_as_ExpOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_ExpOptions
+               ? static_cast<const ExpOptions *>(builtin_options())
+               : nullptr;
+  }
+  const TopKV2Options *builtin_options_as_TopKV2Options() const
+  {
+    return builtin_options_type() == BuiltinOptions_TopKV2Options
+               ? static_cast<const TopKV2Options *>(builtin_options())
+               : nullptr;
+  }
+  const SplitOptions *builtin_options_as_SplitOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_SplitOptions
+               ? static_cast<const SplitOptions *>(builtin_options())
+               : nullptr;
+  }
+  const LogSoftmaxOptions *builtin_options_as_LogSoftmaxOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_LogSoftmaxOptions
+               ? static_cast<const LogSoftmaxOptions *>(builtin_options())
+               : nullptr;
+  }
+  const CastOptions *builtin_options_as_CastOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_CastOptions
+               ? static_cast<const CastOptions *>(builtin_options())
+               : nullptr;
+  }
+  const DequantizeOptions *builtin_options_as_DequantizeOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_DequantizeOptions
+               ? static_cast<const DequantizeOptions *>(builtin_options())
+               : nullptr;
+  }
+  const MaximumMinimumOptions *builtin_options_as_MaximumMinimumOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_MaximumMinimumOptions
+               ? static_cast<const MaximumMinimumOptions *>(builtin_options())
+               : nullptr;
+  }
+  const ArgMaxOptions *builtin_options_as_ArgMaxOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_ArgMaxOptions
+               ? static_cast<const ArgMaxOptions *>(builtin_options())
+               : nullptr;
+  }
+  const LessOptions *builtin_options_as_LessOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_LessOptions
+               ? static_cast<const LessOptions *>(builtin_options())
+               : nullptr;
+  }
+  const NegOptions *builtin_options_as_NegOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_NegOptions
+               ? static_cast<const NegOptions *>(builtin_options())
+               : nullptr;
+  }
+  const PadV2Options *builtin_options_as_PadV2Options() const
+  {
+    return builtin_options_type() == BuiltinOptions_PadV2Options
+               ? static_cast<const PadV2Options *>(builtin_options())
+               : nullptr;
+  }
+  const GreaterOptions *builtin_options_as_GreaterOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_GreaterOptions
+               ? static_cast<const GreaterOptions *>(builtin_options())
+               : nullptr;
+  }
+  const GreaterEqualOptions *builtin_options_as_GreaterEqualOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_GreaterEqualOptions
+               ? static_cast<const GreaterEqualOptions *>(builtin_options())
+               : nullptr;
+  }
+  const LessEqualOptions *builtin_options_as_LessEqualOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_LessEqualOptions
+               ? static_cast<const LessEqualOptions *>(builtin_options())
+               : nullptr;
+  }
+  const SelectOptions *builtin_options_as_SelectOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_SelectOptions
+               ? static_cast<const SelectOptions *>(builtin_options())
+               : nullptr;
+  }
+  const SliceOptions *builtin_options_as_SliceOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_SliceOptions
+               ? static_cast<const SliceOptions *>(builtin_options())
+               : nullptr;
+  }
+  const TransposeConvOptions *builtin_options_as_TransposeConvOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_TransposeConvOptions
+               ? static_cast<const TransposeConvOptions *>(builtin_options())
+               : nullptr;
+  }
+  const SparseToDenseOptions *builtin_options_as_SparseToDenseOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_SparseToDenseOptions
+               ? static_cast<const SparseToDenseOptions *>(builtin_options())
+               : nullptr;
+  }
+  const TileOptions *builtin_options_as_TileOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_TileOptions
+               ? static_cast<const TileOptions *>(builtin_options())
+               : nullptr;
+  }
+  const ExpandDimsOptions *builtin_options_as_ExpandDimsOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_ExpandDimsOptions
+               ? static_cast<const ExpandDimsOptions *>(builtin_options())
+               : nullptr;
+  }
+  const EqualOptions *builtin_options_as_EqualOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_EqualOptions
+               ? static_cast<const EqualOptions *>(builtin_options())
+               : nullptr;
+  }
+  const NotEqualOptions *builtin_options_as_NotEqualOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_NotEqualOptions
+               ? static_cast<const NotEqualOptions *>(builtin_options())
+               : nullptr;
+  }
+  const ShapeOptions *builtin_options_as_ShapeOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_ShapeOptions
+               ? static_cast<const ShapeOptions *>(builtin_options())
+               : nullptr;
+  }
+  const PowOptions *builtin_options_as_PowOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_PowOptions
+               ? static_cast<const PowOptions *>(builtin_options())
+               : nullptr;
+  }
+  const ArgMinOptions *builtin_options_as_ArgMinOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_ArgMinOptions
+               ? static_cast<const ArgMinOptions *>(builtin_options())
+               : nullptr;
+  }
+  const FakeQuantOptions *builtin_options_as_FakeQuantOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_FakeQuantOptions
+               ? static_cast<const FakeQuantOptions *>(builtin_options())
+               : nullptr;
+  }
+  const PackOptions *builtin_options_as_PackOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_PackOptions
+               ? static_cast<const PackOptions *>(builtin_options())
+               : nullptr;
+  }
+  const LogicalOrOptions *builtin_options_as_LogicalOrOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_LogicalOrOptions
+               ? static_cast<const LogicalOrOptions *>(builtin_options())
+               : nullptr;
+  }
+  const OneHotOptions *builtin_options_as_OneHotOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_OneHotOptions
+               ? static_cast<const OneHotOptions *>(builtin_options())
+               : nullptr;
+  }
+  const LogicalAndOptions *builtin_options_as_LogicalAndOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_LogicalAndOptions
+               ? static_cast<const LogicalAndOptions *>(builtin_options())
+               : nullptr;
+  }
+  const LogicalNotOptions *builtin_options_as_LogicalNotOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_LogicalNotOptions
+               ? static_cast<const LogicalNotOptions *>(builtin_options())
+               : nullptr;
+  }
+  const UnpackOptions *builtin_options_as_UnpackOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_UnpackOptions
+               ? static_cast<const UnpackOptions *>(builtin_options())
+               : nullptr;
+  }
+  const FloorDivOptions *builtin_options_as_FloorDivOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_FloorDivOptions
+               ? static_cast<const FloorDivOptions *>(builtin_options())
+               : nullptr;
+  }
+  const SquareOptions *builtin_options_as_SquareOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_SquareOptions
+               ? static_cast<const SquareOptions *>(builtin_options())
+               : nullptr;
+  }
+  const ZerosLikeOptions *builtin_options_as_ZerosLikeOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_ZerosLikeOptions
+               ? static_cast<const ZerosLikeOptions *>(builtin_options())
+               : nullptr;
+  }
+  const FillOptions *builtin_options_as_FillOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_FillOptions
+               ? static_cast<const FillOptions *>(builtin_options())
+               : nullptr;
+  }
+  const BidirectionalSequenceLSTMOptions *
+  builtin_options_as_BidirectionalSequenceLSTMOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_BidirectionalSequenceLSTMOptions
+               ? static_cast<const BidirectionalSequenceLSTMOptions *>(builtin_options())
+               : nullptr;
+  }
+  const BidirectionalSequenceRNNOptions *builtin_options_as_BidirectionalSequenceRNNOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_BidirectionalSequenceRNNOptions
+               ? static_cast<const BidirectionalSequenceRNNOptions *>(builtin_options())
+               : nullptr;
+  }
+  const UnidirectionalSequenceLSTMOptions *
+  builtin_options_as_UnidirectionalSequenceLSTMOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_UnidirectionalSequenceLSTMOptions
+               ? static_cast<const UnidirectionalSequenceLSTMOptions *>(builtin_options())
+               : nullptr;
+  }
+  const FloorModOptions *builtin_options_as_FloorModOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_FloorModOptions
+               ? static_cast<const FloorModOptions *>(builtin_options())
+               : nullptr;
+  }
+  const RangeOptions *builtin_options_as_RangeOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_RangeOptions
+               ? static_cast<const RangeOptions *>(builtin_options())
+               : nullptr;
+  }
+  const ResizeNearestNeighborOptions *builtin_options_as_ResizeNearestNeighborOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_ResizeNearestNeighborOptions
+               ? static_cast<const ResizeNearestNeighborOptions *>(builtin_options())
+               : nullptr;
+  }
+  const LeakyReluOptions *builtin_options_as_LeakyReluOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_LeakyReluOptions
+               ? static_cast<const LeakyReluOptions *>(builtin_options())
+               : nullptr;
+  }
+  const SquaredDifferenceOptions *builtin_options_as_SquaredDifferenceOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_SquaredDifferenceOptions
+               ? static_cast<const SquaredDifferenceOptions *>(builtin_options())
+               : nullptr;
+  }
+  const MirrorPadOptions *builtin_options_as_MirrorPadOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_MirrorPadOptions
+               ? static_cast<const MirrorPadOptions *>(builtin_options())
+               : nullptr;
+  }
+  const AbsOptions *builtin_options_as_AbsOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_AbsOptions
+               ? static_cast<const AbsOptions *>(builtin_options())
+               : nullptr;
+  }
+  const SplitVOptions *builtin_options_as_SplitVOptions() const
+  {
+    return builtin_options_type() == BuiltinOptions_SplitVOptions
+               ? static_cast<const SplitVOptions *>(builtin_options())
+               : nullptr;
+  }
+  const flatbuffers::Vector<uint8_t> *custom_options() const
+  {
+    return GetPointer<const flatbuffers::Vector<uint8_t> *>(VT_CUSTOM_OPTIONS);
+  }
+  CustomOptionsFormat custom_options_format() const
+  {
+    return static_cast<CustomOptionsFormat>(GetField<int8_t>(VT_CUSTOM_OPTIONS_FORMAT, 0));
+  }
+  const flatbuffers::Vector<uint8_t> *mutating_variable_inputs() const
+  {
+    return GetPointer<const flatbuffers::Vector<uint8_t> *>(VT_MUTATING_VARIABLE_INPUTS);
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<uint32_t>(verifier, VT_OPCODE_INDEX) &&
+           VerifyOffset(verifier, VT_INPUTS) && verifier.VerifyVector(inputs()) &&
+           VerifyOffset(verifier, VT_OUTPUTS) && verifier.VerifyVector(outputs()) &&
+           VerifyField<uint8_t>(verifier, VT_BUILTIN_OPTIONS_TYPE) &&
+           VerifyOffset(verifier, VT_BUILTIN_OPTIONS) &&
+           VerifyBuiltinOptions(verifier, builtin_options(), builtin_options_type()) &&
+           VerifyOffset(verifier, VT_CUSTOM_OPTIONS) && verifier.VerifyVector(custom_options()) &&
+           VerifyField<int8_t>(verifier, VT_CUSTOM_OPTIONS_FORMAT) &&
+           VerifyOffset(verifier, VT_MUTATING_VARIABLE_INPUTS) &&
+           verifier.VerifyVector(mutating_variable_inputs()) && verifier.EndTable();
+  }
+};
+
+template <> inline const Conv2DOptions *Operator::builtin_options_as<Conv2DOptions>() const
+{
+  return builtin_options_as_Conv2DOptions();
+}
+
+template <>
+inline const DepthwiseConv2DOptions *Operator::builtin_options_as<DepthwiseConv2DOptions>() const
+{
+  return builtin_options_as_DepthwiseConv2DOptions();
+}
+
+template <>
+inline const ConcatEmbeddingsOptions *Operator::builtin_options_as<ConcatEmbeddingsOptions>() const
+{
+  return builtin_options_as_ConcatEmbeddingsOptions();
+}
+
+template <>
+inline const LSHProjectionOptions *Operator::builtin_options_as<LSHProjectionOptions>() const
+{
+  return builtin_options_as_LSHProjectionOptions();
+}
+
+template <> inline const Pool2DOptions *Operator::builtin_options_as<Pool2DOptions>() const
+{
+  return builtin_options_as_Pool2DOptions();
+}
+
+template <> inline const SVDFOptions *Operator::builtin_options_as<SVDFOptions>() const
+{
+  return builtin_options_as_SVDFOptions();
+}
+
+template <> inline const RNNOptions *Operator::builtin_options_as<RNNOptions>() const
+{
+  return builtin_options_as_RNNOptions();
+}
+
+template <>
+inline const FullyConnectedOptions *Operator::builtin_options_as<FullyConnectedOptions>() const
+{
+  return builtin_options_as_FullyConnectedOptions();
+}
+
+template <> inline const SoftmaxOptions *Operator::builtin_options_as<SoftmaxOptions>() const
+{
+  return builtin_options_as_SoftmaxOptions();
+}
+
+template <>
+inline const ConcatenationOptions *Operator::builtin_options_as<ConcatenationOptions>() const
+{
+  return builtin_options_as_ConcatenationOptions();
+}
+
+template <> inline const AddOptions *Operator::builtin_options_as<AddOptions>() const
+{
+  return builtin_options_as_AddOptions();
+}
+
+template <> inline const L2NormOptions *Operator::builtin_options_as<L2NormOptions>() const
+{
+  return builtin_options_as_L2NormOptions();
+}
+
+template <>
+inline const LocalResponseNormalizationOptions *
+Operator::builtin_options_as<LocalResponseNormalizationOptions>() const
+{
+  return builtin_options_as_LocalResponseNormalizationOptions();
+}
+
+template <> inline const LSTMOptions *Operator::builtin_options_as<LSTMOptions>() const
+{
+  return builtin_options_as_LSTMOptions();
+}
+
+template <>
+inline const ResizeBilinearOptions *Operator::builtin_options_as<ResizeBilinearOptions>() const
+{
+  return builtin_options_as_ResizeBilinearOptions();
+}
+
+template <> inline const CallOptions *Operator::builtin_options_as<CallOptions>() const
+{
+  return builtin_options_as_CallOptions();
+}
+
+template <> inline const ReshapeOptions *Operator::builtin_options_as<ReshapeOptions>() const
+{
+  return builtin_options_as_ReshapeOptions();
+}
+
+template <> inline const SkipGramOptions *Operator::builtin_options_as<SkipGramOptions>() const
+{
+  return builtin_options_as_SkipGramOptions();
+}
+
+template <>
+inline const SpaceToDepthOptions *Operator::builtin_options_as<SpaceToDepthOptions>() const
+{
+  return builtin_options_as_SpaceToDepthOptions();
+}
+
+template <>
+inline const EmbeddingLookupSparseOptions *
+Operator::builtin_options_as<EmbeddingLookupSparseOptions>() const
+{
+  return builtin_options_as_EmbeddingLookupSparseOptions();
+}
+
+template <> inline const MulOptions *Operator::builtin_options_as<MulOptions>() const
+{
+  return builtin_options_as_MulOptions();
+}
+
+template <> inline const PadOptions *Operator::builtin_options_as<PadOptions>() const
+{
+  return builtin_options_as_PadOptions();
+}
+
+template <> inline const GatherOptions *Operator::builtin_options_as<GatherOptions>() const
+{
+  return builtin_options_as_GatherOptions();
+}
+
+template <>
+inline const BatchToSpaceNDOptions *Operator::builtin_options_as<BatchToSpaceNDOptions>() const
+{
+  return builtin_options_as_BatchToSpaceNDOptions();
+}
+
+template <>
+inline const SpaceToBatchNDOptions *Operator::builtin_options_as<SpaceToBatchNDOptions>() const
+{
+  return builtin_options_as_SpaceToBatchNDOptions();
+}
+
+template <> inline const TransposeOptions *Operator::builtin_options_as<TransposeOptions>() const
+{
+  return builtin_options_as_TransposeOptions();
+}
+
+template <> inline const ReducerOptions *Operator::builtin_options_as<ReducerOptions>() const
+{
+  return builtin_options_as_ReducerOptions();
+}
+
+template <> inline const SubOptions *Operator::builtin_options_as<SubOptions>() const
+{
+  return builtin_options_as_SubOptions();
+}
+
+template <> inline const DivOptions *Operator::builtin_options_as<DivOptions>() const
+{
+  return builtin_options_as_DivOptions();
+}
+
+template <> inline const SqueezeOptions *Operator::builtin_options_as<SqueezeOptions>() const
+{
+  return builtin_options_as_SqueezeOptions();
+}
+
+template <>
+inline const SequenceRNNOptions *Operator::builtin_options_as<SequenceRNNOptions>() const
+{
+  return builtin_options_as_SequenceRNNOptions();
+}
+
+template <>
+inline const StridedSliceOptions *Operator::builtin_options_as<StridedSliceOptions>() const
+{
+  return builtin_options_as_StridedSliceOptions();
+}
+
+template <> inline const ExpOptions *Operator::builtin_options_as<ExpOptions>() const
+{
+  return builtin_options_as_ExpOptions();
+}
+
+template <> inline const TopKV2Options *Operator::builtin_options_as<TopKV2Options>() const
+{
+  return builtin_options_as_TopKV2Options();
+}
+
+template <> inline const SplitOptions *Operator::builtin_options_as<SplitOptions>() const
+{
+  return builtin_options_as_SplitOptions();
+}
+
+template <> inline const LogSoftmaxOptions *Operator::builtin_options_as<LogSoftmaxOptions>() const
+{
+  return builtin_options_as_LogSoftmaxOptions();
+}
+
+template <> inline const CastOptions *Operator::builtin_options_as<CastOptions>() const
+{
+  return builtin_options_as_CastOptions();
+}
+
+template <> inline const DequantizeOptions *Operator::builtin_options_as<DequantizeOptions>() const
+{
+  return builtin_options_as_DequantizeOptions();
+}
+
+template <>
+inline const MaximumMinimumOptions *Operator::builtin_options_as<MaximumMinimumOptions>() const
+{
+  return builtin_options_as_MaximumMinimumOptions();
+}
+
+template <> inline const ArgMaxOptions *Operator::builtin_options_as<ArgMaxOptions>() const
+{
+  return builtin_options_as_ArgMaxOptions();
+}
+
+template <> inline const LessOptions *Operator::builtin_options_as<LessOptions>() const
+{
+  return builtin_options_as_LessOptions();
+}
+
+template <> inline const NegOptions *Operator::builtin_options_as<NegOptions>() const
+{
+  return builtin_options_as_NegOptions();
+}
+
+template <> inline const PadV2Options *Operator::builtin_options_as<PadV2Options>() const
+{
+  return builtin_options_as_PadV2Options();
+}
+
+template <> inline const GreaterOptions *Operator::builtin_options_as<GreaterOptions>() const
+{
+  return builtin_options_as_GreaterOptions();
+}
+
+template <>
+inline const GreaterEqualOptions *Operator::builtin_options_as<GreaterEqualOptions>() const
+{
+  return builtin_options_as_GreaterEqualOptions();
+}
+
+template <> inline const LessEqualOptions *Operator::builtin_options_as<LessEqualOptions>() const
+{
+  return builtin_options_as_LessEqualOptions();
+}
+
+template <> inline const SelectOptions *Operator::builtin_options_as<SelectOptions>() const
+{
+  return builtin_options_as_SelectOptions();
+}
+
+template <> inline const SliceOptions *Operator::builtin_options_as<SliceOptions>() const
+{
+  return builtin_options_as_SliceOptions();
+}
+
+template <>
+inline const TransposeConvOptions *Operator::builtin_options_as<TransposeConvOptions>() const
+{
+  return builtin_options_as_TransposeConvOptions();
+}
+
+template <>
+inline const SparseToDenseOptions *Operator::builtin_options_as<SparseToDenseOptions>() const
+{
+  return builtin_options_as_SparseToDenseOptions();
+}
+
+template <> inline const TileOptions *Operator::builtin_options_as<TileOptions>() const
+{
+  return builtin_options_as_TileOptions();
+}
+
+template <> inline const ExpandDimsOptions *Operator::builtin_options_as<ExpandDimsOptions>() const
+{
+  return builtin_options_as_ExpandDimsOptions();
+}
+
+template <> inline const EqualOptions *Operator::builtin_options_as<EqualOptions>() const
+{
+  return builtin_options_as_EqualOptions();
+}
+
+template <> inline const NotEqualOptions *Operator::builtin_options_as<NotEqualOptions>() const
+{
+  return builtin_options_as_NotEqualOptions();
+}
+
+template <> inline const ShapeOptions *Operator::builtin_options_as<ShapeOptions>() const
+{
+  return builtin_options_as_ShapeOptions();
+}
+
+template <> inline const PowOptions *Operator::builtin_options_as<PowOptions>() const
+{
+  return builtin_options_as_PowOptions();
+}
+
+template <> inline const ArgMinOptions *Operator::builtin_options_as<ArgMinOptions>() const
+{
+  return builtin_options_as_ArgMinOptions();
+}
+
+template <> inline const FakeQuantOptions *Operator::builtin_options_as<FakeQuantOptions>() const
+{
+  return builtin_options_as_FakeQuantOptions();
+}
+
+template <> inline const PackOptions *Operator::builtin_options_as<PackOptions>() const
+{
+  return builtin_options_as_PackOptions();
+}
+
+template <> inline const LogicalOrOptions *Operator::builtin_options_as<LogicalOrOptions>() const
+{
+  return builtin_options_as_LogicalOrOptions();
+}
+
+template <> inline const OneHotOptions *Operator::builtin_options_as<OneHotOptions>() const
+{
+  return builtin_options_as_OneHotOptions();
+}
+
+template <> inline const LogicalAndOptions *Operator::builtin_options_as<LogicalAndOptions>() const
+{
+  return builtin_options_as_LogicalAndOptions();
+}
+
+template <> inline const LogicalNotOptions *Operator::builtin_options_as<LogicalNotOptions>() const
+{
+  return builtin_options_as_LogicalNotOptions();
+}
+
+template <> inline const UnpackOptions *Operator::builtin_options_as<UnpackOptions>() const
+{
+  return builtin_options_as_UnpackOptions();
+}
+
+template <> inline const FloorDivOptions *Operator::builtin_options_as<FloorDivOptions>() const
+{
+  return builtin_options_as_FloorDivOptions();
+}
+
+template <> inline const SquareOptions *Operator::builtin_options_as<SquareOptions>() const
+{
+  return builtin_options_as_SquareOptions();
+}
+
+template <> inline const ZerosLikeOptions *Operator::builtin_options_as<ZerosLikeOptions>() const
+{
+  return builtin_options_as_ZerosLikeOptions();
+}
+
+template <> inline const FillOptions *Operator::builtin_options_as<FillOptions>() const
+{
+  return builtin_options_as_FillOptions();
+}
+
+template <>
+inline const BidirectionalSequenceLSTMOptions *
+Operator::builtin_options_as<BidirectionalSequenceLSTMOptions>() const
+{
+  return builtin_options_as_BidirectionalSequenceLSTMOptions();
+}
+
+template <>
+inline const BidirectionalSequenceRNNOptions *
+Operator::builtin_options_as<BidirectionalSequenceRNNOptions>() const
+{
+  return builtin_options_as_BidirectionalSequenceRNNOptions();
+}
+
+template <>
+inline const UnidirectionalSequenceLSTMOptions *
+Operator::builtin_options_as<UnidirectionalSequenceLSTMOptions>() const
+{
+  return builtin_options_as_UnidirectionalSequenceLSTMOptions();
+}
+
+template <> inline const FloorModOptions *Operator::builtin_options_as<FloorModOptions>() const
+{
+  return builtin_options_as_FloorModOptions();
+}
+
+template <> inline const RangeOptions *Operator::builtin_options_as<RangeOptions>() const
+{
+  return builtin_options_as_RangeOptions();
+}
+
+template <>
+inline const ResizeNearestNeighborOptions *
+Operator::builtin_options_as<ResizeNearestNeighborOptions>() const
+{
+  return builtin_options_as_ResizeNearestNeighborOptions();
+}
+
+template <> inline const LeakyReluOptions *Operator::builtin_options_as<LeakyReluOptions>() const
+{
+  return builtin_options_as_LeakyReluOptions();
+}
+
+template <>
+inline const SquaredDifferenceOptions *
+Operator::builtin_options_as<SquaredDifferenceOptions>() const
+{
+  return builtin_options_as_SquaredDifferenceOptions();
+}
+
+template <> inline const MirrorPadOptions *Operator::builtin_options_as<MirrorPadOptions>() const
+{
+  return builtin_options_as_MirrorPadOptions();
+}
+
+template <> inline const AbsOptions *Operator::builtin_options_as<AbsOptions>() const
+{
+  return builtin_options_as_AbsOptions();
+}
+
+template <> inline const SplitVOptions *Operator::builtin_options_as<SplitVOptions>() const
+{
+  return builtin_options_as_SplitVOptions();
+}
+
+struct OperatorBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_opcode_index(uint32_t opcode_index)
+  {
+    fbb_.AddElement<uint32_t>(Operator::VT_OPCODE_INDEX, opcode_index, 0);
+  }
+  void add_inputs(flatbuffers::Offset<flatbuffers::Vector<int32_t>> inputs)
+  {
+    fbb_.AddOffset(Operator::VT_INPUTS, inputs);
+  }
+  void add_outputs(flatbuffers::Offset<flatbuffers::Vector<int32_t>> outputs)
+  {
+    fbb_.AddOffset(Operator::VT_OUTPUTS, outputs);
+  }
+  void add_builtin_options_type(BuiltinOptions builtin_options_type)
+  {
+    fbb_.AddElement<uint8_t>(Operator::VT_BUILTIN_OPTIONS_TYPE,
+                             static_cast<uint8_t>(builtin_options_type), 0);
+  }
+  void add_builtin_options(flatbuffers::Offset<void> builtin_options)
+  {
+    fbb_.AddOffset(Operator::VT_BUILTIN_OPTIONS, builtin_options);
+  }
+  void add_custom_options(flatbuffers::Offset<flatbuffers::Vector<uint8_t>> custom_options)
+  {
+    fbb_.AddOffset(Operator::VT_CUSTOM_OPTIONS, custom_options);
+  }
+  void add_custom_options_format(CustomOptionsFormat custom_options_format)
+  {
+    fbb_.AddElement<int8_t>(Operator::VT_CUSTOM_OPTIONS_FORMAT,
+                            static_cast<int8_t>(custom_options_format), 0);
+  }
+  void add_mutating_variable_inputs(
+      flatbuffers::Offset<flatbuffers::Vector<uint8_t>> mutating_variable_inputs)
+  {
+    fbb_.AddOffset(Operator::VT_MUTATING_VARIABLE_INPUTS, mutating_variable_inputs);
+  }
+  explicit OperatorBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  OperatorBuilder &operator=(const OperatorBuilder &);
+  flatbuffers::Offset<Operator> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<Operator>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<Operator>
+CreateOperator(flatbuffers::FlatBufferBuilder &_fbb, uint32_t opcode_index = 0,
+               flatbuffers::Offset<flatbuffers::Vector<int32_t>> inputs = 0,
+               flatbuffers::Offset<flatbuffers::Vector<int32_t>> outputs = 0,
+               BuiltinOptions builtin_options_type = BuiltinOptions_NONE,
+               flatbuffers::Offset<void> builtin_options = 0,
+               flatbuffers::Offset<flatbuffers::Vector<uint8_t>> custom_options = 0,
+               CustomOptionsFormat custom_options_format = CustomOptionsFormat_FLEXBUFFERS,
+               flatbuffers::Offset<flatbuffers::Vector<uint8_t>> mutating_variable_inputs = 0)
+{
+  OperatorBuilder builder_(_fbb);
+  builder_.add_mutating_variable_inputs(mutating_variable_inputs);
+  builder_.add_custom_options(custom_options);
+  builder_.add_builtin_options(builtin_options);
+  builder_.add_outputs(outputs);
+  builder_.add_inputs(inputs);
+  builder_.add_opcode_index(opcode_index);
+  builder_.add_custom_options_format(custom_options_format);
+  builder_.add_builtin_options_type(builtin_options_type);
+  return builder_.Finish();
+}
+
+inline flatbuffers::Offset<Operator>
+CreateOperatorDirect(flatbuffers::FlatBufferBuilder &_fbb, uint32_t opcode_index = 0,
+                     const std::vector<int32_t> *inputs = nullptr,
+                     const std::vector<int32_t> *outputs = nullptr,
+                     BuiltinOptions builtin_options_type = BuiltinOptions_NONE,
+                     flatbuffers::Offset<void> builtin_options = 0,
+                     const std::vector<uint8_t> *custom_options = nullptr,
+                     CustomOptionsFormat custom_options_format = CustomOptionsFormat_FLEXBUFFERS,
+                     const std::vector<uint8_t> *mutating_variable_inputs = nullptr)
+{
+  return neurun_tflite::CreateOperator(
+      _fbb, opcode_index, inputs ? _fbb.CreateVector<int32_t>(*inputs) : 0,
+      outputs ? _fbb.CreateVector<int32_t>(*outputs) : 0, builtin_options_type, builtin_options,
+      custom_options ? _fbb.CreateVector<uint8_t>(*custom_options) : 0, custom_options_format,
+      mutating_variable_inputs ? _fbb.CreateVector<uint8_t>(*mutating_variable_inputs) : 0);
+}
+
+struct SubGraph FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_TENSORS = 4,
+    VT_INPUTS = 6,
+    VT_OUTPUTS = 8,
+    VT_OPERATORS = 10,
+    VT_NAME = 12
+  };
+  const flatbuffers::Vector<flatbuffers::Offset<Tensor>> *tensors() const
+  {
+    return GetPointer<const flatbuffers::Vector<flatbuffers::Offset<Tensor>> *>(VT_TENSORS);
+  }
+  const flatbuffers::Vector<int32_t> *inputs() const
+  {
+    return GetPointer<const flatbuffers::Vector<int32_t> *>(VT_INPUTS);
+  }
+  const flatbuffers::Vector<int32_t> *outputs() const
+  {
+    return GetPointer<const flatbuffers::Vector<int32_t> *>(VT_OUTPUTS);
+  }
+  const flatbuffers::Vector<flatbuffers::Offset<Operator>> *operators() const
+  {
+    return GetPointer<const flatbuffers::Vector<flatbuffers::Offset<Operator>> *>(VT_OPERATORS);
+  }
+  const flatbuffers::String *name() const
+  {
+    return GetPointer<const flatbuffers::String *>(VT_NAME);
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyOffset(verifier, VT_TENSORS) &&
+           verifier.VerifyVector(tensors()) && verifier.VerifyVectorOfTables(tensors()) &&
+           VerifyOffset(verifier, VT_INPUTS) && verifier.VerifyVector(inputs()) &&
+           VerifyOffset(verifier, VT_OUTPUTS) && verifier.VerifyVector(outputs()) &&
+           VerifyOffset(verifier, VT_OPERATORS) && verifier.VerifyVector(operators()) &&
+           verifier.VerifyVectorOfTables(operators()) && VerifyOffset(verifier, VT_NAME) &&
+           verifier.VerifyString(name()) && verifier.EndTable();
+  }
+};
+
+struct SubGraphBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_tensors(flatbuffers::Offset<flatbuffers::Vector<flatbuffers::Offset<Tensor>>> tensors)
+  {
+    fbb_.AddOffset(SubGraph::VT_TENSORS, tensors);
+  }
+  void add_inputs(flatbuffers::Offset<flatbuffers::Vector<int32_t>> inputs)
+  {
+    fbb_.AddOffset(SubGraph::VT_INPUTS, inputs);
+  }
+  void add_outputs(flatbuffers::Offset<flatbuffers::Vector<int32_t>> outputs)
+  {
+    fbb_.AddOffset(SubGraph::VT_OUTPUTS, outputs);
+  }
+  void
+  add_operators(flatbuffers::Offset<flatbuffers::Vector<flatbuffers::Offset<Operator>>> operators)
+  {
+    fbb_.AddOffset(SubGraph::VT_OPERATORS, operators);
+  }
+  void add_name(flatbuffers::Offset<flatbuffers::String> name)
+  {
+    fbb_.AddOffset(SubGraph::VT_NAME, name);
+  }
+  explicit SubGraphBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  SubGraphBuilder &operator=(const SubGraphBuilder &);
+  flatbuffers::Offset<SubGraph> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<SubGraph>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<SubGraph> CreateSubGraph(
+    flatbuffers::FlatBufferBuilder &_fbb,
+    flatbuffers::Offset<flatbuffers::Vector<flatbuffers::Offset<Tensor>>> tensors = 0,
+    flatbuffers::Offset<flatbuffers::Vector<int32_t>> inputs = 0,
+    flatbuffers::Offset<flatbuffers::Vector<int32_t>> outputs = 0,
+    flatbuffers::Offset<flatbuffers::Vector<flatbuffers::Offset<Operator>>> operators = 0,
+    flatbuffers::Offset<flatbuffers::String> name = 0)
+{
+  SubGraphBuilder builder_(_fbb);
+  builder_.add_name(name);
+  builder_.add_operators(operators);
+  builder_.add_outputs(outputs);
+  builder_.add_inputs(inputs);
+  builder_.add_tensors(tensors);
+  return builder_.Finish();
+}
+
+inline flatbuffers::Offset<SubGraph>
+CreateSubGraphDirect(flatbuffers::FlatBufferBuilder &_fbb,
+                     const std::vector<flatbuffers::Offset<Tensor>> *tensors = nullptr,
+                     const std::vector<int32_t> *inputs = nullptr,
+                     const std::vector<int32_t> *outputs = nullptr,
+                     const std::vector<flatbuffers::Offset<Operator>> *operators = nullptr,
+                     const char *name = nullptr)
+{
+  return neurun_tflite::CreateSubGraph(
+      _fbb, tensors ? _fbb.CreateVector<flatbuffers::Offset<Tensor>>(*tensors) : 0,
+      inputs ? _fbb.CreateVector<int32_t>(*inputs) : 0,
+      outputs ? _fbb.CreateVector<int32_t>(*outputs) : 0,
+      operators ? _fbb.CreateVector<flatbuffers::Offset<Operator>>(*operators) : 0,
+      name ? _fbb.CreateString(name) : 0);
+}
+
+struct Buffer FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_DATA = 4
+  };
+  const flatbuffers::Vector<uint8_t> *data() const
+  {
+    return GetPointer<const flatbuffers::Vector<uint8_t> *>(VT_DATA);
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyOffset(verifier, VT_DATA) &&
+           verifier.VerifyVector(data()) && verifier.EndTable();
+  }
+};
+
+struct BufferBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_data(flatbuffers::Offset<flatbuffers::Vector<uint8_t>> data)
+  {
+    fbb_.AddOffset(Buffer::VT_DATA, data);
+  }
+  explicit BufferBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  BufferBuilder &operator=(const BufferBuilder &);
+  flatbuffers::Offset<Buffer> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<Buffer>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<Buffer>
+CreateBuffer(flatbuffers::FlatBufferBuilder &_fbb,
+             flatbuffers::Offset<flatbuffers::Vector<uint8_t>> data = 0)
+{
+  BufferBuilder builder_(_fbb);
+  builder_.add_data(data);
+  return builder_.Finish();
+}
+
+inline flatbuffers::Offset<Buffer> CreateBufferDirect(flatbuffers::FlatBufferBuilder &_fbb,
+                                                      const std::vector<uint8_t> *data = nullptr)
+{
+  return neurun_tflite::CreateBuffer(_fbb, data ? _fbb.CreateVector<uint8_t>(*data) : 0);
+}
+
+struct Model FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table
+{
+  enum
+  {
+    VT_VERSION = 4,
+    VT_OPERATOR_CODES = 6,
+    VT_SUBGRAPHS = 8,
+    VT_DESCRIPTION = 10,
+    VT_BUFFERS = 12,
+    VT_METADATA_BUFFER = 14
+  };
+  uint32_t version() const { return GetField<uint32_t>(VT_VERSION, 0); }
+  const flatbuffers::Vector<flatbuffers::Offset<OperatorCode>> *operator_codes() const
+  {
+    return GetPointer<const flatbuffers::Vector<flatbuffers::Offset<OperatorCode>> *>(
+        VT_OPERATOR_CODES);
+  }
+  const flatbuffers::Vector<flatbuffers::Offset<SubGraph>> *subgraphs() const
+  {
+    return GetPointer<const flatbuffers::Vector<flatbuffers::Offset<SubGraph>> *>(VT_SUBGRAPHS);
+  }
+  const flatbuffers::String *description() const
+  {
+    return GetPointer<const flatbuffers::String *>(VT_DESCRIPTION);
+  }
+  const flatbuffers::Vector<flatbuffers::Offset<Buffer>> *buffers() const
+  {
+    return GetPointer<const flatbuffers::Vector<flatbuffers::Offset<Buffer>> *>(VT_BUFFERS);
+  }
+  const flatbuffers::Vector<int32_t> *metadata_buffer() const
+  {
+    return GetPointer<const flatbuffers::Vector<int32_t> *>(VT_METADATA_BUFFER);
+  }
+  bool Verify(flatbuffers::Verifier &verifier) const
+  {
+    return VerifyTableStart(verifier) && VerifyField<uint32_t>(verifier, VT_VERSION) &&
+           VerifyOffset(verifier, VT_OPERATOR_CODES) && verifier.VerifyVector(operator_codes()) &&
+           verifier.VerifyVectorOfTables(operator_codes()) &&
+           VerifyOffset(verifier, VT_SUBGRAPHS) && verifier.VerifyVector(subgraphs()) &&
+           verifier.VerifyVectorOfTables(subgraphs()) && VerifyOffset(verifier, VT_DESCRIPTION) &&
+           verifier.VerifyString(description()) && VerifyOffset(verifier, VT_BUFFERS) &&
+           verifier.VerifyVector(buffers()) && verifier.VerifyVectorOfTables(buffers()) &&
+           VerifyOffset(verifier, VT_METADATA_BUFFER) && verifier.VerifyVector(metadata_buffer()) &&
+           verifier.EndTable();
+  }
+};
+
+struct ModelBuilder
+{
+  flatbuffers::FlatBufferBuilder &fbb_;
+  flatbuffers::uoffset_t start_;
+  void add_version(uint32_t version) { fbb_.AddElement<uint32_t>(Model::VT_VERSION, version, 0); }
+  void add_operator_codes(
+      flatbuffers::Offset<flatbuffers::Vector<flatbuffers::Offset<OperatorCode>>> operator_codes)
+  {
+    fbb_.AddOffset(Model::VT_OPERATOR_CODES, operator_codes);
+  }
+  void
+  add_subgraphs(flatbuffers::Offset<flatbuffers::Vector<flatbuffers::Offset<SubGraph>>> subgraphs)
+  {
+    fbb_.AddOffset(Model::VT_SUBGRAPHS, subgraphs);
+  }
+  void add_description(flatbuffers::Offset<flatbuffers::String> description)
+  {
+    fbb_.AddOffset(Model::VT_DESCRIPTION, description);
+  }
+  void add_buffers(flatbuffers::Offset<flatbuffers::Vector<flatbuffers::Offset<Buffer>>> buffers)
+  {
+    fbb_.AddOffset(Model::VT_BUFFERS, buffers);
+  }
+  void add_metadata_buffer(flatbuffers::Offset<flatbuffers::Vector<int32_t>> metadata_buffer)
+  {
+    fbb_.AddOffset(Model::VT_METADATA_BUFFER, metadata_buffer);
+  }
+  explicit ModelBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb)
+  {
+    start_ = fbb_.StartTable();
+  }
+  ModelBuilder &operator=(const ModelBuilder &);
+  flatbuffers::Offset<Model> Finish()
+  {
+    const auto end = fbb_.EndTable(start_);
+    auto o = flatbuffers::Offset<Model>(end);
+    return o;
+  }
+};
+
+inline flatbuffers::Offset<Model> CreateModel(
+    flatbuffers::FlatBufferBuilder &_fbb, uint32_t version = 0,
+    flatbuffers::Offset<flatbuffers::Vector<flatbuffers::Offset<OperatorCode>>> operator_codes = 0,
+    flatbuffers::Offset<flatbuffers::Vector<flatbuffers::Offset<SubGraph>>> subgraphs = 0,
+    flatbuffers::Offset<flatbuffers::String> description = 0,
+    flatbuffers::Offset<flatbuffers::Vector<flatbuffers::Offset<Buffer>>> buffers = 0,
+    flatbuffers::Offset<flatbuffers::Vector<int32_t>> metadata_buffer = 0)
+{
+  ModelBuilder builder_(_fbb);
+  builder_.add_metadata_buffer(metadata_buffer);
+  builder_.add_buffers(buffers);
+  builder_.add_description(description);
+  builder_.add_subgraphs(subgraphs);
+  builder_.add_operator_codes(operator_codes);
+  builder_.add_version(version);
+  return builder_.Finish();
+}
+
+inline flatbuffers::Offset<Model>
+CreateModelDirect(flatbuffers::FlatBufferBuilder &_fbb, uint32_t version = 0,
+                  const std::vector<flatbuffers::Offset<OperatorCode>> *operator_codes = nullptr,
+                  const std::vector<flatbuffers::Offset<SubGraph>> *subgraphs = nullptr,
+                  const char *description = nullptr,
+                  const std::vector<flatbuffers::Offset<Buffer>> *buffers = nullptr,
+                  const std::vector<int32_t> *metadata_buffer = nullptr)
+{
+  return neurun_tflite::CreateModel(
+      _fbb, version,
+      operator_codes ? _fbb.CreateVector<flatbuffers::Offset<OperatorCode>>(*operator_codes) : 0,
+      subgraphs ? _fbb.CreateVector<flatbuffers::Offset<SubGraph>>(*subgraphs) : 0,
+      description ? _fbb.CreateString(description) : 0,
+      buffers ? _fbb.CreateVector<flatbuffers::Offset<Buffer>>(*buffers) : 0,
+      metadata_buffer ? _fbb.CreateVector<int32_t>(*metadata_buffer) : 0);
+}
+
+inline bool VerifyQuantizationDetails(flatbuffers::Verifier &verifier, const void *obj,
+                                      QuantizationDetails type)
+{
+  switch (type)
+  {
+    case QuantizationDetails_NONE:
+    {
+      return true;
+    }
+    case QuantizationDetails_CustomQuantization:
+    {
+      auto ptr = reinterpret_cast<const CustomQuantization *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    default:
+      return false;
+  }
+}
+
+inline bool
+VerifyQuantizationDetailsVector(flatbuffers::Verifier &verifier,
+                                const flatbuffers::Vector<flatbuffers::Offset<void>> *values,
+                                const flatbuffers::Vector<uint8_t> *types)
+{
+  if (!values || !types)
+    return !values && !types;
+  if (values->size() != types->size())
+    return false;
+  for (flatbuffers::uoffset_t i = 0; i < values->size(); ++i)
+  {
+    if (!VerifyQuantizationDetails(verifier, values->Get(i),
+                                   types->GetEnum<QuantizationDetails>(i)))
+    {
+      return false;
+    }
+  }
+  return true;
+}
+
+inline bool VerifyBuiltinOptions(flatbuffers::Verifier &verifier, const void *obj,
+                                 BuiltinOptions type)
+{
+  switch (type)
+  {
+    case BuiltinOptions_NONE:
+    {
+      return true;
+    }
+    case BuiltinOptions_Conv2DOptions:
+    {
+      auto ptr = reinterpret_cast<const Conv2DOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_DepthwiseConv2DOptions:
+    {
+      auto ptr = reinterpret_cast<const DepthwiseConv2DOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_ConcatEmbeddingsOptions:
+    {
+      auto ptr = reinterpret_cast<const ConcatEmbeddingsOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_LSHProjectionOptions:
+    {
+      auto ptr = reinterpret_cast<const LSHProjectionOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_Pool2DOptions:
+    {
+      auto ptr = reinterpret_cast<const Pool2DOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_SVDFOptions:
+    {
+      auto ptr = reinterpret_cast<const SVDFOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_RNNOptions:
+    {
+      auto ptr = reinterpret_cast<const RNNOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_FullyConnectedOptions:
+    {
+      auto ptr = reinterpret_cast<const FullyConnectedOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_SoftmaxOptions:
+    {
+      auto ptr = reinterpret_cast<const SoftmaxOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_ConcatenationOptions:
+    {
+      auto ptr = reinterpret_cast<const ConcatenationOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_AddOptions:
+    {
+      auto ptr = reinterpret_cast<const AddOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_L2NormOptions:
+    {
+      auto ptr = reinterpret_cast<const L2NormOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_LocalResponseNormalizationOptions:
+    {
+      auto ptr = reinterpret_cast<const LocalResponseNormalizationOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_LSTMOptions:
+    {
+      auto ptr = reinterpret_cast<const LSTMOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_ResizeBilinearOptions:
+    {
+      auto ptr = reinterpret_cast<const ResizeBilinearOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_CallOptions:
+    {
+      auto ptr = reinterpret_cast<const CallOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_ReshapeOptions:
+    {
+      auto ptr = reinterpret_cast<const ReshapeOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_SkipGramOptions:
+    {
+      auto ptr = reinterpret_cast<const SkipGramOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_SpaceToDepthOptions:
+    {
+      auto ptr = reinterpret_cast<const SpaceToDepthOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_EmbeddingLookupSparseOptions:
+    {
+      auto ptr = reinterpret_cast<const EmbeddingLookupSparseOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_MulOptions:
+    {
+      auto ptr = reinterpret_cast<const MulOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_PadOptions:
+    {
+      auto ptr = reinterpret_cast<const PadOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_GatherOptions:
+    {
+      auto ptr = reinterpret_cast<const GatherOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_BatchToSpaceNDOptions:
+    {
+      auto ptr = reinterpret_cast<const BatchToSpaceNDOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_SpaceToBatchNDOptions:
+    {
+      auto ptr = reinterpret_cast<const SpaceToBatchNDOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_TransposeOptions:
+    {
+      auto ptr = reinterpret_cast<const TransposeOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_ReducerOptions:
+    {
+      auto ptr = reinterpret_cast<const ReducerOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_SubOptions:
+    {
+      auto ptr = reinterpret_cast<const SubOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_DivOptions:
+    {
+      auto ptr = reinterpret_cast<const DivOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_SqueezeOptions:
+    {
+      auto ptr = reinterpret_cast<const SqueezeOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_SequenceRNNOptions:
+    {
+      auto ptr = reinterpret_cast<const SequenceRNNOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_StridedSliceOptions:
+    {
+      auto ptr = reinterpret_cast<const StridedSliceOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_ExpOptions:
+    {
+      auto ptr = reinterpret_cast<const ExpOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_TopKV2Options:
+    {
+      auto ptr = reinterpret_cast<const TopKV2Options *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_SplitOptions:
+    {
+      auto ptr = reinterpret_cast<const SplitOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_LogSoftmaxOptions:
+    {
+      auto ptr = reinterpret_cast<const LogSoftmaxOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_CastOptions:
+    {
+      auto ptr = reinterpret_cast<const CastOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_DequantizeOptions:
+    {
+      auto ptr = reinterpret_cast<const DequantizeOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_MaximumMinimumOptions:
+    {
+      auto ptr = reinterpret_cast<const MaximumMinimumOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_ArgMaxOptions:
+    {
+      auto ptr = reinterpret_cast<const ArgMaxOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_LessOptions:
+    {
+      auto ptr = reinterpret_cast<const LessOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_NegOptions:
+    {
+      auto ptr = reinterpret_cast<const NegOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_PadV2Options:
+    {
+      auto ptr = reinterpret_cast<const PadV2Options *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_GreaterOptions:
+    {
+      auto ptr = reinterpret_cast<const GreaterOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_GreaterEqualOptions:
+    {
+      auto ptr = reinterpret_cast<const GreaterEqualOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_LessEqualOptions:
+    {
+      auto ptr = reinterpret_cast<const LessEqualOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_SelectOptions:
+    {
+      auto ptr = reinterpret_cast<const SelectOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_SliceOptions:
+    {
+      auto ptr = reinterpret_cast<const SliceOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_TransposeConvOptions:
+    {
+      auto ptr = reinterpret_cast<const TransposeConvOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_SparseToDenseOptions:
+    {
+      auto ptr = reinterpret_cast<const SparseToDenseOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_TileOptions:
+    {
+      auto ptr = reinterpret_cast<const TileOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_ExpandDimsOptions:
+    {
+      auto ptr = reinterpret_cast<const ExpandDimsOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_EqualOptions:
+    {
+      auto ptr = reinterpret_cast<const EqualOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_NotEqualOptions:
+    {
+      auto ptr = reinterpret_cast<const NotEqualOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_ShapeOptions:
+    {
+      auto ptr = reinterpret_cast<const ShapeOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_PowOptions:
+    {
+      auto ptr = reinterpret_cast<const PowOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_ArgMinOptions:
+    {
+      auto ptr = reinterpret_cast<const ArgMinOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_FakeQuantOptions:
+    {
+      auto ptr = reinterpret_cast<const FakeQuantOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_PackOptions:
+    {
+      auto ptr = reinterpret_cast<const PackOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_LogicalOrOptions:
+    {
+      auto ptr = reinterpret_cast<const LogicalOrOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_OneHotOptions:
+    {
+      auto ptr = reinterpret_cast<const OneHotOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_LogicalAndOptions:
+    {
+      auto ptr = reinterpret_cast<const LogicalAndOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_LogicalNotOptions:
+    {
+      auto ptr = reinterpret_cast<const LogicalNotOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_UnpackOptions:
+    {
+      auto ptr = reinterpret_cast<const UnpackOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_FloorDivOptions:
+    {
+      auto ptr = reinterpret_cast<const FloorDivOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_SquareOptions:
+    {
+      auto ptr = reinterpret_cast<const SquareOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_ZerosLikeOptions:
+    {
+      auto ptr = reinterpret_cast<const ZerosLikeOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_FillOptions:
+    {
+      auto ptr = reinterpret_cast<const FillOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_BidirectionalSequenceLSTMOptions:
+    {
+      auto ptr = reinterpret_cast<const BidirectionalSequenceLSTMOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_BidirectionalSequenceRNNOptions:
+    {
+      auto ptr = reinterpret_cast<const BidirectionalSequenceRNNOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_UnidirectionalSequenceLSTMOptions:
+    {
+      auto ptr = reinterpret_cast<const UnidirectionalSequenceLSTMOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_FloorModOptions:
+    {
+      auto ptr = reinterpret_cast<const FloorModOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_RangeOptions:
+    {
+      auto ptr = reinterpret_cast<const RangeOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_ResizeNearestNeighborOptions:
+    {
+      auto ptr = reinterpret_cast<const ResizeNearestNeighborOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_LeakyReluOptions:
+    {
+      auto ptr = reinterpret_cast<const LeakyReluOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_SquaredDifferenceOptions:
+    {
+      auto ptr = reinterpret_cast<const SquaredDifferenceOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_MirrorPadOptions:
+    {
+      auto ptr = reinterpret_cast<const MirrorPadOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_AbsOptions:
+    {
+      auto ptr = reinterpret_cast<const AbsOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    case BuiltinOptions_SplitVOptions:
+    {
+      auto ptr = reinterpret_cast<const SplitVOptions *>(obj);
+      return verifier.VerifyTable(ptr);
+    }
+    default:
+      return false;
+  }
+}
+
+inline bool VerifyBuiltinOptionsVector(flatbuffers::Verifier &verifier,
+                                       const flatbuffers::Vector<flatbuffers::Offset<void>> *values,
+                                       const flatbuffers::Vector<uint8_t> *types)
+{
+  if (!values || !types)
+    return !values && !types;
+  if (values->size() != types->size())
+    return false;
+  for (flatbuffers::uoffset_t i = 0; i < values->size(); ++i)
+  {
+    if (!VerifyBuiltinOptions(verifier, values->Get(i), types->GetEnum<BuiltinOptions>(i)))
+    {
+      return false;
+    }
+  }
+  return true;
+}
+
+inline const neurun_tflite::Model *GetModel(const void *buf)
+{
+  return flatbuffers::GetRoot<neurun_tflite::Model>(buf);
+}
+
+inline const neurun_tflite::Model *GetSizePrefixedModel(const void *buf)
+{
+  return flatbuffers::GetSizePrefixedRoot<neurun_tflite::Model>(buf);
+}
+
+inline const char *ModelIdentifier() { return "TFL3"; }
+
+inline bool ModelBufferHasIdentifier(const void *buf)
+{
+  return flatbuffers::BufferHasIdentifier(buf, ModelIdentifier());
+}
+
+inline bool VerifyModelBuffer(flatbuffers::Verifier &verifier)
+{
+  return verifier.VerifyBuffer<neurun_tflite::Model>(ModelIdentifier());
+}
+
+inline bool VerifySizePrefixedModelBuffer(flatbuffers::Verifier &verifier)
+{
+  return verifier.VerifySizePrefixedBuffer<neurun_tflite::Model>(ModelIdentifier());
+}
+
+inline const char *ModelExtension() { return "tflite"; }
+
+inline void FinishModelBuffer(flatbuffers::FlatBufferBuilder &fbb,
+                              flatbuffers::Offset<neurun_tflite::Model> root)
+{
+  fbb.Finish(root, ModelIdentifier());
+}
+
+inline void FinishSizePrefixedModelBuffer(flatbuffers::FlatBufferBuilder &fbb,
+                                          flatbuffers::Offset<neurun_tflite::Model> root)
+{
+  fbb.FinishSizePrefixed(root, ModelIdentifier());
+}
+
+} // namespace neurun_tflite
+
+#endif // FLATBUFFERS_GENERATED_SCHEMA_NEURUN_TFLITE_H_
diff --git a/runtime/neurun/frontend/tflite/tflite_schema.fbs b/runtime/neurun/frontend/tflite/tflite_schema.fbs
new file mode 100644
index 000000000..ede4dfa3a
--- /dev/null
+++ b/runtime/neurun/frontend/tflite/tflite_schema.fbs
@@ -0,0 +1,795 @@
+// Copyright 2017 The TensorFlow Authors. All Rights Reserved.
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// Revision History
+// Version 0: Initial version.
+// Version 1: Add subgraphs to schema.
+// Version 2: Rename operators to conform to NN API.
+// Version 3: Move buffer data from Model.Subgraph.Tensors to Model.Buffers.
+
+// Change namespace to neurun_tflite
+namespace neurun_tflite;
+
+// This corresponds to the version.
+file_identifier "TFL3";
+// File extension of any written files.
+file_extension "tflite";
+
+// IMPORTANT: All new members of tables, enums and unions must be added at the
+// end to ensure backwards compatibility.
+
+// The type of data stored in a tensor.
+enum TensorType : byte {
+  FLOAT32 = 0,
+  FLOAT16 = 1,
+  INT32 = 2,
+  UINT8 = 3,
+  INT64 = 4,
+  STRING = 5,
+  BOOL = 6,
+  INT16 = 7,
+  COMPLEX64 = 8,
+  INT8 = 9,
+}
+
+// Custom quantization parameters for experimenting with new quantization
+// techniques.
+table CustomQuantization {
+  custom:[ubyte] (force_align: 16);
+}
+
+// Represents a specific quantization technique's parameters.
+union QuantizationDetails {
+  CustomQuantization,
+}
+
+// Parameters for converting a quantized tensor back to float.
+table QuantizationParameters {
+  // These four parameters are the asymmetric linear quantization parameters.
+  // Given a quantized value q, the corresponding float value f should be:
+  //   f = scale * (q - zero_point)
+  // For other quantization types, the QuantizationDetails below is used.
+  min:[float];  // For importing back into tensorflow.
+  max:[float];  // For importing back into tensorflow.
+  scale:[float];  // For dequantizing the tensor's values.
+  zero_point:[long];
+
+  // If this is not none, the quantization parameters above are ignored and the
+  // value of the QuantizationDetails union below should be used.
+  details:QuantizationDetails;
+}
+
+table Tensor {
+  // The tensor shape. The meaning of each entry is operator-specific but
+  // builtin ops use: [batch size, height, width, number of channels] (That's
+  // Tensorflow's NHWC).
+  shape:[int];
+  type:TensorType;
+  // An index that refers to the buffers table at the root of the model. Or,
+  // if there is no data buffer associated (i.e. intermediate results), then
+  // this is 0 (which refers to an always existent empty buffer).
+  //
+  // The data_buffer itself is an opaque container, with the assumption that the
+  // target device is little-endian. In addition, all builtin operators assume
+  // the memory is ordered such that if `shape` is [4, 3, 2], then index
+  // [i, j, k] maps to data_buffer[i*3*2 + j*2 + k].
+  buffer:uint;
+  name:string;  // For debugging and importing back into tensorflow.
+  quantization:QuantizationParameters;  // Optional.
+
+  is_variable:bool = false;
+}
+
+// A list of builtin operators. Builtin operators are slightly faster than custom
+// ones, but not by much. Moreover, while custom operators accept an opaque
+// object containing configuration parameters, builtins have a predetermined
+// set of acceptable options.
+enum BuiltinOperator : byte {
+  ADD = 0,
+  AVERAGE_POOL_2D = 1,
+  CONCATENATION = 2,
+  CONV_2D = 3,
+  DEPTHWISE_CONV_2D = 4,
+  // DEPTH_TO_SPACE = 5,
+  DEQUANTIZE = 6,
+  EMBEDDING_LOOKUP = 7,
+  FLOOR = 8,
+  FULLY_CONNECTED = 9,
+  HASHTABLE_LOOKUP = 10,
+  L2_NORMALIZATION = 11,
+  L2_POOL_2D = 12,
+  LOCAL_RESPONSE_NORMALIZATION = 13,
+  LOGISTIC = 14,
+  LSH_PROJECTION = 15,
+  LSTM = 16,
+  MAX_POOL_2D = 17,
+  MUL = 18,
+  RELU = 19,
+  // NOTE(aselle): RELU_N1_TO_1 used to be called RELU1, but it was renamed
+  // since different model developers use RELU1 in different ways. Never
+  // create another op called RELU1.
+  RELU_N1_TO_1 = 20,
+  RELU6 = 21,
+  RESHAPE = 22,
+  RESIZE_BILINEAR = 23,
+  RNN = 24,
+  SOFTMAX = 25,
+  SPACE_TO_DEPTH = 26,
+  SVDF = 27,
+  TANH = 28,
+  // TODO(aselle): Consider rename to CONCATENATE_EMBEDDINGS
+  CONCAT_EMBEDDINGS = 29,
+  SKIP_GRAM = 30,
+  CALL = 31,
+  CUSTOM = 32,
+  EMBEDDING_LOOKUP_SPARSE = 33,
+  PAD = 34,
+  UNIDIRECTIONAL_SEQUENCE_RNN = 35,
+  GATHER = 36,
+  BATCH_TO_SPACE_ND = 37,
+  SPACE_TO_BATCH_ND = 38,
+  TRANSPOSE = 39,
+  MEAN = 40,
+  SUB = 41,
+  DIV = 42,
+  SQUEEZE = 43,
+  UNIDIRECTIONAL_SEQUENCE_LSTM = 44,
+  STRIDED_SLICE = 45,
+  BIDIRECTIONAL_SEQUENCE_RNN = 46,
+  EXP = 47,
+  TOPK_V2 = 48,
+  SPLIT = 49,
+  LOG_SOFTMAX = 50,
+  // DELEGATE is a special op type for the operations which are delegated to
+  // other backends.
+  // WARNING: Experimental interface, subject to change
+  DELEGATE = 51,
+  BIDIRECTIONAL_SEQUENCE_LSTM = 52,
+  CAST = 53,
+  PRELU = 54,
+  MAXIMUM = 55,
+  ARG_MAX = 56,
+  MINIMUM = 57,
+  LESS = 58,
+  NEG = 59,
+  PADV2 = 60,
+  GREATER = 61,
+  GREATER_EQUAL = 62,
+  LESS_EQUAL = 63,
+  SELECT = 64,
+  SLICE = 65,
+  SIN = 66,
+  TRANSPOSE_CONV = 67,
+  SPARSE_TO_DENSE = 68,
+  TILE = 69,
+  EXPAND_DIMS = 70,
+  EQUAL = 71,
+  NOT_EQUAL = 72,
+  LOG = 73,
+  SUM = 74,
+  SQRT = 75,
+  RSQRT = 76,
+  SHAPE = 77,
+  POW = 78,
+  ARG_MIN = 79,
+  FAKE_QUANT = 80,
+  REDUCE_PROD = 81,
+  REDUCE_MAX = 82,
+  PACK = 83,
+  LOGICAL_OR = 84,
+  ONE_HOT = 85,
+  LOGICAL_AND = 86,
+  LOGICAL_NOT = 87,
+  UNPACK = 88,
+  REDUCE_MIN = 89,
+  FLOOR_DIV = 90,
+  REDUCE_ANY = 91,
+  SQUARE = 92,
+  ZEROS_LIKE = 93,
+  FILL = 94,
+  FLOOR_MOD = 95,
+  RANGE = 96,
+  RESIZE_NEAREST_NEIGHBOR = 97,
+  LEAKY_RELU = 98,
+  SQUARED_DIFFERENCE = 99,
+  MIRROR_PAD = 100,
+  ABS = 101,
+  SPLIT_V = 102,
+}
+
+// Options for the builtin operators.
+union BuiltinOptions {
+  Conv2DOptions,
+  DepthwiseConv2DOptions,
+  ConcatEmbeddingsOptions,
+  LSHProjectionOptions,
+  Pool2DOptions,
+  SVDFOptions,
+  RNNOptions,
+  FullyConnectedOptions,
+  SoftmaxOptions,
+  ConcatenationOptions,
+  AddOptions,
+  L2NormOptions,
+  LocalResponseNormalizationOptions,
+  LSTMOptions,
+  ResizeBilinearOptions,
+  CallOptions,
+  ReshapeOptions,
+  SkipGramOptions,
+  SpaceToDepthOptions,
+  EmbeddingLookupSparseOptions,
+  MulOptions,
+  PadOptions,
+  GatherOptions,
+  BatchToSpaceNDOptions,
+  SpaceToBatchNDOptions,
+  TransposeOptions,
+  ReducerOptions,
+  SubOptions,
+  DivOptions,
+  SqueezeOptions,
+  SequenceRNNOptions,
+  StridedSliceOptions,
+  ExpOptions,
+  TopKV2Options,
+  SplitOptions,
+  LogSoftmaxOptions,
+  CastOptions,
+  DequantizeOptions,
+  MaximumMinimumOptions,
+  ArgMaxOptions,
+  LessOptions,
+  NegOptions,
+  PadV2Options,
+  GreaterOptions,
+  GreaterEqualOptions,
+  LessEqualOptions,
+  SelectOptions,
+  SliceOptions,
+  TransposeConvOptions,
+  SparseToDenseOptions,
+  TileOptions,
+  ExpandDimsOptions,
+  EqualOptions,
+  NotEqualOptions,
+  ShapeOptions,
+  PowOptions,
+  ArgMinOptions,
+  FakeQuantOptions,
+  PackOptions,
+  LogicalOrOptions,
+  OneHotOptions,
+  LogicalAndOptions,
+  LogicalNotOptions,
+  UnpackOptions,
+  FloorDivOptions,
+  SquareOptions,
+  ZerosLikeOptions,
+  FillOptions,
+  BidirectionalSequenceLSTMOptions,
+  BidirectionalSequenceRNNOptions,
+  UnidirectionalSequenceLSTMOptions,
+  FloorModOptions,
+  RangeOptions,
+  ResizeNearestNeighborOptions,
+  LeakyReluOptions,
+  SquaredDifferenceOptions,
+  MirrorPadOptions,
+  AbsOptions,
+  SplitVOptions,
+}
+
+enum Padding : byte { SAME, VALID }
+
+enum ActivationFunctionType : byte {
+  NONE = 0,
+  RELU = 1,
+  RELU_N1_TO_1 = 2,
+  RELU6 = 3,
+  TANH = 4,
+  SIGN_BIT = 5,
+}
+
+table Conv2DOptions {
+  padding:Padding;
+  stride_w:int;
+  stride_h:int;
+  fused_activation_function:ActivationFunctionType;
+  dilation_w_factor:int = 1;
+  dilation_h_factor:int = 1;
+}
+
+table Pool2DOptions {
+  padding:Padding;
+  stride_w:int;
+  stride_h:int;
+  filter_width:int;
+  filter_height:int;
+  fused_activation_function:ActivationFunctionType;
+}
+
+table DepthwiseConv2DOptions {
+  // Parameters for DepthwiseConv version 1 or above.
+  padding:Padding;
+  stride_w:int;
+  stride_h:int;
+  depth_multiplier:int;
+  fused_activation_function:ActivationFunctionType;
+  // Parameters for DepthwiseConv version 2 or above.
+  dilation_w_factor:int = 1;
+  dilation_h_factor:int = 1;
+}
+
+table ConcatEmbeddingsOptions {
+  num_channels:int;
+  num_columns_per_channel:[int];
+  embedding_dim_per_channel:[int]; // This could be inferred from parameters.
+}
+
+enum LSHProjectionType: byte {
+  UNKNOWN = 0,
+  SPARSE = 1,
+  DENSE = 2,
+}
+
+table LSHProjectionOptions {
+  type: LSHProjectionType;
+}
+
+table SVDFOptions {
+  rank:int;
+  fused_activation_function:ActivationFunctionType;
+}
+
+// An implementation of TensorFlow RNNCell.
+table RNNOptions {
+  fused_activation_function:ActivationFunctionType;
+}
+
+// An implementation of TensorFlow dynamic_rnn with RNNCell.
+table SequenceRNNOptions {
+  time_major:bool;
+  fused_activation_function:ActivationFunctionType;
+}
+
+// An implementation of TensorFlow bidrectional_dynamic_rnn with RNNCell.
+table BidirectionalSequenceRNNOptions {
+  time_major:bool;
+  fused_activation_function:ActivationFunctionType;
+  merge_outputs: bool;
+}
+
+enum FullyConnectedOptionsWeightsFormat: byte {
+  DEFAULT = 0,
+  SHUFFLED4x16INT8 = 1,
+}
+
+// An implementation of TensorFlow fully_connected (a.k.a Dense) layer.
+table FullyConnectedOptions {
+  // Parameters for FullyConnected version 1 or above.
+  fused_activation_function:ActivationFunctionType;
+
+  // Parameters for FullyConnected version 2 or above.
+  weights_format:FullyConnectedOptionsWeightsFormat = DEFAULT;
+}
+
+table SoftmaxOptions {
+  beta: float;
+}
+
+// An implementation of TensorFlow concat.
+table ConcatenationOptions {
+  axis:int;
+  fused_activation_function:ActivationFunctionType;
+}
+
+table AddOptions {
+  fused_activation_function:ActivationFunctionType;
+}
+
+table MulOptions {
+  fused_activation_function:ActivationFunctionType;
+}
+
+table L2NormOptions {
+  fused_activation_function:ActivationFunctionType;
+}
+
+table LocalResponseNormalizationOptions {
+  radius:int;
+  bias:float;
+  alpha:float;
+  beta:float;
+}
+
+enum LSTMKernelType : byte {
+  // Full LSTM kernel which supports peephole and projection.
+  FULL = 0,
+  // Basic LSTM kernels. Equivalent to TensorFlow BasicLSTMCell.
+  BASIC = 1,
+}
+
+// An implementation of TensorFlow LSTMCell and CoupledInputForgetGateLSTMCell
+table LSTMOptions {
+  // Parameters for LSTM version 1 or above.
+  fused_activation_function:ActivationFunctionType;
+  cell_clip: float; // Optional, 0.0 means no clipping
+  proj_clip: float; // Optional, 0.0 means no clipping
+
+  // Parameters for LSTM version 2 or above.
+  // Basic kernel is only supported in version 2 or above.
+  kernel_type: LSTMKernelType = FULL;
+}
+
+// An implementation of TensorFlow dynamic_rnn with LSTMCell.
+table UnidirectionalSequenceLSTMOptions {
+  fused_activation_function:ActivationFunctionType;
+  cell_clip: float; // Optional, 0.0 means no clipping
+  proj_clip: float; // Optional, 0.0 means no clipping
+
+  // If true then first dimension is sequence, otherwise batch.
+  time_major:bool;
+}
+
+table BidirectionalSequenceLSTMOptions {
+  fused_activation_function:ActivationFunctionType;
+  cell_clip: float; // Optional, 0.0 means no clipping
+  proj_clip: float; // Optional, 0.0 means no clipping
+
+  // If true, store the outputs of both directions into the first output.
+  merge_outputs: bool;
+}
+
+table ResizeBilinearOptions {
+  new_height: int (deprecated);
+  new_width: int (deprecated);
+  align_corners: bool;
+}
+
+table ResizeNearestNeighborOptions {
+  align_corners: bool;
+}
+
+// A call operation options
+table CallOptions {
+  // The subgraph index that needs to be called.
+  subgraph:uint;
+}
+
+table PadOptions {
+}
+
+table PadV2Options {
+}
+
+table ReshapeOptions {
+  new_shape:[int];
+}
+
+table SpaceToBatchNDOptions {
+}
+
+table BatchToSpaceNDOptions {
+}
+
+table SkipGramOptions {
+  ngram_size: int;
+  max_skip_size: int;
+  include_all_ngrams: bool;
+}
+
+table SpaceToDepthOptions {
+  block_size: int;
+}
+
+table SubOptions {
+  fused_activation_function:ActivationFunctionType;
+}
+
+table DivOptions {
+  fused_activation_function:ActivationFunctionType;
+}
+
+table TopKV2Options {
+}
+
+enum CombinerType : byte {
+  SUM = 0,
+  MEAN = 1,
+  SQRTN = 2,
+}
+
+table EmbeddingLookupSparseOptions {
+  combiner:CombinerType;
+}
+
+table GatherOptions {
+  axis: int;
+}
+
+table TransposeOptions {
+}
+
+table ExpOptions {
+}
+
+table ReducerOptions {
+  keep_dims: bool;
+}
+
+table SqueezeOptions {
+  squeeze_dims:[int];
+}
+
+table SplitOptions {
+  num_splits: int;
+}
+
+table SplitVOptions {
+  num_splits: int;
+}
+
+table StridedSliceOptions {
+  begin_mask: int;
+  end_mask: int;
+  ellipsis_mask: int;
+  new_axis_mask: int;
+  shrink_axis_mask: int;
+}
+
+table LogSoftmaxOptions {
+}
+
+table CastOptions {
+  in_data_type: TensorType;
+  out_data_type: TensorType;
+}
+
+table DequantizeOptions {
+}
+
+table MaximumMinimumOptions {
+}
+
+table TileOptions {
+}
+
+table ArgMaxOptions {
+  output_type : TensorType;
+}
+
+table ArgMinOptions {
+  output_type : TensorType;
+}
+
+table GreaterOptions {
+}
+
+table GreaterEqualOptions {
+}
+
+table LessOptions {
+}
+
+table LessEqualOptions {
+}
+
+table NegOptions {
+}
+
+table SelectOptions {
+}
+
+table SliceOptions {
+}
+
+table TransposeConvOptions {
+  padding:Padding;
+  stride_w:int;
+  stride_h:int;
+}
+
+table ExpandDimsOptions {
+}
+
+table SparseToDenseOptions {
+  validate_indices:bool;
+}
+
+table EqualOptions {
+}
+
+table NotEqualOptions {
+}
+
+table ShapeOptions {
+  // Optional output type of the operation (int32 or int64). Defaults to int32.
+  out_type : TensorType;
+}
+
+table PowOptions {
+}
+
+table FakeQuantOptions {
+  // Parameters supported by version 1:
+  min:float;
+  max:float;
+  num_bits:int;
+
+  // Parameters supported by version 2:
+  narrow_range:bool;
+}
+
+table PackOptions {
+  values_count:int;
+  axis:int;
+}
+
+table LogicalOrOptions {
+}
+
+table OneHotOptions {
+  axis:int;
+}
+
+table AbsOptions {
+}
+
+
+table LogicalAndOptions {
+}
+
+table LogicalNotOptions {
+}
+
+table UnpackOptions {
+  num:int;
+  axis:int;
+}
+
+table FloorDivOptions {
+}
+
+table SquareOptions {
+}
+
+table ZerosLikeOptions {
+}
+
+table FillOptions {
+}
+
+table FloorModOptions {
+}
+
+table RangeOptions {
+}
+
+table LeakyReluOptions {
+  alpha:float;
+}
+
+table SquaredDifferenceOptions {
+}
+
+enum MirrorPadMode : byte {
+  // Doesn't include borders.
+  REFLECT = 0,
+  // Includes borders.
+  SYMMETRIC = 1,
+}
+
+table MirrorPadOptions {
+  mode:MirrorPadMode;
+}
+
+// An OperatorCode can be an enum value (BuiltinOperator) if the operator is a
+// builtin, or a string if the operator is custom.
+table OperatorCode {
+  builtin_code:BuiltinOperator;
+  custom_code:string;
+
+  // The version of the operator. The version need to be bumped whenever new
+  // parameters are introduced into an op.
+  version:int = 1;
+}
+
+enum CustomOptionsFormat : byte {
+  FLEXBUFFERS = 0,
+}
+
+// An operator takes tensors as inputs and outputs. The type of operation being
+// performed is determined by an index into the list of valid OperatorCodes,
+// while the specifics of each operations is configured using builtin_options
+// or custom_options.
+table Operator {
+  // Index into the operator_codes array. Using an integer here avoids
+  // complicate map lookups.
+  opcode_index:uint;
+
+  // Optional input and output tensors are indicated by -1.
+  inputs:[int];
+  outputs:[int];
+
+  builtin_options:BuiltinOptions;
+  custom_options:[ubyte];
+  custom_options_format:CustomOptionsFormat;
+
+  // A list of booleans indicating the input tensors which are being mutated by
+  // this operator.(e.g. used by RNN and LSTM).
+  // For example, if the "inputs" array refers to 5 tensors and the second and
+  // fifth are mutable variables, then this list will contain
+  // [false, true, false, false, true].
+  //
+  // If the list is empty, no variable is mutated in this operator.
+  // The list either has the same length as `inputs`, or is empty.
+  mutating_variable_inputs:[bool];
+}
+
+// The root type, defining a subgraph, which typically represents an entire
+// model.
+table SubGraph {
+  // A list of all tensors used in this subgraph.
+  tensors:[Tensor];
+
+  // Indices of the tensors that are inputs into this subgraph. Note this is
+  // the list of non-static tensors that feed into the subgraph for inference.
+  inputs:[int];
+
+  // Indices of the tensors that are outputs out of this subgraph. Note this is
+  // the list of output tensors that are considered the product of the
+  // subgraph's inference.
+  outputs:[int];
+
+  // All operators, in execution order.
+  operators:[Operator];
+
+  // Name of this subgraph (used for debugging).
+  name:string;
+}
+
+// Table of raw data buffers (used for constant tensors). Referenced by tensors
+// by index. The generous alignment accommodates mmap-friendly data structures.
+table Buffer {
+  data:[ubyte] (force_align: 16);
+}
+
+table Model {
+  // Version of the schema.
+  version:uint;
+
+  // A list of all operator codes used in this model. This is
+  // kept in order because operators carry an index into this
+  // vector.
+  operator_codes:[OperatorCode];
+
+  // All the subgraphs of the model. The 0th is assumed to be the main
+  // model.
+  subgraphs:[SubGraph];
+
+  // A description of the model.
+  description:string;
+
+  // Buffers of the model.
+  // Note the 0th entry of this array must be an empty buffer (sentinel).
+  // This is a convention so that tensors without a buffer can provide 0 as
+  // their buffer.
+  buffers:[Buffer];
+
+  // Metadata about the model.  Indirects into the existings buffers list.
+  metadata_buffer:[int];
+}
+
+root_type Model;
diff --git a/runtime/neurun/sample/CMakeLists.txt b/runtime/neurun/sample/CMakeLists.txt
new file mode 100644
index 000000000..d853ba634
--- /dev/null
+++ b/runtime/neurun/sample/CMakeLists.txt
@@ -0,0 +1 @@
+add_subdirectory(minimal)
diff --git a/runtime/neurun/sample/minimal/CMakeLists.txt b/runtime/neurun/sample/minimal/CMakeLists.txt
new file mode 100644
index 000000000..6f4b02761
--- /dev/null
+++ b/runtime/neurun/sample/minimal/CMakeLists.txt
@@ -0,0 +1,10 @@
+if(NOT BUILD_MINIMAL_SAMPLE)
+  return()
+endif(NOT BUILD_MINIMAL_SAMPLE)
+
+list(APPEND MINIMAL_SRCS "src/minimal.cc")
+
+add_executable(minimal ${MINIMAL_SRCS})
+target_link_libraries(minimal nnfw-dev pthread dl)
+
+install(TARGETS minimal DESTINATION bin)
diff --git a/runtime/neurun/sample/minimal/README.md b/runtime/neurun/sample/minimal/README.md
new file mode 100644
index 000000000..fecad6fb2
--- /dev/null
+++ b/runtime/neurun/sample/minimal/README.md
@@ -0,0 +1,13 @@
+# minimal
+
+`minimal` is a simple driver to run `nnpackage` with nnfw API.
+
+It takes `nnpackage` as input. It uses **nnfwAPI** internally.
+
+It assumes model of float32 tensor type as an input.
+
+## Usage
+
+```
+$ ./minimal path_to_nnpackage_directory
+```
diff --git a/runtime/neurun/sample/minimal/src/minimal.cc b/runtime/neurun/sample/minimal/src/minimal.cc
new file mode 100644
index 000000000..003c8a323
--- /dev/null
+++ b/runtime/neurun/sample/minimal/src/minimal.cc
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "nnfw.h"
+#include <vector>
+
+uint64_t num_elems(const nnfw_tensorinfo *ti)
+{
+  uint64_t n = 1;
+  for (uint32_t i = 0; i < ti->rank; ++i)
+  {
+    n *= ti->dims[i];
+  }
+  return n;
+}
+
+int main(const int argc, char **argv)
+{
+  nnfw_session *session = nullptr;
+  nnfw_create_session(&session);
+
+  // Loading nnpackage
+  nnfw_load_model_from_file(session, argv[1]);
+
+  // Use acl_neon backend for CONV_2D and acl_cl for otherwise.
+  // Note that defalut backend is acl_cl
+  nnfw_set_op_backend(session, "CONV_2D", "acl_neon");
+
+  // Compile model
+  nnfw_prepare(session);
+
+  // Prepare input. Here we just allocate dummy input arrays.
+  std::vector<float> input;
+  nnfw_tensorinfo ti;
+  nnfw_input_tensorinfo(session, 0, &ti); // get first input's info
+  uint32_t input_elements = num_elems(&ti);
+  input.resize(input_elements);
+  // TODO: Please add initialization for your input.
+  nnfw_set_input(session, 0, ti.dtype, input.data(), sizeof(float) * input_elements);
+
+  // Prepare output
+  std::vector<float> output;
+  nnfw_output_tensorinfo(session, 0, &ti); // get first output's info
+  uint32_t output_elements = num_elems(&ti);
+  output.resize(output_elements);
+  nnfw_set_output(session, 0, ti.dtype, output.data(), sizeof(float) * output_elements);
+
+  // Do inference
+  nnfw_run(session);
+
+  // TODO: Please print or compare the output value in your way.
+
+  return 0;
+}
diff --git a/runtime/neurun/test/CMakeLists.txt b/runtime/neurun/test/CMakeLists.txt
new file mode 100644
index 000000000..815173937
--- /dev/null
+++ b/runtime/neurun/test/CMakeLists.txt
@@ -0,0 +1,15 @@
+set(TEST_NEURUN test_neurun)
+
+file(GLOB_RECURSE TESTS "*.cc")
+
+add_executable(${TEST_NEURUN} ${TESTS})
+
+target_include_directories(${TEST_NEURUN} PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/../core/src)
+
+target_link_libraries(${TEST_NEURUN} neurun_core)
+target_link_libraries(${TEST_NEURUN} gtest)
+target_link_libraries(${TEST_NEURUN} gtest_main)
+target_link_libraries(${TEST_NEURUN} ${LIB_PTHREAD} dl)
+add_test(${TEST_NEURUN} ${TEST_NEURUN})
+
+install(TARGETS ${TEST_NEURUN} DESTINATION unittest)
diff --git a/runtime/neurun/test/core/backend/ExecTime.test.cc b/runtime/neurun/test/core/backend/ExecTime.test.cc
new file mode 100644
index 000000000..4b89e64d2
--- /dev/null
+++ b/runtime/neurun/test/core/backend/ExecTime.test.cc
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "backend/ExecTime.h"
+#include "backend/IConfig.h"
+#include "backend/Backend.h"
+#include <gtest/gtest.h>
+#include <string>
+
+namespace
+{
+using namespace neurun;
+using namespace backend;
+
+struct MockConfig : public IConfig
+{
+  std::string id() override { return "b1"; }
+  bool initialize() override { return true; };
+  bool SupportPermutation() override { return false; }
+  bool SupportSubTensorAlloc() override { return false; }
+};
+
+struct MockBackend : public ::neurun::backend::Backend
+{
+  std::shared_ptr<neurun::backend::IConfig> config() const override
+  {
+    return std::make_shared<MockConfig>();
+  }
+  std::unique_ptr<BackendContext>
+  newContext(const ir::Operands &, const std::shared_ptr<custom::IKernelBuilder> &kb) const override
+  {
+    return nullptr;
+  }
+};
+
+TEST(ExecTime, roundtrip_ok)
+{
+  const auto *b = new MockBackend();
+  std::vector<const Backend *> bs = {b};
+  {
+    ExecTime et(bs);
+    et.updateOperationExecTime(b, "op1", true, 100, 100);
+    et.updateOperationExecTime(b, "op1", true, 200, 200);
+    et.updateOperationExecTime(b, "op1", false, 100, 888);
+    et.uploadOperationsExecTime();
+  }
+  {
+    ExecTime et(bs);
+    auto time = et.getOperationExecTime(b, "op1", true, 100);
+    ASSERT_EQ(time, 100);
+    // Check interpolation
+    time = et.getOperationExecTime(b, "op1", true, 150);
+    ASSERT_EQ(time, 150);
+    time = et.getOperationExecTime(b, "op1", false, 100);
+    ASSERT_EQ(time, 888);
+    et.uploadOperationsExecTime();
+  }
+  // clean up
+  EXPECT_EQ(remove("exec_time.json"), 0);
+}
+
+TEST(ExecTime, structure)
+{
+
+  const auto *b = new MockBackend();
+  std::vector<const Backend *> bs = {b};
+  {
+    ExecTime et(bs);
+    et.updateOperationExecTime(b, "op1", true, 100, 100);
+    et.updateOperationExecTime(b, "op1", true, 200, 200);
+    et.uploadOperationsExecTime();
+  }
+  {
+    ExecTime et(bs);
+    auto time = et.getOperationExecTime(b, "op1", true, 100);
+    ASSERT_EQ(time, 100);
+    // Check interpolation
+    time = et.getOperationExecTime(b, "op1", true, 200);
+    ASSERT_EQ(time, 200);
+    et.uploadOperationsExecTime();
+  }
+  // clean up
+  EXPECT_EQ(remove("exec_time.json"), 0);
+}
+} // unnamed namespace
diff --git a/runtime/neurun/test/core/compiler/Scheduler.cc b/runtime/neurun/test/core/compiler/Scheduler.cc
new file mode 100644
index 000000000..a4fbfeb2c
--- /dev/null
+++ b/runtime/neurun/test/core/compiler/Scheduler.cc
@@ -0,0 +1,550 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <compiler/HEScheduler.h>
+#include <backend/ExecTime.h>
+#include <backend/IShapeFixer.h>
+
+#include <ir/Shape.h>
+#include <ir/InternalType.h>
+#include <ir/TypeInfo.h>
+#include <ir/DataType.h>
+
+#include <ir/operation/Add.h>
+#include <ir/operation/Sub.h>
+#include <ir/operation/Mul.h>
+#include <ir/operation/FullyConnected.h>
+
+#include <gtest/gtest.h>
+
+namespace
+{
+using namespace neurun;
+using namespace ir;
+using namespace backend;
+using namespace operation;
+
+//
+// Mock backends classes
+//
+
+// Backend could be created without ShapeFixer.
+// But it is used by scheduler to detect which operations are supported by backend.
+struct MockShapeFixer : IShapeFixer
+{
+  void visit(const Add &) override {}
+  void visit(const Sub &) override {}
+  void visit(const Mul &) override {}
+  void visit(const FullyConnected &) override {}
+};
+
+struct MockConfigCPU : public IConfig
+{
+  std::string id() override { return "cpu"; }
+  bool initialize() override { return true; };
+  bool SupportPermutation() override { return false; }
+  bool SupportSubTensorAlloc() override { return false; }
+};
+
+struct MockBackendCPU : public Backend
+{
+  std::shared_ptr<IConfig> config() const override { return std::make_shared<MockConfigCPU>(); }
+  std::unique_ptr<BackendContext>
+  newContext(const Operands &, const std::shared_ptr<custom::IKernelBuilder> &) const override
+  {
+    return std::unique_ptr<BackendContext>(
+        new BackendContext{this, nullptr, nullptr, nullptr, std::make_shared<MockShapeFixer>()});
+  }
+};
+
+struct MockConfigGPU : public IConfig
+{
+  std::string id() override { return "gpu"; }
+  bool initialize() override { return true; };
+  bool SupportPermutation() override { return false; }
+  bool SupportSubTensorAlloc() override { return false; }
+};
+
+struct MockBackendGPU : public Backend
+{
+  std::shared_ptr<IConfig> config() const override { return std::make_shared<MockConfigGPU>(); }
+  std::unique_ptr<BackendContext>
+  newContext(const Operands &, const std::shared_ptr<custom::IKernelBuilder> &) const override
+  {
+    return std::unique_ptr<BackendContext>(
+        new BackendContext{this, nullptr, nullptr, nullptr, std::make_shared<MockShapeFixer>()});
+  }
+};
+
+struct MockConfigNPU : public IConfig
+{
+  std::string id() override { return "npu"; }
+  bool initialize() override { return true; };
+  bool SupportPermutation() override { return false; }
+  bool SupportSubTensorAlloc() override { return false; }
+};
+
+struct MockBackendNPU : public Backend
+{
+  std::shared_ptr<IConfig> config() const override { return std::make_shared<MockConfigNPU>(); }
+  std::unique_ptr<BackendContext>
+  newContext(const Operands &, const std::shared_ptr<custom::IKernelBuilder> &) const override
+  {
+    return std::unique_ptr<BackendContext>(
+        new BackendContext{this, nullptr, nullptr, nullptr, std::make_shared<MockShapeFixer>()});
+  }
+};
+
+//
+// Constants
+//
+
+const int OPERAND_ELEMS = 268203;
+const int OPERAND_SIZE = OPERAND_ELEMS * 4;
+const int OPERATION_SIZE = OPERAND_SIZE * 3;
+
+const std::string LINEAR("Linear");
+const std::string DATAFLOW("Dataflow");
+const std::string PARALLEL("Parallel");
+
+//
+// Helper functions
+//
+
+// Set executor through environment variable
+void setExecutor(const std::string &executor) { setenv("EXECUTOR", executor.c_str(), true); }
+
+// Set profiling mode through environment variable
+void setProfilingMode(const bool value) { setenv("PROFILING_MODE", value ? "1" : "0", true); }
+
+// Calculate operation size by addition sizes of all input and output operands
+uint32_t calcOpSize(const std::shared_ptr<Graph> &graph, const OperationIndex &op_idx)
+{
+  uint32_t size = 0;
+  for (const auto &input : graph->operations().at(op_idx).getInputs())
+    size += graph->operands().at(input).info().total_size();
+  for (const auto &output : graph->operations().at(op_idx).getOutputs())
+    size += graph->operands().at(output).info().total_size();
+  return size;
+}
+
+// Set execution operation time. This method is needed since ExecutionTime has only
+// 'updateOperationExecTime' method.
+void setOperationExecTime(ExecTime &et, const Backend *backend, const std::string &operation,
+                          bool quant, uint32_t op_size, int64_t time)
+{
+  // You shouldn't set negative time with this method since nnfw JSON deserializer can't read it
+  assert(time > 0);
+  int64_t prev_time = et.getOperationExecTime(backend, operation, quant, op_size);
+  int64_t time_to_set = prev_time == ExecTime::NOT_FOUND ? time : 2 * time - prev_time;
+  et.updateOperationExecTime(backend, operation, quant, op_size, time_to_set);
+  assert(et.getOperationExecTime(backend, operation, quant, op_size) == time);
+}
+
+// Set same execution time for all given backends/operations
+void setOperationsExecutionTime(const std::vector<const Backend *> &backends,
+                                const std::vector<std::string> &op_names,
+                                const std::vector<uint32_t> &op_sizes, int64_t exec_time)
+{
+  assert(op_names.size() == op_sizes.size());
+  ExecTime et(backends);
+  for (int i = 0; i < op_names.size(); ++i)
+  {
+    for (auto &backend : backends)
+      setOperationExecTime(et, backend, op_names[i], false, op_sizes[i], exec_time);
+  }
+  et.uploadOperationsExecTime();
+}
+
+// Set permute time from one backend to another. This method is needed since ExecutionTime has only
+// 'updatePermuteTime' method.
+void setPermutationTime(ExecTime &et, const Backend *from_backend, const Backend *to_backend,
+                        bool quant, uint32_t op_size, int64_t time)
+{
+  // You shouldn't set negative time with this method since nnfw JSON deserializer can't read it
+  assert(time > 0);
+  int64_t prev_time = et.getPermuteTime(from_backend, to_backend, quant, op_size);
+  int64_t time_to_set = prev_time == ExecTime::NOT_FOUND ? time : 2 * time - prev_time;
+  et.updatePermuteTime(from_backend, to_backend, quant, op_size, time_to_set);
+  assert(et.getPermuteTime(from_backend, to_backend, quant, op_size) == time);
+}
+
+// Set same permutation time between all given backends
+void setPermutationsExecutionTime(const std::vector<const Backend *> &backends,
+                                  const int operand_size, const int64_t exec_time)
+{
+  ExecTime et(backends);
+  for (const auto &backend : backends)
+  {
+    for (auto &other_backend : backends)
+    {
+      if (backend == other_backend)
+        continue;
+      setPermutationTime(et, backend, other_backend, false, operand_size, exec_time);
+    }
+  }
+  et.uploadOperationsExecTime();
+}
+
+//
+// Functions for creating graphs
+//
+
+using OIS = OperandIndexSequence;
+
+template <typename NodeT, typename... Types>
+OperationIndex create(std::shared_ptr<Graph> graph, Types &&... args)
+{
+  typename NodeT::Param op_params{Activation::NONE};
+  auto op = nnfw::cpp14::make_unique<NodeT>(std::forward<Types>(args)..., op_params);
+  auto op_idx = graph->addOperation(std::move(op));
+  // For now in scheduler test all operations in tested graphs has same size (for simplicity)
+  assert(calcOpSize(graph, op_idx) == OPERATION_SIZE);
+  return op_idx;
+}
+
+// Create straight graph: Add->Sub->Mul
+std::shared_ptr<Graph> createStraightGraph()
+{
+  auto graph = std::make_shared<Graph>();
+  const TypeInfo float_op(DataType::FLOAT32);
+
+  // Create add node
+  auto add_lhs_idx = graph->addOperand(Shape{OPERAND_ELEMS}, float_op);
+  auto add_rhs_idx = graph->addOperand(Shape{OPERAND_ELEMS}, float_op);
+  auto add_out_idx = graph->addOperand(Shape{OPERAND_ELEMS}, float_op);
+  create<Add>(graph, OIS{add_lhs_idx, add_rhs_idx}, OIS{add_out_idx});
+
+  // Create sub node
+  auto sub_const_idx = graph->addOperand(Shape{OPERAND_ELEMS}, float_op);
+  auto sub_out_idx = graph->addOperand(Shape{OPERAND_ELEMS}, float_op);
+  create<Sub>(graph, OIS{add_out_idx, sub_const_idx}, OIS{sub_out_idx});
+
+  // Create mul node
+  auto mul_const_idx = graph->addOperand(Shape{OPERAND_ELEMS}, float_op);
+  auto mul_out_idx = graph->addOperand(Shape{OPERAND_ELEMS}, float_op);
+  create<Mul>(graph, OIS{sub_out_idx, mul_const_idx}, OIS{mul_out_idx});
+
+  graph->finishBuilding();
+  return graph;
+}
+
+/* Create branched graph:
+ *       [Add]
+ *      //   \\
+ *   [Mul1]  [FC2]
+ *     ||     ||
+ *   [Mul2]  [FC2]
+ *      \\   //
+ *       [Sub]
+ */
+std::shared_ptr<Graph> createBranchedGraph()
+{
+  auto graph = std::make_shared<Graph>();
+  const TypeInfo float_op(DataType::FLOAT32);
+
+  // Create add node
+  auto add_lhs_idx = graph->addOperand(Shape{OPERAND_ELEMS}, float_op);
+  auto add_rhs_idx = graph->addOperand(Shape{OPERAND_ELEMS}, float_op);
+  auto add_out_idx = graph->addOperand(Shape{OPERAND_ELEMS}, float_op);
+  create<Add>(graph, OIS{add_lhs_idx, add_rhs_idx}, OIS{add_out_idx});
+
+  // Create mul1 node
+  auto mul1_const_idx = graph->addOperand(Shape{OPERAND_ELEMS}, float_op);
+  auto mul1_out_idx = graph->addOperand(Shape{OPERAND_ELEMS}, float_op);
+  create<Mul>(graph, OIS{add_out_idx, mul1_const_idx}, OIS{mul1_out_idx});
+
+  // Create mul2 node
+  auto mul2_const_idx = graph->addOperand(Shape{OPERAND_ELEMS}, float_op);
+  auto mul2_out_idx = graph->addOperand(Shape{OPERAND_ELEMS}, float_op);
+  create<Mul>(graph, OIS{mul1_out_idx, mul2_const_idx}, OIS{mul2_out_idx});
+
+  // Create fc1 node
+  auto fc1_const_idx = graph->addOperand(Shape{OPERAND_ELEMS}, float_op);
+  auto fc1_out_idx = graph->addOperand(Shape{OPERAND_ELEMS}, float_op);
+  create<FullyConnected>(graph, OIS{add_out_idx, fc1_const_idx}, OIS{fc1_out_idx});
+
+  // Create fc2 node
+  auto fc2_const_idx = graph->addOperand(Shape{OPERAND_ELEMS}, float_op);
+  auto fc2_out_idx = graph->addOperand(Shape{OPERAND_ELEMS}, float_op);
+  create<FullyConnected>(graph, OIS{fc1_out_idx, fc2_const_idx}, OIS{fc2_out_idx});
+
+  // Create add2 node
+  auto sub_out_idx = graph->addOperand(Shape{OPERAND_ELEMS}, float_op);
+  create<Sub>(graph, OIS{mul2_out_idx, fc2_out_idx}, OIS{sub_out_idx});
+
+  graph->finishBuilding();
+  return graph;
+}
+
+//
+// Tests setup/teardown
+//
+
+// SetUp/TearDown methods runs before/after each test and performs actions common for each test
+class SchedulerTest : public ::testing::Test
+{
+protected:
+  void SetUp() override
+  {
+    // Initialize mock backends
+    _cpu_backend = new MockBackendCPU();
+    _gpu_backend = new MockBackendGPU();
+    _npu_backend = new MockBackendNPU();
+    _mock_backends = {_cpu_backend, _gpu_backend, _npu_backend};
+
+    // Remove previous profile data if it exists
+    if (!remove("exec_time.json"))
+    {
+      // DO NOTHING (no profile data)
+    }
+
+    // Remember original value of 'EXECUTOR' environment variable
+    char *executor = std::getenv("EXECUTOR");
+    _original_executor = executor == nullptr ? "" : executor;
+
+    // Remember original value of 'PROFILING_MODE' environment variable
+    char *profiling_mode = std::getenv("PROFILING_MODE");
+    _original_profiling_mode = profiling_mode == nullptr ? "" : profiling_mode;
+  }
+
+  void TearDown() override
+  {
+    delete _cpu_backend;
+    delete _gpu_backend;
+    delete _npu_backend;
+    EXPECT_EQ(remove("exec_time.json"), 0);
+    setenv("EXECUTOR", _original_executor.c_str(), true);
+    setenv("PROFILING_MODE", _original_profiling_mode.c_str(), true);
+  }
+
+  const MockBackendCPU *_cpu_backend{nullptr};
+  const MockBackendGPU *_gpu_backend{nullptr};
+  const MockBackendNPU *_npu_backend{nullptr};
+  std::vector<const Backend *> _mock_backends;
+
+  std::string _original_executor;
+  std::string _original_profiling_mode;
+};
+
+class SchedulerTestWithExecutorParam : public SchedulerTest,
+                                       public testing::WithParamInterface<std::string>
+{
+};
+
+//
+// HEScheduler tests
+//
+
+// Test scheduler behavior for straight graph with known execution time of all nodes and permutes.
+TEST_P(SchedulerTestWithExecutorParam, straight_graph_known_exec_time)
+{
+  setExecutor(GetParam());
+
+  // Prepare graph
+  auto graph(createStraightGraph());
+  OperationIndex add_op_idx(0), sub_op_idx(1), mul_op_idx(2);
+
+  // Set default execution and transfer time
+  setPermutationsExecutionTime(_mock_backends, OPERAND_SIZE, 1);
+  setOperationsExecutionTime(_mock_backends, {"Add", "Sub", "Mul"},
+                             {OPERATION_SIZE, OPERATION_SIZE, OPERATION_SIZE}, 1e4);
+
+  // Test 1
+  // Expected behaviour: scheduler assigns different backend to each node
+  {
+    // For each backend reduce execution time of one node
+    ExecTime et(_mock_backends);
+    setOperationExecTime(et, _cpu_backend, "Add", false, OPERATION_SIZE, 1);
+    setOperationExecTime(et, _gpu_backend, "Sub", false, OPERATION_SIZE, 1);
+    setOperationExecTime(et, _npu_backend, "Mul", false, OPERATION_SIZE, 1);
+    et.uploadOperationsExecTime();
+
+    // Test scheduler
+    auto scheduler = compiler::HEScheduler(graph->operands(), _mock_backends, nullptr);
+    const auto br = scheduler.schedule(*graph);
+    ASSERT_EQ(br->getBackend(add_op_idx)->config()->id(), "cpu");
+    ASSERT_EQ(br->getBackend(sub_op_idx)->config()->id(), "gpu");
+    ASSERT_EQ(br->getBackend(mul_op_idx)->config()->id(), "npu");
+  }
+
+  // Test 2
+  // Expected behaviour: scheduler assigns single backend to all nodes because of big transfer time
+  {
+    // Increase transfer time
+    setPermutationsExecutionTime(_mock_backends, OPERAND_SIZE, 1e5);
+
+    // Test scheduler
+    auto scheduler = compiler::HEScheduler(graph->operands(), _mock_backends, nullptr);
+    const auto br = scheduler.schedule(*graph);
+    ASSERT_EQ(br->getBackend(add_op_idx)->config()->id(), "cpu");
+    ASSERT_EQ(br->getBackend(sub_op_idx)->config()->id(), "cpu");
+    ASSERT_EQ(br->getBackend(mul_op_idx)->config()->id(), "cpu");
+  }
+}
+
+// Test scheduler behavior for branched graph with known execution time of all nodes and permutes
+TEST_P(SchedulerTestWithExecutorParam, branched_graph_known_exec_time)
+{
+  const int64_t NPU_ET = 5000;
+  setExecutor(GetParam());
+
+  // Prepare graph
+  auto graph(createBranchedGraph());
+  OperationIndex add_op_idx(0), mul1_op_idx(1), mul2_op_idx(2), fc1_op_idx(3), fc2_op_idx(4),
+      sub_op_idx(5);
+
+  // Set default execution and transfer time
+  setPermutationsExecutionTime(_mock_backends, OPERAND_SIZE, 1000);
+  setOperationsExecutionTime(_mock_backends, {"Add", "Sub", "Mul", "FullyConnected"},
+                             {OPERATION_SIZE, OPERATION_SIZE, OPERATION_SIZE, OPERATION_SIZE}, 1e4);
+
+  // Test 1
+  // Expected behaviour: for dataflow and linear executors scheduler assigns fastest backend to all
+  // nodes, in case of parallel executor scheduler assigns different backends to branches.
+  {
+    // Reduce execution time
+    ExecTime et(_mock_backends);
+    setOperationExecTime(et, _npu_backend, "Add", false, OPERATION_SIZE, NPU_ET);
+    setOperationExecTime(et, _npu_backend, "Mul", false, OPERATION_SIZE, NPU_ET);
+    setOperationExecTime(et, _npu_backend, "Sub", false, OPERATION_SIZE, NPU_ET);
+    setOperationExecTime(et, _npu_backend, "FullyConnected", false, OPERATION_SIZE, NPU_ET);
+    setOperationExecTime(et, _gpu_backend, "Mul", false, OPERATION_SIZE, NPU_ET + 1000);
+    setOperationExecTime(et, _gpu_backend, "FullyConnected", false, OPERATION_SIZE, NPU_ET + 1000);
+    et.uploadOperationsExecTime();
+
+    // Test scheduler
+    auto scheduler = compiler::HEScheduler(graph->operands(), _mock_backends, nullptr);
+    const auto br = scheduler.schedule(*graph);
+
+    std::string branch1_expected_backend("npu"), branch2_expected_backend("npu");
+    if (GetParam() == PARALLEL)
+    {
+      branch1_expected_backend =
+          br->getBackend(mul1_op_idx)->config()->id() == "npu" ? "npu" : "gpu";
+      branch2_expected_backend = branch1_expected_backend == "npu" ? "gpu" : "npu";
+    }
+
+    ASSERT_EQ(br->getBackend(add_op_idx)->config()->id(), "npu");
+    ASSERT_EQ(br->getBackend(mul1_op_idx)->config()->id(), branch1_expected_backend);
+    ASSERT_EQ(br->getBackend(mul2_op_idx)->config()->id(), branch1_expected_backend);
+    ASSERT_EQ(br->getBackend(fc1_op_idx)->config()->id(), branch2_expected_backend);
+    ASSERT_EQ(br->getBackend(fc2_op_idx)->config()->id(), branch2_expected_backend);
+    ASSERT_EQ(br->getBackend(sub_op_idx)->config()->id(), "npu");
+  }
+
+  // Test 2
+  // Expected behaviour: scheduler assigns single backend to all nodes
+  {
+    // Increase execution time for GPU backend
+    ExecTime et(_mock_backends);
+    /* for parallel executor: set a time, that is larger than sum_of_other_branches_nodes_cnt *
+     * npu_exec_time so that npu is prefered: the ith branch will wait for npu until it finishes the
+     * [0;i-1] branches nodes in DFS order. In each branch it goes deep intul doesn't encounter
+     * branching or scheduler assigns another backend to a node*/
+    setOperationExecTime(et, _gpu_backend, "Mul", false, OPERATION_SIZE, NPU_ET * 3 + 1);
+    setOperationExecTime(et, _gpu_backend, "FullyConnected", false, OPERATION_SIZE, NPU_ET * 3 + 1);
+    et.uploadOperationsExecTime();
+
+    // Test scheduler
+    auto scheduler = compiler::HEScheduler(graph->operands(), _mock_backends, nullptr);
+    const auto br = scheduler.schedule(*graph);
+    ASSERT_EQ(br->getBackend(add_op_idx)->config()->id(), "npu");
+    ASSERT_EQ(br->getBackend(mul1_op_idx)->config()->id(), "npu");
+    ASSERT_EQ(br->getBackend(mul2_op_idx)->config()->id(), "npu");
+    ASSERT_EQ(br->getBackend(fc1_op_idx)->config()->id(), "npu");
+    ASSERT_EQ(br->getBackend(fc2_op_idx)->config()->id(), "npu");
+    ASSERT_EQ(br->getBackend(sub_op_idx)->config()->id(), "npu");
+  }
+}
+
+// SchedulerTestWithExecutorParam tests are parameterized with executor name and runs three times -
+// one time for each executor
+INSTANTIATE_TEST_CASE_P(AllExecutors, SchedulerTestWithExecutorParam,
+                        testing::Values(LINEAR, DATAFLOW, PARALLEL));
+
+// Test scheduler behavior for branched graph and enabled profiling mode
+TEST_F(SchedulerTest, branched_graph_profiling_mode)
+{
+  const int ET = 1e5;
+
+  // Turn on profiling mode
+  setProfilingMode(true);
+  setExecutor(DATAFLOW);
+
+  // Prepare graph
+  auto graph(createBranchedGraph());
+  OperationIndex add_op_idx(0), mul1_op_idx(1), mul2_op_idx(2), fc1_op_idx(3), fc2_op_idx(4),
+      sub_op_idx(5);
+
+  // Test 1
+  // Expected behaviour: scheduler assigns backends to nodes with unknown execution time
+  {
+    // Set execution time for all backends/nodes except for cpu/Sub, npu/Mul, gpu/FC
+    ExecTime et(_mock_backends);
+    setOperationExecTime(et, _cpu_backend, "Add", false, OPERATION_SIZE, ET);
+    setOperationExecTime(et, _cpu_backend, "Mul", false, OPERATION_SIZE, ET + 1);
+    setOperationExecTime(et, _cpu_backend, "FullyConnected", false, OPERATION_SIZE, ET);
+    setOperationExecTime(et, _npu_backend, "Add", false, OPERATION_SIZE, ET);
+    setOperationExecTime(et, _npu_backend, "FullyConnected", false, OPERATION_SIZE, ET);
+    setOperationExecTime(et, _npu_backend, "Sub", false, OPERATION_SIZE, ET);
+    setOperationExecTime(et, _gpu_backend, "Add", false, OPERATION_SIZE, ET);
+    setOperationExecTime(et, _gpu_backend, "Mul", false, OPERATION_SIZE, ET + 1);
+    setOperationExecTime(et, _gpu_backend, "Sub", false, OPERATION_SIZE, ET);
+    et.uploadOperationsExecTime();
+
+    // Test scheduler
+    auto scheduler = compiler::HEScheduler(graph->operands(), _mock_backends, nullptr);
+    const auto br = scheduler.schedule(*graph);
+    ASSERT_EQ(br->getBackend(mul1_op_idx)->config()->id(), "npu");
+    ASSERT_EQ(br->getBackend(mul2_op_idx)->config()->id(), "npu");
+    ASSERT_EQ(br->getBackend(fc1_op_idx)->config()->id(), "gpu");
+    ASSERT_EQ(br->getBackend(fc2_op_idx)->config()->id(), "gpu");
+    ASSERT_EQ(br->getBackend(sub_op_idx)->config()->id(), "cpu");
+  }
+
+  // Test 2
+  // Expected behaviour: scheduler shuffling backends, so different backends are assigned to
+  // neighbor nodes
+  {
+    // Set execution time for rest backends/nodes (cpu/Sub, npu/Mul, gpu/FC)
+    ExecTime et(_mock_backends);
+    setOperationExecTime(et, _cpu_backend, "Sub", false, OPERATION_SIZE, ET);
+    setOperationExecTime(et, _npu_backend, "Mul", false, OPERATION_SIZE, ET + 1);
+    setOperationExecTime(et, _gpu_backend, "FullyConnected", false, OPERATION_SIZE, ET);
+    et.uploadOperationsExecTime();
+
+    // Test scheduler
+    auto scheduler = compiler::HEScheduler(graph->operands(), _mock_backends, nullptr);
+    const auto br = scheduler.schedule(*graph);
+    ASSERT_NE(br->getBackend(add_op_idx)->config()->id(),
+              br->getBackend(mul1_op_idx)->config()->id());
+    ASSERT_NE(br->getBackend(add_op_idx)->config()->id(),
+              br->getBackend(fc1_op_idx)->config()->id());
+    ASSERT_NE(br->getBackend(mul1_op_idx)->config()->id(),
+              br->getBackend(mul2_op_idx)->config()->id());
+    ASSERT_NE(br->getBackend(fc1_op_idx)->config()->id(),
+              br->getBackend(fc2_op_idx)->config()->id());
+    ASSERT_NE(br->getBackend(mul2_op_idx)->config()->id(),
+              br->getBackend(sub_op_idx)->config()->id());
+    ASSERT_NE(br->getBackend(fc2_op_idx)->config()->id(),
+              br->getBackend(sub_op_idx)->config()->id());
+  }
+}
+
+// TODO: Add tests with unknown execution and permutation time
+
+} // unnamed namespace
diff --git a/runtime/neurun/test/core/exec/ExecInstance.cc b/runtime/neurun/test/core/exec/ExecInstance.cc
new file mode 100644
index 000000000..49d561226
--- /dev/null
+++ b/runtime/neurun/test/core/exec/ExecInstance.cc
@@ -0,0 +1,307 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <gtest/gtest.h>
+#include <thread>
+
+#include "ir/Graph.h"
+#include "compiler/Compiler.h"
+#include "exec/Execution.h"
+#include "ir/operation/Add.h"
+
+namespace
+{
+
+using namespace neurun::ir;
+
+class CompiledMockUpModel
+{
+public:
+  CompiledMockUpModel()
+  {
+    // Model: two elementwise add operation
+    // model input: lhs, rhs1
+    // model output: second add result (result2)
+    // constant: rhs2
+    // result1 <= (lhs + rhs)
+    // result2 <= (result1 + rhs2)
+    // lhs, rhs1, rh2, result1, result2 shape: {1, 2, 2, 1}
+    // activation: none (constant)
+    graph = std::make_shared<Graph>();
+    // 1st add operands (result1 <= lhs + rhs1)
+    Shape shape{1, 2, 2, 1};
+    TypeInfo type{DataType::FLOAT32};
+    static float rhs2_data[4] = {3, 1, -1, 5};
+    auto operand_lhs = graph->addOperand(shape, type);
+    auto operand_rhs1 = graph->addOperand(shape, type);
+    auto operand_result1 = graph->addOperand(shape, type);
+    auto operand_rhs2 = graph->addOperand(shape, type);
+    auto operand_result2 = graph->addOperand(shape, type);
+    graph->operands()
+        .at(operand_rhs2)
+        .data(nnfw::cpp14::make_unique<CachedData>(reinterpret_cast<const uint8_t *>(&rhs2_data),
+                                                   16));
+    // 2nd add operations (result2 <= result1 + rhs2)
+    operation::Add::Param param1;
+    param1.activation = Activation::NONE;
+    auto input_set1 = OperandIndexSequence{operand_lhs, operand_rhs1};
+    auto output_set1 = OperandIndexSequence{operand_result1};
+    graph->addOperation(nnfw::cpp14::make_unique<operation::Add>(input_set1, output_set1, param1));
+    operation::Add::Param param2;
+    param2.activation = Activation::NONE;
+    auto input_set2 = OperandIndexSequence{operand_result1, operand_rhs2};
+    auto output_set2 = OperandIndexSequence{operand_result2};
+    graph->addOperation(nnfw::cpp14::make_unique<operation::Add>(input_set2, output_set2, param2));
+    // Identify model inputs and outputs
+    graph->addInput(operand_lhs);
+    graph->addInput(operand_rhs1);
+    graph->addOutput(operand_result2);
+    graph->finishBuilding();
+
+    // Compile
+    auto compiler = new neurun::compiler::Compiler{graph};
+    compiler->compile();
+    compiler->release(executor);
+    delete compiler;
+  }
+
+public:
+  std::shared_ptr<Graph> graph;
+  std::shared_ptr<neurun::exec::IExecutor> executor;
+};
+
+TEST(ExecInstance, simple)
+{
+  auto mockup = CompiledMockUpModel();
+  auto graph = mockup.graph;
+  auto executor = mockup.executor;
+
+  auto input1 = IOIndex{0};
+  auto input2 = IOIndex{1};
+  auto output = IOIndex{0};
+
+  const float input1_buffer[4] = {1, 0, -1, -2};
+  const float input2_buffer[4] = {1, -3, 2, -4};
+  float output_buffer[4] = {};
+  const float output_expected[4] = {5, -2, 0, -1};
+
+  auto execution = new neurun::exec::Execution(executor);
+
+  execution->setInput(input1, reinterpret_cast<const void *>(input1_buffer), 16);
+  execution->setInput(input2, reinterpret_cast<const void *>(input2_buffer), 16);
+  execution->setOutput(output, reinterpret_cast<void *>(output_buffer), 16);
+  execution->execute();
+
+  for (auto i = 0; i < 4; i++)
+  {
+    EXPECT_EQ(output_buffer[i], output_expected[i]);
+  }
+
+  delete execution;
+}
+
+TEST(ExecInstance, twoCompile)
+{
+  auto mockup = CompiledMockUpModel();
+  auto graph = mockup.graph;
+  auto executor1 = mockup.executor;
+  auto execution1 = new neurun::exec::Execution(executor1);
+
+  auto input1 = IOIndex{0};
+  auto input2 = IOIndex{1};
+  auto output = IOIndex{0};
+
+  const float exe1_input1_buffer[4] = {1, 0, -1, -2};
+  const float exe1_input2_buffer[4] = {1, -3, 2, -4};
+  float exe1_output_buffer[4] = {};
+  const float exe1_output_expected[4] = {5, -2, 0, -1};
+
+  execution1->setInput(input1, reinterpret_cast<const void *>(exe1_input1_buffer), 16);
+  execution1->setInput(input2, reinterpret_cast<const void *>(exe1_input2_buffer), 16);
+  execution1->setOutput(output, reinterpret_cast<void *>(exe1_output_buffer), 16);
+
+  // Make new executor: compile again
+  auto compiler = new neurun::compiler::Compiler{graph};
+  compiler->compile();
+  std::shared_ptr<neurun::exec::IExecutor> executor2;
+  compiler->release(executor2);
+  auto execution2 = new neurun::exec::Execution(executor2);
+
+  const float exe2_input1_buffer[4] = {2, 1, -2, 0};
+  const float exe2_input2_buffer[4] = {-3, 3, 1, 2};
+  float exe2_output_buffer[4] = {};
+  const float exe2_output_expected[4] = {2, 5, -2, 7};
+
+  execution2->setInput(input1, reinterpret_cast<const void *>(exe2_input1_buffer), 16);
+  execution2->setInput(input2, reinterpret_cast<const void *>(exe2_input2_buffer), 16);
+  execution2->setOutput(output, reinterpret_cast<void *>(exe2_output_buffer), 16);
+
+  execution1->execute();
+  execution2->execute();
+
+  for (auto i = 0; i < 4; i++)
+  {
+    EXPECT_EQ(exe1_output_buffer[i], exe1_output_expected[i]);
+    EXPECT_EQ(exe2_output_buffer[i], exe2_output_expected[i]);
+  }
+
+  delete compiler;
+  delete execution1;
+  delete execution2;
+}
+
+// Support two initialized execution instance then ordered execution
+TEST(ExecInstance, twoExecution)
+{
+  auto mockup = CompiledMockUpModel();
+  auto executor = mockup.executor;
+  auto input1 = IOIndex{0};
+  auto input2 = IOIndex{1};
+  auto output1 = IOIndex{0};
+
+  const float exe1_input1_buffer[4] = {1, 0, -1, -2};
+  const float exe1_input2_buffer[4] = {1, -3, 2, -4};
+  float exe1_output_buffer[4] = {};
+  const float exe1_output_expected[4] = {5, -2, 0, -1};
+  const float exe2_output_expected[4] = {2, 5, -2, 7};
+
+  auto execution1 = new neurun::exec::Execution(executor);
+  execution1->setInput(input1, reinterpret_cast<const void *>(exe1_input1_buffer), 16);
+  execution1->setInput(input2, reinterpret_cast<const void *>(exe1_input2_buffer), 16);
+  execution1->setOutput(output1, reinterpret_cast<void *>(exe1_output_buffer), 16);
+
+  const float exe2_input1_buffer[4] = {2, 1, -2, 0};
+  const float exe2_input2_buffer[4] = {-3, 3, 1, 2};
+  float exe2_output_buffer[4] = {};
+
+  // Make new execution
+  auto execution2 = new neurun::exec::Execution(executor);
+  execution2->setInput(input1, reinterpret_cast<const void *>(exe2_input1_buffer), 16);
+  execution2->setInput(input2, reinterpret_cast<const void *>(exe2_input2_buffer), 16);
+  execution2->setOutput(output1, reinterpret_cast<void *>(exe2_output_buffer), 16);
+
+  execution1->execute();
+  execution2->execute();
+
+  for (auto i = 0; i < 4; i++)
+  {
+    EXPECT_EQ(exe1_output_buffer[i], exe1_output_expected[i]);
+    EXPECT_EQ(exe2_output_buffer[i], exe2_output_expected[i]);
+  }
+
+  delete execution1;
+  delete execution2;
+}
+
+class Inference
+{
+public:
+  Inference(const float (&input1)[4], const float (&input2)[4], float (&output)[4],
+            std::shared_ptr<neurun::exec::IExecutor> &executor)
+      : _input1{input1}, _input2{input2}, _output{output}, _executor{executor}
+  {
+    // DO NOTHING
+  }
+
+  void inference(void)
+  {
+    auto input1 = IOIndex{0};
+    auto input2 = IOIndex{1};
+    auto output1 = IOIndex{0};
+
+    auto execution = new neurun::exec::Execution(_executor);
+    execution->setInput(input1, reinterpret_cast<const void *>(_input1), 16);
+    execution->setInput(input2, reinterpret_cast<const void *>(_input2), 16);
+    execution->setOutput(output1, reinterpret_cast<void *>(_output), 16);
+
+    execution->execute();
+
+    delete execution;
+  }
+
+private:
+  const float (&_input1)[4];
+  const float (&_input2)[4];
+  float (&_output)[4];
+  std::shared_ptr<neurun::exec::IExecutor> &_executor;
+};
+
+// Support multi-thread execution
+TEST(ExecInstance, twoThreads)
+{
+  auto mockup = CompiledMockUpModel();
+  auto executor = mockup.executor;
+
+  const float exe1_input1_buffer[4] = {1, 0, -1, -2};
+  const float exe1_input2_buffer[4] = {1, -3, 2, -4};
+  float exe1_output_buffer[4] = {};
+  const float exe1_output_expected[4] = {5, -2, 0, -1};
+
+  Inference execution1{exe1_input1_buffer, exe1_input2_buffer, exe1_output_buffer, executor};
+
+  const float exe2_input1_buffer[4] = {2, 1, -2, 0};
+  const float exe2_input2_buffer[4] = {-3, 3, 1, 2};
+  float exe2_output_buffer[4] = {};
+  const float exe2_output_expected[4] = {2, 5, -2, 7};
+
+  Inference execution2{exe2_input1_buffer, exe2_input2_buffer, exe2_output_buffer, executor};
+
+  std::thread t1{&Inference::inference, &execution1};
+  std::thread t2{&Inference::inference, &execution2};
+
+  t1.join();
+  t2.join();
+
+  for (auto i = 0; i < 4; i++)
+  {
+    EXPECT_EQ(exe1_output_buffer[i], exe1_output_expected[i]);
+    EXPECT_EQ(exe2_output_buffer[i], exe2_output_expected[i]);
+  }
+}
+
+// Support asynchronous execution
+TEST(ExecInstance, async)
+{
+  auto mockup = CompiledMockUpModel();
+  auto graph = mockup.graph;
+  auto executor = mockup.executor;
+
+  auto input1 = IOIndex{0};
+  auto input2 = IOIndex{1};
+  auto output = IOIndex{0};
+
+  const float input1_buffer[4] = {1, 0, -1, -2};
+  const float input2_buffer[4] = {1, -3, 2, -4};
+  float output_buffer[4] = {};
+  const float output_expected[4] = {5, -2, 0, -1};
+
+  auto execution = new neurun::exec::Execution(executor);
+
+  execution->setInput(input1, reinterpret_cast<const void *>(input1_buffer), 16);
+  execution->setInput(input2, reinterpret_cast<const void *>(input2_buffer), 16);
+  execution->setOutput(output, reinterpret_cast<void *>(output_buffer), 16);
+  execution->startExecute();
+  execution->waitFinish();
+
+  for (auto i = 0; i < 4; i++)
+  {
+    EXPECT_EQ(output_buffer[i], output_expected[i]);
+  }
+
+  delete execution;
+}
+
+} // namespace
diff --git a/runtime/neurun/test/core/exec/interp/ExecManager.cc b/runtime/neurun/test/core/exec/interp/ExecManager.cc
new file mode 100644
index 000000000..aba64e28f
--- /dev/null
+++ b/runtime/neurun/test/core/exec/interp/ExecManager.cc
@@ -0,0 +1,334 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <gtest/gtest.h>
+
+#include <cpp14/memory.h>
+
+#include "ir/Graph.h"
+#include "exec/interp/ExecManager.h"
+#include "exec/Execution.h"
+#include "ir/operation/Add.h"
+
+namespace
+{
+
+using namespace neurun::ir;
+using ExecManager = neurun::exec::interp::ExecManager;
+using Execution = neurun::exec::Execution;
+
+class InterpExecManagerTest : public ::testing::Test
+{
+protected:
+  virtual void SetUp() {}
+  void CreateSimpleModel()
+  {
+    // Model: one elementwise add operation
+    // model input: lhs, rhs
+    // model output: add result
+    // lhs, rhs, result shape: {1, 2, 2, 1}
+    // activation: none (constant)
+    _graph = nnfw::cpp14::make_unique<Graph>();
+
+    // Add operands
+
+    Shape shape{1, 2, 2, 1};
+    TypeInfo type{DataType::INT32};
+    Shape shape_scalar(0);
+    TypeInfo type_scalar{DataType::INT32};
+
+    auto operand_lhs = _graph->addOperand(shape, type);
+    auto operand_rhs = _graph->addOperand(shape, type);
+    auto operand_result = _graph->addOperand(shape, type);
+
+    // Add operations
+
+    operation::Add::Param param;
+    param.activation = Activation::NONE;
+    auto input_set = OperandIndexSequence{operand_lhs, operand_rhs};
+    auto output_set = OperandIndexSequence{operand_result};
+    _graph->addOperation(nnfw::cpp14::make_unique<operation::Add>(input_set, output_set, param));
+
+    // Identify model inputs and outputs
+
+    _graph->getInputs().append(operand_lhs);
+    _graph->getInputs().append(operand_rhs);
+    _graph->getOutputs().append(operand_result);
+
+    _graph->finishBuilding();
+
+    _executor = nnfw::cpp14::make_unique<ExecManager>(*_graph);
+  }
+
+  void CreateTwoStepModel()
+  {
+    // Model: two elementwise add operation
+    // model input: lhs, rhs1
+    // model output: second add result (result2)
+    // constant: rhs2
+    // result1 <= (lhs + rhs)
+    // result2 <= (result1 + rhs2)
+    // lhs, rhs1, rh2, result1, result2 shape: {1, 2, 2, 1}
+    // activation: none (constant)
+    _graph = nnfw::cpp14::make_unique<Graph>();
+
+    // 1st add operands (result1 <= lhs + rhs1)
+
+    Shape shape{1, 2, 2, 1};
+    TypeInfo type{DataType::INT32};
+    Shape shape_scalar(0);
+    TypeInfo type_scalar{DataType::INT32};
+
+    static int32_t rhs2_data[4] = {3, 1, -1, 5};
+
+    auto operand_lhs = _graph->addOperand(shape, type);
+    auto operand_rhs1 = _graph->addOperand(shape, type);
+    auto operand_result1 = _graph->addOperand(shape, type);
+    auto operand_rhs2 = _graph->addOperand(shape, type);
+    auto operand_result2 = _graph->addOperand(shape, type);
+    _graph->operands()
+        .at(operand_rhs2)
+        .data(nnfw::cpp14::make_unique<CachedData>(reinterpret_cast<const uint8_t *>(&rhs2_data),
+                                                   16));
+
+    // 2nd add operations (result2 <= result1 + rhs2)
+
+    operation::Add::Param param1;
+    param1.activation = Activation::NONE;
+    auto input_set1 = OperandIndexSequence{operand_lhs, operand_rhs1};
+    auto output_set1 = OperandIndexSequence{operand_result1};
+    _graph->addOperation(nnfw::cpp14::make_unique<operation::Add>(input_set1, output_set1, param1));
+
+    operation::Add::Param param2;
+    param2.activation = Activation::NONE;
+    auto input_set2 = OperandIndexSequence{operand_result1, operand_rhs2};
+    auto output_set2 = OperandIndexSequence{operand_result2};
+    _graph->addOperation(nnfw::cpp14::make_unique<operation::Add>(input_set2, output_set2, param2));
+
+    // Identify model inputs and outputs
+
+    _graph->getInputs().append(operand_lhs);
+    _graph->getInputs().append(operand_rhs1);
+    _graph->getOutputs().append(operand_result2);
+
+    _graph->finishBuilding();
+
+    _executor = nnfw::cpp14::make_unique<ExecManager>(*_graph);
+  }
+
+  void CreateUnspecifiedDimensionsModel()
+  {
+    // Model: one elementwise add operation
+    // model input: lhs, rhs
+    // model output: add result
+    // lhs, rhs, result shape: {1, unknown, 2, 1}
+    // activation: none (constant)
+    _graph = nnfw::cpp14::make_unique<Graph>();
+
+    // Add operands
+
+    Shape shape{1, 0, 2, 1};
+    TypeInfo type{DataType::INT32};
+    Shape shape_scalar(0);
+    TypeInfo type_scalar{DataType::INT32};
+
+    auto operand_lhs = _graph->addOperand(shape, type);
+    auto operand_rhs = _graph->addOperand(shape, type);
+
+    auto operand_activation = _graph->addOperand(shape_scalar, type_scalar);
+    _graph->operands()
+        .at(operand_activation)
+        .data(nnfw::cpp14::make_unique<CachedData>(
+            reinterpret_cast<const uint8_t *>(&_activation_value), 4));
+
+    auto operand_result = _graph->addOperand(shape, type);
+
+    // Add operations
+
+    operation::Add::Param param;
+    param.activation = Activation::NONE;
+    auto input_set = OperandIndexSequence{operand_lhs, operand_rhs};
+    auto output_set = OperandIndexSequence{operand_result};
+    _graph->addOperation(nnfw::cpp14::make_unique<operation::Add>(input_set, output_set, param));
+
+    // Identify model inputs and outputs
+
+    _graph->getInputs().append(operand_lhs);
+    _graph->getInputs().append(operand_rhs);
+    _graph->getOutputs().append(operand_result);
+
+    _graph->finishBuilding();
+
+    _executor = nnfw::cpp14::make_unique<ExecManager>(*_graph);
+  }
+
+  void createExecution() { _execution = nnfw::cpp14::make_unique<Execution>(_executor); }
+
+  virtual void TearDown() { _executor = nullptr; }
+
+  std::unique_ptr<Graph> _graph{nullptr};
+  std::shared_ptr<ExecManager> _executor{nullptr};
+  std::unique_ptr<Execution> _execution{nullptr};
+  const int32_t _activation_value{0};
+};
+
+TEST_F(InterpExecManagerTest, create_empty)
+{
+  Graph graph;
+  graph.finishBuilding();
+  _executor = nnfw::cpp14::make_unique<ExecManager>(graph);
+  ASSERT_NE(_executor, nullptr);
+}
+
+TEST_F(InterpExecManagerTest, create_simple)
+{
+  CreateSimpleModel();
+  ASSERT_NE(_executor, nullptr);
+}
+
+TEST_F(InterpExecManagerTest, setInput)
+{
+  CreateSimpleModel();
+  createExecution();
+
+  auto input1 = IOIndex{0};
+  const int32_t input1_buffer[4] = {1, 0, -1, -2};
+
+  EXPECT_THROW(_execution->setInput(input1, reinterpret_cast<const void *>(input1_buffer), 4),
+               std::runtime_error);
+  EXPECT_THROW(_execution->setInput(input1, reinterpret_cast<const void *>(input1_buffer), 12),
+               std::runtime_error);
+  EXPECT_NO_THROW(_execution->setInput(input1, reinterpret_cast<const void *>(input1_buffer), 16));
+}
+
+TEST_F(InterpExecManagerTest, setOutput)
+{
+  CreateSimpleModel();
+  createExecution();
+
+  auto output = IOIndex{0};
+  auto output_idx = _graph->getOutputs().at(output);
+
+  int32_t output_buffer[4] = {};
+
+  EXPECT_THROW(_execution->setOutput(output, reinterpret_cast<void *>(output_buffer), 4),
+               std::runtime_error);
+  EXPECT_THROW(_execution->setOutput(output, reinterpret_cast<void *>(output_buffer), 12),
+               std::runtime_error);
+  EXPECT_NO_THROW(_execution->setOutput(output, reinterpret_cast<void *>(output_buffer), 16));
+}
+
+TEST_F(InterpExecManagerTest, setInputForUnspecifiedDimensions)
+{
+  CreateUnspecifiedDimensionsModel();
+  createExecution();
+
+  auto input1 = IOIndex{0};
+  const int32_t input1_buffer[4] = {1, 0, -1, -2};
+
+  TypeInfo operand_type{DataType::INT32};
+  Shape operand_shape{1, 2, 2, 1};
+
+  EXPECT_THROW(_execution->setInput(input1, operand_type, operand_shape,
+                                    reinterpret_cast<const void *>(input1_buffer), 4),
+               std::runtime_error);
+  EXPECT_THROW(_execution->setInput(input1, operand_type, operand_shape,
+                                    reinterpret_cast<const void *>(input1_buffer), 12),
+               std::runtime_error);
+  EXPECT_NO_THROW(_execution->setInput(input1, operand_type, operand_shape,
+                                       reinterpret_cast<const void *>(input1_buffer), 16));
+}
+
+TEST_F(InterpExecManagerTest, setOutputForUnspecifiedDimensions)
+{
+  CreateUnspecifiedDimensionsModel();
+  createExecution();
+
+  auto output = IOIndex{0};
+  auto output_idx = _graph->getOutputs().at(output);
+
+  TypeInfo operand_type{DataType::INT32};
+  Shape operand_shape{1, 2, 2, 1};
+
+  int32_t output_buffer[4] = {};
+
+  EXPECT_THROW(_execution->setOutput(output, operand_type, operand_shape,
+                                     reinterpret_cast<void *>(output_buffer), 4),
+               std::runtime_error);
+  EXPECT_THROW(_execution->setOutput(output, operand_type, operand_shape,
+                                     reinterpret_cast<void *>(output_buffer), 12),
+               std::runtime_error);
+  EXPECT_NO_THROW(_execution->setOutput(output, operand_type, operand_shape,
+                                        reinterpret_cast<void *>(output_buffer), 16));
+}
+
+TEST_F(InterpExecManagerTest, execute)
+{
+  CreateSimpleModel();
+  createExecution();
+
+  auto input1 = IOIndex{0};
+  auto input2 = IOIndex{1};
+  auto input1_idx = _graph->getInputs().at(input1);
+  auto input2_idx = _graph->getInputs().at(input2);
+
+  const int32_t input1_buffer[4] = {1, 0, -1, -2};
+  const int32_t input2_buffer[4] = {1, -3, 2, -4};
+
+  auto output = IOIndex{0};
+  auto output_idx = _graph->getOutputs().at(output);
+
+  int32_t output_buffer[4] = {};
+
+  EXPECT_NO_THROW(_execution->setInput(input1, reinterpret_cast<const void *>(input1_buffer), 16));
+  EXPECT_NO_THROW(_execution->setInput(input2, reinterpret_cast<const void *>(input2_buffer), 16));
+  EXPECT_NO_THROW(_execution->setOutput(output, reinterpret_cast<void *>(output_buffer), 16));
+  EXPECT_NO_THROW(_execution->execute());
+  EXPECT_EQ(output_buffer[0], 2);
+  EXPECT_EQ(output_buffer[1], -3);
+  EXPECT_EQ(output_buffer[2], 1);
+  EXPECT_EQ(output_buffer[3], -6);
+}
+
+TEST_F(InterpExecManagerTest, executeTwoStep)
+{
+  CreateTwoStepModel();
+  createExecution();
+
+  auto input1 = IOIndex{0};
+  auto input2 = IOIndex{1};
+  auto input1_idx = _graph->getInputs().at(input1);
+  auto input2_idx = _graph->getInputs().at(input2);
+
+  const int32_t input1_buffer[4] = {1, 0, -1, -2};
+  const int32_t input2_buffer[4] = {1, -3, 2, -4};
+
+  auto output = IOIndex{0};
+  auto output_idx = _graph->getOutputs().at(output);
+
+  int32_t output_buffer[4] = {};
+
+  EXPECT_NO_THROW(_execution->setInput(input1, reinterpret_cast<const void *>(input1_buffer), 16));
+  EXPECT_NO_THROW(_execution->setInput(input2, reinterpret_cast<const void *>(input2_buffer), 16));
+  EXPECT_NO_THROW(_execution->setOutput(output, reinterpret_cast<void *>(output_buffer), 16));
+  EXPECT_NO_THROW(_execution->execute());
+  EXPECT_EQ(output_buffer[0], 5);
+  EXPECT_EQ(output_buffer[1], -2);
+  EXPECT_EQ(output_buffer[2], 0);
+  EXPECT_EQ(output_buffer[3], -1);
+}
+
+} // namespace
diff --git a/runtime/neurun/test/graph/Graph.cc b/runtime/neurun/test/graph/Graph.cc
new file mode 100644
index 000000000..faf84df9c
--- /dev/null
+++ b/runtime/neurun/test/graph/Graph.cc
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <gtest/gtest.h>
+
+#include "ir/Graph.h"
+
+TEST(Graph, inputs_and_outputs)
+{
+  neurun::ir::Graph graph;
+
+  neurun::ir::OperandIndex index0{0u};
+  neurun::ir::OperandIndex index1{1u};
+
+  graph.addInput({index0});
+  graph.addInput({index1});
+
+  neurun::ir::OperandIndex index10{10u};
+  neurun::ir::OperandIndex index11{11u};
+  neurun::ir::OperandIndex index12{12u};
+
+  graph.addOutput({index10});
+  graph.addOutput({index11});
+  graph.addOutput({index12});
+
+  ASSERT_EQ(graph.getInputs().size(), 2);
+  ASSERT_EQ(graph.getOutputs().size(), 3);
+
+  neurun::ir::IOIndex io_index0{0};
+  neurun::ir::IOIndex io_index1{1};
+  neurun::ir::IOIndex io_index2{2};
+
+  ASSERT_EQ(graph.getInputs().at(io_index0), 0);
+  ASSERT_EQ(graph.getInputs().at(io_index1), 1);
+
+  ASSERT_EQ(graph.getOutputs().at(io_index0), 10);
+  ASSERT_EQ(graph.getOutputs().at(io_index1), 11);
+  ASSERT_EQ(graph.getOutputs().at(io_index2), 12);
+}
diff --git a/runtime/neurun/test/graph/Index.cc b/runtime/neurun/test/graph/Index.cc
new file mode 100644
index 000000000..c24c2dd5e
--- /dev/null
+++ b/runtime/neurun/test/graph/Index.cc
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <gtest/gtest.h>
+
+#include "util/Index.h"
+
+using Index = ::neurun::util::Index<uint32_t, struct TestTag>;
+
+TEST(Index, index_test)
+{
+  Index idx1{1u};
+  Index idx2{2u};
+  Index idx3{idx1};
+
+  ASSERT_EQ(idx1, 1);
+  ASSERT_EQ(idx1, 1u);
+  ASSERT_EQ(idx1.value(), 1u);
+  ASSERT_NE(idx1, idx2);
+  ASSERT_EQ(idx1, idx3);
+}
diff --git a/runtime/neurun/test/graph/MockNode.h b/runtime/neurun/test/graph/MockNode.h
new file mode 100644
index 000000000..67f4c049d
--- /dev/null
+++ b/runtime/neurun/test/graph/MockNode.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_TEST_GRAPH_MOCK_NODE_H__
+#define __NEURUN_TEST_GRAPH_MOCK_NODE_H__
+
+#include "ir/Operation.h"
+#include "ir/OperandIndexSequence.h"
+
+namespace neurun_test
+{
+namespace ir
+{
+
+class SimpleMock : public neurun::ir::Operation
+{
+public:
+  SimpleMock(const neurun::ir::OperandIndexSequence &inputs,
+             const neurun::ir::OperandIndexSequence &outputs)
+      : Operation{neurun::ir::OperandConstraint::createAny()}
+  {
+    setInputs(inputs);
+    setOutputs(outputs);
+  }
+
+public:
+  void accept(neurun::ir::OperationVisitor &) const override {}
+  neurun::ir::OpCode opcode() const final { return neurun::ir::OpCode::Invalid; }
+};
+
+} // namespace ir
+} // namespace neurun_test
+
+#endif // __NEURUN_TEST_GRAPH_MOCK_NODE_H__
diff --git a/runtime/neurun/test/graph/operand/IndexSet.cc b/runtime/neurun/test/graph/operand/IndexSet.cc
new file mode 100644
index 000000000..969290fe1
--- /dev/null
+++ b/runtime/neurun/test/graph/operand/IndexSet.cc
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <gtest/gtest.h>
+
+#include "ir/OperandIndexSequence.h"
+
+using neurun::ir::OperandIndex;
+using neurun::ir::OperandIndexSequence;
+
+TEST(graph_OperandIndexSequence, append)
+{
+  OperandIndexSequence iset{0, 2, 4, 8};
+
+  ASSERT_EQ(iset.size(), 4);
+
+  iset.append(OperandIndex{10});
+
+  ASSERT_EQ(iset.size(), 5);
+
+  neurun::ir::IOIndex index1{1};
+  neurun::ir::IOIndex index2{4};
+
+  ASSERT_EQ(iset.at(index1), 2);
+  ASSERT_EQ(iset.at(index2), 10);
+
+  ASSERT_TRUE(iset.contains(OperandIndex{2}));
+  ASSERT_TRUE(iset.contains(OperandIndex{10}));
+  ASSERT_FALSE(iset.contains(OperandIndex{11}));
+}
+
+TEST(graph_OperandIndexSequence, replace)
+{
+  OperandIndexSequence iset{0, 1, 2, 3};
+
+  iset.replace(OperandIndex{1}, OperandIndex{9});
+  ASSERT_FALSE(iset.contains(OperandIndex{1}));
+  ASSERT_TRUE(iset.contains(OperandIndex{9}));
+}
diff --git a/runtime/neurun/test/graph/operand/LayoutSet.cc b/runtime/neurun/test/graph/operand/LayoutSet.cc
new file mode 100644
index 000000000..7b0dcc9f7
--- /dev/null
+++ b/runtime/neurun/test/graph/operand/LayoutSet.cc
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <gtest/gtest.h>
+
+#include "ir/LayoutSet.h"
+
+using neurun::ir::Layout;
+using neurun::ir::LayoutSet;
+
+TEST(graph_operand_LayoutSet, layout_set_operators)
+{
+  LayoutSet set1{Layout::NCHW};
+  LayoutSet set2{Layout::NHWC};
+  LayoutSet set3 = set1 | set2;
+
+  ASSERT_EQ(set3.size(), 2);
+
+  ASSERT_EQ((set3 - set1).size(), 1);
+  ASSERT_EQ((set3 - set1).contains(Layout::NHWC), true);
+  ASSERT_EQ((set3 - set2).size(), 1);
+  ASSERT_EQ((set3 - set2).contains(Layout::NCHW), true);
+  ASSERT_EQ((set3 - set3).size(), 0);
+
+  ASSERT_EQ((set3 & set1).size(), 1);
+  ASSERT_EQ((set3 & set1).contains(Layout::NCHW), true);
+  ASSERT_EQ((set3 & set2).size(), 1);
+  ASSERT_EQ((set3 & set2).contains(Layout::NHWC), true);
+  ASSERT_EQ((set1 & set2).size(), 0);
+}
diff --git a/runtime/neurun/test/graph/operand/Set.cc b/runtime/neurun/test/graph/operand/Set.cc
new file mode 100644
index 000000000..e30a5b7f7
--- /dev/null
+++ b/runtime/neurun/test/graph/operand/Set.cc
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <gtest/gtest.h>
+
+#include "ir/Operands.h"
+
+TEST(graph_operand_Set, set_test)
+{
+  neurun::ir::Operands set;
+
+  neurun::ir::Shape shape0{1, 2, 3};
+
+  neurun::ir::Shape shape1(4);
+  shape1.dim(0) = 10;
+  shape1.dim(1) = 20;
+  shape1.dim(2) = 30;
+  shape1.dim(3) = 40;
+
+  neurun::ir::TypeInfo type{neurun::ir::DataType::INT32};
+
+  set.emplace(shape0, type);
+  set.emplace(shape1, type);
+
+  ASSERT_EQ(set.exist(neurun::ir::OperandIndex{0u}), true);
+  ASSERT_EQ(set.exist(neurun::ir::OperandIndex{1u}), true);
+  ASSERT_EQ(set.exist(neurun::ir::OperandIndex{2u}), false);
+
+  ASSERT_EQ(set.at(neurun::ir::OperandIndex{0u}).shape().dim(0), 1);
+  ASSERT_EQ(set.at(neurun::ir::OperandIndex{0u}).shape().dim(1), 2);
+  ASSERT_EQ(set.at(neurun::ir::OperandIndex{0u}).shape().dim(2), 3);
+}
diff --git a/runtime/neurun/test/graph/operand/UseDef.cc b/runtime/neurun/test/graph/operand/UseDef.cc
new file mode 100644
index 000000000..c59032824
--- /dev/null
+++ b/runtime/neurun/test/graph/operand/UseDef.cc
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <gtest/gtest.h>
+
+#include "ir/Graph.h"
+#include "ir/verifier/Verifier.h"
+#include "cpp14/memory.h"
+#include "../MockNode.h"
+
+#include <typeindex>
+
+namespace
+{
+
+using IndexSet = neurun::ir::OperandIndexSequence;
+using Mock = neurun_test::ir::SimpleMock;
+
+} // namespace anonymous
+
+TEST(graph_operand_usedef, usedef_test)
+{
+  neurun::ir::Graph graph;
+  neurun::ir::verifier::DAGChecker verifier;
+
+  neurun::ir::Shape shape(3);
+  neurun::ir::TypeInfo type{neurun::ir::DataType::INT32};
+
+  // Model Input/Output
+  auto input_operand = graph.addOperand(shape, type);
+  auto output_operand = graph.addOperand(shape, type);
+
+  graph.addInput(input_operand);
+  graph.addOutput(output_operand);
+
+  // MockNode1
+  auto operand_index1 = graph.addOperand(shape, type);
+  auto mocknode_index1 = graph.addOperation(
+      nnfw::cpp14::make_unique<Mock>(IndexSet{input_operand}, IndexSet{operand_index1}));
+
+  // MockNode2
+  auto operand_index2 = graph.addOperand(shape, type);
+  auto mocknode_index2 = graph.addOperation(
+      nnfw::cpp14::make_unique<Mock>(IndexSet{input_operand}, IndexSet{operand_index2}));
+
+  // MockNode3(two input)
+  auto multiinput_index = graph.addOperation(nnfw::cpp14::make_unique<Mock>(
+      IndexSet{operand_index1, operand_index2}, IndexSet{output_operand}));
+
+  graph.finishBuilding();
+
+  ASSERT_EQ(verifier.verify(graph), true);
+
+  // Check def
+  ASSERT_EQ(graph.operands().at(operand_index1).getDef().contains(mocknode_index1), true);
+  ASSERT_EQ(graph.operands().at(operand_index2).getDef().contains(mocknode_index2), true);
+  ASSERT_EQ(graph.operands().at(output_operand).getDef().contains(multiinput_index), true);
+
+  ASSERT_EQ(graph.operands().at(operand_index1).getDef().contains(mocknode_index2), false);
+  ASSERT_EQ(graph.operands().at(operand_index1).getDef().contains(multiinput_index), false);
+
+  // Check use
+  ASSERT_EQ(graph.operands().at(input_operand).getUses().contains(mocknode_index1), true);
+  ASSERT_EQ(graph.operands().at(input_operand).getUses().contains(mocknode_index2), true);
+  ASSERT_EQ(graph.operands().at(input_operand).getUses().contains(multiinput_index), false);
+  ASSERT_EQ(graph.operands().at(operand_index1).getUses().contains(multiinput_index), true);
+  ASSERT_EQ(graph.operands().at(operand_index2).getUses().contains(multiinput_index), true);
+
+  ASSERT_EQ(graph.operands().at(input_operand).getUses().size(), 2);
+  ASSERT_EQ(graph.operands().at(operand_index1).getUses().size(), 1);
+  ASSERT_EQ(graph.operands().at(output_operand).getUses().size(), 0);
+}
diff --git a/runtime/neurun/test/graph/operation/Set.cc b/runtime/neurun/test/graph/operation/Set.cc
new file mode 100644
index 000000000..fb3d54298
--- /dev/null
+++ b/runtime/neurun/test/graph/operation/Set.cc
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <gtest/gtest.h>
+
+#include "../MockNode.h"
+#include "ir/Operations.h"
+
+using neurun::ir::Operations;
+using neurun::ir::Operation;
+using neurun::ir::OperationIndex;
+
+TEST(graph_operation_Set, operation_test)
+{
+  Operations ops;
+  ops.push(std::unique_ptr<Operation>(new neurun_test::ir::SimpleMock({1, 2, 3, 4}, {5, 6, 7})));
+  OperationIndex idx{0u};
+  ASSERT_EQ(ops.at(idx).getInputs().size(), 4);
+  ASSERT_EQ(ops.at(idx).getOutputs().size(), 3);
+}
diff --git a/runtime/neurun/test/graph/operation/SetIO.cc b/runtime/neurun/test/graph/operation/SetIO.cc
new file mode 100644
index 000000000..110accfac
--- /dev/null
+++ b/runtime/neurun/test/graph/operation/SetIO.cc
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <gtest/gtest.h>
+
+#include "ir/Graph.h"
+#include "ir/Index.h"
+#include "ir/OperandIndexSequence.h"
+#include "ir/operation/Conv2D.h"
+#include "ir/operation/Concat.h"
+
+#include <cpp14/memory.h>
+
+#include <stdexcept>
+
+using Index = neurun::ir::IOIndex;
+using IndexSet = neurun::ir::OperandIndexSequence;
+
+TEST(graph_operation_setIO, operation_setIO_conv)
+{
+  neurun::ir::Graph graph;
+
+  neurun::ir::Shape shape{3};
+  neurun::ir::TypeInfo type{neurun::ir::DataType::INT32};
+
+  // Add Conv
+  using Graph = neurun::ir::operation::Conv2D;
+
+  auto input_operand = graph.addOperand(shape, type);
+  auto kernel_operand = graph.addOperand(shape, type);
+  auto bias_operand = graph.addOperand(shape, type);
+  IndexSet inputs{input_operand, kernel_operand, bias_operand};
+
+  Graph::Param conv_params;
+  conv_params.padding.type = neurun::ir::PaddingType::SAME;
+  conv_params.stride.horizontal = 1;
+  conv_params.stride.vertical = 1;
+  conv_params.activation = neurun::ir::Activation::NONE;
+
+  auto output_operand = graph.addOperand(shape, type).value();
+  IndexSet outputs{output_operand};
+
+  auto conv = nnfw::cpp14::make_unique<Graph>(inputs, outputs, conv_params);
+
+  ASSERT_NE(conv, nullptr);
+  ASSERT_EQ(conv->getInputs().at(Index{0}).value(), inputs.at(0).value());
+  conv->setInputs({8, 9, 10});
+  ASSERT_NE(conv->getInputs().at(Index{0}).value(), inputs.at(0).value());
+  ASSERT_EQ(conv->getInputs().at(Index{0}).value(), 8);
+}
+
+TEST(graph_operation_setIO, operation_setIO_concat)
+{
+  neurun::ir::Graph graph;
+
+  neurun::ir::Shape shape{3};
+
+  neurun::ir::TypeInfo type{neurun::ir::DataType::INT32};
+
+  using Graph = neurun::ir::operation::Concat;
+
+  // Add Concat
+  IndexSet inputs;
+  for (int i = 0; i < 6; ++i)
+  {
+    inputs.append(graph.addOperand(shape, type));
+  }
+
+  Graph::Param concat_params{0};
+
+  auto output_operand = graph.addOperand(shape, type).value();
+  IndexSet outputs{output_operand};
+
+  auto concat = nnfw::cpp14::make_unique<Graph>(inputs, outputs, concat_params);
+
+  ASSERT_NE(concat, nullptr);
+  ASSERT_EQ(concat->getInputs().size(), 6);
+  ASSERT_EQ(concat->getInputs().at(Index{0}).value(), inputs.at(0).value());
+
+  concat->setInputs({80, 6, 9, 11});
+  ASSERT_EQ(concat->getInputs().size(), 4);
+  ASSERT_NE(concat->getInputs().at(Index{0}).value(), inputs.at(0).value());
+  ASSERT_EQ(concat->getInputs().at(Index{0}).value(), 80);
+  ASSERT_EQ(concat->getInputs().at(Index{2}).value(), 9);
+  ASSERT_THROW(concat->getInputs().at(Index{5}), std::out_of_range);
+}
diff --git a/runtime/neurun/test/graph/verifier/Verifier.cc b/runtime/neurun/test/graph/verifier/Verifier.cc
new file mode 100644
index 000000000..cbda31dfe
--- /dev/null
+++ b/runtime/neurun/test/graph/verifier/Verifier.cc
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <gtest/gtest.h>
+
+#include "ir/Operation.h"
+#include "ir/Graph.h"
+#include "ir/verifier/Verifier.h"
+#include "cpp14/memory.h"
+#include "ir/Operand.h"
+#include "../MockNode.h"
+
+using IndexSet = neurun::ir::OperandIndexSequence;
+using Mock = neurun_test::ir::SimpleMock;
+
+TEST(Verifier, dag_checker)
+{
+  neurun::ir::Graph graph;
+
+  neurun::ir::Shape shape{3};
+  neurun::ir::TypeInfo type{neurun::ir::DataType::INT32};
+
+  auto operand1 = graph.addOperand(shape, type);
+  auto operand2 = graph.addOperand(shape, type);
+
+  graph.addInput(operand1);
+  graph.addOutput(operand2);
+
+  graph.addOperation(nnfw::cpp14::make_unique<Mock>(IndexSet{operand1}, IndexSet{operand2}));
+
+  graph.finishBuilding();
+
+  neurun::ir::verifier::DAGChecker verifier;
+
+  ASSERT_EQ(verifier.verify(graph), true);
+}
diff --git a/runtime/neurun/test/util/ShapeInference.cc b/runtime/neurun/test/util/ShapeInference.cc
new file mode 100644
index 000000000..a8dea3a79
--- /dev/null
+++ b/runtime/neurun/test/util/ShapeInference.cc
@@ -0,0 +1,233 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <gtest/gtest.h>
+
+#include "ir/Layout.h"
+#include "util/ShapeInference.h"
+
+using namespace neurun::ir;
+
+TEST(ShapeInference, Elementwise)
+{
+  Shape lhs_shape{1, 299, 299, 3};
+  Shape rhs_shape{3};
+  auto infered_shapes = neurun::shape_inference::inferEltwiseShape(lhs_shape, rhs_shape);
+  auto infered_out_shape = infered_shapes[0];
+
+  ASSERT_EQ(infered_out_shape.rank(), 4);
+  ASSERT_EQ(infered_out_shape.dim(0), 1);
+  ASSERT_EQ(infered_out_shape.dim(1), 299);
+  ASSERT_EQ(infered_out_shape.dim(2), 299);
+  ASSERT_EQ(infered_out_shape.dim(3), 3);
+}
+
+TEST(ShapeInference, IncorrectElementwise)
+{
+  Shape lhs_shape{1, 299, 299, 3};
+  Shape rhs_shape{5, 3};
+  ASSERT_THROW(neurun::shape_inference::inferEltwiseShape(lhs_shape, rhs_shape),
+               std::runtime_error);
+}
+
+TEST(ShapeInference, Pool2DNodeSame)
+{
+  Shape in_shape{10, 6, 12, 20};
+  Stride stride{3, 7};
+  Padding padding{PaddingType::SAME};
+
+  operation::AvgPool2D::Param avg_pool_param{3, 6, stride, padding, Activation::NONE};
+  auto infered_shapes = neurun::shape_inference::inferAvgPoolShape(in_shape, avg_pool_param);
+  auto infered_out_shape = infered_shapes[0];
+
+  ASSERT_EQ(infered_out_shape.rank(), 4);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).N, 10);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).H, 2);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).W, 2);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).C, 20);
+
+  operation::MaxPool2D::Param max_pool_param{3, 6, stride, padding, Activation::NONE};
+  infered_shapes = neurun::shape_inference::inferMaxPoolShape(in_shape, max_pool_param);
+  infered_out_shape = infered_shapes[0];
+
+  ASSERT_EQ(infered_out_shape.rank(), 4);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).N, 10);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).H, 2);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).W, 2);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).C, 20);
+}
+
+TEST(ShapeInference, Pool2DNodeValid)
+{
+  Shape in_shape{10, 6, 12, 20};
+  Stride stride{3, 7};
+  Padding padding{PaddingType::VALID};
+
+  operation::AvgPool2D::Param avg_pool_param{3, 6, stride, padding, Activation::NONE};
+  auto infered_shapes = neurun::shape_inference::inferAvgPoolShape(in_shape, avg_pool_param);
+  auto infered_out_shape = infered_shapes[0];
+
+  ASSERT_EQ(infered_out_shape.rank(), 4);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).N, 10);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).H, 2);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).W, 1);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).C, 20);
+
+  operation::MaxPool2D::Param max_pool_param{3, 6, stride, padding, Activation::NONE};
+  infered_shapes = neurun::shape_inference::inferMaxPoolShape(in_shape, max_pool_param);
+  infered_out_shape = infered_shapes[0];
+
+  ASSERT_EQ(infered_out_shape.rank(), 4);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).N, 10);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).H, 2);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).W, 1);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).C, 20);
+}
+
+TEST(ShapeInference, Pool2DNodeExplicit)
+{
+  Shape in_shape{10, 3, 5, 20};
+
+  Stride stride{3, 7};
+  Padding padding{PaddingType::EXPLICIT, {4, 3, 2, 1}};
+
+  operation::AvgPool2D::Param avg_pool_param{3, 6, stride, padding, Activation::NONE};
+  auto infered_shapes = neurun::shape_inference::inferAvgPoolShape(in_shape, avg_pool_param);
+  auto infered_out_shape = infered_shapes[0];
+
+  ASSERT_EQ(infered_out_shape.rank(), 4);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).N, 10);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).H, 2);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).W, 1);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).C, 20);
+
+  operation::MaxPool2D::Param max_pool_param{3, 6, stride, padding, Activation::NONE};
+  infered_shapes = neurun::shape_inference::inferMaxPoolShape(in_shape, max_pool_param);
+  infered_out_shape = infered_shapes[0];
+
+  ASSERT_EQ(infered_out_shape.rank(), 4);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).N, 10);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).H, 2);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).W, 1);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).C, 20);
+}
+
+TEST(ShapeInference, Conv2D)
+{
+  Shape in_shape{10, 6, 12, 20};
+  Shape ker_shape{30, 3, 6, 20};
+
+  operation::Conv2D::Param param{Stride{3, 7}, Padding{PaddingType::VALID}, Activation::NONE};
+  auto infered_shapes = neurun::shape_inference::inferConv2DShape(in_shape, ker_shape, param);
+  auto infered_out_shape = infered_shapes[0];
+
+  ASSERT_EQ(infered_out_shape.rank(), 4);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).N, 10);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).H, 2);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).W, 1);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).C, 30);
+
+  param = operation::Conv2D::Param{Stride{3, 7}, Padding{PaddingType::SAME}, Activation::NONE};
+  infered_shapes = neurun::shape_inference::inferConv2DShape(in_shape, ker_shape, param);
+  infered_out_shape = infered_shapes[0];
+
+  ASSERT_EQ(infered_out_shape.rank(), 4);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).N, 10);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).H, 2);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).W, 2);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).C, 30);
+
+  param = operation::Conv2D::Param{Stride{3, 7}, Padding{PaddingType::EXPLICIT, {4, 3, 2, 1}},
+                                   Activation::NONE};
+  infered_shapes = neurun::shape_inference::inferConv2DShape(in_shape, ker_shape, param);
+  infered_out_shape = infered_shapes[0];
+
+  ASSERT_EQ(infered_out_shape.rank(), 4);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).N, 10);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).H, 3);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).W, 2);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).C, 30);
+}
+
+TEST(ShapeInference, DepthwiseConv2D)
+{
+  Shape in_shape{10, 6, 12, 20};
+  Shape ker_shape{1, 3, 6, 60};
+
+  operation::DepthwiseConv2D::Param param{Stride{3, 7}, Padding{PaddingType::VALID}, 3,
+                                          Activation::NONE};
+  auto infered_shapes =
+      neurun::shape_inference::inferDepthwiseConv2DShape(in_shape, ker_shape, param);
+  auto infered_out_shape = infered_shapes[0];
+
+  ASSERT_EQ(infered_out_shape.rank(), 4);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).N, 10);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).H, 2);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).W, 1);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).C, 60);
+
+  param = operation::DepthwiseConv2D::Param{Stride{3, 7}, Padding{PaddingType::SAME}, 3,
+                                            Activation::NONE};
+  infered_shapes = neurun::shape_inference::inferDepthwiseConv2DShape(in_shape, ker_shape, param);
+  infered_out_shape = infered_shapes[0];
+
+  ASSERT_EQ(infered_out_shape.rank(), 4);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).N, 10);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).H, 2);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).W, 2);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).C, 60);
+
+  param = operation::DepthwiseConv2D::Param{
+      Stride{3, 7}, Padding{PaddingType::EXPLICIT, {4, 3, 2, 1}}, 3, Activation::NONE};
+  infered_shapes = neurun::shape_inference::inferDepthwiseConv2DShape(in_shape, ker_shape, param);
+  infered_out_shape = infered_shapes[0];
+
+  ASSERT_EQ(infered_out_shape.rank(), 4);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).N, 10);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).H, 3);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).W, 2);
+  ASSERT_EQ(infered_out_shape.asFeature(Layout::NHWC).C, 60);
+}
+
+TEST(ShapeInference, Concat)
+{
+  Shape in1{10, 20, 30, 3, 50};
+  Shape in2{10, 20, 30, 2, 50};
+  Shape in3{10, 20, 30, 2, 50};
+
+  operation::Concat::Param param{3};
+  auto infered_shapes = neurun::shape_inference::inferConcatShape({in1, in2, in3}, param);
+  auto infered_out_shape = infered_shapes[0];
+
+  ASSERT_EQ(infered_out_shape.rank(), 5);
+  ASSERT_EQ(infered_out_shape.dim(0), 10);
+  ASSERT_EQ(infered_out_shape.dim(1), 20);
+  ASSERT_EQ(infered_out_shape.dim(2), 30);
+  ASSERT_EQ(infered_out_shape.dim(3), 7);
+  ASSERT_EQ(infered_out_shape.dim(4), 50);
+}
+
+TEST(ShapeInference, FullyConnected)
+{
+  Shape in_shape{3, 4, 5, 6};
+  Shape ker_shape{3, 10};
+  auto infered_shapes = neurun::shape_inference::inferFullyConnectedShape(in_shape, ker_shape);
+  auto infered_out_shape = infered_shapes[0];
+
+  ASSERT_EQ(infered_out_shape.rank(), 2);
+  ASSERT_EQ(infered_out_shape.dim(0), 36);
+  ASSERT_EQ(infered_out_shape.dim(1), 3);
+}
diff --git a/runtime/nnapi-header/CMakeLists.txt b/runtime/nnapi-header/CMakeLists.txt
new file mode 100644
index 000000000..fe9aebe5d
--- /dev/null
+++ b/runtime/nnapi-header/CMakeLists.txt
@@ -0,0 +1,8 @@
+add_library(nnfw-nnapi-header INTERFACE)
+target_include_directories(nnfw-nnapi-header INTERFACE include)
+
+set(NNFW_NNAPI_HEADERS ${CMAKE_CURRENT_LIST_DIR}/include/NeuralNetworks.h
+                       ${CMAKE_CURRENT_LIST_DIR}/include/NeuralNetworksEx.h
+                       ${CMAKE_CURRENT_LIST_DIR}/include/NeuralNetworksExtensions.h)
+
+install(FILES ${NNFW_NNAPI_HEADERS} DESTINATION include/nnfw)
diff --git a/runtime/nnapi-header/include/NeuralNetworks.h b/runtime/nnapi-header/include/NeuralNetworks.h
new file mode 100644
index 000000000..7400806d8
--- /dev/null
+++ b/runtime/nnapi-header/include/NeuralNetworks.h
@@ -0,0 +1,6444 @@
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved
+ * Copyright (C) 2017 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @addtogroup NeuralNetworks
+ * @{
+ */
+
+/**
+ * @file NeuralNetworks.h
+ */
+
+#ifndef ANDROID_ML_NN_RUNTIME_NEURAL_NETWORKS_H
+#define ANDROID_ML_NN_RUNTIME_NEURAL_NETWORKS_H
+
+/******************************************************************
+ *
+ * IMPORTANT NOTICE:
+ *
+ *   This file is part of Android's set of stable system headers
+ *   exposed by the Android NDK (Native Development Kit).
+ *
+ *   Third-party source AND binary code relies on the definitions
+ *   here to be FROZEN ON ALL UPCOMING PLATFORM RELEASES.
+ *
+ *   - DO NOT MODIFY ENUMS (EXCEPT IF YOU ADD NEW 32-BIT VALUES)
+ *   - DO NOT MODIFY CONSTANTS OR FUNCTIONAL MACROS
+ *   - DO NOT CHANGE THE SIGNATURE OF FUNCTIONS IN ANY WAY
+ *   - DO NOT CHANGE THE LAYOUT OR SIZE OF STRUCTURES
+ */
+
+// For compatibility with android, check __ANDROID_API__ is defined
+// If __ANDROID_API__ is pre-defined, this header may be used for android
+#ifndef __ANDROID_API__
+#define __ANDROID_API__ 29
+#define __ANDROID_API_Q__ 29
+#define __INTRODUCED_IN(api_level)
+typedef struct AHardwareBuffer AHardwareBuffer;
+#else
+#include <android/hardware_buffer.h>
+#endif // __ANDROID_API__
+#include <stddef.h>
+#include <stdint.h>
+#include <sys/cdefs.h>
+
+__BEGIN_DECLS
+
+/**
+ * Operand types.
+ *
+ * The type of operands that can be added to a model.
+ *
+ * Although we define many types, most operators accept just a few
+ * types. Most used are {@link ANEURALNETWORKS_TENSOR_FLOAT32},
+ * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM},
+ * and {@link ANEURALNETWORKS_INT32}.
+ *
+ * Available since API level 27.
+ */
+typedef enum {
+    /** A 32 bit floating point scalar value. */
+    ANEURALNETWORKS_FLOAT32 = 0,
+    /** A signed 32 bit integer scalar value. */
+    ANEURALNETWORKS_INT32 = 1,
+    /** An unsigned 32 bit integer scalar value. */
+    ANEURALNETWORKS_UINT32 = 2,
+    /** A tensor of 32 bit floating point values. */
+    ANEURALNETWORKS_TENSOR_FLOAT32 = 3,
+    /** A tensor of 32 bit integer values. */
+    ANEURALNETWORKS_TENSOR_INT32 = 4,
+    /**
+     * A tensor of 8 bit unsigned integers that represent real numbers.
+     *
+     * Attached to this tensor are two numbers that can be used to convert the
+     * 8 bit integer to the real value and vice versa. These two numbers are:
+     * - scale: a 32 bit floating point value greater than zero.
+     * - zeroPoint: a 32 bit integer, in range [0, 255].
+     *
+     * The formula is:
+     *   real_value = (integer_value - zeroPoint) * scale.
+     */
+    ANEURALNETWORKS_TENSOR_QUANT8_ASYMM = 5,
+#if __ANDROID_API__ >= __ANDROID_API_Q__
+    /**
+     * An 8 bit boolean scalar value.
+     *
+     * Values of this operand type are either true or false. A zero value
+     * represents false; any other value represents true.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_BOOL = 6,
+    /**
+     * A tensor of 16 bit signed integers that represent real numbers.
+     *
+     * Attached to this tensor is a number representing real value scale that is
+     * used to convert the 16 bit number to a real value in the following way:
+     * realValue = integerValue * scale.
+     *
+     * scale is a 32 bit floating point with value greater than zero.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_TENSOR_QUANT16_SYMM = 7,
+    /**
+     * A tensor of IEEE 754 16 bit floating point values.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_TENSOR_FLOAT16 = 8,
+    /**
+     * A tensor of 8 bit boolean values.
+     *
+     * Values of this operand type are either true or false. A zero value
+     * represents false; any other value represents true.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_TENSOR_BOOL8 = 9,
+    /**
+     * An IEEE 754 16 bit floating point scalar value.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_FLOAT16 = 10,
+    /**
+     * A tensor of 8 bit signed integers that represent real numbers.
+     *
+     * This tensor is associated with additional fields that can
+     * be used to convert the 8 bit signed integer to the real value and vice versa.
+     * These fields are:
+     * - channelDim: a 32 bit unsigned integer indicating channel dimension.
+     * - scales: an array of positive 32 bit floating point values.
+     * The size of the scales array must be equal to dimensions[channelDim].
+     *
+     * {@link ANeuralNetworksModel_setOperandSymmPerChannelQuantParams} must be used
+     * to set the parameters for an Operand of this type.
+     *
+     * The channel dimension of this tensor must not be unknown (dimensions[channelDim] != 0).
+     *
+     * The formula is:
+     * realValue[..., C, ...] =
+     *     integerValue[..., C, ...] * scales[C]
+     * where C is an index in the Channel dimension.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL = 11,
+
+    /**
+     * A tensor of 16 bit unsigned integers that represent real numbers.
+     *
+     * Attached to this tensor are two numbers that can be used to convert the
+     * 16 bit integer to the real value and vice versa. These two numbers are:
+     * - scale: a 32 bit floating point value greater than zero.
+     * - zeroPoint: a 32 bit integer, in range [0, 65535].
+     *
+     * The formula is:
+     * real_value = (integer_value - zeroPoint) * scale.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_TENSOR_QUANT16_ASYMM = 12,
+
+    /**
+     * A tensor of 8 bit signed integers that represent real numbers.
+     *
+     * Attached to this tensor is a number representing real value scale that is
+     * used to convert the 8 bit number to a real value in the following way:
+     * realValue = integerValue * scale.
+     *
+     * scale is a 32 bit floating point with value greater than zero.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_TENSOR_QUANT8_SYMM = 13,
+#endif  // __ANDROID_API__ >= __ANDROID_API_Q__
+
+} OperandCode;
+
+/**
+ * Operation types.
+ *
+ * The type of operations that can be added to a model.
+ *
+ * Available since API level 27.
+ */
+typedef enum {
+    // Operations below are available since API level 27.
+
+    /**
+     * Adds two tensors, element-wise.
+     *
+     * Takes two input tensors of identical {@link OperandCode} and compatible
+     * dimensions. The output is the sum of both input tensors, optionally
+     * modified by an activation function.
+     *
+     * Two dimensions are compatible when:
+     *     1. they are equal, or
+     *     2. one of them is 1
+     *
+     * The size of the output is the maximum size along each dimension of the
+     * input operands. It starts with the trailing dimensions, and works its
+     * way forward.
+     *
+     * Example:
+     *
+     *     input1.dimension = {4, 1, 2}
+     *     input2.dimension = {5, 4, 3, 1}
+     *     output.dimension = {5, 4, 3, 2}
+     *
+     * Since API level 29, generic zero-sized input tensor is supported. Zero
+     * dimension is only compatible with 0 or 1. The size of the output
+     * dimension is zero if either of corresponding input dimension is zero.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: up to 4
+     *
+     * Inputs:
+     * * 0: A tensor.
+     * * 1: A tensor of the same {@link OperandCode}, and compatible dimensions
+     *      as input0.
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scales and zeroPoint can be different from input0 scale and zeroPoint.
+     * * 2: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the
+     *      {@link FuseCode} values. Specifies the activation to
+     *      invoke on the result.
+     *
+     * Outputs:
+     * * 0: The sum, a tensor of the same {@link OperandCode} as input0.
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint can be different from inputs' scale and zeroPoint.
+     *
+     * Available since API level 27.
+     */
+    ANEURALNETWORKS_ADD = 0,
+
+    /**
+     * Performs a 2-D average pooling operation.
+     *
+     * The output dimensions are functions of the filter dimensions, stride, and
+     * padding.
+     *
+     * The values in the output tensor are computed as:
+     *
+     *     output[b, i, j, channel] =
+     *         sum_{di, dj}(
+     *             input[b, strides[1] * i + di, strides[2] * j + dj, channel]
+     *         ) / sum(1)
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout.
+     * With the default data layout NHWC, the data is stored in the order of:
+     * [batch, height, width, channels]. Alternatively, the data layout could
+     * be NCHW, the data storage order of: [batch, channels, height, width].
+     *
+     * Both explicit padding and implicit padding are supported.
+     *
+     * Inputs (explicit padding):
+     * * 0: A 4-D tensor, of shape [batches, height, width, depth], specifying
+     *      the input. Since API level 29, zero batches is supported for this
+     *      tensor.
+     * * 1: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on
+     *      the left, in the ‘width’ dimension.
+     * * 2: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on
+     *      the right, in the ‘width’ dimension.
+     * * 3: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on
+     *      the top, in the ‘height’ dimension.
+     * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on
+     *      the bottom, in the ‘height’ dimension.
+     * * 5: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when
+     *      walking through input in the ‘width’ dimension.
+     * * 6: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when
+     *      walking through input in the ‘height’ dimension.
+     * * 7: An {@link ANEURALNETWORKS_INT32} scalar, specifying the filter
+     *      width.
+     * * 8: An {@link ANEURALNETWORKS_INT32} scalar, specifying the filter
+     *      height.
+     * * 9: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the
+     *      {@link FuseCode} values. Specifies the activation to
+     *      invoke on the result.
+     * * 10: An optional {@link ANEURALNETWORKS_BOOL} scalar, default to false.
+     *       Set to true to specify NCHW data layout for input0 and output0.
+     *       Available since API level 29.
+     *
+     * Inputs (implicit padding):
+     * * 0: A 4-D tensor, of shape [batches, height, width, depth], specifying
+     *      the input. Since API level 29, zero batches is supported for this
+     *      tensor.
+     * * 1: An {@link ANEURALNETWORKS_INT32} scalar, specifying the implicit
+     *      padding scheme, has to be one of the
+     *      {@link PaddingCode} values.
+     * * 2: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when
+     *      walking through input in the ‘width’ dimension.
+     * * 3: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when
+     *      walking through input in the ‘height’ dimension.
+     * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the filter
+     *      width.
+     * * 5: An {@link ANEURALNETWORKS_INT32} scalar, specifying the filter
+     *      height.
+     * * 6: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the
+     *      {@link FuseCode} values. Specifies the activation to
+     *      invoke on the result.
+     * * 7: An optional {@link ANEURALNETWORKS_BOOL} scalar, default to false.
+     *      Set to true to specify NCHW data layout for input0 and output0.
+     *      Available since API level 29.
+     *
+     * Outputs:
+     * * 0: The output 4-D tensor, of shape
+     *      [batches, out_height, out_width, depth].
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint must be the same as input0.
+     *
+     * Available since API level 27.
+     */
+    ANEURALNETWORKS_AVERAGE_POOL_2D = 1,
+
+    /**
+     * Concatenates the input tensors along the given dimension.
+     *
+     * The input tensors must have identical {@link OperandCode} and the same
+     * dimensions except the dimension along the concatenation axis.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} (full support since API
+     *   level 29, see the input section)
+     *
+     * Supported tensor rank: up to 4
+     *
+     * Inputs:
+     * * 0 ~ n-1: The list of n input tensors, of shape
+     *            [D0, D1, ..., Daxis(i), ..., Dm].
+     *            Before API level 29, all input tensors of
+     *            {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *            must have the same scale and zeroPoint as the output tensor.
+     *            Since API level 29, zero-sized tensors are supported.
+     * * n: An {@link ANEURALNETWORKS_INT32} scalar, specifying the
+     *      concatenation axis.
+     *
+     * Outputs:
+     * * 0: The output, a tensor of the same {@link OperandCode} as the input
+     *      tensors. The output shape is [D0, D1, ..., sum(Daxis(i)), ..., Dm].
+     *      Since API level 29, for a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint values can be different from
+     *      input tensors. Before API level 29 they have to be the same as for the input tensors.
+     *
+     * Available since API level 27.
+     */
+    ANEURALNETWORKS_CONCATENATION = 2,
+
+    /**
+     * Performs an 2-D convolution operation.
+     *
+     * The CONV_2D op sweeps a 2-D filter that can mix channels together over a
+     * batch of images, applying the filter to each window of each image of the
+     * appropriate size.
+     *
+     * The output dimensions are functions of the filter dimensions, stride, and
+     * padding.
+     *
+     * The values in the output tensor are computed as:
+     *
+     *     output[b, i, j, channel] =
+     *         sum_{di, dj, k} (
+     *             input[b, strides[1] * i + di, strides[2] * j + dj, k] *
+     *             filter[channel, di, dj, k]
+     *         ) + bias[channel]
+     *
+     * Supported tensor {@link OperandCode} configurations:
+     * * 32 bit floating point:
+     * * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} for input, filter, output, and bias.
+     *
+     * * Quantized:
+     * * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} for input, filter, and output.
+     * * * {@link ANEURALNETWORKS_TENSOR_INT32} for bias (with scale set to
+     * * * input.scale * filter.scale).
+     *
+     * Available since API level 29:
+     * * 16 bit floating point:
+     * * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} for input, filter, output, and bias.
+     *
+     * * Quantized with symmetric per channel quantization for the filter:
+     * * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} for input, and output.
+     * * * {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL} for filter.
+     * * * {@link ANEURALNETWORKS_TENSOR_INT32} for bias (scale set to 0.0,
+     * * * each value scaling is separate and equal to input.scale * filter.scales[channel]).
+     *
+     * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout.
+     * With the default data layout NHWC, the data is stored in the order of:
+     * [batch, height, width, channels]. Alternatively, the data layout could
+     * be NCHW, the data storage order of: [batch, channels, height, width].
+     *
+     * Both explicit padding and implicit padding are supported.
+     *
+     * Inputs (explicit padding):
+     * * 0: A 4-D tensor, of shape [batches, height, width, depth_in],
+     *      specifying the input. Since API level 29, zero batches is supported
+     *      for this tensor.
+     * * 1: A 4-D tensor, of shape
+     *      [depth_out, filter_height, filter_width, depth_in], specifying the
+     *      filter. For tensor of type
+     *      {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL} the channel
+     *      dimension (extraParams.channelQuant.channelDim) must be set to 0.
+     * * 2: A 1-D tensor, of shape [depth_out], specifying the bias. For input
+     *      tensor of type {@link ANEURALNETWORKS_TENSOR_FLOAT32} or
+     *      {@link ANEURALNETWORKS_TENSOR_FLOAT16}, the bias must be of the same
+     *      type. For filter tensor of {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM},
+     *      the bias should be of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint
+     *      of 0 and bias_scale == input_scale * filter_scale. For filter tensor
+     *      of {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL}, the bias
+     *      should be of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint of
+     *      0 and bias_scale of 0. The actual scale of each value 'i' is equal to
+     *      bias_scale[i] = input_scale * filter_scale[i].
+     * * 3: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on
+     *      the left, in the ‘width’ dimension.
+     * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on
+     *      the right, in the ‘width’ dimension.
+     * * 5: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on
+     *      the top, in the ‘height’ dimension.
+     * * 6: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on
+     *      the bottom, in the ‘height’ dimension.
+     * * 7: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when
+     *      walking through input in the ‘width’ dimension.
+     * * 8: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when
+     *      walking through input in the ‘height’ dimension.
+     * * 9: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the
+     *      {@link FuseCode} values. Specifies the activation to
+     *      invoke on the result.
+     * * 10: An optional {@link ANEURALNETWORKS_BOOL} scalar, default to false.
+     *      Set to true to specify NCHW data layout for input0 and output0.
+     *      Available since API level 29.
+     * * 11: An optional {@link ANEURALNETWORKS_INT32} scalar, specifying the dilation
+     *      factor for width. Defaults to 1. If set to k > 1, there will be k-1 skipped
+     *      cells between each filter element on width dimension. If this input is set,
+     *      input 12 (dilation factor for height) must be specified as well.
+     *      Available since API level 29.
+     * * 12: An optional {@link ANEURALNETWORKS_INT32} scalar, specifying the dilation
+     *      factor for height. Defaults to 1. If set to k > 1, there will be k-1 skipped
+     *      cells between each filter element on height dimension. If this input is set,
+     *      input 11 (dilation factor for width) must be specified as well.
+     *      Available since API level 29.
+     *
+     * Inputs (implicit padding):
+     * * 0: A 4-D tensor, of shape [batches, height, width, depth_in],
+     *      specifying the input. Since API level 29, zero batches is supported
+     *      for this tensor.
+     * * 1: A 4-D tensor, of shape
+     *      [depth_out, filter_height, filter_width, depth_in], specifying the
+     *      filter. For tensor of type
+     *      {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL} the channel
+     *      dimension (extraParams.channelQuant.channelDim) must be set to 0.
+     * * 2: A 1-D tensor, of shape [depth_out], specifying the bias. For input
+     *      tensor of type {@link ANEURALNETWORKS_TENSOR_FLOAT32} or
+     *      {@link ANEURALNETWORKS_TENSOR_FLOAT16}, the bias must be of the same
+     *      type. For filter tensor of {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM},
+     *      the bias should be of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint
+     *      of 0 and bias_scale == input_scale * filter_scale. For filter tensor
+     *      of {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL}, the bias
+     *      should be of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint of
+     *      0 and bias_scale of 0. The actual scale of each value 'i' is equal to
+     *      bias_scale[i] = input_scale * filter_scale[i].
+     * * 3: An {@link ANEURALNETWORKS_INT32} scalar, specifying the implicit
+     *      padding scheme, has to be one of the
+     *      {@link PaddingCode} values.
+     * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when
+     *      walking through input in the ‘width’ dimension.
+     * * 5: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when
+     *      walking through input in the ‘height’ dimension.
+     * * 6: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the
+     *      {@link FuseCode} values. Specifies the activation to
+     *      invoke on the result.
+     * * 7: An optional {@link ANEURALNETWORKS_BOOL} scalar, default to false.
+     *      Set to true to specify NCHW data layout for input0 and output0.
+     *      Available since API level 29.
+     * * 8: An optional {@link ANEURALNETWORKS_INT32} scalar, specifying the dilation
+     *      factor for width. Defaults to 1. If set to k > 1, there will be k-1 skipped
+     *      cells between each filter element on width dimension. If this input is set,
+     *      input 9 (dilation factor for height) must be specified as well.
+     *      Available since API level 29.
+     * * 9: An optional {@link ANEURALNETWORKS_INT32} scalar, specifying the dilation
+     *      factor for height. Defaults to 1. If set to k > 1, there will be k-1 skipped
+     *      cells between each filter element on height dimension. If this input is set,
+     *      input 8 (dilation factor for width) must be specified as well.
+     *      Available since API level 29.
+     *
+     * Outputs:
+     * * 0: The output 4-D tensor, of shape
+     *      [batches, out_height, out_width, depth_out]. Before API level 29,
+     *      for output tensor of {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM},
+     *      the following condition must be satisfied:
+     *      output_scale > input_scale * filter_scale
+     *
+     * Available since API level 27.
+     */
+    ANEURALNETWORKS_CONV_2D = 3,
+
+    /**
+     * Performs a depthwise 2-D convolution operation.
+     *
+     * Given an input tensor of shape [batches, height, width, depth_in] and a
+     * filter tensor of shape [1, filter_height, filter_width, depth_out]
+     * containing depth_out convolutional filters of depth 1, DEPTHWISE_CONV
+     * applies a different filter to each input channel (expanding from 1
+     * channel to channel_multiplier channels for each), then concatenates the
+     * results together.
+     *
+     * The output has depth_out = depth_in * depth_multiplier channels.
+     * The output dimensions are functions of the filter dimensions, stride, and
+     * padding.
+     *
+     * The values in the output tensor are computed as:
+     *
+     *     output[b, i, j, k * channel_multiplier + q] =
+     *         sum_{di, dj} (
+     *             input[b, strides[1] * i + di, strides[2] * j + dj, k] *
+     *             filter[1, di, dj, k * channel_multiplier + q]
+     *         ) + bias[k * channel_multiplier + q]
+     *
+     * Supported tensor {@link OperandCode} configurations:
+     * * 32 bit floating point:
+     * * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} for input, filter, output, and bias.
+     *
+     * * Quantized:
+     * * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} for input, filter, and output.
+     * * * {@link ANEURALNETWORKS_TENSOR_INT32} for bias (with scale set to
+     * * * input.scale * filter.scale).
+     *
+     * Available since API level 29:
+     * * 16 bit floating point:
+     * * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} for input, filter, output, and bias.
+     *
+     * * Quantized with symmetric per channel quantization for the filter:
+     * * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} for input, and output.
+     * * * {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL} for filter.
+     * * * {@link ANEURALNETWORKS_TENSOR_INT32} for bias (scale set to 0.0,
+     * * * each value scaling is separate and equal to input.scale * filter.scales[channel]).
+     *
+     * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout.
+     * With the default data layout NHWC, the data is stored in the order of:
+     * [batch, height, width, channels]. Alternatively, the data layout could
+     * be NCHW, the data storage order of: [batch, channels, height, width].
+     *
+     * Both explicit padding and implicit padding are supported.
+     *
+     * Inputs (explicit padding):
+     * * 0: A 4-D tensor, of shape [batches, height, width, depth_in],
+     *      specifying the input.
+     * * 1: A 4-D tensor, of shape [1, filter_height, filter_width, depth_out],
+     *      specifying the filter. For tensor of type
+     *      {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL} the channel
+     *      dimension (extraParams.channelQuant.channelDim) must be set to 3.
+     * * 2: A 1-D tensor, of shape [depth_out], specifying the bias. For input
+     *      tensor of type {@link ANEURALNETWORKS_TENSOR_FLOAT32} or
+     *      {@link ANEURALNETWORKS_TENSOR_FLOAT16}, the bias must be of the same
+     *      type. For filter tensor of {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM},
+     *      the bias should be of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint
+     *      of 0 and bias_scale == input_scale * filter_scale. For filter tensor
+     *      of {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL}, the bias
+     *      should be of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint of
+     *      0 and bias_scale of 0. The actual scale of each value 'i' is equal to
+     *      bias_scale[i] = input_scale * filter_scale[i].
+     * * 3: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on
+     *      the left, in the ‘width’ dimension.
+     * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on
+     *      the right, in the ‘width’ dimension.
+     * * 5: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on
+     *      the top, in the ‘height’ dimension.
+     * * 6: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on
+     *      the bottom, in the ‘height’ dimension.
+     * * 7: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when
+     *      walking through input in the ‘width’ dimension.
+     * * 8: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when
+     *      walking through input in the ‘height’ dimension.
+     * * 9: An {@link ANEURALNETWORKS_INT32} scalar, specifying the depthwise
+     *      multiplier.
+     * * 10: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the
+     *       {@link FuseCode} values. Specifies the activation to
+     *       invoke on the result.
+     * * 11: An optional {@link ANEURALNETWORKS_BOOL} scalar, default to false.
+     *       Set to true to specify NCHW data layout for input0 and output0.
+     *       Available since API level 29.
+     * * 12: An optional {@link ANEURALNETWORKS_INT32} scalar, specifying the dilation
+     *      factor for width. Defaults to 1. If set to k > 1, there will be k-1 skipped
+     *      cells between each filter element on width dimension. If this input is set,
+     *      input 13 (dilation factor for height) must be specified as well.
+     *      Available since API level 29.
+     * * 13: An optional {@link ANEURALNETWORKS_INT32} scalar, specifying the dilation
+     *      factor for height. Defaults to 1. If set to k > 1, there will be k-1 skipped
+     *      cells between each filter element on height dimension. If this input is set,
+     *      input 12 (dilation factor for width) must be specified as well.
+     *      Available since API level 29.
+     *
+     * Inputs (implicit padding):
+     * * 0: A 4-D tensor, of shape [batches, height, width, depth_in],
+     *      specifying the input.
+     * * 1: A 4-D tensor, of shape [1, filter_height, filter_width, depth_out],
+     *      specifying the filter.
+     * * 2: A 1-D tensor, of shape [depth_out], specifying the bias. For input
+     *      tensor of type {@link ANEURALNETWORKS_TENSOR_FLOAT32} or
+     *      {@link ANEURALNETWORKS_TENSOR_FLOAT16}, the bias must be of the same
+     *      type. For filter tensor of {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM},
+     *      the bias should be of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint
+     *      of 0 and bias_scale == input_scale * filter_scale. For filter tensor
+     *      of {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL}, the bias
+     *      should be of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint of
+     *      0 and bias_scale of 0. The actual scale of each value 'i' is equal to
+     *      bias_scale[i] = input_scale * filter_scale[i].
+     * * 3: An {@link ANEURALNETWORKS_INT32} scalar, specifying the implicit
+     *      padding scheme, has to be one of the
+     *      {@link PaddingCode} values.
+     * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when
+     *      walking through input in the ‘width’ dimension.
+     * * 5: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when
+     *      walking through input in the ‘height’ dimension.
+     * * 6: An {@link ANEURALNETWORKS_INT32} scalar, specifying the depthwise
+     *      multiplier.
+     * * 7: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the
+     *      {@link FuseCode} values. Specifies the activation to
+     *      invoke on the result.
+     * * 8: An optional {@link ANEURALNETWORKS_BOOL} scalar, default to false.
+     *      Set to true to specify NCHW data layout for input0 and output0.
+     *      Available since API level 29.
+     * * 9: An optional {@link ANEURALNETWORKS_INT32} scalar, specifying the dilation
+     *      factor for width. Defaults to 1. If set to k > 1, there will be k-1 skipped
+     *      cells between each filter element on width dimension. If this input is set,
+     *      input 10 (dilation factor for height) must be specified as well.
+     *      Available since API level 29.
+     * * 10: An optional {@link ANEURALNETWORKS_INT32} scalar, specifying the dilation
+     *      factor for height. Defaults to 1. If set to k > 1, there will be k-1 skipped
+     *      cells between each filter element on height dimension. If this input is set,
+     *      input 9 (dilation factor for width) must be specified as well.
+     *      Available since API level 29.
+
+     *
+     * Outputs:
+     * * 0: The output 4-D tensor, of shape
+     *      [batches, out_height, out_width, depth_out]. Before API level 29,
+     *      for output tensor of {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM},
+     *      the following condition must be satisfied:
+     *      output_scale > input_scale * filter_scale
+     *
+     * Available since API level 27.
+     */
+    ANEURALNETWORKS_DEPTHWISE_CONV_2D = 4,
+
+    /**
+     * Rearranges data from depth into blocks of spatial data.
+     *
+     * More specifically, this op outputs a copy of the input tensor where
+     * values from the depth dimension are moved in spatial blocks to the height
+     * and width dimensions. The value block_size indicates the input block size
+     * and how the data is moved.
+     *
+     * Chunks of data of size block_size * block_size from depth are rearranged
+     * into non-overlapping blocks of size block_size x block_size.
+     *
+     * The width of the output tensor is input_depth * block_size, whereas the
+     * height is input_height * block_size. The depth of the input tensor must
+     * be divisible by block_size * block_size
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout.
+     * With the default data layout NHWC, the data is stored in the order of:
+     * [batch, height, width, channels]. Alternatively, the data layout could
+     * be NCHW, the data storage order of: [batch, channels, height, width].
+     *
+     * Inputs:
+     * * 0: A 4-D tensor, of shape [batches, height, width, depth_in],
+     *      specifying the input.
+     * * 1: An {@link ANEURALNETWORKS_INT32} scalar, specifying the block_size.
+     *      block_size must be >=1 and block_size * block_size must be a divisor
+     *      of the input depth.
+     * * 2: An optional {@link ANEURALNETWORKS_BOOL} scalar, default to false.
+     *      Set to true to specify NCHW data layout for input0 and output0.
+     *      Available since API level 29.
+     *
+     * Outputs:
+     * * 0: The output 4-D tensor, of shape [batch, height*block_size,
+     *      width*block_size, depth/(block_size*block_size)].
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint must be the same as input0.
+     *
+     * Available since API level 27.
+     */
+    ANEURALNETWORKS_DEPTH_TO_SPACE = 5,
+
+    /**
+     * Dequantizes the input tensor.
+     *
+     * The formula is:
+     *
+     *     output = (input - zeroPoint) * scale.
+     *
+     * Supported input tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL} (since API level 29)
+     *
+     * Supported output tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}.
+     *
+     * Supported tensor rank: up to 4
+     *
+     * Inputs:
+     * * 0: A tensor. Since API level 29, this tensor may be zero-sized.
+     *
+     * Outputs:
+     * * 0: A tensor with the same shape as input0.
+     *
+     * Available since API level 27.
+     */
+    ANEURALNETWORKS_DEQUANTIZE = 6,
+
+    /**
+     * Looks up sub-tensors in the input tensor.
+     *
+     * This operator takes for input a tensor of values (Values) and
+     * a one-dimensional tensor of selection indices (Lookups).
+     * The output tensor is the concatenation of sub-tensors of Values as
+     * selected by Lookups.
+     *
+     * Think of Values as being sliced along its first dimension:
+     * The entries in Lookups select which slices are concatenated together
+     * to create the output tensor.
+     *
+     * For example, if Values has shape of [40, 200, 300] and
+     * Lookups has shape of [3], all three values found in Lookups are
+     * expected to be between 0 and 39. The resulting tensor must
+     * have shape of [3, 200, 300].
+     *
+     * If a value in Lookups is out of bounds, the operation must fail
+     * and an error must be reported.
+     *
+     * Supported value tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_INT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported value tensor rank: from 2
+     *
+     * Inputs:
+     * * 0: Lookups. A 1-D tensor of {@link ANEURALNETWORKS_TENSOR_INT32}.
+     *      The values are indices into the first dimension of Values.
+     * * 1: Values. An n-D tensor, where n >= 2, from which sub-tensors are
+     *      extracted.
+     *
+     * Output:
+     * * 0: A n-D tensor with the same rank and shape as the Values
+     *      tensor, except for the first dimension which has the same size
+     *      as Lookups' only dimension.
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint must be the same as input1.
+     *
+     * Available since API level 27.
+     */
+    ANEURALNETWORKS_EMBEDDING_LOOKUP = 7,
+
+    /**
+     * Computes element-wise floor() on the input tensor.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     *
+     * Supported tensor rank: up to 4
+     *
+     * Inputs:
+     * * 0: A tensor.
+     *
+     * Outputs:
+     * * 0: The output tensor, of the same {@link OperandCode} and dimensions as
+     *      the input tensor.
+     *
+     * Available since API level 27.
+     */
+    ANEURALNETWORKS_FLOOR = 8,
+
+    /**
+     * Denotes a fully (densely) connected layer, which connects all elements
+     * in the input tensor with each element in the output tensor.
+     *
+     * This layer implements the operation:
+     *
+     *     outputs = activation(inputs * weights’ + bias)
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: up to 4.
+     *
+     * Inputs:
+     * * 0: A tensor of at least rank 2, specifying the input. If rank is
+     *      greater than 2, then it gets flattened to a 2-D Tensor. The
+     *      (flattened) 2-D Tensor is reshaped (if necessary) to
+     *      [batch_size, input_size], where "input_size" corresponds to the
+     *      number of inputs to the layer, matching the second dimension of
+     *      weights, and "batch_size" is calculated by dividing the number of
+     *      elements by "input_size". Since API level 29, zero batch_size is
+     *      supported for this tensor.
+     * * 1: A 2-D tensor, specifying the weights, of shape
+     *      [num_units, input_size], where "num_units" corresponds to the number
+     *      of output nodes.
+     * * 2: A 1-D tensor, of shape [num_units], specifying the bias. For input
+     *      tensor of {@link ANEURALNETWORKS_TENSOR_FLOAT32}, the bias should
+     *      also be of {@link ANEURALNETWORKS_TENSOR_FLOAT32}. For input tensor
+     *      of {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, the bias should be
+     *      of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint of 0 and
+     *      bias_scale == input_scale * filter_scale.
+     * * 3: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the
+     *      {@link FuseCode} values. Specifies the activation to
+     *      invoke on the result.
+     *
+     * Outputs:
+     * * 0: The output tensor, of shape [batch_size, num_units]. Before API
+     *      level 29, for output tensor of {@link
+     *      ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, the following condition must
+     *      be satisfied: output_scale > input_scale * filter_scale.
+     *
+     * Available since API level 27.
+     */
+    ANEURALNETWORKS_FULLY_CONNECTED = 9,
+
+    /**
+     * Looks up sub-tensors in the input tensor using a key-value map.
+     *
+     * This operator takes for input a tensor of values (Values),
+     * a one-dimensional tensor of selection values (Lookups) and
+     * a one-dimensional tensor that maps these values to Values
+     * indexes. The output tensor is the concatenation of sub-tensors of
+     * Values as selected by Lookups via Keys.
+     *
+     * Think of Values as being sliced along its outer-most dimension.
+     * The output is a concatenation of selected slices, with one slice
+     * for each entry of Lookups. The slice selected is the one at the
+     * same index as the Maps entry that matches the value in Lookups.
+     *
+     * For a hit, the corresponding sub-tensor of Values is included
+     * in the Output tensor. For a miss, the corresponding sub-tensor in
+     * Output must have zero values.
+     *
+     * For example, if Values has shape of [40, 200, 300],
+     * Keys should have a shape of [40]. If Lookups tensor has shape
+     * of [3], three slices are being concatenated, so the resulting tensor
+     * must have the shape of [3, 200, 300]. If the first entry in Lookups
+     * has the value 123456, that value must be located in Keys tensor.
+     * If the sixth entry of Keys contains 123456, the sixth slice of Values
+     * must be selected. If no entry in Keys has 123456, a slice of zeroes
+     * must be concatenated.
+     *
+     * Supported value tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_INT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported value tensor rank: from 2
+     *
+     * Inputs:
+     * * 0: Lookups. A 1-D {@link ANEURALNETWORKS_TENSOR_INT32} tensor with
+     *      shape [ k ].
+     * * 1: Keys. A 1-D {@link ANEURALNETWORKS_TENSOR_INT32} tensor with shape
+     *      [ n ]; Keys and Values pair represent a map, i.e., the ith element
+     *      in Keys (Keys[i]) is the key to select the ith sub-tensor in Values
+     *      (Values[i]), where 0 <= i <= n-1. Keys tensor *MUST* be sorted in
+     *      ascending order.
+     * * 2: Values. A tensor with shape of [ n, … ]; i.e., the first dimension
+     *      must be n.
+     *
+     * Outputs:
+     * * 0: Output. A tensor with shape [ k …].
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint must be the same as input2.
+     * * 1: Hits. A boolean tensor with shape [ k ] indicates whether the lookup
+     *      hits (True) or not (False).
+     *      Stored as {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} with offset 0
+     *      and scale 1.0f.
+     *      A non-zero byte represents True, a hit. A zero indicates otherwise.
+     *
+     * Available since API level 27.
+     */
+    ANEURALNETWORKS_HASHTABLE_LOOKUP = 10,
+
+    /**
+     * Applies L2 normalization along the depth dimension.
+     *
+     * The values in the output tensor are computed as:
+     *
+     *     output[batch, row, col, channel] =
+     *         input[batch, row, col, channel] /
+     *         sqrt(sum_{c} pow(input[batch, row, col, c], 2))
+     *
+     * For input tensor with rank less than 4, independently normalizes each
+     * 1-D slice along dimension dim.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} (since API level 29)
+     *
+     * Supported tensor rank: up to 4
+     * Tensors with rank less than 4 are only supported since API level 29.
+     *
+     * Inputs:
+     * * 0: An n-D tensor, specifying the tensor to be normalized.
+     * * 1: An optional {@link ANEURALNETWORKS_INT32} scalar, default to -1,
+     *      specifying the dimension normalization would be performed on.
+     *      Negative index is used to specify axis from the end (e.g. -1 for
+     *      the last axis). Must be in the range [-n, n).
+     *      Available since API level 29.
+     *
+     * Outputs:
+     * * 0: A tensor of the same {@link OperandCode} and same shape as input0.
+     *      For {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM},
+     *      the scale must be 1.f / 128 and the zeroPoint must be 128.
+     *
+     * Available since API level 27.
+     */
+    ANEURALNETWORKS_L2_NORMALIZATION = 11,
+
+    /**
+     * Performs an 2-D L2 pooling operation.
+     *
+     * The output dimensions are functions of the filter dimensions, stride, and
+     * padding.
+     *
+     * The values in the output tensor are computed as:
+     *
+     *     output[b, i, j, c] =
+     *         sqrt(sum_{di, dj} pow(input[b, strides[1] * i + di, strides[2] * j + dj, c], 2) /
+     *              sum(1))
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     *
+     * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout.
+     * With the default data layout NHWC, the data is stored in the order of:
+     * [batch, height, width, channels]. Alternatively, the data layout could
+     * be NCHW, the data storage order of: [batch, channels, height, width].
+     *
+     * Both explicit padding and implicit padding are supported.
+     *
+     * Inputs (explicit padding):
+     * * 0: A 4-D tensor, of shape [batches, height, width, depth], specifying
+     *      the input. Since API level 29, zero batches is supported for this
+     *      tensor.
+     * * 1: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on
+     *      the left, in the ‘width’ dimension.
+     * * 2: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on
+     *      the right, in the ‘width’ dimension.
+     * * 3: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on
+     *      the top, in the ‘height’ dimension.
+     * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on
+     *      the bottom, in the ‘height’ dimension.
+     * * 5: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when
+     *      walking through input in the ‘width’ dimension.
+     * * 6: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when
+     *      walking through input in the ‘height’ dimension.
+     * * 7: An {@link ANEURALNETWORKS_INT32} scalar, specifying the filter
+     *      width.
+     * * 8: An {@link ANEURALNETWORKS_INT32} scalar, specifying the filter
+     *      height.
+     * * 9: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the
+     *      {@link FuseCode} values. Specifies the activation to
+     *      invoke on the result.
+     * * 10: An optional {@link ANEURALNETWORKS_BOOL} scalar, default to false.
+     *       Set to true to specify NCHW data layout for input0 and output0.
+     *       Available since API level 29.
+     *
+     * Inputs (implicit padding):
+     * * 0: A 4-D tensor, of shape [batches, height, width, depth], specifying
+     *      the input. Since API level 29, zero batches is supported for this
+     *      tensor.
+     * * 1: An {@link ANEURALNETWORKS_INT32} scalar, specifying the implicit
+     *      padding scheme, has to be one of the
+     *      {@link PaddingCode} values.
+     * * 2: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when
+     *      walking through input in the ‘width’ dimension.
+     * * 3: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when
+     *      walking through input in the ‘height’ dimension.
+     * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the filter
+     *      width.
+     * * 5: An {@link ANEURALNETWORKS_INT32} scalar, specifying the filter
+     *      height.
+     * * 6: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the
+     *      {@link FuseCode} values. Specifies the activation to
+     *      invoke on the result.
+     * * 7: An optional {@link ANEURALNETWORKS_BOOL} scalar, default to false.
+     *      Set to true to specify NCHW data layout for input0 and output0.
+     *      Available since API level 29.
+     *
+     * Outputs:
+     * * 0: The output 4-D tensor, of shape
+     *      [batches, out_height, out_width, depth].
+     *
+     * Available since API level 27.
+     */
+    ANEURALNETWORKS_L2_POOL_2D = 12,
+
+    /**
+     * Applies Local Response Normalization along the depth dimension.
+     *
+     * The 4-D input tensor is treated as a 3-D array of 1-D vectors (along the
+     * last dimension), and each vector is normalized independently. Within a
+     * given vector, each component is divided by the weighted, squared sum of
+     * inputs within depth_radius.
+     *
+     * The output is calculated using this formula:
+     *
+     *     sqr_sum[a, b, c, d] = sum(
+     *         pow(input[a, b, c, d - depth_radius : d + depth_radius + 1], 2))
+     *     output = input / pow((bias + alpha * sqr_sum), beta)
+     *
+     * For input tensor with rank less than 4, independently normalizes each
+     * 1-D slice along specified dimension.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     *
+     * Supported tensor rank: up to 4
+     * Tensors with rank less than 4 are only supported since API level 29.
+     *
+     * Inputs:
+     * * 0: A 4-D tensor, of shape [batches, height, width, depth], specifying
+     *      the input.
+     * * 1: An {@link ANEURALNETWORKS_INT32} scalar, specifying the radius of
+     *      the normalization window.
+     * * 2: A scalar, specifying the bias, must not be zero.
+     *      For input tensor of {@link ANEURALNETWORKS_TENSOR_FLOAT16}, the bias
+     *      value must be of {@link ANEURALNETWORKS_FLOAT16}.
+     *      For input tensor of {@link ANEURALNETWORKS_TENSOR_FLOAT32}, the bias
+     *      value must be of {@link ANEURALNETWORKS_FLOAT32}.
+     * * 3: A scalar, specifying the scale factor, alpha.
+     *      For input tensor of {@link ANEURALNETWORKS_TENSOR_FLOAT16}, the
+     *      alpha value must be of {@link ANEURALNETWORKS_FLOAT16}.
+     *      For input tensor of {@link ANEURALNETWORKS_TENSOR_FLOAT32}, the
+     *      alpha value must be of {@link ANEURALNETWORKS_FLOAT32}.
+     * * 4: A scalar, specifying the exponent, beta.
+     *      For input tensor of {@link ANEURALNETWORKS_TENSOR_FLOAT16}, the beta
+     *      value must be of {@link ANEURALNETWORKS_FLOAT16}.
+     *      For input tensor of {@link ANEURALNETWORKS_TENSOR_FLOAT32}, the beta
+     *      value must be of {@link ANEURALNETWORKS_FLOAT32}.
+     * * 5: An optional {@link ANEURALNETWORKS_INT32} scalar, default to -1,
+     *      specifying the dimension normalization would be performed on.
+     *      Negative index is used to specify axis from the end (e.g. -1 for
+     *      the last axis). Must be in the range [-n, n).
+     *      Available since API level 29.
+     *
+     * Outputs:
+     * * 0: The output tensor of same shape as input0.
+     *
+     * Available since API level 27.
+     */
+    ANEURALNETWORKS_LOCAL_RESPONSE_NORMALIZATION = 13,
+
+    /**
+     * Computes sigmoid activation on the input tensor element-wise.
+     *
+     * The output is calculated using this formula:
+     *
+     *     output = 1 / (1 + exp(-input))
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: up to 4.
+     *
+     * Inputs:
+     * * 0: A tensor, specifying the input. Since API level 29, this tensor may
+     *      be zero-sized.
+     *
+     * Outputs:
+     * * 0: The output tensor of same shape as input0.
+     *      For {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM},
+     *      the scale must be 1.f / 256 and the zeroPoint must be 0.
+     *
+     * Available since API level 27.
+     */
+    ANEURALNETWORKS_LOGISTIC = 14,
+
+    /**
+     * Projects an input to a bit vector via locality senstive hashing.
+     *
+     * Supported input tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_INT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported input tensor rank: from 1
+     *
+     * Inputs:
+     * * 0: Hash functions. Dim.size == 2, DataType: Float.
+     *      Tensor[0].Dim[0]: Number of hash functions.
+     *      Tensor[0].Dim[1]: Number of projected output bits generated by each
+     *      hash function.
+     *      If the projection type is Sparse:
+     *      Tensor[0].Dim[1] + ceil(log2(Tensor[0].Dim[0])) <= 32
+     *
+     * * 1: Input. Dim.size >= 1, no restriction on DataType.
+     * * 2: Weight. Optional. Dim.size == 1, DataType: Float.
+     *      If not set, each input element is considered to have the same weight
+     *      of 1.0.
+     *      Tensor[1].Dim[0] == Tensor[2].Dim[0]
+     * * 3: Type:
+     *        Sparse:
+     *          Value LSHProjectionType_SPARSE(=3) (since API level 29).
+     *          Computed bit vector is considered to be sparse.
+     *          Each output element is an int32 made up of multiple bits
+     *          computed from hash functions.
+     *
+     *          NOTE: To avoid collisions across hash functions, an offset value
+     *          of k * (1 << Tensor[0].Dim[1]) will be added to each signature,
+     *          where k is the index of the hash function.
+     *
+     *          Value LSHProjectionType_SPARSE_DEPRECATED(=1).
+     *          Legacy behavior that does not include the offset value.
+     *
+     *        Dense:
+     *          Value LSHProjectionType_DENSE(=2).
+     *          Computed bit vector is considered to be dense. Each output
+     *          element represents a bit and can take the value of either
+     *          0 or 1.
+     *
+     * Outputs:
+     * * 0: If the projection type is Sparse:
+     *      Output.Dim == { Tensor[0].Dim[0] }
+     *      A tensor of int32 that represents hash signatures,
+     *
+     *      If the projection type is Dense:
+     *      Output.Dim == { Tensor[0].Dim[0] * Tensor[0].Dim[1] }
+     *      A flattened tensor that represents projected bit vectors.
+     *
+     * Available since API level 27.
+     * The offset value for sparse projections was added in API level 29.
+     */
+    ANEURALNETWORKS_LSH_PROJECTION = 15,
+
+    /**
+     * Performs a single time step in a Long Short-Term Memory (LSTM) layer
+     *
+     * The LSTM operation is described by the following equations.
+     *
+     * \f{eqnarray*}{
+     * i_t =& \sigma(W_{xi}x_t+W_{hi}h_{t-1}+W_{ci}C_{t-1}+b_i) & \\
+     * f_t =& \sigma(W_{xf}x_t+W_{hf}h_{t-1}+W_{cf}C_{t-1}+b_f) & \\
+     * C_t =& clip(f_t \odot C_{t-1} + i_t \odot
+     *        g(W_{xc}x_t+W_{hc}h_{t-1}+b_c),\ t_{cell}) & \\
+     * o_t =& \sigma(W_{xo}x_t+W_{ho}h_{t-1}+W_{co}C_t+b_o) & \\
+     *      & & \\
+     *      & clip(W_{proj}(o_t \odot g(C_t))+b_{proj},\ t_{proj})
+     *      & if\ there\ is\ a\ projection; \\
+     * h_t =& & \\
+     *      & o_t \odot g(C_t) & otherwise. \\
+     * \f}
+     * Where:
+     * * \f$x_t\f$ is the input,
+     * * \f$i_t\f$ is the input gate,
+     * * \f$f_t\f$ is the forget gate,
+     * * \f$C_t\f$ is the cell state,
+     * * \f$o_t\f$ is the output,
+     * * \f$h_t\f$ is the output state,
+     * * \f$\sigma\f$ is the logistic sigmoid function,
+     * * \f$g\f$ is the cell input and cell output activation function, usually
+     *   \f$tahn\f$,
+     * * \f$W_{xi}\f$ is the input-to-input weight matrix,
+     * * \f$W_{hi}\f$ is the recurrent to input weight matrix,
+     * * \f$W_{ci}\f$ is the cell-to-input weight matrix,
+     * * \f$b_i\f$ is the input gate bias,
+     * * \f$W_{xf}\f$ is the input-to-forget weight matrix,
+     * * \f$W_{hf}\f$ is the recurrent-to-forget weight matrix,
+     * * \f$W_{cf}\f$ is the cell-to-forget weight matrix,
+     * * \f$b_f\f$ is the forget gate bias,
+     * * \f$W_{xc}\f$ is the input-to-cell weight matrix,
+     * * \f$W_{hc}\f$ is the recurrent-to-cell weight matrix,
+     * * \f$b_c\f$ is the cell bias,
+     * * \f$W_{xo}\f$ is the input-to-output weight matrix,
+     * * \f$W_{ho}\f$ is the recurrent-to-output weight matrix,
+     * * \f$W_{co}\f$ is the cell-to-output weight matrix,
+     * * \f$b_o\f$ is the output gate bias,
+     * * \f$W_{proj}\f$ is the projection weight matrix,
+     * * \f$b_{proj}\f$ is the projection bias,
+     * * \f$t_{cell}\f$ is the threshold for clipping the cell state, and
+     * * \f$t_{proj}\f$ is the threshold for clipping the projected output.
+     * * \f$\odot\f$ is the
+     *   <a href="https://en.wikipedia.org/wiki/Hadamard_product_(matrices)">
+     *   Hadamard product</a> that takes two matrices and produces another
+     *   matrix, each element of which is the product of the corresponding
+     *   elements of the input matrices.
+     *
+     * Since API level 29 LSTM supports layer normalization.
+     * In case layer normalization is used, the inputs to internal activation
+     * functions (sigmoid and \f$g\f$) are normalized, rescaled and recentered
+     * following an approach from section 3.1 from
+     * https://arxiv.org/pdf/1607.06450.pdf
+     *
+     * The operation has the following independently optional inputs:
+     * * The cell-to-input weights (\f$W_{ci}\f$), cell-to-forget weights
+     *   (\f$W_{cf}\f$) and cell-to-output weights (\f$W_{co}\f$) either all
+     *   have values or neither of them have values (i.e., all set to null). If
+     *   they have values, the peephole optimization is used.
+     * * The input-to-input weights (\f$W_{xi}\f$), recurrent-to-input weights
+     *   (\f$W_{hi}\f$) and input gate bias (\f$b_i\f$) either all have values,
+     *   or none of them have values. If they have no values, coupling of input
+     *   and forget gates (CIFG) is used, in which case the input gate
+     *   (\f$i_t\f$) is calculated using the following equation instead.
+     *   \f{eqnarray*}{
+     *   i_t = 1 - f_t
+     *   \f}
+     *   In case peephole optimization is used and CIFG is not used
+     *   cell-to-input (\f$W_{ci}\f$) weights must be present. Otherwise, the
+     *   cell-to-input weights must have no value.
+     * * The projection weights (\f$W_{proj}\f$) is required only for the
+     *   recurrent projection layer, and should otherwise have no value.
+     * * The projection bias (\f$b_{proj}\f$) may (but not required to) have a
+     *   value if the recurrent projection layer exists, and should otherwise
+     *   have no value.
+     * * (API level >= 29) The four layer normalization weights either all have
+     *   values or none of them have values. Additionally, if CIFG is used,
+     *   input layer normalization weights tensor is omitted and the other layer
+     *   normalization weights either all have values or none of them have
+     *   values. Layer normalization is used when the values of all the layer
+     *   normalization weights are present.
+     *
+     * References:
+     *
+     * The default non-peephole non-CIFG implementation is based on:
+     * http://www.bioinf.jku.at/publications/older/2604.pdf
+     * S. Hochreiter and J. Schmidhuber. "Long Short-Term Memory". Neural
+     * Computation, 9(8):1735-1780, 1997.
+     *
+     * The peephole implementation and projection layer is based on:
+     * https://research.google.com/pubs/archive/43905.pdf
+     * Hasim Sak, Andrew Senior, and Francoise Beaufays. "Long short-term memory
+     * recurrent neural network architectures for large scale acoustic
+     * modeling." INTERSPEECH, 2014.
+     * (However, the concept of peephole optimization was introduced in work
+     * prior to this paper.)
+     *
+     * The coupling of input and forget gate (CIFG) is based on:
+     * http://arxiv.org/pdf/1503.04069.pdf
+     * Greff et al. "LSTM: A Search Space Odyssey"
+     *
+     * The layer normalization is based on:
+     * https://arxiv.org/pdf/1607.06450.pdf
+     * Jimmy Ba et al. "Layer Normalization"
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     *
+     * All input and output tensors must be of the same type.
+     *
+     * Inputs:
+     * * 0: The input (\f$x_t\f$).
+     *      A 2-D tensor of shape [batch_size, input_size], where “batch_size”
+     *      corresponds to the batching dimension, and “input_size” is the size
+     *      of the input.
+     * * 1: The input-to-input weights (\f$W_{xi}\f$). Optional.
+     *      A 2-D tensor of shape [num_units, input_size], where “num_units”
+     *      corresponds to the number of cell units.
+     * * 2: The input-to-forget weights (\f$W_{xf}\f$).
+     *      A 2-D tensor of shape [num_units, input_size].
+     * * 3: The input-to-cell weights (\f$W_{xc}\f$).
+     *      A 2-D tensor of shape [num_units, input_size].
+     * * 4: The input-to-output weights (\f$W_{xo}\f$).
+     *      A 2-D tensor of shape [num_units, input_size].
+     * * 5: The recurrent-to-input weights (\f$W_{hi}\f$). Optional.
+     *      A 2-D tensor of shape [num_units, output_size], where “output_size”
+     *      corresponds to either the number of cell units (i.e., “num_units”),
+     *      or the second dimension of the “projection_weights”, if defined.
+     * * 6: The recurrent-to-forget weights (\f$W_{hf}\f$).
+     *      A 2-D tensor of shape [num_units, output_size].
+     * * 7: The recurrent-to-cell weights (\f$W_{hc}\f$).
+     *      A 2-D tensor of shape [num_units, output_size].
+     * * 8: The recurrent-to-output weights (\f$W_{ho}\f$).
+     *      A 2-D tensor of shape [num_units, output_size].
+     * * 9: The cell-to-input weights (\f$W_{ci}\f$). Optional.
+     *      A 1-D tensor of shape [num_units].
+     * * 10:The cell-to-forget weights (\f$W_{cf}\f$). Optional.
+     *      A 1-D tensor of shape [num_units].
+     * * 11:The cell-to-output weights (\f$W_{co}\f$). Optional.
+     *      A 1-D tensor of shape [num_units].
+     * * 12:The input gate bias (\f$b_i\f$). Optional.
+     *      A 1-D tensor of shape [num_units].
+     * * 13:The forget gate bias (\f$b_f\f$).
+     *      A 1-D tensor of shape [num_units].
+     * * 14:The cell bias (\f$b_c\f$).
+     *      A 1-D tensor of shape [num_units].
+     * * 15:The output gate bias (\f$b_o\f$).
+     *      A 1-D tensor of shape [num_units].
+     * * 16:The projection weights (\f$W_{proj}\f$). Optional.
+     *      A 2-D tensor of shape [output_size, num_units].
+     * * 17:The projection bias (\f$b_{proj}\f$). Optional.
+     *      A 1-D tensor of shape [output_size].
+     * * 18:The output state (in) (\f$h_{t-1}\f$).
+     *      A 2-D tensor of shape [batch_size, output_size].
+     * * 19:The cell state (in) (\f$C_{t-1}\f$).
+     *      A 2-D tensor of shape [batch_size, num_units].
+     * * 20:The activation function (\f$g\f$).
+     *      A value indicating the activation function:
+     *      <ul>
+     *      <li>0: None;
+     *      <li>1: Relu;
+     *      <li>3: Relu6;
+     *      <li>4: Tanh;
+     *      <li>6: Sigmoid.
+     *      </ul>
+     * * 21:The clipping threshold (\f$t_{cell}\f$) for the cell state, such
+     *      that values are bound within [-cell_clip, cell_clip]. If set to 0.0
+     *      then clipping is disabled.
+     *      Until API level 29 this scalar must be of type {@link
+     *      ANEURALNETWORKS_FLOAT32}. Since API level 29, if all the input
+     *      tensors have type {@link ANEURALNETWORKS_TENSOR_FLOAT32}, this
+     *      scalar must be of the type {@link ANEURALNETWORKS_FLOAT32},
+     *      otherwise if all the input tensors have the type {@link
+     *      ANEURALNETWORKS_TENSOR_FLOAT16}, this scalar must be of type {@link
+     *      ANEURALNETWORKS_FLOAT16}.
+     * * 22:The clipping threshold (\f$t_{proj}\f$) for the output from the
+     *      projection layer, such that values are bound within
+     *      [-proj_clip, proj_clip]. If set to 0.0 then clipping is disabled.
+     *      Until API level 29 this scalar must be of type {@link
+     *      ANEURALNETWORKS_FLOAT32}. Since API level 29, if all the input
+     *      tensors have type {@link ANEURALNETWORKS_TENSOR_FLOAT32}, this
+     *      scalar must be of the type {@link ANEURALNETWORKS_FLOAT32},
+     *      otherwise if all the input tensors have the type {@link
+     *      ANEURALNETWORKS_TENSOR_FLOAT16}, this scalar must be of type {@link
+     *      ANEURALNETWORKS_FLOAT16}.
+     * Since API level 29 there are additional inputs to this op:
+     * * 23:The input layer normalization weights.
+     *      A 1-D tensor of shape [num_units]. Used to rescale normalized inputs
+     *      to activation at input gate.
+     * * 24:The forget layer normalization weights.
+     *      A 1-D tensor of shape [num_units]. Used to rescale normalized inputs
+     *      to activation at forget gate.
+     * * 25:The cell layer normalization weights.
+     *      A 1-D tensor of shape [num_units]. Used to rescale normalized inputs
+     *      to activation at cell gate.
+     * * 26:The output layer normalization weights.
+     *      A 1-D tensor of shape [num_units]. Used to rescale normalized inputs
+     *      to activation at output gate.
+     *
+     * Outputs:
+     * * 0: The scratch buffer.
+     *      A 2-D tensor of shape [batch_size, num_units * 3] with CIFG, or
+     *      [batch_size, num_units * 4] without CIFG.
+     * * 1: The output state (out) (\f$h_t\f$).
+     *      A 2-D tensor of shape [batch_size, output_size].
+     * * 2: The cell state (out) (\f$C_t\f$).
+     *      A 2-D tensor of shape [batch_size, num_units].
+     * * 3: The output (\f$o_t\f$).
+     *      A 2-D tensor of shape [batch_size, output_size]. This is effectively
+     *      the same as the current “output state (out)” value.
+     *
+     * Available since API level 27.
+     */
+    ANEURALNETWORKS_LSTM = 16,
+
+    /**
+     * Performs an 2-D max pooling operation.
+     *
+     * The output dimensions are functions of the filter dimensions, stride, and
+     * padding.
+     *
+     * The values in the output tensor are computed as:
+     *
+     *     output[b, i, j, channel] =
+     *         max_{di, dj} (
+     *             input[b, strides[1] * i + di, strides[2] * j + dj, channel]
+     *         )
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout.
+     * With the default data layout NHWC, the data is stored in the order of:
+     * [batch, height, width, channels]. Alternatively, the data layout could
+     * be NCHW, the data storage order of: [batch, channels, height, width].
+     *
+     * Both explicit padding and implicit padding are supported.
+     *
+     * Inputs (explicit padding):
+     * * 0: A 4-D tensor, of shape [batches, height, width, depth], specifying
+     *      the input. Since API level 29, zero batches is supported for this
+     *      tensor.
+     * * 1: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on
+     *      the left, in the ‘width’ dimension.
+     * * 2: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on
+     *      the right, in the ‘width’ dimension.
+     * * 3: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on
+     *      the top, in the ‘height’ dimension.
+     * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on
+     *      the bottom, in the ‘height’ dimension.
+     * * 5: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when
+     *      walking through input in the ‘width’ dimension.
+     * * 6: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when
+     *      walking through input in the ‘height’ dimension.
+     * * 7: An {@link ANEURALNETWORKS_INT32} scalar, specifying the filter
+     *      width.
+     * * 8: An {@link ANEURALNETWORKS_INT32} scalar, specifying the filter
+     *      height.
+     * * 9: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the
+     *      {@link FuseCode} values. Specifies the activation to
+     *      invoke on the result.
+     * * 10: An optional {@link ANEURALNETWORKS_BOOL} scalar, default to false.
+     *       Set to true to specify NCHW data layout for input0 and output0.
+     *       Available since API level 29.
+     *
+     * Inputs (implicit padding):
+     * * 0: A 4-D tensor, of shape [batches, height, width, depth], specifying
+     *      the input. Since API level 29, zero batches is supported for this
+     *      tensor.
+     * * 1: An {@link ANEURALNETWORKS_INT32} scalar, specifying the implicit
+     *      padding scheme, has to be one of the
+     *      {@link PaddingCode} values.
+     * * 2: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when
+     *      walking through input in the ‘width’ dimension.
+     * * 3: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when
+     *      walking through input in the ‘height’ dimension.
+     * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the filter
+     *      width.
+     * * 5: An {@link ANEURALNETWORKS_INT32} scalar, specifying the filter
+     *      height.
+     * * 6: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the
+     *      {@link FuseCode} values. Specifies the activation to
+     *      invoke on the result.
+     * * 7: An optional {@link ANEURALNETWORKS_BOOL} scalar, default to false.
+     *      Set to true to specify NCHW data layout for input0 and output0.
+     *      Available since API level 29.
+     *
+     * Outputs:
+     * * 0: The output 4-D tensor, of shape
+     *      [batches, out_height, out_width, depth].
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint must be the same as input0.
+     *
+     * Available since API level 27.
+     */
+    ANEURALNETWORKS_MAX_POOL_2D = 17,
+
+    /**
+     * Multiplies two tensors, element-wise.
+     *
+     * Takes two input tensors of identical {@link OperandCode} and compatible
+     * dimensions. The output is the product of both input tensors, optionally
+     * modified by an activation function.
+     *
+     * Two dimensions are compatible when:
+     *     1. they are equal, or
+     *     2. one of them is 1
+     *
+     * The size of the resulting output is the maximum size along each dimension
+     * of the input operands. It starts with the trailing dimensions, and works
+     * its way forward.
+     *
+     * Since API level 29, generic zero-sized input tensor is supported. Zero
+     * dimension is only compatible with 0 or 1. The size of the output
+     * dimension is zero if either of corresponding input dimension is zero.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: up to 4
+     *
+     * Inputs:
+     * * 0: A tensor.
+     * * 1: A tensor of the same {@link OperandCode}, and compatible dimensions
+     *      as input0.
+     * * 2: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the
+     *      {@link FuseCode} values. Specifies the activation to
+     *      invoke on the result.
+     *
+     * Outputs:
+     * * 0: The product, a tensor of the same {@link OperandCode} as input0.
+     *      For output tensor of {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM},
+     *      the following condition must be satisfied:
+     *      output_scale > input1_scale * input2_scale.
+     *
+     * Available since API level 27.
+     */
+    ANEURALNETWORKS_MUL = 18,
+
+    /**
+     * Computes rectified linear activation on the input tensor element-wise.
+     *
+     * The output is calculated using this formula:
+     *
+     *     output = max(0, input)
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: up to 4.
+     *
+     * Inputs:
+     * * 0: A tensor, specifying the input. Since API level 29, this tensor may
+     *      be zero-sized.
+     *
+     * Outputs:
+     * * 0: The output tensor of same shape as input0.
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint must be the same as input0.
+     *
+     * Available since API level 27.
+     */
+    ANEURALNETWORKS_RELU = 19,
+
+    /**
+     * Computes rectified linear 1 activation on the input tensor element-wise.
+     *
+     * The output is calculated using this formula:
+     *
+     *     output = min(1.f, max(-1.f, input))
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: up to 4.
+     *
+     * Inputs:
+     * * 0: A tensor, specifying the input. Since API level 29, this tensor may
+     *      be zero-sized.
+     *
+     * Outputs:
+     * * 0: The output tensor of the same shape as input0.
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint must be the same as input0.
+     *
+     * Available since API level 27.
+     */
+    ANEURALNETWORKS_RELU1 = 20,
+
+    /**
+     * Computes rectified linear 6 activation on the input tensor element-wise.
+     *
+     * The output is calculated using this formula:
+     *
+     *     output = min(6, max(0, input))
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: up to 4.
+     *
+     * Inputs:
+     * * 0: A tensor, specifying the input. Since API level 29, this tensor may
+     *      be zero-sized.
+     *
+     * Outputs:
+     * * 0: The output tensor of same shape as input0.
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint must be the same as input0.
+     *
+     * Available since API level 27.
+     */
+    ANEURALNETWORKS_RELU6 = 21,
+
+    /**
+     * Reshapes a tensor.
+     *
+     * Given tensor, this operation returns a tensor that has the same values as
+     * tensor, but with a newly specified shape.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: up to 4.
+     *
+     * Inputs:
+     * * 0: A tensor, specifying the tensor to be reshaped.
+     * * 1: A 1-D tensor of {@link ANEURALNETWORKS_TENSOR_INT32}, defining the
+     *      shape of the output tensor. The number of elements implied by shape
+     *      must be the same as the number of elements in the input tensor.
+     *
+     *      If one component of shape is the special value -1, the size of that
+     *      dimension is computed so that the total size remains constant. In
+     *      particular, a shape of [-1] flattens into 1-D. At most one component
+     *      of shape can be -1.
+     *
+     * Outputs:
+     * * 0: The output tensor, of shape specified by the input shape.
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint must be the same as input0.
+     *
+     * Available since API level 27.
+     */
+    ANEURALNETWORKS_RESHAPE = 22,
+
+    /**
+     * Resizes images to given size using the bilinear interpretation.
+     *
+     * Resized images must be distorted if their output aspect ratio is not the
+     * same as input aspect ratio. The corner pixels of output may not be the
+     * same as corner pixels of input.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} (since API level 29)
+     *
+     * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout.
+     * With the default data layout NHWC, the data is stored in the order of:
+     * [batch, height, width, channels]. Alternatively, the data layout could
+     * be NCHW, the data storage order of: [batch, channels, height, width].
+     *
+     * Both resizing by shape and resizing by scale are supported.
+     *
+     * Inputs (resizing by shape):
+     * * 0: A 4-D tensor, of shape [batches, height, width, depth], specifying
+     *      the input. Since API level 29, zero batches is supported for this
+     *      tensor.
+     * * 1: An {@link ANEURALNETWORKS_INT32} scalar, specifying the output
+     *      width of the output tensor.
+     * * 2: An {@link ANEURALNETWORKS_INT32} scalar, specifying the output
+     *      height of the output tensor.
+     * * 3: An optional {@link ANEURALNETWORKS_BOOL} scalar, default to false.
+     *      Set to true to specify NCHW data layout for input0 and output0.
+     *      Available since API level 29.
+     *
+     * Inputs (resizing by scale, since API level 29):
+     * * 0: A 4-D tensor, of shape [batches, height, width, depth], specifying
+     *      the input. Zero batches is supported for this tensor.
+     * * 1: A scalar, specifying width_scale, the scaling factor of the width
+     *      dimension from the input tensor to the output tensor. The output
+     *      width is calculated as new_width = floor(width * width_scale).
+     *      The scalar must be of {@link ANEURALNETWORKS_FLOAT16} if input0 is
+     *      of {@link ANEURALNETWORKS_TENSOR_FLOAT16} and of
+     *      {@link ANEURALNETWORKS_FLOAT32} otherwise.
+     * * 2: A scalar, specifying height_scale, the scaling factor of the height
+     *      dimension from the input tensor to the output tensor. The output
+     *      height is calculated as new_height = floor(height * height_scale).
+     *      The scalar must be of {@link ANEURALNETWORKS_FLOAT16} if input0 is
+     *      of {@link ANEURALNETWORKS_TENSOR_FLOAT16} and of
+     *      {@link ANEURALNETWORKS_FLOAT32} otherwise.
+     * * 3: An optional {@link ANEURALNETWORKS_BOOL} scalar, default to false.
+     *      Set to true to specify NCHW data layout for input0 and output0.
+     *
+     * Outputs:
+     * * 0: The output 4-D tensor, of shape
+     *      [batches, new_height, new_width, depth].
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint must be the same as input0.
+     *
+     * Available since API level 27.
+     */
+    ANEURALNETWORKS_RESIZE_BILINEAR = 23,
+
+    /**
+     * A basic recurrent neural network layer.
+     *
+     * This layer implements the operation:
+     * outputs = state = activation(inputs * input_weights +
+     *                              state * recurrent_weights + bias)
+     *
+     * Where:
+     * * “input_weights” is a weight matrix that multiplies the inputs;
+     * * “recurrent_weights” is a weight matrix that multiplies the current
+     *    “state” which itself is the output from the previous time step
+     *    computation;
+     * * “bias” is a bias vector (added to each output vector in the batch);
+     * * “activation” is the function passed as the “fused_activation_function”
+     *   argument (if not “NONE”).
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     *
+     * The input tensors must all be the same type.
+     *
+     * Inputs:
+     * * 0: input.
+     *      A 2-D tensor of shape [batch_size, input_size], where “batch_size”
+     *      corresponds to the batching dimension, and “input_size” is the size
+     *      of the input.
+     * * 1: weights.
+     *      A 2-D tensor of shape [num_units, input_size], where “num_units”
+     *      corresponds to the number of units.
+     * * 2: recurrent_weights.
+     *      A 2-D tensor of shape [num_units, num_units], with columns
+     *      corresponding to the weights from each unit.
+     * * 3: bias.
+     *      A 1-D tensor of shape [num_units].
+     * * 4: hidden state (in).
+     *      A 2-D tensor of shape [batch_size, num_units].
+     * * 5: fused_activation_function.
+     *      An optional {@link FuseCode} value indicating the
+     *      activation function. If “NONE” is specified then it results in a
+     *      linear activation.
+     *
+     * Outputs:
+     * * 0: hidden state (out).
+     *      A 2-D tensor of shape [batch_size, num_units].
+     *
+     * * 1: output.
+     *      A 2-D tensor of shape [batch_size, num_units]. This is effectively
+     *      the same as the current state value.
+     *
+     * Available since API level 27.
+     */
+    ANEURALNETWORKS_RNN = 24,
+
+    /**
+     * Computes the softmax activation on the input tensor element-wise, per
+     * batch, by normalizing the input vector so the maximum coefficient is
+     * zero.
+     *
+     * The output is calculated using this formula:
+     *
+     *     output[batch, i] =
+     *         exp((input[batch, i] - max(input[batch, :])) * beta) /
+     *         sum_{k}{exp((input[batch, k] - max(input[batch, :])) * beta)}
+     *
+     * For input tensor with rank other than 2, the activation will be applied
+     * independently on each 1-D slice along specified dimension.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: up to 4.
+     * Tensors with rank other than 2 or 4 are only supported since API level 29.
+     *
+     * Inputs:
+     * * 0: A 2-D or 4-D tensor, specifying the tensor to be reshaped. Since
+     *      API level 29, this tensor may be zero-sized.
+     * * 1: A scalar, specifying the positive scaling factor for the exponent,
+     *      beta. If input0 is of {@link ANEURALNETWORKS_TENSOR_FLOAT32} or
+     *      {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, the scalar must be of
+     *      {@link ANEURALNETWORKS_FLOAT32}. If input0 is of {@link
+     *      ANEURALNETWORKS_TENSOR_FLOAT16}, then the scalar must be of {@link
+     *      ANEURALNETWORKS_FLOAT16}.
+     * * 2: An optional {@link ANEURALNETWORKS_INT32} scalar, default to -1,
+     *      specifying the dimension the activation would be performed on.
+     *      Negative index is used to specify axis from the end (e.g. -1 for
+     *      the last axis). Must be in the range [-n, n).
+     *      Available since API level 29.
+     *
+     * Outputs:
+     * * 0: The output tensor of same shape as input0.
+     *      For {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM},
+     *      the scale must be 1.f / 256 and the zeroPoint must be 0.
+     *
+     * Available since API level 27.
+     */
+    ANEURALNETWORKS_SOFTMAX = 25,
+
+    /**
+     * Rearranges blocks of spatial data, into depth.
+     *
+     * More specifically, this op outputs a copy of the input tensor where
+     * values from the height and width dimensions are moved to the depth
+     * dimension. The value block_size indicates the input block size and how
+     * the data is moved.
+     *
+     * Chunks of data of size block_size * block_size from depth are rearranged
+     * into non-overlapping blocks of size block_size x block_size.
+     *
+     * The depth of the output tensor is input_depth * block_size * block_size.
+     * The input tensor's height and width must be divisible by block_size.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout.
+     * With the default data layout NHWC, the data is stored in the order of:
+     * [batch, height, width, channels]. Alternatively, the data layout could
+     * be NCHW, the data storage order of: [batch, channels, height, width].
+     *
+     * Inputs:
+     * * 0: A 4-D tensor, of shape [batches, height, width, depth_in],
+     *      specifying the input.
+     * * 1: An {@link ANEURALNETWORKS_INT32} scalar, specifying the block_size.
+     *      block_size must be >=1 and block_size must be a divisor of both the
+     *      input height and width.
+     * * 2: An optional {@link ANEURALNETWORKS_BOOL} scalar, default to false.
+     *      Set to true to specify NCHW data layout for input0 and output0.
+     *      Available since API level 29.
+     *
+     * Outputs:
+     * * 0: The output 4-D tensor, of shape [batches, height/block_size,
+     *      width/block_size, depth_in*block_size*block_size].
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint must be the same as input0.
+     *
+     * Available since API level 27.
+     */
+    ANEURALNETWORKS_SPACE_TO_DEPTH = 26,
+
+    /**
+     * SVDF op is a kind of stateful layer derived from the notion that a
+     * densely connected layer that's processing a sequence of input frames can
+     * be approximated by using a singular value decomposition of each of its
+     * nodes. The implementation is based on:
+     *
+     * https://research.google.com/pubs/archive/43813.pdf
+     *
+     * P. Nakkiran, R. Alvarez, R. Prabhavalkar, C. Parada.
+     * “Compressing Deep Neural Networks using a Rank-Constrained Topology”.
+     * INTERSPEECH, 2015.
+     *
+     * It processes the incoming input using a 2-stage filtering mechanism:
+     * * stage 1 performs filtering on the "features" dimension, whose outputs
+     *   get pushed into a memory of fixed-size memory_size.
+     * * stage 2 performs filtering on the "time" dimension of the memory_size
+     *   memoized outputs of stage 1.
+     *
+     * Specifically, for rank 1, this layer implements the operation:
+     *
+     *     memory = push(conv1d(inputs, weights_feature, feature_dim,
+     *                          "ANEURALNETWORKS_PADDING_VALID"));
+     *     outputs = activation(memory * weights_time + bias);
+     *
+     * Where:
+     * * “weights_feature” is a weights matrix that processes the inputs (by
+     *   convolving the input with every “feature filter”), and whose outputs
+     *   get pushed, stacked in order, into the fixed-size “memory” (the oldest
+     *   entry gets dropped);
+     * * “weights_time” is a weights matrix that processes the “memory” (by a
+     *   batched matrix multiplication on the num_units);
+     * * “bias” is an optional bias vector (added to each output vector in the
+     *   batch); and
+     * * “activation” is the function passed as the “fused_activation_function”
+     *   argument (if not “NONE”).
+     *
+     * Each rank adds a dimension to the weights matrices by means of stacking
+     * the filters.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     *
+     * All input tensors must be the same type.
+     *
+     * Inputs:
+     * * 0: input.
+     *      A 2-D tensor of shape [batch_size, input_size], where “batch_size”
+     *      corresponds to the batching dimension, and “input_size” is the size
+     *      of the input.
+     * * 1: weights_feature.
+     *      A 2-D tensor of shape [num_units, input_size], where “num_units”
+     *      corresponds to the number of units.
+     * * 2: weights_time.
+     *      A 2-D tensor of shape [num_units, memory_size], where “memory_size”
+     *      corresponds to the fixed-size of the memory.
+     * * 3: bias.
+     *      An optional 1-D tensor of shape [num_units].
+     * * 4: state (in).
+     *      A 2-D tensor of shape [batch_size, (memory_size - 1) * num_units * rank].
+     * * 5: rank.
+     *      The rank of the SVD approximation.
+     * * 6: fused_activation_function.
+     *      An optional {@link FuseCode} value indicating the
+     *      activation function. If “NONE” is specified then it results in a
+     *      linear activation.
+     *
+     * Outputs:
+     * * 0: state (out).
+     *      A 2-D tensor of the same {@link OperandCode} as the inputs, with shape
+     *      [batch_size, (memory_size - 1) * num_units * rank].
+     * * 1: output.
+     *      A 2-D tensor of the same {@link OperandCode} as the inputs, with shape
+     *      [batch_size, num_units].
+     *
+     * Available since API level 27.
+     */
+    ANEURALNETWORKS_SVDF = 27,
+
+    /**
+     * Computes hyperbolic tangent of input tensor element-wise.
+     *
+     * The output is calculated using this formula:
+     *
+     *     output = tanh(input)
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} (since API level 29)
+     *
+     * Supported tensor rank: up to 4.
+     *
+     * Inputs:
+     * * 0: A tensor, specifying the input. Since API level 29, this tensor may
+     *      be zero-sized.
+     *
+     * Outputs:
+     * * 0: The output tensor of same shape as input0.
+     *      For {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM},
+     *      the scale must be 1.f / 128 and the zeroPoint must be 128.
+     *
+     * Available since API level 27.
+     */
+    ANEURALNETWORKS_TANH = 28,
+
+    // Operations below are available since API level 28.
+
+    // TODO: make the description easier to understand.
+    /**
+     * BatchToSpace for N-dimensional tensors.
+     *
+     * This operation reshapes the batch dimension (dimension 0) into M + 1
+     * dimensions of shape block_shape + [batch], interleaves these blocks back
+     * into the grid defined by the spatial dimensions [1, ..., M], to obtain a
+     * result with the same rank as the input.
+     *
+     * This is the reverse of SpaceToBatch.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout.
+     * With the default data layout NHWC, the data is stored in the order of:
+     * [batch, height, width, channels]. Alternatively, the data layout could
+     * be NCHW, the data storage order of: [batch, channels, height, width].
+     *
+     * Inputs:
+     * * 0: An n-D tensor, specifying the tensor to be reshaped
+     * * 1: A 1-D Tensor of {@link ANEURALNETWORKS_TENSOR_INT32}, the block
+     *      sizes for each spatial dimension of the input tensor. All values
+     *      must be >= 1.
+     * * 2: An optional {@link ANEURALNETWORKS_BOOL} scalar, default to false.
+     *      Set to true to specify NCHW data layout for input0 and output0.
+     *      Available since API level 29.
+     *
+     * Outputs:
+     * * 0: A tensor of the same {@link OperandCode} as input0.
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint must be the same as input0.
+     *
+     * Available since API level 28.
+     */
+    ANEURALNETWORKS_BATCH_TO_SPACE_ND = 29,
+
+    /**
+     * Element-wise division of two tensors.
+     *
+     * Takes two input tensors of identical {@link OperandCode} and compatible
+     * dimensions. The output is the result of dividing the first input tensor
+     * by the second, optionally modified by an activation function.
+     *
+     * Two dimensions are compatible when:
+     *     1. they are equal, or
+     *     2. one of them is 1
+     *
+     * The size of the output is the maximum size along each dimension of the
+     * input operands. It starts with the trailing dimensions, and works its way
+     * forward.
+     *
+     * Example:
+     *     input1.dimension =    {4, 1, 2}
+     *     input2.dimension = {5, 4, 3, 1}
+     *     output.dimension = {5, 4, 3, 2}
+     *
+     * Since API level 29, generic zero-sized input tensor is supported. Zero
+     * dimension is only compatible with 0 or 1. The size of the output
+     * dimension is zero if either of corresponding input dimension is zero.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     *
+     * Supported tensor rank: up to 4
+     *
+     * Inputs:
+     * * 0: An n-D tensor, specifying the first input.
+     * * 1: A tensor of the same {@link OperandCode}, and compatible dimensions
+     *      as input0.
+     * * 2: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the
+     *      {@link FuseCode} values. Specifies the activation to
+     *      invoke on the result.
+     *
+     * Outputs:
+     * * 0: A tensor of the same {@link OperandCode} as input0.
+     *
+     * Available since API level 28.
+     */
+    ANEURALNETWORKS_DIV = 30,
+
+    /**
+     * Computes the mean of elements across dimensions of a tensor.
+     *
+     * Reduces the input tensor along the given dimensions to reduce. Unless
+     * keep_dims is true, the rank of the tensor is reduced by 1 for each entry
+     * in axis. If keep_dims is true, the reduced dimensions are retained with
+     * length 1.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: up to 4
+     *
+     * Inputs:
+     * * 0: A tensor, specifying the input.
+     * * 1: A 1-D Tensor of {@link ANEURALNETWORKS_TENSOR_INT32}. The dimensions
+     *      to reduce. Must be in the range
+     *      [-rank(input_tensor), rank(input_tensor)).
+     *
+     *      NOTE: When the operation was introduced, the documentation
+     *      incorrectly stated that if dimensions were empty, the operation
+     *      would reduce across all dimensions. This behavior was never
+     *      implemented.
+     *
+     * * 2: An {@link ANEURALNETWORKS_INT32} scalar, keep_dims. If positive,
+     *      retains reduced dimensions with length 1.
+     *
+     * Outputs:
+     * * 0: A tensor of the same {@link OperandCode} as input0.
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint must be same as input0.
+     *
+     * Available since API level 28.
+     */
+    ANEURALNETWORKS_MEAN = 31,
+
+    /**
+     * Pads a tensor with zeros.
+     *
+     * This operation pads a tensor according to the specified paddings.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} (full support since API
+     *   level 29, see the output section)
+     *
+     * Supported tensor rank: up to 4
+     *
+     * Inputs:
+     * * 0: An n-D tensor, specifying the tensor to be padded.
+     * * 1: A 2-D Tensor of {@link ANEURALNETWORKS_TENSOR_INT32}, the paddings
+     *      for each spatial dimension of the input tensor. The shape of the
+     *      tensor must be {rank(input0), 2}.
+     *      padding[i, 0] specifies the number of elements to be padded in the
+     *      front of dimension i.
+     *      padding[i, 1] specifies the number of elements to be padded after the
+     *      end of dimension i.
+     *
+     * Outputs:
+     * * 0: A tensor of the same {@link OperandCode} as input0. The
+     *      output tensor has the same rank as input0, and each
+     *      dimension of the output tensor has the same size as the
+     *      corresponding dimension of the input tensor plus the size
+     *      of the padding:
+     *          output0.dimension[i] =
+     *              padding[i, 0] + input0.dimension[i] + padding[i, 1]
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint must be the same as input0.
+     *
+     *      NOTE: Before API level 29, the pad value for
+     *      {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} is undefined.
+     *      Since API level 29, the pad value is always the logical zero.
+     *
+     * Available since API level 28.
+     */
+    ANEURALNETWORKS_PAD = 32,
+
+    // TODO: make the description easier to understand.
+    /**
+     * SpaceToBatch for N-Dimensional tensors.
+     *
+     * This operation divides "spatial" dimensions [1, ..., M] of the input into
+     * a grid of blocks of shape block_shape, and interleaves these blocks with
+     * the "batch" dimension (0) such that in the output, the spatial dimensions
+     * [1, ..., M] correspond to the position within the grid, and the batch
+     * dimension combines both the position within a spatial block and the
+     * original batch position. Prior to division into blocks, the spatial
+     * dimensions of the input are optionally zero padded according to paddings.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} (full support since API
+     *   level 29, see the output section)
+     *
+     * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout.
+     * With the default data layout NHWC, the data is stored in the order of:
+     * [batch, height, width, channels]. Alternatively, the data layout could
+     * be NCHW, the data storage order of: [batch, channels, height, width].
+     *
+     * Inputs:
+     * * 0: An n-D tensor, specifying the input.
+     * * 1: A 1-D Tensor of {@link ANEURALNETWORKS_TENSOR_INT32}, the block
+     *      sizes for each spatial dimension of the input tensor. All values
+     *      must be >= 1.
+     * * 2: A 2-D Tensor of {@link ANEURALNETWORKS_TENSOR_INT32}, the paddings
+     *      for each spatial dimension of the input tensor. All values must be
+     *      >= 0. The shape of the tensor must be {M, 2}, where M is the number
+     *      of spatial dimensions.
+     *      padding[i, 0] specifies the number of element to be padded in the
+     *      front of dimension i.
+     *      padding[i, 1] specifies the number of element to be padded after the
+     *      end of dimension i.
+     * * 3: An optional {@link ANEURALNETWORKS_BOOL} scalar, default to false.
+     *      Set to true to specify NCHW data layout for input0 and output0.
+     *      Available since API level 29.
+     *
+     * Outputs:
+     * * 0: A tensor of the same {@link OperandCode} as input0.
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint must be the same as input0.
+     *
+     *      NOTE: Before API level 29, the pad value for
+     *      {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} is undefined.
+     *      Since API level 29, the pad value is always the logical zero.
+     *
+     * Available since API level 28.
+     */
+    ANEURALNETWORKS_SPACE_TO_BATCH_ND = 33,
+
+    /**
+     * Removes dimensions of size 1 from the shape of a tensor.
+     *
+     * Given a tensor input, this operation returns a tensor of the same
+     * {@link OperandCode} with all dimensions of size 1 removed. If you don't
+     * want to remove all size 1 dimensions, you can remove specific size 1
+     * dimensions by specifying the axes (input1).
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: up to 4
+     *
+     * Inputs:
+     * * 0: An n-D tensor, the tensor to be squeezed.
+     * * 1: An optional 1-D tensor of {@link ANEURALNETWORKS_TENSOR_INT32}. The
+     *      dimensions to squeeze. If specified only squeezes the dimensions
+     *      listed. Otherwise, squeezes all dimensions. The dimension index
+     *      starts at 0. An error must be reported if squeezing a dimension that
+     *      is not 1.
+     *
+     * Outputs:
+     * * 0: A tensor of the same {@link OperandCode} as input0. Contains the
+     *      same data as input, but has one or more dimensions of size 1
+     *      removed.
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint must be the same as input0.
+     *
+     * Available since API level 28.
+     */
+    ANEURALNETWORKS_SQUEEZE = 34,
+
+    /**
+     * Extracts a strided slice of a tensor.
+     *
+     * Roughly speaking, this op extracts a slice of size (end - begin) / stride
+     * from the given input tensor. Starting at the location specified by begin
+     * the slice continues by adding stride to the index until all dimensions
+     * are not less than end. Note that a stride can be negative, which causes a
+     * reverse slice.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: up to 4
+     *
+     * Inputs:
+     * * 0: An n-D tensor, specifying the tensor to be sliced.
+     * * 1: begin, a 1-D tensor of {@link ANEURALNETWORKS_TENSOR_INT32}. The
+     *      starts of the dimensions of the input tensor to be sliced. The
+     *      length must be of rank(input0).
+     * * 2: end, a 1-D tensor of {@link ANEURALNETWORKS_TENSOR_INT32}. The
+     *      ends of the dimensions of the input tensor to be sliced. The length
+     *      must be of rank(input0).
+     * * 3: strides, a 1-D tensor of {@link ANEURALNETWORKS_TENSOR_INT32}. The
+     *      strides of the dimensions of the input tensor to be sliced. The
+     *      length must be of rank(input0). The entries must be non-zero.
+     * * 4: begin_mask, an {@link ANEURALNETWORKS_INT32} scalar. If the ith bit
+     *      of begin_mask is set, begin[i] is ignored and the fullest possible
+     *      range in that dimension is used instead.
+     * * 5: end_mask, an {@link ANEURALNETWORKS_INT32} scalar. If the ith bit of
+     *      end_mask is set, end[i] is ignored and the fullest possible range in
+     *      that dimension is used instead.
+     * * 6: shrink_axis_mask, an {@link ANEURALNETWORKS_INT32} scalar. If the
+     *      ith bit of shrink_axis_mask is set, the ith dimension specification
+     *      shrinks the dimensionality by 1, taking on the value at index
+     *      begin[i]. In this case, the ith specification must define a
+     *      slice of size 1, e.g. begin[i] = x, end[i] = x + 1.
+     *
+     * Outputs:
+     * * 0: A tensor of the same {@link OperandCode} as input0 and rank (n - k),
+     *      where k is the number of bits set in shrink_axis_mask.
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint must be the same as input0.
+     *
+     * Available since API level 28.
+     */
+    ANEURALNETWORKS_STRIDED_SLICE = 35,
+
+    /**
+     * Element-wise subtraction of two tensors.
+     *
+     * Takes two input tensors of identical {@link OperandCode} and compatible
+     * dimensions. The output is the result of subtracting the second input
+     * tensor from the first one, optionally modified by an activation function.
+     *
+     * Two dimensions are compatible when:
+     *     1. they are equal, or
+     *     2. one of them is 1
+     *
+     * The size of the output is the maximum size along each dimension of the
+     * input operands. It starts with the trailing dimensions, and works its way
+     * forward.
+     *
+     * Example:
+     *     input1.dimension =    {4, 1, 2}
+     *     input2.dimension = {5, 4, 3, 1}
+     *     output.dimension = {5, 4, 3, 2}
+     *
+     * Since API level 29, generic zero-sized input tensor is supported. Zero
+     * dimension is only compatible with 0 or 1. The size of the output
+     * dimension is zero if either of corresponding input dimension is zero.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} (since API level 29)
+     *
+     * Supported tensor rank: up to 4
+     *
+     * Inputs:
+     * * 0: An n-D tensor, specifying the first input.
+     * * 1: A tensor of the same {@link OperandCode}, and compatible dimensions
+     *      as input0.
+     * * 2: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the
+     *      {@link FuseCode} values. Specifies the activation to
+     *      invoke on the result.
+     *
+     * Outputs:
+     * * 0: A tensor of the same {@link OperandCode} as input0.
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint can be different from inputs' scale and zeroPoint.
+     *
+     * Available since API level 28.
+     */
+    ANEURALNETWORKS_SUB = 36,
+
+    /**
+     * Transposes the input tensor, permuting the dimensions according to the
+     * perm tensor.
+     *
+     * The returned tensor's dimension i corresponds to the input dimension
+     * perm[i]. If perm is not given, it is set to (n-1...0), where n is the
+     * rank of the input tensor. Hence by default, this operation performs a
+     * regular matrix transpose on 2-D input Tensors.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: up to 4
+     *
+     * Inputs:
+     * * 0: An n-D tensor, specifying the tensor to be transposed.
+     *      Since API level 29, this tensor may be zero-sized.
+     * * 1: An optional 1-D Tensor of {@link ANEURALNETWORKS_TENSOR_INT32},
+     *      the permutation of the dimensions of the input tensor.
+     *
+     * Outputs:
+     * * 0: A tensor of the same {@link OperandCode} as input0.
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint must be the same as input0.
+     *
+     * Available since API level 28.
+     */
+    ANEURALNETWORKS_TRANSPOSE = 37,
+
+    // Operations below are available since API level 29.
+
+    /**
+     * Computes the absolute value of a tensor, element-wise.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     *
+     * Supported tensor rank: from 1.
+     *
+     * Inputs:
+     * * 0: A tensor.
+     *
+     * Outputs:
+     * * 0: The output tensor of same shape as input0.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_ABS = 38,
+
+    /**
+     * Returns the index of the largest element along an axis.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_INT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: from 1
+     *
+     * Inputs:
+     * * 0: An n-D tensor specifying the input. Must be non-empty.
+     * * 1: An {@link ANEURALNETWORKS_INT32} scalar specifying the axis to
+     *      reduce across. Negative index is used to specify axis from the
+     *      end (e.g. -1 for the last axis). Must be in the range [-n, n).
+     *
+     * Outputs:
+     * * 0: An (n - 1)-D {@link ANEURALNETWORKS_TENSOR_INT32} tensor.
+     *
+     * Available since API level 29.
+     */
+    // There is no underscore in ARG_MAX to avoid name conflict with
+    // the macro defined in libc/kernel/uapi/linux/limits.h.
+    ANEURALNETWORKS_ARGMAX = 39,
+
+    /**
+     * Returns the index of the smallest element along an axis.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_INT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: from 1
+     *
+     * Inputs:
+     * * 0: An n-D tensor specifying the input. Must be non-empty.
+     * * 1: An {@link ANEURALNETWORKS_INT32} scalar specifying the axis to
+     *      reduce across. Negative index is used to specify axis from the
+     *      end (e.g. -1 for the last axis). Must be in the range [-n, n).
+     *
+     * Outputs:
+     * * 0: An (n - 1)-D {@link ANEURALNETWORKS_TENSOR_INT32} tensor.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_ARGMIN = 40,  // See ARGMAX for naming discussion.
+
+    /**
+     * Transform axis-aligned bounding box proposals using bounding box deltas.
+     *
+     * Given the positions of bounding box proposals and the corresponding
+     * bounding box deltas for each class, return the refined bounding box
+     * regions. The resulting bounding boxes are cliped against the edges of
+     * the image.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT16_ASYMM}
+     *
+     * Inputs:
+     * * 0: A 2-D Tensor of shape [num_rois, 4], specifying the locations of the
+     *      bounding box proposals, each line with format [x1, y1, x2, y2].
+     *      For tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT16_ASYMM},
+     *      the zeroPoint must be 0 and the scale must be 0.125. Zero num_rois
+     *      is supported for this tensor.
+     * * 1: A 2-D Tensor of shape [num_rois, num_classes * 4], specifying the
+     *      bounding box delta for each region of interest and each class. The
+     *      bounding box deltas are organized in the following order
+     *      [dx, dy, dw, dh], where dx and dy is the relative correction factor
+     *      for the center position of the bounding box with respect to the width
+     *      and height, dw and dh is the log-scale relative correction factor
+     *      for the width and height. For input0 of type
+     *      {@link ANEURALNETWORKS_TENSOR_QUANT16_ASYMM}, this tensor should be
+     *      of {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}. Zero num_rois is
+     *      supported for this tensor.
+     * * 2: An 1-D {@link ANEURALNETWORKS_TENSOR_INT32} tensor, of shape
+     *      [num_rois], specifying the batch index of each box. Boxes with
+     *      the same batch index are grouped together. Zero num_rois is
+     *      supported for this tensor.
+     * * 3: A 2-D Tensor of shape [batches, 2], specifying the information of
+     *      each image in the batch, each line with format
+     *      [image_height, image_width].
+     *
+     * Outputs:
+     * * 0: A tensor of the same {@link OperandCode} as input0, with shape
+     *      [num_rois, num_classes * 4], specifying the coordinates of each
+     *      output bounding box for each class, with format [x1, y1, x2, y2].
+     *      For type of {@link ANEURALNETWORKS_TENSOR_QUANT16_ASYMM}, the
+     *      scale must be 0.125 and the zero point must be 0.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_AXIS_ALIGNED_BBOX_TRANSFORM = 41,
+
+    /**
+     * Performs a forward LSTM on the input followed by a backward LSTM.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     *
+     * Supported tensor rank: 3, either time-major or batch-major.
+     *
+     * All input and output tensors must be of the same type.
+     *
+     *
+     * Inputs:
+     * * 0: The input.
+     *      A 3-D tensor of shape:
+     *        If time-major: [max_time, batch_size, input_size]
+     *        If batch-major: [batch_size, max_time, input_size]
+     *      where "max_time" is the number of timesteps (sequence length),
+     *      "batch_size" corresponds to the batching dimension, and
+     *      "input_size" is the size of the input.
+     * * 1: The forward input-to-input weights. Optional.
+     *      A 2-D tensor of shape [fw_num_units, input_size], where “fw_num_units”
+     *      corresponds to the number of forward cell units.
+     * * 2: The forward input-to-forget weights.
+     *      A 2-D tensor of shape [fw_num_units, input_size].
+     * * 3: The forward input-to-cell weights.
+     *      A 2-D tensor of shape [fw_num_units, input_size].
+     * * 4: The forward input-to-output weights.
+     *      A 2-D tensor of shape [fw_num_units, input_size].
+     * * 5: The forward recurrent-to-input weights. Optional.
+     *      A 2-D tensor of shape [fw_num_units, fw_output_size], where “fw_output_size”
+     *      corresponds to either the number of cell units (i.e., fw_num_units),
+     *      or the second dimension of the “fw_projection_weights”, if defined.
+     * * 6: The forward recurrent-to-forget weights.
+     *      A 2-D tensor of shape [fw_num_units, fw_output_size].
+     * * 7: The forward recurrent-to-cell weights.
+     *      A 2-D tensor of shape [fw_num_units, fw_output_size].
+     * * 8: The forward recurrent-to-output weights.
+     *      A 2-D tensor of shape [fw_num_units, fw_output_size].
+     * * 9: The forward cell-to-input weights. Optional.
+     *      A 1-D tensor of shape [fw_num_units].
+     * * 10: The forward cell-to-forget weights. Optional.
+     *       A 1-D tensor of shape [fw_num_units].
+     * * 11: The forward cell-to-output weights. Optional.
+     *       A 1-D tensor of shape [fw_num_units].
+     * * 12: The forward input gate bias. Optional.
+     *       A 1-D tensor of shape [fw_num_units].
+     * * 13: The forward forget gate bias.
+     *       A 1-D tensor of shape [fw_num_units].
+     * * 14: The forward cell gate bias.
+     *       A 1-D tensor of shape [fw_num_units].
+     * * 15: The forward output gate bias.
+     *       A 1-D tensor of shape [fw_num_units].
+     * * 16: The forward projection weights. Optional.
+     *       A 2-D tensor of shape [fw_output_size, fw_num_units].
+     * * 17: The forward projection bias. Optional.
+     *       A 1-D tensor of shape [fw_output_size].
+     * * 18: The backward input-to-input weights. Optional.
+     *       A 2-D tensor of shape [bw_num_units, input_size], where “bw_num_units”
+     *       corresponds to the number of backward cell units.
+     * * 19: The backward input-to-forget weights.
+     *       A 2-D tensor of shape [bw_num_units, input_size].
+     * * 20: The backward input-to-cell weights.
+     *       A 2-D tensor of shape [bw_num_units, input_size].
+     * * 21: The backward input-to-output weights.
+     *       A 2-D tensor of shape [bw_num_units, input_size].
+     * * 22: The backward recurrent-to-input weights. Optional.
+     *       A 2-D tensor of shape [bw_num_units, bw_output_size], where “bw_output_size”
+     *       corresponds to either the number of cell units (i.e., “bw_num_units”),
+     *       or the second dimension of the “bw_projection_weights”, if defined.
+     * * 23: The backward recurrent-to-forget weights.
+     *       A 2-D tensor of shape [bw_num_units, bw_output_size].
+     * * 24: The backward recurrent-to-cell weights.
+     *       A 2-D tensor of shape [bw_num_units, bw_output_size].
+     * * 25: The backward recurrent-to-output weights.
+     *       A 2-D tensor of shape [bw_num_units, bw_output_size].
+     * * 26: The backward cell-to-input weights. Optional.
+     *       A 1-D tensor of shape [bw_num_units].
+     * * 27: The backward cell-to-forget weights. Optional.
+     *       A 1-D tensor of shape [bw_num_units].
+     * * 28: The backward cell-to-output weights. Optional.
+     *       A 1-D tensor of shape [bw_num_units].
+     * * 29: The backward input gate bias. Optional.
+     *       A 1-D tensor of shape [bw_num_units].
+     * * 30: The backward forget gate bias.
+     *       A 1-D tensor of shape [bw_num_units].
+     * * 31: The backward cell gate bias.
+     *       A 1-D tensor of shape [bw_num_units].
+     * * 32: The backward output gate bias.
+     *       A 1-D tensor of shape [bw_num_units].
+     * * 33: The backward projection weights. Optional.
+     *       A 2-D tensor of shape [bw_output_size, bw_num_units].
+     * * 34: The backward projection bias. Optional.
+     *       A 1-D tensor of shape [bw_output_size].
+     * * 35: The forward input activation state.
+     *       A 2-D tensor of shape [batch_size, bw_output_size].
+     * * 36: The forward input cell state.
+     *       A 2-D tensor of shape [batch_size, bw_num_units].
+     * * 37: The backward input activation state.
+     *       A 2-D tensor of shape [batch_size, bw_output_size].
+     * * 38: The backward input cell state.
+     *       A 2-D tensor of shape [batch_size, bw_num_units].
+     * * 39: The auxiliary input. Optional.
+     *       A 3-D tensor of shape [max_time, batch_size, input_size], where “batch_size”
+     *       corresponds to the batching dimension, and “input_size” is the size
+     *       of the input.
+     * * 40: The forward auxiliary input-to-input weights. Optional.
+     *       A 2-D tensor of shape [fw_num_units, input_size].
+     * * 41: The forward auxiliary input-to-forget weights. Optional.
+     *       A 2-D tensor of shape [fw_num_units, input_size].
+     * * 42: The forward auxiliary input-to-cell weights. Optional.
+     *       A 2-D tensor of shape [fw_num_units, input_size].
+     * * 43: The forward auxiliary input-to-output weights. Optional.
+     *       A 2-D tensor of shape [fw_num_units, input_size].
+     * * 44: The backward auxiliary input-to-input weights. Optional.
+     *       A 2-D tensor of shape [bw_num_units, input_size].
+     * * 45: The backward auxiliary input-to-forget weights. Optional.
+     *       A 2-D tensor of shape [bw_num_units, input_size].
+     * * 46: The backward auxiliary input-to-cell weights. Optional.
+     *       A 2-D tensor of shape [bw_num_units, input_size].
+     * * 47: The backward auxiliary input-to-output weights. Optional.
+     *       A 2-D tensor of shape [bw_num_units, input_size].
+     * * 48: The activation function.
+     *       A value indicating the activation function:
+     *       <ul>
+     *       <li>0: None;
+     *       <li>1: Relu;
+     *       <li>3: Relu6;
+     *       <li>4: Tanh;
+     *       <li>6: Sigmoid.
+     *       </ul>
+     * * 49: The clipping threshold for the cell state, such
+     *       that values are bound within [-cell_clip, cell_clip]. If set to 0.0
+     *       then clipping is disabled.
+     *       If all the input tensors have type {@link ANEURALNETWORKS_TENSOR_FLOAT32},
+     *       this scalar must be of the type {@link ANEURALNETWORKS_FLOAT32},
+     *       otherwise if all the input tensors have the type {@link
+     *       ANEURALNETWORKS_TENSOR_FLOAT16}, this scalar must be of type {@link
+     *       ANEURALNETWORKS_FLOAT16}.
+     * * 50: The clipping threshold for the output from the
+     *       projection layer, such that values are bound within
+     *       [-proj_clip, proj_clip]. If set to 0.0 then clipping is disabled.
+     *       If all the input tensors have type {@link ANEURALNETWORKS_TENSOR_FLOAT32},
+     *       this scalar must be of the type {@link ANEURALNETWORKS_FLOAT32},
+     *       otherwise if all the input tensors have the type {@link
+     *       ANEURALNETWORKS_TENSOR_FLOAT16}, this scalar must be of type {@link
+     *       ANEURALNETWORKS_FLOAT16}.
+     * * 51: merge_outputs
+     *       An {@link ANEURALNETWORKS_BOOL} scalar specifying if the outputs
+     *       from forward and backward cells should be merged.
+     * * 52: time_major
+     *       An {@link ANEURALNETWORKS_BOOL} scalar specifying the shape format
+     *       of input and output tensors.
+     * * 53: The forward input layer normalization weights. Optional.
+     *       A 1-D tensor of shape [fw_num_units]. Used to rescale normalized inputs
+     *       to activation at input gate.
+     * * 54: The forward forget layer normalization weights. Optional.
+     *       A 1-D tensor of shape [fw_num_units]. Used to rescale normalized inputs
+     *       to activation at forget gate.
+     * * 55: The forward cell layer normalization weights. Optional.
+     *       A 1-D tensor of shape [fw_num_units]. Used to rescale normalized inputs
+     *       to activation at cell gate.
+     * * 56: The forward output layer normalization weights. Optional.
+     *       A 1-D tensor of shape [fw_num_units]. Used to rescale normalized inputs
+     *       to activation at output gate.
+     * * 57: The backward input layer normalization weights. Optional.
+     *       A 1-D tensor of shape [bw_num_units]. Used to rescale normalized inputs
+     *       to activation at input gate.
+     * * 58: The backward forget layer normalization weights. Optional.
+     *       A 1-D tensor of shape [bw_num_units]. Used to rescale normalized inputs
+     *       to activation at forget gate.
+     * * 59: The backward cell layer normalization weights. Optional.
+     *       A 1-D tensor of shape [bw_num_units]. Used to rescale normalized inputs
+     *       to activation at cell gate.
+     * * 60: The backward output layer normalization weights. Optional.
+     *       A 1-D tensor of shape [bw_num_units]. Used to rescale normalized inputs
+     *       to activation at output gate.
+     *
+     * Outputs:
+     * * 0: The forward output.
+     *      A 3-D tensor of shape:
+     *        If time-major and not merge_outputs:
+     *          [max_time, batch_size, fw_output_size]
+     *        If time-major and merge_outputs:
+     *          [max_time, batch_size, fw_output_size + bw_output_size]
+     *        If batch-major and not merge_outputs:
+     *          [batch_size, max_time, fw_output_size]
+     *        If batch-major and merge_outputs:
+     *          [batch_size, max_time, fw_output_size + bw_output_size]
+     * * 1: The backward output.  Unused if merge_outputs is true.
+     *      A 3-D tensor of shape:
+     *        If time-major: [max_time, batch_size, bw_output_size]
+     *        If batch-major: [batch_size, max_time, bw_output_size]
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_BIDIRECTIONAL_SEQUENCE_LSTM = 42,
+
+    /**
+     * A recurrent neural network layer that applies a basic RNN cell to a
+     * sequence of inputs in forward and backward directions.
+     *
+     * This Op unrolls the input along the sequence dimension, and implements
+     * the following operation for each element in the sequence s =
+     * 1...sequence_length:
+     *   fw_outputs[s] = fw_state = activation(inputs[s] * fw_input_weights’ +
+     *          fw_state * fw_recurrent_weights’ + fw_bias)
+     *
+     * And for each element in sequence t = sequence_length : 1
+     *   bw_outputs[t] = bw_state = activation(inputs[t] * bw_input_weights’ +
+     *          bw_state * bw_recurrent_weights’ + bw_bias)
+     *
+     * Where:
+     * * “{fw,bw}_input_weights” is a weight matrix that multiplies the inputs;
+     * * “{fw,bw}_recurrent_weights” is a weight matrix that multiplies the
+     *    current “state” which itself is the output from the previous time step
+     *    computation;
+     * * “{fw,bw}_bias” is a bias vector (added to each output vector in the
+     *    batch);
+     * * “activation” is the function passed as the “fused_activation_function”
+     *   argument (if not “NONE”).
+     *
+     * The op also supports an auxiliary input. Regular cell feeds one input
+     * into the two RNN cells in the following way:
+     *
+     *       INPUT  (INPUT_REVERSED)
+     *         |         |
+     *    ---------------------
+     *    | FW_RNN     BW_RNN |
+     *    ---------------------
+     *         |         |
+     *      FW_OUT     BW_OUT
+     *
+     * An op with an auxiliary input takes two inputs and feeds them into the
+     * RNN cells in the following way:
+     *
+     *       AUX_INPUT   (AUX_INPUT_REVERSED)
+     *           |             |
+     *     INPUT | (INPUT_R'D.)|
+     *       |   |       |     |
+     *    -----------------------
+     *    |  \  /        \    / |
+     *    | FW_RNN       BW_RNN |
+     *    -----------------------
+     *         |           |
+     *      FW_OUT      BW_OUT
+     *
+     * While stacking this op on top of itself, this allows to connect both
+     * forward and backward outputs from previous cell to the next cell's
+     * inputs.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     *
+     * The input tensors must all be the same type.
+     *
+     * Inputs:
+     * * 0: input.
+     *      A 3-D tensor. The shape is defined by the input 6 (timeMajor). If
+     *      it is set to true, then the input has a shape [maxTime, batchSize,
+     *      inputSize], otherwise the input has a shape [batchSize, maxTime,
+     *      inputSize].
+     * * 1: fwWeights.
+     *      A 2-D tensor of shape [fwNumUnits, inputSize].
+     * * 2: fwRecurrentWeights.
+     *      A 2-D tensor of shape [fwNumUnits, fwNumUnits].
+     * * 3: fwBias.
+     *      A 1-D tensor of shape [fwNumUnits].
+     * * 4: fwHiddenState.
+     *      A 2-D tensor of shape [batchSize, fwNumUnits]. Specifies a hidden
+     *      state input for the first time step of the computation.
+     * * 5: bwWeights.
+     *      A 2-D tensor of shape [bwNumUnits, inputSize].
+     * * 6: bwRecurrentWeights.
+     *      A 2-D tensor of shape [bwNumUnits, bwNumUnits].
+     * * 7: bwBias.
+     *      A 1-D tensor of shape [bwNumUnits].
+     * * 8: bwHiddenState
+     *      A 2-D tensor of shape [batchSize, bwNumUnits]. Specifies a hidden
+     *      state input for the first time step of the computation.
+     * * 9: auxInput.
+     *      A 3-D tensor. The shape is the same as of the input 0.
+     * * 10:fwAuxWeights.
+     *      A 2-D tensor of shape [fwNumUnits, inputSize].
+     * * 11:bwAuxWeights.
+     *      A 2-D tensor of shape [bwNumUnits, inputSize].
+     * * 12:fusedActivationFunction.
+     *      A {@link FuseCode} value indicating the activation function. If
+     *      “NONE” is specified then it results in a linear activation.
+     * * 13:timeMajor
+     *      An {@link ANEURALNETWORKS_BOOL} scalar specifying the shape format
+     *      of input and output tensors.
+     * * 14:mergeOutputs
+     *      An {@link ANEURALNETWORKS_BOOL} scalar specifying if the outputs
+     *      from forward and backward cells are separate (if set to false) or
+     *      concatenated (if set to true).
+     * Outputs:
+     * * 0: fwOutput.
+     *      A 3-D tensor. The first two dimensions of the shape are defined by
+     *      the input 6 (timeMajor) and the third dimension is defined by the
+     *      input 14 (mergeOutputs). If timeMajor is set to true, then the first
+     *      two dimensions are [maxTime, batchSize], otherwise they are set to
+     *      [batchSize, maxTime]. If mergeOutputs is set to true, then the third
+     *      dimension is equal to (fwNumUnits + bwNumUnits), otherwise it is set
+     *      to fwNumUnits.
+     * * 1: bwOutput.
+     *      A 3-D tensor. If the input 14 (mergeOutputs) is set to true, then
+     *      this tensor is not produced. The shape is defined by the input 6
+     *      (timeMajor). If it is set to true, then the shape is set to
+     *      [maxTime, batchSize, bwNumUnits], otherwise the shape is set to
+     *      [batchSize, maxTime, bwNumUnits].
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_BIDIRECTIONAL_SEQUENCE_RNN = 43,
+
+    /**
+     * Greedily selects a subset of bounding boxes in descending order of score.
+     *
+     * This op applies NMS algorithm to each class. In each loop of execution,
+     * the box with maximum score gets selected and removed from the pending set.
+     * The scores of the rest of boxes are lowered according to the
+     * intersection-over-union (IOU) overlapping with the previously selected
+     * boxes and a specified NMS kernel method. Any boxes with score less
+     * than a threshold are removed from the pending set.
+     *
+     * Three NMS kernels are supported:
+     * * Hard:     score_new = score_old * (1 if IoU < threshold else 0)
+     * * Linear:   score_new = score_old * (1 if IoU < threshold else 1 - IoU)
+     * * Gaussian: score_new = score_old * exp(- IoU^2 / sigma)
+     *
+     * Axis-aligned bounding boxes are represented by its upper-left corner
+     * coordinate (x1,y1) and lower-right corner coordinate (x2,y2). A valid
+     * bounding box should satisfy x1 <= x2 and y1 <= y2.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Inputs:
+     * * 0: A 2-D Tensor of shape [num_rois, num_classes], specifying the score
+     *      of each bounding box proposal. The boxes are grouped by batches in the
+     *      first dimension. Zero num_rois is supported for this tensor.
+     * * 1: A 2-D Tensor specifying the bounding boxes of shape
+     *      [num_rois, num_classes * 4], organized in the order [x1, y1, x2, y2].
+     *      The boxes are grouped by batches in the first dimension. The sequential
+     *      order of the boxes corresponds with input0. For input0 of type
+     *      {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, this tensor should be of
+     *      {@link ANEURALNETWORKS_TENSOR_QUANT16_ASYMM}, with zeroPoint of 0 and
+     *      scale of 0.125. Zero num_rois is supported for this tensor.
+     * * 2: A 1-D {@link ANEURALNETWORKS_TENSOR_INT32} tensor, of shape
+     *      [num_rois], specifying the batch index of each box. Boxes with
+     *      the same batch index are grouped together.
+     * * 3: An {@link ANEURALNETWORKS_FLOAT32} scalar, score_threshold. Boxes
+     *      with scores lower than the threshold are filtered before sending
+     *      to the NMS algorithm.
+     * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the maximum
+     *      number of selected bounding boxes for each image. Set to a negative
+     *      value for unlimited number of output bounding boxes.
+     * * 5: An {@link ANEURALNETWORKS_INT32} scalar, specifying the NMS
+     *      kernel method, options are 0:hard, 1:linear, 2:gaussian.
+     * * 6: An {@link ANEURALNETWORKS_FLOAT32} scalar, specifying the IoU
+     *      threshold in hard and linear NMS kernel. This field is ignored if
+     *      gaussian kernel is selected.
+     * * 7: An {@link ANEURALNETWORKS_FLOAT32} scalar, specifying the sigma in
+     *      gaussian NMS kernel. This field is ignored if gaussian kernel is
+     *      not selected.
+     * * 8: An {@link ANEURALNETWORKS_FLOAT32} scalar, nms_score_threshold.
+     *      Boxes with scores lower than the threshold are dropped during the
+     *      score updating phase in soft NMS.
+     *
+     * Outputs:
+     * * 0: A 1-D Tensor of the same {@link OperandCode} as input0, with shape
+     *      [num_output_rois], specifying the score of each output box. The boxes
+     *      are grouped by batches, but the sequential order in each batch is not
+     *      guaranteed. For type of {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM},
+     *      the scale and zero point must be the same as input0.
+     * * 1: A 2-D Tensor of the same {@link OperandCode} as input1, with shape
+     *      [num_output_rois, 4], specifying the coordinates of each
+     *      output bounding box with the same format as input1. The sequential
+     *      order of the boxes corresponds with output0. For type of
+     *      {@link ANEURALNETWORKS_TENSOR_QUANT16_ASYMM}, the scale must be
+     *      0.125 and the zero point must be 0.
+     * * 2: A 1-D {@link ANEURALNETWORKS_TENSOR_INT32} tensor, of shape
+     *      [num_output_rois], specifying the class of each output box. The
+     *      sequential order of the boxes corresponds with output0.
+     * * 3: A 1-D {@link ANEURALNETWORKS_TENSOR_INT32} tensor, of shape
+     *      [num_output_rois], specifying the batch index of each box. Boxes
+     *      with the same batch index are grouped together.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_BOX_WITH_NMS_LIMIT = 44,
+
+    /**
+     * Casts a tensor to a new type.
+     *
+     * This operation ignores the scale and zeroPoint of quanized tensors,
+     * e.g. it treats a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} input
+     * as a tensor of uint8 values.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_INT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: from 1
+     *
+     * Inputs:
+     * * 0: A tensor.
+     *
+     * Outputs:
+     * * 0: A tensor with the same shape as input0.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_CAST = 45,
+
+    /**
+     * Shuffle the channels of the input tensor.
+     *
+     * Given an input tensor and a integer value of num_groups, CHANNEL_SHUFFLE
+     * divide the channel dimension into num_groups groups, and reorganize the
+     * channels by grouping channels with the same index in each group.
+     *
+     * Along the channel dimension, the output is calculated using this formula:
+     *
+     *     output_channel[k * num_groups + g] = input_channel[g * group_size + k]
+     *
+     * where group_size = num_channels / num_groups
+     *
+     * The number of channels must be divisible by num_groups.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: up to 4
+     *
+     * Inputs:
+     * * 0: An n-D tensor, specifying the tensor to be shuffled.
+     * * 1: An {@link ANEURALNETWORKS_INT32} scalar, specifying the number of
+     *      groups.
+     * * 2: An {@link ANEURALNETWORKS_INT32} scalar, specifying the dimension
+     *      channel shuffle would be performed on. Negative index is used to
+     *      specify axis from the end (e.g. -1 for the last axis). Must be in
+     *      the range [-n, n).
+     *
+     * Outputs:
+     * * 0: A tensor of the same {@link OperandCode} and same shape as input0.
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint must be the same as input0.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_CHANNEL_SHUFFLE = 46,
+
+    /**
+     * Apply postprocessing steps to bounding box detections.
+     *
+     * Bounding box detections are generated by applying transformation on a set
+     * of predefined anchors with the bounding box deltas from bounding box
+     * regression. A final step of hard NMS is applied to limit the number of
+     * returned boxes.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     *
+     * Inputs:
+     * * 0: A 3-D Tensor of shape [batches, num_anchors, num_classes], specifying
+     *      the score of each anchor with each class. Class 0 for each
+     *      [batches, num_anchors, 0] is background and will be ignored.
+     * * 1: A 3-D Tensor of shape [batches, num_anchors, length_box_encoding], with
+     *      the first four values in length_box_encoding specifying the bounding
+     *      box deltas. The box deltas are encoded in the order of [dy, dx, dh, dw],
+     *      where dy and dx is the linear-scale relative correction factor for the
+     *      center position of the bounding box with respect to the width and height,
+     *      dh and dw is the log-scale relative correction factor for the width and
+     *      height. All the entries in length_box_encoding beyond the first four
+     *      values are ignored in this operation.
+     * * 2: A 2-D Tensor of shape [num_anchors, 4], specifying the shape of each
+     *      predefined anchor, with format [ctr_y, ctr_x, h, w], where ctr_y and
+     *      ctr_x are the center position of the box, and h and w are the height
+     *      and the width.
+     * * 3: An {@link ANEURALNETWORKS_FLOAT32} scalar, specifying the scaling
+     *      factor for dy in bounding box deltas.
+     * * 4: An {@link ANEURALNETWORKS_FLOAT32} scalar, specifying the scaling
+     *      factor for dx in bounding box deltas.
+     * * 5: An {@link ANEURALNETWORKS_FLOAT32} scalar, specifying the scaling
+     *      factor for dh in bounding box deltas.
+     * * 6: An {@link ANEURALNETWORKS_FLOAT32} scalar, specifying the scaling
+     *      factor for dw in bounding box deltas.
+     * * 7: An {@link ANEURALNETWORKS_BOOL} scalar, set to true to use regular
+     *      multi-class NMS algorithm that do NMS separately for each class,
+     *      set to false for a faster algorithm that only do one single NMS
+     *      using the highest class score..
+     * * 8: An {@link ANEURALNETWORKS_INT32} scalar, max_num_detections, specifying
+     *      the maximum number of boxes for the output. Boxes with the lowest
+     *      scores are discarded to meet the limit.
+     * * 9: An {@link ANEURALNETWORKS_INT32} scalar, only used when input7 is
+     *      set to false, specifying the maximum number of classes per detection.
+     * * 10: An {@link ANEURALNETWORKS_INT32} scalar, only used when input7 is
+     *       set to true, specifying the maximum number of detections when
+     *       applying NMS algorithm for each single class.
+     * * 11: A scalar, score_threshold. Boxes with scores lower than the
+     *       threshold are filtered before sending to the NMS algorithm. The
+     *       scalar must be of {@link ANEURALNETWORKS_FLOAT16} if input0 is of
+     *       {@link ANEURALNETWORKS_TENSOR_FLOAT16} and of {@link
+     *       ANEURALNETWORKS_FLOAT32} if input0 is of {@link
+     *       ANEURALNETWORKS_TENSOR_FLOAT32}.
+     * * 12: A scalar, specifying the IoU threshold for hard NMS. The scalar
+     *       must be of {@link ANEURALNETWORKS_FLOAT16} if input0 is of {@link
+     *       ANEURALNETWORKS_TENSOR_FLOAT16} and of {@link
+     *       ANEURALNETWORKS_FLOAT32} if input0 is of {@link
+     *       ANEURALNETWORKS_TENSOR_FLOAT32}.
+     * * 13: An {@link ANEURALNETWORKS_BOOL} scalar, set to true to include
+     *       background class in the list of label map for the output, set
+     *       to false to not include the background. When the background
+     *       class is included, it has label 0 and the output classes start
+     *       at 1 in the label map, otherwise, the output classes start at 0.
+     *
+     * Outputs:
+     * * 0: A 2-D tensor of the same {@link OperandCode} as input0, with shape
+     *      [batches, max_num_detections], specifying the score of each output
+     *      detections.
+     * * 1: A 3-D tensor of shape [batches, max_num_detections, 4], specifying the
+     *      coordinates of each output bounding box, with format
+     *      [y1, x1, y2, x2].
+     * * 2: A 2-D {@link ANEURALNETWORKS_TENSOR_INT32} tensor, of shape
+     *      [batches, max_num_detections], specifying the class label for each
+     *      output detection.
+     * * 3: An 1-D {@link ANEURALNETWORKS_TENSOR_INT32} tensor, of shape [batches],
+     *      specifying the number of valid output detections for each batch.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_DETECTION_POSTPROCESSING = 47,
+
+    /**
+     * For input tensors x and y, computes x == y elementwise.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_BOOL8}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_INT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: from 1
+     *
+     * This operation supports broadcasting.
+     *
+     * Inputs:
+     * * 0: A tensor.
+     * * 1: A tensor of the same {@link OperandCode} and dimensions compatible
+     *      with input0.
+     *
+     * Outputs:
+     * * 0: A tensor of {@link ANEURALNETWORKS_TENSOR_BOOL8}.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_EQUAL = 48,
+
+    /**
+     * Computes exponential of x element-wise.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     *
+     * Supported tensor rank: from 1.
+     *
+     * Inputs:
+     * * 0: A tensor.
+     *
+     * Outputs:
+     * * 0: The output tensor of same shape as input0.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_EXP = 49,
+
+    /**
+     * Inserts a dimension of 1 into a tensor's shape.
+     *
+     * Given a tensor input, this operation inserts a dimension of 1 at the
+     * given dimension index of input's shape. The dimension index starts at
+     * zero; if you specify a negative dimension index, it is counted backward
+     * from the end.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_INT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: from 1
+     *
+     * Inputs:
+     * * 0: An n-D tensor.
+     * * 1: An {@link ANEURALNETWORKS_INT32} scalar specifying the dimension
+     *      index to expand. Must be in the range [-(n + 1), (n + 1)).
+     *
+     * Outputs:
+     * * 0: An (n + 1)-D tensor with the same {@link OperandCode} and data as
+     *      input0.
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint must be the same as input0.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_EXPAND_DIMS = 50,
+
+    /**
+     * Gathers values along an axis.
+     *
+     * Produces an output tensor with shape
+     *     input0.dimension[:axis] + indices.dimension + input0.dimension[axis + 1:]
+     * where:
+     *     # Vector indices (output is rank(input0)).
+     *     output[a_0, ..., a_n, i, b_0, ..., b_n] =
+     *       input0[a_0, ..., a_n, indices[i], b_0, ..., b_n]
+     *
+     *     # Higher rank indices (output is rank(input0) + rank(indices) - 1).
+     *     output[a_0, ..., a_n, i, ..., j, b_0, ... b_n] =
+     *       input0[a_0, ..., a_n, indices[i, ..., j], b_0, ..., b_n]
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_INT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: from 1
+     *
+     * Inputs:
+     * * 0: An n-D tensor from which to gather values.
+     * * 1: An {@link ANEURALNETWORKS_INT32} scalar specifying the axis.
+     *      Negative index is used to specify axis from the end
+     *      (e.g. -1 for the last axis). Must be in the range [-n, n).
+     * * 2: A k-D tensor {@link ANEURALNETWORKS_TENSOR_INT32} of indices.
+     *      The values must be in the bounds of the corresponding dimensions
+     *      of input0.
+     *
+     * Outputs:
+     * * 0: An (n + k - 1)-D tensor with the same {@link OperandCode} as input0.
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint must be the same as input0.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_GATHER = 51,
+
+    /**
+     * Generate aixs-aligned bounding box proposals.
+     *
+     * Bounding box proposals are generated by applying transformation on a set
+     * of predefined anchors with the bounding box deltas from bounding box
+     * regression. A final step of hard NMS is applied to limit the number of
+     * returned boxes.
+     *
+     * Axis-aligned bounding boxes are represented by its upper-left corner
+     * coordinate (x1,y1) and lower-right corner coordinate (x2,y2). A valid
+     * bounding box should satisfy x1 <= x2 and y1 <= y2.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Inputs:
+     * * 0: A 4-D Tensor specifying the score of each anchor at each
+     *      location. With "NHWC" data layout, the tensor shape is
+     *      [batches, height, width, num_anchors]. With "NCHW" data layout,
+     *      the tensor shape is [batches, num_anchors, height, width].
+     * * 1: A 4-D Tensor specifying the bounding box deltas. With "NHWC" data
+     *      layout, the tensor shape is [batches, height, width, num_anchors * 4].
+     *      With "NCHW" data layout, the tensor shape is
+     *      [batches, num_anchors * 4, height, width]. The box deltas are encoded
+     *      in the order of [dx, dy, dw, dh], where dx and dy is the linear-scale
+     *      relative correction factor for the center position of the bounding box
+     *      with respect to the width and height, dw and dh is the log-scale
+     *      relative correction factor for the width and height. The last
+     *      dimensions is the channel dimension.
+     * * 2: A 2-D Tensor of shape [num_anchors, 4], specifying the shape of each
+     *      predefined anchor, with format [x1, y1, x2, y2]. For input0 of type
+     *      {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, this tensor should be of
+     *      {@link ANEURALNETWORKS_TENSOR_QUANT16_SYMM}, with scale of 0.125.
+     * * 3: A 2-D Tensor of shape [batches, 2], specifying the size of
+     *      each image in the batch, with format [image_height, image_width].
+     *      For input0 of type {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, this
+     *      tensor should be of {@link ANEURALNETWORKS_TENSOR_QUANT16_SYMM}, with
+     *      scale of 0.125.
+     * * 4: An {@link ANEURALNETWORKS_FLOAT32} scalar, specifying the ratio
+     *      from the height of original image to the height of feature map.
+     * * 5: An {@link ANEURALNETWORKS_FLOAT32} scalar, specifying the ratio
+     *      from the width of original image to the width of feature map.
+     * * 6: An {@link ANEURALNETWORKS_INT32} scalar, specifying the maximum
+     *      number of boxes before going into the hard NMS algorithm. Boxes
+     *      with the lowest scores are discarded to meet the limit. Set to
+     *      a non-positive value for unlimited number.
+     * * 7: An {@link ANEURALNETWORKS_INT32} scalar, specifying the maximum
+     *      number of boxes returning from the hard NMS algorithm. Boxes
+     *      with the lowest scores are discarded to meet the limit. Set to
+     *      a non-positive value for unlimited number.
+     * * 8: An {@link ANEURALNETWORKS_FLOAT32} scalar, specifying the IoU
+     *      threshold for hard NMS.
+     * * 9: An {@link ANEURALNETWORKS_FLOAT32} scalar, min_size. Boxes with
+     *      height or width lower than the absolute threshold are filtered out.
+     * * 10: An {@link ANEURALNETWORKS_BOOL} scalar, set to true to specify
+     *       NCHW data layout for input0 and input1. Set to false for NHWC.
+     *
+     * Outputs:
+     * * 0: A tensor of the same {@link OperandCode} as input0, of shape
+     *      [num_output_rois], specifying the score of each output box.
+     *      The boxes are grouped by batches, but the sequential order in
+     *      each batch is not guaranteed. For type of
+     *      {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, the scale and zero
+     *      point must be the same as input0.
+     * * 1: A tensor of the same {@link OperandCode} as input3, of shape
+     *      [num_output_rois, 4], specifying the coordinates of each output
+     *      bounding box for each class, with format [x1, y1, x2, y2].
+     *      The sequential order of the boxes corresponds with output0.
+     *      For type of {@link ANEURALNETWORKS_TENSOR_QUANT16_ASYMM}, the
+     *      scale must be 0.125 and the zero point must be 0.
+     * * 2: A 1-D {@link ANEURALNETWORKS_TENSOR_INT32} tensor, of shape
+     *      [num_output_rois], specifying the batch index of each box. Boxes
+     *      with the same batch index are grouped together.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_GENERATE_PROPOSALS = 52,
+
+    /**
+     * For input tensors x and y, computes x > y elementwise.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_BOOL8}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_INT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: from 1
+     *
+     * This operation supports broadcasting.
+     *
+     * Inputs:
+     * * 0: A tensor.
+     * * 1: A tensor of the same {@link OperandCode} and dimensions compatible
+     *      with input0.
+     *
+     * Outputs:
+     * * 0: A tensor of {@link ANEURALNETWORKS_TENSOR_BOOL8}.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_GREATER = 53,
+    /**
+     * For input tensors x and y, computes x >= y elementwise.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_BOOL8}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_INT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: from 1
+     *
+     * This operation supports broadcasting.
+     *
+     * Inputs:
+     * * 0: A tensor.
+     * * 1: A tensor of the same {@link OperandCode} and dimensions compatible
+     *      with input0.
+     *
+     * Outputs:
+     * * 0: A tensor of {@link ANEURALNETWORKS_TENSOR_BOOL8}.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_GREATER_EQUAL = 54,
+
+    /**
+     * Performs a grouped 2-D convolution operation.
+     *
+     * Given an input tensor of shape [batches, height, width, depth_in] and a
+     * filter tensor of shape [depth_out, filter_height, filter_width, depth_group]
+     * containing depth_out convolutional filters of depth depth_group, GROUPED_CONV
+     * applies a group of different filters to each input channel group, then
+     * concatenates the results together.
+     *
+     * Specifically, the input channels are divided into num_groups groups, each with
+     * depth depth_group, i.e. depth_in = num_groups * depth_group. The convolutional
+     * filters are also divided into num_groups groups, i.e. depth_out is divisible
+     * by num_groups. GROUPED_CONV applies each group of filters to the corresponding
+     * input channel group, and the result are concatenated together.
+     *
+     * The output dimensions are functions of the filter dimensions, stride, and
+     * padding.
+     *
+     * The values in the output tensor are computed as:
+     *
+     *     output[b, i, j, g * channel_multiplier + q] =
+     *         sum_{di, dj, dk} (
+     *             input[b, strides[1] * i + di, strides[2] * j + dj,
+     *                   g * depth_group + dk] *
+     *             filter[g * channel_multiplier + q, di, dj, dk]
+     *         ) + bias[channel]
+     *
+     * where channel_multiplier = depth_out / num_groups
+     *
+     * Supported tensor {@link OperandCode} configurations:
+     * * 16 bit floating point:
+     * * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} for input, filter, output, and bias.
+     *
+     * * 32 bit floating point:
+     * * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} for input, filter, output, and bias.
+     *
+     * * Quantized:
+     * * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} for input, filter, and output.
+     * * * {@link ANEURALNETWORKS_TENSOR_INT32} for bias (with scale set to
+     * * * input.scale * filter.scale).
+     *
+     * * Quantized with symmetric per channel quantization for the filter:
+     * * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} for input, and output.
+     * * * {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL} for filter.
+     * * * {@link ANEURALNETWORKS_TENSOR_INT32} for bias (scale set to 0.0,
+     * * * each value scaling is separate and equal to input.scale * filter.scales[channel]).
+     *
+     * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout.
+     * With the default data layout NHWC, the data is stored in the order of:
+     * [batch, height, width, channels]. Alternatively, the data layout could
+     * be NCHW, the data storage order of: [batch, channels, height, width].
+     *
+     * Both explicit padding and implicit padding are supported.
+     *
+     * Inputs (explicit padding):
+     * * 0: A 4-D tensor, of shape [batches, height, width, depth_in],
+     *      specifying the input, where depth_in = num_groups * depth_group.
+     * * 1: A 4-D tensor, of shape
+     *      [depth_out, filter_height, filter_width, depth_group], specifying
+     *      the filter, where depth_out must be divisible by num_groups.  For
+     *      tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL}
+     *      the channel dimension (channelDim at
+     *      {@link ANeuralNetworksSymmPerChannelQuantParams}) must be set to 0.
+     * * 2: A 1-D tensor, of shape [depth_out], specifying the bias. For input
+     *      tensor of type {@link ANEURALNETWORKS_TENSOR_FLOAT32} or
+     *      {@link ANEURALNETWORKS_TENSOR_FLOAT16}, the bias must be of the same
+     *      type. For filter tensor of {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM},
+     *      the bias should be of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint
+     *      of 0 and bias_scale == input_scale * filter_scale. For filter tensor
+     *      of {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL}, the bias
+     *      should be of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint of
+     *      0 and bias_scale of 0. The actual scale of each value 'i' is equal to
+     *      bias_scale[i] = input_scale * filter_scale[i].
+     * * 3: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on
+     *      the left, in the ‘width’ dimension.
+     * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on
+     *      the right, in the ‘width’ dimension.
+     * * 5: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on
+     *      the top, in the ‘height’ dimension.
+     * * 6: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on
+     *      the bottom, in the ‘height’ dimension.
+     * * 7: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when
+     *      walking through input in the ‘width’ dimension.
+     * * 8: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when
+     *      walking through input in the ‘height’ dimension.
+     * * 9: An {@link ANEURALNETWORKS_INT32} scalar, specifying the number of
+            groups.
+     * * 10: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the
+     *       {@link FuseCode} values. Specifies the activation to
+     *       invoke on the result.
+     * * 11: An {@link ANEURALNETWORKS_BOOL} scalar, set to true to specify
+     *       NCHW data layout for input0 and output0. Set to false for NHWC.
+     *
+     * Inputs (implicit padding):
+     * * 0: A 4-D tensor, of shape [batches, height, width, depth_in],
+     *      specifying the input, where depth_in = num_groups * depth_group.
+     * * 1: A 4-D tensor, of shape
+     *      [depth_out, filter_height, filter_width, depth_group], specifying
+     *      the filter, where depth_out must be divisible by num_groups.  For
+     *      tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL}
+     *      the channel dimension (channelDim at
+     *      {@link ANeuralNetworksSymmPerChannelQuantParams}) must be set to 0.
+     * * 2: A 1-D tensor, of shape [depth_out], specifying the bias. For input
+     *      tensor of type {@link ANEURALNETWORKS_TENSOR_FLOAT32} or
+     *      {@link ANEURALNETWORKS_TENSOR_FLOAT16}, the bias must be of the same
+     *      type. For filter tensor of {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM},
+     *      the bias should be of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint
+     *      of 0 and bias_scale == input_scale * filter_scale. For filter tensor
+     *      of {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL}, the bias
+     *      should be of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint of
+     *      0 and bias_scale of 0. The actual scale of each value 'i' is equal to
+     *      bias_scale[i] = input_scale * filter_scale[i].
+     * * 3: An {@link ANEURALNETWORKS_INT32} scalar, specifying the implicit
+     *      padding scheme, has to be one of the
+     *      {@link PaddingCode} values.
+     * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when
+     *      walking through input in the ‘width’ dimension.
+     * * 5: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when
+     *      walking through input in the ‘height’ dimension.
+     * * 6: An {@link ANEURALNETWORKS_INT32} scalar, specifying the number of
+     *      groups.
+     * * 7: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the
+     *      {@link FuseCode} values. Specifies the activation to
+     *      invoke on the result.
+     * * 8: An {@link ANEURALNETWORKS_BOOL} scalar, set to true to specify
+     *      NCHW data layout for input0 and output0. Set to false for NHWC.
+     *
+     * Outputs:
+     * * 0: The output 4-D tensor, of shape
+     *      [batches, out_height, out_width, depth_out].
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint can be different from inputs' scale and zeroPoint.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_GROUPED_CONV_2D = 55,
+
+    /**
+     * Localize the maximum keypoints from heatmaps.
+     *
+     * This operation approximates the accurate maximum keypoint scores and
+     * indices after bicubic upscaling by using Taylor expansion up to the
+     * quadratic term.
+     *
+     * The bounding box is represented by its upper-left corner coordinate
+     * (x1,y1) and lower-right corner coordinate (x2,y2) in the original image.
+     * A valid bounding box should satisfy x1 <= x2 and y1 <= y2.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout.
+     * With the default data layout NHWC, the data is stored in the order of:
+     * [batch, height, width, channels]. Alternatively, the data layout could
+     * be NCHW, the data storage order of: [batch, channels, height, width].
+     *
+     * Inputs:
+     * * 0: A 4-D Tensor of shape
+     *      [num_boxes, heatmap_size, heatmap_size, num_keypoints],
+     *      specifying the heatmaps, the height and width of heatmaps should
+     *      be the same, and must be greater than or equal to 2.
+     * * 1: A 2-D Tensor of shape [num_boxes, 4], specifying the bounding boxes,
+     *      each with format [x1, y1, x2, y2]. For input0 of type
+     *      {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, this tensor should
+     *      be of {@link ANEURALNETWORKS_TENSOR_QUANT16_ASYMM}, with zeroPoint
+     *      of 0 and scale of 0.125.
+     * * 2: An {@link ANEURALNETWORKS_BOOL} scalar, set to true to specify
+     *      NCHW data layout for input0. Set to false for NHWC.
+     *
+     * Outputs:
+     * * 0: A tensor of the same {@link OperandCode} as input0, with shape
+     *      [num_boxes, num_keypoints], specifying score of the keypoints.
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint can be different from input0 scale and zeroPoint.
+     * * 1: A tensor of the same {@link OperandCode} as input1, with shape
+     *      [num_boxes, num_keypoints, 2], specifying the location of
+     *      the keypoints, the second dimension is organized as
+     *      [keypoint_x, keypoint_y].
+     *      For type of {@link ANEURALNETWORKS_TENSOR_QUANT16_ASYMM}, the
+     *      scale must be 0.125 and the zero point must be 0.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_HEATMAP_MAX_KEYPOINT = 56,
+
+    /**
+     * Applies instance normalization to the input tensor.
+     *
+     * The values in the output tensor are computed as:
+     *
+     *     output[b, h, w, c] =
+     *         (input[b, h, w, c] - mean[b, c]) * gamma /
+     *         sqrt(var[b, c] + epsilon) + beta
+     *
+     * Where the mean and variance are computed across the spatial dimensions:
+     *
+     *     mean[b, c] =
+     *         sum_{h, w}(input[b, h, w, c]) / sum(1)
+     *
+     *     var[b, c] =
+     *         sum_{h, w}(pow(input[b, h, w, c] - mean[b, c], 2)) / sum(1)
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     *
+     * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout.
+     * With the default data layout NHWC, the data is stored in the order of:
+     * [batch, height, width, channels]. Alternatively, the data layout could
+     * be NCHW, the data storage order of: [batch, channels, height, width].
+     *
+     * Inputs:
+     * * 0: An n-D tensor, specifying the tensor to be normalized.
+     * * 1: A scalar, specifying gamma, the scale applied to the normalized
+     *      tensor. The scalar must be of {@link ANEURALNETWORKS_FLOAT16} if
+     *      input0 is of {@link ANEURALNETWORKS_TENSOR_FLOAT16} and of {@link
+     *      ANEURALNETWORKS_FLOAT32} if input0 is of {@link
+     *      ANEURALNETWORKS_TENSOR_FLOAT32}.
+     * * 2: A scalar, specifying beta, the offset applied to the normalized
+     *      tensor. The scalar must be of {@link ANEURALNETWORKS_FLOAT16} if
+     *      input0 is of {@link ANEURALNETWORKS_TENSOR_FLOAT16} and of {@link
+     *      ANEURALNETWORKS_FLOAT32} if input0 is of {@link
+     *      ANEURALNETWORKS_TENSOR_FLOAT32}.
+     * * 3: A scalar, specifying epsilon, the small value added to variance to
+     *      avoid dividing by zero. The scalar must be of {@link ANEURALNETWORKS_FLOAT16} if
+     *      input0 is of {@link ANEURALNETWORKS_TENSOR_FLOAT16} and of {@link
+     *      ANEURALNETWORKS_FLOAT32} if input0 is of {@link
+     *      ANEURALNETWORKS_TENSOR_FLOAT32}.
+     * * 4: An {@link ANEURALNETWORKS_BOOL} scalar, set to true to specify
+     *      NCHW data layout for input0 and output0. Set to false for NHWC.
+     *
+     * Outputs:
+     * * 0: A tensor of the same {@link OperandCode} and same shape as input0.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_INSTANCE_NORMALIZATION = 57,
+
+    /**
+     * For input tensors x and y, computes x < y elementwise.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_BOOL8}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_INT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: from 1
+     *
+     * This operation supports broadcasting.
+     *
+     * Inputs:
+     * * 0: A tensor.
+     * * 1: A tensor of the same {@link OperandCode} and dimensions compatible
+     *      with input0.
+     *
+     * Outputs:
+     * * 0: A tensor of {@link ANEURALNETWORKS_TENSOR_BOOL8}.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_LESS = 58,
+
+    /**
+     * For input tensors x and y, computes x <= y elementwise.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_BOOL8}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_INT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: from 1
+     *
+     * This operation supports broadcasting.
+     *
+     * Inputs:
+     * * 0: A tensor.
+     * * 1: A tensor of the same {@link OperandCode} and dimensions compatible
+     *      with input0.
+     *
+     * Outputs:
+     * * 0: A tensor of {@link ANEURALNETWORKS_TENSOR_BOOL8}.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_LESS_EQUAL = 59,
+
+    /**
+     * Computes natural logarithm of x element-wise.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     *
+     * Supported tensor rank: from 1.
+     *
+     * Inputs:
+     * * 0: A tensor.
+     *
+     * Outputs:
+     * * 0: The output tensor of same shape as input0.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_LOG = 60,
+
+    /**
+     * Returns the truth value of x AND y element-wise.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_BOOL8}
+     *
+     * Supported tensor rank: from 1
+     *
+     * This operation supports broadcasting.
+     *
+     * Inputs:
+     * * 0: A tensor of {@link ANEURALNETWORKS_TENSOR_BOOL8}.
+     * * 1: A tensor of {@link ANEURALNETWORKS_TENSOR_BOOL8} and dimensions
+     *      compatible with input0.
+     *
+     * Outputs:
+     * * 0: A tensor of {@link ANEURALNETWORKS_TENSOR_BOOL8}.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_LOGICAL_AND = 61,
+
+    /**
+     * Computes the truth value of NOT x element-wise.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_BOOL8}
+     *
+     * Supported tensor rank: from 1.
+     *
+     * Inputs:
+     * * 0: A tensor.
+     *
+     * Outputs:
+     * * 0: The output tensor of same shape as input0.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_LOGICAL_NOT = 62,
+
+    /**
+     * Returns the truth value of x OR y element-wise.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_BOOL8}
+     *
+     * Supported tensor rank: from 1
+     *
+     * This operation supports broadcasting.
+     *
+     * Inputs:
+     * * 0: A tensor of {@link ANEURALNETWORKS_TENSOR_BOOL8}.
+     * * 1: A tensor of {@link ANEURALNETWORKS_TENSOR_BOOL8} and dimensions
+     *      compatible with input0.
+     *
+     * Outputs:
+     * * 0: A tensor of {@link ANEURALNETWORKS_TENSOR_BOOL8}.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_LOGICAL_OR = 63,
+
+    /**
+     * Computes the log softmax activations given logits.
+     *
+     * The output is calculated using this formula:
+     *
+     *     output = logits * beta - log(reduce_sum(exp(logits * beta), axis))
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     *
+     * Supported tensor rank: from 1.
+     *
+     * Inputs:
+     * * 0: A tensor specifying the input logits.
+     * * 1: A scalar, specifying the positive scaling factor for the exponent,
+     *      beta.
+     *      For input tensor of {@link ANEURALNETWORKS_TENSOR_FLOAT16}, the beta
+     *      value must be of {@link ANEURALNETWORKS_FLOAT16}.
+     *      For input tensor of {@link ANEURALNETWORKS_TENSOR_FLOAT32}, the beta
+     *      value must be of {@link ANEURALNETWORKS_FLOAT32}.
+     * * 2: An {@link ANEURALNETWORKS_INT32} scalar specifying the axis to
+     *      reduce across. Negative index is used to specify axis from the
+     *      end (e.g. -1 for the last axis). Must be in the range [-n, n).
+     *
+     * Outputs:
+     * * 0: The output tensor of the same {@link OperandCode} and shape as
+     *      input0.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_LOG_SOFTMAX = 64,
+
+    /**
+     * Returns the element-wise maximum of two tensors.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_INT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: from 1.
+     *
+     * Inputs:
+     * * 0: A tensor.
+     * * 1: A tensor of the same {@link OperandCode} and compatible dimensions
+     *      with input0.
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scales and zeroPoint can be different from input0 scale and zeroPoint.
+     *
+     * Outputs:
+     * * 0: A tensor of the same {@link OperandCode} as input0.
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint can be different from inputs' scale and zeroPoint.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_MAXIMUM = 65,
+
+    /**
+     * Returns the element-wise minimum of two tensors.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_INT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: from 1.
+     *
+     * Inputs:
+     * * 0: A tensor.
+     * * 1: A tensor of the same {@link OperandCode} and compatible dimensions
+     *      with input0.
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scales and zeroPoint can be different from input0 scale and zeroPoint.
+     *
+     * Outputs:
+     * * 0: A tensor of the same {@link OperandCode} as input0.
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint can be different from inputs' scale and zeroPoint.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_MINIMUM = 66,
+
+    /**
+     * Computes numerical negative value element-wise.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_INT32}
+     *
+     * Supported tensor rank: from 1.
+     *
+     * Inputs:
+     * * 0: A tensor.
+     *
+     * Outputs:
+     * * 0: The output tensor of same shape as input0.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_NEG = 67,
+
+    /**
+     * For input tensors x and y, computes x != y elementwise.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_BOOL8}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_INT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: from 1
+     *
+     * This operation supports broadcasting.
+     *
+     * Inputs:
+     * * 0: A tensor.
+     * * 1: A tensor of the same {@link OperandCode} and dimensions compatible
+     *      with input0.
+     *
+     * Outputs:
+     * * 0: A tensor of {@link ANEURALNETWORKS_TENSOR_BOOL8}.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_NOT_EQUAL = 68,
+
+    /**
+     * Pads a tensor with the given constant value according to the specified
+     * paddings.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: up to 4
+     *
+     * Inputs:
+     * * 0: An n-D tensor, specifying the tensor to be padded.
+     * * 1: A 2-D Tensor of {@link ANEURALNETWORKS_TENSOR_INT32}, the paddings
+     *      for each spatial dimension of the input tensor. The shape of the
+     *      tensor must be {rank(input0), 2}.
+     *      padding[i, 0] specifies the number of elements to be padded in the
+     *      front of dimension i.
+     *      padding[i, 1] specifies the number of elements to be padded after
+     *      the end of dimension i.
+     * * 2: An scalar specifying the value to use for padding input0.
+     *      For input tensor of {@link ANEURALNETWORKS_TENSOR_FLOAT16}, the
+     *      pad value must be of {@link ANEURALNETWORKS_FLOAT16}.
+     *      For input tensor of {@link ANEURALNETWORKS_TENSOR_FLOAT32}, the
+     *      pad value must be of {@link ANEURALNETWORKS_FLOAT32}.
+     *      For input tensor of {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM},
+     *      the pad value must be of {@link ANEURALNETWORKS_INT32}. The
+     *      scale and zeroPoint are assumed to be the same as in input0.
+     *
+     * Outputs:
+     * * 0: A tensor of the same {@link OperandCode} as input0. The
+     *      output tensor has the same rank as input0, and each
+     *      dimension of the output tensor has the same size as the
+     *      corresponding dimension of the input tensor plus the size
+     *      of the padding:
+     *          output0.dimension[i] =
+     *              padding[i, 0] + input0.dimension[i] + padding[i, 1]
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint must be the same as input0.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_PAD_V2 = 69,
+
+    /**
+     * Computes the power of one value to another.
+     *
+     * Given a tensor base and a tensor exponent, this operation computes
+     * base^exponent elementwise.
+     *
+     * This operations supports broadcasting. The size of the output is the
+     * maximum size along each dimension of the input operands. It starts with
+     * the trailing dimensions, and works its way forward.
+     *
+     * For example:
+     *     base.dimension     =    {4, 1, 2}
+     *     exponent.dimension = {5, 4, 3, 1}
+     *     output.dimension   = {5, 4, 3, 2}
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     *
+     * Supported tensor rank: from 1
+     *
+     * Inputs:
+     * * 0: A tensor specifying the base.
+     * * 1: A tensor specifying the exponent.
+     *
+     * Outputs:
+     * * 0: An output tensor.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_POW = 70,
+
+    /**
+     * Parametric Rectified Linear Unit.
+     *
+     * It follows: f(x) = alpha * x for x < 0, f(x) = x for x >= 0, where alpha
+     * is a learned array with the same {@link OperandCode} and compatible
+     * dimensions as input x.
+     *
+     * Two dimensions are compatible when:
+     *     1. they are equal, or
+     *     2. one of them is 1
+     *
+     * The size of the output is the maximum size along each dimension of the
+     * input operands. It starts with the trailing dimensions, and works its way
+     * forward.
+     *
+     * Example:
+     *     input.dimension  =    {4, 1, 2}
+     *     alpha.dimension  = {5, 4, 3, 1}
+     *     output.dimension = {5, 4, 3, 2}
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: from 1
+     *
+     * Inputs:
+     * * 0: A tensor, specifying the input.
+     * * 1: A tensor of the same {@link OperandCode}, and compatible dimensions
+     *      as input0, specifying the alpha.
+     *
+     * Outputs:
+     * * 0: A tensor of the same {@link OperandCode} as input0.
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint can be diffent from the input0 scale and zeroPoint.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_PRELU = 71,
+
+    /**
+     * Quantizes the input tensor.
+     *
+     * The formula is:
+     *
+     *     output = max(0, min(255, round(input / scale) + zeroPoint)
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     *
+     * Supported tensor rank: from 1
+     *
+     * Inputs:
+     * * 0: A tensor, may be zero-sized.
+     *
+     * Outputs:
+     * * 0: The output tensor of same shape as input0, but with
+     *      {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_QUANTIZE = 72,
+
+    /**
+     * A version of quantized LSTM, using 16 bit quantization for internal
+     * state.
+     *
+     * There is no projection layer, so cell state size is equal to the output
+     * size.
+     *
+     * Inputs:
+     * * 0: A 2-D tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *      and shape [numBatches, inputSize] specifying the input to the LSTM
+     *      cell. Tensor is quantized with a fixed quantization range of
+     *      [-1, 127/128] (scale = 1/128, zeroPoint = 128).
+     * * 1: The input-to-input weights.
+     *      A 2-D tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *      and shape [outputSize, inputSize] specifying input-to-input part of
+     *      weights for fully-connected layer inside the LSTM cell.
+     *      Quantization zero point and scale must be the same across all the
+     *      weights.
+     * * 2: The input-to-forget weights.
+     *      A 2-D tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *      and shape [outputSize, inputSize] specifying input-to-forget part of
+     *      weights for fully-connected layer inside the LSTM cell.
+     *      Quantization zero point and scale must be the same across all the
+     *      weights.
+     * * 3: The input-to-cell weights.
+     *      A 2-D tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *      and shape [outputSize, inputSize] specifying input-to-cell part of
+     *      weights for fully-connected layer inside the LSTM cell.
+     *      Quantization zero point and scale must be the same across all the
+     *      weights.
+     * * 4: The input-to-output weights.
+     *      A 2-D tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *      and shape [outputSize, inputSize] specifying input-to-output part of
+     *      weights for fully-connected layer inside the LSTM cell.
+     *      Quantization zero point and scale must be the same across all the
+     *      weights.
+     * * 5: The recurrent-to-input weights.
+     *      A 2-D tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *      and shape [outputSize, outputSize] specifying recurrent-to-input part
+     *      of weights for fully-connected layer inside the LSTM cell.
+     *      Quantization zero point and scale must be the same across all the
+     *      weights.
+     * * 6: The recurrent-to-forget weights.
+     *      A 2-D tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *      and shape [outputSize, outputSize] specifying recurrent-to-forget
+     *      part of weights for fully-connected layer inside the LSTM cell.
+     *      Quantization zero point and scale must be the same across all the
+     *      weights.
+     * * 7: The recurrent-to-cell weights.
+     *      A 2-D tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *      and shape [outputSize, outputSize] specifying recurrent-to-cell part
+     *      of weights for fully-connected layer inside the LSTM cell.
+     *      Quantization zero point and scale must be the same across all the
+     *      weights.
+     * * 8: The recurrent-to-output weights.
+     *      A 2-D tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *      and shape [outputSize, outputSize] specifying recurrent-to-output
+     *      part of weights for fully-connected layer inside the LSTM cell.
+     *      Quantization zero point and scale must be the same across all the
+     *      weights.
+     * * 9: The input gate bias.
+     *      A 1-D tensor of type {@link ANEURALNETWORKS_TENSOR_INT32} and shape
+     *      [outputSize] specifying the bias for the fully-connected layer
+     *      inside the LSTM cell. Bias is quantized with scale being a product
+     *      of input and weights scales and zeroPoint equal to 0.
+     * * 10:The forget gate bias.
+     *      A 1-D tensor of type {@link ANEURALNETWORKS_TENSOR_INT32} and shape
+     *      [outputSize] specifying the bias for the fully-connected layer
+     *      inside the LSTM cell. Bias is quantized with scale being a product
+     *      of input and weights scales and zeroPoint equal to 0.
+     * * 11:The cell bias.
+     *      A 1-D tensor of type {@link ANEURALNETWORKS_TENSOR_INT32} and shape
+     *      [outputSize] specifying the bias for the fully-connected layer
+     *      inside the LSTM cell. Bias is quantized with scale being a product
+     *      of input and weights scales and zeroPoint equal to 0.
+     * * 12:The output gate bias.
+     *      A 1-D tensor of type {@link ANEURALNETWORKS_TENSOR_INT32} and shape
+     *      [outputSize] specifying the bias for the fully-connected layer
+     *      inside the LSTM cell. Bias is quantized with scale being a product
+     *      of input and weights scales and zeroPoint equal to 0.
+     * * 13: A 2-D tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT16_SYMM}
+     *       and shape [numBatches, outputSize] specifying the cell state from the
+     *       previous time step of the LSTM cell. It is quantized using a
+     *       quantization range of [-2^4, 2^4 * 32767/32768] (scale = 2^4 /
+     *       32768, zeroPoint = 0).
+     * * 14: A 2-D tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *       and shape [numBathes, outputSize] specifying the output of the LSTM
+     *       cell from previous time-step. Tensor is quantized with a fixed
+     *       quantization range of [-1, 127/128] (scale = 1/128, zeroPoint =
+     *       128).
+     *
+     *
+     * Outputs:
+     * * 0: A 2-D tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT16_SYMM}
+     *      and shape [numBatches, outputSize] which contains a cell state from
+     *      the current time step. Tensor is quantized using a quantization
+     *      range of [-2^4, 2^4 * 32767/32768] (scale = 2^4 / 32768, zeroPoint =
+     *      0).
+     * * 1: A 2-D tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *      and shape [numBathes, outputSize] which contains the output value.
+     *      Tensor is quantized with a fixed quantization range of [-1, 127/128]
+     *      (scale = 1/128, zeroPoint = 128).
+     */
+    ANEURALNETWORKS_QUANTIZED_16BIT_LSTM = 73,
+
+    /**
+     * Draws samples from a multinomial distribution.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     *
+     * Inputs:
+     * * 0: A 2-D tensor with shape [batches, classes], specifying the
+     *      unnormalized log-probabilities for all classes.
+     * * 1: A scalar {@link ANEURALNETWORKS_INT32}, specifying the number of
+     *      independent samples to draw for each row slice.
+     * * 2: A 1-D {@link ANEURALNETWORKS_TENSOR_INT32} tensor with shape [2],
+     *      specifying seeds used to initialize the random distribution.
+     * Outputs:
+     * * 0: A 2-D {@link ANEURALNETWORKS_TENSOR_INT32} tensor with shape
+     *      [batches, samples], containing the drawn samples.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_RANDOM_MULTINOMIAL = 74,
+
+    /**
+     * Reduces a tensor by computing the "logical and" of elements along given
+     * dimensions.
+     *
+     * If keep_dims is true, the reduced dimensions are
+     * retained with length 1. Otherwise, the rank of the tensor is reduced by
+     * 1 for each entry in dimensions.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_BOOL8}
+     *
+     * Supported tensor rank: up to 4
+     *
+     * Inputs:
+     * * 0: An n-D tensor.
+     * * 1: A 1-D tensor of {@link ANEURALNETWORKS_TENSOR_INT32}. The dimensions
+     *      to reduce. Dimension values must be in the range [-n, n).
+     * * 2: An {@link ANEURALNETWORKS_BOOL} scalar, keep_dims. If true,
+     *      retains reduced dimensions with length 1.
+     *
+     * Outputs:
+     * * 0: A tensor of the same {@link OperandCode} as input0.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_REDUCE_ALL = 75,
+
+    /**
+     * Reduces a tensor by computing the "logical or" of elements along given
+     * dimensions.
+     *
+     * If keep_dims is true, the reduced dimensions are
+     * retained with length 1. Otherwise, the rank of the tensor is reduced by
+     * 1 for each entry in dimensions.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_BOOL8}
+     *
+     * Supported tensor rank: up to 4
+     *
+     * Inputs:
+     * * 0: An n-D tensor.
+     * * 1: A 1-D tensor of {@link ANEURALNETWORKS_TENSOR_INT32}. The dimensions
+     *      to reduce. Dimension values must be in the range [-n, n).
+     * * 2: An {@link ANEURALNETWORKS_BOOL} scalar, keep_dims. If true,
+     *      retains reduced dimensions with length 1.
+     *
+     * Outputs:
+     * * 0: A tensor of the same {@link OperandCode} as input0.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_REDUCE_ANY = 76,
+
+    /**
+     * Reduces a tensor by computing the maximum of elements along given
+     * dimensions.
+     *
+     * If keep_dims is true, the reduced dimensions are
+     * retained with length 1. Otherwise, the rank of the tensor is reduced by
+     * 1 for each entry in dimensions.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: up to 4
+     *
+     * Inputs:
+     * * 0: An n-D tensor.
+     * * 1: A 1-D tensor of {@link ANEURALNETWORKS_TENSOR_INT32}. The dimensions
+     *      to reduce. Dimension values must be in the range [-n, n).
+     * * 2: An {@link ANEURALNETWORKS_BOOL} scalar, keep_dims. If true,
+     *      retains reduced dimensions with length 1.
+     *
+     * Outputs:
+     * * 0: A tensor of the same {@link OperandCode} as input0.
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint must be the same as input0.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_REDUCE_MAX = 77,
+
+    /**
+     * Reduces a tensor by computing the minimum of elements along given
+     * dimensions.
+     *
+     * If keep_dims is true, the reduced dimensions are
+     * retained with length 1. Otherwise, the rank of the tensor is reduced by
+     * 1 for each entry in dimensions.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: up to 4
+     *
+     * Inputs:
+     * * 0: An n-D tensor.
+     * * 1: A 1-D tensor of {@link ANEURALNETWORKS_TENSOR_INT32}. The dimensions
+     *      to reduce. Dimension values must be in the range [-n, n).
+     * * 2: An {@link ANEURALNETWORKS_BOOL} scalar, keep_dims. If true,
+     *      retains reduced dimensions with length 1.
+     *
+     * Outputs:
+     * * 0: A tensor of the same {@link OperandCode} as input0.
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint must be the same as input0.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_REDUCE_MIN = 78,
+
+    /**
+     * Reduces a tensor by multiplying elements along given dimensions.
+     *
+     * If keep_dims is true, the reduced dimensions are
+     * retained with length 1. Otherwise, the rank of the tensor is reduced by
+     * 1 for each entry in dimensions.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     *
+     * Supported tensor rank: up to 4
+     *
+     * Inputs:
+     * * 0: An n-D tensor.
+     * * 1: A 1-D tensor of {@link ANEURALNETWORKS_TENSOR_INT32}. The dimensions
+     *      to reduce. Dimension values must be in the range [-n, n).
+     * * 2: An {@link ANEURALNETWORKS_BOOL} scalar, keep_dims. If true,
+     *      retains reduced dimensions with length 1.
+     *
+     * Outputs:
+     * * 0: A tensor of the same {@link OperandCode} as input0.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_REDUCE_PROD = 79,
+
+    /**
+     * Reduces a tensor by summing elements along given dimensions.
+     *
+     * If keep_dims is true, the reduced dimensions are
+     * retained with length 1. Otherwise, the rank of the tensor is reduced by
+     * 1 for each entry in dimensions.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     *
+     * Supported tensor rank: up to 4
+     *
+     * Inputs:
+     * * 0: An n-D tensor.
+     * * 1: A 1-D tensor of {@link ANEURALNETWORKS_TENSOR_INT32}. The dimensions
+     *      to reduce. Dimension values must be in the range [-n, n).
+     * * 2: An {@link ANEURALNETWORKS_BOOL} scalar, keep_dims. If true,
+     *      retains reduced dimensions with length 1.
+     *
+     * Outputs:
+     * * 0: A tensor of the same {@link OperandCode} as input0.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_REDUCE_SUM = 80,
+
+    /**
+     * Select and scale the feature map of each region of interest to a unified
+     * output size by average pooling sampling points from bilinear interpolation.
+     *
+     * The region of interest is represented by its upper-left corner coordinate
+     * (x1,y1) and lower-right corner coordinate (x2,y2) in the original image.
+     * A spatial scaling factor is applied to map into feature map coordinate.
+     * A valid region of interest should satisfy x1 <= x2 and y1 <= y2.
+     *
+     * No rounding is applied in this operation. The sampling points are unified
+     * distributed in the pooling bin and their values are calculated by bilinear
+     * interpolation.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29)
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout.
+     * With the default data layout NHWC, the data is stored in the order of:
+     * [batch, height, width, channels]. Alternatively, the data layout could
+     * be NCHW, the data storage order of: [batch, channels, height, width].
+     *
+     * Inputs:
+     * * 0: A 4-D tensor, specifying the feature map.
+     * * 1: A 2-D Tensor of shape [num_rois, 4], specifying the locations of
+     *      the regions of interest, each line with format [x1, y1, x2, y2].
+     *      For input0 of type {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM},
+     *      this tensor should be of {@link ANEURALNETWORKS_TENSOR_QUANT16_ASYMM},
+     *      with zeroPoint of 0 and scale of 0.125. Zero num_rois is
+     *      supported for this tensor.
+     * * 2: An 1-D {@link ANEURALNETWORKS_TENSOR_INT32} tensor, of shape
+     *      [num_rois], specifying the batch index of each box. Boxes with
+     *      the same batch index are grouped together. Zero num_rois is
+     *      supported for this tensor.
+     * * 3: An {@link ANEURALNETWORKS_INT32} scalar, specifying the output
+     *      height of the output tensor.
+     * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the output
+     *      width of the output tensor.
+     * * 5: An {@link ANEURALNETWORKS_FLOAT32} scalar, specifying the ratio
+     *      from the height of original image to the height of feature map.
+     * * 6: An {@link ANEURALNETWORKS_FLOAT32} scalar, specifying the ratio
+     *      from the width of original image to the width of feature map.
+     * * 7: An {@link ANEURALNETWORKS_INT32} scalar, specifying the number of
+     *      sampling points in height dimension used to compute the output.
+     *      Set to 0 for adaptive value of ceil(roi_height/out_height).
+     * * 8: An {@link ANEURALNETWORKS_INT32} scalar, specifying the number of
+     *      sampling points in width dimension used to compute the output.
+     *      Set to 0 for adaptive value of ceil(roi_width/out_width).
+     * * 9: An {@link ANEURALNETWORKS_BOOL} scalar, set to true to specify
+     *      NCHW data layout for input0 and output0. Set to false for NHWC.
+     *
+     * Outputs:
+     * * 0: A tensor of the same {@link OperandCode} as input0. The output
+     *      shape is [num_rois, out_height, out_width, depth].
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint can be different from the input0 scale and zeroPoint.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_ROI_ALIGN = 81,
+
+    /**
+     * Select and scale the feature map of each region of interest to a unified
+     * output size by max-pooling.
+     *
+     * The region of interest is represented by its upper-left corner coordinate
+     * (x1,y1) and lower-right corner coordinate (x2,y2) in the original image.
+     * A spatial scaling factor is applied to map into feature map coordinate.
+     * A valid region of interest should satisfy x1 <= x2 and y1 <= y2.
+     *
+     * Rounding is applied in this operation to ensure integer boundary for
+     * regions of interest and pooling bins.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout.
+     * With the default data layout NHWC, the data is stored in the order of:
+     * [batch, height, width, channels]. Alternatively, the data layout could
+     * be NCHW, the data storage order of: [batch, channels, height, width].
+     *
+     * Inputs:
+     * * 0: A 4-D tensor, specifying the feature map.
+     * * 1: A 2-D Tensor of shape [num_rois, 4], specifying the locations of
+     *      the regions of interest, each line with format [x1, y1, x2, y2].
+     *      For input0 of type {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM},
+     *      this tensor should be of {@link ANEURALNETWORKS_TENSOR_QUANT16_ASYMM},
+     *      with zeroPoint of 0 and scale of 0.125.
+     * * 2: An 1-D {@link ANEURALNETWORKS_TENSOR_INT32} tensor, of shape
+     *      [num_rois], specifying the batch index of each box. Boxes with
+     *      the same batch index are grouped together.
+     * * 3: An {@link ANEURALNETWORKS_INT32} scalar, specifying the output
+     *      height of the output tensor.
+     * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the output
+     *      width of the output tensor.
+     * * 5: An {@link ANEURALNETWORKS_FLOAT32} scalar, specifying the ratio
+     *      from the height of original image to the height of feature map.
+     * * 6: An {@link ANEURALNETWORKS_FLOAT32} scalar, specifying the ratio
+     *      from the width of original image to the width of feature map.
+     * * 7: An {@link ANEURALNETWORKS_BOOL} scalar, set to true to specify
+     *      NCHW data layout for input0 and output0. Set to false for NHWC.
+     *
+     * Outputs:
+     * * 0: A tensor of the same {@link OperandCode} as input0. The output
+     *      shape is [num_rois, out_height, out_width, depth].
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint must be the same as input0.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_ROI_POOLING = 82,
+
+    /**
+     * Computes reciprocal of square root of x element-wise.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     *
+     * Supported tensor rank: from 1.
+     *
+     * Inputs:
+     * * 0: A tensor.
+     *
+     * Outputs:
+     * * 0: The output tensor of same shape as input0.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_RSQRT = 83,
+
+    /**
+     * Using a tensor of booleans c and input tensors x and y select values
+     * elementwise from both input tensors:
+     *
+     * O[i] = C[i] ? x[i] : y[i].
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_INT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: from 1
+     *
+     * Inputs:
+     * * 0: A tensor of type {@link ANEURALNETWORKS_TENSOR_BOOL8} acting as a
+     *      mask that chooses, based on the value at each element, whether the
+     *      corresponding element in the output should be taken from input1 (if
+     *      true) or input2 (if false).
+     * * 1: An input tensor of the same shape as input0.
+     * * 2: An input tensor of the same shape and type as input1.
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scales and zeroPoint can be different from input1 scale and zeroPoint.
+     *
+     * Outputs:
+     * * 0: A tensor of the same type and shape as input1 and input2.
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint can be different from inputs' scale and zeroPoint.
+     *
+     */
+    ANEURALNETWORKS_SELECT = 84,
+
+    /**
+     * Computes sin of x element-wise.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     *
+     * Supported tensor rank: from 1.
+     *
+     * Inputs:
+     * * 0: A tensor.
+     *
+     * Outputs:
+     * * 0: The output tensor of same shape as input0.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_SIN = 85,
+
+    /**
+     * Extracts a slice of specified size from the input tensor starting at a
+     * specified location.
+     *
+     * The starting location is specified as a 1-D tensor containing offsets
+     * for each dimension. The size is specified as a 1-D tensor containing
+     * either size of a slice along corresponding dimension or -1. In the latter
+     * case, all the remaining elements in dimension are included in the slice.
+     *
+     * A sum of begin offset and a size of a slice must not exceed size of a
+     * corresponding dimension.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_INT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: from 1
+     *
+     * Inputs:
+     * * 0: An n-D tensor to take slice from, may be zero-sized.
+     * * 1: A 1-D tensor of type {@link ANEURALNETWORKS_TENSOR_INT32} specifying
+     *      the beginning indices of the slice in each dimension.
+     * * 2: A 1-D tensor of type {@link ANEURALNETWORKS_TENSOR_INT32} specifying
+     *      the size of the slice in each dimension.
+     *
+     * Outputs:
+     * * 0: An n-D tensor of the same type as the input containing the slice.
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      its scale and zeroPoint has to be same as the input0 scale and zeroPoint.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_SLICE = 86,
+
+    /**
+     * Splits a tensor along a given axis into num_splits subtensors.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_INT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: from 1
+     *
+     * Inputs:
+     * * 0: An n-D tensor to split.
+     * * 1: An {@link ANEURALNETWORKS_INT32} scalar specifying the axis along
+     *      which to split.
+     * * 2: An {@link ANEURALNETWORKS_INT32} scalar indicating the number of
+     *      splits along given axis. Must evenly divide axis size.
+     *
+     * Outputs:
+     * * 0 ~ (num_splits - 1): Resulting subtensors.
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint must be the same as input0.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_SPLIT = 87,
+
+    /**
+     * Computes square root of x element-wise.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     *
+     * Supported tensor rank: from 1.
+     *
+     * Inputs:
+     * * 0: A tensor.
+     *
+     * Outputs:
+     * * 0: The output tensor of same shape as input0.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_SQRT = 88,
+
+    /**
+     * Constructs a tensor by tiling a given tensor.
+     *
+     * This operation creates a new tensor by replicating `input` `multiples`
+     * times. The output tensor's i-th dimension has `input.dims(i) * multiples[i]`
+     * elements, and the values of `input` are replicated `multiples[i]` times
+     * along the i-th dimension.
+     * For example, tiling `[a b c d]` by `[2]` produces `[a b c d a b c d]`.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_INT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: from 1
+     *
+     * Inputs:
+     * * 0: input, an n-D tensor specifying the input.
+     * * 1: multiples, a 1-D tensor of {@link ANEURALNETWORKS_TENSOR_INT32}.
+     *      The length of multiples must be n.
+     *
+     * Outputs:
+     * * 0: A tiled tensor of the same {@link OperandCode} and rank as `input`.
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint must be the same as input0.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_TILE = 89,
+
+    /**
+     * Finds values and indices of the k largest entries for the last dimension.
+     *
+     * Resulting values in each dimensions are sorted in descending order. If
+     * two values are equal, the one with larger index appears first.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_INT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: from 1
+     *
+     * Inputs:
+     * * 0: input, an n-D tensor specifying the input.
+     * * 1: k, an {@link ANEURALNETWORKS_INT32} scalar, specifying the number of
+     *      top elements to look for along the last dimension.
+     *
+     * Outputs:
+     * * 0: An n-D tensor of the same type as the input, containing the k
+     *      largest elements along each last dimensional slice.
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint must be the same as input0.
+     * * 1: An n-D tensor of type {@link ANEURALNETWORKS_TENSOR_INT32}
+     *      containing the indices of values within the last dimension of input.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_TOPK_V2 = 90,
+
+    /**
+     * Performs the transpose of 2-D convolution operation.
+     *
+     * This operation is sometimes called "deconvolution" after Deconvolutional
+     * Networks, but is actually the transpose (gradient) of
+     * {@link ANEURALNETWORKS_CONV_2D} rather than an actual deconvolution.
+     *
+     * The output dimensions are functions of the filter dimensions, stride, and
+     * padding.
+     *
+     * Supported tensor {@link OperandCode} configurations:
+     * * 16 bit floating point:
+     * * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} for input, filter, output, and bias.
+     *
+     * * 32 bit floating point:
+     * * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} for input, filter, output, and bias.
+     *
+     * * Quantized:
+     * * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} for input, filter, and output.
+     * * * {@link ANEURALNETWORKS_TENSOR_INT32} for bias (with scale set to
+     * * * input.scale * filter.scale).
+     *
+     * * Quantized with symmetric per channel quantization for the filter:
+     * * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} for input, and output.
+     * * * {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL} for filter.
+     * * * {@link ANEURALNETWORKS_TENSOR_INT32} for bias (scale set to 0.0,
+     * * * each value scaling is separate and equal to input.scale * filter.scales[channel]).
+     *
+     * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout.
+     * With the default data layout NHWC, the data is stored in the order of:
+     * [batch, height, width, channels]. Alternatively, the data layout could
+     * be NCHW, the data storage order of: [batch, channels, height, width].
+     *
+     * Both explicit padding and implicit padding are supported.
+     *
+     * Inputs (explicit padding):
+     * * 0: A 4-D tensor, of shape [batches, height, width, depth_in],
+     *      specifying the input. Since API level 29, zero batches is supported
+     *      for this tensor.
+     * * 1: A 4-D tensor, of shape
+     *      [depth_out, filter_height, filter_width, depth_in], specifying the
+     *      filter. For tensor of type
+     *      {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL} the channel
+     *      dimension (extraParams.channelQuant.channelDim) must be set to 0.
+     * * 2: A 1-D tensor, of shape [depth_out], specifying the bias. For input
+     *      tensor of type {@link ANEURALNETWORKS_TENSOR_FLOAT32} or
+     *      {@link ANEURALNETWORKS_TENSOR_FLOAT16}, the bias should be of the
+     *      same type. For input tensor of type
+     *      {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, the bias should be
+     *      of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint of 0 and
+     *      bias_scale == input_scale * filter_scale. For filter tensor of
+     *      {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL}, the bias
+     *      must be of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint of
+     *      0 and bias_scale of 0. The actual scale of each value 'i' is equal
+     *      to bias_scale[i] = input_scale * filter_scale[i].
+     * * 3: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on
+     *      the left, in the ‘width’ dimension.
+     * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on
+     *      the right, in the ‘width’ dimension.
+     * * 5: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on
+     *      the top, in the ‘height’ dimension.
+     * * 6: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on
+     *      the bottom, in the ‘height’ dimension.
+     * * 7: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when
+     *      walking through input in the ‘width’ dimension.
+     * * 8: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when
+     *      walking through input in the ‘height’ dimension.
+     * * 9: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the
+     *      {@link FuseCode} values. Specifies the activation to
+     *      invoke on the result.
+     * * 10: An {@link ANEURALNETWORKS_BOOL} scalar, set to true to specify
+     *       NCHW data layout for input0 and output0. Set to false for NHWC.
+     *
+     * Inputs (implicit padding):
+     * * 0: A 4-D tensor, of shape [batches, height, width, depth_in],
+     *      specifying the input. Since API level 29, zero batches is supported
+     *      for this tensor.
+     * * 1: A 4-D tensor, of shape
+     *      [depth_out, filter_height, filter_width, depth_in], specifying the
+     *      filter. For tensor of type
+     *      {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL} the channel
+     *      dimension (extraParams.channelQuant.channelDim) must be set to 0.
+     * * 2: A 1-D tensor, of shape [depth_out], specifying the bias. For input
+     *      tensor of type {@link ANEURALNETWORKS_TENSOR_FLOAT32} or
+     *      {@link ANEURALNETWORKS_TENSOR_FLOAT16}, the bias should be of the
+     *      same type. For input tensor of type
+     *      {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, the bias should be
+     *      of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint of 0 and
+     *      bias_scale == input_scale * filter_scale. For filter tensor of
+     *      {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL}, the bias
+     *      must be of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint of
+     *      0 and bias_scale of 0. The actual scale of each value 'i' is equal
+     *      to bias_scale[i] = input_scale * filter_scale[i].
+     * * 3: An {@link ANEURALNETWORKS_TENSOR_INT32} tensor, specifying the output
+     *      tensor shape.
+     * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the implicit
+     *      padding scheme, has to be one of the
+     *      {@link PaddingCode} values.
+     * * 5: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when
+     *      walking through input in the ‘width’ dimension.
+     * * 6: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when
+     *      walking through input in the ‘height’ dimension.
+     * * 7: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the
+     *      {@link FuseCode} values. Specifies the activation to
+     *      invoke on the result.
+     * * 8: An {@link ANEURALNETWORKS_BOOL} scalar, set to true to specify
+     *      NCHW data layout for input0 and output0. Set to false for NHWC.
+     *
+     * Outputs:
+     * * 0: The output 4-D tensor, of shape
+     *      [batches, out_height, out_width, depth_out].
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint can be different from inputs' scale and zeroPoint.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_TRANSPOSE_CONV_2D = 91,
+
+    /**
+     * A recurrent neural network specified by an LSTM cell.
+     *
+     * Performs (fully) dynamic unrolling of input.
+     *
+     * This Op unrolls the input along the time dimension, and implements the
+     * following operation for each element in the sequence
+     * s = 1...sequence_length:
+     *   outputs[s] = projection(state = activation(LSTMOp(inputs[s])))
+     *
+     * Where LSTMOp is the LSTM op as in {@link ANEURALNETWORKS_LSTM},
+     * the "projection" is an optional projection layer from state and output
+     * and the “activation” is the function passed as the
+     * “fused_activation_function” argument (if not “NONE”).
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     *
+     * Supported tensor rank: 3, either time-major or batch-major.
+     *
+     * All input and output tensors must be of the same type.
+     *
+     * Inputs:
+     * * 0: The input (\f$x_t\f$).
+     *      A 3-D tensor of shape:
+     *        If time-major: [max_time, batch_size, input_size]
+     *        If batch-major: [batch_size, max_time, input_size]
+     *      where “max_time” is the number of timesteps (sequence length),
+     *      “batch_size” corresponds to the batching dimension, and
+     *      “input_size” is the size of the input.
+     * * 1: The input-to-input weights (\f$W_{xi}\f$). Optional.
+     *      A 2-D tensor of shape [num_units, input_size], where “num_units”
+     *      corresponds to the number of cell units.
+     * * 2: The input-to-forget weights (\f$W_{xf}\f$).
+     *      A 2-D tensor of shape [num_units, input_size].
+     * * 3: The input-to-cell weights (\f$W_{xc}\f$).
+     *      A 2-D tensor of shape [num_units, input_size].
+     * * 4: The input-to-output weights (\f$W_{xo}\f$).
+     *      A 2-D tensor of shape [num_units, input_size].
+     * * 5: The recurrent-to-input weights (\f$W_{hi}\f$). Optional.
+     *      A 2-D tensor of shape [num_units, output_size], where “output_size”
+     *      corresponds to either the number of cell units (i.e., “num_units”),
+     *      or the second dimension of the “projection_weights”, if defined.
+     * * 6: The recurrent-to-forget weights (\f$W_{hf}\f$).
+     *      A 2-D tensor of shape [num_units, output_size].
+     * * 7: The recurrent-to-cell weights (\f$W_{hc}\f$).
+     *      A 2-D tensor of shape [num_units, output_size].
+     * * 8: The recurrent-to-output weights (\f$W_{ho}\f$).
+     *      A 2-D tensor of shape [num_units, output_size].
+     * * 9: The cell-to-input weights (\f$W_{ci}\f$). Optional.
+     *      A 1-D tensor of shape [num_units].
+     * * 10:The cell-to-forget weights (\f$W_{cf}\f$). Optional.
+     *      A 1-D tensor of shape [num_units].
+     * * 11:The cell-to-output weights (\f$W_{co}\f$). Optional.
+     *      A 1-D tensor of shape [num_units].
+     * * 12:The input gate bias (\f$b_i\f$). Optional.
+     *      A 1-D tensor of shape [num_units].
+     * * 13:The forget gate bias (\f$b_f\f$).
+     *      A 1-D tensor of shape [num_units].
+     * * 14:The cell bias (\f$b_c\f$).
+     *      A 1-D tensor of shape [num_units].
+     * * 15:The output gate bias (\f$b_o\f$).
+     *      A 1-D tensor of shape [num_units].
+     * * 16:The projection weights (\f$W_{proj}\f$). Optional.
+     *      A 2-D tensor of shape [output_size, num_units].
+     * * 17:The projection bias (\f$b_{proj}\f$). Optional.
+     *      A 1-D tensor of shape [output_size].
+     * * 18:The output state (in) (\f$h_{t-1}\f$).
+     *      A 2-D tensor of shape [batch_size, output_size].
+     * * 19:The cell state (in) (\f$C_{t-1}\f$).
+     *      A 2-D tensor of shape [batch_size, num_units].
+     * * 20:The activation function (\f$g\f$).
+     *      A value indicating the activation function:
+     *      <ul>
+     *      <li>0: None;
+     *      <li>1: Relu;
+     *      <li>3: Relu6;
+     *      <li>4: Tanh;
+     *      <li>6: Sigmoid.
+     *      </ul>
+     * * 21:The clipping threshold (\f$t_{cell}\f$) for the cell state, such
+     *      that values are bound within [-cell_clip, cell_clip]. If set to 0.0
+     *      then clipping is disabled.
+     * * 22:The clipping threshold (\f$t_{proj}\f$) for the output from the
+     *      projection layer, such that values are bound within
+     *      [-proj_clip, proj_clip]. If set to 0.0 then clipping is disabled.
+     * * 23:Time-major if true, batch-major if false.
+     * * 24:The input layer normalization weights. Optional.
+     *      A 1-D tensor of shape [num_units]. Used to rescale normalized inputs
+     *      to activation at input gate.
+     * * 25:The forget layer normalization weights. Optional.
+     *      A 1-D tensor of shape [num_units]. Used to rescale normalized inputs
+     *      to activation at forget gate.
+     * * 26:The cell layer normalization weights. Optional.
+     *      A 1-D tensor of shape [num_units]. Used to rescale normalized inputs
+     *      to activation at cell gate.
+     * * 27:The output layer normalization weights. Optional.
+     *      A 1-D tensor of shape [num_units]. Used to rescale normalized inputs
+     *      to activation at output gate.
+     *
+     * Outputs:
+     * * 0: The output (\f$o_t\f$).
+     *      A 3-D tensor of shape:
+     *        If time-major: [max_time, batch_size, output_size]
+     *        If batch-major: [batch_size, max_time, output_size]
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_UNIDIRECTIONAL_SEQUENCE_LSTM = 92,
+
+    /**
+     * A recurrent neural network layer that applies a basic RNN cell to a
+     * sequence of inputs.
+     *
+     * This layer unrolls the input along the sequence dimension, and implements
+     * the following operation
+     * for each element in the sequence s = 1...sequence_length:
+     *   outputs[s] = state = activation(inputs[s] * input_weights’ + state *
+     *   recurrent_weights’ + bias)
+     *
+     * Where:
+     * * “input_weights” is a weight matrix that multiplies the inputs;
+     * * “recurrent_weights” is a weight matrix that multiplies the current
+     *    “state” which itself is the output from the previous time step
+     *    computation;
+     * * “bias” is a bias vector (added to each output vector in the batch);
+     * * “activation” is the function passed as the “fused_activation_function”
+     *   argument (if not “NONE”).
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     *
+     * The input tensors must all be the same type.
+     *
+     * Inputs:
+     * * 0: input.
+     *      A 3-D tensor. The shape is defined by the input 6 (timeMajor). If
+     *      it is set to 1, then the input has a shape [maxTime, batchSize,
+     *      inputSize], otherwise the input has a shape [batchSize, maxTime,
+     *      inputSize].
+     * * 1: weights.
+     *      A 2-D tensor of shape [numUnits, inputSize].
+     * * 2: recurrent_weights.
+     *      A 2-D tensor of shape [numUnits, numUnits].
+     * * 3: bias.
+     *      A 1-D tensor of shape [numUnits].
+     * * 4: hidden state
+     *      A 2-D tensor of shape [batchSize, numUnits]. Specifies a hidden
+     *      state input for the first time step of the computation.
+     * * 5: fusedActivationFunction.
+     *      A {@link FuseCode} value indicating the activation function. If
+     *      “NONE” is specified then it results in a linear activation.
+     * * 6: timeMajor
+     *      An {@link ANEURALNETWORKS_INT32} scalar specifying the shape format
+     *      of input and output tensors. Must be set to either 0 or 1.
+     * Outputs:
+     * * 0: output.
+     *      A 3-D tensor. The shape is defined by the input 6 (timeMajor). If
+     *      it is set to 1, then the output has a shape [maxTime, batchSize,
+     *      numUnits], otherwise the output has a shape [batchSize, maxTime,
+     *      numUnits].
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_UNIDIRECTIONAL_SEQUENCE_RNN = 93,
+
+    /**
+     * Resizes images to given size using the nearest neighbor interpretation.
+     *
+     * Resized images must be distorted if their output aspect ratio is not the
+     * same as input aspect ratio. The corner pixels of output may not be the
+     * same as corner pixels of input.
+     *
+     * Supported tensor {@link OperandCode}:
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT16}
+     * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+     * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+     *
+     * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout.
+     * With the default data layout NHWC, the data is stored in the order of:
+     * [batch, height, width, channels]. Alternatively, the data layout could
+     * be NCHW, the data storage order of: [batch, channels, height, width].
+     *
+     * Both resizing by shape and resizing by scale are supported.
+     *
+     * Inputs (resizing by shape):
+     * * 0: A 4-D tensor, of shape [batches, height, width, depth], specifying
+     *      the input. Zero batches is supported for this tensor.
+     * * 1: An {@link ANEURALNETWORKS_INT32} scalar, specifying the output
+     *      width of the output tensor.
+     * * 2: An {@link ANEURALNETWORKS_INT32} scalar, specifying the output
+     *      height of the output tensor.
+     * * 3: An {@link ANEURALNETWORKS_BOOL} scalar, default to false.
+     *      Set to true to specify NCHW data layout for input0 and output0.
+     *
+     * Inputs (resizing by scale):
+     * * 0: A 4-D tensor, of shape [batches, height, width, depth], specifying
+     *      the input. Zero batches is supported for this tensor.
+     * * 1: A scalar, specifying width_scale, the scaling factor of the width
+     *      dimension from the input tensor to the output tensor. The output
+     *      width is calculated as new_width = floor(width * width_scale).
+     *      The scalar must be of {@link ANEURALNETWORKS_FLOAT16} if input0 is
+     *      of {@link ANEURALNETWORKS_TENSOR_FLOAT16} and of
+     *      {@link ANEURALNETWORKS_FLOAT32} otherwise.
+     * * 2: A scalar, specifying height_scale, the scaling factor of the height
+     *      dimension from the input tensor to the output tensor. The output
+     *      height is calculated as new_height = floor(height * height_scale).
+     *      The scalar must be of {@link ANEURALNETWORKS_FLOAT16} if input0 is
+     *      of {@link ANEURALNETWORKS_TENSOR_FLOAT16} and of
+     *      {@link ANEURALNETWORKS_FLOAT32} otherwise.
+     * * 3: An {@link ANEURALNETWORKS_BOOL} scalar, default to false.
+     *      Set to true to specify NCHW data layout for input0 and output0.
+     *
+     * Outputs:
+     * * 0: The output 4-D tensor, of shape
+     *      [batches, new_height, new_width, depth].
+     *      For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor,
+     *      the scale and zeroPoint must be the same as input0.
+     *
+     * Available since API level 29.
+     */
+    ANEURALNETWORKS_RESIZE_NEAREST_NEIGHBOR = 94,
+} OperationCode;
+
+/**
+ * Fused activation function types.
+ *
+ *
+ * Available since API level 27.
+ */
+typedef enum {
+    /** NO fused activation function. */
+    ANEURALNETWORKS_FUSED_NONE = 0,
+    /** Fused ReLU activation function. */
+    ANEURALNETWORKS_FUSED_RELU = 1,
+    /** Fused ReLU1 activation function. */
+    ANEURALNETWORKS_FUSED_RELU1 = 2,
+    /** Fused ReLU6 activation function. */
+    ANEURALNETWORKS_FUSED_RELU6 = 3,
+} FuseCode;
+
+/**
+ * Implicit padding algorithms.
+ *
+ *
+ * Available since API level 27.
+ */
+typedef enum {
+    /**
+     * SAME padding.
+     * Padding on both ends are the "same":
+     *     padding_to_beginning =  total_padding / 2
+     *     padding_to_end       = (total_padding + 1)/2.
+     * i.e., for even number of padding, padding to both ends are exactly
+     * the same; for odd number of padding, padding to the ending is bigger
+     * than the padding to the beginning by 1.
+     *
+     * total_padding is a function of input, stride and filter size.
+     * It could be computed as follows:
+     *    out_size = (input + stride - 1) / stride;
+     *    needed_input = (out_size - 1) * stride + filter_size
+     *    total_padding = max(0, needed_input - input_size)
+     *  The computation is the same for the horizontal and vertical directions.
+     */
+    ANEURALNETWORKS_PADDING_SAME = 1,
+
+    /**
+     * VALID padding.
+     * No padding. When the input size is not evenly divisible by
+     * the filter size, the input at the end that could not fill
+     * the whole filter tile will simply be ignored.
+     */
+    ANEURALNETWORKS_PADDING_VALID = 2,
+} PaddingCode;
+
+/**
+ * Execution preferences.
+ *
+ * Available since API level 27.
+ */
+typedef enum {
+    /**
+     * Prefer executing in a way that minimizes battery drain.
+     * This is desirable for compilations that will be executed often.
+     */
+    ANEURALNETWORKS_PREFER_LOW_POWER = 0,
+    /**
+     * Prefer returning a single answer as fast as possible, even if this causes
+     * more power consumption.
+     */
+    ANEURALNETWORKS_PREFER_FAST_SINGLE_ANSWER = 1,
+    /**
+     * Prefer maximizing the throughput of successive frames, for example when
+     * processing successive frames coming from the camera.
+     */
+    ANEURALNETWORKS_PREFER_SUSTAINED_SPEED = 2,
+} PreferenceCode;
+
+/**
+ * Device types.
+ *
+ * The type of NNAPI device.
+ */
+typedef enum {
+    /** The device type cannot be provided. */
+    ANEURALNETWORKS_DEVICE_UNKNOWN = 0,
+    /** The device does not fall into any category below. */
+    ANEURALNETWORKS_DEVICE_OTHER = 1,
+    /** The device runs NNAPI models on single or multi-core CPU. */
+    ANEURALNETWORKS_DEVICE_CPU = 2,
+    /** The device can run NNAPI models and also accelerate graphics APIs such
+     * as OpenGL ES and Vulkan. */
+    ANEURALNETWORKS_DEVICE_GPU = 3,
+    /** Dedicated accelerator for Machine Learning workloads. */
+    ANEURALNETWORKS_DEVICE_ACCELERATOR = 4,
+} DeviceTypeCode;
+
+/**
+ * Result codes.
+ *
+ * <p>Any NNAPI function can return any result code, including result codes not
+ * currently documented. Any value other than {@link ANEURALNETWORKS_NO_ERROR}
+ * indicates a failure of some kind.</p>
+ *
+ * <p>Additional information about the nature of a failure can be obtained from
+ * the device log after enabling NNAPI debugging by setting the debug.nn.vlog
+ * property to 1, e.g., by calling "adb shell setprop debug.nn.vlog 1".</p>
+ *
+ * Available since API level 27.
+ */
+typedef enum {
+    /**
+     * Operation was succesful.
+     */
+    ANEURALNETWORKS_NO_ERROR = 0,
+
+    /**
+     * Failure caused by not enough available memory.
+     */
+    ANEURALNETWORKS_OUT_OF_MEMORY = 1,
+
+    ANEURALNETWORKS_INCOMPLETE = 2,
+
+    /**
+     * Failure caused by unexpected null argument.
+     */
+    ANEURALNETWORKS_UNEXPECTED_NULL = 3,
+
+    /**
+     * Failure caused by invalid function arguments, invalid model definition,
+     * invalid execution definition or invalid data at execution time.
+     */
+    ANEURALNETWORKS_BAD_DATA = 4,
+
+    /**
+     * Failure caused by failed model execution.
+     */
+    ANEURALNETWORKS_OP_FAILED = 5,
+
+    /**
+     * Failure caused by object being in the wrong state.
+     */
+    ANEURALNETWORKS_BAD_STATE = 6,
+
+    /**
+     * Failure caused by not being able to map a file into memory.
+     * This may be caused by a file descriptor not being mappable, or an AHardwareBuffer
+     * not supported by the device.
+     * Mitigate by reading its content into memory.
+     */
+    ANEURALNETWORKS_UNMAPPABLE = 7,
+
+    /**
+     * Failure caused by insufficient buffer size provided to a model output.
+     */
+    ANEURALNETWORKS_OUTPUT_INSUFFICIENT_SIZE = 8,
+
+    /**
+     * Failure caused by a device not being available.
+     */
+    ANEURALNETWORKS_UNAVAILABLE_DEVICE = 9,
+} ResultCode;
+
+/**
+ * For {@link ANeuralNetworksModel_setOperandValue}, values with a
+ * length smaller or equal to this will be immediately copied into
+ * the model. The size is in bytes.
+ *
+ * Available since API level 27.
+ */
+enum { ANEURALNETWORKS_MAX_SIZE_OF_IMMEDIATELY_COPIED_VALUES = 128 };
+
+/**
+ * For {@link ANeuralNetworksCompilation_setCaching}, specify the size
+ * of the cache token required from the application. The size is in bytes.
+ *
+ * Available since API level 29.
+ */
+enum { ANEURALNETWORKS_BYTE_SIZE_OF_CACHE_TOKEN = 32 };
+
+/**
+ * ANeuralNetworksMemory is an opaque type that represents memory.
+ *
+ * This type is used to represent shared memory, memory mapped files,
+ * and similar memories.
+ *
+ * By using shared memory, a program can efficiently communicate to the
+ * runtime and drivers the tensors that define a model. See
+ * {@link ANeuralNetworksModel_setOperandValueFromMemory}. An application
+ * should typically create one shared memory object that contains every constant tensor
+ * needed to define a model. {@link ANeuralNetworksMemory_createFromFd} can be used to
+ * create shared memory from a file handle.
+ * {@link ANeuralNetworksMemory_createFromAHardwareBuffer} can be used to
+ * create shared memory from an AHardwareBuffer handle.
+ *
+ * Memory objects can also be used to specify the input and output arguments of
+ * an execution. See {@link ANeuralNetworksExecution_setInputFromMemory}
+ * and {@link ANeuralNetworksExecution_setOutputFromMemory}.
+ *
+ * When calling {@link ANeuralNetworksModel_setOperandValueFromMemory},
+ * {@link ANeuralNetworksExecution_setInputFromMemory} and
+ * {@link ANeuralNetworksExecution_setOutputFromMemory}, each operand in the shared
+ * memory object must be aligned on a boundary of a byte size that is a multiple
+ * of the element type byte size, e.g., a tensor with
+ * {@link ANEURALNETWORKS_TENSOR_FLOAT32} type must be aligned on 4-byte boundary.
+ *
+ * Available since API level 27.
+ */
+typedef struct ANeuralNetworksMemory ANeuralNetworksMemory;
+
+/**
+ * ANeuralNetworksModel is an opaque type that contains a description of the
+ * mathematical operations that constitute the model.
+ *
+ * <p>Build the model by calling<ul>
+ * <li>{@link ANeuralNetworksModel_create}</li>
+ * <li>{@link ANeuralNetworksModel_addOperation}</li>
+ * <li>{@link ANeuralNetworksModel_addOperand}</li>
+ * </ul>
+ *
+ * This forms a graph in which each operation and operand is a node, a
+ * directed edge from an operand to an operation indicates that the
+ * operand is an input to the operation, and a directed edge from an
+ * operation to an operand indicates that the operand is an output
+ * from the operation. This graph must be acyclic.
+ *
+ * A model is completed by calling {@link ANeuralNetworksModel_finish}.
+ * A model is destroyed by calling {@link ANeuralNetworksModel_free}.
+ *
+ * <p>A model cannot be modified once {@link ANeuralNetworksModel_finish}
+ * has been called on it.</p>
+ *
+ * <p>It is the application's responsibility to make sure that only one thread
+ * modifies a model at a given time. It is however safe for more than one
+ * thread to use the model once {@link ANeuralNetworksModel_finish} has returned.</p>
+ *
+ * <p>It is also the application's responsibility to ensure that there are no other
+ * uses of the model after calling {@link ANeuralNetworksModel_free}.
+ * This includes any compilation or execution object created using the model.</p>
+ *
+ * Available since API level 27.
+ */
+typedef struct ANeuralNetworksModel ANeuralNetworksModel;
+
+/**
+ * ANeuralNetworksCompilation is an opaque type that can be used to compile
+ * a machine learning model.
+ *
+ * <p>To use:<ul>
+ *    <li>Create a new compilation instance by calling the
+ *        {@link ANeuralNetworksCompilation_create} function or
+ *        {@link ANeuralNetworksCompilation_createForDevices}.</li>
+ *    <li>Set any desired properties on the compilation (for example,
+ *        {@link ANeuralNetworksCompilation_setPreference}).</li>
+ *    <li>Optionally, set the caching signature and the cache directory on the
+ *        compilation by calling {@link ANeuralNetworksCompilation_setCaching}.</li>
+ *    <li>Complete the compilation with {@link ANeuralNetworksCompilation_finish}.</li>
+ *    <li>Use the compilation as many times as needed
+ *        with {@link ANeuralNetworksExecution_create} and
+ *        {@link ANeuralNetworksBurst_create}.</li>
+ *    <li>Destroy the compilation with {@link ANeuralNetworksCompilation_free}
+ *        once all executions using the compilation have completed.</li></ul></p>
+ *
+ * A compilation is completed by calling {@link ANeuralNetworksCompilation_finish}.
+ * A compilation is destroyed by calling {@link ANeuralNetworksCompilation_free}.
+ *
+ * <p>A compilation cannot be modified once {@link ANeuralNetworksCompilation_finish}
+ * has been called on it.</p>
+ *
+ * <p>It is the application's responsibility to make sure that only
+ * one thread modifies a compilation at a given time. It is however
+ * safe for more than one thread to use the compilation once
+ * {@link ANeuralNetworksCompilation_finish} has returned.</p>
+ *
+ * <p>It is also the application's responsibility to ensure that there are no other
+ * uses of the compilation after calling {@link ANeuralNetworksCompilation_free}.
+ * This includes any execution object created using the compilation.</p>
+ *
+ * Available since API level 27.
+ */
+typedef struct ANeuralNetworksCompilation ANeuralNetworksCompilation;
+
+/**
+ * ANeuralNetworksExecution is an opaque type that can be used to apply a machine
+ * learning model to a set of inputs.
+ *
+ * <p>To use:<ul>
+ *    <li>Create a new execution instance by calling the
+ *        {@link ANeuralNetworksExecution_create} function.</li>
+ *    <li>Associate input buffers or memory regions to the model inputs with
+ *        {@link ANeuralNetworksExecution_setInput} or
+ *        {@link ANeuralNetworksExecution_setInputFromMemory}.</li>
+ *    <li>Associate output buffers or memory regions to the model outputs with
+ *        {@link ANeuralNetworksExecution_setOutput} or
+ *        {@link ANeuralNetworksExecution_setOutputFromMemory}.</li>
+ *    <li>Apply the model with one of the following:</li><ul>
+ *        <li>Asynchronously with {@link ANeuralNetworksExecution_startCompute},
+ *            waiting for the execution to complete with
+ *            {@link ANeuralNetworksEvent_wait}.</li>
+ *        <li>Synchronously with {@link ANeuralNetworksExecution_compute}.</li>
+ *        <li>Synchronously as part of an execution burst with
+ *            {@link ANeuralNetworksExecution_burstCompute}.</li></ul>
+ *    <li>Destroy the execution with
+ *        {@link ANeuralNetworksExecution_free}.</li></ul></p>
+ *
+ * <p>An output buffer or memory region must not overlap with any
+ * other output buffer or memory region, with an input buffer or
+ * memory region, or with an operand value in a memory object
+ * ({@link ANeuralNetworksModel_setOperandValueFromMemory}).</p>
+ *
+ * <p>An execution cannot be modified once
+ * {@link ANeuralNetworksExecution_compute} or
+ * {@link ANeuralNetworksExecution_startCompute} has been called on it.</p>
+ *
+ * <p>An execution can be applied to a model with
+ * {@link ANeuralNetworksExecution_compute} or
+ * {@link ANeuralNetworksExecution_startCompute} only once. Create new
+ * executions to do new evaluations of the model.</p>
+ *
+ * <p>It is the application's responsibility to make sure that only one thread
+ * modifies an execution at a given time. It is however safe for more than one
+ * thread to use {@link ANeuralNetworksEvent_wait} at the same time.</p>
+ *
+ * <p>It is also the application's responsibility to ensure that there are no other
+ * uses of the execution after calling {@link ANeuralNetworksExecution_free}.</p>
+ *
+ * <p>Multiple executions can be scheduled and evaluated concurrently, either by
+ * means of {@link ANeuralNetworksExecution_compute} (which is synchronous) in
+ * different threads or by means of
+ * {@link ANeuralNetworksExecution_startCompute} (which is asynchronous). The
+ * runtime makes no guarantee on the ordering of completion of executions. If
+ * it's important to the application, the application should enforce the
+ * ordering by ensuring that one execution completes before the next is
+ * scheduled (for example, by scheduling all executions synchronously within a
+ * single thread, or by scheduling all executions asynchronously and using
+ * {@link ANeuralNetworksEvent_wait} between calls to
+ * {@link ANeuralNetworksExecution_startCompute}).</p>
+ *
+ * Available since API level 27.
+ */
+typedef struct ANeuralNetworksExecution ANeuralNetworksExecution;
+
+#if __ANDROID_API__ >= __ANDROID_API_Q__
+/**
+ * Parameters for ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL operand.
+ */
+typedef struct ANeuralNetworksSymmPerChannelQuantParams {
+    /* The index of the channel dimension. */
+    uint32_t channelDim;
+    /** The size of the scale array. Should be equal to dimension[channelDim] of the Operand. */
+    uint32_t scaleCount;
+    /** The array of scaling values for each channel. Each value must be greater than zero. */
+    const float* scales;
+} ANeuralNetworksSymmPerChannelQuantParams;
+
+/**
+ * ANeuralNetworksBurst is an opaque type that can be used to reduce the latency
+ * of a rapid sequence of executions. It will likely cause overhead if only used
+ * for a single execution.
+ *
+ * ANeuralNetworksBurst serves as a context object for any number of inferences
+ * using {@link ANeuralNetworksExecution} objects. An ANeuralNetworksBurst
+ * object and the {@link ANeuralNetworksExecution} objects used with it must all
+ * have been created from the same {@link ANeuralNetworksCompilation} object.
+ *
+ * This object is also used as a hint to drivers, providing insight to the
+ * lifetime of a rapid sequence of executions. For example, a driver may choose
+ * to increase the clock frequency of its accelerator for the lifetime of a
+ * burst object.
+ *
+ * <p>To use:<ul>
+ *    <li>Create a new burst object by calling the
+ *        {@link ANeuralNetworksBurst_create} function.</li>
+ *    <li>For each execution:</li><ul>
+ *        <li>Create {@link ANeuralNetworksExecution} and configure its
+ *            properties (see {@link ANeuralNetworksExecution} for details).</li>
+ *        <li>Apply the model synchronously with
+ *            {@link ANeuralNetworksExecution_burstCompute}, reusing the same
+ *            {@link ANeuralNetworksBurst} with the new
+ *            {@link ANeuralNetworksExecution}.</li>
+ *        <li>Use and free the {@link ANeuralNetworksExecution}.</li></ul>
+ *    <li>Destroy the burst with
+ *        {@link ANeuralNetworksBurst_free}.</li></ul></p>
+ *
+ * Available since API level 29.
+ */
+typedef struct ANeuralNetworksBurst ANeuralNetworksBurst;
+#endif  //  __ANDROID_API__ >= __ANDROID_API_Q__
+
+/**
+ * ANeuralNetworksOperandType describes the type of an operand.
+ *
+ * This structure is used to describe both scalars and tensors.
+ *
+ * A tensor operand type with all dimensions specified is "fully
+ * specified".  Whenever possible (i.e., whenever the dimensions are
+ * known at model construction time), a tensor operand type should be
+ * (but is not required to be) fully specified, in order to enable the
+ * best possible performance.
+ *
+ * If a tensor operand's type is not fully specified, the dimensions
+ * of the operand are deduced from the operand types and values of the
+ * operation for which that operand is an output.
+ *
+ * <p>In the following situations, a tensor operand type must be fully
+ * specified:<ul>
+ *     <li>The operand has a constant value, set by
+ *         {@link ANeuralNetworksModel_setOperandValue} (with a
+ *         non-nullptr buffer) or
+ *         {@link ANeuralNetworksModel_setOperandValueFromMemory}.</li>
+ *     <li>The operand is a model input (see
+ *         {@link ANeuralNetworksModel_identifyInputsAndOutputs}).  A
+ *         fully specified tensor operand type must either be provided
+ *         to {@link ANeuralNetworksModel_addOperand}; or it must be
+ *         provided to the corresponding
+ *         {@link ANeuralNetworksExecution_setInput}, or
+ *         {@link ANeuralNetworksExecution_setInputFromMemory}.
+ *         EXCEPTION: If the input is optional and omitted
+ *         (by passing nullptr for buffer to
+ *         {@link ANeuralNetworksExecution_setInput}) then it need
+ *         not have a fully specified tensor operand type.</li></ul>
+ *
+ * A tensor operand type of specified rank but some number of
+ * unspecified dimensions is represented by setting dimensionCount to
+ * the rank and each unspecified dimension to 0.
+ *
+ * Available since API level 27.
+ *
+ * Starting at API level 29, a tensor operand type of unspecified rank is
+ * represented by setting dimensionCount to 0 and dimensions to NULL (just as if
+ * it were a scalar operand type).
+ */
+typedef struct ANeuralNetworksOperandType {
+    /**
+     * The data type, e.g ANEURALNETWORKS_FLOAT32.
+     */
+    int32_t type;
+
+    /**
+     * The number of dimensions (rank).
+     *
+     * Must be 0 for scalars.
+     */
+    uint32_t dimensionCount;
+
+    /**
+     * The dimensions of the tensor.
+     *
+     * Must be nullptr for scalars.
+     */
+    const uint32_t* dimensions;
+
+    /**
+     * These two fields are only used for quantized tensors.
+     * They must be zero for all other types.
+     * The dequantized value of each entry is (value - zeroPoint) * scale.
+     */
+    float scale;
+    int32_t zeroPoint;
+} ANeuralNetworksOperandType;
+
+typedef int32_t ANeuralNetworksOperationType;
+
+/**
+ * ANeuralNetworksEvent is an opaque type that represents an event
+ * that will be signaled once an execution completes.
+ *
+ * Available since API level 27.
+ */
+typedef struct ANeuralNetworksEvent ANeuralNetworksEvent;
+
+#if __ANDROID_API__ >= __ANDROID_API_Q__
+
+/**
+ * ANeuralNetworksDevice is an opaque type that represents a device.
+ *
+ * This type is used to query basic properties and supported operations of the corresponding
+ * device, and control which device(s) a model is to be run on.
+ *
+ * Available since API level 29.
+ */
+typedef struct ANeuralNetworksDevice ANeuralNetworksDevice;
+
+/**
+ * Get the number of available devices.
+ *
+ * @param numDevices Used to return the number of devices.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ *
+ * Available since API level 29.
+ */
+int ANeuralNetworks_getDeviceCount(uint32_t* numDevices) __INTRODUCED_IN(29);
+
+/**
+ * Get the representation of the specified device.
+ *
+ * @param devIndex The index of the specified device. Must be less than the
+                   number of available devices.
+ * @param device The representation of the specified device.
+ *               The same representation will always be returned for the specified
+ *               device.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ *
+ * Available since API level 29.
+ */
+int ANeuralNetworks_getDevice(uint32_t devIndex, ANeuralNetworksDevice** device)
+        __INTRODUCED_IN(29);
+
+/**
+ * Get the name of the specified device.
+ *
+ * @param device The representation of the specified device.
+ * @param name   The returned name of the specified device. The name will be in UTF-8
+ *               and will be null-terminated. It will be recognizable as a known device name
+ *               rather than a cryptic string. For devices with feature level 29 and above, the
+ *               format of the name is {VENDOR}-{DEVICE}. For devices with feature level 28
+ *               or lower, the format of the name is undefined.
+ *               The name will remain valid for the duration of the application.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ *
+ * Available since API level 29.
+ */
+int ANeuralNetworksDevice_getName(const ANeuralNetworksDevice* device, const char** name)
+        __INTRODUCED_IN(29);
+
+/**
+ * Get the type of a given device.
+ *
+ * The device type can be used to help application developers to distribute Machine Learning
+ * workloads and other workloads such as graphical rendering.
+ * E.g., for an app which renders AR scenes based on real time object detection results,
+ * the developer could choose an ACCELERATOR type device for ML workloads, and reserve GPU
+ * for graphical rendering.
+ *
+ * @param device The representation of the specified device.
+ * @param type The returned {@link DeviceTypeCode} of the specified device.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ *
+ * Available since API level 29.
+ */
+int ANeuralNetworksDevice_getType(const ANeuralNetworksDevice* device, int32_t* type)
+        __INTRODUCED_IN(29);
+
+/**
+ * Get the version of the driver implementation of the specified device.
+ *
+ * It’s the responsibility of the driver implementor to insure that this version string
+ * uniquely distinguishes this implementation from all previous implementations.
+ *
+ * This version string must not be confused with the feature level which is solely defined
+ * by {@link ANeuralNetworksDevice_getFeatureLevel}. There is no implicit ordering of the versions.
+ * For example, it is not possible to filter all drivers older than a certain version.
+ *
+ * Application developers may use this version string to avoid or prefer specific driver
+ * implementations. For example, an application may want to do so because:
+ *     - A specific version of the driver does not provide the required performance,
+ *       perhaps because of a performance regression.
+ *     - A specific version of the driver has a bug or returns results that don’t match
+ *       the minimum precision requirement for the application.
+ *
+ * @param device The representation of the specified device.
+ * @param version The returned version string of the driver for the specified device. The
+ *                string will be in UTF-8 and will be null-terminated. For devices with feature
+ *                level 28 or lower, "UNKNOWN" will be returned. The version string will remain
+ *                valid for the duration of the application.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ *
+ * Available since API level 29.
+ */
+int ANeuralNetworksDevice_getVersion(const ANeuralNetworksDevice* device, const char** version)
+        __INTRODUCED_IN(29);
+
+/**
+ * Get the supported NNAPI version of the specified device.
+ *
+ * Each device has a supported feature level, which is the most advanced feature this driver
+ * implements. For example, if the driver implements the features introduced in Android P,
+ * but does not implement the features introduced after Android P, the value would be 28.
+ * Developers could decide whether or not the specified device should be used for a Model that
+ * has certain feature requirements.
+ *
+ * @param device The representation of the specified device.
+ * @param featureLevel The API level of the most advanced feature this driver implements.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ *
+ * Available since API level 29.
+ */
+int ANeuralNetworksDevice_getFeatureLevel(const ANeuralNetworksDevice* device,
+                                          int64_t* featureLevel) __INTRODUCED_IN(29);
+
+/**
+ * Get the supported operations for a specified set of devices. If multiple devices
+ * are selected, the supported operation list is a union of supported operations of all
+ * selected devices.
+ *
+ * @param model The model to be queried.
+ * @param devices The set of devices. Must not contain duplicates.
+ * @param numDevices The number of devices in the set.
+ * @param supportedOps The boolean array to be filled. True means supported. The size of the
+ *                     boolean array must be at least as large as the number of operations
+ *                     in the model. The order of elements in the supportedOps array matches
+ *                     the order in which the corresponding operations were added to the model.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ *
+ * Available since API level 29.
+ */
+int ANeuralNetworksModel_getSupportedOperationsForDevices(
+        const ANeuralNetworksModel* model, const ANeuralNetworksDevice* const* devices,
+        uint32_t numDevices, bool* supportedOps) __INTRODUCED_IN(29);
+
+/**
+ * Create a {@link ANeuralNetworksCompilation} to compile the given model for a specified set
+ * of devices. If more than one device is specified, the compilation will
+ * distribute the workload automatically across the devices. The model must be fully
+ * supported by the specified set of devices. This means that
+ * ANeuralNetworksModel_getSupportedOperationsForDevices() must have returned true for every
+ * operation for that model/devices pair.
+ *
+ * The user must handle all compilation and execution failures from the
+ * specified set of devices. This is in contrast to a use of {@link
+ * ANeuralNetworksCompilation_create}, where the runtime will attempt to recover
+ * from such failures.
+ *
+ * @param model The {@link ANeuralNetworksModel} to be compiled.
+ * @param devices The set of devices. Must not contain duplicates.
+ * @param numDevices The number of devices in the set.
+ * @param compilation The newly created object or NULL if unsuccessful.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_BAD_DATA
+ *         if the model is invalid.
+ *
+ * Available since API level 29.
+ */
+int ANeuralNetworksCompilation_createForDevices(ANeuralNetworksModel* model,
+                                                const ANeuralNetworksDevice* const* devices,
+                                                uint32_t numDevices,
+                                                ANeuralNetworksCompilation** compilation)
+        __INTRODUCED_IN(29);
+
+/**
+ * Sets the compilation caching signature and the cache directory.
+ *
+ * Provides optional caching information to the runtime for faster repeated
+ * compilation.
+ *
+ * See {@link ANeuralNetworksCompilation} for information on multithreaded usage.
+ *
+ * @param compilation The compilation to be modified.
+ * @param cacheDir The cache directory for the runtime to store and retrieve caching
+ *                 data. It is recommended to use the code cache directory provided
+ *                 by the Android runtime. If not using the code cache directory, the
+ *                 user should choose a directory local to the application, and is
+ *                 responsible to managing the cache entries.
+ * @param token The token provided by the user to specify a model must be of length
+ *              ANEURALNETWORKS_BYTE_SIZE_OF_CACHE_TOKEN. The user should ensure that
+ *              the token is unique to a model within the application. The NNAPI
+ *              runtime cannot detect token collisions; a collision will result in a
+ *              failed execution or in a successful execution that produces incorrect
+ *              output values.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ *
+ * Available since API level 29.
+ */
+int ANeuralNetworksCompilation_setCaching(ANeuralNetworksCompilation* compilation,
+                                          const char* cacheDir, const uint8_t* token)
+        __INTRODUCED_IN(29);
+
+/**
+ * Schedule synchronous evaluation of the execution.
+ *
+ * <p>Schedules synchronous evaluation of the execution. Returns once the
+ * execution has completed and the outputs are ready to be consumed.
+ * </p>
+ *
+ * See {@link ANeuralNetworksExecution} for information on multithreaded usage.
+ *
+ * See {@link ANeuralNetworksExecution_startCompute} for asynchronous execution.
+ * Synchronous execution incurs lower overhead than asynchronous execution.
+ *
+ * Available since API level 29.
+ *
+ * @param execution The execution to be scheduled and executed.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if the execution completed normally.
+ *         ANEURALNETWORKS_UNMAPPABLE if the execution input or output memory cannot
+ *         be properly mapped.
+ */
+int ANeuralNetworksExecution_compute(ANeuralNetworksExecution* execution) __INTRODUCED_IN(29);
+
+/**
+ * Get the dimensional information of the specified output operand of the model of the
+ * {@link ANeuralNetworksExecution}.
+ *
+ * On asynchronous execution initiated by {@link ANeuralNetworksExecution_startCompute},
+ * {@link ANeuralNetworksEvent_wait} must be called prior to this function to recuperate
+ * the resources used by the execution.
+ *
+ * @param execution The execution to be queried.
+ * @param index The index of the output argument we are querying. It is
+ *              an index into the lists passed to
+ *              {@link ANeuralNetworksModel_identifyInputsAndOutputs}. It is not
+ *              the index associated with {@link ANeuralNetworksModel_addOperand}.
+ * @param rank The rank of the output operand.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_OUTPUT_INSUFFICIENT_SIZE
+ *         if the target output is provided an insufficient buffer at execution time,
+ *         ANEURALNETWORKS_BAD_DATA if the index is invalid.
+ *
+ * Available since API level 29.
+ */
+int ANeuralNetworksExecution_getOutputOperandRank(ANeuralNetworksExecution* execution,
+                                                  int32_t index, uint32_t* rank)
+        __INTRODUCED_IN(29);
+
+/**
+ * Get the dimensional information of the specified output operand of the model of the
+ * {@link ANeuralNetworksExecution}. The target output operand cannot be a scalar.
+ *
+ * On asynchronous execution initiated by {@link ANeuralNetworksExecution_startCompute},
+ * {@link ANeuralNetworksEvent_wait} must be called prior to this function to recuperate
+ * the resources used by the execution.
+ *
+ * @param execution The execution to be queried.
+ * @param index The index of the output argument we are querying. It is an index into the lists
+ *              passed to {@link ANeuralNetworksModel_identifyInputsAndOutputs}. It is not
+ *              the index associated with {@link ANeuralNetworksModel_addOperand}.
+ * @param dimensions The dimension array to be filled. The size of the array must be exactly as
+ *                   large as the rank of the output operand to be queried in the model.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_OUTPUT_INSUFFICIENT_SIZE
+ *         if the target output is provided an insufficient buffer at execution time,
+ *         ANEURALNETWORKS_BAD_DATA if the index is invalid or if the target is a scalar.
+ *
+ * Available since API level 29.
+ */
+int ANeuralNetworksExecution_getOutputOperandDimensions(ANeuralNetworksExecution* execution,
+                                                        int32_t index, uint32_t* dimensions)
+        __INTRODUCED_IN(29);
+
+/**
+ * Create a {@link ANeuralNetworksBurst} to apply the given compilation.
+ * This only creates the burst object. Computation is only performed once
+ * {@link ANeuralNetworksExecution_burstCompute} is invoked with a valid
+ * {@link ANeuralNetworksExecution} and {@link ANeuralNetworksBurst}.
+ *
+ * <p>The provided compilation must outlive the burst object.</p>
+ *
+ * Available since API level 29.
+ *
+ * @param compilation The {@link ANeuralNetworksCompilation} to be evaluated.
+ * @param burst The newly created object or NULL if unsuccessful.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_BAD_DATA
+ *         if the compilation is invalid.
+ */
+int ANeuralNetworksBurst_create(ANeuralNetworksCompilation* compilation,
+                                ANeuralNetworksBurst** burst) __INTRODUCED_IN(29);
+
+/**
+ * Destroys the burst object.
+ *
+ * Available since API level 29.
+ *
+ * @param burst The burst object to be destroyed. Passing NULL is acceptable and
+ *              results in no operation.
+ */
+void ANeuralNetworksBurst_free(ANeuralNetworksBurst* burst) __INTRODUCED_IN(29);
+
+/**
+ * Schedule synchronous evaluation of the execution on a burst object.
+ *
+ * <p>Schedules synchronous evaluation of the execution. Returns once the
+ * execution has completed and the outputs are ready to be consumed.</p>
+ *
+ * <p>There must be at most one {@link ANeuralNetworksExecution} processing at
+ * any given time for any given burst object. Any
+ * {@link ANeuralNetworksExecution} launched before the previous has finished
+ * will result in ANEURALNETWORKS_BAD_STATE.</p>
+ *
+ * Available since API level 29.
+ *
+ * @param burst The burst object to execute on.
+ * @param execution The execution to be scheduled and executed. The execution
+ *                  must be created from the same {@link
+ *                  ANeuralNetworksCompilation} as the burst object.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if the execution completed normally.
+ */
+int ANeuralNetworksExecution_burstCompute(ANeuralNetworksExecution* execution,
+                                          ANeuralNetworksBurst* burst) __INTRODUCED_IN(29);
+
+/**
+ * Creates a shared memory object from an AHardwareBuffer handle.
+ *
+ * If the shared memory is backed by an AHardwareBuffer of AHARDWAREBUFFER_FORMAT_BLOB
+ * format, it can be used the same way as shared memory created from a file handle. See
+ * {@link ANeuralNetworksMemory} for a description on how to use this shared memory.
+ *
+ * If the shared memory is backed by an AHardwareBuffer of a format other than
+ * AHARDWAREBUFFER_FORMAT_BLOB, it can only be used for Model inputs and outputs.
+ * When calling {@link ANeuralNetworksExecution_setInputFromMemory} or
+ * {@link ANeuralNetworksExecution_setOutputFromMemory} with the shared memory, both
+ * offset and length must be set to zero and the entire memory region will be
+ * associated with the specified input or output operand. There is no guarantee
+ * that an arbitrary AHardwareBuffer_Format and AHardwareBuffer_UsageFlags combination
+ * can be used by arbitrary devices. The execution will fail if selected set of devices
+ * cannot consume the buffer.
+ *
+ * Calling {@link ANeuralNetworksModel_setOperandValueFromMemory} with shared memory
+ * backed by an AHardwareBuffer of a format other than AHARDWAREBUFFER_FORMAT_BLOB is
+ * disallowed.
+ *
+ * TODO(miaowang): add documentation about intended usage with introspection API.
+ *
+ * Available since API level 29.
+ *
+ * @param ahwb The AHardwareBuffer handle.
+ * @param memory The memory object to be created.
+ *               Set to NULL if unsuccessful.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if the request completed normally.
+ *
+ * @see AHardwareBuffer
+ */
+int ANeuralNetworksMemory_createFromAHardwareBuffer(const AHardwareBuffer* ahwb,
+                                                    ANeuralNetworksMemory** memory)
+        __INTRODUCED_IN(29);
+
+/**
+
+ * Specifies whether duration of the {@link ANeuralNetworksExecution} is to be
+ * measured. Evaluation of the execution must not have been scheduled.
+ *
+ * By default, duration is not measured.
+ *
+ * The {@link ANeuralNetworksExecution} must have been created with
+ * {@link ANeuralNetworksCompilation_createForDevices} with numDevices = 1.
+ *
+ * See {@link ANeuralNetworksExecution} for information on multithreaded usage.
+ *
+ * Available since API level 29.
+ *
+ * @param execution The execution to be modified.
+ * @param measure 'true' if duration is to be measured, 'false' if not.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+int ANeuralNetworksExecution_setMeasureTiming(ANeuralNetworksExecution* execution, bool measure)
+        __INTRODUCED_IN(29);
+
+/**
+ * Different duration measurements.
+ *
+ * Durations are measured in nanoseconds.
+ *
+ * Available since API level 29.
+ */
+typedef enum {
+    // Execution time on hardware (not driver, which runs on host processor).
+    ANEURALNETWORKS_DURATION_ON_HARDWARE = 0,
+    // Execution time in driver (including time on hardware).  Excludes overhead
+    // such as that of the runtime itself and the IPC needed for the runtime to
+    // communicate with the driver.
+    ANEURALNETWORKS_DURATION_IN_DRIVER = 1,
+} DurationCode;
+
+/**
+ * Get the time spent in the specified {@link ANeuralNetworksExecution}, in nanoseconds.
+ * The execution must have completed.
+ *
+ * Available since API level 29.
+ *
+ * @param execution The execution to be queried.
+ * @param durationCode The measurement to be queried, specified by {@link DurationCode}.
+ * @param duration The returned duration. If no measurement was requested by
+ *                 {@link ANeuralNetworksExecution_setMeasureTiming}, or for some other
+ *                 reason the duration is not available, UINT64_MAX will be returned.
+ *                 A particular device need not support any given measurement.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+int ANeuralNetworksExecution_getDuration(const ANeuralNetworksExecution* execution,
+                                         int32_t durationCode, uint64_t* duration)
+        __INTRODUCED_IN(29);
+
+#endif  // __ANDROID_API__ >= __ANDROID_API_Q__
+
+#if __ANDROID_API__ >= 27
+
+/**
+ * Creates a shared memory object from a file descriptor.
+ *
+ * The shared memory is backed by a file descriptor via mmap.
+ * See {@link ANeuralNetworksMemory} for a description on how to use
+ * this shared memory.
+ *
+ * Available since API level 27.
+ *
+ * @param size The requested size in bytes.
+ *             Must not be larger than the file size.
+ * @param prot The desired memory protection for the mapping.
+ *             It is either PROT_NONE or the bitwise OR of one or
+ *             more of the following flags: PROT_READ, PROT_WRITE.
+ * @param fd The requested file descriptor.
+ *           The file descriptor has to be mmap-able. The file
+ *           descriptor will be duplicated.
+ * @param offset The offset to the beginning of the file of the area to map.
+ *               The offset has to be aligned to a page size.
+ * @param memory The memory object to be created.
+ *               Set to NULL if unsuccessful.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if the request completed normally.
+ */
+int ANeuralNetworksMemory_createFromFd(size_t size, int protect, int fd, size_t offset,
+                                       ANeuralNetworksMemory** memory) __INTRODUCED_IN(27);
+
+/**
+ * Delete a memory object.
+ *
+ * Destroys the object used by the run time to keep track of the memory.
+ * This will free the underlying actual memory if no other code has open
+ * handles to this memory.
+ *
+ * Available since API level 27.
+ *
+ * @param memory The memory object to be freed.
+ */
+void ANeuralNetworksMemory_free(ANeuralNetworksMemory* memory) __INTRODUCED_IN(27);
+
+/**
+ * Create an empty {@link ANeuralNetworksModel}.
+ *
+ * <p>This only creates the object. Computation is performed once
+ * {@link ANeuralNetworksExecution_compute} or
+ * {@link ANeuralNetworksExecution_startCompute} is invoked.
+ *
+ * The model should be constructed with calls to
+ * {@link ANeuralNetworksModel_addOperation} and
+ * {@link ANeuralNetworksModel_addOperand}
+ *
+ * <p>{@link ANeuralNetworksModel_finish} should be called once the model
+ * has been fully constructed.</p>
+ *
+ * <p>{@link ANeuralNetworksModel_free} should be called once the model
+ * is no longer needed.</p>
+ *
+ * Available since API level 27.
+ *
+ * @param model The {@link ANeuralNetworksModel} to be created.
+ *              Set to NULL if unsuccessful.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+int ANeuralNetworksModel_create(ANeuralNetworksModel** model) __INTRODUCED_IN(27);
+
+/**
+ * Destroy a model.
+ *
+ * The model need not have been finished by a call to
+ * {@link ANeuralNetworksModel_finish}.
+ *
+ * See {@link ANeuralNetworksModel} for information on multithreaded usage.
+ *
+ * Available since API level 27.
+ *
+ * @param model The model to be destroyed. Passing NULL is acceptable and
+ *              results in no operation.
+ */
+void ANeuralNetworksModel_free(ANeuralNetworksModel* model) __INTRODUCED_IN(27);
+
+/**
+ * Indicate that we have finished modifying a model. Required before
+ * calling {@link ANeuralNetworksCompilation_create} and
+ * {@link ANeuralNetworksCompilation_createForDevices}.
+ *
+ * An application is responsible to make sure that no other thread uses
+ * the model at the same time.
+ *
+ * This function must only be called once for a given model.
+ *
+ * See {@link ANeuralNetworksModel} for information on multithreaded usage.
+ *
+ * Available since API level 27.
+ *
+ * @param model The model to be finished.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+int ANeuralNetworksModel_finish(ANeuralNetworksModel* model) __INTRODUCED_IN(27);
+
+/**
+ * Add an operand to a model.
+ *
+ * The order in which the operands are added is important. The first one added
+ * to a model will have the index value 0, the second 1, etc. These indexes are
+ * used as operand identifiers in
+ * {@link ANeuralNetworksModel_addOperation},
+ * {@link ANeuralNetworksModel_identifyInputsAndOutputs},
+ * {@link ANeuralNetworksModel_setOperandValue},
+ * {@link ANeuralNetworksModel_setOperandValueFromMemory},
+ * {@link ANeuralNetworksExecution_setInput},
+ * {@link ANeuralNetworksExecution_setInputFromMemory},
+ * {@link ANeuralNetworksExecution_setOutput},
+ * {@link ANeuralNetworksExecution_setOutputFromMemory} and
+ * {@link ANeuralNetworksExecution_setOperandValue}.
+ *
+ * <p>Every operand must be referenced in exactly one of the following
+ * ways:<ul>
+ *    <li>It is identified as a model input with
+ *        {@link ANeuralNetworksModel_identifyInputsAndOutputs}.</li>
+ *    <li>It is identified as a constant with
+ *        {@link ANeuralNetworksModel_setOperandValue} or
+ *        {@link ANeuralNetworksModel_setOperandValueFromMemory}.</li>
+ *    <li>It is identified as an output of exactly one operation with
+ *        {@link ANeuralNetworksModel_addOperation}.</li></p>
+ * <p>An operand that is identified as a model input or as a constant
+ * must not also be identified as a model output with
+ * {@link ANeuralNetworksModel_identifyInputsAndOutputs}.</p>
+ *
+ * To build a model that can accommodate inputs of various sizes, as
+ * you may want to do for a CNN, leave unspecified the dimensions that
+ * will vary at run time.  If you do so, fully specify dimensions
+ * when calling {@link ANeuralNetworksExecution_setInput} or
+ * {@link ANeuralNetworksExecution_setInputFromMemory}.
+ *
+ * Attempting to modify a model once {@link ANeuralNetworksModel_finish} has been
+ * called will return an error.
+ *
+ * See {@link ANeuralNetworksModel} for information on multithreaded usage.
+ *
+ * Available since API level 27.
+ *
+ * @param model The model to be modified.
+ * @param type The {@link ANeuralNetworksOperandType} that describes the shape
+ *             of the operand.  Neither the {@link ANeuralNetworksOperandType}
+ *             nor the dimensions it points to need to outlive the call to
+ *             {@link ANeuralNetworksModel_addOperand}.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+int ANeuralNetworksModel_addOperand(ANeuralNetworksModel* model,
+                                    const ANeuralNetworksOperandType* type) __INTRODUCED_IN(27);
+
+/**
+ * Sets an operand to a constant value.
+ *
+ * Values of length smaller or equal to
+ * {@link ANEURALNETWORKS_MAX_SIZE_OF_IMMEDIATELY_COPIED_VALUES}
+ * are immediately copied into the model.
+ *
+ * For values of length greater than {@link ANEURALNETWORKS_MAX_SIZE_OF_IMMEDIATELY_COPIED_VALUES},
+ * a pointer to the buffer is stored within the model. The application is responsible
+ * for not changing the content of this region until all executions using this model
+ * have completed. As the data may be copied during processing, modifying the data
+ * after this call yields undefined results.
+ *
+ * For large tensors, using {@link ANeuralNetworksModel_setOperandValueFromMemory}
+ * is likely to be more efficient.
+ *
+ * To indicate that an optional operand should be considered missing,
+ * pass nullptr for buffer and 0 for length.
+ *
+ * Attempting to modify a model once {@link ANeuralNetworksModel_finish} has been
+ * called will return an error.
+ *
+ * See {@link ANeuralNetworksModel} for information on multithreaded usage.
+ *
+ * Available since API level 27.
+ *
+ * @param model The model to be modified.
+ * @param index The index of the model operand we're setting.
+ * @param buffer A pointer to the data to use.
+ * @param length The size in bytes of the data value.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+int ANeuralNetworksModel_setOperandValue(ANeuralNetworksModel* model, int32_t index,
+                                         const void* buffer, size_t length) __INTRODUCED_IN(27);
+
+#if __ANDROID_API__ >= __ANDROID_API_Q__
+
+/**
+ * Sets an operand's per channel quantization parameters.
+ *
+ * Sets parameters required by a tensor of type
+ * {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL}.
+ * This function must be called for every tensor of type
+ * {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL} before
+ * calling {@link ANeuralNetworksModel_finish}.
+ *
+ * Available since API level 29.
+ *
+ * @param model The model to be modified.
+ * @param index The index of the model operand we're setting.
+ * @param channelQuant The per channel quantization parameters for the operand.
+ *                    No memory in this struct needs to outlive the call to
+ *                    this function.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+int ANeuralNetworksModel_setOperandSymmPerChannelQuantParams(
+        ANeuralNetworksModel* model, int32_t index,
+        const ANeuralNetworksSymmPerChannelQuantParams* channelQuant) __INTRODUCED_IN(29);
+
+#endif  // __ANDROID_API__ >= __ANDROID_API_Q__
+
+/**
+ * Sets an operand to a value stored in a memory object.
+ *
+ * The content of the memory is not copied. A reference to that memory is stored
+ * inside the model. The application is responsible for not changing the content
+ * of the memory region until all executions using this model have completed.
+ * As the data may be copied during processing, modifying the data after this call
+ * yields undefined results.
+ *
+ * To indicate that an optional operand should be considered missing,
+ * use {@link ANeuralNetworksModel_setOperandValue} instead, passing nullptr for buffer.
+ *
+ * Is disallowed to set an operand value with shared memory backed by an AHardwareBuffer
+ * of a format other than AHARDWAREBUFFER_FORMAT_BLOB.
+ *
+ * Attempting to modify a model once {@link ANeuralNetworksModel_finish} has been
+ * called will return an error.
+ *
+ * See {@link ANeuralNetworksModel} for information on multithreaded usage.
+ * See {@link ANeuralNetworksMemory_createFromAHardwarBuffer} for information on
+ * AHardwareBuffer usage.
+ *
+ * Available since API level 27.
+ *
+ * @param model The model to be modified.
+ * @param index The index of the model operand we're setting.
+ * @param buffer A pointer to the data to use.
+ * @param memory The memory containing the data.
+ * @param offset This specifies the location of the data within the memory.
+ *               The offset is in bytes from the start of memory.
+ * @param length The size in bytes of the data value.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+int ANeuralNetworksModel_setOperandValueFromMemory(ANeuralNetworksModel* model, int32_t index,
+                                                   const ANeuralNetworksMemory* memory,
+                                                   size_t offset, size_t length)
+        __INTRODUCED_IN(27);
+
+/**
+ * Add an operation to a model.
+ *
+ * @param model The model to be modified.
+ * @param type The {@link ANeuralNetworksOperationType} of the operation.
+ * @param inputCount The number of entries in the inputs array.
+ * @param inputs An array of indexes identifying each operand.
+ * @param outputCount The number of entries in the outputs array.
+ * @param outputs An array of indexes identifying each operand.
+ *
+ * The operands specified by inputs and outputs must have been
+ * previously added by calls to {@link ANeuralNetworksModel_addOperand}.
+ *
+ * Attempting to modify a model once {@link ANeuralNetworksModel_finish} has been
+ * called will return an error.
+ *
+ * See {@link ANeuralNetworksModel} for information on multithreaded usage.
+ *
+ * Available since API level 27.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+int ANeuralNetworksModel_addOperation(ANeuralNetworksModel* model,
+                                      ANeuralNetworksOperationType type, uint32_t inputCount,
+                                      const uint32_t* inputs, uint32_t outputCount,
+                                      const uint32_t* outputs) __INTRODUCED_IN(27);
+
+/**
+ * Specifies which operands will be the model's inputs and
+ * outputs. Every model must have at least one input and one output.
+ *
+ * An operand cannot be used for both input and output. Doing so will
+ * return an error.
+ *
+ * @param model The model to be modified.
+ * @param inputCount The number of entries in the inputs array.
+ * @param inputs An array of indexes identifying the input operands.
+ * @param outputCount The number of entries in the outputs array.
+ * @param outputs An array of indexes identifying the output operands.
+ *
+ * The operands specified by inputs and outputs must have been
+ * previously added by calls to {@link ANeuralNetworksModel_addOperand}.
+ *
+ * Attempting to modify a model once {@link ANeuralNetworksModel_finish} has been
+ * called will return an error.
+ *
+ * See {@link ANeuralNetworksModel} for information on multithreaded usage.
+ *
+ * Available since API level 27.
+ *
+ */
+int ANeuralNetworksModel_identifyInputsAndOutputs(ANeuralNetworksModel* model, uint32_t inputCount,
+                                                  const uint32_t* inputs, uint32_t outputCount,
+                                                  const uint32_t* outputs) __INTRODUCED_IN(27);
+
+#if __ANDROID_API__ >= 28
+
+/**
+ * Specifies whether {@link ANEURALNETWORKS_TENSOR_FLOAT32} is allowed to be
+ * calculated with range and/or precision as low as that of the IEEE 754 16-bit
+ * floating-point format. By default, {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+ * must be calculated using at least the range and precision of the IEEE 754
+ * 32-bit floating-point format.
+ *
+ * @param model The model to be modified.
+ * @param allow 'true' indicates {@link ANEURALNETWORKS_TENSOR_FLOAT32} may be
+ *              calculated with range and/or precision as low as that of the
+ *              IEEE 754 16-bit floating point format. 'false' indicates
+ *              {@link ANEURALNETWORKS_TENSOR_FLOAT32} must be calculated using
+ *              at least the range and precision of the IEEE 754 32-bit floating
+ *              point format.
+ *
+ * Attempting to modify a model once {@link ANeuralNetworksModel_finish} has been
+ * called will return an error.
+ *
+ * Available since API level 28.
+ *
+ * See {@link ANeuralNetworksModel} for information on multithreaded usage.
+ */
+int ANeuralNetworksModel_relaxComputationFloat32toFloat16(ANeuralNetworksModel* model, bool allow)
+        __INTRODUCED_IN(28);
+
+#endif  // __ANDROID_API__ >= 28
+
+/**
+ * Create a {@link ANeuralNetworksCompilation} to compile the given model.
+ *
+ * <p>This only creates the object. Compilation is only performed once
+ * {@link ANeuralNetworksCompilation_finish} is invoked.</p>
+ *
+ * <p>{@link ANeuralNetworksCompilation_finish} should be called once
+ * all desired properties have been set on the compilation.</p>
+ *
+ * <p>{@link ANeuralNetworksModel_free} should be called once the compilation
+ * is no longer needed.</p>
+ *
+ * <p>The provided model must outlive the compilation.</p>
+ *
+ * The model must already have been finished by a call to
+ * {@link ANeuralNetworksModel_finish}.
+ *
+ * See {@link ANeuralNetworksCompilation} for information on multithreaded usage.
+ *
+ * Available since API level 27.
+ *
+ * @param model The {@link ANeuralNetworksModel} to be compiled.
+ * @param compilation The newly created object or NULL if unsuccessful.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_BAD_DATA
+ *         if the model is invalid.
+ */
+int ANeuralNetworksCompilation_create(ANeuralNetworksModel* model,
+                                      ANeuralNetworksCompilation** compilation) __INTRODUCED_IN(27);
+
+/**
+ * Destroy a compilation.
+ *
+ * The compilation need not have been finished by a call to
+ * {@link ANeuralNetworksModel_finish}.
+ *
+ * See {@link ANeuralNetworksCompilation} for information on multithreaded usage.
+ *
+ * Available since API level 27.
+ *
+ * @param compilation The compilation to be destroyed. Passing NULL is acceptable and
+ *                    results in no operation.
+ */
+void ANeuralNetworksCompilation_free(ANeuralNetworksCompilation* compilation) __INTRODUCED_IN(27);
+
+/**
+ * Sets the execution preference.
+ *
+ * <p>Provides guidance to the runtime when trade-offs are possible.</p>
+ *
+ * See {@link ANeuralNetworksCompilation} for information on multithreaded usage.
+ *
+ * Available since API level 27.
+ *
+ * @param compilation The compilation to be modified.
+ * @param preference Either {@link PREFER_LOW_POWER},
+ *                  {@link PREFER_SINGLE_FAST_ANSWER}, or
+ *                  {@link PREFER_SUSTAINED_SPEED}.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+int ANeuralNetworksCompilation_setPreference(ANeuralNetworksCompilation* compilation,
+                                             int32_t preference) __INTRODUCED_IN(27);
+
+/**
+ * Indicate that we have finished modifying a compilation. Required before
+ * calling {@link ANeuralNetworksExecution_create}.
+ *
+ * An application is responsible to make sure that no other thread uses
+ * the compilation at the same time.
+ *
+ * This function must only be called once for a given compilation.
+ *
+ * See {@link ANeuralNetworksCompilation} for information on multithreaded usage.
+ *
+ * Available since API level 27.
+ *
+ * @param compilation The compilation to be finished.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+int ANeuralNetworksCompilation_finish(ANeuralNetworksCompilation* compilation) __INTRODUCED_IN(27);
+
+/**
+ * Create a {@link ANeuralNetworksExecution} to apply the given compilation.
+ * This only creates the object. Computation is only performed once
+ * {@link ANeuralNetworksExecution_compute} or
+ * {@link ANeuralNetworksExecution_startCompute} is invoked.
+ *
+ * <p>The provided compilation must outlive the execution.</p>
+ *
+ * See {@link ANeuralNetworksExecution} for information on multithreaded usage.
+ *
+ * Available since API level 27.
+ *
+ * @param compilation The {@link ANeuralNetworksCompilation} to be evaluated.
+ * @param execution The newly created object or NULL if unsuccessful.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_BAD_DATA
+ *         if the compilation is invalid.
+ */
+int ANeuralNetworksExecution_create(ANeuralNetworksCompilation* compilation,
+                                    ANeuralNetworksExecution** execution) __INTRODUCED_IN(27);
+
+/**
+ * Destroy an execution.
+ *
+ * <p>If called on an execution for which
+ * {@link ANeuralNetworksExecution_startCompute} has been called, the
+ * function will return immediately but will mark the execution to be deleted
+ * once the computation completes. The related {@link ANeuralNetworksEvent}
+ * will be signaled and the {@link ANeuralNetworksEvent_wait} will return
+ * ANEURALNETWORKS_ERROR_DELETED.
+ *
+ * See {@link ANeuralNetworksExecution} for information on multithreaded usage.
+ *
+ * Available since API level 27.
+ *
+ * @param execution The execution to be destroyed. Passing NULL is acceptable and
+ *                  results in no operation.
+ */
+void ANeuralNetworksExecution_free(ANeuralNetworksExecution* execution) __INTRODUCED_IN(27);
+
+/**
+ * Associate a user buffer with an input of the model of the
+ * {@link ANeuralNetworksExecution}. Evaluation of the execution must not have
+ * been scheduled.
+ *
+ * <p>The provided buffer must outlive the execution.</p>
+ *
+ * If the input is optional, you can indicate that it is omitted by
+ * passing nullptr for buffer and 0 for length.
+ *
+ * See {@link ANeuralNetworksExecution} for information on multithreaded usage.
+ *
+ * Available since API level 27.
+ *
+ * @param execution The execution to be modified.
+ * @param index The index of the input argument we are setting. It is
+ *              an index into the lists passed to
+ *              {@link ANeuralNetworksModel_identifyInputsAndOutputs}. It is not
+ *              the index associated with
+ *              {@link ANeuralNetworksModel_addOperand}.
+ * @param type The {@link ANeuralNetworksOperandType} of the
+ *             operand. Unless the input is omitted, this should be
+ *             used to specify the dimensions that were left
+ *             unspecified when the operand was added to the
+ *             model. All other properties of the type must be the
+ *             same as specified in the model. If the type is the same
+ *             as specified when the model was built, NULL can be
+ *             passed. Neither the {@link ANeuralNetworksOperandType}
+ *             nor the dimensions it points to need to outlive the call
+ *             to {@link ANeuralNetworksExecution_setInput}.
+ * @param buffer The buffer containing the data.
+ * @param length The length in bytes of the buffer.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_BAD_DATA if the
+ *         name is not recognized or the buffer is too small for the input.
+ */
+int ANeuralNetworksExecution_setInput(ANeuralNetworksExecution* execution, int32_t index,
+                                      const ANeuralNetworksOperandType* type, const void* buffer,
+                                      size_t length) __INTRODUCED_IN(27);
+
+/**
+ * Associate part of a memory object with an input of the model of the
+ * {@link ANeuralNetworksExecution}. Evaluation of the execution must not have
+ * been scheduled.
+ *
+ * <p>The provided memory must outlive the execution.</p>
+ *
+ * If the input is optional, you can indicate that it is omitted by
+ * using {@link ANeuralNetworksExecution_setInput} instead, passing nullptr for
+ * buffer and 0 for length.
+ *
+ * See {@link ANeuralNetworksExecution} for information on multithreaded usage.
+ * See {@link ANeuralNetworksMemory_createFromAHardwarBuffer} for information on
+ * AHardwareBuffer usage.
+ *
+ * Available since API level 27.
+ *
+ * @param execution The execution to be modified.
+ * @param index The index of the input argument we are setting. It is
+ *              an index into the lists passed to
+ *              {@link ANeuralNetworksModel_identifyInputsAndOutputs}. It is not
+ *              the index associated with {@link ANeuralNetworksModel_addOperand}.
+ * @param type The {@link ANeuralNetworksOperandType} of the
+ *             operand. This should be used to specify the dimensions
+ *             that were left unspecified when the operand was added
+ *             to the model. All other properties of the type must be
+ *             the same as specified in the model. If the type is the
+ *             same as specified when the model was built, NULL can be
+ *             passed. Neither the {@link ANeuralNetworksOperandType}
+ *             nor the dimensions it points to need to outlive the call
+ *             to {@link ANeuralNetworksExecution_setInputFromMemory}.
+ * @param memory The memory containing the data.
+ * @param offset This specifies the location of the data within the memory.
+ *               The offset is in bytes from the start of memory.
+ * @param length The size in bytes of the data value.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_BAD_DATA if the
+ *         name is not recognized or the buffer is too small for the input.
+ */
+int ANeuralNetworksExecution_setInputFromMemory(ANeuralNetworksExecution* execution, int32_t index,
+                                                const ANeuralNetworksOperandType* type,
+                                                const ANeuralNetworksMemory* memory, size_t offset,
+                                                size_t length) __INTRODUCED_IN(27);
+
+/**
+ * Associate a user buffer with an output of the model of the
+ * {@link ANeuralNetworksExecution}. Evaluation of the execution must not have
+ * been scheduled.
+ *
+ * If the output is optional, you can indicate that it is omitted by
+ * passing nullptr for buffer and 0 for length.
+ *
+ * <p>The provided buffer must outlive the execution.</p>
+ *
+ * See {@link ANeuralNetworksExecution} for information on multithreaded usage.
+ *
+ * Available since API level 27.
+ *
+ * @param execution The execution to be modified.
+ * @param index The index of the output argument we are setting. It is
+ *              an index into the lists passed to
+ *              {@link ANeuralNetworksModel_identifyInputsAndOutputs}. It is not
+ *              the index associated with {@link ANeuralNetworksModel_addOperand}.
+ * @param type The {@link ANeuralNetworksOperandType} of the
+ *             operand. Unless the output is omitted, this should be
+ *             used to specify the dimensions that were left
+ *             unspecified when the operand was added to the
+ *             model. All other properties of the type must be the
+ *             same as specified in the model. If the type is the same
+ *             as specified when the model was built, NULL can be
+ *             passed. Neither the {@link ANeuralNetworksOperandType}
+ *             nor the dimensions it points to need to outlive the call
+ *             to {@link ANeuralNetworksExecution_setOutput}.
+ *             Since API level 29, the output operand can have unspecified
+ *             dimensions or rank to be deduced dynamically during the execution.
+ *             However, the user must provide a large enough buffer. The user
+ *             can retrieve the output dimensional information after the execution
+ *             by {@link ANeuralNetworksExecution_getOutputOperandRank} and
+ *             {@link ANeuralNetworksExecution_getOutputOperandDimensions}.
+ * @param buffer The buffer where the data is to be written.
+ * @param length The length in bytes of the buffer.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_BAD_DATA if the
+ *         name is not recognized or the buffer is too small for the output.
+ */
+int ANeuralNetworksExecution_setOutput(ANeuralNetworksExecution* execution, int32_t index,
+                                       const ANeuralNetworksOperandType* type, void* buffer,
+                                       size_t length) __INTRODUCED_IN(27);
+
+/**
+ * Associate part of a memory object with an output of the model of the
+ * {@link ANeuralNetworksExecution}. Evaluation of the execution must not have
+ * been scheduled.
+ *
+ * If the output is optional, you can indicate that it is omitted by
+ * using {@link ANeuralNetworksExecution_setOutput} instead, passing nullptr for
+ * buffer and 0 for length.
+ *
+ * <p>The provided memory must outlive the execution.</p>
+ *
+ * See {@link ANeuralNetworksExecution} for information on multithreaded usage.
+ * See {@link ANeuralNetworksMemory_createFromAHardwarBuffer} for information on
+ * AHardwareBuffer usage.
+ *
+ * Available since API level 27.
+ *
+ * @param execution The execution to be modified.
+ * @param index The index of the output argument we are setting. It is
+ *              an index into the lists passed to
+ *              {@link ANeuralNetworksModel_identifyInputsAndOutputs}. It is not
+ *              the index associated with {@link ANeuralNetworksModel_addOperand}.
+ * @param type The {@link ANeuralNetworksOperandType} of the operand. This should be
+ *             used to specify the dimensions that were left
+ *             unspecified when the operand was added to the
+ *             model. All other properties of the type must be the
+ *             same as specified in the model. If the type is the same
+ *             as specified when the model was built, NULL can be
+ *             passed. Neither the {@link ANeuralNetworksOperandType}
+ *             nor the dimensions it points to need to outlive the call
+ *             to {@link ANeuralNetworksExecution_setOutputFromMemory}.
+ *             Since API level 29, the output operand can have unspecified
+ *             dimensions or rank to be deduced dynamically during the execution.
+ *             However, the user must provide a large enough memory. The user
+ *             can retrieve the output dimensional information after the execution
+ *             by {@link ANeuralNetworksExecution_getOutputOperandRank} and
+ *             {@link ANeuralNetworksExecution_getOutputOperandDimensions}.
+ * @param memory The memory where the data is to be stored.
+ * @param offset This specifies the location of the data within the memory.
+ *               The offset is in bytes from the start of memory.
+ * @param length The length in bytes of the data value.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_BAD_DATA if the
+ *         name is not recognized or the buffer is too small for the output.
+ */
+int ANeuralNetworksExecution_setOutputFromMemory(ANeuralNetworksExecution* execution, int32_t index,
+                                                 const ANeuralNetworksOperandType* type,
+                                                 const ANeuralNetworksMemory* memory, size_t offset,
+                                                 size_t length) __INTRODUCED_IN(27);
+
+/**
+ * Schedule asynchronous evaluation of the execution.
+ *
+ * <p>Schedules asynchronous evaluation of the execution. Once the model has
+ * been applied and the outputs are ready to be consumed, the returned event
+ * will be signaled. Use {@link ANeuralNetworksEvent_wait} to wait for that
+ * event.
+ * </p>
+ *
+ * ANeuralNetworksEvent_wait must be called to recuperate the resources used
+ * by the execution.
+ *
+ * See {@link ANeuralNetworksExecution} for information on multithreaded usage.
+ *
+ * See {@link ANeuralNetworksExecution_compute} for synchronous execution.
+ * Synchronous execution incurs lower overhead than asynchronous execution.
+ *
+ * Available since API level 27.
+ *
+ * @param execution The execution to be scheduled and executed.
+ * @param event The event that will be signaled on completion. event is set to
+ *              NULL if there's an error.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+int ANeuralNetworksExecution_startCompute(ANeuralNetworksExecution* execution,
+                                          ANeuralNetworksEvent** event) __INTRODUCED_IN(27);
+
+/**
+ * Waits until the execution completes.
+ *
+ * More than one thread can wait on an event. When the execution completes,
+ * all threads will be released.
+ *
+ * See {@link ANeuralNetworksExecution} for information on multithreaded usage.
+ *
+ * Available since API level 27.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if the execution completed normally.
+ *         ANEURALNETWORKS_UNMAPPABLE if the execution input or output memory cannot
+ *         be properly mapped.
+ */
+int ANeuralNetworksEvent_wait(ANeuralNetworksEvent* event) __INTRODUCED_IN(27);
+
+/**
+ * Destroys the event.
+ *
+ * See {@link ANeuralNetworksExecution} for information on multithreaded usage.
+ *
+ * Available since API level 27.
+ */
+void ANeuralNetworksEvent_free(ANeuralNetworksEvent* event) __INTRODUCED_IN(27);
+
+#endif  // __ANDROID_API__ >= 27
+
+__END_DECLS
+
+#endif  // ANDROID_ML_NN_RUNTIME_NEURAL_NETWORKS_H
+
+/** @} */
diff --git a/runtime/nnapi-header/include/NeuralNetworksEx.h b/runtime/nnapi-header/include/NeuralNetworksEx.h
new file mode 100644
index 000000000..7a054a1a4
--- /dev/null
+++ b/runtime/nnapi-header/include/NeuralNetworksEx.h
@@ -0,0 +1,622 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ * Copyright (C) 2017 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file     NeuralNetworksEx.h
+ * @brief    This file contains ANeuralNetworksModel_addOperationEx function definition
+ * @note     This header describes experimental feature,
+ *           so specification here can be changed or/and removed
+ */
+#ifndef NN_RUNTIME_NEURAL_NETWORKS_EX_H
+#define NN_RUNTIME_NEURAL_NETWORKS_EX_H
+
+#include <sys/cdefs.h>
+
+__BEGIN_DECLS
+
+/**
+ * @brief Extended operation types
+ */
+typedef enum {
+  /** extends operation. */
+
+  /**
+   *
+   * IMPORTANT NOTICE:
+   * ANEURALNETWORKS_CAST_EX operation is DEPRECATED
+   * Use ANEURALNETWORKS_CAST instead
+   *
+   */
+  ANEURALNETWORKS_CAST_EX = 50000,
+
+  /**
+   *
+   * IMPORTANT NOTICE:
+   * ANEURALNETWORKS_GATHER_EX operation is DEPRECATED
+   * Use ANEURALNETWORKS_GATHER instead
+   *
+   */
+  ANEURALNETWORKS_GATHER_EX = 50001, /**< Gather slices according to indexes and axis */
+
+  /**
+   *
+   * IMPORTANT NOTICE:
+   * ANEURALNETWORKS_TOPK_V2_EX operation is DEPRECATED
+   * Use ANEURALNETWORKS_TOPK_V2 instead
+   *
+   */
+  ANEURALNETWORKS_TOPK_V2_EX = 50002,
+
+  /**
+   *
+   * IMPORTANT NOTICE:
+   * ANEURALNETWORKS_REDUCE_MAX_EX operation is DEPRECATED
+   * Use ANEURALNETWORKS_REDUCE_MAX instead
+   *
+   */
+  ANEURALNETWORKS_REDUCE_MAX_EX = 50003,
+
+  /**
+   * Splits a tensor along a given axis into num_splits subtensors.
+   *
+   * Supported tensor {@link OperandCode}:
+   * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+   * * {@link ANEURALNETWORKS_TENSOR_INT32}
+   * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+   *
+   * Supported tensor rank: from 1
+   *
+   * Inputs:
+   * * 0: An n-D tensor to split.
+   * * 1: An {@link ANEURALNETWORKS_INT32} scalar specifying the axis along
+   *      which to split.
+   * * 2: An {@link ANEURALNETWORKS_INT32} scalar indicating the number of
+   *      splits along given axis. Must evenly divide axis size.
+   *
+   * Outputs:
+   * * 0 ~ (num_splits - 1): Resulting subtensors.
+   */
+  ANEURALNETWORKS_SPLIT_EX = 50004, /**< Splits a tensor into sub tensors */
+
+  /**
+   *
+   * IMPORTANT NOTICE:
+   * ANEURALNETWORKS_RSQRT_EX operation is DEPRECATED
+   * Use ANEURALNETWORKS_RSQRT instead
+   *
+   */
+  ANEURALNETWORKS_RSQRT_EX = 50005,
+
+  /**
+   * Computes element-wise squared difference on the input tensors.
+   *
+   * Takes two input tensors of identical {@link OperandCode} and compatible dimensions.
+   * The output is the result of squaring of difference given by subtracting the second input tensor
+   * from the first one.
+   *
+   * Two dimensions are compatible when:
+   *     1. they are equal, or
+   *     2. one of them is 1
+   *
+   * The size of the output is the maximum size along each dimension of the
+   * input operands. It starts with the trailing dimensions, and works its way
+   * forward.
+   *
+   * Supported tensor {@link OperandCode}:
+   * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+   *
+   * Supported tensor rank: up to 4
+   *
+   * Inputs:
+   * * 0: An n-D tensor, specifying the first input.
+   * * 1: A tensor of the same {@link OperandCode}, and compatible dimensions
+   *      as input0.
+   *
+   * Outputs:
+   * * 0: The output tensor, of the same {@link OperandCode} as input0.
+   */
+  ANEURALNETWORKS_SQUARED_DIFFERENCE_EX = 50006,
+
+  /**
+   *
+   * IMPORTANT NOTICE:
+   * ANEURALNETWORKS_NEG_EX operation is DEPRECATED
+   * Use ANEURALNETWORKS_NEG instead
+   *
+   */
+  ANEURALNETWORKS_NEG_EX = 50007,
+
+  /**
+   *
+   * IMPORTANT NOTICE:
+   * ANEURALNETWORKS_EXP_EX operation is DEPRECATED
+   * Use ANEURALNETWORKS_EXP instead
+   *
+   */
+  ANEURALNETWORKS_EXP_EX = 50008,
+
+  /**
+   * Computes the sum of elements across dimensions of a tensor.
+   *
+   * Reduces the input tensor along the given dimensions to reduce.
+   *
+   * Supported tensor {@link OperandCode}:
+   * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+   *
+   * Supported tensor rank: up to 4
+   *
+   * Inputs:
+   * * 0: A tensor, specifying the input.
+   * * 1: A 1-D Tensor of {@link ANEURALNETWORKS_TENSOR_INT32}. The dimensions
+   *      to reduce.
+   * * 2: An {@link ANEURALNETWORKS_BOOL} scalar, keep_dims. If true,
+   *      retains reduced dimensions with length 1.
+   *
+   * Outputs:
+   * * 0: A tensor of the same {@link OperandCode} as input0.
+   */
+  ANEURALNETWORKS_REDUCE_SUM_EX = 50009,
+
+  /**
+   * A transposed convolutional layer carries out a regular convolution
+   * but reverts its spatial transformation.
+   * Transpose convolution basically performs convolution with transposed weights.
+   *
+   * Supported tensor {@link OperandCode}:
+   * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+   * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+   *
+   * Supported tensor rank: only 4
+   *
+   * Inputs:
+   *   0: An {@link ANEURALNETWORKS_INT32} 1-D four element tensor, specifying the output shape.
+   *   1: A 4-D tensor, of shape [depth_out, filter_height, filter_width, depth_in],
+   *      specifying the filter.
+   *   2: A 4-D tensor, of shape [batches, height, width, depth_in], specifying the input.
+   *   3: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding type.
+   *   4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when
+   *      walking through input in the ‘width’ dimension.
+   *   5: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when
+   *      walking through input in the height dimension.
+   *
+   * Outputs:
+   *   0: The output 4-D tensor, of shape [batches, out_height, out_width, depth_out].
+   */
+  ANEURALNETWORKS_TRANSPOSE_CONV_EX = 50010,
+
+  /**
+   * Computes element-wise truth value by comparing the two input tensors for equality.
+   *
+   * Takes two input tensors of identical {@link OperandCode} and compatible dimensions.
+   * The output is the result of comparison of two input tensors.
+   *
+   * Two dimensions are compatible when:
+   *     1. they are equal, or
+   *     2. one of them is 1
+   *
+   * The size of the output is the maximum size along each dimension of the
+   * input operands. It starts with the trailing dimensions, and works its way
+   * forward.
+   *
+   * Supported tensor {@link OperandCode}:
+   * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+   * * {@link ANEURALNETWORKS_TENSOR_INT32}
+   * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+   *
+   * Supported tensor rank: up to 4
+   *
+   * Inputs:
+   * * 0: An n-D tensor, specifying the first input.
+   * * 1: A tensor of the same {@link OperandCode}, and compatible dimensions
+   *      as input0.
+   *
+   * Outputs:
+   * * 0: A boolean tensor indicating the truth value of (x == y)
+   *      Stored as {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} with offset 0
+   *      and scale 1.0f.
+   *      A non-zero byte represents True, a hit. A zero indicates otherwise.
+   */
+  ANEURALNETWORKS_EQUAL_EX = 50011,
+
+  /**
+   *
+   * IMPORTANT NOTICE:
+   * ANEURALNETWORKS_ABS_EX operation is DEPRECATED
+   * Use ANEURALNETWORKS_ABS instead
+   *
+   */
+  ANEURALNETWORKS_ABS_EX = 50012,
+  /**
+   * Packs a list of rank-R tensors into one rank- (R+1) tensor along the axis dimension.
+   *
+   * The input tensors must have identical {@link OperandCode} and the same
+   * dimensions.
+   *
+   * Supported tensor {@link OperandCode}:
+   * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+   * * {@link ANEURALNETWORKS_TENSOR_INT32}
+   * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+   *
+   * Supported tensor rank: up to 3
+   *
+   * Inputs:
+   * * 0 ~ n-1: The list of n input tensors, of shape
+   *            [D0, D1, ..., Daxis(i), ..., Dm]. For inputs of
+   *            {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, all input tensors
+   *            must have the same scale and zeroPoint.
+   * * n: An {@link ANEURALNETWORKS_INT32} scalar, specifying the
+   *      number of input tensors.
+   * * n+1: An {@link ANEURALNETWORKS_INT32} scalar, specifying the
+   *        pack axis.
+   *
+   * Outputs:
+   * * 0: The output, a tensor of the same {@link OperandCode} as the input
+   *      tensors. The output shape is [D0, D1, ..., N at Daxis(i), ..., Dm+1]
+   *      where N is the number of tensors to be packed.
+   */
+  ANEURALNETWORKS_PACK_EX = 50013,
+  /**
+   * Unpacks a given rank-R tensors into num_splits rank- (R-1) tensors along the axis dimension.
+   * num_splits has to respect integral divisibility of dimension value along axis dimension
+   * of the input.
+   *
+   * Supported tensor {@link OperandCode}:
+   * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+   * * {@link ANEURALNETWORKS_TENSOR_INT32}
+   * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+   *
+   * Supported tensor rank: up to 4
+   *
+   * Inputs:
+   * * 0: The input shape is [D0, D1, ..., N at Daxis(i), ..., Dm+1].
+   * * 1: An {@link ANEURALNETWORKS_INT32} scalar, specifying the
+   *      number of splits along unpack axis.
+   * * 2: An {@link ANEURALNETWORKS_INT32} scalar, specifying the
+   *      unpack axis.
+   *
+   * Outputs:
+   * * 0 ~ n-1: The list of n output tensors, of shape
+   *            [D0, D1, ..., Daxis(i), ..., Dm]. The output tensors are of the same
+   *            {@link OperandCode} as the input tensor 0.
+   */
+  ANEURALNETWORKS_UNPACK_EX = 50014,
+
+  /**
+   * Returns the index of the largest element along an axis.
+   *
+   * Supported tensor {@link OperandCode}:
+   * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+   * * {@link ANEURALNETWORKS_TENSOR_INT32}
+   * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+   *
+   * Supported tensor rank: from 1
+   *
+   * Inputs:
+   * * 0: An n-D tensor, specifying the input.
+   * * 1: An {@link ANEURALNETWORKS_INT32} scalar specifying the axis to
+   *      reduce across. Negative index is used to specify axis from the
+   *      end (e.g. -1 for the last axis). Must be in the range [-n, n).
+   *
+   * Outputs:
+   * * 0: An (n - 1)-D {@link ANEURALNETWORKS_TENSOR_INT32} tensor.
+   */
+  ANEURALNETWORKS_ARGMAX_EX = 50015,
+
+  /**
+   *
+   * IMPORTANT NOTICE:
+   * ANEURALNETWORKS_SQRT_EX operation is DEPRECATED
+   * Use ANEURALNETWORKS_SQRT instead
+   *
+   */
+  ANEURALNETWORKS_SQRT_EX = 50016,
+
+  /**
+  * Computes element-wise truth value by comparing the input tensors for non-equality.
+  *
+  * Takes two input tensors of identical {@link OperandCode} and compatible dimensions.
+  * The output is the result of comparison of two input tensors.
+  *
+  * Two dimensions are compatible when:
+  *     1. they are equal, or
+  *     2. one of them is 1
+  *
+  * The size of the output is the maximum size along each dimension of the
+  * input operands. It starts with the trailing dimensions, and works its way
+  * forward.
+  *
+  * Supported tensor {@link OperandCode}:
+  * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+  * * {@link ANEURALNETWORKS_TENSOR_INT32}
+  * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+  *
+  * Supported tensor rank: up to 4
+  *
+  * Inputs:
+  * * 0: An n-D tensor, specifying the first input.
+  * * 1: A tensor of the same {@link OperandCode}, and compatible dimensions
+  *      as input0.
+  *
+  * Outputs:
+  * * 0: A boolean tensor indicating the truth value of non-equality of input tensors
+  *      Stored as {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} with offset 0
+  *      and scale 1.0f.
+  *      A non-zero byte represents True, a hit. A zero indicates otherwise.
+  */
+  ANEURALNETWORKS_NOT_EQUAL_EX = 50017,
+
+  /**
+   * Computes element-wise truth value of the input tensor negation.
+   *
+   * Takes one input tensor.
+   * The output is the negation, which is logical complement, of the input tensor.
+   *
+   * Supported tensor {@link OperandCode}:
+   * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+   *
+   * Supported tensor rank: up to 4
+   *
+   * Inputs:
+   * * 0: An n-D boolean tensor, specifying the input.
+   *      Stored as {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} with offset 0
+   *      and scale 1.0f.
+   *      A non-zero byte represents True. A zero indicates otherwise.
+   *
+   * Outputs:
+   * * 0: A boolean tensor of the same size as input indicating the truth value of (NOT x)
+   *      Stored as {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} with offset 0
+   *      and scale 1.0f.
+   *      A non-zero byte represents True. A zero indicates otherwise.
+   */
+  ANEURALNETWORKS_LOGICAL_NOT_EX = 50018,
+
+  /**
+   * Computes element-wise truth value of two input tensors for LOGICAL AND.
+   *
+   * Takes two input tensors of identical {@link OperandCode} and compatible dimensions.
+   * The output is the result of comparison of two input tensors.
+   *
+   * Two dimensions are compatible when:
+   *     1. they are equal, or
+   *     2. one of them is 1
+   *
+   * The size of the output is the maximum size along each dimension of the
+   * input operands. It starts with the trailing dimensions, and works its way
+   * forward.
+   *
+   * Supported tensor {@link OperandCode}:
+   * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+   *
+   * Supported tensor rank: up to 4
+   *
+   * Inputs:
+   * * 0: An n-D boolean tensor, specifying the first input.
+   *      Stored as {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} with offset 0
+   *      and scale 1.0f.
+   *      A non-zero byte represents True, a hit. A zero indicates otherwise.
+   * * 1: A tensor of the same {@link OperandCode}, and compatible dimensions
+   *      as input0.
+   *
+   * Outputs:
+   * * 0: A boolean tensor indicating the truth value of two input tensors for LOGICAL AND.
+   *      Stored as {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} with offset 0
+   *      and scale 1.0f.
+   *      A non-zero byte represents True, a hit. A zero indicates otherwise.
+   */
+  ANEURALNETWORKS_LOGICAL_AND_EX = 50019,
+
+  /**
+   * Computes element-wise truth value of two input tensors for LOGICAL OR.
+   *
+   * Takes two input tensors of identical {@link OperandCode} and compatible dimensions.
+   * The output is the result of comparison of two input tensors.
+   *
+   * Two dimensions are compatible when:
+   *     1. they are equal, or
+   *     2. one of them is 1
+   *
+   * The size of the output is the maximum size along each dimension of the
+   * input operands. It starts with the trailing dimensions, and works its way
+   * forward.
+   *
+   * Supported tensor {@link OperandCode}:
+   * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+   *
+   * Supported tensor rank: up to 4
+   *
+   * Inputs:
+   * * 0: An n-D boolean tensor, specifying the first input.
+   *      Stored as {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} with offset 0
+   *      and scale 1.0f.
+   *      A non-zero byte represents True, a hit. A zero indicates otherwise.
+   * * 1: A tensor of the same {@link OperandCode}, and compatible dimensions
+   *      as input0.
+   *
+   * Outputs:
+   * * 0: A boolean tensor indicating the truth value of two input tensors for LOGICAL OR.
+   *      Stored as {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} with offset 0
+   *      and scale 1.0f.
+   *      A non-zero byte represents True, a hit. A zero indicates otherwise.
+   */
+  ANEURALNETWORKS_LOGICAL_OR_EX = 50020,
+
+  /**
+   * Computes the minimum of elements across dimensions of a tensor.
+   *
+   * Reduces the input tensor along the given dimensions to reduce.
+   *
+   * Supported tensor {@link OperandCode}:
+   * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+   * * {@link ANEURALNETWORKS_TENSOR_INT32}
+   * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+   *
+   * Supported tensor rank: up to 4
+   *
+   * Inputs:
+   * * 0: A tensor, specifying the input.
+   * * 1: A 1-D Tensor of {@link ANEURALNETWORKS_TENSOR_INT32}. The dimensions
+   *      to reduce.
+   * * 2: An {@link ANEURALNETWORKS_BOOL} scalar, keep_dims. If true,
+   *      retains reduced dimensions with length 1.
+   *
+   * Outputs:
+   * * 0: A tensor of the same {@link OperandCode} as input0.
+   */
+  ANEURALNETWORKS_REDUCE_MIN_EX = 50021,
+
+  /**
+   * Parametric Rectified Linear Unit.
+   *
+   * It follows: f(x) = alpha * x for x < 0, f(x) = x for x >= 0, where alpha
+   * is a learned array with the same {@link OperandCode} and compatible
+   * dimensions as input x.
+   *
+   * Two dimensions are compatible when:
+   *     1. they are equal, or
+   *     2. one of them is 1
+   *
+   * The size of the output is the maximum size along each dimension of the
+   * input operands. It starts with the trailing dimensions, and works its way
+   * forward.
+   *
+   * Example:
+   *     input.dimension  =    {4, 1, 2}
+   *     alpha.dimension  = {5, 4, 3, 1}
+   *     output.dimension = {5, 4, 3, 2}
+   *
+   * Supported tensor {@link OperandCode}:
+   * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+   * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+   *
+   * Supported tensor rank: up to 4
+   *
+   * Inputs:
+   * * 0: A tensor, specifying the input.
+   * * 1: A tensor of the same {@link OperandCode}, and compatible dimensions
+   *      as input0, specifying the alpha.
+   *
+   * Outputs:
+   * * 0: A tensor of the same {@link OperandCode} as input0.
+   */
+  ANEURALNETWORKS_PRELU_EX = 50022,
+
+  /**
+   * Returns a one-hot tensor.
+   *
+   * The locations represented by indices in indices take value on_value, while all other locations
+   * take value off_value.
+   * The on_value and off_value must have matching data types. They must be the same data type as
+   * specified by the data type of output.
+   *
+   * If the input indices is rank N, the output will have rank N+1. The new axis is created at
+   * dimension axis.
+   * If indices is a scalar the output shape will be a vector of length depth.
+   *
+   * Supported tensor {@link OperandCode}:
+   * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+   * * {@link ANEURALNETWORKS_TENSOR_INT32}
+   *
+   * Supported tensor rank: up to 4
+   *
+   * Inputs:
+   * * 0: An {@link ANEURALNETWORKS_INT32} tensor, specifying the indices.
+   * * 1: An {@link ANEURALNETWORKS_INT32} scalar, specifying the depth.
+   * * 2: A scalar, specifying the on_value.
+   * * 3: A scalar, specifying the off_value.
+   * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the axis to fill. Optional.
+   *      (default: -1, a new inner-most axis).
+   *
+   * Outputs:
+   * * 0: The one-hot tensor.
+   */
+  ANEURALNETWORKS_ONE_HOT_EX = 50023,
+
+  /**
+   * For input tensors x and y, computes x >= y elementwise.
+   *
+   * Supported tensor {@link OperandCode}:
+   * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+   * * {@link ANEURALNETWORKS_TENSOR_INT32}
+   * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+   *
+   * Supported tensor rank: from 1
+   *
+   * This operation supports broadcasting.
+   *
+   * Inputs:
+   * * 0: A tensor.
+   * * 1: A tensor of the same {@link OperandCode} and dimensions compatible
+   *      with input0.
+   *
+   * Outputs:
+   * * 0: A boolean tensor of {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+   *      with offset 0 and scale 1.0f.
+   */
+  ANEURALNETWORKS_GREATER_EQUAL_EX = 50024,
+
+  /**
+   * For input tensors x and y, computes x < y elementwise.
+   *
+   * Supported tensor {@link OperandCode}:
+   * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}
+   * * {@link ANEURALNETWORKS_TENSOR_INT32}
+   * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+   *
+   * Supported tensor rank: from 1
+   *
+   * This operation supports broadcasting.
+   *
+   * Inputs:
+   * * 0: A tensor.
+   * * 1: A tensor of the same {@link OperandCode} and dimensions compatible
+   *      with input0.
+   *
+   * Outputs:
+   * * 0: A tensor of {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}
+   *      with offset 0 and scale 1.0f.
+   */
+  ANEURALNETWORKS_LESS_EX = 50025,
+} OperationCodeEx; // extends OperationCode
+
+typedef OperationCodeEx ANeuralNetworksOperationTypeEx;
+
+/**
+ * @brief Add an extended operation to a model.
+ *
+ * @param[in] model The model to be modified.
+ * @param[in] type The type of extended operation.
+ * @param[in] inputCount The number of entries in the inputs array.
+ * @param[in] inputs An array of indexes identifying each operand.
+ * @param[in] outputCount The number of entries in the outputs array.
+ * @param[in] outputs An array of indexes identifying each operand.
+ *
+ * @note The operands specified by inputs and outputs must have been
+ *       previously added by calls to {@link ANeuralNetworksModel_addOperand}.\n
+ *       Attempting to modify a model once {@link ANeuralNetworksModel_finish} has been
+ *       called will return an error.\n
+ *       See {@link ANeuralNetworksModel} for information on multithreaded usage.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+int ANeuralNetworksModel_addOperationEx(ANeuralNetworksModel *model,
+                                        ANeuralNetworksOperationTypeEx type, uint32_t inputCount,
+                                        const uint32_t *inputs, uint32_t outputCount,
+                                        const uint32_t *outputs);
+
+__END_DECLS
+
+#endif // NN_RUNTIME_NEURAL_NETWORKS_EX_H
diff --git a/runtime/nnapi-header/include/NeuralNetworksExtensions.h b/runtime/nnapi-header/include/NeuralNetworksExtensions.h
new file mode 100644
index 000000000..ca2e04567
--- /dev/null
+++ b/runtime/nnapi-header/include/NeuralNetworksExtensions.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (C) 2019 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef ANDROID_ML_NN_RUNTIME_NEURAL_NETWORKS_EXTENSIONS_H
+#define ANDROID_ML_NN_RUNTIME_NEURAL_NETWORKS_EXTENSIONS_H
+
+#include "NeuralNetworks.h"
+
+/******************************************************************
+ *
+ * IMPORTANT NOTICE:
+ *
+ *   This file is not intended for use by general developers -- only
+ *   by OEM applications.
+ *
+ *   Extensions source AND binary code relies on the definitions
+ *   here to be FROZEN ON ALL UPCOMING PLATFORM RELEASES.
+ *
+ *   - DO NOT MODIFY ENUMS (EXCEPT IF YOU ADD NEW 32-BIT VALUES)
+ *   - DO NOT MODIFY CONSTANTS OR FUNCTIONAL MACROS
+ *   - DO NOT CHANGE THE SIGNATURE OF FUNCTIONS IN ANY WAY
+ *   - DO NOT CHANGE THE LAYOUT OR SIZE OF STRUCTURES
+ */
+
+__BEGIN_DECLS
+
+#if __ANDROID_API__ >= __ANDROID_API_Q__
+
+/**
+ * Queries whether an extension is supported by the driver implementation of the specified device.
+ *
+ * @param device The representation of the specified device.
+ * @param extension The extension name.
+ * @param isExtensionSupported The boolean value indicating whether the extension is supported.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ *
+ * Available since API level 29.
+ */
+int ANeuralNetworksDevice_getExtensionSupport(const ANeuralNetworksDevice* device,
+                                              const char* extensionName, bool* isExtensionSupported)
+        __INTRODUCED_IN(29);
+
+/**
+ * Creates an operand type from an extension name and an extension operand code.
+ *
+ * See {@link ANeuralNetworksModel} for information on multithreaded usage.
+ *
+ * Available since API level 29.
+ *
+ * @param model The model to contain the operand.
+ * @param extensionName The extension name.
+ * @param operandCodeWithinExtension The extension operand code.
+ * @param type The operand type.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+int ANeuralNetworksModel_getExtensionOperandType(ANeuralNetworksModel* model,
+                                                 const char* extensionName,
+                                                 uint16_t operandCodeWithinExtension, int32_t* type)
+        __INTRODUCED_IN(29);
+
+/**
+ * Creates an operation type from an extension name and an extension operation code.
+ *
+ * See {@link ANeuralNetworksModel} for information on multithreaded usage.
+ *
+ * Available since API level 29.
+ *
+ * @param model The model to contain the operation.
+ * @param extensionName The extension name.
+ * @param operationCodeWithinExtension The extension operation code.
+ * @param type The operation type.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+int ANeuralNetworksModel_getExtensionOperationType(ANeuralNetworksModel* model,
+                                                   const char* extensionName,
+                                                   uint16_t operationCodeWithinExtension,
+                                                   ANeuralNetworksOperationType* type)
+        __INTRODUCED_IN(29);
+
+/**
+ * Sets extension operand parameters.
+ *
+ * Available since API level 29.
+ *
+ * @param model The model to be modified.
+ * @param index The index of the model operand we're setting.
+ * @param data A pointer to the extension operand data.
+ *             The data does not have to outlive the call to this function.
+ * @param length The size in bytes of the data value.
+ *
+ * @return ANEURALNETWORKS_NO_ERROR if successful.
+ */
+int ANeuralNetworksModel_setOperandExtensionData(ANeuralNetworksModel* model, int32_t index,
+                                                 const void* data, size_t length)
+        __INTRODUCED_IN(29);
+
+#endif  // __ANDROID_API__ >= __ANDROID_API_Q__
+
+__END_DECLS
+
+#endif  // ANDROID_ML_NN_RUNTIME_NEURAL_NETWORKS_EXTENSIONS_H